From a66f5cf4f547d8e0384632b92f652c120f5a70b5 Mon Sep 17 00:00:00 2001 From: jean-michel-thoorens Date: Fri, 31 Dec 2021 11:15:22 +0100 Subject: [PATCH] V309 --- ADDON/CORE_ANS.asm | 877 +- ADDON/FixPoint.asm | 56 +- ADDON/SD_TOOLS.asm | 18 +- ADDON/UTILITY.asm | 224 +- FastForth.pdf | Bin 113033 -> 0 bytes FastForthWords.txt | 503 - FastForth_at_work.pdf | Bin 1754741 -> 0 bytes MSP430-FORTH/BOOT.f | 169 +- MSP430-FORTH/CHNGBAUD.f | 828 +- MSP430-FORTH/CORDIC.f | 1017 +- MSP430-FORTH/CORETEST.4TH | 292 +- MSP430-FORTH/CORE_ANS.f | 2130 +- .../CopySourceFileToTarget_SD_Card.bat.lnk | Bin 1153 -> 1197 bytes MSP430-FORTH/DOUBLE.f | 2206 +- MSP430-FORTH/FF_SPECS.f | 1119 +- MSP430-FORTH/FixPoint.f | 832 +- MSP430-FORTH/LAST.4TH | 562 - MSP430-FORTH/MSP_EXP430FR5994/BOOT.4th | 41 - MSP430-FORTH/MSP_EXP430FR5994/CHNGBAUD.4TH | 429 - MSP430-FORTH/MSP_EXP430FR5994/CORDIC.4TH | 505 - MSP430-FORTH/MSP_EXP430FR5994/CORE_ANS.4TH | 1046 - MSP430-FORTH/MSP_EXP430FR5994/DOUBLE.4TH | 1435 - MSP430-FORTH/MSP_EXP430FR5994/FF_SPECS.4TH | 563 - MSP430-FORTH/MSP_EXP430FR5994/FIXPOINT.4TH | 447 - MSP430-FORTH/MSP_EXP430FR5994/LAST.4TH | 1435 - MSP430-FORTH/MSP_EXP430FR5994/PROG100k.4TH | 24955 ----------- MSP430-FORTH/MSP_EXP430FR5994/RC5toLCD.4TH | 352 - MSP430-FORTH/MSP_EXP430FR5994/RTC.4TH | 674 - MSP430-FORTH/MSP_EXP430FR5994/SD_TEST.4TH | 430 - MSP430-FORTH/MSP_EXP430FR5994/SD_TOOLS.4TH | 257 - MSP430-FORTH/MSP_EXP430FR5994/TESTASM.4TH | 512 - MSP430-FORTH/MSP_EXP430FR5994/TSTWORDS.4TH | 90 - MSP430-FORTH/MSP_EXP430FR5994/UARTI2CS.4TH | 297 - MSP430-FORTH/MSP_EXP430FR5994/UTILITY.4TH | 451 - MSP430-FORTH/PROG100k.f | 41675 ------------------- MSP430-FORTH/PROG10K.f | 4625 ++ MSP430-FORTH/PreprocessSourceFile.bat.lnk | Bin 1063 -> 1107 bytes MSP430-FORTH/RC5toLCD.f | 997 +- MSP430-FORTH/RTC.f | 1162 +- MSP430-FORTH/SD_430FR5994/BOOT.4TH | 39 + MSP430-FORTH/SD_430FR5994/CHNGBAUD.4TH | 466 + MSP430-FORTH/SD_430FR5994/CORDIC.4TH | 510 + .../CORETEST.4TH | 477 +- MSP430-FORTH/SD_430FR5994/CORE_ANS.4TH | 1273 + MSP430-FORTH/SD_430FR5994/DOUBLE.4TH | 1566 + MSP430-FORTH/SD_430FR5994/FF_SPECS.4TH | 674 + MSP430-FORTH/SD_430FR5994/FIXPOINT.4TH | 479 + MSP430-FORTH/SD_430FR5994/LAST.4TH | 505 + MSP430-FORTH/SD_430FR5994/MISC/TESTASM.4TH | 630 + MSP430-FORTH/SD_430FR5994/PID.4TH | 815 + MSP430-FORTH/SD_430FR5994/PROG10k.4TH | 2664 ++ MSP430-FORTH/SD_430FR5994/RC5toLCD.4TH | 350 + MSP430-FORTH/SD_430FR5994/RTC.4TH | 605 + MSP430-FORTH/SD_430FR5994/SD_TEST.4TH | 507 + MSP430-FORTH/SD_430FR5994/SD_TOOLS.4TH | 310 + .../TESTXASM.4TH | 916 +- MSP430-FORTH/SD_430FR5994/TSTWORDS.4TH | 215 + MSP430-FORTH/SD_430FR5994/UARTI2CS.4TH | 338 + MSP430-FORTH/SD_430FR5994/UTILITY.4TH | 527 + MSP430-FORTH/SD_TEST.f | 877 +- MSP430-FORTH/SD_TOOLS.f | 498 +- MSP430-FORTH/SendSourceFileToTarget.bat.lnk | Bin 1081 -> 1125 bytes MSP430-FORTH/TESTASM.F | 742 +- MSP430-FORTH/TESTXASM.F | 902 +- MSP430-FORTH/TSTWORDS.4TH | 90 - MSP430-FORTH/TSTWORDS.f | 306 + MSP430-FORTH/UARTI2CS.f | 1123 +- MSP430-FORTH/UTILITY.f | 845 +- README.md | 1223 +- SciTEDirectory.properties | 574 +- binaries/CHIPSTICK_FR2433_16MHz_115200.txt | 325 + binaries/CHIPSTICK_FR2433_16MHz_4MBds.txt | 325 + binaries/CHIPSTICK_FR2433_16MHz_I2C.txt | 644 +- binaries/CHIPSTICK_FR2433_16MHz_UART.txt | 336 - binaries/CHIPSTICK_FR2433_1MHz_115200.txt | 324 + binaries/CHIPSTICK_FR2433_1MHz_I2C.txt | 635 +- binaries/CHIPSTICK_FR2433_1MHz_UART.txt | 335 - binaries/CHIPSTICK_FR2433_8MHz_115200.txt | 324 + binaries/CHIPSTICK_FR2433_8MHz_I2C.txt | 642 +- binaries/CHIPSTICK_FR2433_8MHz_UART.txt | 335 - binaries/LP_MSP430FR2476_16MHz_115200.txt | 325 + binaries/LP_MSP430FR2476_16MHz_4MBds.txt | 325 + binaries/LP_MSP430FR2476_16MHz_I2C.txt | 647 +- binaries/LP_MSP430FR2476_16MHz_UART.txt | 337 - binaries/LP_MSP430FR2476_1MHz_115200.txt | 324 + binaries/LP_MSP430FR2476_1MHz_I2C.txt | 646 +- binaries/LP_MSP430FR2476_1MHz_UART.txt | 336 - binaries/LP_MSP430FR2476_8MHz_115200.txt | 324 + binaries/LP_MSP430FR2476_8MHz_I2C.txt | 645 +- binaries/LP_MSP430FR2476_8MHz_UART.txt | 336 - binaries/Log/log.txt | 75 - binaries/MSP_EXP430FR2355_16MHz_115200.txt | 325 + binaries/MSP_EXP430FR2355_16MHz_4MBds.txt | 325 + binaries/MSP_EXP430FR2355_16MHz_I2C.txt | 646 +- binaries/MSP_EXP430FR2355_16MHz_UART.txt | 337 - binaries/MSP_EXP430FR2355_1MHz_115200.txt | 324 + binaries/MSP_EXP430FR2355_1MHz_I2C.txt | 643 +- binaries/MSP_EXP430FR2355_1MHz_UART.txt | 336 - binaries/MSP_EXP430FR2355_24MHz_115200.txt | 325 + binaries/MSP_EXP430FR2355_24MHz_6MBds.txt | 325 + binaries/MSP_EXP430FR2355_24MHz_I2C.txt | 646 +- binaries/MSP_EXP430FR2355_24MHz_UART.txt | 337 - binaries/MSP_EXP430FR2355_8MHz_115200.txt | 324 + binaries/MSP_EXP430FR2355_8MHz_I2C.txt | 644 +- binaries/MSP_EXP430FR2355_8MHz_UART.txt | 336 - binaries/MSP_EXP430FR2433_16MHz_115200.txt | 324 + binaries/MSP_EXP430FR2433_16MHz_4MBds.txt | 324 + binaries/MSP_EXP430FR2433_16MHz_I2C.txt | 647 +- binaries/MSP_EXP430FR2433_16MHz_UART.txt | 336 - binaries/MSP_EXP430FR2433_1MHz_115200.txt | 323 + binaries/MSP_EXP430FR2433_1MHz_I2C.txt | 643 +- binaries/MSP_EXP430FR2433_1MHz_UART.txt | 335 - binaries/MSP_EXP430FR2433_8MHz_115200.txt | 323 + binaries/MSP_EXP430FR2433_8MHz_I2C.txt | 645 +- binaries/MSP_EXP430FR2433_8MHz_UART.txt | 335 - binaries/MSP_EXP430FR4133_16MHz_115200.txt | 329 + binaries/MSP_EXP430FR4133_16MHz_4MBds.txt | 329 + binaries/MSP_EXP430FR4133_16MHz_I2C.txt | 650 +- binaries/MSP_EXP430FR4133_16MHz_UART.txt | 341 - binaries/MSP_EXP430FR4133_1MHz_115200.txt | 328 + binaries/MSP_EXP430FR4133_1MHz_I2C.txt | 649 +- binaries/MSP_EXP430FR4133_1MHz_UART.txt | 340 - binaries/MSP_EXP430FR4133_8MHz_115200.txt | 328 + binaries/MSP_EXP430FR4133_8MHz_I2C.txt | 650 +- binaries/MSP_EXP430FR4133_8MHz_UART.txt | 340 - binaries/MSP_EXP430FR5739_16MHz_115200.txt | 325 + binaries/MSP_EXP430FR5739_16MHz_4MBds.txt | 325 + binaries/MSP_EXP430FR5739_16MHz_I2C.txt | 632 +- binaries/MSP_EXP430FR5739_16MHz_UART.txt | 337 - binaries/MSP_EXP430FR5739_1MHz_115200.txt | 325 + binaries/MSP_EXP430FR5739_1MHz_I2C.txt | 640 +- binaries/MSP_EXP430FR5739_1MHz_UART.txt | 337 - binaries/MSP_EXP430FR5739_24MHz_115200.txt | 325 + binaries/MSP_EXP430FR5739_24MHz_6MBds.txt | 325 + binaries/MSP_EXP430FR5739_24MHz_I2C.txt | 632 +- binaries/MSP_EXP430FR5739_24MHz_UART.txt | 337 - binaries/MSP_EXP430FR5739_8MHz_115200.txt | 325 + binaries/MSP_EXP430FR5739_8MHz_I2C.txt | 642 +- binaries/MSP_EXP430FR5739_8MHz_UART.txt | 336 - binaries/MSP_EXP430FR5969_16MHz_115200.txt | 326 + binaries/MSP_EXP430FR5969_16MHz_4MBds.txt | 326 + binaries/MSP_EXP430FR5969_16MHz_I2C.txt | 644 +- binaries/MSP_EXP430FR5969_16MHz_UART.txt | 337 - binaries/MSP_EXP430FR5969_1MHz_115200.txt | 325 + binaries/MSP_EXP430FR5969_1MHz_I2C.txt | 639 +- binaries/MSP_EXP430FR5969_1MHz_UART.txt | 336 - binaries/MSP_EXP430FR5969_8MHz_115200.txt | 324 + binaries/MSP_EXP430FR5969_8MHz_I2C.txt | 629 +- binaries/MSP_EXP430FR5969_8MHz_UART.txt | 336 - binaries/MSP_EXP430FR5994_16MHz_115200.txt | 506 + binaries/MSP_EXP430FR5994_16MHz_4MBds.txt | 506 + binaries/MSP_EXP430FR5994_16MHz_I2C.txt | 1136 +- binaries/MSP_EXP430FR5994_16MHz_UART.txt | 658 - binaries/MSP_EXP430FR5994_1MHz_115200.txt | 505 + binaries/MSP_EXP430FR5994_1MHz_I2C.txt | 1134 +- binaries/MSP_EXP430FR5994_1MHz_UART.txt | 657 - binaries/MSP_EXP430FR5994_8MHz_115200.txt | 504 + binaries/MSP_EXP430FR5994_8MHz_I2C.txt | 1142 +- binaries/MSP_EXP430FR5994_8MHz_UART.txt | 657 - binaries/MSP_EXP430FR6989_16MHz_115200.txt | 327 + binaries/MSP_EXP430FR6989_16MHz_4MBds.txt | 327 + binaries/MSP_EXP430FR6989_16MHz_I2C.txt | 646 +- binaries/MSP_EXP430FR6989_16MHz_UART.txt | 339 - binaries/MSP_EXP430FR6989_1MHz_115200.txt | 326 + binaries/MSP_EXP430FR6989_1MHz_I2C.txt | 642 +- binaries/MSP_EXP430FR6989_1MHz_UART.txt | 338 - binaries/MSP_EXP430FR6989_8MHz_115200.txt | 326 + binaries/MSP_EXP430FR6989_8MHz_I2C.txt | 638 +- binaries/MSP_EXP430FR6989_8MHz_UART.txt | 337 - config/BSL_prog.bat | 4 +- config/Command Prompt.lnk | Bin 0 -> 1098 bytes config/CopySourceFileToTarget_SD_Card.bat | 4 +- config/CopyTo_SD_Card.bat | 10 +- config/FET_prog.bat | 20 +- config/INFO.txt | 34 + config/MSP430read.bat | 2 +- config/MSP430readINFO.bat | 13 + config/MSP430readMAIN.bat | 13 + config/MSP430readRAM.bat | 13 + config/Preprocess.bat | 13 +- config/PreprocessSourceFile.bat | 4 +- config/SciTEUser.properties | 250 + config/Select.bat | 1 + config/Send | 14 + config/SendFile.ttl | 13 +- config/SendSource | 13 +- config/SendSource.bat | 17 +- config/SendSourceFileToTarget.bat | 2 +- config/SendToSD.ttl | 14 +- config/UNIFLASH_prog.bat | 16 + config/asm.properties | 40 +- config/build | 15 +- config/build.bat | 14 +- config/forth.properties | 51 +- config/others.properties | 2 +- config/prog | 10 +- config/target_MAIN.txt | 16385 ++++++++ forthMSP430FR.asm | 2977 +- forthMSP430FR_ASM.asm | 650 +- forthMSP430FR_CONDCOMP.asm | 271 - forthMSP430FR_EXTD_ASM.asm | 1002 +- forthMSP430FR_SD_ACCEPT.asm | 99 +- forthMSP430FR_SD_INIT.asm | 151 +- forthMSP430FR_SD_LOAD.asm | 564 +- forthMSP430FR_SD_LowLvl.asm | 61 +- forthMSP430FR_SD_RW.asm | 869 +- forthMSP430FR_TERM_HALF.asm | 339 +- forthMSP430FR_TERM_I2C.asm | 379 +- forthMSP430FR_TERM_UART.asm | 371 +- inc/CHIPSTICK_FR2433.asm | 210 +- inc/CHIPSTICK_FR2433.pat | 68 +- inc/FastForthREGtoTI.pat | 159 +- inc/LP_MSP430FR2476.asm | 171 +- inc/LP_MSP430FR2476.pat | 98 +- inc/MSP430FR2355.pat | 296 +- inc/MSP430FR2433.inc | 88 +- inc/MSP430FR2433.pat | 572 +- inc/MSP430FR2476.inc | 116 +- inc/MSP430FR2476.pat | 691 +- inc/MSP430FR2633.pat | 237 +- inc/MSP430FR4133.inc | 76 +- inc/MSP430FR4133.pat | 665 +- inc/MSP430FR5738.inc | 26 +- inc/MSP430FR5738.pat | 282 +- inc/MSP430FR5739.inc | 20 +- inc/MSP430FR5739.pat | 650 +- inc/MSP430FR5948.inc | 22 +- inc/MSP430FR5948.pat | 845 +- inc/MSP430FR5969.inc | 30 +- inc/MSP430FR5969.pat | 845 +- inc/MSP430FR5972.inc | 30 +- inc/MSP430FR5972.pat | 238 +- inc/MSP430FR5994.pat | 250 +- inc/MSP430FR6989.pat | 260 +- inc/MSP_EXP430FR2355.asm | 138 +- inc/MSP_EXP430FR2355.pat | 52 +- inc/MSP_EXP430FR2433.asm | 163 +- inc/MSP_EXP430FR2433.pat | 76 +- inc/MSP_EXP430FR4133.asm | 163 +- inc/MSP_EXP430FR4133.pat | 82 +- inc/MSP_EXP430FR5739.asm | 35 +- inc/MSP_EXP430FR5739.pat | 46 +- inc/MSP_EXP430FR5969.asm | 35 +- inc/MSP_EXP430FR5969.pat | 84 +- inc/MSP_EXP430FR5972.asm | 26 +- inc/MSP_EXP430FR5972.pat | 48 +- inc/MSP_EXP430FR5994.asm | 40 +- inc/MSP_EXP430FR5994.pat | 116 +- inc/MSP_EXP430FR6989.asm | 29 +- inc/MSP_EXP430FR6989.pat | 46 +- inc/TERMINALBAUDRATE.inc | 18 +- inc/TargetInit.asm | 69 +- inc/ThingsInFirst.inc | 425 +- inc/ThingsInLast.inc | 35 +- prog/SciTEUser.properties | 11 + prog/TERATERM.INI | 972 + 256 files changed, 77712 insertions(+), 115572 deletions(-) delete mode 100644 FastForth.pdf delete mode 100644 FastForthWords.txt delete mode 100644 FastForth_at_work.pdf delete mode 100644 MSP430-FORTH/LAST.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/BOOT.4th delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/CHNGBAUD.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/CORDIC.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/CORE_ANS.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/DOUBLE.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/FF_SPECS.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/FIXPOINT.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/LAST.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/PROG100k.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/RC5toLCD.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/RTC.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/SD_TEST.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/SD_TOOLS.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/TESTASM.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/TSTWORDS.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/UARTI2CS.4TH delete mode 100644 MSP430-FORTH/MSP_EXP430FR5994/UTILITY.4TH delete mode 100644 MSP430-FORTH/PROG100k.f create mode 100644 MSP430-FORTH/PROG10K.f create mode 100644 MSP430-FORTH/SD_430FR5994/BOOT.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/CHNGBAUD.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/CORDIC.4TH rename MSP430-FORTH/{MSP_EXP430FR5994 => SD_430FR5994}/CORETEST.4TH (67%) create mode 100644 MSP430-FORTH/SD_430FR5994/CORE_ANS.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/DOUBLE.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/FF_SPECS.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/FIXPOINT.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/LAST.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/MISC/TESTASM.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/PID.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/PROG10k.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/RC5toLCD.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/RTC.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/SD_TEST.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/SD_TOOLS.4TH rename MSP430-FORTH/{MSP_EXP430FR5994 => SD_430FR5994}/TESTXASM.4TH (50%) create mode 100644 MSP430-FORTH/SD_430FR5994/TSTWORDS.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/UARTI2CS.4TH create mode 100644 MSP430-FORTH/SD_430FR5994/UTILITY.4TH delete mode 100644 MSP430-FORTH/TSTWORDS.4TH create mode 100644 MSP430-FORTH/TSTWORDS.f create mode 100644 binaries/CHIPSTICK_FR2433_16MHz_115200.txt create mode 100644 binaries/CHIPSTICK_FR2433_16MHz_4MBds.txt delete mode 100644 binaries/CHIPSTICK_FR2433_16MHz_UART.txt create mode 100644 binaries/CHIPSTICK_FR2433_1MHz_115200.txt delete mode 100644 binaries/CHIPSTICK_FR2433_1MHz_UART.txt create mode 100644 binaries/CHIPSTICK_FR2433_8MHz_115200.txt delete mode 100644 binaries/CHIPSTICK_FR2433_8MHz_UART.txt create mode 100644 binaries/LP_MSP430FR2476_16MHz_115200.txt create mode 100644 binaries/LP_MSP430FR2476_16MHz_4MBds.txt delete mode 100644 binaries/LP_MSP430FR2476_16MHz_UART.txt create mode 100644 binaries/LP_MSP430FR2476_1MHz_115200.txt delete mode 100644 binaries/LP_MSP430FR2476_1MHz_UART.txt create mode 100644 binaries/LP_MSP430FR2476_8MHz_115200.txt delete mode 100644 binaries/LP_MSP430FR2476_8MHz_UART.txt delete mode 100644 binaries/Log/log.txt create mode 100644 binaries/MSP_EXP430FR2355_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR2355_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR2355_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2355_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR2355_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2355_24MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR2355_24MHz_6MBds.txt delete mode 100644 binaries/MSP_EXP430FR2355_24MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2355_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR2355_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2433_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR2433_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR2433_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2433_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR2433_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR2433_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR2433_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR4133_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR4133_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR4133_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR4133_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR4133_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR4133_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR4133_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5739_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR5739_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR5739_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5739_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5739_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5739_24MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR5739_24MHz_6MBds.txt delete mode 100644 binaries/MSP_EXP430FR5739_24MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5739_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5739_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5969_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR5969_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR5969_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5969_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5969_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5969_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5969_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5994_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR5994_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR5994_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5994_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5994_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR5994_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR5994_8MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR6989_16MHz_115200.txt create mode 100644 binaries/MSP_EXP430FR6989_16MHz_4MBds.txt delete mode 100644 binaries/MSP_EXP430FR6989_16MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR6989_1MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR6989_1MHz_UART.txt create mode 100644 binaries/MSP_EXP430FR6989_8MHz_115200.txt delete mode 100644 binaries/MSP_EXP430FR6989_8MHz_UART.txt create mode 100644 config/Command Prompt.lnk create mode 100644 config/INFO.txt create mode 100644 config/MSP430readINFO.bat create mode 100644 config/MSP430readMAIN.bat create mode 100644 config/MSP430readRAM.bat create mode 100644 config/SciTEUser.properties create mode 100644 config/Send create mode 100644 config/UNIFLASH_prog.bat create mode 100644 config/target_MAIN.txt delete mode 100644 forthMSP430FR_CONDCOMP.asm create mode 100644 prog/SciTEUser.properties create mode 100644 prog/TERATERM.INI diff --git a/ADDON/CORE_ANS.asm b/ADDON/CORE_ANS.asm index d311d55..5e9a9b8 100644 --- a/ADDON/CORE_ANS.asm +++ b/ADDON/CORE_ANS.asm @@ -4,23 +4,190 @@ MOV @IP+,PC ;------------------------------------------------------------------------------- +; COMPARAISON OPERATIONS +;------------------------------------------------------------------------------- + FORTHWORD "0<" +; https://forth-standard.org/standard/core/Zeroless +; 0< n -- flag true if TOS negative + ADD TOS,TOS ;1 set carry if TOS negative + SUBC TOS,TOS ;1 TOS=-1 if carry was clear +EQUALTRUE XOR #-1,TOS ;1 TOS=-1 if carry was set + MOV @IP+,PC ; + +; https://forth-standard.org/standard/core/ZeroEqual +; 0= n/u -- flag return true if TOS=0 + FORTHWORD "0=" + SUB #1,TOS ; borrow (clear cy) if TOS was 0 + SUBC TOS,TOS ; TOS=-1 if borrow was set + MOV @IP+,PC + + FORTHWORD "0<>" +; https://forth-standard.org/standard/core/Zerone +; 0<> n/u -- flag return true if TOS<>0 + SUB #1,TOS ; 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS ; 1 TOS=-1 if borrow was set + XOR #-1,TOS ; 1 + MOV @IP+,PC + + FORTHWORD "=" +; https://forth-standard.org/standard/core/Equal +; = x1 x2 -- flag test x1=x2 +EQUAL SUB @PSP+,TOS ;2 + JZ EQUALTRUE ;2 flag Z will be = 0 + AND #0,TOS ;1 flag Z = 1 + MOV @IP+,PC ;4 + + .IFNDEF LESS + FORTHWORD "<" +;https://forth-standard.org/standard/core/less +;C < n1 n2 -- flag test n1" +;https://forth-standard.org/standard/core/more +;C > n1 n2 -- flag test n1>n2, signed +MORE SUB @PSP+,TOS ;2 TOS=n2-n1 + JL TOSTRUE ;2 --> +5 +TOSFALSE AND #0,TOS ;1 flag Z = 1 + MOV @IP+,PC ;4 + + .IFNDEF ULESS +; https://forth-standard.org/standard/core/Uless +; U< u1 u2 -- flag test u1 n1 n2 -- flag + FORTHWORD "U>" + SUB @PSP+,TOS ; 2 + JNC UTOSTRUE ; 2 flag = true, Z = 0 +UTOSFALSE AND #0,TOS ;1 flag Z = 1 + MOV @IP+,PC ;4 + .ENDIF + +;------------------------------------------------------------------------------- +; STACK OPERATIONS +;------------------------------------------------------------------------------- + .IFNDEF QDUP +; https://forth-standard.org/standard/core/DUP +; DUP x -- x x duplicate top of stack + FORTHWORD "DUP" +QDUPNEXT SUB #2,PSP ; 2 push old TOS.. + MOV TOS,0(PSP) ; 3 ..onto stack +QDUPEND MOV @IP+,PC ; 4 + +; https://forth-standard.org/standard/core/qDUP +; ?DUP x -- 0 | x x DUP if nonzero + FORTHWORD "?DUP" +QDUP CMP #0,TOS + JZ QDUPEND + JNZ QDUPNEXT + .ENDIF + +; https://forth-standard.org/standard/core/SWAP +; SWAP x1 x2 -- x2 x1 swap top two items + FORTHWORD "SWAP" + MOV @PSP,W ; 2 + MOV TOS,0(PSP) ; 3 + MOV W,TOS ; 1 + MOV @IP+,PC ; 4 + + FORTHWORD "DROP" +; https://forth-standard.org/standard/core/DROP +; DROP x -- drop top of stack + MOV @PSP+,TOS ; 2 + MOV @IP+,PC ; 4 + + .IFNDEF OVER +;https://forth-standard.org/standard/core/OVER +;C OVER x1 x2 -- x1 x2 x1 + FORTHWORD "OVER" +OVER MOV TOS,-2(PSP) ; 3 -- x1 (x2) x2 + MOV @PSP,TOS ; 2 -- x1 (x2) x1 + SUB #2,PSP ; 1 -- x1 x2 x1 + MOV @IP+,PC ; 4 + .ENDIF + + FORTHWORD "NIP" +; https://forth-standard.org/standard/core/NIP +; NIP x1 x2 -- x2 Drop the first item below the top of stack + ADD #2,PSP ; 1 + MOV @IP+,PC ; 4 + + FORTHWORD "ROT" +;https://forth-standard.org/standard/core/ROT +;C ROT x1 x2 x3 -- x2 x3 x1 + MOV @PSP,W ; 2 fetch x2 + MOV TOS,0(PSP) ; 3 store x3 + MOV 2(PSP),TOS ; 3 fetch x1 + MOV W,2(PSP) ; 3 store x2 + MOV @IP+,PC ; 4 + +; https://forth-standard.org/standard/core/Rfrom +; R> -- x R: x -- pop from return stack + FORTHWORD "R>" + SUB #2,PSP ; 1 + MOV TOS,0(PSP) ; 3 + MOV @RSP+,TOS ; 2 + MOV @IP+,PC ; 4 + + FORTHWORD "R@" +;https://forth-standard.org/standard/core/RFetch +;C R@ -- x R: x -- x fetch from rtn stk + SUB #2,PSP + MOV TOS,0(PSP) + MOV @RSP,TOS + MOV @IP+,PC + + .IFNDEF TOR +; https://forth-standard.org/standard/core/toR +; >R x -- R: -- x push to return stack + FORTHWORD ">R" +TOR PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + .ENDIF + +; https://forth-standard.org/standard/core/TUCK +; TUCK ( x1 x2 -- x2 x1 x2 ) + FORTHWORD "TUCK" + mDOCOL + .word SWAP,OVER,EXIT + +; https://forth-standard.org/standard/core/DEPTH +; DEPTH -- +n number of items on stack, must leave 0 if stack empty + FORTHWORD "DEPTH" + MOV #DEPTH,PC + +;------------------------------------------------------------------------------- ; RETURN from high level word ;------------------------------------------------------------------------------- FORTHWORD "EXIT" ; https://forth-standard.org/standard/core/EXIT -; EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles) +; EXIT -- exit a colon definition; CALL #EXIT performs mASM2FORTH (10 cycles) ; JMP #EXIT performs EXIT MOV @RSP+,IP ; 2 pop previous IP (or next PC) from return stack MOV @IP+,PC ; 4 = NEXT ; 6 (ITC-2) + .IFNDEF SPACE ;https://forth-standard.org/standard/core/SPACE ;C SPACE -- output a space FORTHWORD "SPACE" SPACE SUB #2,PSP ;1 MOV TOS,0(PSP) ;3 MOV #20h,TOS ;2 - JMP EMIT ;17~ 23~ + MOV #EMIT,PC ;17~ 23~ ;https://forth-standard.org/standard/core/SPACES ;C SPACES n -- output n spaces @@ -30,13 +197,136 @@ SPACES CMP #0,TOS PUSH IP MOV #SPACESNEXT,IP JMP SPACE ;25~ -SPACESNEXT .word $+2 +SPACESNEXT mNEXTADR SUB #2,IP ;1 SUB #1,TOS ;1 JNZ SPACE ;25~ ==> 27~ by space ==> 2.963 MBds @ 8 MHz MOV @RSP+,IP ; SPACESNEXT2 MOV @PSP+,TOS ; -- drop n - MOV @IP+,PC ; + MOV @IP+,PC ; + .ENDIF + + .IFNDEF CR + FORTHWORD "CR" +; https://forth-standard.org/standard/core/CR +; CR -- send CR to the output device +CR MOV @PC+,PC + .word BODYCR +BODYCR mDOCOL ; send CR+LF to the default output device + .word LIT,0Dh,EMIT + .word LIT,0Ah,EMIT + .word EXIT + .ENDIF + +;------------------------------------------------------------------------------- +; ARITHMETIC OPERATIONS +;------------------------------------------------------------------------------- + .IFNDEF ANDD +;https://forth-standard.org/standard/core/AND +;C AND x1 x2 -- x3 logical AND + FORTHWORD "AND" +ANDD AND @PSP+,TOS + MOV @IP+,PC + .ENDIF + +;https://forth-standard.org/standard/core/OR +;C OR x1 x2 -- x3 logical OR + FORTHWORD "OR" +ORR BIS @PSP+,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/XOR +;C XOR x1 x2 -- x3 logical XOR + FORTHWORD "XOR" +XORR XOR @PSP+,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/INVERT +;C INVERT x1 -- x2 bitwise inversion + FORTHWORD "INVERT" + XOR #-1,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/LSHIFT +;C LSHIFT x1 u -- x2 logical L shift u places + FORTHWORD "LSHIFT" +LSHIFT MOV @PSP+,W + AND #1Fh,TOS ; no need to shift more than 16 + JZ LSH_X +LSH_1 ADD W,W + SUB #1,TOS + JNZ LSH_1 +LSH_X MOV W,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/RSHIFT +;C RSHIFT x1 u -- x2 logical R shift u places + FORTHWORD "RSHIFT" +RSHIFT MOV @PSP+,W + AND #1Fh,TOS ; no need to shift more than 16 + JZ RSH_X +RSH_1 BIC #1,SR ; CLRC + RRC W + SUB #1,TOS + JNZ RSH_1 +RSH_X MOV W,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/TwoTimes +;C 2* x1 -- x2 arithmetic left shift + FORTHWORD "2*" +TWOTIMES ADD TOS,TOS + MOV @IP+,PC + +;https://forth-standard.org/standard/core/TwoDiv +;C 2/ x1 -- x2 arithmetic right shift + FORTHWORD "2/" +TWODIV RRA TOS + MOV @IP+,PC + + .IFNDEF MAX +;https://forth-standard.org/standard/core/MAX +;C MAX n1 n2 -- n3 signed maximum + FORTHWORD "MAX" +MAX CMP @PSP,TOS ; n2-n1 + JL SELn1 ; n2 u2 + XOR #-1,TOS ; y: n2 --> u2 ADD #1,TOS ; u1u2MSTAR PUSHM #2,IP ; PUSHM IP,S - ASMtoFORTH + mASM2FORTH .word UMSTAR ; UMSTAR use S,T,W,X,Y - .word $+2 + mNEXTADR POPM #2,IP ; POPM S,IP CMP #0,S ; result > -1 ? JGE MSTARend ; yes @@ -94,6 +384,7 @@ MSTARend MOV @IP+,PC UMSLASHMOD PUSH #DROP ;3 as return address for MU/MOD MOV #MUSMOD,PC + .IFNDEF FLOORED_DIVISION ;https://forth-standard.org/standard/core/SMDivREM ;C SM/REM d1lo d1hi n2 -- n3 n4 symmetric signed div FORTHWORD "SM/REM" @@ -128,13 +419,40 @@ NEGAT XOR #-1,TOS ;1 SMSLASHREMnrnq ; -- nr nq S=divisor MOV @IP+,PC ;4 34 words + .ELSE ; FLOORED_DIVISION ;https://forth-standard.org/standard/core/FMDivMOD ;C FM/MOD d1 n1 -- r q floored signed div'n FORTHWORD "FM/MOD" -FMSLASHMOD PUSH IP - MOV #FMSLASHMOD1,IP - JMP SMSLASHREM -FMSLASHMOD1 .word $+2 ; -- remainder quotient S=divisor +FMSLASHMOD MOV TOS,S ;1 S=divisor + MOV @PSP,T ;2 T=rem_sign + CMP #0,TOS ;1 n2 >= 0 ? + JGE d1u2FMSLASHMOD ;2 yes + XOR #-1,TOS ;1 + ADD #1,TOS ;1 +d1u2FMSLASHMOD ; -- d1 u2 + CMP #0,0(PSP) ;3 d1hi >= 0 ? + JGE ud1u2FMSLASHMOD ;2 yes + XOR #-1,2(PSP) ;4 d1lo + XOR #-1,0(PSP) ;4 d1hi + ADD #1,2(PSP) ;4 d1lo+1 + ADDC #0,0(PSP) ;4 d1hi+C +ud1u2FMSLASHMOD ; -- ud1 u2 + PUSHM #2,S ;4 PUSHM S,T + CALL #MUSMOD + MOV @PSP+,TOS + POPM #2,S ;4 POPM T,S + CMP #0,T ;1 -- ur uq T=rem_sign>=0? + JGE FMSLASHMODnruq ;2 yes + XOR #-1,0(PSP) ;3 + ADD #1,0(PSP) ;3 +FMSLASHMODnruq + XOR S,T ;1 S=divisor T=quot_sign + CMP #0,T ;1 -- nr uq T=quot_sign>=0? + JGE FMSLASHMODnrnq ;2 yes +NEGAT XOR #-1,TOS ;1 + ADD #1,TOS ;1 +FMSLASHMODnrnq ; -- nr nq S=divisor + CMP #0,0(PSP) ; JZ FMSLASHMODEND CMP #1,TOS ; quotient < 1 ? @@ -143,18 +461,19 @@ QUOTLESSONE ADD S,0(PSP) ; add divisor to remainder SUB #1,TOS ; decrement quotient FMSLASHMODEND MOV @RSP+,IP - MOV @IP+,PC ; + MOV @IP+,PC ; + .ENDIF ;https://forth-standard.org/standard/core/NEGATE ;C NEGATE x1 -- x2 two's complement FORTHWORD "NEGATE" - JMP NEGAT + JMP NEGAT ;https://forth-standard.org/standard/core/ABS ;C ABS n1 -- +n2 absolute value FORTHWORD "ABS" CMP #0,TOS ; 1 - JN NEGAT + JN NEGAT MOV @IP+,PC ;https://forth-standard.org/standard/core/Times @@ -167,70 +486,61 @@ STAR mDOCOL ;C /MOD n1 n2 -- n3 n4 signed divide/rem'dr FORTHWORD "/MOD" SLASHMOD mDOCOL - .word TOR,STOD,RFROM,FMSLASHMOD,EXIT + .word TOR,STOD,RFROM + .IFNDEF FLOORED_DIVISION + .word SMSLASHREM + .ELSE + .word FMSLASHMOD + .ENDIF + .word EXIT ;https://forth-standard.org/standard/core/Div ;C / n1 n2 -- n3 signed divide FORTHWORD "/" SLASH mDOCOL - .word TOR,STOD,RFROM,FMSLASHMOD,NIP,EXIT + .word TOR,STOD,RFROM + .IFNDEF FLOORED_DIVISION + .word SMSLASHREM + .ELSE + .word FMSLASHMOD + .ENDIF + .word NIP,EXIT ;https://forth-standard.org/standard/core/MOD ;C MOD n1 n2 -- n3 signed remainder FORTHWORD "MOD" MODD mDOCOL - .word TOR,STOD,RFROM,FMSLASHMOD,DROP,EXIT + .word TOR,STOD,RFROM + .IFNDEF FLOORED_DIVISION + .word SMSLASHREM + .ELSE + .word FMSLASHMOD + .ENDIF + .word DROP,EXIT ;https://forth-standard.org/standard/core/TimesDivMOD ;C */MOD n1 n2 n3 -- n4 n5 n1*n2/n3, rem" FORTHWORD "*/MOD" SSMOD mDOCOL - .word TOR,MSTAR,RFROM,FMSLASHMOD,EXIT + .word TOR,MSTAR,RFROM + .IFNDEF FLOORED_DIVISION + .word SMSLASHREM + .ELSE + .word FMSLASHMOD + .ENDIF + .word EXIT ;https://forth-standard.org/standard/core/TimesDiv ;C */ n1 n2 n3 -- n4 n1*n2/n3 FORTHWORD "*/" STARSLASH mDOCOL - .word TOR,MSTAR,RFROM,FMSLASHMOD,NIP,EXIT - - - -;https://forth-standard.org/standard/core/ALIGNED -;C ALIGNED addr -- a-addr align given addr - FORTHWORD "ALIGNED" -ALIGNED BIT #1,TOS - ADDC #0,TOS - MOV @IP+,PC - -;https://forth-standard.org/standard/core/ALIGN -;C ALIGN -- align HERE - FORTHWORD "ALIGN" -ALIGNN BIT #1,&DDP ; 3 - ADDC #0,&DDP ; 4 - MOV @IP+,PC - -;https://forth-standard.org/standard/core/CHARS -;C CHARS n1 -- n2 chars->adrs units - FORTHWORD "CHARS" - MOV @IP+,PC - -;https://forth-standard.org/standard/core/CHARPlus -;C CHAR+ c-addr1 -- c-addr2 add char size - FORTHWORD "CHAR+" - ADD #1,TOS - MOV @IP+,PC - -;https://forth-standard.org/standard/core/CELLS -;C CELLS n1 -- n2 cells->adrs units - FORTHWORD "CELLS" - ADD TOS,TOS - MOV @IP+,PC - -;https://forth-standard.org/standard/core/CELLPlus -;C CELL+ a-addr1 -- a-addr2 add cell size - FORTHWORD "CELL+" - ADD #2,TOS - MOV @IP+,PC + .word TOR,MSTAR,RFROM + .IFNDEF FLOORED_DIVISION + .word SMSLASHREM + .ELSE + .word FMSLASHMOD + .ENDIF + .word NIP,EXIT ;---------------------------------------------------------------------- ; DOUBLE OPERATORS @@ -241,7 +551,7 @@ ALIGNN BIT #1,&DDP ; 3 FORTHWORD "S>D" STOD SUB #2,PSP MOV TOS,0(PSP) - JMP ZEROLESS + MOV #ZEROLESS,PC ; https://forth-standard.org/standard/core/TwoFetch ; 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack @@ -259,6 +569,16 @@ TWOSTORE MOV @PSP+,0(TOS) MOV @PSP+,TOS MOV @IP+,PC + .IFNDEF TWODUP +; https://forth-standard.org/standard/core/TwoDUP +; 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells + FORTHWORD "2DUP" +TWODUP MOV TOS,-2(PSP) ; 3 + MOV @PSP,-4(PSP) ; 4 + SUB #4,PSP ; 1 + MOV @IP+,PC ; 4 + .ENDIF + ; https://forth-standard.org/standard/core/TwoDROP ; 2DROP x1 x2 -- drop 2 cells FORTHWORD "2DROP" @@ -286,12 +606,35 @@ TWOSTORE MOV @PSP+,0(TOS) MOV 6(PSP),TOS ; -- x1 x2 x3 x4 x1 x2 MOV @IP+,PC +;------------------------------------------------------------------------------- +; MEMORY OPERATIONS +;------------------------------------------------------------------------------- + .IFNDEF FETCH +;https://forth-standard.org/standard/core/Fetch +; C@ c-addr -- word fetch word from memory + FORTHWORD "@" +FETCH MOV @TOS,TOS ;2 + MOV @IP+,PC ;4 + .ENDIF + + .IFNDEF STORE +;https://forth-standard.org/standard/core/Store +; C! word c-addr -- store word in memory + FORTHWORD "!" +STORE MOV @PSP+,0(TOS) ;4 + MOV @PSP+,TOS ;2 + MOV @IP+,PC + .ENDIF + + .IFNDEF CFETCH ;https://forth-standard.org/standard/core/CFetch ; C@ c-addr -- char fetch char from memory FORTHWORD "C@" CFETCH MOV.B @TOS,TOS ;2 MOV @IP+,PC ;4 + .ENDIF + .IFNDEF CSTORE ;https://forth-standard.org/standard/core/CStore ; C! char c-addr -- store char in memory FORTHWORD "C!" @@ -299,105 +642,264 @@ CSTORE MOV.B @PSP+,0(TOS) ;4 ADD #1,PSP ;1 MOV @PSP+,TOS ;2 MOV @IP+,PC + .ENDIF + .IFNDEF CCOMMA ;https://forth-standard.org/standard/core/CComma ; C, char -- append char FORTHWORD "C," -CCOMMA MOV &DDP,W +CCOMMA MOV &DP,W MOV.B TOS,0(W) - ADD #1,&DDP + ADD #1,&DP MOV @PSP+,TOS MOV @IP+,PC + .ENDIF -;https://forth-standard.org/standard/core/AND -;C AND x1 x2 -- x3 logical AND - FORTHWORD "AND" -ANDD AND @PSP+,TOS +;https://forth-standard.org/standard/core/PlusStore +;C +! n/u a-addr -- add to memory + FORTHWORD "+!" +PLUSSTORE ADD @PSP+,0(TOS) + MOV @PSP+,TOS MOV @IP+,PC -;https://forth-standard.org/standard/core/OR -;C OR x1 x2 -- x3 logical OR - FORTHWORD "OR" -ORR BIS @PSP+,TOS +;https://forth-standard.org/standard/core/ALIGNED +;C ALIGNED addr -- a-addr align given addr + FORTHWORD "ALIGNED" +ALIGNED BIT #1,TOS + ADDC #0,TOS MOV @IP+,PC -;https://forth-standard.org/standard/core/XOR -;C XOR x1 x2 -- x3 logical XOR - FORTHWORD "XOR" -XORR XOR @PSP+,TOS +;https://forth-standard.org/standard/core/ALIGN +;C ALIGN -- align HERE + FORTHWORD "ALIGN" +ALIGNN BIT #1,&DP ; 3 + ADDC #0,&DP ; 4 MOV @IP+,PC -;https://forth-standard.org/standard/core/INVERT -;C INVERT x1 -- x2 bitwise inversion - FORTHWORD "INVERT" - XOR #-1,TOS +;https://forth-standard.org/standard/core/CHARS +;C CHARS n1 -- n2 chars->adrs units + FORTHWORD "CHARS" MOV @IP+,PC -;https://forth-standard.org/standard/core/LSHIFT -;C LSHIFT x1 u -- x2 logical L shift u places - FORTHWORD "LSHIFT" -LSHIFT MOV @PSP+,W - AND #1Fh,TOS ; no need to shift more than 16 - JZ LSH_X -LSH_1 ADD W,W - SUB #1,TOS - JNZ LSH_1 -LSH_X MOV W,TOS +;https://forth-standard.org/standard/core/CHARPlus +;C CHAR+ c-addr1 -- c-addr2 add char size + FORTHWORD "CHAR+" + ADD #1,TOS MOV @IP+,PC -;https://forth-standard.org/standard/core/RSHIFT -;C RSHIFT x1 u -- x2 logical R shift u places - FORTHWORD "RSHIFT" -RSHIFT MOV @PSP+,W - AND #1Fh,TOS ; no need to shift more than 16 - JZ RSH_X -RSH_1 BIC #1,SR ; CLRC - RRC W - SUB #1,TOS - JNZ RSH_1 -RSH_X MOV W,TOS +;https://forth-standard.org/standard/core/CELLS +;C CELLS n1 -- n2 cells->adrs units + FORTHWORD "CELLS" + ADD TOS,TOS MOV @IP+,PC -;https://forth-standard.org/standard/core/TwoTimes -;C 2* x1 -- x2 arithmetic left shift - FORTHWORD "2*" -TWOTIMES ADD TOS,TOS +;https://forth-standard.org/standard/core/CELLPlus +;C CELL+ a-addr1 -- a-addr2 add cell size + FORTHWORD "CELL+" + ADD #2,TOS MOV @IP+,PC -;https://forth-standard.org/standard/core/TwoDiv -;C 2/ x1 -- x2 arithmetic right shift - FORTHWORD "2/" -TWODIV RRA TOS +; ------------------------------------------------------------------------------ +; CONTROL STRUCTURES +; ------------------------------------------------------------------------------ +; THEN and BEGIN compile nothing +; DO compile one word +; IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words +; LEAVE compile three words + + FORTHWORDIMM "IF" ; immediate +; https://forth-standard.org/standard/core/IF +; IF -- IFadr initialize conditional forward branch +IFF SUB #2,PSP ; + MOV TOS,0(PSP) ; + MOV &DP,TOS ; -- HERE + ADD #4,&DP ; compile one word, reserve one word + MOV #QFBRAN,0(TOS) ; -- HERE compile QFBRAN + ADD #2,TOS ; -- HERE+2=IFadr MOV @IP+,PC -;https://forth-standard.org/standard/core/MAX -;C MAX n1 n2 -- n3 signed maximum - FORTHWORD "MAX" -MAX CMP @PSP,TOS ; n2-n1 - JL SELn1 ; n2 [IFadr] + SUB #2,W ; HERE+2 + MOV W,TOS ; -- ELSEadr MOV @IP+,PC -;https://forth-standard.org/standard/core/MIN -;C MIN n1 n2 -- n3 signed minimum - FORTHWORD "MIN" -MIN CMP @PSP,TOS ; n2-n1 - JL SELn2 ; n2 HERE + MOV TOS,-2(W) ; DOadr --> HERE+2 +; resolve all "leave" adr +LEAVELOOP MOV &LEAVEPTR,TOS ; -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR ; -- + MOV @TOS,TOS ; -- first LeaveStack value + CMP #0,TOS ; -- = value left by DO ? + JZ LOOPEND + MOV W,0(TOS) ; move adr after loop as UNLOOP adr + JMP LEAVELOOP +LOOPEND MOV @PSP+,TOS + MOV @IP+,PC + +; Primitive XPLOOP; compiled by +LOOP +;Z (+loop) n -- R: sys1 sys2 -- | sys1 sys2 +; run-time code for +LOOP +; Add n to the loop index. If loop terminates, clean up the +; return stack and skip the branch. Else take the inline branch. +XPLOO ADD TOS,0(RSP) ;4 increment INDEX by TOS value + MOV @PSP+,TOS ;2 get new TOS, doesn't change flags + JMP XLOOPNEXT ;2 + + FORTHWORDIMM "+LOOP" ; immediate +; https://forth-standard.org/standard/core/PlusLOOP +; +LOOP adrs -- L-- an an-1 .. a1 0 +PLUSLOOP MOV #XPLOO,X + JMP LOOPNEXT + + FORTHWORDIMM "CASE" +; https://forth-standard.org/standard/core/CASE +; CASE ; -- #of-1 + mDOCOL + .word LIT,0 + .word EXIT + + FORTHWORDIMM "OF" +; https://forth-standard.org/standard/core/OF +; OF ; #of-1 -- orgOF #of + mDOCOL + .word ONEPLUS ; count OFs + .word TOR ; move off the stack in case the control-flow stack is the data stack. + .word LIT,OVER,COMMA + .word LIT,EQUAL,COMMA ; copy and test case value + .word IFF ; add orig to control flow stack + .word LIT,DROP,COMMA ; discards case value if = + .word RFROM ; we can bring count back now + .word EXIT + + FORTHWORDIMM "ENDOF" +; https://forth-standard.org/standard/core/ENDOF +; ENDOF ; orgOF #of -- orgENDOF #of + mDOCOL + .word TOR ; move off the stack in case the control-flow stack is the data stack. + .word ELSS + .word RFROM ; we can bring count back now + .word EXIT + + FORTHWORDIMM "ENDCASE" +; https://forth-standard.org/standard/core/ENDCASE +; ENDCASE ; orgENDOF1..orgENDOFn #of -- + mDOCOL + .word LIT,DROP,COMMA + .word LIT,0,XDO +ENDCASELOOP .word THEN + .word XLOOP,ENDCASELOOP + .word EXIT + ;https://forth-standard.org/standard/core/CHAR ;C CHAR -- char parse ASCII character FORTHWORD "CHAR" CHARR mDOCOL - .word FBLANK,WORDD,ONEPLUS,CFETCH,EXIT + .word BL,WORDD,ONEPLUS,CFETCH,EXIT ;https://forth-standard.org/standard/core/BracketCHAR ;C [CHAR] -- compile character literal @@ -407,6 +909,35 @@ BRACCHAR mDOCOL .word lit,lit,COMMA .word COMMA,EXIT + .IFNDEF MOVE +; https://forth-standard.org/standard/core/MOVE +; MOVE addr1 addr2 u -- smart move +; VERSION FOR 1 ADDRESS UNIT = 1 CHAR + FORTHWORD "MOVE" +MOVE MOV TOS,W ; W = cnt + MOV @PSP+,Y ; Y = addr2 = dst + MOV @PSP+,X ; X = addr1 = src + MOV @PSP+,TOS ; pop new TOS + CMP #0,W ; count = 0 ? + JZ MOVEND ; if 0, already done ! + CMP X,Y ; dst = src ? + JZ MOVEND ; already done ! + JC MOVEDOWN ; U< if src > dst +MOVEUPLOOP MOV.B @X+,0(Y) ; copy W bytes + ADD #1,Y + SUB #1,W + JNZ MOVEUPLOOP + MOV @IP+,PC ; out 1 of MOVE ====> +MOVEDOWN ADD W,Y ; copy W bytes beginning with the end + ADD W,X +MOVEDOWNLOO SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) + SUB #1,W + JNZ MOVEDOWNLOO +MOVEND MOV @IP+,PC ; out 2 of MOVE ====> + .ENDIF + ;https://forth-standard.org/standard/core/FILL ;C FILL c-addr u char -- fill memory with char FORTHWORD "FILL" @@ -423,18 +954,18 @@ FILL_X MOV @PSP+,TOS ; pop new TOS ;https://forth-standard.org/standard/core/HEX FORTHWORD "HEX" -HEX MOV #16,&BASE +HEX MOV #16,&BASEADR MOV @IP+,PC ;https://forth-standard.org/standard/core/DECIMAL FORTHWORD "DECIMAL" -DECIMAL MOV #10,&BASE +DECIMAL MOV #10,&BASEADR MOV @IP+,PC ; https://forth-standard.org/standard/core/HERE ; HERE -- addr returns memory ptr - FORTHWORD "HERE" - MOV #HERE,PC +HERE FORTHWORD "HERE" + MOV #HEREXEC,PC ;https://forth-standard.org/standard/core/p ;C ( \ -- paren ; skip input until ) @@ -449,7 +980,7 @@ DOTPAREN MOV #0,&CAPS mDOCOL .word lit,')',WORDD .word COUNT,TYPE - .word FBLANK,LIT,CAPS,STORE + .word BL,LIT,CAPS,STORE .word EXIT ;https://forth-standard.org/standard/core/J @@ -471,10 +1002,10 @@ UNLOOP ADD #4,RSP ;https://forth-standard.org/standard/core/LEAVE ;C LEAVE -- L: -- adrs FORTHWORDIMM "LEAVE" ; immediate -LEAV MOV &DDP,W ; compile three words +LEAV MOV &DP,W ; compile three words MOV #UNLOOP,0(W) ; [HERE] = UNLOOP MOV #BRAN,2(W) ; [HERE+2] = BRAN - ADD #6,&DDP ; [HERE+4] = After LOOP adr + ADD #6,&DP ; [HERE+4] = After LOOP adr ADD #2,&LEAVEPTR ADD #4,W MOV &LEAVEPTR,X @@ -484,16 +1015,42 @@ LEAV MOV &DDP,W ; compile three words ;https://forth-standard.org/standard/core/RECURSE ;C RECURSE -- recurse to current definition (compile current definition) FORTHWORDIMM "RECURSE" ; immediate -RECURSE MOV &DDP,X ; +RECURSE MOV &DP,X ; MOV &LAST_CFA,0(X) ; - ADD #2,&DDP ; + ADD #2,&DP ; MOV @IP+,PC + .IFNDEF TOBODY ; https://forth-standard.org/standard/core/toBODY ; >BODY -- addr leave BODY of a CREATEd word; also leave default ACTION-OF primary DEFERred word FORTHWORD ">BODY" TOBODY ADD #4,TOS MOV @IP+,PC + .ENDIF + +; https://forth-standard.org/standard/core/EXECUTE +; EXECUTE i*x xt -- j*x execute Forth word at 'xt' + FORTHWORD "EXECUTE" + PUSH TOS ; 3 push xt + MOV @PSP+,TOS ; 2 + MOV @RSP+,PC ; 4 xt --> PC + +; https://forth-standard.org/standard/core/EVALUATE +; EVALUATE ; i*x c-addr u -- j*x interpret string + FORTHWORD "EVALUATE" + MOV #SOURCE_LEN,X ; 2 + MOV @X+,S ; 2 S = SOURCE_LEN + MOV @X+,T ; 2 T = SOURCE_ORG + MOV @X+,W ; 2 W = TOIN + PUSHM #4,IP ; 6 PUSHM IP,S,T,W + mASM2FORTH + .word INTERPRET + mNEXTADR + MOV @RSP+,&TOIN ; 4 + MOV @RSP+,&SOURCE_ORG ; 4 + MOV @RSP+,&SOURCE_LEN ; 4 + MOV @RSP+,IP + MOV @IP+,PC ;https://forth-standard.org/standard/core/SOURCE ;C SOURCE -- adr u of current input buffer @@ -514,7 +1071,7 @@ TOBODY ADD #4,TOS ;C BASE -- a-addr holds conversion radix FORTHWORD "BASE" CALL rDOCON - .word BASE ; VARIABLE address in RAM space + .word BASEADR ; VARIABLE address in RAM space ;https://forth-standard.org/standard/core/toIN ;C >IN -- a-addr holds offset in input stream @@ -522,11 +1079,56 @@ TOBODY ADD #4,TOS FTOIN CALL rDOCON .word TOIN ; VARIABLE address in RAM space +; https://forth-standard.org/standard/core/BL +; BL -- char an ASCII space + FORTHWORD "BL" + CALL rDOCON + .word 20h + + .IFNDEF PAD ;https://forth-standard.org/standard/core/PAD ; PAD -- pad address FORTHWORD "PAD" PAD CALL rDOCON .WORD PAD_ORG + .ENDIF + +; https://forth-standard.org/standard/core/VARIABLE +; VARIABLE -- define a Forth VARIABLE + FORTHWORD "VARIABLE" + mDOCOL + .word CREATE + mNEXTADR + MOV #DOVAR,-4(W) ; CFA = CALL rDOVAR + MOV @RSP+,IP + MOV @IP+,PC + +; https://forth-standard.org/standard/core/CONSTANT +; CONSTANT n -- define a Forth CONSTANT + FORTHWORD "CONSTANT" + mDOCOL + .word CREATE + mNEXTADR + MOV TOS,-2(W) ; PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + +; https://forth-standard.org/standard/core/DEFER +; Skip leading space delimiters. Parse name delimited by a space. +; Create a definition for name with the execution semantics defined below. +; +; name Execution: -- +; Execute the xt that name is set to execute, i.e. NEXT (nothing), +; until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name. + FORTHWORD "DEFER" + mDOCOL + .word CREATE + mNEXTADR + MOV #4030h,-4(W) ;4 first CELL = MOV @PC+,PC = BR #addr + MOV #NEXTADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default + MOV @RSP+,IP + MOV @IP+,PC ; https://forth-standard.org/standard/core/TO ; TO name Run-time: ( x -- ) @@ -540,7 +1142,7 @@ PAD CALL rDOCON ; Skip leading space delimiters. Parse name delimited by a space. ; Create a definition for name with the execution semantics defined below, ; with an initial value equal to x. -; +; ; name Execution: ( -- x ) ; Place x on the stack. The value of x is that given when name was created, ; until the phrase x TO name is executed, causing a new value of x to be assigned to name. @@ -548,13 +1150,14 @@ PAD CALL rDOCON mDOCOL .word CREATE,COMMA .word DOES - .word $+2 + mNEXTADR MOV @RSP+,IP BIT #UF9,SR ; see TO - JNZ VALUENEXT + JNZ STOREVALUE MOV @TOS,TOS ; execute Fetch MOV @IP+,PC -VALUENEXT BIC #UF9,SR ; clear 'TO' flag +STOREVALUE BIC #UF9,SR ; clear 'TO' flag MOV @PSP+,0(TOS) ; 4 execute Store MOV @PSP+,TOS ; 2 MOV @IP+,PC ; 4 + diff --git a/ADDON/FixPoint.asm b/ADDON/FixPoint.asm index 7f69be9..da8e81a 100644 --- a/ADDON/FixPoint.asm +++ b/ADDON/FixPoint.asm @@ -68,10 +68,10 @@ UDMT1 CMP #0,X BIT Y,TOS ; 1 TEST ACTUAL BIT MRhi JMP UDMT3 UDMT2 BIT X,W ; 1 TEST ACTUAL BIT MRlo -UDMT3 JZ UDMT4 ; +UDMT3 JZ UDMT4 ; ADD IP,4(PSP) ; 3 IF 1: ADD MDlo TO RESlo ADDC T,2(PSP) ; 3 ADDC MDhi TO REShi - ADDC M,Q ; 1 ADDC MDLO TO RESLO + ADDC M,Q ; 1 ADDC MDLO TO RESLO ADDC P,R ; 1 ADDC MDHI TO RESHI UDMT4 ADD IP,IP ; 1 (RLA LSBs) MDlo *2 ADDC T,T ; 1 (RLC MSBs) MDhi *2 @@ -90,7 +90,7 @@ UDMT4 ADD IP,IP ; 1 (RLA LSBs) MDlo *2 FORTHWORD "F*" ; s15.16 * s15.16 --> s15.16 result MOV 2(PSP),S ; XOR TOS,S ; MDhi XOR MRhi --> S keep sign of result - BIT #8000h,2(PSP) ; MD < 0 ? + BIT #8000h,2(PSP) ; MD < 0 ? JZ FSTAR1 ; no XOR #-1,2(PSP) XOR #-1,4(PSP) @@ -98,7 +98,7 @@ UDMT4 ADD IP,IP ; 1 (RLA LSBs) MDlo *2 ADDC #0,2(PSP) FSTAR1 mDOCOL .word DABS,UDMT - .word $+2 ; -- RES0 RES1 RES2 RES3 + .word $+2 ; -- RES0 RES1 RES2 RES3 MOV @RSP+,IP MOV @PSP+,TOS ; -- RES0 RES1 RES2 MOV @PSP+,0(PSP) ; -- RES1 RES2 @@ -108,7 +108,7 @@ FSTARSIGN AND #-1,S ; clear V, set N XOR #-1,TOS ADD #1,0(PSP) ADDC #0,TOS -FSTAREND MOV @IP+,PC +FSTAREND MOV @IP+,PC FORTHWORD "F/" ; s15.16 / s15.16 --> s15.16 result @@ -120,7 +120,7 @@ FDIV PUSHM #4,rDOVAR ; 6 save rDOVAR to rDOCOL regs to use M to R ali MOV #0,T ; DVDlo = 0 MOV X,S ; XOR TOS,S ; MDhi XOR MRhi --> S keep sign of result - AND #-1,X ; MD < 0 ? + AND #-1,X ; MD < 0 ? JGE FDIV1 ; no XOR #-1,Y ; lo XOR #-1,X ; hi @@ -132,7 +132,7 @@ FDIV1 AND #-1,TOS XOR #-1,TOS ADD #1,M ADDC #0,TOS -FDIV2 +FDIV2 ; unsigned 32-BIT DIVIDEND : 32-BIT DIVISOR --> 32-BIT QUOTIENT, 32-BIT REMAINDER ; DVDhi|DVDlo : DVRhi|DVRlo --> QUOThi|QUOTlo, REMAINDER ; FORTHWORD "UD/MOD" @@ -149,18 +149,18 @@ Q322 JNC Q323 ;2 yes: REM U< DIV Q323 ADDC R,R ;1 RLC quotLO ADDC Q,Q ;1 RLC quotHI SUB #1,P ;1 Decrement loop counter - JN Q6432END ;2 loop back if count>=0 + JN Q6432END ;2 loop back if count>=0 ADD T,T ;1 RLA DVDlo ADDC Y,Y ;1 RLC DVDhi ADDC X,X ;1 RLC REMlo ADDC W,W ;1 RLC REMhi - JNC Q321 ; + JNC Q321 ; SUB M,X ;1 REMlo - DIVlo SUBC TOS,W ;1 REMhi - DIVhi BIS #1,SR JMP Q323 Q6432END -; MOV X,4(PSP) ; REMlo +; MOV X,4(PSP) ; REMlo ; MOV W,2(PSP) ; REMhi ; ADD #4,PSP ; skip REMlo REMhi MOV R,0(PSP) ; QUOTlo @@ -184,7 +184,7 @@ FNUMS MOV @PSP,S ; -- Qlo Qhi len S = Qhi MOV TOS,2(PSP) ; -- len Qlo len MOV #FNUMSNEXT,IP ; FNUMSLOOP MOV &BASE,TOS ; -- len Qlo base - MOV #UMSTAR,PC + MOV #UMSTAR,PC FNUMSNEXT .word $+2 ; -- len RESlo digit SUB #2,IP CMP #10,TOS ; digit to char @@ -203,7 +203,7 @@ FNUMS2CHAR ADD #30h,TOS ; -- len RESlo char MOV #0,0(PSP) ; -- Qhi 0 len MOV #HOLDS_ORG,X ; -- Qhi 0 len X= org JMP HOLDS1 - + .ELSEIF ; hardware multiplier FORTHWORD "F*" ; signed s15.16 multiplication --> s15.16 result @@ -227,7 +227,7 @@ FDIV PUSHM #4,rDOVAR ; 6 PUSHM rDOVAR to rDOCOL to use M to R alias MOV #0,T ; DVDlo = 0 MOV X,S ; XOR TOS,S ; MDhi XOR MRhi --> S keep sign of result - AND #-1,X ; MD < 0 ? + AND #-1,X ; MD < 0 ? JGE FDIV1 ; no XOR #-1,Y ; lo XOR #-1,X ; hi @@ -239,7 +239,7 @@ FDIV1 AND #-1,TOS XOR #-1,TOS ADD #1,M ADDC #0,TOS -FDIV2 +FDIV2 ; unsigned 32-BIT DIVIDEND : 32-BIT DIVISOR --> 32-BIT QUOTIENT, 32-BIT REMAINDER ; DVDhi|DVDlo : DVRhi|DVRlo --> QUOThi|QUOTlo, REMAINDER ; FORTHWORD "UD/MOD" @@ -256,19 +256,19 @@ Q322 JNC Q323 ;2 yes: REM U< DIV Q323 ADDC R,R ;1 RLC quotLO ADDC Q,Q ;1 RLC quotHI SUB #1,P ;1 Decrement loop counter - JN Q6432END ;2 loop back if count>=0 + JN Q6432END ;2 loop back if count>=0 ADD T,T ;1 RLA DVDlo ADDC Y,Y ;1 RLC DVDhi ADDC X,X ;1 RLC REMlo ADDC W,W ;1 RLC REMhi - JNC Q321 ; + JNC Q321 ; SUB M,X ;1 REMlo - DIVlo SUBC TOS,W ;1 REMhi - DIVhi BIS #1,SR JMP Q323 Q6432END -; MOV X,4(PSP) ; REMlo -; MOV W,2(PSP) ; REMhi +; MOV X,4(PSP) ; REMlo +; MOV W,2(PSP) ; REMhi ; MOV @IP+,PC ; 33 words AND #-1,S ; clear V, set N JGE FDIVEND ; if positive @@ -279,7 +279,7 @@ Q6432END FDIVEND MOV R,0(PSP) ; QUOTlo MOV Q,TOS ; QUOThi POPM #4,rDOVAR ; 6 restore rDOCOL to rDOVAR - MOV @IP+,PC + MOV @IP+,PC ; F#S Qlo Qhi u -- Qhi 0 convert fractionnal part of Q15.16 fixed point number ; with u digits @@ -290,7 +290,7 @@ FNUMS MOV 2(PSP),X ; -- Qlo Qhi u X = Qlo MOV TOS,T ; T = limit MOV #0,S ; S = count FNUMSLOOP MOV @PSP,&MPY ; Load 1st operand - MOV &BASE,&OP2 ; Load 2nd operand + MOV &BASEADR,&OP2 ; Load 2nd operand MOV &RES0,0(PSP) ; -- Qhi Qlo' x low result on stack MOV &RES1,TOS ; -- Qhi Qlo' digit high result in TOS CMP #10,TOS ; digit to char @@ -305,13 +305,13 @@ FNUMS2CHAR ADD #30h,TOS MOV #0,0(PSP) ; -- Qhi 0 len MOV #HOLDS_ORG,X ; -- Qhi 0 len X= org JMP HOLDS1 - + .ENDIF ; of hardware MPY FORTHWORD "F." ; display a Q15.16 number with 4 digits after comma MOV TOS,S ; S = sign MOV #4,T ; T = 4 preset 4 digits for base 16 by default - MOV &BASE,W + MOV &BASEADR,W CMP #0Ah,W JNZ FDOT1 ; if not base 10 ADD #1,T ; T = 5 set 5 digits @@ -320,18 +320,18 @@ FDOT1 CMP #2,W ; JNZ FDOT2 ; if not base 2 MOV #10h,T ; T = 16 set 16 digits FDOT2 PUSHM #3,IP ; R-- IP S=sign T=#digit - ASMtoFORTH + mASM2FORTH .word LESSNUM ; -- uQlo Qhi .word DABS ; -- uQlo uQhi R-- IP sign #digit .word RFROM ; -- uQlo uQhi u R-- IP sign - .word FNUMS ; -- uQhi 0 - .word LIT,2Ch,HOLD; $2C = char ',' + .word FNUMS ; -- uQhi 0 + .word LIT,',',HOLD; .word NUMS ; -- 0 0 .word RFROM ; -- 0 0 Qhi R-- IP - .word SIGN ; -- 0 0 - .word NUMGREATER ; -- addr len + .word SIGN ; -- 0 0 + .word NUMGREATER ; -- addr len .word TYPE ; -- - .word FBLANK,EMIT ; -- + .word BL,EMIT ; -- .word EXIT FORTHWORD "S>F" ; convert a signed number to a Q15.16 (signed) number diff --git a/ADDON/SD_TOOLS.asm b/ADDON/SD_TOOLS.asm index bb01c09..5a16f43 100644 --- a/ADDON/SD_TOOLS.asm +++ b/ADDON/SD_TOOLS.asm @@ -1,5 +1,13 @@ ; -*- coding: utf-8 -*- + .IFNDEF ANDD +;https://forth-standard.org/standard/core/AND +;C AND x1 x2 -- x3 logical AND + FORTHWORD "AND" +ANDD AND @PSP+,TOS + MOV @IP+,PC + .ENDIF + .IFNDEF MAX ;https://forth-standard.org/standard/core/MAX @@ -113,6 +121,7 @@ DUMP PUSH IP ADD @PSP,TOS ; -- ORG END ASMtoFORTH .word SWAP ; -- END ORG + .word LIT,FFF0h,AND ; -- END ORG_modulo_16 .word xdo ; -- DUMP1 .word CR .word II,lit,4,UDOTR,SPACE ; generate address @@ -158,7 +167,7 @@ DisplaySector ; ----------------------------------; ; read first sector of Cluster and dump it ; ----------------------------------; - FORTHWORD "CLUSTR." ; cluster. -- don't forget to add decimal point to your sector number (if < 65536) + FORTHWORD "CLUSTER." ; cluster. -- don't forget to add decimal point to your sector number (if < 65536) ; ----------------------------------; CLUSTER BIT.B #CD_SD,&SD_CDIN ; test Card Detect: memory card present ? JZ CD_CLUST_OK ; @@ -196,11 +205,6 @@ CLUSTER1 RRA W ; shift one right multiplicator MOV TOS,2(PSP) ; save TOS MOV &DIRclusterL,0(PSP) ; MOV &DIRclusterH,TOS ; - CMP #0,TOS - JNZ CLUSTER - CMP #1,0(PSP) ; cluster 1 ? - JNZ CLUSTER - MOV &OrgRootDir,0(PSP) ; if yes, special case of FAT16 OrgRootDir - JMP SECTOR + JMP CLUSTER ; ----------------------------------; diff --git a/ADDON/UTILITY.asm b/ADDON/UTILITY.asm index 2e0c5e9..a3dbb1a 100644 --- a/ADDON/UTILITY.asm +++ b/ADDON/UTILITY.asm @@ -1,6 +1,6 @@ ; -*- coding: utf-8 -*- - FORTHWORD "{TOOLS}" + FORTHWORD "{UTILITY}" MOV @IP+,PC .IFNDEF TOR @@ -25,7 +25,26 @@ ANDD AND @PSP+,TOS ;C C@ c-addr -- char fetch char from memory FORTHWORD "C@" CFETCH MOV.B @TOS,TOS ;2 - MOV @IP+,PC ;4 + MOV @IP+,PC ;4 + .ENDIF + + .IFNDEF ULESS +; https://forth-standard.org/standard/core/Uless +; U< u1 u2 -- flag test u1 n1 n2 -- flag + FORTHWORD "U>" + SUB @PSP+,TOS ; 2 + JNC UTOSTRUE ; 2 flag = true, Z = 0 +UTOSFALSE AND #0,TOS ;1 flag Z = 1 + MOV @IP+,PC ;4 .ENDIF .IFNDEF SPACE @@ -55,6 +74,91 @@ SPACESNEXT2 MOV @PSP+,TOS ; -- drop n .ENDIF + .IFNDEF TWODUP +; https://forth-standard.org/standard/core/TwoDUP +; 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells + FORTHWORD "2DUP" +TWODUP MOV TOS,-2(PSP) ; 3 + MOV @PSP,-4(PSP) ; 4 + SUB #4,PSP ; 1 + MOV @IP+,PC ; 4 + .ENDIF + + .IFNDEF XDO +; Primitive XDO; compiled by DO +;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO +; n1|u1=limit, n2|u2=index +XDO MOV #8000h,X ;2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X ;2 + MOV TOS,Y ;1 loop ctr = index+fudge + ADD X,Y ;1 Y = INDEX + PUSHM #2,X ;4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS ;2 + MOV @IP+,PC ;4 + + FORTHWORDIMM "DO" ; immediate +; https://forth-standard.org/standard/core/DO +; DO -- DOadr L: -- 0 +DO SUB #2,PSP ; + MOV TOS,0(PSP) ; + ADD #2,&DP ; make room to compile xdo + MOV &DP,TOS ; -- HERE+2 + MOV #XDO,-2(TOS) ; compile xdo + ADD #2,&LEAVEPTR ; -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W ; + MOV #0,0(W) ; -- HERE+2 L-- 0 + MOV @IP+,PC + +; Primitive XLOOP; compiled by LOOP +;Z (loop) R: sys1 sys2 -- | sys1 sys2 +; run-time code for LOOP +; Add 1 to the loop index. If loop terminates, clean up the +; return stack and skip the branch. Else take the inline branch. +; Note that LOOP terminates when index=8000h. +XLOOP ADD #1,0(RSP) ;4 increment INDEX +XLOOPNEXT BIT #100h,SR ;2 is overflow bit set? + JZ XLOOPDO ;2 no overflow = loop + ADD #4,RSP ;1 empties RSP + ADD #2,IP ;1 overflow = loop done, skip branch ofs + MOV @IP+,PC ;4 14~ taken or not taken xloop/loop +XLOOPDO MOV @IP,IP + MOV @IP+,PC ;4 14~ taken or not taken xloop/loop + + FORTHWORDIMM "LOOP" ; immediate +; https://forth-standard.org/standard/core/LOOP +; LOOP DOadr -- L-- an an-1 .. a1 0 +LOO MOV #XLOOP,X +LOOPNEXT ADD #4,&DP ; make room to compile two words + MOV &DP,W + MOV X,-4(W) ; xloop --> HERE + MOV TOS,-2(W) ; DOadr --> HERE+2 +; resolve all "leave" adr +LEAVELOOP MOV &LEAVEPTR,TOS ; -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR ; -- + MOV @TOS,TOS ; -- first LeaveStack value + CMP #0,TOS ; -- = value left by DO ? + JZ LOOPEND + MOV W,0(TOS) ; move adr after loop as UNLOOP adr + JMP LEAVELOOP +LOOPEND MOV @PSP+,TOS + MOV @IP+,PC + +; Primitive XPLOOP; compiled by +LOOP +;Z (+loop) n -- R: sys1 sys2 -- | sys1 sys2 +; run-time code for +LOOP +; Add n to the loop index. If loop terminates, clean up the +; return stack and skip the branch. Else take the inline branch. +XPLOO ADD TOS,0(RSP) ;4 increment INDEX by TOS value + MOV @PSP+,TOS ;2 get new TOS, doesn't change flags + JMP XLOOPNEXT ;2 + + FORTHWORDIMM "+LOOP" ; immediate +; https://forth-standard.org/standard/core/PlusLOOP +; +LOOP adrs -- L-- an an-1 .. a1 0 +PLUSLOOP MOV #XPLOO,X + JMP LOOPNEXT + .ENDIF + .IFNDEF II ; https://forth-standard.org/standard/core/I ; I -- n R: sys1 sys2 -- sys1 sys2 @@ -70,7 +174,7 @@ II SUB #2,PSP ;1 make room in TOS ;https://forth-standard.org/standard/tools/DotS FORTHWORD ".S" ; -- print of Param Stack and stack contents if not empty DOTS MOV TOS,-2(PSP) ; -- TOS ( tos x x ) - MOV PSP,TOS + MOV PSP,TOS SUB #2,TOS ; to take count that TOS is first cell MOV TOS,-6(PSP) ; -- TOS ( tos x PSP ) MOV #PSTACK,TOS ; -- P0 ( tos x PSP ) @@ -89,12 +193,12 @@ DOTS1 MOV TOS,-4(PSP) ; -- S0 ( tos S0 SP ) .word DROP,DROP,EXIT STKDISPL1 .word xdo STKDISPL2 .word II,FETCH,UDOT - .word lit,2,xploop,STKDISPL2 + .word lit,2,xploo,STKDISPL2 .word EXIT FORTHWORD ".RS" ; -- print of Return Stack and stack contents if not empty -DOTRS MOV TOS,-2(PSP) ; -- TOS ( tos x x ) +DOTRS MOV TOS,-2(PSP) ; -- TOS ( tos x x ) MOV RSP,-6(PSP) ; -- TOS ( tos x RSP ) MOV #RSTACK,TOS ; -- R0 ( tos x RSP ) JMP DOTS1 @@ -105,6 +209,42 @@ DOTRS MOV TOS,-2(PSP) ; -- TOS ( tos x x ) QUESTION MOV @TOS,TOS MOV #UDOT,PC + .IFNDEF QDUP +; https://forth-standard.org/standard/core/DUP +; DUP x -- x x duplicate top of stack + FORTHWORD "DUP" +QDUPNEXT SUB #2,PSP ; 2 push old TOS.. + MOV TOS,0(PSP) ; 3 ..onto stack +QDUPEND MOV @IP+,PC ; 4 + +; https://forth-standard.org/standard/core/qDUP +; ?DUP x -- 0 | x x DUP if nonzero + FORTHWORD "?DUP" +QDUP CMP #0,TOS + JZ QDUPEND + JNZ QDUPNEXT + .ENDIF + + .IFNDEF CR + FORTHWORD "CR" +; https://forth-standard.org/standard/core/CR +; CR -- send CR to the output device +CR MOV @PC+,PC + .word BODYCR +BODYCR mDOCOL ; send CR+LF to the default output device + .word XSQUOTE + .byte 2,0Dh,0Ah + .word TYPE,EXIT + .ENDIF + + .IFNDEF TWODIV +;https://forth-standard.org/standard/core/TwoDiv +;C 2/ x1 -- x2 arithmetic right shift + FORTHWORD "2/" +TWODIV RRA TOS + MOV @IP+,PC + .ENDIF + .SWITCH THREADS .CASE 1 @@ -115,11 +255,12 @@ WORDS mDOCOL .word CR .word LIT,CONTEXT,FETCH ; -- VOC_BODY WORDS1 .word FETCH ; -- NFA - .word QDUP ; -- 0 | -- NFA NFA + .word QDUP ; -- 0 | -- NFA NFA .word QFBRAN,WORDS2 ; -- NFA - .word DUP,DUP,COUNT ; -- NFA NFA addr count - .word lit,07Fh,ANDD,TYPE ; -- NFA NFA - .word CFETCH,lit,0Fh,ANDD + .word DUP,DUP,COUNT ; -- NFA NFA addr count + .word TWODIV,ANDD,TYPE ; -- NFA NFA + .word CFETCH,TWODIV + .word lit,0Fh,ANDD .word lit,10h,SWAP,MINUS .word SPACES .word lit,2,MINUS ; NFA -- LFA @@ -147,6 +288,35 @@ ROT MOV @PSP,W ; 2 fetch x2 MOV @IP+,PC ; 4 .ENDIF + .IFNDEF MOVE +; https://forth-standard.org/standard/core/MOVE +; MOVE addr1 addr2 u -- smart move +; VERSION FOR 1 ADDRESS UNIT = 1 CHAR + FORTHWORD "MOVE" +MOVE MOV TOS,W ; W = cnt + MOV @PSP+,Y ; Y = addr2 = dst + MOV @PSP+,X ; X = addr1 = src + MOV @PSP+,TOS ; pop new TOS + CMP #0,W ; count = 0 ? + JZ MOVEND ; if 0, already done ! + CMP X,Y ; dst = src ? + JZ MOVEND ; already done ! + JC MOVEDOWN ; U< if src > dst +MOVEUPLOOP MOV.B @X+,0(Y) ; copy W bytes + ADD #1,Y + SUB #1,W + JNZ MOVEUPLOOP + MOV @IP+,PC ; out 1 of MOVE ====> +MOVEDOWN ADD W,Y ; copy W bytes beginning with the end + ADD W,X +MOVEDOWNLOO SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) + SUB #1,W + JNZ MOVEDOWNLOO +MOVEND MOV @IP+,PC ; out 2 of MOVE ====> + .ENDIF + ;https://forth-standard.org/standard/tools/WORDS ;X WORDS -- list all words in first vocabulary in CONTEXT. 38 words FORTHWORD "WORDS" @@ -156,23 +326,22 @@ WORDS mDOCOL .word PAD,LIT,THREADS,DUP,PLUS .word MOVE ; BEGIN -WORDS2 .word LIT,0,DUP +WORDS2 .word LIT,0,DUP .word LIT,THREADS,DUP,PLUS ; I = ptr = thread*2 .word LIT,0 .word xdo ; DO -WORDS3 .word DUP - .word II,PAD,PLUS,FETCH ; old MAX NFA U< NFA ? +WORDS3 .word DUP,II,PAD,PLUS,FETCH ; old MAX NFA U< NFA ? .word ULESS,QFBRAN,WORDS4 ; no - .word DROP,DROP,II ; yes, replace old MAX of NFA by new MAX of NFA + .word TWODROP,II ; yes, replace old MAX of NFA by new MAX of NFA .word DUP,PAD,PLUS,FETCH ; -WORDS4 .word LIT,2,xploop,WORDS3 ; 2 +LOOP +WORDS4 .word LIT,2,xploo,WORDS3 ; 2 +LOOP .word QDUP ; MAX of NFA = 0 ? .word QFBRAN,WORDS5 ; WHILE .word DUP,LIT,2,MINUS,FETCH ; replace NFA MAX by its [LFA] - .word ROT,PAD,PLUS,STORE - .word DUP,COUNT ; display NFA MAX in 10 chars format - .word lit,07Fh,ANDD,TYPE - .word CFETCH,lit,0Fh,ANDD + .word ROT,PAD,PLUS,STORE + .word DUP,COUNT,TWODIV,TYPE ; display NFA MAX in 10 chars format + .word CFETCH,TWODIV + .word lit,0Fh,ANDD .word lit,10h,SWAP,MINUS .word SPACES .word BRAN,WORDS2 ; REPEAT @@ -230,13 +399,20 @@ UDOTR mDOCOL .word EXIT .ENDIF + .IFNDEF HERE +; https://forth-standard.org/standard/core/HERE +; HERE -- addr returns memory ptr +HERE FORTHWORD "HERE" + MOV #HEREXEC,PC + .ENDIF + ;https://forth-standard.org/standard/tools/DUMP FORTHWORD "DUMP" DUMP PUSH IP - PUSH &BASE ; save current base - MOV #10h,&BASE ; HEX base + PUSH &BASEADR ; save current base + MOV #10h,&BASEADR ; HEX base ADD @PSP,TOS ; -- ORG END - ASMtoFORTH + mASM2FORTH .word SWAP ; -- END ORG .word xdo ; -- DUMP1 .word CR @@ -252,9 +428,9 @@ DUMP3 .word II,CFETCH,lit,3,UDOTR .word SPACE,SPACE .word II,lit,10h,PLUS,II,xdo ; display 16 chars DUMP4 .word II,CFETCH - .word lit,7Eh,MIN,FBLANK,MAX,EMIT + .word lit,7Eh,MIN,BL,MAX,EMIT .word xloop,DUMP4 ; chars display loop - .word lit,10h,xploop,DUMP1 ; line loop - .word RFROM,lit,BASE,STORE ; restore current base + .word lit,10h,xploo,DUMP1 ; line loop + .word RFROM,lit,BASEADR,STORE ; restore current base .word EXIT diff --git a/FastForth.pdf b/FastForth.pdf deleted file mode 100644 index 6ee8457619fed8b98ce22e46ce2576050dcd56d4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 113033 zcma&NQ;;r96M(n2ZQC}^+P3+wZQHhO+qP}{ti5~I$oD6y+$0yd>*|@BscFr0JvHQt zqT=+-4D2xE!zIH#!)?R)Ff2q&ME1s3FnoNBvH&}C7YicR|1`>s;+8fp04GLq8zUEh zD8R(t6d)h~U*uPXbxnEj!pxEfi|@TedBNg6@c?;;s=E@ zgL~6Ey^F`v4I&07mnLJaUcBQcT1=%56(%%!?*Q*Me|V0!|NULzcb(78$@`G`r5pdT zTsrc^8Ckaf{k#$U{d@6yjsEo8|NVFSD&GG4o{wKH*C%cH@5T5p-}hCy2g>8cc>eG6 zQsh;IK9A=&g8`50H-kQpFZ!~~y20<&c)#!G+rv$~{)Y2@qgJB(i-Ouz}R6oxBD7(*Z;3dbE`Qb|~VJJ(ofpCJPcx&XUt{n74>I%6h-VSGZOvt?b2y0lz0 z_5F7S%2eB#Xs^tAw0jNx;sp0?TeMBNr@yk*17aI|tX%!GASGG9*|r-3CH;J_1b^Py zygn08$q(>Ll%Bhh%D_uKffoqb!tD>EWjbCU7BUe*r+g6g!EC>gLw1Jv?SG0ygFj!1 zZu&iN7pqUMe6*dj1Vh+ipSTLIG2y;cF%IgrzPdMY&AvX(0l&Ure$4u(5Xa~c&dW-q zKmuDJFl}%|L+zy6Ex)^af?CbuUw{N2vDf~v@d5bu1s4^j%SHW2%-%X}nujI}b8UWu zdw#|>g+cqh`hCiEmN70f$n4*?dI#99UhQb+ek`5jGWOB|##GE1*5Vyg$lpe9!M#UItXjSFnw>qy$+H3&%NikSUG>4X1?Rd0L z@6X#647Srd1Ive29?&VvtcRVj^GtD4KjuLhBy>^fqoVZf_5~o!7ZaA`NC)aiLNS zb-eY}B?m=x-h+#zT>j56IDusa`B%%?hv=gnZ{>vt>nuUaLNC3Uu+_0Todrcgw0jou zefQoOcpMCB^`P>a~Caz?$a zZCr8#G_Vt;OM^g1g@XO=sG=k*jYr0OOjbOJ+8;V2LY711KMX1Nkt$HxTyi{WNdVl$ z67k)bK83Pxe3hw7Om~%_;K2gno%d$n5!jmu-6NwbxH7XhOs`+7NF{dor> zYlG!5C@3cS^2FZB%FUoF*HGGWek+gJA6_YcCt{jHK{ezm1zbiRfK%105j+Uqb0m70 zfty=!l=VraHcemc-C1SaNJHMoDQFHpuKzxfP$yTUQCkTrnFWRcJ9*0X_KY@Mu$gPr zqyh|=mp_67Wti3ncRInpog?H*d8W4KtTO)xxo$35^Dmoo;vrVA)yqCLL$eq+CZy3~ z@jENfY(rnyB9$m>5R-}W@MEIa39T2b!75B~ zdnkRv+G+RT_sSE=Rt=LZ%-L=OUvr_}rK`@Uur&kI9VPb{PbD`pjh;z+`%#8az>^(b zCA6ky(Ef^sHZ{46-CG`21l{~C1m~4un&fZ@4#^@>arjKlDjol<_|Ec5Q*1JPE!Z>W z;9--iw@)U794>uI(JU*`t4mmD#m!EVLg;Y2RUk~EHa9T(jD^Rxw#cO>ws5kMo1itQ z{pm+%;v5D-guGCj$7S!czH%&NyA3}uX7*|syUA?hr>xi} zX-DI3@O6V?mW%4#waITnv4yd4+oGSPx3xUxUlX(Yo0PZu_V3Ioj>EYjb}bWm7$!6t z-UMv8?qPo%aY31j(4%&zxu73SFYZ(o-{SI$^-ot-YG~Y>Veg^URIuQdu!~cDo z;$q)kLEo)cmRk0IAZ|<2bW!mkrEpm{Wa;FOjtw=z(>B%{1%KK)p{Z@el8LRzJ`f0C zyWJn^;r0!*;@l=gwS{a_GJpEd$ny|a)aMOpJF0-fb3lHRX;Qj5tPW~3(bbOzb-(>x zIZF-01Pdn$aD=bZB_=aUcSREB#1da*i7G?kgs(0|VQE=C*jI30Ync&qD_ynf$Fv=z z;@4c%e(TOa0Qj-G!l7F)L%ufd1Cy*Sl?=BT3@q74rC#;+n{L}n7Lc%k{zzpdqQJQe zG9b6u<5$GQy)<4r3owCZV?j+|MRCD1*azc6i5x5E3B8Qui*Wg5|G~1+glPH49U@_; z@h>8IM>v?_qQv%)_#ei388k-^Ls7oe5Q;*tL#hu}or0CCF-=C%IAOBQkY%xo&J$B{%pQf~ZSm8>vs zd8s4-f-szI41@(ja1o`%Oxn=}PEod{Vj$no+}hcjNdbf@fu@_} zp6~?6Mv5dx*|sifpF1$m5so!adfhd0gwSS<^bJP*>m854l6J0+J07Zx${V6``}87 z0jpO{zdJ3pDmc2PCiwbd;Vg{AN@$~pu?*jhByf|sjO|GBiKb<5Lv)t_T8E~TY&RoE zNPDa2A9YhVJR*3F*R`V?W?l?)De*0(%7m~SxngSz~(#70uFdiOx7mKKBdnT=G1BW?}kqP9#E*C<-uHQm(D8uZ+mN?h& z!X=MIDVF)w&^3^G`F1^w9NiS`F1Q*BG~(+XR1f0 z8<{!uorh?ZORz!rLh1Ny)9j6EmCLiue|Kq#^mw)AL5xdxf|O0UG))OTcQup|H~V%d zz1%Fq#`gPQ^T%N=1Uqii^{jo`cJ7i*w)$?$Ddt4A9T**A*E5v%cF!dR2jZaG++v4U zHuLmEBLztny+pODOcRL2G>BbrF?;R(CHIy_)&1q`))zWHLM;P>3o3RyZ2^`<3nad zTWR1}H_?H52N>gy#Qnp@s-V3StCB?@65tR=OOn8;Ob-W1os#I>q1HO zD#$0>#wg#y0`F^A{Z(vD+L`ft&(Z?d?$bpoTiSO{!zGuF*+U{V?`#He1i>*Aoi`SgE)z`hh4RB)uG4z;_q z^3HXAYHnMy#bA6yKG4*`N9?EQjPGI5Npv!DK7nfZU-`sP#c#Ir3?J^O69C6<%1as1+~xzo9GUJRp(hMJnp-OugMZQ}V90FrVs5i&yJV{Tnf4 z>?B{gjBI1==p*^2E8X-aVrDv0TgnrQQQOka0N^7pt<@WL0!Z67NwGRK822Jg2IH~%AOmNTTA$j%6nG%6Vin?Q|M&(f23bck z?P8FXhQrqs2AjI$WLzbTY?Q_iPe2t;z|{2jrITGu8$*y68(|Q>R}3&1&Q@;JoI%8Q zR?}y#CzspK>Q9TX7=*0FlGVytCwTCZkP0VhL|JNb%fC(~SZ>GAj}f&ctLg=-LXA)B zEopW5tqJwF!tPZ~nk+587?Sl-iAkoYl3*&A6;man<=Cm3ab*j~>1GTzr`|m^fZjrZ zgXQGBolvCLuoP?+maRj~YW{(ffN6{@WwYGoaenXMdc^|wjRCtUoNm3QUbD3BuQo2@79;<{81t}kxa2$+wzaBG4z>nin;n=+VP$0xqHN_G(1ZW+`dz_eh|e8aj$=$Sgb);5T$M|`^GH!0ekxWF?ZmL z0~4O4URlf=QRCl&E76fr_%>6FWnmX%UQsA$b*nj-)|fR&GK}*N71ASsBC%5C1d*Et zhP2nt-^-Je`=3RSwe@pQ1KZUqwo-fKK#fPE(Olf~v?N?{IDVY|ZqgA8%}dX@gEW;- zW+kl_D>l0>O@I}nHhsQWS~tl6(JdNVkj{gA;lro@JNhAgL1Ec(`Vk3hHzFH8C-}Ef zDT5aru@c!FmwrwyK{NFXEhhq!8%Ts+nmh{_=9mXUgpqOUOpN%19h5fdv(jG6<=EL| z`D5Ewt=z9w>&_Vc1v2yS7=+;kO9Sm#p*6M|B+P(B~ znz7tuL)eg@K|3_4*)e7PYv>fn_KSZst1ICHbaiG4(70fMK)PKapBp$_)T7sc>;XWQ zo+EoODMosYbpqmgCkv8F`eSUeypHa4K)5Yb-n)=b3MV^FrP3hA>K&H0fYWIBnQ2fO zA0MS4dyW8KxsVxEok_x6sYlSbzCb}zmU@;~Piy9}J&O=*PrUo0rZVZmhd}1r6?PIp z{hDnPCW(w0*U7p#PjD?k?ZN2wOcJep`QuOWw}--L>tEARt~BQ+z70G|8P-Od4j39) z+aXtvkMf*kTV5KZW-d2d{PN`Z{mOIlS%@*Ox74R5zH=uJEuDja^wmhWzddw_Eo_X| z+1LT;zLg^f8!H?(Of4ys(_35rJrWVyISf@i3;y0WwH0vdry*}fd17}n0Klb^(*M2x zQ&f0jksp@>4ry(qafYqmw$1et6(PO8ak{4L7`mDJwCCk+{FRk=k4osgSx^ zk@)w^$>DMupw(NFTEgX{gNC1`X;W5Xld|6{^@fgd8h?e_<;)^W)WJk_%_`&L9Ta6* zG26g!uXHF?RbHEMG+R9)WH-K#L|c1(aHcJ%r`--|%>k9UyR!thg)ikWz5O$mFTQoC!8z*$E-aVt9W~tyiW_cw^TXAW&!0!1*gyUsR zhTDcFa#tp_wU>cv)Cyi4t}P-RLaQ>eE$hB|bpFr{bK|-6&W{yx>+2VDcW!2&)jxfcq#vt$4glr> zZKJcZ06SoJN;9{Ky`>U5+`6RB85lQpaGvoB&2z)qyR%g}Q1f|!*|EmZoYkR*Kzb&m z-kh$P&VeCA^M(v)%Yoy{q+2bIC;f3tL)oiqREIQ9P= zHv?z`pN-7~h_)Gj0d#a$!zT}P!fCo zg(!RO{K-nMGv`k7|J*g9Nue$Fl-YVvH8sbTE6a#C|2dmCZ)5Gml>ZJ+H@Ezst({I; zafi($X4(R}=NIC0<7a~D`SU#ol;-En*MO^0M(<6d7A<{UjtEGn*;}2_M4qMQJ9tO$ zOQM2f-3phSGsdrPM2#J;X8Kf(0~+gMe7cyG*Vd$FZOnv6A!N}f&@?bCnGJhKM|W=I zBxbnK2{D@Ss*PQX2K}5bAA#)5%|;7tdFoPJb-~CBN`+nP38vTR7@Hs)@#>0A6(UVj zwJ`Z%V^ai5nb9btt`^BJDMr_&br2aHe|3o14;2hH6`ViFFALwhWb0pedz6=^j~~rN z-uR&!#Srx#N;!Z19tKIGyW}-hnFS1uiE-vk&NWKW#vS}Cc0772^6de3+uhY-C;P@- zA6Y(i)CD}K7>P1ER6PL%+!|-yNmNMlMfd)8VK8ih8eS|_IFVvtg_lRTZIEAatIc17 zp@&km-^uU?{_b4_wb1OS$F5Qp3gItk`8Ket`9(Yv(~Pcf0VJiEZ=rba%%g4R(I;If zN{dntsD7SWd{nBVqRUKwcgi}DGRL+hK3qC0$~Z#TW42@=(0u^I#R&+qsq_XWGZC@0 zf8QB>VdMbwM(spvvRkg9UYh(G?Y)rngD=83ulnHw-?fu4m+7^6AZb$L;_dDKx zSH}O-oMwe_*J)7Du2;V#u>be$1@auY&hvto8BxgRRpA*)nf~`365ITNWgHUwQ0OE) zQ7JS2^{+_Wt3k*cgZJm_<4yd1dZ*Jnupi;Z*@JuF+2W65jqD5^DCwC#D&mV&_P>)`aPiu$42Bwj9kwM1T*lbbQgzg%A36} z1q5hte_YbG+87-)XyqZp#mW2b7fjC*@BP9EA`y2LJZM-ahi*5d!BAObkZm;GnVcQM zt!Ys!sR=Z4>>wZcvIX{HDNoRCW^q6DUslNMj+=hSY`p7P!wDv|0MS81O?0dkH@Y@E z@Y_~LIzL*JXtk2hfTs;(CETPPcfMbihUn}%&Urnj! zye~?l*y76a8|A^Ocs&}~SC=X#)D2T?t}o-pP}M0kH_U8mDhKRGi4SK4jNaH5*k=f#BA;xgYp*#Xo*Y?euH@YpzrHYSn!uU`zkYx==u_)n-nw#7}G2KEQs zn}ljYlJoPTbIseQ`4aSwprTmj+%(I`9}r*JHzKaR6i{)eKaWAFLL}y4t@^`FSWtmF zyvJBG(#n}T)Wo60;$%4q9!h{4gRp-6;}9(KC`mGvui~#svKoH=6ppWBQkZL5)FB9- zcx8lMic^EVG#H;qcty&dSi9V4hwrM5_QPofdSD4_pO;sBVCCY zhCebRVeQE}@a*k9N?>{$T!hH?7aC*uddgrvsB_zO8O@|Ppy-g>@^fktVEb44P}Ds6 z!AP1#)h2()(Mbwm9O15-3^YWN!8Rm#1 zs+yH-zf_*Vsmc&AOO^her$^!vG(vA(i4`?Dib$xeSvmc|WqWupqQ3$&z&7oz@zR13 z8I3!iEM+^LO*qBr8jA5!Lha;i=USipz`Pk&r#!*$#BVPO@=r7U{_nj%0A%^X>PYn?`e;Vg_n2bCC%(y zpY1bx&*i}k*@!{hrorTjWP^+mM_a6xaWrdkpQTs1X-U3B;ICEg>FT% z1~Hf1>I7WUyQ3c$`R4jutomG)r+4tR_-7?eldi8pIj4%2wIR|v0&&OfnSsOiLq6iU)!%;w ztuO4oUUtixw3k?<9Fe7wCo8(Kjk;7b(%Bhb=J@x~{aa&gOfrzb7s*T4Q|}SeNh7YB ztPwa{NPfobJVSPr`?^$0Abzm5rcri{ZsE_E8j>~*tEAJTi;@z2#8z26EE3pcR55xm znE&r|%f)6C{Gd-Q9HficjHnO=H{tI~=SgwL%%QZ&h2EjutOA2NZ!C3G-(SdfA!dox zWC7%ZRn(3j#FVS-={y$QQJhXw=(maDmJ247@ts|Xh^}FjPOlw&VEn26=bG938EqUF z$vG6``)@%6`xgk?3sqAn%GMmj?5YACj|sV<#doEP$`)E6RN70cq zy2Z@2ve)F|*1+j-kyL5krg8KXW{oas7DvA5%fBe35cWvVOfAAd2@sL4H;gSnQQ3)I z_>`YdIW+TV++-sH|3xVRfLO5Es96bdh%SIYp^DG0EnkKo(M9&p3RF zmsMf3>z~h7Wmjdf*E)y&j6+i*}dz-z|vy0uA+ z>oUgn^l=jhB|ZahoxGuw$B{P&n>Rj)lIE4QipihvQ7tY1F{l1d4&ENaV#sKKF>OutftqhwMN+#A?&b-i40 zF$}N78JnZK@1EnRdS)S->Fx9tUx?Gidus6r%cVUV^aX<#3&MaDn*d}UaEy7;Q7;~2 zaK1^m^k26dSd5&sA)4RO{f=`wn~REy3raZ(b?Xn=@q|#z7v+Y)v8U?DX`(U3%>tu|XFZ_PhX64C;lQ15+x z-O>jjd+%n_mU*LTXs+#}kFfm*Z?Gr6?^PQ2Tsuo=Nu9bupC9l|iGzKxcgL(eO^s!@PZdGjJ=w6q z|J=8;%_}aJb!l$cILLQX$AtYc&fj{}oXk;)sz)t--p<*q-3l4M{B9sjrFEY zt1q&EXIL(alNnSrV!NSNV0&l5$yq8@bHF-o3ZaY}~SEnVZ{OlX4vSjHO+@lj&SuJWw>$X4m-+?Y1bgas%p8GO(SE?;WnM3n1YBEwL=d zq&z$BTmx~HY9fYhbJDNvj9yQtAE%i=4A{==Z`LpK)w_ZlHA^F5+?hQ#Je>@3gTHnmvV7>4T25_1Oa^IlB)RGy6e-lH3mBJwvz0*&h zxo?J*PSb-TqP^1W6{|SZjG6M>DVY}dG+c#qUt)4|J2<6rWINggghQ3k<34;1YEshg zidgoQtK$yFJlZrf-~Y93Vh+i{F;oSF0|uMWea7rFSc`1 zJjlw^+_gavq%Pw43M~8SQ0p$pw1Cxjga)d#jgn$VjcuJR$x8fr$y9!}3BsZ-DQ#jX zPMf9gX2~>52WkOnYyb;DqjmE2r$N64z00Y~dS1DAXm+mBoS728gxYf#RQjN1&HHT- zSsp8sz*JcB0FvGrzh{v~>82zIh^9O{#B{5n($U$uZp7{$@QnoKF&3LFToLmf_HEss z_krhmi;l|1V8xQnR=PA2%wO66x0lsRc4IIBi>* z*Bes=4_@p1EIOh51hBi@+ z+91x=H}gv5P#M{XKgesHTIRq^v1D86apM-31ZRNfB1G%7(oOrQ@8I>4%%XY4-_4os zFS-alIT>VI?k%nW4Lz>-@AZ!kZ)_gPdO~-^n1XtL_{*)Uo8u-oLf#Zbce5LH_*Sn| z#3bB2s^Xj->DG+h7=~qY@Xf|JlFz10D$!ro9NjZ0c?+QU*Jax8O+ZM1Uuu6RT*K_d zBwZ|b(;G-PiA>KOr=emjueqxU+`OBB?j+*54JRg%ier4cF`6PNXxJOE{NrYilgJ2o z6Rdl&Rnt`(-xxSa5daB!9f+27m)gl1`()yBVQ5Z3Tclg$&D=3=GN4<^^p}3p;QSz5 zk#HhEap|Wd=?g78Ku_tH%xb(kknXjzw{N%Gr{4ebJb8ClSTEqhbudloO%C;tr3<#- z_wmw}Jk7P`JSK@pk3a();7B6Teh!e+L$NmpkI151jgE59H|bgJ$@h^)@OrWHe^2s6 zl;0xcYTV;(Jm{l9&B?nqnDErgE1qB-8fvkfci81-KX^9M0C!f6PF}lS=<&qVG8$FM z3l|nJr{e`j{o0`Q5!q#{*)v|Dz#Vy%MLY8O)0<4P^X&5{o#YGrjHV2Su6avC%_QAY zD6i_n?ab+qW3`*wnFy{#5LFJG6#6YGM%Bn$QBnKBB5lj4qNG~VkYX^bi7JPgM=lo9f3G(k;`Kf zdr99f>e7EG$sZm{(wD5Qmu&71l|#7rM)mh>dz#_qfyZ&l0YQ_j1DvPy!prX~W2PuF7;{Me4qO zTHE{D3{)tARXS^ zo}r&r9Em;lJ%qXKsZYYC&M`Gsj=k>hP`6+@Q_QGx(XQV6t7UK^7OD{lUta|$w2s+` zrDm*)&4bwA1}AXg5vG6n4e~GeP=nRe8AuBo!@Vi>+2CUeEq=16DmVH+4``8!irZ$r z_1!?x6PjVQ&_`a#t#9p=Kz8wylXf6Og&)2^C>S?wL%uH+MnXxHi4x&~r)laY{5q-b z!~(fCoSEfCa0ox898b6sbd#5Ua(4I5*iqwEH*Gsxx%8M#L1{%hQgGP|+Y{@&5f$S6 zYr(8>`zN^`QI|j=0U)o)ZZsDJ@>}Hv^S$mlEn&4ni5!)Lj4cDF~$arl=`+jAPFhmIYv_wtH(t`4jkPs zcoEVvD z+tZUpmL3$Tdw>vBP@Pl=3A&Zm@Zt%?Tf_NRoD;%Z+HH z@&cv>9ir2ki4~G0VZrZU?2uw?u=_HX$5n5oWp-Ia9J@dpABG1c(FcLVX^Sq76Pk&2 ziE9Z@Gqe#5-}_MRc2Fi4Z((aue;aX}VbLT7n#hg4CLCqk25m~0_4G-hfg4ZhW55gURa~t@oF7!kW7jFom%nYksLxI z0wcZB#0D*PgqDIXX$d1Oc`G7Cr7uJLS7sYg@+~{j=WMxdVar}=20!9;5w7Kq-;wAeT+;c zU1EZu=ZM$Ri-Vc^0wWjCIk%EjPvDkT0(&PvUsG8kQ>&W!hCoz*Ss}or#Vv_zPc5-5 zZk&}YZru;J_pI{MJ_`8Q6N$;YhLVFU3of&d3zIX-1hrX6Vc)pSjqq{#=0^9&Zbr^$ z9;Y<1De=|gPWwOLm15(?cd*GBF%ck<^QXo0(e0k(}I|*VQMENvX$8?E2 zz-;lC8Gq856jTFA)ptq6Eo#*eP;P0GgZP-MZaKZwmYe&8NjM!yH%=QyFC)rNk@IwF@(K z%sn%25m8RA-^CL3+5eG`!BaQwP&(V;vv-N&-q2CZt+NH%Z+xy<+!B?YOBR5-W5#Ni zgvIW$#;09dwwZ&{mN<1@D>#1U-u?^8)tpBC{{fHwM}__`c*Mf~|G*=z{}(*s{{ID! zX5;C&;rsjhi{>S_Rg*qa)Jgw6_Xr)e-IF0ipc&gJGR4723iu;rZY<(w_%_ow#FOr&6jsx&F}W)^nL$*zS8h!vHsludGl@O+q|=VecrwI z<+LT7{ZLpR-ar0Ww7JRM{n5|Y7UZ$(vhz1+^AEd`88#Stx+=!#Z%NZ1`gyoJyZ`wB zSd23|@`WG&UToX<`+UFrg(N|{04*xp%!Nl~Cza!WY3zf~KP|tLl^_l0e!aipvDo_c zJfC6tP?BBGtrduA4HO_-BBoqZz=gl1eeVA;|Mn4^doP@g$uIZ@eDWzN%(F?2-z-c5 zwJ^;mRuSBL!siYo2LxUuSe?6mV&sjK)hd`2;AhRy_VO&r)=%Wqvd@Cpc_eMEV}hZ= zH!S8DuYJFdGZMuh#|xSEU(GFFj3?iOKSlU|Jw1Pd>?{`y*e2o&dDH=Grs<_EC;G_eKwuvXLk7UeFNDWx2NZ@WOXc@)T^9~_>nT3A^IRJdUt2Y z^k*wXe}bh3X1AHDcr^F@(n@e6u6rr^%~Xv(pYLFxU=GPVh}OWs6Oo1y)f`lt&JuR0 zjZ$g_Jx+mznBZW!n!;Ibj0hg-ZMVWvf)%a~b({u}XG zKZEwR9A49VF6-@V(gbVAT2c}1%olmXe=~geYwrY!R1v!EORq^woF_ z`w3)nj~cprQWh?A6kXU#;hzO@bCVaCLF12#2660>QI`BIfk)nE7$qwI~ARm^6mttx)`>pcLd9%I$acnuHGFOALk<|r&;&R7tN z>T6_YSQp3#KErK`1y?~C=i6_a&^Nn{Pxn8WPO^QD(Z+DhuygH$U{FOLeO8D~Os!s#qh91;%9 z$k5ZrWQzP92^J@z^1 ziaFsAsMOR+F%r8z0<|)VmL1B8Dm*dReJ}Xy$7zliFC@uWpFIF*!BE^RCFD{Yg(n@Z z=N(aiIFN6P#O#Gre@m(U5ZP8ZkZ2N23&RvZY|uGvEA{t$A0tsOwRs@^Q5nN_PH1Hb zS%*qtpqlJ<&V7i`A3-jr(f;g<8p^H&zW~e8jt>O
f3Zvm5_t73;9BzPLmi!zHM zpRXK>WlPT3%?)&1=|tur41_cRcpoi_ugp=rck`a2#mLS~Tr)>+7&H+&$#5Vs{~`rF zPM;y@y#;glz4>#(36`qQ$OXsCb8!~X(y1w<62!}e{&U88gQUq2WoFmOyJKf)@%S>G zuC;N2wdCftm3vAK3!^c#lTdQv)iA0Uj)VrG>!}kf$IKXRxs{bN%dW%81UWS(2X>E4 z{`G4(R#FH>1{%&5MZq#e8}hrZSxSQrDJ(w|%(cE^JjV&HvhZgjq*@zQX@jHDCY+LZ z9W!?MT#kt(4L+3Lur(I8GDgKk5K=~!B%E%(&!)zTfauMw_0lcHVl}ycR3hXY+{Q}K zdIQ@@0D{Hkn<%Zg16?p5%T*SeTE1u4`eG>{dcCEOvk0bJYFIG`p%gs$g>tb~*LCwN zDL*?K^wER%G@xC*K{|+jk-U*jsVFj?kb_@%54E3mbC}hZy3)u_QtAd%@N5Gw!1s?Q z>DeqltnU`1=Vi%s8c4H_Y4D~pR%63(JClKnczQ{%c~AbsH-(>qHicn4=*Hv+(`h;! z8{ev!#(f0nIjmp$JKtq8gX#E0Da8B9?kO;(+C*O>Qi0Nb#HH9#jpDNK&AVAfs_gFG z139L+y0a*vRDXZdgvtTLB0|=TScO}$W(+)a`0z~~ZNj2K2#)e7fkQ$0XdMFy4sZwh zFh!k0ZT*Zb&2rSGNs@-tTjvRrrUIk992eZy*gM0&lr`?OXDWt16`xa2!L4R`*{+^P zHI{=!zIH|$->bQA2`8m&w$n;e-E#99O|DM67*1X~)(!|DTp^UFv61xyZTD+;AjOj+ z>ev{0DlRpr`aC(;G^HXmM2wQBv|F+BceGw~dT<{5&9}sKwTY(*G$m9Zb!Tz+O=SIo zJh8dj$-VW^e)+I)l~T|(i#bp%`I-U*hbB9Bu`gx@0 zQ7@NOj0#2Ffh;))4UCg(>y)(0_ zk_9(=v_j@rR?s5N+KGS$@cg9q5T?;SQ`NZ1+i?ASm?09e9{9B|z0L4p8qyZf1`L@; z`#~DoMyxh4N3EVL;0)8?_iuL^HvF!z-2HDZGuM&OVDOZR*oD>*TMYl{hpTfduu}$} zS{IrSLDbTl^lmXnW8O?7Y;4(^04YhPr!EeNx&w@d5kt!ILARh<)QpqT5FJt$>w~ zi=^64BgSqDof6p|#>11a9yM^JEfYX=Txp+Bn<_~Bq&l-TR~m%jXhqK+qqR>(|7~di zb`G=&3AjM68jclqR1H>DvdeB7_9`W{Sm$#W_PomBKUqC$C5?-EMh7|#ySPy}$Ln`4 z33^8=B|Gft3zfZ6KX^!Sf}41;sJ3mwWvO>KyEe(clW6W3agM7o1aXa0_urhv0_q4|P-yE#?Xlq&@7iF>=cIc(t8}QwoFon7d;A@*Ol438yh>FnHuqWBQ z1oyFOy0PkTU0$ATbSE+fYnftG<9fSwf@+~bsqNYq9ZK zVM0~x=xJ;M{vP-je*x<3(#8*rp2vH(BT)f2Z3)K?N9HafyYU<2JzLsKs>x#^_Cr4B z(l3f995+q>4WX)Zd=)%piPzw{@9*`V>^E#W?EgX7J2qzmb?dsZZQHhOt7EHUn@?=p zwmY_M+fF*RlilyCefBw3Yn|Gk<}a8vuX&F#u0h!i1-?oeKXgKISar-;u)1|MuE4Xw z8bWPU(APs z!EM&j4a&Y z*O^Fpgsx79KnIXBhTE!aDFi%2sVNDOx^llyr*pl#&94kq*}R1swjQ{0V|E(#tBj=x zG)~()zDijGucf>2ZEFx_l+HrPS{=mVyE4Dq`_}jqx%vMpjpC9y-xRd!wMdaNC3$6I zlu`Zq(OyH*hsHsmli!p{pOtd9aSM27FUqz2}H>;zt`$x<S7?HAv^1@$c85oX%8qThkeeL-vTm zHQ_THEbP3ll5JASFbk5EK~>o)du_(*;v;ApLOg*^}MKulX5Xal{XC9sD={(d65!xnb0dQB}mXXW0b8c95 z4u{jm?o_V46AdLdbtygg)c(*zs)igD?|Y7_+l`RtIckBqm#8*imjo8`3M=et1I(yB zFM}!NisuSaqWJgS5Pyr{RRe34lY51dWNm$_o@Flt4d%3)EE$geV4=YbjaAzaWrW70 z|B-PvSRtK(7u-hZMi=WU>NQluzK_~|Z2sm&roa(!8hK{qwy)Maz<#)TK3hQcyk;%4 zZeiM7=Zy40&7<@VW+R=y!Q|p9W&JC&lOaiIG^*C@xEMDbr$sImP2L8&Xa8F*HW^hE zkKsUViWT9suJ#1yrY1>v1oJK!hI3b`0^ZynhY_;g_YUJbD*lCw{*yt&h3)$!%XON4 zlk@ND9dUtN`Q?>y6Q^dazF+BL7O<&_$J$fd&|($F!D6fKMT)@?aE%vH+GA$GPUuUK z+n59Y{UhpNA!uzhUz5%|iD>SzQ5*L+d>6adF1)=3B9%__&MXaIGHRV-N1cyVioYmF-Jk)v`?iQm<1waffM@d~Re3^`z(A`St~$ zgIK{Xr8*=P|H!OzAlH48?PZI`uTpn%KBg8RWtPe9*b}SL0wNg~0wJ@yUGZd9uOCJ+ zYTmsx%I1SRce0B(ne2>Ng&;%RKLtIbQ;6M}{9uVkfH1<}CprSQ05EdZtZvKCEaPew z1qPEQ#95}efO5Lygr6=k<>;e0ykA`D7|&@feYQRY^t51O+8EvBviG`sQw++UXL{F4 zKu7XTMMWt*!U>manohA`9QKVtID!piG~XvkC4(aHW3``0xn!1K<&|9nzsOc;6YM$g zps0A43CLx!lu^{z?x=|{!!2Y7i`L{3yAuiUfhkd%^7Jm*0H0gKcB?mP;z#!%_6gm0 z1uyd#kYXX$r%?-CRYcw4XH=*3>o)KF_#tl7qv2w|Of&#;F(6c>+<&5yxJlWiUt)O2 z!2<0$f!yedH(wm@N5jlKHxTSj)00*#%SV-{ACHuN*FGW8EAUo)L7+~(Os~NqPER-K z**G9&;d*QSDRANBxkxOCQBgi{Kqt`IAhS%;yYAmQT3BXwm~0j|(@LOwB3!U!sJacSXb%K-j|Zq<9(byf8-?6h3O>Uc|0KIx5t(^sNN45 zY(6XF-}41TFSe{_XNpbpS4MyT(xXwqBus(q4WDJWYv25x_@X0lB=_X15X{ z!+7goW<(5mzcoPpR8H4f4OjNH5C(Cc6xlJ)+4SW?yK6JUYOF-2EG2I0a6OCbkcQZ* zG62gcM+Di6oR_?(W7)mrT*qNG}Jh!n-sHfVE6 zWgqwDO`s*Da@nMXpi~>_N-RLUF2obU$l_jDCY~6YGJx1agj|4u^B0P#Yo8wwd5y28 zXu6{B4tpFW0$+`*BwZya{e-;51h29~xgO4zPRjs&Sda%h2+DL&h?MU{xYELAX5%FO)V0#WAw*qr`v?xtlO*|?)N_13&iQX6+y`M@b4c7Af5gTq6~NEO8HbAb1IGj2x#q2cxC zfp@wOC-35H(Rt7J;W?w<*>{j)aIeA7n~SgCy@{av1Jje4e#c9%yPr>x-Sv*&_j#13 zZzv z8J5>vnsg)1y`>6dq3abbfb65~K=ZQ=1&jhO&Hzp$urIm}CPOZ9!ljwa@8j6=Oz%a9 z{64S852xcM6z~^te!~2j1o(D;IgPoK!_s$YMoPv6ah1?#!O%jKmm8CaX$WZCgxN_e z#DxRFAO+4g$N}HMj10`u{He*uI%tb>bAw(QZ{hTz?)xT($>_q zA3O#38lJp>{_-#OhZfEofu0yyzBs)zqDN;;yVaC+4PI^1B}vV;WzL%>hnWM63vd%~ zO};ir^%I>=;!-mwlBFYpovN@a2TQ$oqXi`SfkB-FzED)NMj{wpi8$R#{(&grFs`MW zKu)8;%_qKZ{iHMT_@(|97%JAIYpnXPJ7y|()vmDbD8Y(`i0#tOO~o87a+1;}jhLE2 z0yad#)s)nmNQMieK8ExQD4>WXEw}ll@dTZavVl%vBe@cnlzi$>bH4Wv&Mg?nCp0;y zoU_pSgcs_;P>pCH8 zaNM7GbkutLhTx(zh1!8UvF5XgB;jeJ=J>FAyD22O)qfhGQgtpmB)%_avD1%UHjRIp z6-Appt#W`wvlS||)JG>X*Ylxv`m703Ve8^+ZEuWfsIJ}tXKWhO4(JmXWA_(XIlGmA zW-T|jbca6rW%d@s#Z5Vu{4*~M8J6*Jab@W$`&dZT0R$LFd9>um0)USaT5hPB_e=bi z@)UAnQygk%4vDxkA{a?p!bUT^ckzxDSa*ScZ`=W48~dciT* z*Omt#d<263BQSB*J}A9p65=InTvod#MwpXmV1i$jKEH)snOX~S(%+%%J4cn_&j#(+O^WAv-&{~dGB?+Z&P_fn!Bw^9 zN#4px6UIl3lroESjU5U^Rn#`N@8_va7A-^$>%hWYM|q}=?rY@W{gVA;NVM3-?e_zn z!$}*p^{Ts?SB$@*$2DT>E9TV5-TZ_4@V(d3o(Ef&!={_kvAocv7A}sZN&e#~b7W1w z(7(!QL$=ghIOs#bv>IJ-7!JUP=YE@z@Lv|KKA1uCYBVLawx)ba-6V%q9sMf9vorVq zEgF?Pa241jpbjRDVV^5|C7BJYaCvmmr84o^Q6HYgTua4}op?7+JI#0`*o;}84d}Y# zRG_D)0n0e|OLq7hLZ}EO(*y@Y|CxubR3czDQrRe{5U(Zl?2bEh4AkeSHtwpXz0;=+bVAbSgOp>hRqQA)3AR(&hie? z5D3U7t2p7j zG+qWGFT%6D+pAK?2g0vtq^0xKTT?;{r>d-QU*ruz*^*$S+EFXy3B0#1t@+Sd4VeBc z@(7m)#Xt?pa8)ZHYFO8Li?UOrA<%7fFneaAki&(T(9T-aK&!iBMEv7cMMpWv*Y&fb zdv~PMnOoZg9qt%f$`4R1s;lbCoU9RW5_NiVXVEXiBkDfHVzAGNwI3#u5Qvkd^A}@e>!-V zcrZJ&+PwsxBk-`yx_6nQF-FgDI#Uejm(Et3N% zf*NyFC3#6wXsVbeJpDSF<#GnzqsUKpHS+1o^VrRyxTZ;br!RcLKX}ox6Qh(dZkD@oTx9&y_IigB>?lk^USX9wN+o&IpeR zM9E5Lc-!nM819)E>ROp0uDSN{mK3eYxTA6OHb!%T&fJC|rvq}*R0T;KWLOs>DpI%K z;}2cjp@IpVwtR8FN?3j94qv$Y!ti$H988o15?|m0XpMnO*0xTQg@ZA7OE$9y)quwC zj9Cj>-kZ?thd|>LWm*I%l1olYq!_%a+7GqtAH+bxmK%eQx=p0?R0a$#Xl8)3ZPvV| z;5Vu0v>AGvyplybb-EeDSX&5Re2N#sxD6uHT=5=z>SwMARFy#KoTG5kW9{*d4qnXc zj=VO(u7p1kWo5wz`La7cG7Mz$;8v8{n9l}4eKQp&h z8fJ1bV}1ddZSJ&0ptH(%`&QGPb9!zxaCMABOtX;f2nB`7fREgepu7r|oU{M=?hgk$ zbrJh6ZgP8lRIJl?w$CU3WMNP1Q1sxH>-Lu8(gKzDqiic4T)VO_P0q4nYT4`kMU%|1 z%n+pj139QFw($u=tWj}ajTfQ`(+{$m)X>_ruaA)QI5$%-B=d)QH9e7_60xU;1h(!3 zJ{}dPS^1trO})MjosBtFe^~Uno#6#=34omcU6b@bAnbpk>3F9bkz|D(tj~56TbBW2%@MxWBeu=q7#;y=`x``C6y>1(jlM)`ZC?(5Iz z>;2XFos*aM-rl$xB1h{LTeole)#ECDbuxb(d*ZU&8B~}8?$g)1QLf+~3TF+H#@KEj zlNB#ok5wz69P+z+r^(m%weDi{p#>^DQWjPQ1Xv-@6>!m{-+}*l-`NCy#HnzoRl>W& zUy(HmqNFdlbuaOxXeHFZq3xyV0$r$?_p%zJiI3^2jLpcnCO9nlU3}%!e5J)X@NG*= zx3C&G-FUIgN0uB{S&Ub!;Su(ne13%?v@Cj2h*HBwVm`qF0P%KvPPUB`687H-_BqNP z3zOw*CE)JHw`euEYFXB9fqLduw62#@Y$8N!$Rj1!=lcfmi`OR0-yqI@WYcumdFLu0 zHzV9We448UczKX8L<3@Ej1HtPNIU?-OLkJ{dzk&sd*D)yjtQO=-(MjwQYj+hI*7v4 z+Be2BMMAc!Y2_1&ez|=Ts3{<_fW^Al{n;4=FJA<|&v{>idaP5h?h8`L+-d(P;V5Xl zfjUr{4ga=+`$tY~v7MQsm_4y5QgO;#T8QL7hTugnFIa8}$dl-SM{$KIM}%^tnN&89Q@HA-gprhjN@kBRPV~M34VrCdbFa+`b*eCnvb;rKEHfU7-Ap4=YAW=}YSY(LQ5#x7tSZB z%r(ZfzP6ABPn|_c1#;hKXmw@p6w}}^|G*_mmA^M7#?S0dev-@*pW4beC1+3P-sE5< z{uz*X$10`RJtkQ=YB?Z3BJ7d??oOFul&iw0eXI(v#0 z?qhLG@LtKJsXhmjOm~!+Y?&oS?PErN$`#{6(vaJBpgv!eaW$4viZ|PeLvuT!ZRVNL z7vpmh1ihAhf|0o{^#P5fL%7O=LjbhahW)h-d7%hC5QW-d`!`W-GFn0}m&Phpb~%&$ z*JVkUU~4jqX0cI0G}gtHPcK?NM5_4qtp*$sH0x4EM*#rg&H2`DFK4WSebIhss}%z- zQs)<%`C}6I4oL?+Su2KhkqMF-+yl9|k%@7n@Na!&!!z#WmCYg&O^YDiPPFTU>laM@ z1Sq9a^H8!5jIeZ_D@HpJqGoJCRIt7;iN@|#MT6^D*k-O4bTm`!-8oK61ijA%e2E7n9lwoXa{o(_fNV=BQR}WGcp1L=AG2E`ga+N zH;&1Bgv7ZW8{Dd9JaOoi;OFcJI4()Pm1}%^Ym_Gfa2|`OGDK*gT8aJJj8=0pwyra5 zljU}S7E>A737??s@7%X&CJEeXI0oFvPAb+4xlrO)Nh2bACSyZ$5uFW;^{OU2_cbnlEh$vL(SaXVw1RST@+nwFe7BbJssFp=#ui!g`VG{a2^Y7s9~uQ}_1=)5U0EuJ~=hriMj6)TOn^NPdR&{E%m?fMYPlHz@u z*4i2PSVl+mA7JXWr0~Esk>NOI%jP!$?h$>-owDhNW_qCG{8t|?v`-K3K3&uGxG6}W`LC$*c}gDHhromAXkueIrr8_ zuFZtN|9#y{4ak5hFj<$)){4rCs#wV`9^Wel-IoQS*T z!CQv;tp2emKo*}+QuM7tKXnW~`7Im3z=SJ-~k1C0SLe>TeB8 z$JY?}zM0iYEi7pfj$?_dFfL^s&Q8n4v^2NsE{T#7b-NE#PI9QnM!pQbZ|2^~7y`|C z##s!|igxt&b!b9;r-ZI)rDfrTuaT_GqK05@oq+3=s%*vG;#WB)T@0GfE5)oH%zO`^ z7z@*PH74SWjP=sYUwxQB5K|{C8$O-U)Ft#n4=*>*dBpul5_9>DSytPkjl+3S_?Kbw zR8sPY4CBp}w)V(=tRk_f-KJ86&!{f^v<{`&L!x<_j)t1~uh-Iohjy^5PH_cB<)Z@u z&6x3&I#++bosrbaXKyb^Y5}qlYSrRr4n~5qYz)?vvdKae`;fweq-+lGm_FJG_ejHu zKH<0{oQCss1X=q8$?6(wISie{{)Tyk1&LVotf+ZKqD*je{Th4W&Zzb z2L0b!duAeLPEKx)|F6V;*~ilmP5j#)-&f9kc78i4WBe#{oOz!j9!bQID2NPr09`l` z_z*|LUx}&7K}r+~Ujphvjb8rS zV1_Rh;o4$QLv)U+D1G2o`FQwqNmQjyw*O~M>9c{b92E94S1A@# zEQ*X)J!`wbs)Kdr_<6`16(uS0m(TZ7(_^&IiGM&41R^$%jmJuO!a8@6ljLd4I3X_s z7eGYV;^21@OjIPLVum)0?R#`aqYPsn|7m3V?}u8tyxzS^n8%;t*@JE-G-9#$BCt-p~8WCBhj+yo`!NJX7*+utY6SZ5+ZT84k9EX721^;{-_d1 zQl{h?`0LX}uvA0M%-$-<2Rld9PWd?n924u8h2ne2v!rkw6h^{@k<+rMwn54LD{!Nl zQdBA@MJy~D=~Z;1QPRyyHPzzu#mW}yE1DYXS@=5h6iz{Zl-G^7&paYF z&Ar#ZvGEP}=?c~Aq4`{ij{eYe36Vubt6@*#{ImJ|y@Qc|IkNV;H0a@^rR@PhZ^CRE z)Wh)RbP_|Db{qj%@_YhrN0NFAKlJ?~_yDt#qj{8!w~qsknQLG4Y4;|Y@?WsmuI3kA;Grvpz!(=L#m$*4tiZl22(QguPhrk2$uyR=zPNGNT?2}T_)VEc z7E&zMwz!N)t~mtiN3F}nTCxHd6;{*nqc&vmvu5|VVztosCDVto+$Fk>-kv7o#77!1 zgnv|rZOqK5E{0!Q58_7hVov`o!(&vP!!#4KEUTbs*kus5(#5t~xH@tntfzx_cKbGn z1y1>p&Y^~BcESoFnX%`)Z zK-Iv}WF~kVVLj=v#+`cFcv9J?0q&}@FP&@nIZdY_w)O`FyLDPy_m7j3&w$&9av{XI6L4HNswYSd5k&xBP?B_LJiSL1NrzpbCdVtdk``l(+V2io1jxH5t zvc)2OBC4rtRmNYcCyA6_5==m=uO9As`oQHIMJKkA=jKQ$8`hI@LUt>SoiU9gA3(Ct z=DEJk53o01`!Sm@#gP4a{Ys;vlKlEE?=`WC6wG=%Fi&YhUzzKhqSy0(YBwo1!-wG; zxP(&uZJTPwI96LIYUNQ}%HXxw%izf(pIsbPNu2kdqT4@Ht3BdtNNBdGgp~E1Oa4}@ zdvc{bwe+QQ{WRT`+#xG`9Zl6sCF0fr&Yq-5>H(`xFYzLmqbpDhq53~feQmxxJ88kJ zdB%qa*^YsthG|+BRu)1V4mR+nV2{z!9!K+sWhVGU^q`}ZC@f&DkpDF^oZ5x(2*c3rpi5`+a1eG; zvY!X~fV~G95wTtenuwkoSMZn><`}(olE$=?3LrtK2((%7wZUrc@{Qa)bCVcxQ+XWp zB^Lf5|E>7h!ZEia>^goL%d_OjFS9jUEQDA86*tut#$H-9_%~tIE=%j<8``__cq$Ow zoUX#nB)~C{ouUmKhn3mISo3bh@eAj{$%B!t)U?YHXTyn|NWBQ#hz>zMTQ-ZjUO9tC zQyJ-`-cUH4lEoF35uU1j!pbXZ*|?F0rJ&2gF`OGi@)_TP*9&1TTGXz2wziKl3khK9 zf&|V6*Q?!;8oRI2*#S$5bjkC>#4NCGluf~RB_O#iDA9(!4SD7ddlQ%=T0Q7`OQ)SU zU#V0-gqTQ?Fn$lBD^V%Ux-LZ)acVk45?(k}k*t*PW-?y*5J(rEZWs`x2u;ScFBVH; zB@Pp1mM(SJ$a5&nr;0=e#bS_z9t|e09}|ALJMZRZNWlS>qwuSOHAVX_4*zv@w^c%4 z`vXPb9W(bEs~DHr2oWX0lh6dYD9bUKd(8yXY+*3^XF_ zNU`6Ym*`D&lx`$p_(*&`vqgcdz(8>v^N&>X_4uZ%J}W&$wQU#>Ua=6bp#P4*om=BY znEvbM1M;%d?uK(=pId8_H&|IhujABJZBLx^yOmOYRubL}HmF%TfM@aP$vA zW6(@=S%kO=>m&nq%DeUWcL*9wi>_|tN=$Nwcp$YCiuUoKGxPbEg}dw}0c7k3;%@hB z4JmAr1Tj;Tt>QRB3#dev@KTlecLiknt!O$(Cqj8Bb9@0b;b}`@nq=lzzlyQPo89#z zPjDF*uU@|Q`*4p)?L=Pe z?p9+o~pi^GH zr)mzK&V-Ok(ng|&lGm@yfs%o=DJZLq#YX-~Q6RBEp$JL;rRZ8=zQh{NZ3o9BxFnn^cNRa`?d&~Dp*FD-%31VBR^D!5UHo*shq9W$O7zY%nYLmB|a- zNx9zI_i#ICxTKY?$4WzFWSQ2D91d%XD|k5CeAaGr{tMeRHLNFAj>KS9vD4GB7)qOY z)#3zTscrMyq6^GK9j!XiU(CVUEvi~+o@IkajiDiR(z#~x_4r=9eZ501mA--OR$Ulb z(tk6(khorx{gBnIGCW3GaSo4P`D{Os*-yiNJ%1XwG6A4t`E|fd8p9msh_3(Xb96Wd z8;3o;PhFMj^n4w6_6OFp)c_Vn0f;|LSOmBRN}jq{V@|v&w?!F%ry+;oP*a|=8OZ_j z?+p^eFEkFO_L1PSDF8wFJI#i|MNs7vUUy1u-*3!VH(hzg#xLv*tn0N8&iss)l0;-O z(AfsT$!~2s=-}bc(Bt604xf*W3y$^%G;=4HkItHqWi5Ml7!(~%p8hC2I7*a?Ymsf( zf><1|3FkppkU)&NmjF%*AqgZAY=rDI`4tHyW**Ff!~Qs$|L{07Mx}!88NaXS$aN3x zQ2>oO>tJL!5Uq?E8rp^jUF&c1r)r~qYWY(0u%XR`hQ|dO7H6T}Zh56>vnZO3XNW@5 z_jNw9mO%gNvS8`lats@iO=T7zT+UyvZx9YNHV$s^^=vE`pI6_$vAK`%4gXy2@VhYmq zC=Qv0*vWtS4v$D1MYAHZG#Fw_#4#BZWzSzVgh8FUFJP8=@~%3F$MgvlIV$Z|hzNRB zg7&H?KvNbH1d)x2a>9g-p~B?BAbJp=wa$$1b^v(q^64mQth(iRbX+*TAa0W)OjU`I z3omJ*(hwJ<{Nj(ar8g8kH9L(Iyr2DR-l&%*olg}r#^%^|A2R!p9_c^550w;)2ZI`e zaQ4cm@zXaQ$7`Kd^|QTYHPeuTzKp5x2*1C$jYK%}dg2@sWsVuCo%2day{736alNh} zOcl%ORkv6w0gkmo2or5=pjq^=mm_1;_Tr?m3Eqmu$u9TSq!Dqx2a$v^bKuz?RnG&foQ>kiPsvTYFZUIgFt zK$5@(X8(H~Oic8FIqEje-IC=$u1Z3ZA&1?E#zk^a3&!IC0TWM54C4D51&?Cbloz{! z&laCahJPA*wTTyU4>KTU9UEj6&jlZu>-HD;Gzk`1^aUTg$09<@s*)Ae5qW4xnM@A3 zrpFuofY7{0g?Xxg{(W!b%dDUJhp(R9$o7EZ?If5!0zs=m^DS6RQ3mFw-YHhKvMkcE z1N22eGGqn164Lt>nmUuRTk)XCCiYJWe-Gv7_|G~SYE%FXlaeC`_a13BZLF*!?2*%a zI2SD9=*bZ3*CwGG&Mtk2<+jx&v%r^E*qtKXWry`kVwnA9+YjTYn`0io?{L(w$;MCw zZI9~^lcZfM%W67mTu$S^ptha*lJkz^;BuePp*|Q0RFPoU=n;`*6?>V6J_2FSgXIU_ zfpb(St%LEA61-OweaA=7Lb{dKm<*h``BgEL4xZ_`aABRGW}guZD^8MYs;o{ua9Fd- z1ddip@FeU|hdbbe&XNQBOwrAaM2ix?C@4GV(DvHrpGmyiwToIRb=2mq0*eV;Wivs; zAq`EpN&wUgvy4wFFbpYo(7hvPLt3A=l)YU4>M1VU^%%R3H_lgl_#VTYHvl`2ac#Wa z2CO4JxMv5@wIJ9S=n^uOIw_kDahJbfg>@vZwJ`ghE+WHU_7tiP!-}P<@w5o_uQ#DV zvpBu1EqfGvj}@Shd7hhX;fphNp00bQx?y2^bX{JT_83?>emvIMnSoMES)g95yKHo5 zm?Et8A$jA#RbZntMl-e%+|N|AA#01(f&l?+9xv%(oC~FXIDhdr2g%)o7tkncZl9d#-Y)s|3*su^sQr-mELo98X zHnIeA485z0@ML1(xK%|G7tgtnj2YVMGxQ6D~>%N8u#os!e- z1kX~v7}12zJXu#lA#eKQ{aDC{^lbav6WQvV>hXCwqbt0=i@o^nA>ObG_|{%y?k{2q z-M}th$Do!9qA1IZ5uX*N{Pp1R1J9HNCQ}3_MP6ErDixKPF1a4-eq}FG!nz-<{li2C z=eS}$0?lBUntTk{}DGr_Nn1p>; z7MktB)8KUm)Df)W!hJk`Y-lwaz?MZ|as-8OKQHLY=$pMW8u@C3>C=q(=v6X)y^VCG z5qv)y0Y1Jsq&4mwLQA(iU>pTLP|54F={s~f=!O}c>9HNFjcUJQuTY#_DyvQ6&(`KodX+7s(_}l81Cjb`sBXVdY6Abww4daXKe-RYN%Pgv_AA0U}o{!lC!2fa)|xHmim-AMKT~mXp_~KAQ#Ec^ls_{}Qw2KDLb;mMbbEh#5Awp1n&)Pw!&FV^w`@3# z7+wx|j@hZ2i<$6PnVWwa@0O+;L_S;<5bn=PUo=tYBCBensHCD=x;-Zkl%V&2Z8!%V&TxT7^MW8LlGW zbuI5!^XF6|#&Lklo{u%GtJ!+4VwKe2e$F0n*7{<2sWX>SuqRR*u-T_P6@eDY9AHQu z6k8bL!lBp4SUmaW)e&o7)OrUq$CnEOrpoBg*;F1qix>9XzzxKTV!B5dEgxB8rF>F{ zJbw#_%)0Zf!|6L3dr3HzvJ{K`?53;)=u-uc{Wi1U(g}IWV$Jlyn`hSsQjUi22Xas4 zS&h&Un~7jEB-F(qrM(6`ME4J#&?$CGs~56rn?GgziR-eG_M z9i`8pzttU`yjN|<*!5T32WIZABB`i`Pys8A@7K;eKYuX;MXHp;nCIdac69YT9c|&A zlmOM&uXM({EFFm*l&PzO=Q0W!$PJ>ar!g$S{x#h1~`f>+;0TrbV8y0V>%r;fi&& zL#z6wDu;0@wEqd>&VO#F4{$1k*8@2hblzePFf4=aGqCy^NMyxO`WdAvL$u3fpx^+? z5W7YRXkuWwD6pyA2}x)Zv?!Wc`P!eU$nonEYixwV>PmE^9#{NAqbE-r>+_>`9d!Nq z5A=s_pOZH+?$L-+{vI(rKITW0V}y62669z72wonr z5@G(SVUZhD2=G8=8%f|dq;*(>H#6|dZ$ zOw5#O^p;Ny6yrosa>+Vd5tsX{4DDLGSX!BEog|!4jeU8_D>Saclazmmem_kh1+j}u zXC{JBwwa-c-2&4tGi}|nMhP3f`rgOLJozK(a)p*Xeoq?>@%5wG59A97;OP% z!)7^}rr&_{0?8RN%${ZRQD}1uCy0%Jd4C2;soUEkPt-lD(H;$+jJ!34KXR8D5*LsSPX%dcdqMX5=4Rf_s% z>Tz-|A>o*Z;&pplGHlC$ItoU8Nl#-+V7dYBz};~444BMKv!V9zJ&YG?)44C^z&B)sQAI1nQwzZY8H2)5*|P}B;*}yJMe)ik2;`O7TkB>K z@vqs6a%V~MfFb`zA0TFJmjOkdz*t&kp2?Vhpm4QFS&fck3BG?-3|B?nFy+?RL-)RX zJZNqisHuDWMFX&%hjL=Z=qz8nq&>iO_3zj)h2hvS~&^*s#PBi}>&^C%`5l8*Xj4!sdLsL?0&QkVq zktXjwNJQW1fv1~i-=6m@`mk3BKO`PGU09sy{?&P2->Tn5@e{gosdZs><9k0(i2yM6 z2^+=odz;idxIP%=+fMq-x%szk-V3nD_2ey(8 z6;ysE7lGZk-!ohU&~bKhD)ODL;|>IcHLkoEXZNGs^|qe8f_xEp*?9|{*6_&?r*ZRr zl7E}5tM2eUzs?~1DSdOlFwZ$#1HY$bZc>?}EtsChGfTf3X2>K0KQjdUK~uVSWWb+{ zOL0OE-6U5@U`d-fJ(YDv58b8(>P!Q6;|$8W>A%|a2;KORoRaw07@TLw;m7 zh0~|yToTbgip-P!IuKp6=X4u>*iX7K=da{bh-HpTVz$P$3CE_FO{{5qz@}C5EI=|< zE&_qu4vaaDTxnSOrThFqrEL6^uxeW`ZX#9BvH264vXDC)`3l+s zR$!uuE+Ca)(*Z5hSQVnoDH1isKX}@?7~7O1(RYdR{!z5Gy*+{W>%Yp(;^?UNCG5(} zEjqs|BjMG^NgHKl_OPSQcYwX=0>|`(i$tNr8*deadr+wMagxxq>AF-@!%M>*T@1t2En^OMqIBI!W{^{KNzBX(E zoTRLCK)CwRg_X2h z$~2tCj&oFYdSp$~q(MD^8!xi=7m%)BomaKyToD<^KtN7WeE0uIBq)H}a8Me5MwgYA z8GXzQTNALEK{$=cCfNV+m&7vgU9(yDT(`d&S>$rs!!DYB-CuN%@gtJ+8G&vXjs7|i zmFd#pKJnJ^$?{>6S?0O%V!V3?>$`0N=pa0c@?U*1`Si9QLPdv*x%by& zASXF20#=64XIHztUPBSxex_gVy6qVch%i<^&5l=WYpkz7(SH_ZutxxgM;9Zzh(1=I z$gTU@x?wNh9$&QkVY@rNr>r;3vP_xnKpLTV{)cY`(PH)mwj3@2wNeOC=6s6%gB43B z^iI>R$Z4h8f5;1V-DY#4@U73a4P0`QR$JGTU|k+BpV52**4z~B2I4$T^>1=#FQV;@ zaRolo>jN7^84~`o5c3_tB2mgjBHXU~0pTG?AV7XZ*O^;VcgRVrL^Hq6arl(KG)!X+ zj%bYzvp&wR`6vgr&mtPhr@CnExxkZ3D{Il_%w6ft4}W7_jG%kA=bpJBSB2cgJvPNo z+A(xLX&1%o3i=oi&P!ZDzx?TZPB0%#m}=F}Yaq~kH8JJp+&VgBIa>=!R8q5OGSpo*ZY< zqu4}_0VNP{Pd-CFw@5%3b4G+Zx(lR@JNXk!Y`=GTH=_Thxat1C$b0j6sNe2?JPDOldlp>sur zdQI{P^A2G3Q9^c0tW$v%o%!Y=2G=cUy=)$qH@%f&d+l}#t6ulD<`|Ro?sjyLZiJTX zUCU#~uU&*yubR`J{ro}TLsHz!fmVBQro;M5Cok=aydHM_JJs7G0NWnlpvu z%iPz>_j+F(WLq06=iXzzGwx9SuJ`3vVtdF>M2DOXH&MJ*)~K3r-pe5`?ewdTejDo_ zHZN?awU#YTkcQj7Ry%}^q#7v>8-CH4zaJactq^x_Tv`2$Yhi%ixw6MsYS(6Y=06>G zYc`3|3gljyDcqZ2%Rbx{e1ra`leV*=!4%8NrS=srcMS6L06i)gbp?YpSPZ zb89X2an_lcy8WrK1FHi4mp_*Z3u-No-OwyuonhlLTzoy5AAr;p_Wb#ZFGNqhAZsP6 z9okWFt#sJ8l-8h$60@hoolL8m)STlUq8;7g7Ms*1@IiT4|I3HZ;k->}Sh6#!9%k_8 zyLtKyo{`3o$9W#vl^DlQlHL|?RWeb(vJ&aPe4zjPz@&Zd_r8J~t;TwmeI?UTUOKu{ zo^NxV&nDbN7}VyYgsWp~W+l5`zKf~I_8OX$Ixt!Kb9A2eY}|7NeRev`&ZOQW_u2+~ zKK1ZkJxdz@RGbHWaXQWD!0I5+#Yb}s?w1rL^)95XC|RD6ZN8&f(%s`HqMZ?zy60s3 z7ybKLEwt6b2k&Ed*X$fCP53s!Z=RH)u6(`RX?RqwnW8tQvoqT6>&QnEv^dslr=O&* zqL)|LadwZH!KvHX%wBmbC^x%q+u~mLXTFSBL7!O_(+*8k@p{`0m)qHj$HP(2y_ur= zR%fMB?4J~VsSfDynXa(9pVytY-9O#r?iCrCkj>b1J%0G@ zwHNy8EdxdQq1m((asdHR+FcC(3bEMfV>|79$e_c0$t@13nUN526Ps?YPmqj;SA|Pru}v_F60_ zvpc%{G4;Zw9k8+YR?-Q5H@FI!l+&u4IixiL1$orQ%^#_!dB9!bU3e2uUlmj2rzfe_ z+)=8Y6I*{gnUo{;&Se`iK}dj1tUnzIdr`scSZdL?T9giQKJ|NHkzoSAz>MfjW6tNQ z>f3sSO1tO64`}7G@!DVa5+irCaHmKOx}tr2WZtRkbn*!M9_Oc5?KExoaMY{r@*C%= zjku7`^kG6ldtSj|;qn@n@GMpQh0v@9)>mq!lBHsOJX6ua5o{j2*$eJBQO7KQ>{7Yk zlYrrQOhzR&-Skdzt?_D$Jj0HjPI5D-z|N8)!KaNRucNyT$V8i;AZZ`JN_`x@7&;#! z2yN&0`J`!GSyueBGd!nseL&x~a!mHAL4oT;*8Ph&-KzF7+jzCO_PVsiNTphaW>W}# zT>J!^*BP(-STrUpT-EQD5{1sw6lqZ>xzQP$>7wa($c5|K#7*(9yIwmmR)0qZuUoJ5 z1wbFpvvui9kRIe*eOwfNU_zG@sTp)o(N43ocQwe6-?yK&+GK6EL%~+wslVTePSa89 zVM|wk!9dr^my{`zR%OBq6(eoTjZEb>>P6%sqTgCGznjr`?zz)6qKxG{7jWlc=A+`0 z5f1E5?H{lgBzGuzY2>ed^WY`<{1EEdykbsuj(oJXi}KvLpkrT5xlld+hGJ}%%!4J& z_kG>{qM?xVxkFM|E=dOLwcJW23P;$07YJ46=9N65Scz53#z>pIB#=Ju9^n z#Bk<3c`=dW(zRv>$z^`#^R*6pet1EpNn=Xmf&Y#%pBIR8tx{u|vtra0cDD|H4*P6g z+k42Z3gg)1&^zkcW9!`FV(+xxfq4D=d_s+8jn5aRu@WH>*%C~BBRQHrZ6$=&mG)G?)}& z6HVslTIHl>!)=B=KFTdO&ipj@q)iSTD&Vrc)j%gN^~O6OWWfF+uC-i}U<`~$O^ zPxS_YQqXG!>UUG>0^b)LTQhouBv)TSR@&Qe${2a;H~Pc8;`~t zoMvyS_A3=UewAVM_yGrXDN{q~X!=9*6rc9Cdl@OKr*z38JF>DeYz=nxOh%U4VQe#f zjG9<{W&{1@m`l1J`K_ON5_?&>sevtvB98u2#=Q#@myhPOc)g*wxMXCs|9zWUNn+{K zN6#LSU(#1AxP-CQA4r4G3$3o94f)f9TNIGt|# zH_hjEQSMshdZMjG3a64nkoYmYrBu6hi8YTp&x9dE^37Y>84LcUz9tcQ2mM>e%3qOi zCsMurI%+@4;4q$){np~`sXE;dodNy*I=)e&cEUY-YNdB1dPk6^ziC9Zn+s-s5;}Z` zh>_x8_oTl$M_+>@$Zxo-pZ!3Lnw^a9<)|$ zyCstG;-||`IDYsvjIPV{Ii|jdWx3yP<0UAqbnBV&qz_k0V?@@$zGrDy>I4}pW|qpa0F(nk=in^Oy4ln)`3{KnLy+oGteWU5nsR#j2mVXgC= z?on&2+udS$N-c>ow(ENH<8e9&KI&;IU(VDjV7{gzd1H&wXXqx4bB z{yC}MQf!J<)B0F%?8Rx=_((|Y=@aX5aBKNJ%e~GVAEoW+QLzkEU%lN`_dK!i#8|FR zH7wY_qh1tWKNHCKV!>j3*A>y~J<})pS4KxmcU~-PF;<-K&KebxXr8Y3ZK`!9VP?}7 zsy{Si95Hm*pUbelV)0HOSsIgOw$OxD$tTL%eV2<&i%V&i#lA3#tTNQT%uQo*#->d< zwSVJOD-fX9lVaT4Zp~Pxq$u#z&zepz`>N?qM$>j0CJ%?EX5)SVM)VkYz~0IG4whpE zjFfEWu(O>9)H^TVNnT1`8q7CqKJ$JL)gE4ksY;qqe`V1X#?mL=U!HJvN9px--3(Y+ zp;!&F5Tjn|?=Lc_`%67Op~@cD#R-E$k^dacjDSP`>El%MaKJz$?d`DQ7-v%_D+jE- z6aJ}!u`LE7CW8APr<{wam6@@ay`8hY4TcgTX=7~R%)$r!0ennU)ZSee%EAqYL0OOp zC<_V=)rZJnjcu$i`ls`uy^inVsy)f|x)&C;WQ+kG^ z^7{vpDU%|fzWLr43rK@|VhIhZodu?)20}HbqwN<cP0mkvzlyV)|H-{hX<#qLQ+sPyJp}lKL%!(I54UB=&YCxyc)SwRc$3E>l@L;Q>+4YuEA6v`_xLymDTZkV zk3OIEFgsAE*w|t5CjRb&?)5#3{)==T7U&ZJfpnLBms^G3GCSHo6i&2wSXM(1{0gW< zYFSO;&Q%k>$pVX3LsR{0Yo52{%8YJbTeJK+8WLmtP*@wNK5o<=$u>T`6#e~XOaCSB zwU{RhE4e(6gg?I$^{LqBzqUK=?E@p~rSRED!a9PhOE=}pbbRJ3xh88F{nq^GQ-sU2 zW~3SoM`_;7oXJui4bf06tH=hf=v`jR;aI&iJF~YhuaMbVdFgOR=Gv;!n(TU;XB#Bu zdYhqXe(UPvkhRr^KFNl;ebQw;9!p1CZcj?JNS9SGj%sEJF0D*xPZlK11l^yXqF9q& z51&ml90-}=?2||~gtZLzQw@iYXlAjs8dk=S&=hA6{;VxhSXpv zN!j|9CkboxQ?OQu!|A23DmFr;Z;Ti!gcdElIO9Sb;|q`<+R-k$=Sa zl#y6|m1zGP8R59oesE+we;)FSbP!b+6D*E_YECW~{8dq7XADmH{}cDDoSd;@mc~vv zUdb7Qf1?qU5KSvHtfjLq5(;PeFaA;f7oWv_@BeQpMj}OlKyLIdJ^zvqCkNhr(NQ&mx zJ*ln886~M4AI!bhGr!xloJ96(g zj*iJ2L}&Kt^zA)|TKY_{6&Yz%b)_l_GOp~>`*R+*st z+HdFUPBxM_kvSjWq>|wd4jHKD98~VQBY4I!fg;Vk_;Z-T6bowLc`P=xS1UF8(vZL5 z;oiXqjvA;?&N@{6rM7U1ALq~43_o1csWWAN7tP)nZS|h_Stqmw-dJ^6>s7#bmB3DZ zw_%o|CC*bbhNWE^VHA72OcIOqI8`O~jY47?>VJ+ihKcE%sYT?}&xZS$pBxo>dOt2j zr@my(#q{yifM@7ExhpZHtW4^*N`lvV&Pm>UIhXO|QGQ3%a8sNw14^&^#af`tZEJ?H zZymcdg7Pvoo@$k5nU985w+Ef|9>S#j{My8w@a6u5K`3mCvRg?L`zCCpJu)2`#`O*=OC*;#O`T9Zm4f@Xaw~!73UvE>vsmI zo-lE3etiTZ=SX?j-Iz?9b^pLo75n!d{_k>JR2ibEIy}Tg$4qrf!=hfjdJz_IG=zeK zUGq?Z=;aJ!w@!!4v>twkU!kpwtxeFFltFO?o@36r5%;F#}*GSnryN`r+osw#cDMxYs%T- zl8Wz!yA^7ee@MM!JxG?wGrTUEY!av)?%QO0eAEf~Fe@N{p;#0sbme#Qbg~T4{8UnT zW@c$XTre-ci}Be4yp8$2T~RsXt?%rsM>cG3#sRfX5=4H{m6oqp!W62GiXss ztL67Uypmz=Ya%l6&`Cj9Z zQ^|P6ek!@)^o62O=^Gw8_3L_9E{|7{4AaYt-li!ET}q$t2#74})ps4ga6tqWRd?fU zThyU%IV_S#Znr;p{GCpmGc5`N6Q?64P=Hoatsq|Q- z)N@Qzbk*Udg1N}po1*jysVZT#Yoe?}!c6$tLmAEw8U z7UY2W(I4>mV8U8It|Yp*CjLFY=z9&Fo(_~(r+rUPzM8SP-QB`3f!{2!Uu>NldLNRc zzNprDbldS6tN7qS7G9%r2CZu?5vf{1sF0m$O7#w;oPJ1$uzkp9p*k$@YsZe9PZxTk z8fm6rO^+x^PdPjHJhgRnkH=tURz$hE2puiQi!dbyggk9(j!4kltJF~6Q`$XjNi;ph zF#Ea>Y{^wdal9y*^J)!&(8rBO_4DL1F?;q_i=Xd`PnWKc zbI5`x54&g;?VJoCw=pNa8DGBmFzbkz?k7K*$&Xl3KY_S{{MDPa#owEw^3&*yI{Zi< z9d^!nG9k5-hyF-|w9+1S^I6=$gi6;@+YYf`?GR8PeFU{7Cr|#ud$Q8q zS_& zJL*Q^jY`(~?wd!|ulwBHIdxVo-0dhlu_Mi?IQPQYPKLXm@(vYi+{k2mNiKgR>*}D` z<7FetQ+r=#G+pQ6I8r*yI4m5+d$i&qywOMN#-Yl~y9#zVD>0xULdJZtjgmX^dg9-l z8<#wEAdlgTWNPDXF4(lBWEz~l{TvhXfl=NGR;Im|6nc+;mP=!Fcuz7fU{psULm|%e z8g2BEAA~21@_kc`TIGIGGR+Y{fU&&9^)%HDbAI<$T{$Qu*=ZX1GSG|U0QO{jIJ6pKqg)b`@yDU|^ z{XEl0FC)b)MfOEV%0;LBrbqFfp6Zt1MRHP$hA*?8w{Lvy+Uaai3KM38)7^e;dMByV zfgJiG!09!%Z{OF(@A-5Fuu2XDBVXmJd6zx#%XW$8mN2pVbQz7%+I{8-2lIvO&z;`; zMUY4-N699314MAlKn~rF#=B6lxBC+5&Ni~dTtijTO5D4a)4C6#p0igyqV>8{ladDV zsduPOSu#{Oqj3t=zOcfU{P96+RJx>R$9t{}_Nez{R~}w6739h}?tZdlPQ-nJ%zdi< zR;NNQ5_W}xaY1k;QAee{zx2KA+3ULRP>%YCudD3bJNUFdr0ZwKX%$IPlSp}i7Kz}W z!KF^o9mNihG6Z++-P_nacel6k_OekUg@reC?7HJp*7s|ll799|*zSAv;$m>pt#+2@ zhvFB3Mav&J1?);E zhVMjvnL58#amoH`=m%!4?%b*T%S@c>yd6KkX^dQ{>2x0%u9?Vu(-3XfU0^%d9X8{0 zyd)7-?D?iarGGlpZhzTIvmVubP1w@(#gRAWTC53tuvfuRd0MmLd(UZPw$o`d1>Jdb zkGA4Pz|HgyN^;I%?Ewi+#%C2moG)}quI=}BtzNW9pK_Vca*_vFTPnR+CQIkh&(T`BZ#mynWX|KL&xh&4ynR&Wp#{-K9E(lrTUpKIr}{-XtOU# z7UfXWj2_n1cJGV*S_QRlLNLhJoag&`%>8qf||NhCty|6gt|E4x+C@z! zGqXx(SVF6x&hlK0vv53kLB~qsd8hQ9%6fFAbWdOLWC-o#X(x$~4nNN}H>CAM z@_uDGZET|UIWK;*x9wxdu`WH0w3BCrG~Z+>k$If$Fy>RCfF4#=KiJ5z)A^u-M9z5R ziJQkn^i!{t?rv_)2DD5mIm+hrEQ1Qc8Bj}C%dFa)6SXM z1qrH36geE;|19SGg29y){xAH^GS{KFumJnIC*zhrJ7># z9dn8*&LYFlt{=9WBBBB`rJsLwUTDp^+{rj`3>LOaE zZ%!U1{-mss21}NRxBIMUuaooAcd$n7h$99uZ__42YYpLyf z8u&dV$6lIdvB0^XUFl@TPpLAZvvzWQa$@n1RsTd2Ji@?Zr0TQ$$^VQqDF*oQ?xnfV z0j~p0J?#j7wfkJNtrv~r4Ue@)$WtkP(y?nMOD$3^2<+FM8ye|jGoYY(o{Ir{xe9Jm&L$gks7ejiA zqQ=SS6h#I4YP(fiqGO^)=p9BzN@#_SQguS-&hd;}XY7qT6ypbXXBAIhOc2NzOhqZL zPabBNiD~0k()*Zo;xftU)TNgR9Pdm`GQQ5n#Ei|xzq6{LCZAwUyY*&&06*604$~Va z9pyP)jzN{7%M#`!QA-ZL zLea-({m}kKJbtSF4lk%DA%3g=cNviKcRnR|*Dfw)tBCvFX+^yhR*v>sfA>SN z<(c}66@#Tx3&pcA?NxzuExO{WLg$$8o)-*SluEe8jUBw7uoCxDE4ni#Iy0ZazG;4|dmOm%A*f+Xj$JU?grdrNbJyoO{4autV{wB|!6mb6{Xv&FSTP}YmB<<-zP zcJry+X>AwpFxOsiqP#*XMr&28;8@_jXl`Ep>UAy+{92UmsqBe2XCRNs9qrD2FB=^8zw) zxim^n&@a{1aDlxlgC-qDHdR$3t-6tJ`NN5lk3`-rDCTwccReVbOFfg{UkG99bw;T@ zd*Buc(fUE3+rkR^y1>Zol$w+=*v%q zZdxfmB^fgRc;rM!?fBh_^GyeYio&Mr=#u)glh5&`-fNJ(C3Cb!F{yz5`t@r2AM{O+ zYuKW^ukIh1W3UTsUz?78!x_crH6OR^2A_{?^7?u|>el5<(v?d^aXk@ddaF{qG+PtT z4gwh`h``ZJ{@TFR8CQA|}o2ij8EWAoIg&gx6|M3u_tAd zLjj_>nVdcj?q5%q`nRvf>12O&=+}t2KQ~z^kt+OAXTEAyT_U0I&J6~tSN$WiWZy0! zk7z_?cZ<%>^FPg<&xH)oTc6}`%ub*V*Rgfe+83gS85kOxo5&&!Nq=`>@v*7GoN_Iv z_SZAf$0Lo{jom4zJ#%~y4ng;yHKy2QWucnTkuYKN&b3!tU_V=BgTdLNwA7GAiTPte5CcVLimrT# zpF1sTDEnTPhq*7bM(usz)zEPMaRAxl0E$-TrkMUnIzIZh-?%mMLXXc6Wd?JZ4lfoP z-9%Z=plMGyb4_5W?l7$BYg^bHin~%4L17`96#v@mYm3e>dv8cKE?l29NKbdN>oC zo<|EE80`4)fvVj_?HQzZrRmlOM$Cuh^3v5C?Obk#gO~b0G4#C%Qnj7B_-cX|QsrHL zZQ5{`VoJVHm=I(y>WnF?-$Fdi zkMlOqJfE|Yrcn(`e=lAy5AT-gAPF!#jg3tXN+C^EiSU+mhMC3+oWyAR$Yn8e6;3x5 z{wNvkD3YT5_RX5R=KARCYaJc=x>TtJ4^@xk41{6S`Pi<_Fh`zBop^~n6QWyuPSy6n zQF(s&q^R&pcs`bNndj@NpVCJU4hVcUOK-72WbV~G%FXuk=X9N3c7wK>Wyg~PIql_l zpCq4>8jAlm)Wrz+5Xv{#S+Aiq$i-^3({@4+U0o)H9=U3^Bay^%&jtM*89Sk8b`0-u zAfes+`U45={v9WnQ|gw}PQHmbwc{(P!<`dla3-{;%mcpe$5IICZd2!I7Ps@JXVkcu2P55N&}tCnD5DRD;%XWa7u}OBO(UBdM!K)Xm*(7u2p7G26lJTo zuY+QWVP$^mPH6}2)9&y0r&eZOeNJA^nty$dY`^upc}P~NjPxl=(UhyXytmx>GqSy{qqqQ!tbNtb+ zovZsUge;_`3Vo6G>G>+S{{F|=(@Zo}@Ke!Y$Q^B=x_sxo;|Gp^Tv@#@#z6Yi_lCb4 zCj~8}f34@?w-plIfxS+p2gO%W57)TOj-lD@Tz1e><{i79QaAKkFuHue)hKMhVMPA4 zHPr0$Y=%5*iOYL34w~SXpK|uz(7Wp((nTghLrs%a5k2BdNwb^hlRi}82enmC`j459 z@p8h@W-i`i2*L9a$SBKCl4?(lUhK%|Q01d}8M*ArQ(Bhz*-N+2YxOHc)NSe7Q~r-$ ze8txESJ*8Z^v8JCcdI?{iJJVlFXXs@=QOKKt&kq?l>q1a5|Y(%(jwOcHM2Xr_#~cc z-!Za`dbER6LtxlTBS=OT;m*;-Kj!Pq<6ccxx9_Vjeb&b*-{ifCJeH0k_xEP#L2Jnr zdV*DqpJ9B%_`mpaILenlXDV4ObCHFv1{>7`>beaH^MtqTM&{X-xELYd#^_dY}-cG6Q^7-+c%kVOwFN;@`f7i^awfoXyKjzY( zF$tN{PrREjKo?f8s*%up9yYykl1llq?A*mt{zG~lc3MAZYPi?!zm|2}UtFwS|9BDg z*e5{XX}Zr!a;XAu0#ifv8+9QnbIm{I$7Py%5{{ZjyE}B%blLR^Z5dew zsIO3*>19^Zx|J$zClwQ$F5)SA-sYfH`Scg}F9+_v|6FoaP@3K`{*aBm>EJwh6{mDs{IZZ_))O-4&ipF754^a;5y4gXxlq@#$?;IGW`T#yzG{urp zxJonI^B9`6wd;lP9*P`aLoaEhMf{XuEt3755We>FC;x}kh-f zYAZhN7~&i{?{s^TJ|$i;18d*uGBvK?YRDW!*(wb`fvr01wOr)p%I3ewwAZg8P~vDs zkGr>pqMX*@DaESgll7DCh91rLVl5*p%*PX9VO&Q$W?dpsE>kz_Uy3?sl@&QV+k7=r zO!k?*Ae9B7|3=f`7fXxyrfafFs*>`oI5F{~Pp->pr}?YY2g6oFEwfN2 zW&Y4DcsF?VWKNNyCAU2fjc=$~7KB55DN*#zk%5}#=E*y>WUf_9;RnU89JB;^dx7dWj)Cv)1A^hfChvmLdf%{qn4pGi|H5}r=p;W1V;yKu9H zywGjV_{*J=3M@T|?n(aW($WRHaVNK|Ba4&cA^Wi|^AktNlQ}rwi$3EFi#XlOaB`2i?eUSxQ3Vrw{m?aO3fXiV#a%K{Op_0#fZLW@wS)Lw2*(O^>Wx4dHR(U8QyH`L&(!gLi_9DAF@PH(!JADE0w0(S>1JC`alE~ zc0QtZ*=-4lJF-rbY^~we z`m+~4* zj(J0`-MQh&BRuUCmbyE>kv0^Y#pWsTeBK>tmP>&St(iz1+8t>Tp>k29BTZ@YLeb$; zS4NRXx7j^MlT61oUPf5T9`$f*`?`avfU1_7-RD_US_roiTH^70jQqTbb=YTDmSPGY zucN}>B+~0lCzQ@xQO&;L!PJzzFuZ2-dj9yOqmCH`LM=8KUxHLZCsI{&)vmRj&S6Y@ zURReJJSKThCfMn0DmjvV6UVLNKzneKyC z-Ya((6QjFyS720AVFLQW`rMHR9GdQPs|BN{N)M^|cCWPxS6_rocO|>~^hb2=H(#`u zJlsTk{hnp9H2d7Uhtdi$t=9+n5J|%)80}kwwd*>%ZqJ??vbfstEWX+JOul{9!FxbU zXSNL0G&c5|AJ0oqimKfgXvR;GRqZ!^M$#k0nRS{|q^jViEs1w_dEpFCK&0939~vjT zk9KIXc%#V`Q9{-~`fkp%7Nd(X!IV|s2R@{|f0JVnc*Oqm;Sp{T>w{-YvR`|iEbTly zMef)6rN|&XyYgJA3@vXP1!T$lApeh3!Sb);4ztL;E`_izu~zs9RjKUEOc(@-wNzvf9!FYdO<6(lxU1*mcCe5&{+W==+L1KXoO+ z@xe!Tr+yiv_r86#A8TViodiyItPJrTP@YdJmFf;)KIG7e1k#ZS@>j{hVCcX_$ZPGcEy+7?W+Xt03vbhzdiyyeS3-r^P!CF z)%>|B?pO0Syr@2A%6=5WE)RU@e)Qo$f6e*4K477`2Inc?@GS< z?aEIhp9`6)e=<}|Bo;A+KJC#N=qq%+R`lBblKOxjTAVk>E1xH1iL;Qy~TOssZl2%mjmjl{unaLC42VCW#@@y zYhmq7JHx#p1BR8V`yt32lggcj*SkJV^EO_>=Ig9RX`H0h@hE!~Nuu`R!HcDR;p8<& zmZ)(=4!O$37*@{5pLiLCTHEwgo~^wwclx;$fpk}=oRm9?x~S;*t|MZp`G{4or}~FI zSABN(x_)QbbL5GlI4;zCE>Tj_`a_-~GJB#Ze#pp@U!;C{ z`NEB`bXOJl4pQ1Aa`uA}(z~6QzH6VzW4(|_n%pOJAvxf^)``P1?@49dBDAi&^}W2j zPKqooF8*uD+Q#pFpyB-R->NS+&Uya5lI@?ur+>;vMZxk>D-(>9G1ki7P8H*1WeyZd z;R{HSgo-JA0Vy{hFM@>|0Y$LD;3$3;G(Y@56_N6zVgI9u6d2{7B2qLz@Zw*KNa46D zt4)PhNZ=A!khf8Ih2s57(bex|R{CL0cGsc%u1=koxYPT{cNe|R9#)qWX~wyvT)`b| zsbcgbWS*ZUXg>6wo=}>p&b<%0U8$?u(qL;o4h)Dnmi+j>aX?LB3P_L7K0An^3nAQphvxEU;SgB^f`F z$kO6}t$E(#QtDUpt9LW zX5$*=D%-O4OvLzu&-$m9tydI*|2P@>+-?qAoh6A~<(oBI_iHxsx$UMrp8aDoa8+F- z#Kq^RH!?o+fg|-q6Iz&(*PEAgVX4Hwe=)vhPv*${{!cqz-ukO*qW-yg__|4a&E$Ws zru>hp_}6+$#6R_vC=`l?j}OU$0_rz$k4T`-8O{gPIRnp;NWyjeYf!>d`?f7*`7*Jb?lN?Z62vk-B5dV1h#*bG5+{TF%coXjPKoz5slf9`b2CEBE5|@Oi zVcfC$zn5hHR*;Rq9ZJR)7>JUw6Ry-70V8~+3dY&q#mN-o3=B#*|6LwqW@St$AcwN> zq4{_K3xGzTpimS)ikF3-7sdmK5QRhlXTkHq`Sl?pc6RnyXI)Adewx4;@%TDP;1Mqg z;Bn(R{tJQUciv<#}AIjj~|Z`#t)7M z+(Z00XmC6%iEI3AiX9vry;xN+f7!gz3?mKP^`IA9kE z*9qgnp@i{(s($b~VLUjLFdiHVjtA%={&V;r9|guG{NgC^2#yB>$Af|6fpUctZWtvT ze{?_YbKrRR#sT0tp^O!HB+M61u&%&!a6C9T9vs9+&^h3B5Fg?8v%rCV0X#kgI9~)f zUqIgp*TL}+;CKjdJOnsj1UMc7#K#Mc#|w_f3*rO#g&&U>9FG?qj~5(|mvDdKyx@4e z;CKMf@t@-Z$KwOX;{(Uz1IOb7#{=vG;r$>!K5#rfa6BY99ugc63C-sVoQ(m-rNp^f{P-Y0;2=NXAU^=F zPk0^V2OQ)F9OMTa-sVILHq;$PYMyACz#AA8?Q#aF8ExkRNc6A8?Q# zaF8Fs@9E<4AV7W~2>f8d#SOT5AfN>KAwYg0Kz<;gg!v*sejq@8AV7W~Kz<-Vejq@8 zAV7W~Kz<-VegL*u%E{iv0kDy(K;^!%owEbZ(wTZd#8iO>7gsA&jEa;fM1}3W5)0%NNGp(4AgMr3@ewEhGKxSbpxFQq9;6e2 zO+XhC;UZy1AeBHSfkXm%1kwm(5lAACLm-6+459=H1oDSKAE2KJ|3x5qK<ihqOia~qQF3+z(AtFK%&4vqQF3+z(AtFK%&4l95lg^u)sh^0wXvQTt6CK zbTH77z(7X=104wrbR;m)k-$Jl0xS-|&k;lq104wrRBafj+b~eMVW4)y5O`&vgn^C( z1}ZoV)NmN6;xJIhVW5)3KrM%XY7PVS90ocP7^vwmP}O0euERiOhY_@$5(cU}4AgfR zsPHgQ<6)r6!$6&ffl3bpwH^klJq&atFi`PfpytCs)rWz)49|DC}DwPV}p@k;g^dOQpMAHoN{JLud& zUkti-f_2*nw7@ulzz#6V+V->wB>#QhxbOUbH}4Ij0dkxW>ui5EcuD;>8^UsA^K_gk zA%Cn-C?UTVD1ZR)D-_(K1h*EuXl3TC%R;y_gj)exCeW}E?h^1uF?$za3B>o?_v3Bj z?_ZB!)%@xNl(Vw4hKSlbnPHrOzFOe_`T#IftS&!_2aQ`NqR~7kz)S%qkp~Hw2YwiW zhYx`U)m7Rs5jj^4D3$TLI0`#0DD=$Gs*?RZR0jZJx++_0A1#>S?Wz--Jg=lG#eD8wA=05Nuk5LTBEQ$tsb zlQT{P#?Cg}rY=snMJNx}*onu&bMtg?Dz^1o0ZxaHAbKFOf$|^$&&dae{hR6FZUq6V zIdBs&Ja!l?1Q7lu;3hjmEHJjl5ObjM8T=FXoEyf&%dH}Ye+~DyiWs-ElPM3@!V_X< z?`CIXZ)~=CUO3KddtN9c8h@MkU}zqk2Le(P|7KqJX_;f)fKZs*%!UVR#bau33$b-} z;6*^e2cW*e1ZWI5basQ-n!0SfCa%eE+ZdP^(I0VLn=pcEzcZqbG3B^c}Hs3a!3)}jvfM}Kn3Yb15FaAEUz>x?Zen2mge0=|MT5fJ` zJiuWzc33ML8-nRmHRXlDcrfmm%@8-cx-DrI5)e4fI3swWJZKz36y8|>SDN*kMF6Ss zA4rdnnYS)oAeqF228=Tja4rgio0R<)KH*kam4;s*K6zpFaD4gN7u)&6#Cb_z zO9byFQM`C_{C`uT|I+*#N=m31iaS~1eCNNj!T(h#fZ7NJ;BX#(+%5dqp#YA{pl`w2 z+uMLngxj3pK7_@^yD0~bC0sSCsRv6Q6RR!`4hPFR(`$4O}O$GO5hjh+n@xTA0PDsi3$QI_@F$v zBn6Ow_%|U5emc1LmfIO?Y-eWdWQL#A#uEtOvM~^8MLBWRP148b5w;E&0R-i^olGEK zfQO4fpz#z2@&H7GtLA2pwO84UcYB@{&WGlK0=9nxFC6e+I5rX)uZkoFYihX}^7cF} z42_GReuE6<#k(tFLpFD^x7~~wx6s?VQUJ*;9$eyRL&!jK3Lkb739*?y5L06y;+xk1 z_*B={(SlBB11wm4XyFBddfeI)NTCsfavRdc z+W%o9w&(v4XkL(VAYLfJXAl{$4#vq|!qLTe^U4XI=-j$i;0zmqbp+Hn!-fkI{})gL zOJC>BsD2!MgG6OOZQ#8n9;8<)*G44A0xI1ik8!b=bWZCfhMq8&HK5qL>D}W9D{{^iO7ZKg;^zi#zTgQvDYka?n z7>*0taI_<;7K;OMg}9aLW)W|5ZMPA%fm(sHY`CNo@gb{O*<${%7Tfc909IU{eM6Hs zf;ZwySzbhIlZf%Vn_Jh4U$%{akA)XS$UFhNkwmm@;_@;IoAKiIZMKdVZ`yF;-M|Zk zZYZ1<6BVyKULXF{WBiu!Hb8GINkPyEBrgviPLGKS8epD=h>DDesN7}?hu`7eI_zI7 zQxG;#5=2<|6C1XeqJpZLh{ER82!2C;>#%Z;Ykdl0 z1_DlkGaHhfsb z2LJ|2%!py@aG6kN2mp7p!^RhmY+a8x=(hnEx8;Ic?-3QQ<7Q3Rp3~b1E`DJJa)Y>( zCsDC#DysaEB*YitY+bgX=5D|RoitI=imS^jZ4xfNQfTX7H;e;R zG4vLnfR$I&*lf!1^-NnwyCGT-?1pHGh*d&MX0xln*IaD_D=xJSL=&JSf$bh(?+|AZ z{@qTr;zBjts*ado9sh!Mdme2g$My>?u+@w6!o)-?uA=yd zY`5phHganlXc54^A1*>8CR$ZZkw4IG&yj5;)i%&>B-MzC_Rswde7)kg*`38LT=hor=vbK0v0G$4g4;zUI z_HS7pe2MBdz`_a1U=SV)A5epatDi%lh_{odXovYL;_YQBaW)s1bKgMB3&i8NWH2!i z|EFyNeBJNXg^V-2xQzQR$UyRs*h0oZ{!2O-U#Pzg#JG(OoEIi|U7#HT)M6s4#osmv z@C^l9hl{tqzrn>>UwqI&M7V!Tw&NQgwhk9>e}9Jy2e$EXj+lsW|3lsZ-=nb&#NdX; zhCTq5_k_@ah=~6~$^qX_vUS88Rv1)ZpjH!?rX;3>#T6wsFDvmqFWbNhmUDpUfQDK^ zIR^r$llzxN%s|cT|93fuhRC0p5qxjX*5Pg>C^z74Y`zc^uA1T|XN+$k+B(*a4T6IDubu-}Y?Ze>{A~?@RumeC1Dv-y)^Ne_! z`**zCTd@5~ifrJ80UNVK#;Yz5WU1v9|4@nTE!uu%8bHMOk`uhIAfAL(afnqUAKt#ZQ+la+?;BH;M|CnD8E>KjD4}6IT_pinm zp!asRC;l0q$&081lFS|>?3U2)n6Y8H%4c~OV4X7Jg2f}^F z2fRSyp9N=*w9^!EJPufzig`d8xNe*yF+PmJ$o-@2Ibc?X} za2rM#)QF9=12Gi>K>Jq#Z_mZ?0j3z&MF`piV84w}Gsg?;2@uN^0~?u}>jel$ZERg1 za7GwcGPeO27yRNp2QlIPS%gnG5M=9Uf9<#t?mxb~0oOM`RJ4EVA|aeyvJJqvvZ&w0 ziwl5pjYY%+3=~EE9rE^;Z}<@SH^}&%H{wGEk~~hBO>Tp59?aII{A>RWR14r>G5j)v zNKyuyGw{V{e0TQ$RQeY8z;A;V|HvH_+m(F_F=V z{nZxZ53JfcV0=LQ8{my92x2OP*k3L2HcyY)u*4e@29BD<=hBD@Sj^tm)_Ak)z@O%` zbqR08!yAA%I*W)2SVUp-a*l9N+1Am5CU^rZ*i}SKtcrgGmiV*OwgDB~g9E|g>&|d{ z^t{BWM8*3Htv}Ij^T-x_4jAt%z`9vry@9u5L_{m20EF$EtNI8>(`{Y6_(&LU83=%J zd0>3pPDH?eDSsfGptlXUU>v-m4Y>LTV$0X|F99X~puerd{m1SSqzjx#iqESOQ+ef7 zrDY`lREO>F!{Lv<0_(o<5ipV2rt){d|HU@kZ-m2jtK%w6h$&$p)cISkop8$I)|KLy z@g?ZQhVdmL;c)TqAB|;%!zi}_7u<#eB}y>BI0^sz1MG$}XXaO1hZKcxi1{i10 z2;u~qv|}HZUgQ{_bD;;SXyFpA1C3M+^wVCFuR}U{IPsEilmCgl8P_npzzGpxgF0<8bGjY+%K0#^Jitc>ym%th6=IH})so z?IkHU62TjA@!>C#;mZCY+U>bEd=VNh)FCJ;Q2Pt!fQcwt(LXK1_P5~hNiz^EZVQgU zGUDlhs*;G<=1wfaQP^AO*sp}c2HuU-FA;@{$NR^I)_-}F$%Z!I>(7X+x#|jXihr~X z0Y@!uD>B=#x}bnJ(!NBLubhO)ADwxGBha_55BTjjJlXL2`cKjqARV#n7}j1?@&EL8 z^}lf&NA!376#|MNEeiYiO>U6}kfl?s#+C$0ZjuH?q1b0vh^!DiI_k+%oRATF<8E*uf=#mi+{_n|M(|8!OGS%(L3b^F7Z(tWY~hNB?g zM&RjqJ@-Du8@4};iTBO%#Sz&y-|oPGH>|h?p9a!sTlsT^gw?QD6v+@qYCv1Cci`St?!%qz!t zs}TVoq{lA$Rvb^4Zp`-vurc2|BG{wUN*Jq?M2Ayc%Zn^ zD^-Y4Fj<{-y z=g6Z*#FZ3=7i&Bs;`5U?XB=u8Ym^8D%efX6afP!^-uWF9@WmFDFjgr+3r=6tQSp{l zU&44y0l(N|hA2Kf@B_qN; z-J^{IzSEWgElxx~)Lo=t`)vA%Xz7S)-wy2QV3mA>BB4})3fE@k51l@Ci@fc zdq>Ad7e}ZznFe##$|dON(ZcINtutv`S>;%~@a!i493`lKy?6F46Na&JiH|)o`2t+2 zCnv3YP+nsMxPAG$?&3I*kTi{cf z3a01;oU%pU&Q?4nvUmV4$JhFSi6ox8Dp3{mbhZJP!*OEp18_}R%?R8UZ))C3fotMwM&LHP z8Cg6?TnhKd+Vf<<8&VaU-Ha?AfJYXehE;OMz-{rSvUtE97IJ2kx6NvL7MH2n%hzXA zdPPB>sPS1GYloyLHmfNtF1srfxUl%lz-`fH%%}v3S2*Nn=1z-@LjvUmU4#*B&r*NnHBZ~*%F{3gca9g~oEFN$xi%$eQr^JM@3{7P59_RxW zf7BMer?WT%w^_}|;sN-E#b*OGv$}pB$uTG74-#w;Vt9JKfjH~kH=e1`Uu}XJ ziJir%ds5kwv+>-w0+)V!$VW^Cydm;7*11vgR*6gN5r3R-B8hJSZZntaf-CR>Q&Tq4 zP9^b@C2lj9O5PE8aKUE;ZZnrk-U?jP;gbQUj6`KKmw~($cSwiN2-{{X#Rd1(EBmR~ zZxa_zk(!$mENXU4hBjllVevk5_X_-w$9 zwR1Ks-UE*;J`wPWT=3c!W^PzK09O{D54g>4Zdkkr9$9=U;H2ZV&2B~(?{O=O&j;IP zHMP-HU~OOD*?WdKcRmG+SH$ARdOO16zSL+hVQerAg&yVuZnK-7#U+SP;L_|wJj02A z({VQ0KWd47Jc~a7?pa*y=6t|yc2ig!n+v1FJ&R8XoH@l7Zwib1PBTGOd}qKZRfT{z zws_OC_ybjulLc~sdMZ`vXcMimI*+n=5V#f%nMlL8z_wXU?~9APd!RjwdwEZj0V>H) zF_!CzzIXuc5BvD3IU8`B-Hg7t0#{$Wn+ABx8g7d=qc0wSM_+tC;5NG%eenR?7etv* z$2;17)!6K2WN`(ag$i0zNt_lne`lE=WffoPbV7-@4BTcnmBoX=Lpr>gNZuW-4H`@S z=%Qu-+GkWm-VVpXC&;KY=>bAGMkdeDv$!}|y@c^+aB1fQZnK-Zs2PEWMa`)sUa_j! zqD^6O*(R>Qg~feev}q)cvUKT6gs~8iXYmKBq8kh+l6aAk-87a2iW!xlr;l@M!^5j)o*t)Qm?g9BqqFv!i9ka3Z;r!^Ew8c+>`C?g# z(FF~Ks}0@9)Q2~$3O2*$(_eT|1?#zYKESHRjGeN4bw*8J-2&m?A>nbRD-qL!XzvV~<# z)EC>}+6$g8Ie!3;$+U#6pwcZTx#z1~V9S$l%h;61W@>)O~ zL-`RA-&}q8_uaFf`o8WdZex9%$Zm=oe1`h%Y!3sR#oOUqZb*j7b;F$)c&|gi@oY&QS$lf(-rB2&EiFB3vf5oHXdBx znTGJ%EMDX`#f!2gK8-e_c=ylHo0B!zX7S_zpCqN)zRAHZ8YlEgRp`Z7`mnX}NNKEi zqf-uD%YYAbjDFMN$9KqAKGLPQx%_nb;p*=B`sTypZ>!7eXRogohkNH2&ko^Ayi7HL z&R_3e-d%oNe^{KN7sBmsnTr)X+gY6avbx@Tdv~?I{!z%}Yzl6*mxqTLvfD@rp-yMx@MncT zYx(!rJB!ns^}GAGE4{AT@2_cat-l`ERk*)t!hdmpgE&O)$0b>b@nVTTD?H2pBw!z0 z-mU(4@RtHtIb>V?Im^GyvM)s_iuc!>)%%@nw=9btJSzNWx2bC!hJC-=k5!$I zdgTAyy$)meyOgdOjy0|9iyMqpt|>A524h*%%BsO&487H45o|D4XPrxbBQI--Xa?8i zT_^pJ24i)Oo0BnICmE>0byzYh@XZHfb&j>VWDM8IX^_EnMODZF#lcvOj%X>qI`8WA z-nzi|Oz$m)_({zg?vpPyu`k@FtOSjXQ3ica@JsHqN#(h@!l@^!6vHN)SnJ4vPv$B)kDl}Bipf(v5ql!nUskcUf20zyvbO} zI@#6IQ8Br$m4@iam}9xPoMn&8=y?tY1k>k%OXwT9j&;ga`Iw;ugTEulg6NI zG}g%WpXA<--nRkMruZ5hAE)2VOZrAlUeo+-@|NaXgNjzEZop8;E}tR3qL7n4$r$Tt zQ$PxI9qVZW+DPYgQ|81&4H8>~58Jg;-Dt{2I*QHc?2~;vS}!nHg`175f)3BJ&<1u|0R`uTdZ%Tt|f z#oGt@maOA#%{tyfW9WH~=OE4+(sf7YfCWU;d|7j^m0$eYKnESOOt#R zOb_B5uqo?b<2Qy4f1{~r9(9du`bw~XOGr<_C3GDO66q;um-H05F}|)Pj_q1UzE9U7 z`;g-6O5(MytI21D77%xK$Xk$}x{TsMM5g4|fpUmn5E&3>cMi;vVn%$F{;tb>Oe9rnG+q{KfaDR(Ur`JZi`<6H6TuO6>}o8LoEA>Ing0u zmvWe^nG;>joak!iM6CG`CnDoPHqRkll5&_su7$oiTt~i+IT2nCaiT+*LeGQ4OV5L& z$k)|X$~mrOPQ-L0PDD0>I1wR)Y?d9)w~jf{b@n5?NuakTWn3-wk63#%T6>`zcNd0RE|^?zc2P}(t98cl6-UA z3$HbOw-U1<9jo$`WASmzG=G3GkObX}2}fg;_eQh|H0gCUDm~B`948v1yd$31l7CPm zmzL;ShFm@QyO`zV!(ohK$rA2(`n(cTKb=PqGjS(oH2F;!qdW*Urx4d6Yew-04kuI0 zgen5*`$8_TwyFHEQ1n2icQ=NUMBER FIND WORD ." -S" . U. SIGN HOLD #> #S # -<# ! @ CR TYPE NOECHO ECHO EMIT -KEY ACCEPT COLD WARM WIPE - -RST_HERE defines the bound of the program memory protected against COLD or hardware reset. -PWR_HERE defines the bound of the program memory protected against ON/OFF and also against any error occurring. -RST_STATE removes all words defined after RST_HERE (COLD or have same effet) -PWR_STATE removes all words defined after PWR_HERE (an error has same effect) -INTERPRET text interpreter, common part of EVALUATE and QUIT. -NOECHO stop display on output -ECHO start display on output -CREATE https://forth-standard.org/standard/core/CREATE -; https://forth-standard.org/standard/core/Semi -: https://forth-standard.org/standard/core/Colon -IMMEDIATE https://forth-standard.org/standard/core/IMMEDIATE -POSTPONE https://forth-standard.org/standard/core/POSTPONE -] https://forth-standard.org/standard/core/right-bracket -[ https://forth-standard.org/standard/core/Bracket -\ https://forth-standard.org/standard/block/bs -['] https://forth-standard.org/standard/core/BracketTick -' https://forth-standard.org/standard/core/Tick -ABORT" https://forth-standard.org/standard/core/ABORTq -COUNT https://forth-standard.org/standard/core/COUNT -LITERAL https://forth-standard.org/standard/core/LITERAL -ALLOT https://forth-standard.org/standard/core/ALLOT -, https://forth-standard.org/standard/core/Comma ->NUMBER https://forth-standard.org/standard/core/toNUMBER -FIND https://forth-standard.org/standard/core/FIND -WORD https://forth-standard.org/standard/core/WORD -." https://forth-standard.org/standard/core/Dotq -S" https://forth-standard.org/standard/core/Sq -. https://forth-standard.org/standard/core/d -U. https://forth-standard.org/standard/core/Ud -SIGN https://forth-standard.org/standard/core/SIGN -HOLD https://forth-standard.org/standard/core/HOLD -#> https://forth-standard.org/standard/core/num-end -#S https://forth-standard.org/standard/core/numS -# https://forth-standard.org/standard/core/num -<# https://forth-standard.org/standard/core/num-start -! https://forth-standard.org/standard/core/Store -@ https://forth-standard.org/standard/core/Fetch -CR DEFERed word, https://forth-standard.org/standard/core/CR -TYPE https://forth-standard.org/standard/core/TYPE -EMIT DEFERed word, https://forth-standard.org/standard/core/EMIT -KEY DEFERed word, https://forth-standard.org/standard/core/KEY -ACCEPT DEFERed word, https://forth-standard.org/standard/core/ACCEPT -COLD PFA of COLD content = STOP_APP subroutine address, by default --> STOP_TERM -WARM PFA of WARM content = INI_APP subroutine address, by default --> ENABLE_IO -WIPE resets the program memory to its original state (Deep_RST have same effect). - -words added by the option MSP430ASSEMBLER: - -ASM CODE HI2LO - -CODE creates a word written in assembler. - this defined must be ended with ENDCODE unless COLON or LO2HI use. -ASM creates a word written in assembler but not interpretable by FORTH (because ended by RET instr.). - this defined must be ended with ENDASM. Visible only from assembler -HI2LO used to switch compilation from high level (FORTH) to low level (assembler). - -Other words are useable via the preprocessor GEMA and they address is in \inc\device.pat file : - -SLEEP CODE_WITHOUT_RETURN: CPU shutdown -LIT CODE compiled by LITERAL -XSQUOTE CODE compiled by S" and S_ -HEREXEC CODE HERE and BEGIN execute address -QFBRAN CODE compiled by IF UNTIL -BRAN CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR CODE NEXT instruction (MOV @IP+,PC) -XDO CODE compiled by DO -XPLOOP CODE compiled by +LOOP -XLOOP CODE compiled by LOOP -MUSMOD ASM 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2 ASM input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1 ASM input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR ASM content of INI_FORTH_PFA and MARKER+8 definitions, -SETIB CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL CODE accept one line from input and leave org len of input buffer -CIB_ADR [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES restore rDODOES: MOV #XDODOES,rDODOES -XDOCON restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR restore rDOVAR: MOV #XDOVAR,rDOVAR -!to find DTC value, download \MSP430-FORTH\FF_SPECS.4th -!XDOCOL if DTC = 1, restore rDOCOL as this: MOV #TYPE+-16,rDOCOL -!XDOCOL if DTC = 2, restore rDOCOL as this: MOV ##S+16,rDOCOL -! if DTC = 3, nothing to do, R7 is free for use. -INI_FORTH CODE_WITHOUT_RETURN common part of RST and QABORT, starts FORTH engine -QABORT CODE_WITHOUT_RETURN run-time part of ABORT" -3DROP CODE -ABORT_TERM CODE_WITHOUT_RETURN called by QREVEAL and INTERPRET -!------------------------------------------------------------------------------- -UART_COLD_TERM ASM, content of COLD_PFA by default -UART_INIT_TERM ASM, content of WARM_PFA by default -UART_RXON ASM, content of SLEEP_PFA by default -UART_RXOFF ASM, called by ACCEPT before RX char LF. -!------------------------------------------------------------------------------- -I2C_COLD_TERM ASM, content of COLD_PFA by default -I2C_INIT_TERM ASM, content of WARM_PFA by default -I2C_RXON ASM, content of SLEEP_PFA by default -I2C_CTRL_CH ASM, used as is: MOV.B #CTRL_CHAR,Y -! CALL #I2C_CTRL_CH -!------------------------------------------------------------------------------- - -MSP430ASSEMBLER word-set --------------------- - -?GOTO GOTO FW3 FW2 FW1 BW3 BW2 -BW1 REPEAT WHILE AGAIN UNTIL ELSE THEN -IF 0= 0<> U>= U< 0< 0>= -S< S>= RRUM RLAM RRAM RRCM POPM -PUSHM CALL PUSH.B PUSH SXT RRA.B RRA -SWPB RRC.B RRC AND.B AND XOR.B XOR -BIS.B BIS BIC.B BIC BIT.B BIT DADD.B -DADD CMP.B CMP SUB.B SUB SUBC.B SUBC -ADDC.B ADDC ADD.B ADD MOV.B MOV RETI -LO2HI COLON ENDASM ENDCODE - -see: http://www.ece.utep.edu/courses/web3376/Notes_files/ee3376-isa.pdf - readme.md for symbolic alias of registers, symbolic jumps (IF ELSE THEN...),.. - -?GOTO used after a conditionnal (0=,0<>,U>=,U<,0<,S<,S>=) to branch to a label FWx or BWx -GOTO used as unconditionnal branch to a label FWx or BWx -BW3 BACKWARD branch destination n°3 -BW2 n°2 -BW1 n°1 -FW3 FORWARD branch destination n°3 -FW2 n°2 -FW1 n°1 -REPEAT assembler version of the FORTH word REPEAT -WHILE idem -AGAIN idem -UNTIL idem -ELSE idem -THEN idem -IF idem -0= conditionnal -0<> conditionnal -U>= conditionnal -U< conditionnal -0< conditionnal, to use only with ?GOTO -0>= conditionnal, to use only with IF UNTIL WHILE -S< conditionnal -S>= conditionnal -LO2HI switches compilation between low level and high level modes without saving IP register. -COLON pushes IP then performs LO2HI, used as: CODE ... assembler instr ... COLON ... FORTH words ... ; -ENDASM to end an ASM definition. -ENDCODE to end a CODE definition. - -ADD http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=135 -ADDC http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=136 -AND http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=137 -BIC http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=138 -BIS http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=139 -BIT http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=140 -CALL http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=142 -CMP http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=147 -DADD http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=149 -MOV http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=165 -PUSH http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=168 -RETI http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=170 -RRA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=173 -RRC http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=174 -SUB http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=179 -SUBC http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=180 -SWPB http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=181 -SXT http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=182 -XOR http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=184 - -RRUM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=218 -RLAM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=208 -RRAM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=211 -RRCM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=214 -POPM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=204 -PUSHM http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=205 - -EXTENDED_MEM WORDS set: - -POPM.A http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=204 -PUSHM.A http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=205 -ADDA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=229 -CALLA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=232 -CMPA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=235 -MOVA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=238 -SUBA http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=241 - -EXTENDED_ASM WORDS set: - -ADDX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=187 -ADDCX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=188 -ANDX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=189 -BICX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=190 -BISX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=191 -BITX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=192 -CMPX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=194 -DADDX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=196 -MOVX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=202 -PUSHX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=207 -RRAX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=212 -RRCX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=216 -RRUX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=219 -SUBX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=221 -SUBCX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=222 -SWPBX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=223 -SXTX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=225 -XORX http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=227 - -RPT http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=219 - -CONDCOMP ADD-ON ---------------- -MARKER [DEFINED] [UNDEFINED] [IF] [ELSE] [THEN] - -MARKER https://forth-standard.org/standard/core/MARKER -[DEFINED] https://forth-standard.org/standard/tools/BracketDEFINED -[UNDEFINED] https://forth-standard.org/standard/tools/BracketUNDEFINED -[IF] https://forth-standard.org/standard/tools/BracketIF -[ELSE] https://forth-standard.org/standard/tools/BracketELSE -[THEN] https://forth-standard.org/standard/tools/BracketTHEN - - -VOCABULARY ADD-ON ------------------ -DEFINITIONS ONLY PREVIOUS ALSO ASSEMBLER FORTH VOCABULARY - -DEFINITIONS https://forth-standard.org/standard/search/DEFINITIONS -ONLY https://forth-standard.org/standard/search/ONLY -PREVIOUS https://forth-standard.org/standard/search/PREVIOUS -ALSO https://forth-standard.org/standard/search/ALSO -ASSEMBLER assembler VOCABULARY -FORTH FORTH VOCABULARY -VOCABULARY creates a new VOCABULARY named word - - -NONAME ADD-ON -------------- -CODENNM IS DEFER :NONAME - -:NONAME https://forth-standard.org/standard/core/ColonNONAME -CODENNM assembly counterpart of :NONAME -DEFER https://forth-standard.org/standard/core/DEFER -IS https://forth-standard.org/standard/core/IS - - -SD_CARD_LOADER ADD-ON ---------------------- -LOAD" - -LOAD" LOAD" SD_TEST.4TH" loads source file SD_TEST.4TH from SD_Card and compile it. - -ACCEPT becomes a DEFERed word - - -SD_CARD_READ_WRITE ADD-ON -------------------------- -TERM2SD" SD_EMIT WRITE READ CLOSE DEL" WRITE" -READ" - -TERM2SD" TERM2SD" SD_TEST.4TH" copy input file to SD_CARD (use CopySourceFileToTarget_SD_Card.bat to do) -SD_EMIT sends output stream at the end of last opened as write file. -WRITE write sequentially BUFFER content to a sector -READ read sequentially a sector to BUFFER -CLOSE close last opened file. -DEL" DEL" SD_TEST.4TH" remove this file from SD_CARD. -WRITE" WRITE" TRUC" open or create TRUC file ready to write to the end of this file -READ" READ" TRUC" open TRUC and load its first sector in BUFFER - - - -BOOTLOADER ----------- -BOOT - -QUIT becomes a DEFERed word - - -; when ADD-ONs are compiled into the kernel, their respective MARKER word identified with braces {} does nothing. -; when ADD-ONs are downloaded, their respective MARKER word identified with braces {} removes all ADD-ONs words. - - -ANS_COMPLEMENT ADD-ON ---------------------- -VALUE TO SPACES SPACE BL PAD >IN -BASE STATE CONSTANT VARIABLE SOURCE RECURSE EVALUATE -EXECUTE >BODY .( ( DECIMAL HEX HERE -FILL MOVE +! [CHAR] CHAR CELL+ CELLS -CHAR+ CHARS ALIGN ALIGNED 2OVER 2SWAP 2DROP -2DUP 2! 2@ R@ ROT OVER */ -*/MOD MOD / /MOD * FM/MOD ABS -NEGATE SM/REM UM/MOD M* UM* 2/ 2* -MIN MAX RSHIFT LSHIFT INVERT 1- 1+ -S>D XOR OR AND LEAVE UNLOOP J -I +LOOP LOOP DO REPEAT WHILE AGAIN -UNTIL ELSE THEN IF > < U< -= 0< 0= C, C! C@ R> ->R NIP DROP SWAP DEPTH EXIT ?DUP -DUP - + DOES> BEGIN {CORE_COMP} - -VALUE https://forth-standard.org/standard/core/VALUE -TO https://forth-standard.org/standard/core/TO -BEGIN https://forth-standard.org/standard/core/BEGIN -DOES> https://forth-standard.org/standard/core/DOES -SPACES https://forth-standard.org/standard/core/SPACES -SPACE https://forth-standard.org/standard/core/SPACE -BL https://forth-standard.org/standard/core/BL -PAD https://forth-standard.org/standard/core/PAD ->IN https://forth-standard.org/standard/core/toIN -BASE https://forth-standard.org/standard/core/BASE -STATE https://forth-standard.org/standard/core/STATE -CONSTANT https://forth-standard.org/standard/core/CONSTANT -VARIABLE https://forth-standard.org/standard/core/VARIABLE -SOURCE https://forth-standard.org/standard/core/SOURCE -RECURSE https://forth-standard.org/standard/core/RECURSE -EVALUATE https://forth-standard.org/standard/core/EVALUATE -EXECUTE https://forth-standard.org/standard/core/EXECUTE ->BODY https://forth-standard.org/standard/core/toBODY -.( https://forth-standard.org/standard/core/Dotp -( https://forth-standard.org/standard/core/p -DECIMAL https://forth-standard.org/standard/core/DECIMAL -HEX https://forth-standard.org/standard/core/HEX -HERE https://forth-standard.org/standard/core/HERE -FILL https://forth-standard.org/standard/core/FILL -MOVE https://forth-standard.org/standard/core/MOVE -+! https://forth-standard.org/standard/core/PlusStore -[CHAR] https://forth-standard.org/standard/core/BracketCHAR -CHAR https://forth-standard.org/standard/core/CHAR -CELL+ https://forth-standard.org/standard/core/CELLPlus -CELLS https://forth-standard.org/standard/core/CELLS -CHAR+ https://forth-standard.org/standard/core/CHARPlus -CHARS https://forth-standard.org/standard/core/CHARS -ALIGN https://forth-standard.org/standard/core/ALIGN -ALIGNED https://forth-standard.org/standard/core/ALIGNED -2OVER https://forth-standard.org/standard/core/TwoOVER -2SWAP https://forth-standard.org/standard/core/TwoSWAP -2DROP https://forth-standard.org/standard/core/TwoDROP -2DUP https://forth-standard.org/standard/core/TwoDUP -2! https://forth-standard.org/standard/core/TwoStore -2@ https://forth-standard.org/standard/core/TwoFetch -R@ https://forth-standard.org/standard/core/RFetch -ROT https://forth-standard.org/standard/core/ROT -OVER https://forth-standard.org/standard/core/OVER -*/ https://forth-standard.org/standard/core/TimesDiv -*/MOD https://forth-standard.org/standard/core/TimesDivMOD -MOD https://forth-standard.org/standard/core/MOD -/ https://forth-standard.org/standard/core/Div -/MOD https://forth-standard.org/standard/core/DivMOD -* https://forth-standard.org/standard/core/Times -FM/MOD https://forth-standard.org/standard/core/FMDivMOD -ABS https://forth-standard.org/standard/core/ABS -NEGATE https://forth-standard.org/standard/core/NEGATE -SM/REM https://forth-standard.org/standard/core/SMDivREM -UM/MOD https://forth-standard.org/standard/core/UMDivMOD -M* https://forth-standard.org/standard/core/MTimes -UM* https://forth-standard.org/standard/core/UMTimes -2/ https://forth-standard.org/standard/core/TwoDiv -2* https://forth-standard.org/standard/core/TwoTimes -MIN https://forth-standard.org/standard/core/MIN -MAX https://forth-standard.org/standard/core/MAX -RSHIFT https://forth-standard.org/standard/core/RSHIFT -LSHIFT https://forth-standard.org/standard/core/LSHIFT -INVERT https://forth-standard.org/standard/core/INVERT -1- https://forth-standard.org/standard/core/OneMinus -1+ https://forth-standard.org/standard/core/OnePlus -S>D https://forth-standard.org/standard/core/StoD -XOR https://forth-standard.org/standard/core/XOR -OR https://forth-standard.org/standard/core/OR -AND https://forth-standard.org/standard/core/AND -LEAVE https://forth-standard.org/standard/core/LEAVE -UNLOOP https://forth-standard.org/standard/core/UNLOOP -J https://forth-standard.org/standard/core/J -I https://forth-standard.org/standard/core/I -+LOOP https://forth-standard.org/standard/core/PlusLOOP -LOOP https://forth-standard.org/standard/core/LOOP -DO https://forth-standard.org/standard/core/DO -REPEAT https://forth-standard.org/standard/core/REPEAT -WHILE https://forth-standard.org/standard/core/WHILE -AGAIN https://forth-standard.org/standard/core/AGAIN -UNTIL https://forth-standard.org/standard/core/UNTIL -THEN https://forth-standard.org/standard/core/THEN -ELSE https://forth-standard.org/standard/core/ELSE -IF https://forth-standard.org/standard/core/IF -> https://forth-standard.org/standard/core/more -< https://forth-standard.org/standard/core/less -U< https://forth-standard.org/standard/core/Uless -= https://forth-standard.org/standard/core/Equal -0< https://forth-standard.org/standard/core/Zeroless -0= https://forth-standard.org/standard/core/ZeroEqual -C, https://forth-standard.org/standard/core/CComma -C! https://forth-standard.org/standard/core/CStore -C@ https://forth-standard.org/standard/core/CFetch -R> https://forth-standard.org/standard/core/Rfrom ->R https://forth-standard.org/standard/core/toR -NIP https://forth-standard.org/standard/core/NIP -DROP https://forth-standard.org/standard/core/DROP -SWAP https://forth-standard.org/standard/core/SWAP -DEPTH https://forth-standard.org/standard/core/DEPTH -EXIT https://forth-standard.org/standard/core/EXIT -?DUP https://forth-standard.org/standard/core/qDUP -DUP https://forth-standard.org/standard/core/DUP -- https://forth-standard.org/standard/core/Minus -+ https://forth-standard.org/standard/core/Plus -{CORE_COMP} - - -DOUBLE word set ---------------- -D.R 2LITERAL 2VALUE 2CONSTANT 2VARIABLE M*/ DMIN -DMAX D2* D2/ DABS DNEGATE D- M+ -D+ DU< D< D= D0< D0= D>S -2ROT D. 2R> 2R@ 2>R {DOUBLE} - - -D.R https://forth-standard.org/standard/double/DDotR -2LITERAL https://forth-standard.org/standard/double/TwoLITERAL -2VALUE https://forth-standard.org/standard/double/TwoVALUE -2CONSTANT https://forth-standard.org/standard/double/TwoCONSTANT -2VARIABLE https://forth-standard.org/standard/double/TwoVARIABLE -M*/ https://forth-standard.org/standard/double/MTimesDiv -DMIN https://forth-standard.org/standard/double/DMIN -DMAX https://forth-standard.org/standard/double/DMAX -D2* https://forth-standard.org/standard/double/DTwoTimes -D2/ https://forth-standard.org/standard/double/DTwoDiv -DABS https://forth-standard.org/standard/double/DABS -DNEGATE https://forth-standard.org/standard/double/DNEGATE -D- https://forth-standard.org/standard/double/DMinus -M+ https://forth-standard.org/standard/double/MPlus -D+ https://forth-standard.org/standard/double/DPlus -DU< https://forth-standard.org/standard/double/DUless -D< https://forth-standard.org/standard/double/Dless -D= https://forth-standard.org/standard/double/DEqual -D0< https://forth-standard.org/standard/double/DZeroless -D0= https://forth-standard.org/standard/double/DZeroEqual -D>S https://forth-standard.org/standard/double/DtoS -2ROT https://forth-standard.org/standard/double/TwoROT -D. https://forth-standard.org/standard/double/Dd -2R> https://forth-standard.org/standard/core/TwoRfrom -2R@ https://forth-standard.org/standard/core/TwoRFetch -2>R https://forth-standard.org/standard/core/TwotoR -{DOUBLE} if you type {DOUBLE}, it and all subsequent words are removed - - -FIXPOINT ADD-ON ---------------- - -S>F F. F* F#S F/ F- F+ -HOLDS {FIXPOINT} - -S>F u/n -- Qlo Qhi convert u/n in a s15.16 value -F. display a s15.16 value -F* s15.16 multiplication -F#S Qlo Qhi u -- Qhi 0 - convert fractionnal part of a s15.16 value displaying u digits -F/ s15.16 division -F- s15.16 soustraction -F+ s15.16 addition -HOLDS https://forth-standard.org/standard/core/HOLDS -{FIXPOINT} do nothing if compiled in core, else it and all subsequent loaded words are removed - -UTILITY ADD-ON --------------- - -DUMP U.R WORDS ? .RS .S {TOOLS} - -DUMP https://forth-standard.org/standard/tools/DUMP -U.R u z -- display unsigned number u with size z -WORDS https://forth-standard.org/standard/tools/WORDS -? https://forth-standard.org/standard/tools/q -.RS displays return stack content -.S https://forth-standard.org/standard/tools/DotS -{TOOLS} do nothing if compiled in core. - - -SD_TOOLS ADD-ON ---------------- - -DIR FAT CLUSTER SECTOR {SD_TOOLS} - -DIR dump first sector of current directory -FAT dump first sector of FAT1 -CLUSTER .123 CLUSTER displays first sector of cluster 123 -SECTOR .123456789 SECTOR displays sector 123456789 -{SD_TOOLS} if you type {SD_TOOLS}, it and all subsequent words are removed - - diff --git a/FastForth_at_work.pdf b/FastForth_at_work.pdf deleted file mode 100644 index fc3f946ded5d5570870f27a6cf9416fea92ce8e7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1754741 zcmb5Vc|6qX8$YbmDMgX8WKTl&WXn1s2_f6qi7>XY@7q*D2xS?&$-b{+$uflO%UH)w z*2%t%!7#=%ol~9f@ArECcpiUoe?Fi4zV2(k-q(fW#gnJ}LIR>>9BtWcjcqk;FtUet z9^7%Vup^U}7JP2y2y(Z%BTQV;5`1dw;BMtA_|(DN-Rgury3at+SWUXzJSuVH;L0i9Jn59Eksj)@%6`sjA#Zp`KC!XV{MdFV)qpv=so@hxwzsNKp5mI>g4Smx!j)`9V#*I6*NKEL$ zBg*I$WB*F`mP_&E7OFX}EOk<~LvASGJ0_`*0%o6M=`^pB9z={?RKU1iF{Zjre~X7R zpsVj@1d~+DchkP0Rh^x`FGU*zQn*SZNXXbKSnBK;?)E?D*M0Pny)64?{mS9Q)tK_n zU7_z+bmbAt*U43QgKGcoaPNP8^MX3FhCwBr=&h}TR)poF>W@6khMqK|vrbAk>PEAb zXSI5gl6szOo2j|Ybxh|fUP0*BKD#xbV%$>}v);l1DpBu^UtjC;DC8txQ=Tp;cN9ol z<$(?y?m4T>xC!d7yH%s*uA;BL{I2`A#v#J6n{-1wqQu<}6Aga8+CKB`(U%}iHH5;3 zBUFo)4ds#Hj>sGd(`UWNSYImb#lRVQ|2pa6at=4%v_T%heY1t<{Vhb_o8=AjUX!=> zb&d)N$60?{UUkmS+jlmd@oQhRs7v?iyxz!O74fny_phU1&!O2iyorq|ETs(gp^MB% zM3D2NN6u{|N%wZdZWgs*Q{f^eIiy>b`S z_ONjO`L{CI9AqV^XKP7RS|N#t4+NiC*@A4`?+873^gvMF*4^!em8*gi*xAX^%F+GK zqu=^1_EW#f{$CVaP{GN;$yM9g{FRm96Dv>KS5{g|@?`(3_M5Y${?t|kz^>r4iaQg% z1zhPg6{%dN6+xW^dFj6CzIk~7YcFe0kgBKn0)~K$n72Mm0;T&{e>XkXU};teYGQY&RHG#M^E0sLJ-m^Y zlIKMJXX$Y$dM|riN?c=}_RrdD3gnVVhu)+D8)xe#-8 zlc}|APs@ZCf*2kD+vG9n;y)X=*WDbkHZz+~F!fbF);@Mw?)uaU(*FCb{!@z6-9KBs zrrZCAH2+Lf$QhRSZg*!Vs69MB=<;=jhnDYmm%2W&2g~H%nWC1v_36}!4$7Mc_bLHblvot>RJac$bQG=IKkDt~rSBU+Q!JYP{!Q7q*ucxoq8 zI{ly!tO0@V#>4cEkDUxz{9aCf`cPSD=oN($0W7wzhO!3gKhJP;b$tg2mZ71c5kwrs z?Bc$+1htZ8ywQ(PIKHz=%8{%xOMoUH!1ZbpPe9Z6*Fmz-29|ja}^Vz2FszDq=IQvLXWaeNeB(@wZ731(L8BSC; zkdgy7`VjbVT5OhLfRbh24Dhsu-CC6kCB%vMfi}5qzkr%Ag-ZgC4Vre}B*x+}kL@lH z!QCNfrTzT{q1gE*ZcnAIq8wSJF#XE<_^ybK(ABY2fRRWHfE(!N`~jOc6@udG_9Qrz z1doB_mTqr8np-Y0 z`M0|nX3c@Tz+&RnDh7zJ*syQX1yVQd@9j}7*;F`(ChGB)Un|wgRIdIObHvLPQc@9j zplT$Pu*ugWS7AGpv#O)%X>t8cN;Q6xufOInxbYS)iMby(rj#!!EhXs$re!S~OlaS$ zQO_GcPOR=oL^Z)>E#jXRy41$M+WhYQmfwVC`#HhkOpk+MLi}ntMC}vcm#n^oA6g-q z1t2J1#s2N9FzmL9J2IF5b;+jkoE8l_>gUC@Y7PRtJEj-<;Lu%hzy4-Rn)iZ z55nqW+H^{vu~bUM0E%X)I|bFaAp=@p>}xpna35+|gh$5o&xWVo>$<(*rA)_67K9v| zB(06sbiS+(j*WnUJ)BP6yI>do<-Ku%8ye}0`8o++fV1G>V;3S+lTWc5bW~JA@6)7x zw2I5wa(fnsZT9+uTG4C@A@46#>yuB7kLz8_q$z!}(44I&pq-H_RQ)tqB`o6}LWH;N z<+!A}K@EuMbL8lVf0bPuJUOXAtlY&8z7$v1W!+IKdKXyFt)Kl{vwucH}XhVV_An#?1HPd^KqBrYUwEX#c+~5j}yFsU|8BL zt?b4pz;q9+eGzFl8Moz9)}7vGRP7ol5Q=rGTcz7| zBb3L;jrEzVo;T)x*EJJ4Y;|<9rf40%>6E4 zNXD7s?OR@Bas>yUL-4{ByI>{%XmtJYR7)(EMii5T*73*KSayFgtAW<&rlzJ=y~XIC zS}rE!Nh{q)UHZ)en}raR5N_8b8>*g&ZcW>aUY0CnSr z)F*&_J|Y7+@MN#7=z33{0^!;(+EwV}2_LXX(}#v5-ro-N{bN7xf_}z=_X@}U#K7Q! zCi)uxfB^Qya;4&CHi3_{6S|PL^?D1R)#+qu16r$(jrTM>777#%L83V#8d)VB#TMfz zUh3NG;#I%3=u6M{Kk^ z-HyLKi5UrF{s61iNX;E#gIxZXM&}%L7$A!PKl%W@w*fQrUCSYc6z{H&Y!Oz5F_g{ZDG}yC3LDaKz@V0C%NWR zhQSW}>>j0rkRU9KhSK99q^6OZ0W~cd2T-Me<8_0!9&(7W2v=X41Tz=SIQgvuinvBf z2h=$P}zFBjH0SCuki0Dluz0M$F z*>yw6hqg#EqBmV5T{`LG$Co_U!NVHzIF(`nTPXZ_a$MnI&-@ukqneDD!yP;p@zEra zk6y3&#s+g&^N_xuAu6o3Vqg_{NIFQdip(9H=-{QLIW!9Bi*r-MyffrD6#>*usZ}3J z#d~(Ei=w#4WiPML8lr#=&S&tk^SBE*;eW|{U1ZY@Q=1XKr>7Z_JbO#7fq!UAKgBli zvXGE2ZGuROso?!UT7u4pG*&UKbgz{Unlhu6=^p#h8I`oahY#V>z}|+@s_P?*e(n1d z6aqJ)kyBH2`|8UE`6D>^%GiYerHm{bykcYUMenE{2UB$g!C>E2A-<3zIU+xCD*s7I zG9+v9W=!W}Rg$fjgktVMPm?nc_J8Eev9$q{qTOJFGv2ik@2sId`>)l7G=%%o5`24Dx(uRl`B6^}-L3zH6`${{{#o zFN#&n+1Kq@--t>pFuEhtEFV?8u;PX?EwaIE0#O%?2I~F!YV52h24FP3p1iZ3!GAIG zL?^|ku$id}L`;GkvtMk9O_~aqq(Sqh{0+f)!s9nuFV(@Mrj7fq&N1J zZB+q-t?X=vstx6?@S5?8j+Z}~I#H&Ps@TE4C+p=OUB|6f~&DhJ)vh#qom zO|1UAS3c#ifk?d=>GLNRg${;ud;)>ANFj0!*oCMQ{?Y$P?9Sre&0v=+DgNrcF`K#AIiul!{Cf z$52%H6Ud3H?y`=m?!j9}3f9tR{qn5mYOOU}&pH+kj7M%af~&T~=KtH1j?8Nn8E!OR z>mLl5PodsiYPOvnSelNq^lr166+8d$#kBZN45)o89D?6J5GP;B5ZMR)dH6c2bx9Nc z|GlK}IjQ;cEs47~i-s@44RZkg70ro{e(VzSZeR53+Vrm=L|hwO@R44_4)l-IUi$O# z=Qhm$ubM}Fz-~WWuo*8ZFwfzY&z|1Q?B1&CO5VrleYGviru?o!fClN?W`ke*GyHR) znn%-zurTU8E}TnqO*>U-G$-|dJxA52^m&Ju>PvI?W@x{Du~hM)r9t-}MB3-|mcHS3 z6-&0yi|cd!D)8)vj4;N|TZH)`9as=rJJV#u0n?yFmQR^o>u;0)9i~2i`ltHRL92?o zI}-yuLWvg#U*IKGV5RuncllFe=BpKC;RW~UK#jc5rRpoj=l5#}Wb%?vT@ny^72eb` zGMLqm0HcS^Ci{?U#ryTg^uJZ)^|bd-o)NE56-+S~2S{;~#_kQTgj2Y)HfByP0!!(>v2>g`nG1==DO zL4rtFNz}lA_P-{C`Fj~TCHY%EuCB6=+x$al($L_4j6tq>~3s3gT6(u@8zUyZv9#LNvg@ z{1-B1CFxd5QUr~UR&~@%NFb?`3p_Y&Uj|58a9s8-_Gml`KY5bhN1+us^-B*0oPU!~ zx(|Xo4-Z)ms}T6CS!m-8;`c$I0l_T;g$oXtk;M2gsMQj!awOjM`9k)Jt^{qi!R0}+ zt0nz@pup$$>&r2Br=j9q`;u1U;H)>6*_A5aJt;MNo#YIqL^)lcaLZ45g@XBG&L)-U z7Cs7(b(OL6%nAR*_)tsCPC*IY;H**X{F3u5KyFpJBHpiH^lQfn2rJh^h<9!|8%qWl zvBpo*0b!p1GW|7q;x9qYeptr0% z5T%oWxa3!KI+Zoj88v<&dg;>lx29B_!m`{P0-P&p4@I1<^~qkr2?z^<^_gbXq1lc5 zrU~nq?+5XAfsK}w@O5^(jh%u3ryp=3J(QnkKR^z3{%|SsAWnHBwjCSbiF*xt})tIwjAY$5c6)ARJ+6|drv8*YwI)krj zPW~tQm%l|Hx(~u)J(7J4h-}mEwMrfbSJ%612Y8qE!8r0NP$gJDQ25ff!Pv*$o)K(IdkkIk1WYz-HU<+`;FAJ0wC3{VJdt?~0=`@{8s>-&dWV zz*HhDomR{YH{)P0Dm$lqz}RAcjzeL0+c~vq_r+CN}V%Q$I5+X zPUf&xO>Qywv2VYEmAm^tY=Sd zR^!|@e1P}eGjMZZa&D>IfzTai|Cd`@=aZ>HBYDY>jr=nXjFZh$Fj!c%3?*=>SFC?^ z-y)#-*aBzH=!XN%Pe>CMcK2(L{ZPL?LzO1SX)dYMW?BvFtwu3FU=wu%{fWqi;#666 z3*&Th^pHh#wOkJuD!pt=y2s&;p;C@JrLoA?FSo=D`-iE;9ZsGr$o+2uKEXj1upaY8 z$a_bYje=EVR9;Q%o7IXepPrJyBx|!Of*uBF@id~BDzL`jej8P#t=1-L9kJAC@Y3MP z*LaUmt6ndDCCj2WlbIH9UYA1OnttEL4xA`!*x2~@Zir^)R=rM{&NXPx9y}g$HKlLG zF?F|{u9w1S6D--d8BsHfZ=*ANK9OjDGIU(0+@$0HUXRh(4L-O6Z;CXlB{*y~dLH%x zQlhnQDR5Z_*s%C-uwdMJ4)ZCs#417)46c1^>D83%TkNoBjK{y_kNzc^FR%X%UZVbP zcOa+~Ejp!1s)rziRPmm6u(7_0k0~x}JJt2qgjHLWLYWJ6lbr=1Kz=#% zPDE_Uo~R#J%B{ACJ90R%7Xza{b#?hvG&5iN~54f!S#@lm;9^A%ju4~`> z#&dekuRG|t3Rt(IX*s{83ZKhQe5&gE(p;f=Qm5$>U8UU?Xg@Egx(I`EbT`8vl|j>e zI?*u$G=ft+7?$NUeMV`Bt*rRIOkq%!ix3oH)6A5^&VRWStW!doBqI{lC-kobALlLq z13q%aNRaF<_l}Pi+I5YrUZ#|)I=~}CUO()4NA}BZN{bh zwb5gbE_+e5DWl3-gXk7@gEU{c9cHs15$p8ZvZ}G5y?KOhm}C-Cr^`rk<$DZLmXXy1 z)sCo9LfYLL78n^O6q`j|9QP2j!-HV_5)*;!ze>3uUH_&nhZEO6YwvjziW8+(FM`rE zON>&(n54w^pHCxC&t%UIwBa&yIyZ^U%}My==AQ$qE^1tA z9H*qL=gQ68L3IGO9r52SF&cR(vZ~+{Bb8pTa(}?l+P1!D`7{RL_W&Y5`kF!!A8g1S z+c9wI(j^=Ympg$YZrR%Gm!|<6ut-WuqUU4&ed(z;(^<1r2?$vnVa1k`>qoQ9Tw_so zL1{)sMS=1JLvr#uBcq0%_`sv_151_Oi=pcR=Y3_p-*;qU0A(bvDXi*-9@fO+D%vCH z1dYEqx4gZCK_g+}PIF9ReutX|4xA}}vevDy{dJCI<6QH#h2M9k8EWZ7bj5F5pivej zjiMs-i$A79LT<%h2c+B9zj6Y@ob)_>tg}xsAdT_LOC+cII)P&G0kq_@dOA9B@$tdG z$$#xvCoz6@mRUu&$Oz|QSZ82l{IKAr8Zk%BG$t;#zRqa3!PsNB;a{1uJy*7|*HN~O zgvpqwl8|h^;>C+H%)g;o5@Y=t`t`X3t6dno;Z0XY`wd3< z@zOKviE`ywt};`&_4Wa4sQ>Z6L6R_+M$&%w$0Mk~adm!i<5NAa`oe8it`yeyy&Ljf$&GwTWnTc zDA;o-M`>1V7%x1vL7%yev9Rm(!P?uAi&CWU%F5x9k^d^8FGEBGnlBE1b_qDY+ynGCkJeqj6=g>`ziH>u#to8S5Aypt1R?C#OVRP{zlz-cbXN*9F!j*dEZkIz=rt%slY?+xG$%vI9V z1y`;X_TL}w?3_}rcDJxA@K#)e0VzhC@^!JA2kwMTyjqoaOt9kznaKo2BjTp8sB{2% zLXAZ`*+}GrEjmxbI=d8{o3HOlcP!Wcipp;R=Q}4c@SNRSS)gD5}bychUltCs^aPxb_g^(*8X>2iyx z0q;*sLi1@6+yiy}rxREA(I}&@DeZc8N=f@5B05WSFX|c^0GGvY=(E#?6SEh;t+c#D z#>H{G1u#dzbT2S6^4i(8U-31vSftT2cG+vEqhxyYV@X4n{&1^SA;cfQtgT@}g!!Hv z3@T8rq$24U5_ENUWX=3Q&sXAikQ+q8O?=9*P{aD+7=V$}9kA_|t&0GpX1LBC1A16` zR3i?7t}e8u8aRmg>9aWVt%UB6#A_5C$S*jFO59RmP4=R@@GvA~_@e&*y zmws1-B(GEIxQ7C)zoh~0oxAC3`*=j&mZM9EFEK{=?tX7U_+lRhJIpqCH6JfV1XHpG z9%#xb7Yu%>DwKSXwH;MHYJs+!0hm^~R^c-NBP*03+kL!+QpSpB0f5A3mmb!E)Ng z$;iobVxjTz@la^Uf2MRsG$q*w7M*RvDI;Ws?NYXazB6nUPn&b zxW8T`<9qM}RWf}S&^+A3qd+h=z_!eFH1!U+GvgJw`eE4ID^rUaf_*T>a8gNOz2PtV zE*~kDkqje-5erEm1QZ89&WmSxt|(TFw{;>o?5q%x#P*^W4Yd4JRoGW0AgmY$RD{-b zeEA7L-jB!Q_xJZ*U0qj^FhP7G6zYjTb{YK*=MoLAmZM(p%x|tu+XLe{ngAS&(_^fG z`=D7_9(*rt*k;)6V)vT!K`VZEPdMC!)8`@MbafMex~z}PFrkUiKy9x&VSi62LNSA! z9}x?fux<~h*-sOTI5E@|xC%3g0VLQzd$_V?Rf|+|0)A@i^ewp>GYS!V+Aph;GJ6r8 z$h#r3iUbC^kCjzbRZK$s&`9|d4przV(W3P9(96q~AP~`U=}m`*o} zX5%L6k}C`Cgx;#FOH|l&4=>C|9-pK*b)25ed7Yn?5iqb$jWnK;LV=Rv9{wVR`n)|2 zMt8bq$tKJy(szU7QI%!1#XdJ@U-?O_6(6RP@Fj#%mQXQPMb>U!t{dPMoY zRo~9uJghE(hz%L_!&Ww6x+kNO_k6xP2*0i2g+QafEu0|5{7{eN7jMs7Lg!*5HGPuIot zA*SZ{z*%DQM9@YAFQWK)iuQn~ zFR2HtyB(>60vK72GibZC?@k`X$6sX5*R`0di+m$7IQ$mc3>>x}tqnnkfuqU&NY=wXUVMm*h9fPaIn5LEv=@(HHo= zaGPs;nbD_hprcjfKnQXLhymGN48?$4eb3l`mm(rcr?Jd__EL|izA1BK z8!!%JNHtsc&gaHAQx)o~NXO4OM-^P0k;!1`A)%$GM}^3-CvD6Fu$1Iv9v&W*ElndM zUZ#mwrbq0*JnZAV1%gd&uQ0oy&)PUw-YP&0zGBrJVsO>NXt*#Isk<{!Xqc3J%2&BC zw8F2!H!^!*^+OSY`Pu^#Muh91a^J zM%f3O>ahT$auzwGWn^%0@T#`#TboBi;!!I|ViH?XQNecjOj((V!okt;=^we$JtAhV zCZy-ir=Sg1JO@@5_BNDLPe!_Am2!l42d3jYek@FhZ`_EXR&Tim(9wGBMt3+qOT*2(vnmVJEJIt2#n*0pVkc|0}_lP zKd<26RRrN?$lyo7(aw3@#q(!mGNJF@6`P^qpracpMy;r_vojF0wD*hXKgK=d_(_J? z6G3(~wt99)+$!~bHQ?bSSid@t5jaPWmIgs~k3UwSk#lX>&z* z8Xmr0d~ae){Min~CXGHrMpZ{u^1bPKAw0-8G6{v zHv3M-2Ys2eEa^RdQd=cfo{m2pxqtBBml&lL{R;gTmXULH60C71Hd7v@&g@kfLY*t& zdYIw5Qx^slx&cVpM-#VgJZ?Qq8sQ4Z!GHG5pRaLlR)|AZ8+CX@3Py{GjegwGzJsoV zxliiKQOr_b!ze9^Y)JIVm|>Mnc60=ID=5ZUvN&_l!&C z_31N=E?@bFBw$Q_-p`G+T&3VC|0VZj; zsV56<`BWiWVVxAFerjtUDdk^f$qq;r$v~i&+CofXM5;wC{Ll&U zHTWZ-NV=5F53xt_Zzbc-(*=|2SzUW{on-TS6kfu-tL2^e$!wa0-EpSEVyF|{*y{Cs z8NlNScKm(fXbU=rg2Hr`2t#g+0Iz_mFK`XyHtONIxlQ@mXq({-LPhbY?*~)6X=_2N zPBhUkIGEqH=BRoaoTGS0`pJp?>1&_k4}F%H|Hb)#=zIit#r2Q4Fpx~N5QP9`n^X=0 zeMoz>o}!o)!q0%kW=?#Lwuh5mNh!~pH%THDZ)Wo!P^D*T?6D?n8si;4(bp0_$FbLz z%GKzSwPpGTtB6`-MJCtqlbfz%0#9Z@XGYo@V&qR!#$dp3H4{BKgFs>3r(AWht901` z57bk8z4MpXIX*RSUFd4FZZ`wp`4!e}K>r6*d`3Pdf4ERhfAMKRb^d%>QmDmTzB22b zSvTh_bB(!AEiJs@6{H=v6Qg}Z43@{I#Mhh*i=W(=F71W!n?3?z?ZA424_SkX1%tg*u;)Vvswn4^bq*(WshVdM z5e(h;OSzQEzo9yvPKBwwjl$?`Y-3$*_*f>C7d>LsiD5TSj_;VQ5|9O~AGro=(!#;n$ z^YEc-f3hgs)ZdpbF-yAV*VNS1)frTqfy?gb^sPBGu0}$xU9X<83OIw8NDmUt2Jc%U zxC6CHus$<72ilshh<+*&EtjQMng~Q>_Du3k+vyi>6O)uUKyA%?J(&3KQGu;%I5(xq zZ!gFV?oN;+KPXk15sYqU?qw?|o&Z`vHF!(^0-mDu-C8Yjst+$4 z?5z(q1;s%FQ_`LoRvHC*W$Wr}7M?rI|D-I1Qy)w$GXC{$|F;;3ocW0zHF$1K)w!Y5 zW&959%bn(BGggSk^A0&SHda%gknlsd5bSWaxl1*Fj}CiTU?Ck(Uppr+wSts)B0?OYOs)q%hGu4Fl9Q7? zPx2Uh zZv3SRN_b#DB{1>wnoqwJG_AJeB2LfrM)#DzbzklTYF5+Yi*HeFI&yGM+kE_DiSI2F zF&$-s|H~PY%nM70U+zLsYwpC9Op$`>vbKrI?8L-``nh}1tN%KcN&mq6-(IK^Jxwy_ zRQRCrO#q{ov@L7$KB#(x;niS`QyszplChJ7M#c!z$XjDZRGMy1)tqHR)ftcUIb(nV z!~48gp}J34PzPRO5Zc5eBgITi7@0n{DOBSd2G#!*(T=$FR~WdIj0k6dpO%BX*crS105`%?p?@h2(FKxRMM?q42 zWmid9T15!FO!0z=A)U>VG&&-jnK!0`H#$*FOm#w7b+udhW(pHLqIbi zJ%R&2T0{^GmX(Gxn%CVm-p@IXpL!>Jx)0(S2NZpHVotcnZ*|ME;^VyQO&TsGpZNMI zgVCLc)))O7&|ajY!SiG<6%1N*r)F&aig(Hn%4UbzlaZY|@Hyd3=1frFSH}1?_!7>o z0gdbd^DUW1z*cnQ;>Q81lv+PpcVm6ukVo9D?|7-PXA!sIl&I$eZPHQa*U>Fx2T!6Z z@RPnckS)JGoSh%_JhTY}1sJUk?I&~42ElnDsH*q+{19L>7K-7rFEEXo&a7KszQ2qF z4rCJZIZE}m$zI}!+uP8-u01n1fZtzbV7zfj}9U1fSc=@6~hQFw#fFxpg^br*IdCdy1br-8X#e^ z0*kC!*Habj-6Z3?Y&kSltitj|Ez67VT47gwu@Hkwe|4gODd(V3Tu z6vliHT~n~)FV6pFeuQv!l#2^Nllk0leE+8T|NL~S3UFJGWQzKB^Y%cny zrpqs$qS{zt))5D1o`mm9%p?Ga<8v0SGcf>r89#|XzKFzWWfEVv@p(bK5kGm+332qp z&q)T?0%19yhp+@5%}$##x^~0ojbG#3PKgCMGauv#R+2iQl5<&^mxd>emvd=VMl!~) zh-;7`w{%OZ4@Ib#hM@G_+twv!QUI!<88yy`Gh%rU5>)zAzj4uSq`nq+` zoF0YFI?HZ9oQ-nqZ>Sf!=gB{f!dQOO-AI@dT0U(yA>hZ;L?9^O`D8q?pBWw9W#LR5 z)G$c3=V#LSqTgRv<2rT;^TF7jP<$-^IESjBT6hC4Lp)Mf-r@S3MIxD>2pXw^dC74n zL3h>JjNpLXT=^XiNJtvv^Y+nZ9kRfiUM_AHbZ6=@PW)lnsy}L8Vf$;(H?q`|0KKZy zhWBDs3{ths|CW*mRK&cQI-PxoBrCf%8h4S`q8Nf+N7e{F~R$uAzl{h4}YDV`ydXW-jiB;f`hDZKiT8<>d@=Yv>(aq1Xni#ep(MO zNAIkSsS&{L(QO?x_;i0E<)kF`kHR96=oEu{VdO z|E$&tv3Ah0+EX7sVI&UU6Kj54D&Svy4D=stzI%fRAdCbu4>HZ?SdoJbou`RAGf5q2 z*iCY~0(`J$Y=WESQ8<`Da z-%P7~2u=Y_Cs|N%`>|gyyKl|6;fW#0_TIR87p$e%qZq{5eMH6BUMF?scREEvGS>~p zxkWcqOjj&F4d7!ob={gMVVJE$Q?ahGk}9Ke5OE zX?ofW6mX8)s#R(8`;k>3u$bAVT9zcd*u)A5m^cyJE()#bYpSy-S-5Y0YB!<%laQae z`Tt1(W?X@_%mkvTYMHRwC2(@zZekGIwP+6|xQ~}9upaNl0`R-tZMopSgl4ndGnp_q z$KoqHY*o}X9q&s|o=u6I`4aiFvfJnV_kUKuvs{DsIs9?Ti1O;b`bA`M+(`Y@Y_2jR zBJiSU>5i|!?l4%`F%fIhOvNfAvbS-1muoh)Vsn3LH{zXBaEZ4Xa!a^0I?-EuAhzhk`oTQwLy0?z$j#PRCiQ5l%5#b3YY1&%i*nmI8(8BPR83S);5nC*Wybm1ddX zfCk`Gs`LGl&-K}+hXDb$;Dv&F8L*|vNz{o;9cSCuhfz!)!Y29Z>c3@=#wwmnJ#Fvc zim7FO-diS6z*E9686WrMXtzSRHF1NlV`k=aS-*teVplqtRDG4#q!J_|@*~`pf@^!; zqH**XVMJ*OD=TzsAxT-saugVJOTDrX@4UwZNKV$&O7*qroXgHK04-yd)cGS%rrgl# z96NKB=a!~c72`7z9Vanv-BOfQvk@|TrvuBtAL}zxA97EI-MSlMVxu;tOtdrX7t>m2 zdH5yWcq9VN>>PbGr6}@qD+tCXbKgv2ngbY@#JHGb5*FUV8A>xBolY#M?S+m+xbYZ2 zFxFJn&JsA%Kk3d&p@69Z8rgZV#})Dcx`^d$kao1gRBW;~(5C+V)M7~EasXH55vy#v zm*q&tXzGFdxQ4x|wt{U3VJY;;N!IX%4!6%BBM(FGNc7eu?e?xnD3mAvlzj|iadf%rdem>y%R1+rs#eH-O{g(jPK=*XCdx86h_MdE)P2{$8*Z0;~^*We{+NF<|(-L5oCF7;F*Oef*FIWd%_ z6wM?N6BpguN#?tP`iDn&9EIYi0OzAgZIfAu)=I>x5F-xs_QKq-!Q(?eF?N4>!t<0|;LZlS& z)jHy+jY6It;(rEuM26rSmGcAvuHKl-=XEVc>NKG7FI(X{RU#WHcJ{o;G}ZZpa@VU6nuHez8pqvvP z(CK)oVp&;PQ7NC`eOm-wzsJe`a+VQ0u+NYgrsZ5e1!mV|%~&v9UbSYPV5xc;yk`2` z=wTaR;jyPd7~E}abjH|7*Vs@Ks5_hOWLJTzs>^81{c+s1+up((l;EI_ykERBPkn{G z>rq{R!dFT-`w>jWU~SpE_&!Q^J0eZgcJ)20QY4nS^SlNxX?24Ck=5`p4WYr$ABolF z(%8OcBy81FIC0BQV_cN%^c^TGx00{eRDQEmb3V@Vq08*>PVPHSYbI`686~%&?(j3-)w1a=Iwl|gv$8iEwVf;jWsX%Y zUYpGNuhcYE`dW2WSI?Nr#U&bwxBl|LVSU1c2y*83UYqgf(hR+EwL5_0{_{XVht|+b>`ofVepYLREdAyt2MeP& z)pg}&AL4y4oz6Vm&m#S1-71EjmSR+BpuOzrW<=OrTS+B(Nt!nfKqsWl*UfpYuG44= zaqT~Jd#8XIprfV*j*k6sSM!L^32wKd5fxQCu^!`V2NGtC%Su=iZeh@auVL1~4uB?c zVGSJ}pn)b=bVwftP1cs!`%Wl9Z(L+dyf#&Nwpzl~vCC5kEVhgg6{WFi&wVlle?+Mf zWrnak`S5xoODd|?)OIdu8J>6ZC;rl&>Cnr6_ znK#o}z2-)qB4nikcA)Pk<*t_4!V{0kjxw|5$A5IkPh_t82H=KXO}~XcPh+^@=6xzO zf_MaV<1s%ksQmC3m&S|SB1!1&8#imsj|f@;!B!JCPZJUX12w*tzA7-f<+VkIosUmX zuu2pn4k4eu0`;3!KX6b`nJa+fom2w@&3(Y}BS!@VP1~CTB}!gSQ*MVpawia^6xPrm zDGUb^d6eLYM3yi765}oJjJ!+}8rUt=`c4uRxWai=qQMhXtU|tEUtihtn1UQRvrq2# z9C2|@kW?1m2eKttrg}G}fp(-})8313Eq#S=+oawGEoRp4@D3#yA*4Jh_?iU-UE0>; zF}Zza()KP6`;*s3nydP+^Iz9pY3InX(pAY2{}se2iL#a6gkPwBW8!uuz=B;sm^EQu z+cKU&j!pvu$9q_v)RV`!EH)ad_x*l2o*3ByDOgR~z;{5THDte|M;IOMt~d}?mtSK6 z>H83zaUtav88!!aYaltZ5z~1D6DaJGO-S={-w1;*dJ}UT*7s@E_bnA?YUB~By`v%` zqB_egs{I39lJhTIrgj&MGny()VLo!qQpv95vH z_-HE*j%@wW28vpRQm?M0A$xi67u+wgwG&}NO*jlin=862+L~YRiiIWUX#oq0md^c6 z^>j6%W;#GE9UUDlef^<{AJ3~PjBvt~Ssy}OWC3~Qi$Bu4Uc4eWFuD0C>Y5n%EW9yU zcoP9huI5~rnA;p~B{NZo9Vou5v=ROTWiM{5D`&3k5j5}s77{}h(t%Tqr^(^qP+S}( zwo4h&of7>tqKZnl@VW0opDJ0csk#?#d8d`HT(OU27oo0xz-k`o;-jqg>Xn;`i3h4K z)`hJ}7@traEotykH?yd;%*nB^gpYQ$^9!M_E~B8SviMnQAHFp_JSOJhtN0I3ZC{zf zxVO1iWcbziL*NN%PKX`cC7Q8TJW6*wZk1*g9adzGQ7PoL^XONj(QPL^DmAM<4qdaa zxwj*$ZTR)5Rp(RC_*gh^rmC8ruWa+zMU`Msab;swm5y(YTI4{2s!i!&eD0>cn2f*L zw~*%nnk9x(IaI(gBW800Wsg@1vCe`6%Q;SDDI)gmnblNW``VbIYa^{R5cM#jOtT&r0=w@#Ki%r6LiStX=(2lCp(rp6!yxdB&86YTS7{L*SfpuHg0CMa4{zP z;*eZKQwkHcmkoL?2JdPTkTvk)QxI#(;$jR+TZH_)tgg7?#R^G-t$W5%` zWa!OIF65;Dav#w?;sQAXk5E4}FDR+60_$yL0=37I6xOIlfbFbdQ%zig=8i892tU}{ zBk^CZ%-2-?xF&2(oE+Atn)Q8yMxtqGg|mE+I|h?ChEriB=aE{3o<&7CeVo{2gN%QjT|C?+fh)17UXoi{$-N9Qvw3@ksX z%NGX;HyBe~WjFpvm|XZ9CNhrT^59=ax=I=xZ+?~5zc+CxokX#MY>!tAtraju6qFF$ zz+i)uh4M>9)(rOCWwT8y?k0-NXk>F=_*@0I<<@#|Q&X&e0H`$lx*89!5EIZ?*WbGc zHW*z&{8HVZV|6zeZcTrZxW3U~y>%FyM;z-u5zg~;GzE+~oiP9a&AQ}t9dy)>;KoQG z!8k=bz0POrZrcOS{=}v`0ivQm#3`JX5*i6ZUU|~1z?9E_J=EZx5>;zeqcevo}EhSW;HTmeD`g_ z9(f2~eD#(xo>o_id4DXOA34$JyC41$>lZz`Ry6iknYH=5?(V%9s)1CxD)Alfj7P1T z2Qnd4oZmu93`Qhd>E8_5Q_xZat#Wq^=%f$xD%wJ#nS|C8y5VR?>AD?vbv2*;!xj6* z=UA9MQa5d`a?UC0LDH=}HKTHur9x4v5FUCiGL7*#2F4v420ez-#G~RHMlCI_ zzBz7PDQWLh|wEb>}m;=iHfE#`I( zY`gO69hHD^)B}q#LMuMJukRui+fpFQQHir)Ak&Iez)Yb@N>uK8Vbs=@D+bMjf_x5Z zeMuQDDN)uU;-gSjsd|roe8np+jl}O8Qh~!&wr|2FLy;Ra`{>on0l12#t85*6e5qn? zOQrDk0U%igaej@f$K&gR=r}?_p~J_+??=xnz2w0#LY?2J2K! zV9fl9ZeVXh8MS)F(sRwGZU5Q2cRy$_Ah&8ivw2-P#%RkQMs^1@K1yEq`cmiv?!?+l ziEpIrYp~AH3I()4m*KW!^-oP4UB5u^Cttfp&o034X0}ph6U&EdkcQgJkz~)MlTv2; z#&xT9UdV4QOH4*vq7oHm@n89jgIv_1f=Ifkl$^Q>iZynI|{{4>|*K434ARr;A#Au|Osg#l;F`5fV zcQXX0(kJ2>aL(bpmExWS;kq0y(`luN9huNYZiYl*xWNgmEro$&6$jV2Xw1qQ_dT7%Y zq+e%-6dOLgkK}#IX4(4V-p>e{bEohLH;MYZrV{b(wLIaLXRC<&C3fa2%XKNusSz~A z84sNIbWIbHmHa=DJ#R&M;kAxNTV?i5mhB2hqp1b^Tsb;7=oD&RJY3iaotO6~x(wF0 zljku-kQpD(jN^M-uiaxdWJ11uXgc3U^*)}YTu{(!m()b+GQUg{)NfE>YBxQI(`(26 zP&!snHM(DCYiFjR36*{Qvtavu08P=J3C*}fY9RrOPCp(dRKA85BnEYK7*x@O$-Csf z-{_?uigCKFC*#{kSb6f1o?@vw_g&KHGL2=X^aG?H@|VH**%1+Gc_YMWI^Nj#Y%SVj zb5#{C=G)ho`}1QunWJhqPoemef-a5WH}Q#879NK`nr~d?w=+Pve>Hh-KT=X8D15Ij z?=Yd*x5VPBZ!W!=&VYWoShE+N$c*L6ESA@B%M)N0aUQ5E{SKVS#-6u_X~C1jHUQ*dBAs79w_hGmVKnUs3;eY*ch+Y@P4PJLnbO0BE!Kz&5cgDif)^XEuc>j9 zKur{I+(5Wt5i<>*>IyxzMU&xv^i~6V>0(|lPV*`?&dI)gTUj6YW=|3xoAFe@`=fJs z=%dtpJGvmvR|i%LSmgSYh&}0T(pwP|_c{8!ybpW6REDTA@w%1|h3j5I^X3q4t05hM zigd*G(3uA)zD5>BF`Jo*!@yAQg>PT^H(5cdoPDF(+cB9u48mUi-uB)j9Vw+B?)B!W zr7=~qJ<0j?c_x|KVhj9`;y!h`jJJ`Bik4R2k5Te6m(928+iJQrWzMUJRt5AS$-$ia zW1_CH%V@WzWJ@v`ed9mfX&;WJL><)B_+-)(q0c?N&Dz#`K22uy`Av;QZM)!h>2w1Y zYzhvyZy(cG$w)~_{4-j2o%SY)w4Uy7?T#;$ZtBG8?Nq1an60^nQsuKYWf=nY5!2=7 zF}c&s*mOxpi)Izq_V8`}>zXtg5EgyNBq6||$lwM@G{ z5K!M$VorVK1##;+{ia%%&##GUwOLzYgJ0uriVd^kh0vH6;VG=F+*l{^X&%ABo%S~Q>Tn;M{#R)v)h zuuqM&XTnIG z4DU9-__ei@AmDj;I#xNha2r&vzp;^~#t>~#Y2SA^Zv^d(I8?1GFK4!UdXX2!*!ZlE z8>Tj{p#_<+*0`L|CD-qRa}7W;=9(O{otnd=H1rG^Yen*<{BUUng4blL?0XRi>sOL> zHo0@R;QU;k?T@&IM77q@Z4O3{o{fRTi0&>W@t0x#9y)qHTL(Az$@f7x1B`5s5Eeqs zQUWK~H6N_KDpOG0t_|-yonIHc93?_nK4#^lbnDI@ zZKI`|&O)tabVPn1wnEPrYh-FbG}JXIk@OIfv7X?I5Aa&Pr6`KgP6CCrac2^H)p4=_ zRjM#K>M#|#V{MkV-y}LJJeojFf5-XTyR2}MEHP2*++Q^x>6HN<8YHlU{X6eundt`0 zWo|5a>X}(<;;N2?!|hCQuE*BHNw|BtN9!C05I$NWZrmblusi6iL*LKS*UWi-4IUtp zOS3En<+B~ovb;lP*mqWwfb(f|-Je_ilopp6I}AGKoA{-lBbyBIv$Q)cnz&lHw0MuX zPb{|7vb#E`gGV(~;_Vlwk#)4=1UbcN?|1Do8@yHe$`L$B`n~8tMve8@M*Dju^ljXf z;TwZGF4vBCFx0(G!NVZm@U$&J2gT}UQFs)1PWLUS8{SJ|r|hNJpF&f^-f+b85#(v% zXs}B2-hF9b0GpSi3#sMv9Q&5a?9U)P=EZP1C15kzr!9$$N7HQd9Lu58XsmsN7rJNk zrjmHVRHMbSz7|f>NWMSlGf7qn?d#$$8cfcGFx}P{bHOhP*T>P*2caTC6l1&>jt6Nq zvXaBN1J{A&ZL%3Ul*`6y#&A2RZxbxKagXY&Y!d8zY5G?{a2#DrR$fK?6sGc#Kd+<{ zEM;L&Ra~!SL9)7tAY*N1J1f2*|C4^m3uVkIb zGe?Kz;G#N0nk9}CvEan(sT; zQA=`dHK<53%j>Bm-|oolRv>Gy8JQwmvbeO)Z>Q(Yd={bhlIyZJW846otd!@;l`&mx z!MkqhX@ncqmNmKDHsG5jcFgU5c64fTKK~3kC!WnZ4V)d{CoM>sJn9wQ-9A{RaU_9D z$AXoiCPbAT{c8^TGn{PUpy{`)<7Tgm&7RvLuXfY1v*qe+Fk+Q>4JUQ^kE^Y}Xm0EU z;@?ef1`et6#ov4F@}j&QI!ZTAuh?5yo>A(Q*)U3gVtwXP3n6mt8C|`7HpO=h^=H1@ zB`l+F2y4p&AvcM^8hwR0a?id|NShpo{rtgXHE2u1ujqSIL2gwpaqVZ<=Unro_6+u( zqS$40u>bM4alP~6uU&tlMG@NDWNv@SR}pqOT$G4XU_f(8rZLddiTTV; zW3IJPOH%$Wu9@1z@2u~PFuD zGZn*M2~>rcip=b<2U2h|2X9;R7f~!Q-o65HN=hLQg14rU6!3KLqaydF==|p!+=ic& zz_L(14+PRVjUX!{@0<(;`xn1~WA>&fsxDJXHlA;7-6$kHWmd;fjfrfg-*Io3WVSrJ zal>AX+mW3|O`^eNVi|$DSOLKYgU{%f{QUe0(6b@+IgCk#MIhP004GnbetIU%000C0vHj@KbIv z4n~PJHZuvTP`%>b_MmkU#I5a&q>j4qoCQhI;&etok;XTeA}2@3@4VxW9@O(%Zv`J7 z66lZwaa38&+TP$JenF7KxSs&3^k=DW-RopmUxU-^g<;I@fP`_10i2#jV%Uq|1ty5; zoEENZN;)2T!!?*`ob-_(%tYC5zQ_j(fZp2#zbJ5_TenJc;1OIS1n$%;93Py|Z}2A0)1( zg0v>(tk*ir2zs+IH!8U?FR{IFRh&KD^He`ny7PA;k_9$^DCwE2WES!rIQ5Xk_4IKC zh2z~$d-x-AVyN>V-6w#*xnpHD9?mhRenMhQPhp;rQgN|d+cTN4JieDG)1slYlD3^^ zd|6wdVAAj&VmRF(FR8W+(Ww+sTk0^ouzG)hB@_+C5B9PZ-3gO&A4<7`fl%kkt4vn# zKP9{a4ia!M^UNOk7(cWdr#$Vww!{b$dZ4ws6_z2*C*+&X&yZ9wzzL>8PJ3zZ1qV1V z7jddZWR%-1ot4HP$qTP{E@EyFrNA4`#g z{0*f5rbWZR{l}n{JRR2?0YJVquF8qz*4@d{Ct{YeZFQsmr~zHtA5UNdV9i+SC9unA zTIIR=L(2K!jiJM}^>p*G;4EwQqSxvZbuxRMwXq=ssif)?Y%@!JjqE?fQGAxfmS6W} z#SHVj`E1Jz1h7GEZ#ORSFyBWnJsxr^@<%wbJU3im)myS!2JTU{d_sVR# zV%>n$!bSRitIt+Z#f(Pr5gdmewdgEL<#$?LmgiCtMDg=lI!z8D2OdoQE25{p(+v-~ z*ffS?5Xp`PO$~zFSB2e-fFds z?wLmZmB!L*_-H^)_-*8K=02QN<5tUxVq*8PwH}AVi!>>NiiBvzZNsb{xcp85>P4Jh zk2X`JgcZ(eY7<_$f-c^K%VMMNO(tlh@N9Pa0i-hoOy)g{`&mZ{;N~9XdTghHH|;#A zXca%@7n@L0)Kou1)_fgvr%b0$qqno&Oxxt50y29Hx6{e#DIcY3n`FDO!K!MBwKa8z z%^kFEtvU{~KE@_&hcf_C&HsFo1NZ3x4x6X%w@@NY-;y6~RLxw^j;hVBT9#WJYS-Az z)Vq|D6p;{kiu_trB@I|p(sXt>SgJ?==@Y?=<{QnZ@~*tHxrc+1rcv(X8CJYZgI?sF z$b(UdOmHD^C)3l^`ui!En-;g9VO3vfUO-CJrcGva2S*l{AH4dGMb~AdZK>Mj;cu2q zHX-WDrnkPeiyUCHzqQf>845$jcwZ5u+8J3Wze80VxVi*pEZOSp?HN3=U?^&i8T$gi z*1uu7cHmw+)pEgn4a+xE=cq7F1h{{Z7h5r@GGG?x#p$j+)iBnxxWCQ8sx}}mM?HSd zcU~KKDNufCL1~k{)p7%^p#P~w5n}gr?4(I;@92@}YH~MNzb_T(61P@ZZjczdBkf zFjK*7F}-K;pV*v&z%bYoSPp3VWZ=azIxQP@Y%kYKZ=O79q!#NH_>>QY*=q+jXkCEpGJl=W^cJ!)bhoF!QG4Y$5FY^u*rx4_)Ne_K>VS$^qV5AQJFYL{q5IRlI|B*B<IXzI_t1UR?)mwIA^WIPa|_kLy^@DL{qS^6;LFjFyAGNpm{_ zb;w!J)~oK`-T}&$)sFC318k_qc`7mSa@_QGx&Lk|W-vo_8*G`;TnFE-s|^ee}}=e7>kI)(NOVgk`! zaBcD0zx0cB0_1r}GJ&c_Vo@$rdXLawDYjQ@)Le@aBPTx+#4#HKw-VhvJ`wbk?@`97 zWO4*mVL!Tyz<3=?Y>PPhXJPMO}+FS;g_1lj^hSjJs>vY0cbbFL`R68D2wR2bh znb*$^iw^%uBvIj4Ir-8m51DW#r~mGLz(nGxM-aZ-r9Md=UN7Za@Rjt{a>sZg*Xlr~ zjL(8kFA%kqmx;M~X)TYqL_mT|BGo7TpH^p!BP<Bc7`J!}p)ST(PkwFDxa?i!#R*Nfo!yxPW>hWUK2)xu3AVUwSZIe#^^I z(zoQ-vzLHFp=zYP+SFWYw~Ee0dEzFeX*sav+&C*g)tnubv#KvCRhof{K}A9tPhX44 zn>QNAfg#~h7<=6^_Z~v&ugch+@2Dq{rM!~Tru~1z008dELSFpj50u8Z;ad~^gfctW zUW0su4$rX(r~nmfVweaMv2pABHmH0NKoEV+=~}UZ?)L$3tGtE1_6Qv%(m51f_l1i# zbiY74L}%dE9Mn}ky1-dMR?|qsa(Yo1$###4=7F1342u6S-p$+m+iod;6IZf>3Wrdm z<6G}52NWj`5wx4tyWdQNuQ0xM;qkQE7y+d;wmz4UicB79(OW; z0oTJId{a3>lah=ZUf~Vhdny|gyB1Ye2s!JA3;Fu2?G!ChRjS?-PYwGTOH^hp*s42T%fQXuU)0*|MRa%4*;7^Oy{x!*3TUK~B2*{TJv*cw( zEb=TNVS!bN)vw?0C$I1!8XD@kd-pDCr<;+nCa&A1aib>dyepRr7kd`38_=MS>@LvF zel))me17sX>za}x@&jZuSvoCTX`4qr>sgCG7F!K20{uy=jy2OYlgh+>7mDzbEnSSW{y{M*6!z51M_1U{_sn+Cp z%Rb%vG}X38!CkdarZgjvc1k~#qwNhSDmYe~zY0iK&v>x6dCj_;eqSIF$zM&*&)b<~ z5Eu16FEDF;lkR?Yz#Jlaljra#vk#OiBPzC|wNKlsE%cCBPn_AGu6bn^LG;lWqxjNsS&Dlzu7DUbl>P%M@I_8ks!6| zu>t*Z^;5_6U%Dm}>>0MZ3vcFv1OxqFV%u`FxKxE1Wb8a%D*aryU09P?0EjjBjNdg3 z*&ubC9-su?)lSf!vqTx3*i)Un6Thgc(Wz_L*eWJh#tw+gM9>liA&{)2Zc^Yv4=F3b6Q`(@TFw_1>NzDF_GZry1r`qS&P!%1*R6k)Y>Y>L z_*`?Z{v?@>=<{wkDi1gqa1~3MSV6r%JD;w% z&>77Ry4}VRa>&{M654VGgsZVhXgkd}Z;kbbN7y5CG%&iF`dZef2fhHkOJ4r< zYdz>kZ_lNa-okc%(TyLrO1QfY5lSRn?)MhokVMKl*o=vej%X!3xMQ^c`T!tHa$B~J z=$giG{f``|okaE8vhqvKmv0J~@jk2j3c3acHgu-`{x8DZ13g9)S8lK-_PnP{Pq*cY zn6i}hrrWKK%WTTWua|7$~43jbYUT!JSfV!WBNA3Pk4(>ia97y~M$KQII{VwCbn56rMGa^Sypr`etGHJvXQf81d~# zwhre1XIXw1r9O0!lyCA5_r+$_lUwm7BwP1@aGd!`how?t(@+GPFRFN@Fq4 z8t)~pv&#Y$^ZK!jdmz6WG^M z@-`L@iCcsAj=zMpsA!TQ$(S{LeRrU6N^9;d7a@_~a1M{dlJxdQDEHorf1~NtFw+7y z$(45ygc+wmyS0CB!4F(dU*&7Gb~?WwHo4e` zyeTVtt#!;vB0;+t;ZW}PZw0lxPZu1})mC+R?X36>67z{?GNJo;?cIBB9gb>6qDn{Z zK;C}F8&o)D`NxU&r(;QDoo@)+0sR#011Q)Vf4&DMlix}4f)$`{*Oi6_WNN{Cj0%Zv zg}2hLp9w9TkWree&ezK(70i4`4pRMT6#(MA3K%oYWt`*yWF+!ca*4t5c)@P9Z<+|y3nlqlo-s8^ zIM}Y1M&}7E*wdUHQ$gh(M7PY#u zttGOFoUZ?#`5<8U2Ud#iX{^8A^=ajD6lV1QJ!E|txc~XM3*IdyLL)fq*#lnzmB)eO zxj%VAi7MqLwBr->2UgaiJU)I76SeW6>Q4Kp2-B9!3E0{@$Jl~Tf9kTDZ~R;M#@n0N z_`wYd4_8C}Rp;g`gK2zrxI2gXuS)33bl30txU7Llqk_irhJlK|>aL5M8k#s{w>JLz z0lOrQ{vImuYhK}ZAtTP+a!YADab;x^;zMI7Tl}|x^)D3c^3H!Bb7uZ6kp`6z^kh}H z@}IZ0(COt4s3TsSWB>ce2l_ukv8iQTPzl`iJ?e||6S9912H-QI{|cq$3z|a?+*fbT z^PHXRf*Jq&~8@%Q$6A6c^jFhz5FF^q;Oj?6x()?%?SF7z)C zA80V;b|h2IC?ARs!oqeyb$!Lmf0S+kF}TeC$>D}eO&Dv4TiPI9c-++z;xBy8ZUfc< zg(2$MlA->}Bk5~T)yb5ZP5Y{GDd%EBtBk&<(sI?V5H<|O(USe~ou#ZDDIULC7ub@g z=%9yO^1~@Z<|$^7({MW4zi`=b=TKR!%b1l0y2sJC&E)DR%`B$&;bu z6k4_}qVr4m2HWEU;*T;eenElPf4UkdTKPPzP2I=Tr$(a1J|jIjQ`yoDi`ZdG4(zRCNi zeM++dRN{Zy!opX}OuPj*iF`c-X~`yCiB$UNV(0eKKMDsHuI2+^`#WN@Fv2In8+S;9Zwd;6Ep?s zJHND_#?kwWybaBJcp}v{d=&r9GSudM)YOTy^}l?cD_5qwhyT|)hWAxWCfitmr-Z-% z(SnHVhuQAg62>z=Noy>MK~teJOI;9m62#y=wn-<$E56~F>nL^i{IY)Q z?5Ejy!%&9_sUISD znN>|6^?s`de)FI$dPyevV9||l|2DdcX>cy;ecgWJd5}5&c0(jIQ5NsUbLqL{Rtv5sdEgr-c7$f#+16p)a5uHh&Fn#-03p zeYAQPPyL!Timb-_#RfY7F;$;T*H&>|fqc^R$jy?w&Z>wCd(673vL z11;OR+;3-G9i7Z!i7k2>g?AI?6HtF5(Z3naSMAmZalXCt{Pof82%Z$s_TQ5Ajd3uN z`yDq*R6|VU+=VZj{-Fd7p#a6WW9%Y2q&9>MU!uAotqj=5#=8(_(U76lwC-B%eL(@A$*1)qh{fah8zGrQqd&Z(R1**S)e z7OW_RH(B6h+#>e!A)nRbOM$0Ap)`?;>{JM>;fG)U^X9BQ2C9)Yh+B1O=(kz^ZC4tC z0Pz?mahZFuBMP^$9u50xIIOaFKa$BRc=r|OOJL{=hSAJnno3N#ZHwri?H@*1@i=ee z9m%A*pyU?iFE^DAuuW2+bMJ8!ax%SxP@A$Tud?vvJw46yrkFxo>*a$pdb5crTEd+! zFQ}4g2`KG#MPl{(G~V4`azP{d3lE*aU^2*A0EEq{Z3sSn+VVmPkL*7~w`t%^YGhqT z&*;*X%h7iPm=zBScrw$!;8x6Vs#8 z4Lz6yaKtW?%Dnp-t?{AV58`0EuasvaY>zeCcnRMhEGynMdOFa?WvCC!5k)ZzOrAEq zipXgrK=Z%hwER`yi4SrNWZ&dG;=o{1z$QIzVgV#R)98uv>v)`nZw%Ysdr-{Yu(hAj zAKmv4C;KWyDd(Eguf3FT6T!8dt4?@h^m2^Yn$aOSz!LLZX?{h zrF$9sGeKrc^sJAF(VLcS&TvuvtbRaR#y5692CB9b>n;=O^%T8_+`*LVi7 z+Dmu=M%jjs#v@PnwXFC@dlpu2H!6 z;?!lco-a#{|K`l}iMdw4Wkg|1{*!oPjFn@=$-aM3{ zo6XGuxCCrUjtF{(5Z>oyiFRTsXTZzH*$sEXs=U9B(&tT>I(Vpb^OopgjWjGGRF6Iv&kpgNtGK>V&;BD$}v8Xv|7{Z%(gC zBq;9SeX>TW47H$vnL%QPX16rh$ZX=@_03T>=Djs&O+7=$Tbu*8<=kQmx3<)Q^Q;pc z-fp@nWcA~}dMa1ELvI4bG$<$m)#`>jIP&q6l?9Z7RP~@xm)8ZQx0wQ&f-+km*n@*0 z%a=-v?CQfHU zGgRC*DhneOgVi6-lZLVC+Zsojkzp6|Xm0s`)4I3x_$DULUxr0#d6M}=*~fqEp&b}O zTxtpf+%`vzA0=PIqQ!4`M- zlFh8f1$|k7VN7iyo3%*0`A1c6{)yuNfY{?#0OkiUB_7(^rW!8t78Z$-rJAQo){liK z=}3TDZO`C*CjQ^9afC3tKNm-pGZ`qPF;bOpl@;N&4>>sqNsoNLv%FU;dFd@`6|D1v z)(cB{v_fq6{~Ombe|?qQLX>x%n@8x0NYjhAAN5@NM3p=2jmV6x{W6Dc@nH+=U)uCh zV+BUP)F>3tDS(>-xmX;yR~5JLq@=Cq54nu$qZU(mN|cp~x?BXwD$`ey?${rX53+e@ zPSq|H;_6KLtx(1S;F(CATjRGV{q5Lvd~?bFW8+RQ{3dCBey~3n8f%O|*w`0Qi(mcKn!!i;F?neYiwlaiCVyYX17TXmEy|9&w6?AviTUGSYv|7jLi%x3QaNmUck=j_uBARg7Wuy9a~GBpprQV0C}P&(b1FEu@H zI{T5NEDOfZE##?v22TN1$ACY&_nbJLylF1Qu2*$N!sk!=*r&Vr`kxJZW$#vXF>D8a zstCmg)lE)rqopW2_~v``OTXwL5Cug=!V832d4xKnj4ux=Y_sdTMwF^57EM!w_Xzx7 z9NYche;_;_6qTFmBOyhw_-MV&|ML`G`GRu=XzvI_$J)`EtC7*_a<^pYvBz#xEW6wB z*4V8y$O}M;(FFELxdLvD^}uAtMDrpFs7QS;3d?{xvwwXG@5ivF*trSO$ga*BzjiJ- z!g-VZzX_6Rm&Us#cY>$NE}en121pmg8=EwE?`vcOI`Rz42{I1)NMjQtJ&s_sqRhFy zpoVKQZzrO@WTW}&R~IO>*7={sCYG<1%V^TQL*~EddA0z}*an09)3QWHS+6)0<$o)& z1qcA)(>^kV?$Qc17?n0Oyg(ps-Ibaso{ClGolr@TaWO+0&wax%;rCj3!@ zNV(!t8yPa?_3EFg6S*L{r7+@J7;;YTFl`T|A{Q^^@?SfR=>Lsl4t%D8z|c@rB_}6C zbZE5_lEyZU5`la>pgkPc%M0)pH-BbHt9$JF*E!8i#)Arj5K7ATB67L7f_@JIe!12; zkOjuRYF!-@n_Ry#`Fjfid-RFNBB54ta5vPEb)z*%=8x?X%s{@9?=EdFW|QPj#9cg6 z1M1=uWo!Zo-69dwP2QXE6L?{(K-4+$*=@ ztx3$t12vXX4FZc#-VF3|@p_dh1|#0nxIbu?O%pnOZl?0*KUTXyE}{_b5=N#P8n10^ zZg642y?00okIup;kT{>iuIP`EzoG}ev@5sv|;9(6HUq*txCpJjroZ=Up+O6bFTmy&= zChyZ{iJmJENyuD-%cw>hPsE$$PdM!jey!6@?9LdUlNCf$vuUF2=|> z`k!u(+x^7H;+Pe}fLz4BZxd9p*H9d$vPgow8QZ4)Hd7IfM89Y^EX*pS#xu97vU=k7V`2`s;ap}A~e}BZYoD{eJGcz zzu%(0J@4;4S)jeAngop4r<`S^bCz1Wq49!v_mPnuaXMnDo6J-J0vi@tiB4l(^ z)14ac9%xX+$c-OU-f$E0$thFii+&4`u*n6z#T^AsaNw|A`VMDy zs+=FR54K=O)7g;K*^szK|GJ9s2ZxA!|2Jhnvwr7`y0x1?u{d13;qtNKncnogj)OV1 zANt~!s2S%VT~@}D@9sAzmWHr3`KCa>4)F($o5tBsGOkA`P*9PpK0b?gK|f~1>8oMn z8=>vz6itI>;4-<7zGcA1k<1n_u8>NPk$#?_oY0>+%}I-%gI>#BBA0>niQ~1UQeOFI z+lKuJbq!T>K^kQ|Nza1!)-*m_<&jJEor|Ghb*3N2nIFhtmnE`oj#c>nU6kjN|6}~G zl&M#3jT>ldYik)AvT5i86}CffE9@s~d->2!r;FLS%DqQtL)lMl=ojuUG#5*r+|D%A z#Umesdhoo`7ok_ZBgP1L7gD%pn3=cuj)^zbzN{SDZ45-GI?_e%E;b0t(3NSmGt?B< z@=b!wHnl?!D2zeV$!ny>_vqVhFNk*d7gf+&+T(73(3-Uavas2##h-@gqmS}2E{?u& z*Oy`B_vTCaKUh;D4n`N1jQbjrG~YyYoq0wJG1nAsh7$YX$$JMg2GG9U18B@anpG^& z9wtN96q_%FHW!ojpCS_UI<4S8zwR)JHO{qY5bm3&r-x>-_yk#haUq4VN%R#Q{bNqg z16*&RNp8;Dc3W7=tYra!3LREI*^G+xPFSN+!_4uc;qb>ksp?OT1;f{F#bEV#k9@DI zZ~a4*ZsFa*-FEaOn>$gCydcEh^o?XsSo6qoSTH_y<0PiqXa6V3_5tFmPUN;nz=ZR1 zb5{%wTQ-`a8ZcKdf{t;Z3k=W;_px04rQ(-cTcYnns=g)TB-hM3;Yerv&U1;#} z(H=cUwvW4t-<28H4rGAQz0 z^K5&PV4V||YykdP!UuGWg-|+R=^iXesL)eos_iei2;Kfo=L)Q_w7<2%ba650+(-U8wWEU3VN1&l~O|49X*J7>XeBKf7?*MLl$ zi;Ih?>DN80K|C(k$8SHJ3JZ|Q?BO!*>2MuAs8`yQ?O_ysBO__@&$t-e1+xM zEW2bfZ(f>IP1buno2I6zO~iQZ{cUWwvKSd`*tgHib(OaD95I*yj&R8Eb^1cM2oT*r zRp0NrY;J%3s{Ffd2HZ*PEPAD<`zb)`pvmgc@a1Ld_De>=_9U~-j2}B}D8{yXH?8is zxg1$irsHvnayEw7R+P=b*YT#WKxyqK%1eHKk^_4TK-hdegajsYH0P9_o{mJX0+Uj~ z)`vwWS5!PWKgSw*&D0i_a2l3ne=93v2b-wm|1YdbN}^tPt_h-fOWaC>-2d0jDaPZ} zGZ1Q}X-xWPV0j+{J%YYm?+Y-~Byv08LZS2#1U#oPBjG71L$c;^tAfmtYMiY9a@`#Z zDc7NOLEfT( zCoJ-Kd*641Fk<+4h53lnkc4mx4g76^9ZO>0Ap@F_qahs*hhC}(A&FDUtb_xz!55o-TgNTXe75?wxPpzIP4z|*Jk zmSOh(@!s`n6x4SP{0yhZQ#HV^egYZo>hI>Tw&gs;^==O`=f6Ms)E+^yu@RVQcn6gMWr|gK+`VvF` zp9zb=o|s#xUhiLt>l)JUX%ril`Dx*Avg+#^{WiU`RyAdxH6U3z*yT2jsj-Sy3;F(B zq@rKji`-w^FmY;XdM|z^qylOs7s<~M6}@oh$&-$SBbK^!63L9!WgKsJ3e!q^wH*|| z36s)$bHT)xfZAZp-H0RJNoE-DYBE`xzsVkracSnj5{+LEN;7l`g9{rzAniP*XT>8^ z7StE*$UA(6=V)B|@{Z8M-rD$QC5b%8ZcOU(!I^kmr&NQg6ulYPiN2G$9}er~$`;*! zi{DH;H_TfiD9nF~b=w z;NA&7moHv1EH%h1FsfTw9kpc9hpdeZSmP&shIW(ixq(r5STbvQhYw1{B@VVSw72hp zhGaYw-sv_^(ycy>97#1{RA3TaH%P2*fzUKe@N8g(_Q^*Z7o&?hDpY174zK%QU05mMh z96OlA*9`jlXIHe#kz#6x*mm^Ob`kRFRVwpI!i|t@%9?)f>>JbFJ|))s^xXw>s}}}h zqZur;xXt5{xyNdH=lk`fB;voa`e;vcW%=W*O{0{v+e;~vB?LUYV?X6AwRh>Y!0ee_&BUl2YH!+c>Bg*#l+ER$_F8sR zMqr4`LbNlH=R-_c>t)x5Qv({MJ-DCyA6Rt{y^QWK8!%!zKdl4WU7TWQ(2XaVf2NPR zpZ7DNHnV2W<~8?IzciBb>&}H^gjBJM^UrQwOC8(Kk`+%8W$XD2xBUkuin@6iNY9mQ zndh1}?SnFv#TcR&-1o(C!reNPp%En^`vqjme^a*I5aqse&7}S666b3qb4G%{75e<9 zYSVnn_pksM5P-k9Rgrm-ut>3nDDb# zL)uQj^r5~*jW5KMpOBed{AsW3&8l7uJ3iCq4Vf7^uLk9 zeBx&?Gi;1qRb4);WaDo0b$|y>G6A5`;$Pv^1<^10f2X#Z!CTqfVW$W zd)=2F2ui@XzK)WVlKwA!y0-PdZ~MFEx#2H7&ckq1EN$%}CM~O1_&Z|n@cW-w{0mZ+ z7)hX=zvl7+i*5`f4me#Wq^{BX2Q5aedi?kg#F`Aqk2l_(mdd29j|1}S)*ycyA2)B& zZ#*>afWEpr_B(;J`<(dSSIXkthc+|Q^97gk;n6({ulPYd>seA4fiEPzMay3Cgp$`ugegJ3PdQNE%sxnTXsMg8fD{tX>Ui0q+ufTr9G$iZ%Fzx?;!ae19(`B3$ZpL z`DVn#x^?!99Ay}z)7*(b-!cYE?-DGk%ENkgdH^LyS#hWw9`M$#e`QVG} z=h?|o?`4D(PV!X6Y&kHVRoDKLdwvdD`gie`yP_8kYo#VIx}S0=fi}Wa+}!%sUGRu- z?)vgBxPhC#-9*VtNA4_>g~#S;MG3-^Dd2cnd7;l>$xa{yxSqW&_d*Uqchb-T{{L8e z%djZhsBM%GQIHS>L`qs(x*3(BOF}|QK?LcPW<)?5q>&mOKtxKqLn)CM8tG=}n4t!S z;k)rspXc5C-N*N5|Ix!^z`1f==Q`K9)^bF=AIaojyo-^9afb1G)>SJ>j!mnHyh}i+ zdFL6%Wye-AZnLSfd}fzY7fFp>?;1bQgPCMO&xNZnfuGWjc*REVUR}QOIJKpojp2~R zCu^11GTo_`QMrl@vfWFZH_LqMsl9N#Q~z07=bzqyj7$Gaf~_lNuBTSib=w|Y4iv8f zaIOfbdvg?MJ4aTU)%nBK@}Q@VPhI~?Is+U!5;KBxAWomn1=&`07X;K2^gvW;FoKco zB+FBC?y~8mcOi#?i_6L$*izy(mSLbWxwLRf;cNvI| zL!CJdoFz6pyW1Cm04iQq7l^`RUWM+565oo1>2SJQ8gJ6D_=}w_JwlheRj_^hY!wgmb+IzBPX^hk zS|=q_@Nj+|zO=gqUaY6YSRYjZuTUc+y8*lORW0`^I2_JG4!V=tFbF0hTd#hsi zsn~!aj64Zb%Q-M@;x3g!2eP$C(bJ62bmG<0($ZdCjO}+i zQR|i8)0w;f&n=MJuY@u?C4cPw4h70(uUxHofGsp6sVm}X*P&Kj6poFz!mU67&CCUb zkk*|xKcE7fK5r~%ZUF4vsV^nT(nB8-@zv=p{G|F!;#X0()7rn52pE()zh~*ZtNDsD z3=_`bV$l$mLVc>n9c{?D0v9y7!b2^Zsm@2 zRJqjvv{p>Hm<@tWOUW!jq|u2ZiOGHGK)*-+>gXR+2y8@STZNIrB+N$1>*Ols3piAC zWcF=*m1h056DpmbnQ`^FRKRF=p1{SHh@bD$H+#Xq0>T{j#l z5i>d%n+g(`N78iG(P`YrUaG`Kbaw~F&IUEd`pQ!~<|HUhMU!Xyk z4RZc|*OJ$K$2|)j>U~Z8Z;j&B+y9uzG83Z$O+Yl5-(~NKojTN%2WcEYbG=J+9C?{u zt;gHzvT_2up!;kI9y5>#GVeHGN$y4>=)6LlrAp?`D8+{s2ppT?hBZI+nj~JKj0a{# zD+JeCm+zY~r?rj<$GFI@2gFM;k4Cd_Bd(m0SWZkuvaT-DbJ+p>0F={h(NOc7I3)pv ze{Lcu#kn>f;?{uCl2f=<@;ad1FwRm;z=QFdN09;&gH|P7GM|%`uAx@qO*uF&s#5zM zG{b=-f8CL8SF28svJ*N7?cx(x^HUU}>Qdczd(RCY>+WLvW%zm|j7phD%Q!3i^u=VJ z-&4)t??Bw-;=1=~qeS=*FmIMfJdeoz?NwC6x3r(1W|6kpg)aHbn2)e0$uRMroW!g1zcpK_nV=3AW*V{ea(W5_6S? zGY$d&cmkiUISZv{U|O7Dph1oB-InSMsdN%$WQRk$ypDyzt&(1|;EGVhJimj%Z&?M- zZ!3maw9NB1{r9b~Hm153`SWPHO+-F%T^U9k$ zZ(_iwwOHh5HE=^~2k99DF|9o4pBMva&EXTG@K$ch?LIF+m)qbdjat_RRIWt_e~Xn5-xk$hs)4#; zc>(Amn}Yhh6Inwz-$@v@f+8j|a2BQbeRpy3LiU(t^ldj-$Oer!${KLGYd;b}9e}F_|wDbWD186|drB1yeVaYi2Do#Xp{|$GkIzAqdK~r zpdC}2CV$%AA!*X4yRNmLR@!^7IPbauM(g^(&4BQEnPMItpekgl7^EX4+rKu{#iYy< ze>T#fWq$snvSa7jR1K{?UYD= zaILdj8r}YS&t$;oO7qYz-Qo$Nq;}3NJ_q`wSi(Ojf$|UD+`fRf<@!51aao1DKL~bR z50~N7k{pe?5>eICl76GdX&{<)MRyYGB2vA{FN5vbq*G7YR| z!R{e0aM2Fk{gjLiG5(dQY0Rf4%t#|f?rS<)b!Wlmap8aq!?{;U4pZr2*y+x1^()R# zvI`w^^x(c;;_Bx<9GRA;Kdnb_a58{ykr%N0FYo~xTwdtRuQ><)r}+8v3ne(d37``C zjcsviXpt9s8ycX(Im10q*bLZn_muGWWZy5MoB;ug*H~WYOW%c|?O6ZeGl3oR{m%0Z zsX2zH^_!)h#kY>38|R0ky#h`C-D*1~r{CW4<2N_rT+}ygR0p)Vzk{6sY5Hm-Jc~Vo z<)mYX_0M7&>|O|Dyx{lco&1nn#+R=(ZINkB`|Lm+Yqq{lZr7oT#!48@b)h3_{Lxn% zy?otc8%t#q76jzzA>&APPg9vy9v`2ZNNYl`UlCPcD`+ls!$bq2K)~$mBLm@zz5%8G zgC*8+MT)b8RZTc)_bLZ$ELolh#bn zGwd=Agof7Ly9*up8SeSw`^I3r8lQDOd-~(DPwYXDbzU63p)2-TS>)G(xB)q}nuLAS zG8X|6VhyyLILr=^BJYzAoQJ&*BfTEY;`5VF-aV*3jFghWv|m1-{f3l5%4>HPi$UNz zH3Yz`e$JfS8Z>yQ#$36S0Q3P{-bG)le5Ru&Rha>66*M?JJN2Eu%nW%MT)>zlBD)q+ z6gK1WC>CcsmkZMLhDJsJXbdkBX(O#IHn6Ih0um644RPYAGnt$R^vEvH8iRvu5@N$h zDF`TjT^qIqF@kBe+NyG@{|pT%TiggmV)ak{ib9xKVoWW1{T3il>X}bWTbki8s!k6|HFk)*eAyBl}%Jw z5m51YFNQIIQ=3AY&r>M%6IqG%wvtHFos`9se=#-n$(7|RC#;M?;dkfZl>SfcQG5fj z8R&E*VkYBlv%JUyox4l;uv7Hr?_Hmp2KsN1(PN=x&6xFq66|4hv+RCUaEGpP3=&CU63V$$5mE^q}n)^DO+&}(^6uoN! zv6#GgMukdew>qnQ zYZ(v7VH+8%{d(u?YJ>yb?$vg6%sEf8jQ zc8oWG+eRPib}Hb1(p+L9v|2#S4SCLQc+n zV40gb=Fw738l@>yj2{gUD8|FQUa4#Ygt)CCLNIUTSn{HIdn2#Q_8?`GP(HOk8nT|hP$=tzIB5(!+5V|F@r&Dfl z5XcMBXJ>rt4tjM2E_;MjI^U>d#U?8;F~}@z*j<)IedC?oNQT#*hI5{ujJ)+V2bw3J zV^2Fe8Y0tl>X){g+~=e(Cff~YEYxVrZSp8>097FegV1XQ?9@9zOS3KSPM4yzEiitv z*9SQj1j&JQB zk?pt{vk}8ye zCb^>|5s9FHg-oHC!mwTW9{+dPewOmbNq0n4VbC3%Skxv;fb{Gnwl{is@ZMw_6V;&`{m(%nVN=L^WeP}3uCb+foT%kOlA*#7L7@B%4G|C(b zOSZR_RG_`uh{def(RiL5z_q&u4M?k~=bTSOg8>6MxSvB)#o{ye(iq2SIB)}WwD9E6 z5eBbaca5hMV7WnT?k*nSHT&TJPU)o_E!_5UUO`@kB1%BWy7r?F0;lrkOjJye#jn51Xh~u zP~MUu$^o1Nz6y>E3*b0;v#PZPdYIoW;fKwzxh24e4O{&M+h@Sdh<&fi177@)(!lDJ z@POgV4RNVOa6p zIveA&6s?U=d*-)eQ%OQRhI+hU)1^>UT8;qt!LTO%bu?FBg}K-^`k`20Jz66Kf*2Y5 zn4LB6<;~e_csGmZG17}VGzOx+psxLOWEE4d9{{3s*hzk(k? zd=j0t`<*ICuF<9+*fUaRpz{|$)f!hX-0BRs<{bcj=#=`auNGNNHe$Zj7fcK3NA69{ zUCd>=HW`^2A4##{Wdrel3ed7i$o1_8?o$pJPn2(QoW`82OsPL0*NR>5HV+^26^=#l z$9!zR#W1!Pdn6_J{Pz@g=>cd46zHrDl=me$!9?7L9?~AG>;Qi;?vF3O*+O*_`ZG@k zXF{(!oLoEEM+QO<=|vJR2Sj4VaerOkKdwgHpGW|Zp?Il!1x|n8llIslC9he~9zT?} z+Ub!PHrcpN*bneH`nmp6GC&h}PXwId*{^KIUwUVPe>)zD|K|4t|9UYky%%wTDvsC6 zT6!yKp(HKkfL0G@I^2hH`s)tUZ;|<{7&3G@aAmY5eZn*Dy$vSk}yq51Px`6359vq-kv~FZwRha& z_&|Rj0(MWyX*C1?#pmF0py;c(Kt_O)4yhH}03rAYHU8T-Z0Y_d6Y+rS3yH-ZiP;%1 z7v5I9#DrBWQSv=`Ld5VXVJHOy>*Mbq3Z$dNb(&pJ7inMUA%-5zT6ReYw}8v(buGVfSMQ#QLPAvj9C4Ef|#Wqi2Mc5W1l=d z-T&n5wmAI5f5xkiGk#QnJE&zv@36YRyk5Zrr3TJtOwU)0k;H;S3}npLv3F|=T;hxy zVMLEPait~o`J@(cmlu)6Rf;Ud z*^EC3__1HnMZ#zlMa)9%1umUJfXxybdSoDuY}{-=*re_!ejSpCTK)eZjRR`uTV>v) z|7Aej$^RkqxOY8*bFk(1B{a+MVBnqwO2&hl+nI|%0)b5(*l*neyQQa5A(0x(k@ynL zRA;90bO~}8p(cZ{m0dat7)z$rg(g&QjQP$23&U6+Zhk%%t8!3#FnjnkZK8P0AZ zcsffjaGs#MA!0^w7E#L5X^$-$B`>z)i$}l>TyLM_?Tmk|l(48R>~s>1{gXN_^Zi$< zsU|@a>2;cW#+UjVhQ^8d`2(JOxpYg4_Y`Sey4k@COTx^PhH83)2F@kI58~`W$Ueeo zhi%;#sHPkem0OUuY@!v|K<#~NVtC@LU1f(;+<}lC$@tW#LSylZ!+J^4D z`kK7AQDuh#Z5k3$j9~;E4|qEe4-drffAed)Bxua|!|ux%AVd|6WBlL2pQ!mCiMvm2XLW1AVhP&ZO;U=>vMw`lwa}yw;|} zkY8#qc%|^Cl=V7D>+P07540e>%57z{b&|zWaO)3JgN=YKkJ;a#YKoPwBH$Ji7+RW` z!)3+}m#!ERur{~^33L1d6n=Bs3fmie6U(I+55X(oApnV9K&`EXSNnS}8FLBt8Utr1 zjU42OOIh|y!0_v)AJCtEA+2N}&1jViwg(oVJMz1e-ZD+^d7eqEpC04$W^p+aWAW9i z*hV&(2kK{Oa*h$D@zador|hB1b8_BB{xSHn|JaMQo}Wn*8(kLzumJ{8k~Exu*Wt+d z`D8(+(u)stG&r?i`)uhRhfzs7#_Ji3!UzYpR8_n@&64~R*nTuAzQA)@9P$tceHMUt z2sCT$K5rVVmq??wb2sS(&G4)#70Ozmk|KXkdXD6OeCPF)drB1sM>zb}|8_>j;h+B% zdi^JBhZFEJf!2z@f8AMJi?ea2_MaLIpr<%9|0Q3G}CAyV$8xNwe&qg6t-g6*3%U%uBo zYq(z4QF}{~{bg#w)1H^@NF=F)*xTx!B-424ZC4Ssb?%mn^56*nHwvi8wnJNgO$SLRO`_Jp94?mj;$qqkV~WJ7}~b2n>JOV$J6Y@KegkE`rMgd9P0MaK6uIgR z6Nt+6Q`i?Gdo?`iS2X-FbE=Id>w(BPU*7L`cl9BV-Kv2t3>IDkfZvJpSKS2+g^e%D zTK6?Kyb%Z7gbi)=>Gi;au#r@1uG+(e$k1apLn)ISkO;rql z+JFrCc(f6mF9W3o!n?1-80Ry}7jJ<@pm$VUO((-Yx-|HO7rKBneY7as$uDply4uqf zq+l`wo;oDgVDb6!b56d?U?EvaPxXe{K9gnoHh7Gp@t#QL&ak%Q%P>F#PGXtfef*Ml z9>`M*PA&+?vV`}Bh>_i?^wwj4Y~V(sv^}`R2x|h<7|Rm)~hHsGZ#Lf zFoh({3+B;af!20B^qui8DeZ-ZbC9zmp%x$zvg9%c>XwIY`rcH>SVQj(6*|6|6sr{g zld4gB@cgBO-d`N;l?xoruM9O!0@YU$RUBX>zuhe5eqMyMbhFx9xtjazQC}~RG>jR| zM7zC{ZPs<>fbi?mei3nqxx0d*=4uoMiWUGdcfeNoQciy}W-`n6#qUfv0`t^-50W-j z+`ow^wS6SC>B^c{U%ltyvAA)owcx#V8lob_^#+D=Kp)UWI3HlVUss_HmqvzX$q8I( z6M!W7^KY`7^Y4G^EdUvi1D!utOi7c+$QvD}P@U6<-@j4qSB!4wdlkyi>UYcV0W_Mv z2|h2P4=A-L=VTC?<7zyj$(9MfvS^)&=9SCtbyr5RJN$Wlf3MuI*w* z4bMzha|)`)Z+@jx2rj@T>}{GO@z<30JuTB`8r)4DZ?GokeYyweL}-v#2QC-01MGH- zU4uEtNpw}*@3nEK1~NyLPWnjAgk8>jn4;60&kIZZo||}~h4bKjjW7G#tl$yEDff)w zP>=W?BhE+%z8F4TRSAdDqc0Nrb@`3G{qHd23nsSriyxm^d((BUgOpOm`>~Uk0AW=7 z>}}=KMCv#>X5*S|XRIHfqmfUpXXt_Yy79$~m^_*1svZNRd?CDMi#eVGWA7OsxMyyh zoM!>>r=;PAk-Mz*0Nrr`u8Ci(D%PZ})K6vrY(^Up^25k+C3kVw#cRg2?3@)AGRDWTb>JFN>>AssYvSSRCfZ$=*e*~p*fKF3|dfS750*?`njTFc6>$$IPm|hSPf1M z2qO0mspv3*6K%ZN5l3SIsPMnRi%ifpHMUnPlKdpT$(Z*hW$NuI1Vo6!_!J!{)M?A4 zQP$|YOO2*LH}Q8l?0E4d2rH<%Sx1m!~-1+3=m8 z%n>=bu@p56#_V{Jn`71DH%{KJrj~MquWHF0(*vFdLEZ^n&0aLUmAND4_rY-v+_T5} z9ZlzzG=3bm@Lg*UCYFZ0d~vclff;|K_P%HdZna{r@Lk9-5@RGdspqTo0az!X<~p_J z9g;UwhLBcYq;=#0oJIHX_BaNuSd1ZW#qYk`bbH54dJJ?lZ%c93W8OLz>uJXPVrWdC zE&(AKtFiK%xt72bw(gaL^var4JJxuefF9LaZXZ0K+nr?rv>ee1VX!c4 zZ1oc(EN_)$n*%mq&Wo5eEY0hxJBNTLe6E|RPuBctLk3fAVC<4R@`#KG_(LW*Gb8U|{Whc1khql%jr$M2QN}XdsM?;UJKfLsLzV`8J4ELJ>6&d~rGhjj z*q&T*lbayW)&ge-`>!>NAok3i&)NTJlH^sc&YshI5Q8z2x{2O6oO%oD*7e_*(mywP zmPQL7on7t2-OQvHZt6gc?(qnAvhjKP~2YE94fBYtLK+J(Obl=>;Kf-qj5D3N-l4=^7p{(WL8NN%9+Y zyr=a)hMbzQ{<;XpfcrCe^*=DpKeW*v(^tyHAT>}!$(DzOwptbZ+ zAI4{L^fR=4RJUPD>g{TCM$>2Sgt3UuUE61rg8f5z}6sF>9K)W^)d#Ae>fB4Y28&ZLF6DO^kMI`kop$oFWWaPc< zKNgp#KJox=>oXZY@_}lZ0v8O=n^?)We{9j)3tQx}8l5(UE9(8GNdH)PY!^{!kRpdp z3HlcL7^{uBEfN;p@CER`_R7^Raz)PjfA)YJbh@D#hF z2x#?9zXPQw-{T?e2_#inu1W)5JgG=yRyZ`bIow&DPrGti4nU~e@i1zDjiRIf`M7Y$ zBi)SNbw*=fQd=Y?%Xw2F*uRF`l~?=I;C%DEvq#D^+LzoVTKouS5AKxHyVoPNFJckq zRoGhTyv|7AWzH(Msr8f`A!GJYE5o9-GC-%avvkLzB@S6#8yO0a`8m^@g9070<}Ylr zLqs6dXMr{%Db(+tnViccm2W?7_-52_cnTDMD)cP_oKl&Q=^8@8$}D-kuPUd+hf#!B zXro(Twe926bF%5xtYX(_olFzA9O9%!{iXPNWmRno3ic0)8sbFSu4{^_dd4?6*;JIl zFJV(<3QwI#t(kUwu{+q{s`6sPr?~LN!A78K=}X#m-FEKgD^qOABZU?p?CeC!0#a9jcovR? zsXh8`T&b^jw36`x-az@wGi#4PyTI$oadK)u%nQjo3u?cWjnWtyZ>DaT2-2|PPGM_V z?>_oCWZ2C|mgs%(I`ySP4k5lBcsRDa%AFc+(pjfH0XpCO9IJ7$Oc!gldHLB_P)Xft zEIjt~2+?^~x+ZbZ%7m1kmTJ!M!aP1`ZSDoyDjHWgdm`a42H=^4LQX%_zedOA$;ar9 zw-y>~rbwHvi*i>ph*ny6V9F87m>;^IMqVdB|bU&hA&hRqJq_sV+kie)e2LsSUkw0qVqSX+#a@^S`18X ztgPmEo(_yv>&uw1Cv})pZcQ0*%gov@gUrbqxV=|if=~*o;;POvzwgciWi%%-8t!DW z-+8i#ZNy5PHh=cmXjrIYg#T=wa2UrsLFlQB4XX$eq`kd%7mkEazS5%DgV)WJ8HL00 zZ+@Ta#)K#k2o{hee6E`RnB}7I(vDxHHcN7(jz!7R05>|KZ24|>0!Q&{#zzX(jO0AU z)0^z?MnZ1}Ng9@gX>fmMkm&KEjy6>zx*X1xP-iBNAg?t%9pwJrD5d!!X1LM@gCj`7Ppy9$hF^bB zTz+>1*OJ5b_i%C&+Q(`^g0YecWwPy8!io0be^%iNGc89e7JY1%&CejT9p6&aS+p2i zXTf&n#{JAU;yMM@D)j2_D@6W4NS))%t&+d>a!iK%WQ|f#_55PqjD(MCk+4%XL^I7^ zOYi{`)U34wo*`-nlra$C{9b0&os}k7 zjuN#z#3;p_BG`@9rgMtl%crt`$hnu|b&#-=E26ewtL}Mku&(U8QpUvSm=g}V^l8>v zTdidX*7A@(7XN5jx^I~)y7#+Kkt?P+eixoq{oSP_c>Adi+alBsM+rw9CnbL|uu+~- zhx(zxFjWoXO)dxWev(fPm*|Nyh^H(FK8?~yT>Zp2sb%$^z&WO}x^%3TTX|v^^olO< z`rwH3dvWKA>$)VXc-KTavQOM)a&HU1cwjn)7Bc93zU2OAU6uRdXwUt?vGs~Gp6Bvp zvinbTKH-PP)B=f@o-1XLnWPg;iqlMPwk~x)b5Hz3o%arQ>)Ye{aREZ*{dom9JgnYf zX|W$G*uDnX6Jbh-`UWyYZYg>%tG_>N1TmU8m{N!_&kB9f%>r7BfNDy zLOdm013b4^v9F{9o9p`?UH?Rw!QT0~+>bZ!6vvCSravN|`%H$kP_P4a&H43*`mIz? z3(JYRL@&SfALiseqx2GnU?2K_kMY~#?@h%bqb@vbs;~hj9zAk1}>lQPIX}UE8kxu2y_vMNpsH zcsLj$*EDwj!x)2``-XByRVO{dyB43wKiHcBD+y}Jt=)*IXEJ|h5GT=fjNl18dNu3T z4ywji#6<A?_1FKq4iX8THj>ud=aOKO|F zu@IjMhzpFqdg3|Z7`KlUFQ4l=%aEQt@w}yQZt`{HLy6!*3G8xOs#(V0_J9$XQ3wMcDhykCWK!bC-o_R%SVrS*=j_B*GWnw~CKn~R0kpidL? zb{nqZo|UidE*@K#*M$K}v{Il!hvqi`H_n02+yc*a?}!w43s(7+AQ(AAWsE3x;Z%Vf zut%M^M=C`7J-ldyl+Io6s3kt=o$Sw?)Z&tt@tE*DZ`K`O+50pbW?qE1x#ltK5zi;1 z(N-8VkHw;O<{o+b1-*J6kD8hqoLE2HX3ndpJidR~IoLywhfDTM^zQw{1394yrnbE_ zLHV|;TDwf;bR(^#DlkXO%rl>Nr9&ii=J+-Y#v7LJ*h0^3j;%eI&jQh4Z`z)g{jjV&W2y$Bbj- z;|xfajup~nkLn(|#i@Og;un4od1>_$fXsWMn8ik7|I3zU9^rOs zRTwvUmw15)gv@;zTi_oATqb^UyQyp&eMx@PCtZhP>aMlDuC#LIvGz`|u=ixYnhra6?C@_6!c%X*)JIjS zv*H8VTmNGZuY`wSC55m?^@z+-v;Z-~n;=rRx}11CQwuJoBHAsmQD|yNikye%@|po9 zdkv&22sjU(ZZ}Xe^fdvFM4svj zO5%EaD6W7N9ArmI(3d1L-^F5zYJ1J09hco)h<}`M#X&>5iv?>YmSv&W(LWq7vXYOy z(HCd&opj+CLAQLpb|va5z8tgL@&3VpOJ{pDJiVLi4l~1gb zWXladi3?dHd_S<=J!LoT+=Ex+p5w|TEHF!z*A+$8KExW6Nf>kAmBzR!(2j(pVgtlauTRR0*0y54=?LzBcgd9ES8Q&W4QOGvl}dx=NJ4Ovv_qMkl2ZFQeH4jI3b>?{xTE!i zUkfA?u?brhHTuZ4voD+?%oWVd?P-ypVedhgv&g^t#^6u|`Vy{AM=LT7IGtIo<_s1i5k*zC&Krr$mg zpL^uo>c8cvmHr7r3RL4Thoh}B2ZZICfI5}T<C!owL}RLqy{-QoF|q^0h}dRfugoOV!#i&9YE#626#O*Tfp=-=o8OScMa zcFMg`KCQ*aRWGP=X@`pC`B|7bWYMm4)tZ)$3@GaOJp3|9Z}>=`YsKE6#fFk%WK z*>xx+TCalRkC_MyvQM9}sY(oX5;A0mYK%7&;DySoa;hJ@aY*tQF1RJGLDevJLa8ss z6R_i%qZ@slq}?FI>F`&6X9k-zV^4J$c3dXKH-jTrP79=bxu%|}6Q?KL zZeVq^-V!_z()CtMc|MGkIhLDz1RTsrYQov|b0gj~>g`mlkz3)-W2YQ(UxjZ)El+5(nm|Rba2M)29~*z}=KFkG*2eDa?n7RkMmv_pf1eA= zG6$dRaUJ0%mAx@okYJ82bZ8z*oInu-JdxHRM4_rAW1!Cb@OkTShVgIACkUYu1~bpD z>j?l_m>PC0_oi;UGeqSpXLR(Ip06Q^P&5$Z#@^-c;FxH!&BEwW8rGj&O2sXt=$n7| zg~-b&K;o(mi>M$s+fOb0Y(pih>k~&mdLhc-3dON7GtQS|C7W+FfQjq>NL}p%x|prI z+vWC@i49J_vbKu;h8@*5FdRK$vFkR{@4-1wyH@)C$q;hdz;2Qp-h%M zwK986Y1&A}jbVe)_8e3Gth-w4*_ z8-x63)xkYckQhrBV#`kIWXPM?%dsF=PtGp1wHLdAbj240B`?a|dD<5KWJo*o@!>ef zTgb}<)icC!KDRzfN~O2aIKnC8X3aur`g05YP}P~8oB1L_G^xxZQAgz#Cu&W5FS&RG z2W{nZmCL03n7U%N9URO_F{BM#T)mz+;^EImMK1N>WF@c+>MCF~6U>#A$*yMONxvy9rGVh=L;PFQdSFZkd%rTGnhc@Cf zI8@FHc^)8e^VH@;uIVa)H@@V2cBpy5Jd%_`H=@8urDoC{wnkG=0dw35d$o0^V8@g_ zlB&*9E)z&Wyy11WsYTH!wCY^N^PF_6Mqmg`=Q|E1Z5Y-4c@?DK1>^jj1@{-i# zK~$5XLClkpuCMV5n>8(pEV&-)x}{%}Oaw_REpHK;z3l&3Jf^_FlHxRWGynG3C*m)w z-Q(t@_8hrt?$I$PNISJ`C+l*Y8#gfiKgKxt+5aCOs=V-7Qj0^toL6o!kB4C2v8fXnc_Qx`LEioyr^;K0 zA-djVK7)p5c5CMLrWC5s{66wx;Z#!9rDE#3Dw^*v>ywV@&7QT@NUKmPSe*&N+8`}q zjr`5DRBRjst5B71!-Sei`4SS7{{qe*T)!s&A#Cy{F}by($S1;IA%3|@z!xOK3^ zlFL1%^HjP(D_D%cek`ry!BAI( z-EMjIf|~@MR7QBb4}fh=9kLCd7-|fGQjA=`{`Gmm|MhuiHxOQG79@Z#Pm4YL8L$t$ zYquf1$_r#fR&h}fMq1=eijUm=W>Y)iS3jP1tbJi{CIkQumEjx`ZtIkFWoAz&TRvr_ zpGwm9v7kW&dBEuRFgdk0B+=YsyKb%)J;`nyJ2mleZQb0I%G|t>Sce>V#R=_OWp(m5 zco1cSp&}_p)UwbiZYbT;ktN5;N;${NZ&YA4ThIbE3{^{!qG_C5OWeJp|IoFYjQt>` zE|9bys(9pzu1VMaby5BRqw3AY8g-af;YpL}??^mP>HkO-n@^-#%{BNkUN z{Iw%XJMc(P8Y|>W2&zsY8!gPO>oF*+mICCxk`!VmuJGB=FhBj!9b7%!ZM-Hz$Lsft zBp(EvJsymI)RGlHS*Tg@u!@OWeAj|2TaZd(Y#pIFM|izf$?&YA?Bw0;bzdg!Wl-3n zsO6h5%B&}uJXb!4GQ@+YJETqzgbMQ1;%uXR+KMdg{CN|M_p|4r#;RB2+I12DcUPcx z0fBSMzNh^6X`m0ifb-+7y>INRs=ytfyi~j*z_}N$eAOFERg{Z89NGLK7#|OgcXEhm zu)WFb7v<=g4B-7*iSz{g zrd!sQu;pvS7z|d#T$u#(W7SYx&|?{K(WSmB(8R%OBD zp+Ij7>H23}od*xQXqz5A+f1-fI^}p2x5yL^mC@wgXLf~7W4*sj9a6y}JMld6huCz^ zCQN_mx+iDL5yl9{d}dx8zfB;kSqVP7zW{B-dm205v0oQcjOnp`P=iW7 zyA$QhUk%|$f~KYyuC;u~Z!K!R4!IUUF}cIRR*HRsnG2S>rf7j3|M(`Sy)T(}s#J$j zQbJS#RdttI5R;Da345wxr>YTkEGT9Qepj4Q_hXSAzt-i;ts7FYCyGzFoU4v?K<9qa zyG()|*+uFrRj$Q53MOMItx&+Ri_oE7WSvu(li{M%kzd+El{L({zSG_SqqBJP3iu^k zQKr~hmoHo6nU9kexJRwM<7`gdWDrk_zkTTq7lA{R`# z|9g2a4(;{vgjZO}**aU_r5N3majik@c=<#7Eq%ydM!hFXb zyjgX6C6ce)RHN|pa(>ak;~yF_+ekRcvkJPvyg*8@0F*g5iz!8BUSDX1i{(>F_eqei z8t&UQ{&V{yR217|&*X2cq~}xjraS`MDo8Re$?2^$tZz}!qP<-Y1;F8+)!eS?@e%ZA z?DHo7af+8Cl2tt7f`Ukb{+yHX-uIB0LVzg0miakg`^Nv`7T^Crti5GeRBPBaOh_w8 zi(&?FEc~{IQ9sRF)`jsOdDignl-xZS$=upid{GDma~#^$ z=4R_G0Adoy?7KS2+3EE|t@ABEKJWW+9)B+~>QkxMq#&NJyVW98COsqjqMcm!Hk3{N z%%vk+LUPq}aq;GPljwzD!8i4|18djDVnypH+k$?^-_?X4crd|`9>Zq8pi{%$qT9WB6c2l8wQSiBqO9#%{1-$v(Eke}>(XfM!oxYa5A!rNEmdrom!QY7 z8#BSfM7}Yd5W)}}Mrk6PBFrac`1;HhH=mkEkDYyYPVmqxEE2lv?!do+LNTR2kK1;^8>MmPNJLy51z#bf0Flv`CEG-pb;U+@**L z@`3!b+JSNB*W?4D!b@6Athm{bVH!?4B=zc#Cs9uMw@%`8;th_y?5x1?bchKWalJEr(R6>VYnI=;{; zRnXZohvsVfr^9axnQNeTa+io%iKJxzJNf-6auUvKTb~%6J{r9@HaojFdn3{He(sg^a2!uAuy!er~vMS}SuOIIzybkK1 z140xga2ELSlvSlXYq`D?f%j?ximsBC%n{Y^co0)r`HHd8G4wC9gR`gVws31}_ zyoEcI)=&?)-`fw7?Nh1D%g~=6jEt8w&=D?CsG>J!noQ^@BbjLPZLF>M{wA$OeO?li zI+GL35C!ehq!F;q)>L$$ui0#H+wN{YYEn_@KJQJ}huUv8@98`3xDodyv1;Bkk9urM z$8H~2vz!0D*Cw3Qq;c?lBCAyjJ304;A5VnGG-Ozyj@*mJ&oFA5;bjqqPuzBm8Sbx_Bg1HP11thIH8+K|KF zpBKh2G1T>~V-qTujLYAADYxR?B0Lg2rEPe9hh}|TH{^vq3AL8V!5#^xW!}mzrkVLs z%$sFxc~CivXH68b7H<{wiXY$1NgHenr`KZjHPiJNocA=Kt3cd;d!{*b%1^bgz?k0F z=>pLv`Q(b+Kipdv%YdFTW>L3@-v50E=h6HqBR;CM&8{)k;1MIky2Yw~)sYrk6ALwo z0T2!&@C|lLqEvhoVIbYu+s&$BHsq@QbwPvmxFPt?(}8$86S%L6+WYj1UKWoUdv}0| zN{bo+CyefxP>DS3sSW_7Yr?b80P}Q`GE~T1SNVFsI#w;FrOG_4i*S5UC@p)&gG15b zRH`gLYjg>*2(v7k{dh@<``J@HxW9&_hY|g|9CHKPjb}>WYqjq%ND*M8!(XbVevJ$^ zy&26;l8;jP)dJp>)?{@-dYU(rQ6pTO|2K*o8{q=|KYzG%;qpbBUHEKyq5X*LzrZ}9 z`*c~|J9`vhwweA{X8Yj3%ytjRaV5&E3-5}+uBZUO@Far5F#gSp&c`{pBUCD}n$}oF zn^?m=zjS5;T3az`_ekuP z6|#$p`1$f!hs>Mtm_hDK_vZ)Gn^19ccFzk6&5|=;Wxws~yrHdJkorX5to;r5NeRXy8 zR`L?;5Ec*9oF(~KRGQD>M7HB$2ZDb;GH+`jr5+ewH+qrFd3(~%#uNwh!#thbpY@t4 zzjU$RwmiZ8-e>s7!_SjvR+tb}Lzi${++?qkSc?D+K;6pTC}I18D9^c1s1`L8!EUU~ zl~{0};>=>->umYeB}fm{;GFP%&-S*6&%OGTXT*4gB}NtBXhd62#{p2^$Lq=55V)~t zjPRIVvy1eHINaUy#43@TT*XW0jELfzTw0~I@De4wg?4aF4LuyI4pVTkW11P?z$Mbc z*Tmv`H+B;`9h#T{zkPtWf3-htckL z71x)`*S>lPrX@L0qtN$fvXvJlifTX_)w9e(!!n#FK;HS5V@YP%FGWaMV#!t(E?i)k zs=-`X_R1qZ-##WGMNRwWU!hTN4q)xV9pV9A+O0aZQsU`9C zu?CKfN%R^b526~~H#t2wh5;m=?egB?Gsb3sppmvfbVk$yH$9`Sh7^xgtc8fWfRV$E zSu|_6ZpB$!{voTsKs!YZY}`3+fw>s1NJy=ks8?<9z!p{w+vh<|4y-Lp+jb@DfG|md z@V-8pC0ezq({3|w^4Rc${gl@es-18vj7Sc63eydQ6!GlpqE#F4%g8y<;|(hPW751O z1$@y8RuhF&u|M1dtJ`Lh2asb{@1|1>FkS+@>>=6kbwHqyNNGSZVw}V1SABUXJ`MVd zm1cs$wR(Q&QAei}0uV-k1`v}@*O z!79_jNHGg{Z7@x)!(c$VRU4+Knb-0yr2erB+s^CvlS~DE2Koq+rviE>KP z-f+biKlu@Lq2$lQ491veR&CGD$n%^ImUK~Lgid;M7iBzr$b=u5uL1hj-@ZBIqAi6T zAZRgVIeKCrPCx*1-m$AVM_Iy&HSf;XBcEA*jT#pglWIQ?1QBLa%)RZZC*JvB?(i{~ zmF9!Gy2r{AG#}VE10L*^Z_0xlvqXEnl z8V^m)%7{3UNshk>>zCZmSKh5cIXj@_tQZrrT-DWPYB9kywz3K92J|DHCXB(?QIop( zW;47jN-w*?(a1)VR+O;Rufr@B2Pp3&ZWV^fIKvY^Cg~u&z?t?&)L2s`K^0}2I4{-@3vR3QzaGiWIYx72?Mj%r@{Fib^?X}#WpX1w@`xFO_r@F}ud1;nB5c;WHT6^n?}i}t}mLc(BZWJ zfsJ>9>!E=!bRQENyc_KD{YM?b#dX!HsS7xYx=@dL{IV)ec~C|g{b?g$6?fAa)A)yE zC&ihPj_48}B=)l!_Dh|iu5yH~LlcXiCURVgK^{$9nJ0Bz?H)y$ZudX%{R7R1gq~WJ z)4Ffl)U(vxS3tNdjL=uG3nmH^f=3`~WP&e77{cbeCKyMs;u5=4Dj-K(vBYO*uXo8S zpg!_*fcOXHrQFy{GG*l-%2S9&csgIgnw6t& zyn{I0$(Xt;T^|ywL&s?=A{^5*1=JhCsYU3fUs}}lwVr6ttsVG{@5YphDibj9tjuDf z1grTYCXjj$@~wr`|AFS^YI$QYrf_hmv42;Z-H0jaYH3GMPS4M zhz1Hytlmk6^E&R69>deDh@9Wo&jy~4Picy2pf=+DXna!q#FJ~blY^{$BSh97*fZ-u z=9Sr-`dUUurG2(Z&3G|~X(TXe@M}~xZ8n9Cgz28ORO|%-00V}*#i=c_1WtTkI+sq( zqUl)^7dw@}oPL7eF%>3*mFF(5D7)?hwkx`Grki?fI4h9hEGO7kWhfg;&l!hwofQJ# zrf1Ll3I&fJ(TG|L=0ndjX?=c9`}w+D^X-ja`Ag9yVi!0 zXX4lw(#I($v*d039$#Dvfe^s!tMraqRUD3RRmLQ8zJVxNlWW(it4xD9S_#oM?51>EgDNeiH%9s{(2m$lBMj$)n6c^=^peQq8@&;mkGe z9L0Y!+pdC_%r<3SZ7E^RxBQL3>;R44j55XT7qAh{jX4_5CA(RD)3*y8wng`xGqtO6 zI(^H#^r4Kky}Y+wGlixK{LTywi%QOF+kwV}To49g#dSbUYV1{1Q#qV^d9Lub&(Kyx z(Q(!OXr>CUEB9Cu8%FdYPpuO9Hva`uB~dgCsL2jBucOI$X6wZJ9a)kJogk)BP2Z=d zR@X%0J!_yh)OtYQJ{ZxaLkJU;?2C3*cwAD6ff^W=3EL(RAkR^9ooSQxAiTfv%rf^s z%r><#qxmm=yT2XfoQV8ahj`<)uk=_?u%_cub}V&NNZFH06*DWgEG|)b=&hL7Mu))e z=81WB^M_wt>(M;rz{IkVUvAfh%=g2W`Ov&QA1m+&M^&~<6?xPTHoQO$=v12<5AAC7)Yvg@cH}w zL2~A4>};xM0fO?h#D(9YFNNJE8yxTI3Mp#6qR9u;qTkF2V8jKVxwQ|Sna#(4Z>5=a zc>+vMCBU#E+WPz_cEFqI*63D(YYPh!1Xkx=f2w!U-#!xLS+f9y2ORo(PPLPXO=hz= zhW{sZ4Kyrg%gkUNEHOENK*a|NE9d)H65l`H=`&hzfn{w;%MxWg)f^I@92B%MyZBL4 zfe1^nsUNPO?R|W`aDJTg{R?p}htRM~%+0~J{lNp|MI|ek{bCNDUNrKSo>8W3J@Rqn zxl`nZ4SSU*M6@I^mZeWfY^|%9JIpWXgz}Gc+YQiXuR>!oBg^7r1p#RHdwVc2yIxU* zWt*Yjm?s27BXfZP!0*#H+WP;GA7-uoEep5(hb;U*;5p|?jF6>@yXg4D)-!{{i6qy<2jrJykalRM;s* z_sTJn(3UZ(Z=u&!-!4Tw#;ilbEKHDcp8gBHI%{CTMnhA=fBoeS@vFxpt=W8=8!9Je z+qUr&>fT`$)gvaMgiK`bWo84Ku45eG?^W9YQ2+PZX95wVM|=w zLPI)y-+0zS!@}>UzPoEy{rAYH}^@oqr>^r68ug70@nw;uDcw3a3Pq0q3RrP z?ZQPoKEFZ1!j7(&2Y|n%YjxfL0450NfKkJAX1DZ!Z~>AA?QX^(Pui0na`OztzImyb zJLDT4J&qBM5nc)g4Z%wsOEl`N$QEK96~o%nOTn^QU`PlZ&Pzb|9hvZ9&!jow&cO?W z>QkYeSR=)M>b1!_s#e1+3BZWDyUmvmDf1%60pKv7XE6&(V?b(Q>wB~J3g`6a zM8x^5^0GV|CoTt@83bn#z5;MgkRTM-jPs$9VF108W(Pyq2MTpBa*?AvO(tq<0kqbzRPvgg005HjJb&Ooy zQV^DE7Nf!%Qh%!5HuLQJtrzqAnGzj|(YTx0tWJ1*Iuh`C5LxW=sFNM(1Gu-6v@>Y-MpSov4F*qi#j<``w5fQ$V#{>@=F51X zlh4)cObAWrGcy^ zg*Y(D$(JvIztQi8<->jbJO_Q2)$UbW5qTzUFa9okT&}S$%d#U zXqNWAiMP7@4Ov@uvLioCL~48pg-6ygu4e{<#i7?X9bn}!e0I-IwbH=` z-SMAklgbMc(2@L7PUp+vWkBxqFFEE*2f)Iq?6B_`n6br`RvYe0S^+`o7d86+Q-2Cv zCeV}w0A-aX+8-i8Q6uN@p5N>5o2mC*5x81bJ8xSvJ0M+;Mp ze%wIR+w)$3i##Kbp;D@~{kG3qa|A|6R{OrF{D)9mX2(;7z7wWGVU_00RUZ`+0n+^D3-PHntIx3{nvKS$EiWh70+ z99cMH$8feM5yHAZN0r@$4_}`NP3$EiMQ>gn2$$czP+t&^?8iM9EPcGvr#3^v8-9cu z?q7xsf_0{JJ40isGV<=aFYz&b49ahpH!k)|QjT^y91Rc>sI%b^9xcr@{mtmKQmMPt zjwZF1aJG*UMjM|+AID=R2N{g~)qu`F`NN%Zl`TOZ+$eIpXir+V^b6T0RAbmC@(|nl@HZH@{NOF|X;v3Fz(X8|2?E=Ke zHsoSe+TO=^sJ<=5*>925s~?o3R+V#$K?CR!e;?n>-z>&K?sS^_+f&;#=d-{sO;Gd@ zHC{Zg##{cJ?Z?M`KzpqEd1?v675D!zNCqNYHiap>{TyC^!5v3)oAi)Isr;qWe5j-N zh2Bt_;r^@XbT@=vh4I_G*;IUBijDQZIWl9AwVimnp-DSVz^72o*h{$BjaW^44fnWB z@BGN2ZelNiXxG<;fo%7WleKr=d$Vav{8Tzy&IDWg{Uz&UoiHI&thVIDJtvD|X-+Y5 zj)F{WM;~;@?RsJ>3h9gNju~< z8Dc)w0u?&uX;Q~Bx_IPHeo;Jw5?PAf7i^$;I&R@KeKyzM518g&9F3m@vdDkdVm@%i zCNSO;9q$*gSb>(~AOwRxNjP!rF!KFV2Lr+u*#e~-+e-YeE%v2@S@=X-U6b~SYfgnC0B-tF5WQz82{vg5X~z;B`vki zrS$V&QRDsI&h>HIc5w~&ym!|&NUP~xi^|d4NOQ4Y28D^Xkzc7lF{uMesYGdi74b4d zfEo4Cs~1Eap3}btk*E30;H7SfKdClMYg{#fTy(|4*G3pz94mk~f>doDgCNC(cH^H6 zYY*WDTp{3Lyq+fH*yPhiX-DJexmCbF`ZHTH{!QwmRC55NUhTP$LVTEdn06)O)RLf& zo?bYKPr@UOW`L&~k96!rpqyrjP5Sxp z`xDv`CTCC(Dr3>51EMro9PZCHlTze%2*}b?UizLMz_E8PTx`A|-w0}Gst54wanwJ( zKVdcQCI%9Q1(+9`+sO?xumpB-s|-Vy>gCtj-zl4!E6r_j?+0IOMR*3}#q+Qq(3dRN z?inM;j8$7w$F`c>njh%js^%OprDS!%0glGa0Plcm7AD>E?qopqDGw*`s=MnP`8cHp zR|HFhVui39y$PExvf;VvgIT&+ZqrcL&HDx;egXO4=*&VLq)s@%p0!R|H3 z;d*?sn@RkRQEL|N2XKvch&*7@$2+yE9(qaCIz_Y05iFGW;+i$hq%uog+k8&=57M_Q z&?)a2Wsal4uTp0H3sCWID%Ey?&k&VR1K><`oNVw{7ZckqPexOdYdl0=bxye)0vFe3 zzhBdOC7y>)bEh!7plRghEi50b?pQOXB&~ov*t#Udwrk9Ja}8-?{jxG5VT~B}i-;oC z!+S_z^xR%l`Aq-m!A7{~KrmHgyXy@sWMomcq3gpX%x%S{v!C(_8N+QqVD{-V_9!Fc zxneX2A)AN;^zdsoEPqrRZ}co$LEC+2{p60#$IDR26T~2kF>AGJ#j|x29o0?5>Ijr4 zad@coI7vS~-`KIh%ROQ^ep3gjAHS)n4|2!1FJfjqnqL|g*y z{frd&oKN{y`(F~pMTFxrxlx|?N)(k?=b}owS*LaAF15*SPf{(e3Ks<<=Xw=m{~Y)vZ03jeEyb%( zfZaz^y3^`Hzd8FHbzzZbGY)D#=$qRbP!l+wE?r@*MC4gfZb=;8cjFen73i}?mJX3u zWbc)_aH09K!X~OJsBeKgEzKl>hq7Cm^r{;;=^u C;=`qhz5WCK|+TLSEs5s>rc@ zBf@Iv9)2L+iB-!}M&st2;^$2sT~;gz5l+Bn&*}L!My`7a{4{cb!+8*`t}{L0xU=*1 zY4oU%qFwiwvZ;n6EJjy*wK$R=^O=0@QjGbkC?oO}F2lz}ZQs)j!cIw7Hvu;5*^Te! z=H_CG-TUcnwpjId%aN_mXElfq%l#dqn+sR1QUQCCGBrPZh6=!|afNe3#T3g%;H{E> zs8PXD3@D%eLtls6yTC4#Xj}>+$cC;w?*bWrP8vTyr*9@of@GO*Pr6%e=&Tb3K0Z9< z{hGo9#1Z7IKoJ<-n+#`GS`lJze^YP8R^_|6m^{)H}w zwOv#hb@H>SNiOk`G7e{eCa7nwH=KV0*}*W)o1DOrji6`ayd|9dr?rb_lR=&?7$&)` z907gE$zB^TZ*t%19Gkkpge{h`_P{AzP#0vgrTN9g5w%whbSeeD)uA2BTxZL@i!M1% z2*Iz40X!zB@U(A&IFX*Hl+F_&tS@QvTPY}?Yzr(9p%IHM+%-OSJOXGZYml>vz}*<< zCzKd#>g6oi)M39b&BMD#DRdU8IIiyREvvJ=8GMkDt~meg`wzEx&0EmcVaS%5u{S+? zmk%AET#;|>t@&|h^;Q7+3+CUf_y)@Va$&3)MGN@&jr!zgtxLyJSy}=5Ai+xZHIB*- z@Jtw$<)1KGJ%o#$8=dOwE+jA?<`#dja1NUQjZmEXW?LjQv*;zq0a4;`1)@N36^av#PRFZL#n{{X z8P=fRZSf5@o-oYx)c}4%VY7Bs2og{9{-3cu#-EhpZOfxqT`zYp7q{SLENPA~u8Z@H)+% zO^H1BzHjfXIf6Yx6t`!u+?#(R?|dqqI1uAQM)FVI)Bxi7BlXrYTo7txGlg=+HVLDc))2=m>=-oFV2hslJzp zQ)+CFUi^mi8}cwS+B%Mw)9A2^OZJOzw}Ld2uzcxJ$J=Q}a9@sM=K%+kwm0bx^&>8I zoAlUgeUo?V{GvVVR1IshI5r5GEJHXg3%*Y#w!0=G^#=?9`U^0NkmC&rHiF}X1_AzS zYuQpXV_MT#pqo>XXxuwHodhKYGgHaUy=KEB3QfrE|FiQBKh%G1@f7`?;V6zl-?-taa;- zt1uz^nbk?WR23dz4h2zON8fsW>3f>SpW9OH>5TKV-g5bn8Hu{COSRdrH?=vvj@zCI zY0_}^+7Bz3Rg0E9&ls#%%$;_=TM^%|t_|zj`vxu}F%$2K#m))PD99+o-P~myf};0S znPCTO`f1qcKUa$mU9>lguvM&FTawRP(_*GQlhdfTq+N9=Gn>cn@EksUod zPI|2xvc)VqF#-4=s~;*Btz)g~Q?GuBp14Rpv1-ivLz~qq|C2V8<^s|owDYHyUX8)I zdDz)cPe-8HjlMIL1Zs_EwK3Y>WCj_@eepPwahXr+A=$LRrFu-#ylq9_e{;CnBi`@uXf#teC!9mnU`Zc=WQmrLKA>u zJ6Our>7HRR%~M>B>d)@@0cAf-pQ2g#j4H5ZY`ISX%mYXuejgH^2wFb1>+T;-xbxST zL)@*q+yX3h$+G2{iBsNUdEyn!?1y3oyzooN==oGO@zA(t5w7Sr`&;sFf8*yj%+i4f zK{2Ad-Q#`7X7~PPKh!*MqF)>>7gPA%TSwl1H+`sdxp)Xh;L~UO_if_wZ~4IymE{c3 zZ%0>y5mq38Lb^-}1F8Swt}O2lowwT zEsLJ@(^2uwTYG3+w9Z7_XWp{h%n{TphVqQOsOwp=YEra@6R`cFycE#{HlbPCHUs-B zke86nLZNZ#2PXigi!1h7&W(Y0`HbB-TfU~q0t7|bMFOaknPQOVUZ2sL+MuFMR`cWB zJK&b9kf_!oCVO4@bB@5_(ry#EkxF{Tw^8E7#yI!m{2Ps4J2GdL&!=!Isw55y6}3Bd zle0Kp+!-6vwA)8In+mckr`x_9j5jg7jaU(5qw-t%eQ|_68ZI|NE}tm{O7PA~CZkkv5gH;-pk{AHMhAw^(_{i`cBxCo#Z z&2ouS@EdTi_ZJrmNiLr07A{KP89H=HsVjiH+a7+(YVHz*@g5z@=#BvphH z#UoDp*Il=?{V8Cgk|wjvrl8`4HA!95kFJ}q{mTQ!DkixTej-4dZ6#SQ(@zWSRpnTolh4#_?^av4a3C=LgYjes15+&B9B*a=o{0#Q;Q z!D@imp$MCXKm}(STUgN$vm1LnD4r+cG1^s@5oV)*P5@EB1OMiF#-U1jEEOyr{Sjo* zcXz%6Z!1&$62j4IWN66&A7BU=F>G2#MSFD_uh!KP#P&X3*qkmR%#&4^6?d&4NimUx z`CqZ9h5yyX4TctjULeW|h(|Pb;HLQZINEtP@kW#`?VFtnjSuH;``p38%kdVZtZI>WJ>3e$L;!O6RYu9y&eK$bKwL zAop%I&7EZY@l*VJ?8^Xhcf2MM=`%Gv9GBt$G+NLnBKFa=pz-UM=>WHoHtqL5r!W8P~Ks@t+Zd74BRUp(b z>=JOkk=@#VWcqG0OL%w;r^6#V#A$diGUv3$!#b6z@p=NL-Tey}vEbl1aNt zt50^n=6G*n!B?E#t?7}FHy7n*>(PU7sz2AQ@ZO=ZYX^>_Jhs4_#pg`GpOPpwVlQDb zxOLm~5)!J{PKY2qZ|xY{S%<%7W;r2{NZ|5 z`l3l}CtX<9u!2<{B?8MSlvrP;^&;rNrKn=8%0z2O`PWZo#6q#;c>zZG+TNmbb1p zMVB!)E~Y=^!X%iZk4WSp`SYHY$K;F(Rfl50ht zH)`mWaOvM$2o_cXrDmzRpISXwq8h24<0Cu4O29Vy7Z{4zHUP7Z07)M9r88Dafv1LL z3v&XyJ2+T>lzh^Ye+fgFedZ%okS^aZ1c8!V%Yu%&-dAF!Bo!Fd?+`aQCfyNgf2-#9 z4l!U;u-9R$yAdCzpwD0EW9CK8&-dzFi9Fm>^OG6C4l;ix1w`YJg+T z%cY)B)fgD8L3(0?-!f%3L;;7)bF#`&Ek6l4qjl`Q=)|0)_Wo}H>zQP&b+MF;q4Urm zwj&=n)#AoS=)3ygBqfy<&1kac*u_sdIb|#et4A+l3E8u}Ye1{{_I_+Gn2M9%oz+6_ttI5G(zD=u=i)-(e8O$-JyTpcRLk;#h#T68^h= zUlgedf($!&-YfwtX`5J3{ilDg1Q>?$*l`DF`|psDn`SXr=@y^&!x(ZQRRU=;FR!9q zE(`oSpui_9v;6!NE%N|7f#bAQy>r~>Jj*>&?Q`&H17QO0H#n&3WLqON)66o50>PpL^*0qr*_%og@n5d^>(9Z9 zom;p^!_|%V&7|Fg{%1hhYY+8!WQH4q7qsC1{A3$=GsI^-4IK0&6#a__Fo z(XrYR{ONtYEv7)n$Aat3~P!Mc{S(S=zL#_E_CwX((JYI^Q;08y;&Olz1q z=)4%O%l}Y!7RRidm#D0vp}}FQE)VtD;yijc|f{V)Z5o z!GSJGXm;1Oy8bl8H|J!Q5c@#B>u8~2brh3APXhn)LX7&>NHO%xb*1-{O$c|o zJyxU3`^9OHZ6a5{em}Hp4=#3B2`LJgdVJyyd0buBkKlF0B-kA%R^-!<$D3BEv;y;3 z2|YPV@JH`#8qZpP#C+5hoQFGz*@HnB*+{QEiUV^od-=l;Fj##*a(N|UrK&xfTV@8( zTjI5&|4XLHZ42OUS3h)KXeZ~?$)z`_c>XE1{H)lm$0j}z*BFT?mqJ4o$W-z44U64I zQauHtTx-PGomUr0;-iMqvGP)rZZZH_sZ={<6PcWZEhAz61xZQKY?)@5UO)!bsfECJrrjHqlDR$O2xfP5j{dbF;Ip`LS`6us( z&6Xdp^l*L95F${@t-$L|@(${;>+N=ML$_VaX>)}JglugNHM zUq)9L&uXd2aIQ$N>jD`BnGn`bKx|AAM#Z%~f8K!2JsFvf8$Eo0FmBFIU4_qnG$tfK z4o1cv@@W;j8&g7Hjk!7|#27Oa#{m5t;O(O_vdLXoN=Q7e(n)+%&^Y~V3%SJ$69|m? z0aNQf-!EH}#13IE<#Wq7+NAalK&m2D&5e`s9r)T7EuqmbN!**L^WVAKktKjHb2#V+ zusVh*yw-;c*P3m*ikp$+g@*SJ_s1)3hln^NN9G=Za>LfF4rjV4=M?qN&K?CqD3%+P zMS=Tdsw7)sqz^N?IZ-$PI;T}soVzrGV|js3-@C#HO|!iSqUSoOvct)q&@p*-0qjqv zi2Pd%Z)#j0+)4C{sd48wC!>!3rRkH$v9a5_i_bh7ai`-nx94s~0d_@k<_(@%?^z1s zK{rtK`)yjbPJ_w^0rq9PxVqgQ>qb(ySdk`E0rQ3BGiW~e4_UwJXQXw#*ejVXbJq05)&tp>d()~rA!FU{ zIacAoC+$qNcRJ`|lwQkvE>ocGdp(fN;53LD3)VPyoPBr0bA^O@NgM`tV5BfjpMa(k zXE7W9%wU?6T2KXx-QTBaWmpJiB-uzitX@_96i{J0d;`%l2X&gDMJRiQHD;kIVO$;B z$efe4Ay*mXzR}I(x?COU>U|Q4;Qj{NbQd$ zFzCXvL{OZd&b;(@qn{C=Aomp>Z9^AUnBb>V4P?x#MXGE7o&H0`$#cfM+CIg{Zm#P% zzmJ8?uf-cfKHbSLmD)IT@2l0g)h4Z0oXj|(|3C>Cb8{v@mv&q0(| z{gC)>TwJ08kTPJvdK8PYyYJrkTw3!EV8~0bz~cR2)2f|`*78kr|5FC;=$;bUXtNZH^j+N_O)*Zw-2$^VS9j)MVU|1mcg|V69FhRC^)p|y#wd+ z*^^KQ-&wn;Aws|=Wb?x3TEpF;PsOnuKTJGYeD3m3EduKr`{L3v6s1t2ALu3MR4_>o zL_xl}Hi=bH748gJhCV&)9bv&bGYYcfc>3p1Qxxk6g$$FYDTLGH<=bDJtryF@BOKx} zKuo5~5o{)o6dC6qRXI!3Yg{@n&ga$W;Y5H*z}qstPr?&J%&K0m2Zx_?gjWJVA0*;_Va&mR2d1{_;V^QYqDdnCR9&Mqn@IFKm>B-Aq@j7ep zTi~b;nh%R*P2ihn(Kd{afz*x|XR1F@mPH~|9+JV*M3rV<;L^p@^zhA#<*GSoj(+X% zeK2h(IQnjpH6S*|(!`f>$>7W`BzI9@G#5scXICcdJF>)#J&D>eq|#PiuM3a-JeAx6 zS_kqt5QdK2BWVYXps7(> ziz*Dy3)%`mS@w7I@p2QRh$kxIz3${Q-*}+TVR{dJ4J_>_eUC5L^)ZEucd^l+3}d>` zIJ0AH81R-0@}qzncOdX9?z}{L&D^%AqTulDa2&7$AhyctoUKn-_%1y?V3iYLst;~m zul-eF1pO{7;EE=F=VVBXLSFUd%PuDB+%}<*=>FkN(uT0#Um~80pT?DXQA<6JN1bvxKM61qBr@xB6W1@Xv0 zpIddej*+r~`=DAd39jcNwu!>n2piqWP$<6rT47cnVN; zLAHhq4S~ku{BS)dU#u8duEm16ZmV}n-G>X^Ogb% zmkDO!?50c^-cqx;U^>tp;p{Zs?f|^-+KBv{oiRCD;DK6@R&w=%G#uj@K&4X3{EU{q@M*7){#_FJje z1z>`HCm~X$lNtz1mDA|G(HQ)2-54k6=z7z%NiZ-}?(~Sx1&m6;2Ls)AIh;RgkdImN zimo!~sJPUwbruEW)xSs}A9(Dbob}zjGt4T#$xnHEBCJGPn?dTIOl+KL)~%M z=c`x^>w^s21d9!g-vFha1*ipV1mhg*v6jFNM*w|uj+=wM6e@)VKu&KZDg|(ZI07#I z7>982B2><-j4=%IEmPMD_MzlcTnF&Fy}+u0wcOMWI6k0KY~KSiEd~Ass}im+gC>Na zu4(0n@*)Cz$I{oXK-iq;vK~-l7`p(MQTxAKMo$HnpzgwwhR+@}>a&5?Ur_^Ni^P7f z^PW!X_FNx8F2Kz8>5parw}X%B5Z+(sx^B7tj5}p>!76plj`KNU=6W*Vwz~C)o**fM z6yebDTEZQQiM;12e!sIj(vGKr z7eW}@0g^s;tyD%MtH=d>hVx}441ZQ^$nm-HmYdOy2CVBC;q8BDjGNJP0^7i?NGV%V zr&8LF_)H5m*|jgKUfhe5i*gRx#$~<Q#!sIEBJ#w?Nq-X(iGjL zeNFOmTnIt#0pr4Qe>zEZQ#2>>Ugb`akqWmwZX!$&Mza4Y%y%x)5nBxXTz_f|dCFm3 z-2wl$xXct*u7f#_>1$DJBf~Q57&st-cMIbsMW6k#3zJi9#IYLvIohVbpoQX))>a{Q zuhG^{VQb}aoF@Fp_3~3ZuYGGUyK`I;^01h*V0nm5SbplKp?^%kK!M-jDmG>tT4ljE z9E_NS!VLmbbUrn+!BHf`lRp!bRX_=h6#ak1y?0oX>$5hhSP)TA5mBllMUWyQy+lRn zMLI}RKvAj?I)qq3K#G8%w4ihXp-FEl(xikIdPfL^5(GjCBsouTt>yadZ}0v6an5y} zzn0fBChz-{nS1V;x#!Ye9}Lh=W9Z!f{%G5NPTDhI8U_4^ptlN57#Kkj*PutH-8#N? zX5fh9lRQapmVyJ`w=@ad69?X6a%wK#ue4W@n1?2^SDm}GudlV@@V>m!{w}V^w)~5oeu=W z(j)fCJKUBv;xR~-ywr zdyDpMJ#^hcZ6xVXwV-Kjyj*U8Wn_SMr2mB1Q;n<3h|N=m!yMk4hgXC;bwp%jSVO-n z8tYY2_?EQqC0&}*&wW4q^wfmSL_l`1Ywo~A|1D9Vd@K@Emc-BVj(Fb3(zuyqE;`s6 z4_aGhI7LpCjcdCljI#vgGi2|(7IQ$SIB`vQRqAz}T43q6=HJKg#3@NI-+_R>d8DQD zzBUV$hHulRj1(~}zm@-a(ppX;D0pf2ZuP>r5Zj>MoAuBsh(f6HIPZtgm(zR$6>|d5 z_Dg($e!1<|oBrkM$z-Kl&x~TC8E6%m2{{$@81%S>gzVLpkKAD{Z|#|NXndjy6K{cb zdntymqK4(IoWo}&Tdu%$9sMtwa;+T9_WZ=z>AkQb$Lr#grhBn6`1IfwjkkJt z^X5s)ZqU!$j3uR?OYPlzuLiomR-J#aYL4Uefc||OPefhXqgDkpthj!xp!s4$wFj>U z$(T`Fpv2`!Yv(+!D5>916umi+k#5^)KWsicq?ZBr1Q7nx%Bd?ot7s|JF1nsu3n89k7f7Fj z<$w+N`^fRE{pRAc{9z!2<5hIpJ%>j2CtW>A={OJ0Bm6LfrZyGVS8dvVG(KKMmubL) zxz$j85|L8DS|t6?_Vis9_qVYkZew0~O!FJHuScM7-k$@r0(xVjE@EjIX}ErjHb;xm z<{RniMAgKZ@DB-=`aHNt897;QvYKA@I#d$D@`q*7v;32YJh0bBI8xLDvASbtmyOkm z3No)Bh~uO9hnCNH6nTy{4|s+fzP%_!8Bx#i9693`JE=D`b?IV;F%WcsA3((lvZK|H zZc0zcBh{5p^v)cMw&5z%UQayD=_8DSI}27!nLQOSYM3>(##c2OUHq3T`a%CUQw|5} z{k#k9992i3q*WigzXi=O5TZ8QB#|pDl9H^~=moa?-|x3e9#&kw#jLaRDDYiwKb zMd4?Z9}VU7;zx;a*WuN2=&J}-2QMvbHLxzKFnt7c`Z){*5v571e=l7}U zjhS;?nmZr0Mtd*!esBU!e#lb}b~Aw?zSr<&z&_Q+@QjJ)9vc(94prmnyVVXUtMA}t z9Y3Y(pMU!6BksX(%&m&o0?iue(9xPMPEq)SiZroJL@YcwwYGQ2?bTU7j|~SQ2iS|W z44wVjCDz&}R7gp$7vfi|!O*S)JRe~nzT*)SGyhbj@W||S-RgPNiXGfQhc}-XS<~*m z>O{Rm7vxCLBw0D;nLNFKZIPB{j(wVk&xBr+bU2UaXY~x;>ZY6e5JWQ?mOFo*Y)bO2 za3{y}7?1P+O1MgF>gPb#qU#0cvcgZD%f%%EKHV@+4fnr(wl(0>H^b& z+=$KfdH&0byh={*sVLnr4e_v%SE{u18ncJFns#PBY2U)^K$WIoa~4BX2BQDMr_H4s zeaAf+H)F7F*B8Y{A+Ok7{&~E=lI4Fr-rVWAU3U*1)w$i7f6Y8oeYkh#TT8_mq8-s! z{>y-~jJ>SO|I5FO$xx|1?IUv34)x$8<+VO{99L36(W~Ucyus{xQEhE4t`v5nY~TjX z^RT@1Qx{cvQ-TYVQ|ugApOtX@?eii>WB1awpIauX2@UD#4GU|#7h@fTB?f*c5R|$r zJI;e*9Pv4X(iH22*1hwcf@us18i>|s@+r3sn3u_4{O>7^Y=oFR`e$`)U;L5IelWjq z-biqVh#e@{DttzFKQ>M0WDf+d2vi$w!7wEL+u=Ldlb}>%^vk#sZsqL!n%OG)E%g6;oapqSG|r7))T=&{?$6$1;)d0lT8<} zCw?eY9kKiL5)2HQxOf4`1Us=#h6LwxufaOrWdVU;Tv{jd1ZTm{tpEl|-5-lhMoqlr z`i+ImPK+Av0K+n3G*g_*;X0+7V=JN+0xyN4wJH9$ITC5z_vJKj8fr=ASlI2Cco0g& zf4I(=!VijaILp<49O?heFn?s^m^;lzaVfiCkU0(ee29z%L!Fl3&5=v{Jt6zEkA9{l zo_)s~c%bH4YVN*a2$G3V)G_l~7u2*jS{l0uoO6o6;;()?*%(Zolt_j>^>oX%kyqJi zI`$3`u~NA)og1ATHR1Fx2lnYW33_d}xUl{b4M#{ggA*zyBavpwM7+c3yEDbnS!jI~ z&3D_jKDjcnK3M?Mnwdpok%P|MI&;%jm`;-KF?T8bg?q916_u56CkJ9X3+u z4PiT0=FhTH^T=@6DVaf@M(ChOS?LJfVq_R&>jvY`NKu}N>j;gtwD?EEu3yZ)7~M-1 zLY5iDj>(OOoV$=g(w(><6E{>v2UNLKc%WMML@Q9GS2(_CC-CZtZ!6ss zUr8N7`&BpgsORF#0_xu$RZ|o*|ham=7=Eo)gQ1`q7n3S;MLqvx#gs zhyqW5rey&8>2p%!Yd${C$5c;H61jvpfv`Xjr=KSg`_;o!y}vBIys%}m$n~u)1D@WT zuVdS_g-P+Ov}P&#kmB2G7FyRSyLC}fr0Pq3Oy6f}511#Wz@0@`eJ&Pgp2`_koIOoj6~CO12(_#5zlOq|GX8hz&E+3|H?$ z&Fi2mxGKNtJrr`rNDLhkqo{qV*skRQ%!1=zH(Ev=lt+^z0!&$-PP+Kl;bC|~ zX+O=p;n+To%^RbI4w(F^Ab7Z%PifypO$oZ+!>Qaq#+iicQ)Hw;zrn=CLQuob!QETf zrIXHwLmb$cuD!5-N8lR6`XUeH>7e#{T0m9Q273G~K}xb=5dcuR-mg4r-)rtJB4@8; zJA9PXj=eUa^i=GVlghrlu=ll7s$5L{m0tHKyQ24AsosV4{zA!e-Y7R{TN9KS9nVeQ zcX{9OumI)eim`*vh1T|}XEx=&(43qXex~cDvwW@5Kg)dQ%mkg9@mQ1eyjVB3%#ys# z?I54}Cbid__3U(^O&|y;)w#2Rf){G*F&7qG{sAm9>dK_G&-pL5u#`=By0H*3rz0sJ zKR6T4S|&2MIkt)WnK!7l3(a*Hdyt}k8U#6U26`#=1oX1rm)ocsAlu_Lh+AC-{U1l& zzCo0t!Z-+sR~8G5mcmh<$p(IXiNb_SMz3Q~f+1T1xXm&SPMJ?^H4o`1k7i{Gt)DQv3 zB8!IUXM*a~dbS6w_D|QFbw>Vas|}VsxsDDQr(h`_zBwtx_Rvjf4->+LP=^T9qy_Sz zU(guqg}pRT{VLk|5Kb~3ltimo9GQh==986QlLsFr&mhW{cAetjin<~4E;P<1-%uyF z{kc4sa}Fh5 zSDi}X@UykaVNOv>76Zu~7UE9Z%U$T(%U|-zfz#${y&@v+Y8?i<#by#ziMhp0P0E{c zkF<6oI$T?x%ldlJ6hdM=7#{F#6&?0;`HQUDxB~N|ixNTOCzh(Y?r>}coz^6q+u!KD zMil6QATF20SZTh1b8;j1EADe&j|j#ic2s3I*;^JA6*elPR?t#vkmzUHNZT3kc=~_!f*(=pab&mabowxlA4uEdAB5*dNG42k-XII1?AV zr0rz)sJ~OS8B)b^Nr-UjU3%gDSBm$439O#8%)ZQ53om8-Tvdcuz6m5ZAt3U2i+(jA zRriJ9KB99)S3X_pCIO9TCcfZ<=Iz=ILzHqC#jVY`SY+gtzA?Pr5-hqlSwH2Mzd!yi z$sl@hF6;|5wvOY%VD;wfuc&>!hYqWA5{dxbRr`fihA`uXtFfKtyn0tITBa7hEPybj z-L+7wjhcn9qu5ciWKwZWX$p(7>v4y#H=<*fpkUDD{UYY4p~p<^cP4LTh6mm6of!OX}rQoP=Fe~PaoA4RKCs>d%TFcHupD*cXmlI!WC zUm;c2`a-+ap+EzxJ54X;B=Xf-v<1ANb4J6-6qo5wpLd`CZdLggl~`atPbMJEADKIT ziW$_oPC3?ZbxU<}@D-n_@j+jmlej!j6&w3=jFi>U_` z81uZrBRrhK>O$`#_<|M|;(5w^GYVN#soQ<9T+_M4Mt<|$PPl#<(Z`%OQM zvEOYen&o|*?^roPpT*toPG-3FndUAH={Cyw#F9VP6-@@86LSw6%r7&`pqT2CxINN7 zHT3k|4ak8V6k-X>tx&ezx}NgR)xhRni0Y_#uFwqe%Tk|*aMVIP?{>>_;?LRcOxcFx zmebkC&3Ttc#gZ>uh!tCiDFH)#mGY0|K#T5G9D-|CNQPqWv~?K_3yMZ%GpS2D5-+*) z>Q*tOsj+*~Qsi&O^7&ssDp!?#Nqyt|#J!0t0taCQ24e*dEXE+egqf-f&T$g5zsuqF zRQGm8a!f)N*TUUsrMUNsx3n|OG-Rr3tW&TRy^k1U3I|Ih78hijD^W_e`Bi+yuxEst z#$sdB>0qXwJF??FuWd0jovwC0TBPS!DQ>fdR=?zAA>_Dd5lSGskx$<$E+PJvK9>aRiIQ7> z@pBb%nK9rQ`1gA8T-zUnzuh^t6yKeFXG&1H{oM)ia46|U)PY6DHlPFMl;7MP^!M>T z(sCHI0PT!z21Jp!8xMivuC+dvxY#rK=(T|oTjV&wuZflyBM{Z%ad;k~Ci@ZIaYGOc zp&g$p&G<4l$jSeYctKT^8pWL7C2S+RWH|uYm-S9U1=T4bMZGd5llcZUPLDD7Me)#u zs2Z1+alhs%!51t>wevn4R*yS(-IftHqi)-)=p%B6WW#Mc?o%A~Vop*LL+Ovie#L*G z&`=KS(r%UQ5)(#%gqhP9sjXr0KWhN$;&_3$#fAbhx)qL+e&P(SC{RSW6}yf-=wHNM z>7k~c$p~b-6KJ$3nv_JoKL+i@O>Sj?islSkwy{V16)b=?zhO<5Ikv;zM|_c;(00>! z|Iw;$rtWQ1~o2Z%YPp)4ZHe=mPW~m6Yo$^93MU8DM zN(qlI(9o06QFy`$`sqOC!{rBVbdm?35~TiNV1G|N&(pnJqJwh9I>;eR&`JL{cA{Y9>K4bt)VAR2aMf*-$T^_ztzv>?zo=2G0~hrI9&}6!_~{W zEZY%H`A6LoE6*h7U6SMraDAL`XSaCz4X@>Vr!$u`pEf8ykrASPJGS7#6kI`*DX!{ouXa!)(o9W@)M92I@tV*85%KgBVJfJT8R(5?5ITb(w|mL12b z$6b;f7ZXO_AmGC_ZV=v%ZzY$6~$ ztjVTP2&J6eTsoh|v}BqjFrDk@#J%60yRU*BEYWYhMK-YK*Qf%T>M&nue&p+cPgG+H zJ57BsTe^Qg*eN1bbsL+qz{GcRE1J*yD2m_ppxX(GqnwEf<91{02~zRSiB0a{0Ovk5 zi5Qmlz3J+1Lo#neywqE()x? zI)f#D=Tg&s+Os`+UFstkR#y}*ybeDTem~~yFX~gC+W+s_U+q`$wj{n!4HN1 z`p-_D0`sBwA@uu2RT)yq`zt(`hOX8dyb00#1Seugc=lLr zr>oK~FxSVAe-W#_t04f$N+_6d77d*y$K3Scmmk6Um<$H|M!`X9J#kNRKk4O zI5x4;_bvryV^W0i7vA2&4y0J5p}??39*_f;*-w4&aPWarMAPghVpaaH7w$M=C7Q{N(3nR+ z-|ca;21zc*hAxM?_ieW)lYNYFYgV;BapBsg*MqL8fn0>!o~d_@&Vnzy;;UPmAj4~9 zJCy&*JTjwgS={L%eqLw82luOmJ`PZ1Wc_5WYion$veI_JI_xc)(Lx(BSmJ@ z{2%mV(COfWsPED5AwT-#u7Wwu39VU}lQB`MB9W8y(T1sZDyE4&r z2*&ln?^jwAx(5Eklu=W5=j#qS>FVUzwx~A|dqW(-QFJd>wyz%o7t6MY7jh-~?qTo2 zC0FEZ?+jFc1Vu&d^;J+Cp~B&wGjc&`2)S3{I@DYXgnI9$_;e}qTP?R)Mk%-A{J3PH zyFZ;7<)3sYF`@lz{Wl-m;LQrY^gtL*uPl_ZApQb*Eee{G>>>Ul>F^H2zf(B@-`CK} z`{(jBMg}|8nEq;U+q*Ogw@7Oh(-|HdI}@f%{2mGZ6d6VxX?&L}7UDVnO6O-7?0#(~ zymqO9f0>9q4b*;$uLlMThu-GEe;Q2_ZSy7|6&?FM#nl8L+VS*{Qc4+9wRU8M(dEX z%A48KBJTt6w{^y#Ep1gzqVd>y1fGbEsWxOf)e4Ul7W>h6|6TiB+)jnC+a(3Fs{=!6 z5l;Ob6%9Qg27Fs`@nJbRXwNO*`f%c3YknqVi*P;}PIef#IwO0GmSfhD+RTFfdr68- zq0`Ts@HJc6VsRa;nCbZ{zMp8)QkfNHoU)T|Pa)wcIUC^CKqzYvcx~x+d%tAe+t+Z< zY~%Xw#teGD3CT*e&BfBzQ`19J7gDB^=JE|sdMR&*WAYuS#vxMm>#p6Y*Lw#&COw~# zOdbT2zy%xM7CmQxmQpi6d%@{JAUK{6BWpTYv5a;0Ukhk0 zlP%26*N0u|oX2ZPO-Z{eKnIHg3S8}{MeBB>vf!T6cEL94H=59J?E>s+Qt^1OeB-&r z-{44f@=V9aOOO6BXw;Ui@4HY_%%>M8S6@;$q3qwA5MrmY?z>z%hGwks?TT#Cuw!N> z>46`gj(}V$bs8?UX$t@JDQR^Z$h~L_PzJx~4-g^Z_=Hiq-V`6MJm0=Bp92oTS&VTe}f(bcdRiO{c!ZPdVoaf=SOSMpUshu7hV%iwIT>EcB9wdZ;XxUO)pNg>*!>PgosK)! z@IU?4zq7EvFLw%@Oxhf0soUy?qD3_;oyMxS>nJ3bQ{%s-N}HDtkf6@L?c(o_BN=Lq z(Q&F@as_GM%j8YqG$8`lw|`4U{Qy8u>Q7$Ly`4RYCJBLBrlaHd{ZB^z%7R4!!133L z|8C0vdsOu6{{W!B_vHVpPyBmwbc_CpZ&7i3ivYTve%mB~RR0ghE{_=1C}kC`0Mgtt ze@Sz{zQdz0c4+T7{5MeO(p3NXMrvQbZV$t*mdBHu?|D9EUXN>(RMB$?E<}D`Scxi% z@qW8-+F(xRdO(gq=l}E!59S>{%@k+ZF1@eG1(Tt6`$hT#ZRzeuy?jrz^f*u>y^==g zt4W3|(6=v+RAq>~OU*k1um3ko&;^3@-&>)fyG@*0K-73{wc=hLu}gl*?cyYCJ~xB{ z*~W!i8yEP%Jf3HT>7Cf#H2=5%%h!ND_-SN}NBHNzrV#spDa7uzI#-Lep6PrI7N5qKgsXp72J(8ln8nCc?0n2aHCO|hX9W#mGkn=PQ({|2v08b<%O5LWM0t?LT7w1i9;CxbKderduO>=3yCx;VJ^dW@P-^mr;`a3r}tA>F72g?MyNiL>d0S% z7_azG!)U49-x{s|zkMS8#sMHZYG2?H>}3GtPK#cgy7*`C!9PLYEx=ls?xE9fE47Ek zj0UYln*{AYf|-6f{OFDU(=`8C5rd@s7fB#n-d=SJnrrUqJi?o&FWEVmeE;RGL;uq; ziT`!{X>5C7^w@(08|Wts-ImCIg>iqI3~mtU3H`1gq#Hl~+Eh|Mp~kTIvJhR7Lj958 zqyK3%4+4sTcP}Di9%tK^wCL#jVDpR()SmAD@+2X6VJ6Z3+#UoBsDb|9KKy)H_yAXz zCPh5S?UJ0HNUr~jYV-lM3Mr^?k<5`VRm zPhglTe6zD$Ksn`_q;JJ9~$uNum{UOedNeTY%pZJR+_+MV+zkC8@GuIaK z>jDsv2u0%DYnghoK)hW?;^RQAWO<+I#;|0&L4a^`O^c@zry5wSj&V9(ecYX< z10fl35b7BrZOID5BUASXI1DjzcXt<d*AT5%qLExfe- z&c;%u(x!+C1oRqSjqoMTXJQ(InfL=%Tlkk#`*KaE6@PrK!q+ZvP6A({NZy)$`gK-! zp+7$YD&;ulhp+iH-2`9nQgO8&gHvFmO91fW$97sp>*RM9i|z5CKS*(RMQKyl`HYas z30p_!kdTmBG$P;kEQnA*CqbL={_TkujPAx8x*KPhFco9SZ&7D6D;e!y;#PdtX0uQ7 zc@=)R(at1c)_Vurk+jpJ19{+Z);N$S|aUcXS*_r7L#@REa^ z+REFD#b{3dl^Y&QIDIvkWIDkd2i1r9R$3Lf)NVgaOjQJMTtGh~>k8plp5piETRA#U zMn4kyZ!{~7*8phYBe zBCstjsnMSU)ZWFK1#m##h(DzsnD;i}y7y_h{8!jqs_!ooK}=HSIOx_YT((%!Z@IHv zmCveI<4X`U%Jn8-jN!i;SQr|9{c7R@-Jo{~sn0QXkvaGL zdLWc-9lxE;ad>|15+`iE3#@lUYQ1HRuZ*n0*UQEzgSgb^9&PW8Eze=o7<#1~U`=gM znX^}IUr%51=r%+eWq%!3G0eBL7)8lIXZ?4U%9e|>etmWsw@i9~R@ihO&r*LUNSN!I z20J=l3#&RxUTqacEABXoXMjdML1iw>Do-b<@!D)V0dcrjmp{opDnyrr#bT?Po=`}e z3zutfImlWf?lLL=5hejKM4E}SG8h>38n0>M^n1^rcR~Kwcc$5QISA0zYm50fMEFK8 zTJGn!@|Bh_m|s41)NdN}BT;@uz_Y^ahx~qEg17=qxIDl;soFfl%$$9adiKIkf&&W0 z*K8(BIt@vU`%g>%>{8*vaOCW3(l=5u%+`B=>&;$HW#=b>7_=#j&A7tt0mdwG0z82x zV&PM$h#TGzO>7fK8~9<~z`)U8T8e;>%N5m+H?k+oCWVZDeyo2=Qb$2uB6WTDgM>ru zSa-3VP7}u+yWUKcAu`sczZk8EtdiXvfqJy*>nO}9cC~#F#}wc3L(5Lj-HA5aV0d|95CpkCpnoZ-Ihwbr8W#a+ZWWQyw2X==+P7<65 z`!BPv+7e~fR_YmzRg$0`GQiBCuvd0>*TBN0R~n9I1G6JvRX&Bqn!h14l$2iwS7j_18 zh*qGjcd+0Jf?m9iMgQfI3Y;sl3f6eeF4w$5?+|{Va2hkI#Q+1I0`51C$-D;bM@A%s%p)%D`v>uA zS+Pt03+yntQvBE2rQ|$oR=&{#m-Gu*DL-J;brK}oi%+PWpo~;NvDx~WzMQqz4I%gI z1DEP3!L$`&BNr|91;)P z&Jqrpb4WayxbC$b{_e6d1DE3NmjjG1TOs36v;ro_P!5|2oo)MI<05qF($>y61@(M$ z*agC2Zek)0{y$h0L$C#h(8&rr2`;s|O;q9r9Ipe1kD0KR5rY~x&_M9h>BHBCsBL+N zJ|T}v*v6nr(%s|NUEsh+qROX2l*3p{9Qv0(264Kbo+=maO*Mq40)c#Rij1{d!TI6}*qXF|o@ZLzI9B4n zy$Z}UGTURswJ94ZN$)y9-tN{A^>EMPD`0>FAQ zi+E0!G5;rwSY(}kLg$d7NvZDr8vah99+$XJ!Fc(}*d#jB&hL&~%lBw>Tf<)Pn&5^- zgf_4|Hg%u-7=(K{0A#pLVXutGX@M_W1%4UK4-QdckojKxF!kK@3VH(tZq--UUT}yP z=*vbu6Kcf5;eBs774CX@lL-BCo?++28~rsi-~kiQXv5`KRaLA@L1C?M6BoRCs5?tH z)z}J#39sH9^YbVp?QD86w%qtc_UXyc0!QRkn!nstUCaUdepJ%fOk|tuZt=r!FX?>G z!iejx`1Wde^0miN49gf~oF5*zg;XbKd%Q%6lQwlcP5H$0_5`T~Zk~7`(e@)oz}Gl} zQ(+`?2Vg86xut8WNym%NxUy5sg`Bt7dvt<&YYQ%GOVda?4x}{Z()6YR^RfzTdnzZ& zPU{WG?acz%*ICs8q4;|R1q`TM0I9{%YaR=VWq0a8Mmqf7tJKxt_-DR;Hzfz;e<;4f znI0b-d*C9*2y~?|(H@MLHRr5tN(E!G@#LIo1K`*8qtmrNTE4KK2KOzm(UCK~%-hqM zD;)qnvzz2W*K);vz@$!bR^tZom2DOPM7>whD23e@O0h1J;q)p7K`6r(GP!qoXVM18J*k;>xMLOz4yJ4WjZ=` zQ)>up-h6kuy>FQm71C6!j01CzDr+*$>2800^5VKK?r}~~7H2xqXJz6mSfxAo?v0Ax zGizw>1|aF^D~cPbD3&oGC@*cZ93^OvjRk=V*TIoL#*Cr={)TQDp%TVA5o=dS4XPGd>4cXQ&;5-T<}(KQVDi&^lQI4H0)fi;>C4O2?$3MjUvMMg+V8*~W(&i1HVpCT4P5~Hq4G346crosfL-sJ%N?O&vgBDn|_Ri1gi(?w-E2*uH^mY*%rqtW`L)+VT-l~;jp9f2(w z+?0blNwN|hGq(Hw0S7z;hqq<50|NacfrBScYf%>G50)U@mqWtFXIPSM6b%l|O`fmm zm^(N7#zRiuD+b<%I>7-1mgJ-o*kC(_&uJ{*?{G&O7Ig4)*YFC5kr47z3So5}SgvV> ztX>gCkfQ~etBeuAQr`{$qDBC7jsv^~8+IzAf-n1N5D>U;j|0a{y=6dQpnUFAD6TJ$ z>b8)0^M`Mb_Xy)bEFv}LojUIU&~Z*}oBcw%>lXGEJ&UFPuZA2uf=({5=G%r5pVc}b zaIjmI&Vk$S+gyE59Rl*X!!F|<{T4y&Zm)@LHS-w>y-=~uoZ*DHIH0*vg~K3``U#%0 z_T+7lGvSi+bOZuW0C#YybVX1pun%_06%)_t1&vW7=^AmsOpT0UfWK-4e+f`KvMER7 zIjB6j@JiaCY-3A-v=+`GM@1ie_CW3d#Afaix}%xHz>$9sW->Ge9_|YA6_CWk*HLQY zWq|v6H1s*!*FTw1kEvLn#4UPWV33#v7rF9<(k2?0o|6&e+s+AX6T{)!>JIwo85n%N z_m#$DVR4v^gObaq20SRnyZ3X&-SV{#x%}!?^^!v(l-#knbyP=^+`@zsqrztZ`Ry6t z0AI^0kBTT*Yt# z5K+tOaxeTC?gQ02Nvi8t4WNvtWNfBK@*KRtn$y_@A@f zIk?*&H*!wq#8reFATIjSPZ6=l*(5cS_dHBsDe`r#`qe+0Y&ps z5f3!DwGZmtFv6G!H7&oUNgVU!K>CbV*Fez&4MJD8BKxSQJxA_X;nF=q zu3>>MD8Ss1&9JHqAfBdPGj^1SK3-4%7YL;R<}1M6Xt#tdfd{W%ENbnI^;@n`Syj7AAX!m(VWDlJl>WXF01aOONr9WuNAXt%nH?G!}z_9x3Q@5G{lP&OS9nh zS!G59qZIPe$A`5F5X>a*Zs2jYjoAd3A*>!E5QoX(t0rDE$hTtdtMT)~eDsx~M(!Mx zvLnp7Vh$aSW=Cu8}ruyyvUQhV`32wn`$}@79qWNgAnVT&6Xz`2cUTStVQc|Si z9;w(R#3=29AxM>oFgsPaDJ7GG72W3vB-+03jZlAc|cI z15lw>7x#6ZZKgwBRJ#*`Y!L_H$7aa@oW2|ctm_x3M${&B3a~wWlrKi4EV?_h$3cgC zg)ado{;=%{LP1ni2hj?ewg7IIuc8ADR!xlix_aD7L0OcnA$9fC+{3hL%@wRXFz#vKslXFF#s zk8Gd?O|$|CNQP2T({>Y%+}VQKHT%#rnSdpz`yh)f2cdvRSw?)H0@4+iOr?}|>}ncn z>2RjVWQ<34X1;G<{|r!(s|Q9zhl>mZ=y3HI_wFDh-9s*vr77;Xkpc@LhNFa~H>Phx zPs@#jLi$mu6c6+U;w7qPa+~(j~H{K>)?GsR-S_oh$||bKDS)Bu04wM z5m`JMUiLlmJEo`+@EsJHjb~)_i!0W-2 za~+$$Omjha98Rf8M&l$tDdN}1C&qlR93B_!vw(jvsr9dbF&Y*S%MBD3 z>YV42!JP)&&=~?F9mp&LnZ!T21|kz$4Eq`Gc~*sy!d^UXRHcmPynmx9=H9xMwamk~ zGI%%?^^|2+k%#Wk!ijb~r|K@e0w4nYIPlk=$}E)m+H`*ukB)dB+JgrArK zbVq6NL`csxqHcSZO`?P9!9Zka|I<@3Q|%_X0)*=zBzn1XmqBjvib4S(D?B_2HDj<1 zK&axNK16H{uob;ox>6%gUWB(ig&XyBi+uxMV3=btkE&YkJ~zrx>N2kAy>gEu)v``- zHqI)*6g*kG)Oa<3f~Agw-McT|@>P*#fE=5ajKuxk+&fTZ<3PGDh?L9N2q^}mTq6|@ z4*+}=#@0ympahSE>JG*B7dWIK1|E4!$$bt`XV&xKQl~2KU)JJV0DBlq-Kcps0%$*6 zX_hc`$IaN&W#ma~MGsng<&AqL0Lyb{%{*=iL#_bs#WytE0DV`%oG^mvDWi8S2dLFb zPjo-9@R`1ouUOjZF==`V$oeH9NQB7|(W*&D3jEBvHU)0)qB8I}y$MUt57B=v6N-HU zBjj`iUICUBhs=)^vB>F2AN#?M4Vgwn$jrW{LR_LdDCtU7i7?8SCP;qLfSwNZFo+v3 zxUWP|`{?}ooID8gNwm+k$spcy^O*0x%@F`dqMQU5F4Wk8wbj+$E4@{pM7~ds=?PsP z$T5!eT{Cv^!ZClQ3Vf;6k63$UjbSltxw5;!QD98-kw$rXqP)O6Gs^&5r-wb72fuiWHE{oe07a86+0GhvfH24IM{PR?hYb{iBB`jtPDj=EU|h4 zE|0H_v4>xKjwnvw1dki7DkGX|8F+8oNmu~;i&A`xafeL>^Y^0nZX>Wt;YDjGC&~zj z?g{v#Bz1uFF?A;ES_N_jlxyAaz~#Z>OxbLsc6-SjctBQ}sRRV$@LlBlN&YQhu|XdB z@rAw24wz0GA^q?oWw1n)e-G%fvwjw$IJ$V8iEaimgAxzzoIP^L=Qvqr$3B!l53Be% zdp+re_P)J)^?)1v=4QTPVHW-cZsF&|*B5c3R-BnZz@iT=WOaS~7Rbm|OCj$d^S}7A zRD-~F^4qJ8$X=-u;D9`qM+Pn40uBaH9<_k3;A4GrR%{9oF7i{aF9sev_vzcB(qa)B z#3u$;f*8WLaVl^d;A~8fv&^Zzig52%18j7br`#l<_QZyoUZplGgMp*KcT(Y~3%D(* z3<~R=vBG9KY;yvLP^NV>;B=OUN{~Bu*Y`y}q?iMbCEg)j5A#$A*xIu5FaxB13a2#{ ze4aLpAOI6#&~xzug_^I>aToJhwbd^Go)h@E@RI;I76S8!qm@_~Vc7!EDr@06awrhI zjqr!!1;kPjdbG-m0(^f5pqO9c5SVFC$b+hQb#_Yb;S}Ct)+nW*$^}3V5GmXrQ9}kl zLI7!WS?JqJBrITfAR7ZVge>3nxsQBrwBfMX4|eX_<-UcFwCr}U zA{Ld>KO}~$9EX8w8(^+`%(MY8SGoPDM8j;VM_aDFrrW%5xA04HAs`=0INvWJFz+!2 z#%9`7o{z%F>rJv_BOJCyXw*c^i&cRQo66Eo89Q#@mz(XGji#y5aMHz}I?=M2g{Oiuj^tkaw?>lr0C+esX>p$yGue8|D}?C+&zhVDiGY=b(Az1Ss}O<57Hlo`X0(=iI?H+r9~+=%yp$=>O>f%C-!-7V*#V4h1WwY;$E1I zLSY6#p#mVN_i))VAW9V%Ol4_|D5uJoN{8Fv-O_i!wcr3=C@G+75prk@FpA;Ak~ro( z$yn3-La=}GqF`XUD5fxRLo0r2&`=wh;yVSx1-JUlT!ecd2|UIW(d$cJnJu$P@GXqe*;7AHI5F-mF^6rSa@ zWE?gEIR*(5C?NFl>wj}jd|el~6V!B;5O7d7fI>ee5ac%V&N!nU!f!#5i6)ymb&2$6 z0D_o!?)Fy*au78hP9>8p4&BtUAT+Nl9P5V+WA%!=6yq#-FIJH&0Q*HH1h>h#oG3+r z_u|2E8niJo{%F0(&DIbIckan(r?T>%S;;A9hHmT@zW|IkU_{svDmV@kym~W)HkXpC zVZT1#qr%ek{>uI52)Gf~GVVi8J*KI~_XlpJZ3_!9jTyh-!i1S~MMJH)eZ~j;sZv`i z%{|RI!~l5>?~whcHUdmNPuSX!0f)!p#J4AD4~TX_;p^Fa?0x}=_%=m`YoP71V=hj8 z5hh|6>ov%7=83WVn~xO)Xe#^29Pb_RIB5IaJ(tX&YbUr zDZAi29b=Qsy&ZZ61c{l%$t16_kMPpq7&r(NVgls4OC)-48R~CR;RosE0s_F-JT!*t zW+hRL052a-ae&$OLy+1-rA`jD5H6peZ;86HyHs^wDxaiqlTeyH`_we~+XmV`F`NO@ zl)ilBD0#b6iP6KKb5QUq2YDNS9yx%=0o;dM=qWj^12T>2M*DFI42J(XvD3ImTAXaE zWg+3{N2goT4|bNv^Kpzd7^eoWlwST=3+f!A7x&6%z=(Ll_0|XQ?Gb@~P%-#S`wL`v zSR9Wy>5!tdfxa*D6+4aa3Ihcv)T$oy7&$7cI`a?k!o>f!=`pgh5&GZ1ezJlPNx~-0GRxAKO-wu5ToHBRfSGa z07@_`fF}r$kSC>=fKZQ$<>r@1z$h>(CL}a$3$m0dXf#9WfOiH#gc^0XKvoeXHR7E= zniy&L1LI%mg|7uj&}(T3WBD{!+8G1@m>rPDc?^&l*nF@Tm4MBuL?`f3ayu}oDvTZw z%wVSGhfiAJl}9}eU>;!%v;3yc<~;;?a^NxaIdW1JN$WjRE4ynTRVeK|QqI63D{a{f zY?jz`Q-rZpn%m3|K-v+iF90Y{dYqXQcxxA0xSKr#*kofrq(Sy7fVM-!nBqQ_Y&!os zdWo|Hmn-G!(3i`IejpEe|Jy;rY-gHUG&Ko326M#-M_~YtQ`uI<?T zg#z-Sl&zDU5K*gIe~=V5HtWsIBeog39Ko#_LpVxqla#ChLrpXpmPE3o1VHuCLt~#T z-vmH~K=MpC-)KiMONv&35z`#R$mLwuKM1sg>gxd!6cJ@jw2NZ?-EE>*r#)o|^Sm`v z054@I5D$(10q?j+IzFB2dDQC?L8?2Mk}Ee*p-Vzu7$$$9Hl*=H{mg;)jQ}RF5|Q9s zspcXEnuqAWOCs|F8j5lwGT~$pVQD_rf25SrrQ7&>$Z0<6_wN!SXgoCK=6Z?c?jw!=}`L>8GK=Y2m~))ZM?fg zWaLfI0Nh-yRfFMNH0|c)lT_@_3~u?8^n2-MoBSI!O`lyq@G61|dm$Dg8l zCD(S!xC3yQE|**Ktb2&@C7EN(oKDU;BY?f~{!vN-SI-O1vq!}PFFuwbA-OcjhDWzv z=A#wM2TjiA{Px<;Zk55`xtOleGsbUx`eR28xz|%7wKIi#9BzT{Vj;lghi*J@LX7iq zN7z=7CGh#LJw{sq(XStOco_Jc!)0kA(-hGS`_5bU&QQIqnT3{#dQc;XPQnPfieG`| z11*TYV|NMh5_x%T>>(}OY_4&32M7_@Tf%g~3l*lb1TVY^BR zn(@jmIYr<_w=L?KU=aWS5K^@l2_%5M0vXp|rq`GtoEC%NA=GIB=zuxdV=ai?W&wg7 zlnwMtFUWRNG|EWr>`=Xp(7921f!|PCOK-X}?sexgpXD!(s*5_@q&e0}m;`yK<-XJG zhlgtKG_~xPb9?RDIXF-qlNGEn_4ktIoe-c@n}W+%SpiZ5@B<#ZLI8~%?@^|~!(6yf z4|p)Z1`~m5#eJg7lzOg0fjPJzR9B7MCnq!c^VHLg&)Wg5(R4veI9|~mvy$7dNbAjX zI{_*sof)$C68QIWM-jCZH=jtEQ|*te_dt&fW@%k6J3{ozu)QYzEx z4Axfi9XcX*>40*|1QdKAzCGNctS8Y9-fRKlkQwt<+m)a~AmLz6fjV#W3{%go=1A+% z-RtG(tX8s*$W58_*M&%rr(dwUN`Zw1WYQI8R$BUuQb zN0Q0`{IP7+)=R*Ft<^hv1-u6ypx&HYRFBq-S#uBDCan*^^)?mfl%5KR#jBve5rcs; zRyF%KQgoJPDcegrwoIRQ*=Ju&vMF*hmJYDj1}GeAYxB7}=y+R!U8GOtD8b@a;0624 zaeFg5pP`bQkjJbp(4E(O_D>#RJJWTrtyktLXiYH@wCmm&L1&2{^@waP&xDXChDN-1 zr=^{N+32rk4n9pyXQ%zOq9xLp4&+3mYBvPU{NXgX#Y4SToqmobJE=#FyJ2`a|NBhSV;7g{h3=1uGZt-1)TP z@QR`It}Ag@FE6|CWY5HdO?&Nktk-ZFD|mL~JnrUGyQ6t!7k!(p3MYKWOIxfa&5QlY z5L|&Rs9UXkTQhSept6$D*h*^wniYv=y$ZuQ&QzB4NlwmH<#Ma~50mGD%Z{?*Zxqq< zlbA2u5$UBH;B(~n!@k)5 z9n!JRvHfh!UgC|0Abumn)*r5|oQ~A*JA~>x6k+m0N*&tqwqW)KjUc&CqbVPq77;8< zycZ$9o%ma$p>9q=KSz~Co{O?(ML81sef#}pi>=*cD!poayXi?>k0;n%ytu~L6>&9) zkM)eGbO{7)snZW_pZm&40PRde2MnZ>gZ;{F{dX!S#i1z?C>+Y}$6XiSRklSox6laE z_7g8lF`kO>W?TfG zc^Df0ELlX6@^(@JS1++kd>48y0yb_R-sQ5N#n<%r%rGLf50Iv-&;;G&NhA zZX);oA8JN4kP7%sATkoRv`R!k-LF{0=SCAscCps#(OzMPWBlxBvI%3QJEc#sU-hH! z^^5PUT-%5a-x*Zp$^RnF|Kg6oymq+8)339$J9>iqw+L!KmBq}3aI}$1gdQHG{(P8U zyQ2CXnxs^YzI>5BO zbKzt+JP8Tgdg~F0kH|va+yLvj0B+C24`Y-`aMdHq5|UIfGAvOuT1;dAWBwO3H>lG3 zgA33{wU$nJu!c{^w6?&JWvgKg-h|$8pW&?zeod2)JxQ^NTFQ$x5H1U9eTYr@eHT0z{YkG>I8$cCs`HOf1R*-7fJ5 zD}53e@Xl5%Kc6e%d@diD6e#i7kEB_T^!feze43(wHnviF?r#ylku<*%!z9{cX)& z7*9}tT=K>d>3_${%w=cBl#X2o?`ZSQ5)p5MBNcDDE#Ia1$l~5`hKz|Bt=J+D^4sf3 zlf(fjpR9FDzZ!d#JTXdZy+Rw0wRlyj*btOAnMx?*jaQ0?_Mgh%A?Tv;Eb?|GYEc{D z$ev9RJ- zsRxJa;K(#IGee)p&=)YqhVS=R7}C~b->yvx=ict<>9Nj4%a$#Xl?_j@r}?_^?^H?* zxQ6*!xc$v-)u5`dsEVB`EO`yq%sGWgZvPjdlRxX%qn8tVjneN$yGH2udJd|tJ(eeI z4aO*yL6Kt#+>P3`+o`Pk`q-;%v_&TBv9{msU1hm4JseZ9i3Yfbnd7w!U54W1qdB7F z&!Tync)>57WQ)^|JQddQaPDxgS{Yp}vU(efetO0#!bS!fWR+WU%ee<46Rid8R;bkr zXOc(Pl%j=mYb&q7vn9wbsHD9OXu@vCbK*FNmzU}{8{jZ-`hc;NXZPjhB;Uk=1rxDF$mc$+Rq zmbb&!?1q>myP4;*8W{!qzCavsy({(o+-Pw}tU8H40|R%7N}h zc#rpb`_N*#xILTb;!#{+iT2E+mDVE=I}IY?U>Tr*!?0g)$KEUOg$D}4q&>gOZ!QQr z%8{nV?1ZiZW+!Qk{$3XKs^GAe3@hHPNPifTzyf_$n#Q1@ERhMzA+duRxen!t?&@qm}+i~9PmYN4JeWS7!m9?xn5J1(^va_@MlZE*`KFB~A zsT&aB4)|A#rooNxp@8=($ZnCIeO*z?8+XY?jS5{N({vZ1+sA>qQkv6NL1t#V=t{Bg zf*inoS4fi+foe=uG3;Q`9Dkvgfj1{s@v5wC*KA*bjk+PRhw)ZIoV~+##?I(4zXl( z$=;DJU&fNTt0Q`(BV4%s$^BjrQ-cgDU5->nOLN~ypYyW1#ER(2jp!-NOe2(*CQeMj z0y?BeFcL7cXOjDsEBn3bM;1E>rWGs;ca)jaw)om5M>GljG#6DFcBen>G#jp@JZb>b z5}G}^O%|P;iL?|@vVd!g4x0erot~eMahNeD>`rWdkOystTDv@Jno6d5(lBU^%QUS& zqp1<-Q#+yPGoCtpi$}0k5;tQ9&W8_6K$Ek6imb?UBn;_;$zGPtIcCUCh?ZelRqTmC zbQiwvc&#$k-O!HGAb4;M%cg%=Vd>Mib;(KO=1LFz%Cej#H7(JXP4=@*te|BZFC_3b zExKcP2I{_)tmBff!~Kv{!+8^Jk7yTIrO>G9)6URzbS_H{T^rvDFV1AxE?V?QGTP-u z9bUP1HEEN$UAo*U$m$T!6k7J%F=*MMZEL4nbRd$omvAiMX^vW{% zM=EC^Jv1SJ>IbHAEQ-H!(XpKj@Xbji#s?L)QcuJ?enM`IRt9lnOk@a4jDEusZRoRH zIN-UvsEa)Bfl5mIOn|7@$`jDCqs)KpdHo@lLiC2AnWBUZL*0j-1`+kxX&?7VAgwXG zqdw?}>FD>*0^;%wmhH+fw5ODj+DRDHaz$A%QpF3 z4>EI`Xpc#xf0bxqNlNsrl}`auG3bVvajmkqd4Hg-&WHj#DILBE$OGbdCJ2+2|!r_3+|F zf8FDkygCuneN>CmUwkGlw#G8`jMsrSyumm@r}7sY&v3d2Z+{uRYSd+`k=3Y$rJ6>1 zd|jvC-vPr+3+iKPX0&)dju(^|=`OeWA z>a!Ry${N=gr$}og(bc^vFVNOUx%i(JOs*j`r!&3(=67LMxI2*??LYc65S?HpDMsjs zt|B#u7wI@m(e<9OKk%;T9xpn?D^^y4Vp}34Y0Y`f8Dxe%gZkA$YEn0KW5=6>xO>gVE9KZM}|)D zWYPL&989BT%(F>KWYsUNg^!3jP)^P|a0ZO0|2pqCy)Js;b6DO>o_B-I3iq8n;&nG# zGbyQ^x-Alxm389NSJW!Y4$bf_coM(T;l)0U3y-iOoac3;{|HQ9M!syE^owK(+IqY$ zT0&`Lga0`{XLOKbp6l5?@mk%mVWG?OQna%CX!1`pxFUM%BU}A8l=Q;vX3PjhMA8a> z9ro9bC^eE$kKgRUeA2!+zG3=2m`(8Jxn}LaQZsJ{s+_A~owMpkdmhUGzlG4X{naog zr~CbWwKM$u26%Dw^M9@Jis)25@7FBaE0r3`MbS*=)pyp1VpPvDvduElw#1`o(j?~m z?D;~a)(JyS%Z3>wSq81Yfr+FtqvKlc7>QXA%^e2j~&I2C#n?irO zYjriZ&y14XjGz3X5qE$?e;Emz%KoQ*y2WGQy?V0OCqB0DT|eUg7dor)B(y9Y?A!wD z9J--S(p0! ze{!ZR;dcp&dKd-g*75v8UvJXw++EDl6U)jdpARcP9zQ-r5vGx6*@u2_0S$9Ji{7ab zlQQ-a>A7P=a=#pH{_c{OeI$DiBCpQ`t|+&wA{PYifZf=b)6lX@ z5&V_+JSrr;)F)iSIy*Ypr+#6vU;#^3{mb%7lP~QQzZoFP;@6q{dMk67vPI5)I0VBu zN4_3(UBx;+Z16-(2d!nIoEw<3m8y13{MMtD2bZ$BW808XC1>n9OJ$zQw=43N1XRF& z02P?>f@Zx04~|WM9vo10Nqckqq;t_r-uyGT99i=DQlB^M&H0H}hbWQTW%eSrC|EA% ztt)xlTlPb9Z#;?AaJ<$F-1I^jF&=9h0la_-LcyH4!Pycc6+K67=?lYba80O@l|eF* z;!I85Qi z^t|?aGWr|=-&vrJV2C$vJMUoAiQ20zv$L!-)y^E@w33Z8(AG|EX&tbR@9Az>e5Bim z+>pj&y}d?zWC4+FqfM`m5KfWBFI2vCMJ0N>u^9(csyO9<4S!X(yn69uYfi0FJl)@{->pTP%*CItE^`j)M zZ+c3ZRCfHH=O>nOC$cB4MtoLV~s^+pOtS#M6f3qn|WEdmt zHPf?5JxG{@e*4NW1^jc&==(wWEbUR1!}r%Zcob}&`_t5E1%uUFwP}5<`TFV>%V6nR&NNI=D6T(GJ;^}){rzp#`!)&GkqcoyMs9<;95g+a za?Yz5)KbOhb@%uyPoDagS*EzqSD3FB=PKlJmCgCZxGkF5IDM?KTEDwHJN3M zh(z_s7f0GKt$)>)rrls5XDux$xgWu13j@pB2W4o15FyjCqD2I$_iq=XFl6sRVRe}c zsCj9@v~(HhY_o@H`us}tSttzmM${_Y2`dDu8e+(dtTJ{M8o{7sRX)lSx(>Fe-30#V zpTpnyjPv2Dd`wN1;nVF~zg=756FYKw9i;$t5th?_0I=fQ9s&<6OW^WZ88AB|3}CGe zut6sb^(p)Hp=OB`fP3Y-2xeT$+=mTzP8u!P`T1hP(xg`Sh~K|If{2#hx>X%)8#gYO z6$j=&0Z{I-nHf(K&dUo7hnwgD0Gxo1nxvBvUoxWW;$t{`znRZ{VXHBkERMUGHvr1o zPYzb}xC=d}<#?O^dhk7?6viwMOO=?tgb)6&zt#)C8~5{AtHW-eq?r!@{CoD9L}@ys zPE5HgoPV1AR)YMJ@g58L33rSZ0|ZZC$Atgy2i9h@v)cLELNoiJ_<7qg$HzA6D&qi> z-~)7}jxJMq;QUW7D7qFz$YYo4XORB)>RqjIpj&-#`x}nnL}3h7g~oGL%yS>}pdpzl~KC z3|X<-)i?o2YM-NbE}LpE{`&9s(sz`}xplVkW`Cln-)EZ7p~uwjESr-M^jen;$h(+w z&MN9Jm~OoqdxPW*f<23>s*dp@#LY~o>-)Sqt`M2J58H&Hw4i;8-mRYTQZ21>;}MmV zC`uC-BbCzvzc0cQ@&oYyY;f6JFrZGTLaTuI6ankan>QU4UttRJkNfJb_j*)tthITd z0A=0f+--A~m;30&@|a$yJPq9v->3*I<1w!?wl^BP232f=X&Z5_mJ1kkmnk@Pv<_Zu zKLq@t@P0hzzk}w)t@#7iegcqr0P3a$7ziy)YU|dWVX083wiJ$;Wt|8e9;GPWek0n= zoA5#-Diqd(+_?u}w<*4i6luxM6I*|rnW<$?tUx`Bl0RP0K=O}7#?ouY3glluy8gN2 zr3G$c5sw%Si}%q>R1m1f4rI?D*_)qGb^b^0Us~#au(D~OFTuAy*viOfC~%AO8E6OY zi>UP_pQ~hanmNFU({@4|58ae>%?OcvRK|N31JbKeLR&! zd{>_1DZ>MLoo-5dNOpwMt6dX4FrCGkYON?Yg;3+)&Uf@NaMUphcv06b1U2goz{mBJ z9~Vc^HOHa4H|qe&S|YcrNYkh6EvsuV^<{#yA`?LcqmjLsBj`~|THLooE$@QY=3)or zC?)UaN2i&ng3{Vq%Yg2k3IJ@p9x|IRJk7eW6bJc?|=?E8&c%FUVCA)pvPc zr7`-q*_7T_`u8RiF2qGS7!jJh$E+iO|Rcu$EMq*e%sbZv&eg) z^8#)*mj_azG2jJrRg~$9f`PJgegf=gkjnPUqKPwm3VA9~>H`4&*NF&<@Glv6axoVS zD}n-U;nt2G$!4qP)`;1|^`;cjogcXf>e1^axDkJJmGZ>6Db)8ElxzUw+4f?NLl@pG zemwy734Wsleqq^6EC0hMYoQAg9`6KT2hjWqK{`%b2hvNTl^`05-ac;OldPmk7Qp*o z^1bRn*8Gn%sNXTGWFJatt>}Vv2&)}Cu9P$3V9ay#&=yNS9+GmFqO}&z7GOKRdtxq6 zh55jwq}TLRrHb-6x5|W^cOAZF!@lYE>9gqZ(S^B1f47gW14=pgIxnQMJ>}H?xVKIn zu~|CT9>4W)x}Dlp%9P6 z(v#=v+EYqOOuQLGd$QNY=f4}YnOekS?LO@A>G8J_qWN2a5BrZO4*b*^KsObUwq5{@ z)6@<7kO+|trG1*vztO3ZQgPW(KV9$7>7!H-N z=xgQpwSeP;m!SxKH5a^0IOE+$tw%Pzm)XXdW+i%zUg+G-7s6FtYx4y3fB)_`n0+{}tepBXIbPN=k^^0n%@GtW!6B z7U4V|JTqyM$@F`tK5`ZllM^Xg6X_P3o&DC1myL2a3cw6_`n|0BqNA@@H1ovOBDTcR zhuM{kd|}@R+_`Es40c!xh zSZBGaPK6qsSYxN`Y-YYgtk%TMJd>WDPu1SCWq?k9(I!>c&dtrDq@#?iqpRcN&0M9$ zDqbj757g)$NOb-h0T$gk^Sy)uYm#eVK9yss^a7yuJ%`?rFoW;{mw!@=T23(;nJF=L zY#OHtLrA$tWbrKW;iZMoQ`NI10z1ZeWp%lTz0BGCU%y(|0zex~HzJj7K@wc1uF4wn zzWbc#EgKV>e>K6G*npk=+o9aMUSjVlpGr0HK{*gd6zk!5WOYoa(WTEe;VUgWVRIQX zieBND!21Uo5kF6Pjh_SlJ~3Hdf=w@Q4j5X`C^?q%$$?(TS~v7!qt_UPRd_^uc2|i3 z;g(i@Aiqmh?lvBfPmN_(l0JYq`<(Nas=L-t@Q9CAj}J2oMHo{%d3VD5?lqoDd}+e^ zzUv5D|3UDH$;11)>H%0~`)1}=AHTcXVARDuNnk<0MERA9;bWKwmXp+e+68bwv#M}E+us7!>T7qa6{j-c_}XNxsqsQShQ3&Y ztkW9^fTMqt2%zF>xoJfwo^t0A4>zmS)Uuu@5Ud|I$2!pcjYb()SzCS|jG-RQsi#&= z)bk~kTgMMOLMYXmoOlP%23YN@CtE;DfbopoUr;)WSsI}mJ`drxyiJn$7)1(9s7lqa z&UoL?^M0J8=Ta+WHdyN)Yf83EEmYFohKl=;pw?7!CB}KiM9qWbJ;8XkuIunS(v8)l zEZXMs;_WRWo}#zhe*&;ltf%F5fXi=a8XOrH;j|(b*z}z-kJBV+w1O*D?#j*2us3XT z53rOJFJB-BTkn}sny5E=!eJsKPOGv+vU)Ue6X$+H(|QKYn+nk}zc3b!v(8gQpW8r5 zpKOnN*;SitjvgG!u?URkIBt>GIyH+J|D-1jx__!+w!Yr4d4`Rk$Xk3(yHMgG1Q7C&Qx|3iOM zvH9TCOu1cc`8b*5v4Oq9JTl*xMX{T79HM{u_2(-90y*&DNyZmD-Ck)>EV`*9tX>Vp zaJk4z_k%>^c2r^ruPUkiV`oO^6XJf~p%aLqYJNUw!RM&i4sN+2PkQn+*qem9*gBb? z^f)mIV>+QxkcfTfybmA+KOmo!esj+@7+7igA&E|!x`9NI^W=wmI4wUgfp~tH(nxxw zU)8#|R8_F1nM_TWQA*n)8s*94mn3zY_rO`D#ls2brlkJ-8sQdDD@m1JuL_Qt#JdZI zYu5{B?lC;qQKBSQ9@0W9-xK5QdtvB@WU3`)twpK;#DYMaU6|H%W(P3;?&@&F## zA*q3gR-PmW@+~^ry2zXU0yB@|E*F5xe`@`rMZd|jFd6)kSRrLoF}42nHcR^*FpM#G z3qB?uk>YE$%?_$H>E(Gl>2c_O?|vOjth$HDdH7n%DUEote#6d6z!#wx@7b&9DbloZp|%*LFu(|9OTjqgqMk6J_Gmlz9S_eFoV z&687Qy`AZKBbez&ZVsrubs9pyxO0@!J~r@TqoSI?+rVO-Pui6)p*IHj>RE+BTV`ix zjIE#)l!$&y4;(B~2Wts=mPLym%FkoQE68GTeRL+%!R-^_bOS6)Z?9$vEbMv6+36br z)l~0WGKAkwqlP9DC7pT5D#g+V<=!e9TNe8y3VFgscV5kNa{wXJ!&%p6SjMCrG4*N& z*~2W-V1yi2Ln7U}{SFx0=G2HAWH$y6$lda559!-%x%{;(9<6xk^u5JG&hz`$m;UL} z{Fa?C9@&|ZcjeUlMHEws()A@9+^^)&cUvZQCukIWN)$Pif2P<-L@FC?D^}u6(5rUX zs`#6MYQ`Zo-@#MjLRxsyqK)Q4Nftnis|UT-yhyj4AU^fNN#W7@ZfCtawkzsyNj>Lf zSo7hCchQ&bKLcb>x5DPNousXrz`DVwKWz9$ojwcYvFhq^zr{;go%-1~CfLcXR=Ebg z)Tq~hAh8cFnNtT)68QLKM z;tA!x?E&PsdLaWYAs;_3+~Ec3>5rq#=hr_Dv2DY`E3?3Ff?xc)H}f3z(Hi3G(#t_5 z)y3u-R!6_(>i>-8)8DOXUL50)=azB2q7$A?jkKe-_3RmYiAkL+$PWln;~ddC+Q~YV z-gAcxu(B7^lN#F}pO?);17$TJCO)|ln1@SG! zsv`&YmBh4+9E#+TwCLW%1N$aDe75tv4Hw!bxF8aCcdgDx2c=WqF%bn!)GSS{nTd30 zCqTwUubS|Yd)BF+$;R z27W7fiPq2Cmr&jhO7s!4O)MKF074WFuwPnu=kT!||GK6rF2(K|LoHl&BOJJdlaF`Y zis4(R-i}Mjl5@MZIe5DLM1^xlw)-kjS_4=UZ0A>7TN#dv_sFL3oYkHTLm^E$0+1}) zK?)SBi59qV+}3<{&$vbLJ1b{rjNv6cLJT{<9M%_KFmrIB%oQ!?ypNkn-S~p+0Q;B2 zQ!&@yq5Ha;fw=qj@YN^V#(658IcOLl0N}A-9Y)3e0m8F)nSkN7fVC{39Z@p9?>_jR z7(|;xeT;>t6lh=OP3@)EgT9jiWRzpQ13=Fy_$QIPVlaGV=v8H_9ySH9{OpI}FHd{r zyo;k`ghu%+2Xh)=W1=6;O3WfOF%d-WjIz>~eCB+0jJu?uH1dJkX0dQ?x0qh37~Dij z-x{{{j_Mg?-wpsxxa$mmtZ+DpoN)E|RGQe8zjqT6cNJ5l&;ONyG=eh!pF6y9zrYHe zTXm!=%kjkyv~`bQa|Yn2QLJbV2B?6wp`6f>tF=tR(oa@@ND$&f8{O{-D`VZq-9`)N z5Y8j`LRLC{WU}B$-U%qlNJhPtft1n=&8!OCxo_(?NB8Z1ScPI111=2YB>(aB!;3^f zcHn<$;pJFRwSr&#>IoK7lHiA5Z^MH675wa*BmHlgxtIq&ff^q@Hkq(#0MR^y+FJt<%?F%yKJl4MAl_Pnou= z3vaWKt!p6GMinKtTx0VP|rd4xW#**G#%ry_dxSg(&wj#BmsH3r{r8Thq}!J0H| zCBj8%$=!PVjL{HCGUy$nv>&XKmrX-Q3aRz);fKAxC$EpQJi5Qp?VTQOlzxAVQrLjB z$TQRx>)3|?^a+0R+eHQ9lypM~b+`=qe0iKz2OeL-BeE`H!bT`xts!MTnbLIcxdayB zK1w;z00RUJ4Dc<@650uvNocF7LhYH*hWo0fAD%6kx6nE^k7%o0I6HeXai5J)p7VW{ z--6_S9pQeXJ`7s-e`B9EVw-MruJWC43*nrmmz2D3LNf5kZ=pPV%Gc3hmR6A26f^26 zB<(rnnqS3c|NKr0z~fZURfD|laE*#}Oc=OLsa1g&K{)^SOo6uOlG)R+cz3h-;8#TF z&J{mC3{-jJms?Y4MRt+KtelX>_s!w;&{+|N((wfGk{L(!wSRLFd5C+8cJ)>&&xM&!J}NpC!7(% zD6POQd1%*9TLend$L1}>p{u&C&OX@dKW>1~Ukx|GNVSG|N0RuDpRPDIti0mKk1T{D z!BoHIcmMMj>6@Ifs=d^%l3yE}ysGw^8*rlB<&yvwG|=2UAjYTp0x&KN2iOqaM=cZ$ zu!ckaK*Rh-no9e~0*VtbyKiB8z6d>WySSwIBB8ZqVxSMF;4D7<7C13BJ#LutEmeKC zMwqGw4w0AQ*%m!94xaWOo2oaCXvc!A$m&V-Fio?Z7uI3poz_0c`VfaQoqbSP95tKW zLL0HF;cOj`m^fcK78Fn4vL)S@9X7T;2PR^L|RMWFr``9n01*AU@~vz?p*c9&SeH&uV13m`rbZB`dK+ltHdD2v*VP=IAvqpOMQsEpHgiyA|tPl zIY4AQj^?Y!N@uGklfK5Q&y3~5Y7*z;64_!dnksIrjkzAjSOHw#vLTAEZFNndCX}-k z>gShWQcG4cj`4`h`#cUk%3Fhcp3roG+ixzWVZRSOPbU`D)&E^Yvv|SLd6OlL(16JPe{)=}D-zD69vTE&oO17L=or z26pv?YfZ?=vrX;L1mfd1%eN@TtzI}s4L29%ftOgbmY$F3?eV514P0b(YtP40d!+#1 zaHevLvVdhqeOt>qTg}>vbCSx^|G>2!bpaQDQNp(QL)V`iPsNtKF?1EYp{>~rU=lS3 zLL1!AQ&D#D1(K1O(`*Lfcrj$;BVnK+kJ9MOBYGYg2DmI3;ZCFMd|5kOnz&W|&7;v8 zkHsXEwj$6CsRQD9WwAV0x+wQAYc ziYV5L!2ljh+x2?b^{){vO@F?mT#t2d9G@86;noqQbDee5MyZpv`@(DjPyIBc&;z>| zSoE=O$GpuCGtqUPptS#4#Xx|a z5I{kL>EGJ?UF&M^SMlc0s**wP=-OdRSZkOfM);g{vacZ@(ce3RWE$LZ>~J!(+?P_? zqtul$HRm10$8vjvC(%#T&R2lPB(7)E0|r@@tc+^#fXbRU@U)Rj7absHex?GErkynZ zxZlm@m(+=stFj~7>4uz0pCC?scmxcrg|EIxw-`~S_F3H-n^Pw=(0iD zJ4A6vMT;Mw&&B`J7Ovs{I@bShbMX-m?}Yessgad$emCi8ZcnZib4_2noj0T)-;q7s zm$;!~oAsag1aSswbYXt=V*3&o>wR6f$7vJBoE!;)h|d?Y$w&NM(zM+uMI@ilrNDF4 zslC_>PlO+&Xu&y&7Upy4yP79C6<)p@MlhY!Td(tJJJk;^FF zQGr<@Vr@D0Oo=P?NqRh@*d(5dC9`lBDI@ly4O?06*t%Qc(XFaIKH&kAS(V2J0?fKE zRQoDwn6V!Sm6L5_5?=Z;(sAcdM}4Vil+XEvHPddMlAYqG3p3z59RCOP+u(vc{JyQC zD@N4_%>%o^-OTAx*d_X~{djFF^BuQVF1O6}ymvOnW1R8S`GgB+u|#Ss#>3Dv%MA5t zhN+yhL5H(*_RS629yPTu9X1LUP>Oqa7PZ^*Y-8r;=6P*5Cdx3oXtn?iF>cq=`!(|U z*e_Et3uE@NVZu{)=na5V#MC}?z`lBSb97^L#k|A$SiAZU{@oW!hw+_-P=q{>xQAjT zf1@q>rF8=y?bTIw%8BdJp3h-ZnxW%oIP~J+V(Ot-F6)Z`^g)2tea%?F>4^>QB5glj z(eeKx)&}Ekdn_#3zzuSWmKkC%l5~Y84lPxE%TGY-#i)|b3o0p*E&MJ<9exOGW8U8$ zPS-$3SC-tV(fJg<{%eZ|zGnmIJ?Q1D46sKTMR-gHJ~)3A~pg@oU|E zgKG@&aMwH5!JaaxF4MN4s5}#!tw^ z?HK0~?M%O7AluC5LA9rh`1THJ4boq*U-`)3YYzQd^NC_32sJddSDv%gC}Ipx`rO`> zo>lQ_Rommxpg69&Y17}i#s|lmtIS8O?#KV>*?8P|loGR-`g&m1eO(yClnHDwdztbjH&#bdhAnI_$hSz4rp~IQ`=*=4JIrR_97H+v zc@a1p)96#pA`}_z%8?o|pdUA$pcEn&9I32oHR;3X$07QkX1~@kUvoAe5hRcG5FyQA zhfe-KE3?6o9(z9@zH?i)#ui#AW$E6P(rtk&utZO}-1wSX3ln&u_x)Lp4Tks+xT1lS zlkh~A5!w#tdOqP|f1kGXi2F}qj_nUi_{(I0xDb5!YjyJ9%e1XxDpZtfZ7>Um{z|QT z0|+6L<2Y_*RZvZ1TWvqkV;dgufra?nIiKX_u3u<$zf%cMjbKAiyiFWD<}da6k4@@( z^@95h%KD5Z58bZ2)yDncUuEZb?gm=<>hCC%*#mm5tOptkANfz>YF{(p#OhFoMJ*pT z$!!E9-2$x_%xtHRqKPgOSt4TV-LF8QzHDb%#BGwty~I<=MauTPh+MG#`Hq>E0njls z(dfI3vA?x)+a~(c?Rru#n&3!V%ft}-E$EwnRRY}(MAf-KXw)=yQ!MT25Wmupi?)?4 zX5cgYoR^S?K!Ojp^jodWdoX!on1P%+6kmLJWK|$&!qLBrYOT`)`FjKRedckFy(P*C zXjr|~N>$%)$^nAYO;+}+-f9@$iZ0eM@8Do#aK9|9pnYU|%mU&?J=3eGe=x5CA+v^T zVM}0dl9rmXcs>3qV6W}ZS%G$t8qEDZ*CVrqM_bt*!|3&_r*oS;@6%U9cNXlv7AV%z z>R^eStOEcIeTkk;_(j7px+G3C*+gy^>oR|+`6>pu4)NZaw2Hh8s)@PFjPgf=jqSE= z1Cg6%tTzSz3)ILZI|2W;=eV>6>Lixz_cw4Y5{E>_D9D3Hbc2ESd3*~qMhXDyu4s%L zxGrb&@Z~x>vCE+_Xuw};T1Bvz5)B$@j54pc}qV!)6V~v61o6jXf)(MlDWx-`3Bdx6))lt@H zM<|Ig6pNFoFs3AXUOT{gnm0x-aI-E+<(KR)_^=HvAP(%1#PTtX$$DoB7JBZ$v9dz@ zn6{11HAu-_#V1i|$KWiZ-sS|C35qEOnU?%!N;C}mmq#cxtWhsruBQB;wTCFWY9*G zdcVdbxRWW|`bB2`6D>x7x+2`&C9{W!mnBGTuWZOc7U5FZ)wMI4Oty^|d*#GjK z>-c}q4!@~T!HC~rj(K#oQAnIL3p@NIJV~!L{ucca?xgY?X3w}URyq~F~iFOEZOv>Jl3^;VWlQLO7t~U z)i>T&&wOQvk|fRm{>AziQYqTD6F4lB2M*4U2UV;;@{mFc{fTZktMh)s4`HIk&I3`X zKB?G3|7H0>0a3u-qUIs0hRDhz9J-$K-J5h+`N_hM=mu|ovD$|3{7q^6WiOjj zuF@c{WiBk%VoqnsBQZEVLk!@eEOq17eyxta@u2Im#YfHlOesaDg{aA4lCm>~56%%x=ZWi&7ds+N19W$6m6C&7fg1m3d$Wqe1L|XSWQV0SgOY zp*Hj!y}!_!0b*z`6)9R32_qL(a{*2J46PsMEc!&(1!XR{d1Rl7)}ABE<3&b~$qnjg zm3Wc`fM8fJh7F*cRbEo+$qR=9u=KO8=+O<`yR}9ZchHmHC`7qu587jsI;+tgFSk|{ zc))CG^dv?8{?TI5D^5^1cxi%HRZ#!?h0Fl}(_a1dBdqz~VrG8CBo_)-{`*d89-i(! zJPAt77^9_v)`e<{8!6QjUln567z|tI+AI*?3fIwhB2<3E*$^>WU#mqyv2zU`>lU>zk?6j|aM#G*wI#v13Ft&` z2UK^{^iR*|%puBCM(B=CLqlxL<_C&R>-*&Bcol6sV6Xaan9SlTiEh)I8V@pA*0yTK ze>nQt81`j*ziH_^oM5hl2X4bRR3Fep zyBR>5T)Q-=oORp50$@)$DkhUkx34E9>L~9X1MVzlh{CF}sG*3mG1u`A-u6oB78bp8 zeITBljV63@NJ=z#m$~zxJ7~XLIBHQ`%+QHHQDZf%j;$t8Z7%UbB9g#F95q4`S^26n z$jFQ;VBKz*_NV$zU9@*(1^O`~L$`z(Lg>HA(_VPK#fskG?w?j3{Cqh{y_0y{Ba?9u zFt^Qns#qV@E1AgI38jEYCIw15()=!jawn&8&ZsM5XF1Gas6Y2B9`0C_@K9I zLHx1#>wQ9<1SUgCp+)=tdS0J+Sx%P24QH%cS$?kUNQM8w;-?W{M zq->~A>*p9iv1weG$7`+|GzOJr!M@zp)xevIO{+i>Zw;W@4MUgOV6VM8-uuE8OISi_ zHlscz3m{@A8UP`ff*B?eC&JnJUpFpip3DShB!u|@bykEiw+zJt$mkes`f!2ieGM_c<$ElGkQe_-w=kj9rZ4d%(Ke~i3`Zd^3oie`}cx{ zR8ee?>&vI5@)Zp*9SDhv!+p~`U@zc)tN)NnycjtZn^?*|`zDx;Nxb?zBop+qE0^9Z zA0hp0kEY%@q})>F0Uw*};pgTl@z(w;fjxsnMeT6F4|7Z+8!q?)~P!FphsCNp?rT?-rI2-+uftt5|K@{~zq!y!&f; zi@TxVJd2(8f1jNDV_db+|Kfawc@ZhkLbv+B4Dw&e@Am&+$nXB~)kCq^tRlq?sNSXo zZ*=Y|C_244A-BKC2)STe9HpdGW%AjyL1QG3W!=l{t%C*VN#%2wyED$+CL0it!mBCHF=2lPmDL`cUdBK=G&Vk7;Cv1^ zF4hAuw7U-wmgnhw;rn~2y?6$8Z3aoSP_2F7N*d6nQX}>su?{vLJgbODmbzWHiqEY{J7!z{+6K6{ z>W9ZI?{4N<>~&VXv?qC#;vjsj#6R?SC|T&qoF33iPR%OR z0m<15v~7M&{?(E(E^^lO!cbx$7%7TFf6*f4+||=*?#&BfZ&f#iAO)#okkr3;{zEL! zI(N~x*Jn*%fLZM#py&m+b>3WWg_72}7{BgH6tQ&+zTEFW(cS)~1)7*@$hwpe)0n^d zY3ssDMcCsEGPS;Y%>OR}I?(0c+%n-z{zLgi_N&r(>#)9?Y2AeFW8QZyG8{f;ICjvZ zw9j<|HerM@IF@{ULj6hXsSdpA)J>j>!)K3T4>PO2+sDHj&L+0EA5!!IT?}BO{!ty8 z9}!lF*RNujGyc5)#oSkiHQlyy7I7 zb`~$MzKa&cu{KiK^{D;CV}c5z#k2vJp{|MJ0B8!{|8>0;lC;CyU8wI*RG00v!UO;i zC?~MpL70nG4a(a-NvL>Cs2RMdJ57NN9*in3yH6Ug#y#G=Ul>RNa6oB9=*bp5f@N+N z`Zh$fPwiLzLI91*pDKS@qTFo+5w=&aZ8kIf2k4D&%>=7a*}@cn(f9vDdXpZ9jMb!8 zn9IdypH&L@J01~K12jR0I%nR=e-jP2$Tn{;+XzSW0BgU&kFC(B!s!<$0eBH8@`@qi zO2m+Ii)8Y^fhgM*o7s-|<%(-7|62$j5UXY_wf& z31_35AYnODmZuG(8M_r@Fb%;EymH!^H)4`NlYpM!aMJP#J{r!ZY6b(Lb2p0VuDF-9 z?mA-}`nwM)ewqxk=V^ut^y^Ny)vve~CWVyg5W-Q_LZqsM-ZWV|H)*LqgWoFCyj{_C zoA3<-SX0pCmPnuMNkp*g)PD(Q7c{2UQl;}_Y+2GK%1?tkuF0=iXshD&5IiVp8Y4fk zdmtGa#gc%XoPK#Sy2cb<(DFIfT_FDHCahk3pe6uGcqUfkY3~Qz7(a$kM%H-3 zsDBRA>wUudt5FIxwV$$r^Qv{2$Mm{WNqK*6$m1%)bD~KUrP}ej~$XSU)_QLOe2(^V-RK5H!~jWbusxCf9udm_EaN-_HkPL-k>zm%1TY z4aRc-fbf1AGjVnb+Q&~(w2zPp zPh$5rugrP$S2hBS;sGG5TH_)ILx^>kVdTsH7KzK2eVg@Aa2Y%V#+T!71N2r&bpU*3 zPDShfE2i%me}z!nb|db0yRtCO%eYDg9D(ZO_%A5L#6CwiaFe-O+P!X`cE`^~@Az3xEpz6MD!Y2jQzQ z)k^gqk`Z2U#pkrO$e>s4ND~ z`_+O668s1pDcu#*RiUL*taL0C&~;MejR95DS=pPLVYP{4ur%l}{kG&BQJlV@nf3Dm za>2-e)o*#}L7{rZa`u!*DM*x8$Q6uOE2vs{Ua0B#Hh7$^9^prcO&x~UF4>w$`~J*G z2`!u0hFp$^WNh>XT29I- zUn!W99+0JC=`%2s#UB{21-7QzZS(X+I^l878li$1+g`E!7uz((>9=dl z0C+PFE!ix{vJ-um2(;!L-%)~zobQ*6RFlP+DLT1tDoVQs{F8yeS%fx6;KrOQ*btq= zq+sG2MsrmibXxpZr}+}02&@@`>L(IIi;q&9r@x%SRd|z$4%zGoiUm}U0~uQ5Xher9 zV!f0ogq7;Ab3cXW9Xe<8@_l40+NDCzJ5XHZpvevf*seqJW)cqIqDo7%2Ki2Bxxe5L`tHXo^QbK4s{Xve8=OU6=HWj#S z1(%yA1#EW~s#H17hRv4LGBAv)jr-|T~8`?Ex z<*DH~P3VNq-Z61UxmiqT5%o4VB_njc958LKMz9K3ESnYXwY8)pOH!lM$QMfoH1U^qv4ACxK_OzMI-JZtLf{ zD5)tJtVvr@873C8oFxD%;%z1*zW(|>;iE7yJoT{j)ea=bLn$1Q{r)sTZIcpU-*Pps z2Isbn>spwCQq`?3X#;GC1^RM;$oXnU28*NJz72Ht0w{N^4%YO6Mj@Aje0IwfiOJ2q zZQ=9`CLsH3rK#U6Aq4J;SeO(I%Ur%>JWTy7IiyRTEbMYJmYKta*`bkbY%>1cX3+9j z!02+Yqi0(gV(lP;u)`!W0!N|MY@?+jeS7$PYeR*7J_5^pV4Kix1N`+K=}Vh^TTfKR zDr==7Q^uk2*;EMDhu%jV@*FIr_1Ns1TK6@W0$+m;?~R+P5Vn~E#|S^~RA2`Nv( z#9*vQx?5gaI#nEYPskt&xtVd@Mp&cXh^j%65bXHn$BKthD7 z&$1&X;9o)1zk;vU140?=Vm%z}|A8Cu-*msfiApDChw{u3xW-$%EX8C|C==RW#O7y^ zwCoxg5)BBse;Xk-Fl2wBfG;tS;YO@uW?hH4NqK%PlZsZujeWgk*}EY#z0+WT-HxAI z!vgG>(fy&mGQ-}a@;f4yzzpAowDmF3PibI1N`%@3OvFEo#c|k@O$P~aPcq#)Y%j@U}S-lQTcS2*_(!o3Rz0Pf(9-PeX}5OQ`#WJ9cHX@*|5RY2C~$berIAmRj2 zKj8K>qJ8LDsOm$B~SI!F*0>#Ey|;RDEax^NA)*j@l22H8`fQ8uRP2w{bUnL5L)P zlts-8ycPGebG2kJ!fo(kT#O8FiPe?>olb}vF6fhys=OZJ%pK4*Dx4nra%3WPb(Ywv6mt!)e#|f z9|1|wfEQdr2s^U0BVmMsfN6}qqj?jNJIIZ?e`7UO{c`RXK23^lwzo%D3CDvV5eXu$ z&sC_{*SlfX7f^{1k9CGR4dvG()xtZhhxVU}YRP<)ZMi>eU?cb+m8PJVu&7djVdmI?`L4!7B|YZ*Kos69;jF181rgDX=+?42T85 zG$hOPds%WtcIT}U0G|}2U&g;su?;TF^4tQ=cG>;O!~xtDAcPB1(Idy;5mtuYD{D8Z zX@>V+zELkx&j_^0!_`0YIl=|aX+wsZz!#{yV7nM=H3tRE@%tn)&?Nv(w|3OPyM1&Brl%U->ct)ABf_0&q%!_WX_B`pvQIHTREG>OUCGoJ0O+$KQX{vzLn%n$>yR z>&Ndu7nqx#y@h)w)A8b!pKH{yxvr%JjX<+kB9(WVcX*n5+#l&AZFE2tMHJXA>R}-Mzl7ALXy3 zB7qGyNzb&rv_w&$q52aeZb8-I!;NB`*vTqGKC0G#JK`3cH?fU2ix1R>08!|28tJ?) zF=mTmqgxvS@JM>83NBZ{k8u@1b)H)CD@pSVrzevMl{dqXATT|pGZCZ1;&$srF>saH zup5tveQas~lhv|NhD-h@lO|(9FRU+UNLk@frYv{Fcnr-j>I15Y%6o~`J?$=K?oRHP zx18f}BWUA%=^~k9S46j*PPYc@H1ARYx6=b}MIC92!t{xCeq@`^d73WVcD%@3)ZuJJ z?AK-Ko4e3`bAu5QS?RZ_7yG-1WprdaZG1E-1eH*ng65F;42F#bk+$hhU79L$d&nu< zPzQX`@w9;!Bt`uZ*X*4s*&W4FMpBaFN@PN^G6$=-%5q8+@J-(+07wM|pZvEE48Ho^ zh@uTR(~spZR9Il}Gf*A+j?;6Pd11Ue#(WVMKsVWB$(elZV|!A29DW6o2xy9Py1KBV z`5@Bd8&)-f;HdY)Tk;p-u@+4zc^Mz!*-K&7mX^wTaht5b>cX0zc}nr_I_)GFzsu|K zA|Q66x;1_W$4T{wDhPUIBOo^fb{?Uyu$->tM*Pm`H3eB~0#e7RTviES`ll;Sy`?j@ z{sHv5$1{~EtS#S*7QWQ2GR3nWUJ1xLyw z0M8D#j|}ap=8;+7X7HG>0mF$E5ta0bK$m=%zcwO*PMNL)m>H}9|4;F`GjZl7-Z+PX ziwoRF#W=@-pY7@;JV^~(xJlyDzT-*Ulz3?A+u^q-rDQ$H7wVJhAp$4)5U-M1lA(^z zUw04x`0E!Irb`w=hjN#btEC}lGfFzQ$KM+UP(TmbPt#mjIR{^@rZG?do0F-k(hhRX z6~3+Zs!d*9$OoujcDk7^GvtzLPJK7l^}93VXUajDhO3<@m9Y*7$z7ni9ZxvOurioK z9NS}c@}Uo^N#iQhcPuC;h5*YYSR)q;A{Oo3XfXb(g;2$;@ARK439<7v$tm$6<2?Gn zNT;Z=M)d;GoFfto>p*=w?q;5fBE^=54KC;V<)Xzr! z=f^}I`>qSfx#x-{M$iS;h2Yp2`+)gA4F5FY@B)a0w|%o$aI=r^0+)lB;XZ}#IBsjP z`261ePT4Xe=xVPG`A18T8`)lLz!A*`;1_S2!RZ<~7Jf}GtGFOCU=q_`+h7i8nQp@q zlyR=ew`9UC5Gir2WR%pbwAj)2p&kRclKUQLZWLuE$c}8M?2|eQf|X>wyd$4bmKcZ_ zo=N|VCqXSpOAFE>enn79I=kYa36Mluw_&;`YE?NTDhicp_So)sx^I_Mxi#i$-6YA^ zjN+FPg8NPm4k1-lK2rA$D@Mc3#YipYi#>LGyq_T>HGDJZf zRr1?X7lZ>;qg^k5_9B2=M7j;hJ*J}RM<)B+y>H?j-_Kl6lCxCDmrU&O znD)^e>3pb2{>t^aRNwCu*u7)ZY-O>vivZVFF(D=Er{0i z7z5#FdI&#d=M7-)sqkhh8YEPZWFdkP?w&p#oKbs2;}jx6wF%Az9CZ2U8|n{3ilD^k zt%HDzP(9xc;Xnq!o*N50Lpon9=xlgM-wLun)T{@oshaKXfKjUpHNr!SdI9qm*o@qZ z{2&>@9Sa}Osg0*Ut_$Xm+Z>;UmC$NF)Pf0I)7_g6A|RI!XG10i>h->SKmawb%$geP z!RA3RTVI5yUj2?Gae5ELQ@74hcb!0^g|&KXke8?vY4GqZQbej}jeLAzrWc87^UE$W zm=a$r(*so4=8KD9YSeju&CcUL^~cZ#im$7frQyw2ZLw|Xl>|d)2;l~@bHIp58-SFR zlDBZhr7TOQ3qUQ$4x~+dF zU{8=4q!7MNTpE@AxP<#=0un+v>e1Jg$hZv{kf@6J1{1OM=f%Fh zJXIWYID13R5N3pN{YD&H?v=;~*_cuSD+FmcdE5+Cb7MqX|Af1NfD5%Q&aTH8*s0EC zJpw7u& z7L}gisin&eM4W`oJcbTKtRTC!;dDE|g9moiMjQ$td$1SFzyL3qrM1^c2R6&0Ltmd(zru1s{)|oJwejM$l(@kR;D;`Z_>d36Hpe1*YnT;To9h2K7a0us0_FQ3E|Z+( zV6~s(@W3A@nqh2=$Pvq{u<3ugyc~n|)F3yT2g$JF zyDIZ*a9_Z?^q+9Zm#84T)dnMvzR@c0mT|>^-@9tF?+U<~doyJ$`9X9qS2~1<$M|H0 zA^Y6{1ELJFf8a=D`y2?^Y#GJmgJSUAWWv-x#x`Dw1d=9x>LuX~Jg!Qhr6k%$OjawqM^Q#2y!<8CMu0xIloz za0xWZ;cQP{)yo+u8}54HN&6ej^H3{l@IPP3rE5!ORfrD6V7z>DUZGS1?@LIIHB18)1h7>G=F*UE)EWKbWcJ__kFZDEG`|}f5cs)&f*U6C);@wddVso572Tq)6mw16G=-u zP%->}eDRDVI6z+10G5gH>`udA49th5!Vx+4wg9hH(f^X_bw|(qX*=Mt0}JmLTpHxH zIJC(GzaF*r-$?8NWFnctW=)2wd}n?vE|wE#lVi4dG1~6`3b13TFBsxWs5zho_~`-| z_wr>+q~r1PfIWBu_=%@n=k3NE)I&vIKGl=MZ(xjMUNBSyMo_|yuD1eIv>|easNZ)g zsy;$*t)V8rSViQBwDEa|0THg#oD@Y3{_Z&2MS@-X=c51xzuPTjnmB&mMZ`1z`xZ_0 zBT(sYM}CE-pIcXa0aYVvF0jc0h*qY4S_FxyiKU8b>4Tnfw$0HI6xfuEYP~w5nd*Z5 zxYSH`(0|t5iwvAYLxiPI3L@HKv*`aUZC#D_-B6%Q3yp6^J~*zPfp) zIT~FSN8U6W7?EMA@x_2>^KOZArw!2NQlW)8<*!jgz=UW$nCta1Os3Ua<8d>Ypk%>9 zMUN&RWTWAEJ;-_4;sYBNoeeHD0718j3=6e!QPpqG!iZk=fpieIqA!NR<(nv(0M?vU zu-%pF!nWLCtkwl=pUsBif#{_#@S96%0Dr~^3u11z4usUrt@!+rT|7XgNKM`fkR%7R zJZSym0eK+^535N|fMx_C1O$}MiIxeiC@Jdie@OKL)Z~moF5L9{T!b>(LE> zmOQ@86$p98%h;zvM6S$!NnM0+ysp>uO4J zQ|n4?#i&7^H-Za$?5~+3o9rW&A~_&sW*=Wcw8#g;90xAfBQwy#(ugi!sTQE~Hmz5^ zvDN|ENy)A5?6_t`$Y<#M5eiJzV90tf)qU(tL!+ND43VHR9uhml;sv;{%{%#9z@ZDD zpgo-eJXeUeRo|KQ0pGq(u>l+x{wK(U6$iftc%SR=`uRV8(@3yXd$vYC;;5|fU2Jk! z3U(?N#FMEG`Z$%V`s``O-Yw)xo03tnwH{B9hYl^I^hPeWh9-DUAN%n(YMdaTm=XRi zHR1|&C=-eRWRX7Q6Y*j7Ag*|=f8$!-fN@lemR#3Dl%wjDEmjNQ8tLv^fLy$ zOf^4NygI6P4#KZ|Eg;CKgPcC`LMMG89$O@{&QkFpwTglP!fZ21msNJuC0B?jfsrzl zo4#5L-OPV70utwbj}V9w*`Sp#Czj2RRtJjsPN{C}soU%FQ^QlT(f#-#NrJriJRIZ{ zUI_6hrOr7b0Hr$_Wcu{7v}ELBXy*XQ1R1$bF<#BT7%kRcX92F>S1B8*U*|B6@G%Y( zkX~{ll6m7=A&bYIB7s4#p!PG$2Pa3f{Cp|MoZ(outo`fqN*W(X)b{E`K2Enm_|?h} zEff@%2^l>Z16d*%Idni?+utm6X3MziEbpOJSisHH`|DIYbsWg{&kkn;*M-)*`BFl& zbm_=`MmrgKZha4ey~hM#)XSDVOnQiH;mX$} zHQViX2{#)*)UP|>i4QC{%UB>l;MnoDocmX1QDkEnENKahvNW(e~xwfm< zJ3g(DBA$69Gr;nNpTH@*MRP13fL3}I)~?VW4PGj%z<$97j;I9Dz%Iuh2Q4|SR1VeA zd8`rj1E4*IJ!i5C9UL8p;e;keW=rE0kOy-qS;W`5*>TIa5h12H2wjG+L$kW3)a!T4(FGaU-U4&;EA*AdD0UK~T5U;XzxIln zpdG(8o_Dekq*{=dm-hga`E!NCv}a(Hy9^wC2WN~u8U}2)m@ZP7;_Zu!dMD2gSi+IxjkNJI~A-h5}4tee3$u#WC%MS)vZZ0X?#XRiZ80t zm2Xp;1>!8%8#NzwQpVyk6*LM2dI)?2jjDM~H*pU?IJzjIxla`41;_zI6s8ufb5z-{2gw4ATc61(cM7w9DKLEji6Z|`KE)0qP29)K z7vE*k50NF_yS#^nxy7x$pj|4K=W#p?s$%4Cxu2ehkqw9L z;A>`#jh{_yYi$2)9HqjP+||JSkhU$&uVpTjtHGCdTm0P1?bvtv`;7PK951Dfu+5qQQXpWXxvUz!K=PXV0uweulR|z?8h4H zrGH*+{a*PL*VW5^%ov32faqgsBYpMSeM87t%_3sjhN?5xjs#ZlwIjHdCz65Yq(!~n zTOHoxVLixzS4}QWWu)&oT~Euo(8#MlqXmmD=(|EmcsBd(+;wXbCp0~mH8Y*ob`SA_ zUVlk@5A~SD1kBkU%g!~C5KzwEu?M|e$7yVzc(`Yvt&o~~$1xLr-2YTB&FaQ>!PY*-a+`OD7LttO!Om%>-)EZvSf^wa4b|=l*~lLif;Ka;bj}iU9wUQZYq2& zMG`JeT6--Mns3A-l^>+du(%bHr1@baF+OE z7W@@mi?$Ym-N-Axr{?%d;c_9PJ`7qACaPB*&9K>=@I1!$o{+S5Ml2z^{lQ46;Vz%v zU_Dp^w6H^w*_MT^xjc6(EX|#Zvw|xA(RaB(+ruzELch5Z1KKXe2hP~|>Is2XAHFJRh z;NoXWEIo zTW}lb7ckBU@yRTGL7{)kosXRwxP~VO<6_n=bo&*og0Q!cvjN} z@?3AwA_7J9U*lb6qibuJTaW|>x#D@>Pa@^C#W_9O6-62&IDU_~hQPBeXshMYC^L{@> zu~6yqRVKax66JjMrh=ME2fts~v44wubadxjj<;PjR@?LOj(8ZUxMb36ZvLb7Gs41? zs`b`&q2_uFboP9!#mIX<&Yn5sfl8p2*06q;sdIjgEZc>i%Ix zMLuEV2}%etmn-7i&exvsB~V9c>MstHjIjkmR|isO_0n{TsE6W6$goOn=(APh$67gueOK%O@5;Rv4(2dd7mEk>j8BfHHhcFnumq1vgJSRO6}e_@=W5|1a?S36tHo6dGe>g^kt>dNjxJhG z56mn?u3ETTn_1jZxx5zw+54-xo^iAByWkuXq}t(&RVkU56L;uqUsp{GS`@K3mwD%% ze(T4`z)X2P<(Ov#v7LPvHkU*N4_$HOT`aeRvxUMX}`bS656hw zW6NvFeQfi?$AA9UAI|M@G}}>gU?9*>Mt5^r7autlPq{Un>(?o@clYo>P?x*W2y~%V zirR=V$C0JukNqIeH$VU5$$H&y+&kWini(UgZqm|)_WkZbAm)9x=kq{6zgCKq>b^65 z@7}SSQ4!}i_vTCTMpbj?hlEPd=<3>9n8>xDx!e)xp1n6PYNIXWL|U^~g}XG%y4 zg?u-d1U2AI9B!DIjm_j#G?zi#rjHPxG<>NY{bB6HjP4$&*!^wGPHB?p8oM;_aIcW_ znMuZ-xBhqk)q~b=ET`z1chVHfN*e{NY!`c;wkr~h=Fu?v&3h=Af$hiFNKE6*L~D`? zEGdu@!m}U z1{X96ZnoE)XKRdla5sCQMy%;*cgBFJ|Dw67WYd|fyZX;>p$r$^-&x9N;$jZmrCeaG zJsaNZCytjV)T*Wkx2LNGN?o{wHue|(%xasV)z<^3F((tpQ8I=;t=@sj$LG#UUTqWp z-5sW)eOyoLpfiF~6XlVZV%jo>HPmQffXFdeFps-q=z{N!6T8A;n3ezR1h?-}>!(i_ z@xwJWHJ{CDLyn6+F{mrC^6>D$OAL z?WHE6#P)?qC z{ki-)dGV?^^@;atHgE3Q`R9nIY6jaCppUj){vb*0g2qD6hy28>aON1hy}P%3Q>-7S z;p6zJI_$0eB8J8G@x5w;%q=vAGhqGC>2xM?Md8O9N<%}E7z*!Nj%v;C*%@V%m8b~+ z%Tiie8q#+Stk-aUEl;+lGA>cm?eo!^@p9E!U{+MnYj`}~5PNWYg%B~PF+q0<8L{su zk{UF7jje0X(YJ*mUA=t?k>maEuN}Q9>bMrZoYrd}EUndZHZ5;17$JqYb@B&tPTsg| z_L9JK#F2+c`TR7w-gKeD%F8SUxa5A_(nUkB8L2;`dI>64L`600$`E7WU6s&S`-{+I zuW!!}K6vmT=|xb`KFHUdjuE7^*0r!*=x(r5CU!`2GxrS+#I;YDml2RzFLs^n-zp$i+4dk{-9olLu!hf-=8)$i>Y;>6BI}1qRWex?-@vepi&|T;sy|(Tr+*+t>AlMOwpOf;p(MUNF7(Lo@Sl%min_r;zV;QI62&DY0S5;T zL1;UnN-h~2(cU59#t7eD&;rb9=MLrlb5cq{fRG%(ioq<$rS zs^mND(b3U;{gU+FuS%lTAu?43Tp}Fqm0jLEGeT51^~y(T z^64r^SrA>YBrTrSyQcKnJvH;&^q7T%y~v3Nyq94nMOwGrw0m7jkWeeUR%(mUn>yLZ zF~{?fd)Glp>#Zv~@U$PQ>JO{nw*u3?ADb!~x^dN(dSR2~2<-`A1&of3?N3bHA9Ub! z1)o$?Ld44pFRDlPhCwKpNUNg{&;0zJbgL+nU1#VZVaN4uU3MS+JI@;nR>+owUDbW@ zxrb&#qWtsAto(C#;tzY+SiEzd>A%k(&{W%)vZoPy2B+KY_iLnpc+b(bYPpTteoiIv zLkvYli5T0;saxLyP1-YbfuI$$Ka_3U1V;aEgHzctPBHSMp>iF?Mem6be3lTwOywNu1e>&QdWt_i)5^@e6g_UBFQwLaYzo$XGsWL|I3UXGBc=zML(C%4eXH}qIM zQr}N!9&8DTrrS-7NlZw6y5^_~!LmvHW1-F9psa$8s#w2UE!0d{MBk4)S&|DF_--p> zNrF~9iG(?s!~8RcRL4;ok1aR>&PFpeKTWl7;kVZPTmyP6)}0X}2jC6%+ND_`3T2s44#Q%VV}WR>i$fO_w$5#|y?h^^67P zglJ_XZ}n%%RD4IwpahrQF$bo)`{X1h=Bj(epGh*p$2jf}Si4*~@MmW;IUU@Yj3~G! zLd<{i3{fzN^x9$nmejcG3D$(*oVZ_gUo>d;fGvuq#~7B*BPJFGFj??mnD2 zJY#-w`4g{lL&TZyrs_P}5;ZQ#x&A#Xo>!yoEjrMkW$hZ#<9O=A8wVi{ud5G1(cmlS+9WkO*%w?Bgn5x2=6@iC zq~40w7+6#-J@i`?=XSa>izG$2t-0Xy-^1}d$1dA2Sw4C?+E!FB;x^ayx5Ov2b=6XU zgR!AFmc&Hj_J<)!Y0W!#G|_DduRm>_yuh}7S9OH*T+&!y*1CCTy%A2^e`2(y-iBsX zs`y~5lsLE`b+w}x>nvdpkXwo#8GhI&kJQ>7gg&tLHNUv?UjMq%x&Go0s~^ZL$BSn@ z>+K#P+3cT_8gZZJj{oTx`0(Zab{d*(KlX<|>M>+*(ccXPzingFX+dvmU3Yf;dFP@g zeRAN*UYMxH$U2Pp_Ye1fwmM#mQvILELB1Q%@ZS$#ygR8$7mUSwW8x{qG36}|{lxj3 za@L2a-a;b7Ey;m{}#k#J<|E^%4 zXPkq#k+>}7)9-H>|9*K?JC)M?|INekWih$-U;o-cxxnf2*G^Na@0U{p$$nd?I}Nu} zZ*`!Al)dViwju?8_u$LT^*-^hMBP{W_DV5rpzz0&5U0|ZS83frc?Y{4J1&+awq0F{ zedK&S>W;|wmDmTtW+e?N&+1KcVrI^&KJ2@{>-bgNQt6?Nm@QMvl)dd&9QqUAtfYqd z=uSO-;D-9~_k0RCGxVPiJti;P61mq<%RDg)81lWcaLBoLK__14+TSNxDsS<9fJO;@ zOv;KI3oyk9?RMrMDHmv)i5-a_B-DI?#+t&5KJaZr6~*~I`}_7I?@x_2?pAwAwTO3h z;-TBA&1Z!MYUs==i?)^BN?;qDFDgc8&t8b7wDfLmQ^+2av%K$(`=0VTd0u0zv5kki z>56JGSy#I5%;qG{AmeAPI6ISFN=7b|d#kCa-mYHV2wM*0ZijgBM~H&#-$Tg6^!CTP z^7OePJo%|-u(hyr$M_IGGjnd$hpkBi&!pXJX7kqqeX0i~LQV*!7pB_78-(r7gjMjR zdaBRQzPl^MLClh@)sPCcdd#_a$3bgsTj~+WRmjsDTEQ-T1DBa8JbNf#EhOc_pQ&2} zymt*U7!tX?z{?BSaDyn@;p)OV7l z&oo<#dW{$lU&UeZI!d+$-TIBSvU)w>gW^0jB9%oUDL-6~nROL}VRe6c~geiYa7 z2BDqZJ<9&YIrWs8mK|32yTzxAbUpOzH>kh1h2-SZdf^#C+HX1Meh>JU12yYA&J+=? zF%a(2oYI!l4K3;ohE?)Y#lDsV^K4n|*Y>E9I!Z$E;fQ zSb?vh@xtjTd+u1rxN`wQ>~;>?g?o;+;t%uMsY@9NmLwR*KGYbJd+@}^)&H{fX#O?X ziS%yEi{DQhXP8*0#CP4dHaXgt*>eu9_8s3|%5&>VA*paXjgJ1!&%OUeH|^ofr%O@W#WHpRzryLh^tv+28t^IZZZ zmm#!k^R`j<<%Thf4kuJtZ|yZtoV`BrRD4PJ&7&gwT%k{+JugmtFPnYA@tl4Jp3KwT+9=h>i&n&ivBHFi(#WP$P0sE!s|)zn30{$-Qc>6gLWx0Q zJ9-}3QG&Hk9GDjEKi8{xNF-eQBR?;y=uPBb*Y?8X+9@^;fw)N12 zw@`#y_4UtaovZO8HrysJ{A&n~!5r45U=tiAwuFpjNPG)A;oz1b80!9eMcsFL5EkRU zF%!Gykn{n0!&YeEUU99=-nx?-i?IZiDA04GzLhrwU(?j$&WsX}G7g8pqhbF+|*oVvoEb#kTwr?JX23SRo*lB+~xz zh%*{{LS$UhA*uclEI7}J$;SLv85~%u=vVsC~z-;nc!HYt=?$W{9OWzQ;mN0JyM}`dcg|~8?8$4%_*=wd! z9$oe6L#mq35-N=l`OQws{&n)cYZz{czQbp!g0=}H*!7a$q0@Jt-ze1YT}|Mral09LUiwbkXBL_Am$A_&J!kYSs;&Nr z96L{&+MaW7@iC&7V z)8b=Do*n$kF`qC{0Z1_BnHgWSPji%Y_mWGrZ1-ZQL!Q{v*9a+yH}7KaHwBXeAiV9w zW9`R>6HH!2A2#l>QG2i&ms7r|phQ3XQ{lmz`dfRmS}Vja)LEH@$(@U?Rt+-XvyVG^ zyj$pkO5PKLQx4C1d2j6P1Qa#psq_1MQw(z?d175(j9=G%Tz@+1h-vmhUR#ml2h}4S z)(kyg?{?oBVX^(6m33X}qr*k8EibzGKbm|1hLoZ5PkX;S+Y=9w(Ulwc>5 z@o|T~;Oh#@l_(SMlc=|j*I|uGIpmM?H+PEN&-*Q$9=~&Z`|B6arF5;T46TM_WY-P0 z1)SU8Io^JQd1j5-IcN8&sp)E%+c@5ZG8!1HlG&&zA)C7pC^Fza!SeCV(n*r=_JOCs)6FXY>uq>f=0Jozr-HWf3z=s@HJbwG>b8%CtXqc+9 zva*+#7yIp-;eQwW==9Ece@~UW#>U3CZ&#{LO;1n9#GLTE=4xh^q@+|>SSa7RU`)fV zl?;5vuPFF56yzCDT^xp9JNK`2_;m9b5lM2XfmXO@^E=;Z9#nCWYIMT#Nx}H`<7X@5 z)&3m2puYQOckI|vU0rQqVR7{6(R=sqU5NOu_kx&90Y-BQL7$y9+i}U{ z!J##DSy?<{@!e@a-=eM#M)CgrcPN9se|LQ6p~sIOgZbs*;faWd$j{FY4i2`-FGiN( ztGIe|YODwx@_l)IEJ_d$j~Q=43H8Tac^-KM9vy|idg?ZWxD4yjw!W%Bix zpglW13$wPizJ2?kM`Ydi@0Zv1|6SMp!w?80RU`hUx_VP%V`D>ufUvNzh{(KVnh)i# zM|@SqV-0y(bDTeGSDP9T9I;k5hV8tlf68^E^d;2`Yra+6(xiAic?Yzzh*Bje-aOG~bhy{>wC zdKK)0BlI|8tx#|ni-%NR0d9Q4#CN$fj92|mVF7l0-0$anDw0abVPE+E(PzkqkTa#H z2kJ##J8alX`@%lR30sk=hGJr+HM6wkyN|IPA?M{doyx2=HPKtb$jZtB%i7Nk$KCoE zeBp(|;UOnwUC2vQ1RMr8K7Qobv6WOrxut2(bw~Tl*0IG|Wgjx*MBOJMbjla7u__^) z@?mib_I;Y6&I+{ErK$Ei?QLh?uV{a~+jK%bzSwQ4H+y)ec@>n%sQHr}pj+4vTHzxDl%Fun@OhmFC~L&uM? z_hzdO3*No@Pa7O$&>NcQXJJojl;h+RV!otz2v zuVQ_#sH}%dY|{@|#pUHm{96lOym-N<5qBN55bRA1W?q`EFiT4FKqvch4uT5vtd_Li z+0Jmd2l)H0RnV!}W_k6}VP!TWSDcZ@#5hhmzd$P8fK}TDFWUmA(z}XM5Roe=>dGCP zTSDpArKMpJ`dZIVr_ORM&|`XAZYm2JlqVjOXO_Nun$nl@tamEdtH|`PH+HaAEFo5; z_5@v!rTp{?2Aqfk)~Ds=IsP^wF){V*okxapLlfS-X~WP+qfwRv;(V6chALXNwy0}K zU3olQ5HaV)@qzcFZ`yLdy!$a2TVb*T0SKo;`a^>4taiv_a*F@7WNv!JwcQKKa4Z z+Qv$?JiNf(zFZZ+$}MTL#Af10stSdMa8jzpF%TcHKE-OdyvAR@d3jS9<_l|h{j$p^ zDaLQ1zIe+x(tfcF3)9yMmjs&GPG=4AD|H%lyA&s2UFU5i7IZ=bePy~WdFxI0^zZJy zxqok;cB;@2v+c@9Hd^%OsUT`&k7khiga-3K{U)Ca7~hwNsp39eK zWDJ?iDeqCfIvS{B;+wCOYvetZ3|fpchOdxt_wwBgvBlV9$bkZ%Co|c89`%O4t=+~C){=1O51p7 zh)SVu-P+~Q^Rp(_(b&D$BFfO^ML?>hkrrwQDlLidR`cnO{2FMyX8nq68Ly-iyEgNL z7Omob#fN+|Gth#gmzi!C_Qmm)$5;w2n%=Fp=h-QahqU}oXn(OhumRUR?Ck0ilhTr+ z?KC^Q**f+pOQst-{1acS5@plHX_I5CEuA;1`PQ!Ssfz|`OH^uH=9k4 zGHDh%pZP!dde5*Xx2+3wTiJ@BqJUCW6qKscq(((RK|o6A0g)1V3n3sSDk1^`DotvX zDue_fB#_XQDmAo(4pIYwfDk$%x!LFJbI$(meV+R(KhoB_-nr%)bBr<9>*HPI;jLoz zg=uQG{Wd>p-&AwE6mD+TgZ_nZrn6Ny142)z{SAW?O0GZ`rDtzYO#F|QHX>I$9kDCE z_jp z`*=#C#k@=kc6w}bKclvZVYgU#3WsJ5|{N@a|`Vw}MTJXIG4Wl={zho=w^ zmJo73!4o_k;&kn_Npkyrr|qBLzTI?#&jxNWPoV}E)4bl z_KYcyQDeRdvWe=1Pl#XY&KEwmtW379 zDkwISj2*604=XceN0;1l2da!HZD+}UQ&%&qx*KOsR$gmJGb(Wo&=R>e?q26R6EoH%=ebTS&tDYM zU|A_Bbt*o3el-7L5)RuBfD|6vKcM%DIWBoH{Wa&}a$fPBYiXTnd14h?Fx#{~jvwITbjKgZhpH*`|Mw}@LEl;gVl z;4%*{-zN;PhwBq^vEc^MKMGi<;Nr%_R5_wHh_$Y`*c}S}hEL6wdqeviXE3X?_QI_z zMwwODaC_kO{AaJa2QE7QOt@ty2StW*_tPE^#^U5<`&6wuu%`Iq!`P1+^4>YU?rAyA zOZiCNK|(xSNy8VnRfQzykNq)BcuxN0=1{M2=I@Jqb4Dbh_un>yM51acTf8AGG$X>d zH&+1NoqM%5B(c~GQBVQ1f4u-8U0m&BH>D-dZND}W3RdhiXL=Q`wPt>nin3d zDK`yK5rWc@?{3N=WcXwyTMhPdVC%!*P@X0eO|R{`;ojf&zQmc>HULCLLiUD6#YBE) zD3NlnuQn%l@cGLX7?2AK+1el70O|`SJZy!PAXBVBtseWV|y5b?h*L4 zLo%S17~TIY_T#(}B*0SAH3*^|oE5tZ)*?(}ca>{u=To*dyr09y6G*9Q{XupLaXL;T>=T3Tbh?of+U1B+Oz@Md zsvNt&0u5%y9tziB;xnFH2L`u%%|BHjwXquU>U>`I#MTY;`P&%f!}@1LKY*#~E3y03WbmOy~4<@7eaWR6oC zZuV1mEfe&2C_80^(~}~8@QI3Ok-}Ym!1Ia}0NHx&Lgnj_4w+fIRB-KuZkT>0d|*q>=2ewo|#dJ97&Fj&s*cRn!KP!_is|G@7v8S?XhYEOTh*wN3W3#VB^D&|>x z7gBSS;bqf>k&$b1>ppQQdFtlj%i3_C)*Y}71t3^|KGw{+uzl3BgKxx;RbpEHLFbFO z)0ROw7RVe9sBQkEw_q(_X8Wz5<)bW#|H1gFT_k>m`(VscI*wQtx2^?xw7-D;c0bqPI-s9X#m}e7r@i= z^NAFni^_$!-DjCr#lp^Gm{1)Me2>B@gIP#MX`9rZzb4_?r;F=?{#bZy@sb{Pbw$N{V zk6r9F0MvZaB`>_MVt!hz-X&V2aK*)v>gr>YlYkyo27_UU&>SBb86lDKEz!_~OG%pn zd?IumpNLnF`O^?=TMfqu4H36J$k_0Xu2ztoWLV?FlUp7rrTz#teI7B_DkVAKl0Fzy zM6E@4++*S;bl>^c|91~(M~3AACb(^^@T36qBJ<*gA{yYb*9~C1o*)^mEiEgP^#FEJ zPd=HGoBNmNi8RsM>wtE}@0{Dcm9u@D?lV^~o1Xq)v60!t9R7NIH;Q%R^(8jK8O(~l z<@K@QotMfxM#Zx9(|qjx&J&4gWHR_?g0cC2?E`OWrSY}t_v3xJV(~f8Oc~%&s{ebq zQouJ8wf~~t&j}Zkn8O0KW3c}_ICcpvsu_Cc#*M{=-du^27i#=|DyM~2n`*t?+{(;q z6dsh?dOFgL5Q$l5q@ydOc}iSP27HEdo1mNXPL%Jmb0wU^K zHd`Ny?t;-3H8nN;wO14su_YysQRdsdMW;8o|GVVaMb=RU8>=sP*upzEKETPY3T!s0 z*zSj7L4LkAlC<^z_wjK$$A2_Kw&?xjICB`!R9SG;2^E_CepnO+nEBlILTf>kWzc%i3;w6d-X21dD@~}c~iF=)UK(?NZ(2>bP4PWNcPXz zJ4<(L2@<573*hN~5A{TBLVDra6X@reqzlq$N#N+v% zaW;YJ@IY8+;l;}r zCGd%~qM5}069ZNh9vQrI;={TtiLT<({s~XdKf6<%@!&{7jYe?Op-AVAip=8W z=vjyJJz4_cTIJD?om}wI9em=O0^6x3^w-WxyI_bl`A!AakN%GP_2N6|NwNDCggH4ha28Oasz+vf}6GE76G}LbkRXh z*9pKrylKc0k`OcF(_{$0@P9_Y&A@c9r{GcTv#9HdjWIh!9sS2bNXv&YlE&txx9ONU z>2D7CU#?;>&v$dWBH=6J46yzhvboy1f6L+8O$?NB3JzC=Qm*ck0m3qtr z#v?(uPM)IqvOJx8xG>QFvz`VU^BMGJxyM2WyJ~hGEZ-|T0_(3|e0Rl|<@VfDvy#*00D>vN-xRyG^<>~!j^p&X zzTy~3DH1TP@LYVhfs~~A(nxiZp|*7vy5P2i#x-U@AW+|{+9@mqg1+w@5B?g;%w;Mc>8%5b4P_ zHi^)^o-+BO-N-)Xq7ea0AoulkCW&zvIVCBRsyfShaDyoYSF>t-rQ=(Kic6$kMCz}S&Z5JRZ^sFL9COP13zLsv_HMAp0$hA z?JC4is{8wH3deofLse~bohGvD2>#a1)_3_kM7{%vbC`C6_x5l{!Q%|g*070CSiH8> zpwAE@OjRDEDWMb;vAwd;52of@H{Q)KOiiv)c4}QV_)tVr>H4^dYTm?`T^7Xq8>Y#$ zPAv$gloP@IuybHyro2bC8nNL0&ZkgNL{Ze#1h{aSbNH5r;{!eCKgICM{(2WO@M`uAuM+uW8ZL*{_ch&+Lp!AOlWNFtCbakLT2w6Obc6=%wT=(~Sm=SP z3|(3zFOG~_rwbIjhs0}JWS}o!Q&jRCEzY{-20SKnK<1g_qb6uuSuxv=)^m-XYJHYA z7(-i=h^2baXvl6fnmnIQXxW=jF$94t@g*Q(E_c%I%;k*3fk%Ucf3~5#^VN>oa{9~j zYz46@R2dKabP}^@x3uC47K1j5wWTCj>R$2twyKrVmgS*gPSh#&kOWg$C63*oE_P!G z-o`Vzu;F;j%i8;*veJOTX0oCIO1QR0qL0)&Y;Br({sLajX$n2i^gX%k!%G{Z%4DVW zW;bZo@WtqAB_nH|q)!>Pqo%s4lDTV5xXtSLpyRI*leOQ$u=^Xs?R==nTt|<_3U{FO zfR24BRK6x5|2)Zl=$?UdNbs|P!1`Z3TCMKTO<{2xe~B^1ve?;C3E9(XAK?>zIU@hY zL^mJ!qT$S~>U!KtU6op>rNz!o(9xwKi1B(shLTae&kxw?1I8R8d~e-YD_vu1ipx~= zp)JJ5@u#z`p{!e@Y+oeipaXt_b;?$VokiIVERU+kEmp?(&L-PsTQqoC+Zh8v<3j~x zSJlyUYOx1ZkVG{ErRM0D%_6EtP*SZ^znLmOL-vZlzoxgYw+EYT8pL^-C^{`81UJ3V zl##I>_9Hb{sj{7_p_f9vo*wqe*sQZad6$&ly5L5+uc>~`rEqYaccQl_s(X9cE!aWN z&t-b8q$M;ti+7-S$*4I*dTaCKP1&sdT^uv9 zvKsFh@!a;KdiqEi#u#Xnvt0eC%mqgYqd5{)RW0D!vBH^#l>Mgsq|H8G4@m{*s0K!E zpl+67sauI!CFRNEp^~1=Og%!|!1xyr^~4&VrH`U;JCOiM@#;cu12=!S&SF%EQB+pD z2U<1c`gb3Dr-n6aP{eSqqhq7wX#2VC<*_pFwmk!+l6K*Fia>V-NO)Yhi%Ss;-R$!3 z`>&Gtl%Fk*Ai)P;9JjymtV%WVF$hoh6~{x~ENFOxXm|X7u@MEUESWiRzUVK5$ zM=DMrWYl)tHstEFw!W;4O-i@dZD?r8G0i_H_tyI7QT-n`zt%sl8 zuTkD@7Izs)7O)=b{p=+v4RkZx!da0V!^tJ_{$ji~KX5f;LKtVw+Cbw+a*4)@TTwB-iB~#lCYdDJT=ukhuqT%ek zQ`WFy7fp^&e@t2w*1Y^^N>|^SFrwCRE}>PsYg0YE?g1+zdZk;*V4|+SH`{~kWm`kv znUE(bT(&n&gf3SQW8UYz6T8+0qG6q*FZ&sP$cP8>52|@0)Z8&1Mj`uemL~}^cY49W zzrJiVUNaBp{x9(mIAzPKfimB&JWVN|;!o5J2^vX-kEzpO`4bj_tIr6a68V5n;tSI? zG8TjTpaQOo1-X%^d#THyb)?EnIAD$*Wx)&rq`n-jnPfot{)k9o(@v+ZXlQ7#1^F>N zgl*bsYik2{XQ~9R&$3NNA3uI%(*#PML!W)G+?qjPv#gk}URCK`u)B_iVs1`(9^uxeYtZ{&h)5-61*J-ovKc~M zXd2_TC&}7@w8l`21r>#}1ajXBX~^e^fL zl>R($6a~e(1Kn#VAK!oe`8E`U(zzwtbxz640oiju>qu^8Jj*;g5u6 z7FU+ZgLd}4kTEHwfK3(C%fomu*}@`)j&bSmuo19P1ZBl_DHg`lw#GO5{aFz=bWbi7 zFIZl<;@?wa&2}_pIT%SvA|G!h2|5~Zv2p6O25n$ORQ3zf*fcfJwPXDZ>zhWfDiCR+ ziRV+Q%MFIp_|1GEYTOvuxepG@7x2qZ-qTa7I@CZj z^a42=c%7@n5%gTh0T!lU8)H8^t8l~MV5{I@mwUlh+Ex}216o?*hj5WZzI~cnme~`V z;m>Y^?i*)STwO^616yXj%?E=6Pqeg`67G6=9T{}oGkR$HqiFftTpfogTen)!id8Pi z6B()Z)*fi9p^mWqYFqQ|jdiVC-dpi;AX=D{&;5IXFuj4I7{gXwSv$xj{7p>cm3;md zq3F2G`K(N1^6cl`ovg0NLP$f(Zp&5Ot3omf_Dko2uiVD#=r=~%jEAlh=j-A#=qm|1eHAh5B1KptCPfbir z0Q(e0`S8iJ-)}41(Pt#!3?}?EBs!$bp?$Tx9FqAo{{0vJ>%>TdBK!L#l&C}i?pCgz7=sKv>$ zB&~DYd=-kg5AbZf(&@7z$l9`-h^=JPQ%`EYJ6GJ{zf|H=h>cf zA95wGRESot#ukB7N=AOcYi=8e?&N3{N_A@ToU04fzaQ`of#9EnN`>VdHXJOnUQP)` zHFM!P0%a%os`f4YGtkv);rEokh^?*b3&xbo0_Uall6s>QlVE4 zjDSF8%AC+R?@jPtrl`1Kn!4BgG|6MzMM&L44s*VtXQ+Pe)Xk~OW)$b zHQu7)fK3{e{z&cBme=T6QPG<413j&Qg{xYRxeU?@6vRF0gk;G0I7QAMu~aL6TM4TO zMXVCy`oq&1v;=?wECbsO*ETc%B8mJJFt(zdT^*)T={^1f==b#ru&BsYDlTCR7p|yX z4TEiOj%H*cm&}(0I!sSDm)cwmzMb$)4YsH%#c9|aDKqJNGyhJtb}lI?|FvhrFzsA6 zv>^m&`QT@p5U9|awHUvdF`xL!*nB{HKVLOmRrC2;`s>*SYuzTXRk9zKTI%`wz~I^F zO!>%N85M`{x?9!UPNY6vi$aeDSADfx;9XYpe`IfN#P!|eEyjYjk0-If!40LY|vsdap}}HD9bcfAb&^^hYeD9zDsRLn8h>{(|;SNX2C8 zfr*v9pKIlQj)A`N^P{@7__xzTq8UNupNn$REc!hj8Nd`hNKkFC>FMLgS5BQeIU=kr zq?(as++Wb^a&2`S@7!Jk9n}ikez3~L8Mkg#*4qeMjPG|-q`H8dwdSTYIIH}565T7h zM$+3i8e0#CF^)8DG{272-CZ7n{NAa{A-vgom*fgSXKs#0z?M~#-oNi1$h#9ca59Ls zTkzQ%XKw~B>t|K0N75k}?w!~BD?;+-5iJ&9Z8V{?hv$Kpl3Jc}KDogDvJ@@u{PDpBAM+ZF$(b8pu(U&$7-FEeg zJz%3}k8Q2(Y6<14^*aG(4TsPbzs9R8ORag&lyAEl8r-9P0acS_?Cwi`rZ1@u$iL6!fLe$RhkeY zuY=8q_pGDxen^pWmxQ`wW z;?Sj?pzNt#^^dY&SbT+%R1-t}UPD+sm$k%bUYERT3vYQlAqr71#JxsVpzcU$O20uW zTz9Yh+9ywPPM<&5i^QYI=+n{M(L;i~%eCN+KJ6tj#ta0xxl(7C95QY88Rq+I1vg=c$+SoM}G>=(Jv3tPEqdeS*v>c3n)1x{qVt^oU5U-(Gorz+vL= z9z&-a>M0qWl5#C}muXWI;a44$UkQDb9X_~OrYPBcO=SI(V7U7BW2j@bxV#@_<;WBV zk$k>&_h`$TW?`Qd*C$!(8E0xen}5h3Q&hlPBKtD|@P+R!c!yR9vY57XPh&hw)xd6R zEkd&cCZZ=N<%aeu)u^3RzN)_b8_x$yWa6HBg)A)|EU6!~vxMZ1+E+W^lceaE?1 zf6>@a4$)nSo4_|h4sxP9A~u+KEGAb$?$-3vr{4qXC|dWg)P}*bIyHc_&hM)K&Psoz zHnTZFyt2Lf(DO%hvVO|DeOfAOxAxHX$^$A(~9u$1A>4x1%?c1-`R&pQ%B$fjawVv%2i;yu&SK-Ar5B0-_X5fLh z3`}t@9wjX=dp&44CvN|C0zXpw8vEAPDjQ_Z;ciPVKQImpaRmREIHFcV>Eeu+K})Uj zu-!`qc$ouFv+pSvkw{_=y| zxDQ4cOd4crK)OqUH6SRh>3(|k=!j}RafLp9J0$q~)H+=fR9H}_ISd$s43}65M#M27 zjLSfqMDkT8=FHjjZDJg69Pf#0K0=7ksNe^qsSh^#0{+}Pa-gYmK{wImwPj*zP!>0_ z%^OoGJOMMzUvee$uEdTnYP8B+D)?N`*^OAJoE@Y*@EJeD%a>?8EH7$u-@@4xIK9%$ zSyQR=hJH)cT3?X<>~Koy#)-GlC{G_(q6+`al8PHS6BV^pV7{bk9iY8Gb5JwxvMc(t zRF-xHRO6&E?7~cgk@y)9Xh?*(ykd(_M`!b)D7`9F^+>va$>CfjIfP1B*n2E9n38hC z+aoYveEvjhEe2%@vdBIC{Xr*beo}XiF3Rmzasfsq{o{*29ZS`7XL!d_;I zQ+*s~rT01@Gl%3a+Oo0J)5R`SR@JhSOzrGUEW@u{S8`eHJ96!q;$q7h0;?MKVBtFo zz^qYPNYczZUYRGaCgw00*`*)bZgg}>dD8wP(JMQ^x7DmZuVmfCL6izf$UdFUdj^s6 z-jq!Cl^&A|pJaAY0}Tv2yTxu98y}P5E&A|?qp|RqvkUNdVwM_|U9Z-LxI7qrWT6Y5 z`_R7@l8ORk+FA~l^t+C>n`(t^MZQ^W^Ff-yF78vh)5)2gjXyF9JJ%B0RDeZGE1o`& zN6#(QPE(@UDW(lzPt0mhSOr!82m$><)8`ho=jPH{W2S3y4-i~NMU~a4f9Hu8_ufJd z=)A;my9#Ri3at~ij&hs~{*9^BwN5h+4FeD2925oRm^4n7z!j!S&TBQ>YiGG7yX?+d z>69yUhUdC*E}FSnvCOHK$1!lj5n7!;1^4#r#(K@i?4RGEGS+eCvk2rsSFvep;4z+cKJ>(K)@LX< z&I?rrudLAL3B+{OFjD+62TI41scB9`s0)fy!z#ttr@m_H0P=o&1Nia;C1Ec5nE|Z0 zdMQDaT^Tvh>iV@evDP41YJq81=hBt0N-w_rX8Xm9_BJY)@I(D z0+&NocXy{zkzDv*O-^@`OMf8YuUJTwO2(NGU{+8 z)gh0Tf}aC1LRc%7ZIK&$^Ei7B?@gLWJO(|VghOEz=N>23Q#Ljo$a|DCs|broAsJPB z388I5W((%t=*FQt^PL%LONFBIrPvmL1;6qfjSi~ll3VyWtOSy$x!Gu0xi74L{XPC= zSh$#+SuxZ@1EBs?PfE?1><qe zcAYk;Ty@z~Q^&kWC=j7r(!juENY4ncdL&v=7^(>FUKuan85IQ^!ZPv`>TeOpX_Si{ z%0{R4I?#`k>BJD6k)1&1rwo(P{MF7D`L^DVU8%u~%B2sJ_bA=P6$CLm!EGVVXq6I8 z(TW>8Po9_<>qZsq4RtpiR1ZodWyNk9jMaOzG1nQ{i_^9+LEYE51aB`JNB4()Oi+hd zETmWwL_nkCQ;NmHd#f4q%WZ8%W`esEJ+C;bC-uwM+{%qq)tN5BGyvLgkKI?9ilUx-9a1fEW0Gd{rrv zMi`U7q;OO3(%R$uI&P*O)_MUyxs|=8@V;G2xk4$Uwn1Q+o!mj+ol5UWBE`g#K0qv8m{$?TiD-Dd)-PbF<%Gr!d}henqX+9SSi7xjH}$0(U+hgupn!703Y<%Co@TPD@cg zoI0{FvcgHVzNrT8?e$eXP}*fOeKVTUA?WI}k%6EnSCRp%eVnuM&Q=EJe|*MPY&^c7 zS(z}It#QaWq#=;DVf*cw?t5M)zWm!QHTV7d_N<_<(q`0{8RI48%c?E4KFUpV?-MN8${p6BOW^+u0mvqij;yHX^ZLGpXty)Wki6K~Ki7r+r zAp;Wq@>MAM>umrZ9xtGyC6CRpu}$!Lz-+uWKz8f*i4En9kK$2S3%1nAcC_m%gXX&a-aNwZ}#;!q!JM;JIm+-I_^>23ZGiPL*Q zBJcj(R+}`L=mbb(^$Vql05(u=mEW@UL)YGtvBr97Q(!(DHW<%&!so0XdzZvNoOSq; z!Cz`u=Q6z>p}X!OV8DRP70ot91N%Q^2z~RcgnuTM zQESrU%^UA6Qy2P*ZAJ+r8BP>H>Q#=?xA8Hjh(4vHp&5isHyrI&q=ttzk35|`QpQVo zj`s8lHr2kr@DUnb&ctJY7GXOJ+3)iqfx?m|z(7SDxj@2u;(XaCdo;*gvBt)ARd?(C zKERR!P3Bn959HR)t{1>0IoF+EG}hZo-@^uMli0_gDE6KW*_wrZwWe(mW7yeqg>$l2 z&BA8f{WdGOezK3I7AT(W+N%^8I68dnO40$Q-~p&&5`fn3RSI z(K0t27DzV992D1l`6q7p9egE?B}BMiA8d^7oj?RCn7f%VOonw*1gqLz(HNTk3&=K@^7SB1xvWPU$1*T!dohOEZz5a;W> zn`7Agp&tw}NFN*AU0H#EiMHzW!mcTb-ntt5jET@ouKAVQTSJaABhPh3y#JHgeZt`FuJ%|)J$|bCR(lNVQX#%HoL9kguDZ#mF--7Y6CXlKO(X9xxk)-0coY>-&GhUb4#}Pj zO4WgiI^k+uQ4*(MZjmCV;1flD0a!qeKns*i|#<;d}tmjgEIe-Cc^wV2Tj!O zQao*G^}7#1X^f+L6KunIb+O{6?iCBaH%Hpv!O?wWoJ(OVN04DAR&(QV zX!f0&NOnqK|7j*re+$uVK^h&7#_SFL`SOw@vSk!BCYPRvy_Fusr&E8G8Yiz^-N6Q z#eS56-nf)yGeiHh5q^Z;F9@!OEag>(D<05B%|nAAv#`OrD$qok=Y>=W*u3*9gZ5HC zd#?sC$Bvy-hS7(|2VXzR{HAalLb#uOQ>uM23!akV_{tN6o=12P(y>%R&bc-YoDcof z@9|!GHBAeQk#`?autpw0;&4_rrfDJ>vy~3CH(55X{r7G&-%O^oK?c3JZkzE!mKjAk z1t~acds0|brL29mq7z1w`{B;Sg77FA4bt?O@it|R4dcU%bgf@i1JU8M;c=>p-5_i;ld~|<(Xc}Pibs*%DDXXL(id%BWtQ)>r zJu$R^4;$pxvP`TE*=`ok?(~uN@pk(sbygRthUXK{OJZZap5ZCPzX>o3x6m*l;DG$J zG`o9aye@pad~r!@lZn?t%F0EL3*q}cieP3pE%qnaB$rZYdRYL5!JsICyxP+~^=x)1 z?HrFPd1wktd5#|fdD#%&nu{3k#m6bF|UfdiUNYe7G^C!!52Z^CKptaUA}MR_E9; zQQ_V=BaT1xBs)l5);*rG25IIBd^71PqheD5YtyNZcp0T{?HZ%hi|TiC$0Qnh!RV*d z&O+<%vXhg?$dY?GkC8X1!p-AFlxD-j*@=ZLHT6Nc^eXj*hs@m;a(Dd4nx@acX?C%L z$BsR@d%Edg54C1z-%mfHnY&SyA_0PQeLvMZQv%~WE%__gN*sH?k&p2g@!K{XjN*JP z2cNZ+>LL7h9pS+nIfeC9@a`#=v{AkGOGEy&A4K{Kqtu5d*G#9QrF=n6D2?P?n`@X!beKfY3TLt*Oa zy%0y6d-Goorj{aj%01k4Ak~Hvb|(F{5G8V=6vfO)1$Au`&v9P~Z9NzMkVK#cuc%rfJ$oQZPC0(F=>aMx7mN|Lq2>X*fw>>rt zXafrZABiHrM;BJ=K1o{DDLu7!G58WLr@B$U1mMw11D@0uy653$8s3REK+0`U^$?28 z!rNwDdjf6LWlXBK*!P zRy-YYZI%0Oej2XrHZji{l}bTgcle}mr5hT-b>)xjwJfU9mpA_rQ6=s1)_mc=+L8 zyFazg{^+PlC`?kk5aV|J4#az#r*u3j=OfqIwQ2&EN~V8^=D0HdW^UGecz@XYx_Sl< z?B;8`{>8R`)GWQdb3G3=nj5d3-9`PkMkV}w!BR$B*yp;Zn&>noA8=0EvceSX!!4V{>Lw?|lCZ(rv$BPk6OsbOu^Dg;mjLmrYmq;Is zd4CC7YLEgX0hQfVcM8l;7|>Swpv9y(EXmf`?2$7Nl>5l%!tD-ezoQ`GEH8siN#jy; zk{PL3aYVNGrH6xuN8*>rNEgnt=>g!}lUIx&&E@D*4j2In!Dd7~dUFE-0X`OQKQ9B;MjZ zYoLK+Vja5M8w9q|CzgFhBXb-bhHBz`YQl|{nnFgNT59hD<+?oyO}AQekmEa+X8x@? z`Pke<_xJ3}DG|Qgt%7^UX)B-ac43YuvWc-9W(Qu6>bCfk~W`)FTz!?LY;^0W)^cQ%Bn0-~zqP za78vt?LZ)d$DrC=E5urCxyU!*ywa+>q-!@feN&@q|7oDi_?s^&fiRqsg7N^6d?Ef4 z&5j+_bsyC@l)iF#X9;RKQ(*fdLl|Z0dQ>rKVy(%-cyM4u`eHgrI6ZzoJ^f9}acn`g zjpG0yi#CoL)77bmv(MKdad9a^x%Ld7RB}dTsD+V=WH&;O4bpRJ{}wi0aNc1z6XqG8 z8#cAKTcf~q8O{S=3q_yLq=ig|Z=sbDwUp*UIIG7#8^6~Edvh?ysYKN+{K@Wm(q7Iy zEE9L{vS7!3G3zT!2-J<%E1MsSnoW|9R_RorF6xeRvTR)f9X{O$9V{T&9r?NEf0=JC zUF_fXKu`r&`u*A8J7k;@e8nARx%1<*eEt;2oY5t{%(s)Kp_12oB!ae? z{kt**vS9~rdSO-7(6f9>cNU~6`)}m>LLEJa;9A6s4q+zC!1cU+u)S-!;;JZ(-$a*h zkdqZ!HD$T&Wi0@yxgr?*q{3pP=mF%}vz+R~W5wYbxhm-+Bi3?qa>Jm}DnCc(YvG7X+ zGkPa)D%b03%Y&+@Oo;uQ+x*i^Dt*aD9<{G{;>pEJSdf8?jGp6TQL(&Y_lLr^DxVwO3i+n>WX!2L5x(QTbopXlgH*Y!H9iQj}%2_u~Fq zfJeUno-Ff?Nr+I4KLh;7a-L102THE%=fk%#Fge=%Xx0Xk{zXYT#&%Vx*oku!gF z(zW)$h)0*f0qv4QSB+|&qIJrfoKpPlcfjJ0p-L4JpkTSaYh0Mf4|JWtfAlOoRs2n4 zPs+GyC*un4a`Sk6PKcOjm+Ab@Fs}RZ*brkUt@^6fM%WZn>0=CKe4rnM(jv+5ko@YE*s9Ph({o^Z^ zaV7A7ogz4Uvvm3JhK{DSQ_tg?citnuO@|Gb4@ z&qiC>1r>j%|1_-s^~2^z*hiKvKWxA1@ctg)^ZA64UbdCN|8IZszy6tA_N@8jUn9MF z;pPcT(4<5%`xEQ6{|{Sl9TnBPwvU^rNGPB*NJ}?Jj&y^xvX!DKCHzbEaut!iF?m}uKT{O3sC;}xBA?*Yebgp zni&H2BXr^_-#pgU|Ni^6ueNLbiM|WoQ^fx}f>(z^fd2!aK9Q4?!_&4*_z?^Uq5M== zj-wmM{gkutAF@)T5#L){ynTGcL`6lXwJa>?|MCj28Qu5~>V&}NM=--{+>A_#obShQ z3SSk9?Ok0W0@i=CUV-a|Fq|U`)*vkEUV3zY@^fXPetq~~MRuS>fAl6^x(8c7Eq33t zK!bUgXKJR1ib(Z8xl05cAVTa&uJ> zi0A23f}3RjLCyIf7cYuy0rZLh&yCVj0-XN~jJ?VXFl(dS|9$Prb0k3TEYV2c*w{E7 z0UZpD9}R5%o+?SYnw(;I&mgmT7lWk(2$zrkd(fzVI%j5nz1Z%*+82Lzd@Kq0USLsA z0B&H^Mc{S&_}2nY{)6UujS8J{1S=^ii6EiRdiHLm?*<^uW_RP=PY~%{{O;TT^BTf9 z3E%=NJ&};0)68EWK)PsA^9jj0^70%55!A5F$bKsRYc2pN#>eXx-KU@$(dkAA7p2JH>7dvo11GHnrEL6zoNT8 zJ2Nt!_8h1~h?gXHjgJSa!;wq`y7H4?nOAKiLj+$+TrPY&?L8(5@w+~xrN`Z&o;6p z4q-pK|9MIQr6gE_QXAC`xHL4lciI$MchONT2^|q=in@IL08RiU5t@7zplcB$D&!L* zNDAH1*WHi72&cK(NSIH^#$5GGr^j4rt`EI&k;(1I4R*NTaHQgX?ZR?mDf>h8>lb^T zFlhL)-#Z!44{=3m_tawiBae6Ozc!I(nf`j&esn(5HSGw^ikZv#JuRu5=RKZBvs!5C zU?#4+0@a}a9E$v#On(bM)n~Jbw6!3T8lj(0{&A6Gn*1H+!8!3gR@T?h!@qUwsb}A8 za_#N$Vu=_G{M_rkFY(d1;%{dW8%D`Cw(5lMs3F}8OW{BtG5A@^F6LYA@#UyLdql0B zy?DoxUc!<8L@YbncC2qcA>#5|zXN+2`6yXj4cO!bN!B`+?G+SDPif7XAfyW7f z@Tri^+5Ns9{+J-`q|vwSBICy;gXODJruJ3faynsI{cKu9S@tmvD=& zY0tt_Z0tT|ainCdv*%Nrn$O2rMjJ@d4X1~XdQ-7PHsYUy>#?_p%gCYrd7>kzXA8S; z&woUk4s_TH8L8UoXheLSKYu%D=T<`cJzO?&WoZ6fmztC-I&#iQ!Uh(7amZFDj&$Ma z3*0W%wUFE34X>s4DmK#RWtV7k;CZL=mRhSWC?~F$k@_+wuJJ^4k~5~;W3|>=Yr9aE zzZjM>Iksy3immJt>2@(r`5ju@UqEY##n`i6Nk#3u=ZSPQ_LXr-uFEPQGk>5>zI8CW zr3-Jy75Ht6!E2vVU?#jpBORZ1(jgeW$kkiM-l1;hF?s=4h`AUi=$J1>d z{pF7Sd|(G`v25j_-yr)Jc&}gK;Uu}$V|^T}Ng7Et-#=YSJ+)u%;>)epFVn#7)`!fW zAbKh77ktciX6pAOE%bwe?*DT2Lv6wc+Q2?Kj-!#Bk#CTb_@bKBtd5$IK(2?fQuoGrkI=*C+^z4@ml`h`F|)ZS*^T$T*BOJuE>besR*lRm`rzz z7%s)F5x-^0CGQbWY8qSeu6Lk1^p6Vj=pg?+(>vXV_KBFUdRfviSb*~<3@Yn6UB7bs z=PgqqLv9tqNQGAy)*! zb5!8F4Ts40-2SuAvrhW#|5)Bih;VG=(-F3y_7@O~>*BX73xi4N(SzNjlF~(*!aD248nU`;MNiasLv9Kv59DUsIB3#R0uu24jv?-7o+>DwS zWe5SsJxHzp@Fm%jf3WoZGS>ldRureDp%OyBWf1y6$gv9TUL{~$pIH4H|NJ9=l1odw zq>A?CBd(U`8OZ~b4(rm}>`^AIpK9G5&lrnwnO`3CDQGeC#q@OfNIni`l_vJ4FQu1I zH!O!=UIfAa_K+9)#tX7=A(Naf?jK3>y@8bIu!&MBUYj8h|Lw$ZXsudc|cbf+k62w zasRywMcUi$W5O&2DedtMi8bN)-|LxbuQ9wyrX7WTlqchRhJ~kJOKilA*IG+lEj8la zGjEx9S0Ca0Kh1=6T_TT2JZ{**C82!wySF7Z1CcRhw0bsMp+yDxjND;{jLCNXDME)D zX$e1I#n}|A{fJ<$uUYC+9evOYCgQF&)MKW@usg8|;xx-~vpd=s9~5;DKT=6bSt#AK z+=kR|8Jx0n=1VUN_lggd23*fuOH@X<@^?SW(I}G*>629`>$ydv+Xj$F=_GsE5D`06 zqURiB$DKv65!Pk8yyv-gr8$^}_ORa)+Gp+Bs%`<^V+Ao~d9@DZ4PK)xn|_&Ix0gWn zTRTNBHxF06815HcUsaMyVxJYre9sc+mUmpH(gD`oFY(c>Z@x$WJ=_P7)x1FZw9->^ z5~AudW<3|5iOGux6@^6|yF5Im$`TBb{o|V$ldC#ohp714^}YJ(YHO3~wuh=yVSvaZ z`GH|Cg0^JY$OzWU#$@v&8?*@^&D5#Hfms?A7qv2$h&{AIcv+D$*o)ewm~bVx4IIESlbn&$YSL+Njib^S=D)9TUk50*n;(F}-{qs^R_t+#zM*%O@zD zQlx3{wnmPIN+8dbO!wS|2n{d!W@Q;AP9mve!|47y>7=kckOENHC^DqkG+dDU{QF_S zs`7?{SKl%SP2cBx9ITt|EkD>DdX43NSZh|OG(B4MhZO})G|bbeA2_4~XVtsH4p`I@ z2yaq`FsyX?o+cu?sKgSMCiY7HV|S zwVGlXwbDh0IO$a+3qMv%O(w6jMbs|awjVI-izj(SfLfe8awNP?YDZiGwg;48>|j-VOt&ta=`w%bN_^*9HW{o)>HH?i`6W*LgtmeX(im1oZlHJyq;uDf&J!i#){5aqQWeeiG;Q?BV(vwepYBs^fKb-Yx%$6l5;1gR z?S=j6k|xJEyqFvx2M^q%aVH(^*^pfQCU#_N08N?_;u+WL9L~??guw5FS}kfSRQB(` zo&O~wTc*E9vJ@ois&@)IvR&vbl=c_-BD_U3X$ye(GHNr!$(3CR?VF(zA7#gv;Me>< z6h3X&T&ze7M}W7?-;0(=g{j_;rvVSTlm-y4R^%LP@|@9L6uYoh&MQCCDlBmJfK}%n zYqIyc9+BjS*Tu5@GF0P;6}qUdC?$7!81%}DNqAC|W8jgkgFXD*KU({EM@g`uIobX) zYZfchm^s&G^+KQ6@<(cv#q+u2rH~qgE-fG-!dD~)R#=J;lmHhTe1AIjV@z!JA^!!@ zqK2WgcC(vISbZpCkc6zN?|wBIeRM>Blzr58RDKa>^^V1ITU|V~o=FKocd1r*kis`B z3YJs~NEXAl8{;x*%bUmY9*=f)d;P(wEwzYYkgF7-+nj1V(L0;j)uYhOmy@jBSR|dK zemm+41`^$6+!$BAM3E`iPWP zVO9we&A+91C7er$Q;aoHu-|o)e56xoMr6-6ccFii9nMHldfg zMbLc!9w_&2-3Ypja_eY0Pw(Vu#a$#_?(5sX5%u*IpB#TnO~Yvx1n{w#nlXbAZTfkf ziM(PYHwNiKk9emR);SV>s|kZ7Y7LZP!lrpL4gWOZ%1Ukz?@Hz?sZ^DP-D`bYS$5x= z_i7!YQg5_h;=H!ka4Kza5^ev$WEJ8&_U6Q;m5RSanG2EkeMZmo&l7?o4PGY#B91d@w#&lRXPLOh#Sj96?3 z@0XH@^lSk2pgfY#!B5mi_#K(wT#1G$4-_8RErOc$ag0=#yxv)+-+Jo%{TUuiSZe4$ zWh@ZF_&wovMZ?->PD@EJH8am7b{sePiXp~>O%h=Q1G#89fyk;~ePA35b@uJ9Sk~Nk zdG@g=y1i`sL$xc<`zPHh=n5i=8Bi`DubEs*tAbfoie0n$(KJWzJRYq)E=_auZ-{0d z!5*UT@a2?pMwvxr{Y`0M;o^b|0zEW1u8pdS;S;&YQU!4Cf37DbR;(lqjcslNC zMj1aZZ;{Is_2w7;`XOO%!kmk4qY=9T7HPcI#`95D3d{8Z$W)`Oyyx&I=2(dv9=3dyZ7O_9Ua6JDyG;Fw60itFbQpx3G9? zkMN6c22`-`T>y|S5K1kA!_*2cIf!IArG9Cuu1<8w2k%r?nt8QCCn^W|+rI7=M$^bh zXL+?=eBn|cAaNsi>uzcit4;tAXUrDtG-AnbM7QW6&R^9!1pK%!>`(eRf(@>iNcU0> zi~_4s-X`v{`9s5sVnPfY|4>Q4spa9Fc?Qch*tn5}u2U14Yf0f_Jt*M5l5b_r(J+1s zF5}h;9x!q8>2Tl&XlUIH{P&p4xU^9Y$J0w&h4K7lsZsAgN{7RZ;1o*fs*vcsyFQ;% zW^b+9hgO9Be1hoL>Cl<2{|T*}I$0xMWb&;0+=^Cl+Vg8=uCFK$gipCA3b_hc_NutQ z)TaM#x#lsrb&Qg`*z&q=!NSk(4b{D@N#r&@rm;E!pQWC4}veXE>8JO0NvbmI&UVKg3YmgC_%TYj;W;cikE zT3{XWgX9=-wW0<8^y=trmou1YE0L9Iu5{nCpA~*jloEpdv)Mxoqm3F9*`_sJaWS*l zMq4h&`x1}EnY;%4wm(v>dYJZq%vh6nmD9(hwhi(28ZSlI+jhK5S@n~^o9mR7inC?* zMnYKVpPq3C$hxvC*&TB_6vdy4(0DuyqOKp00WYe(M`=ki@t5i^u}V(F6dkz-Ju(7{ zRkwmC^_Ed{%HqX~1xM{x&n~pk{$RC+9#+@V0KFBDx-IrslChP1Nk5%8?bhFqF;$kX zUXspAIjRynI+e|dAT|%*z*|-z#VJVma$HFOxPB8**)l(qA9Jzqs4gqF!L&9dp9RE8 zW?Ch&M2w_$7=14Y2kj_-`)Ov#-0l3tMZZK5vO_eeUw#B_kIgyV7$ z+KAUGWB&Pi)zudA7IR@9#oi}M+ok%yc`n`)lWnaNEzi?xvn(SQFOc?|O|yPq3d0Fb z4YnI@Lvfj7@l72MWH&&%2Ma96F!o5i)A{|YfG_Uv*;O5eM6%Lxvh*xCHw}_TJo9S2 z7`T10_?Lf=-{gDVy<^iXEYHq>J-h=O=4RWjuE6#SI=Nry*|mc%Fw(V&DsP?YM;pQC zT)pBd=W^TQ{P0)_3w4lMdbza-_HnYM4^Yge*Xk7%Ye$Ovm;-a7NuVxl$sgP_MkQAyP}J#p zs-|B(H?C_>T$Jndi7#S#4F!phDV+s$9lej>YpB1)@0&DU9SPnqrlrQKK#w1sz|@Z` zlgnko1tE@sm*Fts#N(WjNZZwN9p?2?TXDU-qcy%yta=TZ^T&7OvoWtYGYQ3NLRuXN zslWI`1*f%+HA@(^V21rRI!PxmEibx0xGs5w!{>AqjH|WfkRs@N)FUTH7L$vRV^1Q` z6Ej2W`EXA!0tVsXO0M)AXwaAC3fj6E;e(O~I zCrQ=v2ZDL_=qyTekXt0aK@M#XZhY`F6Lv^@ta|{^A7ri)!5O9Bu_4vbn0_+${XxL} z#1%H!RkJbSHFhTGU#|}hpYOf$v&$iNpxCOT;aF*LW>MyG(Y|^o`qMf_s#7j0x4}Zp3ScNUY zHY=#`K*$Yc`^ByL9oAl9=B$|3u*|trmHz-rH_*Iqb4d2hY}YIc+$c%CK~5+wF9NaehyaJ2cDdCYO1H;= zX|09l?lTLs~uHG$P=X&v7&KRE&6bZ=9A5ZSiUaG66uMlCcv8W8#fb+JiOlg7ihL z{`?~8Y`0%)@bq!6Rw)$!#eQ;d)zcCSqjTiz)?^%Ekf8V7n}58Qbu(5XXEv@pZ`n*G zC*X;Ld};S7%@y8B*Ht*l1`n!9&L6;I&nce{sn)%?`!~<|Ki?eYG^pX-{r!D-oyQ|x zjd24bF)!aKmpLPk1#cx|tG~NEF2KytP{kRO^LKa8Z(OlMauSc*ccsTps zK;h|O0c}Tq<*wptq(9$2@D_9LG*7^rBL)43_V?5|mS^4-9ddM__TeRXtTm5kQwKUL z9G`=H$rSZDRS7s&xOz3peyqM_6T|ynZs{D!IKW#|Bf( z>K}Zzq4v*CcO(=9{hUO^`}oh8ses-Fr}IHD*Flk=%w*MWx~FfNWWrb1HKqW(U|cbH zATSAvW4>=JM>$5Cc(FQHpJYC-QF!`&EGWmb&{A{_lR~o6EpmfYJ@6T$4}hjyH<$GD z0vZLOViDZPm`BCcnSLabYg-l`2H4onF%>n(2eTC55Yo0~zVp*Sm4iBw%=pfCqqnl6wY+qHvg?tprj6y9Z8 zEHiGYwFi4}NYVI=9WWSXgu7ww%t>S)jj3eH)LhpE-vG{w}pfJq?O< z-wJWlRWI8Lu;)>_wo|y_S`?7Tt#|~(ynM_Le_QoS$G0!9*hUiJ zH{@OxB#w1O$lJ$MiG<4LgRU8k&E((zC-;#+0G>X3Nq5C*$PIBWSA zE_C_1PQin%H^gDIHI5+SaJnR&fiK<&bn2_tl=B>{aA$EUPw4WUP9@uhb5)uZ|I|z` zrbAhakH53#BRy)(c#mL9sOsMLmmfrxVAU zXr!mr_wVge?5T2F4B{i-pWNc4xO0INTV{IApTJv@er``}fo+N^b)QHmyJ8t$<0&Ca zQ_BNA)owKSqfzKsc!mf(rrnwx2psdQEAHdYv+EA#em@FlpAC%L)KAc^uY(j*n_!bt zn|i>q+A@di)Jgsgkpqv;%GS6)J$n66V=hP46*n@yjH;9jqg?g?JdF%Zmz6?~u}Ec_ zT52O{0d29&b0i6uz``k#H268xrY3)bD0#mj5~51;;0=&bo5se#favbs)Tz@FgL00Ljl4I)FeXx}g)$Mjz5v}c2Lj&G-D^&2L3_9R24Vw4Ie=Q>K zC2VDC(|J1xM5NCJ*^Ii?yl)cDkkfd9866Kl;Q2~-4VbT_Bdk4rP^nv)uwnaKcK$+I zZhpkockKd>xv;~HdxU2nPDg*>4k`#catO8~jLXZVD>?iQ3Sm>XxFXz{Ky#Se7aBU) zKB$nXkdmLzVRplP_L3lZU%F2ek_iyetJ}HHx7VTV1AdcZn7)vG!mD&Q8lQg*9H`(# z41bGZ&JOAsvC|V1h6d((hK3V18Qfe>ZEem??);tWX>eM%^2H_~sb*+sbnKHg2z>*5 z#cYU)Pza@9>unh1HvhrX#msgR%SgwgFMTHx8@h%+7srLdI1t5tD{T>f@0X~9u`Cv z*;zbLZ6C{jM5E-9(cI=a(13Rc%rw#rdX_{Ymu0Sm+>E-^-HsJv!l7t>ch0{%f?#ZF zGjsCV`fEycc{@w4kIJV90KF}E1rCN{4o}GNLps(n98peYiXpDI8Y7l`Q8*Kgb^GWW z{H%HrU`2u_8X_DmY7b^5XNT2klFwc!-3gOc8{hR+n?KU%a|V8dL8&i#}gaM}hY7EngJLUUdUr;bJ! z@t?vh)+Wxzrh`9t<*5CM29E7RFjrir8#6ZE&VuGEkJYOx-Xn2sJ)Y>PP1`quyHGjF z3my2=y@fwW;6Rb1^=X|NE);$avlQ9!POEhkhtO?8%r^I=QaV+u>A0`z)4X42t@^+ImO?U{LzONWt!rUn77aWs-r zxn(-O2Ut(0nelW-vP**22)+QPb;P??-4lw1v3gv_lqnrxO4bc=c*aX1 zJF7CV9?bi`{|P=h0^%@5LqS8QVRLd*XxpMI&#i#`1Qgcy!4xrTAtHp=j>>CZ>f4ms zUqVmtS6@7!KbxxncNAm&li;Oehc7D+)6E{|-h>n&+`n!zI1|UNxxG(RdqizSjYTz& z>t_5vklGI`>>dxn*d2drZ2vR~`(#wXHTWA4SfpWu{I$HPV=t4%Lj{@Sn?mi z)I>-+$(7S-_hdnxQv&=`?clUhuCR01?S^=binL6$iC=VZd%M0!bls=$Ge1eXzyRnN z8~EE(n7SF(6Ch8rq{zNLKn&*x)*S^?q^&iJ*v*HoX(x9Orp!r)?{DlrSRWhpGgD{D zfuSD0ndANoy_>KPkh6(T@r5dnH8vdlcy_VV&(Qw-Q&`Q8Gn^6>DSHr3!H5&3$Hf!mEQ7CjjCMx6p743%14V+}126S8lr3T(Rz_+{<=-BL&ZJkV z!AJw=i?|L#$}zeTyzaCFaQZ5-*W4%61lrXsl?=2geZ+viZ3bfW)aP&#I@uSqVrAd#ssez zC-(WX+AO)}ov{4t?~3B5v(b@*WL#DG`bY61F{#WFlyLS{#dXbx(DwAbBM2xz5#~F1 zHlFtgeHQ-mwehHxvoFFm_XvG8$I8k3VFXn3f}o?}1(RF2_Gb~H%tD(VDoeM4C&6&u3Fl{vKA?ItvkWO%u6$peZAIqq+k>sm5 zoSI3AAK781eo#$ikFFtv~bYnIe{gq}p;t0+h;et0T(qw5JGz6c`5DXH!dGwY1`%d%KbyhmPjC ziFAO<3v~L-FUC=jI&H~pUW!!IUHTN3F7|@81%AxqwpR+Yc*!# zDYZg2$yU%N_k23F2IF-6R*xQw6SO;R-?3?w!;6pjd?`Bb+bLhrjtRmvSo@g4I;*ze z=2GcKW{z3w=1BheCHkzmBK>n7Xj;pPTq8Dqi>S3M-(ZSLGLvFZl>Z~N+hSbe$Fs+Y z9yYsYUg-k51>#0Y^fI<$+hJan2W$Jr$Mv6@$E^6VNe)gw)yIASxkO5IRUiLM8C^2+ zzNF_DB}2MWVeGNk1>WJi14GENb&EAKN?EU_iEl zM&NH6*e*iX*lfv9wtYgcRR{eb6~!F%*%k(R=f!_~yLGB4bud9q>!PUqPAS~zHDjLQ zI*9c*%2zTLITm-oQiL;J1$+_;YqbA`ZOP)l>c9d~Lw7)Hk0_d&o2RBG4Bv4I*Lw`6 z{ob2vp`2)JG}mu2G$-K84&LzW9JDXPAjuqiEZg?}dKWzc-1V}mOLvB#x7^BzOhj6^ zbM5j0>gVyMH@8JG5^mbfZ-0N_dDc+jRw4ISJ>4cvu3v9&_cg1WrnjsVm*l)LFt{E$ z{F-StL~9*gEkoa+R`PVM@uVWpG@IYwBPXu4R(;c6b{$TZ%y`~x7KI-=FurLKeY9?? zi+_oqmP>BcyqIM5hOd7Cu&u-$;WcC3no0DR>)|A@Jaagva&->DH(t6gt zirQKk)7dscHI73=ds@aC^?`)dOAadu9pV{M)L!DoR=z@xLO`GRS0g?r#nw@e5;3Ie zEJAISONS2~s^w3_nXI|$ETU0GsbbY?CDEW?w=f}pr&80cHJEa*L+x#ngyX{%R?C%4xA zRfTb1p&Zk9t<2-xc`oa!uhjPkn6($9WZ`Ip}5jmc1++DXFJ*sN1t;}{% zG}O~|B-|4$etRL<|E!gh<+3?h*?EFV?9(cmF`Q`o9}e z8?U()RVM52jQx7^o(iB;No!^%DoLOIopRpHjj1_m@DBxQR}s%MT)OTjydJIJu7Q5PW5uDY~^~P3L8nTSHg{3 z7|zgUr6et^!P}O{G}ReoR&5mc|EbT026DKJQ1Aljbf8u*!O=#d?3#4}aw(hga3Rd)okiv$q8D zym>9>Qi0%qN+GHKvXL&|jXMlY3K|v`5#FpO!3vWBEoqRAcbH{Co%FzLaQgcC=n7E4 z&zCncit@BapcGg*Gukm_9%%1Rf8EdoLjO{gni&59zQ-<+J+y0(FWsQTZ+ge7a;*Pq z#UC?p%e$bCzcei5b%0sr0{SmN5TxVu1f& zhTB~H|6?AYh{gNAeow3AphCUgbq074yYOIl>T5qX__F@K$*pr0^FIyUJ%P@Am%~*& zB~1^0y~_(__?BWH^X}gquAl2$cksJjh@GtenQWklQ?^Uk%sxf|LR_&4IVijHy~cW1 z%X*+>ZDpSsWtXAQ^`e(#mo9uNW$Mu1J>hZ3 z#&~eOC8lyOtg2{%(Lamt`#AC zlB{UW!Dzj!uG?fK>=T+t_U2q`{~k0=NX#?^Nzx)cNEOi0d3Fz&^ncp7I{@cv2jG0E za;7OxTOSuaV6;&j{0&U=>kjE0kYr6~hXBGe#giccb9q^o6A=c{YR}00cB>S)C z1ny8vfVE=QdYn#CYb#u#t)M#)(<>mB=~XhoHh zI1PUa6NElSv|HWueW97ksHjn0Xa}=)0m(4+k8V_WiS#!4Tsyi;{0%R3%4|c5cy;=k zCxWDhQEA2x-@Y)toK1BpMR9CC2Wz|aufb2>#-d)Fz+_JS-(u|j?bXZ4Ky|Y5jTs}P zX%tT~pYyQ1TSxVatHAwM3wgdah2<5}NiNUaqQ(buR&3O$M&L{`2m-maA{KwWym7Uo z>?mQweOpB)$7`K5CQSGEl?#In?Uwg587Hh|0X8!x6=5^VNN)H$H9`Gxiami%RZNM1 zm@dWD>UGnubgG7zB?1!2N^ZEg8lt$@`O1IZ8k~YKR8(M|u_vUB8k+Z_FwU1Y& zWn!V< zh`kJL#c{bj>VL_ug62hJ!i#1RTI}ohm%=t-UK;DSb;TAz{K94w2axo$H_m?}_;35raR(^h zxUfG$oN&k0XIpvV#K*ZZ0YLK;)N_AN-+;PN^3FhC zat_-EYxVnc&x}ND^~T!r6j2Sn-j&K?m&_^NVb1cUQ708#0}fWc!jp2QC;rye6~92) zhkO&XN}r|xi#$U(dpx)AFOlEE#wo~0Uz$G+tqmKgET1RYk+@s$8jf{UIuh<5uw^bi zp2gPMPUyrKCVvn9)b(y&=U87U>YP|@LojBK35L(IouDWny{Xn}sdJwg=TAldr24cd zW*rfD(3w1KZ~Nt-s9W+a5~P8NsU`B*U5OJK0&gh9&CB_k@d+*-l5ijY&pZIX`AD&- z2SAZj5MShHV=O}I!zF=qR@CTHl?5r`Vv%~s$;R;LHixc5YoTUR zeHUbO|J#n|^`Gj?pECde@trpstR@%EOgcb9ZO1{JG)at+J4)S^!2~~~V%#C0G^36m zGFx$XEJe#^jk|sV07tgy;LopVmb8FjXQmHnZ02v2jrHAY>|OY^ zx+qEiICH8u(b5NzM#T)%w}G>US9SasU*Mkn@7mr2))oa@%LzyUM3U&yex~==pFu%$ zLJG6G*RyjUfLDX-5}jid7(uG>B~t8)WNB}1h0&03OmXDtTscQgL)PuU-4j1@L=+gLYztwSvUjJvs3%;_8A)y?T>b(qdC3YmOxwFEgwH ztuwJPHfkRnqW6Tk`rL^3ZsD=){!^rCinMQ|z$46;7mtU>)-83mtH6_RuN7%I8wRE@ zzvia^%NO&A5F9i={W-5#0*=s#xU(=FV zZ!fu9RL6mQr|fMq|6~SVAaCac1zD-=iBP>Fjk+5YQaml&)f23NaCeRDb^T){!v4ci zvNdy3H8(KCYbQO%O zeLZ*ODQt5u#+9t=nI==4UotSvBk^Dzk7JJ2&kq63~e%C=Gt7KRDn8W8M=c{$SiI*~lwUWZc#Q zYvtt(NJ{VkFk*SMGbxd%ypF${d; z5N74?xho&G{& zfu^Cf3{rgG^et%K!?35An-vT4NqYosgEm01#r+8!mrR6UaxG)|b8^5-)OalR125}g zTR#XTc4Ct>cQn3Cs^>+q!HVCVKBwh>QI=cS?POP}q1Ls;*Z%Se<=hNwywu9Se2%aE zC5e+#<9XhE1K`Fi@IL3<7;a`Zf}YEDa|MSnjcQp|Is#rH&n0C=`tHQ+SxNzD>IGL^2d5*SkFw&?^>#*yrLzKzh&3WJi)+Kq*R7{l7i}B52im>Th&R7&V z`n=OhPsFjqxa{P$ms)JGr3 zJY4^GxDwnrgdM`FS0VM@ntg1BHDIenFfOyFI#M_-({1+&o+s*nDONzsOphRJ6OmL% zTw;>rwZMqO1V>4H3zz@H^^W`AKox~;_k%~v0s}*xg#HYyA@tn8|EQn}-P0&ULyVN} zIg%?K3LLVT>|82pa|LXEw}qi3f~T<#O{kmW{WsTuhYkm}Vm>&xkoH#i4N!^15NVWp za8iTMjRkgrpE|L5ERv4{v$(Pz%KSO6F~{e;a;ezNyCKdF;Xu0dKTt#+_WrVWE5&Z0 z{uS5PZeIU;bUQ~{<{!S2Lwu?_gVnu6%_}b4#=F!KAqvgAK%HvG7=m12Va@5wW^jwc(A3z5 zFI)kw`Q3yssXJu6i#8QCukkR1KRLxNZ)Z&s>1N6oi+@|?k?l_AgLtqvGg|4Z=SZo~ zuoWDezgRI!yf3q@F7F*)5tTdis6&ZIM;+EP&ME!ied=%vS`SqZ=d<~f6_o39b z&(W_scG7>1P2j=i9elg6eji5}w^h12$zk6qK!s-{d&e`;0wm}Pp=QqIsXp*9EGk5N zlY=)v_imi?Wi{8oK7Q@mAG$w~h;LvYDiXScNUqXBpI81(h0^iUb(6Q73eI5Q7CAK10242=;j2<`3kO^amI>L45I&xS8q8|Mvg$51^BQn+c{9 zr2%$f>SlS@he`xF9^kY7s}WiL6&Ts;`-h7@gt5nQeiSEOLyrD?8(+KjcllKQ{F4;j zz@l6!C@zGd3{P(Vhad<6``@j8y88c7_TJHOZ(sPZ5`-v8h+Yzjk`O(k8=^(Dh$M(k z^ltPvL<LnvS)MCh3cVFNAw&kd>m*CwcCav+U#jb0EE@~%$ zPiycz?rl0y@?eb+xs~_RtR+O5{e>fuWfaUxGzqCMVEGxgX|Z8f+RN?QdZ3OhWt2vY zoh}uf+Ze3SKKGaYgvtJtcd`t2I9EF`Xbm6e{)-mhuv$V><1wtuF(dR7+!V0ZAZ_B0 zA1#LZ0Pj2^V^7>J0?Hm&GsE6ol)mKoTOLFifE1R1B;G1<%bQ}x7)wXiakDH#CjWOO zw$A}K#wx~Y14xErJk1Cw4H0CD5f@PHO8#*5*dwfD6NZib@RGnR%T)A`$kLM0KcOVj zPRPZo0JfD6OM0oZb(ZE(!XlvFfA+Cnuw;V(i4BGhi z`>r0$$$A4Nwwz)^Z@Em@HK$|VSJMH^PkzsCq0tYJP|mMk>I!PeD%%?~NSoqHx~+4kmFE7b%K(`ghSyAaJd`TIfK zZ)?o@MR>7$Tscsm;{%l3iN}U1-1jg+73Z-XNQ2+2n2k6!)-`lR)Z%DA=akAvC< zB%$m~_%lA_R3|tdM4jX?1D`I}VH;`Wc7KCT)p%lRfZ0;=rH6qYJFMWQsF#uvL zsAh$#@?n~FXY*;#f;yl=MW2Mvbcgs%o#VbYpizPN=jFpsc(K(6IkKJ?hb%WVCg3WE!hV+qHw926+9q(Wb8sB8G$UdD<=qe^! zRQ?M30UA&`4=XS$268=Mg*Snm=aRb3X}7uOMyd)e4P2;9v5)e|#=K6mBHcd|3?=Iz}NIeOp& zIFyD1y9wyx5K-OUqQ3p(_xY`X-AjiRT5TvUrhbqqdmvZL(<<|3a1W-*NwNtP0o@4o zZt=dPsGb(2ennKE!e}s@$i-@dJ(_fnTXO>SLG3ul?hRfQcK2fkiso_Zzgk43(xIJT zyw?w?i9ePD1;+1gjNhCTW3aNu{Y=zG1|F{MiQ3ff?Wzm<_)p<*WQ%!c$Gbl!RoSaM}!t0P1w4?K(%j4+c(*;#( zRI5yx)!u5UY-VEnve(Q_-LJ!59vq z4NSmj^gCr}p#gzk$`!AEoMh3iwg`+RUv;FIOk45 zj~l;(51`Vd`YXH?{os0=0g7X(yM`Ra!TLi2@FcieE-o>uETTC)_Bg}n#JAyzO5rvl zBOUsowsB(T-4&{4)WBi3@(*yBRvLIwQEh!)C>NKp*J5l_z+7Vt9=E&WALPBbGMsDz z*}Qux-xTEi^WCV4_Yg3F2ToPf?%UJJC`Qx|rh@&Br#av=^tGIbx6mN1NBxHsw&w}q zE;c=x{J(772Oa~-%`8l(8QeTJ!iQ`m8jMXQ}>?G0T*=|1MRMV%*;oxq4u~-vDnC-bKX0F010G`ms zqnGtePPZm`YRe1iLfhKbfP*K#3_+0Om)5p1&}1wWixpGAFJSV=cDlzoR7+(I4Gg*Y zFhivoUq;$X+F^G#OG zb^|1clGnjg;AluK3SCRncVw*l`Os^2d(5fnMLf8r5tlOUDtn5a)%Sis1GZtW-imi= z6b;y~3Y`Y4vx9A$0)f1Th7Z8=iN7#B#l!6Hz2%4W(FNU*+u@rHdUUbA5>|C63C9*q z*s?5;Bi~hM5r}@1VKM1 z+q$8>fEEqay0g`EZ$Vv@=V-~+^N~V}>8AyC8J@`{TNcsv38-4gJ`Q6$cDD+K+aDa5 z1>WUP@kqGJbAL$@m<(Aa997NEBekF7nah8a+pe z*>N-izx-^sYQfm@r6{#a@H4M1U0Q4Kz2?ngS-TZesK;s3Z3sN0ZYg1zk7IXA$YSKI zy_f?#+?E3khHjBiv&3--zl*c-mnx8%>jI1{cJ7btsHPgY`){+PJfS_{G5|I*9ZV1B zv>Ss@zOJhT`fjck7qMXv?wyEjr41}{MHwF7OGeiYm>P@z{MxMwZCAlw1d5aWe|Zt4 z=}>MGS;rso01PvMt6;BxBR=GB|02H>%U-FlQ$SSWaA6|m=a=G z18Ph#v)|-T6UBh2;Y*-elM>H|TP<5eza(k}ZaD8oj!i#pH`$bG}>ie=p64nNY*;Ka+XO#rPFv5o%02}b}Gs~ZH(*%^( zfcKaJ1$q6g>=OQ4+2uEo5BLYj!;E?O;Q&^Xl%=_m*G!FEU^HwWQ~%H#DSCL_atpRB z`mA@1NbNW-6?Ts$d9hWW^WC9}=_WVhbC`vrtfeq4@Fu@+xUea*h4IwrZ7j=IZIMIT zWqu1snm<}}!3viEs%jUtb(`w(B5MMm%a;)XxDpX1129c4&wx5x3_r3K9LX)kg}tIIy{}NpW@U#k z-)}wk7K7n6n|ow!`*&SiH}qhdHjcL~A$C_AIsV&?%e$zvDVx)LX?54%zSv(tI;}zG zUHz|nAC@2E&!Dio7C;RMrVox)iT#FcV*$}kS5(+fsdY$!EXuf&e7ifIyqek#4=-Cb)9G6>P_^BKZQ5)oBZF=%)ugKUT#hvn*!x?d=l6VvG678GBHS0d5$uY( z3dAj&gTMa(*aV1b0{}?XrYM2voTW#=cm3;@w?FWbjXstSz20?3Niux^1omYYdV_y} zAyaDeS3WQr_KX#u+S`PzyOT`!9m6lbQBFgO9A@w`!<3zK+)@;2=mBvt;o57QLC15V zVq*YQwxa%Dr2K~>{zX4V6tF{;hUKRq+Puv6w?arB5L-gZnK@F)Li@uE=up10mM)1e zapIONjM8dXKqj=iQ;LuM1lQK*_c!hreG(Ii)Vt&h)RSU+;!bCo&RF+V(2K4bG&<1n zD@i7O@HG+BX&N`$u(bk)joJ#l1#In_D?Ujc`|5Oa%N9uIGw5L-v4*`pv~~8{YtG)> zOAmG4TIg+%T$ARdcO1KPXma_oa@#v@&O2=aoXQ1!M9(glST++y8ym6wv{2wbf*!%K zrQ|$`FF>M+)8m<#86FyMkffw!XNJO-bQ6|3e-)B}bXtaoU%r3wM%d;1OLDs?-$i(L zH$3^Rjl2U^A;Ib@cF!E)gdnFIAU7gDQzyYPeWN?3^NCR>+p>6)d-%eu{Z`SfYU*qI zR*1R+k?Co>n|S`SF|F#Hdp8v;wKRG@>AGoK?JwM_r@R zD)Xs6n`MY@POlq6hCWlvb3%qBpw$t*mLB{&xyknLsp?1>9lyvN;rG6G`LA8vwOJN4g{ zeygm4<{)e$`pQTz8^>|syfw}$fG}jiJ1&7w54*rIUu+7Y&fTjpzT30RB= z-WR%4{CyK?{d6Cq2oCeD#js_WR|1*WwVKFOhLlH(zMozjehakOH`f)aJs>%`alhn@ zN+@fnPL|ess_*E#S7=6Fp6e?GIX(qLzhnPc=W(dq@l-po{Pc^iNF7-qE^sB=$G zY+XvzfYkS0t|L@oFkf&9LjKUKR9Glo#PxcpS21ajx4TRP81q=s6%#0678kz(@j>?H8kk;LGO%i-=PEBQQwiMD-1p;>UsJxEk25=S6kmXE!yHe=o+{d#GuOF8lOtiwmlYjx-Pc`E8&>-+>C9GeCW`>yu^r zKOS_Q?Fo=bWR~t^qmY-+S-(Is}T4 zo@*5{x9>M&k{FT+K7et-YcpACEQhC4gP27~VDJmjap2UH{d)7qH0=8t~iS+C_1S8!)UA?GyH0@FUuMIq`$&IiWux1EFF8{wlE^ zVLsvHv$Y3*7S0`coB>V}QYssh=)TbM4iLue-lmkk8o;W1M#rxAgAnxrkKog zK02Kp4PRTmD7I`XzDs>?$9yCfWR0&l%h!|0qPhud_k&gVj&3SuL9iVtNr*jR?=fQ) zffm6Q*$i0`iPvF8L2nWnQBKHc2p573Aq_0+5<<4~#e4Z4GX@>7iz?H*^;|LXsXB$| zs`zA?#O+PJh`qWs)~L36B%@O(zZpX{DD1IIVo!FE4bv3uSTe zCt)Pq*eWj(s1Y{&bV43_tmg}`ZaHoI(jcKm53%SC z_-y6AaPGXbAYC5|)Dw~sdc|3*P%dnvWx2jhHwT&{m+P?!*$!#Bj-Mi0CF!y1jtQAw z?WtM_n32i0JYOsyRDeSppHYRAWLfOEf_J>Sj64BXai&6xw6%S1?nv(3bR{M!Hb@Mh z+F|)dkfLEM154Uf#`%5%Cw4 z9XsXpI`=VJ6LJu`5Yg-^tLBY z1*&6?1jc2t_xa*@gus!lrHp9iFBx+f`i1>ZS-USB@7c9|`tn({b0|KMZG0zMDf_%% zNO;y_uz7@%J&tJXNpK-7XwUTGR2}-lTzJ0obe?vA(TPy%ms);p8?cj(Lw>F3GYA)L zDAZXc*+)EZ?IHc$?akOX)uhKsCT`L;sAh!6NOIhZH;RA-hmD||43J(~Z-t|7d=ypH zpbyIId2#QfIq7^&Ms#V*2=k5tQp*8x%5?A*{jFEF5pGDG~~; zDtjp0Gjit2DX`#?vA~a`2>S`d4gbl)is>k}w9PxL9%3)+$dATSPtZt@H#EA`+k_eI z-@`m-UDo5xnQkt1_j8^nnBT)%!+iC=4 z6P!L=2Bxp2_7~5m?D%YCPZ88>PrL|Skw>hn|6=RtE7J*@7!!uxyQ;{@*I*M}!gBEW zmA3GL^wmm2dF}i!GE#tfk{OnlFd7A^zHBadHJpz}wBD8T+4>?|gNA#{Zk`O0#!Ff~ z`mwox!?IF#Z6aVFYf!iWfj-3prG3NvwiPDm&-lR66e=FV3!v6eqThY7B_O!=)N;e_WL2Rez41f63IyO zzD>omvSI6&LwUs5y@y+p(YZBf;niaIXPLJ?oj6f+5*hu|*yq&?k_beC*enP*EAo2SgU+Bh<=D28NF zTJPnGf;L__PA6t>&aYyhonpao$K}(Q^0YaSpC53;DN}nW;!EwQ4B>@e?UBk;TTS?+ zOA*r<0GE6yS!P9M3|wz)MEp*JXK0Euh)6!O&u2vDjNHv9H_1Tzo|{9cE2Np+@8fTG z`p`aDfggPkDnH1{jB=AqIO=+Dq0f?J`#a54qA&%_SmE+W`M{BCwPi^0Gg7TwZrUq9dl`G?=_h9p=UGqk2(S6jxYHA_6o*@RVS`su9 z)R!ObZTmQ8_M*o=vnOQzdzHv=%fS*319&_~-i~{I0gqxZBi`Q6Zqc2uC-;{b`>1X? znV+cHs`%>ObZH@=;)YB!Y8ika$+Z0Uhkl`E9>KCn=c5?S^FX5bjBnz+Cp8NS`D$FJ zXk3ATvCP=8{AhF3_7>1TOOD-%k7?)bIE1oB6{ ztiey2)M(Ez!56LeWhGU;5Au6gjC|Z)i*Ghlua9*}%6@>FXoZYNxu4!mn^6xI9r}i1pz; zugXPnwjs$77L3-Py<^WWxeXVe+=!v?g{qC6?3=s>j=g868HqUG&H1_O%PH70F!2OD z$K0cDrP(;Q)ZI*ikg5OOB3zp8tz9imU=*49?MO1+nUUQSv}eYf(Oc^@X--6=92-=u zJ&J;*el>L^&y3%mp(Etgach1n)CB=JSa_rHxS@W!c1T?YNT)i3*|%JW$|N2&e|Lp+ zvKq%kso$7*bil3bH!{jmJ|5@NtGB;L{$dqAx(IQ8A%l($woLVP2j6UDc_KFP1vM*? z^jWaX$G8lKc{-Bx6=!gcR-F^laTsjQv*HPywsRo0$+y#@n8HG>OlZ0o#wp&I!Emz1 zM!Sr9+-aq^QySm18q0V9K{=up+!qc}&(l-uIE+3N(f#$25CtkLOE>t7I!P84W7 zt8Mv0GDrIyoOpsXGp+ngvX+hJsOC1>;iG%#%58-hj%RUDcAZD`Z(K=eQ#3*E9Rs4d z%kE9@x)gY2X?&H8T4RcTv;-(%)F3;1cdEv_?G{hao1bY7Ap@;|nzrQAe%x8C`IN8l zx5OcB)1>a1)-bZV=H4fb-Yghoq>3$VcrVk`uj{US;fEMlcUBM2VzlNEc+!`FK`48X zrWL%sLTO1~c6;UpJhY*PNg(wUJ&d^j%wm!uvnNs}oO|3_58bcW=aVNX$v$~31t{#$ zxM%J4Hln8l3!C#bW&19Rw=dewX^%+GF89EvGm}PGe#9I}r)wkoz|gmQkfR;kA84PZ zrgehObz!Th^*J4$O>%-hhtelw$3Kh<`ft>a`TgR7mYeERt;nXD;>HDn;+}$!U=APw zLFLaCg-Q=e>Kxo2-!yt!3sT|a!W(%#pF4p@;Urg|n`eRahqw>xygKGT582U35#f|6 zGaVu*R$ym))h|Ubjtr9NX2lad(warD8ASh7+~egwjW@whgiN=DzoX8!yBp zLW>%|me|;&p~DNPDkWuC8#hR{Pfm(_2sm)xvlVqDdcEK4=`RO;`;~;5tX^ki-&%JC z+sNP)Pl=BFMim3X?HjazMlmrBreN+I0TBG^oNuG1^&%|{S?uoYLA7c42W8YO~9glxWd-%4aBbmySuJ(7_2hcz;oe zWWDK;vQ_7eG*Cf~8G3!R^)sauh52;YtceP)#$UnUN-5i}3xsc!#r4#cF|o27!eR$g=Z$A z!9Y8&XdqkCdqnh5?4wVW%ZSrrQ*jaNW8K+nEPGcsL#dUUp?C2O?f0^f0e!{`K7CAY zZnd{&fqMgErG46s1PdI_Z_f{;iRn1s0iCbOE_n3rrXIAu;lSdashHrg)e#%Lp&(9- zCa@k`-@e-k){73>Vj6YqnF6=oe6*%C)HC~Fza=EMO^Y5vHz8RtL6# zwi5vV?42Tv)_wlrTY>nJrY_Fd7t3P;hRb?|xBlZCX93rnI+~-xuk#QpFg}AFnmF00 zn47{40VO7!W?FYqsaGdGWUlb3>)hP8e|82*`si(S=OFL5_F%6uyD^vg?PB4KyJ|M=ZJJlH*1?`c20Y?ac~RxRY^86*O@PHjRq zj?t`dP_Lo%e@yKlc1MA?U3V+m0j?ya!w}D>;^Nr?$dqURj>iA#&-1jOL0XB6Wn9Lp z6>_*$W=Z3-JO&P`#AJP5pFt*m#|)zWMALv6Mqi>O4wJn{!4bGWFlyqzIozS269^QK zp^-Tv#h}Z7M-1M$4>64q zd`c{jt?(oS-1OE-eJUv;&3fagsT}Ir)x&^d2fZny^S#mGfj{N7XrsyqTRA}0~3&j;oq z<`mK?a#qKHNY3*h(Gs8JB7A+rzpYa*t`XYxwg!UkQ%msOTbcHs#rkJT24n`hPk~V; zIzM?JB$>bCBg??kfE|{D-52&I{wx$mlpCvJ4S;udT6O8?C-$~oF8M3sU*YqJTa7_i zB@#$_LY%mF4;=GjV?EbqLr4&8TIn_+%81W5oTh|nE>Me47`1@}nVr}P=!s~EBHJ*G z%AV%3X3!vY5qf>X08$wunAeJmU{d?!#>U1tgG5wuAt)K*C+<11u_XPK*!8k&`H}9U z_`BL(D`W4@-lw)5MLItS3yFr~m##@E~#!R~#WyJ9Lvqtb<5v z-W@jAyWbjytYvm?3K6ebmSeJ<{KDcfcPeZ8Y$4aXEeiWwEZQpGFuB8s<|u-e&3l0g z37f4Hb2sz%u@?5`>FU9zA$1ZJ?1VFOs&gz_i_}^yU$KG(pJvC$hiI!~H_0UYM=S+; z4-k7lrqx4^j@cqTw?>|N44rQbrEtJBx#Q@laBn%8-L3tqdG8*nol^3eZMf!SkL=eZ zI_ojF-(j@xD{$#=pN_32rVCTAG*Az_3C_`XA^66v?FT`j88aGq$EupQR4at-OiqJ4 zD9vEw&lDWF_Z^vjNk%c>cj9(&B-$Y6e-CLS8k>&7Ig^OFJ~tscW6)PK2o$hsd)kvB zd0QDj70Pw8O-MtmN+?ahLvZ9)l%=OEe)oKZJ$cY~jApK~`V=t4Su!KZ4V?PFm$bzm zDqVzQk!0msIq1+u<r;uqCDVl?;uKKB zq;m!_jYw?z-dRcbh+!U9h8c?{#mool}%S}Fwl(c?J#)ql2r1rDP+=LLx5 zD{mHxdYZE3+X08cH6M8HM^$0sW-CPsgm#F3218ls1Z%hA(I6ox+t8$Q44uO$A1ELc z6TSUN(a6v#$Ra%_lhB)RLYJWS!U?*ven`?NqsY=aUi-T;Ej_z7`E%XD8TR|*cT!oD zwuGXgTCUweACA#O!OI9*1WBLFM(4IsQdzF?lHmDxzF@(i&vsGH7saC9@2CDg);gc# z&jhdS+eG~GXI^!p6V)q$dbRJdm-)66M@kG2fD{8QgTmJ-(;gb&YVsb%{F-BnEe2n$ z)aqF;0@#P;C#ldzg5yiPgpFP+^Qs6v1T*)bhmBRm`S>I_0paRS@Z?rak5q9*znjD# z0su<9LYx@;J@it@UEt@PzS(0oeFO=a4Uy?LTn&8md7aaiE2+%ufx6yUfOzCI01hUfp{loxrTD*5DQVZpr{`L%FO#dAI@D$6IEaEsnc0a+> z0yS$(ETg3(!~3yIHX15NrB6E5%QW_C_#j@yGXSvuXjxpa+u+k|x;J55nP{TP`SiZ} z8FB^*Iz?ARv8KNMecpb?pl4IO&8g`hN|uP{PGa(Lb=!%6Ox$`RAiCPFpg{-(YW(H0WtILmxOY~`{2a) zuiEy+ARYaCMa?T#g;-T8q+KiFZ9ETktN>Du6$Sg zyq`~Kz97Ih)BDd*cW=(8Q)?}i-A?bOmALxRqwDvY1eg=K$Typ;C-Xvm)DM+?Lf>^Z zWP+y0Hb`=sJw}wPgifLcSNNls_h9zuBAInxGa^x+^l!0HnQbDJj@4wwnuAcX^EYEw zl-3g)<{iF>l9?JQ=) zDHh0;+*sMHB&5$&8E9eIJ{%~PF)0S1`SrCIW;tV<(@H&0YVrDZ;by0BNe-S7M3NI2faXQ<+8C~bP1$EF}mfQ$7(JPb)0l2|AsxiKS33d3sH9nO^7xCAbiYN zvO@+O73Z$a@yrq1_!Bb{Z#b3PG5lEJHiLg@`xk<#O#<-Ln&^;$z6Oag zU26dSy;mam`fmh+#EGA>jr-o)q!aBQWaYd_StIpd zy!O141ZW~2H+m;3R?;bw03stoM=P;1AnhEfM`Mg>6c?E&zhpO59qsZbNZWDo_k9$u z{_GuhslA#x5{neNA}SanV9wJij#n;p`s{*do{e&7DK=bkFk&@-;uYC;1)1?C>Bw8( zoEX||F>8Emkk%F4M1Z@1BM4d~#zaYPs~knvG6Wbt@>-=Lr4u9lNjM$sh7d;t6u+pX zxkdyh2Jb36CEy6bM4w*VdhU3YOX^1Md*j`Sp{_GG3ax?>{wc zXJ@?bAHBfdm*utJ11B0iMaoPu?Om*OE0giR$PwdNC_U!LdF`ZI!+6zbz*hO-S@?>6D>&sJ>zY?Us6<%XU?Y64C8G6JOsxgw%ce91k& z;KuKL3fcy!h!6pBHT5HvFN0t*YVPI?;HnFvJSIEtM#GzSPS9M4H3YZDCyAPkM+PsN zhfMGr?0zizogexe8p5;dL>kRVGG|o88j^KqV+p+C4+&U^{0WZ+gHQw~5~qe`uRR@d zN~JzP1+ps|yP5WgHME4VsFRX82Io>jy6>E)2Mrt)rOm=jSt#yg4h>BHo(4bw#+ z?tXRs+YM!x48-7TsZDu&#?)QaBUI;XaeD}q4eu!O4mS?ms+HLqa% zaQPL^m)MMs%yPOE~Hc&o9 zPCox%tDerm^8=sQyBO#-4%>J49Os3won^c}W{nSyvk^e16J<_;86>0c^;evr?jEMj z=Qftk%YPXI>+$Y<9R%Z*@Mo5*zufUg-)*OA5L}49AAOd=x{T0yfK`wYi&10t7xMAt z)*k;cX&I83_3OqCtCfq3;!V8=JZ2!OL*Adww;43dRGUl=xOWHygjzl;R2S@MTyZNZI4 zjp?3%Ho&7U5$c=|CJ?lX_8Iaz4}`slp02_1>UdVI8fex9*1q7EYlv~N^43&2x2Acx zxcTcgBY`u$c#0#?!xhjCD%!VdRF6`sPOf|u0-k;DB;q3au%sob;zm9&;8cPSv3JDzH_-um3pt} z1Mi)8+(rVf(Jpr%c>BL{vDm#mZxcwrg!(A1pbB-LbZn6WfI&GSOy+>eIv)!@K}m-m&pG}>Parc^19@O6z1^|;B#JP z$yXVnY+Z%w0;e4qW;?gmecN1E%JSuC!)2#;P-Z6q@+t#BSlU zaa2vcSXkd4W<{Z#`#9!3JzK-vVm+t9Bv|)wmFu)>CK(A z+$Shu70&M*M!kx`cnbs>er@bDjqEz z)4iS@zVfTcx?>^o9>hUeV?7l=Zn1igx(tPI$&sB43J@Sn0UNz^|1@xLs z?W@q58J1_?NG$0|eTS}*LeS5&a7c$9snwMI!<;2B$07`)fWEK&>$8B++5BaJ?qg2% z7loS;WISswZ1xM+;Te^*mnDA;T>Fr_D9nwKr?4XP%1mDIkhT0$!g=iA@-V^gn?W`c zVNU6x>c!#lhDHyK?;t&M{$)&3HT`%iC4;Vf<)qk>AKO;UvA8tQLPuwW zuzDTtP568_ZVRnxtU+@3O9YTBRAAsI_$|f7;Z503*MpwQz8IF!(oEV3x;ywkL;?W7 zB;ish&ch*=0j!WLp8(7*Q#!Dp8|qAE^Zg;7mUR zMe4n;@_mTZp@X;9K1*N1)o_(%7YduM@j*8cPxt3+fC91B znU;8GHv=X>F_E)}N+?fXk5lMn$`|Hz;(OET&$h6SKZCGi z&@Ei**6HBFJE-73{(u~t4II;zGn?=*j1APe%wM^x0Y7z5LGg}TpU6GO$}>oI`BD1b zmwi+`aETC~wdq?X#&_X(_fVHEb=5l)6&geub@(G|UrkUh-F9g02TfB}xX zzP6mxp3v3HO?S&^d$yvVW2HhwZ|&X57*jR@n<{?6Q{ANP@+aY zY5f(rKivh}c`1IJqx!s2Bt>ln?QTYYkJOK>W;Um>AY#)g1>+<&Z;KSjrmc1 z@E2zyMTVaX5n3z`J?T2!qvCz`EraVx$dvT3_;Kc+wF=lDi+!5Dy0{_bgM5QWFIDyW zII4)6K&CE^Vq;^ek`HqKYa%N*{A>QpIEB-^IJP6!ul@o#kMpb}xcWn=CDlqJYbeb1 zH$Ck7KSc)+jr7!g62Y@dy!qzy^UfX$WO{ri3S@7QkgU!8N$t21_K9%m4HUOeeQP`j zy8d!d(1jOkp+EL)w=*o`2=z`WSEIK_JzM!e|paQ2=r-x z5t8Txf07xH1dUSy`t!jL$fr49fPcl1-#`Vh8(;c2bINiYcTsCP24$jZMiHMd9e+~h zfZR(N$z^ylRflULR4e}f;`F$8gW*Z@-1rRk-|iLXe_MD9HSv2Gk$wj8I}ZeRC_E>u zBV>4vck=|TADGKSax}^2F3&yA>HY2V3|R9leyTGj$sl#K5&KF~e&KN8X~cz!sImAz zu8-Z)TPSYlJEb@Vz29L=K`*>ib1MtOZ-3beSEEW;OYnd9f8;IAZkp+4J#LqH!Z4N+ z$y{bYSMb$P(Vk3f|6oWYypGoQq4->Y*^O_k$CrUbQW_u1F*e(!@)DC-ih8?pgYUAF zL{u3d9wH8avj~2QD3f`in+|_P95R4dM_dK@llfd&-7c5B@d<7^j#7Ji_~?9`m+k@M z2VRBGC(-^6FAoj^xm$p0gubwJoVvBtrHVc?t8Wq76=PM<+edYiX|IRWVIZ8=LUs>W zkRQ>FxOK-i84@fWd|TdSRnT&Q%P5G#|r zG2?X6>VWat!^v`jL&B9^K~#*SWnCE=AgP>H&ao~SlCFR6-?*Y2V9zWVIjthwaQup_ z@r!F&TB^e)-qW25 zq`YiWe4J&}%KzJWqVu_uLc#hoqm&pzxSmoXYQ z@2pZW<>|z@v4(~eONyRKIX%}=@ZPP&M9;q8r}zmm?nCT_tkF$uW?*F{co+z)2n?mJ zo&J@3l^s;jS=DG4gqHGNoj8e_~I@NC}to+#=|32uC(ORUq& z7xL|iKox4MdH3-ujLL(ORv5Ur?kRwV@0CotZvS%qKu*go$-o6C`$ zJAXtnd-u3_ORnUW)8HPeiLiU*uw(=*NT@{yGA~@|L`*-i*Y?Mj`L8;eak+xOsF@k%P3m>vGSdU76yG3=UT zW?ujWT|7c9SB|sPnDebsT1qUW#-t|87rWJ$*gaHd^L5zfCoe5kS3H9xRB4)hc6EOk zu=s0nyXL#MClp-t;7HwnQk_Bd>$m{5p9T3eH=SjjrPglHIL1WkK_-X7foV6FP6 zY3CQr^3qaEhQafQ*1w#}J1=l5SG0xMo+}DefH-{E8MR|&Qg5)!)~oeh6M4IfF;qE@ zbG27mhAT6RWkVXtj$hvHjcqYB>G*;ZHmd8_R-e-vc~G?WV*4LIkQS8v{U_~RV^m7%SNTBYJpj#78tWug*Za2s?XT!TAD(YVt za@S0wnRFK=sTtTO;Lt^NX`EDuBTsFKnnfrCV>Cy~ZB3`6;6guGeWUdQkEy(wth*raP?I&0lLpSONR5t!jX+-ZXAi#?JU3(>>VE z_?2=fwWQg0Ujczsol^ICOQv!}{z0UAnCH`XI3^V%l{v*%t8mRo_;+yn z8Yg*RMAUNFn+>tEJ;fV1->U}`B5Ac{H4$^JbC#5^S&~!pHOY!TBRB5hU%|$cIW3}!!y7|42o_#&c`FtAIjojqIXAFs%*S67VO&~UJ z6h+l2EK!f5_3mi9M+Z^#SSKAnQviw`8I*$)mAla=(MkAL@&F-MY1fDnvG?6=89zC6 z(u7v zO{vGHbg!JGto4bUPHoC2#_7K)n+!Z>b~f!Tx~fvjE#o3d&hUE)4!V$8j6_q9p=>gl2oQ; z&0Ubt&NeKv5tB%nZrrMfaT%07beo{e?Vk*3`xL)(u>9BT-_48h-Vfq4cg{>Px{~sV zb;R5u$gcFBdK?dgKK4=J2t0;E6jL=H&3n6CsXI%n!P%f z@@$7qK*>jvOc0-u_&uv>{_!Q-wlBEk6n0Be)3Fj3OM|ljk*2wwp^FkBrlnIF>6>Ur zfojb4{?ReJz%&!2%kO7h}WN^i*bN z{PTQtIkboz!_rZ3VdC1iwz!T8y0M)GtX{wI-Z84S#WX~d~5a% z<#h$!_Vgz66Li(p^a5ZvrzZPL?_7|bjEI01wdEuWbzQ%4&HQ$#2x*zZ-Ji`_1x{J_ z2fWGmqzZtXT1LXn6PuXWYS2Oq!r}yiL1%naE5NW+G&D0DNTlYMCgJGvH7&c$9V)@d zEaFj$f?k>yr?;pEgZGeiyvSYs`{4rcw@Zd5#;NT_TCeC+_{Yjw`-Q*y-uer zrfyYF;#WRFiw@UmYCjqiZJwYxi#s$I;M26U1uo1ws1PLpefJsH-PEr32*-Zhgwtxc za}|PZN5M^NcBLcW$v3_?yU?{Jc*n16SHyf8>OWs>kc2Tg_J@r#C;C2v3Mh?HFy42N z9qt%;^%6*!B0L??C?dsa<0Mt1#GyI4;>Q-cE2+h13cFXd(gUjz%NFbu>op{MQtaro zbj?o**bRg!t53Y>Y%jDiYqrH`o6)Wg-X84Ga{4E-cPG*405uHl{(i)LQ!Pv7bue|( z;O(n>A2sSOOi*SEk+_HBeC;Z+Wd^~X-qP^4Y2}T~Oh(C*woM zw^M*>1y_9DcKHFh04s>_4fMkC_S5rY<`r;P0Ir|=c>Q7aG-&82dJHQ%*juMh>z=d* zAH8tx=p-f#h}E0^NuN%B{0VP9i=CCp2l7tBNvtr$QI+wG<*ZaRzp%>_M;pYmkmI~T^t5dJc4y5ko7Y*bYJnB-_D|$EHv6@c> zWiZ2jOfG9xl#cv8}EZkxmEMtVBHy?%aaMUy24T6N@74{h@orf z8k%9|eQ(`<(z@d6Cgmo5#3+hQ?xjPfMs1peB;m0XO${NMQ1EXC zYTvKjUtW6Jc$6pv&~`1Yshut7mxpsONH2&wLR4M5)fR4vtwiH$9Y=NRA;O?hiz zRV1Ri+IM#6IRry-Sv({R@B{`0(90O4N&>*@-6V04DtID~YGZBalk?UE^ijC3~DYx7aQ_ilA}mdv{{jk!t(chmJ^xfKKFX zOY0s&GRI5pZ0Fv!1e_3o(29A{tkSi3Vt{h;&UUUq>2l-Q)hTuouOuxe>Y;!mPj6u6 zV?hS*(QAxSI^lqY*sSnd5^^x8kKWDa|mUAfxTiOxm3opfbEj%Y{ zb)KDDx~pP$v!!YmF&@u05Wag@UT<6;(%1HqV|fvCIKs~K1kaxJ=lr{74{Wt&5L@7p zRrE3%c0r9|hqaw8DZA`fWaVCO)D_-ZvF{)z4-`o(C3ntu$;%*Is=BxC{{HL-=f<+i zdS|Dy#I>0;?$|!Cl5mCW!i^0egISl=OCcSK^IZ#njjs#TIaDneLY|UNW>T2f8h<(; z8!IvEbF1IKEusClesx4IjRB;S^Bhd&W^#Aoz3h^6hb#@g4Dqz=N_4A$5?OFMl%r=c z-g2T~RKN_*i!hu1znIRVvZ-t^H`AJh?vfizXI(Sxnrjhtw0FcMjWdCr<*C8=$*#ucWfxA zzV3ZUlsXro#@3U^4FlTqU5Y;riv%Ew51%YutkF)bo(9GnJ&*r+ah*>@E+1rcEiV^9QiWzjh&Yw* z;_YOxKq32(>HebVLq6`97dg`~PRcDrv|md?moSG^5?5x6KA-0)sYIyx*-;_H24P&) zJQ@s7ofutkao>>%^7W>o{-=d$Q?lDLu;ZZ7;KwIB=#|dgIGUzYstC6JB>4`B%7RbA z+w%|`y;$^R?-Pcu?G-QX8@E30ldaFGxv;BL!j7iFi6U0n?>K|C{70}(D<8{AS1^^- z>r*+ij17NenzuQBTP)xIKQ|_{cAa{DZagqfGhwSY(DlyYu={-H%egS~b|A{(9_G*g z7lAZe22cxE;9^PNtBI%db|)`tJKrgp&;;%#+KIuBz?`pA-q=H{nPkgKZ`fM&Yju2Wb+IkN(uF zGXORVh(~6UBNJlo)Dl$;U#PC=+C8?4i#lJqx{qKGm}7d^XfGW)^Lc3d7#+1aaAFum zc*A-bphF(wu{zJA*Xh~+Vvji7-+W4DW5rc7Mwm3a`v*QHv86WcyDVv0dNU@lur&Tq zDpe#7yr&^dTbUDhrFT>+Da ziv30WYHGZh&%irR+8Y3I|9X9t!=pKica<9qq((;Z+MFoX;tn;mqRVk3vE6Ks6^3?? ztPC|G(w?o%Yp5*tn0K26-0Viicb6VPt~Tqy&l{|KRjp9Hq)B9w)+GC5WZ+Zel|rD_ zo4dTV;IP_JhTdm+JG}s+BcCvPT%Q}V@*kq;XtYcyuwpP%Z8YRV}+1sf3Xmmt3N(BCK>YLW=X+cBCkk+V!Ky8IG&ye)bDQq^>$ zTVssoAgJ~bF)$>dpVS!n7okL8p&vVTN+?b7*bfn_l}LHqo`+cFG|`S7-X8Kn@!!~o zBNmLvoLC)s9Th5-62Z0vvMMWzbE5eNDxJ=N1$(5E9~xLKP%8^&?PsIQeAtkxI3H1J zgui!PplxzNxB{riM&9_dxu%AWTV8IQmri;wY!4bgP!u{&X!n)Kd((cVvQawy&$Qpc zVnpieLd36HCEz?X9yt{@-mAKO0(rk-fb(3f!a^S3quqNl`QEa;v{B<5j-`9@pa=3G z0cxW6DAw-d9a|ks#**f08b@)49b5y!1k%}){%c%t$(tQk(|bzXqZLb`gWwAa26%#k zj5n#Xc5X!qI`3|Y0ap1FP4D(x>ixy%V%AN&gq)Js6fBF|8uBZ9CV--{>EZUFYEsUj z;^N#2`f+AY3*2ME$ocGxXNUkt2L;~lc<%fU@lyV5~{%Dz;6_+k_6^SUU{Tg33%%1 z6ZHXCeN`q6%3+G?{+BM1CCxjKpn28r>(%t?U)S>GYcF1-r0~CNd{C3xpC(~-(5Cvm zz0F9zNb>_2Ih#D$ZEb&%+mlt7?Iuy>A@S$m6UNl-2u;P=y z&oFwmGg{zO)5x?GUPHN;4y{67!nNRTF9o}>5JknZq(6s3;Ca9ak51l1=w}1`kSAB) zGv$l9M(INgwA+ZY>IkUowM-7s>$kLEF18F`kM56HX_{|F6#`+qbU(Yd(l2~BRhft5`rQ)BEg zXD)uve9haue+9K8ld-PJ{o^bc;D2yJi?IEgy!#O?g_osq5rfd0=0l`3{c-4$Ef`5P zphU+ZY=6QLQKkv}mjnMd(g*=6Y@Cgx>-K!!lPC@P3=j8B2{!ARSP zQLj8@Pz=^uyp%PL$NCUWeWuZi3~(l(B@`&f%`V$n5y|^!Pgt%H8T%>p_Pb7VNIdU? z_|g0G`vtY7r-bHKp`O8Q;I4`%c4Wytz7;!r7LPfH>7<61<{nH@o7q|n^ZOh7QH4?& zld#j4ZSHA@@aN0coM)a1MLU~$O}gh1+EFHxCeN`UXs_eUALU*IoQC> zOdh@OAJI|n3#DHaPYoobFYWW?U6R$Q(s=tWSkK7j5G;1*Clr@5_Aw8?lj)Ml3U~S< zP$WzzZdrOuPj_Q|yhbYEtM=B&waF3UDh79YJzDQ`-jsYqZNw-78Yzk-CnbBrWP&le zIyxh&RrZN=ej5;3D(Mk%eyH*pgJtItRS4?^LWv0xgzd!nVahZI?~@4XUODgH24fgC zlM2cPs6vlDBcNXUbHQEN5}pF?GR2*k9vIRUDDvrZwAapOfPLE}NR~ zgVqhdzwhpM%c=mJoEmq!u|PWb>gD}sYGEKdv~4BZ?%X}-L1|BzR%j6`yU)tB&g>*! zuU@0@`Zss!<_FPDr}Del0)r>804X6XX9Xm(Kdp{P3ovsmkEEe zKiP7bqXM;g8R@#Iah!kT^T|{p4y*HeGu~%SVo2UKzZ`uSXHu$J*opJl`|y*pwWLzR zn^q?1J+m&*PMy2$6{h<$JI7pIiKMWxGU`LJkyi{;msV}QD@Z!8=W+>sgbmmLgOO0gLxh5l^J^nnU1xX0x(4Un z$z)~|)&Q~Ju?&;@IjLqZ)3bB-)j0qil^mI$0`{IUR(osWy6dvXEbX4_VQ2`{^rV&t zmd`1e_V_bF~G+7>6J{INDsYeeWrc)QDvuhMn9dpEa*AAYZTkT$S~ z_)6)hOO!NZu)JIL&NclGo?WNjDEaB(&7D<;h1APg8V_(I8=IiC4i}GixavTa2mp{Y zX?`)Jp@;AgS-H(rjQzO-=nE_TKk?n0KpnI~LyYzJs)?%JACiInx;*kPz}FSEL_*W^ zmg|uB^5oCO_oig(PwUHmnh2CiDX(=S9mJSkT!-b`R1h}aDYo3*y>%?^zjPlE;^^qm zWqbp#tmV+GWH@B7o7`1gD}*+XxyScNOfLmP;L-k>Zwkt31>FQTY?B}3y_r94N5fx+ z9xwh_Wi@QAC6q1qSZZQNl*bH;MjxSf-JQ=5*36y7!2Ejnx*fFPi(`qSJppo7HoVQZ z6*66gDz(>T_6i&ECG(iXMx-9-rdSoaRW@Ha$3%?8E7?@^q*PG^pR7OY2yll0R}9E6 z{U@YkxHLi8&c?GHFTAXr`ZO5c9-y-(Bz&uBuJfXx53aN}SmNwMybEfpGTv-vH5}j8 zWZj?M7DgPUVRQcOn{f-ivZECMV_0UM4Rxhs5P@dC%Zbme5Pwm;=so4pwnm#JpVUm+ zburdJJ$w=*ncn0}=zfVA{#^5F2IT4{vDJosgEBDMo65IEBxLZ|kRU>L4rW;N94dsi z;@H5|AFLt7SJC}IaEV{z6(M@}Fs9pcYTF)`y?GG?%f*P=0~amMS=%(+LoeTtjeMJ8 zn~e0J%g?haj~|z}m2wxl@I%4Vksq)SLZL|5kJyPA_p{etJa}viA)C4lZ&85)uf56u zV%%+2lLD19>9cpZ57P%gPJ<XUN483+I;B7!`l8il;DhQXze!NQ)-Ua)dbO|TMA2UmBQ784 zD`zHubCApOk}pm+NqPsb*O|r*-vA8Okdm;BDX>OJ(sz)X+1eH}+2`P0$T>s`%N$Ix zRyJCC5E<+&tg>TArjzu`DhgAL^|Y43D^$a1M_v*TyPC{cIo{~X=PqIQq`aW^O86q<7Z$)egSUisyV#CpI`w-_QQNn zmf}0fx!C0)KemwRhao0-glqf!CuoI*tOybzZ;=!Zu-1TVnxV5cY!P5N z)sz1sGiiwGi&06k9b#BW{D|h1Btjn`wJt(Ope!1{MvRmlrHn^Tf}BSKM~EQRQfBhF zCwOp7x0k1F($IAO3bV`!Ke6SCQ;s@)+I0)U?yR2Qtfod9)V|#Xxlr`I%tED-=M|$y zmC@9t$(rc(z4Jq}s4K1ZLsp6nYhEpybUTRhcnOFE@5cx;R@IAmET`snfHVlP$!bvx zE7hx+j5rBAM5`J-abz8kPMzjn;n2Csc}K-g;Y-(nc_pj&4;Qk+srU9L7*gyae~!sS zaz6`dYZgn&h4owo6SNFQ%vjxi55>`0WYA5$CuaV7rt!#Vi&DlNR-G;v@IE6v)1WYv z+x_8G4~Ovbkqhjc41%%?;U_(rRv_TkHFaMq2YgXL%m?!cWPz&>K;^{ycfP(~gN0B( zt8I(S&8`y%JI43ZX!lrZY(LqEzkY-cL{WDWZ|yV2;#Vc^Z6Z_{#?w%14)7IQx0qw} zw9&U!k16AtLUKK`gejPp2))_GA;z-baKw)!8?)Rc3OIhT>1H4QkSHsAx4r59XshJX z`i3 znt_r^U&ccxk~j-wdFpGov?XZWBVa#7!z}k+e@N<+-hTvUoG1hK{g+Tqb+ax=Oz6Dq4r%^+KY1b8_rsWUt+J@Ko;%V+1;KqK>Ad}a&gF! z<`}=Z*WO7r(()LcGvPC{+36Lp7Odb~T#lb$iI~^IsUH3eaOyy(3LgO)S)!EAqX3@A zGob_Z8MfB+5A7m1lvElDh}tbAs4o5L#7KVdIr+Wa}kyQK_`Q;h)YVSiJuZH4pL{0|Z3!P| zRxkAwX{4vP-UpJ*5%x`WX`Yqx>*tg9g+XM~l?_EAo_A@~rAS&_Q&R$Q7QtBROeh$ld#&>-V-7>6ZM1ruyNiH$oGG{gFfzmZ8+-@ zImFs#-iWx`^EqqdRdV@d(CGDq`3C(1;_`3GP9AodnN#InRvUTJ1K(AAv zAe_DB5-W>9yHYik9(^%f6ME86X8;w-{)I08E`41TP>mx%y3GBn?Yju|lu?@@vtSoJ z_Llo9k$Edm4CD?<4_9d*!D|dyvGN#S0E%3*9_3c3(I1 zgz$2)JU`Y66lQ|08Cnt?2=|-}kPE@{5;~XmvmGUDR3lRQ5V!5S>Q9o%^FA+)ca03B z9_%k} z7$Rezmcl)MlR$XpEY2W{lEry!bjfZY(fc4BD6R$FK3+N0zrSj3j}T0;1-k+cn8Jr* zboyb9*e%Q?POrYRz~|dT1*?8gy8z6qZ3PyoPvJazi1_;CIkku)D|cKaR|8vKQM@!5 z&(0ik;rJ+^lVQgJZrY@V1TY;Dhr5SHK*b0amw%I;8z;$-E-5GzK$9qBXd!}FM!Y>| zNT_U`pTj!B`dH|slw;B9G%V2K(3=;$ zFHv)|&&ue?A~IYniWNj8i(-xhuHz47797UlC7WS&vm;?lDec&g;JW?6Xv<>*UysjP z$$$4NzZ?N~xa8RMA`>&A4~j~X-3_0*u-9DTfwbf}N}sC@RIWrc_KyOtbloA;^y1h) zV(X(_9H2FVzIxb!`aTv*fueA_fHopWnVMyiM zPSy5D_;LE7LrEeOlQWDD!rC-dk?nH0SMY0;sNAoaZgk6{e0UG4DJ9=^fe#WDMObwH z!C_)g<{tc}%=BP8kP(G`66EUIq4EWKw^Wg7+r`571kO>%bX@+l_d( z0Hm9MrqQO*63vlU8!dSQka3W1xKH>v==%6W>KC0L?kU=a8@F^k!#37uwh<~5^6CM% zqsOVwL(2TY8OK%_gPWWLcp^}ctM(~17ju|PVlc4t8=~N%>&YJ>YS-SLyftyS|k(4yA!39abc}Hr%g6 z_uks=m__2H(oD;WN8a~Y3~OQ1lUcc0`M;GMd>(Nh6Ts0!hmpk19R)OQ<1@khgK;jzyE-7R* z2Ry^Sm^ZWKxXf*uUE+NQnig}e)5{Tkoe$0V>Ly2%e0=+z>z_93o22vtEFTO&LEdIa zdRt`P;o%VMW~1CpUhuxW4{`$Ox^F9~pL8-h>e0@7-S=>fJ9p$nl+&TcqVaYtz&JBR z1Jru?HsW2yQ`68xHU^U}xq7j=t2t=cG;cxp42!o%xt|EJPU8QP1FtNu# zH4~n9P8j_UW%o<`s=Zfo1cz2rMSCn*Hq~IyVy~`X!2`{r+$F z_J0w(zX<%Zq|G=R5@*6*LQR4S0;DLd%U^gJ@#^1r+GSRPV`8)nSb&6<*dWlzR&>g4 z>aLl3T6!VuB-B@ch<1Nho65RVSWlOw*%CawZh0@uvwF{ZCl||CeoppHW;p13#??#%o=i$c(tt)FUJ89vs)O zyE97luIRdv+mlYr_5b#-j+OEo7x#E#FX_pe5-CjWkqJ=^qjDf?wkZ_e-)(ov4OoI# zecQZ_J(!2v7jq;)`hSC7c6+p&=e$a#C#1*68wh>p8MItSS1HGuaXrU1DQ`yW3(2tF zVVH3A1y&nO*B2x_1deE%XC$^5d3bhGXaMRHG!`-)^(-q32#UBV{i^7>D|KA=Z+NTj z^S{;JUp{9O)cc^>$-Adr>xxT-yJQ`RQ>S^rp~@+K?S2$_*LP9BWe5c5{@b8fbb-GN4-H+k9;pu=X6;*V!f1?+b@81A7E-NSY2S_b>KU+T*_!YElIImx& zKe;|x@*U8u0R_&(YwDE)C~kmXOZ3P_F<(9yN@1!bKat|{>$vzeDm!6AHm(W&Wa?(B zZRw|t2B5G(XH~k6+O=;zw306!M`ZQ7hf4&3kJ02|T`r^&bHT>{er#PVW|bjZhjt6` zeotB-b?Ke?wQnRc_}>82l-B4%s+juj!SU{_o`LjVqJ&@izg@Az!+3QJn{cV+s)V`D$4<+0l>O?`_?Y`H}){q$nVz;(joM_AB(` z_QqBJV}TvnmPm^m$QIN}w(drsd<9QFpAED%zK_9jY2DvM1k0T4xa_T}jT|%56!q*S zqeApgnRH;R*EOxOrPeLJ zh4vqS;9<6fv*Zj3O;lz$K<6b*ELQ_r9QDK73D-t+y3=tUZ#~j}r=VEGzq{?<3qk@e z+J}+jf#R{;#BSPe<=0NFrT`QKKgp{R3%Tk>+D5>u_p$oI%11#f{q1u|h$=VW-va_r zq`YW9D<6kjSU24vj)dtsoRDE>S`sOSGV|)7H3-mg@d92%)1h(!FNPd6gxFbGX-TSb zL7N|iAHiknbl6_a2`4A-m0!eSzOJHWGGPVO9wwUO;C+bH?rt=n%6d1MF}u7y*=&{A zi!ZxZZZEpt-&nacWifU6m6aRfi9&*LiafGhz|6hlu9ck7GOSkE_%jE2X2hqn!s=9( z185~~0HdF7732m$gC3+|erp^?*HjC%k>NMj0FA@-SHCq5&Tok9cWMfQ_()RdF^hp&v!QY+hdb=un>AP$tlt{XX-EaBtEcbb2YMf#7DnSpW3p<9V+SUMojaSR1+Nd zN005cu>rPW;@A;4t0Dl#d1YDL45d=-IXJ-_u380F!hGS!nl-JS*tC((%i4$a2*Zb% z_|B-M3dKxt8{N?PiKl64uF^~g@2h*fn7wp}faDB2pAQjJ=q^_5LT}Ds4}jTe?PwT{ z2sy5)oPjrkfSykd006%(-vA^OfH%+z=wz?qqHsoJi1mj~l0hm_e}gQkU^+At9$g~z z^RwUf8exIY9y^Eb#zzAG8=ujzrgJM_oo6%k{Pn&DP4gXO=Ccazkq8kH8O^zN%;VXCdJaco zh>Imet|z(udE@n=eiy`4eu6&d*=6$zV5~gQu%5I{%hzBEouzHi+mSDa_o_~T+5YPh&R91 zekS8RCCU30ix-BjE|M`(q`qZG2SRd zO)$M({ho^657yqlF#=wRzc7OEEHPsZZ5HGmSJ@wWocWjKF|u&+-pi-{f11+-9aeRt zL$(U2$&2KJ3!A(}ln3##?hZLGEgp<>>-BkQcCbQ!E5YOW@ki6=no zn?B$m?B3q0P*#AMVIDj)_}!&Z1w^qxwyOI1HaQ;P+~Nd8>=iF2-fdSG41rLuJW13; zygalocxnqG{*i3lFaMWhBSY0U@JVkrudTQ#v4G27Jg!>6RzvG$*os>o)=shW<||6z z-}`If*V^;sDsItObWwvF@3MZ9kKRgce4BV4nsH((MB{5poM`oPs7WqIQG!#x{DCYH zL{GD>T)P+`sYDx94+Brwr^=R^7zidUUX~}}y*bcWM>VF(seRdq*UTD9mIo%?iN4V* zH*S8nkKZq^c9T=q50!u4`BPvo-L>wK74BNV_F3#pMjK#Ap9Fv#Xn`e8pR4b%>2Ig7 zFs~V3SCpYw5|~=9bvg&i6FV(xcuj1JVB`hv*UY?i1I6 zZXj6o0R57OzpTRsm;%uJrUdIxVo>_Aq->U;D3 zvG?n}6Qf>nDz?)h){E@UE|F;9iPpUR8G7D4QK%`&GR$%a{@^CTT1H3L;1}I7-Kb-1 z3gUQkq#vBQ3~a<^L8E0h8rDr^^YPxJ>3zfVuT9xlJ+AoA+AMQuffa(o!X(&&$vyvQ zllK74>nEt|?NkeA#7jVV4xE|=0K7p(St3t)Rzd)S7~cPu#`cPQ5)lVp#g+f1fz#G6 z)#mDx4*QSF98ijTjH+er#k$NJ=2zIs&PsjF8?lMI!}LsN{~9p!`HzhcF!TPW4LrNX z{(q>+6IAaoO|egrm{FO@Z}gMFaqwy+G@zP>q?e$ADACgV^Vw(K%>t~zfb^0@qv=|Z zTpW;4G*l8Zo{0KcCHNT3^Npp_XdSjf5av%C<1(I-&sN0KcYEX|Bp{U$+S?OK>~;3zpX@{YV&%F}htr|)*n z5Ja)W2%`3_aVPxy>TYSc+g9r(ZYmq4etO z)9fOO2K5Td;C)Y7Be=+~bztm56$p$NZg@AIU(UI*R)m!Gh$??^Rnm%6eTZbGO^ zm4=+n(7V`+so@D)EOu|rF%0P=0!yBzN2J?@K5Ge!QNIpd!0J?U;hN{uM8Dx!4#1B z<8G6`>h~wS;C_V22x4;Dvc0NnqtE(YYNfXwTN&QemMO(nU&Gr;e$&KBPXP8?C#I)p zW*{p9MpxHUGe#V05vG4>eB3SE5asRtD1tO*(5#X)lWmldX2;8%NbIt{iogbjrqZ0++f#Pjk}@oy6o z>3cKa4^>}i>oDTw{?KniJ(rp`{67Qy9Yd3iT7}SY=P*XEols%p$bKgxNwrmnk9OurBG_ zS3^X;0Mw=R#h?qe`%?j(R zPPW8{pZM+m_fduMV}+)T_4i>4KC%3Umi0wsW;u>}Ak9>{5!(48li~M$$hF#Z_QM(2 z(1NlqkYWO4QUM|g*o8IDP^fxUtVe6s#8Cg1;HO1St#}y;!AqIYJx&efZ-!V}ti=I( zQto!`7-&B$%`4J|A;4eTZ#;A?lqBi^-9{}RPioY%Ifwa@hSRIJX&yqh?~sW?Ea+P8KOVt*ligdCDhT_TQjXls$Bn+R`dEISA)WQP_Dwe>lRCFN~E}i-fAOh;PFEbo}@*i z9ja21^*Y5v$ePrO;mUUTtnYml1$idRWe<5qGj80|=cZP8M8xzqWc?0)HA)U@5w>CN z=`ji-#CzJNHZJt|KEi2NL)XcYl|`|_g2Hj?rMu}NwhJqw@1YZc{XdXPR-%5DRF1rx zS9{Er+hiNnx+FW^HJ*EMtNf6Py_-AlC3w+xfMgM_P|Iehn~2VaTjq)RrX;!rd>&$L z&Jm-K8eRGvQizlhz}xM5-xLi71_6Y=Iw7+Ruw&Ut#(cQ>kQH{Zp>19{Iiqv(L6LPM zi=jfhTv)|4AVDbN-xqv7f(bTq#F$(5iWPomV>r7`N|Xc+t!h(8kX>FI_4{+3(fOc! z&W&1!Zz-kbyw!aKlEOr$iHHp`MPw@g16MJKEtmIAWU6Npb5kh-g2cb+xc`L~5^BhcF>emntqJ3+JgqCRCig@5j!~I~7dmnHk zIy*4wl)C1(OtK!R?=!HKEop}bnZB$-i3TnTK&W@KDjIh|N0)~ekz0f=LOr01s%(8?`4srV43Loa8O&Y|{44dE7{rux zps$2iZA<34f%zI`inGUh zSO52mb}lkxE)}{yR5HExD#s3s01E_n}8 z0j9mWr$r?Y;-5wcjwz@Za6~Q9AM~Z^iNfRkt zoliodaF=tV{F?~gLtX)`+BS&72n(QRBF4Af8JdA7w!_zTNNru8(luic)oODR88+(J zkg`ulRxH8ypYt?sFZN2Fu}^^=41mM{MS(!B4co9a;*M6}{={G=aQ*t}t&zYaXky1P zZeP2WxA*q#Tb}4nqkXcVB5P$K+CwCrzfxj!F9}S48*oG*} zhS{M0t3KYZOZDm({??9_n{)KqBM<)iVA!or4~1$Ro*>$hn=erm~u07 zg}g!R7JkHzGY%T0MWp)@2VoteoTJFWNhiMsgm3Cv8|G_^LiV$M$9gedUpA8O;KwMd z-sI4U-KYrTsNK5c$WTOsNc?eokz3!$hgeWDa4;Vwn*#(Jc->aZZNaf4EXv-EU;jlh zI|{ovMM=0K+mV_{O&3OYoPhBNngK~EXz#l!Za02j=fjUA ze$ahw+3PqFazB|{yXs=rpY3c2MD z)ooVFft;Q1AVCYBtH8ll>)+klAYTv@-VZvqO*-Md5gT-CzK9AKrq{`ZN&J}kl`#uH zH|KEUV-e2G;Z>z%=&v_%ODg;OoiBvWTU@K0XzN8fSLklW1b#F*?z?L#RXHDVT%3CN za`ts$k?W}Oi%q@jEPeW~La+0* z&_kHGI*ydQJT2}_^mHptYI{eHii?W+WM1IiCw;W@dyu`1sK~@6ShS^WAmzfVRai*$ z@&ILLALzOq*$9^jJ{fDUS@77}9uOzNCt`2PCz?EVHp5}G=E=KGAoQx7&f-s~YJ_Mj zogU37(q}VP?mw845&M$w@qpjK>-dpZ&^~e+8K2^|Wm3SeENW*UbS*RMG1@3NZiU+J zI}=6Rx$CP2YoY8xjEXjN<9-@6#w^3xyqpHwIT}ERLPS0g>GssTB=8;`z^!s{zFtdH zPGZ?m;cfte&(7G(Id&iq9_(dTc*FX{#(0Q!rpQFlu%dfH+6?a3+}wQa`C2hXa+Sy? zBr&-$5`tq%_;kl=9X35sL^0S1SY-0p96tJs z7;U*|eHuCY$9opo;Q<^yhDpY4bwKG&2YiqO!u4CJ@m`(XNC_zwV^x2jfH4gqE9nBM zU2C~yeMkie$GNq$_OQfH2`S;;Gzv7!Rz26SxSU=*kS@5F<4Y-xVl_zx@DbECdsv{J3t zSR3%myEUs$9iSYQSnlHg`B#9OwMznC@x$Ju)EH|=ZXXZ8L@^cnaa;~*4*(NJDKLcg z+P|q&%w;gaDqXVeiDW$L4qzzYO|xNC{bv&7?dk=KBqM$m( z9LEt!b9q#D-#JgfW3g)^-OE;@XkEmX%5w9UAQxBR*}wsN(W& z^Bb3c7CKm5Wyn$hI_XWIlUB+XjgJEe5ePM@l>@}j_7<6O?_POvMV$WyxIH`weiygs zFk6xQaMzQu$WJ9_JgiriDB|(SNb4*B)NO*E6VM*>`svC~5`TuN-Va`OJNb+bU(MMs_e&i><% zah17$HRG+3;nX0y-@UjY#q~e-o{|T^)S8m8;i!?;f)H0xSQn?F#2kd{z^YKMKp)2f zaC~Y%fKbaRNizk8El0+;3hIKMltu3cc33O);Sw#O9dBAjvI!Qo%xyQI@hUl8HUZmFp_Km!b8BV69$;Y1ERfY8Wp)@**Zu5g6a$gcvC$p99N8lf53x9HV z(}Cmx2coutr*4oo(RXMA;$i;>u1pQSWL4*eWkxwhhGfX%n{74rO;%pCU=0IIdnAuE zXD13t!l$Ckir0O(9-Uid_ElNoKlqv<;YBnnCA=7>DyBE3L?qd!0aKNgr5oX2!K5eeG4HH zes~uE;5h*RUf5^K^^%*hAIhKei-4D`Mq#>S1?p*slP1mPR)g||6O5ZCo0r_I%}Xl+ zpHK-rF>d{Na0wv09ST>ASb& zHfHJ(Vz(0v`)@mdV-jm|9)b^+Rz`64vmt(zHg`t6xM9=EaPwYVETBMi+@t<%*l_i$ zB#_bp>#aOcm^#1lX#c)}c*^B+j|g2tivt4Fg&SK#AiCLo+5o+ViCE-`fN%Zl7h|*k z>>CXLjasg5we=f%qI@FylqkiGs8;TBMag>Yt@ z^O;p|o2h!Q+LL(R`1l-Uw<%QrT{ zC+?{|`O~e4t%R|=PAP$aQ`@zs)mtI+P$_dR6=yo9hX zF6Hi{9*G>Eh`KLc?ahtwZ>4VV{duna&%N{d+?in-kRQN+*Z}B@1yxY?LTdYHKhu(> zA+VLqlPHV^dQ1xQsh+(uvvXL$d2m_4A~Jr;#Zhi?O+C7v)BFlUN-oEGaH;AOS0NC# zOF?RrS)8T@N$y(UACL`$UDBn8)lzsk5gSY zkp=*&BxymhGvIxbbE`GXTe*@b5tAbG-ha@1MNT2GsNXLD1!AVpX<&!K*l!V~z!qGHA2JA{KChgXx$z1JfBGxk&i9bp3-d7w!4((zI4zDl3 zl~W{kne~c!c6XP`M(7^nd#R$jfj;pv-;LA`QWkuRz2MALdr_Yx5Dd!uX~~vv^D?4l zl4Q^7W2@~1zyo|+YT!9S)MC#|drTU7gM_&Fk_!I-K@k%&k@rbp;B1PMjetme2(h&ci%hy zPCp*S_S<(h&uZ({$fuz9dub^*1{=m0`pUx}v1XYn z6;$4{0r5=!o?r=~gfzB0g>@KUzs;Xl*n2rvt$5G8@vMt@Ec%rQpX@SVC|?22;xKonAhC_>fTx^%CylzUZDe)9i z0dmh`(RhUo=ozV5hiXSGg|WDXKBh2s(%o2g_s5Nx+}$AZ><#?& zE-MDDTe@EPQF5E|trgY8u8iEcK7s*Y5&loX#KP?hO^F6?2dYMA%=f&75bX@BhHG6dRCO7avEKk$0mcOkCL z7H%-(wHRo%WiXz+z2uT0He)aboN}^H4%cmr#yu6{gpMqLB=!)gZOK=du5+R+URstK z2y-x2M>T$L3HxE1XNtrMA;6bl($pP&G_ilCxC;C-eQFBVmBr^>T*O}K2RW#<4kfZ& zQW+C)`4)b1$kuYpUy!yW9C#@i`Cg=`cDX53vW=h_$|g^zt4y#U2(0Adq-TXsAmEDX zcPhVfwRaG~kL)LBzl&4Ph8*iX@`*2W0xT>|IbyNPRr!_m9JRv1Tz$w=`PlMuD&`*H z_cLzH^yvt5(yA~Z?Rm9NM$m*->gbu`2eEk$QrFGuW#%XKPVHct5G94k2; z+VY#^B%UW^XAx9p1_Fh%qAy8noQ^?pqCpouLT0o5aGU5&oM;PG+swHJ4DDmPkwCZb zz?)wG!CHIazHd~r<0d9+{p zBjYcl%uR*|9mHXYFXD)kk7a%hk3=Q>)ZLEBp4j7ex4tHtEcuynBDigk`knhHn;Tv- zImxtj-+w?VN2?hoi465Q7is1-mDDXY#^&phwxQ3Kmdd307v+88(m8Wvz?w9#FpRu& zbpIb+Zygoo+O`i1CzO~k?)1+0#y`bTdm(@sZ~>0Xp$HNXVdxjJIx}Vjq!9z?&ey@Y z>2e62ae@Z^TL>BD z&4&>{fBrlp_Gup~jc)&!amt$Hx7-rBpq1OjmW@gFGJKeSoeqno8qQbPH1e4_vb`+rKS|0!D^ZNC8DaCNHew!Ff2OuJi=u-sy88VmU%dbA8esQUkY&3k-gfd6vJUe_t&aAq7hLUB`AWI1y z&;c?&x+h~x<$~}yj2SYbj$)^`s(SQu5xhtQQ0=YNqxd_dsBgxaH z>5#q;z%aVx?q9B{1G%)v`jORAv@ajy4xZS^wF6KvZdaOq{#gIOkg!8)yyhP_Q5=Yc zj{Ij29q^CDrdcfO@VegUitwiZac>*YIo#}>9p#c|8dcUNx54|E5~V+DDc@ytc-SdJ z8c*cDn9SYSbPpz50c9BTqsWm+kj^kB!Cn=(z)jM^n-9Na`lDsj@xbxeDoG)1>UQI^ zdFB@IF|jid+of&yNuULb-Lvj$LtYvY3g^wyAkKG{W$b8jbPn^myi2yrF_L+Acw(0j8(iS~N3}cg&3}kYO!s`m~ zh1&N+Cw`+;jA*;f47*a%sm=971)7r(Wp^g_ZzCg;>Io*&ldn(mnmQX}9pU}98W9+a zbuX`;F=!8j!73jJw0)K%Fz)70ta{>zVMIG6u!^UzIp=lybP|*WaujCIuH^Zbi=9qP z$Vj|9E@OzlYTPR7(ydYfb`_dSp>2ftP5w;Ef5m8~v5DM(1PviP6EhQtUY`h+?kVVR zs2`JDMb6y4D1xZc;+w7;)M1yLZ9WtqE;(y= zX=QaJn=fob4{VKOXG}=^p173PX(>1*osonayJV=*@YS3JjD<0+tu-QoU~eO^!# z#W>{yj~T71I?u*in^-E8VK+-fZPt+OM!R@W>IU83e{}?%pRrl9$a`-zZMhLz6c15S69Ci!abK=j|^D$3l;W^=2s`1eK7G%{DkgLT3)NHj(Qc5jMRx<-*S<|4>$AX4 z*+uWAznL*@!i|RKu1MYF&y35g%C+2 z`-~B(J@h{w|DzFV@DN|M{)fN?NavWp$eRAm|Gej+xj5AA;HNz4TqsfUBy<=cx0j;- zY+yMBKK7h;gOPF@H-8(+u~Ug$!q<3blCU0jYS-+L(96tx#ZN>;)`yY0uswk}T}}7% zf5%Ag*|FtwFy5exggX>TN~a;iJsa5$0(@nFsX@oUz2RiZbYOV3-A{C8ZKzf&!Q>8U z+@60Vawh3*@sGWXES;bIAH5**jRt_WECj|X+exadyt=$8)$KZ#Ho-KPhEPjS#9EYuV57J78^w&oXmQJ6+lF23$9*bwC6ne7*>)o9wP zO_ZRf|M~1TrCH4o2lp`8YiX^U(Xy}xI_l$|Q4)4AZ!$3tY5`9vbyMm)$j47ysu?0v z4x4ec>*?B}3P*m_iYMFu6xHi+ih3oG#M;7vDmn<4RM83$TC^$}0+*ALK6f*vb>iAu zv!yRYBP}NJfc{n(<^=@NB=E^}{-H%;*Z1^;=8w&YM3#Q z=gWWBkwXMH2*!s1z$zRjd6nT-f6?mdc)At$?f%=hn0&G-j2d89LC>|t0H#FbTQQuk zu*sZ97}H58<7FdPl)kRQPWu@Axnj9w-_B#QGcHOs$~%&J#55;M5!$^anYXFa)Jyq) z6fBKV*$QUDa83ESUaynOhPqd|3NntSIjpHFxrP_gKp>C8xaU)SR>jH}L%}s$%f$B0_bR-STmDDsmvJ{3S`!R2epom*S8qtIAlVR~HRr@&s6iXl}%3VubJLnR{>+Car;6QOA{@S&qIsC^`;uwuK-RvsI1pK$07AoiQF4+?($t7WQ`eLyD?Y3tA4&rYOXIB*GrAD#GUfXq) zb0G|IlQ)|~|F<~-DLBer+L?NBQuvEWPxWe`E&k2b=Q;p+4hcmU zoo<3gm242(j@GDsa!Zoc>T$%+*Cxub5V~7uKv_cojt{e-bP-uwyq4iUp&pog!LN0H zEJB^fpI{srddvB7udi&oNT}>fwpOdhr9bvxcXbk(HZ9bx9s;Mne&qVfc9LnQs!?;) z6wa?FA8-4Y>e%II5kTJO?WM+&B!}0%3xWVA)tTSXVhoEKL}6|tQ<#zoJ%)8#F#VD) zAEq==z)1v;T_@5GfNeKw^d|_ol*>fK>^`+}YNAZK5`#$cg~hr&d>nvM zOnv*`EAB}HjuaarMG(p-LZs~3#cJ15s(MxGM*NVL8|~O#M4D}9NeP=px)K0y?f~N9 zm@|~7O9>a{&5zlDn4lN`ogw#bgLOag_uuoD+T0+wk{0k`YWjV&+us;az{2hbh$P>y zIe8!B{=Bj6&;aena}2+?<+yZ=5DK?*_9ccCnI6#4^_G8N`8Dv4mr>mAL-0%A_^1wq zFAmNAIY7Mfb)Te)4`rUPg>pOS=_iJjnXBmck1krGTx$EG91}~IkDhkMTZCb50TZt1 zAR|w^p4p?+&cugCph-r=rM~zKOq*ZjP&)I2?*#{JWhCJ$;4Ut$HfR*^r%P^F~tq4?>x$yf=9a3xg627fZq}I<*il=FUS3bKIv^Xz>;zW z@a-bPPvqE_SY{&!rsIkfea(LMVHNSMl^x!51xV(i`-7nrQAB^I6da+zw4XfC<>7%b z+N9&=2#+-@^;yXExiUC@9RjX$YGhz00Js4~PKBJV074n|2EELZg&I z&)1p$=4aYv{G%G_WL0|3JEZXWzVGTY`%c=wAet&u64nA}F^WdqTG|X2H9Jk$zY*a% z_fl)FQe#@H(i+zO|_adtFpwx(dj!huefi~s|mHON2@3nNDq&6u)1s8 zCcyP_;>W}YDMQKoUzuJSmV|FsPQ(ndLWvnqA%u7-%U5WzQOPMQg(xfkcrW{cE);vo z2E6Gi&o1s&(gLkjVq19F(1uvKjU2Pwyh+gjH;|5YQ>;T|Qb+Go8J`B7L3a7$H-JtP z_UX*!X-mJ)DOgCz`fFBXJ;On&qgn&m}yNbbsCj3 z{;G*@O33cMyl5d%@LH$?DCWQ?5@g+ZUHqUKy-k})@s(RFtHZgItmUe;wjvuvAJ0rl z1>}$yg@>uvQ4|@y-}}CQ_uEG>;(d5@vDb!2|SI$*1M!)OrU52zKV#(aC;Gn5#D)i!t(`bp7D0( z5YgaTy}iQh2Ph>6d2}O0uG{=fMP#@Dj47WG3+n0~8=|J&34$U_fEWlLAUgWHllMEa z=5fK5w0boVN?M&h&!FBn$(4NZkd-qa5xk{xtfb@#zu>r{Ho;FRnEJ*|HFfr&)PReK=w2A|YQGJLtQ+X%FS|Q4&x}raIMnlVf=@bIuuD+|} zaJ`~Ck#E&hAk9C(fNo5)az?%NICKGiMy#dZ1sd(-U?7`rADK8!ck@*tg2vmKn>k!8 zxEn)p>b$;pNCk*p)0X7vT zGHf8s>DPsWlB59*R{vO6T8H5|OE|Ol*n{&@m{sZF?JG5OKW_X-nB55>I2Iw#z?0#A zPBZulogzPgZ@{xza+D3d^(Y3QN3sk1S<=Q6gX^X|wUQl8^_7WY1h861UtOLpPb9Xm zXLzG2Ci@fAQaOCz+8_IWd0Aa`5u!DeLIMO+hM?}*x~CbZ0(EIKD}Jcl zcjM@dwjbUFt_Y&2jc})GO(g{c+pG=wUU*+})y;&hcttFSa9!1LF3LN@xeR?O08X~Q z(z(6+QG5TMA<@~ha3Qf%pV%KB8X0QzSJw=dZg3{aqhDxAEymO$YMkf!S*Dr*+T8S~ z3*L=VKy+9edM9z+B&mOPc0d2QH^t7X;+L!hDNsa(=QY9YdcPsF!`TxFe@gR+D)NSz zcuNVR=3|G#68yZX-_4cxp7T})_o$r5!0`5u%N613wl5zi(94Rh*3YINfd^mc!f%gC zF*?o8N1i=g&4BM%94%+qUY+Z|7(u<>UVkk9vrbDfHRQh?XZgS=yM)hCjM+C6@rEM{ zsZndfX1*Xp;Pw0k0qGafMX&R(5R5lt+phCc7#fN6OY+>*iwm;$3h7Fn21{A2+3Bs^ zm@1u*WUb4g8vTxULP)Hr#hXqAbTWH{l}K6@;2ncwdiC#dl-z3U}J3#_CC;URAJl7vJ@pdoJM8f@(~E*mR%4L#dyFHAEHPG0A^NEijXsDWG(JZqDBE+ zqERX#U{G)gyv?7&n;QdA1>kANLKCLGWJnz|nH)N*9sSFr`C|oOc@DgWQFSL^_cF}< z_Arn&r_rhsHlNLc2K?h4v!LIFQVzXyf8y2)jwIZvs~U6N9ok3Ooexx8>ijcMf#ey$ zp^y1tm^lJocK{0?}5&%*m@Js)Bqlb~$}a*#6a4Gj|J}M7^zl^R&@USJj^H* zKR{kQ4<@4E0GJevac?bD)i48L);6}|y=F|%`3;cm-LsWxk>#xBtdgDA*!K;1!;)8r z>|k8!;B4*~;cSkOB)Ql*q)gZOXU=2z8J)1HafWjpl0x=zf(R0xlgxrf#AnV z=N$p4Oy{}U`i*m_OoxW%J_7#w$OL|inoaB=pngnUW;5t4g26|lLDY-=?slJ*bAsII z_lXAFk;5Apn}Pe$R^;Ca)v$5&#`04nGz$xr>;Qn=`{}pWdh1T(=sUp~YX1@tJoJyw zhHb-^dX`iW(l0klW7@#pU0c+Nk{Gjpn#VJ$;?Rjijc;Vu za0#L^v17kE<{tWA=l&}G8IiV+nD`4Yf>6<&acGtR^yhBbp^LW-ZiD`A-F6!HSp7Ki z8z#KK|NB5cis`CP`og@=2GzGI^LZ_*eD6VLvzY0DstqgU?QD z5DI78n^SD^ki{0r(|G@b%9_)Ny1L`urK^nK@|`U!XTQ~fdj!8GoVbv$_eT%sOc>sJ zS}4}~1AhUqh}RTDuq_4O#N+;bLG*K%G^yit)BQ{=bkbVlQYgc|@eKr^d<`_9e=qtW zB5oRe^4w}iVYkhQn(g%yc!G<f*AV89o_GG?75GhJu^*$2 zgU&sVp=Oe)KUP~hofbRlpK4=~d^vpGD{R%vYoSAho#FriJnQTm#DyA-upwgP&KF3R z6@tXQgvW2?v2P7^9Ve)b9ewgaMAS*XDh7%AKC-NMCuF@Nu5O8<4OcslD1MyI+oSaV zH3;KpC*S1bzL_3t4mr?EGL|>?O}}s-DWM_**UhF>ZJ5YpG|`r9n3-x5ih0&e_Vs5% z*^8zMe48HJod)~Pxb^NMo{_sN{MHl1sAl6aDbJUDBLxxD(td-PoIAC9nZC}_EBFm% zu!49$*bKe7^**#MRhQ5s&t{Wg9@{$#B|Q;z6OadqjZfIXYr2I#_!7&%+^3WwlWU;@ zEB$_9!|Ol&gkoWRqyV~XtYIM*SkNSN`j|DrG1TU<^%ro)e2mZf#|cIgg`f|aKsW8d z`Bt2-X35v8mq-&Sw%0qmRvE@qgeHf!n`(ru3NykE0q@{M!0j}Q9sz_nSb#$l0Xtnp z!}~N^!Dquc7It;Z%|s{R&Xe+ITVhiuM;9-zTGJcW@L3w<^cMwr{2o4yGSMa^k|4jq z>iwU;f)*TAQ3L+R@zXb0M2kXu89oJQVqW>zkbsu$z_AHznq-U(ytPgPxylGSYchkG z90JsB1;$nTD#i9Xo$N5I1+HXt68;u;mDjNRmxDGw)beZJn=<75mV2RW`eoV3 ziaCGWUOPMN&e9nihQ|Q25M`c*gga^@;4|`)U&(h?k%tK0qr~s9t2NIWrGF;t6!Pw#6Z5)<_?pb@DJms&tN6)q z(QnFM>m-qp#HzPn{#^M|^{4LvYr$h6<=u`G_v6OXe*(Kg{_maIt#E3I{8^$buK?|# z5qEy&b~-*mJ&PS4ehFo(1m58c{%SD}c;a##yn%noC=}SBh4VM~VEvik_$&%`WGe|7 zgmUAnh!ZxEU=V?M;pXp)#xdGh43e3${O48=&wnLZR~6@lmr0&SxdCkR=eUMHH=AlF zn6LvQ98bA4a69&l-@z=S;CY0XBvSs|U>PnznC>v4l5RecsBZzOwk2@&=Y4MZ44~by z4#K?eqV_(c{BuG$LLUxvf4u{+FaP$wbtUQfQXN7!f$4KP{vvofd7)VAcPD3OfOY>Sg{&w63zfK{lH;Ww0iVV{S00p1(D5Hwh>1Ea2 zLk<86uIl$&6j&1&g$^Y-S1k@n*&e^PDiK74T>olK-Hk^Qx172qRG%)Mhd6W4)-Twp) ze>0&LasH_=2EuGrp$y3>;a&X*`6YOqCpj>7`)6DJLBal0K^G<%^8#<5_EZh9TiHK$ z`yT~MpzPCEy_T13luIoAAFWQzKcYW>mx}?4@D-q|34Dh7?^fvl&(Hs(>&XHBulM-^ z>r4Di*A3L|9g0s3kRHi4ozS}}FtZ7+%DB$)Mk=eC)Vz;@kh;IY@+SiJKh zYrU?IuRMUrb-!`4N+toE`acX%|MZ~#H+>JN_6u!^Ri$-$NulN#<7Zg@3LfK`LN7vd z(p8j#&TELT?DaZ&dif*gEC~Z;E%R(TyKBO&FL_Qsb_5*GSXL>+q$V$#Zg4LNc_0@g8SaN!Kf80`8|(O=E47%0!4l&C`a>b@F8In<9;NBG(vtv{3~~{-%`d2rKPn zqt^fPL)1?oQ~X-8Q-{64L`v;}Po9g=*Z?EtDg(FWa_l_-Cw7xid-3FAWo&Dm9z*e% zXE(Dk@)@^iht_5I4#^R!!%Wf> z->GO*!R;emNJLpR;~-C#NV3@nSw2NkomkC#=N@m%Q(z(*tK??#Jn%>oA%Ct68vI0xBEfNTg`!yY#|?yWSoaNj#`RpT4sgLsW3MQ^ zq1(?E0)=F;{S zP_ETXfA9YN4#1iQTl`+4Pr#CvmDCX$YP;r?BivJ985r$}|rVx9=z2JYzZ`+iZ9ik9rzQarP32{uF{wH!KWFOlM= zo16<;@GMSc`Fsy7aPMG;>mv<+Muwg*>l3cU0&W`s0Cs|ziTe3%&vL#GahI>@e|rfi zH@WcSa|rE~iF(nIVIVQlDMjy1_yNiv!(&S`p4;`wGY%LH2^Z^d7mb@g4y<1JdtD*N zV|d!ZHGaLmMMraHM?;1L;|m95o);ypZtueHJ6BQB?y;8Rk#Ipne8?MU?kRtQm7i99#08r03lXq)bLx*FqUh15b@fSQ?d(Ji41n~! z$i?{Ho=+%!xZgEBLH8I5XY+(6$0c?&kMV;-`tCef?hCm{Vlr1bqk+M>l`s?p2tOV= z>J#QG@XK&agWMlj%Olzi_8))zoj(R5b@AJ;XQxjs6CxPD+!Ll6Y_PyETlg@kzLEs- zQataqJ3(E<%9BmH_+}VHZ%GY4;)iiQ2Is@nn_+8knv-Zi9kn)Q2I+)GqHO4*Vtfgz0#%ER|{{uYJGyKSB}osj*hjJ zE$$;=L*l|@rVGTdiVO5bm$A~P&@u4Xinkgf|nU+WF%_P7t{4W3S z9PaORMspHjh`;p(KtX)ZUleD#Dq-1#_UZHH7Oh;;TRLF&b8@!S1Iy_2w(ms*c?-VU z-}6K4^;q(rl;<+QLX`%9Vu0v*ByjFOjXJ;(Kw|(XfY&!t@q}^y=G+1FSY-h z9&30v_{=KDp&EvNv+bVdLf8OQ1>|q!mdk|!!gpd_2>P#KMdBheA0i)(fTwT*);P3hqxMhsA#g!@mO}7I zUs*8{J_oTm3|9ViO#ifVoS|~C=-1aX)ZN-;%JCIPZaI38I^Jy5B#vR}>oRNP;cB|b zN2Hs=xRch`CyJM^|Jw}%VCx3=f3w^u*$oVY_-Lk^5Sy@YDGlu+Zr76n_D?=WaU~@} z%yvi+vIxgz%g7UqEx@#=5NQk|(#Ol6{WD>D_GLH0X7v~6a5E3Fm-Ky>7Qb^Kr7e%> zO^zmT4Nk7ZhU$zN2aF3jL+J}aE&S0)m+`T0FO2yMd&3)_W*@HNeTYOtz9RIblZ;!( z=!rD|W>;VU5=-UP<09*IdT|;3+^>*+Pw^-o!f53$`a+JRD&r9bp%^m$Pce8x5ii64 zyM67+0q=dVOwK~CDQmL`k4xjtr+%?itu@wF&B(-yfe?t_JG1iofo5!5Z}moN-4LtQ zG)q7Nl6V7K*&Vwvyw}sDH$&faAmD7kv1h2MuT`Qz@KV*q*Y=R*5oLA! z`!1S9o5LO_(ER05>M4lY{Et9!VBD`DKA=|E!7I-npAxyXB8WfevX%IIa^x&dN~?JMz+reuabn^8axHk;Y?$l_>~K zX&0U_P^kg4IFY%VxYkE@;0am~ zUT*X^C)%Y3MvwBBT}r~<;-uz=o)qKyiUh@FG4V-Q3oenfo$iLbFp(9){;gbd7w3dX z{iym$P;#VV+j%@5@;f&K;^!zqB)sI00PLGDUu#fed^Yx9(shWb3h0C$d*SYv(D*Xs z$5Lt4xAqlk^}-}UMePR2E%6_)pbFip@yZG9tU`DQo^d!M9hO{w^r#9J;p|Xm;}rvx zD1Qb1Q^)?>z8-;vQcay-p8pf3{5iMhaX+9Cl(zQeo*q?eJ%_!~ zkRX+_5YUOpw@5gT3b_A?3d(_-mg09n4^&P80WEd5&rwRmRzI|;<~pnZpw2k=|M9Ws zxrwze9VGIu>3zMVoU$Bt06%AOzp>e;stDJ(Ob@%L(0%l1adL%trdZw%V59k+#{m~$ z$Da>5*HSB%4^;|J^*!Fcbe@=0RfUuJ6LS-*KzzAgIwb|1P9#exh9v$YuWJ3rX8s4K zdCs-dPr6EOY>%@+I-*GG0=Sij)ZVnb;SU1_#A=ABv}%#b%GBGE4APgzyI$y$y`VZE z79!4fn@n7H8e))+e^3Tu>`<>}ZYfvCvQ=JPjavK*C?JmglRy1^I?q9;=c!94Edc05 zeJr98&vr_8=g!@`bfmizd#xLX)@`(D+-PiP+0AIIX_T-x(i1+mytM~XPM{AM2z&P^ zi{n_pEd5tSu4XbN%W`QJNonc@_V(v>?Y5x-!EaiUBu5*|iMB79idP$6NF;anm;`!M zf^T}gWsZf``^~*p`YQE<%l#ezvw*z93&leHxacNh}K3qdo*XF0U+mIR8c#=ZuqlZ>HTFE*7CD+rZ&^@J}x32#~kY z0@RbOVBcD|5I|2={jX_l6&^qq$A#SeMrUFRej+vXF%~@-He2aNaEx1V?qD(joh*_9 zWH$=m^b;g|>Q_4^&1-sH=V<_pRirzaS>*Ci9Pu#;84DLK0`pf?`v~r`7vIT>xP4Ne z6E;yC^RMZ)w-Z)I2EuL)j+XVAo0N9%HHs(RLWvgsVD3&fIdm%F-`ZFj9%CLdVJDex z-D6oS1;znbnG81+sY@olt0&ySPpo4MY$M~p-U3KuF3_w7aM~JgUI`dBrzm%gF z2V38?Dx#6*t1V}|vR9Zqm;~gukvDhhDu^OP7v9(8y_~GXSKV37ggvq_pi7^>n~ zg>00`aGQyvyvC8zWolv&QMg|?0G!bkxZV)U3GYRT1g-T0cznf>)c>+YG{DtxcaZ!8 zV(;>*_lhN;l`()TX|Q=4WWqH3Azbo$SMOXJlP6s^p37tFrq_ie~CCtiJmP&TEGbs zmf9U$rrVn7ni+wIiIL0UejNg<1G%F@m+ij-gL~=i$!$hc;a*bVbxzKJ`X`+t*ZF>) z@8#cDZXyIPvvAMH-aTmJTAL&*ASPR$B?4=y{geYUF`h6&PAzFJ##G=-IBu+dq>~p>THK~(Hg~n=MTG>$1vBvz_Vx6;7wNm7bo7RF z$mTLCB<^EArz}$j?~@Ds^eG<_^h~3}M<_LT*1e=@GmvZ3IZC!#sxWv0a5b?>>J2nS zkl7L!yrO4x2gslh7vzOc-<7NphduF|%{_Q!zu^K#k zh@@2l1nSe|5zzal=wSDZ$=>AuGTvDr=6~N@Ry<)+QdoV0s?? zGsa%JGUD5KgK3HNZT{VhCm&2$x2zpDdz)8;fvHX+?P*}fw*tlSCQCD}+FNcHJkP%5 ziRA*sdc>8iIp%ncUYKkYG-(!~GRCAk!_MOow+7a3xpvrBU#7XO? z@5n*D@yms-AMQ0JB*XGWK2&r0$yxCB2XLxJYiKSy#mE^?-aa}c+qjVTRk!GqO^dB` z5Npj#O3F89zA-|YKN!>Y80f?+DD7PtcV%dg@3-{{4R;(910r^BpaHF$)*7!L;Sfbo`H+Br~d5^4UPHWp}=+%iuzTt#F7^SJ$yStF^& zAnnv<=Utix$dejivg_F5q^+)TsC0-m+yRi7s(Gd$ytGD7%=%(rX#Rrki@El|PsAy- zf_q|LM2`>eUIhl^0!**W#W&4XGf(-4vHQd;Ep2oIaX#OF#cYWPpti>#tA(2u2l7XN z?<)vj#r5`Go*dx{{GyP$37Ry*+Rpn|@RJb~*o87tjRq9f=5}Kvk$%vx`YJ|_X^lOg zN`0k8si-9HqB6L>Lj$m8Nk6@bYv{CSTsv&B^?gO+3Z)5I-Gzmqo^VF2NYz6B1Q zFOk0#prEQU8kT-=AEj9EOxWw7+)l;mta!kdBIoUl1-$bS5`BfnKaA5u!|mvbc>+3I zGLIo-@8*--8A-fvMMd-OrHg8#8Orrh>%I?mzK5@tLflI8!f<3Fj@CaaB&siogec9E z6>G$-$Vo&Az2@Y0JX5KOpO^^-2>Y@#VE)@xDCIzLpM9io{Rv0c+Gyx%@Y7s;UJh5) z7g%5bYc(z~>PV#dRfJd=l0I)&eW>QezLZcJnU2L$W2iDrBahxr4uhl*AC#uzb74!z z)$_>6r;&e}wc2ZVsUu>f$!filp?7=4I&;LD!9RPeG5byKwD0H8Z!p3`LZtWS2G4!W zR=)P1qzed?=9=Gf1N0tIxJ__8`FRd`khd~9L?a0VH8Q!ugOAaOfP~J$k8TMxmzh+m&c)F z^-S%k3oKfK@@n;cB`2(7CQ2YMbgvX`vU6RCe+RN`%yeV0^%Oy#3(gx``40C#T^rH> z%kR{p?Z@(GYJH#%k4E964i1rJbFxh1kyGQhI}K>Bwp4pnOz#}`u6s_}hyupGp z#qJ%5XaW-^K&t73gwss5E+%(pe$M)8L0)S1*VMxU#5O}uZv(eEz@Y5F z5pN1B;X?3W9zEtT7TP2_1$cje(r<@&Hb8SX*FZ299!(~tVsflI90mH#zV9>if?(x% zlh-|>?T(cTL0eN5a0$EUyIdO@8)aqflP;`Oo9#}U(a2niV2hcW!;85na|L+e)!w$} zLQF@$usiR&fz~?Q6)@h;xysLM!@wV{F>fMPr(G{+obiJOT= z{vd}DF5=aq+vc7NVX&The1B?K|0MLlGGqdrvXr+T`fK*$N(h8SK!G;LtigW+06YOr zZC_N97b!m5@g^Y=d2rrW9(*F~G?Fbq$=jq*6ioYKul0t3K_s*kfm0lE@o< zSVf@8FyUBZevZomzKyI{!rR1FxOf3{vF8aJ&{fPRwuJ=U?*H-XPajh?9F53%i$^R0 zU0iG2124?}GGMkFckqnYd!ifEqLYD7KK=6RRg`t+z>Y+xNbZx(;%*_AdW`LUd-N=! zJ3^uP-k^8|<9fXx8lfXXJtY1lt6oi&)K<;KA=*f45x)NS%c?y_WK>pqS3P(SQ~4V1 zlqB0xs z=iYi3Y#%}K7}V6UbKRpsi|7haI3{s@N2>MEO!+wX^NK|?jrdM!vjGa$5G|L<08u=z zT>o270q|gS|Kh=rK`?)S>M%n7XxzkWX5@6}RT3@1(d3xdvhI=C@T%80YlhL=D+I7F zipchE5q?4A6&d}rd#R5r_>Y>)j%SsA&4MUC-r=)s7rIQB8p>MqhN9B5=`9Bzo%Tga zKI0r(IcRemb2GypGSdE`j{yb>>? zhZFH2Y`VK-#DMrMy$-{kXpGY=e(tnCn}#CfryRuCe)cp|K*B&HUb)?stBqCDO48tI z)uUpud^>lot+c7YJSAPDT+8k*drmGF{X{{!B4`VD>-426lWHT48qclaY7m%%FKm2< zb`^1H0p3y`UzN`2n^f1pA*p@USCOwDoI#8e$3fi&w_8*HB0of^?R~FiYm++3j{btx zWV;opEp!P5hX4lw;LP$EGw}kh!UpVq_Xs7veyTG|D}(LT>UW2Nx+6B<&6j|{W`gie zLQq%MudJ@D{-pKK?p+{gm5twV#`U{onxdhxMU0|xI)``}*PTjff`_tf%%&h5=>Mx~ zl{o2N%6#juA5hDmJtUjwHn~#TFZ8o~y^{yNc@!S9l}KxV>(owz9XZiKW)QL)xxh0= zo$Tk?>y5@|yRTDemCX5}dp+ZJdzU3=vnK4qhEf}ClydD7)A@R=nmbL2k9~EGdQ^0O zFO;MHev*U6#|BEbdUsU8)J(Sh%na2weqrj21G6w(v6MXsuE|+qv-sgvQFFPhOWk5l z*%hzO`3hLJ;?o$_aT-lv2WeN~05w{Sr!e;=)lAr|2J%)^g;HPkzNAc|keHrzVh7$% zAnBT7Hj&RZ93g)^ji{5hvLDTz$TcX*DX5ERvRlBe414d9qMR{c)tg;F)e|W>`I=`<+;;Tgaq^=|->7}HsfRdW`Go+Q! z*15|D7>KW#v~b@`eQG8~hdnW(t zI^#>a?CR<&0pIHu)`vVaC0Vqqf&)}g0^bZPDnY)w&^}13jVb4o$QgjF7t&42*NVORZ`0d5LveF3e@NsJQ$~tLF+V&7CXJIG=F|J! z?3FgMp6P)Cg^kXSa>t0R$+D@YC!mzsc+YN-mkuBf_D$h+HM*dBBwLP<`^5urK+?w! z2`=?jQ-zIVdYs#vKlDjN^l^);2d^gZefN>w^GUxm>mq9%~(Ge!d!Z+p@Wz^ikIj{j2RC{NiZtSl8gT z)#C3r`oX+{*Qo~eN%^{4j9keGljmM~HF38FB=yR`-t(;BFI%mdBoOPkulUqAap&FK zFR>%akH!lFL1W4CIVRUkq)~X8%}mDHy02Ce|I#q`+W!&mSf1EymXx;;cz=flrN(wi5X{$6-%bu6sPXG3RK1!0K zOtdTl`oly0i!P&=D|eYn(PZH?YwdgAkM6W~w>33VN%`FU&4l)gJ3t)1p%MlC>oQK; zK{q)L!=u!hWyzLld7GF#$PIPJtH+v#Cq+kR4Cbo88ZtK|)7{dV`Y174Her(}S&%Wc ziJjujv=Geg;R)z2?mpNRGRafVNP&{WxB>C+!wE# zXK3QL*E&$J4ykQ&U*D_qT-RRJ-T>Ifiy>ZLWj(T|QbWe{W^6Mh=Pc)i9CqiM;C}lb zW}5Fu8H6lJa8~@@uWso zduVC%tBT`d3oQ(Koo&ZnGVeTbh{u z%`0tM8969xTS{DqokTodM@4ZI7}!iVeRUUh%zy@LCL-An==`a>>lm0y*!Xg(&R*Ac za7AS(Mdb9aCy~B;UEUGY)^T)sOJR)9@8;;LfxvKk*66w%kK5g_9CJzloNj+o-5}%! zPW6(=TN)_|=uo|{HFvXWAVjaCTTa-GO4sbKAMDESsTD8PB;FCzuzuTdtBt|eV8^># zx^7u8D&ZmCMtfPnvbaNO)SfN70^K>9ieIHgg*qnM8C_Sr5re`{)IX_S&(0YJ)dInh z=`ZHfm)m%bZT^yKwPcXjw&awfR)arI$fQ~hKyA*wK2Dmsa(KfTN(u3pZeEu+gVbqT zKs0rGGxa~m8LraPZ5wJo)zupZPcid#ZuezB?Ws8o1f}hF=zz7YbI#mq(nSe9{6{=m zs&%(>#9~o_CT_Ps#dPZ*|Fz`)Bm*jIqJ1cfQfdC?#Ajy!?323LA*)@I=+Wl(T=6#~ z))nuNp3#xr9M~mcsd;c+lQpELJS!=B_fFI_m_M=Q{f@{BuN$a4>z-U?l-X_IGuby) zaV>79%Y{6t#5gG6Dd|7Jj`WvZ>o#?U&6lwYs`Sb4B08?EuD3H0jM?vZRDAHeAX*uq zbMQFIOljpFCp8V@B`Yk&^b+Z1HU(Ye4U}up!t*F42DULP(vJs9Z#JAcDy*;!@|}$N zt+2Be^@PD1aV*N0!|Sh2$*IEeZl(I*JKIiSn|%8Ux=m?pwH4wkPomhPJW|Ul7~d)R zzw2TPx8zi^ZT_4bIQi`Zi&O3y=c^gG$Y>q=+svPK6lBh0=+x(ky^v{7Ar60)u<9x* zvin<}BV|+)UB>Su5!ZZ3gzA`o#GyW7Kg`te=zbTHd|R^JU6{_Z{;GWJ5G=4yzVa=Q zYBBfBwz{X4gAiPZ=`LK;4)Gv+w8k7xoBM9pHX~d3q5rk2kvq8zf9=O~cyLTvPwEDK z`gJoA<|*W`Q@xSz3Eb8$bM?SK3zt>BG?;0*)|KXa_Twr#M_c*a7MZ@iR^u_-h-P4I`Lm% zx?~(BPWBmGa*vT+U{EmSoJIdOSKssDtw;9s+TpMxj|))Yvxwl>fqy(bFp-#0US%xd zyIc&jt}0b`Oo8@aXCyYk=`X<(9uO3$n#MUZS7SwD9w?Q+DfH<3;?=~V-qud>n&qdJ z@tI*vUyw#UyTM&!CeAz6di`!S&EFJA29lmHoQABy$AZ}FHIODz%ORUHw36dCBBKXP z!&>zCBgxNx`pA0@-&KOzpF>)&S0~fts=k}=Owt+W^E(Q7@m?nG?y0$2ueHq9{QlY_|1 zC0>;Lt8nrxMT$OfL0Cql0tOj#zCR_sk`5!;BLHtH1d;4Cw#i?DO7@j>7~PzIN9}*I z5X}GAklQMsj<0eU!vc1r{+Ua@(!nMWfs|cWFLaeu{PpVnLeH|}J&3q0GrEb49lM@W z(38~%ONv_Yj41iu>}hjQt(Ov3mmZJCY3?V^q{_Y-D%z^Ih#67nUDrsz zj4hcFPf}e+bYYfsViH9yU@vvn;7KMao*####Mq2(*w1zu>E>fgrV2wIY(HLlmbFq$ zo$-5zJwd7A(A-Sd>|kRIO8Rb%RicRq@x#rVF@bo4h0Xh3p;=)2vkqNG`CC97rv)J2 z9$`zuqkDs5gerPx<6q=xD|M)uSzmU)YZVT2=64g9*pco~WgY^Ly?I-&kJPgEknZC9 ze}uhfK$F`NF03L_q*p0Y0)mQk6p#`{s?tf&xOQp@?)4 z351UHo_s5~&pvza@7#NT`9qSt@2s_EJ@d>nGZ{s&ViHNFOH&gRl8~$jS*PT=rLWtl zBI>;WB1PFSB_VO&Wa~prRp}arOTvzefuP}jtncw zo#N1(-tSPH5?YFzvX;;eaRmvjx%2ucbA(I7@>2GnixfKqjT)l8ES}Oo5e%?)T*wv| z7>ThN?1AZ>v@a<7e(T9Vu1Zf@@B6YFPN7@lwU1rXH+saU_n*^fbwicJuZ=hN7Z{bP zxTQVxQxwMP6phI7DZbrpiT0=IwH9w#Y*E+n*5Ou%Rmb3Xlbm`0ZtY?4UL3HV?@k5L zZevN@ZOe>}kVOgrkMrL6UCcMX)yrNr<_1Jzk3WqaWbc+A?PV2Me)PNEQ41^1jdI4X z6#;V0BqJ!hQv#Y1mY7QSl^bKIdU<)`ZTn)Xn@-=AUvJ)A&py2_f9|4eo_LhnSI27q zF|n->c}G|D`#xq@x&PNyN2?zypBZrzv@H%r~Rfl@Pb1Bu|ZtL_YG;)5*b*WzGnAyrt`Lr+_WY#^qeoM1NPaIa6? zMWJGhh$*Fs>%C|m<*@Q@YVKnF-XeW-S^Yr8yu$&e4U%q|M|n>@QBk{Oq}l!{G# zc0C+OMsU*h->!Pq&K*Y&&KIt=CJPuJHeVE!wsQryV6}tpF6+00;e!+G(RzK4#M;N% zKoyb&L{5!|@B!xjY83SjcSe_UOZixu`D*T#}5lG`+R$-^xkCkSTkVsBmgxeJR$wE4?12UMf8mKlf;qS zOSfPNB6bWFot}1YP0H=>wGU9WFp7r!{QH0I@skQt?^~bBW!f%f-Z*pHb`s9nH$>6| zW22-Wy$;-$Yu4Up0p~EGd8KD2`+vONq{i0rPR!nDRfiQqV=-Fg)b4+b6o$P(&hqs@ zeH6J6A$~fwH=UK<%o@K|r3Y71q`wSJ=iUvgDPJ|T*@7Fp_ACN+7qXV~tTLBzAlviK zk?{p)Yk#heHaaU2Niud-E$qQvcu?t0Hd;x-t~zSVHPjSTP{BE21`^i~_pUkiP_pXC zitKZHNr~p+o|x(y>D@+!YjJ{r6w{qL8}A4_)Vp-&+r*1pIzOG}$}HQbyvLn-n?eMy zDNPirrHahG4x<1eSE|1G$jNI%Ul66bC%=8Q7Vp+3^*B?+`5@fqC-q)wFM})At6EXs z+}1clq}RVTf-8+#v6^kbB%hi6<17fYyKS_@aYlqEr50GpQuEl)6wkC>NRC9sJ5)5H zAM^C?#!RW16TL|}`ZnqLA?tIIy+-HAe&N$px3sjO^71hY{nZ!Y_a)6+-rxkB38>p` z19nsB+w1~c51NZKPlPXI#jJQy7T8+%AzU+{OYs4`7E($GpFr|B51V*DGt~vetm%N3 zqJ}bnlmJ-@+{dw^)3oK8+!oN>@)q5;W>1Bn9ldthg{zt1d zKzCwX<2+exT;KSs`J#GK1}t;B_mXXc=+F%#73`?KkL^W?@h=my<~>3emBenw$NDMP zM}$ZT%%)w?*FL%hzb4E%uW}ue*cRx(>^1_{bYmrTb-coXY=?13&tE#hdt2zl*zk%3mOqG(5oY(lAI0W$tCUZ zz)gUoV%#8M`5nx;0HrJ^V9<|87apAf&LN&j^r`eFGLoFd8Bn|bU6XaEiTj(V-a0A6 z&!ZIcyCe>g`Vw#6n}dsGoS$sMjcHh{w0SlWify5UcH8etSd)ToiQdroeHPDJ(93*Q z?1m*#^r#_eKXlx1wzP$!e!cN113+{A)xr3ld@USn)B6x2zKF-!CrX(^3|nw;awcU} zm>DGMCxsl$5Ce*~v|56M9+-O9K59X4sMEZfQOkHeeCJ+2{GjXMC-R8%gy#rqvWJ1rv{Y5VN-0i zIX+?{ye{Xm>(2iyWAl8gqHDz;e1W;z`c=U&WvUEY7_H9sofqpYn(q?e@AhxYqt~)& zuN9cP^O$c&?vm`WhS6{3F~Dz`p_GGc2v zMG7Voqc>nb5JM^E$~|Q@K2qyEn-q-(3t}bV_}lyn6s*D!5vJH_ap3I(i(g>>=1%GX z{T6ro?~T;IkLivP3q9{y`l9zatIvIaOeg^|IgGYyB%j)`a^W$LSVq*`S#alr5BA;5 zn1Oth7p0MChO&oKEfY~erRiFn`fB$qpC|TGWv_D%dzQR5n|*Ri-aRn};uD(@W-cMy zA+Bj}{rt2SL{QQj12-k3P ztU;hU*M94cw5%R6Zlz@xHNJev9@&`1Cqlx4=7#rpG7UlttTQ7xwzPpDcYpo|ab+Ll zm#GV>s#(KH8Iv1PNWQ6^M_pqLKUtnr(GUY0EN;$3vG1-=!-g-#v&r0EZNoRhl#Dzj zI^$ZQ?e}L3t+vu0*}u!}M}gCK4%Z;ISM|KXA_1net@I}HnroI*!}}BzRVsPOf}+%3 zD^h>IbTUgh`$xIpbD{Wf%=V0`Ke6dMk0hanNZ|k`>i$rLn#ktN@cfm}8nkWZ##SL& zxyEZ1uIbmmAaAFLQN=mWXF6Pdf`TJ2PwJqxkW(Jw<5(r=~{t29|@(6vkHy zFdPm8DmsujLS_4tH=G3;p-36V{@z$;J$S0nue=}a5js7~KMLY{4cOnbXI!c*^!ZgL zSJO?B-$O+4)MevN|0pz z*(jVMX7^|;0Vw?B+{u130#Psl@s3-K$a!}Hr{^QGAP1(y*_WFS$V?NVSL|{%CX4jV z{G39=!lBQW&8>9hi*Mb{vPyop|JppDYx#r9WjIlbT65oJ%QRmvA3o#^=vcZ(aWG)Y z`l5X;{Fuhx)j)eV<=cH;ziNyc!*cd(x7y?gl7|TDyKfABWyzeP%KkQ4N=z?21-@mMznFfkg00$P>z6fQFp!!* zKXYh%Dph>Wu#E!zqS2@0il!&ctt@j|_lH6BQwF*YsZj|8u!V-R)7IY2)nM)!BYDrs zrXbo&F^~)F@cb_B_bm2-(BB)S1)BHZt*2V#9Y(2O+)6pSyG27nIEyxF5h*Gya5adC zGyIv+oqv7?u;`EVKP7SYDX8Vcyeq5MrgVxQ-^lqZS!>KLN-BnvoU_~+?N2V!5iyYiS@VW~)N^*vy zg#nDkKP@-^srO99N=nAm{Sf2!Gl8dLRY{4PU~7avhuO;SkuQZlQQXXijmLQ2HK7MvgnlPKo0jJBHxU~*Qcp&=UeSa?e~5dKgx4;8?L9PAj*KyU1yU-b z)-pagV6P$Q09s_H**;e6!*hzTm-svi%;*^+*G?6l^6K04Dr$DH%=7$WN|l!MDO0fuatAz z38H;26kG|$O_-ty;nyI%(Utx7H8IF6h)+!S9q{VCUNnA>(9U#ENUsD$B5%M6{Zryw z>E2aI8KZB)m#KwT1|FhG;2zB^{v6DGl*J`wNH&PioA*RdREifkHa{Yj;h%nx1(>-B z`i*;h(Dg*vt9nK4DVWen%BG8)E1G0Z$cTns@pu%d&frI=arTyoVzJ<6G?GwfrbQv^ zt83`ZMec$xs5m380k+4(^tHz5q1QW)T9zS{a-~YM-#iQ({MCum4qqYFAoUAlhlYe1 z0^+Qb_ez~IC-*Lhw0Me+{cyzil=e{GY#Zr%WKA(>eaQK#yQghnXi36apiF0r<5Q+a z70=GSBmufn?*D19pNJ@wY3*2>ZAwtYW*hXumGCVePF(iQZ(m_IvoZLJ{p_pp)Tua0Vw%4@;DFlDGeasN-&)76deTI5zcPrX1F|J^YspVnz~)~!k8bo(He_T{^T#!8Rcl5DuKre4CcP~ z6Pco`O1X-I_Lux5^0Tn{7>kuX-M*}B|BrNXBQHA$;ziWc*YBoJ(@2tAkHs{^v@|P0 zj(!}-UEXH3tq6>|DWgAJQB(|zMe;(nIEsl{I$VmoB!YGXeHXhn@)exws;TB{F7f3v z2+O-*#vgtxe)!`YYqT@*5=l5({GX?^7WA`OOzN`C*6n3?e$_Xiuhzqh%V?omxFfnk zc2U^N0I4dd~j zZH!d53~!8T`+#6LQSrqnKbbaZ^VTmE3=K+OLnAr3cr$N zT_v$R(`gh%ME;?tR{+bTUqvZ=Trt?*tB7#BjS}`9*+@g4@{6Ga$o$vZjhcHc?NsU| zCg)1QB<~v*blkg?BmU0jgeRic^#18dJc=~vq`U|4;3ZWm+zhHuOz$6JW+p%eP5 z7KfOKwv@M=aXg#=Ksv$WelWq^Zcm0JDhfG*S*<@Q_6W#*;!CG4vBLd>PMYDGAOpwF2DviPBw11&@nZ5On64553J0KLEQM#Lsh_OPtaBL{EY&^aR zMw+l)VJ#9j^EvN0EZRvX)aghvEyZL?B7M$D2kXZwD{vt2JU^d~PdsiVp|*SnHO)mA zcquC}UhYm63hMKj4R#+5Sy?Fl)vZ1gl%N@SX#1%2pLhfFW*gPND+vQ}F4aQ(n)sVP z1f6S}v3`W0M@RV<>iXL)~hQTR)}&?A0?sVlEtxc zolH(&{9($Am!Qe-i*?56Ws}!A^_22|R6^95k~()$Qn5yHm)-JT{lb_ZOw(N6##G~W%w8R48-bp%()&+@WQ}G zxEP|ofY5E{dmp`v+V!=-b1JtqTa!31nSL#6aqo;j5x|lKn0f>`I1a zBz~WE1?;7bwC2ZiUm3D}Rv$gY9h2v}5uHzJiaGJ3Sn@on5FPf=>!X{T=T&HI(UDQW zvoC}fL7;_)ekvD#vw0#o)|We@y4Rs69?z+sw1KXb`hl?0YoQ9$G=9X5YjRinBKDij z25&S$^N%Y&UzI)MaGNr87?j06OSa?)+&|=89VHR2oTau1;;h8*LIODW6=#BBzaa3E zGC}WemP?#k0c^RR<+j!}&g_B6fBxCz!T`5JNE3Je$1gW#(BoX9Df@FEim zDe<$WoQ_YU`)sq*P)gpWr;euHm(}Kx`5~sQ@9Qk}`yJtoJeM#OgZC-kH7?AGZ}oc4woHv^|wr z_m^Gw6JBqZD9EpwD2gnZj67fGiuPd-Ozq!6jdRWWnFelc;2DI%hUU+EQ$m789LmaQcxzdx8sa~aS9_J*NqQClR_h~sd#7~ zo(s+;K4+W&>wU2`%H4G05pnNzp4|z{E38E}J*KeqtJl}#iq$d|3E<;{;91e+*fVS{ z1UZ^q`=9x;(-Lp;I7Pr+AaY(lzF#kvHNE>nMj5u3ej#sCBR4LqYa4aFqm7U%uZaaD z^HkR_!7Dt!QzS*Ye$c&hbML18S_0gKgR9aWMF`G&e-^wi5*5wr()|)pe>`CvoYAu@PS`QEE1?@gH161<0zO#lv%Y-x=s98&fG12%$ zn-q-Ksx>qG2j-Q~h%Lv(%Jf3B@+`Fb?Ok<7%kEv`xFGss?S6WT1B%v?u@`reOo;k1 zQl?&a(4`f9kEwkp2;u@d#U^<9y;`^s`(D)S$53KiQQC0Gm&VTMGN|km{dKdZk8bNH zzYdz!;{E++Nsz4Y2c>QTUra_&M<@5cT{QS!ulIe1el$E>i|JohlsK*! zK%Fgg>&{jX2`&=is$EZhKxStPL>gn;jeicx3ll?qbHt_*e>w!x$@RlhTku;jkgQ$tY}P-ount%EM?BqlYw5ON?J>Xoj<@br$~ihAj`{lXvGkCP0{HC3{LJgS;~ zxHI`56Qv`EZG0RmYiwLX;j7ep>E~;*s)|(j8-SLjk9O5AyGyK{&2)Hto?+zN>Q17L zPES=|#Mq^aPHdHhY|4(#uNIfc&$&e3uQR8_fK(fgKG@}RX#5H^Tm)mXZ44Z1C2+asQCz6nA9=&Y0 zM=Yo81rnEk6D^Y9UALCT@4p8!OQYa}xqFdhwNbgP(bQbMK(Y8(UGnQFb?=&Ty%Nwd za-A|n_@Ar{5Wc32|6Hy=9?7X(oI?P8RtN6+i~Zekmy*WArN%ifkLTF%Qu@1L7y7|_Jo@LOs(=Q^i^t`WSrB7|wB)$9pv|pkZB zqe{660v^wie0mWH@&046s`RyYa$h1ZLrN5jhr=MoKZ_VSbCvONOKt=TiUahxT}{6K z#(cWV0DhgK{zDH3d~%Nt+a+C^kX$(39-t9`CXhkd#7*#7Hw_7$7x8c~_OzA33d0l4 z{duE}ct9GlEn06aM&G2(cle|8757@?7DSh0vsyN|kS5jghJ!Rikoftk5AFJEVq`fA zkumXfe)p~FkQta@=OzuQ zfv_@Ksjyi`k>K`SA5)?Z*o!ig$2&uYgd#LNhRQf#bFOjeOyR-Yc*yD`CJ=uBVqzO#@&%W@ILC1Z( zixy3pxmOgy_IA7?@#dmC92aw(@N3bSI+s5Zw(FLQthn?vv5XobK~peWX=~~*@U~8d zGH&IMJGVJU{i)?*FXEryU<7*r5`vkxoYFd#8_d3h z;%hRX*Vl>go1gtpUE>DoR_7h1dTZ;~v`TmK@C@j4Fbq!Fisig$Q#c*fJu0-cdTtFo zWE3PN@K|&fp~8$Ffl9rIW{rEn%pTJ~yj+jiI4iqxh#6DXnV^(}Oes;I1zamC zvh~I0&5?I6&mbIT0z!Lt zGeSKl2s}Zvb~$B>Q~zmxgaP#u{+s9y;1BG_)c9<8R8w5P5HbqkE^u;d{AsuyR2d|F zHe9)#bJawZ^f?GFl&s8TS+5Cx>mwuq-66KXiqIDa-aMC>%sJ#L6Yp6oXC*1Cw@1yw6Jfqtn|i&Zq}5+v1lVBPPV7aD@4qzr@oWkc(70>h$#3b3s5a-SsPfL`&$?BylY6`oX&UYeysjmhejpd+up(3pOusO;;s3^8G?x< z#jEe7c=n!bK?3DAgaU7EJPv#*XpB21+)QA715Nj}dj|8aK`H6Y`M?vbl(^zE@Ylqp z)4g|oetN_zNi73zCtj3tu$YI)Q0qBn34bR2TWlYPg7THH@*}#SGAS1iCZe#ZTG7CS zx>lb)GU`iwbIn4w9kTfG^n4JiaZ1J7zleg@~-=47>s%!oo zbMrJ&@O<_drKWHg-4J2L-2S;xHi`o?nJ{8}bQH!TiNn6$M4clFhBmAj!KVjyQK8+a z9IpT!gI$-Z;C1OC?N~ok`J2#ijro^9#{I(J@)qYH8T7!uwa5+#io>OiQ2AaFjsL_MkE8RO z3P(W6$Z{_X8ouxoHy;9X24rJn!amDb(o2{u1Lw~~OVg_vYM#suCmaPrcyB`d*P1(4 z^hA;|J@+2$e7O4FxZWEmLTpf3pBzU;Fs7Iq(Ke=a)hb&MAT;{F5;Qf5;G1dJKlA}w z;x54^yldDz`#Y2dBHXW%2({mdoMz~H;ox0qo=ssnCve+bD5w>7T%v&JTA<66bFxQB zxu&UV2?&{OH&HwC{>{=FEkevZ-rVtPo+;)v^O>FjS`h0z8QT6V+A3Fu5?FDB(RU2j z!PffA9|)gstA4HasCRYoiwK7=C`4Q#N0ap;K+d-`KIf63zPR#N4{_x7@8Z1@3CJG; z5EODC4&1>rUht24#>eU4qnl1+p5O(%4CX3(nBE&KoC=awRhg?{6otGB8M|bcg#I`X zC+76~OLwf^e|iibf>IKB>D5%%Ci4vQz_h;0Q;HuFPN-@EX`WM>F7}MyKt4D=ziF2N z8F+;D}G z{`<*pfhNN=`r2Of+=q@^m3~iE!RPKk)AyS2T&I}8F7wK8;azeW`P-0H4}LfU(r%*d z$n8#4-TtvDFJ1nXxh?}?8#<)!Y^U`ji!;6lOLGn=^KJpPDDp7M9q+ zT%k^$dgg7gJ2P)Odh;m$9SGv2Iv+59_Rhb1Au zZ(u4&NQHS<9yz2ajJP@F>{@#7DmZ_(9mv7D*IYh29# zA724{nlNxtKr|#c89CPq^;sElTP~_`9x0uHE3qvWzNoO*9y%tQ2w49FdK^n{xlqY% zo_%2EL zBHTdHOFhIHvK;+QToIr5g*!6^=&vd)S$$}aGEV&Pp-4H$@zz~48E`IQ#Y8*v(^yzU zzi$-l#=UNncqw+X+C1*{&WAAmT7lTA79;O~?#xHx=~Z0e&!|oj3v~)?HiFT_7eq3H z&IU~HRMbW6zU4ps6tIUk^h2e~bA`rBF%lWOtUeQN?18_|{v84SRoRl?4Juo7Z3SLl z`CDk?8#OH77Q1q7;6CH(HS4c7Ox8Rx8Rx{8-6H{oQNi)R_;!pmr+YPaeerG=GkL{z z#Z<|ZuZ8%R5^WH0|AbT@bqswRwv@^zVuHSt)6D`>>MNkxvI+Vjd}|w~L1G{OxI-3F zyJ_{R)PYm+MQ(5tD?Ru30qpsoHRw_eVqD`)qlU2Cb-N=bT5w$A!h0F*n=9n;n?WB*0_$ZENHb1>V5~_D~PZC2IO; zcWG0}^!*72WHUH73z2!mgR6vGtMLsF(W3D7>_B>9&=7I;mBZ@~XCdrzPu8=$TDMWt zIjZX!jwEm{bAJ$iIjAw;*o4BH6y8Ozkm92w{aWi98KM~JE9F%8^{H18L98K8Yh=7= zi&bLIRy=vn%?~uRj-%yxr&t@HR&O^K`0EQ%(9y2bbYl>xw_O88FLs0PByqQ!GKG76 zZ9m97kbklb7=oG+i#Sj(&l;-!L)zNPdW*Q?OolFpHoXnzrbH&poYUHDfE ziqNDI`qY>kOtcEO6xJ-}5`1WDFQ2U=*fAPCw4Ezkr_(=owmv~1DGI2DpA7JouB{4* zd?=3k=S ztSik>*xsZM__IKuh+i5mSueCP08YdvziseuNX;3?`u-J=FmG zv2R#T?UIWV?$|}m(bNO2HP$G#v*3cDj)VF9MzpEM&L%3<1)~;;3zS1USOv2^$qi%3 zpREvH)QK<248kUu|N7MXh>dR45HK3}cVpyk4JIYYprqCp9Doit@0~x2m5vu-TsjSb z8vf%NOd5PQPWGmu4&Mta)91g~q4-T81`7-nH*$3PQkMXLF7DQe67gF4_9cwyZ?`7~ zvV)p&9zDKqPBG!Z6jN`mh%@3z_1bsy6S&B4nTflOVf}&Nd*|e};5E^DIrY`g&aKZw z@!A?yTc}kIOGJd5afB8sD(=N4!tacdis*}hbS|Rs3uPx;F!|ut_=^g%Q9GZ`z=wJ~ zQ&T`&$;w~Kx#t%N*{4i$ofT>nDnYMaLTCAkbvXu#aVReS21LEAXC{B0Ar*7-loP+B zT<{EKE;DvsKp;804=r&#_Cu6R5=#N;Dw20?qhKI*vE$v%b(XT^oDZLpzr z?J3H0#RH;;Cl$S^Mj^+jtiW$fMJ|=Bw~}GAId$v}y93PJ{`G0whE>7{LkTzu#KI zLkTqbDd4*L;+RFD?c4junLSt#qvBbx|3n}nxQsa>Ld&3BAug~X{($Y;jeMP}t5Oxg zU3t3{7aZ5s&R6engqc_v{hCVW87^K;qj~gPx4kH@4n3_o&EWVjd!3Sk=HLL&l=f^Ea!=fII6n)QmfWT zDJPm27uh?LQ9wN7UVAy^HkT0vQKXgb>n!_O#4=~;fmQfE_Dt%^@g7-pp9b}ti3iEG zr#=_Htk=(OK9Kk&^SXa*#+A)?8|1R%(Dmyg7gG61o1x+~qnD>4$HwR;{X37R-)j^Z4`vQ2|cK!vi@Vzt~ifegR-_eWWiPp_7LD=CUFWx8phhm#W@Z~uXLk>w*#(mfn8bBpi}R z<98`-`vP3Hv`2>XS)RFTm+HMo3&BW^>=9+ODz{AIJv1xXa5nmia#rC-IZV$-UCjGS z2_M*KB$boPJRHa(e#ktuNj^(d%~d@UMH`*>!ezaM ztzB`yz0~x;1u-*1L7-4wL5lZ-|6QOUYe1{qp`+ry>2L z#=`@Q=nn7k#Ed?-hqDviDoKrW*Huv!G#&ia6tm&oa~j{*w)OXiC=^2mi>yCgIA};N zlc?`Lmono9Mk^9@H3)7(Uib#8lk0!?g%c!*pg43!tqoH!y7Ik)mg--km{HWDLhf$- z<{x;O#xcS7ex$ENn61DgU-5=NoA@2~fB?^9zWV^s3kNxy!DP&03;8)u)1WZfzg>7g zf1wPn82UbzS{9^8F_5MQdfL?yX$wE4Q@!{@Pb z9M;VI!6F#RN0VJU-=~mE-blIdh;pqGpk~?u`Qgp)dMwPfwDy|!0^qk5&j#pEZWOif zwEbKW`Sk1Zy*#}Nq=-y^^E`lfWT+6VUr)Tg!rkTV{xz!Oub(#w&jB!rVofh%CdI4jxVibb2j&E*3 zyvnD40zoo6{sI3h1O8i`zsW}YoXBZI5byx(e495SEsNe1$?sD6X#$Zdp}(&N(6*j^ z*0S^SrQ~D^nxZ7mNU)rXY>Re({R#d7()dKwtzee%#xX9%gYqT}l7?0-ztmjql>?lq zMz1w=dq8ws9)eKR{NMViRwyN+$-PP~+|b+lCSV|)al;2HA!yB1&kJoNf?IP-#sVqY2>W3F@BL(=58m#<% zV{V+X8CJjRecvQUapBs;TIJHg?4lYYTL0SMTh>4KF_fAeUami!50+a0VM86%TXi>OvCc~w>}0yUn(5gQT)a>iW@Y`_MnBYK5P0( z$}JJh@gqx%Lz_2s&_(Rg*r`!5-M>Pnv6fS-KaF1AVDL37J9uF6lff;!sDK; zScLfKT`j+4my!O1B{V_)`quGS7*V3o2ZTt9^+A&YbGo7I z+K*n@TAq7uvn>*NlKna_dWD4Wlgx9om1t$luRM@2`B%|K7t4%Vt`3e}7d66%1r8S3 zt5izHf?2RBLO;>qLRC=4_4Cc%y$1}CKK~Zg^c1jpY5ui&#juh$Fdh;B77gTfLrqN| zF?0sRaK55v;kei?id5<+ogQO}V(sGc%!(aDl4=bab}4XL)sSr zM|=2hSHFQ89k)HSeJ%hdE>%AliTMzkp=QuRpGa3r)3g^c7BsHhx53=DVi&z!DuOR@ z$}^0S&6tsaGyZrb6$?nOr$d^y)In5FKEZrtN?L-`yKeJ8(f5GQkL}FlU3lqdidKNn zCWyR!@{(nB;_}O;=+%lE<%-z#b3iai_%FM#V)Yj>XWp!c0Dqq(f}1GF?Oyx94VqGO zx{t?Iep!F_tVJgN{N+jbRBa4=RZ>0m)zl4k`-K>8P?@(B>#0a%SH?W3XC>3JJ+|Z7 zK9Fu>phHO)m*4J~X!wrBV9q9>I0|lD7L;a?{uHbV+dqFDu%tNEN7>!b7j(ubHx0~T`5T_7+7|(rS*4H`?Mbz` z7C&%L9R3Qj1IXHa7u}pYyl@6cRs52{n+q7$0pulp-P{V~ZN*fRsV}K-xtKMj8sbH_ z@08gWcU+A`D|zu8HWJ;+PbEcb<&& zH@sM>uB$>IrdYV2EUMYE1Ce6plKKy|t4MC|YU8JDB?$jMW1V4Mj90kK9Iox&8WL|1 z5Me&|tMZwDTO4aXs8ov!=)WqYfYvGz^Tr-UBFQ0AEL`Jp(%0Ryu`d#DdC$M`FE4ttv7>s>!kk@x#%eqwIp&60HQfY`gLv?)IW7IgLCVFLQa=+J~Jid(K6yMQk*pA=GuSjv$E07a7E=Ol{7&51A6@>>$saWvOiaY=JGW=C64Wk$g??4XIw* zC&x-jkxDk>tMjp=e5rlVDFg0I6IwvNilkY z$9lG&i?lKi837p-n&1;rwW14#lH;mFiVyF@p{0MEbxpahTKStk7SW9cVwy1jZ{=+{ zi@k3s2dupZlGx}E&bN)E`ZIN7c!)J*6wx#}-4L?GWnqH;O@_NWs$xqIm%SQIO8WIm z;1G=%X#&PEg&NyZBtkFl0Y}G>zvSa-+FG6D+HS*l6pGGgz<3L4d21;av^`u<0dxcE zxLWv83$0XXRq)H0O%06RWGC!ja>R7_b4@_piM|&kJGa&PPiC_Dl7Bx@fn!R8>hAt% zD$=zVl$RP-fPK7c#pK@=;~&EqclG0h6uUmS~Rpcx!tMx&av1=@Y@r`chZeywynQCN`mv{3OGTzpp zf<|QbexPi4a)W#(Q!dJ5L(>{rd-CJp%Xf394f~-^DDED5q z?6)?LDi!-%svlRF&f5S*x~ldnqDZ?d0amTsJthPO?7FWak`0qyz_4GX2G$Xj{MRZX z9{iZz9gHxDag5ETmtVU^EOtUyUCr3-kPX}Mnl&q-!x#PZHPkP}pRb0QMB<#^ zx39!0z$lrPA1t_u#V;tsgPMnNS1%K>Q0Kw4G-a+lOBgI;V2pJn_8TF`ZizZ_h*Nl% znv`54_Hc@YSHrx!R^D}uU~8Es_AiBFvC-sn3_9GP$1YXa>W!aLt)lFO?Ik&Tb}VAE z=Tn9R%@f5#-Bx4gfXH=4zlZ<@*_k;j-{i&hx}l{XkaI z7HB8&T_13jX9j!S$TIB?g9YnZQF7Tu#;|Y&-S>4OvXqJ!VS^D%?`|v*n8uMc55|s- z$lfda`Y!uy?8WV17^@(4zSYv7p#d=VCK<5wDerxx?Q!!LN*2TX10geLT;=eMP4k9x zdijk{iZ=py2#+w))?bZ;173xLc{Atf_y||;fk|iPPmPbUep)K28tL)G+PdN2BikHb zi;k*?YNQhf=$q!^%Yz^_Tpz#nh`L^3s3yxU9p-!(3FJj;@Dj^gWLbjQN^cJ_-o&4R z$=iHA3Wp8!N{p!<9g$R4SO`_m`XEi+xNKf<;8tGMl8j1%>2fu4!Ox}4{PVc}nBXr| zUPBmKY{_2Pyd>`_Dl;{a=k!c__9pj>1*gIQ_V7l*)?zKJUkH-m$rhW?NQ=Un{0XJf zA!f?J+SK-@AW$@hbgs)^swHh^59#i{MZb$$zVo9gvMI@_tpD5Ys0!M~G0D6RO}H<5 z#1`Q)D7^Jgn}K#YLjqVo(6&{UAhQGd;LiNh4?Czir`>iP-W?Q8+Vj?olvb!B{QR1)d_qLcfzRr zJvg?o2r5Fh9ef#Ld!xkN#LO$nE9H1M16io7A^fpBj+`lflY#WXB3tE{>hP&q6Q)aRaYYG=h4iNWc zo5x593^O zAManTu+y9&J;L15+tBSZmbx@6#btxF9I<=pG<)uNRjqX}siyR&6JFQy=Xt)ojZ#=b zXv;o%0A>6HGZAZBHv-VG0DFBG_4ef0?zIOR!DXwuhR|IswY~C2*Dntn_Q!)Ig#b)3gr!954i1eK-S5cz#WiuQhlQ0GCw=7TeKSzuZADOAK zhkXsY!1q!75hNWH0_{%rFOU#%NsR6#$R&qkYq@T1is`w%6h$j;V?QN0Ej%*EO)wxd z1J52g7+VIi&>fxe4tj87;~e^oBpb<_CPkS5Je&R72X;s;AmRp~QKPogdqiQRTH!|j zA7gJB7iHUZ4;vsz2}q};DBaCSgCHPE34*jDDP4|;bPfne4yAN=cL>OU(%nPXPy@rv zd*Xe0U*6B}|Ka^S=bUlGK6b3N_HlR0nYHMF0`ikS03tM#FMr^jz!(!N-uXiL!n#R8 z+PM)0Lv!p6a8fvHtElp%AUZ7qO8vC6LIFcK| zSME9SCK1SJ?Hq|n$vJcgmJJy~#JZG6&){D@2FpR^cDxFaumAB`fiLpBb?FTBumAc* zex|$!4}>jilex=^4e=}nH&2938QdH{K!C$}#VW)6c9I%9gcK!bX!a?nu_ z?#)Ao#@iX=JQn;0tMmH7caW}uDJfBnSd?Kt&(4sd6iglR_aSJlzF0*bQe@v2l(MbE zT~26QlEXQpW`IPixx~ye$jpQ0!ip$gXXPQL+t7ojR8}Ps_^bVg^k&i@Xe>jkgnJm2 zWSUR-@Rlosl%4bKdl_IE1&5CBUIv;QpO^3BkQaYM(axJ0x;}FEy{l(a%Nhda z8NDsK-S(snAP{M$tAVR75gBZjs^srK1WHps{c+4!#PGi6qmCpt>E5%Iu=TI^XM-P2 z_C(ONd;{Avm*ZgV?J;8r4`BIevBdr7O}$U_<2UYbj)D?i4PTwTnUfFiBV4HvSfmC( zb!G-v+r7}Z~yfuUGeL4$7&PH5l7jky%`6r)nB%taZ)CX!^6kF5HP~@wvx8TJIk|y4NLq%75yj2 zw_XCOn4(I=7k6>@7+K42XZz}XG6aVl_H4!gRGX+EO7qfr%vD(PJHbU9qx_qBLO$-J>0C?Y&M3`bAWB*%l@maF@xQf^}C>KIf}h(kxrw$&$*%Zf(_XuMzB zKt4%rMQr8R*C4Fcbl=vW6Edd~h5_C;Rk(J#ec)IXxf|8;pT(OM&SqTAcul2s97caT~nci zhrqk|Ihj+_iy41Va$;^#LotBu6ebb#l_)PkJ-$MD{T^@DC_tBs6hrq*Mic4~&!O20 zITQR;w;8dBp2YadkZ4B2g%zcoOTH)3?Ludt!`4zZkk%~6E^-*UTC)=_as;gTIW3+j z$BRV-OwhDT_YCE%s+y=Zd-tHegj$@?Se|v0$ZIW4E1@F%Mr~U!%vQq8 zQoQ8C>DgX!9&1NxY;}G6Kn!RC-!n&?GwAq1c;hO>qHU{@F0G}ExbaLuBS6JPoLs5C zf#1rIYF6)+0(nll`keyx2Yr>FJQ+TXi6BI@pU~Xym?UCacT0w6{J=5bq-v80?rOS2 zJ6{BUf|YnWY+0W%DG1!GO!#^H-f`&z9)f&NWk^9p?djc8GHYQ`A_v%Q*{$P9^iW17 z*dmeC!mExzc93nZFBN0_(N2tRYQ|D@R+Q*2=<;LyF;ALSZ9u~#Wsn1z2bQ*%w1ad- zW7I7#^W_1N!=L|I$bjvBBaboqPqM=&dymevA&)|3cdmRYN!*WwXpdIaB&0{K7G3W zY|5?K#YvhC@vXMcZo+sjuDuwzKS}_@#;5=1SiDr3pAy>NxnGL zjXtcAzU8f*;&o#j=+ltKBf%X~XFMBzY(rx3jY7t90#I5Jc^W%q&N3n^eK0QlaY}`G zcy21kj(_guDaGQJF%IVCczzv)Zc)T=8ig0-_#Fq$POqY(exWF?EM}OYp=z3^5#N zV2S?NA7I+z0L}owY&s(Q_T*+$S|c&&o=FG)zgZSWsHXm;51J z{r+nx-9PfoUl`*J1*G59O|b3+s5!4h6eNR<{d6Lg>Dk+G%d@SwVequt$3UJe_5Y6)nPvq04cU!M9tDrnGuUL3OXG67Oajh!_ci z?A`eGPmb&NAYXmZe>ft$iB0wfYBsQm4FsYM1ZTyne}RPK;eZ;J1=)9dfvV!43C3j_ zrTP;oO>0Pa)>bImpPL;98|hIdBiVdn+}@~c-mb7n5#V$=E2}GPJ(>Q_bE9hyPg*!~ zw^)B4(Y}9NZg^~MVG|k9eO`>4x55a)1fvKss35=rXvy5yWd3UT>tBcY_YA{}3}}&TOj5^nTd!Hf00|Gp1_4IVbTWhTg-%ha5Kw;lXF7o| zHgg1o>FGk)7m^himxHBa8X6 zz-bh`-b$U_;e#y)Ipm_~oGR)kaXTVnr5aa-)<0`BuN#<&ui)yP3R<+({JEB?u@6`a z!iRMZyN6A)7VQjlaJ8bTV=jAs$IwM+*ifJyq*<|2v7}j|5=DF=^Y=>52gG=~;86LW zQVp`Ow{mI6r?|1VWZ~t?>}6Gc^|jiU6}+XMd86oH^$~Iw&;1GoK%{~RaX#Xu&rkc; zs*bh+6rmtUYtF3-_t1Ia1lsjaHzX3I1ypfefUQ!I)~e7q86$OO04RG*WPkm8URmD) zp7wW8P(NIzOZwAM^8yama)N>BgUPS5Ya#_ zt57x--X7lNwRt{8mj!JfMn(eX>S45aP#cVt7pE5rF=Xe&aQ!{Lqh#lB0BEqG{orMV z8PkwX;1;ytozw7hF$cHDN1KX&Z|{}ghAF4q%et!^XxXZ>0d=NDrThjc{U2MDS2&jl zyWRv`fe9x;H8Mxl=-~eSP{licnrgh!>OzW!LVyf?gMyc;E1d{&Ucw2{Un|+?uRaoq zU>gC@j%4uI%&EIxxg`8jv}zq^7d?mv$u zb!~eSaJncJa~A-fnlQJt_SBcPnPh-a<`YwlMQ5ftC{gB?jEQ;Xd9Syn_`HyE>`4Gh z+LODf*TglNrkFT|2~f1wh^|uKyHP^)w3q2Daj9iwjopY;XgU! z?>7EyzXZwn3;=`p5&Qm501}ld8v_ZIkpVh9nS@Dkl_x`JkwPwkG$|lRZ4k*D1xMV!u+JK39FTG5{Pv8jhtX9><2s5J$cs35JQDIK_wmv zas3sdOOqVayG|jz{lDVv_*gtavR0yv(!*QRV`BQ}da_pcp(`W@>yLV^_D3$X6gFh5g} z2rIA*{o}-VYE?463eoSF6wbAmmX6K&7<(U@-^`T3DrmSp=H-BCIj^ z`WqWYCWNq~?(STuh5i?|>Bg55J9 z?L22(yypPMc{m3OBbh4FqAla!@YZ6icUJ`);WZTXp(dFFDuDh z7!;)xf_Y`$LvF4ZX&AF5FZ;pv6yB-Mo0MQq=_k-#2&ar28DMlx~tV~1VfV|Kl zVV8D+X)*YO?J{@|${8J1|Ipwy?nLl6T?2H)H(U=HoR-u@V+EP%L-7zWAO@o(3PFB3 z5|i=w!29X%!iTDmMEPM2@5xD;u$L!BCd`#G(?jltWVcBwq(oMr>fPP!Q zpV~}psV9((J+uD$mj>k%RK>cRQcgY~L&J%>Yzxk?X}(fnnVP+sJ&?JFt-5;-2N7dX zIT~k;G#VGw10K}?zkz{#^7VhGohbki0Rd7L9*1>OlFGYBz{A}8@PZzd>~GG0vcsh_ zN^ER@e9`!#e*%cgbIK8S1%bv;vFt~%tjB$aFKw9xNb*F`6b84Z8zH^ay$GYYE0rNU zy0EWN^7(|LX$AaiE*8^33UQCw8IqKhr}Cr&1ip93Q4M=6ZN<-AAQ?tLYH+Ph9}S`}-Wx3P zt&vZmk>Tr=whsv|meSss>FI|&Kv!l4*kKym4OQpNtON{bs7q6aK)jp}o;BZ*$3Fep z@kaj$uY-2p|Hd=o*py)qY`EDyUieLR8JYXUt(Zyf?LQ~VBN@z6k+q4Kh5G;wb4|z* zNu7L@r@;y{WGCFq&Clok-2$b*O&#DbIh|Qs#@*bvp3Ehg}0&-5dN(*(2 z6nEpkwt37BG{*oR@2zSY*wZnu3R~BM4N)0=+-D=%02C{7XEh-)a)c(P1{f+=bnp!j zi-LF-07SLZr#W(MXN>q-+tI^3PZgl!O<`#Rv+lkdG}?QDx=DldXQ;qC_{m6n>=TN8 z8JPdKxsy%@7aODNw1E}%cq56N2+*@Ai6)EaLz})27y<&iM8j#2GPs|Y5jV`**e)Cv z2WGg1Ng2LRx%x+Y6Ic_`o4-E}?vnSpIFS`AiR{Me0W7cJ)!$z2WB=bFS=^|k-hF&P zpyE%N|H{W#83tmb|0qz9qI@%O?F#6!>4}*Ploe@WGt_6=KkT4OD0OA6qK_Kd%FhGpH_6S--J- zsvtI?sy?9^UlKpsUHUrQ`kdK$lNmGfwO<;MZyMh6+_9_`&%E3S2sll~&bpYE^{82N zsOL)?KN3FR`)iJ_LgXuK;5QW>(I3BShzDnDhjJmHjzW1kNL-6VD&nqi$~NSghNh!kGP` zS$Mg7WO2uWB>^SH`MvDr#)8A19QvmRFK<1x(nQkS1{Pl(~ zg#;y$gz0_tO{gp0`fJQ~BrF4Ly!xYVG0fT67In(oalhvjc5-I+8!7wGI=#v>T%8ut z#|GwXGeh6SNIBO(rSip{!B>!?kNrs{lV$q>R+2EOf*{)93jO>i0{$Hu#eyTFVN)U( zhtfekfH&8!v3?Q$O5YD}4SdqAqC67M-Cw1BLMT&X`^{H3Upx|AU7l6IhEWelJ0W49mTmxwv{{Ysy82i&8wvn-3Jn_j>qwX*7ni_kPUdX6fys9uP zqBcyui=m5WG_PBX1q`ngtJ2gFEX*}=Nu!zR@7Ei>_B+0M+kAh$<9R<*K+F`}=*;@| z1y?%loD{o9K6m_1TTW6(s3qH1y?~zk4H^B_U@B=>JJg{f_ry zt~&Gm!T9`buYT*3{GWgPFXrf<@w%G6zl_+Gb-Eoib7vM%>>nY2194N^&InVvtdwN@ zGv9Lgc>fcosi|4`Ird)e*Y{pBrz&cwHn5%W-K0qRuNwmRT>pLW@2IZVW->!A9tw^0IMT7%UF z##5S6AHq%^zAi~48XZBKDSb56+3^J0DW-!#l`r44YENe5wqyVPul zL=v6jgXId5T??P7Zxn2xb~yzI)1K|T(SbE9CHf!C_h?xK^e!{AxLo!;a+2&A_8P!l z-!)Mvrg+0?sp|tNMp|cc?FQN`=Z?oQYX&!7^S=bosbXGjZZSutPmSW&yJ?)oaX9#plo&=EL}2+AmwTDo=DFn&ATW(pkrwGhz7>)<7=dgCCgexWLQaFBBuU z;+{1DWo8Uj$9ss7q}kpsK`6YC|8N?FbPt{7I%G#b{?}SYZ(>~?b=JQ`5`x5&-Rfp! zN~kR(ayft+#Mdc@OUozkSU7wwj$nROmiHcs6hIidXdb$Zf5v-2+GDP#ux@3XM}?l; zN|T==ecL4fNPW~Oj~ryCr`C`<4FV1xm%w$UQwNA8vtEcT>pKad5+F<*Kh71nsW=s4 z#CjO2v*V(mRdCN{K6?d?q=m$m9Z?RWbyP0PsNNY`ex+KpwPK|*xZbnNbwC=tbXSqc zkCZWp?p}ViDZp(eprGafc)>t>fDo6Shp6m+v9PmiN$z*(2YtylZDYTJ(Kk*mSRtt{ z(vs#ZE%u+1Fn;m#cun)CLGaH+@UB z#lyOO3_P}caN-_@?y087^212-g`Jn>lXN>tBnui7z z2C`c*iJQI zk&*IwW&au6b)#b?wopnO>Sdj7_yUEub;v%?+YKNkdwNPAO;NTV) zUwK;T7#mZzolRMyQjbxYdgmc5EV>fuxbp4nI~9iehP|ZhO7W)?I-4`=xGMAD-nG)a zJwOm6d0mP@o}WOWIEtd|vf>x^ol_)(?EB*SNknx>(kNUOLr^n)WR_%`XzZl zi#++9Ju3E}`WB46rowB!oXR~nf#4wpd#j)u&~{=Gu?0}nJP?KnF3o!jNRUcZ#`{{! zGyo*Oa*e}Fcmsbsb;q=2*39HyQ%J?~+AEwywSUW@a`|_E<3H@m3Q-lB!U;JWDrfZV zDK1@Ifrix)Wrwi*@I+0PEO31EhfO~9Hp7$Yi#H!t?-J3`L*<~^C|OoR z^Lin;DQHoYGwqi}P5=0>%uOXq+L2Ft!!x?|wlDmDmF7he1GQVVIpqM*D-!!e9AcgK z>~e*pgI@G3qOIrX2=*%>wSQa@1)zrZ879W7%wCHfp1j^gu0XKEhd}@~nVHH%khP5}ig;a;7%HW`;$i(Z)F-O& zo(8^T76eRH0c5E$N(>ueuRcHpM4kdNpMoe#eBYas6*$a@lQdj7T8Xlj)^5(gx>zJA zC*prHMZjk%u0byipqIJ5>!U9u;A&`VNrlPJ17>H|{4&otCePqqV`ukJXljir+m%Db zup0;mk6;u!E#s~9HxYShps%}pJbATQVs7Eyok7Lj;8{r48GG1RA@FC?T+JLKOg8z6!(VO_clOO7b z;uewFi!k4qQ+Y$;;*-7=9o;GTsD!!%5C!)alxOji8hu%FAO7Njgqn};rE(W|9kO7Y z_4~`G8Ol(I#~y>`=}Gq&Zu)>b#*Ep@NtS|4N`ZV=Fq*q-g!{+{NWsU2yG}jBH{oui z*)jN(zAL?-(dz9=4OeDlHB8HaUlKF@+98&?l-#yYLBUStPSPUW9Pa?^IDT+1>OxNfdBd@w03aH_Zm;Nov}pTPP=K%rW2 z&QktSx7{$)c*vyrgK~Z7y?1;^hxf>I@l#D#<{d?*QgJad#H7;?oNwa!Jo)Prd4W&t z1of1`I^Zy_)+3&_ ziZ;!dC6B_VfXyeBnNOfrMH0O}g{CnZAn#YG12-F5h+4RwNz6pPkGRo5%gFJ3bAq6@ z2`4c#hiZ7xgr%x$H<&Fg$b!UvQC!0Efa|RRi=rDzqU}h9_KL8_vSj%IjCV`1F}p|V zww-q#zm;&~E(ciyLG_8g1&!w~{VH!oG@F1b$mKR2n){GP_t#`hGRw>FKbWIJw%Ohp zHjd?ATXSL#k|k=GMzRJUK$`-myap2aj*edDOnFT zJ7Xlg)aO^CfG$qaZ{IU2c>9t~>UO`4`Z;zN#rh&A)eFJJ(tNmeR$7b8QW%>=LcklX z1hdi>jo0IdJLmJ(%pi+psGdQXzMsrxk$VQFjWodwWmY@sklu&6?GPo6@+UX?7z2m} z^qdlo*7w*}^erFU{b|W7RE;oW$(}TtdA#mhGoh@%{_go9=rfWxsd9t^!B2L&_pcpQ zIR<mg-s;)3dnUhlGbPGi)iGb2#2|LSg)mh}8&gowo@kTo^h7 zuBB)GOYTF9jI80tW$FMY>P#s?-ihF^yIy%-R{#Q_U=NMI?=pL)CG;>M~a8tNxqc;~C)7Lg>xfNDP z{$_LMHqqM*SfT%W9T-)MNM=bxI^yg#16fW}n##+jLXCCqX1vrouXOyP)U7I(xF=6s z7;^B1@i#%PPPOZwmQ_`?sKA=)u8iqG>+QLp)bv>z9*M^5psi(M1w4q=7|~8By-iwR z%G@Y1Abq9g)N2KZ?p6ugRQ>=x$sj}@1vhp z;Q}Yc4i4My4dFJL@^20Nj`w|NV!PM*hNtV;(YE9G66nIHm=o3p`EDusJj<%vCc3nH zaX#Ia!mY!aFT+Rqx=Z}MZd^neXtM0321vTJZqx=occ*#b{n)NPUJPCMwIp-41ENZg zN_A@wX)RWM$t^lqE-gF+eqktCLrdfz@sWKp!oljfJ|n!Dr*;A{%h#QkBdg-BGo77u z3Uw{J-r#j-{FvYBCPa74)m7TIhDVI-Y`1pHym1zsq;EMgT0V8?>Zt$PfvX?TN~JGr zvFSFZ$ODS8K&xL(lkzDGK=ViTYaq~b<=a5aMxDOnR8wtCYY@r^Z!zqBfMOlkO@q!m zG@RV?hYE?5;fi_+C7JZWyn&LRDs#>PY5OVxM4Z{0+Icd?ewEpc;yk+7xHg|DAi(*+ zIk`82`GSf@>nTpcBY3b>Fe6V;s8raZML{)M)-yk7xn6Ndnmw%1Z|>)hFIygfLMeNu zmA1YR(0|F|Q}6XTmXHN)x0`f4DXGn6y-#J|49s_oWF2$4C5kFCkc(r9%7n7`Z+ha) zdcg8uyp1s=DtB8~0|Ym1Uw?Lr)M!$)C-IAPLo9>4YEkkBDS>Or|q#!XIy$;IuW_@-ew$sw}7K`g}L_rq~RL zBp~G))w@``cQSmvE2UjBblZ=?a!gR!;&U&BLAAB}h~RSzL%ZbU5Zj0E7`@&QzFhN9 zf4RrC`$~G;UNo2 zPU)rh6aAlI5EC0tTK)Ci`K4saT}A%vll@a2xsLcLN>D|XA3+b`8ELKW*To6B6 zqRYEWx=UvsZV<75m1TKJVg7Sz;>o67{mi6LzuLtHiQ}*__Ri?9wtR_N_0?S4Q7cfl zgo3b4w*FTjx#S)H`Q?OqYurB8%rQX#Nj)K@)a*g)h`50fhX7$mlh|x{y8|3+{LZ*a zD5qk)=?QlSr6>0J5Zy>tyfDK{>l;Eh9&o)_KJTonmYVkR8M-#!G#&ydbF%RLoGt5V zAx2)Wd0Es%VmbJAgt4}d-rq3W+c6Ij-}^@5sJ%`B`D}${eb=g9&YEOC13%SB=k1es zT~ibN&lCoGTnj^-4eR}TM{Ct*=}vX!`NdLqp3O{abomZ_57ZF93ojjas`!RCA0^o^ zT&w&n#Wao@Psc-H<(Xg%?1&PHgM$axcOf6ya+w)6`b5hg;QYAWV8v9bi6%d&z;WJ1 zhHHsL44r$Rk*G*zwa%ZA>Fydn&Hzt26HPkcmHzfsh0&$U$t&F1{*qS;uAe2Xw_w`W zU9WE9kl5hZ{*vRJlSg8!mx_?`!jwzeu&C08;oh>=E3rW{f07t@hxi$R+~P~7TuhKx zcSek)VwxOpJ=uwvOpqBgGSJ~Ud!0Dz9RAP;Vb?@(`s;4$i&^SO@=0}=YjDi~y+>d< zF6UA_fM)>79v=z!MZZ2FN7CPszrPUu4#%tiel5eC++GQT$DlBYDXkvuG?GVZcAWs` zMq))B`Vzx`GD2r$dq*+R*}vZ8-mD{%thTVb%g4VKCo2xbTxz%DSByN9&ot2u03k=n7>nqVpQ zyfqlFefxDEY?1N$v$r;!?+DPj^YV=PJsdL>_Z!B`q)ocV1kIPd<%hUB-!n$iRt6n> z-n5c>Tu{>Q^Wcz5gD%1;SDYkaokihf%-caQ zhK5Ml*QS0!ds6e5&j?(Y4bLyDPkl_t!tRooczegRrdodCiT8|pRqGxLpR3SZC26=g z1;%yP4cr;fvpZMQeJdD+1#OHVg1T8@41!95KCaK!cXxC5sbK-%3A>qUd%AgfOi&;wdwk)TP)n)Y*EBiLWFf(_fhv498iY{thYVCDkvw&vk zPh~r;?!S(oKVE*?#l$BU>)7d-7h*p&o$n}m8QC2`ZleiQZbj|uG35H#>tTj!I#%3; z8A@(2r89!8UtIw@>{D=Mg{BK z0Q|TL1$4xv>$j8lzOVEcy5dEjymFxX=tJ4m51>~x>E$lYI_np;iy8fxxJ!pdDtV_cz?$&yb|b$gv~!H6f0wd z@yV&~lw5vy$|e<8`(q0_s~YAMEcP9j;qDIfWzEbjO0_VjSpj1BJ$@8|WFqSF!2MEa z(3htVRN&Qq_=W>hxGj5^Yl~w9MZ@#%Mc{zqJHo3%kTvKr576~vM#Nh_GcHEsOCXEs zeIxShNX$=TuR5OPFo?0e!PY91(+KJASO5J`tCCSdx5~ctTTk%6Xd9b;_)tyY?xxQ_ zy?f~Ysn$Vu@a#DXksDL4vi7~U%}G#mtUILn`g@m7wjXb62PVkw*V5GDP7*pGxZCSg zpYmg7$n?4@oCG8Sa?(C#il3lUr$Bp={cHD~Oe;jV4vK0SH$Jp;J03XSH+z-V&DZYD zZ38rpk~!y+TK*EUMYjs2TvFP*HA7MLXw^MaQX0Vie-P?U9exSig<$It%YK@6sd`IS z3NC=Cu~>zQ%EC}osS2_HM&w8oRq?1U_u`vDFyS*m?X!xwY`KChCIM|wG!Cf^gGRI@ zwF+e40EmyYHx%Y&gGf>gc7LKhojV6Wp?putFG_fU4qgs5wA@9$E`qbCd3Vcpn(e13Cj+qx7y8a zBE*M4dQ{V(lBlpmZKLz*4@nKQ?uL@3$9cl82?pabjNISdFp8bGV?BcJe3lsgt>vCf9+EN5UG>*AZQ!~5GkS*Ru~>;f_k`1kJ^y^KmO4JcSHoS)AM@8M zI!|DWU7T&83#Gt@Js}PR0QdMj3o~}`q4};Xn&NM@nARo5>k{+|MH87zK6noxEPVWc z=St{ot`({nQzN7p+{L|qGu07V{O+w$K>u2S<5L%rG<(r*`aUe9+YWaK#YjZg*3_1o zfdsLkIsd~+K&?E{k@we;TIcd&>iN>K^Ev!u7Sl;;z2D~bM1(lAo4rC%9f9QO4Tn}8 zV2RwMoD0fK{vodilnN;sFPjbk^^)bb({?@4cLO;jXg40yLS< zdgcu9F77w-p4_!Z-WmKR-3NjR0yp}QidF=G2_$ezD~la8iDlWDBCX*ckyvy>4BgMh&(^AG zBfVj!4n)etz3;^?u&iE0?!#Q2R>5p|D15tG@;CZ7_Iv@DefN`EMVe3MXILm|A|>3O zgIe$UCl_!D4^y~+OQ7_=!ZJnUg87^fAcE^PVad3t@6!1GeFn<;L8O)QKF5iQnt)y_ zs3fOl?(h?YCF!{gkYNRAks$6|_7~qK@nVaw-ImM%01a%$#dbi4v3~g*U(|{|z;$HV zFozPGuhnlGolK8*DlR~8s%0xDf{k^x-Jrr8s6=zk6v`1!k+p!fb1`XOzntmh#rE`e zbR9QOO~k^E8>vyKwWjL+8pTCG`7t~r~`n>VArC~Ntt_I1fxqc@>@;XSQ z+jLR3k;93Uh$fUs%rLL95V}l0LLw$)XX+cE{B9A73F?#$JFan+Y1;$1Pe_m>_Wkwu z6F1jpo{Rb}-qA^n*w5a(-l>yjBL#VC$*w#mpZOFC&B^RIYA3Ox+HGL$!Z*k?c?Twm zJ>N7R$=c^0UpR+*xbUq)bC%Rc@L75m=-hSV^@M>G`NxSjqhJ{&=@tVtl7#E6eA9e` z$1-^wSoduiQ~l~|7qqjZga`uEV0mMUX_y0p!jcORRk}kR5=2J1FpydJ{;loi?TI*( zdsvtDDRI@^RS_^0ARJv(T6oZ1zS}m;>u5lNuEUP}WIi+!C>EaE!{^6e`*Ljg3VJug32swuZEf&;iDDx6aE^87S9EY%s$ z;MR_K4 zMdf6t5EBuqOv)$)QDEZ$BbH&f~+HOL^G9Fz13*6iBZWF`D;LqS@dI*)~vfUV^ z(|0eKOXoIioS;a~vJ&3z(e1ZF0@f1*U(PFRPP0e z4vvaPVD}5tWoPm1h4sDTCg(+H)JK$4$IfQ@9T%nIoMlI@q)*plri}hzZiVCe8E92xUHN0j&+-x(zclP{ugWg?ZRQ!6Nj>MjSMPqU}s` z0*F_kk^Xp&(^;sBmzq#k+R7wgLhx)mqDoV97Eq(J6N6Pw6kEal8Cl2fHP(wX8#Y_q z;h)fx#$#elg>MV-SWt*t-JB{9p&h&WZ9)556XRb6&*9`A*H>6($)U>kt^1<^st0ouYh5Zvn224F=Hf@syL9PeKP{U_ ztTRo@S|V#0SRVkdP;pI9MzCq`iR~gcf@m( z!XcW^W)Tnh4plWD;`l41Hk!&G;PR#?7%ulAv}T+dL$#VRsM6##J*b~rhh7if^1zmH zBxSBjYbE?#|55v@o1tUNRX0PNT{(Ek3jC}q1I1=-qi#H0u_}xU z&aycKj%F95P~~^@5nkt;0#U7kTpzH+hLa<|IjBgdJ{&pR3^{}$?u`YS)#3(r?tp%j zO@fuK#|1Cn-tKFwy$k&qLs$t;3%Ya#r9}_=iS@aebiy#GNJ!SQKxeY6@TRyz!qc6^ zsEVC89`6@3QO+*XtTe08`Hs0dMv!sGcMeC|{JkDKeCLyrjD?2E3$`FViKd`ZoJeo$ms04UzA)hBpj6eqOqjrVstPbv?d#bMw@h zd|(n9b@~L>ee4-IxXe%1Q|aJXSvMRr0GPiUg@;v27}J3dubi6#)IMf8vLY!&%^J+J z647;>JWN*0JlkHj9gy0$-ghi#W(LDd{TY=PMGr(JhZ<7j!0#Ery;+VHTDPUu1=CRo zxfJTr_bqg=C)Ip?wi!Si+~oIOGWeo0A3*kKU}kzK`jKg1`S5kiaVl$C4A)%t&{w7q z$@YT_>xrpyNIxZaz9Tx~6+Ktn9<+&kCF_b~;1(c`0}A$>w%pC6s$`boQgpb_r@zb zrq|wSm=I<Pduk-Vdkmmr^|Ms*fdV08L9r1Idi` z@%{B5M!H|X_Q5ADb}uWqA3>qvk4O-8j=(`0iG<3ZB^+PMCZ{gEGU+ijrHTaAEICam zi*e;9f0L2GAcoiF+&g&kE5Aongghv^`DSt;ILSURc4K*cqQP@-xEBH{M=sx9c&^3j3WQ1cnVbR(sNu>&w<`U=WXAMU1w{xZ1h z>$YCh0$Ptx3`;JbjSw)jip3a=I^)M5<7((U@nFxF0J7d=Aj5gu0R%w4*YyTH_+p2) zK6qc~=&5VMfTcuA@N6A`eKnw9{1h)q1hyz;I_VYU} zhHZDCA7e*y#M+L3#@cs&-*TE+;{dwd0#tfO;S1@(Z0>T^XG({kei4tR%h*-UB<^GdN9ciZLVXXbV^| zGM6rx#E)r?0=qg1Eb-=FbiSYy&(?v|L$R2^cIf;j*Du3_N!%dFY()ClpqO@3)b!l> z99SXONY+~O z!tFj=nE~wuRO}DdT3wJ}?BPGI>OolJpuMnVSmcoZyzJn1`l+5Z*67|_i%<6Wr-yiC zm3#G~8GwGr&GGl$2joOV=<&o|Nrf5&K=Z7g8q4q@2?xmi4nv4NRZayazLL~b8 zd{zgYUj!JxI4ORy&cgZgM%E?5uQp|l!rj7TQGMioGTEao7Dd!`tBZJ9qsK+`#x1H{hYq=>*SMfbTf`kt#~-m>uo!L& zajegY2~Q(MXS`0nLL!5CpNr_3(8cJ3SNeJ#?z{= zLq)qa?ih_B;};1KFy*BrJFLvRzD8ku{gREb0_WC(m_VA8*b7|rRQt^ zw^|lSatC^zZUnFEtE&}X0OnZPI8wagm34YPCd(kd3e0c}4Y_?Sc>i z!`VVtWa(gt>D2a4H2T(|fU>x}D@MF<3jAjL7{)GxX>6IJJYm~?B&9|Zpjr%;p@I!3 znf8Nnt6GbLm7Fgt46WW8J$}*_q8V3)a3B~pu#Eh9*>emFYJDo&_+dQRi?ioJjRN3Ae?Wqk(nPE#)G&bR0W+&JKelUIxri2D?zF=eAml5{^_fj zIG*M3bV{GO?xG*)`hg8yKWiuZ7bSRl$t&@*uJxs1M_=wbs!3kgqx|6nan2)pC-R^z z8&aFUeJ$#U#vU@0L;jM9%6h@d=(1KHRp@W*MQ;CHm8o3t#;i$)AaB>OM7{^)p1ix z*2kX;4*vc>ReTJ4zTSF#5=!T_@NN6rC!ISYnV;2$st?4zK0LXz8N|qZXY|@jE09WZ ze}vamMqAY4iZ=&C(+;I^ly5Gp-*!lZo8^i!t*A2ii+_Vh7sHpWr$*RCUweFl!>EC7 zwcOc99Ul5_V%^H8P~+OW^Ru}YxN4;x2*Ko{shnH2!9P9t36EoAV0(}MrRlNiJO-ikh{qY(-g}5{POuC zM2s!b%dLs(GKU)7^rL|b_`X<@z#YSQ;9eOwzM-Uu^emOV{Zq(&j~AW1%`G%tG<2e1 zi4H+w@(odOx4v)we_Xu-1q?g`@kPu>SkIDnyW)qNC|de5FV zR;--h5?5n7|22(|>27T2kO~FP{6_@7*kCj9s(Sk_c@EROm8@uqrLp7pt&rT9mNt_v z88(I_-<*Lxd2!p-N;tDyv(}4VRY1;*SOK(jdk;HwjG&XFj{(hMB2eJ<{dk+i$J<@8 z*Gjb1=pw0i7|c;x95Ka z(>~zU3cQo2+}#|y8rL!ed;Cg2|5JTGa;74dUp^#KFB2H2&FpEl^&Y^%ljlPdq)d#a;``cKl)D9L zK45r!F`8ZSnLWX-Cp0Uq@&1l<TT_{qsqAU%%7w$-S*o-vBr9BiC*nYqC|q;yHe= zK>+nzlx(h{b%?}@3f!2DobJ;kbcoaX)_@(_wF$yx(n~5XNH>pp6KM6R94~Ie_V`qK z`^C#0s?nZF^JsBgQTSmgE3Gp0>br%m5z7S6#_T;rR2t3cxHM?@bIT${`vB=RjC*?3 zKIlqanU1bHigkYBW2o8QAqrZ%4~j7#rxQAH$Jqkem)!DJxjT!U!zHGEFS;umJs9tJ z>==dnUSX=~ItR;YE3nN>@PR9b(fjJ2GsiD8dp!KF1H?sonXt;`X&K7JU!9ULLp2kg7%SJoq%!_M=^KfjJs939yjDAN{hL4s@swvmCT z?!x$&jr0GMe$q!9)C*FR2|w$G6VQC2NGe7@>+%-?{za0Dwo7_Dr-*{8N28$Hz0H8W zDCjQf>>3Fa?356`?zxQrE&P8}9)Jkte_X33B34FV|E=VCLeur%Z-wrHVp3rLe?`ZC zjKTo4whr}+kLLafC23$Ip}Nu-Rhxi)YjL|X+6#<+1HJf39rUMo@5z-y($<=h&S@e0 zqx-S6(+3S^9Dbh*wAaA|zlv+PCVN_oQoVJ)O^wSrVqGVhwvJ41hwaVaY2}xnI$IzO z11{z1{Coy>L6nC-IM1l>N?p8L3`7e9CuoqkudO%H%^0ldmTa{sDskl^!~cWV;y z)N=dXo?ih8=Bq0AMjUp|+LywnYc6&Rb8<-$(VgPvFT8piY00DJ8LFf$sz<=J>P;Um ze;3dqq=xVa8|2o=jBH}O%j9?DH0KDdQ(v^`U8kzXU&+_aZX!C~WQTpn*WuweD* z(>Q^&i~)ZNd3XkgOR>Xt*spcb!;oC*g8bfnTI+3pk(Y%({g09;fZEV+TK`MJ@)?YJ zLfc!w;4nOS^mqrbIkRh~Tg0!M*zpd++T&?y4&qf-h-Y-t_+a_2vQ~cZi>05i3`YOS z@0B#~x%o-92Rjxvu3Wa|L^L}S<9b{PIM1IO0ta4hyDZhEv#m9_#GuSsazo~W{tFlX z;EA!3CwR6F6YL+A6fC~PLTaNqiW6vB6nf8>Nz=+BLJxElAWo0C4`;+=)MhjHj|$Ibbz% z;4tl=YGc3Wut@p?yIdu0sm(sRiKgm3&vz^00iOgylzwPD=^LFaDmu zwnj+&C5_L2wrCNA1$vO!kXY{CmY4HR7{QO2ZIXJe>v2tkmH$N0`jYYsRwY?#k&74R zR(>zv?36pqGIrLYp5itB1@@0{vw3er&K6`Ucv2}Z#8dPj-aGPBI0pGEJVIXNOSYem z)wNgMS3-$JtLhwX(Pxu{QQpN`)VEBBD-Br^v(uL2!!MG@cFjWoSl++7$@J0;kXYm9 zw=H1Nc_tDU#5G~R=X1>5f4 zQGb`+9f2NOAokY$b1Ss=Ny>5~GMZReBUzY`fALjS!iW`u@0NLGY@WwM-0^*RrhBSZ zAlWYaN61%-Zxe$c$n)y^OcA?rQ8seu?7bVJ>NU>Bfg|7{GW1y#`ttBT%7Xrr&i;O@ z!N3x?!T|<((x$As7oE+vUZmD71=&Gm#MMB_;Df)LkhrI_#0OH%6qNdmv~id~4)yB@ zi29|=eEk?R_?6H2`}l=rY}WSi7qnc44HD%OSbVro^pjk@=DCX0t`L5&IzXn6n`{rX z&Z7_6%T>-K)k#>Z%Cag+IZO758?+bON_adN=tktUQ{kH3q^`fFxEF$bFxtof3td`K znjd4Y?ZB4r)0SL%XM)a`Dhv}-$*UKsdup7Gzi)l+pCxeCtbSp3P|;=RLZ{)%@qOmS z?ViC+5#eZ-&Zh8cO#Z;1>yPBRXQ8kDPLqIpVJm7qo>HTV7BbD_yx7Tn`&s^v4oXDe zs{%$VLx)*r8BqgoGmJRbCajJ|@8w+Z7!3{yUUiq%tAF~;!%$C1X|Li>s@^m}oFVw< zONW?9OB6SvLwah&(&`~)PxoqVlttelzntYX1zfmkZl)I96o0BcOc74V4IOntFWjgU&_Fo+~ibSZ(H%3@^gfkr^Gct=# z4VI|iq)zwBzu4~Z44sZ@Hx3ZemN-?oRRr`niIvAQE}@jUWs^zmnkxe-!E|xwoT&3?y3EyJgdJ< z2s8%@8ZQx1BZ4L@qGsP6Az_D$N{UfsB<~YRBXy(kf+#eM^7`kk_s%KZQteMKSf&q< zPTC-nzeR#mmKoT`ZBEN>!Vl{k>usV6AJ=X25NA6!ZyQhMKYt1D?2qmOGf9Qb4udd( z_{;fZ`qX96)yr!)*0bxsp&Via*W)umcqG@#>qi&58kxXlSwWwt_G3WI5$zmm?tH(Xk0KHUeWF&J zN%RCLn#-l(wmN~aR8^>v*Ccy%*seNWlCEv)G*v{Y)vg**2SoSxe>wzNFU{v|xC}|9 z|FBR#3C5@3PFgZpQS^_f5-j)aSy5QR*4fj%&>RQdhqyIR_LNLHZB<#;*D!94;xfg0 zIzdjwhF)&i=4Cqj^537T?u=gT&b+7-dWIWk)3|+0Jvn~H_#rYyO1edTs%8Vl%rO(<4LaPIRt{j3Hpe69!cq)rqna+#*#~o%7)r(Ql9%t4? z4?Z7o(Y7c}>(>k)ql!@YE%A6qK)t)uEdK|98+qVBM4RNEs%^z(he_BvI@+jT6bjg~ z8CBNf&3pC`j?~o$>&#i->oc+zlltXcUK}v=u6zBtk#h_Wm3_TY(fPG`xRTav&l#+3 zDbm5v)`PpR^!Iv;p_T6LB*UiTj^1@9O86@v*zFQF5{qfN=qy#TURk&yT2+$eyBkXs zfOek)U~gb9$4}Bfkx5QdbUUCrzgqt7qT8#5NB-|3mA?D=UYB){genP8Z3CRIZ?NtZ zHUUeoR>c9D^$mS2*kdb(cj$pvNx51<8v4-$FCi^=0eFEp`3NK0-WP}52P6sIF#q0>m0)WMtEAslz|oN>=tl^+jp z%-39g9Wuz1_Z7J1lc9GNE;ruyWE7%=)k=?Pp&DPoxYd6)jP?~F$sXM$X6sbGn!nl2 zo6QGot`i@>vn8hEY&eI3bM;uBeK0g;oCOJXxgXmZB|$I<^}B$Stez1I=jiMQ3$+_p zt$E+p@Tl&wuXF7H6&LG`1m3yJ<3L!+GzcBUc|w+T?D#oe_y`trBzXLcZ%bc?2=@vh zxd~CiA3cTHwqwM|Xg{@@lcK%iaP9s)1XHPKP7GFdt3QT_}%^edRW+z^+jf3o=m_F`=Tgbv<0 z{8Uda@+3|l$ZEBlPe#-iHoc%$EiyyjV3#8xfq@dT;8h?;NOUpa{2W`*oKkfY@@PsK zPf}_zQfyg!7Xt2*Yjx$lVDwR(qqwwg=l#yDS0Nf5&HeO$8tdl($T2SHEUNxd69)b# z!Ay@%ppNzV-$by0tL^+}+n-!)YY=VJLqydjMFvF(O4w8rbt%4EQSxiCqUX`?91E1U z;5hPWmYHKVGQj!-=DFl^t#)8J-KdCtL)#(NNZj?vnp=}NIYf8a|99q*1=3^pk9jl? zyiy&~DHCJsTny#H#V(I(#m1B8lAZFo=j~I`@c}{7toH_ORQl{sytU16OIg2mufE`{ zuT+(Q$&DX|sp>3|AYCn3CnM(d7R#o~zs<^hX{{cBU~V!>K{bqXeObM*HeG+CFh?qE zBpq`^64!&vwqXm9XdeQj&vXTMhsdwv8aLwrum-BV(CCK>$$5M>G{H6Y3r00McwWpk zcC*VYu`1BcWM02mD6j9U;_3&2Y`R5jjLkV-#3njbw@BDSsF1HGu{*~F% zpARO=E3C(vvu3ZoyceHX?<_hyJw(~;7;Tc*PqBLY9XTs?Ej|kZ<7x3dqx{VRwf+i5 z37)~Z<$Xnb<^WJ*dhR!CXPJ@CCL^G8T-G6A1yhlsO>+413C6+Qfi_eKfbN8DSBT2v zQ6vnSJ5r$MsT2x(oS|spE7+4KogC4EMpw(3X-ZzU3&xX=mwUYL))-yDQ!_(jTsKvs zn{dQ22^{c{<;8sKNS80C2Fm-@0Mf;6mhQFat!qFIkmcPykBh!-{h5Pmputt8dqvJA zh(E6U4DAOh{|n=nNTsP4nI((yCNS{Le8{HkqJ|}%sj%|X%HAj>E4XAVid#wC^J4_b z1?EUi>u;?H-}qc}!|xRlwg(OM-l^g0hZ(`xQ^obAEorC*uLdmRbyRN{TyUjz_w6cF zA&`mKFuRWZ4{!{0Li^=NtWy@;La&&Yb%emDe_G~d6KewU-U3UG0lL}e6mX-GdAd;y zj_n2N5uqR-;ViJuYL9Hv5g{)7uikKbT!Ma^W*CU~()AV4;SkAE%2?<$ElF48B?A3h z*8j)Bs!0z$FLj!+)%^u}k$b5Wet?-I%xM+OJbS~ke{F}ht3yaoCgx>>ha$izOwW1K z?Y*1FttDm)O2!t6`kxDtVfv|@^a)@Sj1jkc<)g$o=d-982bfUB+XCLt2Ehor( z-A(T0H!M)Z3NV^zV!43xtRhMrJ(kwoq`6YT#A+7ny_{)8VQt zz_bO32_wH4T_TD@4Hu|Jq8$xTGj8LKxwV?IvYgKgtHAAmx#10FK{F$QusE)_aw?w@}e6lyKnuH6p|dS;9M{k978E0;2zRNXOES+wqUL zR6CMlJAwygyF5cq5<|ag-$VlZa5K1Qr)G1MVMCOY@5d{|;w$07vlAJWKy0Mr8a=w3 zy55D#+zvsYF|bZ+ydh!Uh9_BPXT`w>%%7m^Kez@j#3H?*a)6f@lUrp|snq85#sl1q z#ooKN2QOoFJdj@`3C1NQ$pY#S`TiWi(7zvmibT8f6;r3%nF)G8O?-c7{C&s8FdCO= zGQ)GJZ*^U9o~q?^Xe?y%d8(I-u>!0g$4Q|F`Z}AFqxijLTt0Y z5q$!KH7>2ch}YxUXGIC<3Zan(J}nowQp97RlD#ppy#u^}-26({kpRK7YeTOp)8!l3 zzR%Hh&`ie-j2=rn3Edz;6~@m!ugT_BI5omCF{Zu&=9E3&yAD#=Mw@(b)nbW_Ie~dA z0?amlS=0HD9-P){a!w$t96xgJub>IS{z;H( z66MWnq}cXI3jXjm1~?iDKNU>bZh;G2?3Cv-O{ksSw$C!pCoNL5Tm6&aR8ZRJ0L+Dp zQ!H7J%*jP+hlYweO~l2Gu|n z$gS1^A3OI-D0(!M1^C`}*R%O4)-?cyY@7~O>XI7gJhDAC)eb~Ip}xaFZ zTdQt>YPiq2)FWwfoA4VnB~M}q`d^2>=YW}1Fu+kGU(u*-I+9SfUNiK1MZ|~OicI3TN+Gaj6(mAX`(DEa&bB2C5cepbeow=^38c!Jpg$gA^<6zqlgE0+Q->4a`E=n@0<#$EjB%_DI>eG7Od;$S3DPg zgtzb5As5>*)W-eJ(Rzxx`v^9-?Opi34c57L`Ce>m+9;X()>YN067pr2t%MdxM9E>c zK2P@cAoXm?3Vs7;E3yX)L;!9^%jp>;95n6yWSuNf)b{)dK%TKLmIOS;ggzKsOn0oh zr&cbsoomIc-r)X{!CMk5dO9C{jJI@{^9$)%-|rIV4iuVPN*Y`WhHk%nd%ej6v?GOU zOKceQZrlTV?;}bp=5jnx=w)gsb||kCykujRw1R-MGjaKKt|Nst{fY)~ROzG#MYij~v?yB?9^hc2lh^u_0QRBinpt2vRAnAe7}`Vl(b zV^OPH;PE9waPg{s0X9;gOy*C1z2S!CyQU8p+nGe~U`83?c;l98T@g)9+*2Mxm92qZ z59*?gVb>pFM~wq4I$sb@E~cP7`@68wdwU3}SAI#5W&wEEBP;IuJi$G6)tSk?^<0Zg zA{Or_g0e_i@MA5t2Sh)jQ3DdB%u=VK=c|Up#rwd&RZDU1KQSX=MwM>g0*BN(XVF@3 z4IF`gFZF&J8bCElo!!3Y1H5Of$onV*`09|-AIEmDuW(Od_D#^c7tN4CpZlwjh2W_B_tfp;X50LD~OKaa>3Bs6QqG97; zn!3(ytdf5yP?~R)Yf%jXFWs2_xD@?pIVbE$swesh;MN~5Pr|)87e{^iOR*PDiucM2 zllf2n@awtestCR#zeqBZ6&F8rFz0nlAN0i6PH&Q{opDf)`g;2G`j59e682@zTKwSb z6IE-bA&F(+l(OSfcktpxwm5Ja4)z;+QhJXIQo4THZESMg8DKF%_;Yd3M(CQUCO7}oLRhK^YU$hc)4Ltf6D22H%(D4cMY45?jHsMr6~N9jBnX& z-T3}RpQ7m`4R;lg&0~*d5ylsoVWVYfCiGDdy{Yopjw?4T^B_2aH`eKU1 zrfsSNE5GGD8k%*!0G06h?)`2nR&9d5D%#NH_G`2xecV5J^<8-}%mxHc(mk$_N_%yMaC5#zzPnXBl2i2j3bFhAt6SM!3zYW{RbJ5u z*r&Qdg^K^gp>1!VS1*?)7Ch%npKqmm5JW}L9R`dwb<4Nn&gMN?c{|SZ2-6pt&}^|L zTQ)=y>^Zr>Eig1VTqbuoPop~?sM#=`e*T`Q)hW&JtgAJ}ntjtlaZ5hcn&DCzN0tR* zyWUj)8hE!#>|mr(Zu>bc<#R|-o*X9IhpCKgdYE^|nPSg}0yB~*>ls_?jD)*{%>?ED zN!Uz%4s;;MG7Y4+w%@@iKK(WGfLDZw$o7MrK^S7NXo#;<)ON!bYJW8R|g;YtnOv9hE{6Pez`BGrc-YVA1s)e zqyGV$G5$BB@|WztAO`^A{_?-C^&e)p;w0Z61bRU4B$h;<4OtreT?_Lsy2;Qqe3cxB zK5+Iz;=SR4E(TV_zx@9H=a=|TTFTZZN{r?>DL%>s} zW08j|7c>m zId2|RqU$B1#|5t8;|%bFY;1+Vm}=U0K=>vF#M?%Akp3ghK(a&J_4yIO9$ksK<-Lm`FP4Q2wi2F^ejDqDKW8j`mTa9Fgxb44 zLF2lwjAr^s8i-nBr#Nnmiiu{Q<6zsmLW9#=nLpxJZ;dA^85I=L^}QW?Y6^ER zj^MgiTjTLYF#1`B1y?oq>=-Zcp5|$F-I3cy&VMp~!?UUX6{@IV_olehbj%(*1- zQ%mUe@syp>lhaW-*lWh(W&L=zAK47e0~q7p;#4D7LXY`{I-R=}5ks3)j=X-IJG8m+ zCI=^9i>FrE0c2sGh?B-}!_tHJFuB+sx^dq_j~fCnt%Y^TTov)$0Ua94mzWPZY+HMc zX|F?)oo%uhUHGcA%+Np)%ga>O(M5xH@RsX(S9k9$t!{WTML@Y9IW}D0V)5&qt6-Yc z*|S-#Se(LNN`hh(tJH%ap?a^B+fz_M8q?q8K%9YuNY=p{x{TN30 z&PFsYKYMGR+{@xT2Gc4#yRZP5o_ohm!c_Vu;YBoc1C>D63_a=w9sV_sK@Jf*^^=oZ zqOh$ulSpI!WNFE%O}CQyyq2RviaC>)$4EvY4vuF3>O!em=}p4LuqF-!y>QDyIt zmcSBuPg9iTh5{#rCT-&28`}df0MYrz2h(R=OGXRLEXUaaLJL@+f)6BN7@m=0f&M-( z8X;!pMex7f?%&DwyMux}fPnoI-x*TxwgpqJEwki^jHr@inaZ|}Elc4}#cFHzMjafz z%~o1Sz=J<@w4WfZ40nI&!O`xYK;Ay_l&MNJhBzQIy}+`bdjweop7yMS} z;qt?Pmh;VQl22XF=i^M*aX!&~8o3|P*$`#Ai}Q+}Uc&!KWgCye@X6mKcy@fxZ{DVQ zKzQFSofwAfsjn?(zeV5u4&0{Dd1&$qCZCDA0 zd4iK*XRif+I!3G^PwUlBUC-iOs|(@e5|7GgFl5-)f>)thb2%!QA4?d#uAH)B?>MqEr}=u1&KrL1L3)E)s(zv?ormtIZ~GwtwSJ*5e9`x}G+hP40O{O8>D7h}u>`iVAx^>OxNkXMs z0F^CD(p(n%WD#S}X^wzE7~p2o0pXPs=y4wB?$vf2phGwNUAjQN0I@ot%JnklTh%+* zl=YkRB|v=0;=;CH>(HI~y+S1z>=1aJUCi7}P+ngkY37M@XM4rWXO6=8MgrKHD1{%w zDwdHC31~jP&@_{xF7Fp9CqDrS=ijbyvJVLlW(I3t zKdHc;xl^M;zz(s77nM#8p6>@9Xw=h1zatMEo0p=k$U#(h4sFLYSVf9OXf1#0Wp4@S z75oACZWN09(vbF&Z$9H6FdfxZgxtFWd|AVK9+~T{dwmn(1r}F;KSmsLRQNv);;pYV<3E`Fwa&-5 zT(*3}*9lsSQ~sT5Ksr9z5&wAf^W*eufZId zVj{C&_&v9=9o>f(BMfaLmY5QHmW9?7dq=2}7B)Vg8QqY!npl}UTwL1&hC99th&~sx z%Jrng<$})|e3VDuJgEvPIWr1!#E=LT82?@FhY5MVziSVx-CS_h@W$SQV77~)KdbrD zTh-k{4aRWX7dJcTbFfI1(JEDd>k)k(0o6C$-*U=JGV0RJ|3p=WQgrEb&xG4T~otdJ~A!0Iw4Z1O)xy(d{FNpD2O-GThe^l$&h1tvM*Njz|%b)06gOOa&Sb z#q}eS&s@J2!wc&q07#gleg&OHk@+LRM*#U7gRuh?*W-!V-Oe@?+D>k9iNIn;eysy0 z5SrIb@jhb|?|NAiHKWp4)1mM~pgD&JaJZdkUC6nx-$x>y>7HulE50{am!B zA6ESsk7=@`D4s^KRo=Q%`bjnrpnTcS;18#lNTt33wDa0I*Lp?em%V);>bSFLx!x21 z;UNH>m0WXAUm~m1ovfJTKg&*VX^gHFXHTMhR5iKG)BFD~T&yCMtPTtD+t;c_&Da8< zXjfHlRE*$@%?Zw`B3Joq!a4yhC(&9GG*zrtmcA7s;CA1ZBk{a$VlakBfo`t5q+4($ zv+0+kbDN{`#z%B%6925;q_fx_zO-TueFq5iMBM9s@UrLg{w4#IcWK=~KC}5X0=$&b zvyB|efBksF6=np)K;AUGTXSwH{p;1ai6d5x!%ndQL1QEAYA@LAc}Yt?3ajdoR~2e;lE zvAi>Ce6rWCnO(q*jRaQT8t2=2?27$KAkgylURn1})NsgaD+piX36cM7`U_&?KNEjU-!q4NVcC|XX* z9RQwxymeI!h{*t)k>vIu?)4|fqkvhHFtE)43=X2mn+F)_>heVEJ}Cv?c+(p)6Ac$0 zFY{fm#%w&gFwx^GQOO2YUEhqI_%J8I%T=w5R z%oV>>Q7>qNF(JVIZkTh6H2CVivwUA+^*P!uSqTV&OR@ud-i7eXlg5R(mjHZ#tT)w( zbb(N0)VF;8C72HSo@I^%3M|7Z(WuM!!I%}&uc2=YM(O zHfj(?pgcl7<}Zm*-;k-~3VDwnqMCvVgT`xmfooC}9_1 zmEZy!;gqtt2?sb2~$mbfJL*4gOP*f3^=s`QvMjhU)X#NSzdMb(l zuKDQ21@F)Lnwj7WnHSiRkuByuWaMc#xsT12$Nv!7(&miN*G|W9Cryxyf8^^9jBGg% z)cds(Nr_GLPFC~&TuziUvrRL)-_awK*RyYkqp5E9S^{~<&TDNoG>{>>p6S?1umj1p zoE>Z%$-`c(tO}7L6Z=!3(Nt=>vYb3ev-T*xM zUi^X`5xpoyhuPy^cT!mI-csP;^YK9@?08#u2fN`V?dT7_aBwL8G{e5ZVWULRj478q zm-f>T44)m*%(kBcex!X~HzE$kj+-l9b}p$*7Eh);lWt0a*XPTZ^7k841mprU1|fWU z*f;UK0a|DSZ%GR_k7&cGbRS>x#0lfCdo_Y;%Kok`%|1=_gEPJhJIAeRsWH`P1tCk5 zlf|s_2zDnr{)Tp+RgG7vb=t}wkImB)wvpuMbUH^bMI3jI!U2IR!g@_7+my_uwx>sd zm32A?u#wuM?+$;Rh#8#zr#TbN2wR#Z)Er^NAKQf70RP~aRY;+%=tLBDKVfxg!bCwmFl2eczZ^Nm0Y=_EAJSpAVs5a80(|yXM_G~+$igVM#XS->&|77hn z_blqcA4!xo^A|b%@<%0`2CtLLHTvZ?w#$Kv{k=r}-&_e*6}je^54YLL7(z_F?_G4`nu>0E1g_2lVe}*2cC>B=uN`*D3tLiqqH+x>Ke}${M1q( zxoJ$g^_AwEMTPK|*N5nijzmvd+fP`x_vYnnuX6PGPaRkmnW)0)JY4(!)W%qT+Y`+D zZ)0h;{1MaV(#}19a8Kd_A%6sW(L{mc+6{uS=;VRbOiFkO0ryOM6lu1~v7i`OhyKR9 zG5+zrd-p!tU2P@=w_O!0n{OQ4xM24De{iq95*dj>B83#1+6c>ol zBbavH+cNHSaJk$ejNvmlwC~q#`>_gHzxp}Nlo_aJrpV0 zNFvcD2AG38Kdbn$P^7>Q-+g2+w}Vz8{e`n-B-`Jl(es8a)1^bnK^pY%@wyS7_|{js znWpU9b(Pafw!uv@1}0kv!0C_U9&@1gMA@{>wyfQK9A%b=4xdCQFz+7snd}id8q5i? zsWU55etL^^9HbgQoZFtj+K#7s+XHs}Hq~NvRzGt<$KZKBH!bCyK*jCbrQZv({PDs^ z!?x5+;P-9-6kQaSeB%^7qin^LVsEt92(%sW@#hP;8XVmE!z=*m^kOHH99%s7xgm0jpITP@ z95xGg52?d55#24I0>7Pw85k5ay)6EHH_9BV!|r>4o|i;=lnmt>#YD)=HJz85s?!A z1_wFr)K$XYMlC~{UWr~d=;Owy%+CGoTfw>9aE>xC1|H=HhJH{>ZDI)4b?e(D)E~;V zLTvpQaLe^g(s#{^ZW^6?xt!7VX>n-xK2!?z4Vb3Zv91g(|2F zXvM6GhE>swvyVLXg}a5YIx}X}6s~Vdrq$Uym+QY3Clb&>5jQT$_%(>r`RgXQunOL$ zYbda~@A0+%-DO(#Mq7HcI{F@4E`*D2dZyhg8L2JoaJ1VWz87a;M z6XUmNGLvh^7x(k5{8=^x3OQ&kn?HolTE`vw2#%z(F1{an(iSYvS|gD=K&2xSGD`yn zHAO8Ar}KUe<;KFhsJyO`{jpRu8K9+5!=)O)>nd1+gk~L0nJofxBMMa z7HG;0jluC|@ENjd#%bcAP1x!8x#z%x;esb%xR1AK>DUGTTp6hFyld0(db)n#p=@_4AiF8ZVs8*mGUy+!;L_yeo6H?{5sG>|M0=kIHTs980ep3z%PQT5OE+?~t_J8m<1R z_I<{8ZE|%^hSo5#K1(_o@j>lkUhN?apkwX=O=G*CYGO`r)}I|F6MSzl?H5*K`t2ur zlZe9AS+0RBqf**_GE~fai$0!hS6dpT;g)6up`g={b1{t#emVNV$az z7ud4on5S{-32rwcsatM*6nGtWdvNxjbB?XyT?<=^UG);Td^n4k-AjvAp6@PJZ*7Rx z^v~iE9V>>-KCbD=5fL_8YZJZ=!yVJNQC3K`FK@~woDl3Q6PXm;(Lfn;Eh?}M!V6GM z5hyE2$?uAe3VKeRAfvZnw2Ec-4$9gXF?mIssQ>0stR`6{BRsUF{4BwAWQGhW2&Eeg z7-#W)%=69h9`$xwjq)*c)Wt?kRb;qgJNEnoOjJ;eLQbowh7Q{ip&41G-{B-lJp zaB^=R{#1JmEQXWbAw%C`{R>170n1n3d|eTTAPS}j!RUVmxH2pY7YtE(vI{5^=VYe67OVB zB*DUA%*xO@ii&~7nl<0SvxspUOmy+#VeCQxbDa0dSC{yKL#9YmICn;fdG>;+QC^sv z*7c08`dh)2z2cekae~`qpT+|wx|T?lp@;mRK^Og`@6XDTpoyj%^icHAm_6#^iOGO# z;qo9s>Ni%p&>i>3LOr`ZWMc}BKtXs}`-^}|c9igY*P7oY1GwQTtjx&lS@pN1MO;^Z zSwTgDTF6i)Z`383@l<0!GnJKqoarLP#C+nDfov`0`;-1=klpkP+JZ{8~(JZ}IYR%k%%z(g5 z?Lxo33CJ$2lih2oF$uL=6czUFF(==>7EWeJ`Iup7o&vaHAjoG>bC_NX?U!7hu2h^O zhTcuw%4g@k{#YJwv%PP8OVkMWQPDCL6cxI;B1F$0{ks&b{9X4rw(Whp3i&~{1o^=O zd{X$ZtZm?jyq#xD_jJCv_M8G?E?g-4XHJ>oDI_z;nx(Y5nf&$~M;DUBjrbUxJKaKc zHzeU4pn}(17>BUaj%J@~($YG-ESCmaiUR)OBUqLoD&3$XKk|Ksy6Ot)79e?f-{I}f zDyl_YhN<6b47})!0#ggqOA?)XsD|#Xg3q1Sr>a+KL(YpDOgRWbhRrYFP>;X+5MM=} zw%kz9NOZou2ihN!koe1!fWRB1f9u#kZJM8+W0(OYMKuHzJEO(oHpq(ABTXx_25MmRrF;zjhHzM>j*ob@U7g;3z2kWzCQepO<3Wx!lJI5%R$j zf4Tyh8ZPW3Sf{Crd-n`&M0_$XMP1sHfAbgdivQb4KoPV@k_jD}EV#-jKD%4yHFY_W zWHLVY^nCS%kdXNH8`XZ2Ze`#F;>HJ^!*oTntiXhK;~F!jT9}#aF733a!(M3Zec(U& z6kqDX`eX7gsv)jiHsQOCIbPdp89RW2$qXOTX}Sev#&YUV>^iPIU4_^}7+V&b<%px` zhqNOLl@sY{-aFSMV7kvizc}PvS)ak;if@~LB*4gQ0xl3&`Q5ij7as+5fkWNnE1cr6 zDsf1Wjbp{!FQgj{DhNt(Skr z!RTHQ@tj}5Okratu7fBZ|21UB0)D#z=~~d5qG#&UJfDP46Zm{4%ZA-zBu(q!U|Pk+0=tQx{T-KB;`&*_q*ckr**~$(z&RRo>$~`h!tiO?!>!o06^Cwi;xt|dKgk>Wm0X&}cNwS)d{*7Xin5!=)Q$iZoUY3`qqk}!Bb z{*}q<8@Me;cESV=K(V*Z%zR3Q4-D4^S(Yr$DJ+`&fu=W)*IUW=^3Obyj|UEl3^P%! z;Duswv|mz{TnmD&J?jGDQ-Hih(upkF{d66lWj*llS-C_g-17JqMJGIb(sK>*<7E}oEQ zjGkxJI!Q{KFB2g?b$H?A5Rmi`%D;W;M=B$r43_Omlb zOKO9Tza!4+1avXreJ|jyy#_%nrEiYkvtE=tyE3$cWGsJ!Wd82vz27KwN6zFe zbDm0HR98d8($U_W;wrZ~p1l>tewvqp&0hlbQ_;Em#bm9@v#F-~ zh8U|BwlgKRq9`~J_#Bt~?psySeM=BgsvB4HD+G!ZDr&7n0GIgR%h$t3mWcU-TPH40 zFXg&i#CCh3?=;A_)cQ=6aEbJP8D2ln! zDti?oe#M%zs~UovG>l$yNb_l0RE86wj5vXTz~qY#YT9mguAxPU`!G|XaER_BO!##Y(xfh(rhz6~bWX(1vKG2ZD-3!5U7hsM^AX0+b?#2Yfj}St2nOJ%=t}%jQsVN|5omZn zZ6tAcKmW{_b_j%)B|D^RXn*8Z;afPvbd~K$2Z}pcbhDOFxf-E6gx#Jh)?`-k`Q~*8X%=3GH(c~)x7GBA&$F+ljNU)aWy$b z`o8MqfTgiSe;!iZy#Jw*t*g)SxI20Kiob#pM)Ynv%Xr7*Z%yFt@> z%*eEsAcEr)uHQIqfIs$BY48dGCv;y_|3Z7fItCZ;>8#4y?>v~?i3>zdTV639y$-?r zcffUCA!=VzY@udc$1kjlFo4fz7eEl|5knGe>cR2PWu=x=(&JoI9ss-{)x8uZ;+)8x z#M$mIZrV>p=OHS7Jk=7DF}ZTEbh=GQct>*xlcI|Azim((BM#hG<-Z$-Kd9(oy5FyX z%QG_F_($$R{y51dVz9p35k#zfZ-F_LH#zGB@5Hd9hDVWjC#HMs>S2I5xbh2l;mxd* z^ZL=@hKN=i5?j9Ag}YJUX2BD*>lUxpML3fJY!6X*E}|!iXT+RY`V`PvSPAu zkpFIX(FWABMdALf@#jrbw=YiiZx9!2!|kuP_0hl!Go@dVt_Ee0EI8E<2`ngx_ZJKE z7w5P9{j`r4q z1h`_JZ$wxs;d_dh>;~{HOFaYH4Oo8O@GO zC3%&ts}3Nc`{`b81->P@X9H^u03OPRsZYOKMiG;<>4+)ywbMA)K&=)FshGoP(!S`| zM>QP0tu)~;nhnpl6V4qzX&RqUZ1NL$Dp6~*`;qIcN6TY|-J-nXbl| zQ7I|ctHV6&-KQ8vQwmgG4<_#NQeI`lk_ODym3h_!uh%w)bU&WdK?r@O?v&qTr}x+& zM}bC&a8VC-mfRmQYJFpRtaMA2ndW^Ceip~|kg4*~gtngC`6nVa3z~tJh{vFb35&K+ zX-pw3y(q0vy6!-fuhVcgj{tA`2>>C>zF(Wq-ab_gHq%*c$iYMs61?hs{OzDB0EI+7Y zXe)I}wl3knlEMr?_)}73bX?ahns@L(z774Fz;@6hwSW1j=axqW)Z^iD0=FY=k18qxJAC}Lkf?DQN@N0>L-9| z0)WFkAlHTefo)DUss2ahHI(ImyZF@R%fvuoTC~;dho;~Bi*UbL_Q)OJj+F~cdgHhq z^=r`QQ}#bkzQc?553>BvV|WhL8umzWs+9`dX?jgS^gSEsWd6{zeurOyo$Az^zGtpY zdwU9u)~QoOWfO834_wcqgXGn2jQW=#Pf0mGEqL*LxIn~=M zF0bswld0mtjhQM+0P@^-=6{gqZPdxbedKqm2}8SpP58t;gAQ~2?!Ocvs3jDi_xdgZ zZb+Rjd?s2A4+aaRky@Q0h|Q5Q4!}^t+o(g#?!SWx;7dMtdVm{}BgI(3HE%;fDND#c z@pY4pdc_SyJi2`N4kXCbV8b4Yprn#iwuF|;yzv009`QF+ooBxAxuWijc`CJ`vQE5to3VQjRpIv{O9n_w$=@1d#UYz>MrMW$R^ws`H`0f)?9u}nvxILv5jcK3En zO+_e^0@N|3x~g!d3LeS@6*vST=E0H#+x^c_1v8l|^&*h5(qQu97AkGJs2!oi?ILLS=?K}UduhI`kMDeR z-JYy`Ki2h0;lA+X7?uO`jX_-2SXt&NMs@PF60Hr22e+=8!knA18~G|vd;DqP)eLBJ zFIFFViOeGBw;Hv?3D!w%nonoR7;GzqTWkB0rJ;--k+C3FAl<^NNG2~{fjQRfqXalQ z*7jeczl_j2auOk}hnO>jbSD)->NcldPzQ}3N|RZeCdnt7zsUn+l0<)G@asyHbssaq+CJBbB+}|xBR$F^`kiMecb=wcrrxUfjk4Y8 zCip}zHi?{E?X_1MpBh?*G>=6|I!U$Gy|*f9fEiuemV+ylPMDcVHGcRtB96zbb;gpZ zfw?RpPSEvHY$y~RdIMck4jKFX`4YJ4m=BFSHA%exF0*JKA308>LIIpm%Txh$)NqdHObaBlrIf)m+1;xbqhRQ73*h-(0c z^_)7;*IZcI4U2vcsGi9l^{WG0x`^7m7#|>mkRxJWu+QODWdP;~T=0%+pSq_-m+<=m z!tI(bdFWDzk644vppf4MdZWj`Yk9XdQtTseD1%;do;6&qCO(d+tL&#%d4KpiuIs^U zp-O4>lCQD8Dk7;2V*-A+=OnKZ{Lp4iYy`y+*$2PJl`Q{qpBm~wSfBp&L?*%4j-1a{ z+A7v%`{w5OlRh7|qc}}6je_>R15YdtSSpX#onW$FT<$`gB+rCfwW6my*#H;(`kyJS zB-g=apG4xx$aa;YSk7765+N`BGQDAW9oKry3vO$muJmN7?U1GItXL%ZWi(jG=$PJ7 zkzy^y+QVo4hxRK^myP$v`eMJMcrR>!?hM=J=-`vU8-y^zw+g=A{{f1Q5s*`nW?~w{ z6f^Uf?$n&4V0{;euyKq?daxJ&D9E3KaQS1t3f>B27!FA9DXR}b_TC?V4)VW)TB{C} z9;iOy=-TkJ8h8|mc|Hq-VBFaad+VE7>7XNnUOV+P+^3+L$>S~)%!t8ciu$<6#}=_M zkiXr2HF|73fN+Gc;aY?H^TzKmHJyRri?K^$JabahOt7q3$n_ExRKwdn9y&ANXK zChH0zbKcKThJ{Ef>Ohqbw7tk6ZcXl0g~EHzJRA}||E?i>nLTf`vT;W6I?#I-?450G ze@U+x_u<%nsJ<_5wppF~-l-KCqUu=Ae7%75qoib;wV8bTYQFQQ=orW>>Qs~|RWe$u zIA$(kDSeVlJR8a(o7-Op-bTeN`BXw(IdqfH*DH~wz1r0Y_D(fs+P7a4MLh*4yU(^b zN+`vIS!iI9LMf0&H22lEch~f##+@5ti8#EvBq>~Oe+%zG^!1x!y}FN@O{-20%-kzo zFyyxh)*?1?a#4uYRU^$oZur1^gBXZ$An^9s=0!K7vG?$hT1%D9_OkY8Yadt5#iPB_ zTL)wXS(WRduHv$$(kxuZ6Au7dYM${y<`h0!<~ePa?Mhi3k_F7L5)E3J>+3gr?jR4f zDvK#!g^dNvgq`CrS}aDbe507!hmw{O-Skxo*Nchb;H{NkSCKc?;keR0F#(J&{S`q5 zE*B|N-;n}(L=%{cwmv-Jj@_rNVK)lL(%y`s3lGr0R?#85qj;zBE~T+HmWpai5pd7u zM56s3S)0wOZR9Wry7oW8T(LWU=a$?*hPZQtkv`;-$<4GUfX5^xzd-3(S8fv_51Mf# zLJbIk~&j|#PNXW z%f2vQW9}=|r#x@`y@H;=Y0Ym1KY45ab(7cX62RO5`pJ+lDZX%5+d;vSp{-_4mw#Ht z5Lxlp0M3Tay3=|V$6t5k6QZAM)ipoUml=qCaEb+@@E2IWewzlY@QQi#Q!KmiAX8@LUb zdCSuLt2c7bP~^(3WBMsi&whOiKPoV(b~=M^Ypl;R8^7pft$FZ(0oC_GlEC%;GQ-Ox zJ0gyulq&qWZ4+OMMtM_XgozL3{OcEo8%O#;8o5zMJj5J`TE3F&9yHcD0aIlD*CUZb z%+G<59hCNzcODTk5o$OEiiXRJNLFt^+X$H1wOb^k6t*{?obz4D8G~oXq-j*GpOinC zx_iA0x_@prq5GK71eCUx@E^pwQmOivWO+906xaUv4no=0eD?ftGgiZlh-30Fh*QU- zELJ`aTJ%VTEXU?$z4d$#%`iDXr{5CUc8uAq3~4cn$A*bSYP8#>1Mk!9RRv>};Dh^< z?ZM%XGD_IyD1&A%b&lqRyi(T+7(01oG&K7)!hjUw2{I?s>Rjp!f_FO{;CjB1(H4Cf zWQTdM{OnF$p!}egkXREEG-=czqH9y~C9W$Tly7ctvl1T$+(#w<_S!n=W&V!cUH$9x37(zWE2gcj1xJA9NblBS)G>fB8){ zIG!>o*)OnhjOiSAJi`3t>hBHXn}ZwF<^Y|ch{NbR1;@4^xWXg|di=N$$z3{n+~xdE zG);*T@IH30Z?L21)P_h4apRWXYf6J=A8Kz|K71YCpfSw$#r0f)4B1yeVBYV^U5>1I zP7hh`Zl?3(x;Lg2IV&BgqHAQ&U4im3<^zrafG-#xqo7=aUU=D|=kF`GKgK?-doRsO zh*-fIugOH2LV=VeQ<~O0#^KrTIKC;4fl&8Si2eyg87$nMXRKpnH$16Rliuj;Oi`=E zWtn*PgyK3Qt>;fj57OfGi0sv$>-G}o56D6XH}BasnM!BFN7cacQ0ZXkrqHdrZ^#3mC+|MgRmIPejD|)oW7N8lDZ9@h-xfgcWxq z<#YlifFY3VJ#&^c%Dt~uTphGXY3T=X=FVZt@q!$gR!oUi(!#MWce+m>D+J2hBlClX z_uTtBXTk-W)!aYMyn>1NCnrKRrXq)8D~FCS&C?`dg6#A-6%0L{Ep}7!!S^?+DZ~d8 zSobHE)OHyOA@tcWlcY{R)lon0=|jaM?42y10LRU#riG}nVwn;ktWrMSl9H1!?06O3 z^T-ci-E`*Y&pLT`CMw!*Gs?Tjmr@HxTg78Z5-=LM<3stY=Q{!mtqn`p`0eeh3tOb! z#EkXV>n-f>3MG)r?`&{Gy-3klPb-p?fM5k#FLPFIKAq8eQ0r%~_G7V!GQU8Nq_Jhp z){kH+1=Dxz0RHBKLkv);z#!W}d~n)B{s{A4@bLEFx2LYq{IAd`{mj(3@TKf7kwKD+ z5@!fxIpPo_&F9uaQM3n`vHbNJ07&n7|HFrjU0C2jX`t*7Si5$0$az8%LBg#(^~i$G zDE%lb@2Wdp)idSsRYRrH<+0h6PSTZrgRCB>&;}e(H=~q)Xq_%Fo@%0sX!MhG_B?{W z@CjAmh`_SFG;L^es?U{z*a4CC`?#Z<+OAb?Vhj4(HJBqYFRzb9AxC93N_)mDgux=S zYJYCFa-;Nsk4+=#Q+*jsx~-zfj-UuYX?`dG_B_#X}5z zehuja|M_!>0kH)Ua`Z2->V%wma=Zl6asQ3ioSg07{%>H(F+?1>FEOb^f|r47qRl9d zCKuN}7!8Ai5?j8e;DslLoYVfCN*JbsKoMTO#t$Z^u}LFkSH*7hq-@yjLlAhRvDhRU zI|jxXHW&jx(DwZgYqEq(YM9@C)coV9+@pw_<{zJoP|cL34O>^_PN&f_0DXqrzV_wq zqK+D7t^J;E6?6NznOexaF?8@AOT`t_l26y4sKJY&0G$E3JXGtAU|GVq3-YOC@_{UDCoriTPIG#Ex*o_=EC)@2e{Fx?JNad6bfFN=@HjMf> z&Myrw+VCCAgBjilMaR{fmzMJ}d%ExXD7vL=s5{po!*{o9_O&E@ub{vAS21Oo&KVS@=Gt_DmIZm{@qLyP>m zMVKSose3S-pOgY33nFTJtwkCJuy?Hn&RBfQ$QX0|Y|fT_PmJfx1{-2F&E;jy8*~wP z$g57S&!%$KSk9(PR3^yep~|a9^b3Syeb|nvHm6Wa9uS4dG^?x}h#1l>Y=M(fr;DGq z&1z`*vlT3*+wCtbda)Pp!e|<9Q%|_A<6j* zC`d5k!sWa)g?uU1u^6(SIVDL@zGauzIh)BV4eiw@E@<=gtMzMva-W?31T&;F2yqY( zu|12xjmUWydzWSgndu~z+DN&zYq+n6#+(`K3uJ&S1(g-Y&%BL2GX4*ES4 zGuom=CZ`Tiq~7NK5dmn9e?GdUcXOC-ALQvXoD3gEDmCR^`nZ54TOTOC+t-|#!iO!(=ZS@FoE{%=M)5G_9&O72g8GIrJ<(-Ux6 zaDk3GmGpi~Y7L;-oIS#PR&izQ4RJNg>0#=lGR(YXeD_?v#t|m=9sJ$S2G?fc1;AIk zvzLwIwMskV$HVp#)+tBmW}~MsP)^rCZBeJmmurlVq>lNs$iVj&&Ib{3MPN{JAdm>I z-OuR*IwES-L#<7Ndk<0qUwXftG2ZJZ>=EaKY!(i7FhG-vmP<)!<#IW$H37<1x$co$ zN3xTgtNx1-o*bRCmpH#z)g3jb=-`Wb zpU71qNtOWg)Tw1-D<9iu=6J*vLZKw#@! zPxquWeo7q`t#?2h3Vcbs*@{|>nDOwaN(5Syuja4ZBHd*$x+z~Mw67=H2}*#L4Gj}2 zAI`3{FsyU=p1o)E%`kY=hwp}Mo8uUZW0)0jAD1GSy5PmKJAty5u`NlRgEy?Iwb&jSJ+=~{$^cWOlS1$%|zFQqs6@Ru>2!@zgRikrxrR6I_OU}NjTip+~s(qx`S%+ zq74k|(+E>lbjysUqvpGWY@iB1#^hZ$+%M#qJwCMCM$rL@D@78(eq+1dD~^TtFa&4J z^Yx!WtU1niA7e&`z04|iBlY86XgREQJ-Z@nJAVRHn)A7>cU&(F;mK5!KO_osJxIh z87%*zZsL{r^yDX_3;iPXIfA{Qw9U!#*kWQW6D|G;sO@7@8TVeX7lcrypxFLE2gAB_c+`fkA7ec&0+}l6>Um#l8sNqI_0=3j zl6GV2(h6D8;$uG zWl~phP1CdI7jO%;Hv{?n?64B(y5s94PTo+cEB_zfQqyP5a7iCv=u+(EmG2?vX<6d1 z{yoT+ftzL~nJ!_<;n&ac76^R>1jAw$`=8=rDH%{(<-4u{$}c4Ad1VVpWCq>`P=HrAu=AinWI9Oca+}L8mOdE571Ej$jW!Q;svGgebwSS^-c8> zb9UicZT8|65*$tPOTL*Y+LchRHpAn=>_U^)q8{z6vyR=N1$}oe<2B^`qA6MZ*~sfm zodIlovtVdo$q!TAV4kGH34?CxUE7li#0E6eIAi031v`H`g4Vk?E*T`f>QK8SvEJ~> zZo=l2r-R=Lmo$_%@RRGO*`evfXY-fzj?NSpB8}Ei>!+?atJY4P^}6$`t+>bIBl?`x zR|y?~Q5!%JlrbzZShRXu-i0*MHE`N0{Tc;Zk>KZ-npyrJW5j~cn_iRw-Irm*7BC-l z@a*~~E1WT(62b-BfDPm)%1iNr6FU~v>;Tu}83`gNX}6cD8ly{j=T4=b^}M$Nd3lA! zokpzdmdP)Wj-%TPC$zr2!^mpxR@XIPh;GB>!SA2=g^vqm0wdOPX(rW=3i|cfq5jc4 z3qu-7P(%kP3zuA<*wDosn{>>QrIT=ag_|lcDf?3tKqQjxSZ8(**$i(QqqE>~`6)#d z&8_^L@oUSVYV8`L-1DrQ;+9DBVCmK~cSH%7cwpIYtJ(hE{raHak5}}O#R_~|qh1(3 zScrly;Yg`>)wfzOnu8|6#t0_AQQ(^9YWx)S3Z|dwG^iyh=d;GNq*0xcNzxSe*E?-{ zil^j$7%^PIxkUqdFchdQS%4(_RUg-vIoS}#zM=5qzkBMpmiRsiYUq)D!}a4L^$>Li z(`+T{iz{ygwHwI3x5N=dhc$8EP`cKx4mkkpeIC|+|HFz)p!&W_;OT3>RH1Y6z6J%& zDtl54UKhx9F+?0&03*9F@)jliD!0|O1m~Eg@d;C_sVs8cUtfLobICj@g&H};IeQH} z%J%BAfbP0lTQ-1{pY`k7aL#j^4C~~i55N0c71gqn(d=YxD)SP;vl8J|Ag}2w?bic} z)_Z~f(*1frl?}gBpAIbJ@q0wn;_REd%R{T#YM3yvd@j5cHxehK$ClGkc4o9+6ev~m z0~%FXz=N%t)JUHE)duc2?9o*WD@t4ag75`^_gn0}dOs zb%oYnB(z|T#9>@M&r}~i z^X3jf-N745sS4m8Pdk^h3*r>NA-f#ISWNOwG z3@%foU3iWNC-NTzVXecFnOm6T;e9Sth$MBI!E2jqvrOyxTe^h4f;e zhTjr-F9Y4MSbeKA2+BN?0QX9}$e8kO#)Bz`@P=JEr~^t4Bhm zn`5oa>{s4)$jEpRt!8cb^PRe-V?=Q4PaK6X4TpJN7jehlHa2mYPL=t9qoPhmylEb( z|2kpxw*JnF_qIC>D$(y>_JlM(Y~)!jV+I+j*MXjhkPp!FG1EXIh(;v(34!yI5*gEe<^+zEuAu$-yr)Vhgw?L= zR=@afxWU^v`}l%PzNJ{*sl@z^(E zOf6I;+`Dk^%cI7)?_Ikni?zM0coeI{;zD>H$OcjJ#UINt(5A?|V6UF<{zXt2WPB}f z80cI*G+fh18)4-2!><>s{4ujm7SXP&L3})5S+K5N6!19+CP|Pfaelst{f|Ea|dNx4Vg$Qx&nAL6u=|JgR&>H7`%oi z;n6J*0iJ^@u*I*#C-q+q1I5&&&(*JyeU;DGPL<_oXWjmRTJ^ecHT0TpW-s3g+-F2| zY~-peATchbMH|&m?i{9oRt4=s{M4d1xL5g>@g$KWdm?CMgqT+u(@{t`6g4E9-%HxO zzK_CnzUCCTxNY;d+5GQIkS~a1v;45f4d$Iq$7|aMG$5Q*pL6|j0_$(d8sfHO0=iQO zQev~L4wbHT)WdYEDar4$+NGgDHCxYXYNN1OeZw3yX(+g<4BNq%;1p|5b@!A{OZGD*=g{W zRcuxIRr06)PAf6XOoPkP(5HGh12_&K0wh=owi0U+%peyUo2gdP8EOw`0J#5bJt@Z&px4 zvG8^9{zL^SKp&MWU!i>nwJ9IKGvCtES5zO4Vf!r z^y77-*)m&wa&cVG)k1F4dmZna8`xyf{~b=d(o_b!yI}2_R>!A>5YXK3ud3k*vi1g9 zXUEmpGdAQ!7?+m+tXIkfC4*l@P=H{A-4@2|FnTpK%D{@+H^EN(Z zx+d!ppQsG;;WHKFp^x6yN?np=1GRZ)@zM;Q?#C+w{$J5Hv3JCd?}xYYAxvKn)~~5; z&-&e(6m_*OM{a-XsERp$`LgJJU8XS*7DPca^v4lTHJ?JN2tRf=AV3#nHI_4hIoFop zXRWaG=$@)}t?-HEagmC&(K6`YhK7fM$E&bpbO1$8OWw7X*Bn2B&Y2|Qeh&IL@xrPny}l}qfGv~!*7c*{F0c@!xyEEPcr6FSVO zYM4#3d-X^J9$vaBmSJ>zRfI{y)i#1F$qcrMSxXNYxxr-A|HMuFu4L46!AQ$gXV%Ye ze7>xf?js5(x_-upSl7OD3f1ACu@w6v*!Q;n1AjiKaUbyqocR8;-dUiOkewm&K0?;T zS#NOvZL)^Iul1SdE*P2-l_YMVqh~r+jfp;$@;+k@U!u#NN4TH8R3B%ieITt7MgaAi zf`hE6P5S9ZEO#Ka2_F^m@gtuab&Dnc;NEu}r4@>lzZp_Z;hbf19TG2}v5JS*NHwK5 zX?}*bULUA%;#moJ(1p$?U}(;RENa;P64gJ@)FY$y{{#O6_}+gM){j!b4!8PY$^Z=* z;@7f}sB&LGzEl1g*%f(zQ=r zsOqoiwT%(`kFNqVA*OPh-^%T30Guu;W%JlSZ`&P3X^Mx$Ge>+{EgP*&RrW&`jFfUn zZ{j>>mX$(QVf{hI{R3N@a6x1Do1v0p6F1SaUebywbzZm4Mawk%Z_*l{_WE&KrW>fe zx!18bTm-%c(|;>c;bQy5%B(&`;LEO)bOC>~t4tGrxj}y;ton)Wb*ABjdmw)Hlz5Oo ze)fux<2QMDGw*i*<|?_-tR$R zf$RQLW}O0H=&N($o;Rs~u^%u49KXqKp*WBrskiI_D~l_uN=oTg63Y#iIJlEjb?X9A z*eRL)g#>ULyJJd^cVE5|^;aEBf-f3-2FAxUvijSX^nJ`{d14Z46gkzw!f2(fo1diZ z-s^7Hc&jCR5*cI|!hXuG0#JLXfk{MRkT7e>GiZV4-iK(3hE8XdrlyHU_62%i5Uo%E z2h6%}i05T>-^A@gnxlqzYH^~th{F{G9kOo#_Hpuk>hO4FQWv~`=7UrCyOGBYMaY^M z5uq=}XOYInDU5fDUxg)k78v$_I+=U{+o%!!emjj>B^oT`tz{HX!b*{-L2#&P3=n0Q zYyY@xk^kLGh3Yjnn=8TU(W{p@loogh{~+j-W;wHZeGO$r3{F;1R^bL&x_alM?T!gS z@{CkEO9d%fBXI*usROL!=QU|(JeCK3LhZeC&<0@1BdR{hhJI%dk6p9@QbAmH+L;lG z+!aw>K=y5~L#k}xe1`BJmGP~2*^Ia11F27Uq>)U(ZXY01xajQ`y<}sb5c*9!?N|%wo)@&mA0h?;;c%Z8qv`f~d`{^uMo!e?|Fbc zJh6_PwchuaeOa5QV7<92(W`is9)@vL(gd==Hs zw$_4w)icG+gD7e#B#Q4)!&1w9CY}WymQGb;;69QBn{UXcP3#TEwHA;R(od}Ew5#}P z`cYY*ZS;C#k($tRa*60&U{FsgPdM_dh$OhhKVwv?tkV(;Yo`OKX^!b(k!4gAOJHnG z9W3V}dv;KZ7mMygh!AqhibV=g$KA&DJlWUXA%z;B42gdpi-}t&6mX1gCSKd^1YHiy zHk0^hfmR9+?FEr_hH=y7#2tw`}*ECMo@1YaOeBZ-*1mhf8rxN|TKZQ-m zO|H`!@vZ2n;7|acIw#u3OI>QGM)^ja)w4>jOS(JQ1m;}JYma`BJEj}=+9sMv@E$*} z6y}kPmZT9TIZPR%Ko}wF1w50pOUj}=er?_iozZ$5fh{z#HMw6X{*j$z+OdMwwYjuM z!U-klESw8WgVZw8ZzQDTF$0C;lMqeT84~M*h!57uWYvPChTmtNXZ`4${Y;$1N>9V( zz%>ZSv$X;rMgy;Usd3J_4^Yxt4#hQFWVR5=84zcw+a5p(2(h;J)F}LjflrI1ttPHs zZ#sa>S{@eoZDiQ2cIgiR7C*HS3@uB1D`;?36V06lNKScHcUxh14D$sN-F$Lf>qZXR zZDV^(E1}*UpVTfCx;}W@%Rm04f>0{Ae28(&i-O0JEVPHtP#P;aFmSzJbLV405H&@& zoNr4NvB4axWM4D+%xQb?Vvba%oetEUCv|V)eo9V*%J1utKV@`E7zWlCDOju@?O3%@ z9@?LT2_~)IOq5^pwUzsMMzb9N2x9#6ri>W+38eHUD6T$0!{zK+3_tnEDuhBBa^`OO zC^dq;T3u|hjk3xJZiXr-F>RitGkO4tGW7|Gw4FN)STQ7s+i3F3(6OJ`$0 z3TqHrx?wV8FcWv&InjIEke_iH6#v0Alzvqv2Czta)U<&kcX6&DMrtY8ccN=yM@Zfs zdW+K7_|__IM9$b_*<4H5VXK>izc}+{p-|-^hTD#LYt*U8Yme*s*H~`LkI>ECOT&aA z|2=DuT!r^&t};zP3RR%Zm9#PlDK8UeUinoWG1PHSjDvP1Z@&ev*4Dn(H|No0O3AaC z1F1vZAN{22Tljg&t^{B~C0}*5%o)cBg$$b()3>xcvFG53R`jReOSL0jVVWvJW6Nb)f;e#SD}Z zG#IS!_e$NMOf9h#;@Tl=h}{;)C$t?2N5=5&OM8>!<}o)MhAet!3&$m8aB`}(@2uYB z<)xO7rMVALtxHWi6K5#u>)xv?&~-xjUDuvJZ)=#x2da%%_-(r$97-{TePrlI+VM7q z;R>L21X9FrP81U*P(ftX025hG#xmddm~-#`ACsaA0s79Bk2J2%ZyWE4%J8mtvQgxe zH(hm}+=v?K$jAdYcW%T_N*|941N6vsPry9eeZGW7we zW)(ujr40ra^DNs}DZEfnyw#!gRg*pgE&b z*3ZIvwP!xHs2=j?67y$FkC zDLXD39@pUiv`-iTL(U3d&F%$-SwYf*1q~jWR6a>$JY%(UXz!D3sGqQwI=ZXW9DzsW z+owAv?0LlJJ~zlCa0aL|_*oQj!jFjDTyDX8Ak%^utI+L>U2q#!?!GO~1K0TlZNRp1 z{6}yhJf`dAuB1zld^KK}AsnCeD3BL_!+!>+t1os7l?=9v{% zVjHKF_8UW3iPka%=Xa-PN-hkDg#LNM*WN+P!UHxhQP?iJ><4%TzZvcH5PfL!O)rt{ z4D5H}*>@8+lXP#V{{9w0z&xB_z+d;I#)jVj$~64y6Yl;gY$f8WaIw|aFgUB*<5j-L z%S#E1EOVZyYd|HvyD0%xpR#KgXVqLmdA>phk3Hj_kI;KLL+YXXYyb9LMLxF?kl4uXC=k1k$;z(vaq6KOdrr^2; z8P+_ndnNlwGBy5q?gskjcMvmxgp!E9Zi79Qdg@bt;S=roG3Xr>UF*YH&_Pmpk7Tk< zk-&73!TY2SwomU;l;Z?VJGytTzkzPv_8g*XJpxk(X?xF*b668_cx79ED|e28S9yNC z&V$?bTH;MiK0TJ#1rd=g$d}|uE>LSbeX~nD2#C5Ks=WPU#Z!NPCCLwH)IL^OqLyV< zx<*z}_1NCFIWT`UyvNi4v3ASLav?kce<=`m5YzwX1|zHXr>V8=2|p zDu=eC`V}3pkg4pM`RR<+Oo-H9o8MaUb8!AG$k@t9NA_zm+9}L;6QP?)EQQAI@v}SW zl4GNe=^aP5qo1|eHu)Fnt2HGVrG}XazpCM5UNzF1vn@7v8uY*a4!4qfg7C+}UID%Z z598OoDg4|wHC-EQc1}Pn>_>~!FdfP1 z*7UN!FiUp~81~bCDARyv9;*93{&taWpK!m**{;T*I6|WBisSbTmlx%F_2qf z($^y+;uXpzV0%yb4l;S7;PU~R5gVZkRI4r1Meo<$A>wjl-`ndK1V0kJ79lVsPQvAW zptuQ?+jO1-s2EpcQ8*b!CPR!(AUjMJZiu@H7_?aRw3pAa`R!e*b(yPUPKQ>PQ?oPu zS0Ted1*&HA>9>6zqr+b?z!gAle-&?b+mdsIjY&sgGlF1Ozdm%B@UtUOKpro&m}I7D zkmM2N?^B&PLM*$a)e-1k{r>HOwoe>hV{36Akvs8_lUrKnp^x3XsWPHK$o_hP=9{sb zCgEx4@NFk3fD}5TsivYb^ogg3>D@Ayk{sGz{TQnKy~+0HF>3u!`OAEgBHFzy8@|n6 zYJAa0d)Nh?+DBx^+27GfvF_S<1x$d6FC%Y96=+``@rB&^gNnrd_+z9uQ2N^$aZ?cI zIuS-t?Z7Q9#QV!Dg{Ip2`K9yE)gsp3l6^IQ25HQ~?+q;f1Jz`@{{R&*807b^TsWG# z0_Yh%RfqTm&fQ$2{^Nt5IP4EwfmLEu*TvpaP3DVNVj|VewR8XV;YndRmFhkjrgd`9OdFm!c7YhaCZ;c?Kf`|R->cXht_Xoh*1liHhu#Xw`yJ6H_#k9Q zm^OLjstMR}zQll5xm|!4^hqdN0{`E_N=cw!XxFmD7#mZ61;UOeLHkMS^H?TVj?At{ zzYFNQzP?Xf*5u=z1Tp(9>=GeWza!8853mMQ3j8-iVk2!yeH^2Hi1~hz`J5c4!=LQy z{J68GckubypSG#gNFLD_&dBFEZR&rmC8oI~Vj}I$Ao?s zIDzA)GRbIKsA~tmhF+2jyypNF)j5fLd_?@Wn%yyj70v-Ow&4p0wwG z4+M~Rm4(rKarT|2KOc|2(2;*0RB(O!m~RiL%=xQQ63C<{#Szi5r0qlXLwnGjz2WxF zcbETbj<9xtP(LIGKEACJ`3Rr9kGPV!4kumf2cnxBvpeKEmjGW9gT(7y`__}i_RryY z8URLD;RFJWjP*m4VFiiFKA?2Lbo6M7^|*a+oS*Ol6qnLXrK0f;i& zA}1A8JhYkYwB9mY1$EW1h@+vX9Rqs?o~ z&*Lin!P>RP?1<7=x!n0FYYM0#^{*c}_0n(~WfsZ__ZW*o5x0^Uh}%735LvnO$<5%Y z@7zI$ts8DWv*g^=9n>H3KZ2RamIEIe^oUnK+IY~}H8seV@gP@AC^}NpCGDR0S83A{ zR*PvxGFk^v6)h#2h1ljR%QF4?$94~M^rOkXbJDd-9(7TOUeM8GDHOVfz*&>_hgCq< zTPPEO#w{vY`m~DH?J3tg9{%#MN&gp{k~&M?eqskb)X){^CZjk&tmdG8^!OcIRta=a zu4?dUi|N4yH;$_yao)t7N5PK3pN@~$UJ?7Md#8gbLg3v$Hht5cvq?m7!)5zGLOv_i zXE_P35&j;a2BF%GubfeVn++~*Y%N2!b+cla{XhlDxjb~Mn@#7&j;Cvw3Z#Wi#+D4z zE~2BbJ(lBcz>wK<;RKTsX}`MEoL#hiiLCf7b``;D&47w-z^NPGs2Sm*4FkOwar+kW z^M4Gmpl1VU@lou|6uB`8ZfDPtUjm`aHS8Ia^A%H3I*ZgiKirE$;_8?0=>#NTM*_K{B<|Id$X%qE9*N ztl9Hupgh!@?C<|PwwN6LH{9yTat=q~5%T7uRWh+VtQ{#WTcIi=_)>aq$-keF3k1QkQ(r5PnSi}t$$mm{s zwodyo&;i;<_s3lwW1SR`JY1idz)dx@aCJI}WPKX!vK6BWB=b=GX&YhIo z%cJEvJ5huQuv4;tlSE66u#P0cx4Hsm7TFA@H9qn?_vh_kSKlCDygQiRD>D-%3187_ zwJxIAFuJWC(&7Bna`aNo>)W+Du+p*wC3;tS=w^ zCSN-fSVzZ+bPx@nW|aUuPvKraKhK&3adBCo+D|H9`cU)zn)CT z&!TT4)TcMJ=ZU5mp&#pwNOI{Lc0(#BTV;Uk9XcsHxys8ocqK3C7h<5E{M}}Kmk_|@ z5^4AjvZjbMv|$5*f_?t1JuH23aFpBdI#V-rmk82${zTVI>gn70pEl-TQKlxGQ( z5T}_m3j%pchGB6u^3uB81KSYUeIFz){n@I8q{V!GEi-AM7nm=ft{r3ikx^o-juPs( ze9zj2H>wTw&ip^t-a0JGsB0g^Kok%ZBqUY3rJGR{M3L?mkS?Wr1VyB!n?dQ8ZV>4l zB&C}nrF)n;8~c5~?_AgK#P|m|56{lE*Is+=weDMSe7OvDFgnIey4U?K>x>y06FrA4d=;o`@dvWhQ^KVc*7jyJ1DDveLOhjs~tkzdv}j<+sh zEwxB}_aW*c<{witdF72MJJ7b*?P&y{ccXh!Z@Nl5MA5r+j&!Wa`}H%;aAm}w_Hh*Z zbxc|E)y1r5Cqq%XIVh?6hK(GL8r$O_k_tg)3MJo?N@Z+Z!J9}h6>VJA~@>ivCal*GM&zga) zQ`ptltBz}G-M-L*_jT$)%c3n?_k}N*#vut0wAwWRvydK(#8K4z+t zTZ7dRbjeMqr0|*V=q zAkU&D4pCq0z8Ho7{XIGb!6~fv^(PW*LfX?S5yO{STSbFquST~&CZL;P#`D<;bHyP{hfNZI{h-gpC6`Fn%#D)JNaI1Q-A8X*cIEKAqV5L z(nN{$j|#1vhaOX)k+tH)9E!N}SjO-bLX<`7riso6$+L zZtD2(a17lLd=i%*(=MFaTyq}5^1`WxFiu#9oj>a-iWEY(r?tzPE9q+XoB!R*SQ z7pi<8VV0jP<^`oPcFd?xxIbFLIkLZ5j!jgj@Caedu+eafZT+%}XASk$u@weoL5X$; zsCik@xN}R2pl*`O?c(kdEYxbj=~Icx?`bk^MG09&p(KYY6L3qzt8PN=53C~-agaNA zjYtI5l+Ygr?$`+8B(R?oR^}QK);-eM(iK27+Doid8ChdTyU4n&X;3CV(?LA(s_KkQ z<180CqAOx;&9Qr?WWsn}WU2~9soV4I&W>_P2RHOP781%PSW_mRY>2;l;9ps*lDFXZ z35`^(-ZignQ`fUe$42fD7FC$6;M;T+_f3qMy47+PEC&tV#WTJZ-ugCKN|J<#@e2ctfYjg3>3_IdU~MpA5bT_J<2NOS-m`&GUcs?P-|R0 z*5xqz{$j;0vE@0)p#NcAn%a|rlWi)x;mGl3N$-1V;yU*7C7H^}@i}U5U~!OHIcMi#YKku1^2b z#$XY^-p`toBUY;ntIL*yR;DM5y+)$2u*~c{XGz8s3NC~dIaW0CjFgd=VqMB9vuL~b zJ@>WqhwM`++U@?G7KVsg}= zV-#Ysdi6`Br=$;)t<&opaq%_@^=e&5ROb2j2kb3lr`~iX*py}Nw~wHzqJ~kG{Vx2A z3(G8{FQN%;XQp|_)2#V6mho^=!IuTq?mB>*(E4@m! zESL61?g_uh)Z?m0BZkF99-*zx%0BAmOiWW0#UAhJq=)OuBN83@oQIiq9#?dw%ijEH zLf%VJ0vH~jRXRXQXz@mJrd1ExsiWj(0P=X?&d?w_<|w|U3u z+k3J&Co)qr{O*EUy@jEgm|W7)f-3$gGkS{7W=%^1t^Lj3>CRfE>H=bf_DsF0)yyu1ztl8w78ZXP_d!X}a z8u?8CEwadEG9ZQ@Y>_D9vaLnXYlS)@fT*k~DwgJS+OX1(@yTD0w_y<|D>yIkn&g6> zRDOPbTe}?X-D34xelNOm)OawBXYl|vmxQq!0v)?{3vC39|SkMLOs$#KsNp2cotnAjybPZ2D7GYf9 z!5Kuj3?dR=cwCZ*+R4SXF?E!;9l~=u)MVdsJ^BV?o@t@kMielPJH-s_28D8*f@|pb z$1}PgA8bbA&Wwb4w%P|mzvq)~pWeVa3HumeBhQQ1dmAO`YnDtPhP&t1=YFr_m|?Vb z(w3@Ae$l&25t7LX(k?XeMvh+~Dny(yH5@raIb5jCH;64nXpFegvnZynMC*B@|83qA z$v)gPfCk@1OmL&L+QS6R+&d?*qcW69r8f1HHirC=@J zc{?YUE}fE>#@PKeRyeP77M9UT=CRDWPO&6`#$icEVxk*3%SiR8D4B<$osa1X9X3O4%9RCa8^t1YAt zqKVzq3YdEoZ!Jv;wLlJ(Pj+X`OiZ1n-B9=Pc4>Up@(a%2r`=&NXIOnwTFYTU5^-}b z;^s>9(Y*lCDa&(tt9PJX@uA~nA?CHhIrm*pTxvRYhjDNUx-d0+9D8hyGmTJB@Q^Pn zr*d}BFCC1|Pdk?yN5vL4Lg`55c0CMv$~QAWTxv_2fv1KGH)GlvkA{fr*NN) zjkfR-okJC&15Tb4qhXqJW&ZP15O?}^F71yV6$P4c868s!G*gNhKJBCH2!QdJ=2*l( zY+^25{~iN6g{E69P=l!PQaNl-Ry1Cwe5X@lQsdx}s?=L%yQdqA^n0m7S*L~M;-~NIEd+KZRuH^?9Ggmb$celw{o@$FYfIhE4UdY?RO?nGTDjz zbQdOXWs#t@las@@Z6kOs9W2XXl!C)3en;WsEbCUWiS=*BPD?I5oYE6jE!*XJr=Q=< z9F;=(PIu0O<5zY(GzEHp%DYg5*ZX2G;aiE657OyB1u;K8k?dywEMy^W=RL(!f7it# zq}{bNk-C^CZu5$#cJ_^2p$XS%*cv1yr4y{`Hrp(-M8Qq|uq)h=tdS^r$pPCjGNM_( zuT$^wOA!VmOim&`h{dkE?6d`TKGT6=uDsBkEbqYLr;#8t>N|yGbWqOkbsH z&lFwIs>vU!DJjQ9F$6$$71Mdj#EO-DX^f1hu@SkXIq>;|zOeczsO}KSC#HBQq%=lS~4 z6SwbK4~4VmCFh zJxjb&yY8x6O--g65xk<;;*=8 zI39X=CT^&jx|VdcxFY)QG~oR>q6bM+9+{}!2RA8E-eoXKvv_LbcxuhNUA1#4=}9gv zE)KUbO(&=TKma`Q*5RASmHXR}kdUsh>kRXP^hb7Y6xZ#>6Y9`O-0aVr!c{?7JxOgg5+0rgTY$-Z z7Zp~2>9Cxb7IC*SI#jz!BFeS4<3@5HYR3KQ&MP8VqG0#^xB{aZ-&^|vK>m*hpg_FS8-e) zeZ|`v<5RnwFhT7+B>rl4YvbeN+nxZAOR-~@tCGtp-xj&UiG4JwR#^(oc{MhcGY_K< zYdQ(PVQP2ijENEiM?uuloyrEf-JC5lIlcA9qXEkriW?-)H{p6YRw5Y>>T~v2*fsYa zwdcrEzgQ`sT@h%0WE4;3G%A<>mcFs7tIgL)cwBu0(O-ffCrFE(bp2}GyvfVgY z$v~XC$L;3St3YC}AE#NSU@Th%j3lt4MgrcUvbHmwjovQLzsP@>Q;q09-ML2D-`v=0 zPlWjlts3lX}sA2 z>Xd)@`R`EzkEft~FXaME$=64AY-p#ebA0rm$SI%cJv;z^BzbKAkqQ6>X(;c~Z(IvX z6txca$$#^jz2Itah+8t7d@E)muIwIcUWQKVPABUyB)*>BiIh6a{tBvcKq&1%RQ(kR zOxxeRY~FOWjSL5eIG^JKy1{8|$_0}Z%3c)|yyzd}7WfpUNy>rjn!c+iRt%G)d&H9~~;1IKQSC*l@1z#ww zCbu*pm3oi(*pDbDnPnDcqngOCwx8-PG&M5}oIYITAmgv*(1Pg4!XLnQK)^0wP8^{| z%0!JrcRW{w5YN?ke7(QrVz3#Xgx* z%@7r@Vhqy8-Ji!sZo#cjZD)8TSSSa$=+KgDZ;fc&wh?_rV({B7kPMFQ*xSl?TOjqW zAGr0jPze4s4t6zxDfRYAmbsd#5ZZLzoz|N4&tI&1_ zUoQZxmi~niRK~Wh_fQH^{V9J|#xn)Oh3@^xu~>rge2^42#Uy)3yRcZR!{lvOSLdei zwfW@86@9_HNJmc&r>USF3>T#$GHcD?pqv^yHA$@DDENZvW$oGNA z`mPKDy!kzX%f}I1^S?b3D_gbzcV0FN!scb zzfbapNt7UpCArh$_1xYK&166^uW@ZUa;qhtatq48LlsllwS z3jeK5i4A`E2Uivmvya3JX>?3?pUruo*YfPc0RO`ra);LHM5r!BcH~Xi=?)=R&M+gv z9(7OrJ5F=b946{*WkI-w%HmT7?nct)88;)5(wJrlq#$|gDl$e3zTi5-=H1mtl6s7I zRKjK>#0;PfYX_8+X?ecF=o=Yi*M1%fzGCNbI&-=e#m%${$B9dv zsrk?;pxgwhzq2qYcT+sc;m!)gsZRYd#~)|aCOi#yjAG2A;Ps;Drjw{A|EDpI5LT<( zMpvdl5ZyPa19<4IeY_y zb~mmYL&D|Bz8~1{tC{W4V`@>cWpUk$8rj=4Sc(JGs z!5Wo^0rc&Sp_x(lf~S(emb9)+7HdpAj@W?J&R|~I2{%fpnR6)09o2Y3IveRC=XnT2 z4LopIDtLETg+HJBG)qtySB?y%mU)+!w;Unx)9%PDo9Id9xwoT^9_JljWvb@3SKk=i z66%NOdSP}e(g#3M4@*VWvFxE~*`|t0f?D1sybn-8kDkBYa2Vam8jU(lJ*8G9??IhZ zNnFuY4VAXs_Pw9o<&4Oj$eP-CZ`t{@1C5OB`9dP(upc~{BAYnX7jk+a)aV>3C~H)+ zG`j|7eC_*((ZWevykU*m?N6`+<<0tm7CzM+PY8h}M26h+y>~*$&_~pV7zBR8x~n*W z8%d&~?B?*&-k^X6+Yzd5i!AwJZzF+0kJ4NJLj>HxR^X|uCnTfCWVtph8k&;awKc;< z9R~ez*Ph$}LQ5{R=&z%3)nsqpN%$x#&TXB=m| zB2ldK0;*imK$T}~dMB@Bg=$LXkRB3+1d>O2J@vpRo(p;%vl2sBT2IlfbJs+R0MDrm z_*dAE!lR$tQmHjfF9|en`6w&)GE7t1IyHAhH5hAI5K+@dA4$!=6wWiE(MW_I8G6#h zAH>b7K~qSZZ%Kb{s55&>!mC4#LJu;P`9$q!&pDPU+V39j-xxQt2$Fj8(FQeK1a`ABx7m}>LKvfS7KV4o@f}$4m4>iX0`M8c7rRvh7pJ* zro-$XP-Y{ao$F-ekdn=>!puPwELv437}lD z8ASHjXV*R!AP~z)+0X3pzkid11qHQt+?JJh%XxC&Yl?YfFQeH~`4hCpoe54qKVPZC zTO+cUs3Qv*YmNAnmfVBhKcU_&JLRlB&&X(Z?iBz0nUTQ*Xh8v9=BEMUxnOR9d5iUKv>>v^=3@Gq0IPw9brUvW-ObTYG5o zq(2j!GLM4KZX45HowA4}RLVaD`2zf#Edi(ptA{p)`$&kF@M`UKHU ztf41?bwTSB1xI&thNswjj#9hveGxH1FUgM0wBk3Hmm03hVt-fR?tK-UFb8KH zRFIwOuEN_lR2!x?P^I~Fk1UUGA0=EmUF1~!MS0X>*s|34;H@&J_q#X3H&I7TBM{x# zg1yxjA|MTm@p^&G^WwC~n|v8gQnZYb$*4@+L?r7d%zKX}ypYb%WB!6Znf`Bo` zs0yl!!r=W27amOD7Z12hsdUu5^cx{eOE>u50dUgJMj-j?Km4svQ7-91nf{LEEubHt zdr2E{j3IgZm}f+>7#KnzR_#|y*xTn}t+A&kirq0rXLLjO=|~_~{{%4tdDkXBxHCFn!`gXd}#LuaI&3(*vlbO)AW~+n;{~eo% ziTld=F~Zg>xHsb!L&e!W43A69`auAN0?8$sztw;2o*zYdlZpN2S;_e_6yCr_%%h$(m zE5u8Cze!QDlXKfGb}idzlj&gpXTV<=6mP+aeNC%(2acI77?+lE1Bfz9AR<;rT4WO6 z0RUPfVojR6g;^+WOb|qS8=8Nq(U9V-e`z2na+_YNineCq;nQONs%JCNK}ToT$}f*^ z{*jJeknBl51YxK&e#D2RLkxn0G~FQ-nRA~>K|G2c?l1z>!C;sF7q{x9(0+~f;WBCYZv!JQontU#WL z=z)jk^x5KPQj=YHzHSl`RX+jVd-kX>q@Cr*MJ^Hh>!_n`&Z*fyWmSRHoR(eqX}F@W z@a?|hH0~pqArQ^?CNy_jnp+_8dIC}vp*)6?9f8nb4b>~yRqp`O?(eX;SL|1RV7j>b zzNU*X1B}SC*!{Chvl{wt+LkDjkOW9kLK2o}M+chXk(TVzMF|~uHf-XD02lb@=lAPc zsdjN%J@T}KXB}wSgJT}?7$1G@ES`O8%QIHostmndJey7|;Vm!Q_Ad0UP`dm}lptN+ zBmKc8=(S%(C9?n$hM%ATYBZ08$yr$mV0Wr$&nEJzw76xlAj+kNaB%H<8^UzT`~Hlr zE7h(Pwy8Cap<~A3GOxD+vl3(6*b}-IS%x=qDV^)6y?V z?ZLn5;u5~jsoiX%Sh2lqEz$4X3aZY1eyrxVAKe#|9$*u4xQ8RGXxC1yZm*S}4@`-}Pn>w0`) z%8g$-VjB@V^goouFLl_~bk?{f|)8-x`)i9u*XkOP2Nt z{(25Lw;spmB^&xO{8c@BSN|$m5Ny_6yDlS5{+%0ynGs?BZlvNrntcRSskbpQ)6LXq zZoH#f{qfh|U;v!?Kd6{oV~~UII_sLhpWVaq{=bPx9)FK=0XS!sz+l0DlCa3BuTH0` zwyruZLE1acg=kwiV=So_H}d`y^LQ3VdUXkQp^;(_-bg=>?H4)FtnfpVb=i_(|I){& zVUu^ov?s|&D9ZhfWz5@kGj1E2Q0EjrK%zS(e2MJU<*K`wNc7TQEAKCCxF1Y7O?jTI zcg1r5)SV?rm-JGH0Zf$rKS6y!ZUxY5jEmx><9tk{iNy3eXJOJr>2y5|{3kRQ&?3C7 zFuUu*qP$$`&xkbqLc6VK5SN#2k#_1Vq{-H=+MjYBA6#gCs83m@Zp& z*7A|X7adpS9!JN%{kg+5`3T7kwrPN4M(F0^J$WpJ?m5EQ%x(?YOV|&KNvb>5mLkmdq>|(jifA55BR{)CruSqzI3b$rNv&M^P(c}AX!MCz2Wz?gI z&M0lcHsB6f%brW%o^-#j^ZrGO;GG1+fS?faSgE%2aL494QAc!eEL|~FmUZ$RYGmz; zLO6pQYBzQV_pbuQ1VB8&&?q}=?siU;pzLF;lun#i`Hn34cauyU*|wY^10y@|B$Ff} z{*Bxh^7hi&*uhy>c3NhiOpid}Uz@H@!{q+P)$;KDAn4j|^O6h>?bbcC^MU{w9w zc0C2;TfH~|&GF$rfiPBK_t$qz25waLtai!}wa<`~n;#6Hs7*rjcC&$n8Rc2#AY1cK zGrs{n-w1)1wdFqmA@cXZu6o?i<;B^v1k3??Buqk69Dk5hrg|PtF+XxS@MYl^e31l?z?!x@=AjpK z|HkH8s9|eV0+i-qruw53gc^tae-#tG1>c3lL=rzDfn$%&8SFsZ=8>Vzdm@bEw4}k5 z)@D@lg-E!Dst$JH5sY$ZEV@_uzdt(i`mAhz1P5MFWu+2!PKGdo+IMuO86>OI6`&d8z(af{9-vmC6 z3-SGg!sWCXfjv?mbc0E!vX2oJ27h%XJFu2GPwfzA_U~Zo((Wy>zt4c`2iS>Vk2A=; zL$_-3cckY2BtF4=?}FMK2!@I| zZl302?GF^PIP1BZh+nf@J4V{nx6;-x7F60Gu;Dj4rX3YYzdlGi)pdNqq{1mhGC(xh6SS>eA!NY8(vy3x%<& zZ=igCyHApQ>9p7+BplaH0q{FZ2AB3OTQGG1!t1)=>_d~-1*R0=$9xQnQ<)0r1Uglh zTrI{PNUNrSQ~tB(UeP@v2mYllYlWP}xK~16k_aaY8W(;wxb|-fgn0+VjhJ85P!cR; z(eSk>cu|xAppSt1r~uYSO~ie$v1w^y)4c%bXXn`{+MYwo1mjp5b&M6i1bt>}4OnQa zIYiv}CuKx#{m?`Xr#xOta0NL0A9E8wq|eB0){)I!kX`QhM2{>^u#2~~mO_tfGkO&t zBD{UvgoNTkX>NTb#lPaRmTG_rC?PZcqk*lE`rV#4tV|Ig(-bqbi^+mXUA8W@x@)&$ z)ilB(NL_-&E4a4m>q6HW^a{tsDx z2kl9M2u@r;MDKLC5neFUzP7Hd9A#Ya;#ywGqlJVrrD9;a@ko}d;N7l7xznOlV{A#&5yrVZ`2{TJ2^UN z>fdaiP_HRI@EIsrG5}ivkzJiTxE4)YyX-a>+=dPf(Sg8t+41+kYga0`_joJ#8?TpHgI5FP;Bqz4P$$%D}`< z^U5b(D@DW(r!SlxlAi;FH7`lf^T`-*I(U2g+B*ZASi|_l$~$C&qMrmA=TtG!3I8fG zpiyt46XH^7zABr1L^_g=p_6mmaZc@euj@BK9{HMbAr7t2y;c#h6*d!mEX^q2{kZvk z-;V^=AEU8!{tU0&VFkuUut_loYbEXpE9&!J@QsRkA56pZu%n5j5pwd6s`<&c+XGIj zKlqpbsDVGqc7X1m>H4dirT>v)z|Zshl>Z+k|F&QO!0PX0B_5H#M&`dN;g1*KjCcE2 zBhFIh$on8?13C^?^jJIT&5|ScDxP5VsXZEszfMi%b09J~cx+1+bU}1EBd4zo;+&oH);> z;}EPL!O_xZfYoT#^%KE%B?Ryv{VQl-SQ>yLp1*h}tWsP9h5(L$|8AxeFIxNM(Kt0A zF!%b$^k!a#71X1SGm>0a0DnBGsOv6RH1X5`kpg5r(=nkX7i`6<{})_*opy**;Q!KA zl5KdBXK>iKjK1WVTk5|jnj3X9`(N1x%QTMHVyMZF5W*ND2RXfg)_#DhwEG{KLtrI& zpid8`+;_Soiq4KM=ZgL@bpDTU`hSjh^330Z&;MzDWl`L;d~t$?1)b&&E}OY29kB|D zbG5aiTXUGB4ZDc){Iwg6LeYP1ATq!q|KJ#LKP6*+`zgpx(0}szjXsgOPG#N;MW33N zYCG_}(RuqC53SF=@7#NuiB_Ne$I7WZcWO5s11Jo8#ag48!I~SB0rAX#+n^Jpjz;c}*}$A<{nT__7AjuO(aR;R zbs$1%9#J`szXaNh1r&N(ytWhZwefk>7)hs9bI!*9S6FNA6IGN;)d)|qjk0r*#?IRE zKU#*N8A9!OIDC}54YX)X90Fh>Z%PxyB20(k18F3=b0v3Gl z!8eIapTJ!s_uzS1t3}Tj$kQ0n+M1holIVm8O4p~)74ojj1pQeE7{0)T@nZUOBR&M# z!BRlMYaRh27`nLO6pVoScnOvkK4xj_uj#mLr~C!Dfen6u=l;KfIBu{1y|jCMz+`RI z9!$C*5}gibeBH{9K-If_*7InwrR3M!P+W38T(q_!N~6WaacL(3UAh6Y>tQvLFI-eN zzPuYKfEhRc9>g~=l=2sqT4p7ctl0M*JokrEk%hvkxWC*Hl~^PBtBaPtG#w+_!x=)z z`K{aD-%f&xAvYUqOURGvcc6h3g0{0weus#-ZFsRqu|+(0+R&zq{Rnnd7+VpA7I{v9 z@BoD5BA=Z90ECXv!R#jhD@d2F!88}mQor$!xkV3P$OFlES3pm2KPK-axGcstzP%a{ z35Ybzk4@lw458`KqL@1QukxP_M_c6C~pz1DsLrz8dY}2!K!h_1-JlI};Er zKfpv}ed7?ZxM(~KL6~G!E$4NAV4WFb*QhN5@q>n_%K2+c*(ZpbH^*(OgN1zjFG4bg zZ%dIX-t*#X{j)vYyVQ4D+zQqbDD2_sP5?*U;qhw09L%B@f=|94yw#ZAIS4=f1CRL) z?_zPZSrFsMz{FJ3~z>* zH0{8F3M@guT7xNtJ(0jLvN}Rs`MOJCG=>P?gokroJeCBuD^}Gv$|6un{EgD?LL&qI zJRP)l*0hNQ9D?8d$!z4*E=fZOyT3a<&ckXya%5=)oF{${=v6s@@6r}ZqvyJu#y{!Y zxC0NTm&yJyGTMlES#TzQdPC>jfk-@_SsdM)dw|=FO_sxigK&Q8g@pZ@CbkguQ`<6t zw&mRbk7C1W3mgztih%M>LF51u&uVe&%pd0_S(5(=!X(MXcpy{3rtWCb4aoV7FZC=e z{A~o@g>x%$)Jh@(to(QOORRVrKP25X$#?UVwI=+V}Dy8Bm-Js z3>P~AHr*U-jIv{DhMnWW0B%Z?^lUSUp8JdsNfH!wgp8eu1yvs}XTV%nvKW$_XG0%R zRc?O4`L`rs(VgiwV49KfTaQ1Y_SkJ_fGJPx4lT-~@SL*BUS5oOkPG$vUWrHoA`CR& zU;SQ%M|1#(iyn;U6x0bBcf}k`LD6#|kQT5jeaH!&hrPbGbe%?0<;`7 zG7U36_aLalIg;}j_x37)@<=8dr%IpgEZD~^JC}9Hc^-oirjR08i#lH204Y|7TXPIg zV|rszm6F83o_hE89%4&8`2rf*MiU}(IQ{xy(rqKrY0_oPs(b?Mra%e|Q53eda0if} zt1kkgA?2^?URK&#P&+w4_DUH^dJdzclMqi%>}dYobsAtLWGyZ(g5eN5St|x>VV0$! zhQMA-;N@%+m=|1dP=A~Mb`_SQkz9L&B1Clm+vZH8?^SZgDUX8*hhZJCd$g{XPkH7v zvYk~I2rh*(FBSM?9d74%cv;Z^QbU0vrFP$JIN7L2pCz1~b@#f{1&n)G z+}LMBS3~|EL)Z2$BS!anLEZ5Rm;pZ5-KDef=!)SyVrc{0o*0-zKSBmiAWC}fTbQUy z0OQnq4vo7f{vsa?tQ)rLd|PODcQ=h>pfeIw?y>t7bQiMQ`vCt~1WY<*S3Kxu^S8zi z{)2~%Pxo(f57m#7e7lsoW{3wO>albTCJ79i#%95M+!S_PJF5{K5;%5RGGLy^M+lf) zk_fP)i=aJ>z=D^5oyxd$>pBn+$mxKRoQqel3l(7q5Q^5FGj3_oeaB2yN-_NKm-%bF zKV*aH;QfVr!^yANIp>;A#F89QODQ2@K#=Z<0lv^_nDjn;WC7S?=GP7a{LW*p)6ZUJ zEor?BV>pMAOmhU>`&G0jLdt39^?cg7q!k?U&%}-CB<8|BwGTznG1JnqAs+Pa!05=v z@hqRUX{{K3{s_4ctv3q;M*)d;;HVj(e~evqi^P}VqiA-*C>2I>=O(!4vsdv%^d4Ej zh|?#wn}^E&42aIV;EE>qmCaZ8Nph+$#8V(;?AORQOm)$hZJmWP|`JtKc#6e5UW&&KTOcl70h#8YA~mwkYJvjCHR z55T1}H9poxOR|-$egwU=Gd+j#D!&`Uw?})UTwn1?lxpMO0tA`e{9-9Sd=^2NSy?ro z72pSbdx<7HIpvPfkQ5N8*6Xza7r^_CsIvxad`Tr?|By6T_nGgO5w#u0lBP0}V8`gq z`JFW{DEkm3IypHfkM!K=?G&(0z3RE`N`eKhA}i~*Fx8EjhI$D*^+ zFm5(LhAD|4l3-KS9*+}y##h9~`MUN6-%6XbU_N3$$<$W=r zY;FPfZdJ-`>t!I~nIGraBCCBymUW{{rLdHND*6^I2>R4IUv9O zWa%*Z*&igVtdiq^3hQy)1+Ik}?XzC#f{ddc(rB!aC2nf19M{AmLj9 zbrgC3)Bso2GZz!LCM7c~l%QwZ1gF^1*eXQU$$B)ZXeg$HUwjUSp^V$+vI#6gZ_Ji) z{39z7)6A(@$rWfYlPpY#PUdhS zql;-Juf`cu#{?y4^?f8htn30;K_$JtMTNezq0nat1J7uak?I75L9Jpf`>%x|1g>I% z3+K`u->Xrn>TUj2Q7j(jmR=A28RKf|M(I5W0Vvk>>WoYKkIk^`_(oV@i zGkpi@rboP=VteC%0?c?Tpis60}ad1zn{5 zN5XkO$r+rV35elVS_mh%TJBtvS7gy1;Gpvw{r2=%X|M7@aQtg1UfVp#Kb3}Qre3qq zqamIr9C|XUIwN~Uh0!>Q$$FwDMj2ZB;myDmq27tirBS7_omF{T$9wZP7;{uMP4o933`F_%I%&mh3Qwi;% z$=?L)@2fZc%KN|Do+#*_fJt*8dgz4RT?@<*`k6{pOEzEu>9M4wNXe$ z^c9&Pzk#Ry0nL?TsV<7*>SGSp->+4I^e@0Tbk*xowmiurZP#ql+!+PFgp$j@EF# z2Oc7tBGr<=NKi~^9s?8U*9TSk1vuY%EgJ@;W=e=sZ`L=NH4Bu>zj6>xDt4|On{-cG z3lby@h%LV{5jR*Kb>|(TORbmF$cT6fH2;E=l(tWRKppSyzmpkzw#qLc0^ivyM~Rj8 zete5P&Uv>aeSm5hx!lvYL7G{wL}bu#+$D4GT5O?}SEx^uN-7UJp^X2F8<(+7YIl6$ z+x3C67qJcJo{VxcT~XRj`%=pCExF0TNV`rNKtmEZN(pnAfaTG&l{aZ~d+z%0abFS# z+r>WInrd8}E=r77k=8tc%~Mn4gJ4)6rf-V?3p_;HA!KHSb~qjPtUB!Ns|?1vZJ)}Y z4CIA+$UkGDu>h`9OmJW<$caMQeHEsS_ms_jF*HY>_rTvRn%^!!uq%KNqrazyvz_XQzwOTf z9&Cx%|NHr`o$Tkt{Xc!&guXzJg{O*bWc}RE-quLp>g+cg19NO_{#$o%o&CZoARs8n z_2+BBUtf!ea6C1#HnBIo#d#NerN|*^W@&F^%OPp0Z*TO_$k67wk(e0vuQHtzB9&z< z#_!?Qo~U(IejH%%-S6p=- zXf?@&ORVyIA1+EW#jJf@e7Cq~a;;!+ImIgEUz;}D_VeoavTE&Fa@R;gtrC)&JSnLk>$NjOi3b!4D^BQXYTXf9z90{%R{y8QJ zmbxsnCjE=INU3jxX>(4&s^j5sk&_IFaid?B`T?h`SKE4wfY~Av%THez@xMsd51}~| zFJ4a0KeENi`B%79;LQ(0B88g!Mku(EJ<;VV?l(<~iI(S@vD&r=N|Bb4E} z?HhAa*M8;kWi`CZZ>|vpzkj2B@$#D&Qy0~(zbzO;i>LIXM<&3(*Atjx8|a#CJ!2R+ z>6;LDY&6a}neGn1>9*|u5x)ClEx)o8N!oQqEH01z{qF9xi^%d`Pj`R$pB)+F+2%!^+8g8ZE5ugnurR;e6!D+$UY&!_JuYyv=0jKoPIf+Zo_QPpw~)K9oX-lD zam;Tj85tfv08R)(6j5EmU48G((QEhXa}kU2m;V$s?en8)#$pN_^~h~IxF}+7u2{b@ z{cFmjkel3+hqhndT=_!v;F{IDWWTo4@;|J(7@u=~RMYMLvB`3zwUt3kOxKyypy@KF z9WjcC+hm4qS={ts>dBvqFbZaW^kex(Ex1-o839#AM@G`sFtV``<-EA8m#VhiM^fD(i9j;26;)o@E$#Q+bwsW6_*-0k}i{7E&eggv z^@|F{CXXxxQYw-(0;3;=P_emJy@C30@LPVP9U8etWBO9Cq*qZJkB#Tru((ziY%eQZ zSL#WkMtoJoHR-|#=Zf+BeFs4y3*Vp1nF*10QU-XC?pe5h>UxoeC>1flIc?uJA8kUW zE+#I)S%+&=NhZcrH+&-F?>IFWBUE3cuuWr9MpF66Ic-E7vktRC$94GyO(Up^JW6UK;Cn9uGq9OG@Og!G?WY^y}fp$*i=tX zZ>Ds!pklzK@vV$O_tlqPB{2}l!8jnm{fL8nY9Nl|m0~Gm@OHs6TsBc*Wj77%*okXm788+6#7U*ZVa`z0**$M-Yby>1=vtwE zBRyvT@v7zJ0w2CFo-@)jY}C}$oWaC6PVZbwar>t`#Cgn^3g=I^{q${E={)*XyNn!( zkCMNAT2g$OZR%)%=@nm!9AWG(+kflAuxR4Q11%E~4`?h-*_kvhEadWtrLbAG*Yu$- zo+RxbbsKtQ`60BqVyuJH@r6i3R6e#7J+us!L4dgye{sY{Y5uqOHUFdg$j+-ySgEZ- zvD+7uylMiSc*D)?uVgJWs?PgcTi0`}c=-5aWA5JX`sgzZd`j2s7Ux<+a5ls?KVJ}c z19SCZ>oPqR3zEf-4jYWpS0Il5Yxg}imgSy7*_p%F{b-mzF?5vm2JH3r+Gd*Usn0dC zYKOYCeV0O6&ZG-?n%N%Nd3EU&^Hy$~lBmu>gxV4%DywKsU>Qcb3BTIh=_oSh=_^a5yWW{? zbdk%E?cp(7jaMuM;bXSo{m%;L*%s4PuAZsF*vFZA9{e@(OgvcD%EC>Pk1vSII$>l% zh`>=CTf`Cke$FP4R-tMR55c$Uc~lo~5012S5_L_uJ1U6S`n!rbs-kgIBm3%%%@&(a zl;+SB(FS1PO)>Mghsyyl^XKP#i6k6k#a4tIt%q=JLBIs0Hc^MOl!YE6BC*T(irnXJNA zDczugh4yK^*w5-EF1KJ&75C&V!K1OD4xdZ6Rf_7j`}kxyuab5ZxRVY3I7 zOBWS+-aDI;^3rzwEgsv@$8f;^@eEA;J<;-@@V9Mel5XTdrCDH@O4m8$Spss0NC4n8 zdS=m>$Vh&}`hTWmEG)7&M#6+C4Gs-7%T#6VB-IbW_yeQlD zWXMSCA^8s1nMil-gviSJKF8L70==VeAzd&(I&Yqoqd0unKpP9FgIWWff!9}3K| zsy9-au0Bq5DwYX``gB?!wS5I%lhEWe49q@Vx%BPp;SWR|$yF+ax#uQz`p_`Ye{F+; zzz6hw+RUkDX!?ye<=)oUrKhJGv0RvP*3^tDcLV@cz!avQ53^z>FETu%T*;|3bk;9& z$Bo8|#nPLGiQPs|*Q-U8bX&?>Bs>KN>onyfwC=7k=G#O6QBa5u7IifTC}gU1N(h*y z`bhof@nyK;(*odk*mUq=%spMg+M69Ty#!-atanc2Wr&Ly%!SuSQ^Gz_DS-GJarqi~ z#+&r<06oE{8~zK|zX9}=9vC;j*GLRy260P3Ubrc6*0T6_(%yM~QNnFH+KA5lja%N_ z4!V6=Fy^#kpIyg-z2(z$c{@gJm>jl_q*mVN;M_2TXEijkyuAH=H)#uVUz$r>T1L)tNa6l8 zxqQn40`hnzThlQ8T|UBt#*D!%>La-J;xbcAU25TOi4Ob27Lj<+DDz{{7!aeBF=MFq zXRPgx@g2C;HTD7eV&$0#aAh`zl+nk7&8`=jYj3$ZDb+S&$&e329l#&nJZZ4m(XkPb zZ#?~H??-(x+k4Vuqu@l2F^hrsK7StB#Mb5CLK#@#2QxLEC*Pi(*OxFZxo)Y079n(8 zMABs1(+;cV1`B`*dg?P=(w87WnAr|YuH-_05)-+t}F3)8#|s>&xJ=lWUx%#Uqu8BR{W z%z|XRWiHrK5!L)%BbC1m-gK$QXn>R3nSKaFnbc2f5ELoc=%g!T+4!F3$!!?hos@7D z@$-c5-3w>?tra-aUM&*b>aAjB&*Lhu6F}akNaDnif*!!A;s-37KS3NdK^JohaPe5LgWYm-h@=Irnl=l+V=^BJ#QD-W6`4^c+ts zq#@wyDB8mtp?4kgp6gm!Ac|LNobSM*&?r-7NSs?cu-WPPKD7;+O61b}zw#6=Q2-vw z&Tq*Yzc`u*;y7Rpw6_X6rOtZ}^WW|CJmQRS(v8&dcMmwuMfnLFxjMJPp%-G_H>zU` zt9A5LC032_is7_Vw!=mHpb|&Oa?p;8!AhjTL?n1l>Iu(g`JrjEr}`oU4}( zHTh9zBbrC^!1^N%s(he2qGHbff!nD0A++{nB4lL#6s|aQ@hDfpA;obmA4e<1xN|q{ zWBGuX?G?l*?$>3ZKj!tSaLbLvS*1@1ZG#bv(%tU{pSZCfe@xzR8(8^&uP~Bo{{@oB zP9?QOyj&j>^ZpkLB0D1%%3d>3;eLQRkqH^udAA$N9yN~mZRo$Vzq0ZFR{}*K<4{xm z%CIrD#cs!)Az8Y%lK%Q>b7);u4s`mq16s+*GA zot@zN)T?0?=CB7fbGzgB@r3P-^WcN#7h;@$@~}To(mBsG76#&2@0BOzd3Jp32{?5( zRWc2FMH`5FWR?(Y2%K=gYQCrcuQX@CqLq1% zIwJMqoa0W{1O+B%UbdcC+gQ`j>X3fkY5|A7(QU5JpY9MnC9{c)o=0oSLgurpMW=Sw zdfortf|xS>mf-7iKlP}Sz|)c9yUo#>tO7Ef_0hXjdIos{}%cj%6_ zOUVrA?emWGg*udoTSPq9%A-kR=dfZBTS9f6%PblrYw8q6%>2E8SMPt7&P@b|n=k8Zxhz_#bXCO_&Gj(6S$o*c~DM9_z zK1)r@lEB!63()a-CQzpgokK^Vt?=xxmwo=Z%HE{820%$b1mdFZTgiM!xmM6e#2#dQ zoB&>g{ksagQva*`wy%B8VABri&Pahb9AhgZ@$F4FYd+3g9hyV?U+7db7v=7E`jVGF z#6MzNiyJ;2nWw0nwK5TVCX{jaEHu5Wu~!%+A%vvgePm~*{m>Xms;SNFJt-0+91Pzhb*W!w#h`U zR>;?QGsHsOLg4SydrA*qOqtp`li3HTMM9w&9hw-!(Q=7RdZAD6W23GX3AkXX<96bx z=!?bUhfICS`?V}*7-gmcusAxb2CShEFoTtLW=XTj9{P1uA_3X8&X2Ei5sqEGuXCK| zrj7#r-xHK3Am?_R1Ko8<)(hHgrq_m`rIk+oTN`?@AO$631bBI``(n$7O~=XOb#-Fi zZCKRpHv){U8VvRutXZIutv9=D4!giM$?xzAb=0!lj4*Erz@`IZ;_tV^^|x7Dy}T%n zJ2URWP`js|>{29_*R|szY^hQwKK+&7iKOt$aHg4H0y2${V|+xz?3*G1IVJYc`)-YE zIQPNZugpy?XyK~nau@~_kFqN{Lw>(!C!F*e4xAM)UhfV=dX zqlFjL#jHZ0prcePhZ87D4FwK4?;T6WS+ac~kjgd3nXVMBezdq62TsEuZzV*z|VXyhfiR zjCl6pV&lknK&DaT7BfcI4{vjH!Xty_d;j>oEC2`l1sQ(*>c4b~A||rr3Yoa?d9RV* z!8dQ?=Rd6I#pVZmUKsM6&Bouq?kgHFb$eNB>Ko-|&Npo%$K5nm=AI7;@e((b^1r(p zqbCUZGrV)m#(rnEPo9)q_Xn_i^-B5{L@MSY{@Nw(w)ckxkQZm+F27v`$DcUQTgdW> z&s0}s#QB{4@y_}7?&17EdqUKQRp$U9aBv>iTIO zl3kGUKEj8+U_8v-`_-DVpy_zwgQJi+IV}J`n~`*){XG%jhfs^!U+c~@f3JsFR-3}+ znJ+lkMh_n88xFN#^n9aXmC7Ul7A7O&Ebs*QlaQx%y z-Q16BzNPw5ro=>j{d!FA;NS#SXSlB-Id8eQGsysMUbSLeXQ=Eo^NHyGZwm;RL083E zIuDvOh|8&KalWJOT-X%Oo?6ZoZ<#)4@#8#6+fpjfza!(ReBRr3K9H1w~KUnvAZ@^5y(g#C+XW>W=|< z6i#41GO{ZhV^^0Z_APqg^`6rmqWr5&ETbsz&ADi#8G54FdAW~3+fsduA^K55(6RX5 z7*|aGzKX_VvJI5O+U8JJbFW}e{k-QE_)iW5Naq!F3V6vp8H0p^r86Xmh?X>4x*+GLM9ph$wh`1T!{rO&9Cq8n~NbAu1jYLdQIi zMreBOo}s#YB%)PL)9!w(=YD+lWc6P)#-bJ`B)Ew$kGtO$3pj&4E!$HVS6=u zwZ}eNp-3}taUWvcOCQ2gZo!4nkJdI&sCw=^y$i`pcJMUM(RV)rvcUqedT6Aq73Dwm z_3Jxxe6sQb zxaahkVJOToNEz4CtKWq{a3Lz$dP;YwMC%(S322y)J-+Ks#ia0jf+L=*Y?l7=Ba27D zmR+^&n9)4}0|K0FA{HbXg&8ToXLc^9>uz65%ZOa0lacv7PnqdD%?s+aS%cH5yyA%< zQ5dbFM4Oc0LDEXc7erav1o|-=?x!$XXy`lj^vW)!sQx9%pf;qTW9<)i&CgF^y}12a zg|ZLquw?9>J(J=!MMtaL%2KY)?ztv2urODF3}mebT2vi0Xq*DVX)I>MHS{v4Uui6e<2(p)dx`slI8}skLVx9* zF@XfB-O}(k!j7~}RfUEPXEtA6$yfDaS<|}lMK{hde$W2mEV`!bwO~Y9f>_Y zKEDetS2r;_LDY#0U@V9jgbH{Le>G9Ie4o79Rg$iiG8=fk6&`7js&Jv?q15J5iCG&` z?o@yr9s)TyQ8=03*yjZa2~vn{KdGW3H${f)X%GL-PCUxmefk4Cu(edBTLrxKHvoaY zaN8u2Gpi3`&IK>Wf&bnbv7ts(ZI=q4VuNYMWG_*(BYQ?d_D6cqWbJUpd=)t(TiXoF zR`{w&P6@n@$q#+^mKqVdUD_sdPdU7c`q3ix4Nds+76dDY zmt6TH$(I070~05GJw;jNn4{ZxR(E*mT738grtWU^Boi&|mCGegO@RzAy*7z>G-$mV zuSp;b^7Aim&1c~D!bNR$w4AzWCol97b*$beE0T8Vi8{AElldIkf`d%S7ax=IcoF^~?|$2OhKL-7 z>Lp;97kZ8B1;xPLaeeOV>h^v@gTs)}9xa;G^mfZe=|tC%sMB{Hf~hBH_Ni0of2p&> z-fBYI`Ov2GjGr=hEj&3c<2REYs;m!=1E_IX!D%V}@%|8B1;sU1qZ=vRwJRUbi#v@R z&OYh4MzRov*WV(g*B5<Ue0JP)hz5?Ja^vmF{WKRdQ&*j8Fy+%1X@9CxbliWxIL)>q zqk82=&i5Pr0(@!iOr*O?YZG%*TgIB2@rn(H4w_3Qe(5r@$HQ6uDw<11sZ#QjDA%Qt zTsy4GWZt}{W;cjh8lnkjQ((k++&k6F2XnZ33AlGUS3ka_VR3Ni&sr!aUs%odn$<8d zlEc>C{t+SB))J!3+q<e*t@6+<+jAhdRMydey?s_fyCe_3vqX#KbDGio*w7q&hp{`d zQ>cHEjelMyI06)vv0hRJJX_1}*RWr%NO6b?f<2J!dXJ#U1AP{Hvg#Mm-73_{)E{GE zYK}J#R7ml>tO@))x0n12HGUl$cmgH+^CVyhOd$F2ljK7AC7{%_u$8|$FEU1AGS;a8 z$3P`UDgSK!aS#rj>G3QD@7T%U(c0}dLz^sN?+X`B7hT8>H5I^o#p!&BU|{*SnP6M8 zGT0{1e^WG$OL0SOqPGviVpH1?Q>nBV5W$(67GSsnisAZ^aSSzgU5*a!RHsAhB&4+# zl_coxtCjh=kjOLzVc!6xllB0<Grpy+qUM_8jZo~QRp$ftsjUdd?1W`*a#1GX_v#jL zBo5`<Pg6^tI-I|u%Kfm*QS?@8sd3VDA}IGP&8j&T=e`Ozbckhg8vbxNO>8iHp$i_` z+vzZs(|5GsJ!FI|S<V-mSqZNUBvao~**z9jq1>pdvY{qY65iZN^IJg+!@OES`*OgP zy^E^e+<mIw8<RrMRq{IJw4yUS!TZh2V)0gm@PuG|aVd=_x?*B*o3rW+@`+j1=DQvc zx$}j$Q`%Z^!eR3*u|)fvjQfwHJVifyGAZUZwT_NHeybkveeMR0B!eQq*~<?VxRWK& z4G1#YYnas{!u^K_UyMvgx5l8Tf{^lV3}y|*^Kre0efGLFcJ*eHC#7b0VDzoNRM2rz z_|Xcm1pItM6U62ssb&)xIrqd`^5f`4jz+5P_Dr47axVs}l!9CQrldUUOE`H6W`(A_ zk_rs4!Ey9}XHC8K@L*{J<l|7Wk@=d@vV0n&{=Q4O16_BE&spx&xe1wkspyKs*uLtZ zn}w5#wI-_(gG_my*6>jJ)Lu2Q0-l96B`u>$1?YfHe|;Nm$}Q4xU>w?wcMnY5#+FU? zPtR=g?sPd3lPz=kl&@dBgr%pi&2v@UJ-?oL^j?FA&ykLy=}k4@%HrwJF1WZLZT{Nz zLPv=B4k0fpq<7&;tIWV5{@Xp<`$R4<J<l+oHphRy;JZWtd~Q@=)ZF+x;wk60Vh%pH zcA;icnnhgVZi-&aE=t83p@l%xunuL_agQCTgFCdBfeaLL8x<VdmUbB*9lt*hdpcDa z)t!)ukL(h$R6;M00?H-(hdS;B9H`m-%Cq-ni6|A6WS!v4C?D`{)fyNv8?%4j9uh<6 zV6;-wDlKd-VOT+(GN0}n5<~yL11@Yo!lqzR3+uI#7jBit+JD#`3xXdRgBd=CQ|jql z^BKAbyt8@)O5X)v0#fW<niKiYysNCTDa^^~pc8MXGDZ(oC8uz$!vG;<8g3dUy0>m> z!j7HACmJ5d1S4jKnC~}DBKr?PS{EoC*(pN(ay&l#kT4WtE0M=`Kz^1p%4Ym<GEZ5B zVVqz=d3kIPv(Y2m7NZwLo$1@XK!}ClPF(A4)3QpMUFFFkWlN~>OuCQgc7Sg|N3aR< zf;i*x(|@sJh{&Y2QzR?-<cTgHzo=b-iv7<Is6)3XivQa=THAJ9(2dWQ%1v2)`|fF? zn+pbQ7em`!xe_RorR{^qRb_K2A0dv&=C7*_7idZ-VeWpr_Ue~dlMPXbeN)2wZC_2L z2YD0m&gQ$AzDoe9HA-xkQ65`6w+?uDEZ&&SMBuz~U1(SPF5G%!n1Otg@*>UfKoc3^ zru|~>tEW=t^m*IJswI{uk#wGgL&5*hSo!b@8utqT;C{6V<@QH7i64tbrOuQ6?lJv| z)6a91YgPlV9DQX6c7T0r6S1;R==+ib6ZPjSy9CvS!`^vU!SBBa#NmjvX@1?wpp)Q) zMxH@nAl2ALg$Khe!b~uqzn>)ANm#7}%E*rcrYI+>T-<t4-%UT4&T()sWvPN+!NPt8 z!G8rFQ~LB_QdGs6e6Lm%%;{02U|{<FvJE-(<r5nLQ@=N)r>6qK8Fs5Hfj(7@T%R3U zGYrH|a1hA%>R|@X$7dMq-0e}JA;Zu`j&F7uZ*FmbdmxW!i|E_$W&Z$tHm<Pn4)(WC zDv1+Exsc5f<HY*TYE`=XDryou(_*1p%#9>?b{yKl3tWxK1;Z4GA=eEJ=bK$&smiJZ zH(j0V*jtJEwuf>hZcd8@tpTSvR-G7u{sXpMrYlu#g;?%C)5JeP4<#n%p(ia8pQ;(| zy@O=hz>ISIEJT!XtW;8kQ)Z%Sh`X^)CDlS5$*Jbnm=`60xYYNKb-MoBoxx9x(!<pj zaf3ZsD*;2RwZXu8iS}K_j^s~wY(D!1>NR)|Pyz$KlY`AXEvwh~1o#})2>1~kp#Q#? z%NRIJOhR;}H~;+j>Qh(S?qpmZak)Kl&(Z#KLAa&OnWNjWT;o@xC8X}Lh6beKY_Q#y z)k@jzexRFdn(-qvEbs{<`+XzyU)_3i;Y{>SXM54rW93EKdBM+Hg@igc2K({RAH6H? znlxiA5v@;o$bY?(R#+I(ZvVE8;fYv@h!C2~QA$d`)6=)jcmsd__-_uqyYlzFap`cE z{avrJ>(0I}ASmU1$gBJ3w|RyAVqV)J^9}DYophxcd(BmA!tMv?IiJA!vce_^6La&~ z9LIv0mh#X}l?v7<@!bx$!q4lJWtwx(d{~UmEuvEjF+vSgb)j>b$}_pOJ+q^=NexP} zv?Ok%xQ4}khJdqD*|)<xI<NX`jN~b(<WrT9*}>xuXW8aWK7+Fy3n`WpbdSFChtAk% zjk7)BN@{$Hy?kA9Z=;~qM@6@dswq&%q&wYie#J4jWUSh8_Oy0c!QmZrFzVF>KX-H? znCaWih^Qopt4Kgj*7Bb5-46i;R3bTGwm8ul@qJmESX%BTRw=Zvnul1350+<jt;N2i zj7R6HD8l~4T%)B@6YaO#P9!_cZ)Mypabi{dVPvUb#VR~|B;B5rkUnx3Q_^B6!il&F zI_1y5e)M~1t1P2ixwot4?BU4&{a$_tZX^^KJaE5}l?CA$MnN^y?{?qIzwQn#Wo8^~ z_U__B=mO!h^9P1;jR9{#v;yd+)@Z7_yrQ=Cq?c_nO8}dK6{|?{Q9qV{r4D6--V$~0 zP$qQ5fL8G3K;OPD)!yG48J2}+<M|4!(?^AJ#V08$B>o+#UKvfMufd=&IywL$Q^Ff- zvW=0AcF@uaBKOc$CMLX+lEB|_zLCrAv&a13oudCPle}X56X5>e=x8u{VB0-OfstLB zrInHKkdr&SD{9ol5rnN?bVx*N7)xcw!=9Ay)mXroDv*?<<kn}0E#%t_UEN~B98{ED zrL9NbB=A?iKUM=A_=bq=fwf3OoWh#k?-$~d_j~j?p`Into-EJPLE~WKE}|LvqNw*C zB?S&k#)r(RJA_?>PkkRf=Q_aeX2?CHH<4Id*~dLqz#pqo-KU_%`d#fZO&GZ-6X`&G znBQ&UKXUbDhP8Y)cR;gjzk%MnTS|LJ{}Pb)o=TIl8}Y4hD4}z7ri2fc#aO*gQ^8Y8 zNCqlxP-U&>M<&xX(?s__R`?4BzQw`I`m+TF7g+sjez$XFvk!*-L?EM94v_Ck33ZK< zvaS=OzLcT7+kXkj%*$vLseZNPE;~np;ifk{SwnO1_L|1;v!O|gz|r2uzcHEukaMge z^R&`yH1*$uA3CZA2+3p1di2LL17&HUIuUmFaO>>mXNU1GO#d<S&mEk<E4;&$-HVrj zoREJ$<N-7d6}`Z#l-w4A9gFOaqD!f(2e-^<$c4w<;zx5<_Ea<yXkM=Z09VV-f8~+= zm1DG^UDTy7!54pXe6C~wuHM_F{l_Y!E82;X{f)1^VOhGBRt~MD92eb6mVS2LgSXeZ z4}7wY4`Qx~&f?L{7ppc1SFwO-AKXO!3kUN5F1u+dPS=11|F}0hrD${p0agg6wnH_u z1+CA$eCYa;S*5*4)QHiTRZ$BtunET^>a|(j+(;j40Z=ivZr<_5MLa#?#X6~@rpweK z4N0NC|DQ>yd+cIHy~A|$aH2&h<-P;H>>tlnO+3`3a=y5}VE?8wU{W%4isS>d`Op6< z$DecbHtjPn3Rz>xl>aJGVKWuhjzP_=!}U=zQ=-w-^H#^Auu%%{)ln4w4}s1@>q;${ zTQ6kc|Bwv%B;2vjY+?Sc8s_HQzw`es02ZE`hz0r<-M5ty<g|7R41!xw8{!|tbwL+l zd!;^nt?HUA7m0j(-wohh`TFn4wD(JCYWpWWuchJt#}ci3&;|wfuXI5|gHXHUKnke7 zXmtO|{U3jjeY+~DqX6uCbaroLkRua`G<a8|KWT_no!x2a8W;7>bDb<P({Q2EuMyfd z<Mjq6aMdd4;JsJD=b8+~ZtS*h6l|E>>QE$q4oV9&u+v1A2%{LLRI^b<MpS#}SbYl| zNJT^d=lDmu-!b|{;naS(UC&|o0ACis{=#+mn>I|YO&&*^Up|K4bN^n|@4(l4qh+1t zlJQ546$v9ne{Z|jRJM`e9e(O5(Hl@Ibg?fM{p2wQ+IU6bV}-{#2UW^uUYLzp)QrY{ zUJCt{+v47}Ba93$c`$Cp*lVocH+-1x@jsF<thc<5I;polLO6o`(tyLxl@}`lxxm~d zG33}{?h%B(td%1b<OW7Pxvtc;J(i?Jk(r>kyT-5E?jP+v+jo$Z#Tc%V+g4%#{MD3+ zkT}i;wp(ro?c?u)`jKC*T1$y`|C}ehmHV)a5eFZqRSh@Uo6Tc1z314&_hCCDdQbyK zR&N8f5Tp*X!DB*9Al6Hp=?%uc|B)n^E&<(e>Dj;9^g*FxiyY3*9?t*3Ou4#O-04^Q zM|_&UBn((85uCmgfe*kLDMKGEAM2%mOkt3ji}ld;wHX&hh%444xmQ`fIRHL`-Pm8R z+CWh#vdeX8>~swGeRGkKsyI6*?|me?w&hw2_bvG%(H~;|0-?ND7cy_<myO%F<_h={ zWc#~6(4qkNd|e<G8Pt^e%l!Y*rz%OXl*7xv)Lg4XQ+zQDE6*+rYttHzQ!XM=7JX0D zenO?X9lDLqP`wxRNccpA?o@0qzR~*+vQ8#rb4@5FftWnGz()t=+k$^Lt9W>fDwV<~ zt}7NH<o%yW2K(=DeD5Vt3-D((zf#k<JzW5eln=xT_|=0t{A6``m*B6g5w79)Rb*=| zvPxtQdzEp*yk%&EdKH*Cm4Z?ARK?}PszN-zu?jj)P9dMj-f@H%u;U{0P%-xIZco2U z_%OSRzKSe*s=Q{;sWG`SaQ(M6o-JMS36jvm-M!zR{+Il%xa(&ypFKZUWA%>1;@;s3 zAol!j|MWX|B|Z$OMGIX*Y`h!l?Zt8lST$MMzQQ1!>5^Kkmz`p?C1k&1Bk0>UgudDc zzzuzElQz^bVy)GE6`I}yjl&ZIE<jD1Kc#G&XL)2j{V2C-G8B!`?ya<pg8Dr#$)FtN zMxn-W1otLg(u^B@a=^Yi6DbAWb+4GWarHWdMWiMU84>PZHca?lEf5!h51@N~c1|c7 zX&YLYqf=hsGuuoPSiwY5LI3520c*m<C)>FZ7cU0q2zpk`4Wa*F^w!3Jg^;e34XtNl zjYayr6a5OUA){TWaj$F@p|{4hBDim&$EJ*>04wsUAe`jmS>%YtS7{YVpVZPjRas!< z-4orvL_uB6>3&|}i(Qu`JVn)Si25cOtF-yywCMcBhQzD)tx7DF5dxkPlMw&3=J@?? z05C(<`yVx30Jm-9UiSPz{|pf^Bu&4gl%4MG9dck-=0SxTd;1dItOaJHrb~`x>k+;h zvWZzAD6&hk?573Y_?P4Q({}lh^HOPqifw?HYI5u@K6|a9tW-DX>`#}_qp2wbf&(D> zU8S8V#{#vFWc)iSEtml3n*<ETCVhNHF>5yW?sxb}Pn$%W4>EM6kuF|S%$f`-HN2Mb zm!l^8NCNl4-A+%&+1`=ulwQ@RO<DBvDkjC&h>!81J~XFO=-MXX+^fCgK-RxB5Nz{Y z?6If$Z?XDh>}u*CC*&D^0)E^tY0=<QeV)OaF`r@isFtzwxSp;wA#6U;E>FqI#MZ*Z ziu=04QI1|=<C_MA{hRz{q|fRtyRj19q-c=VYTx}KML6GO_Em(do?)9Hz2_t_N3uTb z=UJq|MAT{D;>7w>7BZ(@l0;~A&38`&)6!n9X+{+LHNkh#Zvf3P$@PMe`Jwm0cjS-r zgl^%+vnUk}G5oS0h`+c>pdp7p2b4)4Pz9WOF>80&7ux~NiWW)RU+HwWJZJeNo4Zm^ zS&hPw%P+b(_rRKV#M<fnCiKO`*Rz2G!HZshWqW)Po8ayNnIeUg_W?cgwx(0j)VqG7 z1aAIQlvl^~r&(oljOw34i3vv5Os(rmPpuB-dgFWYP!d*!D_m5ovQ-QS_6qy!*434f zk-*C&9mQO;G>gh8!t!~p%KhfkIohf}#0Y@4#cpfTrBf+v)(2_>b=LAXI{!1ET~!s( zz<qS+M;H4SA{!zu0Xh!ygU|FEVl?P}U3!FyZ%Fn5wAH!)bQj-2LX&BY8;3oqW5#ZL z`vuk)fq_dGo{+@`qz&bdR2QGRdiQdj^Pb;nei)BrUm&TtS{4v#vWV?$@y^hzBEdiT zX#iI|<>TVm02S7hz0>35F~)J0G~-&Md}Sj%ROnk(n3sUprU$&zWBQzKPjW_oR%Ivv ztK96iKV=Ha9m<!;>EFDt>8BVF*G8yU9;ou$%woEcsl!_782%{e`>p*1AeU_BT{~U= zj)6g={|<i!{uVQ``<{UTJf{H4OMq76;W`W!O3O7<;-G7F+t)p2kr??-H7Q*Hv`~Z_ z!QI%?7lg5cuG|OYP;MiAMSokQs@mc%Np%+$gDCL-%E*@-*Kkc0%toOc76qEle>4G7 zw^e#F{29qB+>fUB=i1%W&o(=Ep316!SGzmr{9yz*1H>q*pjVm%T_YFm^kiMR8VD`H z&>%2;(bi@m_p3U8KWsH^kK`w{enBIN=Z=L^Rb+q^@09qfVX;0_8mt2;-tbpyR~?Dd zku{Oe;#4VH4N%}p4G(y?0LtQ2)5{zk9LMrZo<UY0aIgcq|5DwL%nuDjzc{jcYx-%8 znxy{X)B>Ti2iT;YVFPFzv7bT7^>9CyDz&@aE-_rrM(NY$<A{<roivzUMpNA+I?WiB z61|Ms!J^MiZ}+V9kJgT$wQRnWgYjP(hp<_vdG!fvKe&QIFc}pYjz&^~9cC+UXp7aQ z!S|;|Gdq{)c%&F#sNv&nAKW^BrK$&=b!C?Ej}PVO2PCG!B`c~qyEHvLz2OGZc-X26 zeZ_fUQZ&+J-TjxEe`LM}IHKfLIVT{Lq_nzxQZtO72Hyae1zsz0IivA)lgAs?mFtKc zt=nnv1#QYXj2zeJi0KSK-G+;m#b1m&YX3i4!*Ufv_5*$pTEC#c-%OLQ#8+$9wlXR| z{9pwN8EsG&XNoUwgxzvb{gB~t%bx!#QP@!mtHldj`2?2HT3MZr;<8^vPT+i%5ulAd zGL+^DIX+EZwik@FB~lN(`%85{GG8a@_Z(|m9d@^=$I=grKAF3$I)l1H9jVsni6`7} zs@8FerHM&5iHQ$4oObpJt72l%V|yyB9i8wBxXaIu<9by_50`YdTtN*bA$&Vgm3c)# z^>uY(ZtK+|-MZ|Vt6f?EfZHSHj^j@u_EzVjn0qY9jgTNRiWD9GADsMvxHOAu;~Gww zF04_O+mAc=QW=&WT=@N;ghCGN`oZq65bWeoOng-5!X-f3ni(Q1s|&2$$Jv=10JR6o z1=90~0L%X>8=$!{b!Sq-<pc1_@q<|P_`NTyFNJ=i&vLu>a0QCS(AeIff<jsQKDGqU zY=FHnx;g5vr2p+4&#=CK#T}^sdD-f@iK5}xdf*8=Ijq(JU%0{SL<^)#A>}lF{cdf- zGY`5~kd4*32p+hS<KnqMH^2M8P5YM%;r7TZ<T<N%nUST<OiaI5iqbt{@bXKf0@oqQ z+Ss_d39uGIJ*c1uN@tqe^>-S2bf*kC*Xde`q=U6nZ;4d-(IsH%U6Kiq5@kqkuj~f+ zWHB@(4tuVTk<pxRdnMknJBs<_A?e=7koYBXS!9m`LNwlI?US?*W-MLna#K4PFS4?! zUaUE0#WOZ6ol>;&J{j5<sR9mr_H*bh_-{%LYcEZlr|&q78}wkci-t|*2pvnW)-AAS z!$DypdB=Q*|7M}mxFKRLB{CD;=CX8r^8GpE?0|qGTo?RMH9m-BmMDU3kpBJLe-Hqn zKsPF5Lj}NGhq-qB`t_S%w==sA-MH)q%uNhb%sW_cXy|O%cbQopFtPGK(jsLfA%8|j zAxH_`!wep}w;9ZhYiE47svETJ@2JiVm*hp%bf_xv9jGv%bX374;1qJBoju6#Ho0|l zzl50hc7|3NM}*a4e5`$6guLQ3KJ&*nq`F3o7?GH#aH2-K)*i~F%03B3vx32tV(w?b z+ANJok+Ljr;YC?tFr+&>f%$C8OBl#84oIzUIdI_<V7f>e_<<WC(#K-qyPb$_Bt5N2 zuL@md$Lu&EY~o%Ha<QI@?oy%ooICvMTt*_67>IPiYDuX}xZaqOsSyOy9{nVa@MWPS zMZ7pIHd`WWx;E(Hw{Z&?V9SUcy!%4xMPfudF9E@!%qemnf}q^zS+X&9d^8CS(bvuW z6M5h88rl>Ok=stalNe^IG?Rxk6mXuRnOb8$9ut}{+PnnFDySY?<yT^b$*7EEyozQW zZGDIvlorYvW50kbQqQgH)8nn}6w7?=0m<71Do=D}3}QOQw<3lc_}7)qj|Y@MgX+3u zq&R^WH~g6a4gr2;Va(bjsk`@i8kDtknGyM*+Xh676Sv8k3ehv(HRlu%3(lyl*O$5# zfXxWeRV(8Txy?z|_2zVqxaIjJKsgNKA&Va<6%FnZF!G}2^b&v%oe8-!6Ydg{>4d)X z$|4IjSWIw9Yvb`jDB$LGfi)y>)KSzPUTY+NzP*(_!G40p4bs_a>r%EU4fB)^tXpsN zH+j~40W4tCckKw?lEe?Bb<Ri1zXY63QO^@LthT=hf9-Mb`s!M~Q@7U|GbQ)=n<6QZ zIT~9|89Ur-u+qeEQj6cDd{SCLDEolgL_?+HRVWkk5QK$`_!6h0+!{*;H=nCFs?bM4 zrs);YxKR#OD@HUR8@-6W?!khOv&5o8m>eBJUAruYVR|dNZIm=YWNOEJQiLiDNo&I_ z6Ihg}hIvae;aRUV<1^%ncXoG4Nu%Oaw~YmY;1ixOmZFnV1dn*LSppqQGj4Nh2+1`d zJVQ@?;E<*uRL*tOMu~A8RccURZhn9LfdgtBCsJL5UOpO{)MKmz6)DxZ!X>yx06Trh z%>en@oo;CRf2X>3ZC(LMQm2(X2t|MmQSQXivZ|^?Bm!4n_5e+ybtFeOH@Ht4Xiz8x zi)n9Kk3p+5$*c?Y-#J?4@vT8vWXvO?N8fbWC&0pZ_8K(wFR2~Rat-L*c#~++CoHFV z@U-zU7ZbQSOjC%p)Cv^i>&hgK^FliV9ZqK)$<z341~xiv)a%;&t$}P6{t?V0hrqsu z`v!MVb&5NS5yw$O_->32pTJwyoa5cD8<?lRS3Je1866@ncX9o_@y*_Wu-REr{yqi* z8j&i5_b;QD7YKn=&=BMKo<0IWDk6cm$3WWdj7Mm<h2GutFxX%<hkky^n6ui<3}|?f zO&I_9go#mwz$D|I`m28a$QLpx0U2+X;eGpfy&+YUA$&k7q(7(d)8|Qw05I6`ZlGnB zf#d9l?g*D=aC6FYqSwU6W>6?|6qi<utl(RvU#foWeSPNv+Q@lxYLZdT4+j1V{hJc7 zXis`KY64>L+P%hThOJ^WaS4F5&TJ^P%ShR>hMSTrcB`A9+~bNsyXz%SBV{Rln<T0B z-Ten<_j4o{;MC1|BbWv0u^M^Bpc$2-dsH`cfO05g#{&ISxsD5P!h~wLcWY`oWFFbr zR#VuxkM}9HwjoEGNu7oeYtR-o0%;fE)RNZ12(4b_KC*2?E<!!JTO)=xsZWb|g-gLf z4Ss^HZU?3RYq<)6;s2sOOYHw}NgO+KmiUqF%S7|pRhceV<Hwy8K?Ke>o?=h!6|C+* zJ!ZNgY@x-2`=oSBS=Bhv^zmAd&Aw{{FTRUirmn6dX~+Z74!3v4+2X=)jF=j1Smt-? z&vg-!ixlXDb;s7)TI^Pg{GwKO&*f5*LXy1FbbF7y-3`nm+}%IPp4_kO>S~)1u~Jwj zsc8E|ZE5ff8hI~QYu7+43%JFlUmbSfAv5=uAvjhlWVG%Q&>gd0P`_p(pp#!h*(V#? za5Ty4V+#b|bBt`XoGEO?I&x;Vlon$pr}An?mELlJKzHw4!gzH2Zdn8eO<*A%#QchW zh0!#vkE)dr>F$X$4sL|Rvz&ZHE;A1X)<v)0mv`vwrStH*1(B_m?SO+?@m!@m?3#po zTWmI}%;Xv-oep`di&g#6aj}cu{k9%ps)r&8ejl|8yrgLe&E`#Y8IP~d56A3&EBb#2 zcnR>?>gQEVh|7~v%%I^l;nYZ5{mXCd&OXEAzx-YTA~PNT_`L+Q4^&J3$v5T_z;^P- z@?S8anoEIyLMo7>qed?8-f);n8|wnzj=zIQRjS7Ch{p?H*VzeGUrTekrt&hZ|5=ch z`zR2}O;viJN7^A=QcF4t1XIH<QNN<3PJ@`HZIeSE{<<%}QUUv~P!u&Tf3M)@QW3{{ z|D;B`-M>K^>%OYrKWFU=U$oHO5dZOwVBO#L+uK_eS6du*U~}|rj~J}TX06zVC`V8# zEMyk<u_?-nN2{x@n$uXnvFZ5KE_2L?qyf@?GD43fU*h*S*!@f4{R@)&Ct~}%kLxSN zNRKn!$D@f;_AgGlTiBut?lWg0f{&e9&&`xhgS?c47zN<DWJ=2Qo?pBMoy57V9lG9i zErN&-ml{b2Rf!=QL`OWdg0tKj-Y;GTIR`vOLWBdG<ErI>HPxvr)8&X|go<Xm8u0q7 z?SnellzdIg;hPDs>qAIr*}IhWOwpQnb>&7FkAn`HS8kgycQ>^+YLGkI-FDUGDR>{# zEPiajts^!WS>_Sgj>lNl<tpH1MBACbrWMN!x&$CKv_x147>ZkS)G`~i>&H0HoSC}G z2cElbHlhsK_s&WUh*~`|Mp!CN7^rb=@RyEeC4Zh)zbW~8DiYzOdHR0vaY(qah$tg6 zT18%RsIBT;$87`LCUdt%*_|R}^B4|PtHtg$zxVKJ%{VJ5b*{<)21<X0iBjjei@|iJ zmG+$$7zY+@?e+yq(Yo8~E!n*9#ND!ye3|qz&P}UcKH<$YWoAAbqHxv;4k5vb+G*8! zMbB0!DuK(icij34R$g$=ZA)A^8o#Y2#k==x_S{ze#H|BV_Go%vcW$;cHUDib#B0nG zaaJTn6Wtd5DD+)qW4ure`6|UWl^laNm$$R{faI*qzjM-1+QiyAt8}b%EWdf?>apXP zA`toy2<fG(p_;mpYsLmVg<BT$Db!C)MbG{ar#wWHWE>{8=nR4&a*CD40WEB_oA8gt zTu^-paQ$$!o!uK~Ly-v9!hLnnMz4KCz+rCEGF$?9@9KC@gsH}nzYbaW*g!Uph)+o) z+N?;0JWPf>J_DNeQX18H9mFJ;8owhln%d06aS3Qp!?bWC!3$t(BJOC3#fzZq=;CE_ z@;xNNahgHNdPv!;q>N_7J|lcwzVOKP^(7$LesqHbZ)jkszFuqhC5+W=xqjpp-y5lo zD-aX%k_2pPc~m~$<+)WI*1`heh|;QOB#mYSRE3sF3#M8G1`5riq#jB-L0ULmFQv5D zxd%3&bY>?wX=z&e>ZBD2tR7O$H2ome&7Cr!&hJNchb17yh*Bwd1k@U%pj)vMOEYqS zBc!w>HeqC4z!I&DFCAQN*~pm_zMU>jE}kaUGyvb$+V9XJR5(W=wa($KzGJVw8Nhqh zmClokd3xoP<zwZjTCo@B!Uaw+yAX!aBxv;oj5=CXt$IZl;p(>3A;1q~EXN$`mB`tz zZssAqDYdSAKdOz}!2hPqbmx$OSGqeJVPo$Be}Nh1LSZhgx^R1w13@7S8+<5RFcKnz zwlfn!%Oc)P+7i3#yXK-gRu9!e1pW6f?+Fwc<<02PhRE<dA>qptT_s)RfalsDXDBzd zN^sJpe8^6Z>wvL1^Nw&OE8Eu8o@m8GVp0^bz#PP*ToH+dR1Ru;vq7B}IrQj2w?<Ji zAX)o~h&aaU?wn}O^7+h!Ar4}Boe`QB`9`%z*!~H#=a4r<M{~1qYtW4~Fg@TTvr-e# z^kbDddeso(bj~KM-tj%eHs_`mv}C)JdrzOK(plbSMMK@p;{J)YE~YD1h(5mfB%|2^ zBBjQo;H8jUhgf_BmIy^zAMNo7{`f$7t)=_D&qAa1;9oYAQ)@=Oh)&*Vx_P7;k`&+| z#f2*2^A4{SPf(D0-@z*hamAV)4Ux>8Lm7cKz%PYLu0{m@p1EG44CRAVB4yeGNi>~8 zk*GV0)KrL;Q;#sbtB}mx=+6{odpa_o^91X81Pg@Pl@^8B+9?5_=Ff6uI=@7Yplv2b z){N$KZ+$U|AQ0Qz5>l9C*N}Jy*W7LCI@f^WY`G1)pTLVV!Z<kg@g9|{HBPT;v@fCt zqpLaR6T1gYk+fNMAfS@+Ae{Om+n<xii>1#$JbGA`g<P4m_74)jAbCvF99^U)Rl=Vy z|54jxBHEnsOsRY<Hd}$=Cxrhj8Q4_}jjs$F8f4}u#K&2EmHUp%+BiOVArG79R|bDj z_%HP5lK)G&XfSovv%<CCM#mtBZF}MeN^|aM0alS=86``B(ws(?r;m7XoaO?(h;z2D zAFtgC)f917d8Hcdfc;rn_-RObZ_wY2kY`BtL8K{E5*{os+~s<Ogf%ulF<ZY&PH?(~ zZ8ehh9?`_;72C&-+j=>3wutP6Y)OSLHPS4C{L71O$}AM9x9hx*XnIcPgM7Z>Gt|{w z{_<7<UPguKQ+5B6;+fcII=0|!llj6jeRf;y2wRE>=80083R6X^k=&oI-B7*rU-bV! zWg^k<3rasVyfMyCXOaOiQn-U>qpI|wU%9b3JVY^C>Lv~A27E~Q(R>z)tT&OZzrVe0 zzfEONx~Bx}F#Y|ky$RL^AB{-7mw9+r2R<ar)Z*>AOB@D57>ER)WbN8BZ6w8AZrmjI z&#j`89vXUp+=Uox=flphxJp|n>+Nhx>s1`Pl>*iMulIr4*CVW7V%?Kp3_+ri=3};2 zMsraqGCHxEDD8}wCCJNvg1&fT;3lbw7?JH$Oj)0e7UhbzkQ6MR4(jV9uy>X4Cg(VP za`UX<y^Yx3LNJScUaEa4&|<`RC@<W1$eXG|Pi+Ky31}(iE85uSrqR2;oFlsJ(VAR( zT&P=tvgFsQgYC|?q@Xp<Ogp`Eq`eu~?7M5(b~jp>&pwpOCAi$FH9|yi!5h~M5d7gu z{i4+(4UZW3Z7U(3Zb0Aze2&cKpyPN`lksXw9p@dfrXotxnH%1MOjddny%rJ!Uy5<} z>C@g}wvK&O6nJ>1${+k`rI0?B^uNhJkU<Q=hlS+xggdCSor-dVl2v+#a2vn}hY(^^ zKIOA}wd@2rgZ2B5>tbCfl!QmvGJ_B)uryhol43k4LDMCY3yoVvizm%S@(jD9>dl=l zh&qx2YRAhg3S$);&B}iRZy+a%xYy|qg0*={ijA=rGv=LHm63_c7>Jkj{3$M=_s$)$ z*G&pYMt7=;g`#87;wcQb(AB^udKZ)^$>)9TYhaZ13%tG;Wq4I|*y?xv`bw;@vEl(Q z1_uGJM$nSq;GE6~q^YzqUVGoKee)@{_6ZWPu!!mm4(AQ&+oZ+GF9&rAWkoPqN>kxU zp5W=23Ey_aX6)wm!>TCZVnZZ(ljkGN%p3IPZqA+`>&%h!gCG;+E1R(q%^{Pf7%YSc z=v~N#q)l8|PH~Uk24K^vn&Jiv+ft{Fcn&4s6rg~=R_83;8qqVm{$73Q{dx0Q<Ed4u z$IWn<!FVN01Fx)YilCMvfqL8~(x6y0B2{xZ&`gwgmRLC+4Vr%L?a|x5ECAkn9cCZa zUF2Y!Fl7U>8sDqQoE#ughs=~m9!2rK%<Ut=0;(9NTdlt_G!Ow6>4=eg1~4uq2qnfw z#P%ND*4K54jd<^&(@A4ruB?16_<&pgUOe+;pk#RDunO_$8BmQ>fK@ndhy?SKpw^00 zZc}|AB_aw}VLx5o0Nfy#>O*~m826(MQQG5_=8VEcftu2&GUYf}`8>ZCEESLO=Tn`Q z#V+1s9w!rHeo}0eLB6E7Y6i-|^t+K>#~+b~A)G2}qDoKfUCh-3^1qm!Y@nvS0ph*A zeWAfp+3wh*E90K{Fh^h4W<aQcxQhfC59IzJ=bdPfC-ipi(fCk=G#(Kv!97Ymw&#6` z1H_hGZlKHKQ_MSEgexC@LBNTlAeA0ytN@9A5mSp4NK)6$1T*j7^I@p@yaL`gs^vqe zv*b-2;0&V=*BKutcwa9lkXz(N(M(ShPEZ5<(vFk&M^R)^kp8`jxE;IHfSa$d^laoz zQHNTrli%EoMTVm}F?0yE&tbdAq3mLte4g0Q2oxRkqE9g~;nrHq9*kh-^{EIcy0ea# z^xn?KF0?|K4t&RNX0&IXjVo76$@cv?MOnCru@t*(6%X*q-Dxg+h&JboNajzr++@wg zVBQh#6nq<)2ttacA<%gQtLn>sV6F9)nVMLCrTh3cZKm*JeSmFi-oR>0W-Iagsi5mH z9*~88gpjOj_1$OsufZ;j<yg(VBYR6yXl;^SvoQ6%SVl##OSx+~i9GS*&+@t789@K) zR_g?|Bsb1QSOv(_uU3MYifXvCF8eYzLhDT_M~6N>OKd+&P9bi(k8ro!RDetQn55lk zoc1S54okvU_+;Yx+N~G*A3JtY+gHeNK5Rj>np?>)$~g}#cFnAx391q?ue5u=QPhgy zg1&lu2n~*&pFTwbEom1)Ncj340;N!8qX;%>E51q4SafO)u!s4^pUC~5w@zQiohZaO z{V}6}7)cgO7-d|3K+vkh3&ZZ@{z>z)QqyOeMq?*48MH5+#5l6892$9vqpwLb71OAM ztVm$xq^5Yv#527TnLz!x=bt$zs-bA!nPv*PIaVvjRo1Zja;?M@ACZ)f^0TH&y*QvI zydA13NyaPS)lwLw)>JKW)_81ty^r;_>TAQMDn)<WsA~zc4z0~^qXUVCQH3n~l%&sc zhy_p6zV;W%nuJjKS~c7i*S!7ki6pMP$g~|YC1k0W_AdqX$_MDH+_MYTS?>)aVO3Y2 z$QVlN_o$<hJg~hpQZKKee#1DARV`w$^sSe&%5!<i4CO>r9s^@SrS`gPRs)%bs#e9D zgRVJK(?e)-Gux!HIUK85!6v3`N~M4J6n3!BLtBTascgsuOcVY*!Sg%hJ!0JbmWyl8 zn)0mDvR3DBh|E4?l|lv=WZ4T3^wyvYWk!{I<JPyI<yh!Gvk)muRqX{Y5AB&avR30w z`TswG7)*>f>AC2h$(==3ZL>G=>xWecy!JBenqe@P(9ITw0C1GQw4$84k3@^<();X} zxhj+o)Y(M*bGXKG4d0}{sgh3Bvn>riW4O(;4N-FiH|4bNwo4RU_lLAx0`?*IE&<g9 zMv@`3IT;G~;@^l<xCdyx4!rKRttB-C8-V3DZW+nJAr8+fO4+Y!fxA1*QDxLReI46f zv5O~7SHE0xCJA$TL4B`Qe>vIT0lCUkLoknIIB2cKcAjg8@P7h<`=ip80zoQl;oBzv zNn)u!2%3opIW<{VBA*4xMk?)%?-azme}l#f4g;k|J0MbIRfZqjHHO7E5mBdU$_}gC z%JBs|nM#0E-+`5}<(XlWAv$K9j#eKim3s&ub%zJD_B`8am?p4=tWMatMVObs-X_Ry zVPo0+E`N)}*trC@v&6OeF7kGcndAE1u17smpshn~x7vkxsBATth#O!Lh-c*5HWDP5 zF99JKyITyqmjHO;iKX*whAgOUdSsHFoVl;7GQo9(o89PMV3CTRT86k&Se%(p?xHDU z^!y-2S#hG{#$rM0dox0it-2lEt3eVbIiwEO%s1Xx5rrI%z59gAx^k<b4yWo=7Mf~6 z$B?(yxwakx0s`4d0Br_7=zdi)Sp@DSLLnd-!v+Vi+*NaeNEW&#b4yaIS}!P`1zrNw ztO8F*(rlQJbw_igKyR(Hq(NGF<PpWL3JykU&=9abR7Gsgev#E1>5Om>c%Eq8Z{a(` zzdsaetLP5O2j>wzk~P5*-N`)>2e(hGj?lOt8;f8rOQQ2H&a_JB^N0A>f!ilDsvgum zRkZPt!}C4cgT5EefX35F;1E8M%d~z8sD%D^&I^}}am=H1p8jqPu_8%vZCGm=J2J|o zp6#BTXMOjj(Rn?!BV->L=0hIYq(WqD8n*qT!*}YJi85^}ut@}DES2B9?ZYslCBA(k z_0I5wbE1^G%SJh+z(gYZ0oDbU<$P69U>Ke@<x3?d=vcvb?GnHTLuNAlDu3w?a^p(v z&eAP51Fap2Sd6J<*nQTm8rpIPrC|Xw%!hpTFEsI^fFbOtVv8lwP6?DFfka~CZJqNi z<e@nFYKxG_|Ha-{K;^MzYvO_6?k)-LP9V6uyZpEXcX!v|7Tn$4-GT-P1b0Yqhs;lI zZr^m@+w-Q^dh=etS+gpusDJ0wsZ&Sx{<hRUJRdSyDhO0e5|buC$WpB}q$hM_b!qAB zeT^rFei>|+NU1mV+fK;@0|9O?n6O!vs}v|N%xu<HkW4E&r*_SzdcY)Kr0LSSADH`( zbGE=GA5pS|B%-6v21ZiZ2qf^|=m5<FQB9AUAu8vfg!UM%$@Mg8HMZV&oA1591nng& zXFKk40ywShv~GK$6KMpQbr~_4cv-M#K&dbB;^v89P0Rc?q{cYAd2`%%))r`~g~&Mh z0d$s{hN{4^lc*X4Q@>K*&MNk_+|+d*idHr~&zn_=&7gld8tfCnBxtPRw!~$D&+4H( z=a^aP*iS-#KJ%1#bj#jXjg1}Q1#o8FdH^N{Hx2iZCM>Kpte>4zl+}Y^W-$=O7&C9x zy}!b+bWlpEOKXRs-I)?MVPmy1ZX0?<<rF*`Z>y}SN?vTc??<lh*F+*Rn0_57Or03+ zarQ~ML&a<(intDq*p2~n3_brSj5xA}NlFyI?(1AM<<8!BknS+)Vn%4Eg?i3F@d0|; z&%xs`jO%0h0$yH_PhOzxNbFC!O4B=LsC<m5Ut{>vga#|r`j>sHhlAhh7!Hsn;Y(K| zV<)FfOAMMMl8EZP{B~=<=}jT%3C3mO2(5Oj4z4}!x?S7)M3a%i$jq2BHd^Z!*qfS0 zmK=}DSwESvJf&;f#n(J}ucE7L>TPmzDl&Dck&qgsrq_RqMW!uE#CqUqsI}l!&i%>E z0zb{KhOT~RF~#_<b&>jozs3STky}>`U?69JGP({IoiK1cxP#*`dae`ZJIG;_{C5y{ zTz0Z?48j*f^V`e%(Qc~K00xy$!^ZLgTM7|HK0F~v=l%MsF(Ij$j8*u$44kY?QA+Q5 z)dUgFc1c3IbE963lu@4$eZ?_uyxH}nL&9e`^(f;q9lX8R$&ZSw_4Q8YLtRJHx+z7l zExBZ7#c;W+-HzCWMYOl$i9LrnAX+cFG%{9gc3as!7`benoJ$DRS+?#R#h$<{AANj? zbW*D(U8=b@vhKuMc47?Gjc}_0rarqg89k{^-`v62u*EV87}$ony}`VlXWmZPb@+PA z^C?p`Q#A`w#l>|uIMa4;l6sPQ+;ulPQ?(TMcN=)@250@<ni>6yxC}I)|E8exeY5=z z!dWp!_UU!iCvl>=1-+PHGA}E%93cXJ=BLfb=?>A22)AsfjgDXj4S05~pbDsx(8hOm zS1FeEo*Et|4cNt`anvcy5uGwmjj(GJ#_j87pGn9fXN<0Tyz#!}-!tjE1LbV9nJO*S zcD`0!X<~xibcKfUe;ujFRA=mj0<)9n|HiYG$WT}!zJt^oU8)3Mc_U)<$BfG?2@rfq zpf6?ZJIU<e-*S{1A4^b=hI%n9evkN!J%Ii-@0axBKM+ThRNw8_Q4+#9FaqXP(mXr7 z;Bc1f9i)Xk2PQGW?Ns-i;qcUWZ~$-msFUHxU?UDHdvXf1ittP_Mnn|Xcag+78c3*w z)=F{64(g0Qdi%}bx^?@1*}=!-Oc>a5`JZ$=vHe`|N=Gk>@jVk6lcXcZcvM731`4Wi zoHx!W2|NRgH~JD2-yQvK!r06{ye%o*Uk^1gR-{%_V=cr2nlyll0>?S^1c-jI7r$ON z(|d^ZZIwuWgfP%(GC@-G#9k=kYr$wNNAzSHgi2edDm`u{k|3&)(O6Odk|ThtV5AUf zK}nfGP^f4XsYo57bMVe%{i0Ihf6%|$yHUY=zTk+CwO>3&JSpKaQAV*+r97eGt&b)V zx@iHf)?~GM_WR6FS7q}cQo-QlBtXVb))FTIV|+?FmLV6sEQFOZnJGG9%j1LyQx7gW zDg{@QVoGpnqsX$vvp4`sDhMf0V{divH6+>$lqO~7Jd*`u9T7Sa-7=$U)zC8S!5iq2 zyhmdY6D&Znt-i6u5l3C~@Fvgt&3d6;PB$nQU05z@MluHcoUGv)9D2NcGzn2PR_!Jz zs`iJU9UQpLw?(xLKezECFmN?DI1XpKqv2bMi`Y}Y!OL52>K+3OzqDCp6$kXZhQKLA zkvB}uYa&JigIDY(nx<jqR3D6kc$LL|2E=R#=x@2k9!GTCq}i;c3H-Vm28BHGcVdn( zl!@m`Boq;NxdaR7KP(vLyoeDW$f;r?*++olOA=Fkp(n-yXPiqA@)_GrT{CwML(3LK zXrdo7NHAD-A%@yNB{vSQyQ9RXcf~}QEU9J&AJlID5KAm7y($zT<Q@Z2%vIi-dwuf3 z91$fWXhR%eUzo^V|3bkih<v6&PV~$l>Z0xjjOHNBRyZQL!D!v&avsP?;622U2w{?~ zKRk9myZrPGh4WSeF?Tk!DZ4|wzclhDNp*i~5+*Q?lOWmDOAx{(&>PoBD9{J&5~x?e z492-<u_AGU?^hjWA1L*SNw*u?8dsmVecKO-Nwe=fn9>F+JQd0{R%W9}uJ<F;qT>lt z03L3!6=dB(U?eez957|C%6=i!Xemofu%A0sEku;3Af<HFgF$26*0<!ekq9{49ERi( zFT36SadBF*JAXN8C(+S-G7H8$DWA&_qlVmwq0pv8%GVCZ%ekLIT<s;%@sJ@AARPOl z8ZIu?h?4h0z2Hfi<G}N<FX#P3SgnSHjm;%V$&OcdJvc6%5kpcE7D!W<nNvS2W1K4{ z6tfy8VcnW<^%~|xGcD=hayq@}{KN;#SMdz@U4D^fHil85+atFZjNd`rR%y7)_#p_1 zYHF}0Yt!3aL%%oKc}V&cXu2Srx&D>-I+hj2bO1tmW-H_Q(s-z^rfT?%_&C_g@;b^^ zel;4R7Ymo9uEsHi@VQTTHA->1Gz~lwf$5htOY2F}!##zpcKBc_Mw#%p{CG-DVvcqv zd1#(mp0%Y-`X)ZxXV`J`92G*5T+d75pN{P%*2xY{Fti)5q{7uP$>A7))D#+80nL~A znvlCTqLB)t`fQ^}-~$3tW-lc(e3V&G5-WO2EtSObCC>~zoltpjTwTSMPEfwXI=(Iu z>fDrMN`D2}G7^j5@NcUu|L3au)xx`(4;ETIGr^V*HnzYj?Z243IzT_(!?u2=t^n}{ z8Hj~Msr4IH$ggD1E`|4&V=ujY@eoMAgS>dJIoQ?w9R$#IX3WGs%dfH9v#-_dh%ROa zZVDUV*1LhKG#gCB76@QNb9P;XgrU=)QDow6)<pKygUK4!0sAQV^k!9ZJL=VFrcl5- zg*BfU;X~(4;C|1=x|>ZqhfX@Z3}zwh{}~~GSit9_4fDTv*Tp(Esyh4s=`)_2l^t3U z{J&|Dinsa?Eb3I2^VPP%l3jEf!)W7W&M<tPh`26qQY`_tLw<ztXn`eBqB%GebG>Dw za1PCY$6S4YCNe-pSZT_atjnR<jYqCQ#P(zfW3b%id2-;BJm9M5Zhj_dVB6?QsS)P^ z+M=;>^F8J$uB4-wW@e6H66xbObunB-NweLLrDCfH-j>Iyj@{D0q_VZr*nio_C--F* z1+|AwA@`V+Q+v-$Mk1c4Ux=J+DS;m+wy*o(-jOuA9{sR-%xE667zU{>KO59MgIHWq zF#WBeY@hIn*3|RuSzXhDo&&NS#Qs&3B+L0J`zV}DrldJ#Nt3F|x!9TxTCAtkX?Y3B z62HX`O(8pt^D)y=vs>-<z5UZh%ZG3&Vc4D2ks7xgq_?B`6x0+>;(5uUaA<)HjAR@s zfH5X7tnVQ2aM=k~NC4TXG`+9Z)gON|#byXk(X3cfvKb!4P<P`hsq)GA*!Y?CI?`H8 zOypL2HNIX7A5%-6{%Y@n`mN}wbe&69#?Y?^S|nO7Xo+052ohsg{<Gq+bnX#Rd2Lla zhUEIuX1JVURwM^(J&S!0MX4VWprdReb?&YzTvD6bHarsW482^sg#5-a+Tv*&XZx2$ z&wzn2Ork>9x{KRtyL7xT={)Tk#wsTlochfpIImYIm6;Lxc*?>gzX|%x)bz4Ud<O|V zCL?iDT}0v*g94}TV{GW(oJcG<qYwuxFEgxbV2y2=&wD$-LsgUq(jYMG9ql}Q>%sWw zsoS%0kY{WVFYSF^ME`UlunWpQ9J~K=?@-;HdY#Kt6gQ-lMqIPd`tyYRLmdO`$N}}D zR0_wZCNn9I&HhW~K?(8X3{6z&>Y;TX2o@jv#i+^xb0mGF=#A+6ND>j@;CNF}4Orx> z2?%aR>Sin&GZ8ESSN$^MerXq<{W1NP5RI5~_%_lm=XJ!ZgIvZ<S>8<0S1!r`F?5hv zwy&Tcn0IUM4xb@IIBWjG!D~}m7!Mq;j|GFG00!5b8dF2L#Zb6AuaC+UnRP*y`}b1l zk#Ed53}&w4$Dy+7C<O%##TIgFZ0zM15h#K8Nl6x#>&4!AO*3(O&7?-lYDn?`sfGN7 z$1kI}xUu~`@gw+S`HjiE2o)Ao4rSOdgfygY<h`tsTjAoyI-G^GuB+CY6K4zJ6rw~0 zuD{@uLe;%yv*)ZLzSe5voJ_@`kS32N6GP*KqlELr+Qrd3&?|DW0Y^J7tqJk5DDX)} zC~sopJPArSD;jDEOe7iC!me+XYq%JaX1}@iq)+N~O@Z81ftNNVt+DnPi(6<GbWD*= zq-Of?{?OoP7PZYRayHS4QFSFlHLA*3il8qR$n(9)6s#of4YVXPl7Prbk>_o-r(01w zNlK6T3w{Lpq16Kghs`5h{Reg6rnmU<JwcLo<dt6qIA`byWVjoYF+QY{!?#uGw}jJS zk*34+9AFda2e707?N;86{7KAx?Tn}XCayke=npx$68iQYSKit`m`&0$VG|G(5k_L} ztb=2don1(MRNsWJ0x*;2eV}0TIIU&k)j$CRa5YEje;9#?D$Vc-R%I-s=+GBS4M_&b z5A0{Lnh928y?D)cCUd9T7JguI%WNMkd#}bE!GF{6_Ye7jyuvk;O!6lRd_Q_r1BYW^ zKd*WwNCnLM%lsf&;hSERhs|N3@nN!($Ot4TRKg@F3W*|ESiaMA@0KIMnS+MxLZ<3@ z3^s5~TFR``LXlp4S^}f-u}qzI?z=Dec#DB6Oi@G0EAh;XJ>DeW^3V1)pbn@J1Exyf z!K-WPR4s42+MJ!~NX}%@lkZP>qtF*;9sEN_{Agn&2MuKnyE_@PJwbZo7SPX<v>^I; z#LVNWT|{;(LP|2iZ;x?_mZrdUdgCK$5)L}Akp7@H>f>MMQWbB)NH*$86Ty$RCgJqK z4P|8`nsuvBl6>=uFZOw%GF*er@qM7Oi$D}lMpH1y7n#QrX@?J_L4?*|Nbig-VT?Ch zp*4QTs=@LGpmOVsIINntlW|vPlRUD3&9tSb6#?D!898NR%q;^kaD5cBr)%!f!raQc z=qJY;(6#v^kcqY5a)(-^K6qh$s`^X8=`+H$)^R>m*LsuI?gSDZFKOgLA^Ft7KWM8U z4dLI8u#iRG1Rlnag9z^!0v<{u0B*?89r4EDA~I&c2eigJU+WdG!+V=%-?=eMr@7`R z&i#A>zAf#G4qZ5JUD3X2QraeceRENj{gD-sk%L`xQ%frD54`PAdBLPDJJosfYCQ~K zv8q!+vy0^eh4oPzpCcH*j$mZ_mE(xAD2t*#-SYtMd>?b>JGMSl`Wa)p%ov1=El6+> z34SbpZOC@J<T8*Yo2w;UXo*gFW)=_N8mTZZ?)1-h8D|IW8BL=YaMW8vSPXS|G54j; z(tj@mr|2BNUiX8UWPT=7et1%;-?B=eftG=+&^$s<Pqu>!QwKH9W?Mnwt?kp%I6>Pc z%SBWpiBI)Tyev94vf_Kn9J%*iFJ=mm79e8ca0O#1TWva2CFa>irU$?X$`|&Ae|Sg# z4hcn{PDsZt#M3450b?`+ywZn_bTvPVKJLAXV-ij2;rx2p@k&2VT#q!F7|>1lpoYro zvl*Cm#W9^k-mWfFT0G1QWAoL^g5f2!htQ$9jvH5xZ>6JrrE~e6^Ap|5nAqN$V^Ah9 z<)*{>H^_%@pwum_%qon$DKT&kgM1@Raj{xewBfyK65%b!SC_;qe-jT&T01isjqtJ% z4{DUdaEWQb%;H5SVTMtMofVIq!WY=sDvk!QPbmNj3ho<*j3BJuLC-dLoYxk#*lB_p z(CAEeh-kz5Y+t6DENVGyv1yR)kk1MtEp_1eAVro4^rR9Q1w-sl7>LG6!ApRhcuWkp zvDWC<;}P@m1%(=bGX7JzIphGol5}uMsVq8HBFA>AIefD#quDe7XMt2dtWi0!_xM>6 zLB#g#zK;f)Ee3jq!o@p*c8eZp0;O{^ciyR5V?dR<lRa<?qzaA+n+&{TOPAP1ce2ol zD5nMrv5N=Jic1q7zG(uONH6?!dKDGj^zR^Kz;$24KAI`x7;9|J2axak4$?7+u{)FK z5^peI(pQSNadv01-x+;=wi$8jbvOAVLV$p#O~m}QacS>bYI%8-#?gxu3s)wJG6&{y zm2I*)*EDA3bG6jclrZx)X^1&1xp7V3YT9?NSn8Y6LQ7UcjZ4O&Q!A6dl<wrFR-$&Z zYH9-uMR8hG;ciz98A_||J@6*B-_4u?gJ|p_(q23s$pbUQAemXjW9{P|#H%e(50jS@ zCS+=;^737jR1;VVhcri5`uZvifEU)6SH+F=n6%`ip5t!(YQV4ln*krlcj<#T&O4V3 z=8&1uUN*``DXZgHt66>BUzITZcuuA{<*W1+ZBD(B$disvu(mR;><f}`%1%q!{tH3W z!npY`xBQ=-1Q<WLu~MbsgDaWOsf;RFy$k#+z%MPJ{m=>j4Ot1&PZb#BwvKy_mKYps zloNfw)B}Kvb>z9p)Roy`PTVD*OlJr+=woI*N46*3l)rPvwd7z31VFt_+(nk114G}) z<nhs1VEIHm0dtAE$_~|Sra??R1dDBN@R_7D?hjZ~0)#bj#XhZ~{@k==?Ui3<=Ddr| z&p|y~cWe@mMosqzBQp$iQo?Z3ED4!q<2u4Y5%G)WnNa8&i2KYXupqY`@h^fTe|tr& zrw`ty^_9)kR0Z`3cb-pzQz%LZQ(GHv_zM8=m<1*nn0qr=)(&P~;Tqy4cFG<(qT31T za>C&iB*X^?nBuznT4MaWk55;LrrF#`BBQPBjuO=aVVtAn4UX&+VH!tw7A0ze<p<8{ zjPFf&orMI=2Ai>S)Y0}NW{zWHlhH9mYu;CsYnss1C_XfO2XSh|u4Gx^+5Ie87-ATe z9iNI(qd$ogW{-=IPNLTTQcyf9D>nDIh7lniikY^Iv&PmQc8&5^vHe3@MF+mKbn-NA zH(&CtG<$kh0ofY2>Sq><s-o=%!AFx4)WodEjhSU`vM}s;$}RL`Z`|<-yrddwH}RMx zO8Ivz!{JY)hE_?Iya-1}gL>8EkviB#v$isTj2(W*5VKuL_)Sd3aOar`Hy`Ds><EaH zsN$$Bo?!xIJhOtj2oa{pTt$TmE8|Qo^v(p0<8`5O4Y$HN!)R@E!mcFey9V;U=0*1s zj;!m&O~P5kV~R<j3kN0Ff~Ic0cM#vfR(S=}l+`*Hiyxwd<RjatvqhYGS~ho^BnP0F zY8P2)@!;GNBIsnj592`}QosHpM#hDoy-0N}*ktzGm!Jm`O`0IbHhL5c6%Ez~6_f~I zMk3_R_d-z18fUlekx-mFdUn2WK8bI#Jx<%Uta5hw$9hwVj7LuVQPhJgOP^VPi&-AL zBj`+9vS3J$@DAtQ`Y}k0#UV_UiDWhtLm4|rc?sQNhQDkAl9O*19P3ivvYN(oND%?k zz5jE>`)`4tC!Lc;z@1b@?BCD>;et(MN}?n__mHxBD~YO_EH%X3E97t}Y@$>hp0z79 zo6Y3uEkwy=%fgX>08Y|WVoe@@Rs96I<V1}w8q|^@qX00?2y=$e<Z$tf;VH!LAhY4r zam`_Xkba>)2}z(s(s}xE{D-)-&7x`SqjqBFCDz>5T#0w4s;G;rWsKWFG0r0cey?5d zSD1iHRc^3Q{M$jEXsDdH`m=5_dPG_F3aKVCd6>{eD`sn0i%vS_<E|Xe4#%PnJ0ktf z+Qv>CFPJ6@ntChaMB-j^HcpQ|!=ZqdQXH3Rus#RE>tT3rLVCW<m5UBNmI-*2F}h5R zvyrn0x2RW-S1z>#@BDj5T=j44W$Iret7tvFN;)Nw9Cr1{)Z$4>n%vInJyZDyl=!!R zL!yk0iAQ_q1Q)c3l)4!%jH$0imlH-#l!S4+IbBC`Jsac{iNs38YZ*+!coFud*Z75f zy(5{NFROrLIc3h*?k|sgHY{9ikihMOa4_lS__g6<iRG*JxT-T0jTA#@sHl=DbClkN zDAD-oZsK2bXfaMG>7J?<E$jj@c7BevRDTFKz8M>T96UE&IvJPBejCH9X{JG0cA4#l zl{8+f?CG0?t-Uk-*BSU^3cG^hyZQxMWEgYris@>_$GI={x)~GjWbcnoqYqwOrHsrk zOxn)Qid#@$Tv&H4c^L#dMSTa^E~;Dmn0pc78%+`Jj(D_utSKk1wrLjf5+jm2d4-uY zt>8LMg+b21QxsG#BM;PKv!<BgkQP9u5Pjbwkji*tOxjW%J6{hzFcg|TwlH%5QzdP` zIzyF9VnLOToKj{wNg`U;HjC&CE?h@vj9Zv00;q;c$XRR}rZqn@BERUQ<6CK;LcgNe zKazb%m+nR8lr_lpMlrh@R(i<6W<RNgq1&~;rrcNFDX$4v3<jBPw<_neGxz}GuT1EN z?m(a!O0$4>C(}6v;H6W?Uqk8xJsNXTnnvQLlXW66C?(HcP@7{jAW!Alud>XB(<2T6 z-xo8c3#RqgUYKhzpd1J6f8EKHLV=U>DH-WfA+W^gUp#jd8V`(U-`xdMXD;03F{SMx zK&CNY<ks&PT4cW&^rTO$81EXPM2<z@?tRglk<=<p2yayGRTQ4LbA@$SUe8UF?CRKP zkY>tLuRW}D&w2S)wxOH@g&LvGUlvRFNb9E2pkEJt3ryjFd9%F@RxVm4iZqof7r1Yu zXC~w0+o$<=g&UeSpK)M`2cl~AaBC}GfGfbDd!VDP1h+c6V>gZ8c+Qd+ohrw=1}QI^ z-@}6HxANHPHC2Y?30e%7XP)2+zdLC1v{-^*K4|zPSVX^34}NVR9uj6$bzARKm1AU8 zs$b1ftyeL2k_7|VrQM&mK2BW@V!0))^;RxLmj^@me8B#6BdG*5CAbQjnfx_qpRN9< zd5<R11O+qFF9J%F9Qx~YL!zVeZ^OE11qr1yr)lOD@UdRlCwx%BE>d$~5$S`BNwn#L zDr7Ixp#7C;JtGmK;N(n=<W~I)NY=o;jXn%oILqoQ<k6}q?Et$Y(j<MnR_N^oQBoE& zUs#M_HnscbUvxd3PRK)^1nSIAzn5gL`B4t|KbX02a4rt~wf#TJnF!zqF6_|t0&n=E z&Wwbgb^Jm4?J++p{)HGeWem-OL$tVl^hf=FtBCpc#{GI1b4^-axa}jb?aYY|lnbIS z*Ya)yYLeN2!lx6e;v_6WZBf=#cKkOOfM+tw@rfON&|}$1eHq=Bq_TmeT0n7)Vo)K? zm~Z{98Q6xMG5PApe=xT4;n0uwwJ7?d<T+{au8H-2h$9)Os3FcwF5B^hIATJ=XPH+4 z&)|p^wIWrk$J~oI3_B?|1}Lf6^ZL}}>)8)8UX^=vhhYVYm2U%>m01!U?+jmUQM>ar zjD&oO4=f@{@KZx3({MA!M)#1p91yF<#!_1En4jo1d{7@x_32|0en*W}QV=%=&w_e} z-=3*y_?fd-4p?0jQHObrS@Q&xvDQntFT$E515{@rT;*4EnH@``G}Sq*TPGbsDq#!D z%GRkcUs2|^SW1SmiAsQf3sR>JNE_mjm!Yqh7B(~v1i})0q&8qWiZZpIAO%y_XZYXr zNW#?~I3=-Kt6M&Z2nEEtyAv4jZ5vw0^W+_pN-TQ~{9G@a<C}Y_W<*EkMkRtFuw#r9 zgQv*@_8E<CS-82A*^9EFr!>{$1K8>7C*lNbh8G4fO!I<d$vVMqPKFoWbvK5Qyx63J z<0IqS{pF+QgYXkJ)e*aNej?QW+yu|U%H(DYW>6Xe?g3LmzH=({q~^ok#RlC+6{97K zby*PJ(<kFW7fF^vRic^&Poa(}m?(v+P8!~i;A%>`7*Nuz<LL?Lc5w{wJGa2+1nm=2 zQvtK@L3_cd%7NP@vMPwQW{KknC?wH1dkF^JpbxAiLs#uYhg_eS=U`AqsD29#0@<>c zR^)IHTrVak3llnIl}4Myb%?4&9igJ!1qDXYH-f8rCI(MPG{B{8FGjc)Bq1Q+ERgX` zMU|}qLau=K?EwJoH8mW%+NY-e;ZY9lm+G1<iju{pU0WJ>iW|E=z~Wb*?yQ(KKE*=n z`)wB9S=JLCbp8PQi$B0V4{Zsv@=dkSeqMcUX0ehj-?!QUz9PaU6Kc&`j#&+pi!PQ1 z8h(Gt{us^t%+IjWyj|3tA^G$qgco0<6D7@UA9CpI^Q-eZNy$~DNlU46U&m9~7{)Eh z6X@7aiYvT1q9ynkXXljBZ6|69DJ8IExPMGlW=zkL1r!@|`#x$}0>j6(h0gdNbK<%r zmf6N=na+u=Q!jcz5UQDw^f7|D1Vp;?h=L^j8N`n|u-8-n<V^8BigINY29zGNIwUa1 zmxfd1ww7Z$YtVhI(_S&no4rCQI2dIE{6cGOnR0f_`Fbe4G9Ui$LUz)r_|e`!wT<Rr zlqV;|RsDx~)*M<(St(*nL3uQ_oJ$LiYDfL<m^Z&Fu0Xfv1D=ki{HmB%{ol|+t;u(g ztkC2E8Z%nrN|ZO!8bh*;K4JT;NKk4A9D}%0-$9UQk^>U8y61ALq0lwWM%C0(Nx_C~ zu;B&;r2A7?<A?5J81_esUh^MWZ26p>*?J1_C_4Ihtk)t5>~eJ=Z*zc@K53DbQI5XX z+}kCw?*SmxgE{lbLG<>u;>eNL;@8&=Hni<7%mr&H4>>VR<KsJqG*rJu$YW>2ko?u} z`(WD14z-DGb5YmOJjYigdc3;#^;sP~XTtqbM3UKOVz_$C0Gn(6nSA{mUEj&7fVrs5 zj&QA)Vz#pJ7sVjr)&!^GGuGEp2gg`8*$v1P);L0A>AcSAqrZ1|J#*mh2!~3hvK21c z6))M>zPD7e&rfXrY5F)Px|7J^zZb|buQqsj$ru$oVXXEQrI!rh2_G2DR!w1)>?-0! z6uXda7Bsr<;bJN4ZUpW7IcB#{8X~wKIzDFgq89d)06dFf6WhrM!G)Q@5Mec~0DEr} zPc~)sFx<dBHFddt8bV0or`h0lE#O(8;v7{^cGONF-mmT>{LvzyF=oOeu`zUPmIW<V zvx>?#sJgM(a@;s+W$ezaeQu>}n#QUalA!g*Trdy%I|#jSGpA=H*4IAcbGukUFUhfT z3Q?8$x3?_-7>}g)0VtnFG`swsc=#>l-&M^l5TAYl)nT}*j;E~Kvd4e1J$T<%M}`a7 z*QZ$J@&Y3`ASSB|D>BiTGo#7mc9=yH)_Nh&#wZvRUZd?(=U`*J7VElW4oU#?!!G~3 zEC0uk?oJ=1^&AuNee=%a-uK%19TV~6N2!<q-t|q+I=JVUdiD@iM9aZY+n2o9+1eVI zJ~J;OkX13^f5I|zf;L)qsS8?WqdJt4+B^~+QsV+!q>ZruypW+KRndVtD;%i~h_=QU z&NrNH33rp#!JMEDfugXGOXW%AheI4w9@ke4_l}r+lbjMV8Z&I|`1*(rw>uy7Du%5k zr?(*aKJ|urtmWnK`zyF|9t-2Q7&(lC3xB7VJ&y=+FFxxhp(-<=7xIyKRWg!>hGdkB zw-)A3r8-<e2^!tQwnep57LFwGO)+Ynp;}@~kf8h;EQELPZzzHAqBU&X89kL|1HplO zjGF^aDO<{Oc)oMyFL1$gtR!6&Z8hO_=QRFB(?^q$#Vh|?F%OxE;*7ZY{oxeIFCU<N zk1v+_XFq<KAZAM<pI27vbowN5%=hl(;HP$s6Z0baW9fWlp#K5HI)&+Xkp3W03>4$0 z#P@m-szV<O-3{}2QC`h70EDq>MtX|Jp<XFrO_8FQ8K4yPrlcD+Z|(Ha&R|qpKqhSA zswq1eqL^miw%ScvgltMEo=3~LFqj#I3ZoWyTtbDF{dr;aX*uP+c>Hz|>`6x)bv6Vp zxdWA?wVBY7nb<;(P*mp!@=m6FIB3jcJA?BZ)KKc8C7o3L!`pDv($ayJHgmHRe)S&; zK64g%1+j;lzj)m%Wj35!mOKq+l;vHK?lh?VyA;THNda;8R28Z<?;y~;anhH)$JPd8 zeq9eNkGtaq+nI0o;oVCQ2S(Q_3@5!lRM4rL^#mF8by|}&G7N{$u$&LQKC6M^ok8@= znJt$30My^VMW#!Jzw{lh@5jognGU(<Fc(RkZ<VNvb@z}TEUoO1t?D6ot(}{Ob;pOa zvGX>Ui&hBNr~2<~x0^sESdgx-|BzG4_2*2ve)dO3A3$H7)rzfjqB8FS1a0AsVVlCt zD~^pV^;$|RdE67bAh^;<1uY%<Bc5<FKfVnPTR?tgv}a3o&kkV~nTLw_Cg7DC?{Lj$ zwZ*x_TUI!1Jtqz{jTxVpOs{O2jeD_+U5_12xKL|6KTIN6z)7l~qk3ye`ge|sQOt_V zH)bb=vPx+!TpNht9_v|osz0&}R|@EnX?<D{mDdmJ4Q}iMJplV+`{$K=>*nK^c)I&z z9O;uJ<pA<(9u(&FC!f&kzk}2P{WDt!!WDTM??c5VFMo+|SmII7^^Xoh692;Y><R+9 zXD!|^o9JNw?2zq~-ep*&C!f-zS7lS@jGqLZ#sUn@+foWB15Kq$%KDer%odJJz$M_8 zn$0F&0~`uO322e78`8*?%?{lnRu%^H*<q+9Cy|*=kE$%FcIQWX=!-LH9xfd|NNZaa z2HIN(m|{3y1TAfH@ou6>7SiaauW$pjq38NiuyC9PCU`$Kj^0}jrg4SbEfZ=;8^+Eh zyq1GuRLd;O7LF<_&W&RieD%$*f~5Z(oCgAptXpE_jLZye2Zpj9@>2uRPAXHe^h->I z)G32JF8#hjhP|^v*7Io`h8vKGNC-p<MJh>fvKcHqLgu=ac;Z`89D$5I=h2^0GLG@M zWx3r}p4%~9bKyMEGj<INw73U+I5Hdd#7*=5!!T}AlHgXsBrx^97_65z5~ry;ubu76 zN<$cu1n?u4IzBEy%um#`&T|o`pxh;f0K&=wk1A)rG{POkrKt$Z3;0h_AdR!@&RBK= zW!r#8FA30>-To8<G-BTX?(V8W^ZGPxdP+wsNo5R9_`?y_q*8QC!N6)kXSpm7<S2L( zw{W`i+A3K$4jB0(cjo7X-z-Ge50rN4%dc4JsHg{>l6D}}`K(tG<UA}ylLi3&iss$p zp?=1;e&w_?<*Ij&CI_VY74vnuuuvscmX6Brr%=_k)nE_n>v2gF?$m5^TB|SSl@4y) z2E^P&r<W}DB!m=Zp{aWiK40>!f-Gz$9>odr$q$@W3?|`=U~b>pxwLb6Tyr1=4a!1s z;vGvW2E!2Bb8)aju^n%WmQq7888|Gr<;r~oy!R885FL%a5{t%|Pb{-g#}<K}$jwHX zAU?1dtQdbIB%)|G;I@VbqB*3>mU1U0CPY<6Y`*_CV#5(i&oS(03=FSc*~{|xpVMI3 zJd)>BrQc1aG1==50zc&UV$n_W*G}ZhS>EaM{sP=w0ccHjI6l8P?L-fgITZ>n&ij&f z8bsVP2`C<~#eH_SnoCBY>NiDh%&Q?HIC57VP8Dnq`72tj47v~%26~Q)c@;1;YZrgH zmsolGF^}NFMiS@H5YK!u#UB465`8KBVWP=4cd~4Uf~jyP<ne?Y5sId)R-f8Bg?LS! z2W+P`^4RF(7nzz%4SY*%Yp>i(HjAo}5Q`mQ4C%38LL20-e!UE!X=0iA?Y#zc-$77& z&ovf}r)}P;F~lFdkeOno){AnF7=ufyh-s>SiE{u-AY5_mikX{%$8HOauN__r)0xN_ z{b#PW*Y^pd#cN6M>H1EvBk3E-UCJ%HPGe?mdMn@TPa(E3go0m`olg|pEyfQYmE$Tn z&T|YGrT`V>CIF=%AB(n_M+#{W5sZpXj4BOD3{hlONMxxv8M9NE2`ZLHq$MdL#02~R z5_t-GCpVWwd@YYCm|u(^c~G7wyCcV?m*l-~?#W$&`J>s*l$SO9VDZ9qPlEq%%^4LG zeskM=QsF_Zizr?W1F9VVqG%>wGc@r|8=x9vP*R*YuV5|&pff+0aR$xafp&Voka8gt zrwnPi70M!4Lm2m~`_{Ow6<>gs)_45YA0!Q10>#FpD{f25mzzJrSrQRD*ye#4MSWe5 zY#90?k$h~0(~1=H-ICo3&B`ibaTzsh<+BWMb={GrB?ZQC{{RcyQ{SklQY;<8B1VI^ zCU58oT&BSTQ>SPJJ;m+46Jv5C`}fzgy^NVCM6ECY^`=DC^Zw(h=~@~cEeAC;a^i)C z7p%L+MGU2byst3lMdy&2NN$8LnICn21CBV?*4pBN!!mPt^$Q5<C2klzZTrS~o*hMD z5gO&lEb<uc>+#Ae@wiqF*Lf0|mN3P)C2fA|2eteqbOw%P@k+==Ch6AsdTN(k@2TbM z613tP26{9{mXI_HtP8F4AnXUIx&#eoRQ+QspCNM(r8ZoRMR?=d@2q9N#FWP3aN&(h z_5L~yJb7|N*r*B|wy~5$b35m$hI-#yKWqkO+#*XFwb9K5vm_`rX}Z$-RANW+5W(JJ z8qt(gzwV&!;-dk%16*hd&uTlCV_|&&jPMBH*LQq2k)ITjDCFO6lc+zv13LJA%z+7p zgIb7o(cc8rmtXpXfMyX>yC}P}4*SF$mR}QpJA!!UYPdVr(^!l709N3AYS6S<Z4oV# z3M+i6c(|MfKMRiEM`ifSm|lak;p}l&!?$_numY!a+4Y&C2e9JMUtwj;-w2waJ=dlU z^`Q=f;~R}W{B<Hzknm%Q?Tx3SzESy)-od&yZY~Y&$@&4^I$bemCokRq!t8K%KFlSv zpf~v&zNZUD6A^n9mkc!ZeA8twT2Jf50Qus>m7Y(tWAO)Lii(+N4z~T?((u{$puUPX zKs@msMD=F`%&$lrk&k9}<c{NKrL-`|er;51WkI$`-JA%QF%+D~jA>lW6ufffj3xLX zHF%d-j+kr$pR_)w;s>&C{MvcHY9hq$fYeDP6%DE1S)b{p(0hI7x*=^(hFV#=hf`TH zJgjS>TQY~rve|&yK6!;Sz71du(C@SJZ_bTp5RDsQ)H^-BwDml9V(~cQ5R^+3%(pd~ zRVx0qixMd}ZJ^ZuQ^duy`FL%BOEpEsIs+J@3zU6)pC76|ZHOH~>c!i<Y$WeuC19e= zsWOWyAF`cO=ABk}oieiF$1&*ciSPi^Q3%~p;9a`-Tfo=v;SWFAKj-zlD=^)k`y-Ke z<E_J-6K(ZUf<oyVV(sDPW<d25j;3PYE$It8Q1b5}8PxI-ll%pn_E2C>S~(xKLw~C} z_xuT%gikf12YW_en+^Tn@T4NZgx=6Fzw}wt!pf?={_ifI^9Gs^9{fo!!p)K_c?VnP z^LuaCo%PO;;YZ2UU~ojN&-erI_`zMQ><R6(qN=N+Y=!CM3b>9&G5U*+h;cd3C)cDe zNh;0s3Gnm<F=xGZN^v*_NlavEMQ5IzR<9E1cXFxl_}@g&{aG3XaamM^>dgSTzmUBF z2WK1IJJ__Ios;H&?Shi|z-FsWoh){`gC6K~8>6&?y4_ig%iaGD!u{@EL~Ru5;4fa; zK3BrQ1jutjf&u;8q*{3v?<4JED->8qM4H7uQR4gyr1(fX+cH=J=2+5^txc_Tvntl` zKXv?H568bkoe8%1^a|(s0T#~>tdL<H9%$zH4@jj!>w$l=^E-^KC#50YaNoWC4r1~+ z{p}mZuQ3<TEScE?rS=EVC-Sa+toLA?WG{oOypw#2`wo)VxljMku9iWqK^j3ceQ3Kd z)?jTQo52442<QQf-K?u${?sQTP(|I*Kt2xsm^A{epq40YxPfPC2O>M9?2+A5T54RI zoca(k>*-NHeYUvWH18>Avz#<_Sc9w#@&b(&^vrOc#~rnVw35!;{3fuv1geuZ8+FKv zYvV;(rDJS^zQeiROnLHpNd|4~<!AKH8Ox{gzi5LwwUyb5{`Kngi+jE#Nw3ay$KnYz zCtOIIS4n8BLQHG6#wDdb@+G@?7BKx_m~(p@fFO>;V6KXdx7{(zAku9PA9)*gYVzbS zS@;9;T^1|K?s7ey+>Mu97Vse8;pOy)=faU|6_W1g@-yFDBSSI4P5U9}8);SsC2G=m z_eZh=_d8%6+~b?h@gj{c=+R(P%Zr;lSb5y|HN5;;JPt_Ys&W3tL~CzN^9(USx8y8e zw!6&B%#s-{SnUKO)+9>Y9Tr>UWGN(YLL8`vpy6Uu&sZ7jQRs5)X?qBkX*-CB(#y5& zs4Wbe&?GX6L7L3@E*Q3}eh2Yqm6z`)?>Hpuh%?QpU+67wm+w?YCwtepGL}@C(p-P} zO6SdC1>fwO!PjTB?7>e-yO|i?DnF+%dg-g0SwXXNNoE$PDo!&AA2j1E4rIvbhM*#c z?TAxpU5*V3f9`JUv}%XkeRmRH>x4HOr2LsJ`hzhw(7qe7=f7u=$zwCX)&~lI;6Qv< z9miv~^lRYPBr1<l8KO2suX(u$`9F`K956Nh`@|>F!!UOPoDzKSTWVit>k{41T&5qI zruM0rXsC?isILmlq`fH|EV5B4s>XQzqR_ay80kt^F#?khiY4H*3r+R9qJd&m6*diC z!^x87$@?dcW6+$MmDK+Z^2%F`@aQ{;m2#HUidMqhu=fA!Cza+)Y3J+kf3$*QIW!sP z0!7<1m%V>UbYPi~Zo?7*C0LtG))yE3`jD{|uIw&WknHQW@k)6%MPDdXBF&nsT^@#M zTA^8*1)B(px|Ic|g^q&9Fqv%Ncu_EzuEL<gcMu_K_->?mC=Nwn3O;1rX{_b;32U|8 zzP-7u+1C61=Y%7_f}W@}YBt2G`)|*j?T965HDq4>E#4KB*#bVH_U!q@>Ci40xykJG zjMQ)`RF@M!o@O}_RxK5TAHOBsuDW8LL@EZvwYVshW;j%`=8+?G1<I&g^SI3vvbmV; z4i3ATj7)ZwwY_2qbHo>KF~B))s!ae(PNrdlx5BSt1-^Z|hp_a<*2|j0{Lmii*@%pI z<z0ny#J@=~WZD(AX&&!->k%-@#*Uvj|0uQ_hj)%*AeF?O;a6Z$Tz-p-A{i6hAj)W< zx(QFB(wRXzd)*=`Zj@rN^iaz^dG^J-q+^t5lBOb4cHilrJ(yIuUF!$<^<BMu^H&*x ze@zn{L{Bn2i`C+fDQ9p1r_CQ;#OMe`_o4q^Bx&7a^7c<M+K*|SWAgkPTnMAa<^A0Z zdFN^qeDH*)n-=+2aKGk=_x?5u9x`Cu=rh`31LY@6#fpVO?P{4;gAAvBuH!JrKa=MK zj#~mhJHj>`U|P-6eJ;{&lxwxlc3SywCR5L|;jZp}eLDRkDCP4PE#kY*U|_aRy4c1D z#i#4rte1~x>M<Z3&VK2lu-qI6!6*}`6t{2N(QbGZX^1M<hBsrsgD}5}68#Q>T-4ql z{m<$vB*2>luCE;r>g(|d_WC!m$rTke;SzT=lKLh^V(DokX=%CLQ4^BLFqp-$b}I@> z>%-1wJ|dwX1#^Q!XZa5lBZ488Qt+HiG(V#j!xM{$Cpq=5EE+T?l3k`Qh@o^}zX&W0 zYp+5n`}7%7&-epVXq6^DL~oWc1CAx9dXaa?tj@;Z`L(yp4_9i<DRxnIY9*qdc|!v* z+LXYkd}}DR`r{<4=KFZ%9m{dmaRc)TW6F|K7F6YWK~`(1zWTQG>G>@Mic%-?)KVs1 z^A3PpWondpn=CM3)d5wxfn&R(>s?|iaV#q!_ha0rPSu}NCfWfCr|N$7$7^S3Vf04J zli4v#^en8EN4P_?tn~(2r(s<v8;W4U8_KBzBoVPHb1YA&S{6#cFlF^9iSvV?1+#rn z@C#4<Xw^98FWgM9isEJ0LRa|-BohN%&5dVnn3_tO!e2-75Zen%><rvt5kRoQ6U^L1 z3V)^XNJVogOv*uMAv*kzP8o76uH0B=MJW2E)9tG$UvH9}`&v85S5E1^g*tmkwr*(u z6;b|RAunEC7*FL;jE#r+pA`DXJLPq{t&E)*W?Zy?#Y~NDO@fzRF8LlPlMv2TC%|t9 z5HjPYfL@`o8`W=Fdv2-h{l$!Drii8Ipw5t?@<{u}Y!eJ7w;?KoULjX}SS&khOw86Y z48o!L32AnA@ph}PS8dC^RW)RfdEf30aS+Cs55vH2PkF6Z-9KUeoCZHWPqg|*hxDl1 zg`7MS;eJj!3tZ(Cw0Zr(tKQ7(x*guxH~!!7JW|0A9vXui8mg$XAz!EYi6&Q5p!63m zs}mBIGCl-QBX$b86GnUkZLvg<l754)r`}S62h-nmnKq8bEQ)1wN;6<-W&jR9qa`di zboq{kvkmG#(&DaV+S_ap>s&zjJ+43r9$3}uMA|qaY1@Po);w6O%~bd|4j4CRT-IFl z%WQ<+J%5%H=l#?l5?!~btdYH}$u#k#UOj$0=S9EY-5QIu=*&EQ@rC1-<;C2sBgjlV zaz%5M9~FN)xEVuGsudksetk#c@9hq826+p5Wo>U;1lyPJ$#9-(l=&s^(=MqHZ!Vch zzn79=tT{glX0bRM^JL;s6u9R={iC)SU)?5JN|3<#`wiV9$#|p{6duN9WV9Z0gI+(2 z>B2$#q}b8w<b|faPMZbK?;x<9ZGR}WY}ZN9UX{<Ohd<%DzWsfGW8&~B86-n<o}Bv# zT{gE)zJoj&?<BD_=a18w*-NHsP5<&kCdv8L;~7GQg(u-c19i2fs=-1<f3<eFK`TbT z6K&X$Ci*`iV}w*2wtOZ~r4|v|-}vXn{&ct5IF*%AGcdaCFGis+l@h#YQ?(G^;B~5; zO1OpA!Ss9Gv=Al*In*B@?|BxvEXvkH@l=)UUhqXG2P9$bYF(YkFCglWXVih3YcdUX zSJI6XQY?!WMvn*bW}%G|(Xi}fzb-8oERw?c4x)h1>M5@g(pAsjP&?>dFrL_x>M5u} z*{(;MX%<<{t})lGt6l8NRnW2^X&T)ERehm)U+1gIuvD71KrIG1CFS$^F&7w)>i>h> z1D#O>N3@^H|AV7!mvcSXsMPWBe|tROjCFFNInDl^Ui4#)yQsv*lyHW^<Zlse$J_3# zEqCjYj8BzXjtL6@7yU#e<rL7K_`K*d3HQ<28AJ-)t1EcU#=7Y!!h^hLh`kMFcw_4? zS&^qz`sb|aC>hl1=NUGup~r<%)wpizx=BNs!O|(4t@!oRaE1iBHPS^e5sIg2>{$+l z!f-M5+fDb<=nBvx5>!pLoKmNegPY7q=MQ9LO!i$j5pxdw$jC1-xZ$6`pJ(CiQa1oa zamT)d?oT4J4Xl=~@s)azHXkP+YY(>_zzY7sR<@`f3c(!s5;M#}I+lEEKZM;RED4+b z08e%C<Jt50U$b3oYs5Zv`kgZDXU{(>CCr6stL6V&p7Qun&`F+^+Ko{Nubd#9whn0X z<%NxkA=j|RcoLj}ULIB}1wqx&T6kU75cB5b?9#E1f-2i^tj)N{Drfe>n!aK|<xPn= zWnwqxw~?tG<{akdJV<lRz(RYQVXed+R7X%ktdY?I!aC#HKXLEx7L|v|K(E_1rRDCI z>zB#17Lzn%C>y4UMPvR0p7Hk91f_U2*j_AtyuHb@r{+@y87&1oi)fO<1d`pGNRc`; zsBA|jDRhM>7@r7dNuYYcwC4|Amx(pZA}Pt}l=zrQ%ymbIICg2iGLHpKJ-bcRa5=o1 z?J>^55-XgQe~Ei(TIEOiMu^LNC)gXfD;S#R_2Y{_l$I}N>xgp?9G&dQz9kHRp8zRx zd7&!+fLBaSG`4G(SD_TBHk`9=_=*QQ)!}SUult$|jWt<LP)b*>IA>o$B|-1d*WuDd zQAsfYKa;4YOg~{j34=js%ZjQum3YY|cWVayG(x)w6}gDkl<l2GDVfp9#WvIXBvf_B zH~hQG2RQz46cXp=+p`H<y3hv^v1((kqEf?v`0J<F_uuXi{${26L!DqnZ>anF6Map7 zBP$KkBwTNkzh1q-e-3V?@g-gg!%=|tKnp-xIC%A*XJ+E#P(G2VNgk0AIX1F%ssMw^ z>mgf41!R_w3P=(`sdiBPJhuquu4`yv0+4-mhJvK~(E9jDQRZAsWSK7opdHWxkntQ* zM{o~bMKDo{;k<!SWc8}}*>70=$w5C?c-EfRKWi}(Kd~YhM17aqCN1AH20ed7>?Z_@ z68=A|EI+u3Hv-U0!>J3A;8x}fsGiXBJ_jb1{`8P^OMj-j)j8}9G{uoWN&dI|)}gpx z{m0QL@#Qt&cZ4$Pr_Hv(%nO81GF};kY;$HvV|g!wy=beTwjUxzvjhpm-|7YA)g?d; zFy*B4OXtT2>Fdtl2J45r0@r;sfKS<MroW7-mt>?CK;ZD;7LtsmQ{>RKa|AjJb{i}8 znL!U{Z_TPu-pd-a1{)Ura=>^J%PRPs7xVtp4S;V=Vnm*zau1Zw2j#C%w7jctTS6DD z$gR_NeUC9Jrp*89R5Ozv!sWQ=NOH;!bQXVfcux9IHh(Gh_=Zc=Ef2n&1Z<h(V;Y=# zJ&7(*BVVWyVzFIM?2nJrRmX~gGVb?hu0b;&<iHmrvx;+y<UZEK8sKqx|4|TYZi-0_ zVwALB1xLvKI0iivmxtiTJFA{-JS>Y;rDOb<LAu{`*CXz^yr-L1P{dW>cT6qQ?5GFL zdSwA;@}BVGcLZ6FxW3=U^v$RZ$ovuyjX&VOMfWF~tIv}il=F%#_zoiY%NP+H=~{Dt z>?Oq2vPHDmatIR?OGx2KdX>Zzy&CW6wzBO%Z0-<c?|O?VPsxyyGhv@(0wM9~+}^q= zRHvGG>B|Qd4A?Yeo|HVxJPCo5KlCVd86st%{rqRY^G;-4RIoFQp=WL_1x+~1fcOLm zT0Ke7XBYDc&U^>SwRzL*!k|2!!G#62k%kqwP^dDp!ZbPD`{(99fBN^w0tZcq2`ib4 zpvJJiTmS-B?{@DX=3{C)zo6F2PZgayEst)8mxq6GIrFX0?|{d3YTn#b0KDym_8QkW z&`&N1tzC{^z$;GhoqY~}5Nl^Yrb49;CgA)s%$;zaIt*BEU1z2^x0DCij7x$T3rY?3 z8&dJ&#N_QRHbnIM@7|bFVU73~_BKxIEg8R&;lbi3uKUO`TvENwQ6;SZMs3qrL*;Gv zfnFlAFrM$mOG*J6ERrmK=poigN|bF9H5|6x=kXRUd3}TUtV7XXSDritRSK$Rmwuev zGrwSU!)b@t`JE8qYV!}2KZ>0G((pDF{kGwXh4I;kQF;oCYWr95Utwa6ciw3pEngyk z4fq0Am&(I5H8mvuj-De%%UF|kgS3S>I?R=5tO1ckRZHR;)reAF*o=j7r+1bcaZFCk zNf$GiqAAkE+A!gA%RDB#6hWK<^||5T$h%39oY^qOV}tq+lfmR&7?odBl~-6wTg+4) zrYrXIwPz$+3lf~Ass87XLyQEhtDgMxzU=Hv@0RaYV%F|DK7WLI5<J}vZ+4Ta65M3T zi@EMW-{T!54X|(+Q)c`uTK^oDyRU10GIvMaVyU^-fY$+|?}5^DLmqe{3A>hv*-b<5 zr=|;0^)HY$06j-$t)1y<0RD=v+(yezqw-?=WiG(rpYtyZi>hvicDr}X-ld)M-sg|h z$2ti2K%dvAV{00UGK`KMTt;uOnWHA1$8Usi-Z~BCR#jY13jT_Z*qw8$hkUnB;rKQC z1QM*nA|dZS024w!-$!1FDJ{=c!q;Wg%4r=%9+o(SG344@^(s1uuhJ%opg;=sq0)BS z5%{8e-X_6CA5z`igFfc~cT)rI+jGcyHn<LK*)?2o=NvHCo%iii@RjF$TF??dM9Axx zk0N}R_r<(f&qXexYonFT@xYcBHR3o}Cvo`6Pfo8?rc7O!sUN8Otc(Lz0<^KQ;h5jr z(H%jx^zk9y?&7Yug7jV(s*QPJY?$tRJkl55V>}FX@?Ave>}^oribm96Y>&q<90(#L zy5gaUkcImqV|Y?L9#ts-ZyGX%{C0PbhUr}(WhSo4tHqmlVO_8vHv>ahV2vnSC@?uQ z3BSpnWUJj+rJf$KKq%)yu8(10G50ovb6@b~HSzG7@ek+d`>5^_3J~@jO(OOLo@9Hx z)_sZj|1bWtIzcHVE;YAAq9wf)!4;yG@bveYa+)JayAmt3%@&fnR??esrLQWEUtct^ z5^16u{&H{0V{UpH<v`MkLmvRHO2eKoXDDjqsY)3eD$8S_Jl{bj$YObdIE1cli;%(A zK^3-mmyp17{#j`ng>h>?E<cLOw1K*>3XF-=0gw)gDZDGq1%s=l>=-nFL2dXIUs9d; z!f6&VuB;@VWWG_#&@{i4cs`-l5!w;bGH7;rZfK+Au)s6cCk}rW1ex{WLezlWEGM0I z#r>7CoZ3rv`oPh3yBn<z%>RG!pV|r40SncE(JR9jcT?fzSS^2j>P>?gX$9_iyn4$A z-0E5g83Ysz90KAc3<MY$C<Higdu=de5O87$6h?j|dHoYeRCE$%Ti@91ZX%|)a*BG@ zQ|o990t%$3201K#aXr&eLUunkz6J*c<pceg#xnN;jAAi~oIN3DeCE}zy5sxQ|3%$f z#>E*te}aSn!QI{68C-$|cL?sT!6mp$aCdhnxVr>r&;WtK-Q9CTe*e9@y}jN0+`GFM zJj|nA-Bn%vt*Y+oqeurU<F<nam(j=H)#7Y?jBD&Z;Tm_2z_4+671d*0=p%quyXmlR zsHgj-$B0jc(~QgB1+7=Uz+&_Z!3=KnZ7-fk6+98a19yJU()m^Cr($lIhDdFd^u4|P zFPS9@2?=C9h8i<Ikag0IGM4Bg=;|O=NC|w~HFlS_J3=7?vPRiNc1J5KnhNX?S#EXQ zf0RsW9@OQdpE#`zEIgZpiZ@t@Hh8*P?7kB{1M9L4k5~Yc?Fp^T?sF0JX?A+=qiTU7 z?8**IDr=)+qkLn<%Pud_{4nvFF$b9=DVXZ3lF#+UaQvvXP(@GlX?K}MWQ);hYM)F- zTwOajmDegbWW4tK!l+#hE3jrWms|Ps>aU-c^8So*$vu2$T7eQ?1nLFGuDKC1Y7adg z<HJ-APWzm5;XW_1n|l|0#bBU{3p;Xr7htAA^5kAc6JSmkeR_3$7I6jTpV9I9>*@y9 z4o)=nD4ewD=Q~xUG{6Swxdut~sJ{?4rVzV%_@77Vl%-wLIQGiel+Po_sMdMFqmZTC zLg|8<;~ddBE=CE>f^vwwc4WB{H4_i+tN8hu*LJi%cfJgLMQmP`ivwkcU_M;^1aZq1 zZqQu}u5Nh+d`e~^b9ILcm~~Gu-7%~-2iv&AeB9SJNbaY=%w8ru?i2i%JZl%JCWQuq z*`%4K3L{rbunf%61G%HKsLR;hY<(PJ(6U+AWcdSri|}pD*=1WeO2Rp}RAAU;b9ok1 z0ia?|E+e6q6L+XhXW{q?=4=|rGaB<$veQ$KgSE}+<wlo|Se#t}+IEr2)ViZzDP!{^ z;CmS9*3oR~Glv{4stXny$5W0}U46*SD!jX?;5iFZhOQQ{hiY^~=ryV#*Q^{42Y<Mc zH2StX%0NnW7FfDrwCw8kf&7SmmWgIdlWlr$Nfq`_p3p%C657wt<k*~7o)VmQqtaHc z>cj4>1?fR?7lNC+#I8hX8#}l?0ZB)xZ|iFXc%}Ssy3N8ic0`JfFtjyOHrKu+F>3mq zYqdChDf+sjc{aJtC0PePj*tus^bTQP<FW`ng`SQ&`DbObL}5-t&Q0_&wYZ`vWBE1? zY_p1xUuUrkTKmqJ9M<4DyzO%3ER2FANGoX8$($0JqgTabZijHt?((o>P5m?q_4%#y zrvoUBaQ;=}k5VatS{m-tr_kKS4>i;G&`c=m0S1y>q0=%yfqk=Pm!c++CLt?3^^>tF zk=%0G)WbP`JZq}0B@XG>ULqJ~HRZNkeyux)w!+k{r<ISpB>5@kSY=(X;~%>n&Faa2 z;SuW#f2oF5do(vP6ma9#GjhXYw9m1#N_Kqet(Qu&XEuj2mJkVMwnhzNlZbzU(x>lq z7A(b;gdR^lD%)`yujgggTMdweIiA9>kU=d%*?D7)K}=<W7gnyc9!D&24ZxUBu9{c< zaOWSYw|{bHN`1qGBlsBMa}8=HE+BOL=3vkC;-$U`@;o!aPgD5WrT82gb-&tU3x;4L zBd5s1KG#L8PyyYa?QwmmOM&mAXPIIlt@bl5lCeC{xTK21p8%{8%G%Xt+H9D2hifOa zish0}a7(XF2Z!p%xlGU4^-G4*y7`TlXkz2cY(g$v=6?_@e6l0CM5t3_4}=%ltE+*2 z15%3*YDbMXva~)Lo`eW){r2k_K8No}BA9R=KZmzq!h*qQ@wuO;@T=WIwBNjs+DZbk zbf*`Eq(qJ_K|c1wDGjqQ=xWaUDMd3FChQgll{(J)*bHLahEz*4CSk1Y89A#F>KWBU z-+DAC=x)f&uKPOL8(<eP-@m1j9dTMm8mFYgvq#cXubf&DUb~LDs)TXz6}UEApDf8_ zX0Gd%qgTs(EgMx{3d<>6z8b~~zLs}=%zh@%V;km7eNlRhGmKWU3BCC<Y~PF_0iu3d zx})*jmxRVdpkTmRB?PFHm(%t&YW{_|LMz&oYEV#H?Gr=N6fGfxPAUoF#e!&C$dbus zb}usqT5pw*LGb4sG)}z=6mn+g>oPFaQt~+PgHAC##NlveGS+-+T2rmWM=Mg|LtlM~ z_qLQPu$jvO&apkk48ERPoC!=|2^u9TcYhkgEYQ0Sq<=n}$)NpE>+>=JAD_3#ePKDd zd4FQZ(dC@amHrDyr7WG#6r|f7N%AHNsN$1iGu{ehmQiM^W%&S2#}lrCZa|w#hb~6? zr5sy~joPD{e%+x-CZmuvV;h=FD|{PuLlwg9WEDm}Jf9SO3{OyOe--YPwNam8|I^E0 z`PKf7IgXH86BLs$27Fd<H7$6V5k!d588f?nYnF%>#ah@bW?9rnG5a1}6PVV6fjd}x z3Gl!n-5+ln*Y?HQ;EE44*uR^cia^nE3ZGQ4cYVSLl8gj|NI}sl-ViBUrE*!%LO|m! zU7}YxQ)we^l|qSEGR~7pBgSb5k!89LRrHrPK<*xWt1iIlyQcOF&#~v}_TGOU%8(nZ zRyA*kgXa3uJjCUF#)j`dqU_BPWRyO<PKsaFZPtf`O^3k<b}>$-J{$gppqD~lV1+AA z#GrD}J1$oSscGBJiuq<MuJCh89-eTgPM7HIyyChIm1)l63@(=2I>X#M+OMkfQRyU- zPtuFVef2Q>IMk&=y$s|MWuA{Bcpq(}R;bIRMQD*tf}+MFF^K+bBdGO$kMRAiz4yss zz+j7Uj(Xx#wCwjgGeWB25WlE}^2LYK;BxrJvUPL!^4g~uPV0Jz5I_3upqw?OCOKMg zcBw_r)V~m#yXbP$^Pjw?N*CN&sAJHzflN3E&fS-M-nYv&jPa8T$2bujdj!fUvOn%z zfiJ#FDzpAatjSbHvp!Mt2N)$qftXg!@bh10t=@-l2~S4nB_1^HMch#HOV+llVuDH~ zR6F!P`BV#)Jc*X#_Z{KGOk7jc)>Jg?B+V#rnAN5+*1AR!9}TvsbxLL6WqP|N`>vNW zC21$sx>-MnuM0l9e;4mCUSb36mBn$+y?&{mwJn$NcW3JOh`}S3j<Z{u?fO)pS0<Nb z+Q9YTrE#|e!+BnLj%(kHU)`-AdnxE=$@qM1ha!Tse`_i44Y1#Y^710|VMbG#tfJf` zBw;(1kr6Zyo(JG3xV~K?<<qLXDnp@({i}<KcNDEZ;ZS0Pak=o4&Qg!)SyJY2@kVk@ zQy4VsS5_sC#Fcf2FYz4Fm)aQ}cFVyuH@YgxN*@V9=Idpeb$L|7Iu72?uKh@<w}c?= z_T_8aTwU#l$imnqImeTT*%R0V>?#6%3L@8F*@nwAgxc!W1{NE#jnvvM8m;2#+d=7u z@rF?0J5G~=DeWUCHi301m47HB&zSqy;Ig-ElPqs&Bv#yV_9`Qn#iEf@ZK^W}K2asl z>*6euGxugA%>C>H?@NK)as&FLi&-;`X0ni#N+cxgd5DAe=u~;6i5!>fZGRO8vo8D) z8BK$l?9Xxx=<nr}(O^Ap&eUvTB_ry@(jnT)XPD}CajV_-^$@*k4ozUfP2Q?@WhQgX z@|9<)Q2jRm<;?D9*t!2rP&D_*X~ziY6e>k|AuQ$;9s+%J$?ulnK?G5oJs=8FOXo9* zGp^Xz+|Mnb-rfp*PB%+VJ~U3Le$4v%qj&gJ$Q8mldufu8F4c*?REfYLvInu|7lgoJ zy`9-Wycfw{8t1XOP}|HTPCZ8_=U9zgxQq^q-R2KDh#0dpOcgv9SLEoPu-Vpn8#=Bd zzDy4bSJ75*Xmb2H6fEOr6WIPz`+Qlu?ku#M%p8$lMs6#nLtNFVGi6R*w9h@;v&Z-4 zm8nfZ3z(_o9S|3_nnFtqOQ=wW`SlnQzd>navop88t%S2&-(2F}V&rkNZ(sB5L3eky zgLeG$5^t<RAXO;8m=htP3|9%UdX)OO6*MMiL1lPp5i=z0Z|Qs-5kFc3tCjoi(o_6v zxKUTRml3ie%#vX|b@O@7v!ogeX6~JanHox@;8cV%U3UrdinKA)bMpL<+PA*8o9@(+ zjb-X6Zzs`U(uuSMOs&K#9AtC+NGLBPy`%|N&l^+Z?Zq=DrqU^aDviQT)a^1RKxt|I z;87Pt<wwatgzW%T)ac-kBQpI@k@SIJ(^QhsJIRMlor8<k03!q9<1O+pWFN@L_s~9v ztId;J>t=D<_;+xVh&xy6wcYh)Td1f7F?MWbZr4s>@eQjaI{CYQnr^9~PI9#75LB;K zqqw0@aaF}3(p;*b@(r;PG2}!B^)$=e4nkb~+3Z&Cey#f)F~9mKYUON1to*_as=-ms z>%E~YqFbjSBV&ewAAWQ2iJRrH!~&TNmtloPAxJKA++55soJf?4cZiRQBp916OfomT zcT3^h&_`UQPI%){6KvyRLB&)p);78{J;im&Sw#O`tC6Y}=SHoQ(T2d~p#r(lM5Ves z=98EHD&ZBLnLH$^<E7XYG&7|Xq)QJRx2Hv3{tQu#V`R6L9&>6MnQb$A^*SI+(3vs= zGAxfOB&+v^gJ-W4!T?tdOYQlof1Iu)5x2qFsJ7C5f$cmUBB?dlP?Eqx^S8TxenzV@ z!Rvl1q>kFG4^ja;z{FrqE@rJMxMx1X+@TW)%Ov{?&TORoN6sTERFq`I((1^)GiUc* zJ9-SFSfYJR04&j!PaSNL+{7a>CrhhI4#_#D3w}|&WOe<m-AcB1IqYU2&Gj0&d6UTA zxXPu$W=YPud1SpcJ8VjNUH@de6BH@&N*S7JOX$bH5HYQCZJoCWeP_p>{HJyok%HG$ z+yf-G$;aX4QN18oEdK3}=obv#BQezn7mg(-#K@TIvG99fo>1a=WW}LwNU$;-@Jra5 z(7awtO|~pScAR)DK-OJYmc&*W`*6rZb`Ms$XsH*;?!|t(j?^*eoOlA8mo640)mj>y z0LmEP8+gT7@~?RIm;#|t6u1faR;sp|&PbJ9&4%erLF>J15ehpp8}y;=8^0m~Q8A?@ zqi0bjMV?<uHDiAv${MG((7gO$2`N}}c;I#2z!{~)<u<X%sNAil2)^gN7TA@{MiANo z!>4sb?Ya3$Y(;CzH?%WpS4%BUM$?k`2S<OYFo%x@qv&0g2Ez+8ZEiwFtq;XSt+Ru% zOx}EV6lkWeWk9+ttn%PP`3ZHYa9U9)u~Jio1-MG>rU#Q-ugNqq#o*P<21T-ZQOXeT zN7LS$&bIWVv>%sS&LOBZnWPM0Wn@$u=h2r>mo;DQvTOB0-)eq~-#Atz#ZBtHU37d& zap@SZa0}X$xf4}2;l@N~2qAOYDY;oFvWpZrR9`mL184mCT0d=0t&XEJjP@;|EmXhs zVi=<zU9H#}six-9O;in&1;x64r9`f=LOYrPs>!HghW<lT?u-Z44JCxgJCjZ!>lpC6 zK4=1p%t4)2c;`zWefOi4$TooTB$|Uy1osF1NC5a}K`?j-I7Yf+Wx~d5jtDdz?vhxs zRJ3JYFr@FSl<Fktd%HAmaj?tkIr>oOk+_e+V-RFcny(s!E8pGwOXiexjhUZxYU8;= zvyoLN==M6OpAfg0Hod>#gn7B|+B8CyiL`;+lqQ&w%OTy{14+MS4eW#NYd}>h?~BrE z6$`35lh4Bt`Au%u5NJVLts0aI+tc^wu*9Ri5_GppQd!65CB?jK?bj)_seqEq#Qtz^ zxm$z$(9dfV)Xf^Bz3~?!iXx?ze;f9{yL$dVTnxS#3NSy&AibFW6gcbve(`^N<o|jR zqyG-8Yq=nPT$kuFSnKr8MyrF&2prJ0%E<f?A%Nv%Q*~`rwgUEzQ0{gs^`(i_@OP0e zkx0l5=C4yLh{n4}$U|I%=skps_&q#?OHgS=qA13oSzk|F%r6rq?2%xKZ_M99365rM z@VWyO&B1mMFw;I*`xNfg?2;o5leejm_y9aS&tkFugw}H9k~}bSt7O-B<1#J<jD}8u zlkMT4`Lso4HHX!#jKIn#vc}LgfIjSFOJBuPk{i8=$NdgPqqj>&SHaYsd6+la|KMh- zOph{Esl1+Uy^LL{Tc0?@Mq{oa{L~3ok7j0CnJsodK80nK&|zFMp+wqYdt4eHsglq( zBsJg@bckL$-bO3;M!%3u4&>!f;%pmdESR*`O?O7e7W?7e&xEbdtaIY~l&jwL8qe%W zt=Pp{hdlp6k{^+hF0LS641s_qA2N&@aVNs8X(R!DPGh>Bas@bCu8LP*0%}x1-!GSy zHix82(WJ&=pRy>{xH|EB?UtaPYQT%6_@I1u9??*>_X{;jXGEXmrC^*@CM%hc{A->g zhZ!`)?hxOd_`=xNG^(K^qkTo5pVhQ!N8dm<zVXzq@r35C(`?{X;*XL?Dn(MAd830| z>(x5O8fa6nN_om|{rU9~qp3osLwR){dp^J^OFLpPMQra)b|Qh*g#;i%J(B@Fk43dP z`He;h9HqEiF4ujozknsWnGIf7l{_5oS&JjY&4K=f1*(()nF7#qo^oJbr}6W|W|1&~ zw*e}GC?hdZq;o`&-P7;*g@+KwxQ+RH3JW?(;|TTdZg{U?C%edv(pE{D-^;B<_pm#w zIDLu^G4emXG5>#YqVWGfXtG&6X=f4CEfRZ|BZLT6^b0=wjg+5+T5p&~x*+`*AY|rw z1w+cM$1fD~$!+SWb$m9KLhc*xvsr6=u7iQ)s`n8CuAWg(+5kYLe;Y?@?6D^TpcD<6 zBRB`0gvLvPRC_^f+iI|$A_W;-7LY}rB(X%eCNOEe3;${HJd-n5`XiaVi=v_}M6GJt z#=<BCd@kQV<pIc-?4D|o1?-lb9&R9;M~P{(cLG2XR5x}vlVW23t?)C~k}DY_Z&aL@ ztx?lgKn^WVi1Xw&Oa<k6F#q<mx;LUC;V%-u!r@jxsJ#gvnD@B7VWr-v;~jXym7X6@ zw+mqb(Qyp8&z$cD+UpGTRzFYj+evw#PN!TBc4jqX=ADE*OzYW&>@)N4(L(N-Tfb#a zq*9cB${@F$%5w|C<4xqgNDclxb_-?ZF^zfkC`gX$l}ycTb@wr766WkTZ!>6+DAT)( z$>9@k%k(MAL>D~bGlCBV5ALU>yQr3VBhjPq*K7Qz9KQR)VWyA1zui!frYy&xb!JBI z`&oxshaoD3t0`z^^F085G@wVH7gDo^%RB!JuHmQGjq6U*Fi<_5)ARm)z~tA<E|Dw$ z0pG5BkIJC(M*Hr+5FVUJ5Zt9;(FQlPzl?17_MXih&CKHg)sasmDlqe4@>RfaiHMi` z{PgwRk%jkMRGw!HMP0zw(F`rWb{U|4a>=v{*%VfI9@MwD-HZZgF$n7nk#ijuWxWWJ zb1(NVB{+HRe~jU@Bun)2-eyN+$XsjvuTSO8vqrdm8BZT}%y6>9>$H6&eg}UeYb<yH zkoosZ_<5g7N4egS^}UE&5yh>9$%MR6d>Wg7P@-5f!3+vZ!n+^Z;w+*eo>V{0SZ#h< zI4ue}%2)PX59hYiNQ+;LM>q`zQ){zE4I<{!_MiP4fc;GQKK|proWA$w&)*FcTD!9y zefYMXT!(IsBM+Bw=4wHU?`0AnC>vf#@&?0i;y3qJx_R`jc2OX@_k(RtwhAU9_@^i+ z8QLxv!^dMwE*CmDI4q{NAbM>~`4x_H%`G#>ABc2I^+*|7aHJe2^UvX5vSB;}<VmI| zmv@0CdV;V23U@I%umjd}9cYWrsyGK<h!;IoYIr*d<et<#>{#LIvwD!Ll&RM|2%u1I z6}yj6jJ_S6gP%$=ECihuoJtMJaXtv&icG<g!i2C&k#j6RJP&9z!~8Mal-D_baDI0C zmM(OGh4M@eX7axV=?G=Q{c*18*@uFEzi<~~Xry`9X}@(@!;Th8u&`l&dw=>a;UiQ3 zYJYbZmd`Jct6<lC6P1I+y|V5YU<u$q{%i@jyqH<AgdRBW5|UBT{s#!pbX{D}I}TTo z&IEG*9I4J2VS|g_vbd*Z(v%kvs&fF@m#{*d$3z*l9FmOQy>6&*dNRS(HofI~@HYRR z_KA-pp7_9HsS;>y#Gz8(|NcpH!9L@Zfhaa111#23Vc7-?+>#q}nAQ)!@HY>=Du)TO zoh7<597D$&c7&~>m_#(c)X0tIIhs>RwGK&U_XNLl*llEWHxE34AflHF0x8}m)mLvb zd?s1XE@T7Q?)T&d-4BH_`H%J$=$b)z_6?^ndC?BHG@inxvEc#2Mn_ncS0?ID-ID*> zt>t$@9Q<gAp3-etu)f4k5JntTmA@4tf{;t_&a(h$4C_dL`VzC#5XtK_AebziOlJ|} zCD&6Vpa1A(faC7r3xeCDsP%LOjPgtDFL2v_7I-J`P55Oi%Q3J$r%WaeT_mt*-92)- z^WP1zb;>#qxx)&GHKM-|;oH>UC^zUKhTZ=5e{stHB4A^Bktv^V1&{9d7a}f(Z|=hH zgd(Q#h2$A_yZZB|w|<^uMewTQx)5zUSZU?Nu$N$216=<u-|cvYSiO;@4Pu(*!C){I zN6+UqXnjk&m&LXO4fH1Ao(}?w8*k*-l^@-kJKS7P0*t6<B1nPapT@cr(QQX_0pp^F zRkOS_IYsG73N+xP$xBU7bsmYN@-mCEQ0G<RQ*df6o$b3#7a&Gtv{CDA4eDE!wbgUY zouKcuJzqavQs_@r|77m-vHWsW{vr_bksBti5`(mg?%>t9HU}b<_vAmSBH$eBsf5bK z>S(6wsnhQdEyQb2^yjzqzYvdX<_F62WIW;HEx$(8Z-7<@8uP}JGlgYdQP}+$Y?jOk zGvy69$8_7VnXj?lcnxq))iBlzU+6!p@;~Q1FsKA!5L$!5g<~W*Zu3}*mGi)XZK-(j z&WP!CN*+tO^l}J&B2e1azMs+BV+^zV-T&l-=0!ktXC_my7!D4@;V(q&9#5sl&|iq! z|LK1$i^ggy@D?$bFN2Mamaq$Fyi^~&U#FDmT>~gy%A6;`X;{B^^4*D+Tv*Z5Ve-HX zAg}q#2g7v|BCK8fu6x`%6b!4tVjp=*lKW;!HegJ0GGJB3<ZWEbA!>2qhaLRKxNq9f zZP0yNmn~9eN0EsxVO?;*eMBj@@5S>+80Vqf$Nf<9^d%m(WA@oiZnf=l|LehPR}~z~ zjSWndAG`7u$79E?h8)``=EsyuUxxt-)wOM<1ZG=lG0un$&J8^RxM^UUr6iF7=|zwq zJT8#@BFUOBM%=ojs{s!ax!Iy%Sqm(9x3yj_!OHF<E+!;<KzM*ZNY@N6pxZATOKczP zT=|If7ozgjs*olq%B;H!Ph>=*71Z}uN9x`7U3=@QX=v95?8(PTu3<b9u(r9*1&36> z{I`%QEHo742j~yrkSYY^N3{Pvq>6$0UlCOx^uL(u&rK|FMAZ<6qTmu>JWDAi?o{9Z zFQy9lFQ$4dN1cwIudRi*q*E|A(eYR%^Tn035-v+ju2K7Ys;|0=*7T#MiAWkglfZb_ zueqzsH*Tvvy*#TiZTGVTOpxsjR@RLf(?tU4c)vg`fs?5GPx-0N{j{_e(d~C~XVJ`? zLr}MGiPy>18{HwolK-e?WE8P_q$2w%mzOue7kpE<(l0iI_}j6|Y+IzAf*NcScY!7! zf3hn_1b^G-Wr)Y0(Fb&YFoUbGv4=}W#|u7=5mpp`RCyDrJ8ZmWp8bWIpE+UqDPIqx zD+5wnOw0im4=;GX?V+Tz1xkKjpSH7Ab`h#^f;Jve!@!MhiY4jlO@N^QXw$Gv;0Z(p z*s&`WiZyZs2X1UuX?!V7cbc^5_M6ZNjg`Itc2VJNDRhv2_$6iNDR0?RvWibs&mdQm zGLQHno9|Z+xC-aWKrxD|foQXOarhZii<PROGyee$Jh-QH3h9$)#@%jq(K7qxW3v~3 zCCk`@4y>XnN;1LkcOe$_ef1nc{;P%H65X%VHEYL{lb%{mdue_n*z38R#S)E$9n4|% zRlBjDr)F$9hmwDc1$`SF2TO|Cbyd5oY$@HScvxR(oH=aHD=w{2l#6?4(@Mug_bWV2 z!IoHD+WNVDQ^MBSrXIX2#66@ph9C~w6cV-Ot<-oA7CNp8?uJjk(3OCoh#s<+)+r{e zLmCjw(NbQDBSh*Dvr_0#q5J~CT#HmqplP(A3S}v!W$_CXPvZmyHrddSK6PbCMDz~v z-i8MJUx+`!nn9ni`n#PwYg^4*J$hR2D$f>66wCeqJVk&6Skv=e1m1EOg4j7`E6y2X zvVPElkm1U<FKsINMK?C9g;>$ZfepErWFiGjIfVAM)MB=5)Y0z`8x2SFi*LdvdY4wS zuc5uf(@h`)1+4`uDDhPc6-)EE7O*KT#4PjD)+<KPE)By5Iq3xp_{n*zFrTPLyz;x5 zjw0srB^$d5sfCE7uavTV{HLs%Gl4w(A=-qvqluKy;_42zjthLo)y!UG7${i7+Y|Dw z@d_ZS;jNTrl}-zV?%b_{K%Mi>xcr<4ddM}g^S#W`A)oH>`3V}QA{c#ViF%Mh2KBeD zE~*{>xP&RM-CcPpI3&pK>e6(#wD`@)Gs|?_tFw$S%K#avIVyar9G=W*?%^a+MjV0o z6hBu;M%u)U5tqcR0ke&hiYPB0s*!Jcm7xv&z1HLUaKYG<6<F1^jwV0Ti6Wy!B1YZX z)M%Sql{O~>zn83#4LTZ*n-?AHk|GpYF*cR`v^`CQ<&X2|a(;-zQ2GneMrUz%eMZZ7 z1?j}MSlw_2-Vlwtxlqo1VEQOTnH^NFAZqm|gXn7Z55P~=Q-ZbWk{NAgmF#4ncfU;9 zPbxCL8qro#urnjuyZW6G@@Y<w5(?RTs)l`0;u3rXI`=i?qo{B-{2G`>-@T#^sVo|} zCMZED&{j5jcp-bj?k9@%Vy_a(=c3c_c%Azj670Wd#BK1rH(E2P<)(ZNb7D;dQwf{Q z=39f9*N}OnxnON{fmzRUjEE+(BE#DCN6L)0KQ`|1V`3=@X!LVCw252*`W*t7$%yTx zbd^kbk{q_XE+&lTt^nJ)*qt9Q0@PQ+9o+=C6cTy7Dy!fg;0&@@q9dgesXU1&!ykDQ z^7%Dc6fL8P1m3H{N6JXP<F){5$GxoPDd|w}LZYB!X=1tw2{LE_tV`zbvKYBp&B3#Q z2iDNGRO3z*Z6bEsr6(M-%{ggNL5NOkpP{W92EBDo78o5?s!>}lC5Ri35ryfrV=<2j zO%PclX7#X?HoBSvA631DK7<WJm3~FIxybeb`RoMmsx7N{op00=`J!KnwpN^j5viI( z$%D_#O4Jp|5n#bQUEv+p(B)nE6A87K5&mF4y6?w_QfL=z^<JJ&R(|#7rd4bnQu^~p zzUAl6@&rPI2Qe5$&9eqyAsGr{RL!=kV_LNjZxvMgv?Euc(#*ezH)=!d5;WmA@9W7> zRZ!$fr8{|fV)Bb+Te6OxT)wf<1!C43rCku*mIvCKW+okPhsDd6(3PC=FFDkV*8k38 zG3s)+UOn!=gNc<DX+)82o<qu?K#GR~9FNW~e0^nu6wH~pTcPr3&5#xPfgFuJ{ct|( zP!NCyWch@MkuwY&!ma9e=1bzKiabfi2ljPUK{}r)Z(XoXNGnLM$C;KuQ}fTuI&9Sb zY)X2<plG^8fEe)24RSmdFZF9>;FyqN^7=`!#nGWBox76y>N^B87KBM7ZLi#;jg?e? znVMk!+HHyElAS#ddR3Y=Jdx-)FNY^*v0vH<PfL|_`re~=ne!Bf4n+8kPh=jr&CSV< z$fMtz5^3?`e&~=XML*sbx)y4|WZ6ilY$9XIC5CRO9;#IvgsD+DBsjB$0hO^8X?t#W zHvw;mk}_|kC5!)olfW8v1IlZuP1Mg7nS=Zpnh(ImcbrY0jaKboG?*tcupu#Gl~lv< zkpy{aac~3_A}At{fAhn$aB0dC&#3!KG>uFSd(h_bKPn>er&hiY-gh@2pTiSo4rGdk zQ9iu#tUDEhFOX=#lzN;*@#H*kPVT?+mvfQXB0Q~$awxR-HjuSLt%0U4lI!N>E_Mn( z1;I0asFV3^-sWKyZ6>7B(&25@D;cGLEG<gYwilC*k{78(Y=WG)42(E^Q2c(Sm$Dp2 zd>rB?)Mcn$#CzPqu2w>eL2Di-M+!j_DOr`uKWs@PK@c5+-}V1O^lMiXhJVOi9Xa7T z&bfVQ-Yftfw5-@&o;qxC5set{qkTPaTiMVd*E&_UzY-aY*Ux@e7VH_}x{C=w_A2hP zj^G^L(zcB&9l*X&13LcO*vBmaKL=SKEe1bWqF=*mhawX$&RViWJ%<i4u4ynGw;Baz zywgloeW^5r7H>aC#aK3jU(3^vQuN{f>^DWXn|(zGXb87&Ke-yK@l10C_L~c3e;&ji z5g0A7nsi3Y5}Z)7bWNDL*lWinTL573D+M9dbT3A1F1%wJ32jE80V*-Z3Z6aSp>8u> za8{RtS{rey7@mWC>P$wkG${PH-881%An)K0xZ81SpBhS5G5>7-J7#{=`Ul8BGxphi z0pD4v)h|{twx>{V6XV{hr-OZ+eOik7>@y^&11ZF}GKz?E5_&`j_>gW7)z5(djAfy7 zwe5wyI&^|r8$SEcSJ`{}Y7Ax&T<Oe>;=t>{nAeutF-zbRZxpuZ=8u~sUM=nY9E}R7 z;>Z4W!n=kQT2yNQ7=Ky5@}G$NQ-942if7%|bH1E8)Z3+It3tO_kAXlnZmE&Fbi`c8 zs%f+PojK&eO&A>Gyxfw{qlHhvb~|9N-#EoGaOG2RqbQiDo&$fd>3TX+{>3c1t~QIR zmISaUvT2UOP&%-_PYG3iDTQ6u>}ObZmzEO56ZU5{G}1-may6#U6Q5Bk+UMjyw9t6> zhfkq}WGtji87g?OE@yc2?>W=<mpcf_Kp{h!bPwSZO2wilugNea0}F8Q;m}sHO}w?* z&T1wj7P;5jiNfRM>f36ub^;Zxn}pd`X4p9t>N?p^H-kIoc~DG^U%Ji&6kzZ?Mt!Lt z7qXA7`@K*xT<7UqP9BKy*>3NArTQ(rab)biP1m+rgM2Q;1h2IiccP(ySl>YHgZ7I( z@~78V=di#fbqnD<Aoeu;XP)H}F<Ua%Krt}Ta*IkVrmqB$A+`7?%}q#OL4eA62CFX4 zPZIo%<6md0p<pj2y>4m65oC9H@oZMopm-GQMt{hp-Q3W|W#L0B(j?9aowO%$eGbJS zEKko)_h4{+j&7^94^a~%n)$}(J8iW(pWjV`OF9u-@+x%y4IG@hxz7@{%H&ht)nEPG z{0di-c%B4J=|(a3$<Dj+hiB2m?f07KgP6&~{j<3^+Ne-XH;RB1P=Tx0j6l6w-R)Y` zeV@7KTbZxO@?$|e30mB1LB_@<*MEANBDc0~l`;sI7z3YX$ObVhN|}9eD{sWsYHd`z zpc^p@RC1;3IuRxI8ZUH?g}nGsosYqsDq$1zg^8J@NW)I5)cD66GDZPnV3?hAaHI`e z18V-tI{xZ5-cpVJBRYi<pzAlwpzU?ibL>UvX2Fc~kHcEYMDM6~lfd#<X&k<6ow_P~ z0fAW;K<ISN3u?7~XQR+Tf<g;bqwSOMX4%S8i%_Gn2on=y)y0(MVEt&x8PURYwRndE zsE^|ZHj&z}k7k*-@~Kr)liTxd#~c4#u3H)Zv+0eGs^#8ED#$0IyAS{6o_6tGGS-uD z@A-z-#S$M<sI<tqn;;F>EH<!CG6J1*iO*PHYBn5x+}kw69A=^6Pj7m{FHEcMWgqoM zs~+uS(-0lb8;K0z^aN0Y0<|{L=sg%|Qsoe;azi6y7{Rexf=7Melfq;0mrXE^ae(UJ z=$?O&|DOJoWCWMWP25uu^r6mzao*D2TY`rN&c2#}maSEKi8<S&WciojZbT68<ANix zT*isxs@6kU+=JA&uqtWxA*X1EwD|t)#7P7Uf7|R(ry7o>^LX6f(M-Mw;aVt%=R!6p z6E`6_j81ciMw});B||LHh-pi8mh<KBCS`qhqfsP(aB>LkAVw`hipV5@w6iT1>l3og zL!cV*0|7x4oDEW7P%4cdVP9?!`mFY5Srd52jgGDQj^PXG%7UAU8oz2TV`DDklp4tR z!3l{cw#rN+rIir^dOCV!T133Xeho&r*!_-zy$3PMJyXflKrhw8IMFE--W{q-@W%N& z+47u5-2*g|?+!)cdBydKr(?APyn^g5Db7>QAI^1C;=VHDxcI2HQFz}ImHhx9?r${j z-Y2l*o;;<$qCz37Pu+~Qe(W+$vyUh|@|2<Yy$6$Sve89?PqDq`98sD87?Pb&7?h)1 zx_)OD(NWB6y*9Aq)%t4!mhBP{ABj|M)PA`Xg9*8`jT;HOgcHbctIqp}Dd*h)Z8UA2 zi^v;{|J~|w9t3xj8UBQ6cb+{nwxlniorDV{Z=FkkBZ@dj#GoCvOh$6UTovDP5ZCY> zB4&YFt`WF?ouPAcI;Oju1$v&+^M9U=Am%r`NWgP1nbNKGjztI!HJZje7h4D0HD}Lx zlvJhm<zbcf4dRX1Y2W3w7}+*fpd>d+wa&hNljY=_ww*6`H|^MqrFWiG)CTzu(Z6}H zb7;ar(@QHf9BY9OqJi2-BKRWl8OudV(>_x3Qq|A<XQDx3`E0`$L+k`b&lLaEQc>-4 z-zII^F&9z_UxR{A{NP85g_cR_D*VLLx)uD*0QPC8)<1X(cW-d<TK#;u=*g;uT3hw@ zWe37q-<csa;A!envm~Km82MGH=v`^F4ST6cPA}z~2Asz^6+19jZP^v_nQxFb+0Mb} zfXB_etDsR>-mJT)9gsnhr1L10;FY$g2VNxZDa5cweCP;Rnu%spF*vjXHsKT9ea}~t z>HYZFD>rKVVZH2pm8u%wzTWz4N+bPpZ2<ru+_P4@06)^nRm;!rzyRR0G>A3WhEi%8 z#TStB2kuy*QFFW&_a&eC{4P)Xgcb3@YF6)B@g_Osl!@(&QnME2%)!PQ?ch&6=U{6- z!&h(RW=(`F4`pS_WBC|LHl)kG6e1}d#yByp{s79q5Yn3Zvva6lg_||=ws8qNFl7}B z3tGE?Pz%RM#<&F%KF3kNk9jtxw5*l7$c#gKr?8z2erR@E{=Yhi&AM^p!3K~>{~kgV z?!o-&J@dalgcViAWEH@(3^5u2Xt{o22hl3zq&X77Ev*!Ks^8GDIwdWxU0tcD<~+@$ zcr99D@Q-*-awmpP9p%dj>iDEk<uwkBS&te<!|?og1dGhqHpY8;*Ieynss#|>yK0W* zJgT#1Ezw)q63G;dgbf{IQK?oH_%C0C3HMzYd{%mwtR<|T*p3yjW*+m}sb<R@uKjc+ zR#(mNI}@K!j62;V)m$35!TBdbszY6c0O#(3VRmPZslZkJcU+F-ryd7&%eqxq&V8Xn zXk@DFx)r#bPu+zmm_#2Mp%j`@Kvb5E_2+k&2jKY%2*H7?0s*_K-U7<8aEpm(dxldw z{GAK=lP;n<p|9|S>UyChi5+EyUu-2#(@&I`kb_4W`PAg2En26_@0M6Fe^q;1b^b!6 zySq?~85K9>hCqxVYNM8D2xWCqY;N-?Q%`XSnNF%NSwLlHW3lR`R_?>;V-u@2Te!JU zCKqOLB%&A<2T#}@(20$;_|ec4^kaz-lV>0(0ufK{@kE&fu@};Hd0P?7+`(q=(Dh7> zr`a4d)waiv61cgd1%G+xh`u_Lf1z6$tVGxxL7N}1e-GH;SK^lI_bKjVlu8XqE9SbP zbv(JE`aO538yk2-DbdckXyoE{7>g4SYHV%rL&(*_Z}r-TdW&$B$QJ<!BsBSz)pSFn zloM?AWBDu^gIzRF*1`vExy!WaX7vBuPd-Uuu<JNo&C;7jWBjM1u!{ljbfO}iief9a zxD1lkdt0MZce(4Bsmuq0h$6$6eO0|6|GOI$W{>hG2>&0vAy&uye@`27Z~pQ|A4g~} zV6|tvOYo{p&Yj90#7X~DkW<}0jy|icl~DgA#E84a5H6YYbHv_rA~Co9BL!ztii&F0 zqKb}EUc#h|v9?HjZW*olPo0P7E-;1*3dDAg0JH~L485~qst5XDKhZLt_dA`FKV1_B z2(J3Y2UuV(r3PnvUQnX5C<`~O8(;E_SxLFBYTmpP{Q;yNM{U}Cb8k6ZrZ$Q%x09{t z4#og8KDj}S`lMtBzhipK?%cINeH}zFftGVu)y<MCva-nV;|B+ECgC+?7-PATPUxVY zCNVb&Q@(rPAzDQ<f^N}<&Jq)yxQxBFjMn0u3#<o`Nj@31Z>S1V>pWqV%nb}}!Y0^L zwP+k55daCzKQqkc%<;Y86zYNdRLV4^gqVfre2Dw8@bsVl1uC}i^?FTtd_`}_WHaD; zKqd>z0#&MhN<=zSn?{@M3|NHtFv`RJ^>!X_a!QGQE3Z0(@a0i3QrlZ)jA=|sNtf2@ zB78s#R@oJN0vN6R@lS0(5)H<pmz7Yt6-o9H5#wa>c(1gz5ZXVGy1!Nd<1o?e^OZ)v zo5VFT2GsmoCgZ%k6=Lmol&Pios_bQM;j2JYX0~vDU|_Eq#rGUvC<4M_)>}LLfpwDW z#G`1R`a@{We-w?}Q;7rP<s!ti99)SR_apeP2{5*uJ!&m|_=>e1vf>kQ=?vh8^+GFJ zG_{^ZjG9452eDATDbpB$roBt-^+7CDfmZQQ=Stq(nBt1{dc7W`rco0u3%lJW36#Zx zn7KRe@RP@z?8H_gg&+FCHR&zqs_ypUcE3j<_on3n__j#A*&qS7D<xEbF<Gc32vBr| zSXr;Caz0~VGf-q;lhVIOnr`0hkwW&F`%EGl`A{M;XZ`SdVN~e)Au08teN+mMk-|lY z_!~J|UPel>fLX$DkiC0`OR4;UzzhaE=rbh)Ri!nB`U9DEg+7IS4FBs4$L%Q?mk<h} zT4OLynVf@k02YFH(smE!%V+BUL;<017KBFzkPH3`5&W*CdAv!d)a1DW-*hbN69y;F zwMx=WYOK|29>DY2;NBVI@E}IkPL`<p+o-i^1qrby<o&JjP1G$uyi7Hzkh4w+2J)s+ z{PmTeLx>D7<o{~+*z|7UbW=I5B#&5Y5S8n?75~@I%I!rk8B}5yp%KY(G~QIV5^2@W zqhJBs39kyBy7~#x;%S-Da6NGdf1~uM&l8`39o96>48VArmHtV5v94!9(V2=w5NK0k z11xt8_it+$L7p7*cE6A(UDTJMbWhOqe0~#r$DR}yQP`9Ciz>I8TO*$k<8L}OyyWbS zUyQj=!AEN$Zc+Q<t(IjIFVvd}qadB%J-E@&1i!NnJ*Ki&gfO|P+T-*2;vf>c^(|wR z2=+oGo?enBm(O`g@Q@cW;&Sz$Uw3AuYIon8A}eel8nMeq8wr5#?e=co8z4JQ*mo`+ zmE0tJ_z0dIFiIA%LK*FTaHaiYqHt`)eg?|gV%C@cACWIB?{7$gni<ve8-2`5>CXLy zXw}1=idzOTHbTT_YMwt_3QxGXA5aTt-<GRItDdFi4lA}c&Al^|{eiaRRhy4{UDkIJ zJtN2Wv1JLsKG(7Yo|4zaSzkW%E}r8XP@&rwDqyeYdMHKh5>3(;htB;YBh`G5T)P0a zk5%KyLN;XxY>tY2QRz>!<r}TUv!Py-JV=KxMGWAm2p+2MhgXe54y1|teoibQ1fU!6 z5P^Xr%J~o|pw_10UXhK^L@}DRurglS2Ji2h&KMvrz2ssB_|8+VE=%_p;v;!0HJ}CS z!^JZH5zw~9msGp|+f<-hO4GmEv-mZx;F$#;O!qP%<u7)4O99!K{J?ux_7n?}4V}V_ zT}!^Y$P!iD(_f`hpN&$C<;=?+cXOzwyb{Z5h_{@IPu?#IyWH2-yE7b=j)5!^U<|MT z_y5TD`U`O@d#aqV%9MjgfkFB;XUHz_c^Kh>N6wfJLy*KibmOkiWw^fz4P@0&Pbo3F z92i1V-%aA;>PD|{X5dumz#LOc1?=*U-)Yb2jEB4ywbMp^tdK*x$QbvLdMJRN>y{;Z z!T-l?#MR57hCkKdUT4Mv-pLLMPh>W0DHRgcre;j$Oy!+VREpsN9FzyF8B(2ILdQWN z&#@M34h}tzC(kv=IA?;nu6_NlBMoP*JO-_IK1&~8&)~n0@=aQpM9SHIKGOJT{s`Lo zACIcGi|(xeiIKNraSNEMNrR6eD8cN?c^4v0Lj;)lX~px;Brj&cceE*NaQC_|<6cys zYZV4p>DX4G=d&v3fOFMaj1tROGn*YKtO6RSJE=HI7AY9(i3^;_&=23j6`+upA8DR= z>Qe{7*{QCVf||&TsULHH^4>yv?PkT_=!6tTrfT?h?=UXaj4qISorjoFVUPBO#aXx? z%4~;t?>=I`3ux}3)+sbjmb*geE_2s?g$2E&H*)S9c(KL_R%wo(wBntN&|G_WnTcMm z9`?8I*<{+^_iu6oVPoy<Rde>Azc>KdI=|lA2*(Gq5pR-fpy1pSFL2N?qiu73|2^qY zn^a4F&yVr1BpSu=APT_2OqO)Jm+yFR(6gfbvO}Do)#)=cI?AbFk6FLSYiY|#tJLSl zyVq2t*E4LbNj{*tS7a2U-|3w$Q|hi?>as(#LGqh{S^u)H#-mRvg4v_N?wx$2R@%lU z0?M;blH^4!%hCl8RsNr1i|B*9@le~BJy1K!&kIvRPu88B$8mw5qg*V755mWdIYcJC ziq&j0I(YF&U#O{o9E%o;H(B<0W${%Cqyu(;+}@Vaep|I*?rVXtYA`L&&*UOZp+I<1 z^+mTnoW~iPj5THiG;%(OFP|0oS-ovAqla&NE|2DO(I+&Sf2=KJweam{B^GF%K|otA zS^$HaWZDSTY_iBUE<lA#?_PwYp7f?_UWPor46v2jlaXRg3qS%h1T+OcjlVOEmW><b zb8=}JBC(7HYdGT)Q$@wU5Yub;LRyMLP=`_6`InM-_NTIkdLJ=a5!kx5Vc5lx@KeAM zaFznvzYv7&Ycj{K4At{BEh^xjv%o&S+=;&s;9#&GDtJLH)CXvII9NDHm=BO2kig4r zA)wIE$)GXV*a4{ESg?q)QG7xoDTSz`lXE};kW*MCDgS4E0~RH#lA*CnP@n27jF>~< z*2SjDWpZIZHWion7d6wlqQ?1uLE;Y(FrOh`vqo+zUZnjaQU`447@C7KoHswv%btR5 zvI!OX+`6=B8G+Qy>Y^C2iSIqf9I6p%;2l@18C0r}J`b`n-aINfmJ(JF6f@Bh{)GVN z@nr?)uWtA0r`|PF&NRZ-&Pd$(IKH7EaM;wmv)Dvzh?&NrijnNviw@3ifWXeW^TZuO zdaaHoVK?+uRJkni0XUI=5n(Pjwwj{T*3?oAPen<yssr#g#8la8EDdHT8i?vtviovh zq@;ok_NnCCl{tl@?;rxDHl5aD`|*+di|I6%;`|Q7@GSE?e`7IVReKg_VcGL+Rns@l zN#+n5t;)<o2F8bo^ZfeAo;1&pwTN20H@}jCVXb1#Foz5nikJ-e%BX=c3a7`!2fN2Q z$An3}lZ;-p^fF+%(ZRY|V97+X2f4=7x)_2<J)4tFjXiE{2PXqrQG`*tiY%11BC7#S zS(Fh!8AUZj*OW~65eiKvS3o}l!%0HO<9pK#9sJHNVO--+W2NQBYU3t>Uh#Gu<H$%l zDvE?qs@~Ely^?NA*D!QQ1{-U_n`&}<-m*zLc^cUEsyy)4!YYcZ2A9aqvzbz&kgZnK zO|^>RaK#8;T2wHJrDT5rlu)rN)QgPvBfe4(R_`Wdl;l|*9)u3uF|{D&TVm#4i>6>E z)rx)#jyv=45nwy|V^*YcFI|wFCo)wIzeg)irqzOeC{-?NUP6pu!)b*1NsfZsZcI}V zRzr@d|5^kNO9(8h?Wp>B4pE|ppNPavU#V0G6kM5bu%QQ|KG6kOp8@(T@CTSI@b!LY zaDBm830rk2+WVC+Rr*S4N%p~7yLyv83k;LOrBv*da4UUz816*KpVh~|X*VUSv^YN) z$<s$FlFifvL6A{)I!qFg-i#ob+3+M@yap$rC6*XS^$c^BlzCY1YqHVS0-asarxBQ~ zOM@5r{z5!!K9V~(g7>)o6R}WTTvuoj>6A<eb&W27Sjgm>e)x%?J-Jv$oN*<DKVphj zZGOX=*II~;84`O7AD2vK{`0T)#cUXM8}Yr0H}{Wf3I1R63^|Rs2~@Mb$Xo4-r5Ep; zHMqKpuQTjlJBfGBc}8!C&9DLD0~@611UUg=)Qg!iNx?<L!kC{Y2#-h2?k+l+7s5v$ zhv<-TP~emJP$+rR^z@yzMv##B@@Xfzf<x)VtFjpOf|<4c><n#%x1S3U#&hH-+46oV zs!W9!^)~)ZC8GyHSXv}ruU4FkStVL6kOgGCXp`r5P)|lhVWbPiPEFY({HP<z8xfq$ zBt!?GRVKUy0O7=<@}*T&!&+96Q1<N4Q85vcyYQ#V9>q%VyyErg47N|7H}`UttScG7 z3ptbo*{G~*L|iW7Dx8Ql6X}>q2zGgjors+=Myo5PztZn<h39T4Z!{9{NrG2<Q?>k{ z7D(wI`)VLTf`Po(XZ86So}sjc%B=DWZSqCp4&|ou0#fx*zO;w=WO)m*f`I^CX$pZO zy#~}F&z1AA!Zhj{j;b4G?|^)rvp*w~tU`c7n&*IyI=c5QK{88q-$bQfum3zy7=BRS z>TYn(uG*Oq!A?CvGKpavg1wPB;_CaShlpuD-vf&!it`9_Ud+nmJ(8C>Cri0<T1Q!$ zuw9zOX>>B-(h)-x(&5ZRmcI~Oc0%A3ij&69Q@I^)F}79r#*m53GZd(zpTg*i%gD&q z=mA$)1ge4?p?@@`phIUf@DFN72H>Q+7OYD+%Jt?5iw-oz)zr`e6I_Cx;kdB4`t{{+ zZCjZMIi1AgVG2Ea3TJJc{NAR=6$98_>3h(PIM}C4gyWpcWjT@Y7hBO{ay&jfmaDJw zjepzCset9wHZPf%pQEZvl;fdDNki6~O@=Sp5QmEXh?0iM_?2cafJ){ItP-6+gMQ*B zPv!hpYEeb*&DLI)s`b8fkpp|w$m?;(dB~(Z3*XbBQ`sjfUIDn+!><pCe<5_KKNo9k z$w4>S?G6@((z5}=)Ju0|Ld#X)(FI;8FskYFnHuwooYk9x(!RHpmvZG<wPG){q@u^* zmJQA#`z-$1n`~BnlarxVH*5OyAQk`*-ycfkcw1MP^Ak?=FcjZY9J;x&H7H-2^OKW_ zS9yxc*tm-$w0O=>DVY*IyBtxq3ixM3zLrceNzwVd55a9Y_FPry9d)e497r$<VJz6W zwlue)_vwZ;$01Ga8HP+v#e+of(q;UiUkx=&8lrQ*QJh5#vTKUs%1AgK&0f##1@GtD zRW|D9F~Cb{%On<Qh?5!3V=@BiJD|U}2*}KYTvv0Wbc(KhU;HRvZAr$2R+!QvG9k1& zKbNTq@E_a5mo5FpfOQo7)BVQ;*6N%KCg542nolJpP-6FPAG;Wej6_<3<IJ2`=8O8A z73o~w5^<T#{IjLB{MN22vWJr$bMvtkOp<0nET^%SoFH>as!qtQdNkbs@#R?jYr9Q- zeE)uq<#}_LeddkZp_A4y<$@jhLdQ011k6#V&Ze?}-0#gcg*<r-a4OlNDqu%zV|Z67 z>XA?alDKkPiMovpRj*@6B~PYuV6=-U=E;D3v1hRj<j-uKa9M48`hgk&)ya+!5BN{8 zs&?Hge-x6agyY*-pJ>%r;6ql((%r`u!s67DxdJn-rX%*F&Rp?oOWlYZBJ}P;Rg!dt z=_-=-bdAk)P7&agWwb=(nVxhn3g!nCplmQ1@kQsU@tbhV)_H_Hx>8Y(0J<S+-#C~= zj8|1gcl&d3Q&S-{x3CMoJCqJ{;N4ySg*g1fd=%07><=}84b(=qhE+1VTcevrec#|w z*8HF7k>YP%dm;(sW4PfU32zgrJbKERIV?ywW%x5FkKc*eQ@iP1h5oQj`Icr>8te|e zH@}}*UQO3e_!AI;GcjA&M(5pbrTblx%7n_^jBM2alj#vM3^|rt+>GK^`b^;reHwzD zmE$MT1Z(8&T24R;4Nz^NSlKj2G?zhKR!**cqIkAf_lZ8Kb`1Xuq6}yEsw^_ykbMU& zMojS1hjA!$eUULStY|yJxUiCNG2TpVN6-APBgA4-W{amP?)5*^1ew@`;{7pX1}YsR zR!kT>qJ;wb44#1)$Sj`>F30ZDvZv+7$3LmW1+oA5^TQHmb9@v%zZgeufMAJN#$+es zdqnWB0EuGE(y+9n*Q28~DrtHnjxp8IVh<c*g|bB5g4xS&C)?2({u!1u)5v2JtKHFk z!~Yw5?*Y~1)9sB?6+#caDkVT@B7`bZLJx!z5=sCS5G0{DH7JTmFVYff=t<~^^k$(; zm5x%BUKJ6r0P6qa|9{_e&-<-Y?!D_<-#X`h_gz_8Pnnth?AbHVGc$Yk{%wo)gsVc0 z(et_1XEVjh*bt{VS;h>rL<`8gz4oi=-!^|xb>yafR!v)W8C%w!FqYR`#$*O4U#f<f z$>&r&7f+w(S5cNRVIIV9au*6+-b!rv*z!C^pcob`uPc!HW`JK9uAa%+&29QL^?!b1 zoZOGrZ)?w_@{6A-31ykr_}(pVyo8h?{OGQ*GGY?foT+>{tn)oRAWCb8-{QMf#k8d~ zR5#bxIbwPsj3;eFvs{Yp=1s*Se^yPyMQ)Ni9+HL?u!i9tWWM8<y$5EU`%&cgnoB(x z*CsAoyVE6tSU@-);2F9iKmv{{@aH>(^FF+njt#@Ij7&m45deV|_MI|M>GC}bkf{~Z zQjcQ~2sVWWeU>J~%+@4k$T$<9D;pEbzz3u&^0m$jMmn8UrUpZe5lo_twVB{Lpb?JK zj~N*O{LXqHJ*Zca{sLu1k5%aZ7$ai-v3(sl1Wy~8WX<PD%)PgTZ|W_=PPY+XdTWyD zZqzAPW7~gr|3QUQ0|AR`l@+jZq-{$G%wuY~(jwqV`Td0rzKq);(bvs7VP24+*~RU! zhH*|@&qDHq*fMO&1!!dLc}L}TfX|<e`m`YZcl!G{cYN=Y!Xl^s&a9_@Pz_dok>m^| zo<&xI_loab4z%5dl(MWp{d}1M>C1xe_}lza<4QgYKkZ1GAgX1&?C8sy6mT;SNY`<= z^J|QqApPiQ3K=?#N%|}QBt6#gRYBp&gyy4!v}RMXx}W?*+~1NKVfNflsj<e3fM*tG zXuoAEncx4Sgh^7&omwhA@daN9c%pP`_bj?yn_!qiMXYx-cEGx4*7Wa`&mPKM?nm?B z@vh0vIT|3DT{|Z}*&#`>a6Y^7K!!kqtPOWLu?VI_&)3=!SKQ1oksBAx3^31mX}`q= ze7`pOqL$MtS6AqjQPw0+xfxC4lDx@jp|tuhy&7fK3x{Xa|6T=I#Cy75=Vwx<nCZ`7 zC{yWk>HdA@x=mcqP|t+e=~ewpMgO(HpW^sG<*qh>80-}NtO+>tHIr}#4KtvTf-cQQ zGhb06j_2GMH*;;8Eh*?E2KbQ27K&%FF_+D~KYn)=b_;D;O%k-rP6>F$LQO_QKsW%m z9a!YS4nDf|*t8-NyP@7;-{_m$qQ2^rEKQFBGe{Ct8Y@#xb3)b1enT4>{!%F23n1t8 z5jJzJA!&CKceO*I=ec~7QDwQq>YRksbYbz_EhyQ+tDgk4`k0eD?h}%xofF#g=fibO z{-8S1QSLarvZ~?zf-H-^C0h*KHE$qY_?<!*6ajv;71j7Wdx<Pl{W#+#!@GBTJt$zZ zX1-x#x-*)4f{O#HX>k6nd)+%3OU48iy&^8L5_Xrh&mKlTwmZ!J=YRgic7<qq9?o05 zXB+L?;`!S!#OSOp7l&#b%<f*4BgcW-b-iG7=|`4G6&0Ci5tngfwS1!6ty}Hv=&*MN zFBmLbz<}GO##H{T#uDeUZd+TX*<>N0&SjIYv=sCQ1g~6u8?}~V|Lfu-!~m8^cr_72 z%iOfXXZBP;^}V;#OU14AjqvJ^0~Kj`dV{)uP+hLCUyS{;8h=(^_4d7Ie-cQ_%l`-! zct5<KMz-x7uuPQyKIhINZaR|uORD%%&VcX0U>@fs#e}PcC=+2B8e+qr`TwkhsKtvo z53~iL1s^WTiKsr?@*?r{B5=unHS0eT|1-1rS(P~cqo@Bf!{1urpK|y=K@LkT-SN$u zijo(U?kx|5<fgnor9&P{6i$k`v8rh<Ay?O`@6K}mL3O67cfYjdbUN9ZsZ(_}JKC*h zuCPCg{)=|$*9(EcVgu?6bC{j3C6nBwhm|TtunxUN$Z7^tk{<^5u>yHHpf#lFYYf?P zYPRsgjVcrVa-kv>f`Cm?b`+SWsLqnn6xJ1DLN`A$&VT(x?Im^OYjf3|MIT>jynKa! z22v%1P0qso+?je!;W-Ed&3>d0#U)?cFdH4prX(hS9ZliWrn)skErDVC-?xtM4_9?Z zt<BLmLSURo>a~Jq&cfJ-(`w&qI6!hy*>NP<=<s!`N1oO^AOqQ`M`Z1l(#iCX*^HH7 z^EgCqVX@pfxWv4kuC0opxr~F?8`HWWBj;hphMBlmEQ}25tA;d~kaFVJm%m-_2wyvP zY?W_pJ7w~%#9RVPkETJBfS0OGsBYPfv>bEF*M7sIFigQ>JK*1Ua>~Y|EOP{qS-C#z zW!1{SJ@aa<^B)--sb{ux4I!23CVjxQF7~*{Y9Dn075HlhQ}GgpK~6>o`pivrRZ%@u zKuD*lRzzMH1hbvJkbfdbbYb(uMNWsmlj#NfsLw5Gj1&ezoqY6s%A5!iQyjp9>Y?&K zsD4CEsO5iC?T8n4tuaV^c!V@>&Y;O3O7LCQAUE@Kb#~A<NO2wJtiDc0e^?bv$Ek*t z510mP?_u330R7kPbcD&rG15KDv6_9>F~R|feIa9q75+trNJBtUK=CQ9VZbBpk5j8Q z4H_%m@mA2uh>46ZrbYCcr3IXc?(~+X?ULOt4YipL@{84h&%U`hDIR8o*%X9|SzzuC z4w-{yCrckgsSiPhvRh3ZDM#}=`V$(JPoi!;5{9)&AXZo0Uv<&s!)jOsLn?>t@hL8! zcCPC`DPIe>GjQxQQAaKg4Tq(Rg>6dqnZa%WcYw<AOstaA5&)Mc>KLJ(jOGT)Q3|uF zBb?+v0*lt{wu>4%o4{LknidHaD`P@SD3`MQt9~eN=~fUVmT2el1~SP9#0AO^`v9LN z0dRGZHiB_1l_59ufk!}(DkV*XC7dSSbXxaBOcEp{p?ZqN7;1VNim%HRjhe~>EwxEt zIfDAi*Y~$GD|3z2es5pCEWK>y^KEJ(K6or1`XNY;iX6u8q$6bRj)|N35U?@G<fG_F zYZWH`J8O3VnX56fSBXG}Z3@Fn2B<2j#|smg!8a)JGN>|B8VW%(RC7S9cIRhWB-Q=i z>wNA#+O3!jEc*&ituzK%F)fiAzCLk2hbuLM2`lypgPgXROziQy4NSEO{KQ3%q&3cB zJ1{MeOAD4Cd@^YKBQDO4k>$l)uC+xDhe=3~B|-bx7H3ZBsRqChB&(V5=*gjLu4>3; z5yTGpOsTQH(6r9Y4#<@xSSP*?@bjOkYX&2b#U+K*q@MS_w>=#1Ukk!KGXdD9$9s`x zEp0ho=$ML~elFcrwHyDyRcaKA$G_Cb!pL8T*+vjz0{cAbM=y$f6_^Adg9NPZX?^u= z0XIgGk#tX91XyoK0y*PGFMgH2z(PJ2ZHx#j|KY1yz1D5niheO~%8K0X%Q~8+9kS1L z9|&(nX*k^GL<kDC1@s)NPZC#dsGgWo+ewfOWlT2#e6jpc7-j>}kgC+3ps@Knt|AGm z^F0F?DIv<p1w%+volVRqbtcZ11S*MMd^4A;-0b^WliURQ{`K<NzqzDyI?MHMZ~sq) z!WI6a_3!1PYWdF!-w^!282R@K|7Uy&^r<_^X}DQmwJysqo3cb=r7Bc7rv>76k_^5Y z6^EAmM+rp`svE%%1>p~2PkZuuZqDR{-24#qjr}cnA_Zr$ae7ZRBTou40rWK~pYTey ziYD6ZO=AF%=4C<s_n*5|W1fGA^kKXAl3`Bd`vZ=Kt9w7iJ?}04FdF;bzMoX|`OZJH z{eM^>H9!7p%Fpfl5k@GYr7nxhp042fdT{OocKJb0^AqZh&@mU4yet&`<$94k`}1Mi z=f{_<PHVl?PYEi^4l(WL>Mbip9ChY-g~+N!M-144h)cgfs`y`20;Nk;?2`GGCe3Vh z@*gbI;co5^nH^tzs0QDmc^S>=Yn|guEN5Ari7hUb6xK1lZTHcfCvjou#<sk)#McS- zRK;TkE?#Nruc`m+h5se*+r>sAqW6)LOz_XI1y(x14)%tjaVf*T6t!*;)v;4P^X#Ad zmJ6@nC;UO>AJw!2T*Y!Bcw`t7b912}`>Zf<ZomtAYa3GXjc+{_2pWWd2^H?;4&PU| z&pKCcO|kVnrG7__tW=2rR`VJscZ7|R%q6!C0kT)vE+28n<i5)JO}HL+B{smsG=RI& zz*UV2jA8V^k3{ZcHsX*ZIuay>>d==n4<SgcE<qayi3iyzGrUwIVjAY}K(6LlqZlSG z^XW;9u}Hi^xWBi#1>Mr#nPD=4zPF!Ypa}bS0Bn<P%9@1lhLm2OWUZ48f|fGqdtv%u zU;QXojQ}$~CKERZN=?x@H3fWr;SEK@>?_fL80onMv(O!rPQ`G1`LrAoB($*a++#KG zqiz=jO(B(&NzT~ql6=7>dFdcJ^`eNPLDgp9`?fSibJ0Q>uEp<mT`==@$~rntzW-A^ zp6fz!^;{&ldpPG|R%Z+_2Tzb$(EdPIuEJ$)dOjuAvD|&SA!i!;-qIV{(9{n)>MuJB z)3F)BGY5=v?D8&<5P6Wbn!RUvT9nC6_5?uo4}Hh%to5O7T3>Ro@xg~%CY#z+|0--6 zf3%4Vyy+logdn7qc`lZ|pVddbERRb6a}q!u*Fk?pX2Yi|*R(<C>a)ft>lYa2`U8_A zecW1&yHtx7#g~BqTNz~g&2L64^Fh#@ZkBT`2KCghg!IdCy>oZ50<P}*1pU1jjoS7R zC)W}KxWt!7tJl8(ng?zy&c+-^FK8w!vFH%l4u4-H+gH_bl}sSLfP;6*J%qVj`lg() z+UXkUMa49~zLZn`u6;*<l?32P8G&)#@pjMRhaHVz2zO~HCC}e7_2v2HA6-=wAYz<V zKC0OpzWBQ&(;%LUEdJHo)6*h$kcHek-arpBw5L43tgzx7V1}3=I8{X170W8;6$OQ_ z@V?rj)2pSI&B`%OgdrXhP-meJLAx(I<D!b#G7)unbS*o0-2S0@V|e)E8@AkWxaiL; zEnD1<qy@Hvt%XM3y8{G?ccrG|oWZOOi-m<PZDk_YY=BARSt|5M-=R%s%sYkl99>vM zP)ug2rG!M)LLm%`^TcrK=^Um9UcGvOA*85Cp5q(z>KU}Oo@XZ4EDZD8&FfzIg-?%z zhVD#Kg!Q{~zn1Jv1=>wZ?d^YWL-4FTJJP(-uu(UnUvRb>E1*FEEjJM5H!Kri9ps?c z`F{Tor*3{1?7V(GYfi3g{QY*me|qi@DsP|Folg&&RKI+^{c>LL?n(RgPe~nN&QHJf zz1Oap{oh=o2Txpk8|pl?XXH-P08PHQm1I3FP*MS5`0K5w=__!=Y?xE+dcU+lmGX_0 zk(*vTc76QK;mV1}A5;trh|d;UD=OpDykOV&F0J8K+|@<c=1PNWdQ9ViT!;s+!7xwO z{2-R*Thw&`V--;txE$fF?a5S(FDk5dNAAXO+@kMBu?EqR1fLMVhQ^=5Nu@@QZ1gsS zQfx^p!7H9m)z>2zSZoSODaJ?-Z~hmas*i0*Woe<q^dL<LAcswHEuvA1vy{^i*DnY1 zvSbl^q-Vgv*3fm=OsEuie*;*Uj@+t<V?1Ovc@Zz!Y*m$dU3CW#1!L*rDrP}dV_%;i z74@Qxd@c#}o>r4^@=PCZp?qADUNAP7rvvMS`Z_2^aiGMxx`?#V6*R6>04Z}-GG$#A zn;(1j?IZv=s90!!$ABLwa=ZEjn4TtjUH$NMl@V$POx4v=L4yOzw-an-v=}dK8?V@n z2HyGp5bPMA4r>E`PHPN$`1uTPhjqA>Xb*2J<h!TslKzt7x1W3x1NtTX6Beam>v%0R zvu*LMjnQLzU#0m3=qPsFH+Z5UE<`&cYRh?R#2+788{;#gzSRixm%DJ&zj~?VEu!9q z=kWyO)TKwkx#8RfBKn6o$H*jqo%@3B%ZLn&U%_MGYfJ`yWo{KlA4ADwXF{^f(Zt>q z$dAl=fD~nJYfO+HL+dt|8Ym#?Bt5}K2NOs(W22St-9C}!s*Rnz+(9#ZQ2k5RNAK6S z)o%EQqs_dYuSqYl6do&f%wvN;w|fGC)#s@x!1+73jQLSfbVr_Xb0leUnxRpwehp+C z>fnto=0pigiNtrMAVxWnU*f6<ni@E?_2G%*@XUrZo304lag^F$va<Tv?(2bHr~k#> z|1olatkHhi>;-D!mtvPNYL83>MpeVL-Tp;rQo4^%%4T%!@HKarG|^jL;o7fZ_=73Z z76>gK-KbDtG6R6dnoh_*3Xf`QEc86v)Q?1MvgCA#M_wb8UD~Eiq>5QE5ukENINbXH zbH-IE%o5=zQ?^<1<mu>9e3T0ndPeAD$uhmhcR6)?ZoO$C?sE0B6^{`8p9djcTcU5L zQ^%L?;P$c4Y@fpsh`AV969%1|{tJjNPZ?(UOcbgjSJcs>Apu6euz7wukJ4YZAH(+f zztVn@?PQfSDU$kyq7x~h=1kkYkw>?s?RF}c_e=R<q`_O_T?)S8ny~~rw}xeAXW68& zNm%}D7tDhBl6s5~b$4K2<m!1xjoh}gB*qbSyez7_!o^hIg06H(Q_X!6vaGLBzs@nl zlHnV|GzEjh+Ezj=Ks`+vQI47hW(|{<c$h-Ske<08rq7(NB+G#s>vjRQ;87MuB!6&I zx}idrB((tRvex(u4`luA3Pgn?OS54|NrY9N8=EFczHX)-I}=%=wBt8r%_k#uJqz=j z<?T#3tLIJC`6t}*<c5_B{TlmcIVcjJdmW4OIIG9o;7B_G{Uya65vT&=MO*$rpVE-@ zu5law2BqB{+NfNC+95omn-cNX5!YC^0x24~QZ?9AsZ3~f<{)}kiJ;4J`hj~M4R357 z(?>R}j?yg}u$p89IyW;o;vpAqs?NAf>`aCfdPX2Jr!p*L{ZLw8<CF;dT;qyB!5~$* z@(YXIzNW1n+_Ht@*FhMzqAH7FL_Ivjw)z~+V}*@f=(-|1KXpIDGFRik2ymonz6N5Q zMAavB6SA2wYj-g`Wv+|6Vte|siYk|{Y4PQaICqF;0(G~=HIo2Q1JR}(X`DGtH5hc& zv3jtfm>|M0M*DO@cZPA20-O*GSVxe=2iR9fxn*j~Kw723XK)>kFw3-;C-i^5@Yv%~ zi{GEuWnca6s~ZGX&i&x|C9riINk*HV7H!leNtBXfo<R4{lMG(pc9wpPg~xW>?Umh* zec&AWNv`me?PK7bqmkbnoWAN!)ec-0F%bElNu?%lrgI!Jtu|Q2(I|ky5YOG|biGdz zCdFnvb`(MAfxGSF{;058QcJF>gO2a+B@p9X5FOY1^B;hRa<zaQTX`pDOU))_+)Oph z3+PKuTTgmh$Qqm9HPL*@*do^5((H3^<EWQ?j_VtNI?t=Mk$D$=Iq302{2BKn2-GGS zxn_3N+?A-!xPGn~pMFE&qMOuQzVv>ZV%!neejeh}cAQ<x=v{I<SA3s!2e}cvK&|bG zN2Eljy%kS1jf<X;!@;bD{a1P@-(We-aI8zY>sh1+bU<03h$G^3`I3zu&4QRQQ#=py zMWX0t^%pEu_e%APUgeQ9BOTFgpO5jbjb%prCAVjjM*#?-yRHL1U|8!i1iM~zuuhn` z961bb=geugcx<2T0z975D%L0P*@ECQkq`tq_?3RPnijNWzk0gqZL3k%Js0ozGouqx zY6qp>Qsy6a^YjT?KEe0gw9BuaL|v4e8>4_Oc$kwJOiewdUHG9#b0S)tAEU=M%v(LL z=-SP50{6<Li$|YPva-zf8l92;eX#+SZSU?01J>dzVR+QHy^h0liv12rw6j<WlpS<G zik+0(scFEAcGJ#e2YQCM&I-`K`Vype)X=pp+A#uIM4!zr!Dr*j>fgteYqZ*h4?uT0 zfrKyBt;EuU6zvP%H)oM=Wo?!lW%IPgEtt%kv^p;uEDVM?hnR_AfA>p~TEY$5-7F7c zB^u>S4|SnDa|j5PTaqzWed>0}zc~OF^qCyiQDQS@@X~B`V}U1A0cD^5A0C(}$oPkp zPqi7bn4ZMD9<^K<>s`?iU?J=k>%Nl4|L9<4)!0PJyO_1&-WEwm_92Vwp8Iz>`@gwa zTodhdR4!!RY!x59-ucatHnueX??o8p&C>3VnTck^oj^GL6Hfj!F8`VKpElxum3Smc z($ao66pskY=jMDYT7p3|6lL$GW;>{lZh5ykh`|&+<q3pjIa(CK)gK#*x<(4mI_sM` z!fn(WC`H`k*L-@47-i8(G)C!wGeAC44p*M|*_`+ECH^V(U#n|6b2D{xh$cg{!EcLE zdGfWip<bF7o^o_?4sKPE0tDQfkNJ*Fq9g%{px6=hm5CRgqnFh2LCcJe*Z_<z)g%5= zC$!Lsr0goDG>yT<E08#z)r$L20(jmFrX8|~onr<!QOZb^JuV&Zk=CN5@dBqE_qj2y z&vGg<aceE55U{2wJUbn^%rYF8L&nxhV8WwDrjg~eX{wI}^^ywv#$4-_KZ~Nq=JdiJ zsgjGJYgy(KrQAfR1j?VZDgQ`&EbjT&m8s&Kz@A3QOP6-2>Bi^SAU@~*g^-))<p#bv z=6~M!yI}v<<iW3vIpXfvwFBD;nFkm*xy4_tXX8=A46;GG4V!!&CK_kya`HGdhmtq+ zeXXTG$nxwP8Zm1WPGQy_2XCJFw0tksIrC9rdfG;OvaVx?AS%SACb8h3b9YC<L|pj4 zFIboq)N&1iaSPvQQ~Yx_m$#o@OngTCAg?%|wtmi=pt^D40OC00to{0RdeY5bOWURa z$_}T8YaCt810>TC#o3+oVXYm(b9jx$h4>?ZCuOgrKBi4_D(gXA^?KV4n6?OB3oIJL z4|^>%#3VT`Zke~k0&YmwI3}@}yWgbf--jtu<Xsp8W;sK#o-~s&hn$?OSJUoHE2UR~ z6gnF2<|1rhxP6`b?ss@4-)7@kxXkGlR)g>=ypAQspbtRhY(qb@a<eRgyM>4IhJ-o| zCK_L$C5a&t10VSIsNZ7W5k{Aj&#gqo&+2lBXU=n@a~^8zoNQrGp8&FRZXlr;*%Q5N z+;^U6n5UEKd(4Ea-d3!yhnKXwYWx}n4=S~_yDV?8%WUX1P+1I;yL9#WTNeK8e3g%; z<voXoSwm3NyKl~;X8Uzs?)~>)=oZB^Nm^&(gDlK{lTY9>0A;OstD2gGR)`Vo9(dT& zkMvw64{uS`Raw-1I}w-YZsfiRs;^PZ^xz_C1fqy=j`G6bz<kd<gPmL11O`v?KqI$O z!-oh5Q*vo(RN+?K7v<~YeOSw*>nEYz@oUqQCYa=j^g|a;8=cBw$t1N`L3Yvi=gx-< zX9ua*=6dNWe!Jf-C#oXTV#VeS8H~etK`K^o4aGNV2A!5WuX+9%D$^NdU?$^o$Bk^Q z-b@qWgYp`R<eJ+V`FU}m4@AR{Bfcd&PXt7rS;crKi5smQ#!Y0fy%&3T9SrI{-Y%9P zX7Cm<G@4q9#>r0Dpbok>A#Ki-x0wn{Tq_g2N1->~`vH0`6$J2iOP%>iS(7;#hxr2^ zo=77e{OYyPijt4?gc&^xUppQa6_4ObXM6g9JlF16ebq62$O1o9&|z5j-d^F-8#w!b z4a>__)Z^5&Zg?aZgJMtC^1F>#*>Dn385BCN_Dg&~yBIiR`lg+HBap#txMHoKP9PJy zH8e3G3x|wjOQS)s4&7`1l8@;TIiW9a9JQfVu7PDusa7DkhP-J;jdyXn)!yCYGn>|m zK+HB-!isl6w)A?`U+b;ok{wL1s;@d}g0tK4X<%U1viX%j+;p*=O+3O2&B@r3qR}G{ z4cP9NZv@*Ha@acA+&YF|<jr%$pBO#M{lMz+JL#>j%rw`6G-ik!7H?^AH#1}LK^zG* ztyQ-YEKM}vs=!RJi6YN^)_9iGk%9+f!4}~bNw3ypRQ=o2Z}(Aze6$9TPP_2|PCF`z zlXt+H-h%OshH3zTz+Oag`Z#s_sJEM+gsOggWoXMzuiE_L%f&}13-vzy|37}c6{XsO z*-}#m-4)ccBGwYA10$ULC9gv497li;C(m@y#I?_RzY!hh!gPPajw6Q`Cdo}fkxY=R zwD&{k^xGPpCLwtT&-bzZLVRyV<V{Uc<qQ+9j`uF9PxVzKOQ?5Wda9kr%goH59i`40 z($pYh0E%-5>lsCSVO5;mlW}?GWYf98T#ajQv@{1tP1nZ1$Ccdg*m*32s-C-iSyC{# z0(}d5Y+&ACtLtgou^%`40YPmIFLdL|2<}*f<n<}<O6!K8+gzfGx?1lTLKCk(U%aP2 z=eta@>JG}x#n<J!!YPEn0-=tS9RZvdjsfM%C!`_D`Sb;erZ`u(kH-FP%fP`ul<FC( z$&4R|<#--K`SFM;9#7?nlvS1&%UQZL;H6gvL-UJIOPLteB!t*>_9(wNeqyf*52x>_ z-Lz92dOFZF2yB3)!Q#-Z4Xg;4DD$BT=NS*4*2roYy?2Bz*GIO~5-E@w)=2~ZKGVjR z7kfZ6L1Rc=`i`O$Ih39}&?rNen6U@9S9U^C#B!;T)<3A&RW2#$X6S1~MsZ>gsk5X$ z0~je^-*L?pzNtXHZY4N5c2}R(bD-Bj!6r<LP~HbTJPR+@0st^gJ{l{_NyVpnpjz($ zpkt+HejdKoi5;!I=N^0BjH!3%Es0q>KEiO|Q$C(>$Vxi$@6o^pdySaTM#&qyar=Ep zpEZ+;%>}4}g$Loega}8s-KV%&UQKjJn}>j0+O>Y6`*{P|k!C~Lt@o$R>lU7iHGp2# z>pQ7vzaH2#A1syVIC>3g;%OA#J(>=HXf6C4E8q4Y+c)75Tkq>N)>;;2((b~FYqutg z<<j#$e4Jyw199xniI!w;FVjyfr;1VWQK^XAB7w^X2(=_to}IKv`$b#QSh<(U+G()C z+~z@frcd1BrtNxtri)|4;lu63{6=@N$;q7%=H};nQ|pp#+Lv`8!=17i`1zbbln`lR zR>tzJXm5!$ujIJI!k1f@4dyES+uH6rjpL`JrasPCjDWt?a~awlp>9JC8D3*E^FCOp z&yzO}4K)ZJgectozxw~ae38Q#UJ91TZ8-wkjLv{=;eWdJIb_I)0|1>Do;`rM40oE5 zO`T=LtUHxNd?YKZOuLwNPy)+tA0um5vk9toh&siKJ?Y+eXR>DOv@}#Dm7}BkUTM`{ z;MWgrvt(3FXMrmc1<57{MZPM8Ay2E7_<+YrE;1H$(Cbj|9HJ$wKn8Aja86w={xQEs z6M^VqKlL<Ua)Fb7T8k*n%0B%3y^4Z#YTIy0I)5h3R7HwOoMbr>??(R+qD`=TKNJzC zt5<vxcI9&JNDGpsG*ZlPMusxSrMP>#bJ|r#W5E~Lt@QowT1&AF3;1Z^wU#Iw$mV<9 zQn3}gXDl%zWGS*8reWdfK9kQWdalug1n#SA^#KT3TU<8n2k@^WTy6^#w}>P!!cW8l z9W3BHL>#@YNRndqO$*IywvTdk7;yL%yi8WFqmS2x!JJp4swBH@fbW>A+pRmb_hk>w z>ftlXr|kHZV$X|@Nxlow8P7)Xv#)x!GOaMQKXk8<H5J#w@$p$=jiu5HB2P9<zY4Z$ zd?R>O*AmE1J#yWFlhOTTRH#ko62ZS!G=}M?>ILMGN6*r-ij=W>q?tTouP&k(-!46| zg~SF^Bqas^po&>jW_}_#7_#<gW>2bEKyX=Gt}x2OI-nl03aiLdiQ$%4v~of_p%C0C zi76qMR>RhNELAPx2${6tvF$T^j$bmF+d2WZw|ln95Jal>q*_bdBVsm#Ar|QS)WBT( zx><Y{46);cVS;`lH=3U5w8s^Ob7L{n+B|c7n5IYm`$pmCjnrM;qzA4Em=BgKO<3gs z)4#cmw03mm_+Eb;h<0IkvB=9V^VIvgN>;#7jV!PlWN?&1baf_@71m0i6_^q^(D(#Y zmv){p(8UOgx!sg&C4-|Xj4KCA7JOh6HP`AAXm!^r#>e$dOin64q5B-oEt$zit0xWa zB7RZqblGlq9_@&B4`3oUqRQj$tmTGz-&|=F?R(oQ?_6zT`9cz8)uwoC8UW#&FXpxT zy53XKBA&oicuIFwB7-+*oqskT%|&)BK{d>#bK5EjDzk115`1Rf@jSu?{ax4k%DV-s zYkILVKNV8_t!tB@>g-!D#J;#R`6lwJin8Y5gd>W5e!8ckwq){@_m?;|m|H51=P6I6 zN?H_3|J^B5N~C&?JLTCKunoR~=-|xo&6j<GYxxXriQ5h9+>*n>aSySlo*zsB2$@1- zL?aew{7s*Jj{e2bDvsfQmCKE?>8(Wb;g~F3T3tt*G+n(Wqpx0O)pQJa&u?O8b?khk z3kx3$SW{$#b|EXAY=PQ~iVc{C2|nG4(%93Y2|*nHOK@jIQER{h2^4B82DN(5i?bwZ zKic`rBk~l7l?e%iY>RG)@!-4t8zr$+#6T~rXVvL`BaB$v^`&ChK8r!7wL%D2#JEhL zyT!v<TFBrL=O}tJLTCca_Ks)@_2s@e!w#^GD2f<-b*kag%+l*sR;aEoFLSVDRq?3n zg(q%e{>hK7l#HT-_N{ONb>Zr3mj+KL!Nj^+9%6DL#=hGu*NUdgF>0$fEMC&8%}nF< z`Bo0PzLBboK{I%#cTGmB3UySw?lE?X|Ljhpkil9nJEwHpKHbct3+~@}TUTQEG;^fw zZ^IZ0lg>Fm-7)&BZayf!Epy+iSZQb*m|mYfQ;+L^2jg0dXeys7*9@y2BnLh)f77b; zJAmMzXq6}r?@kwDGcE`cFHbx(gG|5dm$oc6cig|obF)>0mmlm|cbbk^_O#`0r5C*= zFtcJ@r-YE0Okb>8F*wCA7H8`9(vsU2OZG@Nd)9BRz1sVE$F=U&bO%+tPEO9-NlQ7i z&v9A>GE14kkmYQb8RDJSqvyg+XobZu+_b2Nbl~UHfeNB^k%Jq1rF7g<5m(#%pGvsf zXf33-+C9qAz3sp}zmA3>r-Q?uE6yK`+{~u`o%+I^?Zr@bQ(2lac4KC0on%oB0KoDc z00OLvIwoMof?AI!aJWVC@q1&{8XYsf5INY~u_e9ZyUyf-`von1mRZ>=0%1(ob*mUr zBR7vr^9Ofx=r<h$h|>)S0ts-4>CRUQ{ex=xxE$w{=bN`5ElgfeT$bP*zXlh2_6HRg zM3PL~Y9Kw>A(`8#uYpLb7*`QGiX-O9YAD1ViCL+iyoa&>_O?bkyc$d0q_FQD<heRE z6ULRuS}TsN)YNM6+dZ6c^**zL%v=w&t;KE3=EO=DFP2~h4X!9*7P}(@X>!bTUrOw> zOXT(J&RuTBFWBHT96-%veI^2f0=Y8kD|mS-nfxRR|8#5N_pf{R{FoPm_%l`NAAa+4 zEB%{BJWFSr&voy<=+8|V6!B>eOIt?@5Xo^JjHcuEJ9ZDIab1Vk_UlIjtyXRHGlmWP z3e_^9U)gd4k+QZw9ypk%Y(PROZ5Ly6@8aY*&)hMXt7PxfygbD)-^#-k<=JrqMQ>*a z@o@}_e)Bf*1lfk?I7WJ;ke)#-`F5~r;$IVd#R>~=JiMp26|3ve$lcQ=NY7<L!Wi(9 z@hm60ks7c$FB6229s*Fqg<?=V0LFs`1Gh-Z_w356uW{4K2b236qQ_F9QSZ3{qQ!*D z<68FY1c=RJdmLAdzs*RZQdD!OmFW!Gi>k~iXGLQfN15U(^094Oo@QxtXzh_)^cIzG zdFLEmUR(}%Fbb%ZehL!p=gNJY1-{DuF4KF_nF-~^NjFrUFzGoe6qYhi&Lu*9X1WA? z@pUc7%WUPj`CLz#Xg@|3^>AOT_+n`Fm`zl=*r`+@-q0xPd7tTZ`Gi89o97n2%Ov(; zD5$8>D65|;epWYeM611$P2(0{T8^E85=w?VCoOa?uGHL|J-0@S+s=6ZwvX7{u57-{ z<@5As5EGu#8qMcRTGPUeK1R0qE582*|11ktzsc4NFen)riNB&mar$x}VYqNreJ3l! z3=r~dff$JD7tEAUI*ZApe)KEl_qSoKjHgmxGtz4D+aM5%eZ>LS_qhC-3qWjn*iBaD zMNn=hOHC8vG~QTSU_2GE@C9>blLGFWfRghHRktS%8PapES!FBLJG@GNelBn=2fGOg zo)J#R`fO*ubAEE|m5=r)e`3Xs><bWLF69!;I=;n@b9|ChY0yPpL*9HlWJ;8=<_QO+ z{|!Bj6(Ob`K#f_dEEPI$+9l;7=q(?oc`Jh_N0Rb5^Mc3b_QlgrE8!f<mvYS-Cv#DK zJGe+Q^P9&jCn7}P^(y6@Wnnu1Bm)hVOG>R7IXTGO*1n*dazU<G@p~33*`Z^VzUOH- zqFNQY@?o|aBU!lwGyt=v_=FaIEjPU&tf?|i#9F9aao@a<zqGmS@JSI@(AG+*3n#M~ zJ!BbS6;#H{wN1qt*KMGE3<$K62Yd;NZEW<cn47fu_*k{|2LA|X@3NYGu*}>{)^?Nz zUIe%8aF2_!n9C&ZT#0l>el^k$b*Y*Ug14<oF8Nwuu2J1~A71J5six|FcX<AnI3t>c z3&IyTgU0xJwLI$5W?2?B@T_v$8GK{0gn)C2A~7V*BItoJ!=4uKe3D`Gv%mldMKK#? zR(E=Xz`PWl-&r?PY*VC27LB$d$4ft|W`vUMLl^1Y_(nBKb!pST*FT8;t@8I-(^V5Q zUx=W7g^v$u5j#DoS1PBPk;Vr{<(u6OUxC$-!I36cpQ}1-N`Z+pt$MawTa&DVLV1es z!n#)Xo~Z(z`w9h`{DsC3B7Z$BI&;5%A0rYZNzhSp_;B-Or@vU1gkxtpZ9ZTVgw7Ge zaC(lA<>sE1qSU8c63zH2Q)`D>!beWCeyK7-tNFr%L4o|ocWiCT&A-6?PoPRw#e7Sn z@AMz?Vr#zjS)X}Z^AktB>m5q1tWp%6HE`vewy@`yU$WH0h}om^Gv#Iq4K{B!;->h4 zt4}8HwUs8>_ZM2*`<lNV8r0-g%YD=Gv9~+Is}o+FbvVN}JTMF^$^kKdPN9rFu}Zzs zb2!zl1pc6b*T|D4W?yP4DRk4*8#j4jVRl#9lfP;^NF+2XpGB3&L!eQzVdQD*gTbu4 zEG6Ii7r;57yGM`(1c=pjZsQ8>={ChH9dAGXR_y#zP@Ynjm~c`PbQG9p$8Wy=dstlB zWTWN-)_YT7x*^}vTj!)&Ir}P5$RojL+4HwE2f@q>dJui4rSn&6=1Q@NoAH6{+Gf4R zWTw5ZQJpW^R3<yDdk~T|w9d_EdZ|W?p%kP9vc?6(4Lp-LiXld^XQ$LlFSq$hhU80$ zfS!^nXJeb&+AOi;MM=33dcek&aQ#>y8<om6*;jk=9UIswXZx(@!!uq+0_I{q#{>vh zaSFb8%M7eB-)j>s$z3qqLc@)8MksD1Zpk;jPavX-<q&BlKch>&*Q=b3T4`D}We05~ zgFDHx75_Z_e=i44I1kI88UqitsX7Wk36UXP2<~31fU}u<T=&H&?X7!^%?Spm0gAIK z&hWk-_5>!is?Q(zw63!MU<d*GOHPY@ION~Hzt(514-46-U#@!F9|^SX=AwmGK1mub zk(;9+ep}jz_GdJ_{klf0=XV}%B*}eA;%Las4@}XsFvq8OIeAiTZ1xw+rQ|xM!#gO8 zE_Y<9hY)k%jXs{3jXQOSoJHF&pITyl<jg;(6d|xP!t)7n1K-Hmxp|y$Wv}5FD7)8d z+$aZOQsFvA$#16bwdgp;8q=ZD%ciA$bX3(cFsPqoCTd>z;*hu;{PbLLsj&fUfZszc zx0T<<*PJJ6c^E#s{VE)6Z}4%J)%TjG8TqT1JUw@jRzvChsaD>v4}*5$v*j0X`_d`M zQ1STd9x{$rB7X1AW+Tr?+?81d;mm1hznJkBKzgWg`WrfC;+*Bxo%kz~F>fYh#DJhI z;Cpwz_j_fQt#GZ!^QHdO6v^+uf<QuoBiK+isVNqQOr5*of=1qG<V#q}=%H=^ZW?LD zH?Y^*8JG{TZOY2RtzwY`tMsRlqR$j0*BPfa671D&xPEb-zDu^%_RPh%r8?1hX-o@@ zh8Wf7Syyc$|C?U`8qLbMdwePD3M4z~{}QgLMa{~$7X7A^{_OdIK{yo)N<iRDiBdbN zs>VJuu%0z8yVBA6L9>=(P2N>WDvjZz!y$sUI%+zKDJ@`=l4WZdc>C79l5qFKzG2pQ z&xKF~<~Z@aB?CGK**oB+3%~r^r5MB?tW|=49ah-vk24;eEETzS*QI=W;S^Spqs(sz zz?RS&a?d*jV-h60r30JrVlK^G=@US>*zEv-uCLX_Dq+c0Jrl&bWIh2M1<3X<O#K+0 zmYtcFkxBGE&qjUSB#6((bTBB+2PLB$hE$mx8WMaH_Oj#X^Zn(KZ^8Ns=iGA#(vH3$ ze93zB*ATtED4mgw=&2?|L-oSzVa=HPx5k&!^~b4$<RvbiMbGsmzv6+A=HP64`$PvE z0|H|-;(I+85VH4oW$Sa3(>LMq@d*}L8OVkm2dt|L^G0(U3qio^V+?Sm`wewM6W#1v zottM^MsAPMM~1eUKux`0NqxJxV=ZPz!3-6Y3}KRw^K|jg9-FMI?@Pf{$cv(xec&N{ z$jW#oEAFyi8!vVDO2#g<Iv#c|{Jm*zntf`yglRAE8S>HfPXlAhHV^gXhE#2%)K@B2 zlI%goF_p>mu*AIFGXo|f<?u6j;6`1>;DjC>r3A3E%4teCL(d5cQkL=eD7duo);ql- zB~3x=XR6c3n6reTKd4?vZ7}~}9K5#(@K$ZlqM4|xk`BSiQuuL8AL9rG2Hg(5w+wSC zOd4s%Xb_mho4<B!WcUyh<y=u#KrbRd(<_>83L%+?-20XiHgRVL11l^YpX3i<hVyLX zvrwEdrWIu!CMW7f=&+a^%rS8Q>oax$^h^!KF7n6(Y?I&>w|!!G&w_`3HnPi2cP{M@ zf95P@+?=B{DJ6@(*4*m>`@YCcS&heimy}q{%f!tFIZ)QK5nPYa#Fc7Zm+fE!;tP|( zwB1aXqvuvJ%JFx889K#V1+g`$<zAT{$fOL<52fpud%IX3XU&S3i(ff0J9?U6at8DD zMlvB(T)G)AXf^;g8*XY?AhgAgOEq#j_T34E%=;9h4^9N_Sj?P*f^B&bIbt{mUTOQ& zW3&5-lUPfd&Qa}*RDOW-K-au<;EmDZ?pWJu|DIqY#K0t{uXMTj=i6LJgfx6=js0g1 zC7!Hf2$|rooiBjr3HYn`p#y^0BrRMJD;CxpPF|4nX(@&0J=(;7^Z6ZR{2s2|3DQV> z|NRSgX?F1N2TN$`_X4VxAzT;!AV(kfPIWrhK0xa#U^6DAJou5H*vmhAn~SUkKtRlW z;47hNsYLJoFTqD(Ug<3w06}JpHsft8MJPaP8-7DFgj^)`*6phF^MhHV+Hby~hJ%Ac zJ)hK-`M|L=>2fR1IY9*^<Kt2eF%Hg9*?}l87WFw$P*g8XdAMkXfRUF5EZ6gD%At8v zLp6gPb49ZY|GKJ2ezmf+GeZO(LODO?(Eq(&q{^3y-ZY}T>bm_>Vc=aem-~#5E6U_s zq>Xm2)xPzwl2Xt0<vwHZOrIolJIt^(ic)4de%M9c;Iu5RfvRzAF%Z7G?Je9HGq+Z} zd!L$Y9cgYkI@GF2QfH?TY620`9RvD2tV0DSiuh9{zuYF&b=$LObtkn2i<%Zilu8sp zjZ_fKpnK!H+%TE$M2VNuhobgOV}>^>aXOw8-ikt@sF{>tuqTPzPwJBZJX-k-r)>T@ z+~lHB7%&-J@Rf!|TszJf|7MZ_vQLAMG3Sy)7qzM=zIEp3ql#Z-Vjk35)+?^ogG70d zodYNJu@IvWCCiK#S$ZTDytjYUOnE&rsPD)7WDm%u93*@Tf43=ErrV@tK${b7+f8i) z9IZ_+tcDyXU_)e}c<uZw2S!zTM0>&!>&{i`HrQ8$EKhmH$1Mv*Qjjl$jVJ&>i{4Vb zSVJ7gB4DkNS3{9Jsp0YRAnm&qxmH4J#*B2h9#tV|8bQR~n!(mPuy+88*Lal>!6<YT zFM&K{cy1~>RGx@}mx~i)YkZK0hKMNXV1@=}T%iOru6T}f7(=15!E%pVbB$D#rlsbB z5pdaJfSk3R%0)`AlLq+g_6tvKd3#LvE5A4A176yyDOr{+T0g)j9Vg}y;l3xgI1Px} zZ_%k|));xeGdPu2GJv%<g#bHC19vO(K<i~m!Y04N?IU!hFPy$qB#3!k&4b_P%mdNX zEV2>^w#xN-^eV4E`bS2<Hzrq?NN%T*AAn{3xC7G!!BBL-;*rGELfZh?e~T|%w0T4R zY&PDABx8zWD5=-gy8r?<;EQ(s+R-uS*huoUQgP9B_7mZs65Yp^(zj;1t{b!oX4=Ez z)YB2Hk2tG_%xiZ8Yv#5Q@n-OeqTc0V;`C#sMsuzEA)|_(f((4@5xGRV)MEU4q&tsr zSkRR<#o869l{(!r<;BA~fx)z@&#0nLA5TRMC=F!@uVm5gZ@9l1!8}E1A1>KXSa0^d zyzgoJ{7VwU=>tXbm}JM}Z<kJt1TRHU^p>dsXs4|6uYJco7s?=)p@)&7M$$1nkH&7u zcvkm3$?3!3<8D8Q*S?b7hr*V_xua^^ZXv5hY48g<fNE#YLYsUV3YRS~fldvqcnz9T zSJ6ag+A?Tr&{E0<E9#%uudoT<KJbqO_YOn0CUe#kCUOz<=QVzP?5`Az3#NQw%=U0@ z%{ca5i;}`A$$*zUn(HlA9SPh(@20unr#Uo&CdFDW!X_e=lYVj1_p{aK1}G~iW+w#G z2lfAiLk?cs-ikP%{wR7~GTSVjg?M3|vT~Ig_@XLo%oTkj;7Mr|x4?~DLsoo0!~(n> zJi@&H1#5kVnu7-pvQIqrDTNv`yL+rJ$PCI{<J*r980QzbE)A9pQ)ziBc>hbros&3N znN7fUVx06^CnjP-#WIIyK5hQ}yGQPO+yvJ9E<U&JTX^o{AV#)kd$;6qAT?nDHz_6I zFB+tXeEmrGjSZnuh;$)AnD4+KxAlsoWEk<aDZ*JS%gwr&_a*;5P*G%BCfbhLe(Q1; z#uQMb;$&8)J}nZYdU-vD-+|r)QWoi7)o(7^us@Te5VYrR%ZIKfKf?lRvTmB0`n_w) z)7Us9%bq{m3@pxgzmM~i05|0E8MOM;D-OPuK@R3Y&cy&cqs<I`A(OkKbJdK|izx%9 zc^NhrZvnT@!1tOB9(IqMmp25$^tKZz5uea33UO;)Qp$U`ka15~`i%<Sf$on<GLCTV zQfSb+W}dI^GStL(TQ>I2$zN71t$mJy-{IX7o(iQ6?$~1x!*3>Z5p@O)xbvj^^%DgE ziOh6GRjYA!49+GvX$zl|og_$H?hdb?9IU(>eaSTH!P8gT&f|te4bi%<n1|rF+7je^ zv4C8CUSVH6N$PdQh;9tc-L8CQ)tDrf{T-M*RXotk-d)Y#Q}G)#6`S@}WmJ;N$4O?% z-1RPMlF^aqFkKVt4Njc%6OyfDO@qY;OSZWrUwl_wdxA{JUo%zjj)HHP_~pxR$6d=J zEMsVDUuy3@xO*k(<k_FPuw5B5ct_^VATyu2aZ?$s9zHX<q1qvEuK9{pZW0$gIBuNZ zdRMSr8f1EhHfpeCQY7{P`Wh<Q?30Hx4m6aJpBnPgW3~U@km~7rz2XT?P3W*;Kw%H= zqW-RtPpL4GbGFbm^YZw3BKTp+y1Ou9aB7u*l()9*NfCWux+Sa{8fD&MW%3P*(tsRI zq)9XFaZlEWWGa2MFw-Pe)hlxQ42=1U3HzTz?(Stu@{nflv+&3s2aJK4$>k1S>j}B< zCU}E*w`rsF|DXzSJM!Clr!?|zXy?=HyxG^IUwQ1K=BZ}cDH~y%`BdQEiJWucI=B92 z*)H%^{IibY!wE%BN3S8))=R2!5pOHfs6|+*3RHKjLmJl=che3{vgKDuBo0RR4%tDR zsChbqMV1L#I<HXry0&-JqA2PYO@s?`(bNla{JsHKyZW36ZG1x)MHr{_@v#|R*4`&| zRXHbK1gR;Qt^WohLkVBdmuDh66ta`6Y2qfak4XOP<P))H(nTSABm(Vbd`8B34a>c6 zSM3)aJ)MEi#k*|4&g|9V-}r4Eyvutn)LdZ}HF;B^Gy=D9E#4;FWl3?P&w$^QDD|ir zZF<?r8yIf7SSTeZ-fysWzv!J@{?PUt5y5l--DGhpsZT~~p1ZsX6F)Tr$tpyLANF2C zX?=M_!f3P7B|~l$Uwsyzh&Z&=Lad(szuLSJFt?>VgDoElQUffNO8SH}n*Y}01E1M^ z6yYhLwb;lT(LVRrfAMl@*FOwH>1PN|p!=Ir5APfh&OnOAg}$gR)MGQ88xaF-FIisk zR9X*W>_N&kV5fIkm4~wKPMz&Vg1ysPq1Gm&qadXqt^<vSpB5NRT8(vM_)Ob;#*H=7 z$APVxZ(F?pfi>3GJcA+$$k_-l&U@Q<`XaSkh@6nF4X2fN{i8TB=Y9+NVOLk{cSw(| zySMkFg}%t<PU*)pB__tS%$;p4{oLT8zkU|}q13?iBtUz(j=8-@5ML7VfPFG;jodG! zrk->;O(djhB`pocFqvq6<&x?;P=>-=_~5hKbaKu`GF`&CM?&bfk_0<s0Cwkzyt8$0 zWrccUh%rx1*~;|vf7c`)WCVST$)X;Nk%xumzl_}?x*}a%;hx$~-=DkDb?~OkN*x_U zkUkbplE-z(MoKt6;UpJ$%OtATvM9h<)Gk2dv9IZo+ogS=DC^aIzOBPo2nv5~T5by( z*PsW@gU&$6D%~HCpZtSk!k^nPOcts1WH~xvRTA5|jS+5cbbPYKim>-MM&%rr5Q1gy zzI|l%xp>pE#GNENO06ThHwIo#!^C^H*vq7BlD<)+Q~gHjwH8tG4ID#R;%-94@lsPM zeJLDBeI*uG;uU*FCGA<)B$i6iYT}1fN_@AO4Z$X~MbF2K`aHax_WM1Ns{51nU;EnH zR-K&#YHC_$?VP+SYgDFZ1$K6mLPGv~B_v<ld-h+!)wSIRRlYY1tlL4hU1{zUrt7mv zbeH$J-RGt0d_0>7wXQsr1_CEK&s43wlQe42D%8z4&%bm1)Wug?BWUJ4Jv}`b9ipdD z57QDhJ=3Z`@WdbyJW)baOR3J<cSF{YAmhvpjeoF*K5s{?@8_tzrpE(k*?;0=|Mun2 zir<&jCtYX84kl8EW&heuXXKVt2LrO8pU^)AFR{$(U0&sgncz$6b5N(RNL7}4&OWZY zR81T8DRGW8A2xXG%Gqh_V*-%Y8*??B5ggg%usP?YlsN-0hmLRp5BAK&Y(Hr{Xa89Y z%Eg9nELb$LXUAljz0oWNW<mf49Yc)In$sPPMHhTAGaJI_3>z=Sg^t#j>h!?iSbsmf z<_dddF0B#A3+FI7Wi&lkI#1Eq{)z5`{j)F8Dl+u1vHN4eQTG?w&3~*XV`CCH<kq6O z(>MT*S?f-G;pM4CY>fMZ>e|bm`;hm5R3|8$kzJC!=7^W{U0_6%`%U}_^6aMBRNrz# z7N#F(29i<0@?!6wKDt3`VaR;3^xhEQ5F$3!&~@VETT9%)I<bJjO==C#J<d<uF}@YR zQ_*YZm?QMS{hhnQ9CNRNT|Tc`{;jZd1JLwD-ev3ucQaeHO~u_fh@^*8dB#>z9{WxG z0r#GoWnAIq^l{=F{`)-75_QxHd_0RrA}cET*at!wvM>gTE7f#-8F-8y#$7$NxIIbj zlIlF$c`g&1jGo7&A~W4Dl}7R1Z)$vs2_V~Xw0~sAhWp{omB}5ho#g3qn1A*7wdD8A zq0fFAdzsk8WQ$RUkek>hxPDO>pRn(9{QV15Y>V2?bvF!>C)h;Rcp|a}(vv|lU{Dj6 zr%`G#*KoI)%i6B$ijUQ|`yc)q&6bpR&ac>oQ}}Mr*kVa&7T1|;EK+b9>eHo`7#d+) zLS&+gZ;LN_0Fi7NJ#SakKE-)2I!@%Sh2<~#bmcC$E6#_VWHEOYKuILhb3xXrE-iKF zROq+&M#FWUx_1H2?Cgi`08Q$|-9)hbVdpT!iIQXFGc(9L?54R2FuT7W#KH@vq*(31 zcr;iysPcyA7|unmo(?42sySp>@a8E>7-Z5k`BjcgZ&G5jTpb9*9w-dLrB_9IW#V0N z>{^tWB+C70+YhhzKbU*ZuqL;43zVvWfEWVOL_rb=CA3gQgiwT#P?FF=1*8NB9VG}V zy(2;rAQWi{BovX}WGPMQ5Q-uoMXFuEE^FPaz4keK?YsAR?%(_Cd*&CIU!QZn;~itX zq?ffTZ0<#yRob0&v$iBD=w^yU{_rRcH_%j!PeN2U`xjUf1=Kq6J6o|FjEf3FZI_Jk z16R<5GrD87*=P1rCoU+r-JQ74=X<katLSPi=Zxfphu#n#olE$r_I{t_I&55h<W#U) z_X`oHAF>=TJOYfhXT$sB1R!P)><`R;0<wdn9rcDKH#;wi4iyc6_7?bSrc`qtnY<&< zn)!KDV-(v#_t~u^WPLF5qx4bU3SnMSm@}@xAu+7L<QOqjRn=bVBaNmJR>IQErNgR` zD#JLluEb&lLB?83v9*m7Uq1ZvTS)M#--)v~Oqs2GqR$w@=E|HF4F#(YC<dRGz%K5= z?6l`fVW@#JoLrRCPKwStwkqy1LeJBFUQy^rfM-kU*+>>-!Wy8uS~j_rV6@F|0(Bst zY-r2&oo{Iibh<ZWS1-d2_t<k-jO!Qd*Q>u?kfT0s6Ur>L7618r?JL572DQ0)`^UKZ zMM&1PbOe0)O4rOIH{0g8B_8Vs@fDJ+NaQtG)larWiG!^W2jzS!;-m@im(jNhT8;h+ zcs^bAy&PwSFhO;if?rxp=wmsSWSk#*iJzZUZg3wVChhK<_PGy2L5`6o<6|ApWTjQz zQVhV-9r#FE<+3#x@E#JP_`Zg0VonbobSoD>zj<ZX@@Vy`A)X>YWTcx?fD;LC(F%?0 zZ)j(E3Wn7Lf)rbEGnHgrm6n6eNa<+{nLx1HA#mq#l@+ko8TQ!bW%AbTo5&~maz4wF z#;fO-;zxsB0-pfXGYjZ?iDhcm5$<q-h=U<?Sk@S_jXO)X7F`2>kE7B|?}*j`@YBM^ z&!DzNT-;)%IND+X`C43mG4I*&Om9m_;Oxv$5^teHtCF2lk*12eT+4{U8I7*J>;gGT zLHXKf2_(Jr*jamNQFN!V78yq06%tn4!GFg>2bD%pFcaicePY+l2o(IWM4ulynu4x& zR4VLk;dU~S87wmd-+!QVl>bamUtd0vC)8Npu{gGIW)BdC;V0jophwvDQyTlTbf9hI zk&HY+)kKo*Dz^u}6<vJjva>Dv(W3$*1hd=4f?;Ennf<G7MA9P%u-bDB<)tz*svie? zbGvNWDp_kt<0^xN<-T*EqX&<gdAf&XQ8Ct4+n}Wg;2m|AR#(|&(*c`Qr#NFBMS7{x zlxGdYisqAW)`p?N?B4u6^vWCf+OnI!i!$HndC7~W2V{}gzV;Ia?d@0B&-l(^pA`ok zb<qv0F6Bhox8YK^Kc;Rcqs3N^9vVhnzwlT=d*LA3fa||Z356g(J2=xHm<N}E>bB~x zS2M7c=%_!(`zu(iNez*#T>scip`lmcO|YJ|MJuB9w}a{U=yoWJgx(NQfNffGNwW`D zOtLbZh>Z_GFmw7AtiAa|{kBrb18x2u(`L}uhj$<PI8Qda=9#&eTG5GH=%EUaZ87pV zQeT0(e7T9gu3zs<KnOcl_Qc}{EqpRki>br{GNxQnk>MC<rO(vF<v-?~ITlG*a%hC7 zIWF@aN1PPB2Z6eZ_o=Yio&B01T^D8Hx+i!+Ey1;U*2Z3DAzy1rtN&a01?94Q2%^BK z$jP0ec35J{O+}a_!1HK8MlRLU@_$G8{~%?549~PMXq%A1Qe);aXGfJhCM(wcZe4j% z5^V6?RxzlhBiunJf9Jwn{60CjH6YS-7=gDAnF@!ynk(9sC26;ps#c@utIr;{wk$=T zmC^x7+1G5U{h*!>werKJu$^$ucZYX!UJ>(mrfzF?RP~Qr^|p?|l*|Nq_l*J>17Y_m zIz{HMBFhR0^y~AT$w_|Yj}84+!mU*V9A=Y;z>*5~Z#$syc3~Jj*(tEdJY)zTVIRt^ z&+p*xZd_~mWSpyUq?nWPk5u)A9+vmXx4FLtsc!j0H5TLi-z2&LkTLC3$X39N|5Wwy z3l#B{n;Jgu_71QorKg79u#M`f<VR$>hTj|Wu&}Mj^}Co%BqcxAADKFP%L=8Z^<&6? zJwq4~j!QW_3mCmr<DjlF+jq;Ze1@UcCjc{=z*dr%)dKymD&;ax{1^?U-#XM{=Q)(l zN8c(Q)QGccj`)L(RR2!@ERP8)z25vbeA5Z<?VBCF(xeK&QI77)QA}%Vb?c7BXICM0 z-=P<A_Sgt9l1VrYXZEPIVg^kpm)8}|twU*fdOYzbzu;qJC-6gv>&&?@;cBs*eBBOW zZnTb=ti9$XEhmWF5Gr!;w3w3TuhP^a*EnNsM(bwZ3FU*PrF_L2jLWpY+XP2WDDy&; z`s*i2rZQF+MwFyX9wvw=cN|67j9;8!Zfpw#`L~rCPqI}dwe+Cx7u(6kCu~jTs<UCf zJpJqyF83pAL5Jd3-@|mSF|<S1$a=TJ7R}uW?ZEwaZ8;4AY2}HcMIP7d+R{<2uYj<{ zzO@^&{`fY_d=f1(T7_PgG*Pai+b0~hA6#x_QLkt#(9htkC6|HNSp1Q@H|vM%F_#KV z>Bugc!`4-ev^HXQXDVNx7`!Op$#PK$QrlJgO~`u|b3<TMUmPEFRyRq}qwz)F#7Wni z&k1}u+P)=xwjC^qP;sF1DVE<iHE7#sZ*wd{FBRf>yUR#kWjh~7HHHynfJ2arElV$m zNtEd%a?$++<)}CpY~BdZqy8B`h=R8zVrG+X$1up^5EP~<e)u7n6xkkWLbWNch_fZR z+aK^9|LxH*NVS~V(uKf8+O0o}tNHnt(&3~0UdXEkVU_A#47bT^U9Q`x*hc!c!fZ>Y zstUGD=*<(3^^wVzZ#X!>p;dyb3R{5B+Ey=Jx$d)X{@RsxSB<CqnC_`D=1M5)5Kw0z zQEnz*8KJ@lv7P!;uQDgMCt@ZZi_gBwxEno-Z3q`{?OmTfKs4U2qMR5#sgV2Ep1Z6) z@y?Mb;RDo}dVeLm&2wZewO6<;M8)TN#APO!1HC^X1mhHK{m0HSy1$~`=0856zRQdY zG5)C~tJ%u$t<M!V-zZZg&SWA`+u=2_G8YA$ic2Pv??PcG>RAkEy+7D=bi8HK0_rB} z!0-Kv0C`*9-#x+>Ra_H!JHJ2NVtzC`L2zsW-E!v3E0`^4|7H4|FgAl;r$)?-uYq_( z?6wj~AyYBsoyFm|pKhj0VV>4Vb1dewBM?Dau&noq-<CpjjV+mm0cmyUj+j@^4R>zb zs8WIzkubctv&of4XEoJ091*M6fyuWO5r_u{@#2U;my$;yMS2Ryl4p&`8GV^STAWIH zZl#5ZfNe*!u@hRP>L$~7%<vm8P-HuP=Nd*ER%=**=H<%9Qtm8N{*`3*&Xqh~j}-Q7 zY*~JExiR(L<y}2v*<X*)o7Et4W6O+_om@iN4=~8w(t~>ld^xmaPt*~bXJs)o^R6Ma z_%0zWndn3Xe5;&z$wwMo4cXM^mJLnW+I$IZ(?svRr9+dJFG;);;VdATV@rYp^uuzg zzs%BWwR7yR0sDwRuw)6~t<?zahJnxG#8S&MORjs3=9c*3^4zKgH1nWIsMXaiJPoGR z&7OS+W<}RCk*{zkzx5sHXmhcc$^|ZCqx~WVcSZp8T(p>Q(U!Bd?3HR)?c4;vt+}1F zo;P(`IrE<`eJr@r^?JqxPn$8bWw!I!-%fO7BUHlb3Kf5R`ZS7ZkImqGn}`%qI(UT? z2eL{{DDSuv`ut0VPyWGn(aN$d#XNM#s_J=&L(|+-LgkH(2Sv`2Ds^10(UQG$#W2R& z+;QEXPd${#kuCM}BQv4aB0$|6XV3Ny*;!dPy#TN}t!a4?r(5211h~N_m`ZW|5Zq}= zs&8NBY1d6Ub%P+7gsC{0CpFR!8rLG4)Y`%)LW|7fb0Q8|?AH^`_d@BG42A=Cek#1& z1;#InK#mhfGAaA2S{~&QD}K6ORfO`eqYyc27{u((_H0!Tk3OV`lV3qe7(y;_*}EAD z)nIFpi>nI9sk5r|&@smf3;gY84XPFGBTwmD7xVmO^6|)|t{&BufTio3-fYd=+;XRC zrh%I7pFg8f3)(c-OXe2dHu!_B5iwPfR5c3$Cte)UjQ!E8u4YMB(k-w`owrU;?|Y^u zi7r_!^LbQl{hpr5t_Il4urzp33?$t7e4;XJv*pxjQ;NAws0y`v8qEbMd7HjPL>%lH zZ*`q^tE@Y(Xh5D)ygSEEW?80}ViTM^s^U_)r%I!4+WA>rO(<fA$>uDkS*)lkXQbA% zr8y7C$s3f4=zW!p)j0QVeeDQCR+3D5)M<TO7O9_H>hcmU;+lL^&|)RHepCrBA);=M zrJnsh^w%fv$oPZpTps^f_W>ap3w<<B+{6Dds4D#)0@URB+xEzrN+u^y@o?(2szUIt zy{UFSORML%GlSq6?tZ+R5)&3Qc}AYB(XTx6K?EdMe^A5t72#E(;rcFQ!OFSW+RPkD zMBj3b?5mO|C+Bz<-a4lafqy>I_y^moi-|LIFW5UhkKu@q&PRybOC}OR_u7P*pBh)M zL<x^tbE)0@#J?$Ori$n<3saoor4*1?0tka_xfMmY<1b0#F+&mZM8Cwz52~s<g*{UT z^AgyuK-@gDoA6uY&!fxYW)oNCKcqB~49q%*4$oGcDkwZzP7m3=$eb3q0G&9{TY8Zz z5|Y;G<DD*rBUPUZT{B1AQonIu1iM5S^LEq}Z<^wU+3C(pcz<=`p6?qej-Z+>03L(O z^x{&swlcum2)5Y1xG(S-<(7{5Qudm|;>m*8pLyc5FJFE`U2Kv+70HdRkybk8m*b62 znj0(Ek-T%HXIlH<u^+Wv8F9(k=*@{AjH$M#_cQE`4&%=|Ee#u1Uc(|r9%^6|l?nqH z#h`GL8ei~uS6fysLd;IV;0eEsKdaqCR46y&SD4B=YZ~0P0nS%~hwplu0VP7SzJ$e0 zk=ow=?(KjnZIr$xk7}B(&J0cBdQ~Z5LU>!GJrU|4`vnMfRO?5=Mhmq=kDqf}^!G5f zqEYy~IGi>X9%x{qeAQ}42)h>8j^VtdgNzL4B)6mIA%aaWQAMHixMIAr0-cqJMaqm# zpo(s2*Pis^)2=O8qv`ZJ>*MCtKh=1f>EecTo)7PvJ1jPTCplY34}HHbKdz+`H>pD6 z@~RXwz6Bm{5-m&g6+;I(o)N<(7lnhZwcAmWhyq)s^I~2+`3|TetM?qX(;kjWV-U&3 zgTR;H+w}^^6n_$SQ9^GNhMO}83|~nrK1H(#EQTjid1Im73i04kGBD6ly`Kk@$!go? zqOr+9qq8=0|L;50a}QSN!tFb%*i@X{DD~$pS~$b4+jm=TXCt$qvy-<FE49N%Ae|AW zT)yx(E$__*MaVI>`8hwe{AT3`&dcVKJQl0{zu!%KiARO1g~uRt750O;%U+b1Jx0*5 zXoBp}B@Av$NJRg8*=GD$uBL*nNQqZxKz1_bAhizBQh4Cj2dN3o{Mk&m#Q3AgQcBWL zZ&i>B7GNfOrCqbvVI9xQE1T0QPJEzS$BwpaF|ld;Mq!)HfgB&#_!f$gIudVlgsZN9 zAz#vdI27LHku0W#BQoE|4pB+Epc1Pjr>cUxp^B47xJ9>_DVJ9qUy2w3Li))<>tV^C z!$}~y!MB+Z_<icn$9EhIK=i>xc^&FSnl|~TU1ERqankW0{y*0M>9OYS67~JilSGH7 z>_>N)r$UcIlp^eWONDzcW7>A=Wadd;sal8>IUgE$eqFCIiPt#^CP*>=vBI}<+FJCD z4Mb4YY5yC<ougi>Jo8&fxf^jK-dgS(=cDL>gc7sl#x?(RK|UbknDuBYZ21{i_a)x6 z6bnn$vpUuuk`uEFv7a}S?^}qsaPi%I^W}IKSQ2i096ZA!=-vY+I0=iM`Kak1d>1Zh z71*x0=-(kzFS4CfgJ{fm$Pitvw+9g67aZiOY2Y2=?~Mu#srbS)ZSY$lV!7TZ5!psu z%CjxCh-?@0_s$nsXpi9J#(4u??dVi~2{-ik`d&%CjhM6dp1z%C$*lmv3!XCEx%(hl z+QkXgpo9>RIjC<zwtQj~T{rVQuxeK}Oo+a4g#|nPNjmtqY!8_ErjR^x8$+zGEX^q{ z`Vnlh@OJC-W$kp+r-%kt9JT)lVP?6J#Hd%O6p>M4q%?nFKWn+2)N#x@ad*67UB=21 zE@V(G;&(d*mwhI|_6mwPo$JRB!70Fx64&d6#9g9%&GbC{KlwL1^Vnn07sc^dqO)(y zeg!ST39}``zR+%iT-^B2aTbv)`a<-TfZIQN@#@(*hJUavp8ad7!=mNTPN!Yg8(vxd zMUCSB5%-O>YKu#-1zgN!g)HyY`}-wsK30Gu<|~beyI}sYAw1_fN~122F;j8+AX9_f z7*fkqj4W|2fvkyy?Z4+DaXF4S#Bsa+?(EK1(1{6DpIS>K>dsDWHlL8(5!jr1XtK3j z1h7`_wd<SMkATnV^KH7h1B535^F>sIVmhws+zoDaXo%fdLEiXl5!SS1c;arxQltP& zN21^m*6U~A)pJ*Vci?B(`}$|8gQ`1UOu_{~dS4yP1{~rwOeWhM-hnJ_N~PVJGrJy1 zIT<~?&{Oc)s}I{$qGERv%d?ojAoS~LF?t`TNbN2-e$;&H&Wqz~iT?#D_{%he^F~}| zNTdtw#J6<))sB{mD#g_k>A+i?%HM$lpv&ux%R9E+@o2lOn3Zi)+oIIX?Zbpy^M9~? zXU%O@9#Cz(OXv|%+kO@O2WGl)X&-}m`OcboZaX+cUk5O_F*$uNeB28IKH3F(aVKe~ zEYt^v8zqwL*g4V=FdmJU#`bfYNgA#u@1z35O+l}p+cAVU`pHc*)_U<vMr)^rR*bkU zv_w*lg}rTDKd9#v8xviOWz0X*lS!)QaqzR{^EiehOOTJvt7QFk4_M3kn;Rc$FI-!7 z%UYPxH1Q93Dnn1A%AiJ5RxG9?l>miiM6U9~Ghwz&&bMVpCG@CqUk3*2Z}%#P`fsj< znS4gvG7AnCT~T>{gYZgG14Iedei3tJ-jPp??3<t{;@J48n%sEsBS)v!`XlCP^SE#e z@Z^s4u^<Du%M8aH*VrAou)Ytd*=*&DqOxf~;77K^`!Nqw@5|w>4|5I}KrAur-Wu@# zd=gx<peqh(;f|*+{QQ`f<ui|=nB7)zK5#I&Z-tam2+$__wJu8sxkMP9m3Xz*_AWJS zklSgMVN<Gkx>Cc(r`_l4Z%29#>X3{$tq_WU&<y9XahdNvwr!<>SY<~04Fky&R$WM^ z*L)&l*A@0gaoZdZ6yBV)n|&s>lBYsnrMeKQ4g<~fj*%W{wL)4Rl=<8h(#3EO;0VHT zFV6W(^0k4u9-3(CD{b`eF?Z1JMhrKl8pr0)!W(rH5)NRUo{<t)u^LFXDP-Vz@)PoU z{fWFn6EB075*sBk^z54>6tvWnuX!wN2l4sxc1X(uECgI3Z80T!aZz&K!FwK@F=#%f zR)vD56^;n=t@%!eR6$*EH0pd(QVZxs3rl^^cg=DwwOV2N%MeD@QTJyW`UFxzNzfZO zrrSQd+&x=1(<+W?R}}rhW`25HVD$I9Zh5rMH%^MZl0-O&R<&pkU-n88>}8_K6B!tM z3|B?Djs&*PI|!3i<++X2eP47(S+D!;N8#<{ho^>r^IaC!42N%l@*)#P)M%NR&6ays zDlf|4C3b1T*KC=^?7qK0&&Om|pZiT&E)$o0LU*=85=Wb(nh(e?a-e7H`?H4aG0)i3 z@~N{Kd_CAcLiz5s3{#!7aDC;|UrhjQ<yJTBEZxzujS^Aqu}Y@U*Ecte3a|D8jW}8| zE7ouz8Wa*#;Fv2`Y@*;jT4x(*D~3yI$#n|s_@L(q1BarY;!&Oc%%?31<~G;dGatDK z5Dxkgp=Irt>_dO3?d2<u0$tEAip+jHTpKHVNZ}p-=+>Tcy;P^7YC)OG*V&gXnjJ+v zbZ_5(t&=Z|2{zSzK09NP@7B}nZT6Edjjn4#P#cAzX&s|c*T1ioYp`FPbBTx(yzr2M zUx;KCM?!HV>Te7bg=Hu4&!sljL<L$EihElT!5>ccO-~Arj>Hv7opJDE+f|#1fbY}N zF#etALl$*3+D|44?ZEc?T&+JBgj(ue5{1FZ#WT2i#q~bpeUlM(UMobaSwPhh*OSWo zrhE6Spvpj&Pov`9d!M|HHG6yhUc(#Km&k!|U^vJlyf-=VcSHU74W@`Sz~UDn=U5gE zLBoHrAuj-W!~bSv_^2ZwOl-~WVyU|9WTnk>@E$sS9j%Cy{DNwa({yfZe`b#^?&o1~ zLS9f{AyP8CorR_dK%Tv$NP*(^ZEO+Kpp;eRe2Yo=fVEqI8Q#2WCv;c&5qV!>=xZcA zb_BN}y?l-gi*F6*$zjj6LVf&krU}Hg@h|`fYZ)LWIJ{JYP06qVVg<F5>o<$l77cWs z+tqp%459MTDe2Oh6^*}Uo~zvsyv(c<2_LvuEsVPtDC?3u_xf;ZMq>$7ezpEYZtm#q z-b4v$%0Pef-p{#JwQF75<9{ZA49==8ddvYA;a*pRTg66nUL<u^tlNyaEq{sP-S5AY zsWcAQlubg-9t@0CEkN=MQB<$tq;o&aU9NCGHc@0`T6te)s%S6ziCnE6x&mQ2PY#sd z_^Rit5i+FFj7O<4OYO&dK5{o#mrD6WN81y=SXth5<!aB=XqTs!;4N(*QfK)RXc}Y` zi`s}8IcBov##zlbWI@)nh}3uudJ?yK2WHS%8|QFuDU)t~TN&V`K()R-JNOtH7Ga{% zIg6C3EG1YNh!KX9T=L_%-KKjMV}%7(u0v1~)fF1Z<^aAB4xrwHL~RF2(nU4^;S7ZS z-OQ>f#uas6>=IhoLd&R?@$vm`qK*;~BykMo-Wg%1t{_#!QhPU?dg63TS@(5h1dn(3 zP^2dJwLNA|CbjqOV?X}!sOy9Z_f6DE+jrrt^r(%PTVoM^uD1ufP-Bs@5FJ^#*-+Rm z5^9q?Hhs@ag9zRLxt*7qCc3)DJ0azc%-3@ie}X6syiy`4{dUf!TwVE%utrTOxHeL; z_U7~a>-tYa%AMz07!@sQVxImk&Ra|JpNa822GfR%%_@3o?Z%&6fDm2`;{g|Nc|6g& z^|u!Vp@SU6a{EL*$OSMn{0h+EZq&~+x_f=X{v8*`#Vr*>b?R{t8^eOhGj@u&-yWR# zNAmpNVBddvwO$BZWD$)*jUiH7C*&Xg<}B<ys%l+t@JS=-N>zvP(m>u%e%VdXqtY;b zyT%Gao)nDEx0_Cfa_#4M4N?&Yp6OglG+4=^Bx76&F?8fEO<nHyJyzP8FV)g{=fr^C zf;yV{XxC<}nDu_KJ+i=2jvIusAiu>sREPpl^!NS#?f*ed-48}51ztl6qjanRoy?l+ z=jF9qgdg!x5QvL58CpMO2)laiBB3o6cu3jCA8cgLXCNPvmdPt&jhytoknmeuDu6t= z|4Ypn+Q<*R-}c$mA=--_A;lC#-b`{}?8lcr*7z=^l$aOx*!|<83elm-8DZgRR~>ap zs4BYKtX_|PCO5C%!*@X{A6izfpI`Xx6Cc<*<N@+T?@WjxIrx_eby%+zhATq&<N`~h zi(j6HOHEpiciM+27a{ygz1GKVtWR9@29tj`fT2K;oz<<$712V=`p?1Qy%_IUsg>^; zE<}pygtU4%1g#&X_uy-vCLkPNl=OYLib3Dx988xk2+)z&C33#vpfM3C#^Y;W`uMJH z^#gUv#;a<+X9o+`bQ8uu1VlajQuKbiTc@(3^m#;sbtsbJGga7<Bwt#sbH_F%oEaX( zasTAi7Z`uSoj-4y^R8ZN1C3>JV!@fmzmVZZqG0EaXCg;f-0;Waf3Ov_0-7x;WuKD0 zK_Z*0Tdcy*Yy(w`L0Efh6bN42;WKb`d{;@M?-$-`1`>jS^<I_VBD{Uktkte(EkLL} z{=*y)$12R+7<Z32e-_csfri>mafv9}PaRcx5RTMcCon0GkZ-KuHjP8kb~iQ~vOL}{ zd7VctKc5Fv3c1k?%eF&zshsNlg(OH{?rSq^scE@Ow_+Q6(5+$pdmjKaw<D?g!WO<7 zweAG}&Vk~PG{{3i-Ms78udKDx+}1*k7*}|_lkZX{(6krFuj<dJ)GNV7`W5S+n-frl z)wRfxlkhWC0Z80|Xz1bAlUixOq213{Skn(&p}yfa$8CbKzM5Bj8j`DWSDmgULHAq; zR~o4)M`fQV!{%_&@d1LZKaiaoE5CXkpALGHbyV|OTeXt4A353=5*&#H2o=u}aI{n8 zaOWeWWfL5;*)Kt*WP*M+(P)ZLu3*Ht1Cy&wPT1rLzrL_47twdp@qx&*Ea;cD?>@Dj zFvo9Z|7S9WeQ1M8s^?e-GCZVAVt0~84FNOs4SAclfCq@GXNijX<;TamE=5f28fLOG z#mAKanDm&B*9S#M;`n%txccg58${9*On|Do7ppu|L;X%2;h?22S?t#N6k6o_?o__& zP@UVXQoT|CwZyh;(hsR<9rSBC2ywT{wBd^-|ET|RRsV-k(Adv-a!m+Ek{R@o$k?cV zfDw=>LyuavYApq!uk<8=yzK*d@<NHZX`$BAB$GRBDcEZEnT<6bOhy52x>{@WBvreL zPcZz?@X7!beSg1Gqfcwem;;zV1>gPgv!UhXcLPL_JiD+a-8HO<`S!y#hws%OE_F3< zLD4mL2j#}vM%{t?^)@TQ$lveqM*n_+RRNedj6%TZB4rNs@l-7KV@rQCT19(5y+DPe z!X9BQ^-+2}`O-BrD;MFEJaH9*@v|A6Gs49zpiiB=7hix!2*fAWYthsOes%MAs%yM% zW?+m>#;q+Vg{ECP{b38M<7(Z47J2sw$*vUS1YS{q4XCz}MuiqgM#<)|kT~uCLE=iI z{(PeHlLFD_@@`Ic@kx~NilFBh_Y4eNDCEL%@T)@ikYu+&&Jz37i;xsIVT}e5!<Wyo z767-KcMF}BA1seVr)>&3-t$;5iO^=yrK5r{=b=6)%Nu(lj4$1EqaMi?>Q!YX-**iv zpT??G+Io;0h><$9qC$vja%MBBMa~X;Us<yROW6>5R~=ntFCA`CXtg)qsv2fWVczCT zxtE_S0+GA=PJkOiWvjlku>WPh?&#|>Zk9)V@bh~oLJ_zmf=pUpqRg9p{|B%mlKB|i zp>y}MWKy56w72+BaYdadH>=j?Gf8h{x1=lg3^W~>)t7ZX_Gaq)xZpVss1=D^{e?;z zFTHdgYiGo5*NK~H%pbr-2#t;na{YMi#vfT<t0YoGd8JPI6V{#Dp=1MswOEPN$Crq4 zZ6^$zHXZqd+&FP_4(4BWR88&GD6a9K>vfTku-*8vmAxI0_3{E<Bg<;&9l=YN)%vLE z!eOie34&3v^c$`o21?`*i``^6aB(MM8mjGIU?MPP)w7;u;PNK86tL7XQ2U-(a%5F4 z{&k6WqPri47I(4Yw6iNphU7xkWf*yshmCo2P@BFpj9h(MW=@_Iw<0eWD6V}r5~Mc@ z@wWEU<mW{c+j5NTaA)840a5_yx)&ja_<#6N{TD3224V`5NzWyyXLY$gL_+b^!o?ok zeuQS18H>XN!q0u3WBbu82Mqp_Ak0`wc<ZO@4&ZQzOI|UoU#wBPwv)~cZK|575HB<v zi41_Wn2E;cF=f}8eS~+}EZk?Gry>_kNc|Yf<#_#elIpZbGUz3rkxLC>?GaH`JFnhi zwW@YZc2VTImU>2WKzr$P*ZL-^j6O;>!_sp1bkB2EWbab!1P_n4+|8o)&U&c5OxQH} z{lVp!;J~#p_sA0Uhs`PKE(<f<`J$`D@GL7V{X|4TDRKmbc2lT=Y?IwWU9es^z<3V| zdP&B0-UH=cO+Kl9&w+4-YPBu22-U?dM$@-aY-f^qBkZn(_2nt4(Q+fwIVE?G*C1nc z@lUpZ>x+Z(6rIs02Alpto0%Wo(>JQ+0HI*1zpXT9fwfTsOU0vw$y*rY*Xhk<S0B9a z_`~&i7p^NYpOlk763P971*6ah24H4OmTkxrng;d<7~MKb<#l@~@Z2QB{IW@%>Zx}{ zYb=&$(d6&<J(K=m`!eK!v;OvkoEtYu)37B+=ONwQv_g}eCKcmEJ8gB%`D=rTjS&^` z8W#oE=N`{yofT6E!s(e9Zrb}9u)j+iPMoAg^+o|!rH_`1klI%#eQpDYI*z8o`&-yb z)1-LMo7)go^$@}Eh<@}_0*it2s@Un#>BBnxjmN77d{{yy!KxRWP6{iw=+nS9iK<%2 z#ESI=+nO>^m1X9Ub&US3mKaxFL`x)mFWrYd(xNQCnnw&z)2P+hh18}(?6D0sWUCpR z-$>2w(ILUq(CM;O8CuY%;h2V(>2MA5H}To_ps&?@@1yc#4602?lkz*S_((x`)$O^y zP_}8=(^qW3G2K>h<JHgK0>^6=w9$#+y2PUF6NV|z9^TbpL;RkJ7#_8eBR1@7u(zr! z(tMpvUy{bl6|37oOM)$|A{lSSIpKa@H`<Bj){%n3VR^P?v3K=H^E|yjckwt$^yQGc z6RraDSSwMDr9B_FP)kUeT8h{xFHyW3*)@&%Y81KoBE!D#i@BY#)5F24vhdx^Z>VyV zHe}1<Pd~i>8f@Kbd(++~itaK`UpxH=8><%JFQ*abci)3Phx?5!R(@AMjJH+b%hEMZ zXwca@^znV-<2Q(ih*hx4-I`OGyVSCqS)v&lgo7uUaF}`EQ}QWi9Xd?7EB!Ol*TPbV z6${r$3P}(<wUn(Aw8a^9%4+J>COl{^q|;0HQ)dMAy5g^q1xK}@9k^=&`o*TR8H9@# zIjB^mDPApR#q6oQB>D&2GLU@j(}>=~?qm;)74ZsV%2h;e2w|%uLNLXp4Y?1w$t`6Y z^Xn-hf?2F9<kgGIFMz0MPh8P2bYpX_{LbDtcI{Uc&`5ulS>lC1KhACIpq~bOk1SlV zr-vopeUTAF5=m!lT_7D)*doGtib|sz`b`q4gAT8C75Rg07Xf2=_F(sJ=>8vUNB)_K z{crFjQul4!50iSI5hYd~*Ds-Wt{*o3%F|Q2(e}ze&}p?IVA|$+`(f}OY(>JncsIa9 zE(eZf`vJd9CYb~#4stXWhTR9|*~+xtU)8Cd79~}!A#Ig7+-e6oL!<#N9nTH!cDdp_ zCp>dJs3&z%l&TkM@yz1Y5|{<oV}aUu0#BXnmCjdo3|s}@TzV#8q`rZYKKP#bkhl7S z_Iam|i#H4~A=4Jh%aKR!75)jC0Q5chRG?L{no=%5eZZgvAYS4^qTN6FmVamCu)Q5E z986qvVP}EB<2}=@L$koVF)#cdY<m{pj49}ZxX(4SVPg5VXX^JKUsTpjrrExF`b5XV zbiuZQh+#=-)QeF*FloQ&X8g7b^X0lLs~q3$_<Z@I<LrYkJTi){AcBguSoOkCO~?&< z%RVU+j6&#!S5cLA)mYooU<iId_?Qt}2lZ|uu+!jqlpu75uOM`Gv{CJ$Q=hKKfU>=k zRO7$|;n>7?PQ-Ny-(3ovId9{QmkY@2Uy3|lQ_dU6r~qGoj1H_Z(?jaO-h>O*TR~b2 z@M+;UL-^!&g;rM-A_rs~wU1<;jp_Q9@6*Bu0jrpluN~Yze8F0@it>WRk5WY8mXE@M zv>>I2mj**rPMh{sZ_$d(c=06t1>HZ`UYvz!?{psSsnd#O0;ya5Ki+G4-rsjL1%2<_ zx=MTyCJ_RlvZnM}S|QPf$5%>X=+$wHF_f%3>btk%na}2XD+25DQRhtHGW$P_6A{gi zHMt}M#sQhyuTQV=K2*F2v!c@5R;(I)M&f}ghR-8;OFe9~hG0tA>?n^dFr^f?xz$HG zYSX6Eoz53Fh0@cPY3;!WAUQ}}NEWi$U(`FvZWt9Xy+koM_*rhOD4-o@-}R7J==U!p z{Nr1Bx7d`VJ3Iy;I=$VtE0EokrC^9v4;fP2A|-3AVbjuH0zZOho4dOAI8@VuVEGJg zTORDDB`05i?R)cxZ7s>en!g-crS13W$sl1Z;}mi+n6DhqnW?s(Q*p}dM|Hx<WU}2s zd`R+=us~s??A{j`5)EJaa^ndEJ1G5pB(Gk7wxqUIuuDL=I#)^K8>PoyRnAtybmK)a zu7Vi_Jy(88ZQ>?QGYg^<OyoP}1%{CO{l@R6s2rb^WQjS$Zm;c`V++bUi_)X{)nQwj z?1Uyp037u0XfzC4KG7i@&TDmFV^h(*(co^Ll$C`~jU%^ol!tcan<u&f2LzerpXEUy z<ymy8UpQDury-E5f+7IxE41fI@U!nL@Jl-ZWwROqjcKL8^oiMmeAT6(dXKgXPHn0C zJi%bwV0#$A&iYc6x0TDOi@Xkk2^NHBHSN?ThKO~E5G$Btw}u!sBd(k;mFl*XLC=Hh zf$37R9x4#P-tbA15}eB_`E-zXbyoSTU-BlU1h)<Jt7S3%$XE9gtaZ`;RaI*#7V-Oc zsEHyjz^c5^FQ)z3V>-}e5uDNyP61CFW$$BPiK0Q-t)VP+LafZ2pfQ(#XB9^X1G0}S z5JLqcg5b#Guy|;zzK2Rjk%OeQ^!R@)q+*73;;S5m^5CYtbb{z6Z&5o3mf?DkiQ4#@ zC4_ae+^W)ETbEcBObx?_3y_%tWr_?fA#(G0OG_6PK8NJL+LV$@TNGn-$*c>QEoK_j zV-;yqv2+@c+2PayeVr`X<I9<@y*FfyCJH1j9l4vSr`wr4iaRnTVlR=3pUX*HcJnd} zg}a0Q_D>0lz`jd}2FX=EF>h6<yF(_|L$&17$Ue8waTNi`lE;2IU)^~_pQ$$NaW17q zf4#Dj6X)!?avyU}+VS>)%7g-#3|87UzsTf280a&{iu|aS_AL&@GN8`Fm<8RIA4&R^ zpZ(FrN)e8gUjtYeH@pY@-ITj6Bz`dhD(xh<?xEUi5ePD2zhv?9Ue&$fAep|hSC(=L z(s9Cgaq5I&J99PEQg+P(+RCD|2U%;76=*$k$)}?6=sc9Rq{>!$JiS8WY8Mc(`R3*+ zb%Q;hlZx#CO$@|X5qWg1|Bf6&)GFPQL9!^gTTDQIJy&d!X0~$msyFx-6SV8jSKgqm z{JLplV4o*SRpXWaBL|IIhFz0KD@aPZz`NLLr*LA?8hO@mhJkkHJQ-7(iY!ML!_A=) z{n_*F(oX*qC8^zqA*L{c1G9At3ZC9DsGP%d4~@Jdq3s4PznsmFBGrp*Ugth{F?>F% zI>Nf3s!VJ=g~gC?dlN)DuS^6XoyTX6p*1!}vuaQ6v?!MP_f<DId~Jodv4}U`+Cb~j z&vKQ=4XzF#y4tp=Z_sKqwHdJY8@NhX?X%qk<)y`%e0^8Gz6<8Q_JyH3DvL0v7`dPj zTkbLXSb%g{7=53PehXccZhI%SE@5u%v71JScrHqwP}e-mGH|U7=LI?&Gh%a=N^Pt# z8oMaIEs6Q<J~@hsavSaOZ`#W(Px7|2R9xt`V0moQ^_IcD*M9d^WZGQ9^+%<(5Ke9T zTVGh;47Pj<PUk?_^?g(93<55SYdArZx{{V}i#>AfKvYfHhM5!UDyUnN>Ao69oRpIW zDL@}!hKcs;(&+xcN(F|y_Q%Dsys!#q&Et?G&Q2jp#i!S$ZW!sy&_k>Vsv<KLIfZ-c z?IW(u>cON*r~HDT&mxY7{EGJZ#E%4fSF)=yOJA~&ps1cmN|G^@)MOPMse>DP!9vTn z(>BKEXf!jZMg0R6h!U)ksQ4NA{Ne&&uye$)*in~kapBiMce!&PQAziQOWP|}b@jzt z5A)`eNZf6_9b&~E7^OnO6L>;8ORbWBsv$6*gc%nOv>H>{K4p7`c!Eb^WCq|fihX1$ z%Q-3R4OFsDy%(5Q9BHZ0KPmnb-&w^+$V2^?A))QQ$@LoWR{?;*$KrcGT*1DHL)W^u z6A&hyaf%Dqe~;X%GRfnMq_T=2Bm){>Vb7}%X+D$kIv@HU8$rW%35XHBJh4u9?l>|u z^Yat2Nw<G)3|~0RIiHazcqRTOTfMa7&yCh!o4;B~J=8YzT{nKvqgPnl2C(i>^s7wY z2KC6h@3POcs)f}3y{|vJl=$DC|NS`sAFaM+^a~l;4l$Fsq1%5RX8s?C`RCF8w#o8s z_*;v0CVy+Oeme=dK^Uk~Z0-Bk?lpdBl7-QcQi*uMBfQ}1F9?26-t`~#pj$DJ?@3F| zZ>1$!(=taRTLJL&)3bi3;&|McAJAq;fJ@=(SCoJt3zpFH=pb-aYb`yMU*FZlzP_&Q z#HITSIiv4k$ETc6giqAZOtd<F<Nhx&*4B-6Px~Q>u8|HEt$kby|D=FG2w-7)JFP{d zNH{1p$Tzm(Q*ed^#iOaS-TO66GcD~I;B`jU>yC&%@Ywo(fjy@qlI1x=kI=qdK|7!f zVKEIS+dD;{jSJ`(=D#GE+Sdx)ySA}X4%l~HyJ)0BP|Mg_&foDB7H&9-b(pVBK_Y6D zlN8cRqudzMt^zGN|LDZkHe%ZrWA;<l{quyvq4uvl-d_B|&E!zEJ!F5yoUN`J7WV#U z^u66@JOJu8Xpy&rUNvWa8cu8nBs_K*<ZC}wz>;32V;FgfDjU#eCTEssc#1SLCOohL z?rM1xvQKhEOTC2gWPoi6C*_3PsW4}vY%5N#U<3r!wK_Z4^#Jba{CPsD1pgf@9JAPT z$iMEfQJ7-JC=0n#gJ1sgS!wX!4y=)8l?{0MDX7l2fE*j1zU_L`GOZg7Ol-x|g<b{e zyK&1n?Rj)<U9o>1Vw?!t9lreso07GEUvSa2%jLyL<km~O$RnwtE}oZRe*4b_v!jsZ zu|q<_p{_VareP8!2*l;mE)2i^uWQnJ<?tfo%F8T$nfB|82lQ1(o;BS!8dpLyck4J( z=F|*xTi%BhN2aOi4n@pM6_|_^@^CHHt1S*wVxOfAvK~i-B^tMp0-cJCnTBE1)|U{x zf~rVF-CvI(+F6qim&3F<x+sjEsOv72%{WJu8Em<k3+p?z63ncQbCWq}d++CiLBsY2 zez-+qc)fMx?jvP3#tq*LtdA#8cAd&M*=!59)WvPa=Qgdeg^;SgVd027M%kc=;Xjqo zmHYBKv85a_ACtskv)KjDXTA*d^Mi+2EIb(34C=zQDNoNu)Y2@=bwj?&XtmfYIZ1xv z41lK&%i+nuTS{%P+?roTdz?Hni<z`w*ir@KIwJ*oK1HUtmlgya%c*)+Z03+87jZ|h zlR8tn!jZ;RdWS7X;3#zS2w1??wp#bUktF^PImPTi?a$@GGIu*$kKOAl$6Vv{6Pa8O z52iDDlfj%;Z8Kp3!pPuk&Og{j%O2(TQgm%kAzy<|L0VQeO+OD>;Wh<NY~D_^&U`vW z(!o6IICwbk%dI3(zMHwx%_=>G`!e*y<0C7(yHr%+O+A0Z1_#_sZk}=6%EFj3b;i0E zQg|vDlzDlIDoLCYk~+;}7T{MEOgk;0oPiqdI`!#U`54aHskO7}L-Z%_p6E4A{__Pf z9xhn1b8D-gc2M2f>XGf~4kD0P#SCcHyI5FAnS4>`*Y^$Kc@$x_{)Lnw5vp;@<`x(} z8lTUF&PjA=OE+ho&`hFB5Nhf}_CrB0MA%?GO3rG&v+3pekiul?F+;U_Mg9w_>KdYM zzz$hrqHJpm8Z1&wyH-p&(;e%dLot0Z+e+rCK-aS!1Odwltzn81VL?|7B(y9LDp?2p z->V_GP92l#^U)`>AftlkV~6!?XmwzZl;-1^P^xi4uk>;0#Kn$RI<8SvkG40iXkn*T zdR1EVGi}!=4ZNN>6}j(<K|76-X*voA?*Ri$7t1~D@>FMd|1rAr_U+_t^Q(S{BKn(T z@?vLok**>sMT`=0E{ck#m>BQY?wivqaL2b!@!!`dMg&YAV>D-X__u}+{CUa{Q>u&7 zbhkMz7xcz$Ay~R2EbQ<qm#gqGXT~KU<X=6ffIrL|nYE-C^#7e)J~}tHMQGg05;?4a zb7KkRpcvR`1(W{`qzdJ(Ffa^_NxIE?lHqKB;Xql#479BHLXoKza%_`p6trg~>Yn9^ zPr1i3Xz*;OUv3gF_Qz|g=vx3$7b05VlFsPcYqXXjjh4w@L-$+urK3DO*4+vOeLm<T zd1H9;{3y3B7zEQ<Xn2Yla7(N1YAcbd1#dJen*qE77e49n?^()uK$JrFH^^y__6X%; z6r0!HjXBTG^dnW2LaOCkNZj&I)7TX&Ubx$#AMK^6r@+m{6icJXojifT@f2+Z7*7B= z=_ZX9Z{<eXP9~L@^e5IH1@RlUFG0^i8>>{@3i{(C#}B9wP!s8rkijoj1mj0=&U~Rb zZ6KV80@iCVYfjcM+Xgzxg~yxr>U&>c7I=t0fgNiwdlyI>Cjj$$!i7<*ZO2-kzNv-t z)pHAoJY#^13kvx`NiI<$bw?!iV=BkRFRH`9X2TL~`-4^)lf-48tBWtDISslI#t_kY z+FhcwxN)#{5}WbSBpRnRpR)FyuI~Q;u)gQ{NA~P{7}2|!YvWEYFSB%d4#y^(d*|xs zcs%G=fj-P~dnp-=0M}?eG%+M}BddD(M9a?#?RydCGw)N^x=24z3Bco1;aof~Vy7i- zy3XRhn&J(2{{7GX|NWEM!l&!!<NtX@|MgVwM40?3cFo~61Uz*7zEtQT@%~I4pD{Df zLO5*iUC;h~pV?|55#x7hzNfBSTFQ=8-g6Tce5l`#tZ$DOYFp&_;&E&^ckgY5EjSHL z;YRFsf5GdMHG?o@DKd)l4D;`Za&LqDVuS*HgNv3x<Jh0Ey!3TE_-ggwJSAet##`so zV;$@*EzhV6C4g`U$3}JHy{lKZs2|2jbW13oaOLS`6%`ji84}e|R{u^t#9+N~5vf2H z`$USct-s{wI(ckr6JBQdlvH2afL;QEH3B>B3mHjt7uX}h>klFIysTX2LJ<XXdrp8} z1~7b%UDqu7?ANXn%za)f*;NyRbSbt?PU3x&Y^UK~*OV4C`{w)ia+VW|z$o7~`crtN zDL7<XXV0}!C-~^36FHVPYo8q>?evm4IL9hJxjs)3Bc#b+ig{SAUj&cQrV%@n^b^?& z$3LQup7#u~ju)o@K@ZYB(k!oELN?ilm9}NPPIH)1J3LXZA;BB|VF*OdSTgam#ZVhb zN}Q4}JUxBTgCv=-U#;6i;LV&j_aRR>a@&u{3p!b4oYaAn(BOhR%&2RXP_?iH;@LSp z#m{6iW$@^`+xsMiiezcOQorRJBiy>?v2Z3W2eO6wPll%q#&}W?@pNqb!$4V${%a## z#12#DH`_a1(!ZBqNckr7XKIk{&tn~Ixj!_u;;$C_@aRa&p=a+m7w^j|AQv<C<Sj>y ziaj;N_i|a>-i~!9Th?nIOHX1;+)ufNDTc(<-cS^DFpPbetJpGyHUA6f?BBbJpNP#N zA-gW2L%6<ihfVm*Mo>7#hpVk>sp`M;U#$I41p0ff?Ol6?DIRQHanT2q{>mF+Kb)!D zX_?bvCRt-vw<Qo3u4NKTQD&)k0A>w~zwTkPnta~r`^;a1G2Yyaa`(W?BcNGWx#{*I zjtVeXjDv6^^x5J`9JzXe@1)>G1|z`3Y18-$0+-Le|Ab#t!C*sM8)@u;g{44E(iOEC zAc5L)s|1!vlCk8QvY6qb@|_8bW4CU6g)?ASo+we)qx`r=F%MB&3*JqXFjmocbsGmk zu?%+j8oy)vG&@r?FI&%8l!>TuW_B#UfTEPxy85#cMq2K!tvtNceos4wPlnsKP_~!d z))*pTA)&*8=1bcUs(l_Ry34Q@`ft?SGgY}Heq*V-*>*)2R<IX#Pp^{yb;T?kufPt7 z*g+H4@xjR8h{l|*8JdRMQsxK^H2=+V0?ZWfg4p=-V1gICVM8{p@2EZNX%dyE6OrS? zHXUEC#F>@Jv;6We7<9?HoiDy*@I1D0>22o7mN@#YL#SxZt?>4u_T(~w;rq(o*Pn=G zyfc`FzDn%ab8A%Cjqmd_EdrP38~83eM9!ZQrN^kK=SjIk6&z|<Gt*ev^b-UBa?4T| zqK`xI3(<fS-IS}thwi9EpYKP6+LuFUW>s{Ue0=QPyz8ARNy_y`1Q%F;Te_d)0$^eB zT1FIa^_k?Wj}P6Ngj_fFnUa{`qp6){r%hQD!&)T_)GbM2XXy0Ax!;1(sHgU8zon$8 z6h%5Do{hUC7&j~&1R4LJ7#BTq<c?aJx8)dQ;X28C6a_q=vy^wd*U?2)cbVk^%hggh z+b3e?=8$30Kgs<SIhf>7t+u?qC>(?uQ_1OjSAju?+#a#_k043=jhvhCz;J9NMEemu z_j@(JxF_6HZIwQcuteD7g)do*sJ83=OvRgUe|Nc}vDJZ>&^NpO9~A2|egb;@)>0J` zhy07CqWc~SmV4;Zf?LcBkCmez>{tJ_WS%!fDoI-qKZlY=cNGI*l*HW`fB*va<ui+z zRJRGm+GxUN7GHXdt&XEtJx!uVx?DVZrr|9$UZ2uFkB;{Cxrf45fE~MODVk8b;VX~! z*FI*gdETGMhi)8BET#yNIE8KKt)gHkw?Ua0o<B)@tmC1~vNr>`HxvRbhYLf%DS+`H z(6X1fzWbyo*<ZA|66F=sl}n3ny$DnJ@^ve^)xy0k)onyP#JXPel&Iic{&HM#&;WD( zT}y$tuz-I3``V(mf*-c+q@<~(dfGvEad)n;hI9B$YR~g&-%`*$|4SLD@YcOoH%43D zd;53xZ9-EDa!r0e=ky!WVD{sSLX0q9Y)hOc-J>k+;kWo#7}@k@i+vM79rXZFwnX(P zR#$%Z#+i1|fuAsKVlLL2SU@^QF8S-9jUERbB-YW7<?FIINLeZN#UaX&5f<joESiDy zMa%kJvdfQ)G+NqJOH^6Yo>|i_9$_sbUR$~t*_Q2|&>v6l{LFD2c645W3X4lIqW#0> z=5I-l-mACQ>jG=s8axEFCtP0cWrDLt)9ml*$rrPP6~FVc7*_1$rIRujPe_@D3OS4# zD>fAHSTM5L;CAPTcU3ja!Yu<EN~ihEj9DdJkX>Q9$n_jia=58uMdRxwCvtv(``q3Q zy(>_MC{%U+Ao0YrpBGuLgW%Fvf9>sVTM@Or(zC{PDS*XvxEs(`s+%5}0-Q;ks@hHb z&{+*unJ%`+{Sy1HL&x2!H9;T}VfYi*8CHKjoW9-9BE#SLXvG3I0oyd)Sr%|opj{*7 zi3*Z9qpO~h``SKiE-cy<dd+9!T*-rrH>j^~2&TH`+K;j5I`}8!{MPkP@(mXu3O*Cu zc&XMTQL|C}-YdF|7T0B5^Sv+GtSlPW_q8T(ar$W^^P$Nrrc6l-IJcTKexTRY*4sQT zCgrPl?pXci{u%Qx%F4)F)kx1_GIr!US%%LFA>)(QZ<(mpc@e$$*%p(Qr2jVKDPETZ z+=*||rpn=DIr9J$u!Siq&kET2vFh(swWO}(S=w}6`7obbPxl>=KEgcp%&IBqEwdS+ zorK}I0?|9amp2;d16Y90lf&lO3OxdaD?VA6)Z#7i(G30LDJ3seeRf^zKPr1St+!08 zn^Z>zftvo&V~0>8iRJfsvV<Jkt;K-B|EYMg`Qh=6v|s!W@8+?uGoKG-e_qsh@&jjx z?iFGY>2Jk5efD}}WuaZO_ZW&AK7ajey2B~k%>4x|hhv!ZkMUbS{5?(|YIca5E{tcg zL5}`{f9-i3bQs8f-|gf*_xI8+XpWVTjxq>FeAw5@YA5kSb#vR!YTVbG)An4?C|V*C z=^2lzZ{IV}+Ier-3Qh|LmPU<quj*qZMVcr|!vLE1GuxrqYl-On%yY{5qMZ@ir)sDJ z9-q=2?h}$r_!>g0>TDfz!KY1U2b*ZwJ8RMEd8Qe)$`fJTRJHcS$+EJk?b(FulzW}~ z=#7jPrm|&^j%tzXA8e*GNK1{yqIX(nV+7qi0?U>_;t-pArNGuYQrk|e{Sz@O??K3L z-ZlB*tu*JW61u-hFk+{wPz?<z745dlESZI{7(@{dWP^GZ(nOu3O{t(@A(h}lP=@Q} zOg3iDN1F?B8r6<r2^)en1;rRfg|Mfw0S#2_6FhYPBrqm{A0+sp1vJ|Jbox@Dr|}a~ z^oL95FG)2~LgA_A(vOAjcQq{v+-^-i_$h0@;7b;Zye9PyDzsFgGwL*rxV98CRp`?` zBc@0lab%yCTwB^>Qi->xEvic&=)N7DuuDq3y{z8H>FAVcX}6VG*)zZ1Vfp{C_a0D9 zty{Y=(xi6~5J5_S(4;pJqzVb4gwUHHK|&{h3W5Ssq(ex6&|84e1PmP!sZymQMG&N; zh=8b|>_6MRJ>NdxIp@3gyW{`IfA1Y<j6ky1%34{OdDpw<eCC|bLw*%>&`*0cSF}w9 z>Hm=PQ_~c{V$R5Ikd?mmH<EahB8z}dC)WzFzH&g^-tRm}e=X(Q(Dx-NilQ*J;RoLr zcIoG_z*IPteI&Nxe`o2h<h#a8L`7x<E!exb1<a;<CjIH~8;-gq{1%z+2Bomb#?^Eh zj2+!=a|v^a#z#^FqtuwLi<u}?rY>p3qhtz;qMUJ!D_KIr<xE7y8aG6R6tp=lqAse! zM)z2l&BI)kCK!L3=Y+@Jy)?RFk%4&hY~7w^2vWoE4a=7)0m#0uj<#9Bi7T;Rc|~y` z7j90&v&t$d+?AO@xyn%)E8R7N8loaGGxTXPvD2My<OymqKpU1%0gXw|&(Q?33>uz{ zJKfo1gc-@3`h{M$%;uyeYHYYp##ufjD<)Q&^@60aS7jL3-@K2;X^BFMaN>D@h?1{V zY{*HiW|n$G$!PBu>s~uU@Zg-*1iG?icct-LYQPBpWzsT=Tv#jyQZTF_(<j8u36EaS z(TSr6U0KQZ1j{|!P%3r+<yJh4PL*h!yDK|LbKNh{BI(}J<V0mCp&U=qFt1|>k{%q3 z;ou-@T{uw(FZ4y^`4Lfeq{nSl%@%MKzzpeK;U>H=j~oj{hketuB8jui(RruH-BF-f z^O#Yk#`eZ*;7@Ilzj88RX)Aps`L`8?E@6OfcsclLag12n-zHB`x>UMbd<DfVA4_LG z>~d5P;SKnKyV@oE-hSWImwV1N&1F<4de6H=|KuRh*p6AX9I*}cY)-eUPGZ|Phsdi_ z8sAr}dMPDHEZ+17cRiQYHkh%A(DC8Pmb8H7&j|bIoAqZKQE&Y@c7B#ieh~?^K5del z7^H7@rD`1uI<Mx^a!d*+OW#9)OY6EhvmSVd#=11FNA;g8O0K;QkGHot5mY`8pp>~L zDJVbGVq&KFmivY%dqP1~RjE}LqMCt}5f`aCk4&R#uqee_KYyQ4*0Evb4aY=AiS1G5 zcgP~i20|HG(ow0!oPm8JnYm_mx4bOyyRr8-*XNN==e!gvrtO*0cbiKFg|)<(?+Upb z(E>IdT{kty7^DxBPR~W(NXYD)%5zKiieXlaO_H1;@HS@#RTW;52K3VjG;6!rM8wU5 zn*;WeiAm`Un{``goQ!-JcPgy`xu^giT%kcEof>ods__P?-2DN|L%aM0`N8$afs;DI zZ#}r?Vx1R4K2u(@mAt_8y5i+p{5mckzhx4UxZ%y2$NfMWaJTMCYGAmwj?geTy{ne8 zpwk<H8hlwzC*~zlJ|r~OGQhx*VsQ~NxWzOzRE4LzTHbLF-XjZ(!8kLjMDaUM3yme` zqlcPu1dZeqy5{+pi@BP{Y#n8y2W^Cu-SRTEy=$Skw>f&!?9u~XBAVsWc3RZeJ2OYy zUuY9gOX<bUjes|%Tu0KdnXD;ITRQd<<dklSsSS{8lN0E%4bv)>0}YpvHiNxN*DJ3_ zZqA9e=_!OAR<S7txvQydW6aTQ`r|7$6FwGMnw=|UFMh>KTo$*NF3u^%o~L1GnQ-$> zC_DiS@0t9N%H3~~Us%Nto=*+*ppsRA-W35$-SJR5xuyW>HT%BZooxsP6HX^trCiD+ z20FAG{LCFeC>fl1bf&|pw|5}6(KJi9LIOl!psfijhFl7E5=P+H@c3Bdr2mfitGw&I z*PG@X)m-e#8xP{slGK_g^|J!1`@TBpv6Gyr8%uzI+t?<Dz_11xwLQP>hwG-N0rWCi z15Z>WK15b;R3e#&K)0qzy+bed`EjMM&kahd<OFPu*2JnwsD2;Y5#a$hu5)2q0xye2 zt+9=BYh;f^Ds^xNPV;?D9Fp^nG})Kmhdg*WIC-dY{^*hI`dS^9@q)emCZwVWs<Pd3 zO?Kh-ePjJ08Hq2b)d4pf)q7&yMY0Z`vR!W<=^WCNyf(3LL6>otz?Q^gCZdIj-In=O zS)t;2?YKU)F>83I30WEEePPAJ$;;JT*ubkVXlmW?1+fDnE(^hKwWpf2&`MveW`Sws z)@e}?*Da9;Q5ldtjXpuyB3<Tg5!*7oTxMdSlz!P|rH+)wq)(NDrWcN+O6V1MJ`u$& zhYS^M(1sO@W}xbe0nDzsl+9YmSdY&NSFsFs3V0hcL(r(|bp52IYliQNjoU2|fe;@H z5eYvjJH~j^nP_Vx!ynue$l_QZ_M9D^wkb=hAH|H=%~`P%PMm**=fW)G$&Igo-=lY8 zVQ+J3MjTt3DWi}Zt>A~mcXBGvF1=#^q<hb-NY;bSGH9?RI7g73*GxalwncC5#sxF6 zcQiJZj9`8??N?b%5ULVoN~jr-vfQ`6_<amh8H`J|C2=1LG2)yc^IT^iXwIl8vvr$Z zJJhrE@~45bf@rj(C~U;J1Safdan>(D$jn^3l8Mq>Y^R8#+3h~rt1oUVNu_t^Tw<H# z0tXE@4|l&>ibznFPdrsSNC%lCM}<%V5A+Zd-TpMR;1^2JTw=4C6DTtyL%|l^_)$86 z@V#WPl!cH0qCq4*&M*@$WckqOyG|Bxj|wghVhdo`;+ATA!BL*1P0>&?U8@{eJ+8E^ z(^O@=%%uag5Rw024w?|U+rDu^F>K^X1Q0p8Pd~GQN3w($-^h%!i0ZUe8qR<B15v;2 zmZ-8Nvds+*1TGFru-iA8MKSW@+YhhK1>RNEmEMSkXWf0EAbsqA4MaXk1Le`8a0Q^R z63eAqu5njcnQv#!$UZqL`^cOo8`97A{W<v$c37Vt{Dp2&p!O28+%Dtt;pwH!r7g9_ z8P324j&>+Cs?bIUpgLs3{Dms8bVR2TKo#ZCYPH{BH$6#X__S@iXbZYHt_@*}wbo(b zQJ1;y|H9SDJlG4N=+BTD__VyVOMk0G?19rALRd+`C9wpw?c4ph{mm|(r)1&B6T+6# z&o9ZRup~Kp8WqmM2!)WyM+2n*Vx1FhS)wU7odG{C7JKuP#a%u5jfDEBoow_C<LEvU z+mR-TXcX+q1s;{c={BkQhz^>=mAd2Ygc4W(c%Aw%eJ#AbjQLP=d@_Z5Cg{PamEG`? zAN&f(2hWK*sjf#m%hx$xI^cr#`-B|=rX^aOuLmd{XATzX+cqh(dEVm@FRH~hD1P#r z#*0EuREnlk_(a=OU0FzojLwFNt5(7AX<^(<&fAis$11DZk|ou!Nlm^=fWC9jJcoP0 ze>BYO524bofSPr2o>c{tbJRL(N5d0Pcb3x%t4j~)i^X4s7iF(M<a<rcvtD0lxiOI< zr7?2!tb_6=&FF@vwtk;*eY#ne9}=vU!X0R(R^w9oD;&~;)1Nnh5QJ0f1e-Vq1e<96 zb$jv`3a7|1LQ@oRk6HFyv)vmSq8|kwPImH=^7>Wn8>iV^uYA$|wz)WafyOLN0w+cq zOB-7xLt(N&sE(s4(Ll3Ha9jeRY&x=nonrBJxtX@^%@Lo>#}#sJst=uvq)|(%y{|;* zYuS2rYwDx(%r3Wf_D4No#m$*YFOC(Zh7zK#0r{~sUJ!H!h|oPT<f4kHI6?)|si;Sz zXnJV_%VRgtVNc}?aAK|e2eCTxmu|`FoXVUEK-%Q)&v8VNmC6QNN}=$&_JM&b{Rpp} z)_e_<Ow6)iT8tMzW#^<D2aYU7t8`H}2~c~Hj7N_-pY&w=eELO1%k{+y2-tF_<29Im z@T0YJTTamvVWs);oE3{nT0a#H#gjyzS82vBKxcDcmW`*`EHbFD<XM`J8G^v{jn9Rj z0d(FU)RI+`9&#(BIeUcYO8TztI#_1pYXlgAtxdKm_uO@w?TTo)Ar&MOU%l`Keq!^M zp;E1-ykO{y7{1==H?|$T+;*b%vDCyY5if@IT*K0%P=buA++`mWb-xbSQTWmwM{=o? z&=kDqYm&B{);i%cw+B@$KzsREw1xy<MyMsn9*!}OkN)L&OqzSvXg;xh6l_i4hu?f- zFP-@L@}*E<lPVAJl)n$RF6S*_3LZtN7OOJxklU2-nqDBx!0RK&*{lB%LlwI1Zrg0{ zouy?_h|Z=j>YKmr$xrsnDGWKfr}_s?EU^ZV>K8$ewmV#LFiGV|VO@NinE@vSBAqMj z@IxoV&6DdnN?JroVNjo3I3E!K>ib5Ep&!c<^D22#Ykqg`;>I_-H%(@t4G*1nJ6<y2 z2ei@*FXkZJcWA1V{82H=l@w`JPk6J$&rLX$#-r}4*szV(n|<Ji@xEsHHUJ*<uKD3Q zIz4r)l{sp#lp1(<SMj)}M0LUrP2-Lc%Yg%rSt|HkR6I}-y;j7}=R7jEN=oHAY7t{j zqRl~wy~kK6jU2SJd6%BLpY_g$rgpHkKojVh6(=&1527rXEY=F2X_6@^51wpQoi~(^ zQV|A6N6gK@u9b*0dh!z)nRm$}M67|w6+4WcJ|Szk<7NAk5%f_FE|`Dj5$diI2xC;w znk>^AGsh6wA}Z%jSXLcWt*8oFWg`$xV!)#^0}YNV4v89!-h!|zPFTJcYkQw~U@4wm zU{1cE8ya78dRfvN#H7zF<%h{DC?ALqL=K);RWqD4$^(YPntn@RCv7j~aW@ukP*96p zw5Cr<gUCBd{E40JN4DAV2BwB3KI?ejwZSTz@%{js<!z{5MkY}&2GjLmWyJL~a&wZc z>z2_t(Wz#T4Y!JMP+UuaMleOjRrk8-Cr{U-T+``k{Na2dQr2Jwwr|(H8-F$_vEE<x zk{BAQn7-zu{H<_Y_`r4Ei>qs+hS#gV)Fj2mH6yFrUHe;au8S==g!#MlpO_7XrT&TG z!rzEg;xbaOp^{k=gh32qd;buM+8enFdOb*!crB&W)f#EPw(T{AF27F%^c9@M=`og? z6Vk_=hATIA27L(^Osgmm$K5rg@wPZ`zsskTY47(hHWw^q_a*`C1IB_G-t9GJr@W-` zzeJK{k&<C5wUY%sG_cYvbR2)8p`$j$!fLEKQ2f{n!!9_g!tY@O&Vicfo3iW_2pS8& z&HQmuDf6=E)lBn}OPmvzJc2cH+{1fZM@$oCHi(QQ16){Gr7CGYLjQd4mHZ7DXC_qP zplxK_Zem;GEZ~>%OEW}K_M_n@DnL&D(H?LVZrZLw8KV%z|IzTreztstOH?4$fZK9C zYK`ZxJZJ%?nNYfbjPNQmy>sstJjf~jC^pJ=N)QN^N$7>P>7i0>I^X6|_ZP{wZy>Hb zmzoE$)R|6m2_RkVOPB0=qkG74&c!I%b!*6D1nlk3s-Td}72(P9%%Yiw%j~QU+5=p= zP4F*0@k2#pzNgLsphymT%qxIYBehY2VCX1E%GBfx0Eh--G*)E~p&w)~dX2l;Uf-^A zVcJD}!s*_LvyV+Eoti49E3z}E@v4o;2|}<GQd3cy7l&=V;p?XQGyFp!N<bBweYRJy zF^BNWz<XtpVt#6$<N%8BByC3Jjjw^H!ptvT7(k}g@(dOm2CQ)qldr^vUxD@<VyogK zbXdmnp0v=HO#QblgP%JRWlr=c{Fp_fK<(X9EDQ13nc9!f83?q-;;1Q~F})tJ0QNf+ zHCqDt+tM7uTBG!!4A_TUmv<35LoEbJy&UeT&`+pCW0x;Lsd?DqYS%iKV*Ul+iStdP z&fZ2&5CN!fx<zR-fqUOV^;}tf-4%dzRaOkwVB9jqIDIF5E2V<sTZ_y_^4D;*u(_z# zgo`)g+yb~g4%h#P3NzyJHh*l;&&VoaC3EcpqOG`;V`NTcmZh84>tL;w4Whd`MtWpv z^^VohU~ugSEGKU<lpvjOefuDMGWiYP{%M-C6-dndsnW9vw1`UA4AuC66~=O_J(HNZ zezJRjMmE#KB1y$fk$zzWwZ+Ba#Q76WF9I!lRq};SAqLYST2yAEXKV(q^B^w~lgg0a z$+-orZCLx3lYV9b9Yy*{G%pMLQNH)JlqI+&pjrfwk0z2KKK^;s1a@EWV;tn+hp<(o z;lV@)6BM4IeXN6;AK^k9)Xt|@m2_$8>r()VyPh-(aqF4h9A5hteRrV}sGp6ac;R54 znUtC!tY=WfX?HX{xMVgry!zDpoEJ%vpW4|&EPoHTB<0)Sn~$#kMzWT=|0|wnTNoWx zktiLd*2Fm(mLiN`GwT)f-wZbP`XdS%3NA*#bc0r%t=Gy6@0ApT%(-S~bL@%0AkI*< z(JWiwkp%z;N0ro$;h!5=ssUzrB%4)q$kl&rQ#K1Rw$i=MR5`@Km|`67Rl7}hp`#S> zMJ6Tl_XL^GrMrS`Im6xLW9)VM6YjF3Qaos~S<kB%YE@7<c)Ko4`@Kz+J}l4V_wmRg zvvRwT$gOZghsc?8<%U9m7VO|7Q2+WN{rKM|uAdY#4~Cl$;{v;J9ttAIRHMpe5|G&D znekyYi9cY{DBT<K5O5m`4k)p8sZ^VAdlxWne((!6&rALrsR<sF6>L=jvy@$d+yiaI zSd2om5#HJ9CF%thL8HoD6U1e>xT#G9p9x;oD03<C)rf#aq$|roglNFZ#j$njVsWpQ zgoCOwh0C&MrrAM-#vJc<fZclR(T8&&ulMs$bU&8Q*Z3u6A~t2wt4r=JO>8G|srK>; zUE~9UX09&6oyVb;k%tzw_;B<l*$zjB|4wrfQ57(#9jCbP#7ueB(FD3(RNCB)&A}1b zsVr;yr=%=Z`VD>V)F(_D-dasLi13??^wC5MM^-m($PL!#OeMbGGs(JRdk$+mDB7*Z z6m|y9zQ?cWHmZ)ZsnL>|q*vZB%klH#Zp5h<nFPypF-uqB6w4OK`6o_lj5BAHUTp)P z9eVp*%Qrthv}om@O+}Y69TG;BGp5*D-S9QiJJ>-puM6h)qZrE_YW$O=OXrBo{5s`0 zMxw@jp4ES{(0Gs*0!pABzJP(NP+V60-9)vT)PA3tsK$r5WLW(V<@C8GSPloR&dYZY z2Q7u>IS}c(8&fQht~$*o<vQK~yQ2D}r2JRD>OT#FU#byebcS3RLh0#Y&8uSPe<x4= znXM$2j^<o0B$AWl-5XnWrmL+3EHV}3S=q?X>&I-0%GFfLM(8~r2x=TZk&}-2LZJ#w zHdI05X3&ipAHcT_!6S;<IzyUWlyQCEkZ`QtKm*tO{wp2GkN~{U<3iO$K^awQD7KWg z!n=aHwI<+f>LJ}f;|vNJEGA=EN6fP4W_oF+8>~EY6g|@ZGkZgQYzdH&Mb%bf*Sgpa za2r;IxC#r60L6J1kzBe8d|~%q3_IAp$SsI}hB+R!x9O&$S&)#ej11RWx4kYwiGkiQ zRNl27`M&#FVZhS>6a;-ADG|^^C>id;EyG>nE?1oN>~IuGrO}r$*a!=0xdLUR-b7_H zs4vg|$N2v{^pPK==f{5??SG^hd`rOLgJjLA1@GXmv!!vhr>EFV^ss>{htG#S+hf!n zdzW>^6vi_@75COlevw8i4kph`;bCf%gmUh)O_x__>4V||yOx41o2v|d)Shwvf|CBq zwDBzkU$7YiaB+40vT6dm6nI&_H30EPTEqH?9FZtfD&Lnm$$iW4U%ZS^y0PE&&k`l5 z$T%W-gci<aZ8;c0BptHK)&}uk{zmon=Ol1@jF(mXijYHvSr(~DZ5?RJyW=2-UVaR3 z%7l#_C>fBi29>Ucrh53CUr^<s;LjlKu2vP}AQz>e%)VZ+Xc76?@0&``DBzhd6ZD21 zkrsVwNO{Lw8%{nI^tLSfSR~+I42G9P+C^=q8$!3xuCKmK|HM%8uiw)Y*J4@_#&r*k zvp>lAjYI%XyA;Tn$fG(#W0V>xlw?gzk3<NSnkCf1fi&FWhRz<J)%I<ayA)KNvRj1d zpP8bqJ(Awm<PVBl4PGg~7dBFI)UBc(^e6|Uk67C#BPQA{8pY<%diEY)tq`v{pQjT1 zE~Dmu!+$FrQ<kOjl{NqU$CJ)q8jF8z(G7XYO=hIc8Y3G0Tw8IRqWv|9B?MjeN9?U0 zwx5si*Uzx_6}7kXO(3!hxW~G$Q&M^bLTfCfS11e0-?6ehiQ-rs_u-F-=508i685Bn zSL|*QM@^WsfP;-4P@+-HXTtp4jHPqG1bN5jfejLoy|6C6;+wYR;<KD*JzW+9p9W?O z6|-yZg9<dG3@6p<))@4~EzW209G;!|Y{X^wwWUHHxItOkI@hCr{6TK`cd5P<9`i&D zEoPX%bZ*FY$ux4j#ZT<%rqJOZ+4~dHKlF+JB31kkFEwTEyGGNX-HS=-?B<R&t<MSl z;PiiW`t5m^tEu~W<;mvde^v~W_0%6~)PY{ayDn8eDoXj8VuTM&W`A3jK=$5Mxs|RA z&>p^JA6h=^=&mq3pBQ*t{D17i3Ok=llGXZu`OxQ<F#3no{O$Jjb#nlkV?aL_^szsK ztay&`<n~u#+cBaJc*H-JVJP{_)<ct8May2h&N8Y?|6$W-jM?QXw$O+gI=?H&J)Vb` z%I7w&nm!%AQ+zw~gWfBd`NX_i4Hwn=-4%n9rvAld9`KvGfB*gWY(PyvGksY+ifrs3 ze^%EGe<4Ht!RQ(;-C6TwnbL${{@+N5eYE65!Mv=<4`#|M1yw#bSZ{bY6>)SEo>4~U z(K57v9UudRiz81#;ZT?xIg0~4z?`79+k7!NgNZ#n;q!+HLjB$a%djsMFomE7g`UUD zw%-=tc&!Enuh1a<7Sgj(WRBmvuRK?5JZvpcvRZ0rp20-&&nDd@Qn7$M=rx|(1Mgb) z{6=y}<2lk?7B)TN^rffuf-<4wL=)tH@75%1{HSRkyBkEIkmc=ygM*u2Smg)RF+B1| zfkIAe3Y<r!f#x08>8>9XVdV36BNTcwnEEG^>fcQ^i$BCZv|OS`m#c2su&I#hXl&=d z#rkM>r5&vZG0v>pv!A)l$W|S7UtN=L)4riueM?vk8!}{E5%0nya0g}a(NL?x{ka<G z6&M_AJ5_=wp!AsDAN6#cC~Zv4DF?k1DrnH7Yf*VR5S~!7lf6PHi6kmQph?#!wujT8 z#xTI!F+{(xXSpgR(^@=K^x0GIuh7IkfXfnQw0dJgu4HFFh+p~Mq(av7Vyd997MR*n z1V&uh*jPy6$`vuRM4^}zY*t4eU0*13mwHr-|0AsYMjm6$SDhj{l%uK3y)Gk8J!4k7 z^DG7{td$864aF@ZPrvx_1hKis(p<RZz1A(6w2;k@QBCboOC#0NI)MqS(Y<;(A4{eR zC)OmDKENlNgB7mhk-HO}J|k9HepCP|HNg>9jfvz>^utd1a508}I7DP{zedDFQFfRr z-R*f_{$vS00TMU|zd+u-+tb453v&Ol&FPgoUa6a?181u^`RaFHfH-^XryOjUNoKE5 zNK$COPy9M#<9XHQ6K#p1WD{2&;=2W{%jHx4*vP`hLmpcM4>Rj^aw2zUv$tX7Mz*QR zW*?7-;==nUVDGrc8NrVYZrY@zM)A)D3=P#Tlva!gryP6dDR6KfUdOOeG2A}4US;#X zsx=oUcf7xX9TZd@BXNp;JiLE>^tQYF3_~!~+B?<obB;2DDhWTo8mG5O<i=QK_<GDU zXra(n!f3!orR_~cY(FUpt`-ek2Li_g<y)fg&p0woye3i#wT-N_;S(l_rXxgk;I2fr zNOrYiSL&@OfIp3iMM{uUYwJDkXH4skrlTGKFD$;A_bR51Qy8|FPWhHcj0fPAQ&b;5 z!hSXg-xB%Brf<^cLmiOJxpT1x591NwpVQ$d_GP!vA!f(sYc?)0JGzL$-4N;FP`BMJ ztpTH2VzW~Pv*HGvu3D*tEBd2JwK&}SREch=x}ctosc7LPvMY#<1=8_4Z3M*bL#Q@1 zH@FbFJ>hKL1D<B(?;39r*i~o=60m{y*!1+y;b6Yi@>i3L$RE_qce~r`(I}KHItSHB zfY#DNI%#;${YKJ07Tbs=_SCTv=nk%!7}Zf#_vN`QYX|!TFXYG#6IH4ej*h%tOPRBg zQ#F|Lq+;qX5z%S>HKP22IhlSLx;2eOQ4G!+PCuFFzGXjA!px#YU@tU^-&8O=dQ;{S zz2VY_5pd$&qEb~KlwxKgi12Sq#EtGLW?XHax7&O7@5TR@tg)g}1cHWTrT)4zd>rYR z;Bhwxq%VWs+dQ#oD0r*V;^hA{$ig^@#&6cjW+<Wo@caTSZx~KK+%Z%Sdc|b`s5h6M zpSmZa;(bX?*$+Dx8`RXr600|VGsa4Z#oNA^&WK&rxn+)#$ka}B^+RODMU;CMbGMKP zbd1T-VEZ~7HRmL6W;#|cD0U`Q!QG;*+ognDgq%*AZKK2hqRc9sZZ4-MDNY|H%aUj4 zUeTw`xPA+DK`P@**V>#UH+!6r>!jh$5#a}VPJ|N0FxSI7LT<dO)8emKv0}k@98CK! zxjQl7f{wWDs46W@-cjC^f8X~t$86N9Qqnt}qyXyOSw809)BcE+1W0dKzhoj=Q?>Zi zo9!SinzX34g=cg3>i27KhEmVCo`jy9Z%DWOMUbtigs9sJ@>D?g`1vY(VXK@)x<gA; z<T!X7qR_+rj!V@?WTZuOLCzeTfdEjv_q$K0tevtI!}~+>1cFhnAFIp*Ds=jGmOVY@ z`l-K$t?|}!@beGgCk(S~j5{h4ouxmAe{+q=#N$MlV{#9XT0!e;;oJl7sb-9C>eb&T zRY-fyT$R`P?~VUWBY4^2O45D}_rI2&x|YI`-9Dp{_Sg}otb_58+FvefW_qr>hg$mJ zAnI*lS-m6%ew;RZEYwTJz*-FJ^K2~G950oYtFCVSAwMBSm=8iQ24h0UJ>1OVHuS4p z55-4AY5iij>b!td;wzWCYP_^2wP9Uu^CPd57&2*W#kGvZ()0t3a9!Q{E!K6hTakq= zLFs$J3+X}X(%-A<Ikq&rB1+|gGUW30CaoIWpzOni`st(1rZUpL>m)&i9M?j-iRymR zqC+ja_=jl}x-nWefSR!ZstX^M!;$UW-3eE$Df3_O1KEW|b?InPx_<1@p`Zs_|I}rd z1*0VEh%!vW(m4zGvfpLz{uqau&wpIa4^U8BjdH2rd4geR0U|dp$olCuh8J<Nl1TaA zccw1v$oak>c`a=NuvK*_6dt%6eWfY*Hhs?Ll50EWU$kGk+Rr|L;5<D9OJyIq+onwh z)xifFMl?cPhpUEBL$sxSE_l~WJ=1hizq#RkQ_WsjiHqJ;mMS*T*EqA!<Ojf4(`q;> zxtmKzaVJHN{B4lCfISERl50+TpYSvrVLW30LffM*ppPJZV+&tu(fC1(JmWmXN#Cw( zgMF|};aT0~U6=4oT{e|%dNAN_wO(v{Pb+&Bme{w0#@SiRe#=mE6mkhDgP4C!Fr3Wi zdz<pRbjrEy$OpAanuWd=Pd9kRh<#^o{(juNJh}1!`o(nfTSVp^KV2LR6ASuB!B6lg z{Yc$8^#q8Kpkd$SppF6$#83uWsytj248B~=u<6qxoEl1Gs=(PfC#g0hZ<sqTB({%z zsjz&*E7>bJE+2mw_k7!ulje#<Ir0sK=5*90;Vr}N9osN~HpJ+$l5&G^GX<w&dEB9{ zl>8*9ccqu&$7R3xr+fCVg5uGjWR*xz^*IY}Tu6~vn)awbMnzV@3-g`kgBh0X>kmd? zRd4yhrWKgv{afldjQ~c?zvF@x+<Nv6{N_gf27|`cl(p9b*72xagUUCY38BqDzgWhR zx{vQUbGD*l_^k>>3)TN`pPpV6yp%b|`M&REzpJ9&RhfF3xy00@Vb6p+w_I-h-?Gtp zH6@G2RQekEUy59ZlZ(ErUkT)Wn5m+=XNeBB7Zp^HS|9SyWa~b|{`f33+^rvqJ1-W) ziZmuUxG^BBVR55N-5~X(UY+^CFnKz4KN;onpei{sBu((MONihamakH9g-__^4{JWE zZ^AcrUVi<b-U(n3YERrr3cRyT+zIJuY22j_MxC@iU_P+Rn4Tnl(ppDNeq=}n;B&xt z!L^nvm1Qe@fPqkZjeqa-KQ=@{$pV5(%hiq=q)T#v@9nuiz5kzetfMZW7oG#}mmhxb z4iPi3Zu6dDFUx8m=Cw|DMZV>HZ_rxC2GYqU!mGxp=o*EYRw%TuiS3&61`2uO`dON2 zW-fX)eoikgpb88}3R_c4)fdL!rAY_~<fE~kT1-4>C?r%lgFNhcWB0MIYK9NP(KjKm z0Q!EW3>I9Y8{tu0$l1lm;8^H_yp3kB`olLWW+!D2xz0%b?#8ikWBmR>Mr*Rh@P%i5 znOt6d=3QC64dNMk*L;7!cZ3qzy5#cH%U?oNdgu-dE>U!*`n-lYyL*=IcY~1QLz-4x z@F1O5!e#ZfQp7n_9xOp>d?)~}VsQ|$M$|*Y3ChpY?3rlj^9Y{tVeJ-BAGtc`52<x& zqPq5&)RsLT_5j^)M+py6V1U$}xk4*kyyopil^e@efxYqxl%82aX2mqKrF9x<?3f(7 zA^s-lS48`#)@ELM0!O}Zb03JPMLP5`<I$vSeed)*&c^FH&E!TGDbu@`mfIY-g{&;h zNQRB2s{SQG5_v6?rVQ!A-$-PJysxE@8w^(~_+d1hYT}wbzUWk)f^!3X)bgjyE?2#D z%koP{ka54!A9_*-<RDMm14QzdFuA3;wI=eq^JWf=D9F34FAtn<I}wB`b`mMBANCR1 z4(<e~NbO`hL$DOe3yplhJD0p8fUKTMihB@eQ&DpHNcL)X$m=Br(u-FNqn@AK3I-xP zNlZh5`etU6lUyo#t^;@csh2(yD~=E=%#NZ##b=_Sav#eHt@9;Kx;!s0=P?So^uNjR zo2$ZQ>277v&`m1<L_zLGJPrNDR73DG*F`YP%3RPui{V7gI)sLWQ9a3Oz%!xj!EYpD zUPD-2ZpAki`&)uhcN=B98PslPNMa>aS1FdH7rLlO34$rwFTsbC2_J9pTp4+pE@vd7 zt4z(N_IfKJ1}!Wy+;?gVd3GiH`VBgS5qnLN!@Z$FxmV5TVc~KU@3>EhNu61S<o`Ul zFw2JR`%6XGj7I@0;<;kK6a0E;s*%K&l#~Q~ed<_$Aulc4&+;Njcp{6z_?xRF(gI-y zQ<sqgQauqluXN@-4wM(Jey23(`J_0T=o^u-q<OW)P!E*guPM9sFVk<hY%CNt-yOl3 z8%uw3jw$1GYZ6gT*Y%Hu&4Vx_+S%RZohE77OEarWr;soHZ-|FrDstJRWqWb)gA&=c z>u)4Is&;AFW_nmcDT3c%6F>59ihuYhX8~hLIzT9m-B6d9I$B}714a0}>(-fo<|Q$B z{`iDIXDwTN%3fEr9REo{j5jDTTzPjv79&{pD4Q=tP)0;?uGx{u++2}oqGnaN9sQKZ z)O=lCTFgtRJb-73&+~Grk*ADyFx@;TIdfxwC%!3X>9{F=8PTzK|7ox)@Iwq}ZIf-F z)QdV>9~!jdfA2HZ?_|<%#XjAE5YwHRzuS$SXg8Z3H&aD)n2PjB=6|k$h&L6N$5t?M zx<XAI92k7QchZ3%jqAFwwFww-DB4rccnS4XLMj>dOg4i;PJBb_F46UQl=RXi5@aOG zoOgviau&i$#Du@h7$2&9a}S%GrG>ooYp`jYK0*c2vC5!b%Ti2CvqBV^lZ(QwyzR}> zyk9D68m7e=_|TI!E?(adi*4z_+;-I>4Ih&nH)=+wgWlAe|JaYv$D14UGZNcIa%_tq z0;rG^(oMS3vA`(26Ea@>IyXJkEZNTRl~CnX=}7+TTW@F3yV2Z;FLQn|7Q1Ftz-Is# z3=*1o@EG0_+k(X?Nn;b<MJb3Gg@@tPy8T$HFhBx^`-ze8^9>T`U@yE$`&+bup64wa ziv_#`=trvhYcq7NO%Ae5)1<HjtQOU5entEls~>kW(IeUezarwGpB;83*lcjf9H{;i zO{RC-4(4f@W;Z2~vb|GkD&n0c<;OfujT_MSEz6~WlFP`nt_rOrh3znW>^44~W$zwX z1s-l*K9*h1XlSH{jae|9_X<KUI43r~d0dT{WI3QPA|Hx$%{BP+7&!Js4KfHZhCqbj zia-xh3c;eO@ME3$U1--jn?;<Pf`QRBKlOLBPaY^n=RkamJU{{O7#hz^b8<inlJ|Bg z3QmBW-*#D8qP$(#rsfwE*cIKXG*l<|iZ!%$Nf$V-;{q(p&$b8ir>}l}_2_C2f?+;# zQaNjqb8fvY^`cr6Qt)>Ao{s0io0o}swk^z0hwcg}26?aPy^>sf{9nICOI%Vy(}YJq zHca|lZ|G^l2$!Ctb)bPt4;dc-bW9$C5r55m0DE%t#sKtL`2X@MYU8aIJBR`~-2%ds z!^G=)!Q!A%^N<h6Jk7bD*>rUf<~`LnG0R%PHM~P-G75K}^nYblG!BynH(?*jW|pQT zQGW6~;P0SiET8VjL5H2+b>OrU%L{uhq6%L+`9sU;M+@w}*9TnrHhy*^daa$%vz4h0 zhks$onc-=F8?-_M+|N!1&TeZ+I(A}BBmw6`n%xQwX)4sXek0M;i0=-K-t`xbZm(UX z6~BHXy_)7w=P6O^DpVI(7QI|5aC=7l<6_3=oqg`CJHa;A3_CFfRcuidlY_jZCKl;0 z4lo5;D7Fj6Kvg=Qgt_6Fg_98BXZ%#3sZN_@pO^DJjQBnoP*;6<Tb-_F5TwP0)7;+2 zt^R(@H~;)r|K2wDK2L$}#QRXjP0O!LuqqhDII=1i1D`$t(lb>Z-ocR|qmV!S)U@xT z4{V-?%f=l4Mk1+B_Zvw;e(#F<L85et%d}GNC@)!)e97u9NwyY~k(SzO>Q22IW@$s& zE$;HZGdaBap)<^~(8*pB#RKhoye58;ZzAx?5r6%@vfkglK4*z7PK2!|9=9lNTzZ90 z*i>YS!n(L#0Ok!Jkm+X+GB!xO1Y-$>UYN`G$&E&(=Y<y#=d24*%r=L51`mVyQHRIX zmv8FoKx&8E+a|H2WX1`=aT={Pc-NzKax*<L&H<zW#*6Ey(c&Y9K^g;&NvRN0oIn+C z3M*B$S9(SU8BE-@If@jV65LxHJSzx2V=zK+RZWZSOO;sErL)R+xhl14>V|wmxkeUy z-gX>mo<C2%DhM1D&@J_+64NfWk(Eqj<VG(Obzg=O2q_CrJtXIaGg(F}?8PJ>K_{MK z4!2^N7K?*svnz51FR7Ea8=erapyIzv<ot?5e?;);N@+I3EI4*6rIeqV18t0>ZGw?b zGs!7U228)h8GkxtPsoLGj6Z%a{PBFq_>snz$ftXT8vrv!XayR-ASl15?>eFk`Hkcg zBYUHFranVSMSIFnhWcujf}S67?kZ(j>!!63qiZ!`tS8yn+_ydI`FT#Lvu6%uvO9U8 ziSRI_-brZf`${k^X4D}qyOE`}bgco)!zau`|C*pu^?TS-&+$$eWVfIT=wzCImU?-? zyMAqmW|ZgUTPmAw=&sGktYm?q>cB{I41K?Hd|fmL&eSjr&9(y4tx=G4{7fdW*KGFD zr0S4<=C4CJ43h{{=%d}sY7Q!#M}O_1oPMzuduPndgLYJq!74L=ZSiZvJuPmKwG~nE zyDiSyO|<OuBl8t%c;EUGH5*M}0WPpxvIT4n!58cU{;O+X_>$k3b&<6%&mQUxkz>j- z%}{x-i4{8?^$)SHhAbcD7^fDo)D4}Uiazu?n0)){@O6GKk4?wR)#>9K98c<%8$wfi zE8izcI=c9|p9;oX&i%`c{G?sV*Qa{=t1OqByCtCS50Zq{l9~@x-@V*T7OeRnzGNz5 z4zJ17U#BZ3j?P38d&98***%GehJW#@MHI#+Tm7q9?u;ZSs56FUEcfF&dAVp5ua_g) zwY(8an5|7GqoDE!8T0=4QA$ZZ1E%Zy7`0I-G7w=fG87GxC+71ff7vSBZN`FGU-Hs< z=C|i0Rq+5upeW4~JEL`WI2;JEOGy|+MBo`lu3^lTRzVT825j<M3AySUrpwMwZXjGd zf;(hvNLHSeb|vcvr{Pha2`rPIef}cx2%uLyRX7#t#>t+tM^?F56_b&6W|$};)zf9| znZ}7`OY0))HH4@cBm#Gxh26H`?8>T3TZdE8U62f!d>?Tr)-W_CzG)Igz>%d*MA`uh zD$@b$3ywRx>1OCMNoVUX)Bcs5nJh`8im_>h^?p%p9j4iuMHqWZHoE;%?++g#WZOEE z?~P;+=8UR?f{Gt<MNdrJNKkkoZI_m*({-*;G*ZAFPA55HQe4WLn;WW#b6?4!5Ra6) zb<}pNkEZoCx!^Zvn7Alm{2<GJh-aV3Ppqr?qZ_T!^bN7^E1!64mb<@3A=%D@w|VB8 zUsdostIvIPyZ>VKn-@BI|8nEM*e3yUSNgyCF^ff-rW?$;fENm(lBI0F@>qW#$?lB| zD@Mn6IiaIe2ki<Px}!P|sRkKU>)%yo-^7E~-#+6jQ7V3j^S6FAeg@H)Zu;<aq1cxS z>=h@Z%Ua6gH)G_MM~m+2VEM;-jbAg{InaR~sm97aHOVX$4Yv;9Rz~Mwtf)CC<3*|J zC+Q_4&mshL?Mhg?FOfYPW9_7QljJ~Ucj$dAc24qrG&E;kX~G;z2e->t(p8>^nb=a! zo1tWpj$XRw`kp`-9uFF>rN0DpaC<sj^8?Cu6RYq<6j${WdGF<CBN}e6Z_KRf%0N9H zCtziF-IuS7#PDo&P6*FwGYHk5y5YGO`5zPG{c6+@>O&dxm=ntr`J!~d4EpNJLMyZZ zg;-O%i1na~)*Xm@NVR0+n*kFMIya}5nFZ^CL_E;(yftjLY>t&;2=xL*QpJ$QrKe?) zhN>P)i2>`1SF3oiP+GMvAV)>iZFJdkR0FzqGX_~%D+QzSbqS~B5V0VP<dw#hiE6PY zI^b$xuzmW*RKrF;HL#*CwqeM4_?1L;+taPa9GNizXY0-UbdVKSiEP{^L<J(CrEA!N zeBFAcIer@Rb3Qvg0Xeab6!y+E(Hrs~eeBEOI`F^g>^J$(!O=Iu7Vx?Ic)N)~kIfhm zYi3^H@yxCP51G4V7tj2>V8~|9GJD(AyEGl4W7#jtl%srRvV&+j@M7HzNw+wJrw9~@ zvWZl@9ETYgSh|TVKp;^3Ij<c<vI{X?zih2Byt!U^=aIFQ_rva`H(ldnetfE4Vp&=) z=O_&4x`YDG-VGXPg^?+(B_B<4Z@(8=;ojbx+)oVng7~V}dY|xJ(Ei%|1Lm5%4;oan z#&_}~J<8gQyA&qhl>PgS|I9oND;0PM+s{%8%TTpL!QePoYX-~6nn2-8uZ$ptB>OY~ zXi?$hI|}vJ4#7yT20Je*G^j#FV}q(?0ADg<@|7?oRMeg$vH3MVa&bJXDSm07z9ZfL z`*jJ(Nb?@g1ppL%^e#suKna_ZjjUK%7DbP%z3b!7OW-e9TwBE|i~^ytG{y>){=9YP z1du-WZR4}YmEMea`+x5W&&i=Pqxh(^Xk45_4EeW^NH0km*C{LvBc4~R5@Q`BH<{)& zZbu7XsVK|&`a*j=!F;ZzL?ihe3mzJ*Z2jVkZlAYDsBP~@mpMnU%9+4M=|+ZJOuQYj zhAEH3_s3X5&)P!t$^)c1uqa6XQ*>Do_sFObko;>GUMC`TOfK_BN*H#azL$PiHkO9h zDW|_iayjk({E}R-@M%l+sN43F`b)GqIbZ>7L#ZhMv{^ptG~={*w6<_lymw9%W0&Xu zyU{F&Mx(_S=oG=I*7}tNHib*m6tq_-B~V1Ir>FU=QaV!;rR8eY>H4}s_pD!iBB@hS ze1~BNqwxA=QYzhC8o?05j@D}?NA<RB!%wj8KXLpGxC`!5fT?lqNDXg@(|<%7wm1j< zPH&ew*@d_~HLbJ?wbSrhASZF2Hq=u|%)O>G-}3`C(i2nL-cakR!|3+*{1C+n+y>mg z-6mhR@PS(n_FPa4w4hyu&}ZyNYvP2&-AS7~N9}x*03jdAlQ?y10qBns-eDTR9ubJ4 zQjTp3CsKl5rt_^xLWf&eYHSP(CpM@tktejooa!*s*;)wiqm*mF4P@1cq0aDEED4Xj z#{A&;f#o+>W<)~sT6c-`xWNj~d2&6E`-Wf^G1Q49?V&bZ^FmGQXHT#}HG->7QvRf~ zG8}EGw5?@D74#*2$xjraAjX^vW)=5RRxT-yJ8CJiFUqj@J3dUrl}uIeAstn_6I&zk zG;gcb_^G4@A*%6WWj4A{wf(LLyG+}zazv_mzKi@}{UMcY>EjI1Pcd_p@R@wqc>478 zBu<ecxp0P|<(F@Z3g4{l?n$S5^v=?x-PL{Q3)lE?27MS-|2OT||3FE3MqOfKxlE?J zMO%03Hsr^XiB(5@e@<h*(P_v8KT73C=k#n!+>~!H-Fhrtq8x!f@K)=eG+;(E%ai&0 z>_Zu)J445X7QQJAP_8G!-bMPhPbE}e9);Y2%jvp<w}DMj9};qK^3X_w^qCsCmi5E4 zOLq{&@~Q=IU-L<D;il_>#E3;D%ZHZ@RJ$>}&UXB>6l~tYY?E8SRE)@d-r$~NBOehd z1gjL#0BgV@y!XIr;LsCP^H6>U;YGNv_PI~C@@WhI?3eB@MfPGBkOAG%0cx+?dK-U8 z=^yJk=%x$1F3u-K-Q*{7cyzzgZ%@^hEfdS{<&rs4@|UDos_|kbcKGV~i#Nz<(SixZ z1*`lm;lglSWchVa9bsyP%L~=Z6Y8Blc~n^>t6T4m4QkQ0Far}F=LJCry}o4-n_v;J zxJ2obO9M6Q<iM14Hq5vruLJQMKY+x%AaYo{R;uQJcPw)512v+xZ5cuhzR3hm5I|P2 zMa6c#0nZ@89Tu=1rYaDiB8GL@OvI^MZT@(HCbq|ZGdLstU2Xf18nOQf<fZ+ODjU}V z6rlyXg>EKm)WkUIZ@~7Gye3ueSBmkJ%4T2G&CZtBMZVGsog~hg%wr+-#Yv&`L7)>I zZ9Eti*68Mw0~ee#zx6%}F9jmOuw`#r-&m>&`P8Act{os8myHmA&u)LL_pQTH$!lua z%kg#V$9l2~q)Evn<tDdHYeXge;#%RT*bA3k@&3}d&VWor(OT}PMU-3>`c&Wid?R@W z5_*tb`P}+xLm;t#O%8Rp#Gcp-_^cAoK*#`)X5m0(T%gd%3SuXq&00a7#l=l)y=&|i zf+c#PQlQ9N5u4ngHh_8JVMvYl0={GZd0pVLi%*mkte8v(LcqQIPSo9FZxQt|xjr%~ z+tDh1Zjzqg$N;rc&=`neM9_3EP`R`KgI`>ZodJbbv_4w6xU2#UZJK@X6n;${@9;RV zU@doK0%ukg`EJ;|@L0Q03Pd+wtu$JnR8h&N93@FK3F-zzAUdz8e3>6v*vhI4Az+Sa zYEA`1FoPRg?3#+>j=#5O(%PaTS<c7jz;Bm}$p*i%s}E;nWR;&Ri**!${X`?<5V+>_ zUJH|~dDXwnbwpIf`1Bz<|E)yYj?ym$k<=rH@3_6<SEm886Fz>fQzgjEK@|o34L3kW z$P2fG!}ftKW@)NITIF9C=vP+YZzMhkY2PVOp?dHCXd{qSk6%VVn+p1k#5?1nO}336 zjX@!^s&HxPl9a5;Y=T&W-Pg=ap(zY8+{W`7@_eUB4Ag5awl}RQpM`l;C`@zj{QtWG z-ExnJ0qk=ae7;!!M=``NFkw-uR_hX>L@Kka#GiAZTNHBzhyj}We(jvSY}rVtl7+7= zpb&CV{8U0|o$Dfo;5xCsBWj=iW(%0~jPK!%@A5shBSVs4IM4ACMacI$G+?c4-jGnM zFfg$Pl=lpPPV<_@#^U?n+ENAvc4Cz~d-0zVzsOe~$^jKqVt7|rP~wP9X7mQKIR1`x zCwcANA2vjK;EhsMH6VUnB@<DC5y00Vv;O#zQx8?XvVW&WKPQGq|LiJ0jep=GwLdpp zO+{N55?3gwbHO${3mXcmh<_hByATxla@=}c*5L_2vc#qvIV?m-Pe<3Hc*?|TYGhDj z^Gq4*FpDBiEnV;O#w_)hdAS(FzLPAiv@BoRi()e?mQmwj@s8<QaJ!79nph`yw0b_M zh{)skrQ}QJ1GtAiDC2tp>>!{!nQNe(g6np02|rn?VBbwOjx^~NL_}e5XEiyTr4L4% z!4l^sQEG2Mr}S!)m0zqyrCa;e>CTPe&9|0&cb}1c(P@j<LN{Dy@sa7RY%E`$UV!<z zf2dGyxHHXT)8?KeY2R>zqh`K1-qOqTuW#VhuVy*v#BaxT(bMOo4DIBE0-OnyirY!e z3#F>>yfb$bTW{6;^Tn0TN#&C`3O7Rol)LBp;-KTgcLGsggUH3y8pSgY1B~k`$K$&# zHDh=>tgdKy`x&l)1E8->yU)fo>1AJPo3V+h%tS=|C>1Sf=uYP-Q0i*SBZObEU>Ud3 zLr9L><q!`hlZ~`jA++>1zNX9%0nB*XireG0tf{TkUTeDrHr%ER^DX5WqaRH<|9$p~ z^wQTlu~GKL!cuhihZrku1iZIRM-oCIv{GCI81AzAjRc#c=VtEOp6M-@z4WfPVB_#| z`H%b!02&)`Z<aZaja>0TvJN$}5!(I<&?6);<?qHx?3kqTYEYEc2c3;t1-@MfWO<>_ zfjD!{W!jCUYpjpPAQ#HXk4!pEmv)3*BRBe~Yzv$i@Ea!B>o8^gm9&@VVyqh&t|)rZ zc$&SslQ~+?f>v<0Kuu_h<kb>$u3(Bgb6FsL`K?KoKj(?FoBK|8&ZlNOkW3S+YlwiH zJ~5L^^JA0<jS{u~J|p%y2kL9ENW#)P`~>Sb%SeUS_5dP@-q9SE#>yD=wFRjiodqlf ze8Aq><Zh7+67v5l$2X<&rDwB{B`^AY7s{<5Li1RQGdG}lXEH}S?x1iEI~!N+r&Y#U z(p`aY=c+TOC@7g6c4|!7so1D^>N@#hU-$=A+L4lM#_t%dMyEAVt7@=>6_L))_eD&i zdCq3RPW&9dq=`Qv?d)=yYQdv5q48@bQl{n<GBVD~euxt>YXJ(^OY%Lw!vIiFFHn`* z;_>Jvd(KH<zb{P|Jy{mL@Fn)1aaR^pkyZd{fL`UbE_G%?>v?JGC^l6BJEDm2LTD<_ z3iPOwM!$gHhWxhw=xz1f*IhM!dLP_#rCB%%QoIY)+CLGVEy!fQQprBK;6x32V}r^i zsnns{jYno(F?ar35?c0=oMho5?iuVLB1|RRi0bh7{>LAm1vmWn#lKuV3qLI~n=b3T z1+1UX2eD=cQuSIKQDOXKM~4Q%s3KQp_gEt1O6ro?71eJxDJ4p<Ta#Rp?r<kjbc0?N z{f$R5KeY2hjDnegTi(L}fs)1wMi&D-Rs9`%euMMISpdE}=6CC4?ftTD83yPK&jak8 zNbMTs${Rq+2YL{M><&ZW%oLRM@n+<=Cf9#3`7bTzU-dV~AJow}cP~v%adu{OhKzU` zZczegPCsvNDbvr1H79jnk>}R<yTOyLwLuC??-YnuM1SU-H=DYJFg8uZUDNy5i!tdr z(6SlLW8&bUlWyb{({ghYy#4U$#j8Iu=a%315yzyf;@wl3r_bjSbI*o7KOW!ub8Bd% z^geV_)0E{w^ahmZ^_2bL_1w;FP9Tcl(95)#IQT^P&zO3jiz0UOM^(*#C}C0X?f(#2 zp!j{L;==fIfLcxpjAoB6M%-8VL^ZT_GS*tk*B`&prlbC5sOXXwrCRi*KvZECvKQdm z@rEf<wa{n0KZ;C|8>g{uZ+stVzL23it8xY;FO)K@0&41Ohp~kP;S&HZYLOgrEvvc( zhi+j4y>imrt=Newsx2b%48H$D-pb`N272|c8TA_$wJ?HO;Cc1OW(F;N<uvYZZ(LT@ zkHv|$+PamTtAGR}7)=?6@ltbowO#XvoQPiB8sP3?Wz@wob*7ypzxsJGJF&NKUdn5| zDVi{Y(9)a&V;Z@s+V11;Y#!oGPHPh~S>_+PGn&FXYwNNt<=ubORUY?h`5k_L@x{vh z`1J+lif~P0_4}8pWbCWXCvUim6m;AlPcv5t!t~0C)G>c7UTpp6t6RXQ57YnfWZ>Bi zQi?53u*wOTE0Htdwj7#$QXhPD-3De}oR?3f74M}?V1eSuV6$n4ev+0-Sz`TcpSx!( zj#}0#wL-=&IFml1HDzB(eU%{6E6;QxN3^ggnMgxgNRM;WVPM!jCmidMmTEQ2ISNRB z)I~r>H=iPg=rhzJ$(@GS>7F^-Xe@B8gJtciJ-WVj+EfQ2OrhW$%p|*4uVT;y;zCEt z85^~=`S}F~hv=!O$==Cx5GI0(wm)|8Xd-2TqEX4W@F0AGD9|A_uH~-R)W@;lr5N8^ z;h>=5$zL$fG-w_gTO(2<3%-ME%w`y;8t<*Sl<C#JlU?|<sQE_<wx?3%0ky|qTXqqr zExvC0GP^Lku<XNphC8+&#v)GS48q$jW~M_gnnK-AV+NIb2H7J}E9bvVrA;y_b{o)E zCY1vO!-8(D2QgL^zvB~s84Bm){N|v&EBdv6@PN<yMxVN6%E_R*%t3q1jOnLj%$j<A zaze-x{?F);fA93ag&}%QCqD8Yn`aj%iml~y<T<{TNY%Qr^X_BfE$%)c4IE#rqsqYY zo9{SpF+boo*a5`;>Nk?-Kc2g-bv(R3KmPx)_a0D9HQ%E6NhO39dXbWZ&_XfvB4`qd zp=szv)KCRPrP@mpLI^#Cj;NuCRH-Uh0|cZhT`Zqc6>J}NMAXOkyZ8R?y|3K$-v8dW z{%_rNvu0(^oY}Ky&&)Y<_UzevcKjQoCCH`f?Or?leglL57>WMW-c(##Kethlc;wox zyUGS1%&y<QIcAnV{YXy#-EW{qS#y2U_rs9&y<=Ao(Muzmnh>8k-@|@xqOkfN`P1wF z>8NOMN7c8!h(8tYyleFIs$O{bL!6fuHISC59KIzmvC7Z(mD%Z9>n|yr&$si#2K@!m zz)9b0uC4`oPE}=twj!JBUcY%ad0kc&l6L|#IW(m9@^STd&)WTjs;wiP+ujs>`wdKr z=l-<%@y+A){pV+oT#EKPU2ZdLl%jdbLF=o0yp)cv?ftLTn(JQQAH2Wu)8O7>rQqCp z_*q={()2a#JLK*i-*d*=;_I9aW}In1eobn}uP@yjPxJ0}?mzdFIDp$^ku(dfX`o7r z?VmoKY%y3IdflZ*7KK#x<ZN%6-q%ZU65Z_x*JueYs?w@X(9?B!W(09fzg>{+qx6FJ zu-cPy2odMwrG8{n?u9Aibwx%Ol_fTOUvAd4-D4jl$H&|pg;wFBmen`ikWA=*&`Gi{ zbIKQfySo3yZ-Baa$aGraK1`9a&TidTX(<@9L)QZH9%_7*y1nu7Ui;q~v1a<~&bhw` z-CluOO4#McDj&ocnw_T>Z|VY^dG#v&)7i1#z)Hbdo($=G^|$kkH(HO~2@r7QU|dSk z$Bd7kqK^p8hR3;en?7x#Y&G{KE35k+nlQAq*x|p2Tqo!5EhD05rj#%zYp-MTCi@CF z?Y<h`r8dRB45MssZF#W9-}9Z5JoPF{<!s!_PPw@#>y>aVyluWmj}qSdr;IV~#-?fA z0d8&Mdr#k@$#Jqb&@^82m6I26G`PCDX3Gh8vBR29*Ut8PBn{*mF~QZQ&dsN$eqaW0 zZrc|cpZI!?UPFJJUM58iWWB%nlo05i`n>6}grbgbLbg`<!JsQoWshz%dmS$4`H?#q zSsMQ)^ewAVnY^g$t@^xpL_6Ho>5R$J5aIU6QyBM=CAGI1TkWrEGfvMYeohoN3~z2# zL{0SQ@01-m_UmKMU_@dq3qN^Vx+~!#w>HVWKG`S&nS7f5eLmp&i{cZH*$MB;#k2ND z*Pw@w+$Tv!Bv@ZkE?YOdT3oz!#Lj3z;o0~TSdd|0U}fNPN=nB@i@VkIL{7MqoR^g^ zpWvR~AXllI?{+1#Fz%*Rj#cVC|1*6`7Ms5AQnD^i#V$)*(SJNVLQ8fE?5KMm?Ef_9 z*p@M`#C-?1QA@MTQmcKeF0*^1!gdwusQvWN+mj!8B50;3#_-#WQC00_o6$=8xj#~` zbMx-*e?FLCR?;v!QV_ZBGm#QS@l-w<{Brzd)NZY+C-Or}eo|(K?%zteTYHOJdctZx zN~Y1;wn-yNcPdfx@IK1E1G+W&TYL)$o>dpQaqJnlp*C4DMR;kXZ`m3bYHk=%_9LqZ z643q!<I4Dzr^qu`UMf^IT(368uGTG2Zw^I{oyiY;etFVmvrWr9GyJ6(Gt)e+SI#4C zrS5}}!D+twNn$`r9Pf1M7I}@BO**nVzQx^8e{ZqyN8htk9e=es?)}1HyJ!EE^`E^r z=6xM3FAQUc-d_$qpmy(<=HLFTssg&e1x*j-U;eE8+f=A+a&W~xFx=>Q-Exgw>Jpn0 zA9qcR+;qgEE(c%NG!u%o%Kvkvp$zFwuannuE^ogWWA@46y~mk6{Yx$?u1G4r;$V7h z>Q>wEorUQZAC6cYtWGP>nm0+{F%G(al5B)wFg|sMJaBWv*oeS4rX#htI_of=hZlRV zzYljWvad0$8D~B_e7_3O-vGazc#F3*`OFGqGnTL7>-wUtKC$qCS{zL8@HLRRx$_k* zVDliw^{16a<@^-yP~t(EH-)*y1MwT0CKF9s?)ZBoj1&8IhXXfQvGC=SIREi95v8F> zuSD;j2esuM-7svfzR^;^2?H(U^#bSXCJ8bL6RuGu`MSv^v*OW>Zo7kayB*OnIiH|Q zbUE({&W*fWJx^HbsWx%FTyA;C_jQ5plT`T6Jx2W5<;Aq`kNlq>8uphpqTp*jPPyUF z32i<ddN#(5<3^hg2%L7sO*h&HSP|M{yONX~#y`2}J9(H=4oS`gIktBZXA^}B>HTfH z6lDr0Cnrba4r|{o2mqHR3g2W6Zohtf+jE!bV0`>tKgqhDCyDkMQ4ODJo%Ig4cYN~2 zDVT)vj9hOQiBG&fTy9&dpj&pbA}KXYN2m16l%ZHe;`Kk|``e#y7lh*7T6FHpRGAd+ zc>sOklANPGUmf#d%cNz}>H4&^>sn){hIYfuuNZ_so3K1mSmJ7n>DF`$yMjt@A4ssO z%fzQ6LR=2$j0{H<>i+s=%>>o>6#Xn*VRh<g8s|MTRkZnf!aCJs(8Xwc=f~s;$!(=0 ze4BPnm1m&Kqi@`>-<%y`QA-dR)A6@|riT00U85p-<@PRfd!?=OHE4scc<k}Pd}K}O zeAMQ1bL6X5fz3oFJ1FWJ&d?0UG(xM{t`5K9^|EhNoX5C0>-l_vNODRm#o{h6$$XqS zG+JOg(mt`jIk&=OIaC|#Y^r;Z(2ay=nO6hC4qx}PN1t#P+iDN><&@Rh#EphHmQ>&9 zE;yPrKU;4<&@^tlshpB@qB8rNL)`P_>}`KY-#=Ah^=INvwfCHbJ7cQHZfgEL3-xjD z-ht<f%Nou*zU1zU{4E3wPyiSNhQgp=2nYoH^#e%*7-N!0@G2^<YwQCfx4Z>SAkyZj zvA>@Hh)o#K4$Mz_*IOd~8C}lYdZ*NDno;~`exEWYi-Q%I<48Nfk~@BwZ-4j#9IXE` z)wF7xv**2O%!%}#*^=0(hPqr!oz?PVZiO;YRVWo{*wOtkBI%H~x*bV&K!pcN2NZ;= z+jb!;iEVTVX{26`Ga3pnexT<g`iOyY_I+Ti*RQ(qGmZQcPv)PlIAcCJD*6r4Gr9dF zpkf|-oP3Hn=`UIsw^Q5!v5Kp7dwJV9#C~~Y1sOMpc3{+X&@g39hOYr2#Vsj2aQrFB z;S>jT^~5_(^aG#6fU7}XAdorS1%U;1y;CvpbX85&4Z9C`xjUou{dbImxuCv3QGb9c zAPv&(7U0Pn`F9t$*?<&A*2(y2qC7~%-km0ksf4JUa^Iy+gzjUPWr~J?Rt|%L9(%;` z8bRg0GeZn>O#(P$dDm~inf^(W+NI7GLz_30OXj9iQJ~!I9vJB3A7F>kmkTE-scAd# zzj8C{txp57G9e%yeZ<(t7{R$|^@^4U+#+hkkl#}Gcy7^ut;X#mikCuNt{p{<`igww zb0oCFVgb&NuA4XYn0C{i0eWb2xl0wSxx+F*=b<z(zEAX)l+3x0<dv(4jJ`~KJaQn- z*GU{!GKCM6I<hH3$x<n_8@B7x0dYpb>p;j&)=Y|<Q^QAb_@xTADlpjT=!B{&$NEPZ zlEjM0Nz^Y6x|ml%^Qjs=i)XJW=yj#cjJ?-_Gen5>5uZb9>#mxI7>tCf4#TfOjvH)A zIz7=p0QQ-ae7`Aq^&Pmmyq&lgipnxWtlQ^Z(GeAUt`7ULYyXj8m^aD8zFg?%A^Ev9 zJ+crAH|rBCp?@CbdQSEVUFw`y9zV@Fms=3AaP%gtvPmXP4k1Cl-bOIMV}MozYhRg; zY1LgfA2cZI=0x7Se<++{fZ@-Edju{Ye1ib>3$Fp;iOSlX8jn}@_9^Jo%)Db0UhDQ) zwI^x@!B5n(Q9b&kag|8l+(De1E_;u2b{F5E`F?|B15r7c4D~C{ap@Pan&DuH{U@;X zAG^D<RDre=k;VSmOgE<TMVUGITbFk}ms<JJlIO2{S=*(P%jjWrjs}w6D*bVc>}3FN z9;rP1W#`U!WT!fkd);Zh>av3i+`Sj}fqbiOxV`lzdm6bv^**DB9KSpG=g@CJ&9Cz$ zxoc5cWZT*B7f$?W_n~R1=-YU-XesQF{`ZBjj3XwyfRK>y*Yi)tDu>q_G&|a*XpA{| z-Ry=xn4%|!@j^cd;ag6N5dvTOm)6GkpD%8?9BcuuhV-ABn1sb^`Nl)&Mo5Zq=gs`^ z-vC6GC2>xM0g{C(7$I0zPGI5o7u?5-svHb$$0x?9dCpc&rYejf^3K#Yj|v0CK)->T z$s)Vd(}3&5%umVM;6JA#jb%m+f<9k#DJ??Aex|@$p$Ezav}iA%mg|P6pVWR`IWLi2 zhi7hphue<3ay998T3%NpFGro8^Xmnx#Yoi|JehLoe*%<9((j?;QdM>7+L_H+V<u0C z8jVZmyMq|2U@V%}O5XCU(%Xi-%7k~>xw%=6P27gqLut>4gTdV-hy)|FODp}IYU*Q& ztvH;rytvplH<@#k(p0nn#D15MydRG4mUupXr}-5EGz$W;Op1xN);%|oFI;ZVL`zXr zQwhy+!5)7i&=CLN5xH3(h6I_FnfQ;TGouVET9dlQBe!>FuDUeW$+m{ld5^Uir+mSL zqC1-_nc3q2oHC3b>}6$irnwKtnWsoBpW&lDQ7K9t*1FitZq=&NL40$uUQ3rG5c|5; zhSr_q{JE{1wujz~0%pX6NjzLZd8}T*=Ze1eeK7gXMiR!m4lymYc#<e8Z`2sr0Pmwo zCPpDg0To~-ud*Q6TW52o61@u(YQ95+cpxQUK>xb`mq6q5^^U^|Cx#d{7dMBt2m(gI z{e$K_w${I89N0?PQqnK)L;mKabVwCt<gsi3GoB3|I5w5ND>i*nvUE|LF}rU^8mf1u zrQB~ER9R~+qBH7h$?61K>D`j*l!yeQZ)2(e<nf;4)#eb2tcb&l<fSZ88pGNC&|8#t z1%P}$GmN!zM_facjb)&NpO{oxw*~EMCW3GT+RarhoW09+sgPOc$pk0jXT(X;hdN!V zT&d|4yq)G0-h&)`r8}WK<}kL>NAUPSRs8_?f23a#b8r?dMVV<U1#X)*GHT~c=!#zl zB?OlKoXdh|Dl#0ngYb-<pk$318Y{%>B>5hs+rAhgla3=6TB|g2OfR-R=>4q!L`uGD z&tnGNDk_uEeykyAZ<KU3m2BXEDnHZ9V0XDd<>cd#^K*Op_n;sx3H6LNX|`f`aeZdU zuox1>mx&Um$f;zqk=oy$S8^jrJ3nBRZYh}I*U96$5!bq{1C%)%?JF{A$~CwaRi(-W z(x0Rmt1Y133i=t~qyd_FvOqEYo~a^)J&|7z(h9<yhte_Yq}Y>#0fOQu6*0=Q(cx%k zyyDGbL7){s2>Mw8T-@a-?(KCF341Ny+kJz39W4^_$`5{B_SI}xGEXUXd}&22ssRwb zI?Wyg!SCM?LF~`>m?ozcLzS;=a>F{8JrC)+>2z&4dFUQ5d8070ds<1p2Jw~fWdm3I zuhUhz{3jp{PgLIb0bG%A^eYDZPmp2USaa&D&g2z>>2ry^qAN?dJXyPt$F=LLkq1HZ zCIP~^bsW$6w7XOY3jGf#x~0!&ejif$H6t%7kBD@+(WH!Ua_N*06a6HgTYeyldG+va zWf6#v<f-EA+;j|}_8NI{=VxaeZ>>~ah$ic@fMYfI6Y8?6J^R|f{00UVd7F9vUjsDm zbx71RQn`X+_suU?bO-s$cqEp9`bm>PkLGk4d4`DUqk=&*KOAPRzgMU+yGU^OLb8#B zaUn4;=T?v^XeaSpEFG~jnwE-^reUDaB$omV&5avMVo6|tqiCLZFgk~FL#LB5j7DC~ z%6w+0z47QfbC+d%Iv30#AkaKC6N%NDK0f1f!!-7D5qgqF^Y!UMU@HP!d9GF=fV7f} zZpNEyH)LZ!mu!W8jcqEWb(~7AijxbO#VVN|Gpp*koq7#nhMq)`&Zkx#tbZY=tBj2` zwkq<wtLI68hR_mXKQj_)J6H|DFtE!B<p5lKgo-_ep$~Hb4MktQ9Y5A_(!FQ=uzFtX z=S>99>~suyU*!)8cPR}X%m)Ay834&6%9~s!2HJ;&Ag>I2{tc2-Bj2ZM5*4qdx(vxt z;UC2?#W!0vw_+*f{NJJbubcnLI%F-I%V()=J3TnzlIqVKDpuu_^HOV|ABZAW@kLs{ zG>vS{pn83d6l3V9U6j*Ua6V;pGE~L_?kiV?(2N8uaR;BVEa;diM~JPN!*HdnEAZ@8 zdKV23fCAIvff4gqBQUG@;)OKy06-Uo6ejK34P%e=hbax-5%o{gvVD@}&eEVNU(ljc zsEF8CYpuXu%ot_PCADw$eruj0a@M)DMtaatwf`p|ZA7j)5Npra^0q}&CW=A9BJaZz zFfAr(_H?hzF&dCkt8C_22|Ttecac%@3I@|b54zIe2<&Wk)M-H!r|(Lm5jl!e^4?Yw zEL{sGQL?p`r<trqexs3qVh6QHU>p?L#O4Pwl6wT9F0=R)xMrbDuoSh{50EZhmGF+{ zxvU#dgfqvWIt`AODWFMY^vBexACpRIDSjELk+7Ixmmn1eKn+u}v+bRIO@pVWdxP{P zUFCI2fEF2R>hl}8q^=c<#d^F#=<gYia!R|h;Qy*MjANewP>CnkzJwd6y+02xI@1$4 zLzGFg^bUzN#bv^HS_4`<cV|L9rp!5#0zl*daMd%`uR;{G!hK4qZhMy_AfDKLaujV} z(o<fa@4PD?b3IYT9+0LOzh!iB83g4Ja2Vc!H~-TpVBIC{G_q863u(;6wlPoKF-tre zF%ErXcMb?)`rz{WQ67B#XGtki_M!k1_n`q^iAO|bRX9>zkvQi|Xb&T$n!MxMdlO#h zpkknKUcWNTjY$?Oclgt%@9r%}ndHwsspa02pr=qVlBJS0EjC1p9k1&t*PR=P-3sD~ zU4?B2rODtZx#)_mc`_bf)5QFCtJ3F{oj_=SyT_AP;BN-H;JuY6GMMr$gkQt$lEe8I z!z@C~0%@q{?Fj82wM|E_01fN#Hzfc6N1NySFDfzOL?X7i7r&EAeh2J$*sl8<FdDn9 zR=M_L=ZCL33-2`UKiQGfeoiCu*Y>fEGym(`#G@!+?rQG81@gZ@NIohJovZ%eD=FK| z(UCCwKOl=-9496DZxa4LqpCb0(@FW`|5i1l{vIb0!@IX!w6r~Z{Mm=jg@nFWSr7kp za`0Y*W4?b&NN<LM!M`ICNUv&qH}%=Z?xZPo)rlOBB#Xr2l<K)AfSFT^TuQ#O)LNp4 zquf7-8gq#q?22^Ve-2ro8oeL+e}{;aAnl(07ug&DA@@t>Ul!mXBhD`U9i{v&nb}Di z*59w92}zrkZnPPvq#u^x#IFkUU;2F{H&@M~hzamNi<R~QWHt%5o#v9y2{hw-irc)n z7P+a6Bred1eDs!$cEIeZtB3b{>Xpu}T@<*xt?r<RVRZ{^hPKPq*ER0|PCIP5DRmUw zGo}{0y^lD_bT@MSRr)W<`ainvFv747f+<@-+)RyCCmDh``xo0vmfMkIysrJm%nvay zNRAVw9qX#Uu3P#TmHgET4IVwW9Im#xr2~ZHpmo@`rD;V4(aUF*T$Gn>5+vn1gJBnX z=FWO~Izn6zXG;dCd*;J~Xw<WgI3Q3`@#FVYixgVy@wz6<SgQaZxCtI046^{1F+c<< zUz4IBBf1t_i6<>#9hOG9FZE<c2SkZUj3A+5fq*F9-+}e<c08bH*8vCh23`u$oc1|_ zh6HCw!J(@D7l(yyE~CmW3D+)=iQq~lCGW@c^41+sH%_6M<bpl@z)VO_7ehorr_I=4 zyd4foJiZeGX<BsY@2<Y|NJ-{sf9OnZ-;L-s4KAv^gGN?t+c=ByQV2kFIXgs7VWVL# zXZZo&G}dA@o`GZ&A2DZa0OwH5udsQ&yvW4uhm8R$aIt?h^!?7cuP-)0$pN3M<D%Ye zp&@hf?J)0p_EXe3tM;>JLAo(R&3YguNt-XcUPgoUb(&1rDm)frjRia0L7FU)1j?TX zj*)rHy}nVGKgYV!xin6lsI;ZiduMwgFGvjnhK7Ka?T`rPI*&{FQ4|TH4>~VYXppIB zJXTo>s`O?7o|s+&kg-P3wJ@Shj7wvIWXtV?V%|0C2gbLU)+SdQJszLhS_#6&1a)1h z!a9K9htK4b=;N#9={auYp_%-W;$F6OS1>PKLInMQPDXbt*(Afv2KmodM`*&-DUBM( z{i8~LCaNX~BJ4FEXE@(SkWO_4r##tc6q6ZEn6WpA>WZipf?F$y(94Ma<)A9`;LPym zK4kayi-ld}9n(CqZBOleQd-Hkdo&{V&_h2feYgGu9(FoXa&ESqHPVoSml7%B28hg_ z<!yVge;7>POA}1B`<$(cK<!Y!30FpjS>;f)1Mz)~m5tQnv2#7ClB!n!G6KNO!v&%p zp}j6>K{oBICZx+e9#w!M$MTb{5;hLU&xhaMv+X!u3_>4DFLpqpy3JAj`zf=A3%yJx zgAt}|0&|^DyB;*qX;X4Y)WP|nR_Ly_z?F|Qe`wl?Joy#FVB2|DW0q<KMZ83&oy``L zRlX6tk3-SILo?7#-qGLK6*zGn(?rebPf5qJI!63z+{_66#Ur<npUEUWDlPzavOJoq zXNDdJY`9)7!v$YBHQY}E{V|{m5a<_6`!C%`bzIj=V(K?9MtXeVM5EP`BGuJakE%&X z?Sir={Vf%`x;veKW~neSxNGJ<XSFo3*Se7bL1Jf0jvuc~(z=u<a)IqWHfPKds-d7e zRu^W9Dp`CLpjlO}Ho<mOVPhl@wk@pO^kV&_s^q;9pVc*0&bx!qADUT-v%9XUCc5w= z&h32=<hJ>WJI2&MXGIGO1l<zSDO8l^Q%cdgaUjvb|0Sk+P$6t0(CgV?;;#5%$3%lA zL*Kq&HTnA6(%WjhLB1Lzmp#{r+w0OZDWBWxZz9+F=sPGA<@gRmCkYtFUQwJbJQ&<O z8=*U{)7hWkZ=WcEB@61k<vMFU6hDYa1y?mP1IHUAj%GXI5y}*JLMnbG)YwDRTK6jp zOuf9PaAi!KRI45=na@o}`8VqMA;Q6Ke7ns(SF7lIS>F4$JX0`PjMLUiu-;tUg~`W% zTNKEQxStFEhh{m%$j9!!$`&)}E3cz|No{odV4I5It-0^?l5XvfF%aI3Abx}*741(2 zl}CxT!u%Sl6S{yUpx+^;M*KXR(q&?GCZPzA2Y+T@Nj@40uo^(9gX60ZySd;w#~hn3 z4j$9%m}xQ;3Z8oHKTMcKX>yYgH@u#c;L@O8{_O{`qckWF6QT|N8CCJ*o>b~OLLdr2 zbPxtg0)sE0LR8l2*3{8omez45&n1etc<GxkyqEe8UZ6cs0J(pH(!bW#T7+~0d6TQm z60rD5^OQ*_DxKk)aYD%7$_wC%$B%|SR;p19mDutOWZ}~h1HMFEz9H0*E0=O1v>2-@ zAscB2`Nlnz2e7?uO!cCY5*f&}l4T4rSG$5zZ&bke4a9~i(kw4-+^5%a+5o}hz4J#y z-24refMV}7n0{Bu>Tt9^G>~enNtSNcRdaxzaT9E066y!3tsFXL-oBvgX3)t&hYZVS z;iKB>Z<0-+jztaa-w2PBA0lJHP7=PYnKHnGFdBRF(0ZA4YR!?NzIO6FmZw(0z`P;U z#@ea$*)FHHX9X`@a6G}TP>UR|cUiZOka1SnW1gDO4_cnqtR+E#=5e@W%Z&Tjb|PDG zo68rK^`c!kY^^5!6JoU(Rhs4~`qVmQunMKD3`vR0yxvy+8|a%ny<^k~%G_3qz(sH% z$;Ktiql~lD?J;D0aMUeDuw8RwNP^af5RZw~&Y`rz)tJIvR%j8WryM$a*wgkZ;9uX( zYdc<lqSWYXoe>UM*}o*>Y%3a<RALD&N|$ZneL~JQ1XnR!T%9hN^cYZ`-@uU)_aTX? z{l=|3E0&NhBlC?cl^Wtspri$f4DfEXR+N817swSq$&FVX#U)sDd-qni<jR`STaqr9 z57Dtx2l5>>(8S=p&#dj3VrO3`Of$+JottTibf}wNt=<!kFefmb^k=n#T59$dmrG_h z_8-Yw=oXykSk=7dt`SVwC7q8ukU%babXJMa-(q~S+trGTc9mn6EI61m8qvm{Fb;>m z+(l1v_>h>NRiOowZ1LFn82Q=C{JnO|RRjd3Kzx~$$wEky4#Oj&LMsp#<g{}%Q?jK= z4B5<6#j?*jLd$HDnXR5PLXVSHxvK6*s@^x%ptK&LRF+T#6bb!iU;KLF2#EKc6<S(# zTIV;g#bb5zTnQyt`tD5D+0@xINaEFK*(^xv1RW)YQnL)vT=-kxcekMsqk>5i&yjlc zjtH<DxCpWZABV1r&dLh3e$C7gK4%8#iv0bS4*g$2=nPHSm8+=b=9O6Ye3*tn{s%ab zNBl+U9#E5<9Pr;4{g;@e(*oMqDvVjQt`Zbb-mDt4#|xL9DdplY{TCtsR?+{gxeRYr z%l(5%wb5b9#3(>CCJBNw0WMKY0G0k2K-k@e;k;o=<e)^Dx?>i@F>B&<c<UCxn6RuQ zj|!4rzpJsVxou1WY^<VGayL?hx+8w^j)eL?y43!@S4P@<RP0A=wZN`N398zJ@;p?a zgS|BNlYP4gB3T?(z-(SSmG9|c@e))+r5jY(9?!ZX!aqp{8$B5Hv^g3>Y$t<XWo*nG zv^N2R9b&Y4hM_$v51lXC?pD{yk-g8Ez$0C4x&{M5TnE14pzieX56VbML26ZqL*K-x zr;M2n;Y3OW*yV5vS%nf-2gO6fBL6Cvwjlg4fBb{(@qa?}UpM}p{eg0+DWJZwYznw@ za&Y2EBqx$8rfL!=;;^Utk;?p9iZWlCdS$2E9szM`*T9i1v@BaT-vlO`OdX{-W+l_} z3(Y=P1Hs&M!Ch>&-1M2+;EZfmV-F(AMLR1K@vW-)W}AmxyTO8gt2m&Qak+QtDifit zDrQiXA`$E@gJf30eO$|H%FoytoCK&?`&Z40=mz_)^EEM=J=E}0iz-mKKO!-gNXfEc zyPe8u?w+-GMN9!><#wKCeiR0-v`qC#<9%^)3;`^->mQNg_(jdb?=9{T6~%d9H=8A1 z>n;waIX%|%#LnD~bm{f17<2(hHR30_fqrkS(8`V;zw#CTE5PHTIuP)M+CBJ!nH0NF z;R7*Uf4|9?HfQUUzTs&_*kew0&pC6|a~<6p8yu|nI!J&hpyaa*AA_Ih^I|5pMv6s~ zxJoc*9J(6_mFCk>4&u6{+qujm6e1jT`Yc^8CPMo|4gV)m(WI!t`|*O{B4mztcL`k^ z=<Ij#wq$;ueZio#c`}0v6RXTDpOS<-E5i}i5O{S?70^H741TPXzJ3{4DlBIP=d;<H zj9~v={kOsdM9r)9u2FcUO#h$`K4qkC&h*HzrRV`Gx`U=TT!I?D4&f3w(@-{f)*BbM zH4O?fJTIcEn3;^GG!4!D`jk*4YnXDQ*Za2iQme%oB`cB39=*i$4&_c()YThMbg|?6 z(eq`PftxSwyJB=GyORrCtYgK&(gh_-r>Ua6>`$^!_B%g)?-FUn%hZ<1RZkua8;e<- zb;Do{cV1G-Qka#NFc`P&o6a5CEQLR4VsepWLM?W2I4Pxzy_LHfj^NNo*(_efm0$kD zd|=?6ZRdZ5|64sE((jNh(tD=lP*k0+sxsBk;+Jnz>W}`RvW}9Nz~f5bV-2wvM~RjB zC{DQ#ed2c5doa@IAY5mQh~qPpnKV=i+apH`K~e75naHX9Ad0P`N1Eh-_o4$zv`#bf zz>pLlX{EmAOBh_Vu@svKf#M5$WCEO`i44tyv0Aqa4tPWsheT&S+bT0EF=(8P9A_A< zR{2iysajzu<kNEWbtRr}vI@OcnsQc~YpE-sn=`+a-fg`hfbJewIW{0k3|Cs2#Vr~S zOom;M+Gy<A`u-m5>+#cmkLMMd2bI7vJpxdP^pHe-iHa}Z(KJPR!s!)?jx$Lzv6|^| zG6MurwPsC_COc?e!co)PiJCV~!cZae-Zk1+u`+%pilkz=VIaxL=Pgt&$Ew92uFv<q zOrq|hDJy~Mns~;i-1{H%+390VMgk2aK?dd9WF$31<Yh%R=s8U3ZCMK;$cc^unWL8- zh4B$?%OZ{>=Mig^{LSiEdq@a4D@K-a?-q6|3SOI^-WH4vW&mz@aC)+del*dxow6lh z%nKY@UaNSrICj!^%B>}K7O+Yy`Y3_NgEXh?l~H5h;3B;d+f8}8)lZ1-Le;*X^x|Si zbpf`3?6jT7>IW6>PjFA)F#2n<>K;1bZH;gh4^mIoNVG^mqmy}bZhw4sx$3O%Uc344 zq8_xmGqizX+*gj%h%xlSK12^P|8gnoQ^qSP4?`x_&G`Z3o)BTbC=e;q?MG<E;U=Ej zq<gY?LXDUVn&-TcNSC16qZ`?Cv8oHCO{g3M>sjqoHEGuxSdq_mkL}?N_^Z!&f%6-q z6CC7u3rJi3MecUTnf*%EMG0S1Wz%_bZPe3GkUqyr!F1ZpwH-@`m1A2g28p8Pu00?o z5|xx_7%Zi$y&Q`y$L)@~k~#fto&@md;t{he-}R+}JkI~bmY_@tqFAietd2i|tULMv zWmGD#X2Kjl{Ne+MrP7Vea|dR`hbu%3AU(5pA4;YFu#IYMg;mK#9bY#}vlYK7hEomQ z_ZW2I6UeF5es7T-S+pNFRI*N+0i%LodHL9q{c?)sSCU<h2^bP2oo9kKI^T43{m{{M z36H)IdaA5lv{*OlQqWT@G|0(7pgdfza%UJk{~(-5)O5`3(T#dcp@5*E=A2y;lX-gK zhb$YWZ)AaUL#f)Ba-2)K9Y4P(tJKQ;bG|#u-YQTO`k_Ta7+6=)TsR=`?;bXQw-7p9 zwLM^9{lZvy_#V=E?9_n%{e`l$MnXw@=kU9wvaS1y7y<fC4pE-`QU4PD&lFcc_VsUo z*t4e))iRAMjWMw{hPJnD|5VKKpl^4WX6{JYTw-586432!4fLs1@w-1+?I4ze8AsZ; zLpp$%R77hYf%srg+%4_aaz`tNTTX0F@fPX@hTV?0o1>%6E{FuZA?IyzF~Y9N+zp8- z5k3x;74p*6xy&ZqE;3teCqRfS_~=pU-&AURpyrN)+^7-vki5%*1h`oem#RSAdWo~G z)Jev-*3H!_c(fq{LkvM@a3nfbl(<E^BHo4=Mjq{Rlr3i~v@loNvTA%Ze|mDf1!sk6 z7l^G}#K*s-SSf8IwGg}6{B6DccfhGJVIDS0!3UKlHi&@#(|IcSvoFlUBRSSqi{n1| z&vf~q<+Sp5#a%Lip(5c_8^T4poHI@}mK_5oAey)LDHuUpEMktLM@y5%^$teK7!7lz zqm2%7f<{5N)?)=$%$EnWn`hL}3J+4QywG6&u-&fz_Jcu<p4a3r5AR7$FcBh{Eeql3 z9u~Xz*{e>1$OzLDSE`C?F7EV}tjRrgAnPRsdU^RIh?mUi(u?R2^_NC@W`Px2s{p&L z$Hot@sleyff1F$_ouUbZ#Guz*r_0)pi=}M1u2f!j=V0mfHBtVe72=qaIhowt2)iRP z7TM`Ok^Z5Vs%T#u5&5E8V)c#ao&FB<MwLgo6<hFlR@K}SGMZi|E_S`eKbhImO1-vk zRDRfGPj4i{FgoJ2XUFn*bJpdzAvoHq4q{Fy>k)0>bG$<HI^psKHBbcMF~|8u@P5+R zqqDi$JO0M`TQ<DJ{qoVzI+ZJX@e~@?vbC9xnYH<_mPw2foQ0xE%=9e0Ce!T2dpwO` zS(B#5=(yGJUN9vQtWpFczu<|9gFpWwrT%z-dva4RMe}eWy1oIO8VB=}-|w$|#90=Q zhsyv&1oY~TH;0u;p&ceEe<DP+Pk4dy>k$zkyRgacmnzaUYJ5Tvhy6b`3B^#nF8Uwj z*V@L75hXc-_n~ffnmb;)NA$ubA4C_S^=sLa4<Rl;Zkud9=nw^5)81urqssFpppRVE z^dv&ZZ%&)d$V$gX`hU&z*d-o`nx93q)(KSQ6?M@wuEt~jF@lXDFD!*$?)E23pP%In z$hy1<$Y_6k8{ERf?=r6V)hu(3(Ob8JS|>z3YgyXQiIoP?INE1wTVI}^?NN>Mk?19b z*b$^flfHo!bp6J(wtRE}A7#Bwxh%FP)fm>^-3r?3w*T{Npj}pc7MxoK#DMy{(QijH z>{GkWT-1>NdVDl)mmn(BgaXHgP<1RV`tja%l3qzSlp9mh^}W#^2E{n7Xd8~Bf!OZE zpvVJ)#Y1~{+Escy%rhYh3j3_>;ZN}5B^b*Hx$-0EvQgTVNkngnK^l|;fDE<w5Wo1^ zy$<OHcce30qq@Lk4t%oaf^D;M)#kiP5L^+RdBb>T;z4WH+j}rX&t)+9&s*2!h0z|! ziZ<SO7_Aj6cAY=Ri9T-s)^(jO0_0q5xr3Q7d&w`3$#;35EjtJl72(9GCg~isew9pl zjljZp9%&k;o}B@2LEcjOJim`^8zR9`uKAhb0?mDW5BhrUzC#`Sz?WxB!l8&SWxDn= z1O`z?*ZSIq6Jc`ZmHDIFu(E?tvc77{sa366ZGRaFyYeTQr`wb>XSFUmiTjrBbFg}; zXo0+z16GdLAZ*MtXyU0q5B&?KpxeC?oui`bSaw}@)Y1Xt8FIO7_}ZT*Hd?%r-l>M# z@ce6*q2TC)p-1earOGhfz}_~k!b4<L+kgtOyaew)`m~I3X;&}~MsYc%l6)ekoPvVc z$Q@#l<eT$TItdI8)<H>?y9E$42-R)Rc+;pUuU+H@F#TrOK!^ZI^%fV*-t^y`qio`2 z(htgXHk3g{J;Stk3xUPFd@q(vva~5L9<84gREf4}R;USRzC4><zY8?K7l-O@roTDn zi)hJww=>JAJo<B4irZCM{iLB9#CCP};%%#FAw=c|U9$sZeI-|Ea!DguA4FI5jF$}? z$+K{KZ2Hd;q+MNmk7dIvTiIWu{dpm$e*=mG)5zGj63iTtq%_Yof1T*Bvoay@<40M6 zq}qbi_O3~@ea-1yT_^E!H-rGP*H-3Aun1<X2cx}X^PG!7K9zrL{NSlGFK^s<{$J7m zQ(YiI;c1cY{EZoY7xsvByQ^AdT$vE&6U^ni6y)n2SG!tiOAir?coHbhUCx%?rbhTE z1aS=?$g@9+>Vy6J7*H)_#~6`>E*++ra%s%*Tmoslq5Pw6+cljQ9m>Mp{s)uli)vV9 z#{gLfhGUXg5&Neq<-HdPNaLHkTnhVe%G>I;BLLQNc`{h=?jSQpKKR9bpOI5gSG3NX zwR8OQ<3h+q4=Hfbrp+EPyzS%zan)J22jFySRdPZZ%aXo@5Y4aCzjYVuWb6k_l^lXr zKD~pGL1Xd}23Z(E7ibQoPDkA;du@>uR*?iX)Ku=p9*rT;s$b_Hk`%tIdVFhm3-1;A z;jinDn?8szr*nOeFMb$U$h)tTy<7F7wQc-=ToU|uRHWH2Ro?Tq3hn7_{{i(FK4P$- z_UwtGzt~l$Qx3*ggHV1AIzgU{HiTw0eTtN?g%p=fN}{^cRK*8&dI+slv@oJ!K{Rp6 zO=WL0z@hruz8d1gHyLyZ`Mr@vj76f_$$WgW+={8~<al@%ktdhF=@-~s(9y8tJnBJM zM`xOj1<eGFoeFtcFMkNs?E5Iz$@6S)<wX4}BjZkGlBcmgVk_{=@oChXtt5{O2@Q?Z zb<t)8JRcbhzdoYsBp8XARvqA)9vRi(n>@aAKpk5>Q+?Zvw8o6lUnNRTp9Z*NyTFd= z^ig+lZ4+nf5;7+bEiTZ-l(TqYZNGs%F^|^HU!_Kof$`9k?jwt%O&ib789p-Fc6I-U zwpX!F;^#i>Kaiy;jWrd|1%qT{WyKy#!%%WpSx93}tyv57`xrt#KjN|^d%$^1;2%CN z)6#qLgkQPqPW7u*RolV}p6QY35`ZIps_zuUEj5iY3z09oqu*eWhdJ4`d$8O)y>5t> zsSl}|pu3F^g7M8+$J)<JL%k{9+{5A`@D9XEMP-T18^Kj^7G<!3gi338e7t-yCO8IQ ziBpH2nL5Ve8l}cWAkb#bAgoi}<gsa_xKqmc3e@ww*=VT$DE5&Nm#P$@mUZ0R9Cbvg zPr<P+f^E<X-FBZmdCy1L>ID9_PkvWtzwfB(g;=U~GSG+<PVWA+GQP2&|G3-X4_I*h zbBnCKwFMWL&kwCb49`!;j<gO+NDY_-&c@CjT|_GrDAqhPZHO~JS#^nne&p|jf?%@~ zxy~xeS?e7TQ_$*x5$u%|MU@<B1H8>Bb!W;!A>3fjq5<YvXRnK2O!0~B-jSK;e$fc_ zY*^&yp|*V@;+}xpxpmUUrX<d|{8GplAw#eX_S@Sf*pMU|8&l=dud_v~7(Y;RH<zT2 zFlD=vD<YtFVidHjF{2pm79gc*H05^tim*rKrt0KvAH+rOA!!DHA>;HU!XGHMm?u*x z3;1$T_ZM6UFx&&rgsNeVk>xpExQb7ypt`(^Yh>F!(rBppHu`Z`gG|&_L2oW`A-CjR zgJEv|vt7bhs`Ea}^VUQ%80fd1&r}wZWHt)}yszZn-EiA|?=`3Z5y^^Y5h>^`vG+M< z%w<=S8m6_WCuu1AO_5@=8^M?wAglvf4;FS&SD}*Hs@oA33WKN-$Jn=OvA#+koEgI| zasmx0q4X{e&Q#4e#$M8;@l`pD^i$o$kr`CKK9ge*^%g0-zGGkzq8bkdtEnuNuZAq8 z+sNkYON^FK^i|7MsH91=l!4tvEn3m23(cDc|GRs^R~fXog;7Ke4+>fL#p=TgJyAoc zy=N}s@LW=CKWtJw9TI!x`L$2RWq>o0__#lohDBro&?S%|WgeNMvgmS?ZVEgptViY& zL40k^vk<@;35Ipydr=;UiVSux+TIO!Q0;*I3Qf3-rO(>0=cZ~xVm%+rg7^X6=Q*Ps zLNhT`rY?QF$6i`&jIZPEal+H+F^dl6X7nHKZ*U0ef2a%xD5dF`-H-m-1hP0rH7M9k zn`01CsK&RYzq2=4h=nWcMGm|JE9JBSAB1sqyDOaFfyCsrl%04rEveGJ*Q|~(>1b5t zv}Fe3m)NRCZ*GK0mDL7IjQTArV)xZHV|hc1z%Hdm1dxXGZJyc37h8fCB}mhPego4_ z&1da`%i*5UQ;E;r2?`ssW1=e4`@gW!z3i9sDhBH{_X*lF5c)lOyt6%g(z-@M9+oIM zcevC3*=)A5=oyD+ydTM_Bv1+}QJg>qhg)~OpQe^hrH6wyt+ronCm3iGFfd2(SC%6q zw4%~E{u*m4tS|T$j~JK!IpyiX^$BcA$LSD@p@xj7QQp;^-Ll&G9-kegPzw&CY%MSl zq*yY9IIt&^30&m*INlvao4WeiRl`D1MD2n(#hM{&!9!fWB2UupiD~?krmcT?+z*m9 z`nCl5X`Fw7v1z4reHUIJRkbDhB3FQ9!@p%e57k0@_{I%+zc&k5&m@4|D`CHG`wPTR zVz01m5u%K<tL?e&aHvY7bI|G^@e4PXgcWA0p4r`asOPKtxsP)chCL$r0YVssvwz~# zDC5px*+j7uPEgHHh?7R(eVF*-VAfZdr;jW&a-Z*Evml3$dU28!P^0j`>)CE#i8A@# zzGy>aBkAKKlYnf*sg;Ol^O{U830ScBG{_)H-uP91%RzNx&IHfgzF+!e<xYL;3OCeM z<L)VBT21OAWRD+0w;QQoI}4n*oV&E`A3s;F`U}ySR0BLB*&i)xoPH+!jV|m7Jr!TG zcU;bHFZ10Aw{3e6)8I@<bYKJCovzL2xF0De(}fxBMgUy9MWLG(K3clJrACIF+jYF( z1e%^I?n__1EkU`7o>Zcw$8eB`JW1-a2uPYNu#7V)Ts!&^>YnCXog6N1q6DWa(KpR* zO80!(*fA#?TsZQ^3QLAwLM#Vbi8RgcRqNM~E(Dpg(6K`lkp^Aj`)j}!*G3~7<AVbN zEXaL7N}DRF_)0}Qg=rSTOBXMGKvpq!d%|jJQ9yiYnLCQW4UcSlvkX^63p#L7hdnUb zbsL)|IXhw=r8z+Fq2D2CKgF_`07d!R=2)4Z_Q6P|3}{g4{Oh;QB5FqGe96N*wIh)E z+y^i-ZP}RKNbYBhHN3gyC{xiw@1w^wzytwD0!R+M0*m^6H%f^BHJ8;tC?94ZBzM;| z;PSLCoC6QPzpU<aHQhY;k75*rD+eQL#f7;+(7L-y3hJXgygTE|vyy)XBcSx-3%!Zk zKsE5l1`AcoppN&QvA$UfnQdHMG0<Au;bx@JE<9o=GtRg`N!BQix2Hk7^Hg5~b2POf zYypIwWIe)lAI$xd`LqGt`zI(!w1tqTcpEAP?F?vLig;+{o^E5Hd0_3;gSqylp82~E zKbfE2@%%5folRyA30_1g&yFE15@!u6RSY2co2qeP$}gAvA1J?Hm^)@#(HERZ{uN^k z!uG``4-h-)9l(qoH8k@!Y8moe)|nEJP>5P}`ZWQg=Zu{uJp=l>#p9kLXl|zG165s| z`~_6+nsG%6W8EQN1Tg|#n<0HebFLPnbB!sY=%2xrKmL>hGWPkdZvAz3ll?PVd%*g* zvNSPtrD(U&#l5ySPbB__CH>y~GtyfNHmZmJW9lM4hF9JHr;bH!%A;e%`jnDOSpx2e zp}ldxLiMvlk$SWdc)IRY5w9aibgq|!p}2t0F#&mxR-nxwj?B`_N5)k%qHnwhZD{<H zME`jk`-2)=wM~2Xnbi4OxzdC^PDfI%J}V`N?kU(^mv)@h-|fpAfcw!N%@B>9^b;h( z=oVDes1U57EAD@HM|<e)E~Jsi8Kw~pr6EQjnT6oHE2XIDM5Hk8dqFfcEOMyOb>PqD zO%?0w2RDdVi1aJj2RdcDtuDsd&Yuu|O8dW&L~zRDKq#f0|A0z9N^aW~^p`}hst7SI z>cYXla#pC53^}`69o1_TT{}+rxu2BB@ZT;bcOaGQc(hS=S`|Bm8&A2%<c3JgL7R8F zO<s+q7=zB-OaAM#smvI^u-iXIewJ1~!u%DHu2MeWOrk6QO(wtjipX?Df*`xCE+eIc zxCf)oY1*n?uk{2?lW^<Hc?H1y<XPvmMd=(5C_x*{4LeaY`CMJNTBoQzF)3(%@Dc`4 zq0%DzBgHNRpgShY6viEC-ssq~Fj_?*8H*K%vit`pr_hgtql0v(#oR&p1JRIIzZl@J zrvEPG-Tz(P-)7X;tDDlRb0zh2znCUZT27=XB8sVgkIJ_2jsplFc<uJ4+79}(`3z9e zSt)(;iw<>aJ15GrVaaw5m>=mL{~%9RwnB}auQ3Wim4ibyj;HvJ?nn@Is6!d~7gNlo zn^yFlL~P3|;U>wgLPfb0fA)5s=%3|{=Xhae-wFnwS_R8oo@lTUkbMwZ{5aM-^>LJs z(mwf5qvoI`xIU^0Yg7ig6INQ)4w7$H%&hpe%T@j(JHBc(db}Y0g#5W>i_%MP!v);e z$W$;w_QqS(aQKo2d*N^EFxTCFUbW@E1T^r_!7+9af4DV_Fj&Dlr?J^m<L5Mi5)f_Q zEa>?d5L}VKzkezf`^C&)KSp;T&MiY{Q(-2%6$P#K2gyfR2?=`DKedfq9{bJ%6p$ya z#vWI@PN6fy3D$hG?5In!zG|sEXBNNJ<WJoX9{Xx-bWIXvAxlC~SV<`)zr@suUxgE1 z!UmHEB+-Du#<%iuBs))=i9Z~Co%ZH$I#G#coK{$Iii8@Zv{WOh%oNq(rd{v~5JvZi z@h2&Ii)Z0P^9o^G`jtgZbP7XG>ZM|_FN-huk>-7v^8}oFaQ&r{{|ac79(Ibnl>oHw z?TH5qTRkaM5Atsyx0~O=>|#iC)er`BKlZ7rMK7a3(_V2`P`5q@`&+Ilv&4)%toSf9 z^4(Dv)Fv&@wM8eZ25P!}j{zoC)8e66MhOTK&OW=g?>M?${f|VF;aaA@BC9-AX_w^P z-JCy7?q~l)XYWZH$PH5jIn~$DVILx&W=^KORrw8Q&i#Vfbi|F}86`iDS;yUm6B=98 zUf`;~l#OGT=0>=Y9okO(L21JY-9JJBo5qb|SsxF*(PR;*7-$uaqCX=Q#-Yuj^?3*s zvst>(fg9zodAE@v7x@+jox$#>nsyrjr^!g>&6<{MfxkOb>x<E_l`wx;RuQ1DV#E=- zK`O4ZG-4g&*E5$lDQyXfAEiU^uhnk+l&HSKIkXm}e?%GKr=fKjIzJO(|Av`XX{O38 z?5k%5gi3^t3qb{9#=g_ma^@)Km0eL@82`b+JenwIy-Rd}o>baghlqAV>FE^JunypU zIckXzhw(SU-3Z&mx-+YIBqS>}6fenFQd?I_XvK0%#8F(3`%lVs6m}MYvs%$tW)jrL z*o5pF0zJ$9(57Se7`U30)d#OF&}lZtSq`KNa|?H-b;?91WyhAwN#Rh`<mUvyg53^7 z-^nqQL1*M=t*vsxr(b-#iVEq8gXjAI97ONMn=Km75r)b7D}o<qxDLZT0pFFmJ9pzi zVETvDV|Zu`%2YbV>b-UBT2tG`$bPAB=gT@W+SP#;5yW1i5vI<0bEVqvi#JUL%kR0Y zx0Z6bc|^TsyQE+zOrBS5EU?8*=(&10E|oKPhAGyTg*t@!)VYush?Q*fLf;$a!wV`9 zaHFTEy3dm<R*8xmQ3A((3;VdXePNGl`$X+&hZT_IclTr0m}y^LLw>O*yuKUl26uJ4 zKutiTp9wIw#7=9sZjEUZ2ZuY>fe4z6WmvJj?AdMEe@*n8jtBjEe&T2~{O%qbsd0_U z^XU&d4z4|0>bv1&818YPOuQml+kNWO7P5ZeHY@WQsF@mGdi-2ki>3rwAk)8U+@oTJ z$bP=&l&*4JaVA%WiM)xK-th&1{&Cq}mDOPpmi3bevWz6<=R;?n1Kn?fGWSC&w*k(o zEcIA$gKYlUun-qMr-%q*24DIKiK_kersMCN)Tk5I>F2GT1Yo*C6kx`M;$@*?Q3it^ zH2(ac^cS@ZNkO{wTF{aZU4uxI3<sZK9gK7R;)}TCp_%`@jrCdNiGE<a6<eeX2)~8_ zk)DWZbL$*ykG+#Ez6v_YNsOy18g{efKW1!!OVPXO22X<3R7eR7DZc$vQTk&FxSy`g ztj}6#>rmsDPO=B*%0JQ#Sl~!}$8+lt+*|A&boT3)Z~ZlFP5SbqP1q27xWWW?C+aER z$8`rKAVq|_tJ!UK=%&Js&lXuBn|2PxjZpF|>A1@x=I>@0e_hxTq0yMQs?kzea-_Rx zxtTWWe||YmpH24i3Ss_A3;$oj{6k5^K7FY5zlCZvxz0tw=YOmabR_C89#%HPS-j(L z=Mzmsxndcp3EBlJ@La9cD-4yZ+t~?n^Ie)nGxUV7apD<*y>gz-n|kM99wTPSB8ZPo zA&!+d`{TPM_dKMJ8OaecIWeC}v$&95^=C~0+H6rEDt#mG!VeI47El=qAoxT3bz@?a zP1>SP>UrajX<Gl;t=gsKbT@Y|cF~U`G7P^*zfPPDLQ55Aog?<hDXP^%sM0}8XaXAL zBYeG+j0co?bQHci8EpS(^TWcqMVj5z-z&tHcwV4SH?Ob}(y$@-5a{-YLJmt-YpdYv zg+flzcMwh~@<1=t+VI)ik_HbaDf&zBY&XxxS>HT8viB`&*Z4>5Hk}lwj9AeJ7c|8L z2p+RZI7J1to^gD4|CDIk-%rF5&a!sQ*>gZcqpMcN_q8JV+8|<}fb9Lb0NT##RXOYr ze$hY*7M=7;af!d_D7W{B*pY#+)bxXp2WUv{^@{kql_oZ$#z;k`Zimblb3jITAw%g1 zLMXhT+HrI$2NE}b^r$?`NEu`a9C*DSy>qQPKos9iiVxn%xV6k0My5w0Gt(OK<#FL_ za?OFt+^Rwh(IyjHY0dqpvSRSm$vS}{4Z>+DNv8j-L#?qHW_EL^8Y*K@y1JsP|JR-S zMt^OqvBC))g%+;^&|D8+)D!LI7(WB^Gkhy(`M_=u99l;AYc;0UL4L{ZfC$O`zj5~- zP))5}yXZ<K2>}8G2t5fs6a&&lO+u&whAJRps3Ia#6|p5D^j-y23{{#+Qvp#!00jg^ zM8FP;fY?y6E1tOBdw=`;@Bg2B&K-B$@!vC8V`Z_j#+#Lu_nqaL&z$p2r4I_}2$GRM z&|YruJdSV~w!A>y=$cmTNQ~e$5S>ssa6`)3@(<90=p7|IkPVl`(5nUazDu>&cGrVw z&dV1Nqx0Fr@r<q8GU|SiW}oZE2a~{dTY_M-=Ug5O)WHGOZgM$^;YMk9<@{)3{vIK) zM^lY@F|X;iV1F^F(Z{_`EhB0mgt^^5xL&e4nB`y4Rk5Q;Fr3<hnVlM|s;kUy0>`?) z1GmJ<VhUrSH;+!>g2B!y+$Uox5TQ?M#Xq}<dtGmA&vcP*rt-d1AH*x?b_#J8#lOWg zsV?n#4pLsD-w!<|5hS+k!JAV8)GOT)1BXhLxnoW#w=S5gybWLI^U+LtVicg(z{My+ z^VJAxcOZ=*V|10j;g-=j4{BH@4e5RUJqZ6=mrH`DXW&$#g+)xEx~D*!YlA_$xGT2c zxk|>2;~-w<0(~q24Lio&zbJH_spofnIrwQ@8oKUd+jdh`Lm;zRUn-BCcJT{i-brVQ zeATRvA)lH^>IAQ!m=2Mp5BppIz|Es-iB+4R1?$tefp-)Tsgu5mt>C7faMiT!=1e%e zEnYIfCu1pP*~28;#zIg3OO%<4=G#t5bWi1D*RT`)X|Pk~k^^!Imm43gL96K+23iGJ zi8`Gpoc*$I-z`AtlkUtZzA~!%Im$d9JDmCgWkaN)JS(EM&$-FS1PZqC!XyzJ1TrH? zd&gN^bUA@*OfuC(_j<=o(;H;PNqrC=h{`ixy@Q^9UZ;X|9Hl65TF$6B@pV1-tl1el zxIafKV=v}A+hk*P^l#`7mR1;IOxl^3(SkZY^M!x-vxj6_3jbn}EhEq7T@mLL@?%v= zON~7UH!s!lxm@``^HL^3-<8q(5VOrzFRxK*ax>1v4!1Df2x=xY!WcW(?ppKu`Js4* zJT6S8UXF)K>+(Z+8mzcY!cM@zXUshVVpCi@1_wNRXl?i&2;SMINUU26(^ZeRJF(6u zQ`u9g^>~s<T!a$YK$6+r7#6}(UI!v_4FA3*4%bBfE;dtU(&uZfIXII1_)-TF48HPD zmLxV&E5;Fj#unFWHy{G~=p!@(w!h-p876To3Z}_PLumzP`_E3tsV(Nb^~_@+qN5iA z5cKjwSgfu{e}Y}Y*L!)~dV>P=OxjxM7)!qLr+p$w<6Pa08yi?XkCs^~P^5yavmt9D zxCPPaUSu_JUumKOMi1w^b*u?TGv=ny7J9`gYTQ{7UPd+)Q?`9I<?h+JN5`0Yso%e2 zG?KRh-g?p-J+7}X!9fdz<P2qbQ0E2jz_Lc_0a^ekfsm!6KT#_3QiDqZsGl%BM+;`$ zK%mhC2cq-M+3?CFLnj4TWs%xGXx|b3gM<{hP!C}|n)lG;yw}>Z60~hZytuwh!~J`^ zM9$#F3-4Ue1|7M6@p9Ul3VlBKxl;36VJl@0i=xYt{8(IT^y8Lc@Cml3X!#>WqehWv z&CAQon9{eF*3!j3_)5uir<>fE4sJXfM_&nAbLAC-ED&hRyi!@Ii|pogHn({A$j4g6 z&ezm{JP-G;X8$4J{_wnnJWhp&xO2reldkxi143iRPMU^tTUYOxipTZ8LnvKa)L5p= zBQ)#!{rH&V6ABAuNdX*=0uJfKZdl>!ElydD1Y?78{APU}(GqL<2V9bZ1!F%(fT(dx zN6wY!ugZS{LiE~9_3I9GP(sWRTrdTja-{2@77Qr62yrc6kJ4d5u!P_*o=6g!R{e&} zhWSh=n%EKGdyc*2Uzm79`mINq!xQf_5_Sl>f+V1yeuxW_08Qog2SQvR%LFhQ>#@^S zNwV%I5bX|PU!wC2ENE2dlQTmJG$jL`n3LBoB9EbVEUP^wxe~YU+$9mC?1&|g#>b(? zpd0H8pB}E<_`Dl9lQ1X(sc*4*Mhu)P*=z_X@0?mK5zdGWKA@L&2|+fMR;;k7uGG9N zl;<#pN>@YrAr|C~y<%od!VSgT036X+(hEbiJ(-VET!laVvHg#AdvZQp7|P6AS140d zIs%5yXqIij3UXw%;)o>xKM-A`V}BijuSc?Eb|M<vYd4AtX_fDP0y{75KzDG-sZ$fw z_lMPR;SsUrFCK|rUjyweg_UAHkSAl{4r@`&`eE_>R2bW`(si3WKDNfRmk_2vWr6Zy zclDY{_=c<-wvw1vxy6NYM(nDqm%zScRvDcwAuKPuDPro~v=J>}_uDABQTw&T-kR1| zU{TP#pK%gxEKfzCs6<Y{U%IO7*r*q{UaGMk1X=Io+kpP8p(%J%19ZCU+w|3lwVq7> z3Ao+4=Z#fmp#@>_RYS@7VYhdQ=}<RlGSyB~4Xk`8)e)JFn-TlY<dtJ}=X1aQ_S!a% z-1!6j*y<lpNcAbLye7%WQlMx9NqhtXofQVUoxyc#-5s#12dTkYToEi7SlUyh#sbmt zq)PP_x#r#>U(~cU<_@FDvBL2LhGRdrDpA;sot;*MsVFUP{$^d^JoM=8oHTfiPa0z@ zmcZxNN=ZB+7aO9w4!7K4?K`&?eSHOVIgP3wwnI-OTx)zJB~lh#f5&32u46^W@p(C7 z@S%;*cbBhj*I(iGCtf{>sZR(S8{?|!H6J3BAn)vbct5+z6in7VuKU)z?wJzD9JUWv z`IVobPzb;xJccn$Z5;X96RgEfaTb)Lt-EIGzVE~f#NPZ4`4dM(W#9}<>n-%*Y(lQI z8}ZF%MXQ3R*PgD<9?*9B@|aF!L+SPml_jZ(wqO-)toZSgqt-~<jZcSLYFqm1jl&V^ zvUm=oVdrwP8Tj*Flc@4xYEtX9_{A;N<I1>FIee4qXO@u^V~v7W?3|OXQO)I~Bbjt@ znxO-wMZ4o1-YiUe=+tTaXw5P8bLPWt<F-7#OH{6L?i0Oo>BWp_d<zz&{;d{);HXPk z1X{=kOGBrzOf4RJ%zC@wO@Uy<tL2c&2uXA?dan!U`1Yu6Le3rq$O`b6i!*rN_pTM! zkpM&}<Q|W*C`s<B-zlMipG>S6(uaRhC$XHH1B*TH1y7~hoI>b4<?j8?Y6HK;y${Hw zc#&>lzVK_nNs?PG1%Qg?hXdY&o5v(C2!q;x&J>(&1{6cxefyqhm8EX!@Z0!N`v<#! zNeZY+GP$1;aMBeH{X(>w2Kn#sxwM1S?LH}@D5C+R2B5;{X7-j2Ve#416sKC(Z4ci{ z8D@0Co3Dpys61Sx<b%*W>J5}L1{!2`(&QPVKj`R9^>fcj7f=zGUcn#jfXRF=(w2Wc z_jNeisV)P*CLz{Cebyv=59}qA(j?~JB2@|TtqFV-Bin+forbxuS6w+jdW7hlj6nSa z3WvTq>*OB^bEB5bU0)S@RAIVb<67=D+DBLZHlA#O!47ybAdmOnuylwY#$?Fzl)%`P zwQT7r$+MpsuAgcud6hS{rRyCPARgcjOJiGNa=|^FAV24z&$Ih1<(k793HN^jY04ti zz%$27awYxGyp0vg>Y2bH`k>bkO<AKXnuQ)qK{}j{-EQwG&}OYOOx@$f4wZ4TKP%1w z+;wjT9Co{36r2Ja)Ag)<C7K6TWtb3B^1bhiN6`-|i9KkJ_c0W?JAt_oDL1C3U|F8E zQCI5wMKJ>9=!aDJT%E!id&UmEIGHUD<D+&N2dFJwL>gu;j$6Ggg^@2z=DUoSEw_EQ z&M)apvO^(@wHoLj(++@Pxg)gl0@p%TsdhG<nJOX%#Bcr^2K*;tb9PDzj)jodP3wJC zte%H(rHSZp5vs|?G)+NgUVT!{_ySNK&OBLfn2${|7AhG+%nKQ<B`nkc-jbD`LSKd! z!juW8V?qJ>qtbc9ymkeCnC7Wp!u(kd+QrJ$RKhP$Vs_i}r#lM#5^Bi?FmG-5ZdEWN z?)A}ktM^w~n)KB8{*=L_($&4cVJ6=Sr{dd<pHo72=(6QZAO+&t2+>}QpRHytLBd4u z<qaE@;o(4K8gKrlSxLobfkt*8{h>nNb*klSJ9F3k(l|<4QnFdZxOz4iTRx1}TfZFm z4j*u}ke)4lT<uKzyO-B$6|TQ8teTHW<yr5F{J_=Fe!CMM5ak+j?E2<|qK<yHY+cV( z?@Gf=yVM?8TbZ2U4cbtHw`v8l>!+vKPVlUi;?HtMVPW^&;qqX^sL$%V#Nm~Y1gJsy zdJNtrVjb8;O{#CudUVsewfVHH?WIX+$NU{_{7dFTHsMuSAiFJ2S#sSMbn#M_S2jNu z=60xtZw;9<;XZ0ldR7dAW)-ZLb`goBfeN8XWok60aXG^9hBrqno*MudX)icH^D8;; zAWebCON-!A`(06Z-ZyJAmYm2W=yr$+QdHM=yMq)_ViG+=yFoeiR#0*72}CyPm>0Og zlTd_xM{Dd1P`zrYc~cJjIux>6Ayl|{d*;}R^=cfMC7D_|>$@$$f-)1&3F}SvBG@Y` zqu=ga>@8MZC4!}wp2)(NM-^C6GeNY5hA@t^VbEE{jb5RSY=1cl?sC>_csWZ%Uu?Sd zXkx<MxuYt0!$7bBNOnN{;kZ&8xpDML{l74&70Jv-V}I{uY;g8$8K>!&bitRhj-rQC z^OJ4xQGE<i5Km~Is^0+)RulDtB^~Q+qY0TYNg?2VY=Em8L?2J>7gQIE7o?5`#nb%A zx?37_?R+O5ssYJmZ9)5A`zgB3L{)&`59RdEry<Q`GC847%d8Ye9;2FX<o{c!`}03T z-M8<Xe7}6)Ig;c2ZR?s$iBi^L9n>6LLp>1lpp9U18j5^2I4`RqrrBHIBO*HgsZYQ5 zk-$-^yZ3P;pAE2{1oC#!L&|%5btTajPwW}mB9#06Ht$XZ5<sx%4hza$%eM$;yj$QB zU)#I9m;3@4Lk=q;w`RS^$e_p>OMgDLjjEqS@6wnPBR`~SdsdW&;hGbpAr3L8GCnj8 z7hJ5CuWuX|$E+g?QWzE_;0oTOcp`=hgzg07>-!I99Lc}0vHe~$W#i)0?O`*w7(dFi zS<b9|>_J5&I50y#&NM57cW}`B=r#<J&~iBnp><@zbzddF@#{5p?4j_sX)0?J`hv(Q zrI|}-O(Y%Cx92_}<e7e?HnqxRc|4VX3bqhGNOH}_Yr5Hf8Za!NPBr$AsV;@LRB!4| zZGL;AilsSadUOLNM&V1!LbpRvVDnZ@se++>sib4hmEO#VK@bZJcqwEfWrnv%4EM|F zID3m<6aS1_-e}x)e#`#TA?|eOXKd*fnHJ6I9*Y{E6d1;Ej3I+o^hMn&^75{5mwc7k zY2x7e3~IjOsEbMg&V&PWU!O+2i@fu2%jaMG@82LIG-ylD7@$`u)BT0}PMR-Lzb5F# z3*j`ob}xNff3;6<cS>oiL&qh8r@wYic97CF|5@`Xh14E#yF45<0E(E#IVVDk6bQ{4 z1~G>hSJl|a0OEJw+wDQ3bj12uAP>6hk;$nSG%|nhK7o`v{$i1v=)BR5ov}qngm(C< zOS&m-@W?1dK=I7$WwwMTo^m+rVb^!KUJ##1jNZlTQCDK5#JMb&<%7IpT~vn60g2Ac z-tY1TYGLo22THMX0{l5-u{Y(5RBQS|G9BPSV!&RcBX3;aaM)oX2<2X*zbu)`1KK%> zI9pqF!{$xtHTL94PXXgZZ*x8+30HDB;EU1uU_N${;RUr_3l6D8=t2fHmg<hrHq@is z)kQ`;j9}xWZ)sIwt;AqI?H=M-q)CTjA)#<zW0ada>y~EXz;j6im>L2LD#t<F`+;hK zjy=5yW8mO!aR&Aiu=s`wRzmt}yBm8q_62gLTPc8c?*TxBOyOVHQR$p)og9c#@Y=Bi z(4Tn1fz3cd7PtYl4I+a>7ZsyFM9hTQsqa$5oo~RNx8NtM!GpmVbaJ5#>N~{=6Ym6( za_F^6(mViNJNpzHY^pqaZrt*yTlwr428M<?$pnFmAWxqRx-B(v^%ad$q@WwqJ;=vb z5LXB?@oqOTl}#OR@YaL#!?NxNImP#6r1WAjN62Xx2w(}r=2~$qz^bQi+W`*-sT*oS zm7+OfSC-Z;KmuI;4w8}I&z64eJF%8K$A-JVy%`Z1cll)Y4L?T&3zI(Y0da@AicY$= z9cE<*{IHngb5(nEatGqq^ox6Ak0nx~q^W6oQOQ<bbo<cd(e65JS1)x(N(M<UD)Ssl z&X068>gGOFQqUUf=HF5HnHK5~QRv~jo0K{`Ep@Vo*jz4NL(O?aqnJb<u9L~$xx3L# zTpsDdCE|-V_uB)yES?z^8dUDE(6Nvs#A{9oqq|L)tRmiR%9TbNh;r1ykYN#gk#cL9 zZ<07<dBYnC2spgw$wUzP%xB1*?awd%18j!|p<Jt=QpgBd?UI&-b}WXhVb2ti`U8#n z<r{^8^<+3-aNL~?)|_S_U1!vMDMdGM4;mZ<vS<7d+%C^)^Cfa0XL@AZ%vNy3ZZ}Dw zT><*#cdeO3BQN$+fc{t@gYO9qW`102^F$8cv9`I5c{Gm)s9MA917+5nok8)x9JwhJ zyAN3})5vtZo*b|Xf@20|a(?XltwxAKH3G~S9n5=`+esUMYRrD4DvC&IV$Rwh$7d!> zt%f(_GY1gFSsSc6IjcPDG@vDpG73MAL=y<nU!JS>ZtRT?;6C_+toWt;vg(X`Q>wC5 zz5K~3p*wykx|hnV2Hja8j^q1-RTEP9=gYoRawGCE8ru{%9oaTkYjvOMck537RnhLs z3nGq#Twgw0bm*S6<iYT2(NejNy>GlFcNc)6P1Ru%Z+-o5i71RC6KMKOO7h$*arLlG z!cfztR}_t#GM^rx^r}4(7vuL?ikuSjF!EZ*&#AAsk6+2<_h2{KQ~If_yiED6<uwYO z<?;;7g8~cd=2v_nA$(N$Y*Gvr5Kp+0JK2@~7^*tWhzDkbpfSuDETNgt@6<^Un^9RS zf4C*J-lunnr)6z)X`;nga$5*Wm^%xi%yJS}!hupa%F$b9FQM-xYwe~m=f`LQVo54F z;$#p!A3T&H23a{;`PRhHVe2CU2Gqw9k;}jkZZz}S6gqr}5`OHGf9j?vFd2gskJ}vk zsvSqS8k3jSfz|FI#H(uHEixdwdc^t9#=td40eM+mX%5(s-ys%|ky4R2jzOGWJY%{y z#rj7=viGD&tM*j|)i5WiE|G_*il#ag{>cN7<ay4+OOwrpgTd7W{hH=(XjPGtGy-Vg zx)jY5a$F;zB7Rv`fl5iLv-x^<UeO`xtg;}xC!@ht)dr;Pg=sgZ#gsZhw%4!OrC!<< z!%lPakQu%{pJLaUt4*Re8f57!?DO!In!5Q&r&Qd0_`+^#3kkoAySXeWdl75$UaD%i zB82H5%U>gNpv$%}N)PP`_RyxFG!)ZeC$`%NTYN}O56!Ao7w0w{|I*_u)e1yco*{p= z0DWlvAj`~$5vdsCo|<RlIMwJzG<l~)3;8+VH{6|zYVmMfdZBey_7E>1i5(^G;}0gR zn2%uva*}2G-Un6wk~u<nNQ&}#R}07{)|U8T$)&RK5N3S+O!W;z!7PU_x#6wYepBim z?*f@Sw(<kF2#fO^y%>B}f|mg(lY*UNAFs)!1R--4qx8816>6JkV&B;aEvmO>;u5LP zut|7DQjR%lZygdEVBchK$GaTFN3>+PsuD&eRXqR}_nwUJxO<D#%<;l3Wz4#d4vm}a zCAWeShPCJBTDNQOAUVTN>v*3k+_Jh$2xfGrycFdGp*3}P7bu(h3DTXsgZbZzKwGo* z_G9iZCTKKuV7t3@@!GW-#b8&k-t6*+An>~lc-U8ATPv82j#83z)s+ODF$rBdQR!)9 zD-C+cGy2I5^!bSLeAwPi;RR5u(>SG6aba#y%=zzrGlXPx?8;75LL>c8C*phDn%&6Q zTc(BuUA<0CEH<+_X!JXkB6;-M;9U84-r(zo%`zkCs}HEj!CSf7pH$9!FqYD{n%bjc z$*6#%bX1o=s{X8c@Sxo!=%67sDYSmwS1L1dg{v8J&-50$Firn}DN`>#HR}tIeu?Va z<@Gqvexlp0t#SqpeniwE1$@P2q6C2z^_|8?$oJK~DA&z&w0sT}v<UrB0I0l9m<iZu zzhqP$EXnFLJPI)*Khc3;W@?ArwRi@3>kLL*A?o+%!Bfl^obB3fQ`%nk2R4K#g@6Vb zPD)~KDI4<i(&5uOsRxPPeK)1KO~VZZh==kXp)k7>Z@w_-=6DL2DT?T@U<WWuwAX|s z=mRY8b1NzR`#MV_rPDw}d{XBFF9vYm%@8b2G>3vcdyTxufV?AyA#0089N)8=xkvM4 z5OtVP3ezx{^)0hITySOLrAMmW-w43|{|hfdBQQ<U&_AQwak@VEWEwiE<$A}v8@I2o z+pPD>s{QXnSyu1K2?=xWkbC=g?0k0ORLR~7pL?kKNxFAj&0m)TXl&S_-|y_-5%xI| zvax<01Cadjdn8m}_@Pr}ds$B^7XBVp_yGXfweq8ItbYvqKRK*!??kWi3>hHhLwFD; zTjHN1{c#&KFbHY+?ceYHkFPNX^xCH0gXZqiUgNAKy!-w4_Q~H<<pk_mpjze&R1FO_ zFGXhE6cF64FCfN5L0=yJ_GyJIVLwR*24j}O;&ij{GiGy=nBC9GZ%!CaDDqv4#C>^3 z&h%IjZnm;1QEa>SKSch8RrUyD+sin?`Tl(e3)sz#k;(QV!>ueYu_uk)P}o_hCGLEp zn*1cC@pBOSh92y!L`*Tg*Wdm2UMVG6gS_I+A3y=4B~@^l&Sk0k^&#H_8hQkVL!ZHC zIfpw^RSMK%W4IoMnIR$7a8Xf&@>t1xgg}U$!Xo<(+%&I$rxZ(C%eIj1g%M}l>LeR` z^vW|)KG+PQi}gHk475v-e^J9{E2k`Th(RbvKh47$b+j2YRv}3`!omFFU_AozsI>=s zYpcXc#`UQp`CGDvyC9@Z#HB`jK~-K$b=q{ZyyjQ8*tVOP3s<BQl1rqO+vdx_-GZk) z{dvhGqZzR7DY0z+UG~K>9QFb!a8g9OD$*ROkOSAKf+xnXKE+WKMCp2a+-ua`>_3F+ z;#w-cB_pA^UV-f@%Xe-7TFU{XlS?u;GoX6%1Z#6vdfDp{g5mNbaeG&k%q^(pThfON zUK?%lgQYdpY--Vpc>3NQyuo&`RKqGS|D6pd5+hQ#(eO)PP+=!F4AZ6YUH7*Mg@J}6 z=%?FuJ(T!%Y0Pqy9SRYw=nC2Xp2l)uvAXvt-rM=K80beKp=;0peI@{kZplw@LKsk3 zT29`W^y;bab-5+G9%0~TTs#QaJqUp7fwV^#zF1{|?cp&Po>J>9zbZcc+QQOm)pz3n z$}HmT8c#k}2`n7GoHL4w{I7W%B@mSxL)R@R0gLlMsfC=5Roq<&X&l;;q|m;G4CN1Y z!p5C25Ia%QR!vDF^w6>hi5GruZ9&pGU|bs*4!x7Mt<pYQ*FNW(>00wEyBkkiHyfg5 zj3D-EtW0cr6Fz-ghpU2DzCgrq($Gtj*}{Z-+Dz*0G?A>kZSDNNPqHA>9qyIm*fdUP z0omFN_uSf`!hfLY8st!)p8pdNC{5<=z<v#@GCr+#Ts+9lP)>g)6bSKfs=8X}Dy{Yt zNVO1lJP$Z`itwqNq=px<7v%@I@}Igu7=ed!3QjZA=Fic0`qJ|bDDTfK#zssL;}z13 zh-O=ZgdZ(Cp6UL~9ig)aLWYod{srp=n9E-Z^p+vxcAeIOQFeMLN?8AUxZaOSjQ3jM zPR{EJ1#1JT$#+uIFys&>q&T_S+P11!d&WfCtPeWea76ZWVbh1qO^rS<c|~tfv1?B2 zv!t^(7eHWZcxsjE+sY9{)_Mt$JBXB1khHyH*qH(;;YTnw{hlDIx!;msRuMKpBqbBg z@idxaV6ej{^>+Z3aqlQwR=+_}vpMEz$Ku&-N9Hb1M@Grxz-T*jKSAJD1~RmDBSjRu zzG4gjWdhA{H3q>b+C@Z%?V`v8ZLLSRcnw)LWv{*HbIQ#geai+L8mIppsB}N0b_65F zUep$8hH;RaDBs(4@EHrzZY%a6Zp3&SUwU}gfw?ryew|a#!WACqsdo@Xyc=fCLD?be z)}JO>W?qeZ1mWxgcI+P@(lk{|*B<X}>Xp--ruTAA_A9lzwg4U{!|s>S<-tZclsxXJ zkbu=`B6`;!I@P$v1}QN8khVYV->j71L9B`>qYQMJ*_M$WlYX%NTB{zATGpeN&aeCb z*pZNxkpqC83@f+c()6*1>Hi&enU;Lp3rl<UYJLj*54&v_EF8B!D7^CQ{bPG4NW|9X zzpx*!cyBV32UKtEZxg`r;GtO&nyJw?3WUYxsZ2;Ld=Om_{cxcoP^8@4#-;6F{`k(< zVM)N+3+9rLGwAiq0rznQ--<Dv&U+s9pV<8DDE<Y{-N!?Xs}k6^S2w*r<pWWQUqpGA z1PBBN>-v)Key8LCE{oh*|E05J<T3iLY!W(45m}gKT)xd|R(yz>5YGVAyzU0+tgL<c z#f)OjYwJX{QITFrczt8!K-!w;pheeg3hm<I{GCk-lIENCzQGNOc#3ty%pvNVuFTn| zO&YLJpc5$!x6ZKw0d_C<itd=_G4Uuw@nOut6lr3IJ%^|8=(VYUHz-3<uXSI?HpDs2 zfno^pY>OUOOTPt?ZWfJ#2)M3&@tH<>o@&gU%*E;}J#yF@1!bkb!I$|31H4>l{n!oM z%eMJBY>xQ7>8t1U9*>)j9??=OulJGoY>#t9wc+$+#Ws6f@M21Il7p=nWSp;eA5^3T zgTNKW4W0U0M#&VZ5;m>vH{y!Vl<hl}UEvV@gd$19M*%3{B0(#tO~i^3wh^kkRHMS{ zrNkhBRKkz7|E62}=TgLCoVgC4JiP-qZL9-FX8|5q%-yjSbifa_h^a4I{zNJP6DWbr z)=WEc-MT<s8)Yup&AY4VCZHp704YX8k)3{(|CM(l4fdcy@R0v}Ptg=w>Pre+OvH-@ zlhQ-1F3Y5sLkhN~^<y-uip&o=ZO*!R%uws)`ge;{WR)=v9h1iAGvy(gR!`!}R87&C zO(3!6wj<Q*I_8*ftBH1dGs{b!rkOA+p=kt3_S5K3l}ZnEX7O+*Fs)@@<G(9}qxKy8 zl0X?i;Zx{`lPf3Mw?F&KCO-0DO$b)~p29^C8?h{oZ(#^VMi5NCG-^Vn54<%~(<2VH z#gbxTGm13mAh}5&vx02J+(RBgu|=3JN8a91)97=}zZYC3&v|jfEH5BWZ$d!9Y{G6> zx;`xvb}qBCrtdMki%;dMxiTf{ldt63cv2!r`pB%wEDcI~joNx`c?=xvBiU1`ZKzR7 z;j_j)f|1E%*g!xRPwSHiiBMyG;9OctRtNa)YOO}#1w_Jzx@}{Hnfe=b871ozgWH?a zM}pKZ$r%|hQWdTS9oM<N`Q&ucMwwG!QeJ!&gJGgaW0}R{WwHB;Z~DVQg|7g+29PpP z?l?Ztydc)?_yJE>Z{M$-OugWRUuIxf-tP#@zp`ytLxlx&MsN5<P8*Z=kH{^TF;a@C z#ZDfN+E)wzg`246aNK;d+NOe}IF}zRY)YxdSYx+}paRx>WG4qXcuP>605@)w4a^b1 ziGUe!924fpJ6ROU0k*5Y?Z-Lb1GCO+WZL&$t)jykO`M!`lp^doa^6byx6Q_jvX}?B z*P#?A!d@nEf8o>`C*mwb3;{75S2gtCC6m3w!ZFABI$}Mp-Ux?aZCydY-og{S+Aud} zcV~JEiTZLzSz{zxmK54e`Q{*&u7tRn0Pbw0E$YeCc{eJG4(gpu16q9zC^qY7sfi5; zW70sfhD|tUn7sox$0qSC&X#gEMrVGXRMxox&F>X<Y;Y-*_n`4!D6lp=DF2vg!N60i zh1qU@gwBQLXnzv`C_5HojZW|v(WMQScKpzam|8{_K{?HzIeMRqK9q#n?Wl}l-XkRs zj&S#`bz<`68GVPV$nd4BMqRW6a81tokDC{1XJ1~tef6e#=UZqVkxRh?_ET1`VK#O4 zwpxKa3l*~^X(|+P<$3A9&u*4iu)@G}TYgJbLetRbi;d6Mg<fHyv5-Q5w_qQ>VMXx- zC<s*ApT}!H(57>>-ao&h`cxi>-uU9WuA|(54OFRTn!}5~thPaM6Aol)j;66~ge9Uw zeuo3I4;HQetbX!c>i$F4pP&lh9Oz-<05$q2K>kdZkLrETrd%#Xgrc>BR(=91X)bx{ zV3DimSeOd5u!AfuK>0QtqD1-$9IT(CpR($YIgA%_*34;MpA``X2);5Mu2v&bN!pcH zpM|36%55)`ups#eByGQkwGKN~ic|2FN?yL0YM*7Tg)Q{n6pP(2+K>GMh7(FmP4sE# zvz$Xy7oGq7-lKQ(9WherJxMT6Y(>6G=J|?ctapuQS{Nc$U#v4Om4|M(mN^KO)I{ll z!2uh~Rg>%yC|T`8NguHnqFbby_%cd?(Vx+7vicYz1|i7?Nvx?s>3L>yEUf8iULAFY zDJiT3b!C-$U)`kVzRL}$745Wr;iF<R@^2lYNR6dbVhLCLz^9);&Xk^`wGs1k*gWei zQw>!~x97chQzS>@c~>6MR;3riPajfyjT@&J-m>5dptmknDo!%R+-qka#t_LXB|D%9 z@h)L<uE)ivvUtk=BBQ6#0Oy%R`0eO?VIC*xY1j>hf6nCrnAt%`x(iEZ=!<U(<~VS> z7+yUmqo7%%k~5rf)uUKRU(VPKN3b}68Jnp&O*bQ43Eh6r*5JW$N#}hO;43xk{R<XK z)Mx;T3rhmCrx_9VGcA>5UayWNAmGF6|3xqsK5TU;Us~PQlBz}b?%1;S_ay&f`x9Vy zzWuyNMq~sba6v%;8-6jCrB%61d`;z8tRsPC$02HZvUn^hKRO7lpuHv4fD-=g+RKRB zi2IYS%Firn4*dkKf$ga%yl6k}MKJmkk7G+1+E2kr>sE`TTg$|9=2-}PdL&eLcc49F z8^bmQnpq^ehyqu_rBae`Ody|>!qu_ShLj}=oEe70+q*r${&~+H<*cK`uyvLU?hx1+ z=+{h?8={61&gi@S4u*@d3+4ki6A@*n1Z^e^_ubJNW*2I-hT=BXNZ5lA`Y$lO;Q~U{ z?S1H^8q-2{9@n-wwG!jlkLZ0h*$!O~kJ>&@tEFrrr=|I(@Lu4&oqG?>5}<~@gk|%8 z$j*4z`r0z12k+!E=GGpYJTkslsK=iIH<C95`~(P(;9|QmV+-Haei5%YS>BJnjeeU% zFlMwiA6fc~)~)9H-CPw`4S4A;TNxFap!+~P$J?JCJR2Y#6%VeIxG5Fu4d<T^f2{m_ z>X-BuNQ>^tOu}j3_2vzv9pynmnFpzh!K~4SLf8Ao=C%P3N#``y`K#oGQR@_Fk6J#R z0vTa0k8N15+1r>DfK`yqgUV|MKPz}|SCRB2=qbxJP_90?E)TS=l>ANS2`C-!J0<}4 z&wjKtbE*~Z8N116)-tCCiyHAIVdj*UjgaW4Z}aq>9O8i6T+4g&dM1d@ohT0n8P6rU zv?j=GqGt^cbZs$UEUMb&qh^R%G1Fm?N8Qlh3BHDcfy6Mw(6FxEw9ImC7Y|J>u1>vh z{x=YEjnD^9l4ET0b++NEjHX5sJk%iH-)$D-Xmuq&YP#94i)F>71)2tzdy4CfU7bhs zzv4fWb3DSG0CFTKeX?9c^O>BDqTjKiqW#t{`;sW$?Z;mU{8{{SV?>s8*zjGGwZd3f z;Q?Hl$MGv_n@6J!nwFe}^5-XzzMqGNqMTmU?z#4x+o<DEbG5u3t6Q2hd!+#}$mDI3 z!ZoB$PIhuz4kiITfsg48-jQi%Fe*MydZpkzO1+P9%BwO5DPegVNHSYy+AhTAm^nt~ zYovBz*cxVFeW;$ZLSFreyDgrwt*I>+LX(ZFSYd+BH=hH0oe(`z`|I)z1%ayG*bbG3 zxNB#>+!^x93vJ<`jL8cktm>+#(NR0#Ve@_OQuGAf0=X*q@c?fR1(pW5!tM1|a>JQA zMkNbJ0)?N66&-n5Lc@$pMUH^P{A>8{DEX8nJ#8>60`l_Zqx!tS4a$3Wpux|bcI3;` zWhF<D4l{xGd>yMzhW+RcY){)2QIPdFVX;VN{tSRj3ZgYhC*J((A|xri6B_;KU1iIW zm6g>rYd+FDPol<{qZ7gyA^D;tqp2fJxPiO!6F~2$q@!?X7%uDC{)D%83<S*L5-nJ3 z&%B}rUc_7s4Vc12$M~_#1pM9L-rJkR+`jUb4?ykPg@qc<2MGH}QFi(1W|>NxY3?Jf z(aFmxdg~{+li)TcB(L><@v0QjHVSr7z>xDe_IHpsF9zox;qbRG>_1<Muiax1qYfsx z9_p*)7_~GTX)5o;`(W%p8$S7(Ifi)h$wb4m2Ib`~o#YyXYL3A*&1uRcu1ks*v^wJ@ zoFy8;mb{jSu}7?0&K)~RCpP2=i5NSIAdkt?1n;;+*~0<2vS+^atp;K-uMUMq^Z0Sw z!Rqa6+aTNEEt5*^ZZFl0GS+~>@?OjL@0xgDvt(}~ORtF-9*}*PDDaN<R?4H>st-=~ zjl&~@n`-Uq1@dmTfrC@e!WpWD=V~MM2lL((oQ9s==Lj-3j!ADYuadFvTNwd=ltH_0 zNfD`b%5@bzTi<1_=%2R}CH@kx`IhA^&4QY_T}a|3pHaw|1;gDY5$Xr{8%Wz+5mCFJ z{;)gw3#DvwkF5!v8+1#$XC*2n&$2m81oBusBaVaK#A;9>JG_XsGf9T?eS_*7VJ&cc z{a}2K={@ALyna@4`=8=V&2o2{>-O}yZFR=3a(h$N<s+T0JgUn;b|od$t)pb-DVcp2 zyO!w$SM->C_*w5#K@AtQ1AUGznT4-gg8J#^(qV@Rl48X61|Cgb2loTthf((?EW<Oz znjpoMM$9mF_O&QH+1CcyM(7`PwItti+l8&e`OB}ngR@%C99+p-l%V}^jm@h-NeK(Z znV2-#B<@Uzc})~6TTO_q;LZE>i$g=oO|Ht+B12G>czU0>vD&=Co`;gh?#(o!Ke#rN z>NIIG^Xo5EX;gLB>yqG{wsOL$QFzO`SX`FHZG4ZPX8})0SRKier~-JKBW}E{sZ1Ma zqtpbhb-G!)pC-+9z6UG4FVr8n`Ho2-u6Q^{&j2`GxyP>A?2*<HjZ%1=wm+_m5B{8H zOxv@Z1bRuRVA_c+>Tp{lQ>7J2GF~a0hK)tZm=E%|A9dTcY(<{Yu&aOA^Q)5IZx)#l zLr#|mxpsc=t+$AiO5?%*a#wz_H9zm~e>XiwZ{IkvPpR`)c}S;N?T)5PYS-;7Ejc1y zlHWUc`EhV-e5F7ct{p8lW};0pw;MIoa(`{yh$)2ipF1Kb?Gv1?hGibkgGWsijpc>B z&J^Kl)-UEOoVJ)xqz=*39Ala+!Lw+FBHDFNqptkn?OqVOC161eTqbf!T*0l==2dj{ z_WW9gak;U9SI}vlEKE)sE&iYYA}#814W~0nS>nje;WGvg&?FG=D_>C8T(<Inhs3D| ze19R6Wg3>ri5J_S<n82Xo!5=d&&Qfu^9IBT-SAqN9fBP8e61zP>kgXfZy}~R(gv>~ zWSN{qBwp2q*PXn)U|<#@jZvCCu?I339!Bc^)7;AkZS6tdw;Q=!E$tAv2VtXlJzD_g zgH-DI6ECO;->Ti3+SU!FI~143+g0Zh&dCWg=AIiR@I=yWOp@RpybE6AVW2gLoLjgs zg{D}9jWr362P=B4q|3hk@gU(J6xj-mQ%wyMV@)`3Z!9Q^lX`OgFj{S*4eUv$P?}i* z#k(Q>NKtLPULQh-@eI57c_mV@#ZwzMmY3g_bkhWNZCS~&TS~lg1#C2<QY&Z$x#kU` zeNq!(xte->qVA{yJ<FGie`z+XBqMtZIEJ`pAUc0p2?q84#OhP}AdUw-``La@VI}H% zV9@Hf<DDD~5(NZl<GacuYu2B;_FE*+U3*~~2s)Ac<krC%&4N=)tn`Rh>}BSvbR~td z={O_2pTkY}9WDmWrHhUScY+ddVv`Zf9HY44A_tNJHF*)Ngm5j)H7C}zu~ojj<|$~| z{{)u&XB@r70`iX!l^U9RA<oX+F_m;|<CbfTuM2Vvfvj;+_iB*RNq@qnZuh1})5=Uv z@*f;&`psDCe;*)bF#`k0ZYY9OeSml4K!JzO_}F{58zXa!YPoq0>PlB8egN?6w;}m3 zP$ZH1c-Ptx%BgOwZeWkNgSH-O+<iL3*v;g!OZ3yKHO%lJQd?+EXsGCk$O|eft*lMr z{>YKraMSS8kqWeI_(&0cU6CYpKZQWkT%b#cTHK`pG|?er0&c9G4luGLQykOu1R%Xd zz@?yL3shKJ(r-HBMZH-kR)9Y<Emi}crEo{@Kr?||Q`YFp=H*NZC@^(ocj0jicnDE9 z_!VYh1P<?&b)-~#_ESjW684As(>*0@1+V21W3@hxc{Z*=B5%5`XJ8ziL4n43#^g6X z!gjsFICRq0nFRMN1=-_<VnFF4R~JKgDE1^av0oJ4!`-D5mRxxik008tQQR%xXv|24 zrMsI-ZdpNKqwBK5rH&5f0q+3prYL42lr3ub+MQ;d+C6+SF%7;?2REcaIxcyo)UBf6 zh18{*>>!ab3TP-Ku@r6XYc>kZs>^AiD2M;W@_yI=IaJ;YcVS7~+8Osy(TKn9@b5Io zJkRpBARX`IIK`TaZyxRW^R|yiAO8t(_k32&{cz}az7b1S(-}K$afU|XlVXz=K;LFP zTr?G>Ub{*<+8n*%hB_W{uhEy5PXvNW9j)iX;$FAcqx;X<Si|B1;&E-X`dvO&_&Z7g zxq<bzc`5b9RP~|eD;H0HxZ@fcQ0Z0W&uVOY7Nz5P@y;fDSz|1!<(VsN7->7MCPUeQ z8cbP66q?8~&MzLfeZqst#=i=+iuZK88iSU(MULWk+7v7`G#mxuUP4jnSO2~x6!0J< z)D7Y8uy3ho2GnVNcx6lzr0{D2vF>w+>K5!VzM?mITPS1hzgN(^Y+)bU=+(3TV*mfD z1c9KaYlE`jf%#nm4U<~KKXoCYACsbFW}vpRmy0_GIfZn8?RSgymelL0HN*EwD6fA& zNIM;&SkhL5$c)LdSzjCb=&Kv#J-V=~ml@;=dSN0pir#&=T4??MwOsy6I^{?rM4<sl zdJsMR$mHnq)Svbid;iP&Y_y5AT)Cj&C$MY7UH`7O#@mwYW=gAUN)48=l`Gjx1xM~Y zK;hnki*NSU$izdF!L2p84Hu-mCGHU)$!D4L<}Urx&|feA!5IBp<)n$o5{nehx1`zQ zI{|F~fCzIhf5ALo5RJrjlxl-*9h{7r%=Lt{6l$RXhR73;XQHyM(`n(RTeT)d-D`~Z zC#42%Qf>Z~MzQqm-~IFdh-m(?D2xhdFPwuX{}(pLfPc-uztTaZ3vebwrjl9@Jp<D9 zR!jewuMf_BXG7vf<8c8?EuSX=U@c2(&Ovdk5ijH9S#eaVU~kjy<M+jj)~f}7b(=p^ z?zYRLiZga9O}$X{)U*GP2=NQe>84B3+cEXP)J3!ApFquP-&M!Y<1+J~GI}_i6ETt# zEHeWd#{`=<sbX_I3z$nEfY5M_Q-r__$7kxQp`M0mW@Kb?6W*I}BVacaCk4W(ovyLf zUHN{6pXZfbmR*+1U`RQu9uE8V-tKYvhVQpN&F5Y*KJ=yf&FFullkwO5Hh-l51cLu} z_fXhKgz)by>-+y4NbK76Ws7GOa**)j*!Whan$5jib?Oj>UP5U2`xnE0afk)JAc*h9 z@#wf<YHhqzB4cbFeS*Ber{LYN)?>41`-13=r=Ia!^yG^(%<EDh=|ey`MGi!UcAS*| z2^={4-6?wpDch&_MD?HMl@|b57L&9?*0IOr4S%hBdykZ_x3`$Y{@-s>rM(e@WHLJ| zxI)XFTrSm`a=8VBe0%a!_fMeT0%@kaoptyxCgm?^DzSV+bH3q?KPD*nS(38T*oOC% zZ=;Ym#u7dM&kvoxjjG1o`b6cyvIF4MPvsk)SHDg|fMe+obUNLm>Smn<$CAxZk=Xwa z{>{*~s0;g6m)rfnxvMQYx#iz%-sG!W-f0itW+%20Q9C5szi#gTaq{&=(|-e>Oq1M- z6Qo`rd)+Sl(SBX<lq<a!noa{_2zR;D;<uUWoLR3-AszqK;aDCz>DIm7E`{N7$J}e~ zozR?kZhFe$oTYQa`2R0Yf)VMQU_;Z0U#`GkaJ>_ASDOc}d2ZL(FZ+0-^v5GwF3pSP znI+v-@ueArptoYUk1}U3fDL`E-fJO)7UWOtr^pL4XLK1U8)h+{meqE%UC%(*^a*(u z6c4FMs?@fAqK?=uBS~$~UE;4WO14oadYkOhT$t8Mo}Q`Jyv`5FSniG%Ppb(@wQTV= zuxz7rhLO_^*qY{x9+Y(=FmJ1h(I4w#ha>L(qpZReZ~|l8qrc9LcU?yIMEA+@!&)y_ zJ>GctuBFsYeQ8L_LU%z)=`sSbhM+#{R*hM3wRcTPaokGE0bh!)I}}f$!%~JjZQ89; z1i7U@#L~OZ)+<~1>tx}q6<#E{WV|otvD362!$D=!JZCA$CzLu>{o7g4<y(v1pn;nH zU<t%6lPsiWaHpvAO#|h3KLN)1fUcDW(v=d3@2!{}=HFn|D{HzH6`cF5+Sm`ZH5|WI z`Ruy3yg4>a9YSVSt@hW=ij@h}QIa2qIrBr$Uat)uIkHLdn(eKe%=z7cM~#oi%XdBd z4?jy~Xl>h7Zk;gpbTa+h#{B7cf>IGA{H;bbZ}tpvafZ9aeB}YJiR^nOUjTsOA2S>* zLhqk=BXMmBHmvXh9xP#>|Dst59I<VJda9#Vuf8g0oJ(;IY2u>TgO2^@Do{GF;Lce? z=OUL)^@s@AxF}Ew>(}XehKhlBL)Fw5-=~rI-soy6qBHY_&bSduOtMC=v`nA_tDCtN zBJN1X%*Zl6>M8LEaP)H_Lz!i<{n5dP?ppn1j3Sm^iMxCD2N{7u0<(R8{gVALTWSJq zWs$Z?+H>L`1Eua{O^0eC0yasG=&>osq1d<#Uhj$u3>m~rhY~AWD1LV|qPXWSi%VK) zGStVzcn__Vt}Z#}Q3I4dTPdHRv(5GdN~?@mUO3x*l_1d?iS!lY#pOT&%cHa{a-gHs z-K8s<bLeK&2s{rxKELIDsHlC4PW0E`NQI%e4^5eGkqpFwMyr2M`ka9JAx!^+1Ebe^ z{*T|0$AZ&ozt>lP_W36(YONNaQxe9jR^3plA)O99!MR$sh}nV=T^{=)m_*%D!H_^V zCZS@y=n&_OSR{bHBW;%}I6nyQN3bUDV|NCXk7$p#o+gU3#&|O@VYQgDP%iW%Jgld` zA-H@-MDAwR3#R#g=7R&G`oN3+!=l!EH6GuUcTVt-@@?A0BZFH!3c9d8BC6{5pkn?8 z10sHIJ`8vWvg!jZ-Z1BMlfLvi0AC2Z*Ce&iIp1|)qg~&R`GqxtPF)ORsb$@T_hL!0 zACEYEKH2^~Zdrz5*>E}0`Th8wio$~{#};ZHuh;zY-0Y^q|H&t_XS8{q?xDZ(>HiKc zUWEig*g<k+nP0w#P+I;3pko+6k1&MT$gx{^ji_4iM|Y95h2>P%X;$_d5IU5yxS<C% zAa1%{`pwq2*|nP9CNJRl2N*RJn^NTws!=h)RP_!($?-BSF>~-9>_%U4W*SPaMugt$ zM*3=vDIU>Q-XZ2)h$@-MBVh=$?wrq*y*qaW5jI`#nx?2U>SU`YnILNGwAeq?dr%aF zcT^a)q-W8<T&6wbA2sy8tH`Mih_Azg#mzV=k7NH(+Oq^&mmEY`OT8Zq4wh9a9$?0X ze0PbTfa-&5Q!Eyq^P3(-$PS>$4!|ihAe=^-*@FH7uZ_?6w9BIEva4ZDlvtsd!LX@$ z%Q>E`jmuie(*kSFFhOvc0^9q`leJC(Yu6m~(g!_)Hc2)B=21`xUD{plj>G2W5FAXV zq8**5k;|(sv;OL!t;F}UE>YwC7^zL1mPMz6&;M4WhiipC@i&8*?+Po5h#|-y=Ks;w zZ-&>DqW{{WjxKCY*B(AQ?Hkv{7h9^51mcqGFL->R@@3c?#@Ixd^_X>vrMmOb;XEv+ zLi)?55d3KR?n~;(58R1dJnM@2wje2uO@Mt{AduG2W4uoec~P+bw*Bza*I3y|FQ=xf zcXiA#9=E2`(i>3<Uj}A@t}?f=zz0vS!!^yH=KS6^F2erQsXrVqtG@Z@_pE<dKu&B( zu%EX!B>rJ>e$2i5pES27B)wxYldO*Ryz_rQbl|4OoBtOMZ}+G!UhG}H-t#{4{piJ; zrf;n7|F=F|mfwxR1IPX}FE_dgsSZDmS{#<c3g%A|V$z0N?()4=u6)d!&!Nl~i%~XS zfunI`W^d9TFBFfBOT!)wZnciZr2n;-&8lHE02Ba9TKzcstNPl;n-ju{a>4++uy={G zmCim#tzWb36<2yZU|DX#Uh=3KP>zT+e4>4NTH`id!i|D@uQTxh1P}crGPmW>+i4am z>v*f~JM5;frcv%?r+~eDc>)>`a1|E5B%KF_5KK50Keh2oB;-H&Je^Et=9357GTs9? z1pLS5ZvooqhKaQk;Fxh4NvE`qlalFDPg0zvP+U(LM16ft7BO6=7<pIHYrC+~*z8(g z*#=>;WBTpnZn}PO8{@&i8OK1bZ)Kygnj>xlA9n{yQ9rG_C1sjU(`>Ydj2p>g3mlsI zg5))R0;}Zt?|`It;vHFCOWg;3@ne&FJsogw;TfV+Vi|)4cN-PzxgxWrB>)`UTW8Bt z);JVJd4VBLw?=s-cM+q6S@*!!&@rUZu05#Y_3`W%JY;4I2`5(HsPZi$4ao=N8D?H_ z4{T*lHG9|$Qrg#-rYG?jkQ-40SIY*c02`=Clx7CoX1fuHLFL(#maE&+bh%f{OM_CD z-I}T>L|7(13I&MYOSR%xN5f^srdGGIegc<%i!<3%g&J{7mkDKM!!tIcl)0p88hDv5 zCz)RTk9^fsM!iM*=(AIo$>~8+x6Eu?-i^6j%)fyR4pqizGH0Fd8>g#Lk~Q1XL?sU5 zdeU&wHMi903y2rZ-!B?Iw{81Ax7c;OauIXy{-pq<qm?hU)DP<u`tJ5)@c2<lp5vW> zNo}XVTeELq`N=_TxfvkQ9{aiE+`T3<?x5=R8i!#c<qD=ny(yF|zYR!*K6X9j5lFN= zmyVD=CeANR>u-67`5Sk|Khc~j$lp>c6f1)wGl1)z+iI{o4a0nB&e_|!eLq&OAHM=n zesrcG00rHc8m-Q=KU&yOwz(uTTx6`pgWzjR$;w;GI5RJH+XpCHilL(b@0yK1dML1- zl}ii9mJIfh@d=QSQEk|6lXyWKFM}q8+JvA(gE(2OPveJmKb;Hq7&%UK4OCJA1(I26 zHtZ8aR&d*$)TVWybXwppA?~YK65dAJtO)R@#|W96OZ+@UL1>x6PW_1}dGZL5IIPh7 z`cU^yTUYUcVX?4{3Js^}XH4RAw)p!TmZGp+1WUntx88EY>Ves5HCAD8teZ`NNq~%n z^*2qyqq*D`7Q!-st2fxpD@Bgd>d&D=dcdw&7b%Xq=hC-KTZt53ebUjIi+w<oX&b9W zTi75%pC4^l;Rqsj3emwspC13U=_@0gg^wRVL!vBB3ZUdh`lBD3pPrjtak%u=`OWyA z!-WS{jy<mVPfvP$Fg;QOJ~pUF>`;OM!3e9{|Mj*1HUQRPLUbHP#sGXX<zv69Kpi>R zAgunj%I*;3!#IR71_|iwF~eRE7U?Jzb|$*LnYZvux?F+kCW^w5gB--zvczpk?X_VI zk+Lz?*?a(&rg2M@3YvP~9@!o^+P8b;Fie;O2F>78!C-H#Wy5oJkI}fJ8Y|K@^40I| zwf|6cebU6)x=eHx?en~JWnF9N(?50o2h!&wSH|_-Rk`;QBX`C)4VD!O%VL-%-CLV; z3k?r%UP#Jxsc!fQu%N7sPIfh*Fr!h}`VhU{#=7VN*{H$~>HBKe`B!Q7av2-M@-ai1 z)EM(s)7_I1KApR}as{8xh{-%mgS%C?+K4<d62|(UL)a|Yv(e*k9i1Y^m+DniTvEq% z70&eT@!(@5j<}q*nVkxXPJ?%K8vC!Qw6PB&T_zfA_uDIc78~mc07O%wzvmc-dr`gs zEy@2u*8~ACBqQ!e;XN*e*v1v#c+jFjZ1mPQ=!8)3NPLyAGqLUX9yxF<=idZ4HRFG< z_nu)<C0*NSH?e^x=bUqDa)u`790Vk1k*ElY<Rm!@2!domLCINi&RH@DN{~z=2ne3W z869WFnfH0W=lnS5T&LMr@9Nscy;t3}YE{@(YXemP7G-TY?=3sDCTM%$TOHMO2yE{; z;=xCHmj^)*PViSib}MxuO$^QwVN6sBkEEO-j@&#8%_zd>fC!SQUL|qbWOk8t8MZze zd?tT#!EHf~1;K@$cZ&2+qbI}e%2X86E7M?D-j@Cfn1{SsSGN3w36?13Td~9nSY>7j zAcVx=YHe=11>=<RAasgBKTtDa(8AYx1qkeg6t3$D?;2hCYgP6JL`w(CWQTGhKWbWl zmTx0L9&%dT-X&+9z0Wu?N4-)0G(j*l%y^%6p1m~$A1acgS?C~Zf7nRmBKDUi(jB5n z3kZbDA&ErEz@JQBu7qR{<@6P)IAv3h(qPd*37t^y&q+);oT}$73dVW-dk~8hAB5-g z;o-+RfG%DUTST4&>E?)nH{V!R^s)WVKkTY-6W>x2@#U<j<g=(b{4$Mw9uL-4*p23w ze=Z?FNKtb+>u5tM%jYCQX_C8mhUPq<GeoFlP#eQ}ss*0HDBwLkr22`<Y{?M7ZKva~ zC4c+NmB(wC{d6S48-9q!GbHYT^|aNp$B)S9GeYaKLyV*&gY{`|l%oV4#J8fRp^iC3 zTPw9@8o1#VzTXOHDG?_KWn?1BR-s7L(kFX|@^m0ZiQyp=kR=l!g#t=?Da6$uZ#So9 zh`?n~%%)LD;TNcf?|>z#5go3p#YG;r{W%Pj``kpb00p@ZQ$srgQw@=|H1e<`lwJ>j z!f_mNBrn%Zdn2o?M1)BF1{*FA0wIa}?1oA{)oY)m$&{rop8kOU=+^s*zUP1bS@0Pd z%8T;rYkwqV>ov+Eei=XVFF?<eRNL;V2Mh`Ws$y;mJou^VH#0A~(i2*gmgLDqK4I_1 zy91;wbwWjvR(p;I%ce^RemWzYPlG{rDV0Sm;?6fY_Q@t9_OAEH)uxPAl4Yx0QF4HT zqwVv@g9H>V(&cpqm?4B2a2NjBgrRK=xM||k$ub|+fULJs1FEb=WgXY5XvapR4H+wF zfov|>ZclML!Jk-U33XO;u^h3Id3cGJB5|G708NqYbWjKK$58_ArFf{>&+~ya9!T<P z<h)Q53lyq@QTYlZKP|ta^Dh#-0;wb{ozlQ_G{>37Afy0lSpe3|XP@LR+#rNa$5l$n z?0z6&T|29`FS!3qpBo>{!Q148L&cFj_Z83)AhoAUxrw<wO@TzP#>qAD+u&{Eqy7PW z;iIxEoz_j7H$$*wTptH!6Z!RO4$Z+g!<`>KqXuYUMCU>2@`eIIGZn6H-crGtfz<V1 z$&(tpaT~}<tGzq%UqsVB7}Ls7*F+Vw@=wMJcRY-OA%YM9oL>Rx&t!sJeW27A?{j2A z(Fs_z{+A~_vS@@rN33g4f(7EU?9b(4NWH^e04@h?ehG8{aU?_0Q+WeBDo3MP3Uq$E zg=n%+`K~N(PT%qnRgAERhN?#?K>`c0ZZF}lTMpzS#&Q`exkVNN5=d4uys&J0uQU*Y z5>8gjqG)RWVJ1$MKXrp%e((dfcG&ddHb`Y`Wtt*rwQztqrFn)Zxh@7l=OtA_yCq5- zwu5*l24%93R`}wICO`P1{54<(Q~NgiA(zeQSk*e17s=wCo7y-S6RL0kFd6mEfl?Tr zASG+i5<Yp9p5m#95JOr^k4h@|^l{`H*IpGOs1y!jY-D}7OM%7>K$VACli#<|QunB% z&T9nI3E%1KvC;xa1y|f0+4cNY<I6BUdr&a2)$4I0kUf}8{)k7~ky?r0G6`mHWEOC~ zMCg%n^aZ(^4lgrBO5r#R?pg?8y^Tx~$orlqzo=_dzQsa?xL7_~IzmvirKH4OH?Kgy z?vY4|zV+r{Yh<w-W2Uy*iU|rD(;Pu_Id&0Bo#P9#Hb=mGu;WsgfLOQ@5*K@AzM3M0 zBGeTP^X7ye!M#AORylng4TSR4y?gR<7J-Mr)$Lh8J7y_P5KuW-fUjM(BAR9Xf}rI` zR{;Ln)3nyNHbp!}y>H>}K>SY;$X6rNq%Dsk-ph3dM1~yEJ<#T<M^airn7P%Pz+P%& z;kyF5kIp-n6gP-?-<zyR8WGD156OxZVE#fonskhBQ>Orn-3&L9P4^9&Rt?lbNpTNJ zsVZP7e>OXWm;%ZdPLTgRo>LVgH^e?fGTu3hLR2rm+|_dW11nX$7_?`Vs3?=bF0SaN z!$>@`h6l^}0a3L`M?!8Wk|mCfJsm@l?yFVZNpuh4))^WMb!oH?F}d6O(eh}(Ft-Fl zEEJhsZ1PsrP<+EihjBsx0SAsOC9SDO&k5_dXDvTQZ%79@`Na`x1=1;OoMQK+UWSx< zbFDP`-%5r1L&dXxB41#-MP)29Hi;uz7Wbh5DJq+n6d4O=lSek(C9qgpyIt~Dgy=K( z0<DlVF2<Kv1l?4G&LkW+j|2F^@(V+PxjhWUX$2JJ!l!PH@Qq`sFv#dWHX0=cSq02k zMfqwQ4ji4Akx6Nx3Of+=N^H7~KW^u~9YgjdhAl9EEay%o<t;Uf5Dyvrm+LqrX~u=Z zZ5kD*dN?h#NCvWVIQJDZv5nDu4_CAK*mLNyHw;TGE9Fe^i*65+wOhTQ2pzSF4*z*g zk94r2@{=*0nj&k2!`@qhw($bAV2h$NY{O8%<nJB$y0m`b06Rvwcbu<)Q3O@^8;8!$ zANxox@4(j=4L+*F8;#w_)Y3<mhQ8Jv{N`l!D_|4Ic<uT4$8<s~T3vJ-QD|7b_B?RV zfRd+;o}uMJQ!TL>{-&!j>T~$kG&%pxxJ%rxfLy6##jEiD7sNVtrtn>2{K#b>c?gg5 zK!T#%2kVf8)52;yz?~zDfJY{3&*W(ML*?Yv49jYpgiNVpJ^?>MJcun-5@Td|&9t`d zX3T(2jRxpcPYmTlbPZ6Vg#~ldY#_)6FWlhtMwqz=6Fml@qZ&VXV-N5CNt$23RN}gG z+>Fc%`Y;6&Vq271_|So@qM2VRiOwD*I6qGB#rFydjF?;vDHQTKN^gIRP-0@N7P#o3 zh<BHHWZ0N4JxXYt84a)+9uAm`Xy?xl2|Ji1ARv1MZ!qxIV~IonY9ZDNkNlYNtQ@3O z6z^Sz9^%Pko1$+%Fi9A8eO2juFJrr8+0^cQTj;G(bHmW5>F<$1eO+Xr{5xFG7=tUy zVsnUJB}q3=v^B}C`As!CdJKjkc=2+>)hCKjIc-J)M1;q{9AI^V(~XwsauF~6P$5*r z3~mdu`xH!bMAsg4V>s~y*S?Tox+)X25D-Xv8$#MzDgYsS&!LaxC|i}Ci%g#&LmeOu zur|Nh#`!wWDB6lHn|vA#{(|hFcud=S6iCR{cnDk{<mhz6wFrlsN6pK0f<^3x2^9IW zY$_Vo&)V3++DYTJWOM0R4C)bm90SMOZ@hl2N|>&E9G>o@ZpzjpDr=}L8#IM2A!&JZ zF9zUvJ3XZOa9zau?ZI_x>|X(YEGy<@`nXG8g6Y$<6XN--TjjQ&aY~922o2zl<^32E z17`U11rpyoo)z4g@s?zRdr3=p#(gS@AHj|hjUg@RJPNY$h9a$e!XW?<@)WQbg|WCr zvRWuPv1n>`d|>Xlgx8Df631m_QpfU`&nFuu3&!~hsCT#%L$7R871H||P!G;=_k547 zhzwW-=gY@@fDZd)$%Y_mxxR$Gi`Yrgig{a>TD!?~w<#y?DVAEUoQezy4L}4;+uFg0 zV7!547^bo=#V3pf6;TL9Vyl7$Ac+L^x!XTA;O_<8s}6k6Y}!o+Eyl{yxd5+<@P>h2 z(PVuE1pPk8MbXaEfI;q5d_5*CYhHk<M{&2NIHG6QhC8qVEg>lF(6ValX6pCweFrI! z22Ru?z7JO$?e0>*0F#tQt2D&{*wY1y=oQYl$y>>2=)Cz2jB;<{k#vI_+|QJ+`5hzv zQN7@El3mX{6BVqG#IYP3>#ZSo41#K?XUz2*Ur;g91)3CYZV4$WH;Af_jl0Aqd3a>x z<u6h){T?Z6RMZ*-K;)K&`$>)D>lPa!*%!BNI*f(=HAoGWCxL?G9UlD7JC45PN(64A zbS|mvdp%RL`l1$`=*Uu?Hq{`U-JpK3`pwT#^_f$FfZ$mq-1M@rf+fh3ztT{TYU^<I zg9-#hW2ln|!|13A5+)zc<4%;u%mt$Ucu>IsA6aJ!**;*B(~}lsJT$KQd1zE=o^fX& zA(())RMU{8WAt68AbYNE>p&lAbBIX)Ymm?lbdotO)(>>6Q$Q1TtUyB&{D7okt@ZL_ zd-YrqoG7zO{ReO8&PB5l9lOH93iioD$bwjQb?W*#O9Py6Fj6X=3TLG!0p&NYZFcCg zI#6!)wzc$ixs^*E;&*D|ip%}^1fT(s$pAr<f4>4x2L*t%{J$wC{z`{4k8uczC6}xP z=!H5hEdmW10RpBoS~Oi~YtZ9v;2jGKpJ<#?H2oMmPy-_fSBwDNKPap_dEDL*?p(Sg zkr0LO8Lpl@Mt11E61;-`K*tx4v>*rwav1@lsWBFJ7-jXQB=OmlNh7U303w(`2y~A) zY3nEHjBvMDL@?<9V47n6h@Q}BTcuzPcM^?&SBQxL5=e5v?gF@h$WXmCl@a0m8XVg5 zcx)&Wwc)FB2IquSQAIryM`h+|eSfkSO@ehzjJ<10?d!ad;oKe35Bo!bv}BR+S*yB8 zE8BQ`VIz{N26?Qu8K_&34Sd{Ot&PtM1Q+{n{-1P_fA3R2zl|4wj!qUNA(eyNZ9%C! zFv1OT=SW}fYo<m_pyafOvw^&NRz+V!ug{Ux5yg?r0NC*5OIpHCRxC_c_us^X3E`x2 z*~<6cy>Y~3WSjD*!v=*9yYxtZ9(z<XU#++5M)t`ni|*|+8Cr%_e`*`5)lEP>lfDdk z!Oezh6${NL=c!EF&*1NxT;}tmcK!+=8LyzyMzI#J7jS*RIE0AU=#O0MYLS*h*JcNC z@I&Xhv_x{(2V`+m-1QlmtQUg&%RWbBbjX?fZ3)RtZ_QUgwA%?WlSA3~#zG7zQf!^@ zO=u|hITyZ-u{@Rxpv$J}0b0>{9l3~_KMHs|*c(7w2x@C3$q-_Oow(Q11g6eBl%oiR zyF40&?_(WeiU>y1-x4Z3>YVo<07kaAv@Di6X4v^(BCa+MVrc_Ex&yw*0fO2cCcd;J zUN*Oq;OwH+zsCVuW5q%9QIf^@IP<ZePPny)G!Zb^u{aqxmxke_lcUgSzXBa<I|x^3 zmqdU9vn_;WbJGF9XyJRe0La>eGUU-8^iN}3TW7+cRB}+0(Yoxh`(QnSn<@g8a?+1q z#|s4U_ou7AC`8Yp4YNY(ts&bKPwYqY2oyj=4kj}mgaNUkWWo1|s4#&#N(M#G1fBv8 z0hEhV$wP8#4G8Tx#xF3?XQl`^pEBx`7oo%sk|^;@2hduDh)s<<)C1WgjH_r7+#F0) z&~NI!n6mZe_Y0B>Os0QW)N80Py(81{k^B(7v{gunKyb;Kgw-*(CiK&iWvd~fbh+#Z zMzDb~GPPF;AB&ZqC4UFYN(g#GU{*Pk=94Hs=X`7pKIk}|Qcy@$AcVU54hMb_Pe3lw zLqchM<U1g97Whmt31@BsW>#5Oe%eYYlp%ouKv+UMK^i}9sn$tHt=+w@z`=Gq__1VO zlmX_`MW%>yWSULjXlmW2VXF)R-2s@!qt${#r;P&b#Q`_lY>(^8Ep2@TNNe}vHn~@c z^HO=O_x~UKe;yBIY)I;#SP5HcT-FIbAVJVXz^lP${)`vC&(8@6`nik+1DvJIEs%g^ z`fQIJIH5Cgj*l#Z(Uf8z8uW~JW&*Xqqh6d0w;U`@-k}32bAh-xLToYt<T`x7FRjg1 zw%{kZZM?fT&|0&(97-86WsCT|wW1NM%Gz_f3g7WOuz4{t-Bkc6oYxt}aSV9*33BhH z4EuQY63_irnpOfw67fz177niT(9r2ZLrC~X9$o}7JQuyPAuop`+#)$T?R2t!VYkEw zG!^mzTIm>Y-%4tBXtJK&<7I@oFD*-B<QZ#%G@}uikVy#%p@Sx<jXC0d%8YX%a}qTi zY_zukOGf=>a@&!jf$72(zG~_hoVdz21JT`{BvmTss&XRVRSxCYrl~=VSuxFi+l$^u zxMQ__ARS4b%#<nj(LJ40ucp>5KikzL8(kJjc#0;VY=W&nr*{ku07__QA=nHkp(T43 zsvvF5a@egLAo?6?f%HP4+6Gr&2^pu;DEOh(11pUH_<QJ(<84gQffh34%!VdNF#w$I zqRnn_w+|f-2#4D^faV_AR{+J-xP-hxp$(7<l#~4^z9_8m)~=1-O*waj+x&LXW9fVf z4nw4Q{~rlj45WdP;TAo^w7z=&*I#vUWo`PSWLGLIx$rls{6Fa6UXQ{lzV&qu{ul=c zKmZ^D004M@{R(n5K(IChxloh(3W(ty@Z(<w^L+(?#bG1=#i1z<Qy2dVID35+13rAq z0U3~RL&d7Q;3&ITXgU8ca7V-|N5l_%;LsORSFz$SH7OWaykkUoLj7nY1_B#_yC41v z;Ge+a|8Jzf#_+uAP`|q1{4yd{zbxqslY&n#z^6DL5?|~)U&5&WJM^p6uYgv9rJ)s_ zE+KEPFS;!&>^1)tCqKmb3V>Z+Jpzy~gJH|m$8kRJ3m33&Tnv4?!EfIq-(rR#9pL}r zXvh9TEVzSfpR36Fvj6d);0bytAU)!41OEok8}tXX?rF$X6!sW@iWDy-5L0*@h2aJX z>_?vd)4&ivYygf4hV}h~{1wpr6)*xg>Yz9r5HBAQKN=8s>-ppQe~Nuw6*%D7M{&)k z`yOvO@4>pn;e^1|a0IaL-wcxwy=W=xSP&f<Y8g>)xp0CFn2U7$Z|l#a%TM#Mp8GL( zyTo-b-+UAMHs>LHYyBN~b!?E*Z0WYBJN1+J3c!jm9zOkFq92WjZ)4xz*cXROt_vT& zUc<L<;nYoBQ7Bl7<jemLn((iso*?9OzM%oxYv!A}X65>C1Td)Va`<k?wAuQ_?80AY z{*QF%_dD|I?0K9<mtT~McQ7{T9tT}R8@~1PHCJr!DdqVJ`0^KQ*wCwv?#fD6@iw)d zL-nS=Uj3Q1M+CY@N-NHW{fGPKT}`?d6xZ1J7qJG8(R@Fr`w<=xZ|VT^zy%us-#z`? zjejJA2YLu}m+~lLL2qo>OFxJ!N>q;c1LVyr^c%B_{l)(-)5>p|ZHHUrzkROF^iLmI zew|shqI-J5QsQe};sE9?G;;vz;QB{Zq+Ih~Am_nt<cKf~9sg|{e@8TAZCJbmTNp0D z8n$qI9Kn7|!y0@e5G+P?K*D2Ugg~c#NBd^{)H1dt9GYPa4vqF!>D<A9M@pmzuI+yj zJg-~4GLGY*pXREaLU)MYT26dz5d2%3+&F?1_-cZY4)ePY@yx)dx^V2&W%uo6DL6Ub zs?Kjp0-TRJ@zi0Z&Jg>Vy>H>X-(rS;%KP^q5S!+E@Y`9PK<B`-`1LpW;M#q>0xw9g z_Hdz>iXk3+Ap_#yuq*$~GJUTJ*w=xHCVrja?-~DAbFS+=RpwIFw4Z#onDg4-un)kE z#<DR104{O=03^%5l-_r-v0Jri0A*SPy0uNellqMmxMPtKptCEtk?rM;C7jB?V*_vk zzC--u8FYO`k%mAg?oV=a!Lez09>)3I)(w7mQ|NEla2=$`jbXqC(?WzhBoBVmNZId1 zwGADgez}gc7KhWquampmXk~OE5&9KS@C9y8;9Z9i^sce=Q}oK+7M9?@f#;1#mJUhJ zo{E?7vj7ZT{vtc#2_AEQD?Bm>vmXE;(2c|NoyV3Kp{(p`n*Z|Un(ryUvgOZ}3PVr- zqJr?Bc_UIial)_|@uTYvUH|_1Gbb<_I5aV%l(=b$z^VBCUqQ3$5Y5j#7Z(Yj0rp1o z!%+VOZw-XBV}T$5kQEZBlITx#!@j9E?OoMK_m={_#bUq0X083LN*x6N5WOt{6f%DT zXH1ADK^VXR02vP204X{nJj-T$Bbowha7wPODWSl9mso9hWDb4vD{QGk?&XhPd?)|_ z;HN<bS!|Xv=pX17$RI=%&;bAh1cMHU|0MU785|nRdSqx@=&VZRyKeqeoOvT$Qm6ZH z0T#>PVvq9B@#nNt{DBRGx8FE)-^5<&0M+~n`@$5Cjn4xSfdNYI9;Wq3{S`iML~J;i z;zm|WF93kB98D91!AdRuhu9jvqkwdrG5~z?5GC<XV*l3Uz|jRLNZz%USly<e9cMV} zpt!EU9pY{sV7CrT9=M)VobLK=MGFT25SqKth0FUOx__Ya=P3{%V&DJ}7*^UrDL)JT z109lToZ^Xn5PL;*W^O&-igr5h7P$s)5U2EPnkOFN7%9EZ&=CXx$d3e-{ecV*0TrDw zT32!)01D_QrmWOoqGN=2aC{T^dzJgG26kMVp|ugoFHfi8=)w>H0`x94;Lqp;!B{wz z%J4W2w;}Ma(W#byD#X8N%<q;KE;}4Is~sD!^=Eh>g1&dmpl%s}5@Cpc`Pb;Iy8nVc z?6=`}dd&=+_p{(<EYP3P0Tg+1I512a03riK6Yy(v#(zaObR9?dh7Lm9PX$;7{EQBC z-N$+Cn%@c_lsyx){WZGOzoCza{Knf+01IM-n>@U1fBFE$X@_veV;}%&FaQhmGrG?Y zoe}z1boSM}tx|Ct;{z5%ixqF)4<MD+ANW9fb*+dG{MmpTm96(>7IdRpnleh*PSuhx z#ebl4{wul^{0WUXoSH9XEQq#kVZuS^aMl0*0SfEFdjvxefU-Cb7U1}21M>s^UyF5w z-J(#0SS;@Z=YKZ4x+QMYdg0xg1_!=y)A8Hi2=~7VFM>DEefMJUFyMbi|0X;Bh$aEt zIQ~GF_*ZoC)0l&aYnA*D(BrN-ygs`AApYN(5gC_lrT#C_|4rdxBa-tmQt<ZW|6F*n zf1w68!ah@8OAZ%4hy~tX{M`oq*(Ck0L|}?v+A*eoLI1<jMA7hm*Tlb^zu!~*m*^C4 z|Jl-He@FUe_&dM<`sMl8=%il%hK^W;5M2n3`Luzo{ptLdsJ}-d{~8_lUzo`TAa;p& zDC5Wkg7E@a-2Vj~h$OBX?Y-pOGz=fz{G^hC{|Pe_r5F1n;uHUzOBmL#WoP{#(Gj(! zI07(LpcmHH=)azSIconkI_1Ccp7&k({@?_OW$k<9pA;1IYjonfzsm2S-<GB+d{5-b zgKds4us@~vvzh<nzT$sa$)0bP<}++W@Rx;p=(SWaGUx?c@}K{1J$}Cf2q+7t0jlvt zazGF<z#SxX9U!>I^FjY6`sZgO{J$jqP*e2J;{Lb;3s6)11DN<IQvA@6AZ>~zZ-n{| z`|06dv0E-+Bfn<+P?O-s&|#01Abi?HV&3UzT3CR;QI0_JjdGgbilz0h*r0`HBgDTf z%|lHNjGnzO%TyBkW|tE_KV^Xh=TD{hy=Z&>M)$RG|0lxbPh)Nk;GG)~4ZgeQ0Uy%- zsX%`)^ryft4Gir+aQ@>zIsX%Ac$z;(F++c}O23xt@Ozg3#>0=h{x$Hk?3ZeM_#+5+ z|AQRwU&DOfhu_YZ;GeRg6Z>g->C45i7<_u+M{A0y`yZfZL)!8o9p<riX4RAbh@K}d zGO|=Npjr9p4|Mv8{{Vdt2VN1uBXHS;{#o{gq@>ry<j-sFK6d&cJHju~5B|pW_lAe! zpJbmH`kn;!o9y4_(Ecg$|2AGH@{c0E7M%jF>hSsOKO+B|uypSa9O3W0^b5oTNvNLl z2S~A%Oo9zG1%F)&|B<FYboTHMDOrA#@(+{wUxu)M$SwZ06TprO1OO3%s7OF$;BUY{ zTmUVPw6>*tU_#CTPI=oH4OGkG-5~`2kOKry36#P)20C^Rxl7ZA#)*1+QPshQ3IsEk zVnTh=r`eTZ_W7z*X2*QK6I-!K`=5-vh)YqOAB<N=a&JXOb%7HNa=v&NZOtq;r0Y1% zme0WdKV9H;mg|~Y{m~Nt*?306y5efZbS!+$Q;A7Vh^Jzij~0|XZ+S1{Y+x>91ax{) zYX5LqQ)u_K*fV{iIKhjP(#DN9t}yeKw#I&mt8JBOpZ+h?FE`TtDG2IySTdL=>PlsY zo>66(a~gAv1l_8naw@%g;K;pI@*wc61Y_NLy*kcB?VzxICw9~4T&B#fOreTS*|?{$ zc%6B|@DmzPR)}?UZ%^~(twqYUy$t+y;<eA&6{tikfJDj6F7?=v>a+Z+2hZQu^p6Qf zOh&q8Bo(Vq)I59%lO-Vc@}$cs**-aw7p;v`^7l}vVujC=D??y7N2*@O^`@1J=Fc2W zvrPP0=m{Vwn)PQz#%(*;Nz2X-{IQcbidah<dG|bf9M1EEj$kkqd>hZJDS(TQVkX<# zdf=f7sx1<g6D(o4&}d0QYP?3{YQ@J}=*A<5^TM@}8C~;L%h0D{*0NzucELM1THU%s zbl%%r3*H+J%8U#*4{^IV3<{LWyc4@PbV8Ex1Q?%MaS~^Il+y|1k6^_+iLsfhyRR|u z6+o?^BbIiO9jCE2rOK)CEaY`I3M*5YJk-x98;QWU=Wq*cbGEOndGgJ>T-mYXJ=U&D zZ5O;I1m{n#i$YgqBl{wk7@Y!$98oEwbf3q=ts_J%jxkeRnlpRyyCtwJi00IWMMh1K zrjypI;sZa#H77UlpHrU%X}w#F+@^23)cfqNpXl-s5oUl*TtUr0-*WrQG~DU(M!9-E zjK{c3f&5CRaN@&E?xpMQzV0KZFTP&^ly{i3R|9b>q@#E}i+#GdhQb2tj`yVAJsXg8 zF1>1mJLU`<=XG-rZ6KKfvP*XwD2>X~q{-nEkD`RSCEv6dQ^sUpltCeA_?)6F!|4u* z#$ySjE5qY3q(|7ZNwQ!$)e4T1X4|GAg4Sa|#cgO4>_ChmM6Drn4#7F3#CY<#`#^>T zTvmC?RSPT2vc8bs*}5?;OHa`ZEtMc94Z5fMgq=uCFwRNCDnT0w8|J)&5%g%t{_&oK z75qJ0rHqRU=}rxCbtMnhdq!o*3o|tKbIuB93kNHuIS5m&E}P-CYhWUw;^B?cc>!?u z=MDM22ltBsp67xVL$a*v)=N{86HBaB2Zh5^^3Hl0=ors4Bz9#P_Nc0{z-yUT>9kSn zV$aKlz{&XXZ7|vO3{8T~o&!>T$~;1dwN>5jyjqu<+|VkWuza2ItCCj=CM3cHPqUZN z?U+mOTW1Y!$ntUB<R++=Z;vukb;|D5MK5v71@?AwR@WM&R!;hkzeuic^mQFRej2(o zT)Fp}_+Vs<i~{ca-L4-ghD2Qj_!;PlV$hI!+d@Jt&S3R{-EG}L)GpP`?J4Rzc}u=m zmqgz3A{s5y2L==VJ`<i^uMLbz-WXqyW_c{x8||T%$s6moG)WN*J~!I@3P^r4G4;%Q zoSK_|LD9S=HMd`M!e1z^PQPpZ^r)cWa6dh&rWhv~$J6I?@!4Kny-WgmqXCzl;__ZV zqPqS0JGt%j48<&8UF;0)&!?q|1FuI83_7dAJ2uNb%k5!zm~%ey*{eELtBClD#c3%? zM1U2HlvD+q6Cz`DNaeVClN{zWKBif*7UFf9h~5^#Job!0P?3?hipnNx8chIJ(9O6k zKSzJ!PSe?o1#N38=taTdO4g{n<zY|YfrQgEps@Yaam3E1>}aCzC3uk`cWzK##dgJr zZAB@yn5cnQ84o0AyNp}P0kl!?)2bhiAMGFk^CmV_P(H@Mvv5Mw0{}^EyB)3=>_>6y znC9K*KUf&&%GIGwQIX%_gyHc-6Sy|N-Q|#<X_GcWDzCJ0TZHDr=ahZZga{pk0yk)U zGzIC50Sqa)%Pe=1n=5w9pj<C~`;H{l>JT-b?@?B83dXBmGMA2f4M3o;9es1>Yj!yW zSyg-)nAaA(-?t{p^|9Pheu*!`#5o3P<`SBGfFK<p-RGu2L0WCY;t<|vm#oois@xG| zukgf%k+z_1IsC1yc`0xzq>mVCvyiR}uw8KsE#pIM&tot}!#qhBb6|u{TV}jsLW|V) zXh(}LNYZjuW<ml=qpKn((u|5$V7_Hf!W9$T(vX8D1zWX{i${%*G4iG}bC#r<+64vE z2wRbMgx2u-;|20NRj`iw4XtDt+QdfQ<ugSyQ*76<#wuqUo47cQy5lZw@cN^J3TF9; z-%#xs1-*jxFoh`#BWC`^7yLHC<e5~PlV{+eO8GsPJ=PiHep2Qd|I!9^6_C*x>MXnT z@yOOgIy*0I3pO{prP#H}z$hy`T6u=~v`p4n8f36^4BqOK3O!qGMTW<$H7}Yty43lz z4IPP)7n%5<bJCN6tv2shj5VjNf3AZdY|yGDFuV^?VU3u=Ypu&w)9d953;?;ma_ms% z%W$s74<U#EB+DQ|a@a|SHZSaK5Z!_u)L8m_){p1w2GHnk=DWS3_n82-s|r!P;~_J+ zukO_N*g`!bA=6b=oBeU3-D=Qzz<B;<U<j@dXNs#Y_5>X??Si#yjZ4JU;q6e1-rVu* zqh8i(g=9N+hI6Of<J$upA5+ls!^nokt1fP2E&JE-5WiI8DsJxFh;OaMnobVcJu#42 z9G|dsR7g>B>Hy9<8dB9}RxmC;ak4kor+@I7bYroag&^FSV(HF3jj9<jpUqPi7f))8 zg;=^A!_l^Jyobu8)mwql-2ya0OReOI($#8cp$yYUu}E1_rj|afJxb-RnA0q66Zg_; zwr_gnB}g!`-I%ERq@81RKSAad18G~zg2jSac*zqQ`(hOl%TBDm+?VU!mKCN7!Hpcs zMabn<P2GYFdNbk-Srdv#x=)Z1)|HXWa&|V6y1hz}1?VwBZTE{_<SW&=I9XhJW!=k9 zcNtKJ-P|_%#3vBh^ExwcE^kCwXJq&8BYhS{CZPn%4{KxjQO(_}&Ld{YL|@8F-Vh<Z zmycFjUwr6wRf(U>Ma-l;ym@wCk6?LM<gJF7l|i)F>y4CqDs<AF=5c|oPfHAO%eJYp zROi~)gYN8{YAR7Mg_*>giS?Y;coelg+pJwjfKf~!?TB_=9IkGRT1wyCFqY=^o_fM; zyev8{ZE{|f*X^WmF<(kh6KG?Ytme{1jqs69xb>J!IRW!%QzEET8zSn8i1?)K7N~tx zu3Z^#(MEO4uny4Kp7SV1$tIFOIyoLMOncTbgrP<UhKs_9&oCH`OqE<m)5@eP7KRmf z7@ANPrx0NGL=pKRHnOOm1MwJ4j2_p}4KWvMT%)%W?n{#Dp>ggha|3f?$9<C_jx6ST zQg86o<WW$SGfz5lAHq0iV8hhUyf(|n7=kez?-uX2xeF|BEqM=XrKF3Ss64i`3|h1I zrNVP((KKeGaZt>4kWb{bqzqr!kmd{UBF83d>#;=`v9N8D*7c;(LqT_&Nr;}Td^HGy z*cjOpSGB1n+Hpp^WWA)Mo_*C*pVyB1Ddvqw`m_WQTvw&Q-hyugE6;M-Z|YHP1qpI- z4u&3)_2#4y-XCtc`NG<i>!YC;1|vOEt6qDbrkBg7!Iv3BK%68F3g)NCOs1)k>07qs zv!=qrG4+Hvyn}b1h+>cgQiiuPg*-fM+<%+_tP?>}<Q=>fo;&BX^CoII0^ioYX~gKH z80v7Z)jUPOp^O}`shI9m``l}jk>(aZjkw^sS62QzBo~{SjE{z$N;tE(S??UB4vtq~ zw1*jqrg%^EPGr8UzSB5IQk$zz!UV$4ee43kEm6-ZppInGbPFPlFF<N`Fp76n(nIP@ z(c&hlRw}1`5DX$g0VV1QY7a2T&5|!vfEjzR9*0GsV{jO*IoiC+>2;a4%qtkdo{1=w z*v97GrZaw~o^^{*DAnmSopXb_!G$?3(q$ywSNA^5D7UY1@AmnQyin#RqWeDACm~bV zf*%_vh3|Uu%g<eCD|g4t?>T@-u7YRKLrUzoxNCY>CaS%uDBhH|&lH&Kn%(ApCJzLS zTW9%sH~PP$m7-dk)|t}whK4+`utCnm#2_$0%(3p)9b@h5qJ*{g2&RQR!RjoC<p$(z zx)8AOI>rwwbKH`XN2_A1Fgw9;tI|sX<3bVSxXS^0`e`3jjcB+sNXCy<XlRI(a1wG0 zG6JNv4gwkJZq%6?j9HCOh9mOel%&xvbe-6xM3@jD5D=k7aYoSP0WvV!fPUFY)&7y@ z{H6z1?vQTFF8H2xyZ)qd$ZT5V<LClANCsMR*BDJa(J?E-&D&1-ylI(t@nU)d?z%n3 z$mSNg89{wCvc>9bIU|&)klU|qRWk$cnqkBg?{IfXUve0xJ|!fu7<cJpB?psfAE1;b z^ph4ulWcI?-zt2GGE7^ebHFiyK^I7%9#1zwZ?Q1?4o@IT1q%}`l_*ENlAOVfvsWRc zCP!x&H*p`mmI*CnJjSxNb;e47x3W2%JD?&ZI#DYvM@O-$7aublk5<80|2_^5QV>+^ zy(sD-C=v4$2(9suJMKaRf3zb3feuyXM2L{HB!w{IPWM~5p*+UGXSkrBEwqdbYG)yA zw>olBp(}6A5oZI-IH?J#OH=k@CM@~98!JL!VOWX3YvS@jTScZpM`sf<Fa4yN9*}?} zcgU*c#E@D|M8Hu?AU|!%G020irBExKIsfi)c9hw3CQjohAuN8@S49h|@fk_(<qu8R zjPxpky7LPJd8l77gXyp;QA%2OYUV7;t9QWUvo&j&a<loq&u2SK#uM+Kgw{R%Jo-4a zBP7>MWvk%!XH8y|b=tn<HS&)NHOvY5`%y=oS}Yp1?^$30F}uVf8BH|h&88<zZ?oAn zuyWt3PK3O=Gx|8ojylFRBHY5-cJ=Drt;FM5MAN2)=k|?SCUYmcYoAUyYM(8?mrxI2 zNSzia#K7rJG`3du_yUO1NjcQy$AT}Qs0ulj!CldT$ijz1M9ye?)ci3PynDHMO6>Hu zPZAU2WDsL+#GY$ay0CrNjGzOz(Nr%w#3(Q@29b)WY^te~dxRH5%-C&|Q5|k8IO8}M zv&PD6c%?e4bv5q>d?4e_gu6NbT9K1P7cynD9V3$FTe2D)4b+6?CD~@L<1IR&er)ef zczLRHau`x^_j&wtuGdmy8^`4l?1yikptAY&mUnEr!zE+CX}@q9$$%rIO~@1}4Ftc+ zEci_9FqG^hJ;-;%q-d7&5?97L(GznHb8!pE-k)e|8yG)2?}dyofc_!?jT|?_cF0Tw zh`=EY{g^o&HrdN>l^U`{l%~U(SD?zo^=6{7Zr#{j%hUxu2|;ebuDrQF4C#@Fxy4?# zgK9{H&gP6~xBm@f@u?`TXN$zLjui6*W{YXd{1NwC?5G{(WDPVznrL!&$Q#!VNb5hV zr^+Od_-mQUYRc?TsViYc%FCW{nC9xhrwl_f@`T(U^$rAmVj_25OrSi&>&{nW8)PbL zmPNHKc$#8O42%knRBZ?>nyQ!kC`;kAh0hcAeo>`2t(Lq`P-$+{^(jKw#52jFre{1b z+A3zW8`9N{ON*6JVTSp1j?oKPBFP*MI}H_4ojY%m7ZZhyZ;sxGl-o;W+RmIMDXXv9 zb(7#GZ`1*z(ya%@9#*!<QpL(0V^P)^iA|2C!s`qzx$ca4Bnvpc?}?y7)k^FNE;(qy z-e*jEt^k`RsaRGC$5OR1Pkb&S_tcU+B)ILpcAvIkHjTxdm<z|@a1LGzIj3nso#Fs> z^yuUSduB2UFcF=y5u>wAXSytp!xP$ocl`Ktg1LcF3{<4xkZ#IkBrbO}B~lYZnhsx` z#0FbPs}eV6r$)~CpmTcv7`AHWh0gBNyavv$d4nuVA(hv+p5u&IlYNZfUAM{&I*3(i z-gf$=$^r;J2z#jhS=vwe{djm?#{RIELnPGP`Ykra{<#Awgnlf?E7oiCF7k$g^5W4p zj>gWml1Rl0{VXd9ALZ($vCNy7d--?bMs5Y|GilU$9%VP}yLO!yJ5LtWZftN%_4B8{ zxjDY%1pAWfEcxmqpZA1+!bWXL$Z@~3D&TssiXdb2%<iGODI{o_i0Pu}Kmkbw&yKO` zgHV`EOd}UZbBEFswK<%cLjw7CZj_XXN=L>%yEOf(fm*Xz-N!Wu;I1?<UQ?kQk8R#j zRYA}VSx-<er%{k9*}W*x{=*y%JcHmm!y==2;uKllK+Js}tEY#d5Do@fC?BfRRe1-! zK_S-jgXpV_7n%1;H^daruIuqEbA#k<q_HQR@)x=VGRnz}6P&pg879FK!9wrkk!Hig z7l{g!6~b0s#yYnZZ!05l1ht>@wm}xNL*%T`;^o4)Apv&qO-BZT>b3#%TIIKLw^3z2 zFY1;d^siXE2Zzn;HX<yzg45FMl$lyeXY^)7H5)tNd-*@g!>o{Ja_@_6$zraqS$&Dn zrv@077m^A$jI$#QtEYI(RmtRSF0x2d2li@6I(C3BrwfxPc6a%C(ZU{Lm*wC$N;LP6 zc`Ewou{}ML%GF8_(wU!0t>${|LrJ?~EUWFUIVD3WQbOh8*k;OC2V2N*T%LIrnQ=2I z+BXysa91LK%jpV*aYj5X&aH6icwX|hdgN9*a?DGrWe=MSob_qfb7DGgtDCkaxbR{l zjOClzr`Vk2W!$^Viov3)hLp{4yVe~jKc_I94TWWw#okGEeMrcpuQSZ-2E8LZ1SnTx z)yHk(_tXJ^0Pp3(u<49T*)rHoLtO9Dr6^Tdg&B{sWF)FCTI*2ekAgbKXBj-7*J6f- z$M=40N@eJf$=At2zljvWhZAf*jW+<bE;}#CfbaBa&9z=ne)Cx?@CK1}<upq<mW3$o z?1RyQp~_*!%zjcwB^dLPgOj_<GNWI(G%M2UMA^w|%mMue`HgxO9ue!W?{6722zuIV z!L+2E6z^}md{E%kQuj=NXu0+Q&QUA@4KND!`0NXEd|xWVL$hoU4>h}lf#59-`$6U* zYu7B8ERO45To;l3{o`j105b2h%QJ6oLdo)$p=Pr%tEE!n+sd$>%TMuHk5ps&PFO77 z_f=lo2@E56Cjk1HM6f~6F|l2m3oke*#L&uF{z;4udp};t28RVUm=C`{BHccr$+mqG zSOpICU{IQx1Qn?j)De^BtANtbYO2a|oVc=0i_CHl6-#)79TIwjJ=t!`qS3rrC@}%Z z7tzp}_0h3I5-sUf_>J-8lf6opr&o{)z4~^Z-3jlWziB}n!RszOQ6E5c>8)i!TG>Fr z-Rj()d;gW^^DNil?9%s(mgY~%9aZkBc`V(s_dTDEQQ`iK5U{qM7ht~^mHqDRWr5A@ zldQGzs7^<0V{Y8n7YCDqOPZWjAN3TFn{{)DoyplqxFKKQ4u4L+=^{mhXTeJo_qK77 za$|b9Huf#$V5Y5?x%2rB8L}7N_o=IasSt}@U>xe?lM}7s`q_*DFrVx^SLU0a%6%si z_`dVuqr6+sIHd?JO<9NpUwFi&2v5DAd1RD>r#ZTD97fL`6Id^e4{1tZ6^c6dq6(zr z^M@N2Mj-0rw43>sDM#~;(@}2Ok+O7fzo^>bz40j~sx~WxEC}+P{U~(Y-BYA`3#rg5 ze4oYRyO9{srkR+-d-e3z26`$1eD_8XUab__RE?)55H)la3TlNc5%&?(b#T6q!K5oo zRI)nZ(!})Ak7?A7H7^N@?ovu>IWI^_a44?Q!*O6UN)N1+yvO_MmDj|>mT*K9p9xmR zeEX6S<fxM_8Zz{~SeG|<&00Nhc3{Pb6{a};9<{BpFl}6-h>zP^jyKm0yi3b<I>m3? z2JTRwD#=4$EcxYpG!DgUdO1Y<Af;$ak=6YErhb{zPTzQTz)mcER{cExtJ72b_1v*n zi|=JS;~Gc+UBkSUQ|~_G(<XBFkymYK5%J*eUA)F*H-e$PChK07SPz$OX^<k*wokiO zWK1cU_nOK%E*J~9EYm?8MDM9GdvdJHB|6XYqtKnql!H3wbj4V6+G)z;^FTIf9YXn^ zg}Cp8cIC@7tfvNWHIVC{Ia;D7gTs|)jQIp^hc3*KxJ@~+<N}k>9?u~dTT~Z~j<JV} z@CQqq)IF4I<cO|~8m{sL^rMA09SuP{EYWfEgL+V^LT1P;$*oNvvyRo(t!ZRvv9#-S zMX*bwIn$x2t_H4nG23l?)Z^137qnKG!nev{HMCwb!=vp`DHFJ=tmw-u0A;;-s~NqT zNbqi%!gF4AT2zz8-15HOt)3ch;+WJf8pZ;&F9d*Vg*LY*t4GCpD7;Vtd_DItPKDbp z`xEo<q#3>W6OHV)^w5CGEIm_1<ML+f<tF&cQx3R!DEh`d-c-&7S#_!%U!1_#RNJBz zB5BOLSFJY9^t}pSpH_0@Rz5o|;;HBn2oikKyq<=>#oo$4w^oXgc^Ue-SO+u8J?23& z6cMiBs`gdqRTfWMPkeH8UuU@tiD;&nhn27w6cJ(Siz*IKI3794mW)O)Z#BlrlVgln zH)%`a@iimkff4!a?o7=SkaQKr*y&tq-3b=rvF1}ELUMUWJD#J)jvFLfD^kP8l^j!1 zBuLXYvs?5k2EX7_%qJR|WNVBxo61PkfnE?GKB}{iHtQ2nZ_EONs7^SdWg-Z?m^xP# zXLk;asU#cUsUxCIaPI@gM|Y`n1KkpEof~ztlErc4Uc4s1k$8E1M1K4JE&S8B*3@*H z&v7BN;OReHSJp}u<j@d${JupmnI>7#JBO5v@hQZ4t>X>jjLuNz%W1#GV^;F;RpSv^ zoJl#CgYEZAC4%(j2l@O;*h-lVyIvFNA8+KE7WvW8dBvsQ<7jryx4UN_)cIV^Du4_< z*5Px?h1G4#GEpT@zfC1|#xc}WmBlEp^fLaQkz2z2L<(v9F2ovy$W;~eN;JdU`m+^d zGZMj9eV|*R2Cz@qIzwPi^|O3#-pRyT`sCM*GsQdbmZCrgI7^|(*CS^4c=&47XVO@_ zO13jft97Qnd*}3BgA{@#Dcxn(?NaGrn}<z%rDq0}>-g)XJyPi;!T$IC_)l_2c($%a z0c3s|b;n!=m9tU=FjD()k_gA%0pV<>0I1T8&a^A-umgS*)0yh7#hsTrIOVs6i<&?( z^E`wRYxIy#G*U7}0m?KSWoS?@n=?J1JOdFvF4qnHh@4108Au|CmsA9Kw60hwp2Lej zg%;3pCkPj!9OCrBsl<~2mkJsoT)*(<G&L`oz?y`yS>dzW^A2054e2{WPaGw~t&zvF zh4$IWpy+1gkj|x??1UCinJ)H-VGeDQAq&KZVCknthAUmuwrPSyrh(<GL+<zq7(lnA zr_M^X$R(ZfPULT0iSjfkaq(tkiJOkHgP>39Gp!D5l4wF9j)p{9=_OVsleoP%`vV$@ z$~%p~qZY=vy`*yHObh(g3SaPS$klgZlSyQhSuuj}I1+d|bNE#O3t>hW2eM_wWT4TL zaLUM-$!tqLTq1V|*RoZ**F}ZJD1$SJ;R8C6WEG)!nGYZ?)w@tIGcKJHe~Rus#KF6# zMI}MAYyfFN*E_QXgJ>1fHbjpYqiV)yUg02ucw1|?w|^U(EEfh>QPqCwbn!z9dFnHo zkD@L-73}z2+Gp&J=H8CA2wiUXqdiF}rDPQgnYqJ$<qtY{U)M7`Y#7lNy<s?wtqP;$ zxMvYFyQPK)uj#YR8^*-KEtY<4dcjt6W&#^pfZ42mkJ^{=?RTOo$v?0uJriF{zxjNC zyF-ROcM>1vMJCOub&Q#!oahiJ@me?N$o+Pgsm=;`R7vd_qKMy_-8+OIs>ry{Ki$am z`M>wjGCZjL8Bup5CLiOD6sAOaxd-zsYLYie)FysuiCf0D4ipr_-{$8ZWvB&2UAfP> zMvzA8GcTj#{LHn0<q>_y>)SdB9+LW}mvqXQwl~a+yi>fi+9#LOWni4j?4BYj7jGh; zVWx`S(h6`zau*c8+kIRs(&8@Z$Vqhz8;@hOb>_5D!i+l5B09m>Q+!*SWR~*o^u5vq zCr|v@*FI-CVdQ6nQd9&+nQIf5*#PRoJqa|1&%5W_Y1svGVFor#ep2_CWbKF0Ad_dM zt(sP5Z*ygBPONfZPLJwXIYgy4HYW)RLGFIznrun-ob`#G!O`CgwZvK}ZD?0)2{!n+ z5Y6N9iqi%%##8gM7D6^z>(I5mY(y}8I$$by#WAX4Q70K~V)!KdIX(B59~rJGSSxw5 zc=xEw%>GBoz3-Hu&}`l_uS_Dtzp*#4m+h#`-H;QJL)@LSmyBN6x0_}EB@U5CDew(I z;Kea?+rCs#-DuzM21|fi|0inHGhJ(|hn0I*F$`hVH-^N%5qQygZH1~j?=<dR=p9Nv zffEQ7#T~$1uPv~#yX-wHs(O%rmu?8m9MLFY-dd)R;OiXwINB+;ep?_sMlxwO$6be1 z==9NQ6kn4!d<E{celek9C3zJJ%^mrTJfxF*DYF)M3au@$6P$Q-i?#1<%)s601a~yt znvWNyH6e&<%T6!%z5)hjzD$@mofSap62`;EXOAWOjF^>olOlE_wTR8@K3|drIYiiv zdQ>%e-XwLFcA9l=W5_aC<2O{OIGT7l7vH|xV}Kgw<Jc$mAe%&}a<=-OqNN{;ZNqYC z?!%guogB`0J5uIk-qmhoxofr!&GO3l&mYx|FNj>Fu7>E3MWV&1z$=Ll8%&gT+5vjq z9Liuu1ixv#8hw|L9}&B8DTiPeAFl2s_*%#Gg)q?$YMFs)u{Ujg{UwEor+%T&>_TN# zPUz%UK&I6KD>4Vo9T407W{Ij<Ee7EyCz7mc^%u26^1(Kz_DhAh{8=!`{S`w*r8Ot> zd#-|t%ch>wy;VMFJ5^jfI?-qMM`WT*<|KHaAgS$^QAO%!?wiJD?w8Lk^-$uUd3Z&} zlNx&+z6-+WJ{kpZvXZ4!*jHz+mX~bbr@u9Q@>H2ueYY@mPDA%CA>ehCP%zp|rENKn z+&fv{UNc<Bh=v_Hg{j$HLRJa}jg?1@m(~Y{xyPbau{#fH0-qsyxIAzezI8{`Jc(zT zIY>YHD(ogKC;&P)Fcw@qR!wLUFIKP@cJa~qUg!hbzBu1W3-}YxMQQ#vX4JM<1-sJ` z-8Y08o*_A>b0~B@xVgk^$ERfFMX4ngJs%dsOB8g7`E>k?r!MBxuYlKFpL1c;UpOiE zhuP4CE!K-O$L=PdS1}lrFKMdZ-B%y8UCZGVvBaMZeLv3YjCF9j-S4;}a1rrNK+xGh zg3+_Mh0r?wYOkz|0i(Pdswwtn{RlyBgm-h<d27sSDoRN-p!tKcpqN#G#}4Ej_}-N9 z-KDJU?%flI8JW3FK}X@?<Pzj4@@VcCYHoBWKr~YNB#GS$?tYGpjdPe8G7@gJS-$l6 z4R3{PrlS4Y!VFhYEs)@AeLugi0Lit9B%H&ro~7;EuCs$SEF7NHdX@e|NMQxg+0P84 z@(S=Roqi+Aah~yVZVCO%@~rw(S)MIc8R2K{r%VN6y5jGB+p~w?zki?aqIk6>Ae4nl zOR}S9>Upg>6BY6Dk1j5Xy|N@f&lX4nE9dBhU5af>i=rR!9BXwjr+-SZmkI)Fgxm=~ zc@BTbtXZy{HF;{guT!$0byxhgd;<TO{n96t4e{M$17EK@8`3;vlaH}{X**puWFYD1 z`F2rd1{u_FM{tkaH=SIzgsy6@MknL%Szo?<5;a2muv5S3!=uEuZcee8?7*~S3Eiff z4-M&dPzi{)wOFPoHM-o{ZU{l_NV`9CH(1{RR?P`2n66)VL_$m+mEjK>xbjj#vP7iZ z;zt%0?l<qa*Jj9}K9MB+K&le&LC_n4KX<UL#y%4QljMs~g-!xrnmsDh#GPit4YPu~ z_=v9~)3wrigEM?7^#b~&Z5OiluGaGYGqsN3*&2&juC1;>Vn2fO`X>|mXkPWLFkwLj zrpW|*|CYBK3*I=G2lp(tU_B>6xiZ@o&yij^XMG~3%<|VS+1?n_qO~Y|FL`@kXJ4{h z3#CiQc5OIgaQhS0^gH!ckISB6Gykev0^YUx@HHwL$Li0g+Z=zJM{4;Z7N;JkDY$m& ze@i-@3)8P)M?Y-<w^;$dj$4I7E|a;Yk(HRQA9eN$f5Dr$k?288!-LnmU<TC!p4bbM zbpeN(zMb$BhcwK<ZY1WA5i)M1SZ(693`H^-u<Csw>UR=7IrlT3hb+IsK0OI8Lzyup zmL9!L*qNwkSB+U^#Qe-78*3)^eyR0<eJBIuD*&`70cJK7ZK1A06Tz5O$Cn#(NYcJt z5jN#A_N40~0;V$m{I;gL;AjqMV?&Pu8^pNem`;GxTc$|*3w_-&8vV@&J!iG<TVUMq z3x3#R9>L2tt6i5%mBsVNji1=PJ{s&#mM$0TY<~2+T<}(bYDf(0#rN#&tf`<mXRkpn z4@$_jr{YB;E)Bw)V`1ZDIAJZ!Q@q5tL{%zOEwYG-w+qnsTqP8{kPh+ZRA3oo3=y&2 zUMg#Eh<25E)m}2u@sNaB>)_tRE1^eY7D6h;Llm7fJA0Emf9nXTU}&wFqR)T{N*rF! zZ2H(DU#AWc>#*|T)P0Kq)x1S`>p}*B%;<&zaYSTt_ukBww#Dq#m(dRJd<{!&hSEv3 zO-k<v*W3cr*EPP|pdI>T#cE3jW*ycCh*1dhJkly=^kAoM7G9h~f#GDI9Qd+~rk6<{ zUujx?(!^}!0iC=xpL-=>fPsXutA57AMUPjmtDW-DV$l5NY|YD=#}VtWC_A^pb7G+1 zm*&REGNw~Cb3H3h?E9lcT);l7c_+3l#)@$Z!KWNO4;lAN;tNBGgAP>_o;<19G;#ps z#GRc|C9uA0yvMP4S+iz+;H(VhFDGBwc8uP;h*OX4`*67>zZ#Y3vd^<~b+O<rAKmFY zk>NLoq9*c=SfuSnDwChr)>xtRjKs!X30=8e731WSSf{1<@TQ0V7in)96h{}m`ws5G z-3FK7?(V@MxVr{-cXyY-;1Jw{ySuwP1ot4h^Zw7d=brDkYHEM!s;TPLz4qR{_V0OC z2<(N2t+>nGtMVYRX_GGrr)Lb182<Bh4sCTrbDU1(CjR{8OF;KCNpj?mXU^wmy2kgF z-w%mU3D*vfT8)3_5ex-3Jeg7CP^yMsqMrF~%SAeA+(0+07udmXxFF{IO9{HhbH%b} ztoq)(v#T~W^LoM3pZA5iy&duD$qXrr#`j-hGzUt(1%)!erqa8iT`%)}OrO17DgIf_ z2n4BoAfM^gF)=7*MdXhj&-=H#2LpOP(|{b`F65yu9j4`!lZ3Zd!ZVV&0sRq>%zeZ~ zI6Y;8fZK+4io>FhPNR^;_Tr9^j$pNl*U^^Wa!!(LrO%Y)6)JsGW$otMwhMQ5)X$1M zn=%BA9fdWI=co(l%W8@Q-`PUse}H^R0ATiu<cvq{`O{T1CClye-vG87(>bH`WW1I8 zMNU6wrE`S`K%GE_p9e`2Ef{s?XqdSeGV&jnlNbpTH8eEpe)Ex}vZy0w+Difj3X|K7 z{q^{!A?9Me1M{}yhtbz?l@cQCN;X6TO<WveUWp4h!9AZ(M1fid>us><r_=W@CKNd{ zwV$C~|CF)x8~+yLV;6&&*Bqg4M-5nzD<TP+fZ_02aXNEC**<PM-l^plSlz4Db1Of< z=Mjnw2f0}88eWBuklZM>tRpNUxwjG~#PRZ~Y}3>VE@enJC_i<VI(ZYg0UtqWTu@_h z#}7$^(ka-jQ>Hr?9FgI_az|6T@TF4w_PwG=e>_r#R|xv<y(7<SL;YZndoEv<@Yor# zhYi9fSwexQ3cBEF%ss32AW4);_;bGvJ{i$ZE3Lx;o@>TZcd@U`tHu&TN_#`<<}WH? zva1#xN|%I`bS$d;@|mIW6G@^f^F=)8-d1d?+Tz@B^PZv4i6;V~s->hcUKuq0z}=EY zgDO`XdY))c3raA;ITM(t9bBK0aA+lLl~BPs*V^zzHn{cq0ZP_EU-fnBT6tCycpJiv z&Q6fIpYc_m^e$F$2Sa2te!_d3-gr{JCy#&crWvEeV?5G$!o}%di*$?M3K>qN?8l3* zVnQdcno?S5qpLex6+-MJSEi^!M8~hZqM{RZzHr+lv}#b(*3|_+Cc2XUJuW~PCz*V3 zogU92h!BsPtC?s@6^DX-EAo3{CLoImlzRL4b7_&&m-!6um9QkDZ$hm5YN+_#*ny{> zwf(76f%+i8;>(t&s=k|F^|Xnm!_AL_c^I0B`3d3XsT7B+Pv`shBH7BNF2>^-;c@DP z^Q$86YVKDOpMZhi50tBz+aDcD_n0&&Z}j~aC^&PqT>=><c9;mJsZ(9QurD3B`G1ox zX_=W|I1hN(;nW<=+VLcNOpw?HPW3ouuNK(J@?ID|HG{h%{-2Sl6N|=}Rd`7!7J5~n za_T`d=d_l4&cLCtS_<*cm+wY}P>cDioA%m@huY$><@RE=p=^X0*)$4C^(wu_?6yhz zZh>e&M93%E&Vu&ELcDYEMW$phw5?<=BaL(dRr?}0qO_>u>czs~)1jFtsc|7((|(cf z>V0F-5%2s%Km-9qDWOHoA~!K-k&6h*)@TSyR@nnGU;+zFDUt9X%-A~cC33z;MIzb4 zi%Lq0BqA}#ld<4pBsjx~^xRwt!n;K~x1nmCyd@Z|SUo+2e#3L~Sn6;SnYp2H?etTk zFg4&eR_<y69m_a2_L=Yur(uwHZ`b-Lk8&QgfPbX*g=wT)c}onx$R!yY!_S*qF}fdq zRqqql*iAD%R-kF)XHZ2%6_v>8#3be{jWes009XEAxAQ!3XwYK7VDLH{?~9_a!ErAw zW&En_%GRg-VID#47VJJdt`gMY*n6{J3El#T0JBnZ*+}d^hHY&^THq(-z<z?YZ(z5? z|2>wM-l@hF%LllsfFLZ8)I3g0ujdqY3UhiS5jmjk25bzh16?Vec+**iih*OCurvZh zENhf>CX{5*K#*NvBqs_$V$Cc#ZM_~N7YH4QD=}OT!;q=boC-@AihvlJgoz~5PmmR@ z0}Th6ipO?XiHJZM7fK~3A~R@?E@Kr4f2>;r1j$v^YpA9xXlW<vn(vlU7`X<kIm!c& z&oP{+meI-4qYka;f@QR1C8B_BQJrXrVltc5V#CnniV*ndlgS(aqr|}aOl4K9toOGB zF$J*G<+Y*{aOX8Ukb&Te&fuHN8kkGXK8180zWcQALPB<i+F1Dg>9nav{oC8RbZUvJ zRb;2dlYg_<M$P<q9g+#>t)AHYtc25&R`IB#n9wCAu_}*b<@z(r$aPZjtf$zG(3*`A zW_R%IA0P$mcw3jBz0}>9HadQx7!K4$+02=2u=S2Y%`U&r_2E0isHawvbHCN$GQy`7 zg7J_eFwwnKy}aFb$!Se9k-uf|;g@-lw>-{iviA8L{MQr{yQL{S^IS>Hb8s)(c{pi? z+sw(-OmBqLMBrAV=XUD8+To|I?*$lN+TmM})&8{nKU_H^%zs?@{{qYZZ>}7SmEZiw zmG9je{V%Q@@_)E;QE$b+7Rlepgnj;clH_3L_qhA0cpf;2of5ojr09%nU2w7}P_hp5 zZQL7P`kQXts~PWcY;fW#R9<_}TQ@sZEv{LUMKdv4emd!2Y>mWW0rk6&ugikY%5McY z%eIA2=ovOHPyQBe(>4k_=5y$hI=xg;wC;cXNm;$)Z|#$E>42p>V?pZ85Y_qSPus%9 zpA>+VqUQD1+L|-xKtkKv(|WKHhr>4$a#-yx-MZg;A_TRckT3!cIZucMNZBJn2{LA< ztnvP=+yTx<qoC8vBqrIf>3wmV@8e3%LG19OAs;(cXy2dqH~-&5OzUgO*==8>TRj{3 zv*+usuNiU@##7cp*<bzvGG87Jv>xnLYBz^)WQYEYY`;7*6Il*^5-^P*+>r|31^%w` z_QcXsSi2#`HU-~`_qDyWnGd^U(i#c4zeM4HnJ3hKvXfdXDgE0=hh!kfyAY;9zX#a! z+fsfOXQ+@OV#B%O&Sz}#dtP1;l;z${dAeZ>sXm=0N0@*x&{uua`7Q13<NKJO-^+TM z_Q}cW5C;xQ+2p6MM)6xhpDbDD>$C4K>1^NHs9R1Wp(EdUS!`~h3t|6MG&tz%PwY;| zo7yQ3G}wjX03li<0VOa8pj7*wv$w{T)ngb5ihrW9^~`#>5mckZ12T(x-F2ZuBDu4C zelONm9QXCle2p5MYs3)mJbq&Iy(=%yfL-uB<0Kl~L&uvMT9M7{`9)imqZjY%dSJ^{ zBoQo*>26w5n-QWgtI9Iw=<hIGhkWXwJjwC<+h<T{phBYJ6#dCU@8doOK(IfJwoVqD zA;jg-q!yozvKSKt9i7%lWKvL>BZvrOetpl`O(v6@>|IK%_;n<GJ?AWmsTp5|J+_uQ zG%bwbD0XTRjf789;bx&YLqo<@t@ahsP*s(bAY*B8pIUdy_d4O!{Q^?=v>xZ_dhYT3 zFvY3RLbNhd!>d}N<$xG1<j>qV2$1sLo+Oc6elVhvfE{I(L<H`z%;v<O!_k-mxy$v> zG{@nR{#)-p$|i2lss8|U#scq{2BsrV<$oRhoT`Wh+Vinpok`AK3QwKybrfs}%hF3l z-?}8ruJW^)NJydXPmhr<XWp}8bEIbuK3#i-Vo2pdp>0}(7v9lCb@(1`28<s9s4LGc zU-3SO{5-v_N$(ONTz=4yJ5~)CBj~Bqduzs8iiotMLS(8c=^v^&I{psF*{8$i6%YY1 z{^_UIsK?C#!pNP4ki}*@IG%Di8bc3Fggwe7nhlDjJ4=j?8Ikcxd0`@AC9_S%Y+^w$ zK@J}`$jr`H=~;^Z%sqc9#K&Jm(%Hl4T{qF7Fs2kua=&YreE2|wI`vJOE<?^06hKu; zn%b{o98RWiIJcsiQ(_YsGO__%>qO(f_1oZOD}R*@*Y$O&?WS38!qvJr^i^u6RYEuu zllf>`q|fn2POc9i#pcTIcrz%tC*=%D*z+BdECne*NOC1~`qipfpB!+;{NAzi_fZ3O zD8+fVRG=#@TrH(U?EBx8p1wu>0|aH$-ZYEJ#ALX1(W_4637kpFY3a7HZYY$W8ts;m z`YdIp8fxlxJ#N<(_GQ3+k=U?N=cI0!LQmSjwU2e@CsfV47Uo3W@?0_bG87kW^o{lN zGgc@$!i*=5*FkEA?SAiU*E{`?#v6Whq~mVE>t_HdV%p1JEhs6)$6$^G%vUSmngg_g zqUT639k}+<$jy0sDGB0`-nrK#=kdf`D~Cr$-z2wg??~FG|E_<(h#FK78AmhKEl5Tc zahz`Md=gh!b}jQ%-XzdTGbIZFMqF#FKCR6Se@EL%Yu~%)5Wy$xw3VvF$$XxDqmo_- zs9&laR9a2wEH^PV?DY-kXV9-UX>?iOAea3+33aNcq|pt2B+AIY1}V_eHM%Zk2gtC* zFjT1Lx?a@ZVw)zZB7bkhM-bqV%bY>Sn8o+%+=~`K)T8%x_;3F5gC>guG)@|o)j{D~ zsPIjd%s-gRLvyCSrCHyxX?d%z;zot@4=L#nO30mJcF7J-2FvO|Q{+c`6t3pVg~2C^ zry^6<+$Qyd7-*9M&B_5#7J30=lf+$PbMvm3*<EE;1=QE1+c_=<CD@$_R{q4ljj4eB zQitWa>k~E9R4ojN?>_HKw`IK~Dh95LGQX3GzY<%JNaAV1E0K-c;Q=PqnXThpZlt@D z$g6?cUBS}Q<jcnGa;hycx{58CrZP<i8dAfa+?rcFkQ#(jzx=S^9$rXV=u{mObFpCw zL`^0Kb^g8<A_dXnQ4_`Wvt(L5bspozK4{PxduBSyUw@+}`)Yk3c`FV(v;-X$1LE3E zT^IF15p`sT8jrz3xkY*A29X1*2BxB7hKv`?IMKgR4|w+~iy)&7w$yWhB+cUH=nn@K zgz!b#2w~sP^ip%i5GHIfWsJ<=kPY01GZ#K(v9RJhJqVm4grE~Km3>~`2Fv(V;;Vd$ z2V3!?!h-zBgl3+C{BKcRK|Jf;tglzpQsnc4d0IJEw#~G(1E~BI)_Bxr1f2B~lRhuq z%%TV`Lg-%Ne~ZcI1wcLz%d`p&2aUAbgsgE^mRCD25ma3)f5p_0SI3DMFjNT7(dy)g zD&6`7X#$j>7L9`MMjNnH749)r+0e*!s5ut38`P=L<QcwOY}8P2vS29JTT%si$_+7i z;mw*x(p1fjCsn@^A`8+{ka1#&gz72Q)G3gt7HY`AqL8$eCK$8lxE6lH03}Zj0kgta zTKP!&(zx`1>v+aHyj@(gdTn%Hy}0$H2@Eo=H=PrrwfR={WmYjePjuX5B?`gldwic< zgBY}xR2i;;VM{K)Okf);q1K^1l}(FEu~;S-7I{jx>s#w_%zg~z-VtgxbAr_1a=oFi zf`iTwpWDm(Y@+fQXO*x6$-_6IfSw`bly|*SDWP|BSE~6Ge0W)$j<0UA^7KEjpv6s7 z*WWpK3aVu>Ju!#Gd?J=Y;L{QK@%UhVqkJ_X<Xt7icV||#n)d;&v+S=$n-DcEGf86( zs07E<IEr~|tAQ?Y(PYe8QKFvtD_A(rg1>k)egRba<Fcd{PAVbwdsW~hGouhqmeqHZ zIl14%Cr0&X{JBkkx18-2O5}t{P=Z=o5(~YjRh9%ySH6Y>iKh~Z%s7`-MfHBU<yh?O z%d}_Qw#RX|r=((MoSMcfozNC2&c~AZmS)EQr>i3t8;`xOY8jnKSAl0UZ)2`v9+~90 zd!V#qdCfe8tYU_xOOh>VD-=)Ooc;FPjPvkz?00Iy6A+LMPw~>BfXyxbM$93qb61+0 zkgUYhEle7OvPTm|S=x##n$$_#@8ZXcw~@S_!x+zI>qp~rfu&V5;z=`k*|cs2?UceE z)y)xKni8F%R%PSbXB-w~qI;54_t>sAG-s5Y89B8*FSV&ihEth2vzw30D|uYYMstj_ zY?Py4y|4Lmd%=OI4UewxYcMDYs#!1asRl88uk06eP*?T#)+u#6^khA4UMj%xoXbPH znFR--W3^+5)1KvQ5Sd1;QqG?%TJ;ARHM7~bWpsGnFtL&a^e{BaE121FPJ*-4lEp&N zd1{3bEYaj!QwV(d1n3CqPZNnF%-<;s9AX)?=sv|RVI)A7Imq^>y?Ji83>ivoA~u~L z&^TS%8SL?WKU!n9Vnv){@}P*t^a!KK%`D*;09~$=+)PbTQmQ;`_QQBT9FvRV@=p%0 zyl+29aEl=+n6%NXq?BPP@l;IBiE!|Mm@EJm2=FQ~u2azqGZ-6Jy3868M-Qz(3!;N4 zplJp)N+~Fsx>RG$irnyc|K^<)?8SFbz28Ob?X%PqQ??-TL^H}s|5@9g<2tTu-S1OK z{0|VG>-QzKT?Y3#0`v`=v-mG`y*T9x;*ubw7Olk*^jyHQ#O2q~j!Sv8PMp7C8F+#7 z$g3C%rw|)(f@9C6oPFfH1-8Y*>g{jjUu$mU9}xPQ3n5p{>-l!^hKabF7BNKdw_#>P zrcIC$fsmpZp=Y$RPG(J@5XNQ8<~D7UUI-)P+o~=L#YxJkev3zYChV)2QJ*11LBBr1 z4n}ef4d3e>7DaS|Q8`Y{4q<_<?>%K<r?I~-u=-<Lz?(!_X!rv`dbj=2dd3End*69y z*hoF5lDtPSxqGWui<3xyi*MD(68LkzP8EKcdd4|u7z_BDB|N4UU0IaXwpcfa^{Xe+ zr5XZRIx^4*uPM2&8K*%SdTN5qQW^z^%}80Fbvk__(iP_evAyCGanN6wLs%q7VD<KG z1m{7OfI(6+aWOh)2LI_@1I}Rzhaw~DeJ+oANYVfDrMBB5HNu9GNSIwRa6KofUqDjf zBw<iFP*^dltDOsc0kaTl6S8FA&u=*yPl`v+zIk9i0x_lebEa!5=NJ^j7{5%Bp1ZX+ z#y9vdGGglR{y$4hL&SHnELH?#t9F>9(o{Z#0@G==bvnDmsU7Ifg~x9SU!W(5y<kxK ze?&*eHOp8qG9!8i#;)UQPxm=Qe-W2KOq8Hxx&)};O_Q4gV@sD$Bnzn(4pT$psH!h* zf<=I;615>;XP3+9(Dc!w<<T6iT@%yI(E>qD@|Jkz2{3gA@Jmr{G;UypT^397O))2* zJv+|msAFA0lpIrQGA^O5-KY#=`O8r#(Nu1+J_MN^RAg~yBL-KZ9$6~zJGfJ0I;qT} ztQAPcn5MB=wj6;xEh+rJZJkVq<)M(TI%V+iwT_BJMA0B)r?OFa)u5-<ZD4N6O<8q1 zk!*L3WVVQUIfO*IQDY-dDSBcCw=PtOQ#RIDQMQu8y;vJvo$No@v8^54R2ZR)vOGR} zcJmyz?8A*!<l{O-CH*EbJb4ss)U1F^2Sy8d31~53gXJ&&fKmD6J=H*g01G2hsUrXb zEIzIR&ckLY2EaJj#Avn;oNDrH?6oQadDe+VR%r4Vls}L9XhkuD#H`~7zzHXk_D5>; zRwxYxMwAhb*w7|QJa}qI4>Vvk+^%|szp6^pt{&bm>!T8*#CascYyoRw+^n>RFp00< zjc1S3eC`yuRNiQ8U7&mL7UgQ_6W3_F7=hdnI$V&s7WuLGEiU6|eudl8#vPZxiK!FW zMON-m)f+y3_W0_lScd(8&Z9C%SGL%O57XsGv2A64RB(VOGe@oiuM3)&;*eMdnpeF~ z@<xSMwuwp8h`RK*#sN2qKD?jLCd*SbeSDKBd-D+YSPXD*8fXFyj8Re5B5id1gM&Vd z{ZG-Gt0Ux|p}5Q6!Z36xMwvVPKR0$Bx#ygVP?~<yT2`Dea7QhpxP4$G<|LT;3u93d zK&%A_ztN(CFyOd?l9iO8=4CNG?m9<e7NA3PQh7vm<Enj<Sx<Ga2(|?lN#PKG4^SlH z2dm+3M@^C$92H=unlodu7Z-v=9cyC5qa@<cxfU%v;x^TWQxkt|1vUm{c6-j+%tDKS z(fN7~RE<b6YBg&49UcBei*Z#K1QSoVtD!IeEb0;EH$|y~`4E{{0%Bpyh}pVp#+HY% z3Wtk@-iIiKqO;z-XOMLujWfL)q$r-b>-p3xJ_s7UAws7U#$voHRbDpT{R@<M7|$qE zMF*E18v)^VDmnv|vQ!HN*OWF&pf(OGIbUV}>^vDzdlJ)`k)_O{SOtFD+%kxnUtMdp zO*V-9TUNCkjcOld{H<SjF+6W#PEFO`Hv3yEF;g@-1ftEmy7sJo>F{+P`g2Wcoy#lD zS}_c(15eyZm<-14dwY(5XzXWXIA_#Z7Z@7ZX6R5e(sxqHu(8WXh+X_jFdMA2h|wp9 z+z4*EG4%Oy+hyP^y2I>_FqatvGB5ph&7wUo8=Ha;7;1QMF`n?X#^6xYnX&S12?=2f z`kjGyir^NS8q*dWW{zzg>#+0^5jreY!^?X}GVe7D3baSq6NCt%OYspyu#V68!oc3O z$|%Y|$2yGVNdoy}G-K+a5&s~?IT^~FpNYqQ0KCtLfDrel2h4)!Ve%)ZyNH=+j9{6O zM<uaqvAKF8<lAgOqAk53nNO;&D9(QOz=YB+*A`D`$k?e0gG?h7glG^ukw+mq<Y6pW zA<$Ca%&ZL-I+{V3mNHKV6$UD=TkE>v)l)}~d0-;pDPoFpNi8ZDw-{+eP>`{P2gW^# zR7DlaV;FZotWj`>vIHN!kpC2a_QxF);goqU5uGKOkbpRF%ZKP;Oq-T%1qe}BHFYE_ zCiAdjv$SM50gmu@gevK^Egxj~MNUkdCC&-efal>nM(CZ}o=!y!SGO4}-~3m_+0t)C zVG*3=B07kI>za)xVV<%~<C~onf|e)-7g2^jO$U`j@t{^;^H*GTdYuCw$){7~SZ*Bq zzXYZXN8^43cz-NR*%V;<z59E<Y{v`x=jUNf=NtB1>Ueq+`Cs17gr}8}Ha;tI9B==E zItvBMEdKifq?cm2=$f%$?K;0Q(%m0!;sY9^ZRUQn9^eK|PW1Uj>z|&%dqje+5JO$P z_D-AB?7{ea!B;M6*i=Ug$xLMAZE)$NQ5peKvJYjY1KO_HI&><V6A9PBl}<z-?@+-q z8p2Pakrr+H9*0hxhc2)a1A(<u@&0X)dh$XHf%#$NU5ZqZ)7M%L(JTKMoHvP#S~m$p zMu+U<%(A&=w8t2KTB2e$OczG=%7dlNOp8^0E1Gj+cBF}{&UAZ+615Da>J+Z#&w-g3 z5>dz|_mq-+=FkU(oK~zpF~eDYTwapz>YYHgx=BYOu3JSwa=*LTFyUtYwx@KP#*D-> zNVK;1%`!}ki(t=Pv={9}6lwnma;|EdP*O&T_Q0pmlXD$~4xpF*^N8vv;8iEMG@_WZ zg!xpDjEYFOS<p57ZRSX`z@3`+pfa<<+<|Oo)kc;u+Ab&Tlw~p0DIfpx?W=0IXq7-% z$dtIIkizs#_Rw;;z{s;|>M;!nsfy~?E@$NaFV_J@iYl*4g)Pk^_CHOD9nzTzzK(t- z;mzy_;Q`FJN0PS_)y{98pg@aMTodNW>^{Df`TtZdCPt+46Al`b|1D{qxow+&JawqF z6wL|cdv%PEp)2)YMMX+djBbFB1(Y#vBr5w+Y2TTJAWRFUV_6Q-ze`MVuNOihi14D5 zkAM`b1?XbUL!IU0qi~|ps^xhWlMSYZTdYD&6lKZl5ds-Rk~f#Un3P4LGszF5$dCug zZQpu-X}Fe-p#T7+f8}g2ep_%KiGrZGi4rDNK@5xn^@}4+>ZR1Mia1_CXIeCrOA?ZB zp{>$ss5zEDvk9z1YU@x>^5Sxo3_#3rwT2n7BupzPQ17*tcI6l5{g3sSlCH-#RPTC} z!`;k3tXQUe($P)(8;%x=jk^b8;)W(refe4iB_c5cTqj=d>Xl3uevwB2{tF%H&6!7R ztZ<pL7h3tBour80FG&?S8pbZ3|Gxd;G#fgdF|1|g8Yu|q0e9JPFWvF=YnI&iL;85j z&l&pQ$nR0Qv!3)WM=e6Lj3&7hNBQzUp|yTRO)mi<5w@%2G>0&0$q{Um4-hDeDKATT zi>ZvWFRe~0pdCAI^D+ult75X?B+2*XwC?JF?z11rwb<~3sgX8xfE>sN?hvM02BEW@ zxXP>Fzl37d7Z1xYd$8k55U3o;=#7`lG(zfQhE-65EgnYn1H6819G1?)D|z$61;Y)~ zi}H!x$taG>?nyb9J2mHWRxr<Qi#nAmQOgv=a-;qrT$OBBhN8W4f3gJ0&jKz5zsI+- zH;+Y@|J?Chq~0k&5ABn8bSVW;_E(>H@HO(&lztK@4>*(^UQ1LFmZ?O~yM7*QFHw7r z=yxh7EBpg64|5h}vv}T3#Y{iKzzTglhwr=%DVq@tj4Qizi41(Q2u`n*uIS+1lguxc zwD|`z$y0SM_1dCOslFL^@x<33SF>I9(B(Klrlz`4OiF86@CeoG{<1h`4xl^pep_!z zXpKffJ~>%W#WiA{%qQK_=J{W5v}we=MgOpI4{V}DnC;}3l>eqD$A19JNp&kn<krM3 z3S<E%jaV(1P*p;Q=}-&8U~Pu5rftM5Szx-k6or8sWJY2wm<Sb?^wF(SVQf@AblRFJ z(h!gf0weeknn_|H9oaZ)#vC1!jNCAvG2JBNjIYYOa>Ey9gt$F3hz$*HvHtgP+!i2l zF&c$V<^GOE1OMD#+HSlD$|BY;{{TAa@AmUC64voVErp}P@?6?<rmQdJ!-0Fb35dZ4 zvp109bJ6A$jxkfXlOy{jC^2ogW7CC~-wIv@z8{s>&+KO*xE9_9Q8X;J<-ChX8~fgt zW3ZwTVsu~p19YIx$KU{?j_B4bb5$|y(OmJr#9bh}84tZ19WUxLzOP+>s)ustDgF$H zLYHD67}Bv|Y=t$u5P~lttMSr`9}!k3D-lHmXM<aXhTh~GdT-#c$^HLi1736|I2}k4 zF{!uVFYM1WoBVj@C&)<aSx}3SdRYIYvPp9P=)M3)T2@f0Ul<#D_m{kZY_f?x@?8-q z3{Bgy2+b_hYdhTahk2$VBl*>90VRanLiYP&7$_AvhBAj^O55ac{np2(c|Q~$ft#%( zFnzSS%51!SAG!xV+sTU}@>_HBq+uMQBEHd}fwwA;Q$wW_OuT||DiUm_G^2ZE7g0Qa zwo^3fPblOn5PSxP#F!LbULN7+A<mG9-{y|$qpKaWi9fw|y(iu={0W2tH64=i)5fL~ zk2Q)_!7#bsZT7sUl5BiN^J6n)ug!>df{#m!l{u8weSCa8^%^KwRh$%LEM`;|tX7ZF zkTZQ;H9dCL^Od77d`AhFS)xj+R(WJ>LZ`3sEq=jzNFi-5zU);Ny8eTC2tNWsSeKUC zMKi3>vWQ^lcqOtVb$rl1r>l_n5-i>P4g+XMbtSr1X5wl!hihAZSik(Ad?>a>nnkL< z^>=e5q{wbtZS0|UA~v1UGT-u7<2uwSj-NZGsA4A~{5$lcB8S!IRq0#Wr~AxX^rX}d ztNjH;W?q!g3J7}^>7Hh!`2rQgTgLAVK32HpMv#JAi6$YB!ynQ_r;6M-(6!qJP#l8y zJ932%6iPwEQ9lg&1HU7+p{^O29*cnLkBt{v<fTqXS=*?TNt4U`T5%4c5>KIPiDf+r z1T);7X7=78JQQOsi|qxl6LJjr9gOmn1I-}^I@<Z3iDSRp#LOxXjBwF0V%#R@c=|9V zy9G^!MjpZ6?-mvoSYCFjf0F*Pv;PS&EMljQ4edmE|10iNmt%h}X-pT-HuFXAU3th& z;!6BlESlW`@fj0msscXzeuC$^YCgHWavAgTp}>7#p#8_Yq?j4@wW-|&j1~&uDk66| z;Y_q7IgOo&xWX>bvC@f)7Tp_tntH}FIfZ-=H=D^LbKM1}Lfqt$wp-C6PCSA*VQjzl zYjM}-*Y+>0@l&s1j0+LlD<`HAh=W;F?7tdX&I@W8CU1LUdfr%3XzOr-`Q_ZTd4_<o zVqZeY=DLgz3~D!AYy|RLcC^n_(U$TQ6XXdb@unH~oAZhAQ&PCknkmEEj%+<oMwS59 z%3@YiZCeLIOY9zAPnSlFILw^I!VY`^Nt*bw#1wmC@GUpeU=dPR(ad<dcEW}yNus>j ztMtTv0eR9MlL=KNJ0lDmUN55+w^Jvblv_yJ9qtwv-}mas^wnvQfoT7RP2DQ>v2i2@ zIp2LjpGBcOD0qzihXV&u;$UV1L_2Y`h7Ni%40^I&@Uo6rVsScNfAR{6Hi)87BGcmJ zuwb>Y1qoVqaL2_H#D&Nji&?60qq^t9b*1xn{Xvl&4={)Kg=5j&h{<dNXSv8qW_vP7 z_b~UML>z1!U@?Hy*-~1LmIq6u`iGE8)MV<<C^r6BH&=8}I}R%@deiZ(4Fxn4xh}j@ zF<m4k&qaUEU>J)z7xF%*s>y4)Nf3j%%=b9s^+}76<av+wvl`EXk}q|bl<N*wRuV>( zS!`@lho)J|oOppQ>0<ARf7ElKf84@s$fS-om~m+h6?TuXYW#{^1a3n|_@`=N)qID( zK&bCuqzfdHsA92ZXxhsxpGECe4i?G1aw-8R$|v$5NqS{=cz=hc4rYi-r+PGway5w* z5z8*e=u@M&D^s1hkeN9}7Kz1LF;V3zt}4@?g3pHVo@r7}w#r(c;~px$R`XD?d`i@< zpv9GV6yxp!Qps8tA-d6|adjxU+%PIiwfevaIA}uD@it<%&<(mJa2jWL@XK!`sY(@l zMRc++EPr*A&mG9XRT^HxjdM5<<k>GYW+nYEgPR^?pSsAH0@)|?;bLZ^aFcz5o=+nO z-W;Ijv@Zj2z0rkMvJ;Uw8YZ{Mhh8-|yT4u;VpY(-3S&PrN55qZ`AzJ1AKe-{ztpz* z{;#Y5e=Y=$EbjeZ|FwhF_stgK@?y_7HAFqZJNdo-if-ld7m}=X=4`h#UaS02xtNCM z`HAqg!+cDIdHyUY6hCX3i@4$u;MnNIiE_5Z7c`5xR!V77SuPB1H_N20bcq(8h6V#l z@ch%@bR<I|N*pepxLrd0>(PIsT6)FzdATH2NBi)~xvxL0hH<})nTVN&+F`-QjL~I$ z`3Tw@ghG#$&2G=^Q8i*S?cnw9KF_P+@^pU<PAOE{1REKOfj*LrDf*}Ql)IAj0Q+5U zgrJ9w`)*b?vk7=}i*GX{cg4Y>Mx{-TtKZXh-c*W91rEA-7i4vbX?DA;TLp{uya`Lo z{_M7@sw6X=O6zFJHRnasEx%Ws3eNO4^AhwwA-Z&aAGC$&v!E&90P&hm$*|3K+6%`n zCN+6wG#)H7yUFL+9epHltp{l>f3nZt^Q#!KVjeSUDU=l|HJ=dz46}r2b^m+FvdI1$ zy$|-`jq_`9Q(zaqFQw;0oDj$Hn=0{~l!G7azPdWdxrTkrG4pJDCq!kk{{W*PTno3j zc&zL`E*cfC1G$jEt90)Mr$V5kv=%!5TC|iDO1uA;#VuQZz>}~=D4V(n0s1v@sUk<9 z6~zGAsKay#u}PO+kG~DCa4tB`X`Gfd4_uX=LkcHX4bJ9yIatXQHNLuOAxmf+<xKxg zT{S*4`ux@k_u%--DJXPGH&Z6w+(<Y77hR!;hMCJwR0&j{=NPb6##7iQ$>=17CYloW zt)eF=s<LR*i#j)E>j+EMOwuw0DIjwQpi^&O2=_C_1bnYYc=}z7WD{R^-qbKtjuY-; z?lIQ`P!J%hyvQ~Q5McA8UOzI^>G39Oy_AoFy0U^F`Vt!_RpMKZWPzs<dR?`PRpQ(} zhyo6n`%wiSWNbIAi(S&ruf;)yTWd-%Ta?>5G)Aue?-v)a%{KPq&Y#;)%LPAIZUfA0 zSu&L}-?r;=lw|U47use?WUYXkN{Mu2|INNxn$X=;J^^T<z0=)`5LBO;{{V}#n`52+ zv||Naa4JI9a!g4_G&YR!G*XsZ1#=I;+Z`Pw)U~M;?;p}iouvvDzqww_ctSk4Q(>bY zwGDe1#Y3KaF1o&bt?o1lBpcZ;z3334*f_9>oi2YG`31Drz0K2{`n{ZZE$Df-VE>i3 z=S}cLNAZA!Vm&eOBbc$dLOsIjjQ#o>!#}`v!pg2UYMJR(K;%t=b3CfVbFpdIP4G*x zY?IxdA3pUiO0`Xf2&At3;EN7(SGKa6)|&13ZAn2)-5{%NX(@qmo@S71*0PnB3Z0;2 zJS1+{Vg?779@Jte@6ljnW%A`>5nND9COaEC{INiozcBMDLNN&1MyT&zkY_=3Tq%e| z_W%puv1{<bK;Wj#a{HLal*vW}cVMuCcHf|&5Q1kt&>M{>1yya0*oMsZAK*6*X^-!$ zF<ZsP<#8GTj#rF8>)|q%2UIz8RNSAXMnYy|MQ#)O@xY{CMCmTGnJq4QqW88wcX8Ha zR!wecPuv@EJmQq?5O-W&I-ek0jbJF*Gi1X&*Mi_|s2yV4pn!21_byhi?XgX7x9FCi zjLTGi0yN7n)aETWZnYnx*W?-dNQ65%G(dh?KD7jmnX{$MRk;i#F2B#DwguQ)mPO95 ztEHn5TG%OaC+u{vrtyr&(q<GF`ojlP43wiz`0Qref5_eHUKTgHX|htW5=1_ddmDPy zPr>U8mp@%bnw#AB^7DGLX4Ornl8aj3wh9>jthGIIzkwUMxDlkWuF4JVnE7!<_DM9C zmS4h~Z^;LM_&cPk3|)4LSCX9;SJqE*<d0bt;8L1OhtT;b;masl6k#UeZlg`ytrUcn zEDe8(eks?;*R?SViTW|bDj8qPd#w%S(B<Ii)`bX_^7oz80<`<_yy9o0t$)4Zk4g~C zC-0WfCs)-efaX~o%=Zsqz@Ursh>ak}It4!YS{vwt3#Z@BrdR~t+5}UCx<+<CZRemb z<<(=ZmtM*eGyl-EAFjU`sa3e3Mi;3f9MNyvne7%jyS7p8m?;rwtu65Ni+ze%kX^Ws ze^?7Idwd~@WbHc0)jH}y-A5Eb@1hE~BUXMJrhj2|siJ;&Ao}8#mODcN#SBr%vVM|? zPHZ@#8Uxgi8Rg|F58;S%qBXRuJ1<U6bYEeo)r|rhDXvCvdHi5*6{Kz>PDvJy7>IZU zWc>s1x2tOD0dL#9IJ$ETT$$M7+DBxevYiUJ+BV{|nqTL+Yc8x?;jrkVHKy6fH)0K7 zm{LRaB5BkerlfAN8JRgS7nwU^Gqa~T#oL5e-qcvwnVzFIa2*w^;G@0*x7Qflqg?8} zGQkZkpZ_j+NCex7XHgU)47VW^A#4jKWWD?MKrPUpF*qXlKPT)%1`eo+X>!eE&ux9a zZ8yaUeOjr&UVtGiiy7x7IJh5P6`F21z@r5lM)YFO5o?nenE;CC+AUv=U+COBBPS6* z%MYH<UJevu{N5fal~BbKwz_$pR<3mx64u^o5nUYK1yDt~({tb4XI=s@A*x|Atgb*_ zK5FncwCza+BXaO&1E{?54F}$U`GVp5{hg(reP2{r9p02eaiZIIF$9b`ET+95{EH1l z{E>Nc@=lURWYRqG-yM&isqGItH>eP(-LJkL1_ay+!4<~3uue11PTZTmM5Zu56WmwL zVHaL%BOlakl3-z!E(lO?_H1s({Z)>ld6y149b6miO7MWY#enL);Jd5LrN4z%?Za<e z!z&Kmoyi&TbDsyr#PCbL{gl%!umT)%|HQW^P!^#J*aw%Gws(8B4WG8*ii5c^+wh-X zKP9k(e}7InePkcJagIFMCj40;T`PBU|Mcm7Fz1><A$FN~2@X2A6w49oY~o#;Nz-<h zyF<&T=yWPvSB>~hd|1YN#w<Q2kCJyP^th*3o_3DW`mEw(vr+e+3aut3Foe$xeyg<B zwICM1xUR8CF{7bTuUb0OT8K13%BX}(Y)m1z%6geo)wgA12lsl*)0Et;RsGC9;1ROk z4Fxzwb!K9|UPH}g#fIz})@1(!pwTDCzy`+0rzVRJUQKL)>vee?A=J#r*E#nUx_38Y zYgKH1^YzbxK5#aH6!P!O?ukzp38A*GJHGR`T(#*QQ}p8oO2;)uhY8vBF_r0W8WBma zyDIx~5(E4WL!b1R4K>)48CfKEeOZm@oOpV<zt31Rn<1*8M?|;H(Gz2vf;NCPCXOk} z2;}BXqbkXE>oh5XQ|(Mu0DZv$`zr3fHu-P1UNl3~?h{(<*2K`^?%m$O%91P}Z+9o) z20T!6GWRFw{ydlOZt2(8w|atNvOHa2cR*#C4#bCwt9-!w-yhe+@;`-$>6)hWA`)WX zeuDKzH-eN&ov#!lx1-@AP$7(O^vXIyb31Ly2<?Ku_TAo|n6;zU1*keMxVr=|9VpPJ zt%`egqdWqtD-dGjUs0E*BnM=l0|fr6Kxa@Xw%%5A=_W8kQnxQ`1`8NwwcdBb6(aB@ zG@kt6{|5jsxRK>%xOKljp42?v{^-V`CC<}SjWn*8>R}K$Q2Ht!r)V3!dA{*ERsa46 za9L;Gx1w^Ao~ygioYJ`KdxmBoTIE0m;-A)Ym!K_@L{Z%SKBiwI=>AxC@3yx#A|bvH z8R(}cbo%^M$~A}(f%zkIOpHxtZR$?q$&Y$0^bcTYKU|gBg@5sQbiDe&{Cq8ZwYYJe z&{E#11TOZu+<W$vraYg0D)1&O-hlY2<!%JAiL7}hCEqQd$2hc8{+L!2m8Rhm*RJJz zGaCBa%De?WeOc7Tyk4zB01-nFhw&|Hp$HaIr0THZL}$h&5d%n!m~#}M(Hx(ptxfIe zbws35y1)&w=)R|E=3xGD=lWRl^q?uhB}*8&`0e%I;kMb@-y1$ujmbs_o{x$CByQYQ z9?hUL%E+vItGulD0D#$V;V@HJYJP=xlT<=y7bzawZfn@y8r7)j<<jf(9CcJ#+%`^Q zakL1Z8+zHTKZlKz0l&gBtX)W5*|wjXWnnfuixr0ogSq`P#qb@*S(hC~OU;B3a4U#y zxyhBVvaV@tB;)J&#RW)PO5ctY)f`A$f^ht>gE$zPcfEo8=m(xAJEkx26l6F@BQrKL zBJmLUGlpVXCIWR{t&id!lzhd4ZEASw%C9|NY2;{i@Gfk<c$72QNo15TTXkBUpmHOu zZM?E>nCl&$@+@pO{^r}>b<?)vQB2d#*4ss0pkF`AB7|W4RC?hibS-(6^3*9aXFrIb zcgA^%rVI>M-N=m9w~)4~g__4zL0UC@*6;D3>8*WSYBpFiv~6}&{*CN0;vgluN}N?8 za}+<gk<5ynX#AeCZBVbM)}L?7pI$6qThtuVpc_FC4X7Kn$03GyD<3eQB1dI2bo$z% zSajQ{v(d{>cF$T5n_79~r=mNkgEu$8AB756K)&IJpH0buWogv$j>)$O?Ph+EKiOFY zcbDt^@ov$en2Iri_cjpE?~VJmaP6x)veVV5;t77m9J*Y`&Wb;JwzC&3=mQLcPA4DZ z_zWXXo=?^EMSBy^AIda=^-TC_wJxf1^y=u#e5z<Bedz3#(o{5=cSzjd#7*OLfnBc! zWbO@X>uw+zE+s?kNLl%FRZ6zFms6_3IROjmbZuTNK{7sG%><;n>9MC!7rio0UT$yZ z?-Q$en94ZV8DVc=DU)0~LqjK?ia!wN!a0gU>uzq2Vmpiit-REA)NLO}HaF17-n2K9 zcMP}NQ<ZWlKGEPDT)(Pf8p(OdL_rD|@FYorkDW;tj%5g;d42EM?s2`>DVNv@Ak7ov zE=t%bI|*YiTe*JI$Rmj$?eKNkE3qE=^RW=e+xkfYR~)k`Xm8q+x$!wPFcJRf#F1X$ zkL9eD**+MzT~E3t7ne&yL*n3Pa{|G}8vKp$TL8F{#nwJBkB}eNP+jmT_SKEfo;5CD zdgcA{e-BFy&KPm4nV;tmX7PK=-PdD=9*4CZcbZ$T^bcmR2g@~BWBjb|c=SdH3rDC_ zP)xCBrV1Kf5ikYl&=`sIbq3A_Y22bR18kIp;n)BKbG=|S+H^`g49d7*34DB5D@e2~ zI~wCk9}#+$u-#O%)vPR*3^r&wsZcDrlI)ygs&01aG3pS=<fdULP`Gj!N43<%;HvzZ z70kT_(14u|UW|ahbZ@t%2y!o4Oh>f4WHc?TcixD%P9HesN<QI<L|WVX5UPi&t9L2L zA3$-4eJJ=rGnjr^dy6i?h~#D2ApLyt#FO^8(af)_3e<{JOsZ_o;~tQbFxlrV^nqG_ zNF4HWKk{?GzA?$HJkL$7O1#&^BrdtSR&B#snm@55RIRFH&)~nW_Z~0$^A;k36MkWM zA<R){A4{mXp$x!B&T#4BZ>?OR`T3PTGBShEc~5Pj(Ou(;>I^Ii4LYSG5TBRHKQw7k z)i~g>HN3<A2O#@Dql6+PW+PZ>!eK49mHu$>Rx$FdmT*-@x+N7y`>nwsJ)5#??GuHa zh?Oz~C*`k~3JlnHVBfU~gA<Ef#;+jI9NrQ)joodzGGnPkDp4}i7}L5A$A%bU0S}1N z6by%kr#MI>PW%-XV0H*C8xz^yAR#1$VIVSLg4ev}X5E`JsO`&G3>uCkRBV>K5`i>k z8Ygq9D@gH2NAMffn2LqYS@Z(H7n%^JK#vBBqD6|rW3(I*QXr4Pi>X<quO<><8sTTw zQ|;RSeMgnW?tN^I|DeXI{|B%jFJj8ofeX}r1|R0U=}VEk?rvPmX~^c$zy0+jeI|i{ zg#zBM=#vOzqZ8CHj`K)`W4l@$@{J5W6%ztmaj4eePpTndp<R&pC+r+8P6YyL9nO-` z;v9oIwcPSXY$%a>U4TNuY%qG516xg&HJtT`y;2EI@w?af&43u(9-zRpydrJq%uY}8 z9H$cz>p}tv4U$t^Zv8fstDVnW%(oe5uLK*5+h<PK)#t7k8Lw{G8utAA!Il+%1;w|I zdqt^uAG)o0HT*7&zzabJ61CA>RjEzko-VdTh}QQLg!SKwOa1OOn9Ytq%NdXZ*1-1v zg8&9Ju+9Mz0tzg70Gs6hCwcgP1rIm3Xkah>KA>_zJ&Vzth~wV>IO&6J_l3c&f+-p{ z6CY0%WJJ`liPjM5+Q~s6tkvBg3Q>t@1q9HDT;S%MPx?J$qGfDr+{^DKS5d*hCVM;T z`X)}-iV-3d)XEv&G1mAZElv9i6!8aFy{0guDkKQEB5uEVZ7m4I*hQTE!PA6t=!~-n zy2@KPz<eA!5H4j|BuX7UOwKGQ9Dz;~@ki9UDOpFcqDEojJSGq}D+hs)9KFWkR>hCZ z(LX12hgr{w!n81Z7G=IY^!JTe7{t5=M}>i-zFX9R9b~+Ee8ch~MK9NA4N>*vPffHE zYF4XFZI*FFa&|y3HZ!EfBa;s2mYj6ch!s&iEgbdVPP2afaClC@5BhS9bEMEN2msYu zorAM^%{N4>IY@7TT?iN{c;8*}yGcX@*J682MRGgG@aiDzPU`(UN0Usj1&;o>kOsmQ zRr!~o(AxB{X(h3x!K52TX&$7{0{v)AR~PTyROIlTU+D}me3{Y=MQ!2qUwDN)jq%&^ z78#C!-jX8!091?c1L$)nB<rjkz|+Ty+N@-vYgwe|LB2bl#5qLK_gc}U7$oIW)w4%l z;|6A_v3@vd*%eqPhR`sWU9Hc|D*4LsE>{7ovz=W6fx2f191ahZ<)^4Gdm}-E{#ivQ zmGL2r?XSOa?wTpogHsfFG%<m%vEQMXT?in*{Y0Cg9T?Tj#i%rDb)-KH>6V7<kv_pf zm;Wvg_!T?_P#498uE-FxDkcH164<->zwGTqR=#c!H6uv#Z18|P940ft@MO^nBd63j zHvG&)m*kAV{c;asP=E?mVQN_QY)8)~;$)1V>D1dhjW6zHBJIQj0r<Yo06V|}@Ll>I zU`QDh0zO<(cP}AtI0HB-Z(||`BJCRXQJd~+>_X@x5s;G1ncgAtMSbICjZ>{l>Tgvt ziNP7ygu?&<!yzN>HcQw7canxSokBN>pYw+BxFvEoA=-b55U{5Q65-lM@+lNSW3cP< zK%WaA)cG+H*Z&d|Hf#+VJw^FmXFO~t`vd*@d#|Pl3^5<F6L+Cv5?d57xWFrW0XaR& zogntQrS2xh7@!+@N{XodEutA;{>*p_iWSR+Mk-5L0lm`2(Nehom&-ZWE#N^4m^&Nf zUiim6q6h|NAKm;Y$VrY<KrEOd6LT1Io>`@E6xrrGpD8jflXx#WDTOnH`<ihpb4B)X zs~^NiIA9=tbCybZX?85+!%x}1XpDXv6_VVv5O9(BTUE-%LFw>*Q>_N~t2$RjS2EmK zV5hqCx0KPS18u?HR4&;yj&0w=0!M2TiA~Y-X{8AuZM6i?sflmPWAqasaXEL_K`K<5 z0s^?B7rEZ?R5}UZAQ<pumChc8@Zz%F-L8Y<JhUOQ_v+j2Ly{>^%tGJbJ2J#d`%@hV zyj)M6nwMRufeRmfvKO>$6=ZHj`=d7>LUl86<d4dyjSy)F;77;Mv~}WSPuxO}yroeJ zrr|xiQ_5e(zYy$scZZPml;uDW<L{{<L>~{WfGqd(N8|d=VpNrE#Y+6yiZad&eHZx} zh!}#-S^g}wa6w-gT5h0@M&}VZ9~oIFynF7z_$!bewuPI@xma=CzfnJ-N|(}GcBM8^ z&)x2sK}=taMbnxXT$?nVkI>~{9&{wYLyLSLfd{HcKp_6=;r<7JZ80uTK}SbNld#Gf z`Q%)8DKmBIK86q?hq>z2>?ILa)nFc+g$VZi2ROlrQQk_Y^(Hk%fZh#EhAxZ!>#vR1 zPbfMB{sL?7aQ`88sUcfeL1eNN$C<=O&XVGi%htezk&0b@WVYCg_lHZ(Vp;2c?S(M0 z<9o6ly)=Ho#=Yj|r7WdayU^GeZIA~4Ld$EfC9iRvCO%6b5lSymeX*f{II3m``nt&{ zI?OX}A;|)-VwHg&H<W0AM_4Y(T2ditE$pWit#S<&2C6jo<H>Fk?NY(%(?sP>@W)@% zZ}Yoo^fubc@q;T4ftHCARqCqn1iH?nU#L?=Xq4+Wm$_{ZzGYaK@LZX`K<pz{iy<1A z#x^0J*^!$<uD;{Qpyq^Cp8Ro90<<ZZ{J}*u_<iQniGA2GY%t9rZ1@gYIB)Ao9PcdR z%@@UR8_a+v!m6xr;pYzpr`<JR<>nq(pF;FJw4KhLOd!<6Ru0QFYez-AACf_iXv!-> zCrf7d#ac_9ieuK=-5y!Xzvl%;vUvHnzv>dug%ReYd_wWQ|L1W2eA9&G0i6*+&UU6x zPg_nh#3KHDty8Kyv^=%KoaZ{#klc5^cQqU3Hez$Ro0m3q0Nz}=2x~)hLcgAnNwm3z zY;<geS{cQYBT&L^b9&|14?8}NxGgpo5Rvt`7xoZlsf&<Ah=rExf>K{!*&qlI?VG{? z*})1W3P{4>I;lNA_vAg%a&u#^D8T?}ORypkn~jGq?e=1|Axzo~RYSn#O;hC$P@e<H z8OrbmjZevSFj80YL!v<lJcN`bBq*6h^kEp-flEaTu@b$96Zb-jJlo7wf2o7dBXLS{ zrsm#^*d<Cw@;~)13zZ_H>Y?w*UHg-;3&y-O9@;zcqEvV|W$duX={%Bz+hL*k2_@V1 zGFPzaPeo$WLUR|eZ*@x5v@rO%Cb=<3Z9T?{V5%LsA%qCD-T;-exPTxv)$vew>JDE- zTcStLFmh#jig>8!;AAte60!-}iS@X0V{Df2cmUfuSgTP7vF?BaThU!BQd*3@Xt|ub zTsbiNLaCbR%_SD>yZGS`)3qqY<}oKYOwJN_`1g;qow!k&S>$e0Ew$RT6kt!4RXH~8 zL|GiESbE>{CCcQDRt1SuT2{uy>UV}M<Ymra+H{SpI{HyX7N*3Wk=V$0z~cIdr5<z% zo(y_k@Od-Di;~3rfh!gqQ}_am)?YCIS3D?vL@Ola&u=9$F&G-4BKC?({at)i@SdxP zHa``MYW(E+iKHlrPF50!BE$<+l&jAlLuOxo!4C+X=!R5aEFQlO8kUC4!y-Iq3>T(5 zNTg1CZ;B8`a*dNdckrBE3qDOAQY4fdjha6VR!4@bG{g@1{|h75yI`R}!<LvGrSnbw zph{`3=r5Y@4DAC%B5^WkP8FpqKgsna;zYO9%P0lrm!!G4tG@koPnhWgCN!vETm%0f z_TB<2u4Y*noq-u#1{mDkEw~RbxCFQ0?(QMDySuw<AOs7p!5sp@H6d7ngd~r1zw_Vs z%U$Q(x7NG&-Sz%|uf3+bW_R`O>fODoyQ+58{La({()&{9kY?G*uuT10La-fXXt)f= zHRE?!f0TvoJ5et89zzBLK%)vo7K6M21&x)?-yTFVSav5XqVt*HO`AWqQ)ED$ztJlU zgKRBbU7M~v)<(3L5#52*d3pSO(sza#Vo0HlU!Ef{AM9n7unTj`n#I|VS9!cYSUrtL zAe1Ofy~rAjdHX4&K~#~YOll?peZu@W>W9bBPodpk`46WYrvXfPDia2a!=<&nY$tO) znH;`BHlh-3g_P^F*k7J-jSuF%bW>Gp2a$rG;r|=;^7qVhL3$n2dmwL0Cw^VKTUCsV zmaYDLi65KcUl;$XWw3x+9TaEb{Bbv(=dir{?RDj;mm}l9HsP<L;{HlqCTI+c?mBx) zdNasQUo1(>qk(_5;UC=7{f;57wkOp~2f~Z=+#2*!^V!Nq#P^C`Lc>wQ!dt>9C@hs} zf01f{uGEeLh=-Fox@zVsW;o$zJc}9smlkrb!jKZcL$5%-@PC8a=i;e#TmgVw`A=xe z8=dFHh_a!(4WXhmHc>y^#oRTOD$^AFz5m{~|9v0)+jafh<o#>k|Ic*)p9}xX@cS>; zB}EJK6b8r@{*KtW*Ti_@2H81Yn3eXgf*<vk<~Hn><_J~MwP?gB=cwvzsf!8da~r7y z$)eA7RvA$Yg4eTHXVWF%t!T*{T8_LWuFXJgQ?y+x?j8IK8D8`}8yUf$aGVhR64$2T zNy~XHLPhdK%$qhGG)15<9rj>VRpYlm06O{=g{as{W;|YB*qaRCj9cETzKNb{qV*fj zNE`@NbfSkkVnG@?qK?-Zw^Qx@yuk7bv1UuFoPVGeA?+nT->v5UgBpkvG$f{Sf`h|^ z0t3KblsSc~=1x<|Vv!DRq7?Au%3~M`TvkJwtYSju^1*baZA(<73^*i4(yje5lT8U# z`g|_uH5wI)87v;BF^N77UR$0j<C@i+lDW|kJU}rwwFjDcsbEutVm^kNsAOnx<C5@E z2)hA-;wNTxDAgap&N7SEU-<u-N!2&}|0lPtzNbSs=YL4*E(@y@U*p@7=Mzv-lJCV@ z<XgPj638E+7isv#Ad&tg%Eh5Ga>EJW=ATL3aGT^p0$C4_;%>zdAdBInkpb3xkY3=+ z^GSYGDUWa7A;ucB;H4>=GTLT9rS>eIq)Vy8+d*X$fb>@Dww0yB#jy|Tk5lbJj%>5M zriv|VpiLR(P6VETD>^P==%D+QwP)>Rstrn=$Iix*1CR9!i)1{~Zw@3Na}(&tT>OgS z!7M3&HVZ~dSH5Pym8T<bn2)-g1@81Z?1K)0F^q;52M@!&zGc7}5tn-x$4c0_6=LD| zBrg!yB~lLQl<EGITwCDkJeoJo5`cjY{jx1vu7MwJc4_Fqr>(jq0j!51B88>zL($GF z1y!%Vf`SP=x&>uQSmnH_IZZhQ>nG^D8JtmYEpLqYvZ+QH5j0(YO4Fe@S3L(f99CLJ zxnRKE0Z{L){~)HY9+m#={JH4+qgOawO0mDzX-sYJ=t_jmo@PN`24P>*Z0eGaKN%Q# zAyTL()(ogF)t8G`i_n5J=*38C>!KdrhsK{E6Xl1lTZL@`(4k69SGnRQ!+Ny+=QGlt z;f%V{e#>mx*A^`;!0zHuRV2&-94#@RV=R&elZEV@Rk_g5^GL6zuppJt7((?7u{KEn zYnjx*TXmLx(Jh^DGVYOrxv5A;&vRLkRm-s;0<263LM(l{>-x`PP4KHQQgP*Lt6cpx zzCc|3eLfP_X&f^UBzIT`-f5`D#RrQh>ezZp@c#|5`B7r?u6lBcbw-n0((t=v%m&)k ztRtOT+f)cO3Pa-(&N~+wRsDwJG|`-cSq49zi41fWUJv&54+$>Me|36@>74B%r{AGT zsBKZ70fB@VS^_<`)u&AL#Zt)IM?+s+Bsn0B&~RWe0AP!8ZS$|y6e|Dk228k1*jklZ ztWRyU{-_TQWPAU)J@w`H!>>ZG35-XwTCBe4|HF*J(nQ_nJ<nR}54PSoPV=dMk_mgC zrdxGw^N*^vB>$M(E0HGlPitf4u2%i{4;%Nd1Sq6bmMkQl7XBlG((;W6kkeQEX|D>S zpKMAch)<G6|DAwmYDmLP&e1HtU)yw{<Bd(8==y&y5bM`}KJ|MM%{s4PoXe2_VWl-} zlfptC$;eibPoyQn9sw!LNw@FysPR=+kJUHgf09WyU}C@GJUIS$6#bX#*h`~769gjt z!&;SWO9e)XLJI$B15_-L?z8XWd-pkgr?y}G!%POGZYp>6!R8;e(~<)0vQYX5fGEa8 z*L~}5j31Uzx8?e)6H+os?>9#th9s{hJyB+i2SJpy&_x9WM0SR5a)qSe!!40EgcAoL zwQeH?>=%ak+R3<GqR8MTul_JY7SeIL$M*Ia%jFaLib$8jwcO#(%U28$w#Vi^WZagf zbeRZUCln0LkgSZI$`5?={wh|XW;|H9!oHYYdq_em#a|gIbp$CYshD^yb-`gEc1kty z%8L>{ZI6FK@V}>1{*%g#?^&s!As}M$9=#y_iJBsJq~{B#+~>1_7qm_U1cgF*zcxc8 z$D?SJE%|zT*ua`gK-XH_-F`$E0Qej+VvV*@#7*!IVB4DalHgO?8stL6#x<ZwSz?F- zPBnftS*6g#&;sDyR>Oa&cr1aafL?&707RLD{DbslpD}5z>}U;9MygE#b3nkoh@_*X zON4R@O`RB&c%D({g{lG&DP8||tjHXQuf2oSY4D_p0y12={Ze_UcU#OUdp^<sDQ|F$ zObnlZiK>*fFCWu{2E7=%CwiGJ(c-yxVqc(;L<4VR5=|c8{Tkw)OhAEX--T#@5JCnB zXvaJ;-}kX(0l1^Teau*dvFl4iAu-5(E!Zz^sp{m>Vv7ycUxk5qb=G*NHw7ZVucf}r zswJLWLq|q0#<c(kgm&LqD}xPMBblgivENwNmR@6kwm7!)11pN$-3-*i4Y6KqzbM;U z{^U_{yx-u;haE_Io_I*jUJQRlk8}I^)Yw&v2m#Hr@?JRsK7j#LB*y$G8y`x~&TIWX zKmQ`=a^rLrBON<aVQ~j0`vwImw2pP_m(3?@mB`w`gA*>~o*Df3mG}h&CMo1IoQJXB zH+0n@%AQC&?hpH|TXu5J@UKyi)9&MfO#azcbnPEiAEHh~2Jl~%<k=G%e!Y*vlD#~U zJIKCNm(sJ{T-*W7&r?y9-15Ma4=~y?J6BnmXvTNPRRBUtzeKk=09CAT-<QM;-#=45 z9W`Yl%qyKC9!VnG%!qEc4*_rPl&}x*1mZ5F`>jmj!rWD`VvR3UG*nG<e5h6)tG<Hn z+j}gM4NTY0oy5RvN=Ni-G7UNOgw)6K5lhwXaEa+(+?WMsEtJ6z*|_9kYqTc(l#GJ^ zQ_1P}tAj<iId2LAO+>fg33PiYjRFmG$!gv_r-THBja|Jtr1Ibz+pI2WI+g7^wWzHm zk{mCjCE2Z)jY0T%tU;O_Kgw?xCF59M@lFurUKq)#p#-Tj<%)cQNMk<n9}4_5D+SbW zyyNK$lGK7}`RUI%68`{$jfjWwZBZO-`+ZArnlq=}1hr~lTO;7thnK>Pwl7)lh{#BV zmN={1ACGIjgDy4u6}4#JdicbZ1$<&$s5-G~Yv^?W<$XA&52;CRVBeGqUq-P*M2w_Z zT9%tjD**-nj&yY?UDmPXb-+Nv{zVakODCT~1OFeAnS?LbKS@h0Z7W~niNyqucA^xO zPr=JUgbt&Qgwjnc)PdR2Xzkni84vpVx6iuEUquwe(^n<Enz+4*9-EYRjD+7R^N#b8 zfG9EWK|Eg_DO9pfQA;n!BJWQ+dliE-BdAz9wHKWE;5V+eDF#(p$DyskN12(VpIid= zw=V|*opbdnosWqjMg_ujDa>4g{eXNsqz9F*Z7v@R|4MdEO-0vT))%ilX$<Yp4K1t+ zoLd0F`I%fjMB^ALTMn%cnD3mgd~gbn5rSFK(Pj)yFGjyB8&p=N?+)r%cAUUFmsdK6 z_oaa}gPQaL&|Mkp?eGjeoeD!>zqv_k8A`nUN;$8C-ld;TZG)1A3PIX_^9ZktPQj^N z<u&jpjBfsP5tH{^pmOqsrc5|t7~e!sF~XETz&C9N4Qlm{Uwd4gf<bc+|HWdkb|~rV z_w8!Y&1>B20v;X_cx||Yo>-l#O8)Eg+8YvvZ=2_?Pd_8&+D>nyrsFWhG_L8xSWTZ* zfV(4-%?H|&_yyP@?D18QV4Zrzq80lUtt6J(E5Htb3JG;>shk!@gF*$Dr2O?Xa~IsX z_OeAVpF9W|9KZww9M*R~hibm2T)*1Q|NM&}N(^MUvCE&w39Nd(mh%Y5$FoK7HS-zA zJLgdlam_btCZSlmE)G9TZXO#m0qu{DG@zF5QXdd)0FGqU>SAIcg*gU+cn<AY(FuLW zxRq1guZco)pHNaHM@SdF&nUM;O-Yy)DI#XrSIX~q)jSvF2F--;jAk9HWy5+Fi?4Z? z39!xjCt22|(7b`2{XITLMEi({S99|=SZ*(yFC*B_c!f8(zxN|z$uAIE<2A2a$RIY` zPkh4BWDg)QLx47<f2ji)l5jL0F+je`BfNtl_5&Ah$q$$u(qk|&`>Tr^-GF3JOhVLZ z82{CrZ9ZTy#G&KcQ_*;k%~+&I(5)i4P$Mfr{hC|nLz#^mqYMGi(<<Ih!b!HS*M|Fg z8!bX#+xX&YCD$}RALG<_R2h*GMLit4s?4Sd&V=~vc<1!6ggZ4mpTGWu%M`0!jV$#| z4;`+j6KC0-J*~Irpzpo;t~=9h)8QzSpDerg0FCM*BcNeq4W@mqmyryxR|Y|~)FhLD za;d#ntdH>Cl7o}m>6C<C1>0-+>sYHUWICgM-Q>=Gu(D^2qg+G|AOmH%#UIc!1nu=n zK=q6a-x>CspFnTfxpI7-Yl|F`5U_3s90kXO<CiqYA3(_fyYi_WbI{AbKW;Q!`jUcH zERWntfh2}P10N1X1?0*zk(ZUkv4;C{(wcEGlIl#22VMT=rKXCWB_gNwLQ;pT!1h>& zs^MBpY<l)2LgphiWCQKUAGagolSkQ9;&Sw+D$}90h~zhk@bZvxwAOjP9=)(=NaL8t zw>&a`U#Cs?y?LOh1Q6aHhGRNMZ0hVz;UXj%C<t$jW7eKfBN$qg%ELJ(8=|Eux%Rx_ z@<DA1hD_86ok#G67D^Y}9yiLH8?d36ka^SY1QTYZVdKf|wtnY+nfa0lK?DE^>%Ap| z2Ols%bUL<^hyhcQRJnPwJMkgWG;=*?=DyJ=<)&R0SF8`XRB%p6#lc|d<wxPuu+uE7 zP!U$7udISIlB!oE>isSR7}|Tujj2IcmvP@^V!Y{0G7*qXzzd-hy*#L-?5chFUZd8| zo4&7e_xD=3Ti6@&_}puR38ZRyzr`TN5;(tAePE8p-~1T!jwh@pi<Ow%N|>qHhcuC> zGP<JTno{iQ>?w6fcF}B1aGKevOZ`>(s-g7yDD#qq#y7N4P8rls1bdl-R{&uj$Udp2 zm%Z-PmGt#<)XRXK#<Uy&Kcn7FbZ{^RN#{!8li*{+j>;|@T`y1i3xL0!igVDl7^8AW z6O1ipKrsd<oZB$<W!Ct-itStuNA`5ha>Ip4JYPT_gWay}FUr40eE<{MTk<BrTJ%lY z$8@<N3Vs_?Jl##vcrYW71!;XK{@i=&oxY1EEir1Vg2Acpgs3Ve%xhPibL-487Wvu! z)h<dtInQYl)(S76<;WWsuB%5{h7|B9)T9z(3U{~=UrZn2IUsiTAs|L%Xsi$AoyzMy zVUQe{eiKf{*6mo8Go<3?r&{oiJop26Uk)s(*d&XW0dbyfE(#;5AKuw-cQ#LzeOF5} z*<|a%8xuBvTC+`??w7vKx5$porgLP<-?{aae~;s#T*>v3f_o*7tWJIslaG0-Uget` zN+^17rNdMINzJV0-c+TbZ#TCTdc%J1)M3ER!+TFTw2}{v2ZMW8aE_NbJ-T#d^Eh0^ z$IJ)x08gKCyHGK$m5#}W7i5e8>X46%(Q&sQ4Mgl-d)|K%+F_!deU8x^lR)PjaQUsu zq%p)N;3_`Zn*_}%p9sokCEy7Psw7VDGTIqSEVxc#i(utD2wbB|rb<q2_rFRnWDCt% zo?)xmeRuJYXrhK-(S`PXii*&`^G({G)g^6lhGVt0Sg4;RbS2F!VXP?aMXWb@YZw{D z*7)F<ArTE>Az!P{<G(!Ux+Q9qaIZz<Lc;~QY)>sAu*HO47Bd1bQtmCtxL?qnEE`F) zm+&^|FTNWAsZ6GOSxIBgUSr=i4maa$CJPD~BXb)gD<aC}M(cY~hp)ed)%6F!lPI|V z*BMs>1yc&>usKJZ$>fhVQas_ul=8g1&ws{wKCi5NFp`AMOh%EMaR~vQ5|{rC?HM@) z@v-jdxF(3WrZZ*jW)br!I9L!nF7esrP4%+=^yG&udN$39XCY(be~0t0xBY)N6OC5_ zBhfqxY=re&P-TSZ*%AU$pey5SYPYy2V+k~yF#cG8lc6P_ue_in4ZS!c=fE-$GB4F7 zj!h!d5$ps7Y;@)e=GjIL!{y9__JpklCi|mP6sgN`cq#{0nKg5H+i<k!r8W@eO~vFH zPku}P6c^>m1FZ`;zeyI#&%t-;XqrNrOAhvL<HZ(*hP>7!jZ{5YADhK8t%7Ubg8RLn zeO$7A<Y0KVi~Etsm5m~cd`!77MtncCkxj*fBGY^5od#*kX8AsytKFkbA%3rSv{l}% z_6I<;wwKDhspnFFutu)Hd!9Dx`WCeK(PO?S{?_Ji__MNsJR$B{jRxkV_$l!6V_%hP z+i~x7pHY9FtMCdOrr_{b+hEHS7Lm{<!&=;AxP7XM@QzsDc{4A%8=|RY6l)J`9%uf^ zrtDchG5a^9!ubCK{O{cd?Yd9F&A@@Nk^Skk@Z?KDOVnO~q+ci)0~kl9HCl#2K3Jz! zzD0OKhA<dJn>i7YEy&a;7NrGZW8)&rr>craM~^i(-NlIvJ>*44w6u2NWF6n3g&z-d z?{)U#wu~Qsu|#Tqi$VN_1i}--$Lg-w3@fiK^LPD~DZ~oYi3r~LR12R#hz+yvo+ech zq6^JYhG0xz=^@Cwm)?%6j<1BwA;un5iOL@$A$ics=)?i`_owoc@#+bgrl_Q3SHkhv z<9aXghS_o(Nfsk$WLc%s&-v+P229aQqiKr4Zfp4`KRb%!=#5PQYB4+1GHNIC^4`2% zWv#czx1ZLz6eHwW8}a2hV}D_x-K!x0r}TY(OB_hF?GFjH#6r#nss%RVv0=MOMQub7 z3c**j!7$wQT#70V>XKwRnDHE!3)Wg!)kK8uAAs0Jh-M)dWKzXS8!?gl*|UYes$Elf zva08Vcv&sE2q{Wnr-MR;TFv(J1_CPre|OC%((Xs%H_OpRI&ZkR)72twN=Q$#-Rf&` zu(93G>>_1M?s=pKy1*iEImec`WIEw-W|80-0XpONXgsD-E>uU%tIGvCMr8y$2I|F@ zHo5a)dTCDq>Tpf`J~iEk;exf(jI_$FQ&%R?8AZ?onWtNs?WWy&pr-HZ@vsAAxU+jQ zdcUph5y8dpw?Cf@)KREQ$4exPnwB-*p@20ip!fAR=;^es^*y@8&V>cFRNYa(H9!2d zxUg8DN@vv?W3J))adw)BrDiOj=T(1jB&j&m{Tca&`NW4?)o~pYlixMJN1HKy#t;*E z!accY{%9e9;A=8M=^ZA?RrCa^0xknY`YAY3h@duaL=!bnYpB)GJw>xDeOEt&ZJE?5 zu?U$NUr-1O`T>XTWP4jr(Dw={WTW%Tm18)6R9F!uxQ+{^*E=NJLYk^5f6AArQS0fR z&x%n^(8as*)NP99g+@CuBP2u8#QD{F(hWw>`Lkw!EQvzY_v$}3!J3j<$`FoniFcI( zrZ^ya5#3FoAbAc_RMc!HZ8(ziJVpHo@U`JrGz?6qlH6=EJR(=!3Qxl`G}_=76*2q% z?$%vRC5_k=FNO}ZTQ)Kx|IiSOzvFM#ao0$bF8%f<^i<A>WAY|lkB|iLb?$aJyI2{Z z8rmx~VXGJ+*);RA5d(FUhAEgv*v;qMei92^4q?wuPdIR0%fXjQV5)buL$2SE1s|!p z=JsCZ8%#CZ^Os=;_8fIENtwIVIj9?GeD9-+!vOMYq(;8C<!j9DbVzUs)Ax@eRyz0P z`pj`>yq4XD)m%zaTD8bB>q@_d*6S9G+4hK4{u4tv-hePXEkDirJ(qhIMNXZ0cK>|e z!_G_NvNN1tb@Sa4+wpQ+KUfn*@lHzxgGc&iEev3qren;5JY}%R#|Ssq03N34fdvvf z@ID2l-Y0GN&@hTphTiA*!4OudI&&9RRx60)1Ps`z^NFh6`_q^HBM_d34R=2lMF@f$ z&yo)aQIQiI$81?1JRb~drIbdSTaTC2(+|XK*Zu%(nZrB~K>QKpbkrnkVDBfd!V-Oe zXTuhy_v$BGx7XaY>78)Q1#$p7ITKNuhLVv4vZuS{%Woun>4yyjykV%|`_r&wH8zy~ z30Nu1d-^JCm_;5*#0!R%U{iWBRy%V<A6uQ|aJ!qwj=3h*QHR-kjQ7*N^BK0hb&Kb4 zr%!xyCH;E*#`XSjTHPWt6r|^cX1~Y&+Y&AwpAe}!^p^V^&sYmZw=l;9#_|KyQ;8_> zp)|P^vGBg=aY7}X8sYud2qLh%H!5adHVX@X+$ZwO6$36htNljts-`lMBXj23&e=Sq z_kO$FzaktZq$?K5HXbp`(P3{cRf4}XOQGOTEaFxZdJ6K3tGF=rEq|rAJbBU(P{$1c z>xjDLVnC?nK_$+Za=~Owi<?H*j4s7Uu%)waS!iO&VJ)+QcokG^sAoJz*Rv<8xtXeo zFAwX!?$ql62NOhAy7vMlYfnt)<2{O17RzZ@A>LEFkscBk^o2T)@;BEru=rw@K+C@k z0dY)w7OZp_Z59m##0q(c(%Sb8wrrOa8eZU9_)?Os%jmhE13viqWGo+|EegC8jUIb> z>Ks<^(~Pm`@~gih)Kph?`@PkcSM>1em?d~)C^dZ8R5JQHKuudJ1JRF&1S@EX*~vHw z?yqShcf{c6Xw*!qK8LitkK$47mB%cZl=eM4X+da2E&|4lb7mvodc$Qzt)`EeQ*1z9 zo4^ar0WfEXJ^31gwOq)f;fN7;I{lFhTy9l8E~2nYsxT({-ugR}`qb3mdF3RFSWtU4 z2xgc)`L)AE?NG|0k3$)`ogb`yiWp@uk+*t<K%2myP;BIf!fe~EhHFgc;3nLwCJ37o zCzzNy^jI^Nv)V+iOVHXWT-bw}C8*0c>oCedLMNgY%ap>t2BYcLWiIhLvN3o7fRgaV zW-7pZCVzy%vbp(EB8ZT$)_@T88<HSnGuW12T4-%0nxNV#&c`d7HS1-^<E`%l%i?7t z+gI7*$QY)Z+v!s8R;MP3ofmAg(c%1O!@syPq&cQY*{1CY43})av3(>)U$bsj*-5H< zlt}(Pn}l&Rt8p>(!_2-}Waq56;rjeHA_XqT_QiYLFJum~GhO!_uC=u3<N^gZ22M(3 zMC=8GZx2e+R97$7<-{w!+f(yTe~y)T2cQk1V4{dw8Id6cTjJOiyw0xq_Dj~E(wU7q zW_XJq1)2VoN9COxPm0t?u1pfK8{d~~bfqp&OhRY{Q*v?JX;QY48jcIt6=RqxuNn(D zO<mflR2}Phe<4kxuf8i&mqv3VppHEr0kCU6kB5z+;xy&w@EPU4kCmp@oRB7&DB)5+ z&F_`#VEFNo#v;o3jzm(We{asEU+z4{eo+Y|l|b*fVJ|ueZWEp8j~sqa_ihb9bS}8n zljdYOm(6rLV_de$Dnq4%P~-Q|o#yXu%^cQdR<@iQH%O7MT{!?a=w-0$xL|N+(rc4% z*{76!*IW+M@rs(lN0c3uoB^G#`s(m|#E~}ugkLSP-F_m+-Gvjgbxk?nxd4LIRBDb9 z;l_#}B-QkH?<2l>#>Hpw3y1jc>>`v#iv)Z90jT=V-N^N0{!j|_(?Zi$Qvj`cv{Kd& z``gEBrI#bd^qlSR$GmY9L?EMmAqz^2f+%U?QuZ?!9m-&M#z+o|@z~E%*k`ZZ$|Ir~ zSZS;|m3QC}tI3m=#vii{KplLc_5cH%7mWnM{3M?h%7tMF+>@^*?dm~lIW(ahtoa;r z_TxODP9Od?5;$CiHeu2P<Dl27x(eQtl@;|#Xi08iYHnA}i~uR5%WJIN+^za@MHkLK zTi(epZp>7INzT67@X5eER^wFmQ-}V}29$m{0zc-!qm3$W?;DwI(3GA>vvnWyr3@Yn zj9zRJqLHcoam1+UO(?ZRDYM67=5UdAP=C%oYxmvc#dEZuze~2(&y3b|QEYvkxZ*i3 z20b4>g1X4X4W`!I@Ww+{I7*Outd8T*v|k@vw*Xm9$>-z_W5^%JztlD*4*_rrka-al zG~}qG64Kt8(mC|8mT0JQS>g>EM;#M=9dcrNZK(uT_(4K43^%Ztobwj=K2+zqb24OX z<i2~2-Ayepu*&JOqZW+pQFXDMupZNk9FO^%ah2VzI+=06X+m)6!sWEc`v*9a=W9Io zk+NNM3RM#99As;pt8vZaE>P+~Y=AFiRfoSm_pWIRFW74NSV-BFA7HmQ)yQXvyIbqo z4Giu%CHa}{@i^f-o0{TJ$Z%i4lV<QE9Lh$0?(uqqEOECrw{z#TKhqs$S+}vdpnE%b zQw3aBKL|bVQxu1F>1-V;FcwLx?_D*R)g@d`dZCnCI#g1m0xS6kK;>CZS7_Ih43VPv z3PTn(B0jyqj$Cv({UR><J8V1+AGh4#F4{Nc$T&*m(KsT83pDUhF~oYD5`R0T@#*pH zn0loMY8-wB0j{`StvTan;gHN17z*0t{PqdkH!4o|s7R%?btAfoJcWJWq>!V{+ZocQ zHW48O%NN_V7VmA7V?~cVQq{_0qj!J;V~-wY`i|s}9B&Ud=Y)2ASI2{1(za1tvq!vT zV-p_wo}Kt>4mfWqA|E`j*|*$Hb3=GD_^Cbidm0f!b10{6C52|j93>N6oiIYukhs{d z3)}H`-h9d@f>i~t9{Ftpc_wmeQo49tjUGq!1jR3)$=H5HsUEpw{GHLpH{X&|YaN6T zo{UR#5#YJck?Q%#FL8Cw)XeusQyhIxpcqGA<aWO7sf6gS_h7CKyK|I%{4(Zl@-hma zsYoySl^nnVe~k6$itE$cbDnNFn^<(JVk+*^L15|<TFcXy=<1N!{!XkZ1=fKHryo=x zEnp~mC|fB~IU`{+`<%S&y~wlzNFN18tf%;;)HxJ9hp~T}2m59@Z!97AzX<LBHr54o zKe8dtQZc$GJbh5WywLDYIVS2&&BdBq?YBoPB+I$8Thf-Dc8hZ}cLZxuvU6P|GXrE@ zX2^-dVmXm5=$RxXm(V`Upcv|cRIayH9evK;r~tmE)Z<76BimAT`wQ6ooR2;;7C1Qq z;Iyk8T3_MQbFsW840-tS^`1V$374Avfw$lhXHZ#?R<qf<EK$LKwh~QJ1OM)wd<f94 z{VVDp0N+YZ3reitOrMoajUE>=CF`ZU-2u=uWk#tM8;f9#p!zt#G^b9R(A*KL+)lDe zeP;YL0>psST{l>IpcoD(AVT)vwL(XuHftXk`@)>SaWF2m0bTl7Bwfu#R2S_P(Uhw2 z?hP`M%1Ld?dNN)L`;wfxD!xChmS?pP^))$cWl*u!b=za{&DhG8V-VS(?z^fkk;YVc zWKI(y;TwNyjxl92?kHDr6P*p{uHW?iFS3@04J(n*Ob0RW^T*F~CU^fV<^O2Ey!xy| zu&MDe9e?Akx=G}X+tp1b>h}0DS_}P$NFR?gg$c*iJt2VgptBXDCEC=Ab>!Y2Hz610 zOa4tb7gSBLAgzv)wM;u=?&zrbYd@&FtdGkN@CU$hq~j6I<SKPw!2B>|G{mZL68Ht4 zK^vB;W!(7eYNG2uc#rbeE-0EPqr*MM_@-!)d=y)T<;t{$(DpvJ;3Bd;0u!GCZn^<V z-XJlHJ(Uh$Mf5P+b{@>p!suOliW;DG(9IQY7f1`>Xq0v&)5;)*tQdMoCwjk~G~JAI zfuGd$>uAjH{CvFJ7Nnh5n!5Z#%`)P3yupjZ#Q#cJbSYjjfSb-@B&r@tS$}H^dfR*{ zu#LlG-;Y>Kc|Vgh@B6OinrGodJl1<T;Ni=~p_}{58OQG&Ul2wVv>xBLo~W5GI?oQS zUha5n+AKmf(vmvaMwIQ466ZhqM3@NQmS24)fes@25JlPO$rBelj>&Uj>0&O#@hK=) zseVRVn6mKK%g<SF;CX{x$7W$SGn8b^V`&g<P<xga+49A!1|y)aw}pw?`oRo&{xqS^ z>qUs7cI?gOor~JD322J`G6s(Ir|%z*#atd{U;Xx2`2)!RuL-&O{{a;Gf4(Vv{y?$e z4?yTVXyzG8DNvIku)AOJk_PF&`~Q{(1gBH60-pl;*Z?u)?%T1>*5X7)m{u@Y&-@h% zVMna0Y-tP!=wmpparg34rFz|B(2bI$Id1yBgsAG<bmmF*1&oGQ#x_`1T2y-Y)UwRB zpUbJKT|1ZJ1ta`OPwSa6D3F;VS(eCj_1lC%z*b%iFJ=8J87(zxwX@>w7HX(3$}R)L z__Dh$5&~uiF>5u28}@#UI&*~zgzUvNuh*R4BdVsW1td|*HE9@azH9L@#<gyw)H<BR zHjgPN`s5B=8GB8Z1?LM}dTZ~wWhJrJ+l>XH-uPWeS@ic;2D1Wqb<(QR|NR?{z$_My zeQ}xuqC2i$Yz1A1v3|8+S<&nUncbYda3-7VOI^y0tnBd3HIIHYwJ{V`?WT+ElF!fY z2_>Z#Dh!{6J>$BEQSmqOT8r1e+V_8Yrux6c3KIJD^e;U}F>{ey+Ww*fAU`D)1k$3R z${2Xp_fxhChQNe@BMg;A?NTFnHqWO>p)tk}P)esDE>YSJGJ^^J+R-S;zr>?<cZ{4E zTZBZGqvMDtab?GZOY-lGbf71<<G_-=!w^S;B3a+UPrL1jJ=Qq}Q_Uf!BORG^ScLDF zL#hT<o4%DTdm^YY#j#>-M34qTtrsdTWwiugzTj7@o7Eegl+s&?518d(=tZu~C&%e0 zF<C>kRY@%L!;O&qQiQzCx3@(0<X_8HXu!x5GUZ?UWH>=JiGCZTPAPbNQgnjrDT^gC zhP<TA&sv3eEMZR0?kB_p3@sA+z{HjclH_zKJ|@<?QT578kRfSjbSeDwQ7|y**&Ly; zVylRnR1WVRnU@ntt~xtp@qx%2BZq*4e8s{evYx!!hQx^O3*MJ;{jUQ%T38oCAfhB? z2HLJwwE_$)&RiK2{^P}+Dli(7xiR@oQtLS_j^>eOhwuQ&D8eyoy#u+t#UQCs!4<K} z#jCN|x`bqP*)A%or!KS8)|%!+$zPjGB2T~^;IeTf&nybNSI~uwbz)J)_&X{_%HI~Q z);T4g{ENt23NYUYhFAjJ>3=?9+9lL-AqwmQGn2jEF4B!Q4kNd!k~2~gQ(xlw%-c;` z`S~OJprVq`QH<U#BFt@tS4}~avv8QL1P94|Bj1+jF?^JgVye}YDRd_#Jb}mVEU+wb zX$ubjvNhP(5G%Os!+4R8%D?-9*0B|xZ{luj3<2F2OzT=J$rgg2i$mEc6(&nMIy|Ix zAkR{s+#fQohM~`p565Llxv#Go(H?z-c${BKz@1#_&M?no+FnYkhg7NNlVjw%93d45 zkBur+a2U}IZk#BGh|Dz<ym+vGaoIHyW{e|S4R<J;QA+`%=c&3V+Yk^Qx1#^118AEP zwU1TcaAhPY%uelG-Gj|$6b$p>I%F>N4nLS;(YGmgQYF9Zm$8b!AD*gw6#14PX7^@j zM^qje*FmeeU@Y-o=S9rGkEvtD>PHJGdjd{dqX#wZ%g@B#p+G}9W?BvWwE@P3JSgve zB^m)T{+<@%d6aC16r;#h3?4n`sRhy+BZzn5?uI}u-bw9>lPtoM@tFKj36e9D@y@|` zH*dnmu?!jfVo`dA^Ct0OZs+ZsgRH!lR59^OX0E*E$;F<T=!SBUN)d>%NJWvT?igp! z*XaI`=-d0p|881Jznf?j=u!zCU}0GledP;3Q$ur?%J<FtC|TP0HrZxKm_Hc=H3NW+ zfU8jQt=4d63Suu!D}Lm2JtzZrypBLOsl6%o+lYoxWhld>5P`Eau_Xv%z43rtpY6<G z@Oodzu^cR8xrxU;w@gJIEl2h01EV<x5F;vlHD_}k#Zs?+&NNTiGW;Z&@;)&MOg+nb zh}5V5O|YC0m*!ihTSYF<NBp3o`F~}v63LHZ{J!UDDS#+RLBAs8obRRq41`Q^p#hCz zevZE$u&`Fk6fSh4rs$8O1h3ycaL{OLAG$4=#cR9(oo2FgL}1#wlh1~xgdj?DCNyi> zH$XTE1Ktm<Ls)o8L@Yv+*htRWPWD5>#-N_MO#$ynp2Ol+Oi<JZBfiuL{CY<I8zjK} zg`z4=NT<!Dg52z`gCM-}y#&mwOW}vxKtgBg*ny4UZz8Jowbubs1=ZY(N(bCJth(dC z%T}BlHtM0b$4CP@G0+LVKCcJ?C)*g}skUPYcv37SQ;{PFG{Q3y?`$}5lF=}H@7al5 zQYGqJ+gGAyG$%k~`!Rus=9rRWhj*{X+Zka@Du7(PO6s|#r3QnsjOm{7t*72xOh>QO z$u#<X$AGv|@mBc&tePX{o*<Covy~9sX*>R%1BQdhrR{t@Kbl?f>8^33Q7XXc@&_3) z_y;45TU@<m`qNORvYx!UV2Wqz89&w{qPx*ZT4_m-V^x=CTT*~R$p=CC6d`KlMBhM^ zZew11TMRORbBuE+O@0!Et35N)U2Jz~pKENK&=~*DG1xF#l-EMCib(ifYS;^yn4yjN z3bs1=xLrR&b~?+6$n_pfB_$Kyp_?c%%(WmJe;PhBzJonlaQIFGaq@{m0+p84sC4&d zo}JWr;`)$EvX=cDmwURDdCDqkqQHQoEncZ^ruDQSH*w0rKLB6i12UkcQ|lYo-&L(n z?9jy-E*C%urpL!gL(ZUsXA$Hp&FZVrJ#)nB=<GKbmKi(edQ}7;krM|f^3d~TRD`K) zhqVxt-T;v`^Vzn@1;sx$D;cZg`yE3?$~uo3Nnr>vp7_|6(34ORl(*;Khlwjlsu0pw zZ-SZe27RVdCcCUJ7TH6lnB2X$m53s+Be+~e{e!qm>BRNS40cJF`CI~=j!-ylNuLf3 z53}^Nb;S*HqU!Qt+~1KRt{->bqqX1s4>Qs`@%mF7+TfsN+oa?#e|&fqd<D_rVlB!N z(mUOF<7k35SWzvo2ndd47=8}Ebg>45Vq<ibnz2~b7q0X6Yn7_R>c5@(ied^`aq=Dl zI3^&HYyMq15=l?ySm8cD+K&KtM|eN^o<#;{)Nu8cvG)XfY~84+wQY6(M9%iD1ODq2 z?#mUa(>%G~X=V5SjZ<Y(^e;{iUfI}6ty5N=%9?7Uh@9hcFJ3kW%${}n4ra)|qMcRt ziK?or{R8;e5QK?mmF*NR*eQzF$kBYRKcwga*~5s2sMNddyx3EkY-&{C!d_0^Y<P3E zWr_jgr4TxgB?RiOa9|Veq61m`8{=QL;qtcG`@Obapo$LI4GU=Zq{7V|mZcB;LHFy! zGv|86<K}Q2r|lQ?lHdY-6=!hsIK<{9C9~l$<}yzOjK2=%yo%vM5dQ&XHNc9IfN90q zYnfzv=Hkl{(O<v)rR)%<rf>rb^d);~FkBsRCcL*LBp0Z<4!HREbi5Gw?5Hw!lnEN> z+vdA>`?y1gtng;*W(arxtJ`aAj@gQtJgMp(7*Vm9*hlZmLv2?JWo`S_ofi4nnxEz| z-_==<eIb}?4FS80QefnTV~B=YpS5H~joilGZ!^xe4uBM@QJ^z|wBiQm)RVt@D7FM) z(r^_#|G_=!r_Ui}qXI9kYRKhI7Lx5qKV^kV5^ImPnqQnR0_eS*?|U6%hZ%ePD5V6c zAFQOHJC18Up4j#f7M7bn*KuSsqEu#~xY(t}eV!xcci>=e9Xky{=SxeFKRS-O-22#u z?s5Do{C#TOeC@bUBRSt<WkKhgpH$AwT9zA!?qV9}ObMEiSFsHScY)$*Lq#(|LD-TP zzdFRi{;pJe-ea1_FFcUBsqh1%4@7Uoaa)o^We9Qga0`cqVr!`k$cczfyxvuPb`%_` zO@CEx@#X?TWJIG0Y)7qG;}WjVlMn0lS{1AdIi@~z9`u?<L6ja83^1eW!OTX$(r`MD zTm<+!1(Xiu`W!8VVW*UV(Gqo%+o2d=MPV({lRWeyBQy=(3l<xwo6;{cUL5d!CDaEi zI*KQ9?Vz@W7RUvdoS9qct&isbRfx&U{f>708iNtoBwRLsNq_har?DUY&`A@^RQgX& z2FfLM8K}AxLp}P{^N-R`mVbZ}6Iu-Nc$odRdm{F^Qn;S3gslLf$fFS%wnS0Y_<g$q z<IFO_d?W~cHonZWb^-x6@i)3t$RMeVU;XZ59gK!pDY?X}4X<AfHC?Xu6w6z$@oNJ? z9nuV8(Hd6H-|acXl)AB(l>tu$f*9F^6P@Kfff)gFirCP_V|;%1<-0(D))DYiVm>x8 zSzzk(MsF3jaG;EgucJTidY^6{9J5#6<295FNsLU$!i{605v-slnu!MAjju0P=W{Fd z?C*P1LTvXdS(`(E!!l#Kf17>diTTuU(6IsI!`N{*`Ni|1H`q{FZB7CAZbn<}!%XV$ z&u7o^xvnvgARy$M!qBJV;txV6oHPFD|J8y0@IjiC-+>H>C<urTvyy?&@|FBs!ecS; ze;P0{D|0s!ND;R6Xi;Nd!5xO4Y*B$es!*pjPg>rtgBFhRION6@&Dhy~OnnmJL^_zq z-|$7n=ft9LI&-a}fd~X`jQ1FXFeMDYkQt@(jTp+QL7saAdq~KI6d+);W>wHHM&;tL z?t|AhCs%QAsQSBTMRQ4B1)_A#3D(Wk18SdL&&mB|g!wn|ok6yjE;JIk&q~DccaQ=) z6JdX^xU;>Nx}@*B>w9ta=y91R%OREEhS<Ecu>8h44c30rDFNwW99dGY8C<Oi2WjWW z{;vxO@Fq8YtLkxq<0<5h!p^~T-w6AJGRYY>)LQitQpwdyk2%5p12oP-FJlx4LE}A> zr%;4Dq01&U1C!hqXkWBY3W>goQBXCTHiMHia3}ax$g#)Falx!ep^xZ=-=~}R|Nj9) z<&eKjiiK4g1&7zjf6ye^X}1N_iDLKB6Q$>(Pi2ui{{fVJc-C&kx}Z#wLKGyWv#+96 z%mpRG>orY@>>sndHRzbiN{OcKrdPPbzM%PDT^3{l_ZS&C%4t4O?G8_~ru`Bj?nsIF zS!$Z0ydic6K5)wc>Yxx~UiuxsUc{++TVAn-`B@Vf8s_{pzYy;*Yh3xz*O%-n@2e7u z;p3<zGeT==j>6Mn3erKD9!NY}PUyqFOpA%5!Cm~qG*lu}Kq|e;b^)JrAcJ0Qt$n?U zZhOQCfwzitmRdj8G<fT76~CEqNT;*U&7IEhQzsw${vG141oRYonJujB<6AnTSeK`O z1D@adzuceW15|&Bi`>Rsv+Wt{pawCGFd!{-i0+jY_koz<(6uC!U&qRE5em6)(U21P z$Pd>|2Y{7pNI8u{Gw!|%jyT1hZq*K)Ks9X`KwA&*U$oSeILdvC-P#tw(FWo4rLMBk zv_{_y1hy*m^w(w?aKyTNgkL3FpYL6knm?!iR(6DFO;Z{QPME9janNCaUm%Vo3?Iv; z>f&p5xCQJu1?pu}LC3KP1n>$-6b!Xh*M(}>UPk3YYGTq2Lj`Y=X>hWTt$wClNx{;F zGlJp`7eE3=K*{R~azPCy7d&e*(X_}Bmjcgm&r*Po%xHsNYewGigguqUCC+&~S!vB+ z!{=FS`w|?X?xGnbFX|nqKHi@P{rKJEzpfNgv6_zgS8wUx`~heanxV$Q`>-fl7a6)# zf@G0Oh8a%KsvI3bZf3{>n%^SdXo<mv_@~pjTeQ99_fAtV2srsoh@R}qUa;JFxNNS$ zu-%IS(kSwyA3$>FDR=#$)K0snnP`Wvgmf+H63ZoTuil4nXc33DibZ`5tw(Dt_<5Gt zLgYJ`=dJnfD)fcbiITB&&<CPOyIv-C2}7^4=w75KRS~PKJ-U^;w$sl*w#tuRdGAF4 zA$-SvJh^k^TYJppjHe8QfhY-d>yd9y)8tMssk)6GJSX^Ti*{<o3>#AhQCRS>a)l;G z9SLLr_Bbd(Kgf5QA^=om?O8$lf8%*f{rE;mXhw@l)Vz|5A?z#uS>9+BSXeD%Xl^yZ zXRFwp{eJ*%HZH7X=b@dI?!M@5>Le-yJNYJAflj!{$3^PI{i6XXsfsBHGgb5{?n5rB zBD*2Uk{eZC+d!5`W>`4phX5K<MYL2x^YaeWe8oL2-{>g>;wGj6Gk@VjOOzOJS;J{P zu3*7%^$%IR*HjVwT3-#38oR3z4}h1pY$>9`n&+R{LaIt>8x!(XJ9o}ngcr(IgJ(4Q z+^&;FuYU~GF1(a%HwY;F&`AjuR84BdeU7y5DxYN_zgD$0+*KK+ie*Hf%^ds$r22B| zH@2^?DAm5FhsC8e){H<CeX^O_xJ1{5ZWXAH^8nO>QWxCMPy&gYW7Wz98jT7F4=)1P z$1vKxUVX+akNcU>S?P*beDUxH@S(QgQdcr7Yt+H^5WM%DJn_B;c?}A2T-Z^Q=kBQI zV`(!ypv4BL=*25bWBWb3lHq+;I{yLOCQ~yJ?}rwzp)(0z2fWMrkR=K#<>0^oXmdf0 z%VO-`A*3b%C6951xz9?GqBK5fGQ%`zYLT+DkqZ2&l#rfdeYu1uRvUng%$YhJo8@&2 z-PmLyozzA`giYVJhU054kbbY*8?S{|?#~LoHpJXHFImiIl!ELR=K0*K&V}_oTayY} zmm|KvxX1sc+(|>o8DeCBS-jM9JNWV2_;5^vTjN@0G)v&F)@$UT=l5b<jay7Ljuc8B zPmuwwr(&P(^Wq2!4A)CsMc5FItETP#_NWA_zZj%_NrYl1o`ckfRbU_ET`5r@z=mm@ z>;HZ1lMSc$NS2A?4ZwDzSYu`8{ctxR@ogS-ag~JmG@*x`$YB)VG4|TNzs~1au+3F{ zCCxn7fB!{KjF*DvSs|AnL^a9>t;X@5UdN!07`#a!WiMq9Tfa(S66QPcb8eNY_K{N4 zjmMX&s{|M~Cj8zBET^;=3U^W@IbTHifk#4xJT9?HQB7ORbZ+UDQE?qX*S>mxv2KWX z7QH6R81IHG-?8l9DCos!vSFWOdYTaly@(7b6|6EC8u0E_0I*}_+DKGAV1K#4ns)8< zo6z8Y70$9bo;7i%B5J)i{F+45k<Zv#O34R{sW^D8TRq?N7yA%)uFnXvXm}vr^Y?t) z9N1JX!ua&xW(0#hJ-THnXj$p(1bt$<0~!JNW=2s&e*g?b%fi?kN38LOlnfSupIM(} z-MVI@Qo5HNwxQ7TRr)P!5&%-T{_VYb_%VuT!AGTx0st-SyRdn*z?J->A4UKwHR4$% z210$!k6-=69ER`R52v#JW0N48+Gn0>T<1)Hx-{+ng<&9Ld$hFWtt(W4fDqu}<{_=9 z;U(DPM=c~b@fW9nE(uT#XJZ)%&vo^q*d?cxSF0eTu|6+|@X+$<RE{#nKxke9s*Mn; zTK{b0mFz+}=}-=B;%l_*+R%b_JJR6!Z|HaZh{tiBjA@>Sa$&xoQ2pJrYg7rf`)z56 zQ|gn)nm8_N2uPwTa6TJaV;SILx*{WqMxYWPEYrqw>@<Oar6o7RueiaCCii3EDKz~C z<!(vko0hZ;M{6pL?Vl4jNba3lzPYMdKJHW~wgX@RA*Wo_430+92ZQ>a-{Y2$$+C4! zspdYv4@&xk@~E=+;`!hP62p;wZ7L;*h-ad)&T@$Vr-O*LNLRcO?e@U6Li9MPP~7)n z|KE}9M62Qw3`iaA4NKkHr2~|Xt5xA%ZI%B%<m04>k#D#aL0O^!S2ts`l>az!;6&Gu zeZ%u_mmB1Q{bCV(dF+#25K=jAkfVmfZThBo&X^~_eX)3&Ln~KiqD!eAMy*0s#Y8%w zbL0;Kf|+F^FU9z`*!^<kwAiI_p)#?#xN5Ofr8z>8?R@$O(wN4|%#GNVG~;-ds$LP0 zlw{)~CPhZNX+CO2g?br~eB~9fB9F?m$LKocj`u5_`08cMu|e!X=`2oU*?U|yt-WK8 z&wPx!^M@g#cW>Tc%mf!&KIXcd&IdS+50|#TfR&iR9{{j$j4$E!f>PR06xNSe1V!jv zg}=rDjR^B%dN4^3A+iKfIpl%$U)C>#8vA%KmJ9&@jvAS$nSpi#{YVJ~K#F!yj7y6a zFN)86NS>76=Cs6@Ag!ZCt4`P9vdP5l&G0^mS9-tIP%lRd`9LsDytauoVg|;COrjrb zJ=5=+6rg`DU)9@xXi5^6z&1#a6YQ7Mlh1R5eu=A^@bxe(&&xt?%RS*EMFV=7!#*1B z+xCDcVs2fW!ywo1SbqT3P9d~INzeYl%|a5XRtH%^Ig^~rGrvzgd;1%9aPn#7K1aWD zcm>()y(-d~d|mNFHM<;xPw=hAR75z-98I6JWElTrrsACVX#R>a2LDiY1fd?AroFUO z<N#qjRXX_#lLgC;d6P<t&cvEEmD%ttP2H2Y#TiCYTi)N4l;EeTJx>@#I<cR(1284B zYsmy1RZSA}*>h>KMHC329WoFHvKM%kQh}3W*{(#p_9@PmV%I1G3|PV-2#)7?I~pP5 zA=>^k*<{XkP^r(zg*jECIGHeS;cG4rdq>Y=V=c3(<O`}cLWeOT{J7i-(LaE+rJr1u z={0pMZz<e(iqXwunr)P&rKu8k%Ws}zn^u2IS4~_uhnM)YCZe#<vlms*<Gc^w7(Yv} zoWra$*kS&>U{E2+o~n%Z`$C!8s)Lq3L2gxGLxj%WGp8}Scv}JG^exa$O}kI_6x9&P z(B8xns5Q)>fx&gDyJ=0TSbrAX|78RZ7bA9(j-_GqGY@(#?)w!nEX{Fr#Ke?#6mb7C zEugM;5UR#RJ%66mG%O7qO^^a^Pz5y(sgRer)Km!SowVwWhilC9Wu_dk#A(#%%$Fyw zl|lGyH;l85UBV;g+Nyuh6iwGuMJ(5q&S`ajOu$gqVp-;@;&$0wSHo_PX|sZxK{6<J z7<i?aO=?}gtD{64P(OZ5_vGWOE^?ts%-@@cTsi5U0`8-bX;GYN?|zk1qg?!(y|9r| zyb3H90$+~~EYCK;*#*`1)UD!^3J;Cbejf@=!UQ*)t6c{G5%PhCTG7HyqW55B0y8YW z?Jlz)n6K}GpFb-}Lqx_i_35@`4oI<><s^6gNUE%MNvXU~=VCfyw$p=X$?%v+UN@C` zZf{-2S*`^fa*hZ5{6J-of8l?)G}q|~=J(!%zV742Bq#{L1$Q=*VO;>SFi<3&5=Mp$ z9Rf(EmIOz>#Y-5bOLi5yZn-L@?;-{6{!NsjJ{#Hj5w%A<@8`kFVvjoI!5EhhBY>ju z<6-p&o2e5F!k5yg4qHw0nT!WU)6ZrQYo8e^+=QHa_Jg&!1`R+7oBCk85h38}1Cc&+ zY6?fN!u2$3p%XYEfp!y@`}h{dOy0c*YzUVobt(FWX<*KRxtUgl{W79U2l;KC$p@lC zHH%QiZ#VaxhZ2MxA7~ilt;y}yMWfCpyw%XOjC4!BW_sUdoOrWs#vY6=;l3sAUulU- zUv*NfHrd2ry>#wq#jbJlBojjjJ3^21LF918!Mf?tr^yje++5%1=-QDX>1I^DuLM_g zL99!jeGZ1g0V+oGyZ!Tv76a34jksw7p@3h?Tp@f?NR89NBT|Ul8(U$q-<|@i)-M-b zIh%#}%~_=&+<+DKM|1KDw<}V7?hp(Kr_gFB5h&jyJe%W?b_C+^`Keuw?Lx=_Gu-M( z&<<Ko59Rt41*MPmXODOeV{3t^NEF)9uY>RF+NP#W{qBQ;dL_FoS1>?99=x@JD|GC# z+D>d0|9?^Tm0@jcUE4_rZo%ChiWQeaaEIW~0>xU~odON+4#l0~T3p)V?rz21wFPQl zdY*I6^S=My@5=m{$z&$8ui0y_b+3Efi&p|*?FrbW?RAvI%K&Ae<D+}H1PN}^x@&^v zcyl2{P$@t$A>m-O)E&3y+LNS|o-c>qitkRbn<xfYMU@M4@?y&ru+d)00<h}zT{yek z=|-(N<uMxM)k$VIH34OWLfLUVpzmuDbc+C@V$*|PA+P3JsfZ%TfzT%ygcFq9#-ND1 zAkV?(ZIdVvKUI!P;Cn2o7p5E-ox%b<9jc`zM5Ng}FFJ;#%+!IksxuiX5Y?`_HJa(} zmly!3h#l8&z~G;m0JBq9wEINKV^Mqn{E$=!px&Ujt>T;O_;7$%9T1op0{|m6Xr$hI zaABnR#XMNXE!hVp^!uJV%NyDRAZeu0P|fC5Q_{R+aM!(vo=nAhbcj+Qj8MLOvB*zq zjuwSBNs5mWXavze3egM6^en{XCIy?IcGd4n4oFAHY|yJLqFy(?f|qgeI@o4oBKz`| zH#3S!Eq7e9Jzq$)_j}!|Okx9(qO0CiPl4C5l#P4!^#pB{5(;&ujN6iu9ch05_1Bz$ z`N$|ak{=X*UMC}s90@rINuT0ZSDm(@yW=4_Zr$HJ1fZ%X9FU7sa-bDO;m%TcNI>ra z9>aZyY%r4vw)iOh6q1X)DHUyUe?DCxGSnv|d}`=9|6Bz*^O|dg?)k5{#5rPzn8VFL z<P30dvlx-)$ghmIZ1>0A`)4QwzNRL*3({K5-+ov)l?A05t%`J#_VROl1b+k(Zx3o0 zdIpYVy7x}Rx2O`=+<iAgq%Yf*!m~EeT2U*CNzCmILXbqe;HzZr=`{ILz7DUZ7fX0L z_0q+uRq_w`w`-OLB`#v}m06^?{J-xRyc7lyK+&swfFHBoRB`*sq?s9gz?*WLMaU`0 zil%fRVypPM?-HO6LSFzQ*mvsyI3uuRlj(lf|LNf-2qNz)ZicNm7v9OwHfeOk$@t~K z_2*j;gg^QhWS(mm+C8CM->k~tVAveMEp*T4VlE!T_8}{t1a~>KVz8LsVsrTyiuBTw zkFROz<)!bXNROsjiUB!^k)_2&GQdVCv-W|zI!FGYN7Ew38FBb^SE^xxT(;0G&PS}G zmF3Bop^o39Pf<m#Swz3i-M^K3-Tr0$t=pfa`+L$a?eE#z#Etoq523tR{W7&**by;B zR%_jpU%u3C(bV&-Fww}*&+6{!)#jeycq_3{upIq~zuBHKH^Los0ep4{-=MCG9?c5u zHrG)n6R{PyalA)nUe*7i1G;1?B&$$j(i@R0i&O7`Ca}XTZlG1UAtn%k{sM3wB>6<~ zVnN}Ru3s1_Am&hb4rjuL=E<utd?+D0aqesD5G1FC3AROY@g`VE<tTt70Ui@iyps>H zK*WReW67y1&W<k$(50E(B4*D*)x$O3eNZWLr4h6<(toB%ZhB3|?U|Ggl(H*Pr4!U( zwbge+&E#^WplLHH*tkQth1i1Sc93p2Ca^|Ot6tI209k)d4@6S3uIu9TI8nrWB|v=@ z&s!y5w6F0A4IBrXjty@wG)+f-V@|6%lzc}Y5uZ1Uu*4Tl3U%%id0!xJlz>InHL*uh zCzwQ2n^RI5Fl1M>cZ)&>J&{1l^L+kj&o^w#|EXyX?`c7>@Dks0)hz&slLRzBWP9{~ z&JX*>CZ>23V=}CUYHhc*l*F;^XBx#RUZvB+bpHBXu+t8%WmCoqM(0I#qq-Rk-HE(M z@0R!$Z5{n-5gLHF*FYl-qP|BZ=7+5pq=!Q`>*MRfjgwTi?Ca5&>zn%#{gcF!)j@I) zW_R}v`Zz}?Z%O(0v@)-s3KEE3aAA<wpBStQUQ%wN3!>5CK#KUsT{%(TwUR7YU+}nF z-1dzlvtd$^s+P>x&&tFKC~z|i>DRLB7JsILH^B9f$->qc#`?cMp<oB@DnGiVS>B@I zz<;6vM}t(Mw5}j+B=#<k0}z!-#_qcDi`+y+9rY2-_wWZ6<u-)phM8#YX&79cEvk)> z^sAxY$PlE;_xcU+`V*^Zn+sRjI|z>hq(EKaf%<QStE<hdOlgz{u3$VfF(`CR_|7Yr zUjG@?K5g#i{S;+Q=K|F^X89016~3`DJbO`OM3)@w7{m8J%w<xzS*@L^YyQw<G^YHd z^Iz6~xyo|Be(;L#vXtmxafm4i@jVqj8bHxm3zbbgx3x0%0_!I^tP|d{d*eaQM;(I> z--SPSALXPz=l9K`+F_j@<3IfSg3L&+M5}ruCcM@oQ4pKz3jkge{o&jvULv`KJ9ba! zufzEaoAqL!+kC^{&be)sNfE?hZGGQ5q;CbFuHpo1%_)0~EI5TqDOYIXoCa5vgvhaI zyI736$lvlM);taNAfWvO0Ce$*7a9ug=2F#PckBY$2GaL-amebaP#(q)0(~pS!TH@9 zvEr@1^Bhx>vc`B!_7#^Fer(gkcc<kOq+}U-Rs|0~{JEPE#`CfEwXa5LZ~LvA2%pNm zyNA-ki1~Nh3o7KeM=rYOUa`~d_F-dq3FiAr7s)2BR+<J=`7zU8JWd1}ZUd|WsD@SQ z_|s9|pd8H5H-Z}VO4Bo6EcRnAP6UO0Zzt+lFqju*!u<k<$nDzuw94YiN8S-VDHDgC zdXAH=9z(>TyhK2XX$v!&vE2nf9Vig~Vng`rd)RFe#-hF4d&o3<EbQ5s+B=@1;6g+t zVp|p6T8;C2_XqPZ%Pa12_zp#u1F4Ef>_rJ1E8FHkCte6(tfS<4C$Duh@>bix?86XQ zb<(MNHm~+=qnx9zUHAk(dlqGa;LT$!YIG!rvd5xabpzAgK)%h?lG+%dVndx;kJg1@ ztMq)djp#({8=W(t7J%@h3|nJAdK6E1K|fEXW_*Hz97?Y62+3Ej?8ZZij~|jJ*>|3| zmd3p4o;WRXJQ5gCmrEZ2b|Z@!y}?%C5Of_>A9&V04_Gd3jbHp~{S_yJtVQ|-b;LC% z^T4fXhMWxp-oD<Nq>)@RhdfoP2lf2%ct9SaPIH?ti0kVZpias+dz+hwcqlU868oG7 z!4?fwKD}}uBv2&sq#v%Lm9iHm;e3mO`byBBSB_2id(fE9K!Wud<)F9jO|7y9)m4Ei zt&mHEr$<O&CdwFnzmop>-jl@8s4P!a&otMyW7M}Xv@6xyL8C=9%qWhr+kzdG{GL0) zt#wfV!>)4!U{f*ueXkE8CK}SmIA?7Vv#wTaT0u_doi~qd%1@dDZ_LyL1EaF0qNB@} zFE2cVH|)9PH%%2SOe9_ZiUeP5w?;UiV(jNO0e!iJ8ExMeD*k$V`G{Z=&V0AJ&Wo@7 z#y8{7s|OA8t4pmL@6!JSU^<Y!6CnD;1@d}zZsUwf%w;SfTBSn1h;54Qewu}|>Ypt} zzG%?r$YAV}qoA~G<%Mb#AS*S^s8$-_a*D6Se}){Sfap7-?=O2s*DjPmdQ`OjYv=?6 z4XFG03i9GGIp3ArKG?9D5@7s7{yL1CJX+Tq)rr*LQ!%0q$64`sNb+UEX@|K*XYhQj zS}TE$ZFQq)ukA$*wc}`TF>{uFNki_V@^K?SUH*idk5ic%|2mfyGv?VsqUr`rnEf?Z zLgGp!e0l1Y=EGwx6|X5yb_QBI)ia(J!-%0eMxkm_=3eKLzV7v~jGa3k1-ULSrV#Z$ za^aZZp&ErUq#L)Oe6I$n7tYg%{Z5Tejj&OV!l%HnH#`M$Xh^RKX)O{8`f`wxF*ErI zt>N-<e4|1-8i8_yuBT_@r=rnO=Pj`*7*Rf?`hIfsP9x!qLWIalnv2O7L6j7T76U@x z3E!Z4b8JD;P&r?1+#}*)L_ri~+VgpUE=EC=#MsQkq_o41P%<hxy|(&9IwO7L+$1HC z;I>WEi|mT|7QZO%Fnj0DBX!fU=qzxLqWXdBdcd*nr<U3MIu4Dv+hZ5*m{;zbNR7Zy zRE)^Ps1kex>C^SsY9?umS**4=EL3Cdqs-@Hv1e?3UV*tuKg?1qo`{$K21HN&_$86H ziV!`8!HQ9Poo5K!fp85?5iFsggis-mx6b0^v|2fN5i_6gnc17{z7uJ#aLKWV)Xjw` zWECl*&7GQmL3%I;)+>0ft+5@BD23p&!1>C0S!Lb<2V)uh$M*!YsH?H0p=>JT=fY3b zMS?pwY^AW9leZOuyWGM8iz><GBzVAF>@yv?Pq$PI1jj8wz3n^9F8!L)c;-AI>N46d zB;2CUmdKSHT4r$BPm@Hc2v;zeW%4MC@4V_~j;)Dn!1)pU9vEYCLrMjvjdM!J!#j7q z&RBHPY6`+QmQZmeobpFXLfjJCjTb*C(|k=unW88|``odg8BPW1!et*5-ni7(^>hGm z0Ee5y%n-#~z(f&N0h=DG1%J8os$AIQhWXqnJ0-J+DO-}OJfh+NqOS8BAoN#8Hl8Ee zMhvNaW&8lavXB(dae>rvV5F?F|CFGhy6>&C9IAIdZ=lE)Fg=qIo;hMM&3i39>4*!; z_i`Dc?ejHLw|OEne#7&2LhGFKC_=Q0vqT>b66=V!5AbIH2(Eg=t*Xiw$c|YZPKvMU zPy=jhF`_u+PxiXqJJ>u9YLfrM7`36YwwM;|5Zh)?9$o#Pj8W6S8KaYPV!!e|32P|d z{#Yf)GIze0VtX$<RfO&OROHvRN;Q3&Ax|Z3L4gUe+bpSW)M&MKRqMPehp&niizG1` zXP-;T!6%1I>ocgbZ^!;z&(<r{*dMR!?WKV~TBCHn1io99J?{d(i+m*O>rzthas2PP z_N60o*~M~!3d2++n0|hU#A)&8dKtp}GKbQl!4A&^4j{+A9b0XM=5*%J9V@q@$3MA( zh;vNElu#;rye$H{Tn0KGKqUa<1d%VG3JPU${K7O!t^g$m^;7#=xR!UB)Mmu<9e3TU za%qx)AB=pjm%m?AQq{^QuT|r|Q<=nZ*>k!!lC7v5*|P4s6t|Gs$_LSh$_bio9L=6h zBYAusv}3f63W2R0x-ihA;3XMzvls=<h~w7<@l4R2x|#!(n;w7QSoYE7PlusW8wgBW zO%EcW#<3pOnmh#Xn~-OzBnub<P;#q&{u$w-JZzuazAHVai^RjYE7`Zntn=luhY>jn z<iDh$Sn{`PzB^E^K>4IhKMpiqV_!~*&M9tp09&`XO^EY+8wgo?w3D@Roh1^$WU89g z6>LN1u(F@#Ju1c7NzG-?{T!=NGKLe|r{Pr!gN@L@(}HCk*5}yocbaXJ;o2CWkLyO> zK3!$JR(^RCTDPGFjx#yJZvW0}fBlAMEVEm6y_z2{sS+914iRAA@IX`{vW`9W4pv;P z0bWm~E9n~ffIwg2eP7J+VF=|y*47ReGh4VGkEquK)XbbGIU<PKHP(j&okWECM?D#3 zek{ymku(jpK(l<hq>7fJRUmRD5hfKGS6KxvPlCp-sOx7pJ9e?sf|oU(Iig_!>{*tJ zx6?tUnqrdQOYP6t<*{A27T9S%1Zuqw++v2=R4);L0MmiL0n1O)-^+T`lEQtrCrm+T z1zxE*dOM9;)gC=C2DvCfHT{O{&=bCVUcQmdVvgG?WUp@D`@zEO1rryT$cV2PTTEr3 zS&xo=4#2;f7h68VXX<<>rtCLBtw003VwjaYuB~0t!dppAN6GMN)o0*ijD1s~mC&8j z&4<0h@yq3=M(28^%f6YCqr0aE17GvyjpP<|*3ihDsFNq27~0S(W*`ZS_1k?Ivcwqh zACvqFsKeHAe&Cg1Mbz!Q0XkWrp&sk(f?6AznMbfm@U533KT+;^)d+w+LGe;OT(;H? zW{mb}Mw`0c`9O*MpKo6yV!I5aG-Fn4P{kGRKJFx&d)krcA^%N<X!w89;{!t%mD-_c zxQWCcJP&axOj>yxWAwMwL^4~D8^_-Ub0L=znEPe^a(iXnPYZp~NxrO5JI$xK(4Uu` z-Y|@TH$>Oz$~%I2_$#qfH=kPUhhHK&Zhg=Ti$b|M@3Sbn+K3whN?cd`0OvsrO(nm= z194~Yk7b^rAmk6lemPto?q2?--y~rdk3qrY99~9uD&M;q@I+>fonNpb$?kSdl%om3 zFPl+K(plwnkmnCSPpG9o5#N%UP9&hAv~E%J=__RO5HKKx24WW3;?VfLLh9UK>c0s@ zcY(ROf;{<NwlvtF8CU#tw)E>u*Ezf}ARCKd!LpfDHCS~ae86Xk<Vg;p%%sKiGb5dg z<t;DLh#`H^!j#}Sh*2S8bSo(t|NiUbo+OR_xmDGpIgh#2qiKMx;EtoT$T?CHAuGT5 zR(&M{6V{fS|7uPs+pY{v_RaOcypsm$i&v~lOr;t|FLTa!Ra2+0&8io2f`d$?1{}-# zs+y9Ea_@O|bD)fkIajKB2WS~)1d#*8{ATc=+zoLrTqs7OlBw^GCnyD{OLIHhVk9|P zQFqwwD4xn5{bqc2zJXu7(-Tn_vqqI^5~zP_#;d-&t5jr7f;tS22)e|{;WJBw7EqZM z)hrinP^HqARWI0<b0!FQbc%RQWqu%v_P$6i^tZ_mg|csYe8H=qUz+uN<*eUM1QU+s zGstfj>mk%RyBz%GvL_%B7^%uc8d5G|KyXwoBpUDN=mJfkU_#P*=B(7*4+kgc;j|8W zl@-)uAEwUU(cvP6N(~xfZKzju+3WSfrNh;5MNGGz5)`;}m_?=yjkr~?$Pg&5M8i)_ zz{~OYDqu!rg53ku5#A}NED9dhej#pNV{_k^#AA_KU!z%1J?x;8@jLSm=4gk|4(*F* zYh^l?l2*43QZ&Z0%0Z9MFPDp!L@il9{gUu86rBy7NIv`xSP%yhbUUG1DLDK}`?G#( zG6kd%XT5-8mj@Zzl~XX7D~95o@;}bBL)X@+;*NNcDBK;QS-j=MOPp6lxHJ4oIiQg@ z1d}M@a}gwdP~L)B6f6ktKB)i<1Ob?wirll81zNkCT0LWkPj0#Hdj~G9pYF;pgop>< z-jB2Woa@kk$#XBOm@+_*g5iI?V<AtAb1vz@1GjX3?nFwrq^lz&xMfErVj$w~5Hcm^ z3Yft@Njk(-n#^q#KFdsWJ@VUF`@>2s{Wo^&w+=lwwRRy62AI&ZGZP|H+d6*zfqVyC zFf<!?3I=L<@K-t#?J$OTk~2r4Nosr(MGT2mT%@p$7COV*;f)p77HrB+-H{-@3$MTR zE@?3O;F-;w@GxFYTBIdff1Wbt4bqoiUnf@nEYLFvg9L@+>v}q+P86w)?l0bimnpG_ z8v4=@4t$ffySNGxMo|d=YR-?A9p6)>%X1DI+>0>R$p82%%VU5jqbukOoxc%xSCJJA zGB{P2V3W=Jb)*e_&(#Sz?HcVSnXX6Y0rC?|-aqsYSNB%~$`+GEWx_xh^Zh-Nju(~@ zI=AddG^y(tJ}b}3B@Bc1@;4xoAj$9M--SjlbMvy*0~$Hkbv>9xJgt1T!TsPvu*;Kx z@fAw})WM7n)vu50Gf~yi<bL}TUL}-T>|_(s6`#zO>9r%Gz0WIKXoL?l0+oqpU`MW- zHnOdorYLRR!we=K=BTwnyBN`HUACyncZcmAlT%E<mo)i`_2Dn!9H7=|O|iWCdFt-< z|E;t$$h6QX&5J^B@j(HLE9O@uzfjj%L@OsN;qybuC&X+Lp+(lXR3F&M%c_XHPvEo# zh{eaBH@(0#K2ZWUh>-G`k#U$9{n6gtV1T|QNIctogiwc0RxOVDjp=*zTTTk7_gNM> zCtR^6>tUBGVY@y&*q|fEQ*L(jBy{phebwS?Pk%K;)!;O)CA&1L71Qfpiu3-X>f64U zm3^I!fcVhw58VLbxcd1x<$@&-L(v*A8m7J<q@A*-4YTDed54hYLFWA=OIcu~&F}<L z3EF#=fsN)z1Y&V*mLnO1@(xXQ!irI8u|^o`%IGYEnhvX+MkLExJ34)JNtCiql0?YS zVDlJcHO{!>c4|#GeFsjY4;lh=XaFU7l5A!7K8M)3%mX1b8ODz>=av)ozm9_XcAv(Z zJB49><6rf8AKE<+dqPgp)t~XXXR~sC0Q=hq$PHU_P`e%Dz4*SZ-12OVjjwT~BStlw zLgAL*H3==aganA(G2VlKmJS2n(x{x}jRZ(kF6Sm6!7=Iv^kg7ZSZl#eOTgy#shfyZ zyJ_PjiiZQP`>r?zNI?x_fuKhex#PUb4jn&HT}oFLq1S-ErQa`2X#Q-_d<wEJX^fBC z4n<*>t<p6O|1cWt91f~Jn&nSBqQfYr8D;H((7H+SynIFn*bk+3G~o%OQN)hc+2i4w z(S;SaV{-|GzUk=`gk;+b53l$=7GoS^i*<3DdiV77gbTpSGGCBf4B!0*EFF5<*+AsK zEu=rqZ&1q^m|vx3rUs7yrcmNCsyu)Nu_r=jRotuatC&Lu&2=J31><vF6VWz$GHqDO z8C7?1H<}Dg)6+>+bDyy!ec3k+XwXv5VYrFfY-0IE4h93v9b|(U<CVF0x8k7g(;`tX zK0S!YfhXS&f3k{!LbS@v4o=d7655}FC@(&X;IC%4-xdgS)Xx9-aZ*K1M|dox4&Whf zgoo;@nYeinMdjo1$EE-Ls<ZdOZqQRmLq71s3VKluUZ=-XY3m6q;dhGH4A6S!wsl7@ zD>?RcIQJ~gL?oX~@z16z`Hq+hdXW&XI0`-4;_!^oX3+RO0$Q6so8aH{&i6C!e*Cpc z-M#S#2FdDq8rFvogYAo(6Bxun%s2>_P{`~2@b_~*qNMEwHYZL;;L`teS!^$aGnEVw zXg;H}c?CG3(-Mc^?Nx6tKn}&?yL4p%?U93v{CFvxUYrYP!_$SBBYdci$Y^rM$L0<E zQGj<@WGo_wte&mtklS}k8`;rhvQ2Xi3)qzAwj<pvH_;q^@-q^SS90o%pf9zTeuSH4 zX9PFFe#WKf&yftQVKUu2jNbZsI6I{VGG5)BQVTOIF|Q1D1UWrzhV$z6LgZ8ShLvBZ z(+c_D_1hy~&)0D0kv`yaaXrUY@&4I@uyqAyCH5N3dQFAD3<yF|1Acg)lrK`c>TP;& zFhHa!7DQ#C4!%3l&o-0gLld1nd(6@DwWvgQ`G_)ErONk5GpoVSMs5L|`te9Sa6feZ zB&l>cgw+%6pac~ePk~;@;Uk~Rdk8%^-(983JKzvl4-lp3)^wG<7bjkOB3_Z?m$^_c zs>%3qQ)KgsS0|+`yD6L94c_xw_kYZz+O<i!+mV9!&4JgXI0mb6#*sEhOE9{puh5?u zDwjo>U&pJD)8WY94uIL;S=4j01Uz-N<^oBmsTLjf39=qyXCA?q-Ht20dC&tjjpK(7 zSmOnyL?0<ljW5+?B?>+*VWVeQBh-WPoQZX9-{GHqIf|hz2tx{wPP(0lNzyPzPabBL zJ5V!)YcNu$mtV${suH1;7)N=q!U(g4vg2K|Y~?!#3Ko9@%pcV;0*(D*#6*t36v=|= zTA=UbXTFp|uZ95*?4<JNz2cUsjrNT#wjCY4uy2RBQjDX)^}SU%Dgh7Fj{p`62+&H^ zs4ozo1Xu#xt4iOouP6pxHk7#43+@x19e;i;ONy>TOOtP=sar)y9j#ZV${k{MYSj3+ zwG_dMD`T7}wg*f*qZfod7wfOh_gX5lIZX;EX4`bZ$RC3nt84a`+1-6nw6=AN?W51Z zo-SJSuF#%ar|45#Pk;H#?1+ey<8k1eohp)?*28ya3*w{wfj-2@l`)6@C1+_&=4f?g zQQ2`vuV1W)JwVK55wCpTLD<Q<ix9|9ZZ{h)GMVMk;N*94_iyzD0tRn9pEu}osZ@V2 zz*Tltd=gROnGuQta5x`V&ykWbUhOGxt)fPhpi1~X+#F0+w>N$Wt9?hUl4|<xC(C4> z1l1{h@=x68gXu}18zo7pn}gwF%qq+xl!8NO3ia8Kml8JxD1IbhHfn;~QpD*uuan;X zeW|?vTrrc5*nmV~IEd653Z_0g$l_1F`|F!?Fs;DbuD@=Y=hL9nRa{UpgKF2J5xhHo zP^I(m`qi#hi(~ENUDNciz^+BJZ&dAl)Rg042*+858jTyS)h(2!_TPoyXo>cLXW5h- z=_s5Qp}KKDVCGwAKYfYnh7^&a{B2A)la`%%X*LZ#<+(i^+gEA)H-MaHY401f4aM?_ z7>41mFMl%yqj-?@rGnDjXNJ@u?wcweq2W6r#$Y?tY@V%Ho!kdHG(}nrQIZ-|i5FTF zGN`k_=M^l<5suz{;n=3u_U_z9G)<;jDfk#iizM7SOVQo)&mX#|uXu>8;X?kTmcq(L zAN|%^DV=N>?^D#;j&g*7KX6d;RLPvv2Z<mtS7B9MDQpS=J}{ssB-H&R&^vsQ&L?}b zauVA$k#*^8+((Y0Yl;8S^0g=>MgH7TMBzx9tNrRjKi}OYj22rk$93f5vz%FPjRYpa z7AtdM-hl{<SK;U3!7o+tsj|a2n-XBDez#6HpEpNhTUs9G+Ob=E9`;#qppdHIR&t~+ zc3f+}Ln}uDNV9%5?L@~3$#nK8Il<2PJXpKrX-=jWc9zcp5tnv%KAeBWqg&(M1QBfM zBqm@rs13?QLG_V0cCWfD(?PC>sEeLQ&0Tl0zf|)9B*rtV+uG``_-$sw@2OC5oy~2Z zy{~5@%v+2MEr9umZa83vL_hno3%=5L5>i$q&KZu=dQTb|D<wd9agZuwOsH?2WwP9Q zQaxwCIw@QY?yinx+?M&oP)D-i7((yY?nhOJMZT1z&M3AuZ1XW34q~yHWrrJmrE?DU znvQ`nD5+6#e(5BWO_zNhfl_NPDxPV-zvm|dJmZAawKPl6%eRNFO<#RUWyE%7&FDB0 zZbjTi1Vi>r1tE-+EP5msGz>U9bRSGFqQSq!e&CbWu1tA~DfEUk&lhiZ1@O820Z-j* zo$MHQfX1i@dR_X9TLw{=_tO5C_7&=Oa+~UuEy+_;GAV=EloFrot=M+RoASZ4su)^< zfDDlBRLj}CvnZZ|<cC+?fjY)<=PnDcYS+4D=IfsIA5fr!tW7wwNy#vGOK@zq!Y@_l zRU1nWGkPkd9ugK9Kqw5uQ3GtAU#WRrG*}+d!`8+?HMEqWG)Y+#!n7*a+IR0~zQnGN zDGuhvb>c6S4)saliO|HD3cSnKFYQhYL8%?;O5}ZmN}Tz#9f67cC3XLYNd}`2!4tHS zXp}!p^{YW46*{yi>p*Z?)eIe|TO1$0$$gg~sTwJ6JS#w}aS^2M@OamTA$pU8XZ3C} z^n|zUYsOTBea(;kJ7qi~)b|407DO~q<K?%8AwcUD{DW_njP@r3j?~xd6q)arGlSlM zr14&O1xakHH!Xiy@EKiZ4r|vmanUt)ry7bhei#U_83x=fS5xtopqCgfG7}hqL+G0? zgd6D$92(vm`}ANOfhFsAs9%oS3UI&t1jb41I^)>-b_2totnvGT(6W^n&6Ak%zBg$Q zWqcIL!+E#4GcEe%DtdOWi9D@#gC3;7a%>`YAfv51Th(Q*0*{d9aJ(vl6R8)>)O7Bq zM1W|PuA=@vnNT(y>5h9t^m*p%oY(H1*&X`+8%KFeQ~NXPt+^(3&@zMM@`Ej)UE7-x zBV7`#fpUza9?lQ&m=L`$+lm-EgRmog6Ssy5sW$mLZkcT7v^+k>j{y$~?kY%)wc+bh zP!)+bxwue%Tc7lr2tc?b?+(*oPdt5Oq)#MM2u`T6AH(FI-Kh8Zf|iI~Gq0D;s~>&? zVp8HIZLqV${qR+tql>v?Ui2yi7Z5qDdvHpaFD)le;7@%Zg7a|69#6Hg{`rHOtX|B* z?Px#;YUQik$EAkac-8F=^1!`)Q_H_ExD+GL;_rLw-TRFAGwd~C4Nb6{R*X6g8uTKD zqQs4S{=>~L?T0^DYuCO)<nsQ1vDQC1#K{r_xvqWNqZ<y@Jn6hsAKUth1$fb-x<ZOu z7P!)Z!*epM0FK}<K&|0fn9;A(61Ca+nlm&Lsi3oafK9QlQ0Gg_5K{lGv&MCZh5;BY z$RYBBRm_wv!D~^-Lg@fgz-CEG-X&4noqc23M0glbX=?XIaBG2irG2RrNWbw!v6`%* zKE?Se?NkQcloFJ9en8{5mdaw=@ac{%O8?CP)~k0nyuF`xQEYbXI=mK3Y_pS>R|6+x z@<?5)<l=^Y(o{aY2G0=cnqUYa6Dz=>g&jEeMD5MKph;9egQP6$X3fD;;Z-8h8f$Bo zMW#~EVkzwgCrMRdUiVoz1B;8BwP7}W;u~U93Wu$5`jXqt0lQt=5Z+=xm++vUV8OU) zs(r^#D$m71WKO~o{k~ya*KZx-O)vg{5IdP$&NoTL_AO|-Es5O8bD7>l?KLA$AA3mB zxFDa>RGusa<TS53DgqQAjIMe&X=s0LHLp7S-!>2cszr&}h-g#%=NI<1!e11}^OG@B z4D3pe-L`5~pJyZZYnyXOrGyF(JdMt`qy>bsUda*{byU0{O>r}b)(kqMiSdbuAG_L! zm(BItNPw1@S9e8qSbl%bwc7z_6SPLiMm<~PzX2D*Q8d0CR@&I?rznp!I6&RZm*V{b zxd~6CuQKUXX>z5B-lnbSnChW8gu?^t7-H9y4RlzmdEVM|C^6SnJ(8*SCK+J&vA?Xr zV9<%Al|!wJJ4Yvg9={8Zc}Ys++C$**Wlga!KSQ&FahwBy!H5BFF>&?LUTBmFmXARt z;G={WXXA}FyYf}gdGJq_&ytLGam8A}1$^9$ewg&5E<MF4e5TmurmrfwRo0;aTbm{3 z(WzW-(Y%T(^*V|<MJrOtp7ghN#<#OizS9)Pu`#!E#{<ptF!H#+8?#4O)qL}`s!6Gc zd8uL?-?PU(o__&1=1C5*Ah!N0!};w3ZF|V-XfjzEe#P8kN7V^8UQTI3Z3(_nVOW`P zd;3=0x^;p9?8&i9fm4(IOpaWaZz?#p$)lH?6iJ%m4)b5XZ2;S{!_L_adkjo#TkjkE zJYqlown$O}K~%vM=6@^VHl=X^iqLXpZr{v?qC^JPKiqaFUYiHDp@4%3<dccfbZyr0 z{95_)nBSfKy0`*ukJ>t@4dT)`4qH;yZ&$?WKf|5eIr49K(C8<~S7-=Vgj-{wlko5? zMG@OVBxU*;bEN2axXQLE0l=@n0Y3lml2UyKro<~q39D>@BrqHgV;E_M>(CML&~}>z zB+^$f?}+-3u#5J;UYRNs|CzFdoVXC*Uf|uv07*o|ds4rRz$^xmR=~=REBmgef>jrc zEgz#*DTOdZ6F$RohACW;xP;?U9vWnyEqI?!1Sry62aW`xhkIxFk+Mis;{tfa@-bp` zvbgOnBd~(HVDqryd5zLKq)^Q$!cWUTwzYfmsdn=w9EM&B&ha5+0H)F6t?;9;B6R4v zV+=U$q}>MI3fJc1R4(!AUNV)!K|lHKX9Wu}AA`1uxzAUFeEPH))fIMX9FGvTY>Ic3 zo(}JR@b(>M6q>=!rGcDLT$ft{fY8CEzLM-sz&~DN^j9|NMj3P3$Vf0AMC6X^;x_M( zqEh*P=fqziL{J1!_b65pV2!R(!=15jNuf4@Q^h0i%`BWqH0x^_Q3YnL$X0ramt>pB z>8|w3#f0<P-4A{@EZDqRYmO!~HGFt3%B48#_0>Z^3?E0T`r3(Mf148fkTzb}SAOL; zpkyh>my`+|fhbhNz9}LXHtTNU4lGHRgHN-{(h461U2B6m{Ze16uDUvy^@Z!{okb}I zgyc$jZbSCak{{q==Az}C&^YYGk~OSQ$f3%98#X5QSwhDFhh9`d(Xsm{m!dYt4Bhti zt2bFk;q}1Tm@;AlNNJKj?$P7tcNVeHe%(Yx{;E~`1(XK3*xK0w{ven;F7~;_QmeuR z&`IF6;h8}Vy=HPQB}`?66oq+cu?EJ&byTL9^01vKh3<=UdGblsy(B~{Xw5}{&MhCw za`w|H4p0GGCliAOw!`@DQrq`ADyn#^P|ZA&>4RkRV4c^WqL#}7@8TuVcq5nK#i!Mx z#K;~9&gADA|NjM(K7Mw?f_YD`LZqJoSA_=c{IRk!7@3%=wR3jg6N#-k^^{Ux&?uiP z(mE-&aVq}=;HKx5V23>^my_tZpgKZft@WQ2;~S@LTutq8|CyKMy#SOsOX%Y|V_JoN zINnXDhLo*Jaq(MR@QFQD3&r3nkE`Ogk)@cmS@iBAj|D(V%Ur@deFM?eT#fhKUcnk; z18aCLtlAY(BW|i&?H#)c?3WK}?RCW1KQLumyX^G_8hLa21F+Nt$k+%{Td?fFwCAyY zUqA9C;X(XM;rBf@+4WYEQf$6AQMswenV8kC?vlD`uMbo|K<Ym3XT^M#hu{YexrMOP z%@8v@<%{!5vyOH%#G|-g0JB3QPtasO-XygYn`b#scW<DKbE3(-u$wJmxsQx?U2ZMG z)U|Cg>ZBA1wfSg}z}M9<Vfc}-wPty$wFK%o-q|U9mWDi}Ci$%AUwr0z>cp9JCDd$e zI3V(7p1j|{`}))SFTaxiP^6__y79}7^q#*R;17uU4H)1X14Fc9%`ld1!vLh-DxIKc zMrCn--UZ#zUG$`TJqwoyE$cU>mwl;srd2ECELuWjg|Q07=2WNKZ<GHuD@N}L)#GSj zP=3;8>Bk1<ap|pff~gf$nAer{X-yLY!GHm!vi&=gClVVM0t)|mNBTnNh<G>-D5i#j zKwq&y%dEl2#v4ZndwPqUYSx7mw;qH<<X2RRzm0CK4T6uje_dY^9vp2k*^WUaVwH`y z-(0_}*&rgWvUCFU(mA>i%7C8Te?8S0ArYrIi@0@UZRLLW*QEA=qzDvh#&(qrmIKX; z2rk-4$?v&9^vc2WY~Ox<NSc=x>&1z|k2E0dSk{cY8YLx4A{n|s2k6F8Q~B^spqJ3! zj@oLo13u|Uv^^;|`Na^LRzT0Aoc*3Ds9hI}<ls5;gSxOwV)-Op#MaW>0=##A`CD%W zi<z*htZs`;`b8<=e!gg}H4X>A9<!=+;|^4}n))=y^A$&9pXnbRpRb*DK~<NSkuHs{ zk|a6wCkqqrB%R>TT?CAPfw0T~jiLHH?$wIFJ(I1_E?pL_ngp9K&PKjzUXL0GiXgH8 z8!oc$gK2KDpm<pJhPZ|A>%8SH@4eP6d8Su9j5T!hv5~V77VV=cuj{^?igC^|l3h!J zU@KH|nftC!k|E4+XW(sDKN5sqG3Zl?5%gG>t77xuM-J1Dn##sO?zi6n!;80f@eDZ> zweS9Br%jgdIqRNUskk|l<{9~SvV<FzoOtkXIvj%v=4kZlM1%zkijNQZx6(e`ANdL8 zx~}A=OSy;Zb!HHLx~|4McX8HT216igx#Khq32)O#1*QVIpYi5}dlK!f&{=cag}8K8 zJBJl69jKW-BznE}$?i0LoK_3#Y=3GtFe8UazaWrf>CS{B``Jis722d7g+cycj@N1| za}wC={TY4OMg$m88CCzrG+DM@`tk&ObcMgJcD}~iF|`m5IEf?0F{dTAf2#08z^RFU zy+*(8HV{ZGwdO<^r8Un3r5QZ_Wf&)L+o^Wxa~9NbND&g^D0Y!4zZZiuC_4G>N*J68 zx_D*Ah1O<Cg-e7w>`a>Vq<95wdT$ZwX&4@BS+5LPDcvo)z67d^dKxYbF{>0-+`~Fm zXQ3$wm6&I@yQdd}#4j+ps&B@NNNn+Wq*$A!Q8?;BoyMxglGq>GxdRUXA4$1bWdMCf z)|n_8fZ6x2{oMVW^27gSThOkNVrCx@hGcAE19b4^lb?hsq3yf(m31M@1r=Z}Hgh>2 z`-%=rv+kFiY_iA7w_gRzC`+F+etGcjXHAhFnaa%dHP!1;nUxF9tNiMEFb$GBjz2&} zq}sbu08#za&O2zzkx<}}m?bTt7zWaGG^Lh|vZbf2D1p9kD{+1l_O$m&a33_a5EQe0 z6}Kl?Zo(8ivzabK8|;9cy7&q2RGPGj`7}d<PxWhJmCwxH%LaFDneG9qetYXpb)Oe8 zib)8V(pKRj)l!H+>OD$@aD$IMqQ63{>dVxmV5ofQv64@0e`Pt@c%khW(pFNvb|9L& z_u&0pGKQ3>UEv-Q{oYE5`~(LfnVJ&`qY8@xWJ>MZ^Qj5o0M}z&H!a%>kKp7*ajBbV z%I7ol?3wdZ?!(^nNrd!pk?!l56;$i1mRU>%<<K>y&-Z<8o~C(SH2(~}ALR1J(b%wm zBI%{L0^SjfD+*WZ{5L@9FX9}<j3Fx_8+>Q|BgVU@Kk^>lBgnCT$@jqFz<ho`GPFMZ zqPmi|P4m<}cb+CvQH>z;^MJtbGWDKxk-7v3@@(Fp#WATMDaiI2Murs*rwU15{;_@Q z-|op{oFDM)@+$K;;3(~sVrVMVQ15v~0mTjloOq5aa_X8?uR~f*2ZUdLHo$3JN^#^3 zb5#J9DbkPdtH&1{2#s)n2ru=VcgO^!X^G4jj6Q0krB#@f;lV0P>F8m|(ml%K*<9q~ z^-K`R3dJ}VJ~=)Zl-}ZdNJdmFiWOQGS%UH?pIGCPbpi|J2jcAt_fD@TQA&*1FJ`y3 z>FE;giu}ZU&=~Y}d3gHzeMQF!ir<GNWSQ8_L1gNlxrM6H7ZL>}MY-xcx-l;)BYS)% z6iOQTb%cE~YV1GyCl0cR<TDP)*=grrt&+H;?;hdG%wiF0*>@XbZ&oX2V1nVkZFd`j zJhUe@z~P$It#VP*FL<yH?53^F0W2YDYp#;Aolh^Os7NBp2VsN#=u-3o`@wG6)|ymO zk+qWF$C1!^O=oy~hw~k`2qX7*z_#0PHEw$0hb1e;DsIP`2EEA+Xb?^*7h7Od?@D8U zx8MpI2;i_j8+Sjj36k<IVp$Z)yF*_)rcqrnI%VDaeAvI1X#W+U-|ezN$r%{=ZTzW} ztd*R!+uShhIT2oSvp8um-DU@o%tf?d1HtK&mt>#rNqt%4=V;1^kkaswLp^|WGwSIv z5MG*@uLJNn;}W#M9F(8_pZj%O>=klEpPaxxF^v{^SRuE%>Npw<RLeR;wWcWP7UBhA z%GY>7Xj4Q)a`m|oCY((N4;1+XdJ7?*C(I6;0X?!h_=P~ByDCKz4OU=urvkobOt&ib z{q`07P?;D*(DGBgh)hwi!ICtZ7Q8f&h^Bt!#?|8eT!CV*5;8sDC=o3Xg<jSL*-55U zPH)oy80yxFk8`K&->s@!&sq$AVL3~Z07+mSTP<~SlvKMV|NP_@R7!#^y-`&yDvi@+ zR;9;X1~+p_fkCgc0VsiToJcJ~9DU{~bZs^0j{ai`b?QPH!>WOy<;Wk{W>R)Z-ymf^ ztqso^d7J&02F_D6wJ2A2eu{Q=L><Ck4&kv#<_2qyMX+$dJ<)ItBDUdOI)g?R3cPC3 zm~nx-M!ioRc#<n)N_*(^iJv?>dMAiJ>4a@bEvX_2DoRmA6N_Y&uciV#;uTFcXfulC zukt}RvFS!@Xkn*w=28+3UT{gSOF57pXDg3O31Ah#@AEzYzxg;ND9|_ym%mFA$+Ark zK#=B<3UZ6n+m{`m=SQeIr0ei1oRE8Pvna&4<zNjhUE`X3E<mh$86ncj+vTBM22$2$ z{VLm=0+y`uArJN+T?Z%eohH_w^f%V6ijgXi<bLeiC>t(`EnbfLf)YAVI`6a$%hBVL zCZk(i8ah9gioKCk70U_u_Pq8i`BbBubC1aL*5jR*@Tu%|jI$i`j%mN29}#`^;}xCX z(8D${S}`HHm%!vHu0WByC%+LzR?jtQQG$~ck^KoA`)*J5^J-%H=bi?ft2|Y93YadB z=%q{8tv4AX=kt%`H{lXM?Tm?<$r@-TP_^cAyD!dNE}o9}D#&C5hkQTmR^4UBUmLHc z1*If>BJrj&EL3KQ(C<(bm8?0WABZZWu*$GzEgT8TB@yF6*)}dGa$h@lu{HkD|5pEc z47yqxp0jd)6k7$rk42JRF^ZTBH%EISmQne`$Wdkl=}RmdZ9_SP!S;q3XF5c+n4_R? zhdNs9gsK*}<&{7>T%%kp-HC@D?8Xs+euC%yi3d-L6d;yhC3YZqe<=(}MoOG;UoT9` zDhx6hv#tvPpwRMjgCV~GjBjvghxQ}u-ZQ0m4$vJX_L0eJyWNJi#KGYL=;aZK@)h%M z4O+#kGl?C-Ih7Dno-uzRI+2(Wrq+WKJa|5WT0PdZo&5h;-5~lXIp(e{Kb5aQ?Z^Y# z_xz1YG?Nd54hbzG!95l#r3q4{N+O?2UXBDjZMMZ(u@-jYf_goTG~KCrdZyMY23sFv zI(F{nPp2Iv0BiahCJ@$w6p0GXLU}2`;9o_}irJN^7-&;V#FjPkp23jv9g5!oid3+U z)g;w-Js07@Y~ZW!Z;n~`h&4u#!u1k8io8T1Snu&Ww6I;xWf&tl6Fc78FFv*W(nKU6 z-V%BXm;v|HUiL64DQRfS9eh{=jq0J3`66msKPwSXEk%{aBuL*dB7^cBR<r2g&{t2< zxN)d}J~Cx5_*-V#SHUnFnOM*Ez7?1+G!n90(9a}o5=dtud=}x(tkoRFbQA{Ewh5e~ z4ZGREs^^{3hc_V_o&vB!Sx~LAv1$!b)yZ)O?A2YKrf3Qbh^xtvcM*6!zOLPL*u|qX z-n1JC`lR|ga|eU@CB-{9POsYiPc3Q-XH|1el~f$hk(>Pml-`q9QMqcXfkFW$Pv5-8 zl6%kP;}TGbtss@{<<m#{jWGdZ{AHFX-<?#jGzKCc2i;l&Y_-*rfoh?EtgIxHR`zQ> z2q6<dXjNq9+@kr#xOwQ?1QEp%kIW(S7ikrW&lmf1B>#c%d>G~Ovt*L=v!lJg4(lMV zRJ7EgmV3P|M$jdG4kPCCRc1*I%Wpul@9a$swa@d<FYj!NI%O%MMNx^*1YYrMw?#$! zUHW4>YYqvx@IAv^5WX6D0bwKZ1oIc;`%#w3?5&p^Dj?TE_CoP7o8tNgP!;4F3dgV5 z*&^-~UMy*O>6I^t5GW$$3x1T#V(^Axf9FRPePb;c7=H_n<_W=m4+~A-I-1)uX|c<Y zqZFacIa748Q%{!Gk)om$O!4+;E937`U!e^OE0+IGi-Mg<Vi)09{Z%tGi0OF@F@M>i zz5%NBz8leL(xEWqqVXB_=a<}5>qvTjs=;HTMX(bhifP=G_*eRcgQ8*Nec|pJu$@6R zduXxl5@aS`oct=(Lhb}2PqPy9j_VA5j717Zn>O1#WG5~~l*#=ep<|F_s#fNE^szo$ z;S^ZFLwc|AUq1+?$YpINEm>c5GSm`un<%9Z9QZ5y5du^>GQ+FL<8U+GToIUX(ykTx z_@#WvA~@Dbs!2Nk-LoqmR<rL~`E{@K>{v{>1_nTeH3phvx&|gh_sKU?MeOPywh6qJ zw#Ja1N+hw8hotM^3Qoc?ZKOM^kfJ^{AD5u%-5Lz!<Drw!$7$DjcOyj~xG21Z%nEO) zmynZ!Q`PYrLw>%R<1h`{MSGGZc0i5?N}w%MwpXBn6CZ7|BQvrGzv@oT_lU1BV5img zc00ya2#M|fJf;6evjTagrK_y8%YYSS9y9@do@iXCZ;dU5Mn%DAiK@>}4uh|p#mfA$ zjSGn&Eoj)Ri;kCaEeRy;I{*SFGx`#y2$5`JEG`%lUSVQSA|@lETOz>>ZAC8Nc+Z0k z6e5~)WlfkE|L+Kvzn6PoTsjgaSoL^gVpsq;b|60CPf~@55`b6R5@GjUTp#R>n&{%* zXNMZ{^V&=pTe(q^1ZSW4T0<fm!JoxbzE?BihJod?V+w$x>gl}vX|r-=7cW`?B3x@A zIV$F7E?Uh308(S>d-)s!6?ry&(l>g^f}vhEvn5t)3)4y?1NTA(DSQ}qtOby7s{6B- zdW=|8sL=FjhW0v)_1N}Jv&ex$RQBt;KQ7<np5{PwxG==%dcio_yc9-b-M54{2Gm+e ziLy*aW7GgxX@<e#oD!C+X^9GSZDN6RY#gRVG`tVOW69c!%(!l^v2a*w972g9>dX<M zLZ;to?0UPUxZE<o)}xoMCA`MnC0zG)29uQWtSTz4#1d`Q1#{pTh0-%7AlpE@oFQW6 zE82S5k;O<xM><R|o(vEC+<hK1-wXg13jbg{%1_x>3MtP$XVj|%qQwXgS&|D93RJ)% z<1+C!^$W}3upUVVWw6dFr~DFe7ho?YMg4ufD%n^x7qbq(nu38+wp5KAeX?}1yxoo` zV8uQX`XadWyxUXsq^kS#{vW4BlrOX}iJljmaY*w}J${t>9~=dyph009ZtGGd-DYcm zrk>diD#pLTob{f_TEV~^<-$Y}4+m?piXZQM5r(RR0b#B$#PEo}9-hpKraV=TRBH9- z;k7aOq@c9LEQ@z26smKx$abA3ooI8%y92FeL6e$pOG5!Yx)W{gwf98NGbqptZ#pZ7 z1C^JyM!PKa=23DD$OS~r=$M!d(4IUO<%{yCnoOZGqH>9|A8v-a#xDYKFgDfIH(gul zMCy{m$Z@AWr~C#qAP8|NUC)v6>o5+HO7DS8aqAy<8iSC{KL05FL$!|~AN5=~+|F!G zTBQYLp2Q+YMdJQ#Gv^>uG8`R&9{#@pH!6R<6{BKt2BT7j-ZkWM=;%N!0h@kw^V}jj zqg3D4u9*`0*m`iRiO~}sJVl3-9$C6*%@|r%7>q$cASTXd_1oEi5(lLQJd+CEia|IV z-{+`U5;PxXJZ2i(ia|-F$zx;{f~*OE7N`>P?$7wE%r{}a3UzMrrp6EHAW&PliK0$o zFZDVx7wDBH)dUl8g6EWYsL))OC|rV=X467%?+G>O3)HL_VgR4M(bC>^fo;e|5b!UV z7Z<7=JqjGcCXdCJhPen0`e^;}>Z~=b3?5tRWMpcijVHepBwx#gt;#%Wa}*-YLb`B% zO=Lh2!ZyoaqSZ$Lc`ror<2L}&nr=V~3;+fM&7Ybw*xAU|up>hmr~bxc5IkRmdHRL^ zH-jPa2%@V2@Nn*%e-5lpm<qv3MCgV82aMCojuZhB_!5w+e(c3ezmj%m%S<kL6NHdZ zs0<*`+>C7GIZPVi)a6tO%Gh6J(&Uf*##3g<t0>OruJ{F$+L~w6zBfABCY6Y4E?aE$ zl5m{GfJS8W<^KP^JHDm@+O12^n1G!P=5SRL)<39`oV0-EOm5Rh-iZkjfO)LbegDa- zH!^f{0QTd<>&2uomyu8%G{K?TU_mLLlH$yM*)Fy$sgz^#^NT8Qg_PIM0gB7JpATvI z92+sT4$+DbJC$r#Co1E_K6MGnaYW(m5Bz`9*koK!`3S=RD%38yD0?nio<QBbe**v> z;+ixlcHa~(2VVQJMSzQxE%B_}<Mzu(-Zs+HtIMik<ez=ZsSGlo+ncw1i97Y82ukka zOxV7B6+;D1{RW8td95#%i~fV0m@cR^x1jQ@bxEUCl9UOQ#aZ|M2{iQTIQ_1U$L?PH zHas)Tt(w%cs^pu`_`e*$&ey*EUynkqdqM%dE;H4tF9RDxMdm%A7Jr2@R-ccRDD$Zw zGX;KZ?Yg3oC%@#5*nQ5C&fuZF=Q2fk9<WX!nAl2cZGijy3$8*lv9qv{N3_(FH``}4 z<QV13-NE(?<Yp#N={P|u*A<_fvecC#KMTl<=X?#nXm&qK|I+>q=tfk1|K-XC^t0+k z*vsPa(gx9^O8j}3PM-Y+XpQj~HlYhDACzEKvVZ(I?XynKl2PZ8Yr;1WtjNoA8%hH0 zx^F}NK|8&Sr~2ZP-(#qji_L`ptzxz$mrH$Mys&;c<<_SLBK_;Gh5_1Y8D%8wG`q?j z!oA9%$hYwbVlUGp9w6x3WWZ!VS4uxN%f$exS=j%5b9|YNE_oFKkplmBgU+e7T`XTL zrE<Q-{BHjrWiW*25v3Mfb~i}+%#D4vz*JuwQR?%PW#P@QVwfM);C*|EutKbqxl{Jk zK+(6JXFV`Zni|57*)b99@~Hg-wh1EYUAQG;Mo_Bf0B0BBad%mebz>IY?SzOR*pEGO zi&umzy4D@(Zop`Z-GSrNU0=k!a&6iV$ze-}wvHx=58k8mzBysR{St4Hf1K9G@2?&6 zz1fK4O+5wUDqiJ=u711FKSFp&G72(yGwmlg{adELT849rmj9u5_3srdZ1Of?^kyXe zBsi!Lh^o8V^G7@YQ*x8dO}xwG|L3Qh7ug~nrkMRKxmnXXv-0xgL|;BCdw}Zd`6;fR zm)lfFz|Z5KlGhZoF*$oq+6FDp6dL{=NUYj(OdiGL`Ym@(?mtGnLyk~^>^q`&D56!z zZ@}c+gU>e`4;Mea{d)6%KSuoj*n11$IF=?sc*HD=S+-=!VrFKtn3-j1#5iJRX0pZ1 z%xp1O7FlF5Gg{2L@q6EU`}TJKi`}^UBmVf~CMKr3yL!5+vMRHZI@4E>e>7`nJd#_V zwdsDZ)oHn<#If*AlZW8dgyhQ?usi=W|GNiZ{wqNC%J(2E_L+4GYz6!ON$vTDxxoFY z?k$67>Te)SIQ|}g>;K|H4?h_a7`T5)BpZQ}Q)WE_p^$~RxbY~DUmvv_|E2M@4BEC8 zM}n1(bfPJ2M?(NxLXHs!R3H{}@<TAVpbah!yl>b3{K^6r+rU81mxv}{GoSk3D%6;W z%c$Np)BfqyyVXYoIS!LUX50KTWa2lcs-O-r+`;W~wM9HIG7OMf(6>LLBd!_acYCHJ z!Ks<~VX?H%UlN3cceU`9TW5V)hza&)uP+Q@G_3_jt4ZE)R6rLxhkZ0vu*fO0Z@fpm zzfrbWkp*PEiXJy7MC#@g2uXZPszNt1fY6Y5F($j~_o>kI%-;;&PchZRBrwE}jGxEA z8ZUAYn!2y~O9rA*uFPyDaRx?Zlp<vHujn1)wwb!l+8(Jr>ip2`D92|c*R3kxW$;+E zu+ZZ5*R#a(e~pR;i*__t<tstL7+Rfu?gvDxSeCETvyD&~p&!OZo=ENy1(0cYLK8~J z?XSmq5waS?b|x4I&*PJXtm+q%{Cj&zv<`Prd~D2330zj`r}q_QZ2c|+Te}eyIo}f9 z3?_<8rME0dTvibFiBkk~P_KDem6lk9g5C0!NaQX7<eWt7Q1&zu3FB2?YBj?xP*rh{ zNB1Yh0x*KB80t3k<UqXJRztnM8v-anEB*NBaDC(WoiQ-xXs&A{xRc^Y@l*1spYOsg z-fQ5(b#DwB<m=kLx&Bt-T6RcaF_IDoC0Ei#Xx~~cmk?{^2jdgcZ;;`jo`;#AFkK2O zT%Gbx;c6sE0fi(Md8qZKXC^&=I?H|-xp1!YQ{};<*Wq8b+Hd}Ti=z77@wG+283T{n z1-mzyryDw303_>OZp@~~^;6PNOF7l(qp%LW+(p8s@(Bh?X44v(tS0wfkYrMzT%!DE zi9(VBcoY<G#{e#eVQeu8f@EpgnAMx^>E%iPplEzCO+RzC1-660HmZE-BaNy$o|f4l z<9SIhGpy+_*!02AjAMF``dvp%j7sEqJFc)aZ2?TAc4#N(*(N5+eVDLm#dsFnQ^9TX zq~uoN5ndk}rRAK}`b;E^0!3r)GVIr}!j7WXJG4vHD&}4Gc&;Okx8O0QSIOiP5e&le za*lE<(2)IN0_6!}@DwcN2QoNmZ^yG#<(S~A*dC36<|R2{N26gwLO*vLzJ)#jX_Zm4 z&*dvTw<S187Jo1-_7-3}(K<sq35X67wfN(jCzU|f6KpRdXjEJsa^bFbnU(ehv9pAa z*A|&&Bz!`oNM9e<(A@A(#g(M6jqn0kV~dJhsB9EMYt`ymmXMB6i}HxTS7KHggNF*` z9+d;YE*%<$HPNetC$J%pX*}OiHMD}XmytoU$grl}UxxHoMQRw=+qkmDM$3zu2FC^e zg9X@#M;!$yvcR_wl88uU|9k})sy}&5k+Y;eJJ0L=?|(rL*LfdJeU)pk>4jGst81`@ zYp?BZ3WES*IB^(5Y1E3{JoS=M)I+4hc68rLFi>Ya#KPUwelg%(wZ>#3CP^pan;>9> z!a}8CszAt3ny(g`mN1Ab@n0S?1<U0y^%+(;T2|cZS(N*i;p1v#e&WoBkX-epegH-( zQ6jFT5R4(66qMLYTu_nXP9~*mG4CHM6y<V!&|83NzxN436SBALuNXiaf{HA4#0c=$ z<#;D!SkcD#V)8pw&tQOZY7`vF+Co5-5CSY!O*swiwQmirIBmS2=8(Zr1s;=OParJv z|FI%KgAB1T<g2avU%~ZJKNUBq`Yns$!2D+O8>+2Mb@34xQ_&95czF1rE(T5I_<A%^ z&319Dg;exW?0yBQmgAiYJGOuBX(z&6PpQ&CZtrgOm1anPG72<zBL7T=Hf$Bj5H~Gt z%e5?mAiYA!c6^fEKgtn@N=nUMijqU$1p3zcW*jM0`m2g&0exOD%^NV8UZLWxmzV$2 z_c`jRpD2c?SVJi12S3Y-=Pa4%1?pR7;064!2(2slAEiA+WNA6$A4?ZVcOgHxCPLmj zEWcnrldDo4miI*Q8}<8W5(Z52We=Sk{A;J!Oo3fyx~o?Fq5J{T?*kJ&fXDvirKxI) z$YnFg^H_2kT9pTmhQoaMz$v0BN9Q;lX?TaL18sj>x97mmWuMZ2JIxD2fmbY-$~L#m zDZ}sjJ43W8r+^z5+NFQld*|;Pfrn+(rVNDLH~gHTa0e9*&36>1T<_v3&|`LmpktY3 z_8^v~-&<F6BU_w5sBKU=RS=cXR%IuldRzt}`AIc@j&srV4%@H@+Q5%K>^<e+Q2)wD zBqXjJs&2V2ZN}PvkIMj2boJQ^5zVV_=s`-Rt`-%&I}{Q#gKlR?VrQM+0^~n=?=zTC zd(3pzHF4n!*5zQwv+X%x#5iN5$<#_jfRiWq7K%UPUje7GCA|N$0$cH%3_$7;QfqDB zZJCC1YG-3);f-e_u~Or2Qd{0Nj}B1GJ*Omao}4=+LX{*^;vuI@#+&WU<veT^@?pQX zDZ)<9=B$~A0QnhCsOM{b>n5fxp}}7r^z|E8z*j#2@WSj#T!iO^bxbbDE<(Gs%PKMI z0h5=K$5O)H+edM48h0!v@KNHI7G$M<>)2m~B$q1Wi?nk18EBam=e|_Ub(^VOw)Y=9 z|L)jWdZ?!F$D`oLA9=$+X;|d|D)mJi0kOaN$2eENiIFVX3t%GOm+c7(ch>*><Qu#K zjF_<CO@(Hy@jxUF-Tzz|Wf4E#VdY9E)2Nmz7yh>jHF?Q^9LTS=v~T;~$Q-`{D1W<Z z1|$dX0g%k^qevUHA@uyDkTTP)Zma0uSbwg8OcOqMaYZHKvfltl?F1L=Xz(Oxg3kJ# z9@j_n)&I5PyuVEZ$`1e_fjDpRtuFs((;KlPG9o#aN+z8slQH1k^UM(;cY-INQVp=9 zNE1S@Rk3fq6(xUscNA}9xl^ucM1_<X<*AfvgiX!8`I2SeQ67md28b7WmevTbNp!B` zgDUfakI&K;t|W<o3%!mf<7)`i7RGw>=7f=06-?s)-LN+z+9NCpJN<H!a!j!NR1Tj{ z#SA*6OF$biSm~4J2i+wa!9VVY=Ns8wUDMLy0wFF$aL+!eioz<Wei6VcnTg90vRhS& zN36+58A2|WMW_12LDlrJ&oqi*BP*<C`1{lqykEjsgCJUp=h|a3XLEFE4cM3u*Q!#J zKrx&~^{QH81CU>?NC4L7N{wQz%-Z+e_+QoqtbSlbOmlP0fjt3p2m<im@5xU%U#nQ< z(iAlr_TK1I0>J5k3o+2e2(oV7TXSikk&*+eN~4Y81!NI~43o>T=6Z0CRntik`cpdh zYA>04BH&0;Ti&C?t8jPs3%PiRtbd}gL&e*ze(Ptxo?}g&X!Z0ZDO0%;rFSe~zau~> z@FTHc!}BKa-4(k@gKmVplTj&rET=>qdg;%BHn@v^DC3xu))tkiq`&o+p>$BO1QL(w z-)uPewef=dlvCK3?LTEW!MS(M1Q6O#_Q%5c?V&(Ps<TCS8N%zT6}s}7_NLU>qz%J_ zIuFWjMdSs&?>B<a2q|jv+QVI{VM|!DD|oB6Kn~)eZorZa72y7Ocm_7WPSWcl2&0)F zVt<Z|OBCs`C`p`696AbF#}f%ki?Jsf_H#=hR=MJ$dM7K~)qKazaMcZx!Qw^=+b8g- z&xI}rgkO`~Y#A5@y8wtFrg{=&N#gk+G9~aulq*mNEtEH!B2lut21<Xba>*Wc>riY* zWlH@Z$tXSli+~ZL2fiihTKN1vZHEn;>?2NDNwwZr&p6GOPO#tZc?7&Nevm(zVX)t< zPMZI*H!GTqFhpo^<fJ{IsJA8&PXekY4$4C$WO<g!8HOd9eFlU~5;IPOO~q9xYEekE zi#Y;-*&~f3tQMg|wcV=AwTC8`Fvpp%Sy(hTY3!jV$nit5C%W{5&Z8#(kt7dRL7DZS z#R*{r+vqd3LaLMo+u5fJlCOjoKm_&Jp{p^GdE6vg`ze-4oY>7*ZT~d2*+bYqibG;S z#T3R{!^_(-Y;dJz*xz=;j>#UV>QO>-4@sU*D745`gxF`@no>^1uCZZ@c0T^q67mzi z5+%A|2NLfGywvjN$UJm;h{GuJsu&Ex$};s3&BCOmM}<`ihr3ETVUakZp;rLhzwu6> zw?5Y5#NZd3y#N4S1;2>6Ae2DFqgMd(zoTc2ilH+(Uwu^1Skxo}p4eyAwrh}8z)`WF z|9Ka#BjgBl@!LCc#XA7NCA;n~JceR?XSCDy9^s<<rEx_0rPLK??~kyPZpN~{Z`1rO zOBG3G-u)KEeBuHr0wBe9=HWkJa(x-vI`aNnf=@!z$tqzQrybeV>&qq4qP$U}hD1Qf zgkA|*+3*WBdzXqOj}gfRCu!SbORh%kGR5i&PQNLn!>{Jv*ojO0LXnltRd%EVcQ^d@ zSwC>;1-X;e|Ck~jdG&q#dy8j;?-@4vL5I%<-+k+E6u<qsEA$B!Kqu-h6g2~(#|sN` z#Wl^BrZ;}?6vlo#X7EdQFmaInWvKv&UOUIHYujY~<AU#WPM+m75m!(NwYf$G_Vd0y zuutd`P#e!tQ<S+M`7@Z3$U}l`ulqq@)pWjtr~{)c^YK8N)Z^L(7QRyYD*#2ps_SP2 z5<RVjOd+MN0%g<WVdsh+6*Y$057AS()^DMQ+7_R~yFAw0?hN4(+o-#UxG@%n!|m%+ z>A%n<=kHw(Mp-a&tPJ)P=1&vd!oDwoYW!$V>&2s(x3EGf_)hrb+1(>L9<XB%jc+DV zxDM)d|I9ID;=&=oV2?K?3Zpl#E3EB;6&zqgVrfkB+484Aju9v!N0cyXsBQHgw!s9a zt!I`Y35DzV-9O>fZHe@bjR1>^te4`$ZQf$3k06*Y9SR{7S|VYaMU%5Y2AiJOww?S9 zvacZdWVe1@cdgC-IK*>|m1dvLfLQo2h`#<s5xc)$8Weq<3gA4zhUmrB6v~q-JEtkv z$bgbd1ANf0&IW@>WiFc9cm?_lL6FTHUu!x=rStuVBL%1oD6jeScJa&L)ER%n%DlBE z7HfR9E`O1?%o8g{XB_vS?l0>A$fr0Cm*J*TLpb>YPJj1)n)la@<5JPXGx7ogflCh; zSKK7WWYW&8UhCZe0LbrCwPIrGs-AsbcUl?tOunY-*m?lf{!~&B@sQ2N`dOfa?fU}n zah_n8$FaqOi~a<E+j88h`TZA@=j^%=b^egIsS7U(;CF|&`naloJQ7l}`9ouZ6{kLN z$bKAEERLKz6PFIHc|g0hDKPmChouWMr0YWN5Z`1(cZ=-TfBy?N>>np^u3YOXL3CoO z3c*M*=Wv{QuYe8D)!WXqKYr{2<Vs*(YV-4rnN;Vy<DoY+CSCzhe^*auPtjA{PHP5- zMT9?+S9l`xGuB_R`3I^Q--;C~zW8~n!vC<ZEDA2nP+f#f-t8edAfB-Hw7VRMnk10$ z+VFYzdoop<^uC*5&t>Er=9EGPs0wMIa{D}!YSUBNB0X)Y%jBJmy>sk*$Tqp67gNn| zn0YX){$dRgu%HsXl|z9YfOyPyGwA3+-EV2JYt|W*jl9XP@=mHcD}rGKKX+u!Lb&(( zBme_KJ_diJn@(IGJthKnc{VbfKobQni+TB*+y=f;fpZ8E@_254x+p<ff5?7?@)@~L z06dZYTc)h{%Bn4F=FC@~%%91RB2sVpvg}**6E}$Q62ZBU0VE43s>V10N8bt=YHLZk zNCq>Ghi+xnLjv3d?nvf!2_#Kmbs)8v`r@d*%46R4;!GjH2u-_2k#^@{Ddaz5{9dnW z8lVb;CJ)cctgNTK;;-BXXXF3H6Pjepi?687KWZive4M7&GOlj-`1$Yu8z<j?S)Kpy zHQze6j3OW$pZ(ZKICWw0Gdb2MwD87DWIQTaD6J8y>b#grW=b+c_RHEG+11B|gjvs< zz9cz@<ULpjpxu~8vgN&FE=#-Uw&PA4+-@4oEH`TW+8;E~&D7UkD?ltW7Ae;Ptnj^E zfX#!^ALK?+eXx?bp0g1};EkWhQf8K4QD`C~|9~2+vi0PZ>piP{NGreK>KFTlVduoJ zVZyF09&&Oo6pqS$vt}gEdbm9Wf?E)B+31}XDW?F;7X7MH!6D5Mlv}c=p}7*}uR!>7 zKNt5nBP7%eCh_>FT1h`0h$g|n*nMc&Fy6>%2>yY*FZ;R3-F?CyJbkf}_8%05M=-8> zox%?waunmzEuFi=?>^e)OmZj`!4mYl%dUpqGElljb(<QAYLZ%O24j#k?*+0hOUYa1 z)$hf9X}+H7K-`PM{#Z<m4%2oN&PX;}jE9D<V_ej@r`<XCENCnlp5f~?se5;mq%*k3 zwKPOWEBt;}q5Akwxk7-P6Gpr;j>3;(1sprL*qtepWvrP(r9u5g=UFDAP`jhL+kz8< zM?IB66#9VUDK9KFmQ0;)_NwAXbh*_K{vSe#;nbB@je}8lsrbOQsL$EjC$ix*4`ScQ z5Ia$@RvS6tOPQsC|NhI@Yu;GrrrnzL`8Qt7XlT!oCfcy7E|HB#85D|d)`AhSs1$QW z{+mUM*r#q`w5_3o7$rw)t})mG%MQ6Tu(zrS&i=bT07?XJ)9%I_33XZ0xZlj#7s!kn zR6YytQ#+%=AJ>MP7{OASl1{^Q4&V7VAC(cUo3b(ZP@$sOP%`n<sek!VJE^13UZx^y z_cW2c$I+AIW{sgKiwgt<m7Qy+O<iWJ*>;QQh<7Eq;~K`#9ET(;u@K#DFqU^zO}h#; zIFKU?*XJnjSBc2Uh!y3%QI~vIMd)V%iDui<??eKzsp+gRX_&*$EYUW<z1=nqF-51e z%|M!Cvp*h$Q31&~>%SK49fJK6U=Jrrp~Vy;bPnrG@Ciw}hLF1uDdZ<T+si#iv60XQ zW;u*?WCDvbsZhju?B8<Ye^g#~NkQvFZh0dsyT14krjuXb3OTvI3mixQYE6?!;qJ}f z-$5(xkk`zBLlGr3BqAGg#6~Tj;Ruz;=eliCd_zM~=8G=IH+E*e^*4pfnCUGv(Y<N2 zO2s0URzzH!st-jMM<v|F?wi?&(Y#pSS%ZqMQy>y$MCwz)y%{J$DVHPotO700FIl=d z&`B4|L?F=GIAFAzYot-E0d3hR>NQUCm5%MMP=}Pz*w|H2nN+ld)olV}vIkk|(?0&( zyjTf$Q^&>FU39;ngI;~j84|trp;@A+MiuNEs`I>0+;afBwh<!~BHlfW4#bQ$#E_M9 z!-W)6q&#w0k554OM=5JiI$^Kbx^1$IHo+v=n|Gb#pF*{XpH_DRw9VWj8aQ#=T9=er zJ1?~BQXsKFmlN2WnIY`O(IsP%75cPS2+pV@P2UFRq>#Fi@7e-DxM&Fsn}m|;C>}cq z{rT;1xaB7ufx|-KF9myPd)bxLYzqEWxR{?;Oqr+=5=XH_rWVAc@u<$oZwSVK=q&pc z8nw{}VJVPmlbKr^g-itOtrl~-MyqMj&~ZbYW;W&MwKSypkbdsZ+DiQ>Rn2Kn``RRn z!IH9)?&fTfSb|HC+dYRwI&JF*(Mc1k`{-Dpx1ZSyyk@16pu{=Hl^WYl%r-3O_K3uf z_MxfrSH7X`6bB$94^#xHXmQ&P9N@ux0#JiOz?OTJnvVhyxOr9>a3~Kye{eGDT5KxB zC1S(rX}1e&gTQ9Se+Mp8kzjX+L)R^3tvnogEb?4Ahh2?_j+n@21ct#y!mlSOLvCT5 zI3QH|MayqS15VgD_v;Th>-lk(n`R!k6%JcTO(e=R$M6<X<agYPp`)F0lQBq!q@#%B zxK_mBQK&JIK=JfVRTcEZnC6;-Q*fL^M~XN&aA1!}4vF&|!W(l`(9NU`)VqBI93yx_ z>0Bh{zUk85PTP5w2rfr%-o?1hxlD?nk^mkq8>;goCq;{(%m!f?6shPNA!Ne$4D)C! zI>-4)(9(@~bQVgJRW+zn-*;&jK1|w^u9<rf`g9rOcEDELeS!PzERj1$!<qMv`t7%B z@fc@h_HfkwtlXg(<)8ji<u#;*Z{66p5C<dYNTLKA@#*xIAZGB`A<>KadL~ur6~H0S zd=vk8?`q8YQja&l(xp!xtc`dD7{puu!QMP&gL#&IVlzVcH|3)NbF^qO^_V;U?ZN-b zN+S616lwC)=)gOB`?tpn8T_U}FJ#Ovivp!v?fftgUISS#f||QV^_i?gj#T!3k_p}* zbJTz32dClvkLpL1KU5}n+yStaXgq!(s+fU3XACUVbq>D_Bb019tXuUQG_;YIYbABk zl2Ldl`{{=Smd3-#k>n!h??`?i5g4+VCkm?gsA!?|&6S?^&z*QtCBnnI06Gz-NRn*_ z<Ud@CnJj0U(f4Sia;d;kH+{ddyl_6E{<*ckwRXzD2I*OREVJ|&Fe{gp<JIs8=UJgg z<Uue?td><h!i|G8g)SptzF!^b2tlFJ<u+C$A_Vy(NfZ>>VENNW&;ZQgGfD^AbLU5c z=w<rLRH4U{NTD?<aovA!NLC+&!HE!3gzvdflNJk$ZUD;r{w=j{C9oFch9X~jM`VS? zjJXJq@r5)Dwi_*H%hfBj!NptDsW2Knykt5>ybUI)u2ve6vm#GP{`{<|3G=-Mr$z1) zqMMlC7b3)ejfk*%JJ4w6v449KjDCsCkK5cOLa6OxkCZW7*0B89xv}ChQeQfy1h|P! zfn*Uy1bthKAYR6Mpofx#C)AsBh@SxYCCHXLJMtM*yRcIEshIcXFRHtbFe8KF>%J*E z1j6DxvQz~vGq2$lMqy!h;2o(H^S2kfJ4digJFI5RWy92bD98`$2HS;lEN{uf3&?qm zL1lh<MS~sbymObL)`o9va6N62WJOt~OzDE$j1|k-i4LXNFoX$6#i<c=j@)uJ?9pY7 z&@TOC5g`NYiqK7<f&#G!J~TW3<RclOB4s5&m0pNGB^*<pOhF?;myKL(>1D6rpy&M+ z_teM4Z;I3`VO72V_xj{x;gj_0v1#wy`|TMJo;;y{@{GfM8^apWjy^kwx_OgLf(<Eu z&u%|k2dNoLv<<C0JevlCQj{gAArQZimAP`)j5|&q;EstF)HfTvGk+GERwpG|0s+u8 ztQBve0mQiAchfY4OsG1xu-!elI`NaWZ#>yu=@AcZ4sUOTfLiMtcUvf}<n+yOtpiR^ zSG&riIN{5-#bOQ9hYDcv&lw>mhw+|;-m4)CKNxXoTJ$r7PaVW`&<ZS$tvf^}s$mpF zcK#f9yQ7=WZ9^o+HFn_zGQ$}O(O7pcEy2Z?LpDN{xmExWpch->Ommmlp&=&WL48jq z52}hMYSpgjP{gX*WfvPk;WB7sLM#LWN(C)>a>tS7LHV-dA}cYGgV<EjqyS`ystP7R z5}ZbIuWLb1(X{*9X_Djx9}yhkN~001kEwA*4i9)92Ecnku-jLJCZWT+K$=u;y7GJH z(cji**(#4)yM1@^H1YILp{RPBV|_86)aolEp*P%(Mm#X=5$jSZbNfB>v9l8eF2G_} zA99kB5&-H^vcJPN*pp9iPWZdoV8gsLrkTV2u{Evj=apu>ni0BS>JPdkn$+&~TL&xO zuVT(Ze|`N4`Zp3aQ2n#;3IQv(*NAI^nqxereB!OCP^8f$9qQUKT?9!PiII=Go0#O2 zKO{6f8i^3NFn5d!oJ`F#W^jYiWBP30mey9C{cHbUcJayYT)HU4Lxb<Pa>SPYm_njG z-#h{|%%C!dMB&NJdgduO`I1&hqn<3J24b>-ovL<TITsy*eV!xxJyP9LXHFLrHM243 z8R)#APw17X(FF;{B?EoLByWk#+Z~fd!j<DjCP0L7kaPh1W=WKRq_o9|!*<ME&iNun zJDzIQOsZ&ZP<Ka*xb8R#G|xz|@=Xz<EgcMerY1O~z7vkIexgB$BD2}@r(4GEG&?c) zxTRqeXSIf!9p!Uuf7hVQSHKyXMKi>fYjSi1hAC_k>G9l;2%yjhX=#x476u>>8}>$@ z_y^Oz{NlluNRrFC8OJ-VCTLZQ5=)!FMgBWtKg{;L5kC^)Qr6LQX-Q&lgNMEHSAcHR z4{5Q5`9JoAp%AvU%UyypiXq+KR*jlEVRWj!y2}Ok<Bl7BPe%UKtkDV6zc0A4h~Vu* zZ%cFkr?tOt5AZ_;_@BRUJ}|_9TJ-v%LyIyqwxRG;N|G%)=dKTuo7om><pYCU&cYdl z8^9S*a#i-l)UNOi>nl0@p6YNpmh?pt;G3i8-A2x7HBCOY1?gQe<z*Fmh<~Jp7oQ_{ z(DUdHdf##ROFk*X4G_N3|IHvrgRmP5)ej{^x8IMVB(1E&tw+MaKoTp$8=O%jMl7Q? zUzye0@$^6izFWZ`jlx;)&^#i-3f0k;1Z!|`O6~K{)}F(oRXyE&CtIa`VKPS{=(asP zZ#Q9*X<>5tTX#+d@z`$wG_)F&t!HS43r05qWf3L$sDjA3_<WgpH|I3#1hs(c>4M62 zDyyJ!S$eUEFbW3<A}r!m>K16WUo++zfI$SZI=eriEgQhENt@%i#RI+GJ^VSUzhr+^ zmdHF@j+e*h3S~){7M=#OUGeB8{Le5=|BBZ1-zqNL`SN8oNr|bp!EgGyk&-k2c2>b* z4QBVf-t+9%wPsw-kdMi}_<a8W0SOLEnLgj_bh6yqQiB6C0{05|hD<qf+3OCYN~NU* z1P5&2HwW3j8D6y9m3lhY?<;7%8RV~xwKiG8`>!7uGHiVE5rzQG79ZITTSggS!R(^0 z;VY+|vnYL0RnxG1$%5^YPAf47sJZnsi(+EQ(KNkh33~Vn=3XQ@(X#g5-Mg&ke0G?+ z6%#X&wKqhBMad_y3KCOge1TcJGuWfh(#q9x=8Hp0cBaNaFb*a7i0W<7{tCz?41Oe^ zs*VBYwO4MuBiece&|z@%aUc;mVu~?2D9+K42xFUDn<(6Q?|%Ftw2k@;#tfJ6{=s-P zUZp`<S`n`W=Z7l3p~#;7+|8$Z>B7oqFRVDo4poH^CJEzG!3Tu5vDE|u`<($_`Ay<B zq#CLce(`vDImJFpA%EZxe0o9|@G$^SfDW;c#pgBPm%crBl4Sw?@*S(|!8^Ld*k}Dh zaPBik2q7aHP9Qc@xK20M`S(gJ0_k`P4vvp$Xo$!J=$Q!@@V9+JxiaHu6qd6T;b?m6 zbkwy3kg9Y3x|nwM1f}bM7G#t(u5lSZ4|HwJ4;j+dBp%SJq~vj+Mc8nvB}GN-HdC4c z#2f<>G~y=~NS;Ig<O_O7`v?LizCthVep5#p+xPtg;@wt~Ttd7`M6k;ZaXNEVdG2UG z9wZfK78+>Kh_`iwzF7^#|3oOT7t!^ERIM0Ogp=3I5}TvJ)@EbEp+`(Z0aSnjq_!r> zL+;1|z+MvC4b0FXm3WvEL~j9s@eyiRG6k~pjBV(aX-4`CNE&T|LXOhXZT5HFxFSC> z<QQ&9ylL`(ks4?I(*MlG+=>20_%a7m^;**@AjxQDnD(<#a~QrWBF$RD#{CsJb&AFN zjv%-az%-n=i3d4Zblr!dkBVrH)-yNiAfs1+b|w>oO(&%;pCk#1QU?9U<iG;l@OAAO za;hI+@b3HU>D6*e{WW8VepxR-P#cnxNR7k=yWz{1wLo%p#;0!%a3FsS`3i%@49PwV z2^yS&0jjF41Vf7{O_%}~v~JYBle7Qt!T%{BNZW{UskiT8Pk4G!rv#J=h?O5Z2wqn! zgN?eWp#o3+gdZg#5}j~*2Svp+nD(3SWokZ&WFnF(D@(F))A8V#V;M*Eh4Ykg1sfIx zAINIpTRoA$=QjB(_z!55I%nc-VUyw|(IcqBGnX>eqwpg9&?xNot52?>NvVag>ht8G z3eI7ppY1DMDGsxiZAKs=$x-k+)&!~TbGJpqH5t=kC|e_!ZFvPG_{WmY3>@8TiAwA@ zEbw+$)80#<kJ3}h<JFd4!VvW8XHwLC+)?F1_GRlU9h)cd%LT=hW<ZnZA4tlX6!Wrr z+FvIdh2n&x3Xhv^*BBo#CHhzJOFgTKEaMHcFxJ}O7Lv;0w6qOtWGm;54=^!Q-1&Hx z=gvwSCRy87A@(<<S#Aczr}G*syDO&H?Wa@RxAw4jkJAvmRS_67<e2_$s~{863c=hc zTtvW{f`@Pve^uHWT);_*THaD{1%(G)C8?<-CdR=z;)-fsS289PwKT0WDhCNC6A~uU zgNANlbXb`7zE<4u;}694rgVrJ64ZN`sQz{wdJOC-D7F`y0rV2IK5EV*y^$20{<WYQ zSr0@B2$iq^sqPkTSO~0NEht`$O>PF(=UodM-u1nYz~Gw+q?0V%CBFZA`TyH6K`K6p zM8JIi3Yb6C%f5hwCkgod<?|esV$M150{iUZ6W8&6av45}Um|Ogw2oQ$zo-ANL4)Pp zBVL{#L}QHa>jI*w?I$OYqp6Y2?;|^7OGHFwb`mC%-$#6WjIyS-K#(~JGY9yRGNXir zHOSPFQNr2?WGZHAV)w~ZKmhSy|8~o$RF{ifVnXZO)7bAot2Dc^U<&!PCFH3Cf2HVQ z>53F=v(R~U=E_F4AZ=W%L*-9CH#Ge{ol}8>VCHPBoaLK&;K%!Mt0?^sa6B-Ib_(eV zu7|}HITK5_V=oQAgekG}XY~$e4$|8M10Yq4_a-|1Nf+PV_ThL+_2GDU;gMWZOv&z_ zKq(NxWnVzwe7^Aec*CUmAPfZ;<}O81L+BSmiWi#&NB7=_b(LgHs5?%WuEmJ(^2I@F znzUxZ=?cx`g?9kc;s6y@4&au9<`QLr+LyBFe4oTD7>eu}ga1J|GLW&v3<%#V=3kSL z#EmHOB0`IfY9RlPbIangW!Qp=po&XxA}gNs=d+wDZfS`|3D#3eu49o%{;2B5;g9fP zS4l$&1^uJld({{tT*Wf&-uefum>k<8_LH(-h@D0(cBFGAwN7x!PJVG^_|Tmp(0Wqw zvaS;~jlvAq&euuHZ_$x{IoHi+;xZJE`{ZO%JBI$qa`+K1IA67l6>6up+w0t9R+Nm! zIKC*->mHsIr12?%@Dn3@F%Rbs038SJT1dtJWfx?2tQ_#MVOgPwEd0k_ld|s2Mubeb ziFANTqc|6P!7}+Uf{bCojBH!DVWhfDAOn*r6af))SN7>-+~WJW5RxGw{2t{)3=nsu z5Ao^l?uSA1x_F_T$0u^E{>UdcQHOld=wek7oDI*%HLdb#_E%&Pbmb^IJ^Xce;Fn7F zlv>(uPJ+=2IML_<8z0^`1xMRoS5O90mQIZ#cdh)bcY6t!JZ6@1Z~BAFcW%%X`dAI; zBoII`k`1hn&vJ;}3=0@&F!ckATGWw6It5}snupRLu2q!WU$(>%qmh={g4t{%p982V zgs9!uGN!pC(+txEx<nY6b=GD4tcO_--iv5uMr4NfWZDU6m+UmC{tEF6NVS^RrGu7H z=UX9$+-yamm|2Q}g<pIwM6SPAzhICi!*Sg0-Z@RCb?U;QO<4|lFLJYAj;M#=*c7=V z|BethQ>7@0+~_y}QmU;!6EX9Yk6Lj$eR(O-qpRI8WX@7EcXu&rOpa6EWG&>HwG1}m zoMDx1yAVOwLjNJ->lQt_D?`&qEnNU-qe`o_ohR<+Lf#q|$?NcsB%5T8OIS*Ze$iC# zX3O8N=jbAS50;VoZU~K{H{W5@4&An8ev$FZU1M7>%f;J!VcFNszXbKGDik7v`Qt>6 zdulVLd0CDx0RBh9>wkvhzY+R3j&rlH{u|<R{Tt$|y4#yFYAP68nwo$ZRh*4Mzt2C~ z7y(TgH7q{;CJEduOpH>d7C>_l2{RKH6QhU)$Vt)EQPj@H-p<z47DU4JH}&BDO+66* z6Y{|*YG-ZdsA6wqV#+9H>SAGHsw^pj_)ns8oC)WJ<-9ob4htH4)JTxOo$AniwX`}* zkMH_)rhZv#Tz{$_7Yo}z4A0{%2qQs=Bsf8$1R>W|<P9~Nh=|9T&DsKxC4IqyH+|)p zVdU&_obv4SyKk2Ju3-Jf(`h2G<jgflyipVI&reIpyj-;%!)g~D05Dl<0sB{-P-yp2 z(L5)vT{$iQu&?|1iL)HxuR1_6wmxTPSF77nKL8*E?4cf6hX1S1ZyK>WU4Kot<HQ62 z$k{T<$(()FX8)@eu+G;1$74em3$puVqRxAvs=!V1AP??py_~7?|9zjlPKT|Bx6@R^ zhdi5`+gsn81z>P??-B$QEPS;M;=>1oH&#Rd09WT^(uCtB-3yW$Wj@Z|e=a8dqkAPb zBQlJgSI6}e5BK*lupw6`OU(vfeg1rkmG%3@qMY#IO940lKpq$CLdz&?r?*uikKjK( zCVW5T`RNG*6Ehgs`{4>bv;JHKG~P?$PTH{NjS2u{;Ovh8b;jzK`IcT9%MwbU|9V3A zLEs<2byU0fA;WlWn&o}7&=>j!iLtJ(uAhOZcj*f&FhY(y2-jHBTu@L@M+MdHfEWNc z*SgxSuRLBT%Cu=}4WI`1@6XR-b~wekON<%1GQZ35=RTv}&o{i(U|@IdOjQH<1gR$N zUdr5m@nYN*C9A6H(BVux0&8pTtJ+U7=t1i0;COPHD(dPtU~nK-yPhsncc8(Bb#eva z_DXLwo?}LH3GI=ZjLDkGg*3DNdjA=kwInjz=3>Dt%f@*;&xyfA`U}Qi9m&bW7xd|f zgz^e)XlMveq(BhVBicgLzx_VnwafUVT5cxCca}ZiVWz}*d$Q!Z`~6F=!iJ5ZVc1Wg zsOqFKcLS3$T__H0SmPwmi`EZSnqF7j<`|k);woTWKfooQy=m!ebb~FnP+F3+2Ct8y z>Uo^t;9G2YcC9?$Sjjii!@#mYDapA^59SExdi8`Rt6X2D3LQ3=*(Kp4jMmQ`hl(z# zy1>)q=HL~sXV1aqk38WEeFrDjd|m8qY~$abxW06blb4ujxhOj86BDssXt7P?IpMsP z(l9VE7$ZXbYmj~}X3H%O45;VSF>m>Kj5ftKfP_tLFbZY6ypPeoS4a3hml_B%y{irU zr3-m6B$Ym+X>O~6Yv9)dl$4ZuC%`l8^ZamqFfFM`-Dd9V>kEdl3Y{}5GBUcSZ5Ygt zJYOI1k{-*%=cP*ase6!+%Qe*nQX^E(Rr0MecnuPGzS1p~kbXINL%T#CW#e58EG}eU zq%3tnerBdGE=sAmX{QP_&rB#{0PSaAGe$VQXoX?Ct+FdxO6qu)j&}Wa#YW_I<Za|N z@tIq)*nZQV2Z5`t84Gu~|A{NOJ~5{y7G#?p6ISG#G77BSZEa{!1&wbCs=>g(+{?aA zMEYx@ThgZ}YND@f%f=n|Cv$7J1`!11s$3bfrdo&O@!hf4ZYRL_rEF}Rcb=z^E#U7@ zniq-lXboQ-%-rj-QCTxGF`+OsWxRztrNJvUe|LDGs9&AWD4zIXZGSkbG$xOJ%i1~Z zAs0*X2g5MC3rON+Vcd++MiEZwU2ElwmR%I<ORH&xO92OEHB%Wr{=kC{3I+I8O^=pS z`6b($9rlg!dm!B97Tvg9z%H<={vPQ5t6o<il6^v4TpT>3FPS{fhpO`O@*GYHBanX$ zX?ZLRolF+hp6dtPLbKgk$y9!DHmubm!kZ&qIj=dvNa8Fos`uLxnwpwIfs@_nHJrDB zhn5FiZFMTHx&DnzgO87oNP&+`n_ayMaKJ(Xy9%p9G0(;&A%oKtH4TDv38&ur4~fV? z)h2l?lab=HY?Rx^HMzYgqGnF!t!!t82+WrS4%JJ08~N3qZJsucvYxkB6Y|9Jmy<D0 z_H4Z^7pq<rW{S8|t_-hqj6O}yt7uEM@L#oMq@{cR8U!Gg)vz0o2t^cgB?k!w<$L!_ za-(?D*%Rv3I<7|Z$8xbkc1cM|*LSdI_5dnjo*Ir!{s840#OlZEBT7WeTHJ=OU%yi2 zMJq@bt{z+GH>FrAnQ9MK3|KE9FgV*mRhpwZVW@LWrrazX76MBaKyX|p8jTafxh9+k z*^P`5?yq!&rHv}-iJV!a$s(>#{6d5e&drT}Kl?Y1J*ke8l6Zfv83uvVevBb!WI*?w zk@Ik+4NNpPHePJ*_4bNvtWnqj5&s^_E#TGqID24s!nhozwsvqllQ$T5Lg2CDXBZhX zvy#{Q+>#udXHGF{`VN=%Z1#@yyhXM0wHk8rYeHSBn*``DMH@d(zvk}Cm0yPO26D+G z=np{=9b34vu@YD6olm6U4m9|>sD>`@Zlf^9XbYwv^xK@4y4gAuhlHxgiwqLDJ_1!> zHtJT?-sxT@=C~(1>%UqbJ<;I^;^N}&?d|mmLjBcKV%R&N$?FrCl846<^LgE!`$0ej z;c97V^;)Gn;jBJ@S4Db%GZ+ba-&+Fx+wq<;S=2t2ZSdH@%H(g<;mJ$JS<(muzfr*v z9F5J*mtpT~S`l0#Lv`JTQ+ruZ5-zj#Xd8x0x6R4ni4v7r1NXN`$|3*DsdI(rM2SS} zK;|LwxR@34{8N4Yn>=;MwrqYlbHVPq#0Q}JC5p~3CtF*FC)U6EI%(wR%OR!NFtnKn z9h?pBqcIuk#`W*zkPN0um$$dE#zE}HuPC)b+TAU$A*D2`ktsC^2TZN_i6}EEx+&@d z#aQDs8?<ZY^X|PZ{d2;R8*`wOCF=cTh9x*VmFIeSJEPRYY<7yD1->qt)~h$$&I~bb z?!?WpbCO$GN;a;FTGkcQ#6<G9W*nJ;Q}EIEQv`V{zm|kma56OsD5u?@>nrbCJ32ZF z3JP*^)@Mpp&L{rryHF^^%L0j!64`HJ3hpgtJI~p2tBTinPR&Q_E>h`TFca`SgImRm z*2NzO?RK`(m&4;YXHYR2OWiq49ba?HY(!!uf&I-VnMEb+x{Bu7^hdjf+SmHsDuxH( ztoYOyf&t4;NGtIs8)^M!F1=>|mP0-iCMtB>H?B0i8Pqzf9Iw{B{4#xPunXS9-{k^M zTR{@9bR53woNL45;~~C(vq(J1=M#enk*43hA8$_PtFz6s2CBx57cRkI#>B+5sm!&x ziqCarKn0cYOLG^_ifBF`3j*8J@IWiG5|k}P`16A3TYy7)3QvXd0Q2LcGGFzqNa5>R zhmS4leP<jWs?{uQZX#hY_pR1l9EvH@W6~#tFLj76=~<UmUajw35i%D9HB?o@Ubq<< z&$dSr{|Uh!6N%d^ZR^YFRP@R^%^%jD9XWT}ccrD7X9<&8uEodo;-<xH(x3YJ)X0eV z<;HS-=f?XQ=I2h?H`b*jM)t?k90Pg6+Pp(YUlx-5IC8U-M;f`^ueS+xY3j!ejui$1 zPgPyGSRofJUXN!aC-t7QuLV;w#|4+(3TW!-*;u{ks;VZXr>7?;!@MH@HLoB%z6z&n z$MaHa>=!L-2>LR!+8M11UmQ1e5ifd|RkV|a8jWlL?=Yz&z9=Nd#<85tR^>yc+GxMk z%U?nB1bX<$h_=^C&WZMlik6i3va_`Wl=<e&mG#oBVN)j9#BWz}S{8EFHK&XRdM+V$ z^g6&>VQZd?xZ>>h@U!SM`~mvIHePn8$i+1`)Gp*np=UTq`R$6fQPqdV@8ozy4fT(E z7Z;A{z5))L(ElEhT=uiYVQk91a0rDXs|UI!o7kIrjGybzwWkFML5=1oTNNvH8X64R zw^QDHS#5hYCOYMTW|456EoG!;?<UN?r4xwHB5y8lp|ju2Dh@5ihRmEQZ`SxqjShl$ zwu=dEb2juT0z<EfhEQLQ4skUTw)D?jN7-`UV_E!s0w^eY_K`lzZ)e-Qd8c}}mynPE zPNAeyEZ_4F!h~=K3`M|<H&3?N88iM>|I=RdG<!hW!lCnAyZEkkjLW<fq632An?;}< zq5j(VxVQPk-nVbkt-j;mzX$#M<xGM3n=P^N(83yT+630lEEMGoWXl^MV1jVOowfZV z9oyEIG`=<0JH7kIY6C*OEPU!UwnM31s{e_)cylgXiyJB@aMbJ#3vi2`yTR|;arb7g zzJYkb|7$JmTXzelD}2UNVp&2v%Cq6m9$+5V15?_4qV9hiS0>8c9tSxc2_lg2WX2v` z%Y*UHR{L;4rw9AlV1|uLru_j(Y7HiHwXE=xxb+zJx2=C~_}vje&}prTgty!V_}(1W z$*PyuiV8Xb0fF!MsBihGj={0{{%w&qV7_H->vaTv{T1uO-)HwiWAyQ7dJ`r4Qc7U8 z>5}aw3ILFq>T*3XFfh;?Gn(>Xv#>m|k<fBFdVfiIy4*Sq`Hx3YW?fCBjW$-_BMGkI zxBdik=Y@oC$dBbNgRS{FUcus)`?;U*YF(?r$Bk#WgzO2v8!_jBmEQLqKO3J-@84I9 zaNqZDij%EpdnazLY_I~WM$TRSmQI!f=AY|#9XGzh3O-yTHzxh2OMcV16L))1BNKv` zR}TnV5@9b|Zd1hyZC>be;03i1_6=dpW=);OB>LH<ksn)<>Q==z^#u6tM{P{w=+q0> zh1?;smu>mk9dO6gdDr9aqV@`Nl23gUClHxGf#lDrTL%psl`Vk9LIbe4weRQFD`<Dv zY;`p1ZTs=vUElZbSCkY{#H1Z~cb(4e`~I1!y1L6}&*yiaV;$u`-%ijlTkCzeETkt; z6A;ohwbT9JUQCbq0oQ7Yrox<<+LnDXj!$UFX30W)R>)xakoTn(TVZ#*@^T(?^6<LL zE%;xnrz`RwA}hqNAm7zVyLpP6iM5G_&JvoA_O^4|jo@>2P3n&E5jSH8^GIJ?Gf>{) zd=L*o&a$ERySG*OClvw;uK8>^a)fG2$LbjrI^KTc>)Fn>X3>rRi+1FX!J^TQ0B7-= zV?n3XyUnF9v)ry4*=;(SWF6S*h}BNYS(+U+1A>GDpn?TtxEhBh?CXd#m+Gl972A~} z&l==0Vw>~~#pyb=uGU$~6SHD4e*&p(mC2}2`sdL6&NiK=kJ2NX8Nn<#NQiGEd;Vs0 z`MLitmkid2-)Wtb70!p7Rp2WB@Oyi(xaM@R>%;ggBT}^!sz9xqzv%06nvXiyRtl%~ z+g5QB-izS~SnMA<P^^`mwa%G#wvBS-eXvt5^wo_GrH?#R<&2H;E_FxNz9PGc4jY<3 zs_N=fseOkKN=)l_PyVLc_OO47^WIuuaUN<D;kBd8Ky7hl*24A8ld)NL`VZHEPH<GB zX0Nev>^XLB&umSi&0#@8b~PMk)vt&$l+m+x{JCe@$wTqLA|oPVkaCmw<yd89m8!#A zm$6zDII1e$L4xK-U^`h!RekTqVk45P{X~l!o#{IV2LpE?E}Uzl*%ID~q-5`3ghBRy zhSAoe8ZmedV10P%C!!B{^YwAoXy&$$-HerLs9%po?(3U;=jtLW)p~9gmFw>`{AV;4 zn<&qU;-(Mzz19S+W>}X#Y6e0`ByZdFw+J_G{zT;sAw)9AjVWvzy;$mzg}fP>#z*=K zum1x)h?c4?*H(Hl1o!fP3C3_`-38sv*~(q4aO-4iVr{>DJ+^+Xf0k*bnQbo0vzrx2 zSY-SbbCe#kkmRdw>-v*Kd%<8)DY>?eKBQKGU7*7{I=*)Hlwxz-1Rr%?FW(cyuZHsf z&@{wrM$Oe|#+U+^uJYWo=f=}i%!43rg{rgSQQ7RP)_1iscXfQr6~neF9T^yp6;jUy zL7896vrk$_=ayF)HF~t>z@zL;z7)czdh2%EvcE|y@VxEddTd}oOAhtv>2ibCX~i*E zerT&1iugQ<4{{gf4t`E&>RShYg6}H(-n4?i{kHEb($7QnS3cj<esN(kA_k<r*eqhE zv3Oq>C84D=o7<{^wFN=7$rh_1TLyym#+XLIfRmprQ%9aUD_hw+R>Y|yy!{&+AJ{yd zkFF-{Z)=ygvQM-ltbmCB)5t-4GLBS^kcq)4t+b)d5dya|g3((SM%R)uL(MYZO}WyL zV@u_lWvM6fb~_fDT3p*Qq-8M!%dL4Fc{5^Ij5MYj+^lx5*R7ZB)rsMDKDeGLFYHdM zzk0EpHY*5b)=zt1PoSWnxVyVgO-)6DE%2<8=H~lVdhJ2bK}n#kG*9T<qHw2k63$Ya zdgEk==lYjv1hoLA)wRA;=;P&TJKNbbXJ>^^`4DCI4q8Hlx1Tt;(i|(cbjnVK920$Q z@oOb~SJ!{<SHC~w>wjSSsn@|F-<vz&B|6Gey|W5oBLNasJ9z?>0^@51ZH~^o=Tbo1 zl4skiy7fJxNLGH!w}n0`TXDOI4*v5A>0`#!hg5&k%4zERJ?puN_T`_x`FVNo$;eDr z+ML18kkV38n!td&ySq$Y*WK;ynfZCbV0Dm!xfZ2owUSY}8mJr;Y^-Z)WNpQWnjbn$ zO;q%(L;uU>iH+A_iRL;(k!_kuki;aq>&}i$dxifPHIMe`B%}!h<IpR}>rBUa4_tyi z+ClgalQfz!e)-|mT4AX%Ej2hJy+~C@=xAQtlgQw9qD^Jzis+$f<ND;d!~Y_kw)m9p z2ow>x^Wv^~{E_ov50g^fda=P`YcN`;$$G&yz-FllfsE7oCrJkmhCP=4N{~jmXYH@c z9X1)Clir`R%!IJ2^ON6LRp062$WpRqFVY;z=kagE!2VRoI=WcMGu1tLW9+)oAYE_M z$~EuXH)7H{BFJm0^Y<?OFKh<wm0vyp8F{r`<x1x)?&5rI9A2$IXC{VT*z_GOEx1Fi z-Awd$wY!`|goTBLhlfW->KLUJ%A_K;XK*=)NcEMHL7qWA|D_)-M*l<oxIdoS1&X&* zib-&lvrR_^k$7Uk)ezcvZW&ML5BWM&d#2s!<(m%KjL3bjaK?@PMNhV)vuFl4Tesk2 zJEqG!#$1QZFf3E4cfy#V|A=-15uth_!IPOAc&XgzjUKY7C%sga)|~h7*40bD?mR+g zx{;NgOHGoq-bec8Beg*BAr#Hr{@Zz_PqV8wuh<3FsqZ^EW%V6u_fBjUS<mXhB6d=( zfG?AwXQZzH0r!62n>F9pXV+Ety%oj~-ef&>^|=rfLhu{rXgD}Hr^sM*(60M5k}Dc2 zEiJvsMBA<NH>1{V5%kA?+;%w&`)W-|xnxNJUd!ewSeaUlPxZ7zsgfL1fTb5E7n?ja zTV2xWnPQW~#BcSM=~60)<|v{^=Zgzx)0;QTKR)TW`zP&{^4P&aefm<y<IkI!_r*?F zJ3zWig<A$OyUak*YO_Q2HZT*_`9StskP6k#>?DcEN1pf|_`JpQgtFdcAl$Ulu-roC zewy>bZF3Ok^9&pOZu4PJukWkdeCaVF64Lbav}<EHSYR^+0yWgsxcMo&J^z!D6w)ov zxQt65%<l^7aB@{)sgPxL`Z#6#Ho++Bm{ZEDa4Usex49h6vJctrf2!omX|*cGiuI=r zuDy`?F~`jzFVEil1){2;Fh2d4OChEj(8_J}GY{j+W6usNySHblt=Wps%+%gYZZA7u zl}h}|CGGHC-+qPfxaQ%l(pL*Yoku&_xBIFt?Ck7dJrs;h9$1?L)+pxY_Ke^|tU~|I zN6VA_sU^>3{7uU1r62a+YB&YDyhb;@(+jR^oBd_6==x?-4cNA;*v>7w#DhSkR!9Sd zIWM15a$Z-s<=>Jw+t~U!eVqDm&WM*w@E1nQB(nB`SwEHQ7~xn8Fi<2pU4ZfWlp(t` z@J+->`oac2_pGnzSxe0O_DhYpL#Rs6#>}e;{LyED2lGV<t=B#G@$0oe=^OahZ{p9L z`qZm&M6jHD<++}|=F7Bf)7h!DYFlY`7VmTYF_VN*bakfOQ20aZ^=o@U_ShZp3j&Bs zsJvZ@&`#LGZtp?xC_CfwWnsNz#!8o0WrcStJbeMI9eiymda6(NfhoOYy=PCSeqF9M z`1;1?IeX2y>h*649pHuY2loQn8@+zmYubo>(ZcyoQlVml!v_|qhNi-dZWc#G8X~$k zHn;Y4E17MxAAmbyO*e*<=@>(tX~l=x$&U>ivW<*giTt9=yV;ppw0+>`<i1QpQ@(uf zyMNfLVM=BFyE#9Fzlb{bQTB?dFDSNr7PF@d-RAKg_$7KKwtOK>RAT|3?`ACXrFDnP zpMX@>fLE!s61jmj%!PI_OSApTx2ZUKy4WfQo3P<j=F!Qi^R<5D5gcsMa$Jyb?R%N$ z$kX0Tlh)(bhuB@FIznHV0~)jZ?ZR4#7p;|7{J+-)V4uou<?3NKkJmu{5!hHOgKC|B zGrb`9H0tG9S$x*GXl)ZrJUbg3(VbRo(VSaI8{luInh|rpYLp+<l#@m=RueKGlbPmc zBPS!PaaFIrQqoo#REARh0%#Y}YG<{u$|JxYXe&?pf+qm0@GKtQdTE);Ivd|KzViLh zb7bAg@|_N|uf&iuOWi=QfpCNc`<IS^Am1vwHNJeX0Y+tR>FM$l5c6+4iJ#ry3#CU; zXS>r}@35nMsYh*fbJj!m`GxR8aeOCt{C`mOl>u#K&)eOtP)ZAJu>u8JC{VmO!BPqo zC|00I(BcvZ?vmo}Ry4&mxa&f3OR*q9iY0h)Cwa5G|K0t)`M@Xcz31FBXYR~1^E~IR z`htj@UE}#TiCkVSvlng3q~#YD3%w7O^+Yw+ix>E2_2h;m{7)zL6p26bTfd21y%XLd z*`O7yZ(R~r)j?htu}lloYRM>mKWz#sB}@>iG54YZ@#pSxIu%wAZmp(;&C_-GlSxL# z3$4P2h7<&qrEnJi*z&j4<$nY7LLrFl@wlpL!>7}m{&I#3OmA>-@a3haC{E8G`yYx$ z@OPnWq)81aHE1~vUW2cu4R<D3HHIF5+z+I^*{H;yk7kJ-P0RtkHcsuU{Fega7S4<P z{wE=)`Mb(?Rej6e(@EzFbNcq{V;8B14Z<s@5%YBax-EQ4`sm*vUAWB;s+qI%dRIbf z-Zu{Q+xdTUsQGUW_~hc>NaWU+(LZZ|mChb3A$&NVq9JwQ*y@s(IMtt*TC)6q|3^t{ zcSh;kg5=(6{vw`okFHgW|0F*4yVmfM+eB>?rMK|ZHbXPMF!!Z}m7SfPlarH`l@(uB zVPj+C;21_AfOtUO)zuaMZ8=!&Q&(3fp%Z)d^y$hjl;)qZ%dMYutxWFR+w`6adb4%g z)L1*G?^hw|z7oiD`46iJ1nCv11?S!RG#bp_&Si|G!7(Bqzee*>^J0`_WNUc97LCS7 zI;ME9X>M+AYKn&!@yaAGgoS5NIKlrQ0daS|U0>*)LM~SL*M@#rvK<M(Et_>2+|JU{ zhAjEAx3@Vs*d*!Es*0e5cjZO2ejUc=>5ug=`qmZLZTv_Z(>;du%ttc-H5Lfs`}e;B zoY0X}d<9DBf@Xt>VWce4w4$y*|L|MHHaz*qfNt$|em7{qDC9y6W6uzQ!6zP3Nhg}S z^WFT1YD<<=V^b$5A%ojckwy1a<Q7r;qs_zfTlo6j|E1aAaQ`8@v-_3PZBFR1!fAff z#HndP{z-+yrl#3(<Lst8%?0J{&E@TR%}DN=1N5$dMVr_>-gly)dH6CV?c?MBe6t8m zR${Z3Z~J+B5xRRPc&qtxpGlz|i%yTreb1>^YdP2myY$&dHxiP*kD|MA=x{?T(i?nK z)6r1(D$6-F3`yV9PMugUrvDRD`RPpXKc2_NeR$*49Wnz$C;K!MSJgIi35e%fAhPfp zd-@tKF4op_G&tXlI4|7WVIW=0K^-NXSYo`IhPtk*I%%A)+Yn?(Ln_6q2S`FASXNRp z*wT!4&eq2~pzIQB2Wqv$URnb6P7&k+<b5P8aMa`J57%kkCj>{lPEMtV(K|XFW{A#V zQjO$h<~HatHAiyS{G`-CSW7fogJP<<ewthhLqE&e4Tw#(BJ11b*CACvweWF4>UMVG zT??OcReln(B$i0bs64WSn5oJ*xOB!X$m^c%0J+xmO8c9N7u7OdR(>pU5{eRItTU_K ziYh8t`{xpBec;X|;QDe@oJUCx@)4mR5)`h+8!yz`QxUBoR>{o-FM4A(9Sm<dGkdOu zh+(mURDObqdA#yCn%fO=8YJ>T>+nyKXDTi>=AP)-fNFN#T|r84iwVmzc8SzhR*$nq z+rE-PYif^t`?_$VXnJ{r8cwE`+HbU^CDuivsm%gb2|E)F#_L<%J}eXS_Mf&vWafKI zHP$0plU-%JLV4`t^D`e4+JGnf?HXRn1$(oxagLv%?fE&%u0Kdwy|irQ2iOK0GNoON ze3TFCrBYF6&--UvthGL9TDM;n)-_eN3)^1#iKDcB4Y9vYS=cx+dz4>%)nKz!Cn}IT zt~OOPALArpJ#r!KAi8$<FN<#t?u*=uy2*tQS!+Y9>r3jn*hND^M*)}&jG?>H5fc9@ z_GpFo`&#bqHDNF?f<009H_VWpVt@bew6v9yt#+@pazk%2>?~g_F|k`9^z?~0v|Q1A zV{#Y6;k)~o^lPUXE<@MR`i2*0*h~EE{OBXjsN;etGUJWyWl3&J^mA5ueM%m2OVD-s z0+Th|C>LogKik5<yOsi~x;j*6|AZ=4Nz8*sWW4O2wR+aKt4*q4Kqa<aitTtvCt~`w zqra@bTYxHAEkESRBE6CU6&0`Pdqu~+vFozx<3J|9fRx_d8I5th*^gT4s+wt9dIl4p zPcTse$>VKan%pp;*})uRP^t!<C?joJI!Dyh)H;hw0Yu?ps)(J<Q0iq&Iv>v~tFwV> z<9r*p<lurd|3m%d1IbnBx!KN-;sc(rbmiv?k@xR|p4Qk}RONR~oujSlwYRL<hZK&& zb;@Pb;raX?OU*@pgb__Y9~RZztWrGYt2Kz&*@>jxmMSEeEAN?^UB$5M^>eT~x|CC= zr<Jfjh#307#zw;#HS%66eM_PA0kKU)MxC(f!Om2%)y34cl3%Rk-15m#fNus_+fDbf zBjpj#x5@%<-Rtf+(srEH&yP663%8;DvDJc}Jyhb}mWwq6QdBDJ?QYVYGnPx)O+V*Z zRxhc|GEbwi&eRmNK6PSyt(;ffUe&zc-CH?h7RQ*pr|=-Xl1tELv3xGU%((HM!s^&} zc?FEOkcb$ot)1!+Puc_G6kC#vdS|CURyJ-A1ru=V(s!^lRCjhxIS5t-m-q)b@KFqB ziM+N1JDSUH6C&4;>#ur7NTRf>jlgmFc?MO5`$R&k8|beWH+?d;qryKWR7w6e$Y{Jl za(;IOwl`+imK2oKmp7ODhAwea>e>JH#AO$`8x6eKY&%<`=eOM7k7Mk(!d~H8kH=*w z^~uO-@UBT+Q$ql){hdB}-351MC$RxT*??(RKD}<^pNswa=KU%&PgRA-?riXJhGWU0 zFuEcL#ht^RJ-k!YP<Q*>;-sl%J-q*b@i4&u^xob+f+pocMf=$^Qn%ME;tDeYm`?`2 zz93r-B_$JE{Fx0#Vf%>px%u+b`ND??B^UHcBkdS4gy2Su$L7Wlz6oHs%d~D*XDwj* z3pP{+NVyM4(bN<`3JB1v%+`u{ewgtb6V&yw)6f9PXOGBvQJyXjfGI}lgd|@3E(PD_ zv`BLjyXcO~vt>1-y30lPt*FG*Vr5vB$ecT?190{uta|(~yt(;s#h)RIUd3SIUIY`L z%l2H6e0CUTJ?OZttL`;hsnxzYQ@xyeX1?<hHt@%+N$;JWT~No8E9a>Nt^B-i-YZT- z&+Wv?Pdh3P9_TiCADtR2q^b$dsU{@2S}RNz+^}xP3)((_b+8Jsd>1jn!{n${7G>Qx zjK&w88H_CFZVC{Hua!&C&~$NC`Du5r%avfooTKql$vIrqwSW>tz0C>gb7hi_B2tzc zh2$=m12huaURtZpS2ya1JQxZ;<6f#{w(gIgoYcd{7dI`c)qDLK^vLbFvC=yq6_C}9 zR&{dxH6TEWfzOcF@wGA7A%c6d*-fVH*sBw%4QN?Nhu|afI_+;vw>GS5m`B4^B;w4k zlu)0R^bA#Xv_I*oWiz$?`QgL=L^$xx5c+huWu1-yShtYo<m4x$w!*g{9I+k+`N?R@ zF9V+ufd{|bdZ{e*oObJqsi@Ycrpz>^z)oO@p1#9!OM=e?5Uf}{RIX_Ik+wt*2+R#g zBQ&Nd_ISUd5<ojbS+}(qzIci#H<a$l<Oqyo0AO;W`e^$8%%<$E{rvpuiHvl)%bX+p zDMo5+9mHSQKX5z8C=Fe+$OhWZXwTHY)0D-|g7HN{Ueo^JuWMrXbBwPr57rBO*i*EH zb~S7c?{00EDx2Bj&;MW${_L<4oH+hmH~56<WIYvhQ5RH>&M;K11(+Xy4f12xG}Q@j zyI{FKp-|ZJs~hqsP>z~S^2wuJutF8t6%B|sxg4bRe*<N2#}iY+YR$9_=RW#gn@TGA zl>#U~rP#*M02#$BU5wlFXMWgglCNcmRNiPyg3trQ89v*@nU9YS@}P@PfDY!`KL-Q7 zBXm)dlS0T8vtKF$ibKL0hOWbxE2i!F*`x8krc%y7z7US-#?V_QSi-r*)GFCu2|Jn` zCzlNtH1}rY*%CT*+_MplHM<E2L-)?59VfM{+-6qE<gs3^CvQ1wdeKqv#%#O%=Rq6| ziQQ<4WeNMBa=2n>L}r};PC5)V+SI;bIadDdZd@t)?)z7FV~9}pmg>m^h?jpC2H%GC z@QIua7v5VC=68{M=i}kxBBP|Fp=3K=Fmls@li)m(Mh@&$?uS;iUmjjyV9<*sEeYIp zL<pVd#=H|k-2Ge*q~T&^Hs#k<lCCvna6C3V(GS#pKC4ssM*YF|4`6yC?B4qY&bbLe zz-bmz+!5t^e`MPHsna?`xYo-zZ$7qC)Yp(1hHj52d};%@xzmb%fkK+@w7wQ>a<@#k z5B5H#*xiKDP}7tQ5`_=yY$vCuQG-jvk0K6j>bl9-UFxDnc3?N=-Ftv`?v~d;77V^i z#y}P1pkWf=(h$rn^BgSW407<L3wct_$;Mhyybgp_6u)L4;KYkVDd)cic9dmzCP8SU zulWj9@rQE`jtp|68kj`%4iRdj`DWyGO!*h0f-?6ImmVuQ-8Z^?5l2JTTQuMu5y#q3 z(hV6cCuN6+5p3JwvLh>7DkItq-H!&$dd0sxY#oMw$iHxiDyS~;_X+zgm+`xa2``6? zK=W#&vUaLbU1D}!F<wifDJWk?<Iy9fy1FDP7LtmGNAy7GY4z9d9#k>{NiHr*QB&(d zUDt9a2&I!KmvyGQE2e04N)kDFlAJy-^;$ragu0&kFgT4S9WKiam~vcjIvQjPx`4yW z*hU8sBTq`rox<6MO2BE<Lu?P+Ao}&6kuj?jaHU1>R^gb6AUGqz^i(+cSWi8lcv5<y zu=+9`J2$z6&>^3#jeVQ`J9UuKLFXf<J{hiXoh%4z5t61b$w(&CD40nm>Cs74SDkQH zLNlB3TK6BR3OU5<1#6nxg+Zc@iEEViSC0<EBZf+XR1)5N@A^%Rm~L3afq{jEQ50kU z-c>`gSY`;=fc}1z2}{?~QJwzjs6}pqvk|w9y8hOL3_ubIh1!eA^q2+7tal-=#iB|! z3l4kdhDkSPsfq!BSpYybdfgN@2q}5ZG1tZ@=!|yDeW$fI=U(=@p|+qryLT=wzz*Kk zm6I&RPl(ep(CN>HYkey!`t+4&n<ejhW;9oIm7+|^z^itAPN$W_V<}iey{~Uq4#910 zZCz5@zfk*mI~*XnjZ}It*J^xIrL(M+lmEg=%Xp_~p!AFms5X!}9#b*f%H{g`$Kv<d zbx28{U72t@yMXnMzkrts(r!RL<LUDjaaTK|+e=(sNHm&yJ92gl1}7imWO2vmjlP?H z3xuk?IF8}g{p}%7yD&cJhp)+V_k<|GfA{Dheo|$6^^yV?-fY<8$RFXoY>vOO+=u4< zE+Vhvje{8zAK>Nrs$Kg{y<tZTo$p$l(<mS$6nl*UT4WBA-y_0ZIUf~orLPP^&lV@~ z8&Y)LD@rzv(5x3oLlPUq->j>5gt*taunm(hIdeq<hkP1+GRs^Xp1q766Dv}Z6y2^} zw=hCS&i#aqz;bn6`TIYLiAD^HvEQquYJ$2l5nJ-%cO}sf(P>$FoxKJahuPYSpA>&G zL8%z)$;u7tIMucVab96MNlk>x9_Uuv2Y2A)pg2OJmG5pTWFR;8ve)x9TyH}ePoU+a zZ1TFa0FxDIa3l{F8<AWF^d45z0t0+aSGUYeeoy9naR0vc8<XC&Rxz!?ljj$ht+Mgs zDFt(#iDv-c`QxN9r{DdVaC)CWwL(U&8zqhBdB>SNe0?exn<2kCws5OIv!%?Xl?^lF zb<?_N0Td0+YnGe$Y1uNaUT39_krr~#C42ptJI`4(2KYK3rENGkP4~$L29Ht{Lf+ZW zuju#OP2y5$-y+SoDy58m@KCqj#SWgYrs6I@NX5)j5oacBWW9mRxP4(9oLa0~M#bDK z%b_zFzkL34Mn?4LkbPXefkR*H7=u5rmVW={kIr0XC6I$Vs;aDHeC_0j0$z)M0}>zy zo89U!16`)k&qQ4>!^w##WI!#Z&j*2;8XS)n*&cE=WbsrGl1)#h2x;qDbI_1ia`1m1 z&A7W-ST-N8pAp~eqSA;vKFAm>I>2V@B6n1ZxlnBq_T#mFKyREGj-KF#*Hq_xEs2!{ zZZiE|NpEI6E<p6%FT)1+0_TF<UKQd6Z^w=kMfk4hcs)Fdnvcan=6t2cNoUmA_qdC; z$77w#FoJsf6$hOVRJFTcp^ifTqF-Eu_?0%_b53(%$at3$=<2Zhp-P^ep~c7><$n9} zM59Un-HRr(%}vpqE??T??S`(pbE|K-Mng&)ojUIP0%Ke-{(L9C-x(OtieDeMyHB;( z7F=$P-&~PWDA9;GPug`{T#?WKTy5;t&{^sfk8ty!>{u6|FL)FOEqZ4N*#$FSJJ+d) zRzWF<b?R|HJyDW{F;w&oJT)&6YHC_8pH1Y>2mgre?hdt@V4i7yZ&!OVSu{`%XkxY= zoh0nIyut~N<EFm_Rc)VY{L*duycOvO^u?_=0I@qlrdv4&4y=7dYSFtNv;}!T&-#Dy zIC>W-Wg~15tLs#9YHDorvsQk7cX0_Sxe?xGm5gRn0FAak3R7q4-jl;Djw&Vh&YOsm z=JYBVrhBhgnkh*sxjL?03k><^s@D@JMTUpX$5~sIRr@wi2N6G17Rkt*?Z#+S+G-hJ z7Y%Hm(Q!M<0uRk2VrQ^XVd}j-5S0ZVv0PpOHs{W?{8IJs^IZ08l!2j_y_2PMD;(!! z3(+6FY`mCYAyOA|T$|ira`LCByTqX1E6jE>(lDAIa2rB#R=K_1uktbL%`Y|nN+N!$ zikUjo<FEzv35I$<v~@sCY#Uwi@v%WfF!z<PEOD>7SGo<51<&J+m#ybNzmpt=hX-}` zkSBFo)d{^PJM(rq-dus{VvupGImr}{C|pwRSuAW?t-;7KmOMr~nJy)Q_;xC;l7tiW zR)PAmS5rW+p@NjC?Q>+YZdbR`HVYIk%zDHOYRhGCq~U#ac409he-z+)D)?tck$e%8 zAz<D+9NK8c<M4Yal4)01)3@Z^rwMg!B_R#|PvjPRvkihAHb&a+=hedI-?MT<h`?ZK zwbOEKVYfdji;q$`wCOq+tmXCg&#Cw*BME0+Dl1F6@D8BG>cak|@_27oaCmUnyi|I9 z@Llc)5!JzA;n76IpmtZ(;PA?L^Y?*+>~|SfM~v^1?X)|v_8v_T!eT;c+;fq$E5pK3 zB9f|tRyHn3-(F(I?+PXXGIESYLn~BAXzoXZq=GUPp(KPEyk_&UR6}K0Km`ZXX)?6< zNrdsVX~8eK(8vri*Y2|pWwMpB**5G)SI~(hST?%TST-83#!{O&)j3A=&iqafXH<BE zZu{qp6;KVjA{^z&QBzW0zq!$_5fR8=aQ6YGj)BY5N^d_9#3%Ls-tIiiaM{`}axgMJ zk^G36L!Y_>n1BE|ebhJe988P-dbbn#FolSUD^f>{?=yCAX2dwS_-dLX>uTYL)e(a~ zoQf-g=n3ybx+jeS0B$~UpCfcXXu_9H#C&Zsb!Zws@5Yw9Zz?l}{K_-&ow7`U&5{Go zJt$i3yS=jMca(CkK@shLF;NhG<1rV%0AO9e82?$fP1Ie`cqrhKe^N|<3?A9W4b^%W zbq*yUUp-gkE*=~~2v@N~ZmeJGbXS`lu_)_3Z!%V}Uas<?N#@EFfk@*FnTJ8oTRkz& z0kcdRA*Qr|lC4tS=yLsMEic?XKhDP|^JPAHOh#YBy6Udsqhzwx>Ed11wCr6lwEB*D zG>d!<Xm_=!zFvNsQzT-LML{p-VI{42=nx@ONY+-;emOJdl3hg<P=KK1dq~ckK}$y8 z#*@jXD4O_8;+JlRmD6|sz=tM*4_QXC1aJ*ax^9@~D!_Kz?eQ;E0Z>{#@4;H8(i9tc zQFq?lW*byE;p*-8im7x>*7C!rv;;Be$>+eYkEvNirH@xOyI$r9=Fyj0KPG;8gy^~= zEhZe&3gILU57njP9CkCck=uyZ?>i-HoUxMG!HK>6e7<J2><~AGTzYm;inLMS9DGWw z<HaDrV;yDxW53a?I$&=UQC>Vl2b7-y57zdd_kSgKcp^E3iKYT@nyVV?v`;NiQs&t% zQBjaRskb>8Z*2Vfwec=d?ur(d5}+F3U^N*@_`QRQ_vH&`YzZy+6ho%@T%!7=<D!sM z0m6W+*5;;UYM?lXg?HSo$W<j=L^De(GpU`^XrSUZLW1gXcp+pL?qCfa4^HiPZ>NCD zG}P2`dS$g-Jv9bCBg>MzPpnIsR0+>%ul?MYb#h?RSFzwz78?;k!y!OGY@;o{I$dOI z<#ACy@+}GPo|G=fY{3D2ob&dtMN4yv$}Oi$?#7L&rk`r*48jeGD5f-i=?DnCuz}3a zwW7P4SGpoOMZXsW-;o(Me5L5I6Mi1_^0$fir}UJN6U0>13Cl!+F*2Ali+j}D)YRsO zf4=CrE84533Xd1#f0noL-EeN+9n0l}O0q|6GIu#Sdd${ogzWGqWExgkYiz9as28X} zu|brh_(R?Bof4xD@4x1%sJz4+hMzSE>WQA6Q>k3fNZ!=+6nrBG`uqS!Snh2M>J7M5 znaA7iBbaUB4B}qXrN;<-vU|UtndTla^8_)P6-|ZX$O>9)`l|Y)_lmm3GXy)k-$;CK zCYZ2>vt7^?`(~W3mlo^s|Dk^lGKXua5e*o6uEYzB|7G~x4kO|66BF4{Z4Xma7#rwL z70&5L8CL3=xm(5-!BNZ(7OOXQk^50;^kiF^48uQg?IfurvzsmM5P>01t98HWwA};% z`eM*Fpl1!9yS3fJt%tV<4kVp?FKyK(vq$<$oSzEDY`_96e5P<Iol+qW!Nqmaieial zdb%igOT^$^Cn!~eyZWdf-rp(74=l=z{bmyKF!hNM21Y7GHkmB+`Vy!>n=OOWb1m7K zyv%334)|TG+tl7`4IivcPDS)ak`U{r$LeZnLY<dNV!!;l@g<zEb%grmw|6;uuQvxt zO5IRY05reuuD~|5%oFo^5$SZ4b!dBtf_Pqd!Te!so>^`%!AL|Dg_rXu7>9ykjr)Ay z&mJ&x9hrp8-!rUv@w4Tn6vkG&ihD`T&}u+0=^6E!km=Y~<aL5lS%j>L35rAFh^u1? zh?!18KA&x1cHaA`8X;s#=p{6joWdN^GeRYFj<H%czd7n^x_!;ey^xZ~rGM5t*ITmk z4tzU0U{h9;i;jnhU;3FIB4GUnwk!HBWnF{9Mq9#s?HVwqx|#fLJJnpvwCoY=4bN-m zsX6tN9+zT*Y0iuV=#L*w@>K&D$-&kN=(N0^PN{oA<sU|d91nCp(Q>O$LK+***h#Xg zwQJLHg6kUOwvlu~*4UkOPH_=yN4A)Xhzwy?%jH1<<iiPKCa$!b-9HR5uX=YzYWOF$ zmCF_$Q;50$^gqvSVo964fdvWZYAHVBaa!pD>4vL3I6@_A>9?|aUKd^bHk6zXI=pzS zkxCesz<if8)X=FUyGRoaQ#dM(5bBGBQH$|aue17v2<Ed4KMGxHSa}-;o>0|RZ|C$~ z=_g#m@!J>SDz011)@BHa1kIUYgB7f^PemQ9D|g2NLxe0|4QJBAp1Zw(7Z~ea=c$qg zBe0wzoZ=mWYVkTvLe9OR9yJuUA0U>GB_czfrVL*|CUcTn1PdN?Y(`^jNDLdyd%jMA z`W}$Xo<Sj%+M@45My^f^S(ioOoC1LYQL-czhI7qVcz|X1335Tp%<O)PogU4h)JAV& zM#4BCG0zt8Si;m{rSqhCwk}^cSBg}tTqNF5E1}tZ87<)8(8s2-8?n$R==u3PE>YdM z$|*NLpFyN3pJ7fWZHvZ9=+_559@n{ow!R2<4uMB?fUD#?6?#wG#Bv22N(L5zLKK>X zbhBhU7JvMZ0js&8b<$|I2Z^~1DfzL5*i{P1sPIRIYqq6&<H6%^#YPGwYtILV2LROq zd=97c=i*}nOk9}1c_L!reUXp~t-?it0`sll=9Tc0@ekXM446rMx21&^w_h#4nlJ_F z5RrtJIV><ww%wV7`0&A%@Il(b6719Id5d9Yl|c){rG@_8T_P;VDRN|Iz+q-``ioks zw`&BH%cbBWQqaKV;+n&i7H}Qur4(C+tI12dsii0+RUb~`VZN!!mYZHMHIMv$zPk&P zKfNR65TzrDs^z<`32_L4E;bHBySo1P+9(Cs1aW5iMX=LYQ=8)Bn39~&7-aqvzH2G1 zLJX`ZL6;m4<lcRhMP0u+gY|FjMQ@>-eMED=qpx{|_C88_CJh61S8Y(OroDLRh=$+2 zXz2|UU)Z=Lxmd=8z5Jd_yq3755KTft$Llf>z4M)^Jc8zbk>P5Ci71T`CRBY{WTu4K zdiijC&OHSubtRLjMcT3Knvmg8eA<ek=LS#%aSa|3DG-z{xOnB>w17;i*LT^T-fj*R zIC}}8*-k_H$F~8a^q61VWW<`_VpNAHm+|P&FO4@%R$Sqy_>hUw;pjcrgP291N#n6{ z$_fdCG<>|^y_h3cEGw(-qjV6~_QYhxI46Y`&R(Xx(80`W`SaECgFW!T{vTQAp|b(z zJ$s@_I%XR%C-4U%R~ti8QJ0l)+P?56R$E&Wm&3hAncsja5xm<l#sJ^6XH85;Z>yXa zBGiXY0||6!>>tveZpYGhT-b(F;WD5(Vm|Bsaemp$>1UHVZ0Cw#g_<)?DoV;Wn}M-Q z|E<Y@?c`ycgZE7EvFUay60}9kT%p73^)qs&ZB|y_Cgr0`tC)+-{!C9q%AVqrMXTsy zfU1MddY7sn5v85Y=GfRLL#^Z*yUjpyRRu=%t)tR$yg$jreQ)fMxAGzie7GI-@C<J7 zbbs~u>jH~9o50OcJvnJX@Mu&7!uoZYZT+OF2Av_5h=_e>4pM3|1-2r^5vFL>UmAab zxh^YNb;vdeepCZm$(9Pf;XS|l;u0sS+$2bAd~;NLS8%{)+gU$OBdN)FOuI*tz=yt4 z(D(|Q7EXJRP{4gZG+IJ4-EhIwYPghj{+Ynb7yOnkYDPW|%X{MN=;%v)?<(->QPt_v zGxV>siEj>0zQjOxem7V$)Ib7v#q&hoYCuK_IlzHx6Edi~nwdo|sO+j=VR~BwdeSWr z+U)|4BLyY5munaV1MP;(Dk=t+n%`JWRa<S>oK@(?)>?0FXaJ}<*H^lnQEq{*QRv{g zYM(e7ElyfWeDKv#Ffcy($uPA6!0&6d@ngNXxJknm3uwr${ETRS<UsnKYsp(!sAEw_ zVnN$!|LwcAVeD!$zF-pz(@$yR_4dbA{_?%HD%u}AJj1#4zv=M1Z4TF|WkOBq{RO*! zu{g+>^trwg^_{tx-zm6ZDa9AJWbS5q@BbK{b-IL}-J}>oIj?^WqHyPZlm^}hf5b83 z6S1Ck@>wQwLtCpxHxH#4%3v2goDC18)2LTG9IehjoHkQ0QY)2rh&XKPo*uolNKlKL z2jMtIgJ66u!bQ+zea+p<JUmTD*1le&dS#qu=^g|6#z}Mv*s=msIQd1vNB`R6PJ|CB z$wj+wbqL92C(tYTbO*<AglI}4Z%P*olvSpycQ#QD^C|o|29yoH=4E#^^tBH1j2Z?y zWkfyk%Y{CptaO*x&X6A8I|)%q)}mL8j(K=MdOB`By~BTb1EVSB2uc@%>j7NQ!BS1@ z<eUL9hoAA>CO#}cDEHicXMTwyQ0A8i2i4E!!|PmCMlE<~xR{=nwvY1?n{Ev;5oNE= z^c|8cF1Ul=W$R%X=U75Puq?BjqqdCM`^~sU4=fP{_tI>dk<9Yg##pH)M})AR*2kn~ z=*aj_$qD1rwY*x>ey}ga^s_6>*7!VJce*S?jC1p?GAk^~<?Qy#9zGIKD}B3|nW;8P z`>;eMYrak5<!fQ*i^Cp=q1<GyhtDJ=Ud;zWN5u_X`61ZQyAjDYz*kg1F9%m9XB<jb zlLP5X5EUQ98zG>574;mq%-UVwH<InWNnq8FF4ns9wN%SSngG2V56%)^_VE>eS+0js zGt8#1w+1dt#%mi7z{ZSS#8ViJ0@@FHbjPb}8?>Nn`?ug0^I2*oT&qt{U@9Dpzj8t| zFjD6kb^FOT=g{D->RNJAWOp#P#7wL%D}Jd`lQwx?=CY_fCw&9tD$lP{zAkCBwIWby z7N*6oK&kR4vu>_ujL)5uZzR=8OwB5xSxl(XANA(?5FgdOX#J{}j2*NBe8M(yyOeS{ za8&RdP?o@l8*Ww7K=x~fmXi07246tcifAdluF2<UyWEclWD^oerC2~Rs2a_e!UN1k zqUr=T*&CR9BEx2?1cg7_DmriY4Q4zzFe+A}P*Coz4`h<Mjobysp{-RSwu0w|Zx5LV zD$|L&Tc3B`2a_hud@W*fdapz+)P!rSOXqtqM1}>pVHWd}O#0vpNu4)u%T8vfWQF=_ zkMRouN~dbDyq+Y?HNQ7!?%Oli2$wy}w9lWF_$vX}{~g~Zq7S2<bbB{adEPu9AD(j< zj{mSeJsrO2Ve*ja!7{#&q!N<g6P2BL#Svt-US*}>#%YVaNm-^#Mr55J;D?~v?z9Mp z*Q-8C_r}B+QG;r!o!|hdV8FFDI$-<xSjD9D%W?+!sdX?MT5rU2jM%!g$oy)qu0~`L z@?ee?S2mhAas#7%FPQprK*wU{G4qJ`w#~_#i;yvdgaY4hel!QMP*?mm9tAc`0z*`& zsGHe1f$HRaPS_?qQmeA_h`xaVBBS_T-@(@F(n7&S2{gCZW0J!8fM_udW}t0o+Y+jD zqVz~(s!qveJ?#Vm@?z}m>+5-MF-bnvxB{a^0x2~qerfage(3g}+ExaA2%LEYST96! zQ;7?Fng9xE>K+Q&g6II|8{>~s?=~r!P057Bqld#m=npqXdFL}5MaP$2Tc^i}<h15N zlPd;hE|N!?9RTjSZ_2)$X*6u5U>fky$rg;IuaCnp%fRsCZZ#AMhh|mtdd^nY247pt z+#Hqs;5m|_V79HWc@4I4b$DR9afL}MD;d^^=p7|7sPxq}lPX@2B%(dX_%C>AN-IBm z!_9Re?Fql83^h%EbnT>Ya}<AoT;QA7amBP#r6Yr|&uylKa+wR6MPEAle%h}EY$r#@ z%=miiMw3~1%{N*Zbut!6%a(s&t0tRLaG;K%TWl1x|2%_ER0nV=8=3g(5A<#nulC`D z-HSSKmB|=<<IpeMHg|yRBdmk+F}5ty6W@=j6{2$gL0Sg{Y$g>Z$}RM_J@M0>Hn$l( zYV>kG+1GH9bz+xBaB%e1I2o^K?TOoeoE+_PtS%BmTTU@9yR?Pa0*;DdBDK)^#@8?f zrAc7I(2daARdYTT@bR6*dv2*CEQkwe`(RQ}vZ6O*Q%`f(GEW^>W<SjgZ!GYxx8<Fw zdert|CqPuL>=7gR*9+|d#Mn3kOld^7c<{6Cr#)))Y=k===imFwe2$^SX#)1$lQZ9S z`H~#)4Wj8_&fP_v$3hN|U)-4P84{@>SXT;#SeLMtFVeL0nqGfXop>jRdCn1A{|Qz$ zfJ)6Ua1c|e!8vuUI2<u1+buuD6Of~?@FdL?x;bHsPir|v`La!`4hL~7nJ*JUqSA9V zVcYDSR0o7Z48e+eEvu&TRxX+zy(Kax1$Tn#n{ZCX=Yik$^YL*FQj7nuN0+mgE;g8s zbP)ncU}UvCU}#otK64=#w6Fd6Fj8*>iwKJ&4d_a-nb+4fTwKFj(jKl=!cpy`cAkCc zz2(QJH!z`|NP2OT@f-juqNa{$0~Op3h5VV5JQr0Jw%pj+m0?lX-aX~rM|eDvnUW=8 z;v(Jvn&L64u+76$3TC`5;Vg{KIwz8MKFB5f8uj6GW$ukmtM;@r2QNhy95#n1DiIZo z;(KT|xK}A5;_V&M;Wez@Xg474a%AmG56zjN_Ml7>YW_1Tsz%6as(Y-|)r>5$Q8*}n zbLxun?(hSW`zZT2EG&GouS8i`%v8GKL!SgtR;bKoZQI~5aQ1@8bby2@8kwWGOYQTQ zN!fe;G^+6GUGi-_hQ|{0X|$2gH#)1hK;)ZVXY}NMt5wvlH`DZOYsTXI)4Z;10oznS z#L%C~fY!QGaW*uW#Igp;oU#p@VsF|<HP7^JY-+ClJS8|x=&&CIg5TFPwqQZ7cF*$j z+WohF^So-_fQf(EEM@Jhm`wF|P4};tI|NlxUe`42$3nSmN-T@mM(5kzPOks>(nIu4 z2Mh7~2WeHj!u%hCx-A&24CD1#)?-!nI$gS-d395vjtN2$*O_noWu~qt)m=0VunUdQ z2$>nIJqOdrZjc|m^iwa0q~SG59R~^}3y~GrMTgNHZI{LF#|pGe(+_f$O3ZA**xA7B z<7%1&vfTGmpO7{1<Kb2hX=iOqxfyhx58!Tc^SwWLk`eh;qiTuq?TnrmD^$N7r3BB+ zrIl${IqHu`M^<Nq4>k`TCknjeA^H>Iq~z0kZQ3XS(Cx2WT=9o;{RLv8Iy{eBc_z>@ z!;sYByGMmev{y&9Oqw{orH@Gobr9v9u2~cR6^6jvicsx(=h1FS6SU<ta9Srk-mL<} zYrAuN_lZI>J}%Lzm)q(v5=U0qvKzn0J$>9N?0z!pLQtbnLOc-Ztl^{4J61<zLU~7p zBwV-4f||7cv*b)ccUxB~lE`8%3!5q`Mn)@M&n{?vaQx*PQ)h(Pw6W64>2bWx%kNtz zveQAmTo2PE46~Md1I1a6;8fICn3B2hW7|%33Z-;j+kq`6-Ercq;g9%_f`-({!DQf% zMx>N<Z(xu%NtLd!v{a@H8aC9^8IepdN+r(8;4NRva%p#;3Ta-z%%vk?C~WDjowxff z`qFMqh<u71j~~vpyKfDr5}A(}vTb+7>1xM$8J}%6#z~=vNisV=;5BWhfI=XSo}f+S zg2l+gxZQT26Krc&_;?qiu4_<a%)Glh{<S!~_c5`Ryc`5YFh}p;z?SoV&lioO66!2u zYH>mx=OM%T4sVuD8|9bp^~=vCKNjNujKY%UbJZ^ujm{-B86QXfs545hW^0m8$9Ifb zhet!^0ZZI3ti9&_On7ngdfHlgU*l^{7W+X*6o^{aXJPtJI^MkcJlBt1?Gmzh{<;)W zhWMcJASMgwH95K8GymiE&EJk&SzWBcwM9(g=Z-}PP>lJ^k8lKWcTz>MOy8@P_ri1? z9T^_GAOMq|UIJEJWH$+D`O^8K6AX&HPb;CW`VuM4DBzGjxH$b1n4bN~u+(!52*yX# zmTN^=kVF;pjT6oI-Wx1Pl7_7IVU3sHX|EYhPurl<Vz=yW>5AJfSJfv0HX(R=-N*Xk z%2xZnW{~>tI@pKvP-OfGIA$toicYlJNaMJ6|3o&TF{f$NIIe>A|Ei@mHB8Dbn(}j7 z{ZynZmksyQnwXg?IM(}nr;u%G;k^3ZY%m$cRrkSybt5ePKqcMO$JGorTJlC_0r{`< zEiGntijh%_eKD|h$94apq1?hixC-lV8Cwa*T>2YPXN~!2eI^RJ7Avi<xJie1C2<p4 zg=@(Lc{Vz<;${bzj6ujxG+>T=ud_1Z%;jIea1vg~;7XG0gBV>z&f=xpP5Siy&)+iz z_P$-3di18{*D%+OZUz1vh;XIjDypQ*mhXQ9@QC94ez3~S9S*b^V&QWcO4}HScuImn z!BbzAvzD+aDQ7fTnhn=y_N=6k^>n43918Rl=i~L;l_;6}q1`h)6DG-b?gZY!it%w> ze6mie>#SmOx<PILIKxIV03u?%&fY%<zrsZ$wufkV)f>vA(#X=>U*n!(*sj%6+w2zR zQn3j^dVPrJ<dv`ZU)Y=ZznM{6eDU0RJIfwNwHhS6oS;>Z!J%BWC*feU(%EW~)U{aG zmAdzLnbd@ZOYbG5x_N%M*0#En6O0T4^XmEP=n)A3l2W&G(2A+1EflL5746E^w~(fj z`${g!<30pW%c!E!wkFIRp`x+rWATWv<K68XW)8VY(8Nb|2L{&HuI2WgtJjo}|B9kX zLqc}k$<$wjrgT4?(aSxop*21}zw2<NQg?4Y?y-QcWKQFIfcCjqBsoKc;wYc63~Az| z=I+w7r|pij%rC3dWb)zmKdNsCriVyGdZC@Y=WB`0CAV9rdv|4444CQ#P~8Foh1SZ< zz4w&CnTwkdy?yz#+(m4Fdaz+0^p86ZN`nXfi6$*ilVcwJ*^&lN!ndTA&WnGVxzYC3 zP#SGd2vf)O?S-OrC;!NrW{~)8|Lsoj*U&0SRD6wst<i^=-Ng=@;~g`amD4$q6(Iqk zPa5>0N;<Sh;7`^%S*5Vu@l`KkE_%|qN;j#rLvTsjJR^VxGZKTMZehu9KmCdR5qi!< zQ%~VAeK5XSN5CLup$jE_NDpwdc6PRx-Z|tsB0V()edia_86>8gea17i1dVjRWPE=S z@~UTNU~2g9?)!6&#iy+nVh5}EgCnjcekP)B4zXe-E9F%hP%15KUtCXH2yKVSkAfQ5 z#fWYgp5j6)GIfg5r|Z+lf}&-RP^st|Y}2Ib(0$%S1aZL7%6YM2?W_n}GgZ1(W_B7@ z5D834^R>)Pi{64MpeB*J?c8Lw+&`<K5KEgPHtyGK?4>2vwfq7!c2B3*$ZM~u+?6He zWjyqqOq}$UWI$HF4l+u&-JB_c2dDY@Sy%X{1dz$(7|i;5?Y%+n3M<R9CueMSVXF+r z)J#19KobDIMxI2WB_Md;gMSiV|D;^g70MbM8R2GUXJca>A&uc$*VAD|&wo@`)yOcR z)%}=ZsHx6fkj9cfH*acHR>H<UNcrwS((x#Kh^)qlrmU)$mVZhJnVdq_Z!S>rrlP2% zAUiDPg(+U}0y6YQNT@<C%gENu!^%Ll=`=04pm*!A3px9E@6LK!@Lzbi1FsYB5uebj zKv_k)*4Hn^ae2Z(m-VFl@hHam{2nHmrl8iA6KoZ*`K^hMi-(7=a#k!Df-Uxs&++f7 zcHFL_PUnoOOX8en==ie>$@WZ#$74H{VhB+?Ss#Wdm6p(M>J^{PDIUe@tUZ{{scvqM zi}{vh<kF@u(Im4j0!~X$+hThFck*BpDlEz=Yc41*ZqBJ}EX&KO?qm=+wiTBycMsLO zlKM1D-vz1UbPQO$NX@MR$(6~)eSNeo3Far($(>Umm;JhUc{tv6jocjJ9^{0>N%scl zO14%q{KXuUl=P(@!K|{K3&y9$X4{IdwR^^j?h+xnbiHarJA#)L(`iZ-*gr%#5!q_R zs#KJhG{4e1r`6UmbK33_PxQgJ3``AaNt;cgHCjA@VIlZBQu)V)G^G=P6Y`*-{G@yh zfsqjb*P{vTX+2JF(=v?P)@1SZ_;}Zf+V-nYQ}QXg=O-F^KSYiS15;Bn|87GU7T+&N zlPBX17Ct?c!0qFM?x|1~|JB2TxANR+b>3evAA%4z6l=CE<41y%epi>1(Nm}(-}vok z&vs4~#?S0@w0INQHw1UKMbF+B_Q>G8k2l7IX#<t$u+tN5pENZgGnJA@lgJ7~L(O2I zpdB|gcqrmDxaaQ35j}Z>K&iXz``|@!=GfTS7xUj2m1muvi@FYf7DSfovwLT>Wty-Q zw3oGS^q)4Gsg8layTKw2N^gjyV|K%aRCXSc5JhX(TWh_~&u<<(_$><HuoCz^U~j2o ziPqxp>YOt0FZSOPjj&&(VoU##B+7v=pHN>M<A<A(n7CFEP&x1&=h;kYq->7Jf_qr= znGZiUA3zbhzA{}O1OQmZ)$6&aY51Lx8$U7$j@Xfqg%Y<ILd8^GCQ(ro>cT4;FPld* z+?yw#5U5h#;IuOtx*!;j>^_&>JA*y@Y+p4QsC=g7vSuG9?sY0GW@%$nrW^hD>sJ>2 z-vQ!PePs7<nhtLsN?tAJK+B7Y`o|<^)|R2-3kp(F0dHQW6*3R2`G{j@=JmBv0x(5` z7T0?X;L|gl?M&!PpmHj0yRU+(hP;%zhgtrjxcTmr_>}45a+&<x*`m@?r{{NT=|_~1 z5SsOTK+hDwW3J=v@#{f^Dt=^y%Z9EY1f1)OkiRm9Z>0aHAi#uI^KgEvw}*T9C4yg< zV~UA|gx-L@0g^xS^zAtm<wiToRq68M@44K%^;7e&*&Nj8{dVgMai|Aw{yzd6vESd4 z6v_NQYhT@Uzk~1T`QbWzh57K;1ONQveE;983z_h&s6}i*a5TyFkyVrjPVYYk;s4zz zhwT6o$0AI7P@lPb?tb;)c8aj$TE7wcN469J3Eg}L6xWXDu<k9ic;R^zqOLZ0zBisT zO-M*MQK*9Wm*@14hGRPP)FAVP@Qs`w6aw8Zc79-(&UJKxi2HYN8;}2@3o?{EHB=Y+ zqt6d|dh7g?NKl1RiU&^YUjd(6w7>sFGn3X>0dL(q7v4wE-GY56+^^fjZzMyn-8!v* zZ)ktH`WIiW=!3V?!Yz6N?CkBI>YHTkg8Jy2qq=DW)V~sQw+exOvD`vSx~C@}?K}L0 ziQke)QeFm6m@NWzaUTCohTsp>pMsRCN#|+Jzex~Z*AV<sIL_*A+njNPNO`=Vh=f@T zVMn%<of*gS7tb+j{cD0#;~^U&IYf{8=08lPZ!p-c{W}+TTDw10D*u}bgryvI?p0!# zQG4(2IXR93q3;skB4G`K*pX&GOTbtm{;r26Ik!v92vi@B)dZWIK83&Z9HIgID-mYU z_rF7o_P}L`U@PFT&W>mm0lH$IFSlzyfPyNfW<K*ZZLO9x$k{)i${v1YC-fem+@xyv zJHN`)f1iEz#4O<iqhF0$*A#5-8qAU=d3uuxJ>|bq$zm59?jujWpTlUAB^Bz+;2E=_ zGX7Oknp`?ex+bsFxAhR5b0rr4>Yv5<33f-}xuE#PJu6Ayck8Btvdl;Q_UmA2x4`lb z7sX2pFZkfEWAa)jETEkJ=A`1%T!+(dm%#e{l-#ti$0Gu|X@s&XYIm%8WD;<h_VI*u zvcnYr*5@~2+{~9>ET4@%*8DMjlvYl6;day^Jrr6%dZS)v^;nf_jJu25BF6OJ6+D+% z6vV5B;#WGad3F~XBlU<Q(jnJ_0>9=m<oUq2^AH$mA#1LSoxF{ejoORe$_Q{rO)r0c z447WqWgdBJOKGwG!2HHZFC)`#s?@CBmVX<j+smd@6Y2>U38upByzn?3@?<gbF3|~? z!erx$o!!$1J}zz&L+IDr@TbE>6;^fJU<{~wAOs7BPpIjC+jW|V{22&Ep08P(t*lfe zF1gm7V`S{uN4K~GrbRKZmTG$}iR!H}&77dJTyE77O|M)3h#lOz_4V(yp4ckrDHnbU zgNz|GTNq=E27xrqY%PDPI2xRbo?=1us)ibM&o%4ipP??55y}c+_m-Wv_gISO*FM7P zL~VC*Wt@>wugVJg>mE%-7UG33G*j`aVgsUwL%ps#eoolgG1~%acx%O^TRBJKg0(}^ zAYJ+)qM2S;3TJ~(C*Qq=zNs0#D3xtIW$zgUF5PSk7GpiW$9CM$#feT6;y4@`$B3kt zNR?itNv$C$=8$nxJ7WiaW#qxePY7U`wT|?Ebw6%>@o2ThYp(L-Le|W}%&%)odz#qV zOuK+fPBGCFD}ie?v{a5$oryWx^~iAF*FABc2sGJ66R=G_CBvE7QP^3f6GU~Kj%e{s zO=`HM?B=YUi{4@xq{HY<IXOu22%7YBgKM&};#2SB-q4dNxhvF+Jg%%UU||I|wK{xh zK?>7rxc*?Z+mXGG0D-m%a6uagV7cQs5apis`l}`Vm`IN5eCfrRwANFf{`|2mi{HZ) zUX$3@ThGk^DGv*@LLmvsi_(-&U7QYI|6}@Z`~LPBq+7k_Uc-%M6&Dsz=!hg7mG`AN zOX=)0wWqw;i2YwmjV-NsH)3GZHHPoOoB5S?h=|^bC9emS;#1S>8Xcf${7^i|l_NWI zx5Fsrpik<Iw79%?x+O{D?7(UVmU*$(jDP=s04>VtuPt)4exKWdaldE|0%sRK-hDZz za?C!qE3NfJpGCbhJl|G7H|oaewyK0`^RQzD^CjgNxiZ~9ADLSl&;Hu2E3M6A(^BE5 zaNd_DKPu{b0P>HtZgx#VO>}$vY09koIXS(iRyuc_zh2s{YqVH8n<LrqZ6t@ExW%n9 z)v>evle1^pbt;Ixcdr+6ZE_ps?YdBC7%lmo^b>@RCuqHJ-IB`8;--edV`3pw=0d60 zVlNHqx?eT9#L-egJ3nxUf^%YLeRCD?MEjJ;)J@)t0hgf)GDh6<bLyrQ81D7F_k55E zkLs&2xg1QRXrBq)uMSnoL^*y1*TjlYY<Do81N`@IBk-^J7#l3q)?q=L=48JFJgcnn z-P3O4_l<lCmwvv>{{AW?UzfuAys;K}hK_je(px_Qq-nTLI;++UlWGCg93k@d$F}a> zK3vN<LF7CY<hmoc3DaofkGxx_OmA*+UGx4>SzNzz>YeEH<=kZ9cy`ScZgLPJPoTOc zRDp+xaktlYnx19Ful_j=P8UQ4ne2@amgdDT+%==tlbBb{hL;4}HaT8R1HCV-lvE(q z4n$)ZX$R?+CR8vyzgI^3mscz9-sL~~L$_`@{=H91A;)zw2hTY3^Q=XUCX>4a-=Ex) zaKV^H1rMzl47%RRhmUI{WignT`F<cT)css`A3O*|nfyYT36GtFT<=85$L1HfyQdxA zA*)%5gbJ=^*~TNYSv4ty6#7@#AJ!H432wtq;)Oh8bBOPqEa8d#3n;~_E$VX%I7#%W z9DeoC@G?5Q$WO1EC+fN;K&70GR12EFaf$ghJ#cy6`Ec_hAfXI<p$|bnmp`W8oVR1T zjI^W~n;uUi2n{B+HNCi|8IwBY6lgvKlbkJm`Hy(M_V<!0FFdoN|IRZ<9_3h^%hM%| zvuF``(8osETph4cs)aAmP+9YAH^#jMTdo!~*cL-wCp&a}bzCjJ$;t7|apim$D7dMa zE!+n^ERBh37T5i>@Kpn%{rxT8eZ3!OkbJvMsnqfjSLUU$e*5_pUX_JqPv@ql+IWfm z1flHhsDKy6SZ~mG#BpHo&e+1-wD#PhW7@9f5(9kd)5SEH(Aaw6q&dPD+Kyq{$eI^f z<;$s(mdaPA7T3SP{CGm5aKq0K8vS_p#e<iZVH@I*ikJV2zTCR?dcXcpiKED79;8ID ziF0Ip*J>jIhyrqqmG{pzw!mHaqx>$-W~|qA5K%Wm4<FS|%IRL&=&Uyz0q?k7SY)Cp zN6$f|mmt<}Q`Xuyjc-Y@vyz7ebdp6P<PBFCHQCddMqG_zwa6F_WKwi+L_iBAOAO)Z z^1$uvuuO}0sQIFbr*Q!FL&St(^KLy$88-Di)h7TX*(X2rFb8}-;mIS4p+7IIdBi{0 z+owY-=KA>V6LEH$nk@MFE}i^8Iy1NSeOgOA5F04mAx5HUwa#r1im3}(!u<;Pg*_{8 zSZv-~x*7G|+E&K16)Ui_^);8XP-Ya-hQgbx9AhtMe^GZx`U0Cp7O<$4NJ&wDyLf{} z1~2MU2o6lT+h@FFnqKX)@BP+F7XF=Wp#sk|Veo*XpF7-ipLGdFDbtN>2erE5H>#Iz zn+m+G&h<Pq*x_XdFTn|ca{a<8cJ@N0Jl!`x5U`IZZO4%=xT0)1u}w7W8{1)!_+)VC z=n6;AB6UhbvEO@CqjYJ2EdAauhiseS5$P1iQtN-b$F11u>!VcY_R`sREpwHN)zi=+ z6}VV~xzu!llKxi0=xg~6U*VGJYJkw`)$+g*_P~tb1cAN;woCvUTH9pvJ83_Oiku?m zSio~&FmUFFfo19mqM4~8Eyi;q(t6|e!UnAFO<8FDlKh39<bsbGjlf7%QFRo1F<z2Y z`fxn=Zqn_^mLYY=QmA12qdH)nh<Jxf3$LiB_qSe)k7w9}xg&zQiLoxF4z=eO7PChL ze*-D_(f{~uKmI4J*s)(ul6YEtv$kNor<HO}T6Z}Og@Ma=sKibzUa<qFnO#$xk>Hq# zFIMIc1gd==x~}eJyshN%8J<ulN={00FtO{uod~UuU~&s%OH!^@5|ITXu!wKF8{TZR zi{__Az&cOPTmdAQM1yX;y{(4-okIhl?3?RxApu-hY!8My{c{h^A?W{C=8-Myq*<R1 zw^xAkeoSj0z!a7??Z#?2CC<6x7Uop0%e#k^Vcfe<f6|x42bpWxKlGn*qJBF1xHnH4 zyH`wtb3(7)h^9g7XX$9}F@u)9iewIiH(?j<uJ7btMv#4#mpe1nNK@i2w+=O~Nx*^% z?(Obo*i;9(4AOPz$c8{qm5wEnm?3;qKE|FTHJ!VCR!LF`i?<dcC+U@TF^ryzz=n0L z|Hs*PMm4o|-Krcb0s_*Tiu5ME6P2h3X@XLM6agXh7J7?_NC`!xL~0a8RGJWa?^Or^ z>AeP|6Iw_}?pBZQd&c+Oaev(XgP|epvi4Kfnsco+?`vqB|5p#r%B{TN+M}>Ixie;? ziGA5FJt-Vi1*ylYT)aoq#Buq9P8N#mW}4KpM7*^>u64KM`U4H8gM&J90L%0q=0wQ} z%G$}_QBMKDQWzUQc<>5E_g_cO(^F;DtDUyK+Fl#ER9fP2<W(PphpX3D8MzYnRs*0H zE8k!F;nZ!Sba}rz&BC9D%=Yil=lOq^O(ibw#Hxe3ZGY`Gw!Lj=L8f=<Gz$f4d!EzV z(f-lFk}tc`LLHjCPeYR4viWbE^Pg6GK#-`UV&jQ98kgs=wXlrLQAJCz9W9!Ls#T9K z6hCdDX)@2bhN;^R3*N#sApaYrv5;WZZX8%m@B!oA?4np!y}xqy{*qD_F5-xhprHxM zx)&k7Wqu#Wpn7Nbb0P)_#xR<#)dv1E#~OUL60x<Ld&5z@nBo?F=kF;2OQtFW;yC<h z+N`a+(1PT*{vo$3+4z7VS)$GlXg+iZu!DahKP9tcm`@f*gv-^cmlop{FM>9`z%2J2 z{kOWN)?TzO`kN0Vm3#A6Jr5;iE{hV?J#CEqvWNJ?Ywljw*p<XegC!VSF9j_LqFjn6 z!{(>7JcY2M#YxcZj_#+{E)T`ZU@Te3A-H?0cTHbt50B|)oNQ}n@Oxo*0jraBIV%)w z59WyAzjUnO&D@lj*^UlE1o0zBQJ>Yt_4#0o7D9xT^zKzCgY#9ThHkm6Rxq8%Z{P%& zo}Jr?*yEktv$@EOQO?P1p(+I5%O6Nok<U;oEO<kel&c(kbSMD|4n#T=7V*kC6gSQO z1(B|67>2tSG}XVeCEJ<EZb%(MXSy3e0Ve{5Gn$4!u6piahUvxl#<XM*7UPF+?0$ub z{i$j-9{Ja=hVdn8!Xy^+k@Uw}G8wDZg~gy3ZdIG~Gy+F=N;|LeFyvo90-3*fuY28J zZ_JY#dk^gRlps1Mi|q8KJQIvuhGl`e49&GK>+B{ueLFc=oFMonH?Z(ZD!4??F}mX1 zLwV%#U04pjuD9s+Q`{a)flP4P^7$+fV{OCs!-{K1wD!?AaB<sw2?AyDx<6=ps8+XP zh1o32j@LK;vRs1mndr*g_V`W}QN|cUPc}-HZvQ82dqx|X6TR`_Dm>3(h)-lW{nIR5 zL5@<hv}h*U{n>JqO&}Db!3rm|Y#s$tW>NP7{Q`D7a{HGujkx?iel;+@z~W^AA{T$6 zH<A-yeO<mK`oB$9ercWei!JpSGEHUoN>!2_Csrd1oF$(vYr%MDTMA*vn!B`U`idmS z(qrEBTqgDOlGuKD#cOJRXvfo1wkifQon0!dgW)usmt9-t#j;*O?|O5AL541;^5B&I zE1t+5V-y)Bx)TGg9x0Ae5iCtQC!o|c6m%7P(|gHh=S9u^-C7y`=w(5P?hmq5zGt*D zhpCDcqO6Z0>@Y>11OI}EjV`62OIXRQ&cKis*}^R&s`DhKXRL0bbiU!oU;U2o+0!>K zH=t!=B&Owt4&^ni&F4=d{J6nnosws9<gou?$eQURnR^d*c7bjvjTuxR@<4iseELPD z96upQvi|&QaoJhuN6b2e!QW8*DGPOB9_?n8)$V3^us`t`-DdjMdQZ~{OP@HKv{N_J zw*Eh`p#wci4eEGH+q8frhjq%*cH*605U1g})XI=u99EY>vn6JFDXnX9fHG@%QP+)Y z(^9-=U8r@lF@|?8;%>2w+$h%^gE&=ieC;xGK_fXiflYl^VyK&^XjNx^&q_@m7U{)~ z!@s`V9t|(smf~1jnOIeiLmryGSTutPSY3iDDih!-tRzY7)yyb3Lq;==k}Z9PRitxn zYF%RfUdF^ii^_521;43{`LgS^kR2BKJ8lc&frQ{I!ZRtPgc9VT4VWGIo|<L%A~g1o z;t1D8UAD>2P?tgrt$ViV2kQawqoYaXusgnzK@Bw3Iiv#LMu;}OnP~iXP7S7aW&@}E z#rKKLfHg0LpYL99b#*ug;ssUYwioYt$6rwp+b&C87xg77g_gnmhe6ccocphWAWvfF zJ~GyOXl$iTe7*L<%To}!k|~zb*<LB(egUfshB9PeyqY@KZtx_}9b7%)k#9WA^pRW< zCKkDCTjL>}$;yaN(Spd*{8z>*IP{xkafsUOo%zawL#U8W`xa)p*qOU^aexI@ikHgb zGrd4ow%0N;9Kel~*Lz1yfDo`lA<Vw8cs6s)u5l)*zOzpGkZSlg&m8;Oc*QN5f0l7i z6JYD8CoF9In2|1~^1n!$8Ny80G?xYL?eiRi*12{D45|gpFUjuixLZtZ9S4+mo;}w+ zhbk-){rDG!S|xe?J=ZzcX-fd+<Sd``PLnvou^Ps^lkjTdd0g#hq+T53V?<vuR$MkT zHxH0r?V1<OEqsC}2qQJ9yC3(z5vU-vF^sZHt6Wc65CezQ5N(s&7%O>ql}SqRdpk+R zwf^W;9h}Z(qpxbJlgD_%goCw`?g}EX*l34}Z5U57-87*EGArxCEO_SqHoBV#^jUu3 z6!1aUzEa%uhAj;_@mt70DBDee7NEI#n1CkEEC0=~*KW=*oHRYo)J-w3K1Rs99`Ejr ze@}a{IMad`rCx5Q3up$FpG3OE30|YtiwxK(H7r)lYlY4|qmA>;1^X$}JfY>;!=Mi# z0cR_-4y{+NdSZ%+K?$lbDdiu?O6BmFTw{ft?XMsh*V^$!qP4uy6^jnXDFKsPyJ>mX z#@-a<#kxLq&$uara>mCw-D-wJnYU=)_D25|9JU&=NT~U?H-fJWYOl<xgp;{gRKj6# z%arYsbEe%G^0<b~o7H}^4<J1upZ!A#>||i#gIJ0b9P1|TLpo<bz!l^jm2W2<)5&Z8 z<5fP>K>$nfXk6eM#qIPZLdguVn^^0ydRAiE)`N}GDXSe~b^)61cRX#rYe`u{iEh?C zNL|}>`!vK#6im)z#WCv5{^088o-3FqKp*on`|6-tnugD%^B;bKbN9wvHY|cN2cKaK z8seu+Brxro?~h=LN;uoMc^0!E(xzRQd4x@jY42cV`=Lfe6CzN&Ik<Y@5Jz!~TfHK; zh5S24w!o_#?y|ryz&3FrP#N_6foRD_+q%NW+<Co2oF;+(1+hYh94y}d57_<tY1Ad^ z^>360wC+kDgDQ?PSX}+aCw9h(!wb4fxqfmn%RbHrbtvK|xS_GNwU-k|-VR0*!k+J9 zX4L0Wp)vOUuQBOFx1Dg)*teCeaaeRlRHJO~_4l}ON6!Mive~P&pFPU#@q))_!}Pa} z9qLC^V;`T>#M*G)c<k7}P>uRn?$h3S?->6;ypXHSS-j;ey&69rvqW?~XWD)M6J@y# z*O5Vn?TdZHE5<pxz^&V><LyGeM_BV=uLQ46T2yX=t-?3zua-@+VoKXx@han&h^|h! z=UY<+i#OL$xsh^P2dAmCbL7cL8fkak&2Ha)9d~vkjeyAxvj_SSwmZje$=&vU+^`kI zJx`b6_WBI@nX->;X8QNij~fy4!MiAqI{133eCF!$QGIl>gn6A>5IAm$&C{v{;zK@W z^Utf-J%Va*bZZyEJ&McZlND{l;4a(!`FbWVt3=;Ux+SF7)l#c0p%%#xF$}puh3K6D zW=QZ|y(4#r-PNMKUQK#*1_?Hv=$dwnwt6-dc0w(5^9YBJ$b1Up=&`~Jr@-a#q+1+w z^VHUnL-b;EJCpIfMn9%BWuA%cN~c?11chSScq*Dkzv0i;FOE%0PCPLAa29!Y^J)H< zhI=GDA@E3YEd`W3<}z{#1*(W0w@_*I!a_B5y)FyfIwmzvZ=bGBvME0Gn1X}5Hzy>m zWeLzv3I&YK2$()si<BtusIBP^u5<p!N^cY9=`#Yx@tYsx6sD!ZqS`!rcm_-TE(~fZ zSYugg>-<-K3};r(F2bh-EzJFnUIt5;Dw8s%QClF*k!+`LY^Zt<M`Sn%|0dA83zS<@ zM4y+anPBb9qfK#=DAMHe+_@1Ju)#R&2p-&dfI;3Jr7Lh(i_LuEc}JSt!<NBGAWKKX zT`4>r$WqnEF_=T%M_I2<=IbcmhYClFWXs~C`;~;|PllUTU%K{#ZAjgWlxH|38{2!z zml+5|pv8om)ZE7bBSah`LhVU*dKXhiIinYj>)uvs_JmN=U5ViDGaeh6df(`|ed_Ks zQ`gMXO(Y%hfOFS@UM~>`BMCX%{*tIPNK_P4jf4j8^i1*k-vukB8Jm=fZvoGKyj7b+ zp%!4%cXknZ>n~$qhbhls5m6D>j2}#QiA1ix3K(bkgdnA9_W7Wl4WHmKbj71&fqTpa zD?VVKzpcrQ)5_-t4#P^8WQV@blKz19N{ZarN-}C<{6?}U<6834w&#y>m$Wmx7kw#N z7Uq?tY6^*rLl&}9miUS+%wGK%t_^l#vD6xyL7NkZVrD#teF;0G05o5i{o3mZ(TVBX zn6l7n#^eVSj~6Cr&i{M~z>zpB?8xk3QgfCrjJ}2@pDphg>Mo*rh$>aL&uge9r<5$U zL%tEA2t%)`sao9q&nj*_b*m_*j$;^Ia=L})^xK{}9j<}Vw{3sZq&P=}wijO!v$_`) zW~f&nxw(a2SF@r3zN22f*!Wn+CpxSVxVz#;K$a*<VQP5j&77QE33bFrH|bZH%Jnv_ zWXyr4HTOc46^QxEy$EkNfvAwYip@uSOMqO{O(nxOKaAnYZGjzP;GK~wqDFUIUcBoP zlw#I4srY>4eEZhQA^r`jlB=usOK5Pz>2FP&A=oe4a+E;SWrEp?F!enW??GQ(G963j z;F^_Gh^f$Vh_v(X%5tE$`ujQh3}O%5WiJ4LDU0{<c+vM7#;Nxn9(RZjHe)`q2fy4x zdxMc5^{%@p$-E^_9!z_+sZ;P@1HIcoi2e!#;Z?Pu2QCSFA4>BT?-@o{u~+p}tQ)%5 z{x$Y86O*SWWHWC93D>D;3DU>bzzyR(hYo&R^<PpiPEfjTZ(Is5TYRf{{s;RLs)-Gh zsv#whJOy@bck&6mbz<TLhJahGcyb6EJnAOA3#l&(V_s<%_YuRMv_HS7gGD-o1sUv= zxRwg#8WGqcC^O0Ig+)ifVA&<+tb<XI>jIqzyZq<O2H`!1p&2WqD9sAhj@v>g1@Y}# zJ!Tx$DBEaqMtTGOOQ>3FRzTJ9M|1_>p7YCY?FsB$P=<Bb)<X(-YJeRbv%YQJ|3;Ir zC#vRCD=BA=bNFFJ7Qfl3Jkhow0x5;LX1+?|B-yXHC)AFN+|xX3(%D8-%5eOno|bVT zZh1nSa-f3@n0hUNBNIj`s<4473IC7Bo`&0n&>`AQE4Eu+&7ang(o%3GkrjOAbe-Gr zX&*HWI=_vSQ0HyTYYiPkRi!?2F1!M<%Qi^U`AO0E^Klm@dG8Rpeaxtdh-}<y8W|#H zG`T2;=8G5c>7HW`gBvP4gq=)gNm0H$PkW5^S9}V(8GNqxi&xH#71ZF_{)f|g8yy!a z&ZF>{$w-$zkB-R--rb~MG4$7Npf~B4pVXR(Wk8X8ZDfE?Nr-u#yu=Krzq{Fn-xo>M z3Y!)$(JV?6S?(3j%ZiA6U!KpQ?ndGbb>>|-e(~jXaRjU=S$v~8Ug8ngZeW(9Z@g<& z)N0CLzj0mO!dKhaZ22YO(d(Xz!^2yZt1(6HJgakDrgr%=*J9mL^2X5$x$^E?)E^Mz zN%e6RdQ1I<B`EcOR^sIn-{uVyWc$$o6%Q(CGdE}hzE%{z;Y*%PGY?)EW8tpcjtqCH zpC^Y0OdZ@u5<yw*b$f>Xwvz=tEZtAtHJQ*(F<yxi{EkH2P-#B%7#HnWh7Y3puZ$vi ztW;6ILM#m(5n5Z<<#K@G>rWqP5+=bSgV>of6!VIZZT@Uk8z?5kYW563Q!UB!w~^Vz z-Ud+tHsqoz@@a9*dyB+BJZE8_d*nh@Z#};btqA-)m@+C&3eDkrmD}|PrK@0Z1$vn8 zEX(h980~f-`*)JOdaRFY(~=<N<5p2jsm3yW{rCN}(d?fEO$Oc69olA#pL^pb=L#5> zX;)A*7wjfCP|n5Q<)l4+mMOH{I9YjZh;!bbLL;3#F7)jX+LNwF2~;{knTR!Qb5?rk z{ysA9Q0$5eCs&)USxxiye}ou&XT2zE2?+bj@i7XdbO<PVU~8YUCO(Jr%PUsJ;!rW` z*|uk+<z9(V>s#|Y+&~S|xyd~Aa_Vy!k2yw7?r`3fnnmr^iQJ;#22LL0yjzB(7ld6d z&aJ7_DGS#pC}pRw`vU5YzYpAR=(}XXIlh~HGLwdz`x6$fJ^)%hi1a=qKYhbRC<J(k z5X{8bC-?9wB%nGikwnC?b5YjZgdN7FK?#*woO693j^V7;$pDv1gJ%E$@*n=2>+CO9 zJ-x45EJ(^^u*f0o0!^VPlSa3Z67ACq2h-98$VmThpw-ScxhHO-(#gbETBmY-<Tc9b zR!RvtbtRU+)tJId7<z}~J2&<)WwD$Efe6brR7^deUirz-?w-sI=>N;r7;5x$Z1c-{ zQ|*RiS4&ph2Gz>L;l19ER#z{@5ulZOr6n2x$;-nG<9!@&6<*m&>DcQ^lPkfLA0z!k z-5+T1c?YCh<9_xR974@`&aiT7&W?|}8CCddQkDOUGVtX5Mf$i8ZI5+Yhto)V5*-A! z%2qc<?^jRAi6`F-_y$TycG^vb4_#b-)RWIfak_DpZ=XdcK40B(^)5xLc-4yR@n#pp z|G4Fiiq8zqzuM}?hL-=7;M~}%tGf-HtN?kFO3`2UqKx47Y5xWR6xsL~p8*8ivq`<z zoT^?fiv~ZL08sKSZjRxY<x^Q{zS$joO7sQSe+Y5BH|FijSUv;!5Bqka<m9h6QnMaC z3HY6gH?my*B9EF?EE3){j05MLGcSo;eg>R3wei9c9DE*(D%NMNOkcLo@--LQ0cD)y zjo^OW7MN$k>&AuE&%&sB4*eNOH``l&B|Eq(Tl@5z`_O`Uwq&y&kS1;c)&H0P>;X8q z2F$><$fs{2{cM>g%N(p8;o;k3*53=i;vXZJVH9=FS~!9s()NBeg5G>V%09jkJP7Ut zACErqnNRwO39<hO`EP4&CGlUm1HR*I)r|jysa<4DA!F<IPL;za4T@-N<zvdL(8$!t zACb(LRCPSn3jc+9oBrnNf8Ofcx-yUilHLr6%VdW0xwFLP`tto3YMxR0Uzh16;5>*^ z?DG-VBBC-5FkxVP1p;wt-7jnUU)pdRzj@|g7wBIPd0BPhMBIEj+~rCa?m2Y3@wpHf z0`}S`S3a|2$99w6G>sdJTBv&_i}pUrx|oHGXk*A`(B}8Q_}@0VZfAeph=Qx%ae}5; zej-0nne&S*KffmPb&)oLjEvhJZ6oZ=$rG8aij;KM&14>dqgbXAlv8w*p6i_dildGD z8Ah(FRpCq}hZW7_e{uZEzvsVVv*TtaSBLfZlWh1<l+|*P_T0;~zxeu2oS>T{lQB&D zs!C@r)!y=q|9Ok*VEFZ_kY&}ZTGExK%?O=;&B20M=bwT#(!oYwAjuq1%ED7;il~TN znNRnZEW1!)dz@Rd_Hzci6VJ|W_u|jqp@_Q4VokI5z{-)r|8!9NIi7}p-&D<{Gqz>P z-{xzOxOVJp(Au}+djF)QD!G|V;;&oNowcC^a$^&~jbH<?_P-wLcZQ3V$%fK=#HiZi zJEd(pR%RtlR@L`zR^!xeotHV$@USF+LSxAW-j&4$^|MyOH|}~Wx=waqVE>oRPyd=L zTHTX|uA+|9c{b60u<kQvl)RCmY)Ci)bJcS^|JSqJdvJt<MtsEY02C4>f+0d}QGhPW zRA*O4Po=OVM)9r5{-u0=|A*{&NqD_?g6Iwvm<;BKRP#Al`Lpw!$hh$9THmV7I<E_q zmw62ZlCQ*}^ZUOz8v4YSl}7C|QKEmE?dPSaBMN30PYw2IM!4`-B`!PJYs+(cGXhtt z)Gh@Qn;!3<yKVU`2CVutK7heY!xJI;2jvFFIdqmDQQ>PwIQl-94lhG?icJ}pwJF_q zNh>8fv<PyQeJBlT1<I=U`eZq8)q+c#-!NoIhS$jOKZa^~D@QASkpB3As|~yo{dv2e zwV%z}9wo`Om+VqMUYepTjCvKLfrFBgU{+z^oCv9vvKs;aWmTRHFdssFfIYB|t^Yp6 znwDm5q1fq@4$4k~2xZZHtNbMoU(ok3E(AVgI%chPuQvN%!(oPh24%K`8N<+A9xiJH zrCrz%b*Zx!T|Px~!p<V`pNfQ^<Hl|56rgzoclo`Q)f81$+4l4~H}v>ithz~cV(eE3 z^Pk@X-0Nn51p-*BQfEU|`Mw4Y$0J~@F0d|M8cuUn`Qc5``T{BfTt#5TU*nvN=$+5u zGhbfU`u(@SPo}ADOxzxeg{R;00D>6od(ds6x;;e)Xmwqhx*)>T95@DYR8i>D8!V26 z8<wxQRql^Q5nWTA3|LHoy9C72dfnNuyx``DOuRS$pR+!@;5rEMfp0alfbfsY?eDp3 zXaISTpB{&?G>v<ul~IUzix(%SUSoht<ZKmhV|3mCym`vHx>fbDJ(73^n5)mcn}?6_ z>tG4`NnL<3$OpSJP6~|st6>MgC`Q8e&S@;#`HPksl5V^1GEO}!yrLJ<tEjRhl64v! z5RuG4bHzXYQ@N9tPnKHV$FOsBu#^(^t81W0wS-u{zx?8s<G?H(ZM)Zx!kxaca6WWT zx@>*MjU1)$=k}G@%(pOc!N)Tk$7q;`7_(+jP>_Lvfrh=krC!n3a}qDgo9<f<bf%kH zzPWK&vW2PBs-BP+3^{Y6gagpr(Ur)ZtOYi+(U+RW+2#WH6jfgvS4$rI%FJb}tb&?S z4lEPr!U4%d$B5he7h`nm@~vI^fF+{{t4OtYxxMR0(pZ(OeDGP{(Yu$mcHuRhLgKjB zOEh4C$XNP(0roqdrA{~L)V62A8o=PZ@AtuNA`%SeRZ7r(z)BI2Teu1ih&;nM`Ch57 zQpGk_6i3C0hdT`~THB7JhHo=(;y$-I#kY<&B*1ciy#3D;({S%&%(%&<wCRt=qRCxR zQ6wNYduQhY6Y!)7H*T`>Uu5<UfqRGTS9v}7IaqmsW>%kBoUf%e?vJzyfX5@BM`Xqi zO>~J2cfP>g7T>LXQEsjy6Je)>y|n+$Lwv4(Vzx#DeSPFvT;yED27eXO0$_v8$97M| zgRpnA-o2*dX;JgOKFqD$N&_VOZG%DXvO9r>b>-b>cCQ{K=I`8(<!R@ofOi!FR;KA| zHDzM#*s#|#vl7yi#z2&$WqIb-<`3!hbMxX0Qm(a<pdtkKo!w6|OKRK+EudCO3lEof zU<qZvjsHCFrA$09>~rqb9a(<YLbU1+_B{|1eeG88+A_$(9H@4)cM>hkWjsS&eNNfG zf~BN9qe$7l@bNv-kXVPptrGyk2egja&2lK~iSxLJ;Lb}G_zKpZx$xAzN1pWfZ)4kH z_Ke2D_mNZAs^U3#;kuXAOPcEV!Wwu+dUTMT4$_|1Ime8SgK3eOSJ->*w8s5SHDz<M zI%0XcKNViop}pX5pR?Q}CTlgCKnWLo1_eY9Dc@2!pIoKL8A0lMye5&bpo)>yd0Dvy zjJt+6H@47(OmJ0kU43dWf$`{V(yHUl_tR98NQ)0PQIZ%pkAtO`I<?-(jGwDnU8wxy z(=OixDn!w$!OJmZW<>UNdDlrziEJIzlvB~8M5K|C0fePZ_${DyAR_!iTe+TKJI-S9 z2<EsPKE3Qp4J;<2Q+2H;PBbW*9K)orXPsV4Sg|ODYa)z_;dO5Y-8uCx46jbL-92J1 z=+NdfX>xvr5%7P_w0z63rHqzU)p)86b`0YQc6_NBL2j~yCX~t%*|IhjI#`*@kRBw9 z!|F;`o2)}xm(alHc7O3KUmQTY@$%Tn8rjhSO(z;A?>OyRmZ!I@PUC1fTvzWAHKu`4 zFks%51EVqut#869gsxUqyN!iLdO(&adSk2J-0*Z=3zb6RBX{%U)<1hyA7tD37<O<L z^sTd}@N<DV<#3*!Wbuh@AO|RCGgw?4lp6ubKNjsgCQ4krATXxv_C(!!{_{gW?qJS$ zKS#v&z8C=c_G0Hy2@nN30srV_;r(>R$_~Zn$9ON%Wcls)2OHOw(wOY%fL#5TTsEr# z{36Rd6&kIA!NI7Aky2|aJvcOds~sF3(I0UkLU_ajN}p8p#;lEw^YWbT;vSuc+O=Vi zZ8xRIb85wVv;-=^!8iuUgX)Oj1;gu;HdOv!Ct~@=dSqv}o%b*}hRHi6>2}h3*D+gx z%*42DYsP9=_QCbpX{Ula<%<&6@k$uHX(k4y&}(sManQ3y2~!9$^_wc!j<fia@7<@j z^#)GHu+#&KK!57kuHO3>l;!E6{Io5L?3D!mQbD_d=PvOWi(obk99py8uc_PGmTYK1 ztz5U;`rr`Ip;>?Y(+7Ru3cBasxPHN<c-v^G*SaF1`P4o}9vx`jo=NZ+?Jd6))Yj{* zQn=ZsDrn{Br_PSQj=e0G?P|wqh72Ed%K2(RlL%hb*|@NC5(}#6341k8Khz}Gi|b!i z2V1VSN%WmBnBgw)GruadA?UJ<4W-%7U8`z+SodnVej?!MS*&H*G+j6MIl=Y@5M%ek zqEm02+oyb$ae4el7)1Fj+LwYj_EYWfS9wi*W!fQ9xMUyS4rwy_V}qLlZ9ov!9g1=q zsmrOWtINyF!&(WY%R2I4Gr3jg!YDdi%4MBapG75D7V%TMY7p(jiR|tWO^N)GB6U_% z6BFUJHzm&Hm;NGG()bdYf$4^`+r~&&jJ8?^KbxdP7`kh$*H<VV&=gdvHsohoT>HT{ zPM{M_AE@*`!k8k7CqS95bR3h^kWW!D%E1W+V2**9<qKJ95t(zb?IC%M@C6o2Q-MHw z;t0Gb+Tal9LegqD7WGBp+E1k_4jq`HYhS`Y7Kv?kZyZerMuc(>w4w9-V3k__*HNV= zw>S=Qc*3oyc+*RDFAWGTnfSUubDVol{EZ~|Mw_bczFWXLOEy~tlHy@cRZc@cFFIG( z$C8$6`)B3kVgQ6V5j+7FfNJsH%Jb}Opk+41ZELo`>>x9!Y>VgfXWqLq5YZUs?kPGo zV-XVcC<Xe_)cww0rm7dSrk{oeAMcv4#xz~v2#6?vG%*p<-j|;!knajMHq;uAMymp= zN?>OB>kFdE?@yAHW<Is*zuHYkO7DpI27^uCu&;hA>zA55VK*>`3NPv~>!$T)Le2z_ z{Umloybg+}gJQW>{)!daJm>sv5gc0a{76twQST~NGMK^Ys^;V#*mWm_9G9jiNW$CX zWyE=q4^kE8vcVumv89b`aYf6q3t6itU&Avo_i7BvG+o6TroM&i%-tP``_#mKh^vPo zmPR=jynDUBJguLeeaUg)hQAaBuZyldu<XUF4Sm=BJf}5FJLR}Vy7iB}mcRS90lCZl zNI-tCm5(pm#wIB#X)!yy6tJ4H@%@7hB1Y9mOs{Qg_AKaFCS>_Rxr@CKpe8bNv$R!T zPhTHmz_)g7O>j;8uWda_-ePjn#z-_gwo~f;r;OHC<qyw0vP@!AIQYeBt%np7bVG)& zUKsQBi2kPN_yZaM`@-2*Y*2~pbqIQzY_$16%sNrhFTZzt?^?>;q~s;6tUcFf)w}Jt zIG_a=Y<ODDjMP(J=+qqvOiNYRJo7Lj7;)c3FjLmrF<<clV@>;qRQpAMfOH+@%=Y|N z3o~c4->Qm>Gj`nbHjYuXC#7YZ>XQ10yPVr=+4Z(3$CK#fQ+YZMgt431L9VvW!Re0$ zEv_zFHw<!uV%5!>Q|ft{uGdS*LJd_SwuJY8XdeEhUI7WOqAv-7lOw2e+IM!nZHh>z z(iYyQH}m+iHD=s2$BA6?V3cpsfkMR6hauo&g<b_nI!;mNLOXr?pW(S22-ur~Z$^nS zYX;x4w70kS3ri}Vn{z;92NHHlfEMMR8<pd|3f9nrjeAvI%HHdxgW+^W7t*2-`K|qn zi%sH9u}vG4!z}^SF6OoD@4!!t;$)Zbcy6Svgw+vAQ-bh`$TSweA+I%yiUZ<@8yRsQ z;oic}Po+>la=ax*XTQmqO`mEwW<bePNY<dNDcBE;aOp+op0oa$8$2-3s1zykw1DhB z;UnuQB`Gn@B;*(re}dw4GZ(Ig%5}&A>hd@sFUCmd6dc`H#p{53?H;mw*RrlKV~rG3 zhJrZp^4{2TkCMVi)^&>;?ekBWI_SOzsWzQ4z9r#3Q|{4&j&ZCw^y8zR9VgTj%w^5( z)#TX_CgOZn+U^YFwjQZ8>jy~<>rgk>J>mioF1T)Db2!?I7w}G1)#4S?r$z%mu9(V` z0q3c3Vs-u!_KAIu4>;#=V$pqSQK1Za`44~c%hI4p*SD=!o!t^&kD!tLO-;gxY^%kt zZ<^wY?xQv-Eaq<pt9=aa-@gNcK`h_hcpDv_l$dx<`9d{lk4y(hO*|GYYBpqxC82FO z^)#wSUN!?m`nJKA>67JvxE0sZPMp%9KadSP5zGUti!gbqcR;iL!@x4X3B+=FgyV_i zl3tF#pB+$Q_FQ;gX$NEbS}taizE!@;vIISFSKVejvGCgSujZUNsj<mD_bF?!x$n9P zZ49-UKIESHwEqI`4F)U@@WF$ksOoWmy2_U86>_@gYE1~F#tJfLYE}pp#h9Dk;cT6h zjxrwHU+mD?zP5Qt#livVaptSjkMWB=-uD+5X7)n{Sc&o<#W`%{P6+tXfpq)YY@Vua z)8u*A+nx^M2F>UytXl2=0MVN@?GU7xH+=vk>KGqr*n%|`%5MN(K@*I%Cr;|JUxa}- zZ5p0ibRV^dzrS#I;+pG@Ul@I@Xg-0bJ#v;TP^OTe(90_HCkTGl8=iCI8VE>uBv?Fn z@W|A(EpZ3)nnb#f$ad=gkdE%{Qk#!1PLb{wOMYFWGJfKuC5vVI*qF)Hh)n`ik0b4q zp7#Q()Ihq>tLW5Nt1@^Ul>lV-ubOTqy<0?e0y>x9gPNoDN;f=ZI(1H#kKDoeYdCTt z#O#2S?CMnG^1HAnsPP$;?4x?@RO;d|yY+;->@LYSjU-L&PQyn_$<xh+8(ulUs8)Q~ z=P2uHl1d18_-$qw+jJdWTy~X~8?#dxfj~*fV=t&T2IN%}-5*E#RG{!_UnJ$-T)HcT z$K#Ms3KE0UI1B|3Ul2XM7c-Z+izBrtZ82&untSH(sl8lZ2O@VWlMgKcb(+y9#3B*% z2JQfk$8#9t`zUo!5Ki=C(aTS-TMtD)Lpv<8d8c~3{Z9`kAVQ%#GQBwOfosEP19M>x z#+K?D5l3qemi9>L=s(W!Tl_2=C9u<alZA<iiG>9L(&W2;;X)TX2Lgw|C=%D!(7nQ$ z(m8pbKY#ezC)ZGh*m`(wE`VHVz|qaF;&|TrEE&>njmR|<dFH)Ms|Voy%zfAV$%>tP zniElDpmIIO)dL;7q%i)YGwAJ$uauu?hy(36WTW#c$s9WJ%5w2Yvxn!=(3zIMrHS`b zSZ!tta^LM^QrS}R7_sx6bB!S7rXQ#Tf5=|m^X|&>uOK8bYNCtThYN&wV9M-aw##SY zZegv=p0gO!vt?oU8IBuU88!|AeUM#~a(PZKvWR|e!VbyxLuR`R*}vH*5@h5%dNm^$ z1=(ziD0g`ZV6?MIDPTTRDb>dgG{?%ZJl7CU9`6^&CLctQRW;XQ`k(dW^-wys)0|D4 z{1xxAGh)U_4#bkendeZy^h*Uy6xBa2HbADdfqeXC=1V!s3?DtZe3?19L$DVk;pig% zM)_dD4`;K#tak&d^SM>u^uZM#USPAUaG9688i64I)W1M(CZ`>VbSp`ZS+y({?wx<) z=Qu?dp-=jgA!wIM8oPbCj)S92O44`F=iaYP2Bf3f9`c7cyN}JGO0QRVL^qQ$u?cdB zJeuNp1>0kEn?geMn3v7a_wtP@_6wA}fi}pda`e#mHQMQ_)8tY5U(q{F_(aTVaN+f; zn<fLHwRWyR9)$QX%rUmW#67^BzWA%@_m3t1?m3Ip3gPB!DFF^Nt8MK2{6eU-kvfMV z6HtR#q7UPqk@Jtv96$70%?pL$VpyH|k9uq<W>;xL_V_%D0Nu<!c2cn^rGIGrQFp$I z^^V4J8$W^BzCo-%rE6fL3+MIz*iVRCXe7q*d(8ZQwzj8$DXF_PElB+n6M<67InRWw zF2G=#X=&6{RA}*vD}ZL(^GX;ZtlZD9wZ?!`=$GTLAxT&R+6)=Bbm7hk-yQqP;g(8( zQpKz>Q6`4M>Dbi*`hpWPnO!6^%l0qlyPF<hx?TW<bL|>w?@A|&zq~K;7NLE}0I7~d z<MZEpee3|71Uw=1M|E=zyiC3iXaWRa;^wtA8Fz?y32}Q`&q~!+!de1qzKr9~Z9j{f zm847@haAMBI=UnT6_U~(8ymktp(IG63SM7Etb{IJRPn>!5fHC<`(&yntF7&n{momq zZn>D71JXgZL!I1o{sn}WK(Wi!2(PEb9ukCzfsd5CuXz_&fmXV4?+IG!FjiT(Aul>6 zpO<f5NcNogSH@WJ-RW1CKcSCNJ=dM(xHRI0FP6k_dyh0i9B)4MH|)Obp4;g)JotbB zeecT8c`*IzY$;pNA(To90S`_}vkz>cWBU^goKO<v-ua1;1*`3}m1}Ejrw9PJ$d1WH z{O5;vdV0d}IGm~fN~d}44iy!Go&ACb?2fY7MaDDo^77QmW6uwh;VyV<DuX(Lj6eB` zh8R+|+I*RSvtA#fKqNHOWvETLM($RtF6tL8mR^3iKU9jNb0`mS>jgRTuLIiPJYD`K zpR5&M6;<t2%7SnKVS;H-t5+RHv}?!<ia69`G|e-(_f6<FruKs^J2XI<@sHKtPHq_= zqX)S`q}GGxoQMl!Ca29Fyh_W+nC^SP%9&0K2R*fLzjN!s19Rv6uf=cQUcr4A`iW+R z#}B;VQWZjFY-7Z-zwJ+rfCr1KrXZR(9X0I*+_!15kE+kq8DT&PPxHseMBbm)rc9L0 zIpDsaoJUrTQnnv0Tge|n7w_*`Z+kj_wd{}8qqZEMr@ZzIERT<t6>!MtdXV`k8ScH} zV0Qrbu3LBvSr$Dl{0uJl5&bVYN5&aN$~R49xY{~peBtQmC~)ITd`42z@W>mUORs{4 zAdtzb#h%n8qsJn7Dw$qV5)y^)-rZsqU7ORuuYCZJ&;XaDmM=_(q=W?Ph0Xhe)`>yy zO9KKF;sD3ZM0VW7O~HWTH2#6`mwK!3;{<5w+|Z*Q|4<tD-L*z$>d(f`58QKkrvEY# zerV>KYw}+1z3pp5XFb;eI||lBrohkSNNOmuw~w9nDF4IzvM-JqqRs&os}7&;)Z5aR z3;=SjG9jG6vncVK5k^z%1&%VxrT<wBeJ=sT@9NGL3tj!T_EFKimzNh`YpY+A$HLzm z6P1;C9JRy_A}R`j2-5~~Vc(SQjLz?jDpH&n+r0%HlLzB?zJGEYI=4_9<buM{eW5{5 z-3W6~`zU=Ei)?-e_hxOBjNL;AC(wp%c%k5OYROYK2C3+^|I%-J=ql@=m&Gu1w|#&s zD_y>px2q~x;oLwl8S-#$7580AYqeKj=FCYGfc)r_tbDN?oOKl}@t?5-@EgzJON(n~ zr-&G+x?$mTps+wrUR70_6+QE8*p{KOkQ2ih-&U3KMv%x}@keRHb9S|v?B30$PBqx) zfW<!=8~RiM83D3qa|esiKuoNv`qZ{>%ib+E6Fgi;hDa9&-8WI!Qd83n2EdpHEqa&l z0yQp<-2HtA4uk6DNO&@r#kT3)WAt!csb^NGVc;ZaT4$HRvE*@t3!i`5vRW25>B!(3 z$lRP!N8Mpf)WtsniT4F0`zY6sOxZ~QQv4<Afn}i@7(*ZQ_wEg3^cTgr`9OXIUcw-K zW8b~NX%#X)w>uCwkg&|NPf%%hE*Nwtx4LsnvfwoH6>Jrd%bWY|nF3WE!QUW(T+Rg3 zY(|`rK{}#zPNkbJG4PQ<EZeshN$HOq*q&lZxZNtN^ts_(^DLhaK&GeaM=zeKZWyap zNrGVNvH+QLPj3-_5!=rBu7~i?Obxuac?kWSf@h-(^jxvtoIFNh$mCw1|Kjh{Afgly z6e}s8iPblH@6Vhc%f-bskJDkdbDz-zir_NM4V%4ba^*OXU-PSCmrvPi)0vN^*%Vfo zVywQ3xUS#zJbjj+TAw_S6mIqzNXK`*bm!~SfYfECEaNQQ5eIUd-Fdw;67ecC`n17( z)jd1}T(+nYMN0;0CxSg`UPd2w>6nN3RI(^Ha^vZ{@@IB**eh89kL-6BBw=gwqEEU7 zS`;5f;Q`$FHmMdIS~|xH<42_`^-@0H&Fr?eWps{TM88@t)K{}gS60xup(i!mIF-wU zi)#uWRMQcprr^^%O{1l|)q1aGoqa?&SN|+DV!ueaR#&8V9W1>*FKXCI;B8OQEkP}_ z<SVpw%-0AZ@J7dyA?e>9WJs2$ao}I}vgTC0a>atPoU-NtGKwFc(|^~8%z8x6cPZnV zFkhD?wQ5rRO~uf9)31xXfikr8$6eBSH=U;4WgQ*H@0lNFxUpdsd!zqMQf7d<ARf*+ zL)Ua_f)HNbfm0wK{^N_3z|<#u7>!yxM(o8QLpimpW4&Lt*z9}qYdkWppP~D@MS7K8 z(y*A<`VozL^qtNEysL(Fn_6(v0N_1$un$_9$y|5AVT2=M$jzk?FBQVH7~@o%X=QON z1|3XN{Q^?1diR=>qs0YweVFM0sC)<LRQ=fWn~ANwgHy&4cn<8DEKB`#RJKB#+ulkw zC-gV`t>hkE`AYWi5hUHoJJf*^$b<WdcLxSr$*V;<Ix@Krd8Atc*sz*8ss(+$jS!!- zX;%;_i>XbAGFaGnrBfS+>RvVJCFEI39Hk}8lR>fQOuHACacAr3+Ar-b>hG6-P)LY0 zWL)%E0;rlEh355)Ex)`(0ZnT|`o&7uZ|7J59EBwI&7_VB^aKa*BX>=8td{Q_^J?i_ z&fQZ!yuEALOi{836U+=rA|Z8n0oC-a^Zu_kf6x@i)wpRB@jgn|SnzK?zqI~mHe{YA z16t3XRx+p`XP+U9j&SMbk9v|f^$cNF)QIz<dW;o+>zm?flye2eb-CK=l%gml6tT|Z z;NJ*4d%~eEF{dcC><`2)QVc-sPf`@$1a0=1_9@4eZXG+}4Y#}6Ar(O)jITF~FPnjP zUG017jnf2*d(@Dn<Bp^w#RBaf8_MVXw#~oY$pDakml?;Y)65LzR=(S#&?Y$djjs#$ z*^r1U{}5>YdPqfV5g&OOS8vKk=0rNPeBCr4;^eax%9tA|iF1KVT1$oK5Yun6Kdw<` zj<)`ag~_cNN}_O;PSp?EIqLaa{S26JusXU$cUyX<qD`+M(7}wEllu!|rSakm+4kt~ zZ1_l-k6`GxT$QEM<nN!_6<V28?l?lE>RV_DuZ}NH^zww5fh|=~FoL&I0)=zNN8ge5 zv0BqvbaZ{$D<af=tDeAE6e|(VBVp}JB08a&teZ;O{xNpVNs{!>1cAfL`DDeEn4uV; zc7j&3J7z6-dPcaNu98+UY+0n>{(7Uf`#t(>51wcih$*P^$Icazxy=5P{%(9vRRWsS zNPwEirQ@*XUVcaCeQEHt`zy(bTL<RMA9jv#d=py)*oLgT>b>Qr_M<ROI1!!5SQ)BH zIPd*TwSp@oCd7mciJouQzF3#=bDnoDXgp{kd<I0&8{>fAe1l%fQF=CTsWL+s&#D`L z4R!M8*YVOhUn1~gKC)~%QST#JaRNGfXH&dtV&*?E#y|m=5TB6@XP%G9A-xYuFI4RP z%OKr#{0E9D@ckn2BYzP!Xw6x*SO`e%BJt&7tAxVyXNuvpvyftUUZcIjrMhdb`0}ef z0H<Ku4e~*LNu@qaup#QqGHl$23CK4xw`;|>jnqk07|Q|B|Ig!R!pl#Fw;=~Wc{@eZ z!|^;T7Ok|fYiXEs`<US(<EfUUPd@kAzn;ZT`;O=_zkwD%Cx<*{j<ezrz2?0>(%}6) z8grTOCRb@-#Kqw2Vy~56a<?j9@WO37KMJmKLjTDL&?#Lf<H-z>temYnIt^Wc%N5Cp z@PQGhgZO*_E{YQ(p;t`VX})lFZuU{W!uk(XYastlB*+$pStXrrG|hzh9hhlT0-2GY zb!WJnb`*?Y*fshB$J#+Ki-lybui<vk`aB7_eB<$hJDl1S(Kfbr3mQ_7T5oQk^fzd? zaNL06G5(Iz%LKnHZ@j$d@aS}K6PE|0o`Srz?u@H5P`S>srCO6nNuSjiZ5FKFA)%UC zRs%=h<aqw?fhI;)jLP*h`idZmIN~HHYOGEYacK~>LhA&-N+;aoit5|^tL@#D)@_ax z>2k>j41TW{*Y$r^Uwn&_4YQL*^ktK*1c?1~6)fQ+>J4$oTTZjKuu&XSKQC=Sv7s4| ziK$!MfrI(&UuE`$C#agmdy>$s0xx8V8T;<sOIDlb4AQ*;ro<yH@rvQH&nOOm0yHe~ z8i%_*$`4qGwmk*IO>`MO!dLj*lUh9%sI(51#BBwh@mMJ(1!Cqo?CC6&f7>XfU5#W; zR5&QMGi%Fy$eqJ@gad8kWKyA@Q$b$~@icI0pO=JWFV$`B9oM1n;{-!g&%xKF?C-l6 z7W{!W$6-PMT8Do}vb<ykpwWLF>o0!gN|_tBxwMY^u%0-fa1Q~`Z0r%IWeoFZ9yiES zrL+d`&=gpxHVm!uLEiDYTjPc+Zurv5k1B+V4gFmfO9ctZ6p`IH)HbAd){^(`kS}u5 zdRjyfPaC<pAxUH%hL2rB6j(exFPCbTe%M!)t5}YM(29^?@*C@4<I;@kpGYjq{H$Qv z=Dod$s&>ajJ<UvJS<A^bJI4D>#9Y?`KHRn$>)HDxF@|~l5x&tW_MRn|1TzxHO|@EF ztLaF^vP$+|19*fk6OXeN$MErX>@HyI)s+W7Kl8$lEB3<I<~@Zef&Ashl;^IKrGf8s z-P%{`@wg2Ol7S{a+~>*s`8r*l9W$j6=t`i0G4M_l4-Q7U54LEO2&T4H0Jrq>Xb|~T z#y?lHxTh;#TB4u2=2~Iqn)tU?@>fY9hv>S@_CD7Vev9`o_RQAmv-iI2D27ZPdX|rE zO6dF&E%_5;C5JdmC!68o2PUm%i6G|$;91Np4~kv|#@?Cx!ycGoIJ@i0)9)-wdfSDG zdJV&dsX1`&&g&AQ)4>ZrMyYDFpgu=`34GkbAl<EmO#1^-L58Vhf>W^a<3*IjJVCK3 zye>|<2wMPrHq?rKL?%e>_lH*q?-lM7?2d5U`kVlBkQlUctL`~`P%8OCi-I)p9sT`I zV(Hw^-v=rU7y$n_%p*dQrd@e*9ujcW6`|UK!{wBWdI!iiWWc8d6xGOnw?yL}$r2)P z%+<&${@v(LAD5f$&A*b^a2E@c9~=I#ZYM(|n~X@X)A4soIi=;bOgY=~08i~yzWU{o z?FH5p*wA;({?a4Gw>G&R5*dR>9ioL(?@ZbRt#?c^=2!1X#R!Y_ym#zZ(hrD^4VCLP zW$IFksxEkGDBKmuWkIv}`3>rYjxGYe&s+66X@<G1oyRS^s0Wm`S$|9P{Xb;E21DOZ zvH(rl#rY4%I7PPpCJV}tF-UYKR}+^@D8#FGi7yd8)o!(};Pd0KwxqjfBJPOw08u8p zdI=azW(2|a6%)JlDw@}7D<7zY+DWy?`&2s{Q6`cGr`=p4j$ewR(jwHXgj5ZZ08pNJ z{t%C68+6x)oVKvcLKLz>S=;>{?tfRjssl>imwx0fbBt!i83p&wj~6S*dz=rtFnmOw zQq#%V0cI)k^mbtV-jerpVX=XElP)z^7mrM9=()lt4}pI*Tyc2<Bpf>T!L852%RQ<c zSoYq4e*DLW{GD!<zFlpa?^MLnM(*qcHm<^%QGS%-OV+-eW3&k&br;j_+4ks7@4W$# zGSjV)JQBqGyjYg?B^&Dx|4;V7zpl*2B17Fiqbk=(U4n%GX#kb;=93A5E`E|pc8Z$y zppHM(fryxOWvV|tqHtC!!|pXvVaatZ%XQJt;&a>XoXP4XActL80O){2^h*&+QiV4Q zd#SKIL8vrjDA59S6mM5hcj_!ll`{kQ5fhjpod`VI!42rL8!u707I+G-ePzd}EcGlw zFZu#t#SWIdK7p>eiFW?|E02Tlf&8s2jy$*%^2@(YqqeA!5W$Tcn&>{joGkD#>eD;M zhdFHm1m-a8JP6_;Tb^2paLfcU2x>D0BkMU*+l^+0M;T8PF4fb%X|&)wchJCI_x>`g z3fzqbDNjLY_F<AUImg0Ku66<Bx7)y4`SW;Y^e5LY31J;Rzk7`4wAjV$Jjb0<pAOK1 z=W44Be;!g^MJ?_V-{9|jmx``(Ejg!K>JCt-&rbzViMFZycqBnblP2^-)5a8#7S`(j zSfreFcvn8!+k4FJlT%ur0r=7oV*b$pwivR4nsk@_{?hdIbXTODL5#}{Zo7V9<2COx zLI-ZRY@#HR#}snD-mH#U#Ea$S>sOw_-+{E4o4#WEMJ6EjWU+0x8WBJ1U_|EahfIN2 zLP9z!gXS2tRVgG+<*hvxtp&4vFGOX^*Hcs!l0<BRVD6QmwD}kAx(uhew=kH$34z!0 z{T_DVYzChIU$}^|yoRudmp^>xVQFgam<hk{u9h%VQ@{go;0Sky5kyo?n|l+%Lu47~ zOIu-Y<Uzf`^HfA)q5S+B4n9*D;=fgXrYYaN%Oduo_4z>Nv>(cTm5+BYjo|qTGU4H1 zkql4_Pqu|B-81hR-u3?cP}|6R-bj%h_8xDc_)p|C5%y~X`?y%}38n43NW1WVqZ1@c ze$fd^WrEKCrW0hKjxuNWD{06O^*xUDd`NJ<WZPcuyZo)B+*#CkJW#c9a|0FNM!zHP zl=R-%kH)%?sa5;kwAJKObxxJc$+w@*N|d|8EMFcN`y9+e&($@b(w^FftYIZ1sPi{x zJ$ghc?F^^j)=Eg{=>~!XuFDx@{=72vh-=6WSL_{NF;<fN>9x(C=;z^ZZHB3a+g@zL zA&AgWg=U`$wkAc<+UW$jd~BR`w2}@}`}tRMBbnkps)*6-eL~($&>$giNkOAnL2lHS zD`1jO#d>arFtISJYIw9%8LNs`iZxCRmcuku_kT114>~0|6IASY1p3u_@4K9XNl%;X zD2QY$pbgxkR~oy<m<2NDofZ^A32N}a+3~SXS}}NQZo?SJJK4L9<D|j>n&I;C<z5S( zi?bkg<Hl+_zSOqDfkR>}(8LSge$dvfay8-5WxCT$>Y88hM)KUq4*kZgNvz_%E*w2s z_=kS5!_zB9hV9!KD(UTXR*^yV?<G;Ap!4*<=g*AB@8&;ZK99|c@`BLGwi`ErRqJ#~ zL?&Fvqm!XLYaiqMee5WP*W}Kp$ht-+6{>|Hy)U1<fsV(l5Lg>JrYDvLFEt?ARAXTf zCxb3bjMQUxsbsI}9B~CyobUb27&CHY%a7@XKnbwOypDWR=V~4Qw&|0G<~$y?*{Q?E z8m*%N)_4-Kb$%L1hLF`b7_Eq|HorJ?l4Xm1`__vD8w?Lg85uoxru}}Jp_{<jA_X)H zV(8M(LYvw=_;fPYuD<xI*!Wg9;Z_1yx7NG@w5X-7$E`9v;Qrawc0Z$J44>&0=Wc;a zk%Gb{ZI=7}<`TUD#R@FBa~J3Ln_3htHU)8M#uAL>p@$*$aj)7dljY4Cq%VC)(v@<g z&^;yW&WSi8(63#aR(%HuB%AiYW`#-LukO7*Fx8q{>2!ox{{c5G5VY+t_E^0wDb0DS ztfDX4KKRMBE7ZkNgWI-Q=RO1Um5L_50!eg_O=y~~kH~+AS#;H3TEXE#qcr<hL^f!O zC6y}^kIs+w;IGK9>qWCkaQs6`ZQb~lIsL|~TAu*(Nba{_2f_Ouh!eBm-iLqR;_&|; zl*l7_IDgoOp-16a+llt~9;cTbLdDJ(aL)JnD(Q@g7N2R0oqw~J%RaBQ;V`TVd8l5! z=&;OUGCueWs4M3E4-+ytn)G^xuVA6(MYp3f_ohGd1GCb(eJg1{M#oOMK7`oZ>2!4o z?+(><SoL!n!fDfRjpC)NR#ryca*?5~uL=6&)@xNB<kYGiL$!x~J7$W#F(&T4GW0kH zxfc#AJ`GcRYEM~lR>VN@at!W1M2)4Aw>QaDf8z#jd>n+@_&9IcXn|nGr8i9Hn>w=I zQ%P=oqd6gew^223qujo9MlF0(i2(g7f3`lXeiEor^+d)VUP0{Mh=pbB$~Ll*LZlLO zjmUjwJxRDS$)H0C-d-QuKTc%x?_N+t>tlJvdBv5BelMa-paGOT$+t-Z4ImD?r-eX5 zlUiWk)@bPd``r>Z#CFN&&LM>YBGl$~FRO0zhn~JM7sz1j?P{iQq53bAEu(}XtkT1U z<lNZ~(0FO{OSlV59=Xy;!WD`=zuYQY9{jSKB~LdfoEq}vh)vw0h<=Ytd`8#~)V%08 zy`e+8KCF4x<6W`H?o*-Ti$>c2ymTeHKQCR(5c2Nzoshg~Cv^|367T<^?5(4s+QR>T zLPSMCM5W;(3I^Rh(n?Aw(jqZ*4GqJ9N=k@`G@~G;NOwykF@yrc&^2@oH8Al#diCD> z`TaiYyVjR~S!>SO`<(rp{k)&o``Lj*AXJ_64Jo~*%w5EuWGX^bG+Y-078A}vN$Uw` z>gg;zC&LCXoVec4{DCC=ERLteLO)xbR!euHEGfZXNS$@dg=wcgMNN5#JtS^G0o%q7 zU*>`yRtL-U{O^cBGRyn-#oyIW6eW)_iwB7NyL`|&1;<O{ix~U~*eCS|uu+ZSOEy=( z=psv(GlyS4Ua)_4J768?9+b#k!3U_j_FZ<MlZT@tifp|h7C#aZU$9c!wuxG0z*Pr{ z$WuUbo;5MOB{m}2g-ZE-Rc*C@0+D*krcG(h@Wa30%LHW0(Ha)~rqIhIz@`G&ouD3@ zZkisHQwQMhh-6+c+c--sG%a|P^4aPIb%J-a@i`PbG3le#lNj75r6Y&sx#uU54p=Zl zQP`)sh(iaS;<LDN`v2hm|1tP%W}0{b2A``xF=}kRUX0KoY2X;>|6Vuvn*UGTz+2C( zvd}nNv&(e&6W^LM^CrmnRcA)wwpW%&Mc5Ja?rQ#*HDewPnVSHRFm&0_jHF16L)EZt zOLi8nMGipPRb9gWgU}ZH^$a9$`kK5fXHyR-48py~Gk)0=zbNAe6a-}g7vcYJg#f*x z|5*rF0BXxgud2qzq+BU>5ZVAu&YDCgrzjeow*QCqAd&BE<+|p+Teo*m&|%c&m=`DJ zRjMeMwmZ^Es<klBmUa8xj|_gGZrK0T!E2)s=AxuS3uF`{i0E%hcg|K7!$zZ>;BQ7R zsXcIHeN1G%;(jG`Xloyl8vcEaG^<v30x3r@%7_|ZO=bR`DvJY-)%aWEAHpkFUz$?i z7axL_eUbBBf+%xbmebrntzus?m2W=<d^qQZ*yp9eQs|xJ;)rWNLqcP9(cl%8tm!hL zsmPP=y;{BXCyL{+%TR8%b*d~F-R+`#I$5ysI6rN%-|7ts$wN}&20%IW0;t~l#tM}& zG-l1HLfYHYAQ~>SI><>*3*emsbmmBb>Pu#TvBfFhzt6eQq?oJj9y7q@0nS4|A5^l5 z(Xe@E-SI^pOu&m<&sVsz@*>SSqi&wO%)dL-p=?M$^<bZdYHkVu&89|1jcU?0QY9{B zEEdm?(#Omni~H}~zKAxz{}bk3e4O<Q<_0!)I!@h65r>zlN57#>*+s&S<bYN`14Q|h zt!rI<RUGAmLB9hTU;&``DdgE1{wq}v&ci|R26@g%WziQ`D`JQRo#%SJv;N8ge-uih zmwO-@=TjYnRH{hL2lcM8YcC%O>9P(@DIe{vM=B#AH+KS*M{3R)JxKuMXRlUg0NuQF z^Ku70zC9jYzSn3bey<y+Uj;a?RXx-}r8k4p8~3*(rk4WW(P>>b?(+7}e=HBXc@m>? zB=}%})*2xjh4NpC!9HNd*qP{D`n|^Qp-KL$^xE$tf|QqdJ;3U69M_FPnlwDKMfd5D zxoyfaHG@Yy?2vHL<@48CH6qA>Hn2|m<TVem9{jJxA4sqh>F>^@N$uJ3-wAqo_az75 zz>3+26uyE)2DyI)9oar$@8y#uv>{!pj}WkBO_~xXSlX>*nD^2}f!D^6@x2taw`%*J zAIrPCQyg4(xpRH*;+Qy3+4L9-rb2W%p(^vQ-}f6l@L#bs&1~0f@_IJqkdN|d?U|GF zKje$uKWuw$=@!mHuGK;|Br*^xL)B6Vqc@ddb6elaf$urf08ggf#i8<s%Fj+a2>w$v z3-;FM$S^mBJx`#?EP%QH%`<~{2~|NA@CqD+A@j%A$tESqB#`<#vD-DS+zb?+^fgd= zrnhsFKZa=}m!13fy^%;$?;w79hGzBcj?wIsjed8A&hwi!8CJ%X6R?_(2f;E4qrV{I zW1;-3$_0~_+0h+^ZYx26)$VLPz?R<=O@an+5AkPl)b8H*K?bv%F0l2+<kFA71k$B? z$kn48Sr_@|s`@*{CKpa_=}craL|Cy`a$uz6QhNI<5ccc#e*(qIN(<<xc`R7x!w}4h zF-b1GY!fFl1c>5{$7r-)*Fo7RE3GurTWQg9Yaw2-BIVZWQ&}nj@5@?$odmCNp7QM0 zuE4kFQqfo6%*S3ok)T4$D;JmPHm8T1-QTy!gtJWsS>NF)z}~wDNJIQXR+BYciS>Tt zl5ia`2xPnKXa3x%0g%c1UdVF4=^YYq8u|Cm&iuSH7CIGc&O7dieqj0A+8rRMm9fgJ zdULyaS;fb60Sx(vLOY0R4~_+|!dP1OjGf|1p#{JzlA@6hm^PFp=;S)s;>eAj5xWIi zpUiz)s6c{Vb)95#@YaOEF7U{Q<_o|NnvqBBiw{b6d3~w}mV{U1o!<PoU_1hXcbO@- z8USqqtH;KbuJnujaK$i&0>tf<#!Dfg$%OVr&3~pa&=&~;jS{2Pn%7PSiFI;2metKo zKFh>LXy=sch2C1)2IP7v(fn}H(NGR^!jTEZyvaND^4l<(IYbb8a^5{wPry@GuSa`a z`KVRn|H``jd8|j<p8;b{M@}zS&mK#hPG8BQaMHR8JQw!K^je9b1!WG8=6Sc#p<QLy zRE-snEQQI{`CCcW442usq<aMRYRZh+^7;WqYT8E#G_@^sZ7M!+l>7!!77p~AaY~vt z4Q@<XIamFH{cFGI6+pl$$2tdp16g!xp9<<6ST&r<$CW!rzeYo)RmT3jx53poj1|8A z2)`B;Zb59D(lI?sQY)%GnC>k;9r0>(_210V2*U?{ZAGHnLyw+t1dNUzZ`F_OkC!h` z`jrP9t(;QGoy5eQfcdJ^uP*pTH$IK+(W7>I^}@T&?3bO5a%hD(8FLdT!QG9dxdi<% z0c67{NjS&a5o3}P;@Jo3NmDKw%dWgg9N<b3_u!x{rBjm)SS>bcxdWV?)Rel=wOdXs z;shLmY+F05-)NawI|)X+f3<#&$XvL*@?=^<{WDz!poD&7_B-SA;~Mvlx;@l2Gt0B6 zo<J_ZRYTvsUM3{5yL2BdaIWYt>E51^KUB$}{Z0dHYvL$P29BToa&#(pyu$?}U@TnL zplArfl!MLRe5gR=u8vm$Vs$uOtDh%dDj`)QUn(Y5-ww0a8z4u}O;T$<1l*y1R<-Vj zI@+Uqh%j-Z2(B6a^Nu;)-pmq{H-8$Ed@oT0jgkdGfr8<NcLaA3a<%z2d3_=ly?PQa zWO$C|$m~TXyHvWHOJ6l5+H4!1yy!nhn>+ctR>Iuo#7uDwZ|ry_zDlMY>^T+rU3*u_ z3-184c`xJ<&i8tmUXqWq6Xq~vJj_{pl1eaIy!&{U{&@HKb=Xbjjz;yfJ)IvvcSbJ? zy*T(M=#%W!z?wEVETF@%SwjoxK|8(9G;qwVK(nWYA`biRPT5;sh`bp3%_Dhmd7!*@ z|LXU2^?o%woyqMYJX*%=^dt-BGSp7PS87Epq@P&2V0Scm>(?kRm=SRj;-wVYCuqtD z`31@~GtMtq`XO4=!F9wQ_9Dc-u{-vNl3zS1HBAJT0|F50phP>d>W2i=sy$)(`hQ7H zS9x6_2@-51D$;Wy-e=DvZV`?yzaG1+ZclNRfHlfenH)QT4X0Mu#Hle3^`2Nw8^rt} z-AF2SKEmXQyE@HmlKa_l^8WLYJnVjp(-Auwjv95MhI$YoF$N|qy3J9bW)nL$uy&dV zV3;GZHT?u6!y5ejPlqaEXbs*QdAUX%8JA?F+>0!e=b?rwPh9C~jPP+IkAl}Y@39Rh zGekU(SiT&Sa8_sb@i4^Ny>ExTx?@FcUp7gH5>*YAPf|HL9p)Up{HUZPBWEUifgY%f zR~Cj|bq`ul<#2B}6+B$~Ttg-W*IE1xPP!v8WQXIZ@yoDIy%W}~Qz@_zTueF9l-ao# zT|7)zoV0;gw0FD2abhO_GO$nYROs%;KfpDKvG2goaMjEaNa$d&ki{-0057tYZZE%c z;p($5fki-7?44rSV#3WN-bq;7b>6P-H`?#AJw5SQpGKUz4<OM!!%%<bdMD;PI@~t^ z^h_8mnyU(+_&FVMKesV+j}dz|^Z^TbHTLD*L<6grHZmw(l*k3Rtxe;Ud~C_`c3G62 z2+nZgvq0~-YfbKis=&KOs){{i@5vG0qZS_{<|Kzi$PA(q$zrYWc&GMNn9)Y_P`H=R zx#GUX8AN!Eys6VK#xV;X*Pyn4lXug~x{LW+M*ahsrmQ2R<F~p<LUJ#(3x`pOgYGmV zngUN&^EiS&Zl@#14Bq+7yzzZBy!LstxWS`qnf-^~)L55!;uYwRlO@AVqcIV%D}q|1 zNHePDj{EM9b)|Z+%PO`7Mx4stPLfB%bN0~IKg!8t;GmW9JN3Qt^+TZSGt4BjbjCQ$ z&DOi8OV?bc0-FjG%7J|+ukEjWCxo<l(~7a{V&lgW^zM3ZO<qMzkun2@#7n-~BYsEa zQ!uR?)zXwQ{!yC$UIM}89Yt*<WUI~p=eU)m=ebPP8{eYzEtI}zaHX$m%9|N=%-oV0 z-F_5zMf6`=`a^))3&dLyq02~^9N}2M8Ruc*+|Q&Iiz751$>V47U6i!`O9ec{YoeHM zV>8E|E!8?u{E~@4!%j5ueLd)S2gcEGicl$MKcC_IwPzD8d(w#kAK_co@a51RNH6Bx z)ye^&i+r*AgiE2!A|~5qAF=3h-jiDGp@8nD;Ln;jr$9{4C{w}|jTOym^lkfaAzf)J zhX&Cw&(0?k;Gf1?)V8-Xx5IU5PL_lLDCak+QpGI&QN3wY>o~~Am(X#uzje=bY(5<! zkCk$%|7V>ZGyVelnpfjtpo61k;sS?`)1>bMh}_NX`ju@MY^%*Dz~u=h{B#>Oe<~ob zb$UEPj~B?0z%GZg6Hp9z7w91pJmY&16_zf-qF-n2DvvIefP?C{(M>>^`Hqq3APv6k z@SKDf)TJY%`qitOgKUpR{R~$MfRB$O|E5rG_Vn-$B6IGMOYSZm$okKYm}KR>Zy(6w z==Bd!Gj>@C>o=9QZokl34uHXBCjM|NBF}%)w@n4Y?Ip8~(@?_&juwN`Ap{Br(9uz* zp{e_-)|eN^KGP$%+=Mj5=IJs73|bB#80Bf5Ef#Y+EW}JIR`;USfRjTX<ZuAh>ZywT znU$UWH>vjNoB!H@0pG0^0UH%gIQ<UF#IE%c9Ua~;`>WqCVaHDg+;S4yM5#EwGnt{` zxDN_)f$koYf6tb|uZkPX$2r6eMrxtuaVJzwPl$z6ciLX6jP4`0*0H=@e@x3M1M@(g z{O`YD?clBx&{5z@V;3AZHeOmSCQ)^QhJn=Hoh>sMT(cRiwt{`&oH4eD0Gy3+4<X!Q z93Lv$Gmjegw%LITI5{3oI>bD>TX@XF)73qb_^GQR4(eSG<Ng632X>z(A+WQL>vkcG zFdfei|L}Jtvt;ZT1X%vC-;9=E1$bSRfn#Kp<q$a%<~KFujK0~MUC9WbIcN$gs)^ph zia_^h4(eWKp2~=ERG*-^J_{U=P!;d5oaP9efYaQnlnUYjB+nprDC*gy>VzXf%H#(H z0}06_B~GNo<MvRSvQnh^{=b%J(-tehRAx0}jvFKLn~u-JUt#Q*)TJBXsdo!%Uq;0a zeX}#Zs&zL>|Ab$<>D6PkVS?B9blU?&z`Q`iF5ETq$I;!HeS~_W)6NqGGZ54m3swZo z|L@s$y@-J_zdGbjDSF-=LMb2l$>fYgKz!Gxx%L)vI5d{2HoDTa_6@THA{8UN>G^n0 zLRMy!B?7oCLyDAvL|=9P>JTFR@LtwYBw;@1Pw(8>idHK^3i~>2)XE~3`G|4|Br*07 zA|__|5F#bUpbw!FV|WN*7ehaUh>O8z2UwWCr#l=VOtSbJE4ELkPJ%Ye3CN^>&D?A7 z?Nyt~`mswHH&Jfqbvd%ut?SAti#PZ-xcJ8C&H7qj*MzkFZ?<T_@Lde_@PxMdnfH^1 zP7YLX%!FbZqD58*&d=C3PhQV3kT5S=7OP(6t-kNx=T`doj603M+ZeiM<|>|<PF>}` z+yWv=h{{|HXORQD`deksH!F<IjJ??LOUrAjSu?&Px3lyJ3}Bg|8(BQmi1o)!^!(m_ znjELdORkA90w@4Y%B_-EG^azMa6{_N74ow{kHzFmLWQJ#@3Wp~U0;5gbuKFEMRNJ| ztQ!#a@TWJDueRNK{`6jwilHv0icM|(`ebTxu7kE=>Zh&DE%xK-Ja!kI9~ODqkCF<T zFf-dE5~SN?HZ8Ko?(1xl{D)>#oG&jap5tt1*4)BD5E`Rfe!E}M?0bXd8J+T@OP!Qe z^@m#-{LQ<rNv1QKIL9N|qcu4MTdm;_?<I4FxJl?r<y29ldzXm|%4M=KqqxpxY*`Lr znuk`|L)bqwDULOMA9|@$DF>FR|5764bj8?gAS*om%)ZB==iI<p{+Z29x>-+Y^H<_6 z=Vr}k@A%s$P$QeAQ^O~?(`TMOWiFvAVFAt1uqs&jNl?mmkM*O1-yAB=21SjEL?b6q zCJhBI?0Zoj=@L*e+g<XvZSInCb}wsNtY_WwmPKcspI$79bDy_uNpL!<%=P5iQC$q| z9AWHgKT))xF!wNy;2@JH@fN%wy;l&_ow{Cd6i$vJmy02wLli`?jJ~1aPTJ=S{1V4v z^8FZU;*-klDOgDw&dGLBmNBqZiou&PFMduPFn<xL-8rz%CZ)B_0ELB2u*9~XZ8?-u zV$;udBoi!FFgf5djA5Oz-IVS9WIu}O<37zqzDHAxA3ejOMf1NHcDaP`7krruz2wN7 zNWj)#$2~wzlG}aD9OrLwc1q3Yp|K7?sNhVxCpyWpS3ZA12$10Il}*T#$Z}ddy&F@V zE=($kZGKym{GK<$uF8UpH{Mg7RZm6rGhGu(*{XQ7W)yQ<#FZqIWMU+@h{RT3EpAaf zrLl>YT&;``>#L2D-@j23fhr%!{LoOJ44FnTq9L<Ta~sB+n>5<}OD*cN^sx=`BW_J% zm2N_2C+-Ruzky@~$qb)b$xVvmi|Vsh#~sk*HFz~T8NTC}c}8>5Y4c3<vUZFZ9CSR` zDK)~_Gb3htZe#Vk>E+^1|9*3wFSY6P5VND1V~57`lNX$*3K1FW9|zQaP31XGWl5<6 zgu$TWX27no9Dm{DVPiLvp9bmsHnH|CVh^EsE?(^u9>P=)skW`(>)9xWzSufaR=u7+ zAio&8p}wikH5Hk9L^aFAZ#?!kk~)qAu1hE3&Hwb#)_n@;R7)!A1+C9FF+p+9PIuEb zzBavlF?nV`SFDjL`Cfg!P^GgBc$wwl?U}yLW$%3i@!8pqqJeHo$eWq++#GuLXAs_P zcV;#K;P1V%6p+F+Kj$$kFiQ;X3c+VAJCA_^R@VE_Z#}`ovD(LvyfZDn&XCF8=i45R z|1em7>_ux0KE5~eR}xvTWaCt;fHhPGWRsmsyCV!McISk>8VW5&zI%&!kYMs_MZUcB zEat`-p*GeD>)naGF;kp;N%2PZH&D{hz1ZbC*R+S2=>hHUc`NYh_vO$8>P8v2j=D<w zH%DOP^~1p;B?>5$K7-3sk&>8<iCt;ImwAP3uEsAyuq{cV@Vj=kNhHmB+#t2jfil^5 zoQQ#fVh0%Q;ysFu%*H5*`6ERCc>L*|O6>dZ=JS(4ThhUx<^gXPnVpY^I80}tFq~{= z?{XV-cZeE`dU^R!1@UnXQ4Et$!KAlJY~CDLbDq^D3|lVjl>Z)xqGUIy7evLWtf0FD z*T`qe6S21PaX_c#%W(ji?0qbbSq{Rou&CW4<(XFP0fWBh5P6xm$D2lu{ERCs<)N9f zPi7F_^(E7Rz0$p0UHahk+yLfr)Rxw2bu(Ge$JptJFpN0!#;5{;sm~-+u{eMWRKM5> zN)lO~m%6iJm8@W<LGT01Us~UXku(c2=Ljr8zymvhT`S^CaYsUe)}(ojIu4(_`SBQJ zi%*|MO8eUlN6Au#W2+f!AA#RPaOB<t-aXy7f{V4XG6E(+$q18&24al6b;2`{OV`f= z*o=Ib8Sm5L)f6W=HVRf%egEqL$!J~jL(-_|1c@A=)kouq3|Y*$vFzF72z%Q8lo>}# zA5*ZWvYI}erdBQ~Jxv80c%gFhjH>i@@9UV{bd=WjH!^}(PJCu(8axfPmmf>7Q7hug z8#iV}&(gVCZXjY{1WKjMuAN$=k@4bdIEWlUdiI&^r-s(z1;;Sg4TPG{4fvws1&1Uh ztVZ}Y(j$<bR?MBo>>JUt4*r$fEaM9oM{!!D`-6tmrNCtuEuKTGw0K^n;792wyC$!g z<a1CtjtOV&g~mT2&TSE1z6gKS`_9myyrEEX&-Z>}wcP{zx?$vBBZeP~ibZY_okT2X z6}~fl!eMSbmC4l$)WpiBWaQf)qdQy7O%Yo{vu@sX)15;7$}4sgZc}vy(FeydY~`<N zFJ~RhQF?b~F52}7;dWWQ6`K1?Vt1Vaf?|*Z^}A6NEAZxL;aJ`MMmR)g6c3@IIhAY< z#rw(}zKJlDBw#ti0$joA!<juS#pN4b@+fGAQW6=_hHBq1kb1-Un(Np8_L>_Xmsh$| ztFew0kjihI(I&U&0&Gyr2e;cmv!BNkE&j(SXW=g<%M96oX3`2bNx5al2uz_9WQ}Dl zFCC=NBF*oL%f1h-68KJZ3-_Us7=4}M%@iuSv^zxEH;=25)pzJ^O*b5m(Z^VpYbH{3 ztl571oSpu_fpxx@v<jSGt(wg|eHg~pF7(3uMDcyv$V>oVM!DCj38RiPUSH~6V?7m8 zsGbh3AB<(O82sVd^EvRIN+2Cuz%@L?B*=Yabq+ODdIWChTzK1;Z3mU3qN`fE9;dVG zkst+=ICr8qOIu_mNt3u8*=W{RZ?^?RT)lFAhkp25luQ4^v+~vAx$fd78F@QN4E&=$ z`!vn-8CJw=O1}f|sKFv!<Pedgf$OZTDdg=2sr4?-m)%_6y~CDK8a&WyqL<7!xQE!q zmp5Z;W$j*);rL!W;VL*pXfgS@OH3_{Za916A?XK{W)pg3IyMpqR?*#z{W&D`Lort7 zYN4pmY_r+VOr5zam-&@_`7$t5eUAtsE+d`$2uJq;zP(1m`%U;)N-vN}%?x<N)t}%; zUWex|xK{n8JZR>NlZSbnco1)~SlSVRgr#HCf=P6Klt%I;^`g)2*MTg#sva8x1ax7I z2f5^O2x``_EFysa-rBs(KaWLU#6uEq775+v3WFUgl$)I+Fd-8X*f(oMaUPcDqKYj= z7dgJd0~&-)8PqI<>RyePt4s!kA<AzoHj(X$f=)#qs5_jfzU=1wLGWX{v(kSH&hqgD zeN8(Wqv$_dbfq?fF>secWlOg+LdD5}&(gmWu>k;n@$~LjbQ+?eCE>#D$7B}$el3^z zWh688*_2&tqh-P+#d2XTEvj1~o~twE5;ZqX3d}q<;4J#HI!}EMh{Fd6=t>I68eF5H zaTtZLOz!Mxsj8?s)t`F@A>(?Y4?lrYy3|V({H}B9s~^Xp7KcIGoikj03nLH=T#a;_ z)bKXZ==YO#P$fu-5S`Z1jIokHOGr5nEo-z&k2=-<x4)Fug<347#~MAWaG2ps=Qr%H z(rnP1uYHbNfM@fhzda@(XK<`5(;Cm0d6nh!4-xE|#L3sfJJ*})y!$$C8SooDX??gt zFc{_c-u?0x0V>DV#+05j(>yy|Pctw4oJWLi{^R>p;ZFI<uZL5cwe8dD%i-yB-!Fn4 zcb&YM<FbAPrnd%O{8AHs5s#VHE_}&Wg_BQv9qyhf^K*8Jx^kB=HS)9Dt0&-f?dG|O zSJ^QcF~M@<^aO5w$<Ez!uWbS004$~YHZ<5adR8*l;Yd5zJg{4PfhQP}@!<Mr0y3dl zXt>7!*;`P`-c9P1Ca~oAxNmI3{@vzP>5@O8&0){kp9=Dd&u4Qd=GzvSt5NDcbJspX zJ6X*;3;tl#Jh9KjTdu5PQX=>BJ-l3J&;gqWjH`9z@tK%e`>Xsqd{3C=js2_%o$BzK zSi6>3r9fhXa3$}2yW%TRI>$SS1V3%Mfju_6wsR}bI>}I;3N}c`PBKVbiAI&pU=5zt zXYHudT{3g+^e^N2AcL8JQwJK${`$8$;^4s(?JOyuqdtwPTyn$k#Sm7_2LY}Q$2)bJ z6<f@;m3dyEDIY$^G!4Hk8h|)`0Jg$SF^LHC<bOT=3oNhp5|p2CE2h_eOwMy*K&sQ) zw&XL8P2E=pmd&+vctgI^Rce52G<j%{oT(iewB{emt{rK(0F$@rBbVyG<=8o6rzt#o zE4|zA!tZqyq12@1YU$!WRW$O^)Yfi6a-BA;)9WpNB<oGKvcpf-auohS_lH$9doyZb z{IvGAv2LwmvDbWE9{9ScP53bg;me7!xVR}Bds}tW2wvS)xDVe2x9)=wZq3Us%NzFh ze@uSe0glW`&Cc956%5UmtEL`FeN3m6m*!5R;`Hi3Kz1zJ8Icil5&aJ5PG!|!|4yOE z*UH!iG#Z=+adg?3O#i%x?I@_#TJkbEQ(%t>G?pxzuz|`i#uktch-<xAUa<7>mPgn; zj->Rl#!RDxByBW!U~M$*Rkq_9swej1PSsYABQ>Zphog2GEZYlrL2&-SY-2{7^_>i4 z>+O|xtms7+gFl<pJ6Q3?(Ao~K`l3hT{)wNjl;s6T{Qz~@xzZSq3i6d<tE{KVoaY%n zM4q^c93e2!@NbS6-rq-n)U3lk;$^K)(1}f{%=q%_?^T)#_7N&7*i02tePtmTVGo(4 z#&*BChhg@bPcM0Li+;$E?~9oF{i>eRW$3A1<?G`sLVYRw#-8Z(dBLrDqh=+QO#D-u zoG@patHv_lU=V$p8gYZ^<Bj&F6Z*{cC>V_s`Z2NmmhU2bT^yP&7~_nQqyPO-FNNOw z^;AojTuQDlPv5U+b@ckW!K;wG#K7%rvt}{Pzl}%S*TS8vSkH`J(L8~dqYPQQK&NT& zY#jqa`K^mTf0IShl9}!+!{5o!InGhmKMU%!af&`gMWaZWtJFK=qJlVScB3H6VIbW( z%1A!Kfmz0)P6al%DYX%x(--o>d7Y<G-DNbUKn;qDjC1cLuKdriOHW?Aj+i8ykTsel zj+i>9L1pgT=D&Ma3}(#!P~X@#b-9L<P3#Tchr99dbYc@d-ssv*1({8JP@FNlE4P^c zghyUWv30MKbOrfM=L%U1CgGTg-kEbwK~?VbDzeb23$SaUU)N^gQ#qH@&;i^?8?Q!z zKl4+m_G^A3&lH#Iy^pNMBAanf?>nfKsa#lijrXy&H#RGyW9rU5J_zSCJd-k4LW*zS zpr<K3pQic#6E*K4l{w;F#ck<%p_71Kt~cqu<;<#l%8!lMa1h7$lx}QE2$PJGt<N%U zd~V83;OoD4n_00t-RP@_VL`MGkm`@I5-I|e(pGW7G#Ai2(rdgmXmy9B#s|f^-UT|- zbpxYT>V}<|tRSX!9$RgXakl;=Ev~Fb<HhggcK=#pI-O1?NM&KAoT`kyA6~f_x&^PE zyBrWek`c_`Lh?S%-4ps$XI60?W)Tt>3=aO#qI)kOJNLHRIX8a6H))RqU$==<6-&{s z^xN4aa2HB-<xBM$(ub=yWP}Vz=IIMdP=Bf=@nt-|<V#a?QIdIO_DTimq3zfER`TKG znXY9*ZY4r!3{=d-4ROgTU7<z3fcBp(Z%Tn6b(c{4x*+k0yYZS`Jd1-<(6y`*U@_ER zdo(fCAL125&KEMUpHLL#)Sbar2uXL=cu(;#PHml>#r<^*7Wt9Acj7GDr+E61ykL=F zr4Xx-f)=CBKxwiu@?!EC^4<^_*)~Zv>8X@hObA;DWi2eTyni`3L*KEJMQoc)KX_^- zeJYhLP>eQjwEd%);DzKiB>!@FTClgOg3<}*8N0`JZ`~wY3#oR$_*;Z48C3`(SRh1L zK3^^xTS)6fHA&TA*@x9#TUyrEqMhZRCAUf+!;(~wJrDc640L(oVeeqt3H!$HRcInc zaJ<T-`m1pCl}D+4r*?5>17y?W+@y`^a%MFcF{MTM*2AfHvJ+<+f$q6i<;r`)S_)e1 z*d5Z`f?kB!xA2QLj-pX9f>8q-8+_!pBoZYX9#JFsXaZX9md6Z9k$XBew6NMXNYkNz zU9+ylF^t@m+-f{!W7M=ORktY>dU<;2T8rka%IpPi1s#%U$|{iy(z{Zy_EaH*Ekntp zr9+UbHp3LdID8LxKS-bWUV3ZpyQdWhL*H_9AU#}HOvkdZf1m}qaR=1GgjT3q;VjU< z{AZYIuYV0QM*(~J`Zn()OnE-W-~_!LwZr2Kp*^c0`q7~&#<^Mq8RE2E8v&y-LOpR9 zKRw1$ya$ztq5K6X)I(OoxGRxYYQh~R5`Vbo>*UErGgom@tj4q?hHXzpK06e7dfiR9 z(gAj8TrK2ZMZ4%^VbxaNKlc_P@UU(oy-$0gi_y(;Bu%W`u0c+$sB&xRb7aqG^!H?K z9@iLekf6k)!>yKz7@d%whU^C|w;PH_JE3Ar`crQMHk3vau<!C}ngt}ozOo%L2GA_= z1uAnnkAx+mp0f=dN^%7kBORwi=Ah?)hl5)ri|{3Q=%uXpz+T9v#l9k&MXx#*jM{m% zkKoIX%_|i-B=a5?w@%xlZeh?glaEr}zjp_T$d6!=VX*7&oL~a>g?$_ggKzwi%!j18 zn)_M88DI0Gre%%evNL)z7f+=y;r5Pl8(#;|=-^i&U&fQ6tX&Op*Zuhhz&Cc-x@J11 z98K!>U6DbP5hlw0)U4K<<2r#F^5cf%)Ik*Z9bb9xB<+f&aw$ZJ!M8kRni_EqLWjYq z1PdMk-jivJ`m!L7Dk;S}z6<U56NKf7$6Aj4iP~$-KT}-AbGi==uxMf9!J(F>7Vhs2 z)#W|d+b3wgTkmE*E=+~=v^eTN-9nV9n0|L<Gal>>jw`S}0_2rE?*?rQ)6B@kwSA4J zOeN3X1)SfxyCd*zQQ_X**eY_CNRV|nCi*YpB;$A@bi$QXN5s<Va$3da#l^E5g-x#* z)?99|yAFJ4dQUnXlJ*FbSiF2AFBkHrVzDalJABv-c8_8zR>a-@ey!QJ)6|~Rs6)g$ z=2dcg59`xK5bYc>uCp=>Hhoc&^qAE*Vn!qT{Sd$H%046i#;rdgwTP3*OXPidi9#h2 z#&0RH?HT5@p}iSMUx{wpN3h+7TV#V>tkNeV&-cxc{VhUZqJD`Gw_V|4hwUF^`VSTT z7tYJ#`IZePJ0GJP*?Q|pi+w>{Zy9zJ15U4<nS5>!<ZSg#2#PasPqHkQk!qc}P;WtP zdvygo)7`jP@zB&M{gDhY9bKZh60f&qR=20E7_l?*;6vb6-;b+^1?JdUyDlNA_NL+h z-!HiZN=6BwWJGgv0rO2KWAW2`${`O>N3va-3+_h?2w4{NzVyNepi`4Dcg|ad!3PO- zp}#+tS4e(K6`D1GRFQT`vHin0&`ej!D~guvK4;&^enhyCF;@BT+W^GcKHhyV_j|KN z=?5RR!;!6?QDofsC@TF+t+!j3m#Uhl=)vk!6gdoBw|B;2rx!bSer=u_n#ZcDfG4Lo zIH+iMIZ+c?+Xs&a<1e`GC>?sB7DR1QyY%IWrtpwH8=RvbNp)Tzp;o^BZSV1uSWPHz z$oB=PSu0`3@Hp>aa%=h1b1m!+d~x4fRC~1}a}(x1AR+j=-C&&$`$T=UrFqdnVE*l7 zDmiv=I_G`W7>8`e0SJT0)`Kse#cgHIw=t!kn4JCdq4uK0qIt3C`Ld;}KX?W1#>%ok zex$W}`5o_VE%~doDNWan!4J>HoBUKKn8yrPRV<z@?;!25KgEd_o{es~^d8!3cTEvG z=~Qu3GS@rMZPyl^mS<HP1m!l_v;qcp>A}LLei}4VlWuj3RXSN0LF-o9?0h?F+x_AW ziMFpH`@u1KG#!U_3Ybnpk;@Y&QxRxLRfG>l%<R;@X8_%0e;goed3rlDsCEI);}+TG z9IZbAnQ$%H@QT8-cj^Y@bbP@s#w}iCAgN{)(?Yt)W$M_nSF5dNCGE6r6#(VbZJ*0L zqi?*;{_H{7lnGK)1gUPmfDU(IqNxp>suiTfH>enquD1kN6L$TOT(tME95E{l^FGsM z#}18fr)PVnlYiUo7FalD%`1xjZ#CkZIc=KY^#vny&kL|n^jQUXNA616?G|UtfGZHb zruPF=Z&B0@p$oOrAG9blkHy>o^p|$DLd;>nx<A9o$-FxEbmFDAkMs*IarB*+<jF)F zBLfp_hZ-;nL=GRS9KM{Ld{I_MY9o)`=D61LyN;kzTSxy2V~_JWwquF6J6q|S<1r?; zb51e!*ZzE3!11twaga>WxIssUjSaA2_%w&qH+~2l3jqw0Rc{lXCcHQA;y>`^wwW1` z6^vI%sxm0lM{402bJp!9#*{r5lE;QreCF&Jjvdy@Lu%>r#?tU@KEt{Q%hzT7OE`@K zZf_fulS(}yvD9T&<@-?eur6wYbh6uf{%*P)gV4hK<Lr80T6O!+wl%KLR4PWyYVK$C z=3Z$KC{^(@F|X!J_zZ>wBx0mqa3dQ8)(<(Xiw>^x)(_VB_y~1X9%Jv<9p%Lk++h7p z2D>)EN5>}a#2_<&oci}Gn}6C30<XY7Tf4_(N>;(DC{6Vo95-8c5D%#;E?xIAI7NHe zaY<wcy1ZV4n@9=`P_2g4>)Co|1>>Kuep6%Ox>l-H{c@EFR8FkTbKPuUmWtvr?_`Zu zVoGukDbA&~Ii~3wEWu;Woa`_#GC4!|+wPhR);&M^Fo0(`g*(dyFv?+hFFZ+0xLpb- ziFH3bc04O71`VW_d6$V*nhmr9-<`daS=Msi!9_C!6at%rDa1KbT2zQ{^&TSVnXL2_ zAuc1SLG^T?;@;e)bz}#g(d6sY-BdBQaT~mpD-4#`IS@ezo*Ih!lf6XL#o-{fz~Q+a zLJc08L{qcJPyc?Drn;MOxnx2ur`ECxE}-Bg_G)(WXH&&W6#Uyn2Y*xI9u_PPs(!#P zPO0ZZo24a}vPw@FN5@`lXY8p$tJSQ`)n6$AlcQwB>dVG_&dOA)dDO#4GP}bp)4l}L z2cx4?dz{Y8r=0K0OjS!yeULuaqcC*+MT+~b>!EAC=(FDaTfi}nXwgE%(Xaum!)`sC z(PZi^IlGz>lqYYWb9>#rZl5iEs0w`2B{;BX3{D4RL^2=w(Zy4;BxbQVkBP>ZEAa{g zKP)`99B)(-hc3+j5f-E$#NsiT403L3l?&Rn+*{rgl?&d|ut30q?4aTF(e{k}@)JTz z_M_WqGR)r(T@BbeNvR~dcd<_h7JXn`S=v}_HCP-=@7P$@?aUl#G6LcA!Fd#Z3zDol zDuI^*@=kT3+nb+P`+{b}3&71wGb!+)b(eVKs`E-J)1J$?Yit`|FW&RESJ9IDQIJAo zy4icN)KNVq)ltzy<?KV|r1F-wt+&IFXs~1kTle;$APUQpkw3%3awG;H8q8hXR)spp zioAH^Cz74Zb+Ff~+W%zs(o^#6WrKzM`o^~7cqn-@<DURbp#_X~kflqGFn)lLlMr4O zcc0%x$22v&;mbz=?&)Kz(*DVd5aZfmNkf*kRt&-+<eK8*OLby{qi(QL5v{0Ywvz~0 zN9oftP2WsOH6K&Iu7KU-^}`usRG7Wi=LqInCiFw)yQp!)k=KSZ&*PcF<x*HZ{>`z! zDxJ)Xk=g_4GE!V=e8_`>>}qd^2?(De;?47eXWz#+zKTZEN^;PyW8%F<Ge3xF%M3VZ z@Q}7O7H>Iu1cg!eZ0c>_bxW@*!0f^-(lDK4LJr1^YW2)<cJ%Uoe@5pOGkJ=pfFIx? z9sEMoOe5i=q{Q@zJ=03|4|!ui>Q8yaAk%hY85mY~4Tb+rwH?=+l@ImV^+Z5AVj4;g z??x5-aj#SNjPq}wFEC2UV}AMF;JbGJ+KKwu^!f?I4rrD`wcoI1JKCm-`;dMIY7^i* z##49g>eUb0R^Z31mhCQ!N#@#&2SQ?xR7c)E#=3EN|Iuw<M%-v7)LM0Q@R{J|k^V=i zkH&D2VD;DwC^ypz3u8)pFtXLH3|nVCPS#lWtqylV4i<xh%syrj`@DXakJxbHUPzx? zs`YRB`HY&2mVg~;g7MBQ>9{n~W>g+!LcV+n!V^Uu4^58b(8eevSpFGXnWL@dT_+;z za86%i{OEYSizVAGVrNy2^JTYqB9>(jfz0VXKk`IiMuhHnL@y1CrzGOsXFy4t&s<?{ z<?<CyyBfd``X8F0qKC<j5Rbm}6_8C#Gcje%9Uy`(2*b$LftTbv&}#9|HnrVBX$z0R z(Vh@WJ(EC9pC<_w1XE)yxR)BX+H`8V-Ui1F5uRS{^Zn3*FGtmy@<sheENHrD`Asks z4WB!Ol`<$s6kZ2LZzXWER%lT6-<#C!UHl4a9yyA0^~NTkI3^2e`NVNK0oAoINg1MN z6%&G?0Y)=0u;Xt<+<PHby96{E)_~rw0Sc3Hi*Q4jG3iu@V=&i$B$i4|b{vKUN_<k$ z3xDN}wVLA}4F?^6P#F>kAUYQv%;{hTTg_}`O(<~?+BkC>%^y4GR#F>1NKe7}6vpRt zUtOt#O`lyM-yroQt0N%~cEM)qg$zc-+59E=2DSROPwR!l044ib`7@d1{N%A`rI#(6 z62Frhlgour1<$1)UIj8qZNJpG-$AL+dy$jq=RE^j-rPesnB5`b3fF-8{Iu5=2YhoL zX)9|cfrD`B-`$S+Rk~LN{#BVjyyZeu=*Vh!-t%k~Nvc!;vj>=RofV9_Y^P9gE=<;` zT|s;qoZ!#v$l{r=s(mJtY=DG@B9<bT49q05ky=+N!Cy*avtgU=hWWm3TwQyWR?NzX z6*soFCJP7BXDanQEk^IT+Q)abpNd>N?kbg7e<<@_VS{HRimx9M3?qAmowJRdeFn8K zA@7jgmn%spI_~kiQMv^Sfr*-RJ0B{$y<_mqtgU{=Be%$xhoVeow%tp&jsNVEZuqUh zGLc7dWo86kR0n=!!hc(4eS@Ce9p+ihq|*Zet2;MJ{|rXoX?}^d(`UA_<-Db+d})*a zAr+_rQlV<9YH{c{si6K8AQcw=|D=K?Yid%R7Fgp8G?Kfb(1%QbJbWmo{z)}fG|&Ix z#{ETwCPyRG=`TW|)Bg&Pr3XW!=_Rr)<lu<*)IJu4g>jTgi!bv+as|0Lg}F7=?!8&g zS@Nd=+3&gBxGA<Z(tj9KvAQA-t*VLG@9$FrFE+FaIiKy!m%90J88D6KUTuzNK!!m{ zOL+c2h=S8=VC6Z?faE7`E{iWbz@jw^{&(`=g<KnTL8_~j)uyKRU#I~7`5DDg@oS7K z7S7Nh(iI)Y3FewBw{p&Gz4njM3JF*VFf(EcKk=Msv*VS~Gn+nVYCk?j*K*<MH8&6% zBJc>q@-}NTL&}1*?`$sPP*=T2p7W=Avh|L%zG>~gj)WGpD1sK^GFs{F=1|CCNCw}L za#|EkaMdCYWDEEbhvxK2SDDQ8I=pC8cOQo?zbcp{;c>_9B1da@0l_aI*Ez5iRo#>w zS<&uI1{~PjS+~OB^qL*5X?25RBXqw_JgGCk_J(S|3odn<%!RayVic{72>er(wpIlK z$qU*^sok$AD;L`6dNqQS(jGqQJg2hoPr|^B8M+$Q(zDU=i!kWq{+lo`-Bhnfov$H1 zCi6Wj88v@$&s!O$sxmoV8~mu2OYj9Ak%6^hH5R5H2l9J^L))XQxr(#3=U4i(5Ar35 z6sB4^lfjr;wqrWqXljIbz@RaVYVzCT#h74D?Ie$*ip;Un7L4aq_z4X)If0B2M?XH( z!{?4K4{r+0968P(v7$PeHbg!OqM#<eDA*ifOED3CWwCUxsti8QVtuP5dIZIXQ%ow$ zl`QK#@ecY_kShRFc-U%~PY#nAjHKi5f0I}CdsVzV$JqsdZVa++xWt9nSB)8h9+QXY z*d*A%%fRMmKroBGLo`*@kYXNBI^QWVv=sZyyFJn%BW{o!)aN~O5d51paL|--#R}*0 zPqu_vvdB~}cty>G$qLc@PtrgV)Fm4I7<giQG(mJcBIJ@^nev2UR_^Xs_>@8Yc~3)# z?^1_Z;dVqE2RC1{_NsGu%J)o|i-r{O_T~wt!QiIeLN<%XK_`P`NJ=0t_5hLRmZ^Vy zt+CyxvH$2(wLpo=pQT<0l))s}cV?x=;+k<)4|c09t96>5_8l+hb%XMBnk<AkU*1;* z1b`2=>Dr<7GL;yuD`B)FAfJzcK{0h@G438bv#fdbHPrP_PKCg}cMxS#mug<!rsp|p zD))9v6h*}}CK!^}+))#W8vocRv01tb->is9v;X9(z3Dt1{FNbLJQ;ss%GY&EGY%LH zl@)(x-gEiXsG4^;%s@lB*9j<i=2pt-LwTR&iwK{+qBM8==2J$-vS7L4sThiz@g_v4 z#yc}YG&Yw{5ykG;O}TgN|2(elv$gw(a8vQE6mTXKo#8Vb+h4!kbUFz^u*r&!(Xswd zO5}IGZ(6Z+Qyj#hn&yA~$Cj*`$2BG%SM@pE)qp&oGt5F8J{NcBQ0{3W3u81}H3KUV zvAOb7_5u7F60i2KS7tqee4lS3S)>!WR%Ewx+^47|(<q7|3ilwD3iV<q4tY}8y&KNs zL0NcA^?swoPRb<3h9MQ9mi-a&(sE8is|%($q#pTd`mIG)#>2)0_irCeU3UWp7FFvU ztB(S1Jsj9rSz!G9%#{s0Rhz<?BrVpJH|q5CCnRKh6_)p~PvR3@{a|sPVspR!r$42I zcqS<fVsn5IhLSsK-tA=BZakW<FD;Fl@n8QkFT>&F=b)`G`Nm}WKO%tMqq=rO{nC%3 zX1k^;O%|obR+Cv#Q8thh!=Mci*hr-#%l(6mW!HS`uJfm&CmM_lpSt_6CTQJmL*G)C z{TpQnGx&uvNJ~)vl&@YnPRps%Hn9Ad?<$BK9IE*6B=g&im>Iid2FOk2^)}j#Ou3!{ zR)riK7thZ5F`b442IquSp2^_r`}{oVSb6dDU8dfHIu$U&o2do0@{mBzk^5y^a1*@` zpaGr+4xQ>yj9?c?=l#o>QOO)R4BP^Y1bQkd(4q$)&Ne%_5~3_h8~Ya}UAQ}Q6vWE) z9Qn@|NJ&@PQoyHoW1Y=8#zPU{EUS-y#2{-`7aRmn&moIlJLS<%6@{Mc+n-Mnvg%Z# z=h+PCA$Np7%>ShzRJvyzAVy)ShR0PMyWcjxbP5^fhzYexQLcdFy8GMHPSQ&Z&yBd9 z3i7W;&!(ufYyp+w0NwgKE4bOY4UD5dKWX(lFdP5qIbh1}hpAi<d2{ry^zdI2B0}y% zu0ef=XSu5&|2WNjvcg;-=U{&U>(}O4+o5*(f#$pLk7Io5Y=f!e_Yb{L<W2Wj8tm&3 zcPBssS>ZF68Cwb$)Kb8ET91Dc5w}N}M22I>))3Zjx^Aba?XDbu4?Twx_E@}a?jnrd zKC572vBF{6<;Dts^M{CF&R%}=IyECY6*9gi+wp|$vSv?E((OT+E&}zRNsDmvSb$f{ zp+n*&rtRI;jGyq(ut9W^%Db+9gn54~y&d(c_uF$^c{88%)BNbr^6-l@uLVmRc+FF~ zKms%cM)85qR8Pxy;|+|SeEZ>>DMl7ha?6or15W*D-FWUT{fk2n3#~AT4gXO|<N@Ll zg9ln)tnOk(zBBO6(N{H})B@FtQGZ#7FBF1ShTkEFe(4z_P&J5F+b=;w7vud)(3r%b z&3V&$wpP-TakEtt5?1rOsQn^*esSKAEpcimD>7mM{xw`M7UKtpp>xr2iTBmjF3pvt z5PC4a$pl%}#NMX5g|4*4q<~s}uxwgT{tZ;<o$xPb^<`bH27n68`HiNa=WH7;M9hGb zDeNKs&n`Tk4VWR?#x3l8k3ek7n?rG{?;jax*$+%fPtc#5mYH+h*^UslZJ4tARt=K4 zmHF3U=#JH6bn+^T(IMiHHst3k#{%XvS(ZwWD6tzVdr3ehA~NqdHWRtIT$+~A&x~<r z^3KOg{ja#iTSNw<Cyrw0Vm6~`)QW*da^|kcDLlYqQJJ-aUcf4|^TS2yrWV766ZBNb z<BCDxbd>jxYGd>vf`X&9udYW;_J&{$YQlM7Pa-zqEaa4e7Z!YGVXG(Tru{w+y|ns@ z#h72TMIZ7By!o7O#QDC_F`;y^1FWX^Y}IE#x)Y|!c{!7-#gB(b<jNrygd<!C7%zkU z|L_)NO8jFSg-Rw)wT|oP)CP~ZAKyTT2V<b(3l8bp2`l^5FZx35D}!k&5b;_=KSWH$ z!P@GVDmM{b{STJm^xl7g7vV4N))=x4W_bg6%`fDlb?5r0-pkBWx)=5MEz?zq-zzBV zj~{<S!;!d+^VYF#_v(-eEp(z42{GefhB46gTH!aJI*~Sw74ai*e_KQ7;egTO-NY6X zr?b<jCy@fFjTxHfWt^~38kuO!<ktcrJVdT;3sZAt0bniAU;DO>CEy=4xSrC=6D3kw zE%9I6`Jl%deddIa;d+@+SU}Mo->X)o9JyUVNkVLB=>%mLJj78N+ZC+Wq}UM{nz`&# zVR&rxCue)}7co5rR@EkPC$W@nhxKEMAs3PL8mTk=G8}Dv=^$OvZXz^6fzBXPx2=fD zfll-x0GZ5~o-h3bMXe7w?jUYAjth0SgThVkwtuCH*Sdqpq+d^8k{Jx68|>J)TebT9 zTiIAN#WMScJ!d9S7f@I6NuxV!Y~G1{MB@lPzv<}k$3@%ub}7|r2zV<nQGQe##i(V! z@qjp<K7kR+td~L6a#bCQuDyt^_pUy=-8m({Hj+X=jI0^lGN>P&=|-P&!!Ggo2~Y$u z;%@^$McO|=1;q&)v+Yly;^5fY0sRxG;5Ms}=#)xK8As<88Ln8q*Dp8o?Y}ML&?5Pk zG}^ipjT3kF!#TPAQ5D2EiRtk$?+JKsAQh!*F^F+KS$~uxddPt76%bWgo}$mS;xJ{r z;-I_=*?=~<ob?)<dWy~aD)DA|!l%PWSg-+=9e5a6PX^vRKM+h<aQ$EHpwFbn-+y8! zV_78OrtrqE&Z`%lnf1hc1SdD%MK9+wh`P|p<yAT-k5)u6N>4>YN+2S*S0j}lpE=un zl&cq+?33zEC3d#d74Q`Gs$Blkv)yWI-~2?px<HfJp6O$*4CGCJhNTHWSL6usJk=Ri z(s$VD=d#N80YB}a?Bm=mX%Z=0?LoPJGLgozP)p_TjnhE66Hk{4?Vm=EJkLu;4C+)l zv_vOSOWh0@$dH7G#pnIm<lKLbg8(e!C*Gnr-R#ixHMkPa!#;*thFUmKi3|^UsX7n| zi+vIxm@jHZH2v}vYSeAZ;&xxn`=F4OxDjSplMs7|Fee4-JfoNH;32xYP2hMQaqG`J z-QAm}hnLZz=1#O#Rq`n@BQL#A1pie~+8v^B5OG|&+D#O*R09m@J`~S35c_Ii{2ur? z%y&;>S@MFkJpm$)hivSCt>@wT3EZ-0CoX<Fw}U7c15TCtVc$Cm$<E!bSuu#q5Fr-g zsN+GSc0|+JeXmy0>#ah6GLCcPSadY5Jf66LVzE!M`eMQ;>#GM04TnXzJ-(byZ@{q( zX8_+MB4;>QNAGUDZh{>aRe+1|NzW{;3MM~=$m-Reg>HGZaLV-zRlh%=RLM{x)Vd*C z&W}XURQ_QlI9UOV5A#b&i5;J2T8&w+fzeFb18Z&W$$ClW>iCV-AV5{8T(o$S-T%Od zTQCxKcx&k;q1ONG?iLTQFrT~$U1AN*r^EgM=q^301hjV%;>NPIfyuL(SoNshZ|eQ< zca%1cZ{MZJOG~OrOEEQZ2L0Gjb-S?!^QNUJdYXJso##ow;O)q3xh^`DJ~wy_+a|Yd zof&25vFM$&xj0CtAC13S5zXn2X$di1rAfnj8J^)-t1ltb5}L2F2v;#(b64qz;TqGt z@;i#e8v^4xKq!1Z3p9?!_tKsf6{o!TwiH^FaX^U=lPc`XPGt!H-i}y`$cA(2ODkTE zA#Zf({`Q<5pQc6JfY-n#ON>JML9HOQnI}&ZH_G#&Kd<t)T9du^FA&2Ci1J(TMt`Y6 zrhqe^ZuzR8f(M=l6y0c(xbcwpG>I;H6;A$&K2(uqK&s+YN{h(q^t$oF=%+nVRWJe+ z0A?4;^)U`v0B^t>_4Rhby3hYaE=W&E{va17O?efmrR*g#f|r2W$E6b5LEil3z^4~> zICo^-q})UYg*fP4C|PMPx^p`@gGuDRC-VJ%eG-8i>i{tbV}m-@&Qz4X`K);5?5|a> zUSBU&Qsn;r<{;B}>%(~J+VU4(vE|O^E1vScP=P+>qA3#srG2+DLcLcK^SHiqg<|1D zOKFS2EbjnBgn6}y6ToSxCFfeQ(@3<UWe%=Xpba+jEb+C8Lhm)G&{$C&4;jAa%L`0- zp{`+vqJ?==skCk*sauU^YX;f&J@1yKT0mH$I7Zry3cc_Qx@|%}Mp_=S9kSG-H!C-* zJ=@ZKy4G5qqw*$|S}8LQD_VychJ>iJfLoH%F>Ecd#`(IxSO2fd`hNMPP?bM+k^Cos zUBv1iyGXF#|KaSt<Ej4p_+cZXtcvXMMWrE;a5y-MsH{+tE#rt|?|F#G4%y=<Mamw> z=H%GxSmD_FkYn$4+#i*`*M0r2$9+HUyT8TfoX>l_p0DS4b#7DIN|0qdU^6^pd)xNX zY|ek{Bv96eo?zQERx_htk~gZ}E!~>%e%vQ~KRo<HV=>Fj&3Ibfj&DAgnd_<RL^Sy! zPSY!-(by0+MDOc4;kapbqrNKA5tOt^oU$*UFV*$E6{4}XRXY@~LX8VqR?n?ov?Z&} zpukR6`Kfh9suD>1b?M%dpnaEoQ{|60uK)6k#2Cx>y)T%%n>ja=mgwS}<SL%T;ah|~ z3n#+4U9L^M?V~7u^Uv9@Rdk{c(eE`v`KyP$xyBCMYAz3UqmktlUGI-_^?Zg0&x4~m znzvI!d@foW`>JjJ=*KZ-!*gGObu@@#)yJG4RySs#q@MQXW{1mqNh}$mLN=2rh{Q-V zds?lDHm7Ih?LC5X^82?#i=fwRFIHLv3j3RjI&D6jo>zm}Bg;v4N3&QO+-l^?y>3`$ zFY!K==32xYVQI#EILgHeXj~Z|n0s#9&#hiw6{p!oS2g(ttXH#Zo%O79vz{q7vUxx% znMe=nEZgBr_JDVmRT8&bgtsszH&TzS2pwum0o|GK7mZoks!lvmorrN)hs?Q)6Lg|# z5yGh(l;<|2!V)3aZ}>bwn8|YSse?G*T*Y#K@>p!uzQkd-yU#e0%No@mg~?ly<kUFx z4V&Kp*XEZEVh9pfK;vYIyosO=g+?#^5nm8f`BE_lb-fd(6U$%OWcfLgp=9jpA4z#Y z6qZ7D*985Ox}vx9P>A-HZwd%c`t*CX`E5XAxjonIF281%JbX9NmJaO;7czJ`uxhFI zJ<;+-uMaR{bV6amZbA?Zfj3(Jq%9sly8du{X5-NeLT~@hgFXH9>XF%BCJ+$d0Xd{U z@qkQ^99(~;ObS~~?YKJgZTH$TG3T8b$z2)pHL(lRuTuHeRO$LlH|U?Vi*5-{^-&vj z%==#-?{6#j$!q=asPptw|A_KT8mk*wUkWXHR5LF4r*Dz2$4-N98wpC9H&iGn*_A^! zOWz;e7t~Q5Annh1G=?w@8RV*@y|ihnq*q2fI9%>?;{N#YQZ|)2@H@&={y@N(bb|?X zaY8eA3im~}gD}Rwk1GMSP`PQ`CgB6L^cv(Ex)>d6^lms9gpV$nMjWF*%?@DKtpYy+ z9htGW0;3h*ZQOz;Yj)=Y4#UtJp0vVyIzIO|Fib>{)z72f8r4r%_vmk-;&>-0Y36{2 z{{CANKvr^5UP1}l+_>D=DW>*H8mRIj*Y`x+=R_M@QhXfdZ`sTe_Cp)uTbJZA=VZuv zB`xtmvMz~BZ<K^nQN80YRo1OwJ!4=es~X^`15}WWak>F{mD7kEa78>^TXn$(Wn48& z+-{XibFAALAA%cv?M*FPWZ42)X>WUxdF+>3`#wZ+h?ut@=)HWbO0qw$R{E)hqB~%w z(%^v;%Fp85=xip<`3iOZ97z2pzjTakrNW(8S*kg&$dHu)j<1<uAWoJGEx<?=K?1!) z<i^m;ceRJjW%7>g?Jnp4qrviK=~5_8Z~W|Oe+6v+M^BOX<3vw^gxbu5uK)u@<qX{U zlUyr%5^Pe3#y!X^myJ8Db%&SF29NWmBzV@t0>@w%y`!$P3lCC_hNxXCnMA}9HElfd zZir#r$s;?~ji|j-7GHidZ<Vt)qgl#FednRH{~O)C?%DH%ms1|(a^v-~%QnOUlgF;3 zm{%@N$nf?XSvGzA&^#x(j`Id5_793iBn&kkBiR|Z%|HG%?v$}Hi~6O!v~SbVMOJ-G zoHcETY(jtKe;gNoMe%X3TIY3>{Q&;YuLWA_DzEyVxBIe=N%vV|COH(E-7v8jynE<i zZ1#_59qlAK%fV(k-i*ibu2tF9(Wh4p59Nic;%{;j>O<dPbxAO?Ku3fQ4GdJh)o#qS z1-cqsrfbyaS?9#OGBYFgk*VZpgBf|I_My(f9R$X$WC4+rfd4*DDcN9pF7U@|xb=4` zspU^fbhfc_?902jz-yDGVk+3gUzQM>jBNZOd&QaE+i3L>oMc3;G-#-+&dwqLBw_$2 zv)Q<Ue@hfT1r`t58S8mBc>1}oM*sTUchGDzvDH%`K*{HXnGBb>@WS;`AIUBMX6|PM zx687e!C42=MvV<M0q}4{Epehc__guf2<dvQ2-*U^zW3jnFZE{C5G&ce2AOp!8Zf_a zKfi>~?9v{OX!T%k(E$Z*|Cl{D;nFYJxMZn4UZav;vIJ=Na}uW4GK$Vm)&L)~c4j?9 z$9|RW%iG(Z0x=)qWAV3Ufu=_xS!pzL-rAWf8`n6!1h+yg+py9tZOU_pqyNk+`apcd z9S?X@mR^oMa7dq1{b^Zb_Rs=&%^gq168HMQ2aT4!QJpiX3H<X}xnaN7x#E-y$14~s zpr9%I=a~I^G>2@8`cv)al>aTaXvo11<M(lZ{JWyq6oh{2tO04<?(1&xbE~v#U!4C~ zX<JNH7g7{+JQ8w&KCkD&I5i9nb~*wUg2u@A7RM=$A4oX)t+k_M%mKr~!XA$1OJwDf z50%BAhv7jqKZiF|#7G*~wTt%7H#%Hu4vX*WeyanPMo=)%ONClq(8q_ywjJU!4n+-! zQq}MQf2!Wy=3lbtn$euXMv*y_zIlXISc+R^Q3Sq<?-$J+Y;jyg+c9SL9z&xJScv!< z-MFP}HCu5iN`||ySy!(a*YhAh#R^JILs^GX*~Kp?tkt*0``KM14ZclzyE7I(Mr!_m z8#cP-39v85ySNfJrX+h+v@ReYdVfe)AbW7qK#&F+2=;c5;u!IK2=t00W&SO6#SRqX zAYR*lGv!Ih^TW?*TF(F^JQaurxma^a6lmyflP0v~DHX8&c@vSXya>%fov|33dsYRr zxj6`9t?9(Wq8vog`5inj_;&CKCs+P)2;w1l<RI&e(XX$Kdpvjr989$xlTT9ui75%u z^Sn8`fpHA7ic+leb^Pk*!)so|N6{c%dAW6*d11yCzuZ?waMOf7tLaSvSNqdzH6Luf z1CI8#1iusWg-&bWnzxIs1t8CeP;SHZ_#UU`!jYWQVyN13vyW}=o+JZ>IbISQ0=b{* z;E{XnkkxPF6z1~d-t11BDX;{>dDoMMfY9df)er&}(QO1b@DLXvO<}2d*{4Of#7t&) z3iS>h0tn^WY;44sdx_=b$1qnI?-_}k5)zgxzdoe+haL##`qy@$RRHBTHOTu}Gc|Hl znelV(P(HJ2OS3x=*S}lGreG_1gu91NSytGpc5z+%&XBpI9`6A{$LCafDLE~;Pv2wc z!xau=GlbLm^e5w?t7x~HNF5DK_{+fU3Z-hmM1j@o%_Qr93XmOK=xokZqjV9?{Sn5L zC`+?Axzbt9H3^=vzxdfsd_zfckQXC*RoGAc=nv!vJQM)r_cib#%N9!iplYPGv!~l| zCsbp;;`ZBYaq;=R_d;|tcQegoo^(_yc`dL=7oIY(EI=VYgW#~zoznpcx*y#`XyvXC zn$|o!NA>dP9$SeF6}SEU6Wa9}ihBTe!^R3rY}xznYq{U#(^8XA+3GaA5OdvO@VDJ7 zpWlAy?EnSxw2n1SHay49jU*n>mQbsI*K=iJV-?{@xKoh2q9W!XUA!KKmqyH0ZED<8 z?;FWbyIx9}s0tm+2JbP3XFI<@F#U{Yoq+Y;Jsi_>hE8wl&Lser4N)mKu;@jbg-<$n zXWnPCIA=zBC(;ZrsY3^UVfYBWUWr08^y<pD2PVo;=TBm1xlZjy{eUT;Xab=jV)yL0 zP=TFEA<49Kp?pXQ3^f@#lhQG81<g1g12lYN`tB>cJ?uD?{J~F?^+KCUWJA`X)$&8e z<xgg&sTSweHPpZ-5(PbvyhQ^gY62iQyClr+JzeijQj-URF73+=eEi7sR_WTyq)h<e zOCsOn-pKl%9oaV%RiPhRK!^SnTAe2g_=WGAL<WlAry0i{^+@~>Y0?`OOoY`4upnjf zatj4&?_&%A@LTpn{zR0~1_>DgthpfDt4u7X0JK1x_oP`v`$F`c2XC}+)gmK#p0WAL zt$&WG5#9{<-@-H!YPpZA+>3naGcH{4JZ<s3ERi_@&+LOA*=5-dJRJ-%jvbs}@)zF5 z?}2;di|Gs?C;q+t-~J%q!?hne$k@w2d@uhZYcCoygk_q&kh~O`jIX_$dd%bjNGoov zV}8Udp6kDa7q`*PoC74Szy9~f{^kTYVWx(BT+$z9HKd%A$mys*mg0~|z-ocJP{W6K z18+fn<;LxD(ZdaOgLAp(@0-x=;Vb~1fR7q#axe9fXSTQtMJ`!*^N!MK!-9bb;9HE= z%LOkvsy8Kl3@1$~P!I@w<M62rPwj{J_9bRV{zQtWZLGY88MbAqk@8WIff^F!R|38Q z&Wf)6@mCYP6E6&}*)nvEeR)N~PLfO-I^)b~%bXr#=_j9zk-=&IPZt5~UZiwAOZ^bJ zU9wr@KfWRdpZc}>(&v|3+GwEI6G21xiyE8LFPJ4t`1o-4=<VQhPh0&4v4Lm&oGi!~ zxScBZ0q%ar^RZt$$|CH>@kr19`wAx#QHp+%$44T13-+agj;3A~J<gJ&ISZ7<kIQ!T z20d9nc_8?RR7w4OWqoS^kPO2;k?pj-yDG6NmCwG*w@PaZ&PQnUG7l0nV~#e;sukBN z*{U6#S2!eRwGC;Zh4Eb0Q_TW23ymRe%_&79pTRz)$%&jOJro7%{)F&^BIEcum`!_= zfw7eTu)5_>;#>1$Hgi{`Czs%ql4R^jt2L+Jecv76yWg-;nAqN$xfNF{TsHNs?IvR? zM~PP?c#r>>o$BPEum}W-(b)87qf5#Y(l-p^guO)iw>bsR&d>H06VsmIoLaE%;BOtv zeUu?G=mN}AI#{Uaou)P<&%YVAW>_)Hn<AScULEnmmQ;|2S)RBO(XChoxKc*(*A)2a zD8|Se^K}L@MDigVTWpQRI3ir(fy9L+p8+2xKqvAJ;~<cqqSkdb#sC|b%_5uP{l=yf zyir5m^>C&6prmmxd9-slU_kOAlT>|~?#+o6lp?G^nrkq+v{uT+`H`!^Y4u@|ki3Tr z&I<^%Mj%+A(QuWBA$KP{<9yT*t3G8x<B67)q?TCNw?Ks!-P@OwNu&e*e83#YNVGz# z@x?;*!?$czAer2y)66Dc&y(ulmFma2Fbt(3S;N**CrGt>kyfdr{;jN(3f`WzPlX`| z0LX<~17-?i4U)l|#3&QOD<GfU3855y$ZQ*0l*xpaFzYrOUSl|NUFKgd#d!*|MNwSd zDb^|AbCVDj2%nVQ{pSZ{<-}0n+CWI&yWV+sM7-1p%cz^!C2cagHIS^1Sxvl9lQ=p* zHa@ikLuX$EHFVIA#hq?)?W-;Xx9@4xVtcsF=AD~B(cA)f2^6!GT*&*)s?b+ZnJ`~z zl#2=kSvN+-4#UGp@Kk^mtUg`F23l(c%CSnn+{^l1E9jfAUh<x9`(CIi+{sg$1T56D zN6gx%kH@Ec2Zf+ri#Z#16Z+bw=RGpJm@BgzzUipWfu-q7quq2S)F*V1N~LKz9GJwW zuvsddOsAE!^WGe;WM#o&9XqzGIbp9=@bjq+2dodNydH-dVN9AE%ldA2q74nDEotqx z*{Q194Se)bb3X;DDmW_CA^#dAzL?t2BUC$VPhR669RU&G7=68FJ;4R@9PMyXNds!w zhAXg(W4-gCIhdGr)+>%N8E_=dfg;~OsA)7R)PdaUXB_H|=u`Ojd){OOGD%Fywzl2j z5{uCqx5jNVz<5jEZd*gO8yvDzp4FUGlyyMGI^lJ_IENTvq8zYe-5rbeeq4J*e95u0 z55E||Fmc<qQ&=1aBDhh~>@hb6`P&I04w=1!L`lU1Tkx;oL7JW+2#+<zQ<7Qj;Y=q4 z1G$1$CWuS@(Swkzi^&%(?WxHVb1}>?lOAn6e_AG-B_P(~s%=JSyr#dX*2u&a)#c_4 zh(zz-=sk-PK3pYsNu|XvWpfU)gHm@0(&-PD@6d{5=%<qKzvL@Y)SxA>_}x>PehL-B zqLtcJBJ|=Z?xYZo#U9T|0}K~77!Z6Yk5Yre$KOlgJV1yHZe!8u@_u7}(`JX^w8RW< z5nPWp#;i4PYgQi}61&=D{JQZ}W)}&u#~~n#h{>zR$(%sD(EmIS%MZdH1Qmf_FJTKn zn2yzL%ctfmrU7OY?@^cd;^e#5br{NV&+MD}4@pNP$0)bN!?ty=+Az*;Tu&Z8<9vPR zjOb=cPtxms1BO21c&btV=SZ<DMNN<aD1|-C(duWEm~QY|aQlddROjAB+Jkd(a)-fT z^9K&B3U+f;@z<t$LhMGyi*D`7BlE=8Xex=55)dy1w+yd-+zt9tuxx#aNuVlxk}YiT zA|xPXrZk`1bBWsew49K8-jV`Ob-5p)V|4JJ^8TkM%>H?aM1V3__`~EMN?NNuXebmv zLO;Gqr&-o;|LxER09-%(feobHFn1q%qtgC55J<Ezt&%g~L+x=xrK>HaE2H{Rwn!6T z7Q`AL_&3uyt_P>2uofEi`YLzZbeD7z=em%HIh(QuG(k$uUT@-(qd4j#%i-21n*Ic% zp6C!x=>|n=hr^9CDlnbt_uK7Fu70L@8dSgtnc={w5q-S^(}&D&bsP%w=G3K8I4sZD zJEWVJbaVuWYxv=x{2l*m)F-b@s&mxZ)o!^vx;DqIsI|T5+yI24eD=!cZ$WT<;-~rD z?XqO0rZtaUgcInCdrgJtZiR~>OtUoCRC$F09K!oC&$h)2;29ISl<Zheb!nZq3?%D_ z#iAo8!Brl?2wyr*o^`P?BarMI3xgS<ND6T;8Iy@`4VTpjaMGnvN>B9~JUbQt{rl}R z&O0fEXX5~{B6jD^1^Odw^hiJmHNlUhU-|PqYWA>(eA(o3iBpVAIc)qn%SegHuH03d zk#-dB)~irRS|n#PdsI*jK*UQdVSAao4<*S8LsGi!ZuTnf3pY!w-s50<;UHlAg|D}? zvN+uaQOA^FM_zhb$MAfc>4NMym6A5y9-B_hvlz*~vypv&3llCT8s=d4;>A0-3V)P1 zQqz<V=*ZWXv^s>Qgm_I2toTbkc6(NKP5;77DVlN<bBX=3ROmLeh+ZO}U+P%b%lWG> z(&e!<)#Mc*j}tHNcEI7{{#FZaD|$@$NnC8}Zu%X<mVxXOP0L(*95W<nt_>VX*ccM$ z>l=a7y)?|NK^(2LOIdd@oFmUjN)3y4WS_R8-EQN+B1}T0GrwH|3uM`_ju#yyV<yk# z6{p7r)<-Kl$nOs7x#qTA4Xt$zVj2q18DJA8_7E-A1SERoUS(jMb02;>;e{6&Zeq+( zV~p^W+|j?m`tB?fhn@ou_#0w^qV(8}35b~NJFzbPx-j27SU%j~Q>fHo--FrAy?C>L z__m*D=~xfY>##u_Y!_N9p+D=oV5$<9so<V~(Y{T!kS<?GK4)69-!RGB^pF02KzeZR zism+pITp%YN4bSL=oJtM0lXBpDK#x9y3hzvO3i?CTR$R2T~-`vQnM*(CS6RI7&{JG zX<DA*qTh#t%ck#4P`VFk0&JZnxg}nv!Ri2a7PXW-ER#7WIM&DiSUZXM5WI8ts%Ez8 zZ7JV~#j{8YmkcR#WsjybnWz(<Jp<`bdM0-!AJOY-)7C$AB>vf6-jmv;PN-dc7>G1r zt5Pgu{@CH0+!J_6j(#bIPo(3qtPl#G5f-qUpMw}QInm_-?&CjKDg$Hr2F6sOOo!wc zmi+7;0o#uO3<mbc?ZS7E80;zr`P!Lmg*~$ryNxo!vbK3zwGgB&O52NsNowKpKs18N zKKV1D2$QI|$d_s2Pvm-v&s*LBj!QAatAepN>@N>nBQk$Tj$9vY65qUg;5`mKtP{*# zEKP}yvIDA)jH>Dgjy7IwoJXt?@}AVe*<;Zc?-I@McV5HOJErcA?7g>@R=8YVt--7$ z^cG5!#<_E>+~xb7l^45xNNF54{@F@8u<iB`j4WAZk?>X+@rZrTBvn7+ei>I&>6~t> zM{T$%+HIv0$Y_gKWF)X%6Ll7Ssk3!$TTK;r%Rmuxe36Og&^NaXoD@4OtTlb3bI<7U zoC`~@UG4>Ssb=xTE6`5ftf>gm`=V2Q#UC=flXpa7cbvHBAps68_fIS6H*&z5Y6>hL z=5&ECSkDpW)5!o~+iKWjMc5fhidS==fT+1`aYX{QxW0{j80Ik{!%f|!nD>~Y)u8-_ zkz>HI{e>1zwRm4vZ)y>xXE4Wynd8NH)_L(l%ze2hvk1&fvBL7|N5gwAywQ_N1|5<C zf+x`e#d@={lB4WD-3@J~zlv-_=(hFdZ?)q5E(%z?vS+#o#%(M%&Eb}75<5{@eRC^! z=F8aQG5U+QG}^S)KE+9FBy_6497?|T<DYS2%3iq)**GYpygZqfRA1?;pz%g7H|E6~ z{}JBRtCBqn!`V2#wAr5N6NkjJ(s)^P?U>Tor$_Q!R4d98dMZ40@Tk#c?R-P!X^lq0 z>q6K|mmRg*0W+2*l|%N;x%Z)&N9FCM&W3=8K_qB)v*)8<%PLL5(FQwut)g*otcb^R z3-v6^tDBG(DtD7^=*%3X$p*1)SS%Un56KjL0IkqBEZKa%8gTvt&<KxJG8QdWX=k*y zFuAj9S)o2=eGl?V1Cd!gy)gI0N<%a2o6xbit@QRA5@DXYYxbQMb(kDK#x~35;-9z7 zgD@YNxmvF<uziaCk-k4Rl%VPnAe?8(;6HkBwW=a;bYTWEQ6ia*Y5LL4{Ha<PAFJ{> z0E}BctVRjLw5{VLaE$lH<Dk-Z7X1ChqBFDYF1)KD^na@HNKN1#!Yxl*SB`4W{aOld z77-dcso(l}HwUMm9<%pfv7(KPnZt3uSjX6!th1w;fvAiO_U&xNGM;N?yooZ$$;(rI zBDqpp3rQU*3Hvw;(p$&;a@U>_UifU6k!}DLK)I-fd%<TnlIe8e@10Yik$>Y23do~{ zk9DOTGJ{Kjf3>5afzgqaZiSp)szHdy(?Y8>^ikpTN7);N7KkDoVszPbfSGRzE^l$I z7^}g-1t-Wq*x$p5_(O(~<#YbwCQOd+d>MJp?BNc(;*41RWT*1}LhWJzEsK`w$=A+W zKZ;<Cg^R8uygYcPh3f`x6-St;LUx*0X<isPGI=D1MbANaoeJtc-K47nwK<eiQgGh? zq^+Xt(U}T&X5z?Z)gsq^D>H-GK$EM)H@feo2A!^=A8)I6adqP_+eW`WpL?puF3TOb zk4yaFbVB(n9pk&JkQAaZg)N2eOhTV^{<9!*i((%qNWrO0Gm0_F{In3ZG(m&oxzlyu zpZD+Se?MCkXdcZWM$2#(!}wvfN5GAkwb#4ulgO!N)x8is$yUfCsfT@5bJOz<R{7O- zsaO(mrx8b6TOAe2Glxxc?!KyR!&PyknB}3@_jrb-=OdzGeHrTjUzW&L`MkbPnp+L@ zB9})e+d!81X=(CB<QMUtYpe3z@)z+g@^B!)dpUBF?P3#z*IXGz$*p^#=gyLPI(*wE zNGGee8v`^$CwfiN-cZUD$`ku#=nNU+Hoo1|a#*I-rDBg<NjPl+p4h2@cnm2?fNkdj z*mgsZLe4yn6A%*!9SJ83%(IRb>ad9NM;+kaey9^ncJMr62RL@xOmdqu)O=*O<Zf67 z|FuR)kdpe0hNUlVbiL_6Rw3mg#*oPRru%HmE7MP$pI|q<T)N?dW}en%yF2AcE-@gH z5>@`{Ne3AUjS56LpiEKSG8CDHRKc6vo&WTUzMTewY0qY3`P{-z-)0@q#yJTrXxX`m zl)v|ZKZ#$?>|`hRXZGdL=K}=1+Rwa&$8nW!KJYARL?fpctd$kgp4GkCuAA%qXY@dl z*p-!;n*H47i7Nse$Z8*u?mO^{CWrXC_ze3VB_}qbXi=`qh^8gI;PKJ<&qW?96W0gs z0HFbgKhm})uZH7$-dR`02absAXjG7bP+1GaBV?XL{AZ*|YfRR1P}_~3ha&y5Ww%Pq zxcb|}vQN=~8uLl~T1Ync5x<-$z|TO%wSSDBcpTQ9#CtW3tyYMmee_k7*(Lz1LF#gU z`$zmzqKUSj7n3_x86p=f)k$PVRN2E!m!TuwBi@(Ldk{}1M%3$L^#0ocOLe^m(Li@) zxPAS)?MdF^R<^RGAzb38Sm-MZai{5y6VDKF9`S7w&3vkT?w{jJp|4fG9JWfEbTI$i zyy@vMmarq@Bk!&-mM7AQ!<&qWR?XdWpW|+vbq-eJJ#B0Wo&*dqVtvKge1+KVzm)^N z^hlHqO35%gx?uIL)8chhzsiDi;|DU-0gB=4kj6asqJ}gAXue?CU`*q6`q=0%ZqvfA zUqFiHlb7sLKMrujCk9;zbWa|fMJe_ne^KWD?;U}GbkF4`2dG`G6fOz-4i?sbWiq++ zrRuul#8dq>Z-RO27)LyE?QGs4LKxDJ0Gzj?{KKym>4yTdD+!4jKUwsJc|Mu7^(8i- zQsn=xDH87Sj8ef;Pw+G>YDG+mk~<1;LdK~lEK_H9xCScvsA5UHd{&aZmDp;SK!bzW zGlNX=sDIun_>OgY59@0W%L9F#*98|fNh?7c<?$OVZG@k@#U=;KYA8~C+HyngC`)J& zC{$rlEfn#nS~9%G<y=@nn|4*jmPyUDupKy|luUrE#<b0mDsgZv+igUvCf`YWhxXj$ zfUl;{x4}VAI*Re3YxDKt%P*?(e2cp>>zTKe$jw6)kESH4$>)mZ-nCntwyS2|{2zQZ zFoNr0wVT)~U4ROH4$RjDv1y;WD0+6KMgK+8zV7wB3y^x??%4KRCW;kYE7OUx>rA_T z6xEiMOH?!QPc6wYNh(glJqJYC4$a?vm&GIu5I3Y|pm8$KhK7TY`sogA-w_$jY7N6s zzmIC+RkTN`d7BaB^EkohT!o&+wv+6+RVENFA=!cbSkgbhlX_aNt}I^Fo4U4sK9P;b z^8ew%WdKNzl!COzkNaJVl{&MJ%lTppRoAnQS}Sfp3{$J>PY=B<ec4?4g5wF?7lo)2 zrA`LYm2Eg0+CaBZbEvhdogJ22_HlM!gtpch3@?Ba^b+k?G0fEVteFxaEu3aAo!#+u zlJ6Eak89QL>;M4()a+ErI7baJ((q|9Q_LP`XXdNs_zu_HEoMcQi4oB+8Ly%ev+y_Q z{%-0>g@3u}J#X}XBYZLeLt|UvadBTlx$uG0xKWRNPuW=rujfWVt}8c<?S?CFAMWlD zDLj)U6-7G<Fwu`1O=0uk&tha-wb#Bh2{Kij4YRa)Y!(5}#n8^&*`HMOwE@JTmlDc% z+><x1uy0=y2->~G*1dzf8$Q*}B&b&ZnQ6ML7RtLB1~agkVsj=Hy#Z-3{P|r;ZjHWn z?ooeoLYU28K;Qpc8&E!bOF&0otz*4#s(D)ITkQLcn<+HwM*%tH*(5hYt?X)Wy!93; zC2&II*CINOx$ezks`607+vDQpYnV3Ipc)mQ4cSgl_W@7mD>=TCuwK1-fhol9KnrAV zQX%&p2<7saLi9l`nP(?xelZ0Vrk4;fxrWI}_~%GG(}cp#1Q6X9ZtU5a#c$4h3{+ja zhz8b)Fa7Xu+5Na7cCl|x$`if);c}^_CXD4G`BZ;0yS{@`DC=q2ym#f-?llPz11$JI z?5K}*frdmR4OvRHOGCPm=4Vbl_Uo^1S`0l0#W<+%+*Y*w>KiBcVloLn*ll`G_OsYc zZaMz{1<-lq{yzcq7yZ8g`irJxL;1iYP`9rX%7E16PSj9EYo%_K%{S`hAy!YGXfbQE ziH+F1ja*$1=}c%_<i_v&TcvE{U+KPCb!#<Z0;f+u&xqTEzH^%JlMsE>;q&hA=ll~9 z_2@7+Jxp0cSNA#N4C06elS<<7{;QoZV;9y{k%S{V%Sco1hH3pa#+NDhe1nm{o~g=D zf3%jVl6Qh#EEs(^<Ffx-MIQiFhplgemp9KB5GG&*Ss>{4yU2R~+=r4qEG*7SMs+ym zMu|~ZvC=WD=q6dVNQ))VK@l^&#^-zuT%6e>>0zsRcI0)(7@gX6I$U+~N}p~$^*f!g z<teFapPBLtMW7;7uF)@8ZiRUmw7IN^vUM4{OqL5I2@XwN(KiPp^=;bE;ISk6rfl0R zo0H4Q!)iqlP_wN|$$lPw%5Dc5EL|5Ev%23KI3_2mXUhNOW!0KzhBq1K7{{0Qi|wB3 zbr8g#y&SN8EP2QK0VBnpNmspq;w@XLoMANkAfF_k+++nbp}N;MF82Z)z45g#GVZg= zAlzLpun0)BDpC9bA44D=Ucin={1-Qs$-NCd>lZewkvd2M{{7Eer6-7cPW=BP;s$K| z#D_Xd{|j;d109Y_-9z^|FUO){*tZ>6SFFnSCke^w;=IxU;O|Ux$yUdbku+mhbg8@N zWK<Spz5R^rSe!d3)+}<L|0UQNB!35<#a1Fk!nuPiV_U|&ar_HFtyaq;62O^v?nXTQ zW#0~2?>Ch^a);05DyH6wC-Ez$%uMxhbttw6RgFJu;o}9&SHO0ri9Z|qIhef#IgEQH zLg(^$$BtI2qh@@EMO`R#ao-B}$s`%Ly|3G>7&omy+@4J}jkkJ&@vei{Fn!8ksSKSM zS1$t5xJX|~#$0%0y~04QK|S??^h?vhfrW&imht7`R4!uamr;$zC~;lyZnK*cXS8<| zlJ}IRn)x<1-5KhRKm>l|x$&lq#mKvj(C&*K%<WgGj%gU!z-$FM?hFTCGB;xLKI7m) zR2K*`bR#K%Kb$4o?h@`$@XAJI=mKbfGK+I2c`Hg77x{EefsL5e&O*h-LSNKEKsD!Y z&Gpak1*5Y()Kk{Oa>8==fWnoXNz>xq?^k~4y;`(mY^S_bV|0gQ@~bHRy`Vug&)!#f z>IcSy?RFvE(##e2aGRm!g`b{`JWN2rQ#2R`v$pARCX6<lfO<8BBSMyy0SFC4J7WV~ zE5!S@P-BhHEb(wod}Wu;dkn>ub~q@!7aZTVw`IKH;9{T*op@@o;o@t9eI<#g?$^nP zE&2HHw$q$&O3L7zg<lT#n`Ek8?{e|@T%ymxuD}qYrz|-Di(Y=(<q&$$Y_-xgFaX;* zK3_kEZ^?4-78GIK?@L>0W1W%beQ^1snL(zRA;5BHiJVe8=lp*a15*`xzd*C&31~KY ziOp`kzbM>-Khk=x!Q3#l>KSUvJqGH6D7fMqTH+3=+TynRvIQG=4(Aav^-lmo6`+1} z?u21SB!qOzvLZ_-fco04l5C*7C<~)8wC3pW1sNJ;oAn1NUz~+7h(kptas64n`LF(e z0%el_1(aV6IMSB?4TSr1>X%s$Y&8V%=l*=TJ%56WXX3u4OMbO1noJY+fE?1gJ@^`w z(+xSOwsR+lM{aE$K;eAI%I1l4-ukn;UN20dix`T}m#D<R8PlYeQB{#kmbo48^<l44 zQM>a>`9&aFv6o_}6-su?uf-JG1@X9B0AS$Jg6X)9a|ROu^o@}PuRHNatKb=+MH6v^ zNln;&P~lbntW!JqQYXQ@nmv}D$G@3&9kci0Hu^4kV7<X9s5`$9`AgpfE7wUmk)vM^ zuLk(+aE<7ua0Rm!1uen`y8?J1=n#hr$+gXZ($x&^<$t|8kaLCd%@@7@4R#fz^YTlp zZjQem`h$4w*p1gvS_G`ld*GDdy>xG>$srVpdv?#;Ri#Xob^~+s{(drPukcj6xO?XC zke(5P{}v1i;^LMg`9C=EqNHfGoNzBNEJpXa1)+FEgPx(~0_chT9dCv9A3M5A$5n%w zCOCgB%MEia)e?o{jJQ(#4yMhM$w{YjH09fC_av#({2Nu{I+T$dz?5J$M96XpSt5}2 zce-Nz0WMtW$iYdyC`gm_AdZXLIuTG*OYTCM_gYdre$?IMiEw}W7Ef9Agtbu27Rgy8 z#dj#6L}H`dfw|wuvyN#or@@nkPDQ~_f1#W&VC^V}Z?{gPP}G2{zrU3;I;9-Yk$c>3 z`}&Zk5;U^u{&p23SZpgt;S_eJ6<T|DTgl0;t6uW4ZVK=_CH_k{o@7_d?ZQc$OzTJ? zs<LxqapPhp32*s}^ra4IXtaFxuNXc`S4QS@>|~CD7OX@mVSB|}dS7UE4CZy4hdN1V zNhQZ+j3*2y*wg214NegV<)rLiRQrpGT*utXQO(lfGjuT2OYbx2jj3>=N=wkt;4(i4 z^rn76+6t<r6o9KvCT2g!PNhWFNdl1AJ{>+BKGE0xA!h<eD>DulhVnn}IZYrAX9r;u z<l!ql?^50F!b`US>wXLn%13%Yx(M39rUrPPTNSc3?eau^_VlLGqHL$AIn(OH=QBz( zS}on=<};0%-p<{+eV$=O*^~4%hV(qS+YZK$egFKT?AYwdje373@)rp%@tXuU|KB9| z1T1*|E;F?fsWY+jG;Y|Jckry_`LaOe=Kj<K)Wz+ynM;V$smo9zG-zG!#<*4J>&~h- z5xz{mLdiXX+EYjKpT&q&COuP0mx=V#Q);f7OZRU`63r`GR?`n>@{t0WVM6_AGnWa8 z)>XA|6qh`c7ikyoDBEA{h}k=)W7zQA)YQ~iwTBK|8$!z=(YKGkF)t15&V=X{&0pZ} z7uBsc6Yg|}D>Z{eifnKQ=sJUniCht3HE69O4lrUkU(fB_K_HiNu+0Zusi1RW7q)%S zUp&F;!(+`EQ(lAIReW6$^82<wr{Khz&<O-sP~G?jFDRV2vHM#R!A+slgwynZ=<zf$ z3~h}bvjHcfQ!uh9I#kKMjaTPjtvM{JHZ;0qp3y&74~p9Mg~%fY*;@&?7x<&oP$urW zmTLHNZ>H+XShYepySP!^`&20pTGqSG`*!nPANn~p<toor*arijDiU`BX)gjfO>yc> zD*&V|3;Gw*!ZxepSQ-SBeY||n!j8Nc=9lm`==ao?!`E7hwI!Cm)8)rhFyVwr%Yt}I zKUF!gq!z%(5;fftM0d}P4S@`Sh&SQUb@pXQOt_cKt~t8ysHkPAubYV!v0AfD+&>jv z8&&FX9W4Pv0?G<>VSwbR%fO$KXNQ1wZsS!5PZqI^-TL5w>qI&r3B^DTcQedC7T)>p zKX~hf4j0m6fPA;EaUeO`Xyg|#nqE$oae%_TkQ8E5fxFbsQ;~7RH+^o$=dayt$aY$| zNB!QpWdve#PV(V6;npg#t+?MER%S9FD?%#fUa#=0I-uPZmQW`Y^rGuPV?xX@bB6;p z5IST_UzF35OvFERxpLL$?@GT1xY>6WdNcVJMk{w-lTl^UDaP^_Xn?Z0n!-6O1MRiA z@N)B!yb2W`*nx2ye-_b&ceO&nR+xw$XHK~SJU4*4A4q|t*P4?|By*Ojo%NeP?_U+f zVfO{&)HpMVJu-9a<37O0Vx%y=91VIT?8=iPEFfA?+^vx`HApH3=hYZ7((#B~fRcF$ zk)uIN+&O6x5V2uzytj$cjpU@>*^OEn7f|-C{?ddn1G{e&TWkDj?$xu(bRHIs4pwb+ zf`=L1TcWP?Bl=Sf;727cD`Wk*atE9?S2hVa1if##R4lCnpOXe=$(^Xh_fFK}{y_TG zF%g8sKs>AoL&9VmRBd+h3LK#4dRzu2ldoBzWxZ0zICsJH5qyFM`zK!Y3tVjbDvyRC z!vhuXsi<n|AUSNcZTki?V_V%obo?53*(Q1F<g9est8t-+_Y@9rvHaJZQa3hGZ<Gej z>vEWEdZ!VK4wvd8T>I7Tsmh$TDE|ReIL?rwoH&ndytp%7Yf*Kv=`4N5pg0@yHFEev z&f`jsp&R)gA8z8by9niFFt-OHZEeB45rNNQ1cYdBUsvu0Wk&to2yhcs8!mZUcIENP zcWsp0>nR%F2<0?_uXFlB2BVJX^WzhGAZkB5=hOo@d$ut-uFKQ9qc#S?%b9KivK&B} zu8Dt{+~Z3#XhVz;rrigW^B!-vF<ZNyNKukp9H|(PzV6xzLcpz+SE_wB@Qgi<r{<yi z0IRwJyoxJVfY(q<*k4S$=O^K^tgEJGR5?F2^>VRjD|7Uxq){CM*a2<*4teAN>~E?Q z`q?y3G8YSJ67FkhIlS`Xsc&$a6*l?(Yw;ruRkpZ7ht5Ku3ynV<yB~000zyVV>$_cW z5%7b`hp1=X^1r5Z0&g`)=*acY%n{@EI)j?WT?4TkNl?KL8K@63LV`4|em9S>_t=H! zKi~f3v-J)M9}At<VXBC9Kw3|lT$O~hJ|I`<hIlaYjGO@_-|EtEvwrmCykq+z&YhtR z*KG_T-gMg5#aw<z?}Jn^_3-8}SYtZFM!a~nO8FF}TT+W}V*uZK!s%|Ozp7NA2W)pE zFQi5GQGZ1L2Ve^gNet00=WjE8g*&^)Do_6gxx9|{F<!a3t4j~#+6|)O30Pj=>0R6t zHc0_3e$5`PHVf9wR*1*@-LmGJ=eW-W5CNE#ZGiqT94sZ54FM&ImQZxPzR+s9(KU3K zY<~3J8g{=XT%dx=bcJlP!S2xEf=*oJCjs3u@g#(S$-$Z^3^L|V(^6Dk{df<S=QN-D zv5btZj*Db@#wn+8!)qXT6|)uARLBV7dJu6`+&$n${A|O@GgP!vc+pte)^wNV@3~RF zj&ZKrXpZCs!YP0a=LDR~$PlEo%kl_zyB#?1O2U_crSRO#&aU9u2w+v!2C7haZcn|4 znQ7kyV#(+=>qh|AC)8dJncBMHF&yIu3`q9ZQ^ecY=Smh+hj?a|LESjkfpw<;JS(ds zC5B$>sW{+8<vy4E<hTl=j4vDn+!Vb0S2e1o$&)+f!UH5tj<DB_t~IGSR>c)ycb^0Z z8=Th%Vx+k!s@f@M9l}y_++6ZBmMXa0De{;0n8<yojddNoo-d=UG=VIHPdwhfDLtG# z0NX4byR}<R+!gt9kIh+^Yq@W8jx?Dpc>yopG9URLH&hrLsgno>mbbckPc*+)K1yXU z|I3#z`8w%KF%&r%KXRHvvXT@sJzZT`$UG3)Rls3KL%>>p+}6V5Dd&NA4TyyjddGl- zx@b6Z9>Vvfr5qk3fsAl>ELcLI?Zv-ZGOh(%pP^_f?u>#neq04y+P@TPPYe5<A#sgK z=C0jd$+D`#A-i6p%e2O@b!Qcerl1k=q?g;$@>*J3nnX|*GcYYFONbC9=yd{fw1zQa zfMWa8ZV7JVM*i!%ZNh43c+nTPW93_T7MujRm(uh?`uq=rmlW#}C_fpO#|yM~2TvGe zL8<M^;(FYZ$6_Sg6Uj?^RV0U<ffJoj7hEv7>js^1f=5p2mqj2<U#Djk(pC)hKs`b^ zO5<q%kQ$WSJOB@dL?f2I(15j!mq*I`1A+Qv_#S(aSx2Gf<>E`lNwr3buNEEd0Ysh+ ztX_<QWg4jH9jb0%dC^Xk!th7H3?uQH&KYKcxUH=YSo8Ui8e5i7=d)G`dub#*m$OOS z67ZwG`9gXEVwtx95Nm(7uD18aaPq>p0_2Xl!l=l(oGDT)=b_opCj+D&d<p$)Psb^U zrLG&_ek@h}ws2=MZO>EbXz^e;Pkqe$3_qO(Zp_cFH;>Iv30FP*3zaI3O1%NslC@&* z9Qn}GR1-HLE=qHW@w&VGTo%t7s0et}clFl77sZrBmcF^vzg?|5h0a3<gtQmll!A$0 zOVDxt$s#)Hiefe<*8%CxFCc)V#X?l#1sjH7ORxgr>!4%2<F&Y3kC22kgX;$xpHigW zOd)vJW50dMjc(Vyk}$mo^*9D$fDb&ZAT`=K=Sjl$!Ri>lt%g23?gLb*PQHHys6%!l zGGe7zptyeN{HwS=<$Zk{A7wn7p&s@}=wt#KfW01_GaZ>!N&aG+G-Z6z0@7y!c4<ZC zHYHg7igC9bGxV(&{6&W~M*?&DFn3bj9n8$Nvgtjf7b)~CjmLrLJ7&#7CzF3GeO@sj zda-Hy@#}uXNg3e>%EnMJ^5?q%wcD4nvNC@y5Bwob<-MVgG8<yL-(Zdcnr_Cbw;jI1 zX@5ouY)QZrEC*PQ@uGag+n^wL?$|iwN~t&~jkJ;EO=oPBWc8Py?{AbZ`P;}4Uc9Z4 ziGk}ciHF|m=y!HBo4)&5RXX_*>%Y(_vWS2K*4fF0bg~yUQgEFqmU+VF9EE5xSc|0N zd{=>S(-36ndKcq%`J3Tm_T(hB-j{yFmjXWJhHrl1-NS_U<t%Hdd^^U{uC30`zx`Gj z!t72_5F>)iZ!bFuj(>wmoI*qx$2YR*nmjqZ%e9nSfRjPAGOQemNj>?)9YrZWVWm>H zwek)7vtL->Emnm3CAZ+t5X4<aWjt&?iG_cT^`lUIJa_vM&oSQlYDCC1!s{%?x4K_M z0Ax<L+zF`5DoI%(tq>};iR|ly^8d=a<F*I`w5_T2$W~{?qROhYBkaEL6YvWD$vZ;% zS7Y%X7ly&S)j;Ez9puPrLWsJ&fl*OiFEkZ7fP(eWE4iddQ{oU8mN@Dy%(jWH*9nh4 zS(LH+uP>YCpEv?G+z0urX!Iv+2com-oDUgpVMC@MJHG<y_SfW&@r|Mf{WP0577Eoj zGG}WNCxVsGV(v3&NaY8XZUT19I2>;f(v|Gvl?w#BW};%+fvFotU+=%IlO>$C>;1K? zn(dB@lJ;Ob;+2RcU2~TRos&O?07@PpT;6aJ<&$d)MB#l`?(I(h^Z@v-w64m_eX;*h z;VXTNAFq4Pxfx-`b&joxp%aMl>wEQ|;64EOdRl4na|(yYU}BJAUp7E?1^&Er6w|`i zoaL$V6H&bm%7<dp<NVs~zczIS1NeC(?lR3WwE^0}M@;2eJ<??R_LFAg>)*~-*n?$W z(gU~9&%6K43VVqtzi<|?eZ8gYBVQsMeHF!x5=T9>#t{b!rJkn5`8UTW??bJtJ$9V8 z3U4Kk&Os}GV4rnuBg929fJy28)jt!sfH5oDPhXje0U~nR;!l~QB<8^E3Lv0<-fZcA z2GpNR|7>^3qX;_q-yAT|t?VVgJ=bmQOGB^!5ztOAxwXw{=y46wmeIMA#se(yq5-W> zweQ@*SmNn%J^9Y#7zVW*e1&mlFRt88OKF&F#f>yc|C+8f24v?u1g~EGJU`dyTjaCj z^GN14RF!Gjv*SYM#x)hy%$rDa(omvhvfPi3BG~hwOUxazR@2Is`M~pe093EE<Zr5% zq|$B`z{g%9d_ClO4+kKK<)jVA306ambO7I4Oq?}*JN+e(XpSV>m$#={<h0DH<K7{Z z+w&q#oC^*<j<(~z?#;^nelAYnxyCO|st(O@wx^jt{Nc&As%m&OC%YQQljc9HWys)F zvbFc7wTlx*Q%o*E_V~IU_>;b|#sufrSDMcUnkn5UUO0C0mP<9HPWr-bsK`lGthM>Z z4a#{D+49<6vFSJUl6MGA(=({E{5**WB(5bb633}kjmLfIP!;BUXfPoz9VVM1RSisO zi|`4d*H<|`4OSz$j$tsQt#ga!M8HWOfr0V|p*%Fh(b9b&+IMZU`gRYbG)*Fvod1k~ z;efSl#R!|vZD2@3`n6m-6NODEN?OJkNAi3&952P$;S&<DmLWp2o0?NsNo2W^9pbB+ zRYRv_?{Q)_uBQ0%+M{4?FtJ@(NzeKbSdYuR$#S&$Q4QL9X7g|ZK;QU6Ya+)_Xao6b z&oT`M##N!Eo$+L;VUjqa@ztL+Zbg5O&Wf2)2-93FFz`zGG^*~<f#uDHxuJm}{ZH&L zw*G+OXoHcV&4z@I6il=zuHp)hy+sm0viRhlfqbnyDQTD$zAt>>y7%<KvtGz>?g6dy zRVLEWsF5)il;?z^`^2T<+5X?`D+M`m&S1IMc{uxHC&^oEKzy6Z0f{vG@Z_*=Ywo%w z^>LMWguv9sN*(m(X{+*6$l<S+3<JY6Lb<<%qlB!ebEb36S<suhJvrohO$#jeLwlj^ z!kJ`JPayd2Xv^1|S~b;zd4SZn(gzwQWhb~HhUX7a@D22l^_=YKc7)QepAf8u-;i6A zq|1^iQB`O2x!&y26nE(eKD~VNByNwomc-gfwyc8%#phY&l`K_RwBdH$g){9L<*C}o z1h^4?y<p&}fI)3f`P1g4qQ5t!$3GE@94n*J?Dg>NFK!08X`I954OUk2c2N$}Go$ZL z-~6IJ;PM)rD=hJGT99OyZk3m!lr0`XDqynXbV8w0h`!X?9A7Bldy;9;NvBF8l@+%r zq&-6tyo1(4e1H=Y3I>}BtM_16ZK_({(2Chx&`zBho1HEh;9{54JEr1VQOk<ZJY9|t z-yS-|9y-`z*Mlu$<1S@tMynToy1OTNICF66k9}GV<&65KgmDcb*~S+G&RWCU$X)5i zuIbUiSBG{MJdW)0f<n{!0)tQr5TssoF3@*uP2QY_I&(<x%pv*V8Gf_v2GzcyB46UF zIA4aj^jBXOftU(CDB<jYLlqV1^?G@YM(_L4Zn`_B?m+Ok>lS>yzoLNa)DG?ckO@dw z-^D%6W5<V2_q`Wbi#Zd5m;3keB4u<kZq_QhxU>4D0eRdIIQr#HzTbY><tf^;nWl4) z0o;Ti^QXh>!!grc?~OPH3J&&ZhDL|Y^P#q@R4ks|vBA3{!8=K6d*`zgG35-?CS$G# zz?@U^LzSW<=F&WttjV20Wl({GYk8!urX2_|sdx9s;??qxe-Fstf{M%D0|kvhL=!M0 zM!Bd_r1M#$gfVH#Uxh`|ov%~Yx%H(Y9!aOU;q6kXkFyS#1%r6pqx-&zre!R*Qi)I} z#x5YNoK4Ld)CI<v5Z1}VPN)ymCaI4%U@BYIV*`@VqNLApq=+?viUV@~kBTdGZ>Xfo z_Au2xer^X2%!I0(g0F^N#uwy0!s@(UXf(pkpPrUHvcE^<*tmS-w=;PvKO};T>J$v% z9Y4)C$de_jW=XO2dwM)l7i6d3ygi-EkeO0uHqNBmw{qfEoiNGJI&74j31mi&+}--B zWB=ejxR*D-X>bLxL)s`b$`c7k`hf+EX&bpwH?x2Y{*}^b`i7C1Z&x~JW^#r{u3n>= z)|xOS*F~&=XZCSYKCwVl7IT)@g}}mB$~4xC^W-r8+h!elRrmh;nQysRS+S3%vu9qF z6LGK!;OP3RKfwAeAlM40cX)zdShBS}pZPuJ<F6?d=51|!=AU6lvsMMNAB)I)y{yF9 z6BWKYVDU>k8}{_CqNW|rmF)eKD&mvHdc?bE*$(HV_9Q(_lKR1^dt7x>Qxw+0On(rh z_n2%H2zF{(Z;JE`*s=fK6!iXwRrJWI!G`j}!_$dIC8DAvsZw<y73H_-NEc{7(diO6 znZq*4Kkh3U8gMOxwd8kzRB^DvAk*j_^AT@`+J0yCu5Q)?1O=OBL22pyE4r5t?LEVd ziJHITzb`k<LE)bQf>J1@5}7PGp9=bPVA}kK@>QV|jpabb6yF53sNQ&+_+7E>GC*oe zXZ3C-<Me!dEBO1pFFOCSe~RZ1u{336+4pf1#EZ!1J!_3lf;UeSu`!!LNSQy0*z(#9 zr`b&n_6P3-rdT%+I;_CMslZgM=PW;mXEcj{I}0f#XI1DQ4r1Td%cFmqPa#OY`%bEz zQ(I6qJtlG+FI~`)LVSd=-B`6e9cXg?(QhqA0vsr&xECqq`<sDDo&G=~u)vMh9sZxR z&R>g4IHLcR?49@iZ5E$Lkdlfer`TD%uLTwe(8O*5F}jAbunza>{=E%m5`WQv038Hs zBX88!ezHgh^eBMv={v#k5<NYX*wbyxeJ=3yC%?|kJ+;9vXoqXi^QZZJcDxS=LQWD{ z|FdfR{lgdMN55XfSv<lIU&y=4FD8Lrh62@}oZf#{u3o==;gJ(L7n`o1A%E5Pg#Iaz z83gFb?)L$*#?uSp?T_ETGD>3XtN!dmD6qCmuAwKwZv6e@1sA$F%FZ({z;MLXzBKES zf9XITp<l$fDf)o%+~1Ah#*qd<mw6(`0@_v8MPSqucfRN`tVK#M<#&xpnnML6cf1qs zF1pw?#~;GUCw)s+pc@q*;RNn*wY+L+N1Kx}W#t><Q|j~P<W^3jc4eO@zuU6A_ivBq z^8b*IC6T}>f_>wFLdWf}cVE(9zm(f)^99OM(!?f$D6^MT2bdL1RrQK}3)cUkKn5J{ zVD=Lf!8%<J&0o1_L%c((vpRnjHHtEy_$STnXAq4~ILwu^X{y7Q)TahTK&hbAPz)1n z6VJCF{G}0{0{^A`erJ`OW~`3IS_4dlcN6h|P{5RhA+_y|d~iMhW);iA$mEH4);6eQ z;D(lIlpx}=zMy>9b6WLFEKtmoiMxh2<Di{&hwDwR5GFr)eJ-K+C7?SWZAeJPJLjrW zTKf8OG*n^Kc&ZU1$(GiP_qe1&jS9}L0I?e8cuMxfFojd6#Qm9bdnYTx|JpSmTc_~> z^O-8y1&LI>E@iiDZZN`yXq%*yEJNtS6cE}r7-&sYlV&8{DrODo*BK6K?4-#`%d}6X z3bShjO|z$*JP5q|(#lUc3*CBw`GTr9NSI+N5jCl3hR#@Ws;4YcmWytLdIaqaqX+xX zT$HyR`Sf=H<#{LS|9BA22W2Vidny^v?mCe~FSX<3WuWpVRc9rYII2?}%;8T{%idOZ za00Dv@b=}}mI>Np5S4FRw9@D%hGxDX=N_SjGSV9FR`c4$<N)XAOW}jVnvT9^JbI2) zvWb!~qc^kDiUuY&W*z=TiT}61p7yczOlY2uG)n&71CHxqzoy>cS5C??#W>5QJR3lu zisA4XNU>|DdNGaYXr3MRnwB%1vl$fUj3A*S4txR{uI?|*f8-&Y5uzow%j@LGMjkrS z$ZP>lOuvqih;!?X5T=`v=2Q5KtG<9w<fjU1Bu|NEv2IvEsdkdGt#o0`%>IGq^4BKX z$y<BInytguC=z+89iz^owv5eo1ECUQ1?R_=fcCBv#TV+nyvT-golqPy#(*w_5)ouS z!;}rBRpH?UoM1tt^y^(oEUeL>xfs+6sy1P(JBGgI66oTfk8H`yqRpq!WE}RN>ahL4 zyS-0n9k?W=nJQCWr-bK?WYhIW?8RbU{X08Gr6?n+=Su(NmCr4F7anHhHLKs4kK(U_ z-KV?|2)G$vr=TNjBT7b<vkoF&Z(<;TF;L5p&+G}L`Fup6FB;UGTij8E{p3Y@V`Ys> z1u$RT&`GbfyLCT*+MPE;c6eG#1o7`|PPtKD8$x;0gRo;~*g>^B!h7xQBUNe0|HapP z2U6kx`{QLMqEg9Dib_Ugk5dt;kjTg$Ioadb>(D^i$sVUtBr9Z(qlmJOy*YAl>~%OC z&iKBl-k<m9-rxQGS)I;#&FAYm9?!=E7wMJXzT>j<UH_qczOvr+^fgqD=}=Q{w0*&v z?uiI^$Q~1f><2lx72jvxkq}PU*RMT6)q^HPDzUW4ue3?XU%=VIyvU{&r9#|K8u2T5 z+g}%1MmR?HbiVw39jn{JNho-P@K6$?_kL3MS5fBKNBODm5a~tF?x<Z}$=#(&p+JgN zJc~Wn-nph4LspZX?MI4iLp_E3p1A_xx$V1@ON2Izrz;-;y3bm0Yjfu*Lc-nBPvlUA zRJ4Z$1;<$bp?>3=DZI03$3>WOs<wX!ChPb9PQ}r;r8wU*7=)2n&+0hOSzZIO+U@cI z95Q@A|KaBj^N+Kq)U3qVRP%UDC&>p=Fk1RDXxXLlacOP~$A0>r8_^ZyvLl}IO>!S% zNF^7eByz4?P@pjF4@C_SC{!GJI=Cj!SP@~;e#ED369v70T`Ti!UC<ToBZi*Ttil-< zHqS$^Q5*^xWa2T#k0T_S*s-(cbhdV}8TB%FhiWpx*qmW20(v3TBUOv4wE~pfvm~Eh z@5f;29GdE4+XtgpPyBU`-Yv&iQEI+AHQx<fC&UZslPieLT6M|L+!?`fUtg?+yx~aP zih|Wj5i{u?IrD+dN&QQ+-!@TY51FIgqKvHW$NW`7nL~uX{4DH3=l3)}|8zyz44y;k zCWMBo<>OTN_SP$Iiz|mKq7h~Xb|hqnl-~e=ZT1p7)-+ILT4pKkZUD{aCmqB<0CnG$ z?Nt%E{1|rl9v$)E=-1_irC`6H__o>8i@l4tz6R2&ea7N|{FasmfLr|WP0phCxU<3D z_eqbHx=pu;k_ppqt(bkLHk(JCus-NOsg)7JGN_h}OXGLet3~rCe`Pw`cRF5s3sS@S zAT{i#3rkCx*vX42_1a^2c=^LIP|sdZwf}OvkA{!6hL4_of@*(Wn_W9Gr7ntV;B~LA z&a2v#zU_FC=)8-lycy96cs+b*nNdKK$UtN!HtisSR)jKBtCg-(m;@k{^mU(y^HPm- zVarr$-#2FVxZwB`jp#_i?iX$rly2g==Wn3xqi~P6WsWgPseUdm4^pqcu3EA2wYO{K ze)dS(!5Wskbj)7(#jn+YW2d2VBcG(z|7-RgkgbZx&7|lZQZyv7&|rKkir)+Ai{&&u zjbVY8v6G0KdS8pYcpjZB+$KeHZ$admTaPt)RBPJ9hF-0f(qekw?{O)EnfE>DpEjBG zv718hOA)X&$O3f|PENPeacINdDL>tNDnz%DJ1Nz|*@#NG!Uln`soy8=IL{&YB%$dL zzMo<6NusCzNr$E~Y{xYrOkT%jm|%aB*I3u-=BkCrU=P-gzaomyen^ArB(NNdi{;pY zhoyE?68u{nrMactzPR94{mWae*mZOZOYPi&>X{U1VHv(=XGgw&Zm*+fBssUA!+onU zNB!+Rk_1!9xo1a9RUeT5^64Dnn^yu~ZM5P#`w~qt*y-uc81P!Svg3^R{AtBjux<7H zA|jtRRKYjc=rcNL47p2?UueYpZHkyvxK3C6T8z-?X@Gw`Ljsza&ySWy?*-q#<J_X* z7=B94R%N!Cf@R;Q2N+Y%YV;AfM7a)+3>lqEc5KDQQ%r41vlqQx@G=XX^^67AwqT4M zkkAUtWsfnpw3L+QyQ!CvS8U4xYlj7`56jin-V1PkOC7T6xY@va!e1sGzGojXQ$HXp zo-I?^xApQLdVI}<^19rSM&YNo%mPS-g?X8+38FY&ZgTI@h0bTqh!VPs3KZkM(X>n9 zOX<sXGLiz%mk>Qp!KNmUOvayQWP?6I%Q$$)?!u*iHRD(So%zC2+*--FzcZLkwxav! z*YcI+A)D74B~lBsT1c|{=%BKK8Y;>CoyX%D&Xs~v7!uT*oL<99Mes{u`j~tXT?$i! z4)Ab=-w^)_Ljl4~K7Dc}x=niAq|~l&;-}z7ogWJd-!0ga*B&*o?LYSfvrMV>*=YM2 zPbQQOpfBE|EVfLYpz4u2Yd3oH@Y6%4Sz>UqPfm~1C9to1<%j<)e+e-XJTOSRzE8hU zrY?=Oem-T1kaQ<Uz)Q5VhEt1Na^m4$8-3nS4(0JHJA;#cvf&yg5|x*uLuTLC$N*rc zzu73D#S%q?ZNao^UA8|x$mI!y60czJc!xrNsj=a_OeAG(*GG$Kl`CLljDfa>Y|j1W zzu7pZM&u4U1~+Ni-a+$()79%;6UuCY+>(ED@gCZ1>FgVz02~lHk9!UHIk-PDb{>38 zeHCNa|F&KBAlt%xda!WNjG?#q-?6Bq^Q)07vFDez=4&UnAa&$l3xTY7Mf}(08T>qP zuHR-0qUFC}ii>$bY>zgh;CFeAR)*xE>xN|6Q@^!8KyK)=d4{te>**tl)2}mrDh_b^ zT`mKvDjiaG#HV*@n5m@JO{#gtB1hEglpTYpgXn##<a^cXh3e1Of30_)09=#9Hi;5J zTfyq}7KT1j|BQ^AA4;xVLq`Qf9_#d~^)x}g*i9O-XS6X$^_UG^Ur`KQ&X64*rnID$ z4^T#m)=_iXMukyhR3`V08W{Qd4fYt-0a8Rj>{L8rY3csNEpz+qjY|_+Z<s2Q0tc6& z%S`?)mgP3IVy&m4;$oahR9sHRrF^N$;lYK$ytb7i@1<_7u#7S*P)A72z_{TG?1S`4 zsGt4^Hmv2pC{DB!N4l$gDZ}2n|BUx7Xu^x&VOy%8bO8qdlWmr0LL7ZT;vF9ts}nWb zQ6_BV>gDfjZcWdS`B3Q_xI&0wwgVb>Yr*}$DJ|x_y_iL74{tMWLnbU9qO(TlwovG` zW|K6<P^xIq-r;oM;epMHl0&BtM9?eIBotZsK%m!BONN#lPI6fS-V3fDXQHBdC*bSd zPm{h|uxuaL{b2SQL~eg9NysaC$|&v?-PjKB1MuL@4czS+NPL}kb+s#C$#FDQn(Wty z1Wwe%a?O{ibGdDocs$317d$y*?g07}5G44V1B5w{`RSoWgYjqb_8X}7pykE9Kn|Jo zW9{Z)8<C4Hb<9aE6l~N&`aws4{*iO<U63UcSn1p&vZ}|E0(Y4w9!{w51sK0?m;D7m z=+$5LFCT!opk;-w30&2oPs3Yl*>h4l+WT$bWuD`d{!JtiANN3NZ4H~U(l6Kyjv*+w ztltu+5Ls7`daT`@IP?(BL6WG5m}qG8;h}c89Xfi%`^opQU|3Ld5WBHa=d_ro2FlW< zS<L**=knMtK#g$U{7`5u&0r+;_&4{ci~qT${r7;Ze9=lwRy9w+_t_CWBDon{R`MEd z5(>$1Z(V$=U+ev;)Q~qrIJIU9>kPcjub&s3hR*PUK~<(44^c>jVjs0CdD3~@tjp$8 z5y-oH`hybMXGtHuv1vyk^1DcPh8|?=2k#b_!N3Ku--l&FQnnbSIJd$8>pbo9+Y3B* z*lHz7tL`FtgE4GXanZvZ`9-kXP@aI328S-cNv}(|?`veP+zdgZ?#`heXV6P{T3zkr zOgi(ArL{bAet?`jQdPZ)wm@c@29UT%Zuo64Z9z<vad^C9bX&lpD&2q3H$6EoByL%X z2i!dDlYX6mm5e!TB{YbRICq0Qqz3TkEGIYg>lK`wskXGQR~z3vS;N?wC`2t{x$DY7 zuB6xJsfp(9wb!}M@>Z)ZSffMgNOEsi@b#YTgVI+XU?gA8#(_SOlnmnez`$fi?hK*- z3^Gzc6qG;~T(vPs?vcR4@oZBW|8E#nyFbRnzC?+sX5z3tb_Xsm)y&9jGlkG8Eoy(& z{a*6J9e-Lw*G@z4JH=;r^s-VKBwIK~GW>1lJ6^p>mzw57`P+6%Ts?2CelHlxSYt_p zgIW6W+thu@N=c&b@M5M_3LQ?UI`&F72i|co*!iLFiq_pz>)fgOn>t{skvSYzw$b^( zYN!+}VBJopMwVMp<8r>#u}JJ%s(&L!Vsc{9=J!GZ@^k7TKAUm=C5|nvo93Z7(qc8w zk;R7cSq=fW2&(bPB_=9704x8!d#Z8Lltrg8)OV+B^K6Vz`52uZISI0qmH_vxDYA_N z0tr-OZbu}u96g_v>RSs6FgmO2J$yq=f-TMEJvo~LXO_sd(Cd`UwSNMaVyMpioS5Gz zWB+LW;`BO-?l}g5nSzXv*%!kD!x)cs(2@_Wp*)>oj8>$t5<&SvjItdyz3sjPHtL3p zX#*BV)r81~X!c5Ov7n`)trAz?V<Z^s#I+``*Tsgud-cG-*Yhf23q@P`y}bHCicI(M z<{Sn^VGQ%^V$FqQ&Ra-pSR|VGMm##keJ%VprBQDuB(fqlKGrFJ^mL1}xYes4km|Yt zcrQfLXG%Zrtz1;hU<S1M>iXmRle>fUoW?*=JU#@DH-6XXJ(ICO*D}AY5@zhxR_`?q z|Ngm0ahq~bz2P){T~XjnbLuNY9NTJ%>#XgB)`S;cHW7CI>q@Y5*X9e5(${&3{`ne3 zVFVK{!{r#OubM>+3?7%EsmNIB+?BuHgZI2Z59g9O^q6k(r&wfdaAaC+IZ*u~e<fp= z*mqoyXp~CEwGZ--0gcQ*b%n+h@I>2?Wuy2t2lz*@CvQ+Bio2+|FPu!=A^y6p=I_Im zatDy7^Y+^W#&|^V<SSS!m0}V4a#_8i8$^tX=+R_Oz+L8$hQAp*3K890$~mN%`RXt_ z&Uk)Qmxok>?8Y$xOca4{;I{K{7g=_-Ujc@v@Z;IqS7DmhBgsQ?NDD{)!Q7fui6?W2 z1&Q6svlCWk6dVwUYG(f)gKhSiyTa7`xV<LIDClj7LD|qN#WtOb$<mggxN{TNPmRP? zMq2tPunZAU1KT{W|8Zo(Bsuq}(n`4VwCBPigP_rNAYUl!ZezV<l5;+1cFjsC;H<rE z#kKI&+~5T7M|MSKA9hfew&v=t-C@`8r#LKcK(0_^x<X`yy4bs(Ufxvv^5Hs*)Uh=Z z%s?k#<HORE_#C>58c!muQCBgvEtJc#iyAI%!RozhOB}wC1(y;%A%p$wnt@vaa=|jK zY+)9Tysjol)^t`BO$Ic(s5N6zHIQ0n<l`EXc;x*m;pnorJv@hr=^7mZ__uyJDI>)i zzGqhpu5=iU!j3Mv%Zmhg7p(L@l(@JfH}N?r`>$y6jXeB5RbYDmj5vBYxNlrWGZNu2 zga!1sOh#`Sh$Ah4s8iy~nH!M_p&y3{IS@KJ<0QR&1<u3Lb#N)(Vr2M;M3g=8o4Y+T z5!P0QS83cp1#3xaRu_^QN7YOw7u7M+jB7bv5Yb2zvrKr$DyLe+`?YJ|h%hcc-dTiE zR+hz}5nIS5=h?KuSL>C*S9GnaCN<maJna>pexaB0v`ky*;VE~$k)g4uoGSml{X()l zC&oa3=*jK^jM<2tO_JXB+eOLfHLics-+j#cC8S=@nNOv3V~VbJRBG)Z{>!m9DG|f5 zFEdCl`YprnW#R%Ra}^#$#fP4jie`xD(K6y+Bb5xjHkxGh4b~I;)`zW!(C?U18njf> zyy_{t&%+4Y_A{Ja=bfGg1cD=}4>>~NN<YJma3Db6XYgEq1MF7Vt>NFP(^z%_S$|kE z<WGaj*d?7m0Sksx{LXUaD~CGa<S*9*=iwcr5WkT1)^Vy06gj~Gb>pSF)kpggNa%~s zL)SS%IncrDt51Lk4tKN0Bf}%a5+A3#wp_Q`HtDHZdr3)@JQD3?hEK8Jm(MlttkAAd z?2~_c2}MBDmiuon)z>TRqYG8jGLjFhO_a8N6u?#Klq5Q{2^tSikxG)Oeo14me0Kvv zBT2_aSvZ;>z>lHqN*Cc#F{oAc-D{&%T0uYUFbKt`@7JiB*HC0NlT4zhS3fT?bR`Dd zl(Vvbe1Nm8QwW&a-=c`QZb<Xl<{ZAER)49V>x^-pjP5G;J|i*GLS*)kqqxNHZ5KLT z!kN>uA@*{4ydwc;EC{F<1*!2rK{9T9y{&+Ajk$OBCN^8C=vo^?DvQe|4iz@`Gi@WU zetUz1RPr4PGGYY$9wOn@U)}<7ARplMyNBi4ir!6GeIqM$l(%H5HKJr05u4C)BSy=J z{ajx00-}{$hix`S=!T}K7727ucot4aVOC7>3y)z`cOp4(ztjp>5>8SUqu)vya=7s) zD}4FvbtcQp11*Fyl0zro9~=dF)0;N6qaxGSb;JeJz(<j#DvZ8WfDo1>YU&e1Fq`9? zN<2y-DyeNl`?SCUg~{v}JdWN7yBqU&XU-q5c_1$P9B{n-NO|+}_Kp4vZP{>B4kv#8 zRqJj&nxRY9BM?;dMkr1>OP7;e+4O;0Kjd!r>qu}o-wnxtb-ZH3Lt?@lO**$&sW<q} zn{5BQ*1-qdy*O!TsxTm#{2)DYh{ClNkc<wagn!0KXW))(%b<1`wt2QsnIK}osp$ne z5&H+`2cWMQ{oSi`zuD+ykp-(|g#E`HWiq?1hwhGs?wfaQ;MhcvwNQ;zOMtM0U1`iQ zY7X@Tk8%mDIC+`n*sGy+RM-Y;^=IEz9(_*|Y$C{J1}NXbCWwy3smLPnriK@?eY5bU zcELr>CV1C+FM-IeG?BTtG}ixnX&%}5GloC(aqPASdWm7DFTj-#9i#vA$i_0Pqbm9T zDNEcpa@OPk^pJ;+QG*Yt?7;x{W~3tU1A>j(zkd4#1IJp~J8?9Rz&|+beZqBb_Iqzv zG7ycC|6fhc|HqC^j{xSt-{muqYyZE0>^GD89@^t9C|T|Q&cANQKE-_IK;|<(6i8JM z?4_#re-D^VBpE-FH&h5Mj!#S+ScmWIzph~l|BUgDlTUbS0;lsTXl8b|yU%#(5@=`s zm0Anfu^*>j=TmXoGX;%&S?~<W-AygFKvsC_6~6+gU)}o+3VDT6ylN)1Kbm(j;1se) z`<q%g`{>uvmY$cWF?BS4q0im?k>L`<l_3yf?5jfqJv&Ce$)jk9DA8?gvJiROxuhdt zeGW<?t-u8-EWc5X+MQsjnSka92{w0pH(%1xZ7*xv&0*hsTt`ZOZZ?9}{nYsJ{d{TI z{*tVbaL5GG`hXcFe3ZOncAioyjf?Rp_<a;rOh1$3odHHvGQm(%?-2*4b^ptmNU-?x zQFmLybXaNfJ@~fwMN4Dl_xJMF6au;J_VdTCX^rn<_`oOxlR|G}ygRX>&6;H*ZELso zx;r$(ZwXB?B{cIQDH}cFekDqj%>jyLE%~`l^Xot7Zz>#g3-mj8iaopz+&0j$1l=b= zaV+Ip3d8hTFXSC4#=YCqN{toz=Vy23cgOV={0GB+su?TJ{a6s-Qk?m!BptcpH&TIF z=J3O?en67&_CatS9k-b=tv!1MUa6_r$F*rM{0qP)@PQ5%0#x20v$$mFmNWhqMn*EH zH1@pu&*AD<7L4vUr=%dcl0y9U2{ScW3dLCpxsrGI?e%O*Z2~pS)S~Qf+kLwD)3n`= zcso(8|20$(_<WEFWW9Jl@xXu5n|p2_!`^vqKevezj0hw)a`G;~TluM%y|-Ui3nJt^ zC+l5VGIlzt%OUcLoe+f2Ru5Lg|8h4(i<1VR6UO1oDms4r`$O-&^6eZfWWDkRSvC}8 za-C%+`!t#YG3ep(Esqhuy3y@rQK>5XU#edI<LgZ<^Sm&OuOJ#dKU16_9ncH@CcGd+ z=M8zt_P&VGWI$+c10ak7)t8BvM8cl4p|5Y4==Bzx6AO<T1nqz1Dgb%pD^~NT5c?o? zl=<8hRLw$i$#TH_h98e2zKlMqVtU!MeB5)8yPV5)OCuBEEdYiuy;j7hrBU2*WD{jJ zTBas!I62I@@2I|Gp44woZp9uZV7Xr1q161WHESl|L)(c?4GZX8ufdNqiCWIC4fMiI zZKZ*ifwWF+cdqe=n0*i8(8FReVW4lUdtpy4cVXWog}x^f-q9l#{93o4s-b;mBg?ny zHv1b^Y6w64oD}R9lNJ!ZmpUOVK6c&Hq7jL|P0j_HyT8&-5{yCPp0e9KqB)QiJ3>L5 zofK3oub6Ea=vVSq>A7=9nu}zry(SN`gMSL(PjZ--e>?+B!ngM%WR><U2G~xuQ89eX z6|apdLfLpZ+HKoJn%igPh#DFmfLQx(mEm)?6JkdGww-HQC*KCqr?XC~C{CKMc&X^L z`z^0L@QYUNuycZ5bPVA~RIQY1G5r;_u+Jmc*^0N=1zlHDW<awZfC}6+Uiv%W!<`T# zA{kCuSnDJTutAXh2NNaP*NJqQ<CpGHxZZ_T4tTTzck5@z@n?W~xO*?L*>HHB=kY|2 zHd(bXix>&=)GcU03LFiVE{1b?*5l5DnI`S6F_*TAt^nSe<%$;rquZmHU^3xT;)+Nh zCd-<H8jXABpr|*Lmm&4TIkrT+nEz?I3BJ;A@z)sZ?2Am%DXv?|PTLpv4cpN9@ZV?i z1b}#M2Y#nG`VE9e(rG-jr?k%VdKrN#!d~gW(qYAY>w6BvIn8MIc56bUdNr-DN4$p* zn{NgO0UHJ=IadmE_iU9PSYn%*rYkHFO8B?h&01AE&q52Ua;Cb_fxDY<%5GsPX$wgy zDx(mwdj?joc4vA~ADNci2-)q;wXoG0c}~5`Irc>jKk}%58&7j+_9Nqi!j}eyC*=k{ zzukYR#8pTrkHjaNs8f$9I{|T5R`UG5naC!f)QKgjJ;si&0^}$A4CGty_AEB4LO&t= ztSKK{72}WI=%w0Q$40&!xRiu+RJw~J@~1vx`$s&97de^G9SZs}2ro|xB?ueg`3>u8 zh+AklWvLvUM`9qtZuJz`3bt%jJ(C@K#;=wTy8Pk+)WjkB`cwSJ$_GZ=;4K9N&>}7H zf*x?g%OlIlZ+^C#5sQC4kXYcBt#Tp3Hg5+D1lw}j_F6k2>>D7W9>W^XkG?y#_on_C z(2fSXPj@Ciox+vH*V!V~9>Y`9t*!9gr2$?zaV_*V8Mt#0%FaSze}`Eh;d~Ap&ua5R z=iQskT?A`X+FLkt^}TupO#0dV<Hr{W?hCCjB~8L@4k2BKZM|w5;)gcu_MYv%fk!ER zN{v?!lPD+>_;AKQ?R{^HU*@UDd@A{Tl!*Kw{-8TSu^parpQSs`A$yL$`+RF2(cTsr z$HN)89+$}C?>lRYI#L<1^L~BZEJ0M1@+%Z>=uaVSwI&D)i59*FV<f^<NhrGDVX58) z8*w+!UBpw7vSuDv?C+Z)Yw<}I_Rr9&?6rMYl;eJhvQ@xEtnH?2wHd!01&rCna3=<L znuiA$*yTAp*UHvU8YMcS92?%aR%JQq4K-a0;4xtvWSX7Ib(ID{jhX^Dm;C~h!@;Xw z1%0d)^xH=belV?y1`pM@*Gn~-7z{Wb{&J`GBUY2zzUlyXkkmD0^QFrQ=6vfnfzJ2@ zZtv2shhTY-bA)E6z+YWPw|VP4=3kFwY1DyvzR*EXrm+Y(VH&$4MCh1o=7nz)z@N{u zPeV9+LAppHRf1iXm16u<!*d;xPT|Dt*B-+n!V=opFFht;(_(cf{>|9AT9(Mr+6$C4 zsnX5)ef@BG>mdk&p^d5|%hzM*xc4cUX8lo?q^6~F=(k_%YkD2!<l~m$7DF@@oZdb9 z7$<-O(Gf=+bKeLs7k8<E<(mYR1d;!sKU7}MGUmK-e2AO%o;YHaCR<-A*#{)3sf=&W zIm-F)&2zjU;y}aEN;x`k)1htf!rqMXDHu8@;@v>Euys`6=7I^M%kUYji+fJ`cZ(C& z;%@gTX`kvcMRh&Sc+{-w><5bCd{L$yD%XK~5n;T8l`4nZz>&hvI~CKByk(~)yugcq zcG;-DIZ#{s^`msE*{&)s7kiacHh1oUgyKrWPNGI4Tr>5*IHV^xQPl_84m1Sw*dFmZ zxypTWO{A#<01N8-nleHhm_+F6=mKd}OOz|>w8f|luEz&J#12=mc_*8Co#A{d{ieFE z_eJYJ2o<@dQ`fvQXJ9GV&|nKLs2}zr=Rx^<deYSMt^)ccj5|_FG=5r;OZN6k(K6KI zOrx6iW8c}c1-BHAD447GL`(`ZO+Dz>ScpBWeY$ZA#oM-9EdGQ)zg<px6jD7oC}d@F z-_tKIFE-7Ad+n69m>VcOP2CuUp77B;oSgdGfi|F+9#gw)^w$a7Tc!T;z?7y|^RCB_ zbBM6vKbTB!60Wkoy#7*E&($!Xn8L_xp1T@aFK&MPGjD^CvFZUd?zPE<T=|1uow^XZ z4ZO*QOm=h?e7i9(1v^{B^1_u3``N?i@~W44z{6R3AG2sqlb(Fre6KeKW$bNE(A@QV zRv(+{52{9gIqH#+L?!@B1}8ty(NZEg438uN^MR(2rEB3YPVPSdwBbZp$Bz$iCl8pR z?@EJjBJl3AHU3C42NFv*SGc8%jke{?FHsQk1<+3+;d6+AtS5Czgf@x6my3K0WP<nv zVzFgBJ%jLY!e>HV<o4ibP7ce}$(b@oz?@e)*B4&{%9d9^3<@XX5O8SF)P4xnX!qjJ zFZ=YU;kS&EE47IobOW`eUrU{@B4;*j^ifWpeQjC#b^X?jLXm~uIcuNU7tEAuyE=0s zMFPGSID4<b{?lI@8%m7Kx+XoraLNl>vSxLnl{-R5frK&%G6G$|zD4CL?+igHAs916 zASxK8OV9W|Ie&M&BG#TmwKIH<t0W>Uy7pu>pC0ez?w`~o5jg34TX;&^KW2QlbK)Hk zhv*T=-1-xS3_bfn>nTpSjcs24;WZf8a5Fe|dXpaH-10BJ%!U=+kT=3;7HkbXwLK}t zpVaCq+L?Hp=upOs)D)~aR%6`?Ve1No+zD1V^!R)F5&(v61qr3~u{6v!PBWWXAn;Ti zo7(jj09PCmD|lF&?cc%IzEQ6slQzaf>DUw=tnTI4E3aUH0+4OL%xe*gu2<btI%_d= zLhn52ZjM>nesU=z;kw_n#4AiWS%~`hXhg|%oXI_p(^&}!?5FE^3Sa&jPrpJP<x(se za^O+@5mjg0p$Q0+KlvrLu9=8!@NYda493gboM?A;K*V9r_(C1r=|_p23*R@LAyE>I zSln6PYf~?7^wR!2lH6OlcavU=E9C^qLTRM0W=U+xVq2s@gPD`U;`dEaL>>824~NOa zs`2yZ7moPU{kn;gs#vuJ7yw+xg~yb%`FO{gNq`WQe1NY!LzE~UqpEdl?{Sx$T=Nc2 z72Zk+VN+p}giN_*IKNdWg~?dz;e*cSBzhWhoOQs4_EszBGs(SvO~`Rx>^=%2dL~D` z5Z?8>@;kNzw<aLRjv==U+1=EpCC9WITQO_cWAW!>GoO=g{_0rTLp!YGs38voTD5C2 zRcuS~k_q0IhNOco=5hTzGz-7qmoe2FaX?S3b@EEVPI(du6)^a2Q4mHMO)II2Oh*ZJ z$yR^Cu&s%RF%K4Jjg*7#{hRGdNhtxx`l_DDsBo+O$pBjelHR>*H$G8S-tEUbkH9@X zxC?DQnfj@sA}{Z%ZKUg)hY#37;2lnkUx+1$VW2l_A`5ven3it44MoXVkSi57-Qz&U z@m24|c9yDlBm9mt&PiTH-7-SoAcc413ywWee4;|GY}}Hp1n~k#q^khniEXz)_O904 zEQ6CppI#odr7Yu6(eHP#XFXRvErgsojOqN3L>$Ds<FC??o1PO2X!_r#)*jtvN=mG1 z&$j02c;XQO)QychoCU-<D;Q=uz9g6dwHS7&{L_~skz+1J1H5UpH4KZ*&D}AMBd6@w zN=Bl`lCV-&@D9vrw?N<c`5HaG6COYgbwByPmzR*`&n6RwrT11Ko#gU$2YbnoYwiW6 z*ZXDS>*1CvF`~p-c}}b27GD&!Yb_$vr3&&SYW2*ksO}pXG}uiZl`(=j;Q}5dAMG#Z z4ESMFx6=A>J{9i|Mcp<t^a-P3uDMvUJMbk6tk$;y%O&<ppx`^23`-+oKa08tcBa`A zpAgTjqwYjDpZ3<7>G-TU_t_WnqK=Icv<!Klacl;Z6|E+;?6A5uWCG2^BLU5{lg<J> znslbr88%KO8f;n8NNQu1a{n_fiX#zQ*>^q5l`nqarDuM3)RTl;eqB`?q<*;~=sS=2 z28vz+hEX>C@<9}B72qkZHD%@h<jJt)Pk`lA<tdfygC(C?S{^!8L9-n~LKT#rdgpZZ zPXTK$NeA7703m&&NF=G+^}d$2NFh@@1qanfGfn%Z@U1uuGYRE1-oE>kF=M@kWg$(r z@*b(gF+4Lf4ZvS|i@($pVKc&=ptm_`QT+M*?FM9Ws#-BE9sm2coejQ0V`{(TaGz6e zKV95`J_D!AtLhaL^z7*GG_h=;mZzya>`#$kT%*lNFW}5Xk#2)x2>@cJXCWpuY&b`e zKwHn_gUrp4-NQ8mPOP5PO{<euSGvuOUM{Ge9`F|_?`nHfabmW~bn*@`#c%5#(UjBN zW^Z(5XQ?FnupRy-bpnZZz7n!s^@g7a^AeoIT%3SS1bkYtsJ~|JmpyYg>n`QTsoB^L zoA%WUbgsRazTJayL$oF>Bb8B-4L&8+au_aEb@CaPT#2wv3o5Y;Wd`l$y`;|HT-Bbr zOpQ#7AK$%KPp%w3&Y8o`)5n$F^fB*#2ki_ZHuBWt)LCL=yprI|z<ZuwT&I2S{o-s! zXK~UaEAX?^Zs?3x?uFB@Oel-`VYu|UO67Q&XrUt%1@u-v?GChjOzy_WOdF)3bH;WT zD+W*9Pz4W2N#Y1Zh~obaod8x8{wNKG$bys8nfvP(5E6@UI>)6$6WYxTMk5AU7pg-; zsNm4J5=x$5j^l{9tj{TzsIH~a<agT-CU~;dhNsOlyhV?E4wdk~&Wqco5ugs0mwfuf zZrt+aEiV9j<1A~IC>zfANtN7{k)-dELZ-_7u=X_ev#vhsarD3LSt7Y|F23-?mePp= zxaY&v)&y^?u`uWtsc5Qvc!w<m-l2Ec{R`Z5z9%~)=@9Y_euc?l*O;TB%;(Ue_{~qI zBGCgcQo=wY8P1prGgra+V^2i0s#cMQa6$)=aD4T0{S)II=xJnY7&!|RDkgGIYx62b z%7FWJx^i@@)OTEN>jA?qRJfWv1ZTUFd8<x(9fABbjNL@B&p@6owQv?8Dr-v|moL{s zdF?RI6n0U?m!xN~2@z$FA8p7=PifjarD`jsW=msUq{7&*vk2?xC@tnoe15LYWzfSg z_{^eXc_XF!o!8+)+f%xqX}A2u6`y^4`tL+3JIK*#gdo$vL6{|1p8b$sX_tT9ODiqq zlS!7Nhyo?za_O~!3i6wr72>bj;A}tRw2`<)^l@5T2*Xt!1-jccHM>yM458ncvM5K0 z*VOPOv*+-PuOO&X2ivi6Y?O%AAj`OKYp5ChIV}XU{}R9HH(;Kxb){c8JW@iQP|Vr0 z{7?SpOU}uhQB0opoPf>wCdve(*dEX+75b6mHc@^xfI6yQemB;mBc-?_Ij-F?pLIpV z;V+I0b7;<d@}?U08wC1+wn~-a&|(c&xUpB0cq6fe{SFyOLLPHGgXPpJ{g&O+1E5VB z>M?M<%w2e*9}fxF5+mT5D2Cv|3k%l90s;ke{Yp_Cc|a+}fq?z|<Z6PYf9o1bYj5@J zRR70=Rj{X@&N=#_t(K=8;PIb<8UIjabO$BH2d2SyDsS!;9U)m7U-6J;6r5SNGYc-F z<q@B}js4KUhFwEh*vsf`hqNTZRXc}$L@Y$4n-^FLn0!Jq%&ObGmUC5U(@#>kTzk=P zx#PC>{E4FfTCm>|%I)nrZbRd9%i%hhY=DG{i99t6Fd6qB7^!#i!9{{Ad(ft-Ji%1$ zB{k;3yV&~gM}g3A4yqBtZ><f1n-!qbXT~6EjZZ^gjMmF$cWrQPmw9JcsBcT;9b$*t zYD8a!QH(K=R-qoEpf;HNf926-L6#FJE_;gThXciBZ^^HiQyFkox7wMv3QdQcT8hm4 zEA56^<tK9T4jnU7e~<*{LNy*9h46no=@~d5Ex^75E$JJ|TZ4E;kD!X+o@m|yh}y^A zFjdQFv&bHg#b$Vd8FymnUD2wONQL_pn^^=V$&<1>Q5*pmp(E2|+)~`g*~_w=`gf8X zh-hVzWo6{~#T+w3Qr<`$?uP941oX%#eh%(=e^w>x`G=$4y~YMJ%J(T;Qc=x;*Z|V? za&T~e;gYYAU@A@_0rr8QbN7v!N<&SKKmU%O1mTg|X~{ZHi^62JCOS>|$Q8v^w;5$d zKaci8`PF<Qb}|$Hcz4)9TS=I8Wci9uIGKt}Ph>Ornh6|>F_8V(8zNmlT$H%h%=@S7 z<W|(C^DFS)gY^TxQbXk6XNDK{Q94$@D6_L0T}O_s>+lq#;}eAVwWPx(q?0Xnj(Idf zQU%{7fSpCYj{jxSZgcl`6iLEA=S)T}$oxxLbj!pMlG>vE(?=IVYCSCYP6PhYjOr2+ zZl&pMwm+Gm=)SZE3jD~vfMm;~xEP4+N3kkydGNT`e@jY_E(b7%fx3yfLvTUtE0?v? zf=Um=lG;!fv!P)c@$dqctF*%h)ALL^`j0(k$iu!ayUILd<Y#WBn<4bfVC?TZV+$0> zbpBHlDczjuHMP2Q_WWLVW3D`CxjX`bHL6tsG1QO^6|_rYB+ZtqxZJk>fi6(#>f`=v zr=`I9{N^s*V;<hC)2I|U4<`k)kSh*wf)D9=0rm96vuQMU58B{Rv7=50os_4^nwoPD z+Ln`OBlg-i4vJD2QUfU_to_c7FfP77K14SNR<nN>`hIt)hMczu)L3T+rznrCyMxUP z7dvJ^rEqw|jrq$#&x!t~AsC3p`!+hRDf`Y<2l3uV9lw#6_1Bnw0j1K5`=!!<m3KgQ zl)stwbYU_NE&f1?Ed4xnWJTp#M;6>P_3+Mdb3QR@84*z!+l?va|L@uU<yoFXphZ4K z_}1}+kp~WHQDAHndgjMmSU>AK2?#y=!TI;xJA%^b?fuf}-{R2wtgB2Q3nvATm(^!$ zju_jhIMTSCT;+FR>13OwOQTj`XgkQ9JEy{@GWOR8e-B!oH2)Xpt-IarMBQzJ`zawX zsh=B1aw0wGo*zA%W(|aTbUV!sA`Yw^^paVx3<M!hSk+$$?Ja<NNc%0xD&CMfAOEz} zH7(`a-=dK2v~vyhD5JwEL*J9DoMMdLOx{!mZIImqoKrSgH^Th?`g;G`r^Xez?!gn^ zzdw5PLES#BIO2Ip=;fMo`<j_CpEl{CI+s_dznGWdh81i?#b?dntM}eWFXWdvSs&f- zB_!7zJqv0v`}K#g|7_PD#wMUWwp&K?$VC8e{R_xfsyd_-#0zMpIXYhqvlC0=j<x*S z!8%>Dzcl-^USY!D{<Xh`*`Zkezv1052#jCv7YZ#~O^k%;n-v9fiY}T{^7hh*1s^w1 zCNEu%Upl$rKyHWeioMJr9G<vq4$bb}M9G(2tUBUCw~)VNdFipob;hEd|2^|lfSdCx zM|{iRA#eQ085v2{M;1H3Yghc>^lNK>xJ#B7JLnxJ+>W;i09Ysh31w)b>5!^QuXe%O z*N-XG8k#O&I~2?KzlXcWdszy^B3#T%Z$|0p+-%u->dKJ?n@9BRDaSH^d#coV;&F3* zWI=~bKpC0#ZIRCK@!3OP#COs--JtX$#*fqMH2<$Je?`FR8XBLE-K%}v_foq!ukdHs zjGurNxS{gDX9|cT>FJzg<T1T86BV-&N8F{*r}p;5ju%{!|I}swz1)CK0*W>r5N^&< z7xTVfO#HT=No?KQ>dC*by#E{`u#|d|(%EvBe%aNcni^+-ddS{Pe`_25Q_%g7@w)TI zE7wi@lW>u<T1`qz?IRm`_gkv&mc^6~V5b=QRF?LBA`Gw&?WMb({p-k|{kmW#DR#~= zGpm%A`Xx|z0XoP_;50n@2v{BeRXhIIPtAMho|QVA?i!JzdoZ1L%UC_XMrt4L%VCH| z8BwcIB~k&U+^goIZ`At>&OH0U_`h%d&}!ZD8~^+_uzTk_j{%d7<@(5Sm3o*uKTWZ} ztDp|}h_phEc=}~pC8|?YxZu6KaAck_>U1`Ls0qv4tJa3}m>U4{ALKg(r}`J{;6K-9 z-^va9!uIrqKXL=uuVMXNUGmU(*-ko{6W+&UMuuR(vX|G=-=*@Em4su?kb+4;>A{)7 zKQGH8n1^h{#KIe@{D|%|)25Ol8y8%v_!@v(?9D%Z)xV6;9?e>Bf2vjawZz{3)f-`w z3704eui&VN_gBk?PR!E#x2H?(%EWSLQ8NNG^Tm3xi4*4X**5$jPU5dpI*%`{XRFV@ z=9N8jdqRG~&OGrAgXDW^WDFc*I6|twfY*hvyr!Zad<D+>KM<7vVMl-WIr9g@J&W)V zH9>!u2*xxP|HGs7T(gTW@F-4kao<ay!%kHRMY;=`Gb!Rr7IRMBnBw~XH|Zclc-Wlb z9@FB?-gl&y<nL(EIW7K(m@UnDvqkL$&D)q(ch)`>`%nJpKPUd*GV6P=$zz>X=`oQ; zNhND{0Iu|qOz=StJy&OQD=7R6+=->8BiYy{jY`DOTWa-)@P;bW7N{J@JXuE-)~vT| zUO6rAxj6Yfyqz_lH$PpS<+;h&&IDvWiuFpQj92W>t5j-H5|JFD90A#LCRZmdR7W)j z&s)}UW`s8pHJ9wa`>eY*z3?vUpIb8v;({c6UQwLnyt|U8BC4K7KaDJGLxfQ1SV_vS z^Lt?G!FNlqW&O%F7fhgb^I1tI#vjMQt0f5bYR^Co^Iwj_eq(B^?g1f~pDaqx`{Hun zz8YM;eupodaj3lJk_p9_X2bk3?nD9SV7JVPC4~GzgxGwgD81_tjSSEBaqqBzuE_2R zeLj_)6R+Vsl6JZaE)Tyv)-E(vwC_ll^YF!{d$s+UuTRBdaqA+~GGLW!2MeJXK73fU z*>5E6G&-0OvH5kUYuJ_>kiiIhzK{{}<$#bjdO)h!r$ZKNpjGe7+(qsC5@URI^@UHt zqv8QmzxH(b0fknG^6qXi-e5OB^OzS0_BsK5Bv)Y3Jy&MZVrQi{Q2Ojk)=1WE-7zdH zh4#m^)f)1bYu(rP&<|^`R3?z&Ts7xj*d!6=D&JqrdU&R1Rp&En>p|J-Efx3&gYS$l zJT8zap3v=qs6)VI{NucguAfR2F8pZYW9XV9sdzi_wB*S<x8t<FE7zev%V|+$0hieL z%m!-fS)*N(|LqAvWtH*RItoJNMI8X5(0CuV#QWEyH_};~AzPSsO>0JX#y1(Rw*WDc z+%14d)`F1SePy=BywEeL&Qbo`*y@!!zff+^$GsoB7zESIwVHO!NspJlFh7sPoT^qy zJE<61TwIKal6UISkS@&#+T?mizj30u^6>;K&bZYYFc+Z%w$gnP;34>}M@vO`BQ^fz zs~u0*k(_!OgL8VWjSU-UTV`U(uKy(RK&Ag>va~{nbkauNRnu38h+eTz6VG)qNk9}6 zPyEnjwB`sr>}e@`2D+6oTX-VZ+sl&sB?URgPA=vD20#(N-7x@4$uX5R;A+lUtH55k zlO6<+HxJqjPn~ggEaiOc&ZdnQ;b2qHY$;=!IRHrTD~9yB$}fDWuXQkQFP7EbGN=_k zTrpIi8zz|^KV%;a!nW3~hJwrID8wVHtgAlL&5KybND*gw364NBW9xknbR~K0-L7Lb zJM+10X8x`V{rO(wKG<XYs+Wx`Iu$sYAx7AT{05k9db1kuwF*}Zv&_VS-Q*<7kp-S% z^QT94Hs)|saazN>`JmOaUvnYmfjJp@PHi?XtmIv`1^PK<oHVcw`8XTCqpmDT6DSXe zDxvmTgK=8B*ZaJE+fqQnp<EzNc3|A9NXdJAb$0jgF4od#dn;r7&hcA~kc);s90Kbo z`<bi66N`;**E*IJyUbMd+Rs>$XkX11E=v+}^A!K_BLR&*f22k#U>MX(`O<Wy_hM7! z7l-x@6z0iE5rAI%)Y@JJmvStTuTbL-HR)B9_8!ieG0v;B&ZQkjj~HL)=T-$r$ZZEy z2_ZH^5NT>Wohe<$>UXD#$E53g^Jku~AmBT5*@b}PaTJEi*DuW292hPgFtuMXt8$+^ zYZ(xRK{&oU8HW_GoZ2hcL@VMS_kD`r%-$RtLzH#AObQ7Q-WumGh$q0Eve(cvbIBu2 zwPxJwsD2?i$KfydrIEd_?w5C{{n@|kP}|p4bPgP;{@iJw$jrj{rmJTKY)ooTf-4wo zeRHNcPkkf$DJik<Z0Ia9MdACY4E=9JA(5Rbff>W)^NX=#%4GYSXxm7gO|vnr36pca zmUAXTUCKXN8YdNs!bGK4?-2{ngzI}X7g2VKm&bN`cDSyXHx6)P12lKoVl}#vRT%$x zS5r>Po#URZu5}eMD6!hfQ2@&NZTrFjy+)p^wWexX%B7q8a_|nd7sJJMvOq!T1G{O+ z&Fk6Q%?t~#3wSOOKkA%Vtg;%vRqBtIRM012UB5;<#S%+ge%8?X+QvAFs1E?h-(qH2 zbzWjf1iOKQGxAy6R6s(&O$yNz)IHwTp950Ihs_p4?tFodAC)<hWJgkFH2!feCWLAF zG`0Uh1x7AzH!~ne`F@pz6GZsCftb}<b-8xSbV1FJqPR6$B3PsZx^LmYE=WK-(&Rio zZDzBpYIBl@>Jt1`jt#tmYwjK|m42{ra?G`vn^V%Rx6ll-z+Gl$vyhL6zfCq1s%^Gx zZ^Ut^nF)d9SJjU0@$GBG6M675O7U<H-%g=`R?%~8ycp$WcwNB@p9DV!KkKa+%EK<N zhZtRw{uZk@+lveX-+|j3M~lUaWV9|%wjNP9K@s{f**E68h^))=D<^+ZQe!&3=F#kf zh$G*$*5M?}cGzR!>ffAXJJ{H;>{<G0od2BjJ^lKG%zO}@Tq31CuYmFn`RV{|v0W>6 z`Ou}zjL+d>q*N=4Llm2EeO#1i|2=W%U{j9eXAOsNs5|!anHjvtm$fIW8Bu582jMjB zQ)&}ti&w~X-D?7?sNL0)QpF>e-!zxevD2kdIbeI!luH~<EUR=J9D(Lj#F;3eU_cvS zo~LaUU83j+V@tsvciN)PoUKAYFKh(8xyAx~Or34A>>}i3JEg$5!sXZMuLiGS+wA^) zBNle?DR5tK2q)M?Fnts+WSmLl^UHjlJk~J|97LC2l?=y^)3m*uG^M~Z&wM;26BN{P z_VC#xmAKPe!dFCGwI(^XPHvrFzN2z8qDj(K4O92))UmCK$UD84<wQ<vKV`Tc7hzh# z_aYG<xV66Gv+J(qq3?lMhIOPZvyY>6SWtI8JRW$Yr%1Fx>u~w!?0O96dVVPB#gR(N zUx8NQ+^Wf!pet(^4X6u!^Mds;eSZ2&@uI14rw-i({{n%_clwIH)y@Z)c$;w-S<5Jm zTk_oaCLCK_Q~6^vz8lDDh=fxXO+$a_>hyOyJ0O3)zuRUHV<<w$rlq#84CShG2u-V( z-1P|F)N={D-o21v|NX98WW4>c`7{G%Q{&zHO^I)QW$vQM-yUpUYM^C7t}YF{EA#3) zad-{&pgeM`&+98K8<$6~c88kg@H=*-=l$_ZFi9t19yLBZ?lJ0kWw`8VXT|>&c2^Q= zYb9gH&)}}??w;v+yN3vap1<ktpi+%+Zx}VFIFz@!6;jST$mUCMnP&=S=1(ZW_S{-S zWhpcJm90cF;0Rr6+u!a_Qs~HR-h#dZ?i0LUnt5PB5R1tZJ6Qf?H^QwdGlT_`P2elT z#DFMs=c08v>I|=2jyUmE)|u(m<S9EGC%(k0(?-~HGoow4Nnpd^XVI4%VFLHuD8!$F z2nF&s#;Q5W#Hn&xYScv;hjK&7uhe{P+^sKEr>IMu`)L(A2x;(DX5x}@nfs8agdenm zFl}#RqW7RFejOJfjPktA3yljc3quQN&hIP|uyGzKX6(`Nc-LcY1gLYyxC7*i*wY?2 z(iy}$=d;U<C;1Z}UNx&Y3O@w1l)Nh$aLiJ)U`yNwHK`c8WlUagI!j8axqQ*_e$%HR z{_h!Mm6`X!j=l=`<Rh)#_u{!(#IM~DAHTk)@$;10?*-~`k!q|9RFB&}*q#%Ln13?y zeRDi!Dcw*RHOH7?pJyC?58F8J@47SstEG9s2_;xPGe%!eTRE=o?20d6yxdF3(nrEI zcbM%v1Ro825Bbc-H^7l4-LX!pU5J4@UAmb%?v{|}B;DEM*#9*+eO~5HYQ1*3VfG1; zU@VL07pAllcw&yD73rC5T3nlx6$$5HpLdtk?4}`f^r1`+gl314zgy<c8FxGpRR%BX z31|z8l5dD-nKA(`qnZ%p4ZJRu7kQoH&q=}^<yn<}Mo0+ol}N@JC=-}1q#_Iq84V(Z zb%wnuMeF3uE>UF&^;4;UA&0as^Sf?0!0jH;aijRROAh!i*_+{5*%WpcOR}<k7xK$( zUae{wR(C*l;eiX;8iVKRQ}2%x89JKR<kpln<+nJzc?HM*=Qc?fiBUSr0eqolA!FLJ zI+F11`L^;KArcJKmz6d%zWbdm>^3vqjm}D~{Ifrh=Kp(tc*uU?CUInAPt>oDJh^_V z0jUn9KH9J03$=VB@+Bb|J!}dC29>AYcD(2#Ob(Z0eHlJUIaR<t>+YPZ{XT>)F1d$I zH6@W{=j8Kb5sTy@(`Ux^N#h1&ABK1P7YqealXN{FD4X}QJ4<3#b~%56<%x)I=z|~g zh^JGWHq<(UaxCkxH1pG)Vic}Mv1Z?vSww)1T6Vt6<73(6%bgN=uh}m8R`O638a}15 zEwv{%Vkol+NVw-Fdz{tw=xvHZ`d&nN|6)G8AZ75Y07*~-$-4qAw`d4S_h0`xj<PS} ztGR<;;)8ED@OCKR+MZIk1-{Dqwdrqr0*h%3yr&^;^B}wH8f8&y(>(n3&up)xa~={R zy4`Y6?eOs%LoCP1+CBpWEQg%KOtH*}E~z_r2(s(V-DLVC0xp}eAas6L7w7cq6YCwM zE)=uc#~}S8{qZ|(tG>@g$~9i^UC_SH_r^zbGkur4i-6H87$HgHRuvV}YW7Vfr;HCg zZ`Hn1`<s+Ar1A$D9`w4X?F-~$YNNmae|F6&b&A#xai87$J8>Z+Sx2W3skghb%G1tg z!#xE?4_zwx0zi7bl2ADyCUJA+^I>*UNg+(${_+Cn7OHPO_-YeKh`UJsm`3n7s9$GH z-BEs{JoD&Y=SA`melR>=3YS?Dc~c%VNH`y$(2Psl+3cZ?#kDml#JOyQ(pn?yp1tuL zdL%t)PK`y34qFqxb~@-h?KmvEH3}mkA1f_aU|x~0j;9jOgb!i{wNmUk*x^c%iaFA= zYNsy3Ll8HVi6yo7Oe4z$##_8~+R2MPBi3v(r3CD2N8=H)?YClULU%6u@^f#JU#7KB z!EoLED$BSjyB-fsnfKaMm3-n-{?2PsWr&LUk#f(Omm%BOg44O$plpMh;mkw&EsZpk zQ_<w`)T9i{wbi*F*+PxqIl3D%+1HB`iCv%^m^1rEPK_X_rkszzolchZhn5To&K-fY za!9S#mjC(zk&b_-;VgT{rgA|^DyH;GdD?hWfa+VbY83)@NY4S*){{cgeV3_o(w&+J zEA|f&x*^YRC?J}kGS3n$mArEMiAB`(2FlY3nhlrI;``F>(}X(;`2Z)=3li8N5B6#S zoZ#O<(6}^!ByUb97&#Tz;(ce5q2gJgj#+Rgd;9A7Pr0g5T(Wk(9|Q11&4lc=@hPZ5 zBTsW+x4<^kxwHN9x9rDt@G`cR+_nBjBX;LcLkLCZ)B-%};z&gqspr|FpX(n6uF+3! zu0+0?uC&{|9Se6VhBKp$Y9f~$ot@+ScKgxu9(aeIlU9-~klo!O|EHT?g#musdIz$6 zSC#N~b_<`u$*-j;a=u`yp}2CqlFSlAKEH_kndJN)FHn@z0|{Mm!0()^{RK5tCP1~{ z{&_UzlwVs710(CL@I~9unQr!-mjP`yJ^qm!bnI%mzm#IWJOx%v&PPK=WD)5{zNPUE zB?G!x2aeNJk<ZSx@o7>NTBjq^$wP}@`)9J!HGiQ&nk$UsVm7>BDKyV-rPgb}#EV<T zWkPDi0fuXr23XK$#yno8cB$+P-}%oL4gDrwV?7{nWr1%ik6*Wk#j9)0w`0X81CI7T z)6(9=8v~h_XVk*Po40&K1jmKPBgZ*>h34|HFq9&j{X}15zijIbS+kZ;sEqPR(tGu2 zoz!<<%#2y#hHgs;5tCDe(uG=u&_cNL3Fo}`BPDkmjN~X+mV~vjX|R9~?p_oJ=Ud1~ zeGGiamv=id-Rv=lmx@Sn<b?a#GfP!P9Mgz~7awYRcAklHCFSzrMN)DbKqytg=Xify zJ<S@<-?A>FIZt@kQK~dk{*a>B6BrN6e@iU+c<;-cF!bkJulzRlC|wT2VFO#aQ6KsB zo{#C`@<w&xDpciMFOB67$P{E|D(`j-MP=gcUu`&pqumO4#9f6u7KhT0SQeolv{xFq z5zY>s&K5&|2t(dFa>H{6>ysdzfk<oScUa__4yU2zo<S!mQ;5~un=OQ=0J?p9h=>F5 zPBO@l5P;KQ<~#RccWVXWvp!{9j(v4WX>O(;fl8Bw)xg`4$sYK$Zmr|v)CH$MIHT*x zOXKut;*2y2DUZ)y17}^*)6WqAqdD}>7q)-&z1VuSN>kXzxbJnK<%sup>l%HZ#la#i z#ZBGq$y3Fb$7jd6YLb(xMV@nH{W@|b)Ox5%iXC~MqnM*I<7%yjG80rr*;$Ps8doVn zB4JEgHlL$iD8^wkORB6TMd<T2@Y?9wl+_W9%<(EK^mUG91m_23T-~ugsmLq>ly$|h zM({AY)Q-_s({@oforHXCbCxoy`%<cQ`f??Wv$yA)V2Kgcc&T64pVN7aVAr>?pVa78 zwRo<sk@Dd`lbfwP-9)BO1RGzeFE}ox)j~gc_uS-#5}m@VkO$%C6AhE2X|E=)w3Mgu z1TSu&Izas_88JH8wA_NC5K(Ww!mBlQ8~0k@!{%SNLy#ctw7XorGTW62lu8IV1clfx zjc)VsYao?Ccvp~5#*s7VHaS1dIYEY%gK+joD8;P}=Pe~~5I<wvQ`s~zRSN~-V<MEa zx{jL!?4T6+k@$FS4RO7-uzcM2SGduSV(&~p*s6`?a@7gDq!8(66rBeNjt+5aLLc~Y zV;9tWMy~cl{N!8U$!+O#E4(ZB3q<`1SOKlJrohBi@+L3`-<+i*eHWqv=)r5+v8$>( zauxW|<0al&C+h4aK?C9)C`I%`@;{c-w3!p&IXZwH_?TTFu?Bmty7YR7ByoA#epnwG z<KmK!J8>f$l!=c=%xpsu75|U4w~mT(ZQI6$5fDiMr5O<gk!I)`2|=Vpl#rH^2I(A- zloSC0iBTFs21Qb0kdhoyy2YVu=$QHL(Y^Px_q(6>`+jTv{&Ou{a9?#^*Lj@Bahzu2 z7U>}>7t|<@q*`c{9NGKId1unI+Bvv!81j?`&tsd1YC^Gv3^?d4<}H?e78VrG;-#LU zuZx=mkFrS+r*=QPRYoN!0fPcPT9CcScSvhwXKa>@$?-XRM$AVXnHc#fodmnL3xcI< zKhHn8<&|R5DF)z=Z=O9Abr>!4_-@dCa`o)G7h?Nz%gNP}?s?kNhs@K|AQH++s}$pn z8Z;Zu1g+(1ZsDvuO){s?t@8n+vXcaMuA1_kFm$SE?S`0%@3Xc0-Q4W|+E$}GT=V47 zM-pQsG-n@}x+kj{*xa##exQ@G|7|dO$J(^{*w{<)^^MJZjpJJVm#4Mp@$0>ajc^&; zX)yzn&i9)%y$A3$XYRRyU>}BzVms4&aR1V(PF|fJQQgwZU3=L>MM<j}`ojn^XSISl zzKJTEO~I}ogEM_!1=@0*Z||2EGzzsfgfj2lF-99RHnM*QdZg=dE$;)*FYH$<-0P{! zf2|WoowLDB-w0Cn9Ua39?pp7fp@<Q}O_*X%kW~zsVxg)Yi1@r{fPrN17p|KYH$(ll z?VQadqz%%*>AO$L9~q^*+9Dn&tfurP@aDRybuQfxD#7T;sobS+aRJtsfRsWKATyE7 z$T6g^DDML?Vy^CX)8V|3Bmc{z;A)UJ?V-??MloCf)D98=ZGtul!Gw;;0Ax7wqOq6{ z`+MzMI2P<vPaweKxYHU>7X^SI<kJQQ=>$e~vvrCB0Vwe7_z1?hj%vc?*dhjcsRu4& zkM>4PO`Yra03;3KG+A8$50o;xh!%MgtCPQyON?8~cz1v}`1tFE1(CCT5K(c%@o5sw zQ_ieYt<M8n6aD(e8PKafs{G_*BmaQu!CHE*q?4pt`kFvqJ(Ed9U~GV2X;sp$t;ouQ z2MaMe8pnj&-uq)Vjr$ddv2?MKsI(tU#o>EJK2KDuCJbe*M#fT}1-u(R^$k-?S)3B^ z*ZPKSOI?i?8e!J<Md2@><;_tsk7KlNgB9A*XwT5m?XQ$2JJXee8^1Dk*_G5wZ1NE> zC&%To%#nV!2o};h%1Poi>LGQr#qx0KhG_XZMQ;y=^^FRoq;AaiRiJm4f=TBgG)@)i z9Ap?ALYU%rZHr-x%uFSxN4kGU0w8v>Kla`fjX7(e@uo~A%a{O4#P>)1dqK)uD^bW` z<S<eo81Bl5Bh1*`K}{ELv6^|A@t7IU`uShRk{ii$2`I@Y4MGu><90LmtO2b9pvtI9 z2kO+`3$Z+ix@Rqsm*!gPsOq%p?`=L9&=Ki_qSD1TflPJMB3|}2K(_|g2>PE@0SqTm zeJ3L)qs7}R_TOTuSGNFF2g<|mwO9?gVrk0T)l)ZmKDFbNEZk+A0}GgOZsW$7xT+V> zkk`(e^;mR&y=MBsKtca7R&wECV#95jz^xGQB=9Nw`8^d+IBVM8n+Mos=?|>$>!KFn zZvVfR<B4wgc_!H;O5CZcT6=#eLdSWZibmH+UjCS++~iP{OZeU-&j?6osklBKy!_2O zL^S9fk{hXhZ^X4<NVyMWYX5D8?lp-RasH>`vtY+y<1x$`IdLHIsQ6PKu`+6Jw(4Na z_A!jf`^C7ALmz5-Xh>Se3YRP<(F%3$bO$%v8L4J8IZOyJV0<om6G?=UePSs~5CV+W zU>1-G=m9z^*6fFm0RLKiaC}Z98Flt@QYREZ-KS2hW|MR@eKzY4zP3%1m{Xb5dx<(M zl#sT6vR|WI&$1Z2>vPctI!52rFjXV>s32jWO?4n@@s0o8&TEzig}lYu7;0|6oZghH zCrslOmp}0?oBDEVnZt}N!LoU-X97++<3Em{MSch$G4EU-o53$gp&CV+T_^qBV`<OV zmx~=sq(%zDUr6fl?yvbYhT_*@-#4#LT{X76?#ePMSy*Y960)DMO4ifB)1~v!G2@`3 z@SUq8ZszILKOvb1pCL}y?`#SJqz07&m{Sh7amZXJ&=tFXQH~Lir6<j`Z$d;{l$e&c zk*!D)WJpZ^I+a6D<dRp~jT}?K+or_Za!rTmibGqeW`;a}Nf#E5U@xncm=VccFfZ<O z<Z5mW7255_me(ws8CUT{x$q$xBH1Z*bfqj2QkaCI`dQA&8Yt}|5at#$2!LE24~#~^ z1kRw8n^*%nRXhm^Ujtq;`75^e_f{v+)#E!JgD>MImFN7~%Wjn2dW25?oO1x29_5dx z!jHD3ke_z51JbU3wHHf|0P$<+_%aPLnRe?x0YmNEqmin0Rz-HSOcd%Q{8p4vdpFa- zR&={nK^zhk1u!g)G&CX6hw$(n;3^C}6yOVz;F-DhZ%gnK*92z^s3AA5{3gvGl}K&K zf1AZtD9S7@y1mFnJlC@!^eAdGSK2sn=g7d<8Y0{3J^OT4i(HSbEd;lp&mTA>SZWB; z6Cy2NH_MF4D`|L{x!GZBq(#uckM{I>4%>%>8g+U*Y|iwQIHiMebyv7>ms}V@UoCP^ z(1A!#qlqGNcve#eTk(jL5Ia-wAJbLHc!bV>fPdU_k28wD%Jxd7zLwl7V|Sn7;VH(W z``tDh(dH#}BbhJ*UZ*_qEac!W8_*T6CXk)uW(M@h+HS47Yn_nGr7dFPjoX~&`?Ow0 zW=cv05H|1VZ0{Slws}T}88oe#s5T*I7#sESI+8Lu7dlXZspY5WIo&Ev+$1wY$E7n4 zN`&Q`#ZAltsrtCgP1J)d0{`C6qket2z;`@Og>@oFF{%eB#nB0MPRP+q?2(e0V=FWo zu&w@0sTJk;^VxXBw>eZv6fJGgCnoBZp5{i+HM_ybgWs@9x74;ILsWq=(arL7m!5Ji zV%CQWL=S<P;iUU^&<8?j1)o}raJWlV!sJp6<l~6gtSu{+;kf2d6nOjfNHE;(K9oi} zd=Tn~JF9sUb;$a<ksx}>Z)Pq7)(WC7cMBJV7Y7;Ngs&d~(``~`Pf@yZ5X4+#EAR+w zqYV(cf02K)0W+UJU;_ADtgjWk27;;NZiG3RhPFn>ekywawK4ykWu>{$b~(EMb4O9} zE!xZPo$)p*k=vqxurXg+HndZG7d3`)4zj&=O2<OKv(lr!D#VWoZ4=x8ytKzY0Q-|L zP?>Dq<B%y{dbgIfQ*By$0pmV(ki8JQC1-X}$WG;Yj1ESce4b1+$RZ_t&sC10O^v!P zZ3Ey8CbRx^J1Y4?V;t;}QWjXWiT{8F!-#BVJ*hVJzef;1LxDH&DX6TFoO<>+y`^E{ zmNZxF=#3BSl+A0&ch*_;fFzP<{X;B+VPuw;h2mSkSFjB#hi32D2u2_2uUjaCUNE^q zm`^-7ueUzJ25tNeLIDxZ=#VP4L}K)3ujX%h$9Nw2$rx_2UR-fi#-dq+)`QVYfdc0H zF;*X(n3HieVTxL2-kvdnI1FX?^qOoSPa+gHCJLv+O-@J@_CwoU^kyk%2{`r*BlG_> zm;lJ5HAQrezFh{NCZ_HgxxMG;9ca75vE~K<2?hQp3<&Wvi~`5}SbWkx;v&27eb|N1 z0v{9akz*dnF7zVAs7GPmd${bBI<Ht5BzzyWw!)z+7xH2dgsT&|ynDA3EvJo>k+{2X zD(50Y<ZMa|HSNY=*>V{vZ3!sNI_F`6;GLf71G)W-gh2B8hB(#Sc#H2#A9+oQ#LQm3 ze34;p+6;BR%UlPtIpMddt{isEImNIc2b(6JgkpU-I9>LCx{>MF!I$1>MZwtaHLmll z%8|?ANJF|et;ML=FDm>&-~cQk+;q6dcVCxVzW&niSX1j|LY~HeBalTAAELve7knkd z*Wp3{=Pc4_2uzsS59Ja~Pk<@eKru1Ikdk5?$*Dk2Sb#rHCjPOv9IeJ@PyHTE982>q zD!^7r>&H!#nymR<sld|<Kz{|7$eF`uooE!}>6-et3?=7E9J|}SnXjj)L<3HOnK<9I zJ}9DH=5q7Rjx)wAmfTH=(QhB-xZ11PC99OL;ACFd&|#@UK3f38tH0{p#@^(wN&3_6 zz98Jx05f)T$%d7Uz=t?J6XkzZivY2;{HZ|bQg;8JG_p4Ur1BeH?tV6+Rnl+%BKAB= zXgDJ;_D;^4+Z5I(j$=o1x&;sueggz6)ILuiURl~bWo{tJavuJ{dQ8^kaME2qo+^t= z#~$H`;K$e_IMO-w&JkpGFb=XKwd4G`a`tX9#ymzbt5d=RPP+7T-@)bajI?^E>rIOQ z$9>8j>!H`eUzyLOkpeNz1PFpkB4P$d&i)xTM<sehYp2bU!$JN~{a~u2{<OM;;g(=N z1tVPQ;~C>=UC_HBA<Db~Xj^Lh$nYEsPX=ne10#90+Fo(xOgE>Amad<pTmViT`zJ5( zZ!7BYMgFN<x`(G(ffTTH$D9M&DZ_`Vpe!GIhQ~vXq>^w3kuoB;$lRk~Syml3@H+NB z2+fc3skZOqxNKNpI`{;81PWX`v1y2RKSb|6W}&PRFC$EpjOeTqc!ZI#Ms9U6<o{e+ zeDgr<rFgT?vB@J}$dHf7<x=SPyWe>oKQn%vq~l>6OKxV2`*A*8*lka#Slx`-?}_5` zZZ>X*mhww5)XSd?A&F?nEtLOj^e2R^$kuCDE3-5so|{S`|Bl%PQ%($h4%PFW1|jAe zuf>Fz5)W$>0!}!-z~Yj34MVB<nP><z=iz7rZsD)4Zbh59f$Fb}4$!+O*w1!ztj&4s zQEVKQ^r@Sg+RriG?L&ji`kjz$n`=sL|MgF`@=4P=oliCxcQ7}$OA6p`gLcW1Y12}W z25WAkR8t0YJVz~oe>nc^go?kB4f0EU)GYVlek5D$zpl#;UN31kX~T+lhP?y%w5EFE znowu$8EoP8!EaeOpE#gr^Bz8U%)?Ve9;bR(MkZJ)M&7{No8T$G|9K1mRW9A<={dC$ z`7Z&;Sao2aLg(O$L3MSf`SXoaRP@_jl){e!EcMd+Be+GNpR(RhSmneiA{mEw0o11b zcT|p;{*e1@L!?9ZPNmp&iQ=;0W1r~Ss=MA<Z$Bi_3-gcn_G@>1OJEY^3%xr_rZ?*1 z`SZqkwiDjUQhrT|n}V4FG$ng7#j#_UMi6cdA2SR8%O|UC=~_NJZ&Mk2%du7&>f9e` zJW%x3;zkqH@3X*r8vL&|)9rm~iC+IG%&}+Z*erP>)U!{%x`OM6HqwgV+4DpHetvYU zdh>9L`O}=b?ui*^!>gW7nrtUOQ<vj7iuroa?~XiKLb{aVTgMKT!LFZqz5^Pla^g=% z*H+*fzPYdsGWBzw#FRv0AYDzTF*p}78)$7^)=gt9Jq092NJ+?9e#lY!vOG};$&c)i z=Q4+$VNfcOKmX)E{^w3$x)ns0zr@NJ`b{g7y>BXm5?5zJ)&}~Wj0aT&4F?g(YnbZB z<uvYfF_;PVMeF&2n#VdiPe*g<(?87DCbdvo&^5-0Ivq%}kd}a0&P|e@vPqEX3)CoX z8pILF5#y=I#8&Cy9fD>TrD!<L!h~l|W(zVDznR(h(uRn#Fnk`PseV%)0B7D*+;?N# zx~%x(ApbjCY#jZKH5(1H8^t|^Pt!^LJ;Jw>AKyX`e)x8ot*ao?96EAnX0fa31bK}( z6xMalp7{6BqCDGTbMZqfd;!ek7YHl1rh-TSG}3Pq{*QFFdwDM93qyl+s9pqt4QPZA zt?&9RBq$`9%!hjcC&9^>bGYcLOm<RLB}jS1G|N7FZ&uQbACZ5E4q)7?FQdfC5PP$E z(@2Em%zWK5n0V?^C~AW^y;7ZdX<TmRTpZy(NhM(ev48wo9ZALof61p1x<fG+j;&Yy zsOVkvvg7pmK%$IJJ-eC=tt#d%hA#Q<c_AeczG1yEl7%q2K0C~LkF%wWLFyZSYC!%I z80pqym{t3w)q!IXcwx6ByFmLqEA}Yyb=(jO0%Rz7DHJ|5f06iDj%1B?DC65rSA>yP zg*PiS@cby1eu(leof+qy?dl~4j-@DssHMlF-h7@wAQiOmIgryB@uddYr;vzQbH=JZ z{8B{-BkI-ILIp0A+xDUf4@Lk35MhfB3-@K{xqO1g7sqIgkR+x90@&=ZG{~S{v(K6V zx*rnZ=i1*(AeVh-M!0Y+y7Sm)C7`icEg0VaSnI;^*eiiP(8IpO5aF;c4?$3WISJc= z`OE#9jJ6pG-8Iimt26qA&jm!Fse9l+`jIBIWlqnLe+~S+2@$2ukIJP>|Gp9bLNAo$ zq|V%!T`p+sT;;5&e$jBCdW>#**d8xr-?H6Z+Lxlrz)vi9j?I$A8R)Sf)!`M~6CBud z&ZNtOk;0E%)@H_GP>T65>A@~@lRgxLrJMw<Jr$MX8G{~JU)b>JPIhHieCu313`NAn z-P|_qXMn5T2;>OKcC5pKtwYu!?ta(x)`-mv-|zH{t#cvkyXn>;N#A{0Ii?R?8cf8Q z`<G|e4H<<77#Wc%qv^=a>aSj)86leRAZ!h5>ctZ9khj1ttNPu*8?bkMz%5<=wnzAs zsO1I{{cs!Tn*!F>{gYDN^MA?uK=yihGIg)EKOg95mg2KMknf23mHE8Fu&O8JW8Ft( zz|+mPo6uD#Bsk!-gjIl$Yq3Mk0g%a+fcpcXO=V~XZmiGE`i<tK!c`%$FV?s<zAk~F zs$i)0a8{H1jQ}G)w<EO9&1bN$%@lgsw_vGV4K?h+eh_%uGvx*=zz-}+Kz=&svR<}0 zfRMbl5q^6{(=h*&+yYwzg$BOTk$t{B0EqEuOc6OpUtSb2RPy<r|5sqodulUzH)<N+ z^(7v-+2wl<B@!JR?&5q%6OX4=adkjKQ@-2X9FyLz1HqD3XYAE;M}V!yxSp1ax?H9e z-CSUhP0&BZoM#(2AShRKuoDIDyP16QgHAE`_whq3@DYpd@+vtPF*f~$N+7jm>6WiF zXDu(|8RndsR=$u==)2zHEs<tZVN6@zurQZ1YUY9r3Wl<bitl-rKec5*a401$2_6k? z<gQK>_?)KKvX7e87k88Ax1sjt#rnv^9)m;bu4SwI$q4^X$o(rWQ6Ci^qE}P7=4A6t zC7zoX>jY({E_;DjX1oejy%xq`e`TEHeN%wlz0WI@<>AJT{Cpgl(X>QZ`LYax$g^NT zCMu1^#Ih1Sr)yCF+i3mF-tM-`>Z9j~t)btPy&*BRsUf%dNMr&Ov^hB3Xm9DQEQYJQ zM*oB0c)FRffFl3!kd;;i-s-YS*9M9Z;@Usy7CpPJH)@!H*eWWAgd=7-WG4Gi>8{*c z>@fQ>g}%0Bc!V&)p2g?Bg(Wx|@}k|u|8m@{vTri8wUyt)e!hP{LjIPcR^*HIUx`Nd zc0(^k168_E+wzazt~P19yFg=u8@coFg8RmDijBu~s7C4coVdw&^Uuyg+L&IE*Lr1I z5Dxb%y~NmN_ZINSs*yCDPr=nrDIh(q61;WzBx>+uT`@2)8sp=7a+>K^LURX$$5~f^ zy5$QKGtIS^z=|B037-&gCnW&9(?#P2iM)`sDPJk7X#eMs?p{v1krCmH31FDyZZSr7 zEqp*78W-OqH@}X+T=;6tION!9lI{2JD`tmrI#ty3{Q|k8b#KLE5e4~?8hPt4O0M>P zDpsq3+tzWy(t&y<-C4SMHe3m%<Juo;sI#TDf$X;EB0js_lnp%=`kmd<3~M#HvLlWS znA#RIzK<alex_7MY<N*Fz%BNrTbAK^R!KYMNh>MY3j~O_;!ZinGZ7D@$T&u^LQ>P( z<P37>4rLeosGcNMS1Ao14zVv|ea?l1BHs2*i`NPVVq-^^FnV57_JeRfaU1GA4}T>5 zr)tYK=+<hAL|O+g#QS)T%wGx~b0m&k45*r2^$_PM1V8aiU?0n8uLb?<Xx;!a;m;p! zqkv4fr+X~_TA{Sz!;K=t+ra3VR^b{GMlZtR#urwwKG4r!h~K|238S701CS56>MKOP zv~kF^=<Xk>a7_+4@320Cy@6gg`ey|x2D*7W`h+ER=>|EZ5;dZ>gVJ;B-8|o#j)tak z&KrAHqz!A4Ic}YAlZlA=p(E3Ae#qX<9f4++gwr3!hznnCyT9-nNQL3c6<}bLbNyea zGoVYdYdlD=o6gO&%xAMd1Ydjmh?z7MG7_BvunN6@=;C``m&LNLIW<h1N?pA9PI4*l z>-2^IsscljKXx{*dusc7VxG~ZwJZG`e~KXggT9Qdm*&OVJLuTbT^=HPCG7L#T`$F} zerUv@uH=>BjC#y_Yz@tk!_#%af{0H(7y2PfyC^lCyK%Yx8?<|<kPwmHO-Rm;(!Fon z-A>yCTUXswB0dW$coSP~qGMj2UGeL^vji8<eL5A)b~0tQ%b<y?BZphbOq^KR6F)>< zkTPgmvC*=A7#Py=QZbwm-Iw1>sQLE!hKi&=*_NsMxD6Aji2s9AOr_DlOgV~O*C}d| zvBMu?yy1Rvg*3Qvz4_*@V9E}0#*d%MvEm;S8Eyu?F#n*VpVcT=9W=K%!Bi}gpmjj( zrUOes<S)a|So%rMd7Z-?PLSZZ6>xQ=UR_>{U(e)L8y`4wW~bw$+>+E|Lqi13BGQj9 zYMN3ZG7Dgm{wF6F)l6x@Cn4?9;&*|(0ZqL8441)!^?4&b7Y=>uXP+-0Mt!4T5ZW$y z=4KkzN6YP8|4bI6Y1AGMHYZ*XjbT1(OVN>o_0HPZ4E%Ig0Qk_;(lJ79*d;E4nOtdE ziMx#3>Mu(ch^M^?_ewN|Pf;r8z#v?60hs~iXk^y@4W>h8@4d&?9oR_5_pqk>D_9w= zJ~%2shIUJwoE{qTg7-VAuXKjjS?r~+i6PIJFn8lE%C_%YqpLIHA&F`M1QQuVEFB~V z+hL~y)xCjSDLOA^T1r3leGRLPk&TZud7Rv+<1JI|e($AW^NER@9If<B^DYxKuV|n2 z40GHB7^&8oOb-U6)f&3H;csx`_TA;dc)8;xHG%qFCT(gcb~~O*cDGNFQnKa0&Y#GJ zOPlg@bgBrD0zds$=_%sgGgKpA+Y8+sS$WyEjFtR|vE6<Ph`$c<nxR#d?$tdE&8dXG zw;mOs&fn^@iB+QT65=0ETkvuoA8${cuO{ZyMgm#8G~y2Ql>7`moiyk5_yx!GoIyn6 zb7`%!TixGW*_#7MYMEG&)iXr9(?b44XW2r13%m6Q?Y841aY~OKbX8J^G|3suydB0~ z`IR%<=k3~Ku|eND%g;W^j+Gb29h&=1MVacprv6xGyi`x_Cak5-$Gjt?Wl^#d)gQr1 zo}t+;7iKF<`HAyX$%XsJ?cRL}j&UCi{%?sQ`!gDMC;4hG1ED9f)B>oi;pYcvgnZJN zeU;7UM}lf1C#&z$JN%FN75>7vYNxJ#uIZ7ID$`-Lv88oPcPJ#opn4yq!1f0v3=_J6 zNm_i*dXF!3DgQ4Z0P?Wp>vg1DK+&6aMoKqwV=Do@Mn0KYX9tB`*GJ*^%}OmTsVG&z z9la64S!3Vd(~h=DK6Rd6h4v4W5;GIf3rV(he9sH4bJei8y4kNh7!^<Y>^`|?j}2e1 zn^|9cd5?EEOT^Lb(_}EK1{;n2;LNa@sN7@c%8U(~DQlnb*M6z?qP`yk>A*gWBN^?) zDGJ1Hgda!j1r6ga?%a)biUX4H>{WmiUFU<r0`8SC{x@9!KYC}}9$_4?H~ee(cm5py z&Jnthw^T_eLeyZ~y>hj1<#S)GOP`0+Oa5&XsjbNU0+{Z_r|iB!j!<)_smM}=`0~sv z$*?=N20)lk)ai0n-gwF`{QDpS$7=?6HUm5AGL<_5)B$(O4`)NDHX3nQZk=Be)LObf zLG+GgcqXa%^G;qzmUb%Q4v7_A{GV(?&!oP7U2L!oz`#dn&3#MZ*k+&CaO!JOzeXf@ zR(`MvI~##rmd&{l39vj+R5DxmRvg*Ie?z#cAXVj$n4=cnOti3iI0Cz!X$`Kk=;n*E z&E&zAQ_JFi^W*21OkKLpJT0&A#--T+|C0YDV2Fu#V0;twxA>Dh`?F9Yu2tB^c3~Hl z$tbx3gzAC2xQv$=Nek54RAzNESmcg98GG#|{G{^Y(~DZbkC_nvoDm`UYq0OUczlGV zhCe<6;Ki3aV@W-6ad!CMbQ@>X%4cK0ATFqwd3GuJ)F6@#FVVY(SIkA0Dq?GH;}3n0 z{GV&}jCA^{PWcOf?qQeSt4N|FeXAIzDU&Zq*BZE0UaVg3>zO3@Q}P|${R6ODmGNKm z>G#U~fRiZ!KuAB}82bmVj#!BOwh$W1$T;4@>v6VG6Cx#kcloq@O1+)(Vt@Hf1RjE> zVgadJOI{u&VaRBNHz3cO+05QIgP2+ArOP98&EC3HZxUG8!vl?X3BJ!~P%UKWVAH?D zwY)^=Z5+*Ne)eed+Ws#SVjFtENA^d3ECObNAX*64Mhdruu|IrUOaOZRrlEudJw=-& zMEAAcyFy$rBeSGCUc>j}*sW4ERd0|Zfe}gFxjNb;uArXaVCD1|{lecFzJlGamr=T$ zbK%+|b`dMfvafcnJNB|D(F=-R3S{n@4V66MX%x|@7DpopPe5MhoC%@C4QZ2e-ks=p zppUVv{SHRK65r>r-{TvU9`D_nE&1P4rQdLX&VHOQ|3Bb>@Z9=n`PTn?bzAG7)osO; z-_>oTA~G52hBTU;e2DX}e;3vcDkkKyOn3C8bnQ8kk+Qk}0esGg;*{o)F~yh7CGb6L zn%VpEVZ>?q(z9Q8f=bmE3aFM&zu?NMP6<9J(o35jbxM3z1aK|?zIpzZKrC&c;Gbt_ zKKB?3!b9L?^A~3YhAL0ai*gY{^h-(d`}F+4(1C<468m$C!8$={bnh0jEn?o1G<<(K z%*{*XK(213cLJIq{PGEX66_Uh6BH2g+6F`xj1Fd&03&b(!6}8A?Zjtm8XEPGNBgF> zzB;FvB=Xe?Zk^}kU3~)`%Sb5W5Nq!dciUrdrz9_lgJt&-J$Xmgt6BJ2o6R!~EV;~0 z9B=Ivyq0!EI}o6F&75rvs0pwNJ!x4fMl^_S%WcW+-KtmfJkc`^@Hjo(o=z{ovn9&m zAyjgQfc2x(ykhk~&){EGJB1%P!0TT~%8MeL2YhZ)DdoiSrN`0zaBw3P3u<e&A%?nv z;V|eY#*c2q5OVF<*t%nho_w~#D5VI(Z>bR9Fw7|uqurSTY8PVj)64Jm&Q!!T?Vw;3 z3U5wa<n$hlPJ`AgJ^XZuasIM^v5WG3Dl;+ibV$%x_p&x~0SHE>@TOi8(ZS_NlCL8% z5u11l^m|o@gHGwH&mD>;0(&pI^w&xCNScAd0Y+sP|ChA~YJ7V+;Ik##`GDDgl}ElQ zYx}AI?+^{J2l<*4e+8|OKZDj^=nnf1kTE#Y_0kg>3U9XDaIeu}@Tj9IzdaKc$HMCM zpq`(M_fBHn<@BDPwgGB7^6<8#R(go$Xgg|r`<e@lv%&lEP-UGqlZ*ZlrH2l)+RE}U zpr7%e%Q0HuBZgKojVlQJc*=Sk1w;RUwR((xzboPhgtIl&k+<hz?zWNj!gZWX5>Vu* zJYuqFU4-AE$AhFxQk`q?8Gsv^s42DFWs2PaG$JUe)e=B~){i*&V^K{)^f@Uepj>-8 z68JFq^Xi{f%RABw$`5uafzHkTKz)+@XSH|6MK47=v|12|JLAASb)!pN#otb3FBEn- z1!riHj*+kN)1ilUe(|p)F3skiY8R>v`It0J{|O^28N14j99f*)&;;PA@Rw?g@c~7v zlSp@*OeD7er_TQLxk<7~LI>v?pOkYJ;3H4YVN{HeJ;uOtVO}SlnjG;DrpsIhwkTdc z3v5wqTn1f7#_GT(;F8)U(C82FN-Wx9B)5>Du9u!1|BSr<1SlHfBt@okW@VqNz9<lk zZvC*^M(h1xngi)1Ga_JlJ`AH0lWCH|_(GhR{|WDQS`64k?(U>(@TE(caR=q&hIFkw z+AmC-O50q72fYR1%W$a0#YNemz2F=MiL-082IN(>8V4wL9>I-qzm<5~aB)&$;~1*m z8+Ff98c^|PmaHM4WK&SfNVIxpJ=cew1otTcx9xRFX~1-jWm`X7eN#b^AIJOV`L8>2 zX&XD{SBvKW7v;T{0;ttc;EsPFi+2q9Tc`}|lCE%Un%BJYS>r=dPj`)S2vED#YL@Sp zE{RSRo6vvXT3&Ej7R;{H44@d?NWE0!BaKe<M3I~Q7V2!tVde?V&&;AQgc;mgdCA=Y z=g;395dUY5SyA!ilCux%p(M#3$43jxT~y$egl2}dvvaW<oiQ_kX*^q$IVto6;GG5W zv=TrFg<5p06-5^l#yX(Jmf<AA(g$~V?RWT(Z2IYb2Tt2F3_!xIXr`1VXAqplM;TVH z$?XE@Sx4Q<uY*=cYyv^JdUFE}3-S>Di#*K{R8UMe#L&<%9ZUTPpW6NHmbdZFF&X2F zFRpT}aPeF72VNdm2&0$9p72`RRy_`H%^iNkC>)XU(=uxy@WcA__~)t(`iFgYm@i7L z<PVa2)aCWtKGQSK`*MbU)-TED#cV&W;BJ2l>my7xmEM`SHa#yNYRH6@^utob4~P7- zrk%chC#lp>TNrx&H0H|q>Xs;*m$wM*Rd`R;SM+l2=HkhC0CGcHkqyW)Pu7}J*V~s~ zlMwp#hiX|LT?VBh7Tc%KYns)*TFan3rS%SWYlygVOhAd=Z38&Y8Io0StD2a>>X_hF zXKne-bep2EZ}>+__Ug?KFuC>5gQo|#H$#jZ6>w`1>+Vz#rNrBZw&Du^ynA*Ir><I$ zeeTei7`Oguuk#U=`E~4lVKVUMc$#b&+bQ`PX0moG|AC3+k)7Lx31=>vlpb@df=~~& zh3Y(wr<d2I-f5@YoEbkWmvv^Zg=7MNU>SvrXmiYn*+a)AczFht;nT%LF=*%06~CZ~ zrC7ZlnRj#Q-(7Ejvf2qrh;AK{a~63&4{nFp8Z@7xqy_abZo9Q9f{?aPx>d{AG3doI zudOC|<x{s9-Xpl7L_I0_T->Ffu<1*qabjPR36FS6CAk3SSONi}?NJjS@F7WA5HQVl z(L*()+C0DBYB}vEXj)B)cMnlkc)aH+;Bx<mI%{e}SH#t>G=|*qlv8_b?R{~ul=wG= z6e$xr@8$is8obK2Q=h)Cle!Mw-5=o3&X%;ZPz0^2Stx$f9Z&16esH<G(&Pis>~)1D zQ<6)ML^srHB{_;CCFqK5xF&9`Ad5luXp(CMPC{avF+&npFuUG0i;ni0o(U0YX6I9< z77BT=>(&N^Ma$acf)x=63!3GHR8e2vF1=uiC0nj%;Q<u5I(Cgs%8d0d8FS<K>8PQy zsEZ&08(IH=#U->tH=9^E8_}ou$}@-Ag^DA--8L>lQ%}*#vvRl#N4Ls)va`+}l*av& z!pdZ5;pJZev47zVqt|#mtfMKp2s}*eJ4-NlKbybJiou4pE0EY95)23_PB9P|qlpa| zZZ6$tts?%|(;%+d`C*O>9i|-1s=_K3{fP4klgazhD0fk)=RFJEF>K9yK2P`L`!4{q zvhOyRvcL2#!!1&=H3B(4TDgz*JNJ^ZN46JK>JS$%&QUjRFD9Yjki)UGmy$209dL?2 zlN!Q~;9TYE*-u4fJ(u7kAm8m$#gN}ccZuq=w5!{#6uQ$f*xe3#mtLJz!v*u#nQ5;j ze^ud+k71)WF?~>2q8nT1LoRHF7U@s_mkFy2rWu&eX1&Zc;X2sAq6^hN3b+hT0ghnf zxLt89gV1~@55j*TR{V|dHVgh`{N}G)8=xO#PLJN5VS%)bO-S&p%0`s+QUGprgEUnn zm175}by9-v54uQ<f?n4hZI#S8Zf|Kh%F8aIxHZAg$%S*bzUu-Ug`b0Sa6?0vTn}@G zg_i}wrK2{4Qg3AKEd#5gJG~-{XX-=h7*A?Tbz6TI;zMwye-`3<ex>yILj22v{IcJL z_?RqaiKHSyHc_U@W{wN%YmBoPxz4Qxx_z51jDNUcyF}>bNIOG+uZdm+NNW&%;?^MR z(@VlxGK@+UI{AW(Dx#&$ru-ddfr(gXi}eFI;PFuGVP1+!t!ZOmBA1p^TO9_UpZslK z46hSk>U4Bl81t6SbA2sVO5QK8!F}ph{4P$>Vr_(1T~5|TTZG>?&MMa}OXlfgYeOj4 zG5V@n#NfE@-B(qWc9g;j(gVhH^KjZM%}6J8d~(q`_tFoN*nBH|XI*VrruW;aU^qcl zz0q0ac^?Szu*ipLay2%`>u(r3-sHuKDW>vR+~9C~CefUbfxK^Bn)Ni9)B*C1!Twx< zo!rRF(A4!NhcR)F9cBV3L16n!>y!Ol$@oq|8yoL(c!I?vxmF;-R}dlm{VaHlJ3Ymq z;GW~Q&EXV=HkrWt3%eBoP1UQ%6HZ@^AWx9?EG8F$tQK+L>I-fCACUu)opGe_OiKW= zGtT*RX~o<LBLhi*%znZ0S+RKx<k$vMrMzbJHLSFSwd49B8i{N>btCuk{c-3M=o)Rf zc(eJ(!nxIFUx$HHQb3#SHvsI8$5B~#P)|s#DYrYRqOx94$NtWElD<O)%G96rq)Y>X zK7fMhwY${Mp%Qm`go0rKLj^Gm_k;g&*Db?!5^XJQY1jE*_TK2kk#qP;inRGGz%OZB zoO<)Jnj@_mmj8CW&;c$x(c75N)yrfulAOm;1W*-ih~%Q#B2IxN234mRh^|>shb>k9 z$`j*&$~X*rgvMJ9pDD4Nog4^gUBi1$DgB3R3=mj+oZgx;`!4W0K6B4X!N*b#C}w^s z;kge6%HgYT-jGQ0B4PF`-N*8RydSVqh9Bw#Up*&sAEJiy^}v!CC|Q3qKwXyMlP8Y1 zDz3Vm{pELt3_MJMy}6L?+~AY$Sjh<Jc1pi&_yTFw@!m8E(04A+tHXX)6ta2m!62Y% zm@F#DlEU-xM~n}42ekwg|NWg+G#^<!S^}-~Q}Q&vm)gJWrFe3T)-NnaWNPF&46r2+ zvqwMIbdWY?9o%|jD=y{e-u}o7i{>2=dwusYaG0;*C)`s0S3;TusP&Be)+<bL$0I2K zi@$z<+#aBa{+R<M^(_J7340)0U<4%W-x4?wwJYx{D=V#KL-E#Qf15oP->O%YV^ZRM zuGMCC=|zr?38+(bmOajy(d>6vNo9upy1rK(>%mEt&FRf*KALRg?_eMDO=+npVxkvQ z^*ke2lmVkmxQboM4(dq<zOtM^^n0fRIodz<b|jYon!FBT;EQFI);0>@!yf_e>;99j z?R@pS1AtmV29V#S?@>Gb^O^9B)MRxQnd`t@<QOxFdQm^5l*xQO8W#R8iQcBKE1Fgz zzucT>?(DIRN@$51Q~T7juT9Tgt0vTO85!!e<vK?;AFtzA^V{zS>rKGiG8GX1Ylu&| z7yZtQC5n2=QF5zZ^8tOWw1{8-?LS#QAO%TiCl%^?G@-=mp*ZPA0w7W`SVnm|_bXL( zg6yIyp7Z+>c5bw}AJfX3$D$Q4dL_epy(@tSu>LjfFEA74QHs$E3{>jp_DRHU`rgxc z3oc`I5fMyV)Hk!qPri~Z@jDs<*}CknYw|z4nz(4@!F?dJ5faX$zVt*jA1`hgF!xd+ z=whG`KW9(y4^RYY_Ld&8PaIyJn0)k6RY1(J)uZUv$+-hi1ZV=}cP^e#<yjWT*gNs6 zyqxvM79Yw*^<#!TKBWF@`R~+<F<d)c`kKS06q_@{+6LhA=BB1&@@|Yohz`&&lkM=L z3*Q#a7G)P;#)Zt6Y^TY7_rD-Gf2Pxs*UosAM5RvM?8!`sOLLx3NYZ$-R#S|!7p5UQ zZ9v>B$zOsLmz`z932X-6WGTM06TTq9Q2jDx2ODoe15o`b%mM=aZ<LXh-Et9?p8Vdo zAQ!L{rFG8fEeqvX;+c1AAXK8;`&y$6Wk#1aQnUu_O;nxGAlu@%HFK^CA}lE#QQamL zFC}ZK*e0VzqIr>Jj}hrC`JLaV?f?Dhg08H7H$x+Vun4tnYP3zS0y=;PdK0=3ZPCw4 zDqlVM2O6S~^MzP3PK&_$L1A2UoDgAkxSdqeu)&f>K>+dA^)k*a*4YANd~nZl=;qt_ z%=0C5^~Lam4_B&Fv7Ws4ryYK@SPp=$%@s2!)?9`<k0q_UZ6zCq@xREbfStW+c}(G6 z5`VC%J2Vx*aO6)aNadZyE&s`_*1klqT6ivdo$~Y*Pi4UUg#Z^SE|&*cA48ws{9h2l zzk@uxD94!IKbYr2xaP!NR0#K7Fld@2&PK_}G@Q|t-2a@+1^@VYUwdVxMzuSW0t`s| z8vd>G&B-J41qKX+{;^ZjcQ4n0T!f`-&W~O?yybG)g=~Gd)BS5sNE+h88j(@wx#j+~ z_hI3atLOvu9GLW$W3Si`^;rb+2<hwIWiQ-$yoszwYKFrCQ*3Xyxn4jt+h&X=9-U!k zB)*G>eB?)$<TJYtsSr93e1<^^4btOrLf{!gWZq5;z=6X@KzG0<h3KF6;@`>jt<WlM z3DXM>9d)!ReNCF?D=z|4zs>Wne3uUP2(l`=eIm>@YA?ntk?fOt0xIawH0ic%l?(hH zN6+{reJWFv(3$`|(8Hg*m_>FferH=CxLjfb1yEF3_ja0xzA8TbCSX%a1r2WN%s`<I zCE|sxPqLpjkPSjlmUFab6=g|J1-DSnphmN`UEP?@hDg>dl1aS?*nYc|9E1JL+aB(i z61kZzRE|XASVl-yR@Wk<b|f+WA-p8@FF^L6ut1jl`q3}m!n!}H%hfQ9963+~N`q_V z1yC?ju~3}8Xz*f4e7vU7esXhjXY9?#PAW!GgVC7qqky0J)nQeQUs=BC3EuUi@5MZe zTD-J70Tz04ME>)8YNvH#DorkwR%NCurZb&TMJS<FC&LHmWN<=UBPw^Ee?i0_w<g;k zf4Ip#^!31H_l!})SnCw?SpC+{CBF%or*0A+RR=U{SB4yrT$v;?NSW&(%>S3AQo0o# zED)8Y$XLyMNPbA?4LFXB2#vM+)w!RiSf{gwS0@7nIIT{<Q0339OE!Pv9<DXa5V1pw zdsD&4U;Krb$R&5*LH2l}N^{Re!@?#lG|3=imTaW157*=Q35NJH3(iMaFr{olVogSz z?;SIbw#!gu71p2M4?!me><ruLrQubCe)o03t-&UQo)p$Q#0$k<xmOzE0}n~t6gJOI zX3Rigy&v~;pUb^+I<?}*ZoTcP^dB8Lq&Y-Wv9+~~<62>j?Uw<m%Ks7-JDhzAD*5y$ zJDyh-b<lHkXQoYRtUZnev=y)E_U#?1Ose<4pV_U4p=raH-hRFD+~8qfc~qA2+$h%P z;#P8;mh>kZnbxxD9J?LVS&&9h6$5)6#AD;~+F<vE%wEA+2W2J{F}BI4cTP1DF7)h> z==jItO=p4m0u^AIMq>0EUYMg$!Z^$^i>q6>qNz&S8v2VwLRu-TbJQ9R3C0QfA9M7c zdRXs|N=oGS9iZribdOZ0Peex0qmR$r97>7{JN3lkl-8*HLr^=nQqEW#Oz59o+IYgd zdyyM-q5skUHfkGhV_(VnILI+N&Fw>%P=av~%;c_k<+t~y-2+Y)<k70d#ln`90zDmq zX@!{{14Rzyg_GV96>lsQ<-SONVv=}VJ8@lN=@!I!C?t)x{KTbKLd;w*z1Dh=<4A$M z?-CvZDZBV+9kG0e$~@Es$oJ7R=M>}4{*HkhgC^WK<Ap99#a+GBPP;q6bsxDu?}8qb zH0@Pl^b-1r*&~k%gg13G$WAAUH?$~SOEh4!x)zO2;~ht<hif(7w%JIA3Lms?$fthX zgck^=xBD28;I4k<v)@Dg)CUXYwXw;}_2+^UAA?!DkFIO(XvsY6_bavfTcCOe!%oa# z_W^Zm;33dkhpuNH0HXK5o8q5v!+(_$*czGjEe5Y^IocOr`J&F{xUzT;YX0cX;}OTV ztCLsXJ#rGgg$A4_J{G6m^GR4N?qPRmT)$op^AwMH(;wPv_d;@?)xP!p@tJj5nJfK7 ze_P!LVR^OhoF5cioIzk-DKC4@7g|=I)$MXdooK^ut1R!L&eC?~?bv=)5nH4y;xZOb zn_fP;84R`(*^^aIa5Z<KGxHQPgVXoj(K2&xH+1YZyT3~w&I8v%`-^IEoib;BfU(VQ z54GZX4h<Gr6y#>*co_lGOLCo_LB3uLE&}|8RKFvejBal^?N>0Tcg_d-^{+g*yK!|K z6d1&zCyX%!l|nJTD@JLzYf)KcnJy;xiJItl7z8SY`xDN1)z?8J=RDuxhpK73@9&b` zUv;W4Qy=u_>xzVVPuAAj^#(lh=L+3Ic-@N@?gXbeQH{4e$(`V{pUR?EiM13kj*Z+C z{n+YwRsMsSg(2<8I{ZwF=8I}Z1t_AEa`6-E)>@VQQb-tUZ&s$mFb9MbO)pY0@$k*v z+bXsXFYJ=99^A&1h+(oReySjPwW_-$JB~WeEG^|ioN-N5r>D&Mu>G+0ze^WlH<a%6 zZ>#&`Sr~~l5ueYIxVU1QjM~NhW==-k_#4`pwJg|T)|YMLtHxQ#x~=%5(<O$RQ!{EZ zlevUcTfGV!Hs={5X=6XJLL{|p@)v`{VbhUq-XwB+ylsyWj)3p>AsvVQp!o1_5QZeK zoIeaZ#%zB9ynZErO77C(vp(yaQx%Auvy5T-vYtnDSOvP!U(j5tT);74;0yzN2Ta|1 zMA1>#Bml5>5zioq`m<8-1M}_3B1yXC*)C_5owZ};C42=oEciL)u&X`w#G2ni?j%!# zi^<cWQP&~!a(yc?8ud~`WLq)j>8y-S(GxfT*jf*^s54aT!HIgC{MhvLtNcoq?n#e7 zG|sv4Dm?Ty>fWKw`NX4AVoZsq1EXB?n|D)M6c=Tuev>tr`e`MFpgpa0oR6}aa{ErS z4I&O>1pxEs3}Wxpgh>ew5^XPV+vGPA!I_<gQZYwlBSWGL6YvJ1NLl3j*{=WM%CYdh zwd5S}xS!qN914@MEz~Menk*$n)~==IY=E3|3>{8}^e`38ZenJ9@eCs_`Tc&r)ONd6 zSgoIAo91S(7FYRVMK{i$Ct?scqU8EJ1zjF200Rtx2yo!xb#0dEW4xURzM}hE`qgpc zRe+<z5ARaW7{`;0A0N+FjtTL{7HAF3=jwO$vp;S!iyAp;M<gTQUSUM%G30Z%98QU2 z`tmYqDm$yjvV%8aifV!nGBq(uLbh8DVUV_!1Llyy_Q)n0a5h1IxxP<c9BTkUEygyw z>_MR8Yh-Fh(wm)O%fEn~VKat7IrY5#-L#-MYZTK9-i_?{tn(`{=Zn+r0Jo3KufN)< zYjnB3s6o79+&{(91QbVVM@bUc90QitUe9X1&KCHxyyIS-JD&@`=#II1wJZ4^0`=Ja zTjP`T=A)*M-<K49s^{pGpSF*}n^2fE0jV~2|3<mCNKZBtdsaSbhEhL4G~y$t5qj$t zb?fgFoUa8Byde3IE&@mMYX*Vp`X6((;t6t`w9aHnU5hCy$qepQ#nv>OTaprw+=Lra zc(5>8G+LYQEC)wtze{oB<;XnyAy4mglEy1;VP2Kc(&91pm}BnQUf`!=bW8Qz`zo=G zCiOEG8S5)xr&9MijWYcKl-ORxZ4?SlViDd2MU@|?U8?AT7=e23X-+0w0%VIL^Df`& z)4o2r%&EG+j7NU%S_*|1N&40tJDX=keQe?m^szM`SSH9&B(rjc7WbS}7Dia*8nAuU z(#vt#=*c+_CsNI_i2rHK)H;i{@*a7!cD)<PBDef)79^eMRxJnmpvEl3xVOpB%wplP zqo4D<Xna+sbB|6zg#K4j-2eUie%VcuX?yKmPilo-^}j+|@dQOk7R4PFs7jw}M8JnN zEMu^`lW2@9&<Wt@cYPMey1wLU4hUc|^Yr9!*}KNWu^_2pC$M@@{YRvEFU$D)+YOS{ z43)$4-%AG0%1t+AU}dh$^1e(S;kVN};E;WQsbCIeZ%D|xbT(vQ*G0H)ag2WbT1txM zinL&HxnAJ?UG>nXEI|GMh(M|TrnD=b_;83$y{h@L!|?hzdIvodbg7=@UQyjPDv~oy z%;LR$cJHB0d&Q)a$ao%4tGj~l%4hkK64aQp#v60Tfsw~$)j_>%INpPdgmBAX?6q5= z>(gr@{gowgc{`CWtd7u5?Q8(A`Ta-Fy-EdldVDSne1Xz`_{i2Z>6@d-q=oZpf!MdG zzacuTTvW$HDY&saH^i0php1g2Ib>0#zWq|H&Y>;m)r%kwPCsdqvRS#BaeIaIWwKp6 z*Mq*IAvn?aTBmMbbWTDy@Yza$xy^^ex>_Aai3He&)Z^5&-$Ij(KTW{@Bku(CDm(;z z+Rho&6&Y;ZYczdM+?k2Mt_3jWcfAdsV#%LW{T}K@@LrVqxbCj`VBJPxI$Avf1bCOm zC4Dmif9PF8yW@-=B}CMtHL@}enqFqZrKLM}n1e!3QTK2ecNG=hDn7~f&KmZ41yg>D zu&GWuEcx+e1&{P3{Mq*RZ?YG~P2B-muX|65ujQ!6p<_MK`+($v+45Z%`$?!dii|I9 zlI^aobe&|~!}g94xfhj{*%Is3KdOmiRr`J{P4>0cmIo-UHZNSrye2s&g#JdpE?9k1 z(fc#=h^?gawrY_mP45+vE4Mtmb8=#zzfC;K{?2=)vKkBMMb<$V8}A+x(GVJ(-BBpS z(09C$2FS<;L+Y@sQ;96Jg4k>MCel|tVzoBf;{V=EDYG9U7cNv<_fmJQEfqSQOw!?E zLY2x?eSKU%ZFee0A=W>Cjw_r>y0Sbl>LdCwr*+>Tv}oam*o%mZfHrb^84iK!U*nH; zq(rHy>Qp+qIk*tX7eIL4T;q^dl}xjc<w{Pq%t|<}km7ik==(eyC@}XpP)w57UCbC= z%Az_KNHR&_-`Fo3UHflhu@9^B4c)Q!<rql*K&1OaoB7y_{}brZ{ABq+GpX7$S_Ett zv6t`pqaun(S$qI09TCH;xKE;X%>bINs$!($iI!E}-H&>%`SvIE(&$`>Cs%n%F@)w6 zVzfQbOH3i@Pd(KRMNq5}JG4BVAO$-95&JlqvW^l-Fs8C3DF$l<U#@*pI`wiGu$)ee z*^?w6Wnq}Lt0Odho)feh91#R3oavC9+(A|%`<wLJw}%-mMYc?qijeNJoU`7yaZtX0 z>zeW|O;_;(`GzmK?Y&Crgezsn<%lb>`M~GljTuZ3dCePfgs+A8$w`ITLvMW&;A!_c zIB!KR$gtE}Tpv8QW@#1ZFc96N>uUVIQx18CoI~y-*^oKNgf?=n$E|P-@@-F5kbTe$ zXcH5LrS>MMPI@dY!%|k2aQ_-!cazsma=}+N<_E~vzQTQXAf?(#aSR5|3A|&*+jX^t z(Lr`dpFb0~!rN>GcJ`1M_1))nATVluY2h3&y?9)A!HB?rcyDd`4NFs-07&QXaRJIF zc`5F3)}9_nfMBz%j(D<5GIdPsaga{1&6pYeK5ys0^-+HyQ~Fx(3YKhusH4~e2$X<J zcyfHeoDLDq)XEV&5<C&a`uq)PiNDy(2$P!VxfVQc$3@JA&xO*esN)Y?iW9sog#}VP zXzyq{+5OdAo>$2ZbFWXq+aBKxOdwJhITEx<Q1w6wewzr;YUnv<>r$Nf5J<E=O^iFJ zgOUUiI@m1F$PHDtm*a+GkEf1|;)NEJViW<D4xt1*YQo}tbBL*Vggt|o56`Kgb?Ip9 zieMN5lH~&f?jf?Zi>J@|kFU@2=q|_x19B0tb<HBk*ey#zmF<(9c#zi#cW{nePqJeU z{lUOAGV}C9AG;5miu;X!oy0$J1zAGQg!}I=^gpz&>7_Li{u={`rW(*QUPhV*p&5eL zMl$Y#B|?_ze{+BozI-9(+W<TvW?kFvrpK63?^J}B^eQ;}euD&Y6}dDvhf+bUJukp} zo{LZ(fM9QZ8WPv3o*b5<T+A}BMorMCqlG#TF3LF+N;#8cq1OW=QXaT(wion%y>M?+ znt@G**Vop^Ol|g>=78yIIr4}5`P(Y9&i;jS+9`fgTLKrim<u!OJ^Z4+9^KzBlaj^I z-)6=LQeBX$V>k@;Vomi4YZ@!1Rnj<^kM<Vh+J}V4MeLfl?A<X!a~wTukw|lMBFcB| z9oc&1mmIumzOV_R!VJX8_jn>@V>F?|D=wl=bt5%n4c%6BcmAz<{+~da=r15mux|gx z<CcI_(A<6E)dtl4=@%jc3(GQ4Ko?}>3R~&>lG<kO_V$;B!}mWd9Ik|)pX(GC=Jg?A z(nKVxJr#&JuL||wKOd;7buvXR3vOPTTn%=V=-^}6mX3F=ktT5rALuMqgk%sQ#;gDU ziB>;Z)B9oBE09FJnq<9@gADa(O4hy?a)!IUD(a`9T;`rmkTdbzV9NHnpye3HeW2g? z(dsLXr@16sqHo&5e1!{Om1!+m1$XEN!C(E}&HP+_;wB7<(z1Gq5za_HxEDY<*-qb& zcA4c{Iok_)^WrqGP36=B`3d=;UruFf1gs@IDYXDRg8yIs40s^!o7vPOZYo4BVLg1_ zRWxcbg<EZe^r5+Fln!Fdp$);WK@`BW#aX|b-*gTS!lezoLo6~RrqbowJE4z?z~|h8 z0q@a!!~P73kcb~Ur~*jogx>%K<C%1re9fTbT(ErlH1ZiQWBDUQOZ6(81nXmHhcOjK zv|i2n<R$6CA9hP(NsGZuCTwm#Uhw>QxBru48)(3;tI-cG?$Q9<DP_fx7Q>YW8Za6i zQ<P;=1;bvV%CEaHDsdd7BRS!B<VV5`V0&(IZxG`;M(5$QV;G`v7+c54hV1(jQX`i{ z^HZQ{kUC>Mu@d0C_q#*Ko4<&se-n}cfCX{6jf|#hHG2i-hDe&%02HBmbjmARo@V+) zMsxwbq!-cueWQni5WHwCXNU>?5)t!;*Fm}bOb(+t`E|ndomc&H`SEl@9)?%|Q~_KF z9=@T1$nSP`Ys!SAi9aEh5a3g9^f%~3U2ogPQb<I<8`6<j=crLSOM7+9Ry(he=6B=- zq*YIMuSCQ4-R%8a?o40XLScDC6Tjk^PuG!`)ft`{0!&7zmUrFjsST!{A=#ueDAI;y zp;jCan`b$l#`|BYA|Ge@y0uIq5rq;TbKo~^_>faT{apJXvF5U~ht=u-;p{5|qFSS_ z3F#D28bl-%=^ScAN(Dhg2?;@BknV<|1e8*cj!_U$0qI5<LK=qdk{UW3I=@4Cz1R1B ze|&%Zqn<g>bDr3H?X}h>efYQL`rqWUeqQAox1NvkJmwDgEXya<CMxTF+#FgRvqoHe zWEhp$cdjXQVdJ?a+TcqJjRoI50g2Kn#K%8aqcPjyob+q=&aFW$s*!RQ<~Ig_+?dmT zh=f<cj!IG@v~wuiu4wZ>{WF-~@8G@5r>c62=Hp980b|abvw0;xa>cKHZ3S$g8ZMOz za-|!OH}fov)gDnw>?R2m$n!1iT&cXnfdeQx=yF3``=0*{+Sw8AU4W@in>m4>Zr$Jr zDqMxFPNam`k9zVcuT=nfxrF7%azH#JJjK(ziYA=@t7hV$TDs(mB=Vq2`6pd`7v6~X zFT~6pAc#BBE&n67oGz|V9lm;d#ZYRvXFBNeY<t0e97y=*-G{&(T^9H<zs)E?B5Q6J zmx)I12N<v@!4Q{b+^3LOP!ZfcvD{EZxsi0=%vQGAJ@wqEWd|`D)xU=Fe03z|H+HWN zoTQBLy$&!FD%b!5aRXkryl^v^TVZ~WoB{4c_;f8h)?<=V(e;4i!7PzUjBx6ks;IJF zgsP2r^di}m_K$7=61=p>tm~SH$L{#CahZMxsqop5(ZDzTrGHo!U^-Uczb%w@#PEWJ zp=lC!%ovgCUUv=I@6!H(QHI{J7iQ~8Ly4r1a@#Qr1*_&*HDUvv#4INj<^Rk9e+Acf zy3U5!1G`KW%>&e3J>HzZu|e_F!)L?au}rN-xj%mh3cWS=IZ3IfXWdvXy>#yj<u=a> z?_q;-f=xXRd2$^<|1<nr^TpoRikHVhp%x55RH5TP24gk6s&M6xkPU7T|9Ax7N@y|= zM_WGy1mDBh9!=NZ+eUEkv2VY*7Tu^Z)n)QvzMow-@g)miSCGFW-|}Ll;$s_1w@PoR z&Q)GgR}pg6rFI;b*AcO;zi^eo?n#sVNc)NB0?XSxZ+23yL0&O3EbSu+sB1j9%3Z_O z>$Un8V21^?(RP`KWQtZ%2eikN#f;E)M!p_*<*()uGqH60a}$HgleO*oImK0ytj$#_ ze19iF3{@>AGci0#Lw#xw8C8V?Y`U)Own`olx6HsOQ2{$||6)o_zHRd~lF4PoA8l8| zdzk0E<WDe~c?4QWBA*SPul8f-Jt0e}>T0)bG@9`gfi5Ieouy%XaeEB@J-UsmySBOL z`xRbXt{84&lBG6)V+Oo{Oc`xkGyUpy5$KxBvk@!RD1Wvad(}<U2*wRiq|{K@8ao_C zP3$2kxb!@B+2!W9wOn|))P|LY@jCqhUArUDEd~`@P*^ot?AJp5p)&I)Y#(d!_)@e< zq#+<9JUqT+I!$#*opQuJnwRLvd}DvtSBx(L6(Mf(>y2LV&IZ1tQb|R;T}DOI`0atY zgX-`Ttl=bG{6`L%H>{&dhrDJAOL^Z89$s)(nMfV>70RWWcWil9%vPtuJg86}_-6KV zs32CxsvdK5VONQ*(@cKM`%P1wBTy=Ax~Vtx$^<?AV1m*_oLB~*WDF@wS~r;cAuTBU zTefl!n1nc-uu7Rk{M|2W@mklD8{TyC?N$F@?Rs0m2<qblPL9I6PfsB}vascOy)b3V zgh^O&3L4bcpI@>3a#tAJ-sppIu|yx&EO_)@Q)~b-7NsKoV0BfoJeS-pzFl~vRD3v> zk^Gu+YQ#9}J+Gx`i`b@J$#zFsz}ln^WQ9oG!6cyrI?=;CK1%pp9&Jh6LypF%&TKC+ z)%Pi89*W7)3<EqnY-?Ka#u1w5c7nKvDAp0qBgHYup}LO{N2fP;Ls;}jGH{s1w^;%6 z3VFBCTl+Z)+<tR3e=j@9u!I}o5%Z5)UkgV9PR{tEPa3kM%=1@6B5cieYFs|57&NE^ zw7rOY9pfLJTzLIyTUf1sl%F6+1YNcPyvH-#Se*pV4i%84mbiYl=0N^HO{t46>0XAo zugVwI4jaRtg#P<0ltjv#w9l1x4?qv+a}vDk7*0XHiUu4W#=^ucm;7rXwTC_VRr=0b z)D_zqQt`~ORg<fPWJz@IRp*Nv9?O#$;4cnSV;$l$E?^Xag0?-G5eX!E?5kB&$Kr8z zCHOl&?OV9d1{rywKd9Bd&8uu6!+41{zxqRujNcAUP3X-ir@n>#cpCC<687Eb0Kf*1 z>Kx{oS^GSjHDKK_NkfV*odH#rC4r0XpEzjc0CE_~th*i$vioyeG}33aJt~5l(UZt` z!3rsqUpu8fRqvJ<-&UnV@jtj;07#*_`6sJyX(_79cA&%jm#>F0hk*lQ%MWc<jbp;) zW5!JK=M<#|iVAv0dAsY#UkIsb>nkc+*N+nfOb_lBog8z3+^8>#_zRT*l`6h6mLsky zYlnoS*^SVWAe&C<OgE`7`&2>8A^AC!z1u~>iDU5#ZmJn=H#pw?5G&{?R(ZKcw_=LI zf4X2S75`Du(1x5mc)%h`zj3{;hcBwnL#v*w3Y(5{!=2qA(kfkm;V#OZ#y0^+j<K%F zo-=Fd9_zU0yI9dmIsqzWl>>pzlH+Q;K2yROb3}S>ST46O45^ycATm%WnayXh83kl1 z)PbJd$eafPIw<c}ecOb~%N4AQ$M;#QkGN7M`=?VRUJ}}4rj%<Xr}$M-ltk?9k($vY zU;BF{suk1vfs5Nh*oGhWHT1N+bSw=%D(!vL@R4`R>?$jap@f}=Qlf#c3j`RPa^`2j zGIk&ws<Jm+<ioStI+QmaM+45xCB{lOnK)hx6wLYmR&3>92u^u@NaKDuFH&0`s;^<i zy{P->R;Us6lkS3NROn(}b|xRSmm!7JlaH&-*6Y2$Sk&`RIATrR-{*hfQjyWdUavkJ z-gi69b_5+T#)z7)u6K9keO;GxtttOCw29Wl=)q|9lR^&a*ofLl#w+f65ZkTi*^!*3 z%ehQbsZfP|dIM|!O+3vA?~$sM&#;=Nn8V=WS@9TJJqpIsXccl|3SGXJ`Z2}FW}!Mh zs+6*LC&llRd-NaK=!pT$hPfZVdONcsuC<cF0p0uu?SEm1fr$zwC)i=^rQ@Z0K?(NQ zFe8I0oV`-tQ1X2n7>-8vK~@vE!Oywyd~roZEi6ZAJfkv^02R_jxZ6Ib9!T;YEao|s zmB@rs?WDwzPchZsgQj2Z<{u1X+U}+f^{j~eEJN{T8&w0?L1(`@eZ#xc4g0W92X-j- zQzIpZa-a(+s;Tmh<NaB}t<r)cP_Qm>h|L%P!bRLIX1%d;k97q$|3vK8Fa+T^J0AGf z^(g718FO0E12B-i;u)|=04FhEK84JujWDLuzp?Q-BFp8*WX3m4qQz;ndiC+@OFd`5 z3tR^u&b^$=ba>6^<3L{|6<~s@0GHHc8lp=l@tDWz2qHtm(dzW;8ZVi4%&gN^f%z_s zf0OY$r#g715!h<^G=0*6FWy2|b~76lZ%PMGQ#p{OapZP;^)!9BX3+E|WaTWH!DWgf zJ$2lTov~y=6TKC5_(0(r+Y_z#{osbXi5|=5w~QjTK4%hZQrN#3o?nRZ?^i7Ee3`<b zZiYfQUY{r1MK){asg;+#hh81MaEdvBUy&Dn$sF@ZVh*`aFMmONh-_Je8T=dEdyky1 zCUxy03@!dDZ0tL*`R0dExm5v_80GTGA@;p#?Yp@lNh01UUp$o;=UWQ6E(4RKPo35Q zEDjfmTO^@W-279@pX;mf(!Eqbar^^Z`=~jHe{SXn9#i*VPUM<rR{p3|b?-rb(C1H_ zkx->(VI59`!o`yV{Tx;R=3NGH=AYfaF1L}ZN~w-#y0Z0ej#PMWUTJJaZmQ|>md*@J zH9nP2FtEf|N%Aev;mM;$0q;kgBAifk)_gjGC0xR#xLh@~N&-5I;KGP5iqotLSoiGI zr|l3#?XBhk*VornnyP`gxpe?nr{8Q|M8T3GC)h^+o;BIX$(H`#F{}qK0(sv&uYXp& zjoF88iKdG^rtd;jf;k|P?xRH0qD=(NjQ3Ix$z8eBmmYn#-GC83xO*~d7r4pwHyin+ zy#QR2#YvC9Ejl#y_FwoBX^w6wfyn!#K7(`oXeR3%KYGS8TyX9JLmyvkMVLS^f^)#W zRu4G0)Ph#uL-2_0LS{BAzIGZjPhd>Q>OJ7;(}ZVx2YI!jf>}<39pDf9o2S!okz11Y z&wJesWIwTMxq1*^<U(LvFsIP#e#%(VgMFBl(Zg=p?8!M{KYJZ|o%?w<51;sXqV+#| z7?4+X3&L;Ffg-d@s&Rv1>tYbUu+Bs10s^#NxT92?62R4ohvT_KO(;&l-~{y=%DicN zdIp)8&NYh?a1x(5`p@IA^jnk{+wb2qb>g@I$n~-5?na0QmTj``jj;iu3srhBb_JlU znj5d2yEkaVy9U%s*CgI7W_>XnH@atCrH7V1QwApwhUx~vjDMO>sA4lgnW+{b@bQ;k zPCy1qaFArvxQHeA99;?Pi15JAi8In7li#}v1DOw#gvY@n=@xbIm$`E@n&52kCiqab z&hs>@V{%HSeT|FPl!^YgZzG@pn}iLsCvaaXG8}uYFsGM}c42eL&ybCITVZsFa^Ovy zarfRSU{M>!jV(lky_WA-ft&EYp*!wqka1DIU|bo^4acG#ZMKUr;K)V5Hy4bN*6F|< zZ*d#I5Q=s$N%lm*Nidl`u9T0q&e>7qaBuF10JOA=mnwUIYTW-X>rHXr&WbSprh5OL z_GmPm$0DoJ==*&9U|6#_f@#V-g&NZxwCJWv3~tU-?l3lM9zH=0>Ly`qXwfQLx~4J9 zDPF}f$GiJdZF1%lqaulx?q21qB5BYSh1eyD{Qx=}er#K-CIcc!_xFGeWUo^xfP(*@ z@8eEyXHtPPLPS@6sZlk?V^Ym^3Qs(8^|GGuhaV*_=PVscjZg@N?xhN;FJhz`r|P7i zA^Fxq9qmtA%P|*K1;-n%EhKvXl!{-qb<M^^VnHyJCN)sr0p2=ZSMoz<9&Yld<&QB_ znTgtkEj8!v@lQ1zMnPBFDCjJ-qjXYQu3u~g3fa@ctZF84s7TL-jbJE^^?5LllX0Jt zY3dw(pOHP?O#fKf^M-)^!lK0|U?x|>E63umnj&C;4Pv_2@E83Pfsxlkswj67o%KEO zhP5^mxw+d3L<a%)W56%0viXluN>c9&5olXbg0)-e+r%k_+%J-6hXFgMK*%$LLvhm4 z@39&N60C!PyU33T2u6`PY&gD4lG16m3;Z#6{q%y^CCpafPIsR1bL2;gatXsv%sl`d zkhiSb;fpB83?mK2XF8EgcFr%A+Fw(*gTBIuxR>EJk;UaJ^Cq-xmZcmPlfrCI(!nA7 z*i{^Z4!M_3j6b}edVPUs&+C!scfIa7Nq2wdy1w<9x~uy=_NBzB^@n@BTN1;*ZY5+C zGHAsk;^H<zW$c~QO4m6S0{xiDU>UPu-+sb7gy#a*m2zUM?RHcWuIrs#v$_6mHj(c2 zypImT-uI4av`o9-IZ5A7MwQHQdZkaVmwO8fg`j$hiej6bp2Xb_TrkRJM0LY85m|jI zf(!o(ZAIsb^bPq$J`aoVZw@jKa2EO<tGJHotSAd!k1c(B*zl$L@IezK*RT^v6flR; z)cIY0&;(l$AKFEsaHQ4rkEZ3RA9|2j)5>mq1*KmB#5msmyP&<F3NePv;`7<XHXlAh zEhma!){Gl-EmCm`)RTKfW-90d?w2v$Q`DgjH*<=3`(C%=E<04pKFYtGy5R=b1TjAR z{jo$(Ki1%~r7StJurA6&X{l@l7pPAEZ_=DEHz4B^>Gvo5iJ@DoNz3?rMc2dV-^9=t z$;&S-@r6Mh?YZ}FM=6Q|(zz!c%r{~CGKZ*%Yayt8`1*Ue2latFFXEE>+tL*2XI_{c zHXnY1y-t(Jt%RTsz{%2}0#jnEyn0Tu)>-XCb|9c61*04D?(Ax*1-M}-^Yd=<_N4;< zjw0BBV;|&=KLlYb+d#&?7=l16kxGy!MQ7g&@XI4RTZ7`Zp7JA?`E@o~t5(VC{*Q#N z_kL@ow+33l>RZfIvj8woh>j)~okQlEedJ))<ry978xkb<nhmguH4X4`{VsGi%mHUQ z8}Y<7z}+%%yHLi6ep0wH;n%JmHkhO(0iXHC24Z~TyDmupRtk(lMk>3B98=k7Hsq#w z=9=Zg$|?qj7Ci%=JK+I|gdL!!$)+?M77?IYG`ux86Z2#`0M1Q~BN;m*gujdVEB)%_ z-$!QX>5<9xZb|F~bAz2=enOKZtxmsuB5mC^B8|n81V~t6!{it-T3KGmSKp$7l0(Zx z@$T~mZ?qbt*}v6Jx&BT}valPn_9EOo^vUk1CSW5XX!yefS={i^+cMJQs={pm6D>@Y zM$}W)Q*@|OlPvLjU)>&@$f<H-Hz2|CFWDQ7ckScY?-R(nPbefg6zHfMv>OFO2Xr(u zKYh(|2l?yWzY%c_(lt&Xv8-dZYGbUYsF;TaS9jHyti|-Mai}MMNumzk6tUJls<?hJ ztn=%sX~EHV4Jov^1UIx&%+`L&A>1q}+z2kFSr8GZ_iU?~?#85)ok~V($dwgE;H2oc z61SOMx)V@ThU)(GXx`+LJ>=oQn2VfVYJ(CweR~$*RX&}fHc6EG=`?7v5t$x?<15b6 zEsRt?X`7n!JLEg#LRg^J=MjE=`AnK>tRnoKH;B&TMtVVkndDEF_z)l%8RvH|^UsAh z(6!&Qf@bCh=k?_Rtv1dMhzDmU@+qAm#Co>b#Sag?eUKb1EF)>vdF?p(4r?(@y+{gF z$j+>;oke@@!N@!Bx_lfD(M^Hu_9TlkeFdI?sD84J_D5#&p>sTQqJe%ZbmeI~Ga4O5 zqzW{^w@6K$)3lcmLod#8ubPX!*t?`U@~2k;Kv;;Gj8WbqDp25q<RFNe_eSmmdI5m` zuwiQwjH(AS$5E6CGTF#GbcKT>?i{MQ+ugVUa(wjB#ZLQ<*3lr7pIG@uw_tH`Jgk2b z)}~_g;Rjh$_#|w58r>&=_P)@?%@de(_Ivpw4(UyLS<?J$y#WH+z!*i2gRi*`9tfzP zW*M0?)79-G6kK<QwO*TrIwPBriE<*j*(SoB8+1{Zh2A?}3ymQ6HM}Nn&!aES6oq!; zIaFiLBprN%_F_h55GfbUX;h7FXiR^#Ewur`9s(z98Z`8k=>E{)lV;Xs6;1j)_PM&E z?!nJAhjdAI21LbZf<{D#-?a_O%CI-A28tT-e-a(4#6G5z7<+{M?Dm)2H_t&?U<x(J z&JOjC@<@9`V&A~mz#er_bk5JM(!V7jf{Ef9n@duDlraP;w!M^H%gea~#`|M$41`Fy z3)(pfY#mF8a_ww$QKa++=_G7*;U{Js=Y#3AJNq57iYq_qs{0xTH}W4w=Hq7o=@|ef z>$A`Npx*d3>GyX2wqX|{vAV6ZV|oColx=noG7KJ;>L5ZPzEvB3_!0j4??*aRL<-Q| ztS>ROw-eq*;3j{_FPV9T_XU)vr!iV^i887<B#AR76V?`G$wJq>+@aDx0W+XXel48f zbWbXX<$`4KPx|!*u>%|yPBDQh_mvX2_3ko7(E%l#!0mTW>oGIX4t>(3Gikyk;S2Bw za<t_Uop+!goI28k!Srnk`uT!`_nk%b06k>82@f_E;Rc_-V`w1_51fi)zEllM&1B;- z{>63rO7&0s@H6Gat)tz06Z9Dsgxa{~WC9XCf?!_LJDdj!6YMD=qfJ>r=^x-A^XQpP z80+H4OCXe3u`T*us3WL|R<MZ$Wr`ba01^SO;ba5)6<4n8L0PzQi0*@n-%GYWy$mj7 z^Q<plgZ)S)fvAXj2WO4WT0&HEtK}yA8=OX}+s+G$X#o$LdwWPVRp?bbC}N)fmJhUq zbezDNAl8G7O^%k3fH!Zg5)Nr&YvV1ojO}5Ndy#ul-xfww^)ds3xmbYQFrb&2@0)AM zQ*Ua7EXTHJe-Td^ETjv%vXj&q_Ip(roUV#L3Pr&EkL+yolqj7C!H?088NaU=$4Fyx z9UtI<59J=^OGrl_<7>B0Q;q9Sqn>M&0^J3va)?{3^+>I8*VuXDuex3j*>IM-4Mh{b z<PI)bG<S64%F%t4Pj5}RcGDV<-)bWnx;2ylDfoSjxbplfr(%+k1T1il!(4Z<W@j`a zBcB3Re#T|a#Lj3tyi;!(u~*QAu(7c%Trpd6of(4xCx8};o<%<9jmJ+q#*KqF_Tlr@ zIz<3vK5`9#L4py$s|gr$oR2n;<;{PC{M`c-Bv>~|3RXdoV~c%E$ROy<wnk+Q?sgJy z(3`!CmlBMnYZ%`>0Bwv@Bt7Ki+^~)_9R@RZ^oQ||xPJQM$-#d<xsD7cLK`V&&{<`K z_b~W7)lTvps0U7&P^xJxn7IlxLvsRpiVLSz#5BIAJn?8vL!vRFgZ0X0NxWd_T81bD zvzOVNpH{5V-qU&>k^ow(k>Z#I7pD(DK0m)QK(O-`!(9hk0dNKQ>i(vI%H%uEiAO!- zclnLdy`EC@--p-DQzz}eDqe~&DN8i~bNL*u6lqO0IwT-|FKkj6qY7_{;i8__xi-#> zeBSnKb@6hmX-<U&S=&0|_@mDeu5-YQ(S+#Np|^Hk+w4(J5TBqy`2Epppby~Ul~psZ z=>MF~sSMi*)g0x+Agv#YjwryJ{7tH?+IQ}Rp{yu<-j@zf{ab&gf<SD>B9H)2A$Q~8 zcE@%hye<9(eM)5R=)CQSLm?mUB7+&(w_P>M(0(8Q4~KYP@8%!66d5|48H2R0U{RKW zc1oPIpL2=@8l>gxYAd@fMXGvvBxCQ;P3Y)Z=n+lm8F!VC1LU4~{^R-#f#DQ#)}FNk zT7uY|J^zVPC9Ewh?EVV9-}CkQY`)gZ`H|09U4j5PUhm!Lm+{PwE~djHbLj*$*Z)^a zxXu;kgTbASinwZUyc1TMz&8(_KH;z%Gl#E3x@VIdSl>BTk9I1J7Cvn(x$`a~6g@%x z;6ZuDhLr2=QGrXMpMXXsQ3r@hD7N5g+eTRx)=?zjykdumqlF}?gm0H{x_se|XEM=7 z?fO2)ukSi(u61^%L>XR0%|FPHZSVDmAvglVENh6O|545U#jw5d9dmxpsw8t#f$FZD z+u8zuhIackeGI&h!^`;)EmfN~#O0f9!^6YN*QN*aEqa0W-WamqK1rs!7=(Ke!}Rci zy)EzI7R-CMJ;!RZCZg0$r2H;`_)Iwb3Bd_;gm}|FJ&q@F5S!?Z?T&wdN1on44dfD9 zn8m7+$5uYjl@>!9obDUPk?2hs=;J?ipqMLI#729el@*;<;&fD(=rF{a4;a{Z4DzA# z*I5%iad$j<qJV59r%ej3<Ni&-i|GzGz~nq%XbM!P$A&utsET=or{$^T*IY<EkT2BS zkqTHS5e&50`fl^slIXbzw}9!A$U=^0W}fK$ps=FtKC+}WON>gG42_<=P;JMqV<6R) z{LtCGIbVyJw?FcVt>3f$UpKz>-n-iU4m<Lyc5gxK?RV*yg>GDO_52V@$+nNA{#Nxg z#!4WDvZrq76Z_l^z}aH@*b9+md~BEmwAToo8IMt{cEiZ=w9cM~0Y=MS<le$rJCN1H zIhQT|S1v*;M$;%+Lg%g3p@7Tn+-PAr)mRmWiW80SXUY>L{2G>e;C>7e{+k;|iXA`g z9C_3RW_9Hx-3&Z9Obn3YxG=NYY1!ZCSlJmOrG0%c%u^^&81mXo$%Om{s<G>#91y0Q z5ux?sJ^o9C?!Dih`O`6KP$z9PPl}<3&?|ICKaEppZ`Ho{bsp&POcHA8Wg3e3lE>%~ z$OiOv0YZgcRv70Yhb=wI5A-&5t(<uS0pj)CnKuTZu1N|a!%l-!qKEmKprE5&XqKDD zvH7E>DjP#<ahT>9T2dO<7RZOpnP_S@#GAl7IwlrmPQEzJ`(XZQaJfIP<DN0=pmT%B z)ipMFnpAw@Krg?XZ#gyhcfed3xKA6tM7QM<J4y7%!?Qo<ow8JcB@oCUcOG;S`Me*V z<qCb5@YeSYX#Q7gDYaXZ(rFHo<u6JclKVWLXLkcG+gUOPih7r%+TG;a`4(xaCYT}Z zSYY;q>Kl`9tvf>^?AgtzhZc0ylHXh~uUI`C$_RYD6v_&8SbE>vm=+Xa8+$`YXY!K$ zAyWq`OV1cd+U`f2pA2hvD!jh{Sb!j7pq^gTpd)Ilr|SsmnEC5!tY}j)q_q&-89T<Q zS<m<1r-(SsxA~(QaJPh37TPxGQ(O!N%*D$WC=2FWzSUC`)$@F}<4%FyHZXGGx>(}L z4QFWdf@AFm2(wyg@>}xcXnqz?p|UT}Phkw~A{P}>40@WW;G@CTtXz>H=Z_pV^4MJn zhJs-={v^D?AlfMG>j{RC>&8{X8apUY$00&g8S0>Vrxr&CyOd8<$AkU|q~MAq)PYE9 zTjOmaK8sx{`-)SPZ#tm)0a;47nb|`@C%BIU>eP&NS|<%CFOD8pwA1aEX<0l8Gmsoq zZ{TW57?h+v?BO^)B%y%wi?l(4@DX+Arw(I92gy7(s2uj|1ox}DwFh=LE)6#NT_%8r z23&5)%ASGg_!OzW+#fAGiTso8RY?ez%pVn+@!LI!l-034v;!>7S%7Yc_TB%$-gV(; zpC8BpI9~LL3fMjNzz6~P04@!A9gT<z5!X+8V+V*p1~rYACf|14i6``0ve(ngdN)3g zS9EU~LtK#)sP-{(el47b*VTk<lb<iSq?D%R8{fL0<XXtm7!G9yC<2NNEdAh=O47OD zBhaW-`VO*USGY1~;Y7A^HVuI+A*a{Aaj6!bS17(oRo5FWrO!&Npiof~2TM}G2J`P) zg!%LvPo-_dQ_KW|bgaH$D2Bcn)yk4`g&^5cf^E(V8IYEf4AM$;c@EV(0ppkRQt$oI ziQP-ILFRh&L0N*S<LRcYD-9(7VJjHn^fWDOu~qQYM(;o0<wRMYUaHEWb>-b2#i4k9 zn?ReC>AdSE>gtK8gezc)++Tvbz|hw1TI%xJ?AqgpY$UT{ZagNcZmuEiUS?tl+t3md z@I<MEklhrjPQ(BjKKt`kpUbPxuNn{LHPqMB0}})0XvA6!(g;lU2ftFy`LjsQe{)xP zc$w`TONEP#j}NigtR^+c7)y}<SFjl3!5}Yq4N(=Wc0|5|W9<Y<{AVfslbBTB_hu~u zJRVvHdzDAGN^c%f<KY=aY}gKbz~);(PU}r}n6e7qe^T&T!sr^+?K$x|fnTL4O~S&( zf(o0+VUgnm2k&6dJhLMTOp9CFEbleH<O#n5EQ8f*qBE9Z5o9tDIw$`O@^SESl}R(h zIN0s?J$0fgIlopUUY&kXKzn|PgH3FT5P~Ns`ZCyU1@H?1+<KS;ecC6ZC|N(vHu^BB zbSJ}T=U}f{KH6a;pLsW{=*OQVIrmlS-`!>s+=Dc5mR@CNVsv<*XMbDF!Thd*^;*6% z(4tWDz-|B<u0@Qpin%WO9r4NLAr?LM-QlCbDUW}yx8#6Rko?@4FDFUyLG$c0SqJo; zrZ0;yW7}`x;^beZju>PCHtptA>+y*8d#Ln9LOusNZ4`4(ne2<0zkF1xvR9g)PjkaI zYkSkgv>ii-?Vr8mXL9Y&2>dl)MAS}-vFW{uiaMCc+zYi?Lz)oTe-c(wqE9DD@o(9$ zOz}ngmXqKA&tLjA{u6%Vo`2~-l8p-<2{8E^bpOhZ?taRPktf3cA8K>|)pX9USj~>~ zw17^#5k9`TkWfu_K_C6+v8O1oe4UNuv34%PXbnLyUw>6|Gf4Aa;i#r@{&O?2{?zXd zRXeFK^ToJYlcG{-QK2F$3_ji&0_4f8l^T=MAI5QJF;|~RMx0lKft}|{d^&;Rp2F5Y z(r%rSh3LBPH%xvC;b1`_g67{!&;Cb4n0W8UC3&KP=ds;*<%f26$9tdQso>yyNB!~4 zvkoy!j>Xr5P_C1vTP`b#&&{H1{ugo$n?Chi+)_UO3(=2eViSWI(a@_QpS+nmo>Ns_ ziUXoF?w`t+6CzO|p0jMhg5!IIs^*ykmyU=Ive)M^Gk4k6NPy<oYd6=}6cYf4vGcuf zcZ1>_zRc6Qk>1G^9kI-x{l4-4f-eJ2UYJflGtA*PkT1w1yPjo8o80p99w6rHA7`rT zS$EIq%8tEkVZ3dyXoG}F_|<6sv98`izjcG1p1oi;lM|#*G=U9j$%3L=!0}Nf5;<*^ zP)lW8J<CFjB+9a9TyI1dGW~#vL~TFe2N;RC$tkl8Gz9uS5IztTF`8%P4=KI9PN_CS zsfN&h?+~ng1d`bmz8F+s(pkf604J+~4f~)l_-|MWvE(~^R8;_e?cey`at~e0J*0?B z$Mu{1a*pQZbcTLWo>yfbL2wJYZy@Y8LA7gLj(R9U^&b076gA$jK?cAp<YF6Y)SR_4 zawymD$iLjK4GQC7!WHFRw`;ISv*3z`%3X`lA~Hzm1jm;OzCe<3Wg6!^#v`=%0Q_yW zr2tbjbHL!aNR^k($lL!N?oeoGQuGMoz=XD3tDNzlbK(VF`YA-!yR3F#*UGlPFu)QE zFkG&eb}PsO%1pn1mHXp)dj<7|riLhTYr*nj;n1sXX-TAW0BJ!ABV<?Y`#)zg6V1KT z=nA-A<!|Qq>4!utl)nPxF&|o$?Pj2I8#y&`fEx)e34P|2AN;FpDVZK8I%nK{;4ng= zO3YOG5VksBt2rS6?d<njy8ZI>P~vMDeSl{F<j#Ji+Cs43!leh%P)xPITv!sXj1%Cv z@R<sAP}jtBc=S6~ek3h?WQV&^;paU2iD?#x@wTJRL#K(t8R*u^9{A7cI793Jna=fS zG1=UwD)EoFQlO!i&#ybZ^rf{~N9L8hv<MuJ{Us5h4*l?2X?z`QAPNd;S0$d3P>jzi zG3k_bfA^4i__orc4wOz?jY5&d(RC>)MDdVFxBPycc+v68aOe?{*s;P4|3ANdK^|an z)+yyTw@T<|b7BKjHio$;DjWZSrW+$&B29My6)fOL5BN%Qy@+aAG_K-hvEtW$DOzcb zbxUmjHTC>P?vm0h8*;oPS{;ljiFM@ny8DlSBk8ml&XPTq_37um`~3-8Y)<?D>WMEJ zq@^44HZJ8>XC3WjpV~_)k45YoxYQGn&Qc0@6(obWQfEm`sNOXNapo?yHi_5vlJ$A} zx9<)FT#0MVOM5pBlUVul?74n=o|UCqy#`LzE5w5N_PKMqJ#-kO%%7*nsU|%rI1Rib zy~pHKSEr8PCVCZ}<`_K0R10Mk9Al|~bL?Q+OxsD<7d=gb4fKRw0H#B-XJ8zL5APrf z740)Wd8&PO(EJ@l-Tf1S$~5@|lNC+{mZhcA4=`gBIbPc@Dr;h%5ff3u0h$tO=RuP# z>@@-F@WscO&e7k}Q`&28Ot?&#e4Vh~Sj7m#Y@o7OQqe^R)E-w0KqICTo7P;TwvGCD zhuVf4%oj(1J;9%M4F^S9oAvA>Y4TEQ9+@CF?+KfAf)Q@_q)ydq5%9zF#`G5SNgGG^ z#1_X@l$Lj^(uON<L#}P0!*5C*9>UF|aD3xby*<372Gbmbx_uJ}+?hXXp5Qd3A_$ZG zw{d&e29jg!;|6c@5t`;GjA3Vl11D_JXhJWgEfx;;6}o?Tabl2;`uqtaoiu<<JaS?9 zzS!?w*(zxxxF&4;W{k<il`tjI3ZsaBWfjqge63dH#_zMoD~hB68aN&|3oWv2+g%+_ zXb|!MDsK-aR^bwGC8>D+!P$cz&x;8Nw3Is8-xs6`fGR)&sFB{_?-@>bOyKDuJ^)?X zxgTPE&+N4VjL)NYwAuJ>?cbjWkUB9iI)8|S|9{_gWe14|zp_yfjTV3Dp_9JI1_7KN zPOaFMi`UJ!?YOB`1*FD(CBYyG$?RJ2KEmN9%T}tKCFK8lWa828YHMjOZ4NrgQ910Z zi#&}n(9cXHZB4TtFwQdB*fn1>QddLn9ipHjsbM~t=-;J~7(vNLyZmYPW4?HISotg( z*=GlFK`kcvKnF)2dgs?%65`L+6^lx_3K=hklB{)>X#F>|cv%n+Dt>ShgUBENQ~Q9* zZO#e7+52O7RHlBy+gSc+Q(jh>0ek{`k_&Te+To?1$0JHs6>bxLRX^TegNE)QV^Ta{ zt#@TmA0}M!_y#m%#1vDN3_v)fWx!s-W8#dtF1`oF>2V8SW=kFQqa$F1Zt#z9U1Kya zJIbDK6uo@c+~+7y(#=Og6FM`OMZf+IB3A!KnfqgGzBH2zKVT_vjFx2JA2JW8o6w!W zfxr3YwufnkriCHjvF(YgSV(3gz;<kRTfX57yb`XL0?Qwm#bOYdiv)MYt}+k}NRscc z4cF~aKkjb*y(KX&pfGO%A=!1H&}=#sqa=Ejt?k>w)pp*6ab}>w%H&|@Fkm01b(>j} z0I_AU>1pDmBe-dstdW%X@)|H@Z&-kSVs2?Y&fdD)>8+)glQ@BfMX!(jlUxL>(Nb3& z;Lix(65kvKsK#jHMg?00iboYi>)Oq~Z;XrV*V2jOW1CBAZi{5}2pIDEX_AGI?Jgvp zMQ9bD!$5Z^V>|w-_?CGCXLquoaq)hkXjx%A9#iw35wI0JfmZC-+v;L(gV_BVh{5cu zv7ScU!>1DhX-1V^zg%vnjOXnliEbjC&@7F9Es%fy;PDSxYlG?{^x+K8=wync7j`f> z9vNeZhCe;zzspJ2JbkTbusu?LEB3uLvwe$YuK6g(@ogE<>wRQ4e}xMb4_-|5FXmfw zM&3Gry6rhyG?vS)Z)le2mM`RHs9sHv$Fw$+n{;{rJs21|f)EZSYuao$2qOUA*&obF zYx<pz$f}&wC;$!Y;WRCM^FZUe_CtBL0p!XuOlyivBnTSnu(D_(#w>p?nK$X``oR6R z7l4b^)#L==411?|<bH$Pa!2t_>Mv70+FAFpr0UvioPZ6N8KXXP0~whBb3`|0wh_C- zJx0CF3GwPrdDzll*i>#aTF5*nF~A6E@HX&?yI-$Z^NV$j!~SSt(fZ9yN{9)v(0PhK zVYmo>XCi0XbIYoS@Aun2JmaDPrhz{Z7Jb#;O;<s(eDdv#t@KY4?;N_-#U2k9)Kx-5 z<+&j!gy&&Fk5F!XJ9d7^!0e6OrT&J4{BSUViV#ri!OdY+9wErT&K>k%25@*t^+t!A zZWMpyU_elG9Hs#JW9Jb0Ttb0c4QM2#hS{17==Ipr*@ms@!uxbB4`57O9unwO5ISy? z?e6HvsU2<19c|6M-vx&<taIo>n9x<o&_?z;+nj;ZByuh*R>091SlgP1b}`De>Lo4* z`OlwcLy5&5%b>)Iz$MJi2DIa)!^V`S0&ykGnAGz89{6?2^GBYcA^nX28Uj$^FL9Mw zV(J_-G{rz`8`SIQLyP0<z#PZ^q(&)U{)rPwb<P6P{E_9>WAk3tMD7@gZ2xjpMNgHy z?Jn}cE#qvDtAMxYQlRV9x0Yi%H&S4CHUC|Q157I;(dIrgZ*g#1B|J)0+}=QZl(WoU zflc8MV^e=3Ph1mldJ`N2$Y^H(rn5P#A3M!INAE@Oa%PRs30UI~vLej+rBk|5_aNy< z65;*e02<IJcwaC#Nz9IqHhEyx&N0I#I`v&QW_+#C>?L69u>X-%UhonX)`rrt%LMHF z^^E1^fkvKOV$hB!l{Uw83^FFWkn(}1gwX~Je`zXPu`jSs3@^TdzQleiAU(BSJO^3M z6T=gkFp>Nl{`U6@%(p(!P9%wahKBV_!1S@i#STzQJDfLt>-WMoqTYrwKh6|dF$VJ6 z_h^5O?+>T@|KG$k(EVI&c5-V=1pN0B{3owIpMu|s^8bG>{6GEVAI8oPE2;EXS~cYP zk!iZ^$|tSln1218Szn~UYR7aA2(AcD;Gmsb|9dEaA<n%EL!1)85NBxS&SUvtRI3m$ zmvv+(?HSIYrt@sxu(<q+S%R>#zY&asru@hna#Fb^y*quOI|63u9FO?rGJVijA}u6u z^=s1(vr9tjyvOxlGZwCJV}I!EtQ+1M+!&A}oAaNW``;d$S2lWwwpbGfhc&}sZ)Rua zO@n1V@vR=9N)pII^w$CaXdM8UDow6F8BJc7o47Mr(L~WLHNJ^0MS0e7`|q~_QY$)} zRyH<9mKZ&lG%$N@f=L!sDJMM%Np~-J;s2ljfF-7f`L#3p^E{n&6<`I6n=AA8_lTYO z#xDbsqD>z%gtXe{Ww!&K-2d~J18sbZ1l7hqFbD#eC8QjY0b<4Sp65N)fObL@9h4e_ z8TieY^yqj#&)sD0teJnv!&-sQsQ)FI4S2`1?{&`Ci=H4t5DVl8+Fd!Ucx4mwQEGJS zBnR&t1-cq}c(21<;9^oPn9ei<>A;h6Dbu(8d4CcB9VCr{l7O#z7O1LFoSt?Sp~A_b ziR~q2o<eaf50;*t0x&0S`%t!UQFsV^+&ja&2|ftNgYW%N;)&h#ngaaXdSRGQEKBsh z8DD{fUVw8L0g8Hl+5mITC->r21LID^4}qHfs8?rSz4j+;+=z=Ho=Gk(C?^=w7vw1y zFX$cl*!Qg)=An0Ig>clOfyUcA%r7&ahU6+%NDZ5ABHDBNFw`)CQgNj$+p*h(hu+mS zrVe~<>`V*sFR0R*-nDO`!Mb^{_VQv99+BNa=~0Vf>K4iu)ViBT^al30Q{M*cW?smK z@<koi<shfR#`;aVquc6fEb6V--DoYaS;V7{DZYDMrta&YdvYGYM+y9ySDYB*Pp={5 zsbaZme(|l5>yf9lq2MZb5<7&LMc9_J-*dGY*;L<dVX>ChyS_58SXjtsIChUQ%LKd> zF#+9iB|0765{@~RJJAk9L)?#@wL)JZX_rmb36>O?+5}aRW~|f@cWFI7Fa#%}3DW*v zb?+c=PM=)jA{ue@1mzz@aSQWHYm`f*^*U8pD`<{wr81I$Zpr}ESZ4oW(Z+IimEvyS zi4vqBww;K7#Kg|4H>}_DRw9T!gIigr_Bm#8*WL3Qu8vIMKlwr!-O(=H1Y=K2KkZ9) zrPN@ZS`!rBV%0nGX*HmGhA&(o1xBzlk6zIIJ$BE4siCZz#w;@f;d+2dlR5@kOajt$ zauMICO+ZuhQ#%1@Pa0f9U%$nOuHJ#So$Njq-#iqL(vb>?#sFh(LF~8DSTiMmP?-s} zNY{5SEB|l>)aVnh=JH|K?&BS$>A4R%D3{$Qo=w~w>X#lgCIpn}+7VgQ%Oe3Vj;~jW zazCO(CX=LoJ8pzd*%6Vv$nsDUnw?VK(VY;Su&xwnS=%xIm=i|{+3244Ej)RKcM>ig z&^mXTpgwgX@Zl@<G-KqMKM4(pNTxF`GDwBnr#s++2Y$*~fQ)lOB}&V0AMKjRiH%<} zhdlXqN0lbjO$gvUSek-aH+PV4B}`<pv5F8KJM7pax+LZVx0MMz$YF=N%%-mF(e{ZZ zf!T-^soU%5eW~5CK5qDHZPT5~{6n{E8>$F*f-nCl2f7B2!`%pZbR)Lh81a{*Uw%dH zA=kFXZAQwyS7joc6Iwgd`LuSTsj58%rfR=0Z|IDzNX*v48wwhp|4e9D&uIzMs8a7h z++RZ8)${$(rtFRI-rvm#pc*IWTYH-jb}>GQnEzgDM(YR#eiz#qh0=qg-6whs59j?i zT9KV8V-3=HH~<~Pj;}>lm2O|41H50kEh2{j##^G@K{~}ir`YU)t_Z}(38;jmad1E} zj6}S~_T^jh+J+58rEsNR_Jp!`$d_@e<ULO>a$TVq)a(*cr?Nv5aQ7Of!*ag^vE+XL z`_dWs6WBgEe%ayR)mF42%9y|%!m^HsJ_WQ)Mq3C>>TEaqZpo$A?sYj;NwD&$=&fN5 zBA`EkWk?XUf;)&g7f_#zSYPLf2&t;hyr$0cYBLLTh{AXOu{v!X&qGqQy>17O4iRFL zM|o@4M(;T4v9YEwG)<3XxogVPIAvA)G38Ust*~tb{s4y|8|-3oX0-b1ekTt#Y5xMq z{Tk&Z0m{eMAESeM*Ec6Vn=niORSArUyW#{Dh)b6N13|G)2r>Rp0#Sh~Rzv+lL<gk% zz>WYV3zorgqr&v9e&17tql?r2$+GQk8T5$z)}TZPgpuB3t2<a|u@i5+<p42`lnSVX zR>qQa)qkFn2KC9d`rD`iR|Acz7PyAg3|zGPxNODZbDD<|_7UUrys#3eq~U%9`#1IJ z>E{OKTVvI4b~6<N4!A~3`tumAH1E9rPFdV>d1D~ku2ijvmGyT{CUm;&52Bn*hkbq| z-ZqJkbLXuYiIqx;wTl?4b3K8?H%w0GJCCHGbtA;9JSjDsoq^-G0W)~zL0TO5_}MkG zv@GYS>#l$u=U|^kHqY^zDV~Q=8+cVJ-<2a>^hV&IWeKzhcE~#QR=xuqU@<n?q0Wy& zH7A6x!nkLygX^(@4RKHscYtCQr|;5=V!Q<64gHzPg;_*6lt9>uBq*SK?xVB29w2^w z%?;4`t>zx%R<t3@{4LaMW_T{#XYS(0pDu8T70^m#c`-C8pEQWFp(WuqC#A!IzMXYj z=l#sv_Kv2VLt~xJDsJZHj(HtlZ6de&>aasWPnP9zJFS6HLU~&1HU(NEVliD9nN6q% z5A5ziMSD4^W)~Kl34CSffF3-cKBCTCY&QGeOUL4GZ8!0oyF9))O3ML!6f?pR9f@I$ z`J>(Et;#PX_m6r;nbNU#xmNW3*5nCo$M`iEfl8HMaRNa_od}BgOAx@92Tx>U>rVRa zqhhPo2jhQANzw8j+i|njNxsFqGd4MGH#5E?ymq~|bagVyIk2TNT#)0R_%7&lz(928 zY|t$N*d4~ly340F`79X6dH}TXr=pw7B!Dx;^5Wg}PeiY*h1U_UC4jP6ry_nM(7{tQ z7k0T*G|qD~OyHXtZ%q-P+QLDjRjD1b`ZS8Wj$m|8LjS4Nx#t>|L&3d^UaRAD(sa@H z=kREYclMfnRR@?Gv8!Djt87SN!vzE^P<d;L;ySTTzM$;>Qten>mE$FpprwCUY)qLy z3dd<O_qB4D>~XM|ou--V?|4lAl&;rw1_#jFbT8Q%9OT~&7^eIok+tf_yjPrZHRy$4 z=ax-(e2DuINFSpeJ2IW8wkRLK{Y*r#c90?7DY3FH&W}(}@q0@t!YWHS<Dp}rAYo6E zgMoYHm-EC^O04uJ1LrAv%&;m8NRUD!3ppxBE(YxoH)FRW%r)k;PU6FS?zi$h(v5k5 zXYQ}ocedy$?}`b+RrY7Zv_o(P^n+T!R_)9*;Ew<St-(D;bdTbJEjVn$C3wU$=5o8_ zN9dSe?#PijSnv3GZW`NvwiQ5Sf%*g!=W8#sI_eaASXMx{A~Tm^`TNthdypNK5nv`L zlyr85Syd@udKwLOJ{8o)@%-%K($EqDYuYseR?;n6Z7CNwa_-%MUE!KsA?vm*hU1Et z9mgI|N~(Si`apO}>(qUP<U8IUC0;I#2q~Z%Pm$l`S6U((X$K)bxqkNoNP?3=o0(F; zO2UPCq<m<5>7TMC4~}`sYizA1#w)qYriO4iv?IXz9<0n;v#@|}Jg~-{NH>icdsT5q zRH@$Wqf?3n10u8Yh%kM<uF1?~A2!k2Pgq8Dh{Bd*AUXcl{iQEj7-%7MQ5HBmP=JtG zxw2FLbqF0ob22X82<RdXqsMkus(equvWdvj09yOVP&fXBh2@0vIL{EVLI>Ci+ZH$8 zieXz6L2j>`$@xZW=4V}I6ThjS`J5U;5!W*XBe4tFq-~x~R2@E`DGBthl$4HLnq*CT zpkzv($BCJhE%@H8k?C9R*mQot*p41+nn=`xK8QHmuE3A%<LcLH2oCgk-UVlM(Vx7X zZ;i{%8%a01eXl_xr0gg9yS&3D>t2w1zM_H3Gw{vjvobE<PieEaq~aGjK(q9p3K>@m zCRi!+7HdeTSF5J+9Cv+ujx=h#xF`up?byXTIO^qzwue7uR&@;x?kNVpI4TYQRP(sa z^D(g#zERNLVSc$Gu=_yEF&bMlcC&zA+0kto%J5n+iOtPsJOMx7$HSRenf0iBckH$9 z!eHzv&F=9=vv)?fBU}MO8Axo{xm)*&29rs5d>BvM=6#F1d#b~seEzu92?tBQAwp(d zYyq0@_HDzb2GWnKA7voN5}KOn?5`O2=ExRnCViZuzk0((X#U5Z$`S<VYk1gi@3kJc zWt5*Q7tgE47a>()W3o|tP%fw0joWW6yLkT`J$&&x^}HhGFNN^u_?93aqZbw*vr~H4 zW53qr=)-;{{LW9c$O1rJdQ-x1>EtX0V#!r_@3#>eBLfNS=A<8Aj_7vGMt5P+?AUyY zuC}J2_CVbW##1NfX}Q4gLf7gI=vrrok@fqKbT=X1E4kg>QS8TZPrrOSpuH;q0|ao< zAJdU6$Ub&jHyc+gD)LIW$d2-PyzZxQ26UdZ``CqLJqs{a`YOC0={U84y1Ka>cJC+z zq<O{OIi-6fsu7Gsbd~icfLSobDW{)c<*qa4yIjq82-1bCW7clD`=!45D?@6vEe2R- zy+82qK@pnm$)8aw<44v=XefObvQD|7^WlMAjQ9<P93T~!K>;xCd3psT%qypHj_us& zgEFL2mibeeh3-u|>m+?lfWQH~SPaykBWE!C^$+5GHZoBbJL*GzvgC3Ap)xt46Z;_t ziBx|5ra32zogJJk&Kxx$pRCxRE`%1a*vyX!TR6oK?2331mPt@0P+A8|6n*FD)BVeL z1rpvsCCQwL>5rAzUGM&WtIx5gSBP$d*8SR_QyUGh=8>EW!;DIRvOvm7bRf84_g&W> zgerioy=fqfH2LRA9Yv2p^ytvFll-@?O{VR1Xf(IH2-4>0quxC_NP9o@zK}FI{_hO= zoGIOM+WqgOIl%d={LLeHHwUXCJa{|9A-9MQ-^v^bYf277C*CO2`+o6%nD9^Qq<?}j zwcu@Rf54@G8?zg*A4}tev%(#Kf<*|tc1}ccLmh6TBG36dB~AXbNOh8?|6D`VdNX47 zV<1u8JVh>6qDWfmV{sY{OcAsaT4!33$`6CT;lY}JGbVt5a0JYVcYs@hEApnZ{czy3 zFb`o2Mg>lS(exbf0E!)|5^qhBD9+i-7r&3Iatf{f@%r-V&?8!FETEzh`^&|r)5K*W z9^M9*hm*`DOZUAvKrzEt6gw^o9CriH5&i$#-zdJM`mVuz-ue-EqHst3FAC;_HoaMI zcstxT7<z<V`%(ILWP3O8*IA|H)M7e0G=CScn9kS({8G;<BnTW&yw*=pNm`9@lLCx2 zi!|3HB6A}{zdv9j71q-n+2z3UL&!r_@xrXEIN`Jip~+7ip=J5e52_pp&XFGGq+=k% zRGV<PH3yUw&3h=RNVKusap{PIi7Z!e%$q;V?R!}y>pr{K%cN~*mGIG(XG0<l7VmD; zd&;Z4rngchKOf!*7)mgJRzl=VRuYOoWN`D=TtsZ*6a*es-A0QUjRBo;d3ETWO5lq9 zd)9VN*Xjvw6<)$z1oBiBA1jsGb2&%2m{(v`?L4#eUN7NhnRw(j?&Km^CEmPU`{?o* z>KG*ax~|BYS?-H37^rkQ?oye&)nMSB>-_{2G@KmkkCsg4;%>SI-~l=0srUeNYX-0S z6(dGi?vg<PLwf~XKZbCZI9P7Cf`}*6EB5!Ax~_D=e*{<znJJhNy}X=uHAbipHQ0WV z5ofRopsNi)GfSQtH}WOmY(*_aO35vbJ?TjC>V(r&h{nYVy9#@Z{oda>7kAS~ZU7c% zc>|JSWP|k1Db94h{7C!rL(rK1iKO_=KNJ-ik~6(O0FWu#D3b4E56y&T3__T1i{7hO zDfZzy8`U3+=Uf1P4s?sw**x~R3vOZ%BRTs*e<QNzkhX}Dh&a!(qEtF`rL|GzfBo0f zfQCk#I&tAlL*v}>zU@B!%%?M)?jB&vs-THKN07Nh#P}W$UNWZ{ked9eJ6=!G`HE!C zV_9WjQ=fe+p0nZ?S%p-ZF}W5^`T~+OIE667;eGV)Sq;0CB;8O&9>-_;Tu<DZYfb49 zz;eajvS^+Y%wapl%)Y>%wRLS?%&m;v*`lYnl3{=-uPs^j+}R#E$NNt8q%Lzi+lvpW z9W?dm^=LYXwQFq<*h*+ZCMOSMuokzzn!d+Bp$hB<Gx)E+UiA;4EJg45fMIQBF4f5E zU2tep%%cj06feoo(}bE$xOZ2G2+`{Ex*+%Nk^mh|sVrUy9to%k@9|Q%+?g9XKur*$ z=G(&L<tdrAKKbe(#uzm)sc3pOfSM1#D0OYz7zlY0wI$P@mZdJ5jsR$Hiv5wxQ=n^w zxnWsgq`DWaSFhK7I03v95P*M|_Fe`$x&pPNT5{JC+=1IBb}>&eZ>{Wm8|Xx2H-H%@ z;}C$(-n%U%eMiWec`dwiR#u5sJHt1NX7yW^cPt_Ewq``wRzYXeckKfG|LY}~JHb%u z9i|rb;66;RWzAB?2w6r<x<>dAI!ONEI)Vek4Kv-EFXE;*Bww7WC!txO(>FG6DqHdT zcU|k%uZlefOxB){?5^ejC42t~$Etu;73Tc}Ja_bpA5sB0KdYzMW7A7mpNByu>37lv zVclM<c6GWvjc(}0m<UWKEFvzWuCT+9rI9gCC~~8cx+fFk0Br};8sHcACnqLV^Mw%D za;_;f@A`gDyC}47-1{$JC;~JfH65s(_e@6@yYx^C=sK|IB}SFF&(nc_fG@(e@Hzi2 zK)7AP60d*3_%Nmu>}Ju<KQxelcfh!IjPAt0HsCa`gM=N|&wF$`IJn43xtZ<b8ALka zEd<z>R^-_}idcc+{MyFg_X1<E*}RJWN&fKX<N?_LGqT{~o$M+9ekYXmL<3>81Ptb% z+ve5{8gJY|b}9<Gqa`j6i^p?Q8le!!Ki~Oewbt;4N50xYMvC+XygU+4m)n{ry4^sQ zW(g2pIWUWP0-8MF!X-n`Ux?0edbfCKx_eyw=-(4jcZhli5Bsbi_M*TJEVR(}sao}O z5Q5LvJ`<e|-@VnGj65WN?Q0kNam8DgTQ%BOqdQAH0f6b4@>LdN=b^;j@ZAH{J#02G z!jCpZbst2uLkSUUYwYBuH%W&wV2QWfW`uM##q)#dcD$&I0{Gc4?hzT1QwGuLO&c<F zv)h<Ev=h*=r-)h!jGE@Xz=QDe9|~0+YgQD*+`L>C$nC>a^UE@AA3(jwy*TE0o~OAd z=?Oebs@yQ1V8$Md!x_l>v4fQN8jbzH%pCFyajZ|ZCSSelx{7J%Evs^TKy6UE{efw_ z*?D15QVtAx{Lzibvw2`Xqr$3B2k0LPA&!s;*$pP1%@<u0n-EUe`ugQCVb*mEjCm}5 zERMayxpqmO+I(cD;a*k4LDzE<&(dq>7fv$US?Tzc)4*ehyl8>(QYZl=y#BaNz%<>S zBXxMGX{CQ?Oya8Cd(v@C#6sRtdEt2!F!PDJ6)?AqWkaiMa3}sAqVNOYGiV)M?WR8l zEx-(twyuPh$8{oN3Gv3f0?;JyymK>E--EbG3iF230bm*wy`PrBO=02^tNU+eQ6S4% z2q{^+*wu2`C7}siPV+<Das9|;tKfYQ7vYsfv7xV)LSJp^4W1E^X~jikbmFl|#_-1E zKkRZ|ulFpU)_*be6zZ(5zW(Y<!D|HXN74QVn%UlV_3cbuER`8BllbYv`;5he?wyfL z9Xj;S6W{Fu#(lerM?4WnyXJZxDV_M@F{_q(LOGG|F4M^FBZ2;slzil}F)33|9F3k0 z^3Nyqe>{>v+mV26$P>O<!9PAwHj^BSZYI^;L|IkHF@JY81<&uoB7c)@qcqM=_5(}O zd~+J)iD<|t`b)gnq3sXJ^d~(JQXC)fAK3Xw{XfRuIxfntYa2#N0SN^ODHZ81X-1S# zQbD?NNI|*>1nCd~=@})ZyQI4rx}*mfx`rAUhIjP3?)cvKe(vY{4}QOybI!f?+H0>k z);b0YXd)3%tAjRF(d^UHb>UsJ8#)mBn~Lk(`D!mJ4n!%@6XJzpgMrj}6^}Eh;X~|& zVho`p#sf;7oVM{$z>BEh9hWtbtM(BU&Q$}LXo#=<@qWZJDl!0@SHPA~TATNvmv0Sv zkwH*?wo8eGvBiGgE+zD>kK&*=f8T7f;(yY27)WVmIAWteY!<F4@)rfB{9eLcwAfaG zn%m9pxtYTHPm~KuyiP1AMvdqC9%r2u_2ul0Y~y9{=amHNmF-CD6W!5@4JmquIZUgN zG3g*!s-Y&wEVdFT!2(Y%KNXiq@GCPiO<Yh@?{r&p&ZR1%5aPoXS9U*=JKUlwDU2-4 z-_jXCcIS8%rNAHZgj3w0B$gTN4`~i<6eL|RZdzmt+j|_aMe6F?MmzSofj@5AM6xt3 zVy2<xxUn7GI)-7cV=o371+JcJf%nf_Fs!;pj%k9>GoW&(pJ=7iRrs4rEIW0stL!Vx zxXwW3vttF8r$_-%EMLqXz#{CFK`iedu6<_1Umh(y4k57`lf2cd;!ox_XeJ{6T*Nj{ zXb7M!7_!g>NK>IFsoTEB9N-wd%^%4NbGC%m#sIZ6t$5I4=~$wjd$>SzW&gELs7`ej zqYuU`HpGH3tx_j<l^*`G!r(Miw^;`%q<HzpW*yuy(7`bNrd$x3oMn;n6lx5lMvx?Q zl$Nt7cOI!MQ?SH{hO#ro;FjPr<c2SZ!M7hIgUkgSC2!5}Sz|`W8%Y`-i7u;fY_hB^ z-GNu$Q(){@Xr}iB*S{&b&0~^QS-1S%0b_3clBw2p_A_Y=;D{8qtE5&~tIWIEf4C#w zPyZ+arfKNBTmEvxwtJ=mDgzkq_l7>UpHQ{=2vQw1h^u6rUQ6AC?0pr>n>V@HjiCce zIRIWh*FF)%(BWjzGb@@&%!rjh=s9WYKT|6#XrKfi-ousxv^~pvWd&yzY!q|HbO?%R zeR+W)oNE!3cE|yNRd0Nsj!V<^1?WQ<@mD<<VP97ga;61dcXc#+a|$}%RZ4z+fA$*T zA(pP~Ud5x5*(>!>N8$$!p}j(vxAGeoPp3glI}xrw-Y#R6*j>*A0{Iuuuye6_)mP?z zCwyLmp|`p<eA75l7#Biw*~}#J+fZBENwfWYwQ%Aofy_{<Z&hBj>i&A>y5B!*jjl|8 z&M#(|7uomuXC5D-ENqku?G0-xU)>g7=mqrjK}49w)Y?r5Z2aTp%w4W4vkZ;QjV1wk zQoi=6WqhT1Z*H^2Iv7|FRk>bnxCQtkBHurrT58aklK8E|%jNtSis1nWl^Ni-J%h3f zNJfE5^k}|F-MDN*Lf>eU5L8G7gc4w;o>^2KsNhKvQWF=o6=tP)Wz|l)h+`yyMIsU* z#%y-sV$_%H;#k8t&|fwrTc~Uz5FvvpfF_$f&1UQfpBB30&+h?{4)Z}4m2m`86(#Kj z!J`YD)Ymi6MF^>Y(2uPF1zMo1K!~uHG1otWn}x7H(L83p8@?26+`t3OfPGwgHPn3H zU|k1E)!COdNJd5%K6g1LCtUb;;oVJovnXbe7)#lmQx|UZ>;yE1*$Fyxf1(d9wzt-G zSy`VD?fv2#ka=_IAxbb)SJ*!N)>x&wL{S?+BxM9pi!)6v#`etmOtzu|<IcvLC|lw0 zs$sZ%{-Kfo8oI!VX-E=?9zN^a5{sf^$Y7WH`V9pgR^<liO`&M}X2WRrA%%9+uKbJ_ za1)IE8G<6XHGSP+*mJ2L_}UUWhfA8dZwwq#7sdh8<k$;3H+MOkDs9qecOZHCNC?pp z)Q@JwrzGy-DzQ~WS-fOYu#{MnNECsZWz4!|;S$F`qBWt|Khm+P-;op<DRuLNWnUU( zz;oV8<RH<rbpw>?7+k+@OgrbJ8<(!rZusOD1ZKnKd<FDaYv9jy>5h55(U0Nwk?h&u zg1l9@<JxiU((9`v^H&Se2I8<`iCS0=3D5cQO<Q$X=It{*499VIu=WZQm*z?5Ki=U^ z{NL}OAFdN4Zq_n(+)Xf9|Fa|zW34};T+{;`@=-3`Gn+-vs^Z|J;wr@}5c54uJy7;K zJ-K%Fh?>A#S})`CO}*k=;{GPYjwDc(5KyuN=x`pu@JItzCSD+H2LUYvDB6ohdb*fF zX#d;`?Y}G{1`1@8R_ua9u1c*u@rNop6@p9=-BxKXm-9G=j>@*jfdw~+R8tJ7F5$|V zl^PRzTSdU0ys1|=cc<@T#xgZaIA)SHu#VF;SkXb^UPASIh~}=}5q#XQLDRUlzkb`f z)tQ+9#1r<qMo<yF7u$ejm=C>5P8$b6G2BgqKajs^t^a<h(aJyhm$mzi7+9I=kO6l} zNZgfJPSQi`3Dx`+luWHf)$9I4yYsk3E*ZHg7$lyND_ui9KG<{dE-?ZEuy%!wm3+|n z_2_07^+^Ura34rlKf2IgGc+v8un*iC#xw~P^r}3bXtx^Mz(hi3+5~wPq!#e7n3WSK z=?LJak`DRLrms7r5B^FEh%bgox_5H{d)MhsXNW&Q>3_RaO(6GY6{l9U82rIhi5BrW zH0%?#NH>6W2Z*3}aUK;PYon}}oGq8nWj*%kFXcGl>cGExEonQ@a!<mSZ;ETMg&&H! z6thv#b6PZ#H&Oim!LZnTzU0Qk_@?>j`UxSHo9_E^{Riag4=Svwg+rf<+y<iI-TWUi z|4n!r|4LqExknT~RVs3An6yv|L%GoW5X1dR@UJQn*%PLJR<>;>RJXJgYxPyM?yy!0 zJgsIU{MVbju=xL`v}9xd4evun^CyD-|JUd9pRi5;Hihe-<)42}x?4I{b<j7VbFcm8 zP%vq>G2f-B*V&LFA$TKc{}(2P^k1*}4^$h_Gi!f#J;spR9*<sl!Y1{1m&T~ezp8=% z*1=QOo%;dP!Sig~c5Lelr?@yr66bYr;;_8%Z$eNEqT}CW^*8v-y+Oacb1Prq$5*B& zDZ+2f_cs3`#`+r%^Pln`r_~>-sVzAZX2+le1+$dX$iFi{|LL=P6W#I=z)(JtQtxR4 zb+I<{tI1Qm=l=z*gg;j|BrZ1M-o3H)aca^tWK-wn6!*V<A=Pw<A8McHlk2u$H4<|| z`$y*gEYZ9;dGz-cS&}$2%N`FS5P4y@kpJzE56toZiUY$NvoiBMPp^b+bC}i*{f+F! z#ee#co!8oM|F>cKIeVm4Qh>YCR{H-42g5XT+!ya*O4%bEXKFZh??lKqxcIE){S$z- z5cMFiycO5+0N+y6MArm^diomq0F&eLG|?Fq+~TP^lw<55?fjw)Frg@8DN`I3)E%R4 zJ=Z_5b8;FLWdCe=A!U7csWl1bE04D{#@@)@|I0i2Sc`borfTqE@B>%nuC-RJ-|sla zRb&m*p8)e|)o48k^!RwJp%=Fv3D)6h#zSFy;)zyornpj_;VxqB<DYSOvt;T#!^O-w z#LcCUif4}A3#<*i3J8h-zYZ)S+{KV*h#a~F1j<1bF#h?g%s)kw>7x)<LKbn@t4NDd zIvcIuWGMg2Uea9LD!a!d$cl9vYlpV@s=}FSnao7P#8Nx9iDnE*zwEipWg_5&@AT*} zk;gYeoiBvbMSyXZHxxVV)^%itR;>AgiJc+gJPs;a^>`<WjR(NV_a1QvgPTceWp1sJ zQ_F8CWAMv5k60Qktr(Sq=Dm%=a>r8TTNG*BJ9032(}v)nA3#W*nJjadusDg8xqyFZ z-@;6a1QsFQqNIhhl~{fWA_b=RRF~bCdr)fa_rq!lNOAm$BnNKTw{|cXDOsC8cH!UB zRhSg&xw-4OX_V_6ktba;?#b%XubAvhiO)X|JX%u{{Q13cUIx+!at2Ie$QQxe*V)f9 zObcgeUZ~XGM{oq6+|mMCMp3d@Q14v6b_$EjY2!7|A4(#ylK29URa0hzAww7a46Z#b zxlM$bP&P`-w%zN^q=VSfxO#yD7lJ+)6ixYA3JSNQrEDCT#9q!=Ve`e9wK#ex3B9G| z#4ok!XY}?dg_X>kV5&%IrNeCKA<t61JpSHlW-VCZ8(MRuKEZ(!Y`Rsg4$`(&-0$$Y zf>awuQVxe5blmGM71Jxihs}T(r+xA9ckK1*as;7044hZKm-tZWRQi~3|8j{+hm)*4 zzf@xbpSnfDetF(uFAG=x>(cc^WTO&-$~VacFo?g1CvEZ$b=r!L+ClFYZR)}AjW*fV z9>E1a8ndjVCjp02wH#N{$FFoFxHZn8dh^J7Fv&dY6&CLyZGU3xTz5_&0fNTdSK~q) zw1B86A1=ifxs^r@5?}FkFNLh6+%%f8H_tEPl-z5w{3Z;+KV~Ko4=GhT;MrWVU`Hn{ zzeTSed=?+O?H9f?k4YSSEjWS};$yma#^Jw_g~@+z!hhrD2)n|NePpdqTLWUS{JW_u z+fc6&ddrW|%Qx7EtjlysAck(8W_aN30P~qXS-l+xmu^KBGYrh;3`4qed)6UJDzHcA ztdfWRy@k!;0IanhMQ|@FtRYo?H6!?#(8-+az{2>NxTCe5y3x_;^z3%cDz-mq9iAtt z=;#~fmo&4U<e2oK8mAMNaP{m)w{@CGpfSI8M=)wJSK|13Sy<|6y~<C}S<R|ps}Pzc z#|ksE@-*}2VO_L;{xg3p$(J4<aBCq4!M8`Fnvxqyn`91_r`x3ot`61r#UYG(#9(Zm zOtQ*Zb{#lVRR4p(NDVlGV|wb>q)$T$`s<5R2^mNCw7l6HQ6mRaNkpOVy&*u{%s`@p zxsAWuZug{T@=+l(kc{amXt?y~@My_wZOy{Jue3Gk)Eb@BS7Q*Eagloh>`t0<EMrHt z>cNeVKJlGzpBt7=)B0*J4JRY;i}>NFXP8Mr48R$P<NINM|8D=Uc*C)a44kD$w4EZ( zJR9!m9eybK&ah2KPWKPd$CNE2XQXpQ4~h`(21t5j6y)$%o3~6FrN1vtOHax{6Y!zK z*jC5k?sOes2tYp<he#PF5K3R1H}^O?bwj^ZH>YXusm}nleNZgU;Oa6~U+VB{P=swv z;TCLwniF_W-p}X!wwHnbw-#Wqr2dOhmDbih*uVIS_hVCJG8uz9{a<A?kb@3U!RXE@ zrZm0+gd19d{|&A`6sM@0J)PKBQP4y@;^;Xo{i`qtsRiMo!tw!~tEW(Mzfbz71Okz= z*=ko~UPNqNkASlcFB(@WWnDU?dnniH+)gzokgnZ=$utcxa<S0Y_~bS}c0Z6BV8nf= zj=uklan#xV-o$R#qz|~H_25ulG3^@pNLv5+Hsbb=Z>+a12^m*Rq)o)K3h)IgJOtv+ zCt&1XSBU&blJ*@btT|aFD=@uK&|)77<}m~JV=Rwji{?~)ycX}?UV>ICl-%<Rz4;F9 zn=ll}XE9ACQG>d{$NuDOo!zv3klW+-)nVMX4Wa$2#1yGzP$nW}(627-J58)*S`yNZ z<REhWp}*Wsj9tZ7VTfRmTXV$qm9(!|M3IxU2Oc8DW)M!++^;}u{t0n(IlnLiRZxJt z2)mshAS1I0qD=i`B2l-DhaMmk1!9b^K<n{yU%Z}Pf#O=0khUsb+LunOsL#?jcZMzQ zgMd|LBg?b~lMWYY->yH_hK*ZOXe)0`o8jztY^B@QNiRMz=&{uObYK!BcCx+e#oqjj zj&u+<edSS1(lTrl^&xuQ@AMjk((K}`^VUX)ggchk9-bR77M?NI)XyeEb?>r}{_+(h zv))LDuBXAv+tNv`0HyL*Vreae25H8{5;&}Qr?q%j@bGUNt~?h%1_$aWKt9gmN$Wx| zZMVlevOUM{SJ$WwH|lt~tGk3#^`F{mUta9Aw;U<i^nA0rU9vdtJANq9n9SR`(kMc- zSldW5e+Y5%sK$*yU-X@;KW4?_PReVYAJX|TUjM7brW3{6qv>2j(+L)VD}s9t6hYrl zn$w5;2bUU(DGfW^#B$0YSwa53&2;nC%xM`ECzatl=N=ui$FEBe)5mMi(f4l@_%ZZq zl*S`8D1VWZ1Ehp39L4MpzkWRM)IWovqZ9+`fLs`w6UVL`c#{bE!v*-MrBMA3yPq|D zz?QZ<>>iIMZqauQQ>jxMUa8GiyV&=$9C7XmF4e_E-<eAPw|9)G0KK$+)(nL-8?Qkv z^VIdP695UsF;;w{th0cF0h0k56pa_%^_V9*VF3VNnz1^8atqapr~|7t_WUJM9g$pm zMF{GqsnGU4#nf#dwlVYFdz~Nm9SsG3Nh&|6^b5%ojR0->;efsvf+;WMc@~=P&LC(M zy(&mRndd2;J&h@xjAOCggOt4Mrb3{DGV0`)#cu_#ZD>pKWG`ur^NY!|A>)AB5lZQH zF1DKuN5&2H;l>W@GjeOLN?7#`FWSibW&h{qiNu4qIs0#}_wQU^{0hAiEhkpj->2K{ z=qOg|xka?u`Ao6-S|>}z5e>HFuw%%sA=U-g9O`YKw5ZoP#6NO(ckOz0h2hc`391!Q z1;<WrFv_GEO^9lULPA9YF)>(Np;REgBdO}{gXR=b%w&9x5^1GR$s)Z@SS|BB-?du; z2aY9s#2032<LkWM=g>4jR*GDZBrdM1u~n?hzvxF3jY9}|m@$?5xeI+mu}Bh}4chW` zmQd`Q)nE~G<&ACMETi7@LPmTCk`))E!<U&136!d;bhe0`!Nq%DKI00`EkI#~TNx+@ zIx_Rxk*A9um0RX!J5YR~|Ha0jqW~4qu<tH?JccT03?8@&JL3Mv><MB>aVWsVvI#Bi z7lh}i5)?D6)TRcLxDPIEuP!>rDPA%co4t4$FnO^P+i)R*=byI3U*u=(y=8>@;v2AJ ziEh(&XIL^?T=Do^8HKfLiHr==Kyn5EoD*ti;3@L7j`1koB_&>%#}8vfX*#;AcKkyL z>t0uQQ#;_0Ce7i)b7Fr_KKKpEhNMJT`AzxJVjXsm6hz}^jByC`=!kXv#0rR~>iAH> zx2Lz^m{6oFw)Pe}cFDDd&~|DisjtcRp5L=|2LFu8jGh#=SQ1w@RwM~zhX_``xRU;- zoqp8*|1K5%?mLs|Uv=k*oIT;bQQ<!&EABFZfhjPFKewr3RNsjWTJCHB<*MINYV|k^ zWRwCPx*A1eU;dyO6g0VH!;ET1AIeHE#D~Na*kC}aiGbkCGiSEEBR=9aEBRI(NBnwj z;Dy(3{EgWZDjre6|5FC-#dp01tv84*GoW01{X1fBqW)Qf4<a9x?{gxYY?IxGd>5-s zN=Da<`1Q)6uDf#N4GiS<E@TDSCC5RrBhPP8%;>pwK7Shky^58<XXAEl#8RkOIpl~+ z=otnyjP@ll9XTx(<;N740!M485Ca7O;fYCKNWDZGfHYge`=g#sW}yt>FNCRMF7Lyx z;%bSdEdQQpxL`QXz95=pU&p@<tPFC~VL~C2>a;b^R@!{=ns@^pb&~`xfuM}@JbT{| z#{p@~m>u3DDmK#>FqSKL^Iacs+xgzf(gKEe>*_FVLD&Flc~QJ_>-|7Rv~lMN;UYv3 zJsExg0hm2KQ_COnL2z%1`wRYL+J=a1P)$$CWNu|y$2to5ACwXKZMjhl`=>=;*sV^A zG6Jl8-1^6WNcVGd>Bx*q?<bmwLW9<(Al3J)B14rQp8>LiuG48ZWcQo0>Oe6{hfpQN zul;zG5rkjt^~G`_Lh8^)9PSeJfDhg%c0O1fC4SbT>am(`43p4we`XF)J6ccf<-I{% z5bc~hU&8%QX6%m6UE`5{tQ(NqE?>xz%_ls+?8zmk`x^~0VUM-IKhq8W1VMNap_R{X zxgBx44wvG38IYRR#UaNvFp#8AAUqVEM12@G5`V5(KU%U+w|5nCCFpJ^4y>RNo|Zy= zm~pkn;Kt+K3>2w6@&{TmXmnDOvK_aHJPE-wdkRNi@DrYEQmDtW+6h$SRz_bZQCgzt zo_ues{MwREAZW<%_E2{>1=vHtFGA2-OzH-4C*)8{ZmB}O7{QNlOjpx%qspsN!sLwZ ze31n7@(Sfa32f|9h}3i>B*m1eit~CC^nQhED`cX$_DE@QEAAof%`SW@S*fGZZ5aZ| zvOGpCDz6!v8oa#mGXIFFUKnjkbK1FzD}AUVuYU;O&t$s}W^fen9aY<0;qHC14{`aJ zT3t*>uRHT)r5fr~07MY2>B|rjvHI0jmt?D=zVAdo@j)SUny>uYJ-+inpJRxp>iOY} zmA@SIUEWuKjK2D8JdRjDX)(rhhWmWbHXeRDd4=!*4jk)GatfvIOo*#t8VVllf89b| zKI|y=Cr>=69!1eI>9pI^{`xQ=)$8Nu4s#5KEYpq_?E2O(<HTDgM<6wun};2F^qsHu zw@j{oO)s+*CzMDxgZwi<JS%w<)WG#kKHXGDg>j@5&-xx)c#h4LF&tli=%;uxbZl6P z5>06(nzV^2)`6scX|FyyLx?S@yA#;fz(B8zhPEItyAKBrYrld>>XTXq#SO%M+ZhU# ze>R^ytk%dKGNQ|Bnv~WleCk@*NBB4s!zmKZO<!Rqffl+X+K`hB0(@I|*@P)sq^v@q z-;+FJf0}S}L`Jjw0M^y2{qh4UK6e31hkumyP%lh}YL~8!=s&DMapChDDLFPu8&0{R zu^J*d85-WAF@8unsroyH;bi?o`1KM7-C1P2?JNmu^h+&w0)2bi67b#FI9&ew`75og zT8PY2#a+B!HJUd~#hgQq85o+UrtynMvO~OfA4tB>9_Ak1{E$KSey$<4sa4I*8(M#S z?*cASU+A!8_GKSJbsTvT+7{eXDKf4=Z&!sBm#B~Tadb3?AzxcET7>yy3Y5HbKU;*Y zF%1B$=Hci38-gt2jFm&vb+re}#`3!z$O|;mNH5pe#p^szx#1(v<{T~tw|!c>hB1dJ z*yqk1^BtMSAwkv##wI_567x6EeXUoGZ}<7T%Q|RKFVF$y)&9!6(*{0cYImJEg)ffg z)0b&CI8e;(osX3E06!*B)YBj20inlD=k75Vnl<%_#`L$TLHC{SXuO;smLoAPoy=;R zDLl&Ynn_0Fw55k)uF>HUwO3gvgw#Ymxw^j95%gMYC9UoTM1gYXa&G)U3HlH(k}3Uc zlIC5-j*Eg+he*{Hio4YcMdJ2lRP?UN+4SKfe<J^WYnTrVxY-SAojLe`a(iub(@1p4 z-yqISZAZQzzvQf$ltqkwytGsDL2f}pH-fx5p9o`SFLuBPq{tlrVKZ5~%mKXiZC-Va zZrY9M1%St9CYJXzu>beOr_HUu61n<|`8NO`_$?N>^6Hf*Kpo1@>G1(<8(2@0$==A| z$q2ATu(9C2mC<^O%fvw#!4~o8b%ksn2g^GOa(rcNP*>En6Y<qSv)rkc+WDY6ba0=` zsX31koRjy{S<|D*?egRd!Zm{&KRW`G4Yc$QG6!?6Q4Mqe+qL_)*{>+Z7V-o*?}yL# zZ$RV6Dz$SZ+O!(l{ER<3w6qb{#==u)P)LQT(}lYZJVYH{NnM7On<1ckgzXSD>{J!J z7vjyrH7`BscA7_hS$Fh}!u%sA_i>)rZ2O~s#CJh_%ASI-C5^hCQltZt)(Tjh0*Kg$ zC8-xUYVgk-tMO~pZr#~@)^zvKCzkQS>(2lPcD7r3={C&G+ChYT!*<t)k@<_3NqYWC zPCYnQZN0$a2pAf=bJr0MKG(TR$T|4y1Q}Z1ROFB{!Wdc_9?F(<Hpw^B_<6s&IC=<D z4IyL&@Q%`PX9bTUNBN3LkfSIsjvzDXTT^e9IuHSXq<~Muj|Ax#cq!KIfp}yFqm$z* ztP+3q9pXPr4DrJD=wxhHRxh<}#?uYCS3djh0AxL{hP>h)%r50iB7Jt+7-{SK;F+iN z%n<vQoECLn6J;IHSps^UYz|D5G`4Ivu=W)eJ!-tGdg5klIC6o=pFn81elM635sB}G z08IgsLG^Yx(f&=0ARa3^(H-&mE_+191Np1x(iv2y&-f*Z;gpo7xL{7uez??)+Wf4W z-a-64$R?>{=8EkNs-9j9N$c$xJ6?wQvm1Uh#+dFI42YC{61R!<w&1m6n`HYvBN3k| zXP9{lS==4*C(3PWP>DP_@P4gVZLPJ@Nnw!O3zO*Z;#XNcH6kO6SaHbZDiIegjt|Fh zLk_|5o0%ptf!&RTI8*n%Ynkhm(<Ojr=L4TzKKEBHsCo%7SETG!V+GP>>BOF|0=r{5 zg{xnBt;KxVvB$e4d=CU8pIV?Vjvso?9Bb-JJ#zJ)4DEaC)tMLN6%8G<9r!FjrAi)W zQlyP%<8v*N>zSW1n`$~BFRt)4Sz7aZ5u&-9?txZiW5;fzL{<w4tqP6VM|Cd7PMvXK z!@>@iRW{?yt~Dx;O7AfDLefS@rc;7X_)~*p_)P6@pmN_dua5{C7h;t<wJK1KC{tA6 z=H1vQ9l}L?+GHDee7zd3X_mWBG%MTFRoH9D<a;W~)P(hmJZ|W_HlX6gTU!1+&Jrf| z^ZiieqRXUs#%t`4n1ivkmo;-ZCsz%jiwE?;L0O`-bQ-tvq~<Aiy*eTEiJx#Fugn*2 zGy2as+kRhoKQF^+u)6`d%)6KCon*F#dJ0;yK%LkUYi)y0kY4uwO$y}a9tZA*o&NJ$ zgQJ4VK8E+#VcwR>)pG$fto)&BB3{j(J&h_>>%oeMPY}GGn-KQ~{y<&JFrOsZtECxv zayoKH>BJSNTI<)+OpR+szf%fQkaRMZpt7Bn)8uW}_B*s&{aA~fTb~C4)|loOq_xrW z(JG;}?1mv%o92?v!Rt^j%p%BCoT!lXGk%pM1CZF2TqJMCd^qbJko4C++wwzT+^eVe z_XZS&x44rPsGIF}Qyoks{jbi}!H>imy?AYFuuc{QJHNlg3{mWYFqta~gWO$U=`RK0 zCaBrSQo-wz`{8Gxz0(_C>__|0>W&`sJumeFXHlb&FTO%u+9YDGU1&WQUYhPgN^xE; zm?9Io!^eX}UNzmR+O|c=`CNG>5h<9DXm%do_~xo-@G<=A+*u2~@EhQjK^p{GUMN!b zCg~g$*lit<zHb%Y%-0c>SbSCWz0^F`5T8wZSX_fjw2VAtNpg+q<XELk=Y4H!%1gSX z*IdeRq4GB4YM%5B*tmUf?a>AUjf2u7(MB)(HlTXNGjvE?N(#j-B>K9Ir?KURtMO8% z##u4Vn_*WQdhn(s+&*jOG@a`PYUl+trQy1KJo3gS5|Ct4xK2WSF)E~c7oAQyeSSOA zY)XOzb{IGHDJLbhW<>wz=NyY8_}E?4@f7$i@$$_xtMIQ?a=Oj}NvZYydk(FIkvJD1 z>CpXhvSHL6!|4=$9>V3D`UF<!WD3AI5R0*2?P~S>_CVPIf<laDe-@XEWYC!S*8Xea zgjJGE%_nQ;w;{`OQ;n8~;`9v>p#aE0v29TP*ZcDt;4E!pyWs@OB-y1qgh54)A^p-Y zw7A8GpW|8^YQ`J0aXhuj1lgHx!193yw?Q!nS3$$;F0-GT=Eo^NnG7&(n%C;=*C`43 zeiaOKCE5sVVSwJh86y)1-?ulN4+!N91$dap+CPi|Q;ZLYZJgb^4FcmmZuzMH9iutn zvh45vn4yp3hO~4F4`gR8_vr?@x|_Qo*DvI{CT<~J?rNpu{4fkWP6ix=({z7?#&r+2 zAuGczpe4On_1Qf4_ds(4kOtE}clwKUWl;xTR6X&xEgZ5?*p1hd`HP=?XvkH3D3DKi z%oab~o51xAN$v*;&ZY5rw2y?$*ha-?<;n}hkx7o=W1NHb2c$<&Qy+n(gL;j7c*-Ms zS`=v5I$>p{Uf;T`LdL(gwiLo*FFn7OI1~$pmQmj%{3JFCMHZ#%Bp;XzF{G7V76`F? ztTmgM>s!dp!&0Ms3*VYzE=Rh!c@Efe3Hl951oaL;eg#-J--SX3%xD3S(R*p%nIi$U zIX{Q7UiiO|s>-~n5}C>d*6-AF-?5{C7wX(&i3C7!ueJm5j(H3S>E0i~UsRcJcfUxP zzi_dvyYvpwcWA+C9s|qcmnS0bR0dA1DBoi&Z;8jxRiy;I@A7qvNbF;I2P5H{5ni$H zSmLeZ-KYx+%YB4GTDaS)W@)vUh&!`vWB%p4fahz0X~!Qdb?a!u#UMx*e(ODrMhX}2 z!O#2{2?<?l89hIoa=9nJE;X^@jF0}_P33L+*}PS(a|QZ|`dByxK7c%e8&!2V)4A?E z<;gR*f290)I6VxW{*Z+>6>uXbv+K<!Pc;`@Nnw2Rv}d$-$;#(M65;)^yD_H8RR?X5 zaCH#rbS3)S?%r;6trO$<Vx&@QFd&D8UQJ;rxwGnlN0*5NHnZnF_VLE^>_=l%4{Mc3 zK*Ono(pjQSNJs6lg$}S19SSK^gJKEs5`OtxxiTBy{LwD#4#Q}OxtPl^fhAt#){5?h z%X^g9`ToK^T=7Jd*ED#(9d{Wje!sLMTI#K@UzqGw<=HVjQs<6wXTRMe&g(_3M-Cmn zabD&gIL~dEc6#nG(oY5k6X^!2;jv1$3+#o=C+i231da`MPp|XE96j}*Kced-yk>}6 zwXNeVB7N>Ng<3m=XX)~42aR#9Q{Qr_<aRSZgp;ex!eL?vP5bos0hZMQrXkBT7qrR1 zkW=p~ujhH0&tr)^3q6>sr5;?B-xUy>5O^#RDN?}*dub#7#pf|#JiMT_fT8eIdBlv4 zw@h1zH#zpG@r4o2PO~N$Vupabw)5sREZQ01x(2P_PER^L`?b_XAwCm-^7Rb|zHZZl zVK2Es`{3i2I8zj#sO%A8<XbA!vJ+uHe<2(%ic{apo_7@jOz)%Nd2i4n>8NyzPslF5 z?e?|2+CC^X-<I9yu{&MMP`Br=^{FXBk$%YnHF{r~ZqxYru}x$|^`yK@(5kpV^vPaP zXLAO@-d9{FuQUC)ZMb@~97^+*F`2<XcLCE{roUZJ$WrkWESQ|ze}!D?<=b<M2+zx4 zg?gk&lJc20qD2H|lIY%d!Pq{a4X8U#cRrK~^*j0$CiZp2+w)i>j?;ed0O6YkD8*~W zj-EaQwQYV5l43c9!ljtM7-G^d9A!)JBov_V``8J_+nc2c<J|QDAVDdE=b1O>c^e0O z^%;X|`gIDw7Fi<%1i3!q11#oFup>cJ%gvHO`q2A3!_E?hPe^WPFXdZOQFLu3Dmo8x zwW<@*6dKSbt{V=O<o^A<izb>cu=+~qaT>MxrnObx<OEb_e-38zEr|>5dlxu$pCyRE zl!eBJhX?IT<M1<4-xpuOaYsz%kB0hc{H>u2bXxZHj%RJ7!=<_{Ud7+Dx>6{Z3-c%* zp&MQFvS~Np9RnFfhVK!!LbBvC>rcQs<rv>81EZ&lT&fb!Nxg%Z=5zu%Dit&Kyi7s2 zLx$`Yme`7LGm<T_8?i)6sHB0D0eqFj4LY~_ry}<YP_Fbf84u>Qw;(6pHIzh?Dr9^; z?FBR#=BQw?jwYx5-adA$);or~+GpCjIpTr0uRhI2&?j`P7N~cOn?7<+mMG!_j!^RI z-ZHXK_!fV=hKg;neepv7LJh<0nm7J!+9xVK1CrZHY`^VHmRL`1FoK<>tDkd={ak1A zg77K#H#dkDpannUW!CiIwJoDt*1-^-&s3Dzu6M;&DBQ<?8#dijL!Jk#t*`Y``Iaa) ze#fNxW6U&dfjiT?`U;8TV*}w&40g0aHG;^aC+9}~NH3y+HKk&{%Xr(+G(qCWDFfe= zE@Nq>__agmY@;?_H7xHBJL%l-5)u#VZ-0@;m&289MVYK7WSarqWU%qVj#Xo=&@drA zOES?|D60B-HMz3WS}rJg&pq!p!+}_77()24$b8QLLQ;uaFq>E)!K>)wfMsG^jo<XX z9J}#u($4!?EXWQO^w(Dr0)5tG^!PMFgU#(J8o5h2>F!AH9<5$dKV_Ban7n8IL7cZT zThL>n!?1%kmrr=)$;JoKr!I}Gh^?vtw#b#~97lk;<^oRZA&^>{^vlXE9j+EzODh_Q zynAQepKPi>>{qB+MM-eHD3sdeLCcd>q0uJ5l83PKuFyN0kFE9?ye!@aX62L7!>l}R zyn6i*+=Ce&gpWLK!A^94x;F6<<czY#ro7wGSi5rrt=?KhC?|(n=fB;hBtDbXiEMSr zYQc7)`}V5@&R&)K=YmESy^CM`=!I+9(2erCqKey(Xu9x3QkDCk;?DCTU6iMX`9H1) zJ3X&d?Omr7XS@c$sh@_rj;u(z=l=+p3pbXQWfL!}N&@6n=5ogJn~G;=7CrdECi<g! z$+<zyT`@89wsi6*_vi4Gng~;i$$;t_>FtL`d7uKTbV;Am0-^%$Va0m(Z)1TEn8jvs zzmR?K!s9900S;+)mF^C)<&xJ`7$*nmmWZ>YcKulMPLHMR7J2ShLA5fT^*sM>ojr#H zNqNh?jlxVJYvI^<AUy9UgNc5^Pg{%KbHavF4&}rt_gd}Z&l?qqsE1Xzq8W_!h48H# z@5-f<tt%z0D+7u)k$q{5z`NoMf@6IangctI1mZyROHJ`fodwvMF3nH<B)y8A**>+- z<^WaBSN^G9#~R@wg+TO={qTA=se+#pqZMU6)zo*-!;W?P9&y+!>LsyQ54N1qUO(t_ zsSfrlPGSxZE8kTas3o!Uc{c639JCN$d95J}&hRdA^tP|6O4UisN6ZWPg7wMNf|q<) z+kd`ozI<qKifLAD-94|*c$O{4u8qSvYHhl$b6VtM=-_db!N=U%ZWKme{$T{_=u*J8 zr#{rL_Tkd~WxS$>`Y7;Zk3G6I+D402FgmQW!BO+8zL6|=ya?-)b@k8vRT1XG9Ga^K zbp=0xOuR2X&2D>t74hRyY^`n<fpSZFX(=<Ei8?4}1be5my|}fL^7JA04AX_n2adeJ zL}EX|g7w+#N*o0QN`vKjJtoY2^|b$XPU;EeAQRiK>Y>zyi<zDU!B=9TFBI?w+aW=R zK#{;jD6+CHfRbJZ<HyNm;%dfC=P-75*U9X+k-kX`LK;NK&6{oa+rc=FCr3SbQ-UT> z!s?9j$@a!MIy#*ne{CB0@MOjBEwh>?g*iGZxhHxAcCE?H4&#b~I1+9R{8;`G82TsT zeN|=5F_~R!!XPtS(o<fE_nE0tO5c>ub`P3-ZjMeDx}iN=pZ%@@2Qi6)Vpc#ecOi05 z^xGkFeQz~=p^JeKvaL7u+ZILypnKC#G9PV+*Fy3Z7{p|6e>+LStu14G+^^==t<>!+ z?OS%Bcv1QL?2wTCwRFDuQ(za*^6pi5d()jcDgh!8Nk1gI{$zh>T)i6-?NE6Eq747S zvI5Oq`$2ucG=1#y?eTFz`ccJ~UZUOG31iU;cqt_$PGSr%8sGECdKD0Q##=AL6U`XE z{1t!EKl&^FGO61ch&z4lGMohH`G^rO4gyYx-6Y|*#5fT)v*fMIi3OU9^V~~6m#w=Z z3n#%P!2Im*J#u~i<H^#;-7YF_x!*fB7n^81rq35k=IK%T5>978w->CEaDDAw*G`0K z^`9Q?HWC@(7f9+s&AK1Z-HPzo3tu<tuteBDDObsG!}@^c5?_9b(*1qA{eIeSH|$y= zpQQ;8aR<-SMVdXCNkr<5XeAdKqqI4X%|M2l)xOjNC_qD=!(r#QnaZ6`c<<t`Lv_Eq zUv-gn6zM&kGiLtJj~nnbyqKY)Qo!2i<!guRnLI|ioV+VGMtlV@@jiE-eFpD_xV%Vx zDJ{V!{`@~b;uY38r6}f>#f3rf-iH5{X2Q*VG}pgg{mCdg>yQ1*PNiYhz+}S2{J$<x z_Ti~ty|cmy>$iUVy~sb3110>C+&e*-1&6MbCFI4=|NV25Qpy-1wZHyLXZ|6xt5|gv zZ=#JjTdQ>CoS&f>S-uth$A0}KTI-v?GC1l(QStfj&iOF1CS+ZK{@d%^-vj)m7zHUG z1QNFySTO5a`5(4M&8x@prtflQLG4$M&kL@bCxS_2x1NN*%-=V~Jdr~6KQGiNcse?| zx>*OTANHzwcVoQIeB{4>fzNl^$vjOocB$E~p7j-p(qd%Rf|D5MXTSDGb|Sqo|I5!U zyL#}l#HfU?KzZf{Qw&BbV#G~}HvjwDP3mZ)?)mIy1TDjxw8O742UEQDe~`glk7{7F zy}W(B=fB)AmvC|Z|1STJ6^7>M#s$RQb6$~}7T#nDO;t)i%HK+KCj6gw4D*d&MYAd~ ze)Cc<<6YQXU2Eui^IT2-*Pn?s2WHc_1lIyNqh1zY-*NfUC=F-(uj+G;djGPa&*>I$ zNsU6D|AVTy?|atYXKBywKWjN|NJBH-tV*08vXZw>6$}OH|M%_u+eFx6Oa$@QYn1yM z@jq6c^97Lft{_5PC83~i>61o$WOjaqx=Nz>t9<qR;n#E=uhErrnN$9wltvFU3)0o2 z6ACtvualbiEqT}3eI8@e$p%>I;>hQ3ynC1U*;JM}p+NS*<XIs+n=RuKYP&iX-lf6+ z`Y8BI38aWeFZ7cAOYCd-r!i_gT{j(;mazgbuMM-3&6NpQPM2dCHS#>)dyw?%Qgi|E zE?BIRCm#6y9gyXH;(D`2Jm73WJxn$eJLk_S55{g3gHQ~{K}=n;=UGP4ri~%vzcqi< zzvSI9ylC<~N3mGjmQHPf`S*%!%GA>mALdRx{=FhwMf5bAaGZOe+U{3CLFNRzBDa=p zHaw3-(eTFvN6tPjy~6T0Gu%4m{7FRz4ck!lUx|8o6J7g!(Jn+xwm&AYa=@Cl_sz5I z8J>=6<ZCB9{629nyvwCoy>v|TeiUoML$*on{2WE8Z|{_9l+J82vL<#E4NE89dO@_b za~9uh<LAT-UsZj{sZ8+J$RAatkKaxYdy)TDeIYTmaKc=%+Kf>q!CCXoHeU{dmaPD- z*VPZzwPu$zb%z;#DvXKl{LAK-MNK0!P2QR960T6m|FKBlF$-r(`1v}YSGR}0`9Kg# zn{bK$wV9NkOd&MxMlI1>F`o$$LY%859Pmye;pZ=ehEh(6#<qD5I3!Wdsio-C-nybn zsNqu1JN%5ZhhHPylLt`kRYR4lyOFlvC!BJm-)z%#zd}mBGW((KW4-z;yh~6v-#GDS z&qBXfv6Z4>&P0PEci`*Xb@MT=?=p(lB@=#%842e$#Ba7qbN00h3>WhfxlT2=L5fm8 z-d(+e%Tg#3&*=C@7bD0$ftV#*N_8;gO(?QJ{ieTsCqK`iQFNpDeK@~l|Jm`U^1ehE zA$4HvE?fGSK}cj^;x@Y*UtRvE^~i4pJ>?zEmNy1;IKw|%<(IVIpWC1tmwo|ymZ9Z) zkV4Mtu+;iM4<A2GmHbb^^>GYOjy0uc00-kJFF++o^$Cb)aHNnlo_B-F<arwm`bing zDc|RUK7_v*G*K!3^`Ue0ZW6C$U8xtyL6v<>*?y5vh2YIxw&pKc>)7{xnmF@xa*+y* z#8Rf)p3lr|%>(JaJ2wW7%|M&J#N^2zqte5!T|O4bz05->Cvq{jL+mzW{8yDYmo8k0 zyKT(Rd7N~?zi3xqbMZEsPnuZ$sN$vlfe9Hi|KEFsIRyYLMyqOXf5<TkINgE~=S*?9 z72g&(&__ddII5rLvvU!Tp|E!`>uNc_p$h`^oZT3Z*K+96dwye_cY3lUn=CWJ5LbHK zc7u=}f}9K9Kwqyxb5cAZ?RlXG7Z2YYUbqk#+!|EhHrTjbdK?O%S~rYRnc5Rw^_0uE zRHQF`2W&B3dJ+mun`tzCM)vJN3+4BEw_sKsug&a<Uy4J(G^iL%h4YEB!mwoaJ1WkC zqSr8^MgH(N`Z-!oQO77({J7XpYAkZAH)1j>YY&paqvtNLH&0MrlD~SW)&>@j9PEMT znF!BBN0b*GKB~~uz$3wJ+&5*Hc!1XK^Ig3>(gtVD_AmY0<^8u+We){t2QFGHzkalT zkeks>D70hh|M2Y=>={}D%U3%}d!V%aAcwrQ0n3r7bXa`p*1m^S+xq|;Ix9TRtao-= zMXK-WL+WF&LQN<i$gb;9+{JnCTRah36vui$aoALad~5}Z!(NmD*U}2k(M=<DhUeuZ zLY|41Nu}hpVNp)dh`Ly>4_AtSi58A<N8`XXqC=(lsV|h|e~ya_Wp7OrbUG2fJ`q{} z8TZ4Ux53i-WHDPbA+?3gS1;mn>p5_kFIxCMD=i5~I=y1aI<YCp%}Y0GUY-n1#N&&P zvvs#%=LIaMlK|nBz!y_N>Dn{)O}zLmb$V?@zZ(~8B?tW7HeCE;bSrb1;n{t#Cl3oa zf*(esBFykWieZVb%SDMZtYU6o(L>7PI9M$8$XVQLALu<teN1jE(t}x-ilnYrb1;b& zyk2zlthQgclfHWe8Z?ijvG>~Hj?C9lo9m@jd;7`<Xj@bx5#L3FmyzFhJScbX)a9%3 zXoMi^iPg0~JIw43{ot&m<i}UTWo(MvqTNU#GudPfYGbBBI=A!(YW5F8Z=dm{)M|#& zD$ojOO|L?OimKjck~rMg306N5wrl~*OGcn5EI&3SNc5_P%$Pl74r-noH50|T3yOKQ zW7ccCTNP8&?@wJkA6~F;zDhGR|Deo2qO~>DiRmIB-<+UVsH1atZ5H$9uXgm>qnM%3 z8o8AVPs@*eX)^e}{R%BYrQ1A#Vma)s>A+&jZW-<vZyu3rX*UvRZOp6r+}qG3-?%k+ zx&#cMllQS)xV(9{t*@7T-!SuWJ}7TOX;4ltH2H#&Rj~ABQ@6mojEpRB_UWyT`Wj?` zqp5o!yl!9yi|RF_a}Zd?<mx(up;Iuip81}z*@&T|rmBZp@>sS%PfSR6YMUD#y)=mk zeesXOa;=D$GxsW6l&3>Nc2p*bVWNu_j~(TSz$%bkxsr6xxl~V*7@FL&#3@tUx;~C1 z)q!E?_kj7dc`xa3PrdQlo{IdqN%aAmGV#ILlX&Z+%_`NyY`2f$d_g6Nr{`0AC|zTJ z^7k`0u~aVUDA(`xdlifa`S2+)s&nLsrC7vM(V%T+)W)rP%=rTGDcdcYz=d7#yGpjc z!1HdM)A5ik5flGhK_u$A%!#HO`y5r&{s$}E#5LrZy|ciSWSN-FgR|iJzTo;XLKiL< zG_`c}5w{O+yh{D>3XjdfGF^KBy+fBvW}+6(`wIAoU}XfTIvoCvGwRjTh`%zu>V#48 zMSnYld35M`Y{Bo!Ig2X?7eZ0Dceh$^DXc$MQcZ6vqwvEqIwy{86Y*K?^VV629{OdW zm0Ma)ve0+A>I}P;#YMW}!B+jLXXCsVq}A)Cm;qcJHDxi&J-yegS<87!$GIP1OduK7 zvkZKF?Xmeae#+{68oyHO)>7rLUuy<D$<u7wi|6G9!5Z8=9^%$HKGx|XwevBw*b|*K z!Q+(j@@xMaNG+_XGaT3?0e-Yi66TrFKkC3gN-p2<TGy<(s5a<9{|ha;W_Q0)p%?j( zneaNufN_q$bhdxVcmD|N{g}tCTrYUKogK+>VPSkWiNGWD9eR1VSGBrY#h~j2LM*|L z*762W7VhxSkY=p<lQKF<bA{^jSNeC;Tm>ZpNu4BFn)o4rn3}1*Q_5?&t)1f&yZlok zbGWqV8E2jRO@!umbKZ9kX;1YxJ5(k0=Z_3zc>M+=;C|akOTM=cPYqJtmbgzkcvZkl z-wZGHY=o`sx2qNfZ47aKl9p5s0%-t3r;@Ye8v>R4&7{pI0=k!BfD#celFaWyomt96 zmC8E`zOT!Kip;qxKWmgw&HLGhskhvkW$`+83F=c5X4`iaFWWai;J;gHVNVH+_7#bP ztl*oiV||$`tK`sF=Lo6Cw+8W@F}-UWbgM)P7p6Q@|4GYLBbi*GR?!&42z{gXJZa=- z*ah&uy|mcP$Jq_V?WbY=Ujl)fU)_+7h9$-QsN99#7HnT?S$$}BnRxMe{-Jg&h0U(q z*VSX%t;eeRjdv|XQ@Otku<tgwZrzM&1Ni(V(R0gK8zp(K>==Y$*@>n(nxTaiW0#%T zr-bx_;dy|g!HQL6`dcwNc?#LC&0uk8%Sa^J{20Z;>~_Xmfj?&~WGxFewlvWa@+y&Y zD5^L{apZ&@6n@%^&N#dSRclJTOndL;d@@kEzi^Yx_bEB41Xfe`aia!_pca2=`kws! z?N2xtdUx|_iC=;t_|EB?%^L5%-EdR)0H$Mf=c)Ki(%o&IeOe7n<~`iv^uhkt&38+< zSNp{Ghd_aJk7U|5`I?UHPp=D~jt^8<U4dS`?Wu{<Z``oA+={1}=zdpVDb*KUIdfcJ zwS~=+DK_YQFdAoME|5Pc<VKQ6$F2OJeG_HS5j4`{I#Ej<MDu38T?<@_&*#52j7U6* zmYJCOC5ew3E*>HfBuOuXv74@XePy41y<^20#W0|&E#+u7Bg^bd76KrB1kjDU+3bTB z51OP#el_){b=dZj7CCazQK=>JHQ$cypp+;kRna?}#uo+|MSZ#%PuQ2@@TIMkb(_n? zjo*8Kg(A&|)aFAzxQ+&3;2KCDuw3kF0f~Kv<9AmQkSYxQB{7BSwdL*cxlrXd3Mo|u zm0e;PURw@=Vvef}bDza`Ursu}<q@Ift0R^z8O;R?<Xg^$s-d$si963Y2W{Rht5=Ap z&HKObi-CjF@+e_XMw<&U&Z2A##Q)l_wX?n*V$S&w2LW*5a?jI*9kJv}t>>~iZ&8-V z3qnU)?!Ew<$C|fEq~{&Y9;Op=$?q=@a`=k}+Sjg5Td{!2m6MAKe;y4=-XW=fNI@<u z=hgaNHheLNhJ@8-@ACLjp@B%UBro<1gBrMWHT>EJRt@uHxL8^bG=KxY^+8R@p{H7s zFYBKMSvopK0vHt}56IL!R%x(!^rKT$oHT_TKJX}A+*};NBXuR_U%r@A0_xju7bqOr zJyc=RAv&=7<VmA44kpPmZrE4u5smHYa*fEU*K#ZyOM9o}ltCD<pvb)?X{@}CGLhL3 zy08_bTt3HI#nizmlxlK?R?}pKzkIA+{&LyfT}^2^H@;VktuyzqCI6J$XD&-;?EUTe z3{r`0qW6YfAC-0#H2?!*vmp$pEK=Fc51^tRl77mP9m>g^l1EipFPmjz#ff&EvcrK= zn5yBiFWZ&uFuE&_OK@qefT8H6PyCc(#X|#CDacU8(Ks6l$r$xi`^{(azA>_?1*JN^ zWm=k-G!h2^y~Ei*d8}lbZhiaiCQ3fM(>WjSY#2blp@<bZMHUZ9oB-;_MCzLH;yBUc zKDBwds4DEY`|yi@vLX*Iu=%5~f5@-<($T8YlTM?Ax&FhM4gR}55Q(wWSlaDhpJ!nN z)T5r{ERR4_>v}3oU|H~zV9}#6MI7RdH=!yi1j3{(5f$l*EqeH)^tk6&U_)@>W-zPS zbZw%RbSR-@LOxnkXB^Ms!dHHuFhu?FcKzdWhg_W45aiC0=ECu&L~C~Sl%gHkj78$n z+~}79<Hyb!S|0IV1#3@gSL;(fO9H+cFeC%)m<~f+D~azy_;W*L*Xm1O?}&}rs(Eaa zVi^o6>jV|P$L%fscnyBu0FZZEpymSHQ+xu_dX%*vwMjfrDGXZdqTl23=V(XfD_aV} zR-p}B41$9`G|ecat@sM@a%W-`(N#`327gdtmF{jLdvFMYW>B|`Z+`Yx9a$(ceFdpi z$uFd`zD)DV9xcyM9u?AmKa_rmOW(}!+LdLi*nZy5y#R?IJ#4)<(Mlk+>ixr$l&xd~ zy2!U9Iv&rba$!S6btZ^dWU^S+>bQQG##ibD+q7OsQa>yaI4k6?+xBB2WK|{}Fs+LL z3X1Kj=>bQZ2cE}W#=+jW!>2V+9bqey;3v|g9T3hq$cDl3Exav@V~u#!rnfZyBh*u= z`o~G>G9KP>{`ws555ZNGx3nFz${THL&?u%gFN#_iETu?moaS<5ggCiMM13+Sc~g9R zRmsbfC>gRPxhpjkuVyR`XLbdT&RagYZ~^KSFxT&On0IKn;w<F+a^4_#&-0TzCPysw z{<qJXXGnXt`QhSO{j<xHwbO)?Cz*S_JCBu8lwHq9P)JsBWVDbh<9@yQZ=BU=qHRce zFTcs^{NUhV<MWYx=I%bt0-t0|TJ)2~mupAY^%Qq<(jOuL!*kTNv_|xSkLQ!#ULY92 z<)!Ow6%@Evvi9j49c*J>T*h5N-XR#CZ^KMjP-Y&1VEf@%$9H0h_R=L<oab6)wg|tZ zGyEx%G_1tXLo8!(&OA}~FH=kB5`;@exs^@V3mA7qk((4<Ukv<JY;4Rv3-~PyxFZa~ zT_8ka)6u1NeSzSc*)^lY6EAk&h<)=gaA=0|c>X?#MoiZN%aenFK3d(DB{N;ODR|y_ z8x=PW=%p>0N>QQVjy0t;1c?N_e?959dmjIhujNkccC=qisqI)lf4l3gDEse;c4a&g z!Kb@BTyoVVonPQy94l`q4MM$qT}6-PExKHY)6d+=HwcTOj7+%mVeCpz?R4AEO#{*$ zR#Qyc**<s4PznMDf@$o=Y;SFQ4VA{@z9ou4$xxtCw@-_PSO(($4_9v;7G>1-YfDH7 z64I@7cMFVwbV;XlcQ=f*G)U)2OM`SuBRP`N4MW$^48u1*&-cFj*!zEm<BqlNRp<G; zN~HCD0Am_0{&n<`Z@{dyRSNk6PQfVV-@%@|yX}LycCx#_%)P$6%XD)tIaUqE+3X|w zgx}>_GqE|lAVRoFwkKX)L(jkZGrV?UWHFe%CTp<<L9CfsZ&zkAoz=nA|C+}?i+(5~ z(p32Xhmq{IFB;8-c16>nJZ3Nte#plR5=~9GdgVtA4*!#)th!w$S$zHGdL^c<5}WIh zt3)4NgQ!d$l+)Hpyzv9m>6SKdL|wnV7i*8T7OiK|I5L;gdD^~j;Adp+EK=1$BV%SG z`HY$I7kAt1+ku%l7$sF}FlAbCv7zLt*Awzp#BMk8ooFsk4F?B_RPnX;iAw$%_u2u) zl(FGH*p0dE2K>5B@~kup<a7retE&?EROElvGfYN~8wmkFPlq;S@pJAP<Mo1+W`3sp z{<bzAMB42WNu>7kuAvCcQKoBe7}QbM))0AEEq$XH01H7)wjRsbh>_C|s{M9RtsX7$ zE2r&>U;4bFZ%7FF!ZUFW=11`)2V#*4ww@}#s!93R-_`K<G}>1#Joi)@t;J(B6FJ)x z%0B>BMa-!8nyHf^QaT4$k(Zy)zUvMng$wbZ@V~8Y$KHheZVo;aetFm$8a-98{x|#c z;1}596an7s80<1-vh^+|a^G~iLMpGeB-kM8s_If0*RDS^uX7r9|GMtnZNTVT$TO+t z*6xSZqSnFv?x{?LB7}e|z&MXYlT-@*!XNijje&35&+{y#;99ulIesbKCw6=Pvyz|a zT;d8-!){|f<aHiRP?``^;vaimcarl%476F<P^$4=fvhB54dbW%%6q7HWT3-?HWk`- z^cGN>KBh*CZznYRyXOCFzBAJZIN4Z-d%N7!yt_d<2t6*!QqxmF9L{<WvmfbmcVl6Y zqyM%)xJ{+b0RSiNi>gvy>!pg@-9d@OqyWd>%M=A>-^U_$M(c;jaH4WaFQo${@1R2Y zXSnlLlKeC0kb)gK3c>gHZIS4A?^S|phVSm@GhOsd6kji2G)BD+?yCT3wKbZbL!8-> z<{P*V6l3|V?eNfn@B}MFfr*i9c24Vtp5x!&4%vRkJt2EhG0&6l4@<U{XnfsD?5jH` zu6&;Tion?dH^5=vX_fXH+q;(Pb7#4m2~WHj94e!o&uZ6vCFt|ns(m@>@}rc+bWPuS zM!nBxt>T1`!^M)6s6BwoY*Hxl4lE9VdGiWaEw_60>95v@5g>}metUIw%0W`h{kwZ8 z_3bTs<y5V)#T(&lD@U5Dx^$k?T=&m?)4tjF=j(XC&Tvb4?#G2-`syg!n|z}A?@UAH z(m5W~J?|Lm@T*hgtqMUYHYSLPh;M+<HQ#`W$qXr>p>4TA$UW5Ml-o=@R8=_dl_NMQ zFie+}F}r2&%nYSOJ@pJXeRC-yk{$$3ZOR>y{9DkR9Gp_YX*Dh!b`AlEt<$i}Xmjzx z+9+m@8<Gf^szY|3SyFU>H&oQ}Lq6Duzj^lS2I%GXHZ2%=;rJQ%hL=KDBKx|BTsev0 z+dlR8P{7Cczl-PMyxAQh5cqJyePrJU1E{n`dhI<_v6)YY0&7{MQOZG7Ru2xt<r|t? z5w@NV#fP<t7CkE55E6d6GVn*7e}Fjw_t0q1Ixp+71K%%ZtLLybx)V5mUU8Di7h=cw zC+W0#pC~_a?8?QTd*GQDJ~y60TyxG)h@IZ@lG!Pb8TrN6YaS=jp@m+1iUX4U9isiH zG6HKH6|xS)p*?WfRFMwU)%Qo*JXD#`PRm+oyKLVwMaLg`ohGgqlyhNph5piIqXtBl zv@=$ev}224w{3j80m31#+Tu=U69NXvk2wv<C?2s$oh#d>(0NeuRhOIgyl+@nkKNAU zBP(@7Z2?slJu7{_j)r3>6*wOB(w8EUW-eQf_C|a%%z{AYu^>y1L?^kVc{gR`BeG9( zEE#)XKAsVrYpD=<&$n!IFWO9L_s>&(U<eR>=lcJE=pR4QXJwhN<AU%Lzs+erIIZPn zwRw;OZ5rxrEggH&n#?4tzFJplQ3z&QSlwveBGC$wuNtNm?$`r2z&d0%UE@r03VUD% zzZcG-A)}^WrUR+p>goquQ6aEkmyM+ho?i|?aqJzrFHoEW+`7G|6aklpo?5mF`U^<% z6qGNI38v9|2gUg1D`8V`MS2nb`Fv;tOr($HSz6Ij=WZl(6Ih^#ji7?VHd)m)3!9z8 z?h)Lz@amcK;W_V7_5JK6#EgF;u`$`X_Lk+~jQzo&XE*d5GFCLqM?tH_NDAzZYi=E$ zK%?X5_c!p6AM5Cet48hvag`bY+QzO~OuZ%Y3LH)0Mrh`p3j<J=+WKF%7m%gz-$;7u z3?O7m&BXcRkC%`w_I4Vkew%ioplOX>P^`tl!`rwc|Ah^Uy8RLEq^J)JWjudhZi1gw z3<J%Y203}#P#?7NE5G%D9%U7desS~X=}2yaNs>UI))|?ddws@}SHV2PpB&*;Pa(&= zc3o0qOEdCZf#$+y#u2O6$QHyxFhA-uEHOp3wH_lk=}y?ai~V;Fp+7<gpYdV$c(!wv zFItfm@`fp|zcw|bgJAlP`@->0q4A_dF7yX<(u{667B-?ErZW)eV+P!!P0}@$1lEQH z-2@9e`3~Q;KZlQai{si6Wf2Ekl^*6U&s#de1Bq{u*Bb>dKh4Gj?1IFU8u{&Z@qy0L z;;@lpa&<7D#sKI&_Y1m1hz0A(eUFJ^-elMITg6+6$Q7vXn#4#V;8p-9*C*)@*poX7 zkWorv*O4F)7t3Ki#v+C2z~y3q=eU=B9jES2yRt_A&SD8OG*l9?7(;R7eCg`zNvIwp z&fo5T2+<e@aqJxrg6ZZ)UlVI541wrE-Pkh;8A(35;-+m^aaGK01_eXiM=|I-Z%6fh zR`i>Q;6Dr#M@Y)a?oW0xRiGqVo>hNed3Cz3Pir3CaTA!sZ)TiJ;Gn9duph(t)2JgT z9OfYEpP2Y{HU|oPe!2w#;rEYcw*uq)4X1!#PdCf8zu*sJT)$v<+llKzx2u0me(^nb zT0(8)cJ-SZhc#~Tw{NPmbJ!SvgK8O;0xWnNHwU1isa*X*p05vjg;`+ttP;I9ktV^D zJgOXshRCKO)=)G|pvZIAV9uhI#xT^x9-xa7&Sfn?XoPq$5t;L1szBl8pT?Sq<8{pW z;@cVGu<BZgl5_y>JAlj2gfUl|)i|G61VZ|4|H4z~0(BEiB5gtwbAQ@n`mpI;6C-~V zn4-g65)SwaxopW4vi}ANDK&zM?H-!-A^vtLY*g7bq#MREe@VdsH%g!QE)st50<Zgx zL(OFRUmUq^SR3id9Ud0c__T7`eH(o8d-_}PC8RKQ%Xx3kE>kqIbY?9<a*uZ`1+lTc zLP3M<f<(l(BF9CLsQ3oh{pEgGsCtdDI&=uskpgKcum37`%R?<9#i9#G#FVNsxrw7R z6cCk?m>F9UiVb<TCsfUE>rQ}dEWU}x-Jcse@0QW`fWUmRlWfs-xFVhiVsRT}nLGkz z-(OL}Gp&a0fDO`GhhJM{vTsgg995t7qfP0@#WJyUa{(n{ByVwFYb`!$8lOWZ#aue2 z-JHE|`$L9$Ita}23uhSnK<{~5J}OmGgIVdw-nV?<g{C43$)+rT92>R0TL$9@FCdz2 zKEK8+-%ox9kW7n=q5dB7JglJf*nUOL%82LTAOx(DM)wU@^}<pRQ%0nv!}Qtm+S^mn z6C=KF=Ty58+9N(nCyQ3Te}#!!#so4G40Qh6tm6~@HS2z#_|FY0xx+5&-75t2=nQ8J z6ZnpPup6#p0(eLtn*!A!FR+=Tpuy_LC4E{~_}5+#iSNOcynuzqz9T9GjPra6BYj!G zK=dGUZbPwk(#2@oJl>?v>-9x{L^LfG>%A%xP?dSecA3F%9Aq)8o|-*r2!~zUfPw_Q zQa8a2<FPyOZ+sisu->sdxUKs4gsAztI_(*g)BgscQ~3M|8mIU^+G^se@r(IG<`;X* z?$2|78@6T;gA#fc>?$@N^cLo4`o&jjBm;1SF_s)|ESK8z>0A;6LcpF8$|eXr#pUZv zfxAXDNwM^|TT^hCdAwMrc6ts(*Wv#=4f0|!sQb2*MGIevorGeueJta}QU|F9AU=>J znZBHt1KY>Kh^DD37S@~DeQ|}2$C!#Zw0e#qA&C;8>P=cfa-TZH`Cy1Ko~Tpv7S<*- zvm{Eq`f%yt_u4OQ5JZ%+Y5VFDV`kOY^yl9@eVI+LjGn)ZslNED{c3G;;`(U9j_D(` zsZ(6i_0EGGSH2C}XxQQi_?h|9Y1W2D_78U8bAr%2#H54MwNu9P3%>*V$E*6E<AvZE z&TE*vz}pu<iC8;J{NKz51|z#*tSr$;gLT{{qHur@EjZS$H)iUHsTDEp+JJ+=76!rD z#2`t6jQTr|cZ{H%UjH)pZKZGk8*OLATK7xt%6kue!Lv1<`K6l+p8jgurc@Wi(4}8t zE1;q&h=}{Ry@{6k7UUJvw)@)V?R$J;A+YuJ+rnRbFK~r;GAx}<l#8yugP9NjJH)sy z)md|q3lQ@z#euY%4DYhC@Ytk<?pY~hTpPAkK89L(OP0t09wak|Oi6ETfD`M}fbldW z)nlF)Shq8D6Ja`-d&_NCArkLQPy+~WBvu||o2wDeRsfe`%=c3jaYMev?@h2AKKRHp zjsI|F59~x{Vz^+)uJWeZE?YYi@IGiwq5Yk>2kwQ*zH=;#V@dp1_s91Mdxn!q^*$}J zIcKD-2sB3BNKrtDGZRBpcy(1N+9F`|3!vizuZ_D$?PeD{HA5K)^|~8B50IFPKf^Do zEP)KQ$vesm&YeP`DKb!$!=&-~zHdfVMUos{1r^QxrM6-B{uUFyqINQ=m8CyCiAq=a ze6m88!f{0Sbnn6LPaaD3IFSDxyw~-ayG3kZ->S{K$8}XgPi43V)^_}Y6b@U=HlEDt zF#f#<hL$EE@HdK!{q8Uzg$#!-r~SnCLo_j$D7NF}%fu#zRjgdpduSFrlEkLl6*iR7 z9g`Se^$_1|S~;^cBs#t5K}@}N2eCRZ`GR<81P+iyo|!}2Dl)oD0z|v8JbA{y@Z`N9 zWTIa0++{U^SLr(ke3KW_pF`}O>eb&8jgiJofC3tfyW_4CoH7EiV{5@7Qbfpig0qc& z%s>3_zc-PVw7xPN0BH_@)QU>HL)j<!A4vw|n4A#r=w3^HPnCIJ|J2t$iyN_MVHtoT zHGiMlipJ24NRe4JlVSnhL1{X#fdwKSoF{NG1&1aJv2I+pBXjn{Sl$DX<|f3COfNf0 znRUa*YR!VW)+RtoQnqEtZ0S5T?`7_LD!G93mH{s$)XOgHzs#F`*uY&xQ!F~+G?ns2 z#?kC+U3*I2VoC-a!HiyMKSsD~Tc=aM?DylM2RfrT`jM2n;fQOxCEE5lnwkip^k2HE zJ3`P9xPNu@4wW-4B%7KjS?3L6WK(R%l-eK5MvREt+?gv#m}21ZlZaNb2rpo98iL~% zji1ivx#X}Co8JPzV%0|3e!f)L0uOr(FQTyLSxm<9HaKG)38OmPtHgB}-2Vn0O@TTL zXTJ7>5b2>*Msm|$Et>7nYK$W?7x3Vs*V16z?2MR>K**xAP5u<Bus-Y_!xx@&?0wxh zr1W|0@oJNCynWxS@pL=gpDDw4E@sF-CHe~4N9?uo;(Na9YTk94s<9v^4zvZgb4WlY z{aIlqKI^3C6H?3Bnl;J~e4i92%kQ$k^S*Z|9Gx<A>LczdeduWl!J>e}%eOB+QAy(f zIs2=Yb8UX}Bb>1KlYB^PQ5t=8@D*$#67YAAXIso6c48CU(AKq-#ut(o5l|?$*lfDB zIyBJ^A~JK@VmH5}Lx4oDDz&7y5zAnde}aXF#Q?SD-itdCy>X<}+~7AekC7$&F#V38 zd>-EV!0;__PjlW(V7U=LEaw+&QI&(_1+^d?xs3k8W@f&vaDwn0vhbNXALA)i3r<M~ zmUIwpgXw#jTt!ZR4C^K*EF(@GKzJV^b#MLSqQ<ck6vR~3ZXc)hLt$<2*g_eqeD+XI zd0Q<DWw^XD2lKfJzS5^Y$5&*Ua?n+DL_<X9eI^4^5y}Bd`gyFLq0CO19O*N~YrSj^ z`uvwYvMyo;J7XXLr*1+C?tJ<oBpTv|9>8DoGD*T5fWtbuoN1$2M8zqVYG;(_-*{>x zrx10AcSP+5jGCM4rC$L@x(ARcV{qNoBsbX+)zGu-XJxpj7*^2$qVpa3?uFWu{Jiqs zI<PPC%4bqWGkYL3eWv*3HiDY6eBe5ER5evRfeb1&iXGRR-#sKj{9LZIXd-ti1Ms5M zH|=)^MRrB>lh-l1qXp_*oRoaveZ%}a_Cp%WyDOer5iT3^1DC$s0pQ;(L?&w8^k<=H zn0_V2;G#nCtC<eYy<fE`D~*V^Z-955)i`L5@Q>dkQ9e^Jm_5dRAV|UFjwEX;iT3{R z0&bMzl*)8~tF&VGdKBfEV$gO%W*i&$+aDF>rKs!|hzIvtevE(-d~4v>&3*RdVrhCS zywVO5h3WGhj$)UTP;Qf%AH4=P@9u*CooEZKTI1V&HusyXzi&t=W^#E7bh(4R*y_y5 z$*7iU+>nK8;^x~MLsQ38*-{HHAf<5=WYz|gZz-Ug@nLPOtrZ%O#6Hptp0B*h9k+aO z_4ol#w>(Za1;Q<ECi#Q>Kl<ro5#3!GItIqu25!IY6Ep8yafvuMgVSy@tf02=PFa!K z@XBS*;?gp8Ul_e|=0M@<TJ`MAxqp<fhi|vuK?lV?cF7m222(mf9%dn3TJiv1KtkMv zwejo6?_SAF)!jM<h+8Hy@OagdZ*|2(1@=Ye$2b7?>tsg(Xw0Zzq<grFUBiT-=Zd8h zIAWRN=Hk>V!{>oWma7Y^rzm7NTz~4lHiFX=6Gk2V0P=0=Iex|&4w?6O6$r$X8K)$h zltdYoiuBYTOuk6Jc)50r5}#+%5FCprcnvJ(#yl1=#Pm*DID-fL*6@UP_T23+IAC<W z<D{gD1W>>z`{x%Vh;q^p)J^~amK2SO#c>L%s0d7?tlXov4tD;_Y>?U%<(*dGRH_l2 zQed%1AkPvW_!o=w5i%sUbvkre>^JMaOWUOvJm^nw^KvqGQ!XjH;kzD~msLty4`6)C zxY^_@+O_)ATNOg)o1V6kqvx<NhsQDgI|%_2tNpq)yl{*l7WK5^R-5dv^4TGJv5Az9 zOBH|ZC6nK8<A3RqcMso?={)z1kkJiH8$uQ{5G%1TKGN2_{Dn5TEx!yf>AnA39lkf^ zYWDg!`ZQV1PmDP8dJ)Xb`Nd4VGR<(7DsPeo)L?Q~!qJ+?w@bTb#EQ!y?mkkEIxL{G zbHQkMiur+fEYVDsIxP5TCx4VfSwxyC*M63a!l@gu5Jl~!;+!uvCL3)NcMmspVV-dH z5hE%O>0o!Tp}KTa6U#8rmBI4RG+L)|lurzrmr70G?BTT!U#6`=-aewnE2-_R(_OOp zjlnrfW~@|BXMDve6O*XF>mM7<+#d)$59Gd-Z;>(bV*~}n&v~NkWm(Pd-e&WGd%GQ# zRudv0Uu&w*y&$enb@bJap^9O-I*j<(goksyAUh9nf5I7~aQ&k0$hxW&H6@CRCNbJo zOA=*}lEN~tYo%6ZWus>^$+OPfIKw(PKOL0b<l$x?kUdB2A}uzgkJzJn#o9R`{#V@e z{`o*L*~RtjDJ@)O)x~IwEz{M<R^g*TOIBk$9ytEgcS{rB{y^t;A#0qlz>Bzq^kmJ3 z9gRGw=chMk-#Tu<rI<v`87{R2xpNYvY%(~3-P@Ip+AhK`wtQ$&x(a3E^9#>IGeK!O ztz<XxX@9nY6cZ_zu(DikDup9{wtQ>PGNQPBDbxNOGGzQ(i+zwMPvVAMZ;KID>+WEI z!Bt_KvP$#e)V*#i2&luo5*UBup-uAXd0EFXXFpevq5Ds&XGoUWgZ|A>nMRaQ1BspC z+oSi#_x$TDSIRD#$>9fP`fouKC<}(Cu$7k*)wX@PyCl|eIi=J}E$hw^ewnJy4WkXD z?D!We6PDjpTL5wI>OvkCKVplU^`-Quj9C1b6RK{cE-+d2J9Rnq>n?{#njObeQBCk) zN4~E<9m3oCc>2DDXLYgMM5PXk-2tLH?&zH_1ZDPetUJR^umG`zYGv4vcaG}4XDi*W znU~(PW;`@L-g4SJ!}<-Aq87=`ttuJBh0^=eTbSh#U8;*_t{PLdz3)8b{QJ~-{3#mP zaw)tjXpH`mb_(f-*7jCV4uFDg_k>t*{*qj1*;b_D0D8&g9?j7CZAytf1tJdt<Hrnv zniBWZ?1w@FAK|7r!8aapct~5=iz?VUXbjmBB^dHFpPM@#=_6H@y_Fz`HMGx90H!Sr zhPo5a8kmS|O{mY~hCm)0usPxxa!aMuE)Nep8%u_R*y{L$v3;ipa-_JmO;2XV{mE`j z^Rvbt^~p0(*#s^ge;5%ZO-VXS7_DU1i%=)VBF`KejtDSG<sivoX-;h8(l@`-j9EG@ zocrl0&-%FAmdON`aUV-`5i=$#$c)ZVs-!;<bjvv--hxTyx;Qh;enETXELx+TMP7Nx zsjF^*c5pY(Y>(}EB*jjVVr1}pCuW+{OF>;%iG%mg!Y3}5#UP+Yapk&q;^q^bJn5?O zwb+Sv-Yb^z+V)`cGb+MKj(pEwzA>Lrn%EPEMT>><Sx*}S`-SZyG%(%Q7F-~-c?w0@ zCixDAev{g&Vol1CIeONOZRwS0yR68n7ZYkKY=Cy*_^L679KN-WY@g1DcmUrIKJItS zX=FN_xJ~^zaTKHlG>rhgQrI}w-3JSPGBT--?<%zCdojj4YI$fT^rhA`3lw4{SGGHo zyizGY)JV5^{Fz(7T$vza;$<*LpgJa$e@AGNkChA&O>cp`y(TcSQtsEjfob*Th3DxA zuql7ckInH(CeH+PPWr|CS+CHKmQ|`Oc(3fyfK;IUO`h@@p#7sVCYZkBl~t8=yX5q% zk}dkB9w^KBmUVCg2uPmu-knmh2m{{<pT|$f8;lu05{7a$su?9977#I~Ov6Uar~J9) z)-DgUcM6*={1!Wat+}ewJmxxtqnR<jV8(hksF~9k^Ua7Q@`ENcWzs&V=I1tM;oJLi z%fq&ia>%G#*2a)(C3{{OqEunI?scO~;{yx9v9W#_2HojKyH2Hh(G-BFNb<-~LHPO@ z_BpxRr!I{Eg85F$|4p5ooVa;igL;U@M>bvkHx(l@pBHq9qjB^~$Vo^(+)-u&Y}y^u zZfPxRJ8W#-aZD#8I39!Mxj7jMQU>mBOpDE-Hh7H|jofyUJ6T`!F$X|Suw#_(K?<LR zhhJj8yyTGj5KNYJixMT>K_M#iA`cHZxvP{kwT3O9FXE-eFbP805&5XXGzp^X2HXw7 zpazZHur^k~ln0`-?6&#%|7a)wzX?$oTBb#?jf?^6he9ya$jGVWd;^;Mgl9$ZLRASr zFcqYrdcmvQ5#10+h&cSZ4?h)f<VwsHTii{Jmm$_j$@a<7rsLg-O*JniDTe6J8+W8X z_r0K?1?NE7KM2aT&ADi2?WBL!a|<rS4u|y?o-RT>?mRxP{iaA%YPp;$#Q$Fn25~)F zU()Ptjb3beV8AI~;&*&$IEzBPrQL_!p_)mp(#@AG1=?x7cm~&OU|mK6<gN`)P~DT; zy9URJD4BkPPy#o&#X6M#9G!O;|LEfBwD_94|IMK;_e1Uo^cVhY9KgQ?S9?YQ`n=*X zh`x9OJ{t#sx4?sve*{9nX6uJU|JQ}!rP@3HyAV?N@qe8m5G{JWQ$k}=f*PhzGTuD6 z{tg<KCb5=(J)$7dYq87tCd@A`&mxF_YH*D<kL4qmQ6Ef1myqOk_$5l%SdbBqpfpSg zgbb%lBnwzjO1XRLWnPsqQelEVh6OwUTqt+{t1A8PH9WR!Aoii&2IBOCr~nfp^dd`` z6oQWrCwkqh@LIR&WaeP!3|m}G_(`v$3<Mki{Amj{eg=1kSU`pc7do*yUL|?m<DGwN zUy%KSc?tR8%7gwW^Kr@rI(f`i1hjTDaqXG<pLO{iXX1+GLM5s9cAJ)e%{mwMw|73r zm;$n&UgUj*ALs1W3FIlm5zwH_S>Vm04b*z2srJ%l-Gz{m783AP041=mHuJtzFAg_` zL1}Ot(p9lXtwX3~m+vAo7jx9$Ur0ZC|JC>;wOQt8_Y9Lpqn)Ue0aK0IUi7Pk&UKpc znMQ*hU4vbPO4+)`T*PUf2hg9((ZI?Bmu*yL&^Gpg5(&`7G>S;5Af4ZgP|P}!DNJRX zyJ~&W2XTch!i!B4Rw5^Y-xX$k9L7m`hKalg_U`7`_o>QFCUE6)^`=Sb+xz{uby3#n zlnYmu*!oOu>g30hoBlqcY;35U!0&`OZUdtZDmW!`cIc0Ry9TZR@I3=3Xh|ZCs?S}- zhlb0H2=D9g98r;Thi`k(em2hYQ!fw>e>|%dy3!7Yi6{{W1q-^Ybq1vYaMkToG&0z{ z<iF86%I1PuyeNRfLrdCeqSECyY3;lU<-@9#VH#s;?V@KhqOP6^8V;#TrL#C5E0|=z z(O2HZltwCEmsP5n8<oA9%B`KPT*Ngx{7PtL3e*rU@n>twOkAdBr6F0!nA0zBNhL3u ztw)FrawTgzhm0i&V~>rZ+|P-x({(sX+Svqj%ZF3#2PLeT^Hke-Q$>x-r3yS)-OD32 zAS?og<xFX!*+HD@quQ$F>53{khxm(@_|dPvXuMAP*W3^$xV{PDcsduKcf>g^0X{t$ zVzwQ9jT<W>*A$F14r=J1tPB2J9{N7mdu(EHB`YQY<U}yZjK@_$5Er-w?#3Uwa_j;N zugQM}$VC<M)H%Hf+tSmfqF3rA=dVK+fvO4ub!wbxx=T|gK@I%&hZ19;2A$sLve}8M z_umTpqoE!p*5^KsIQm%fO$2&*e=9~pZ&6B|!H<nNlvV;4+KQ_`W<M)Vs2@_4<m((V z>!=lKl}Bjw9~^?YYcvO0qnNKNHEx-`%wu@#0OjQxx;-oD{TytiqJYBIwClU`L=9Z4 zY8$9Tb$+pccDd%IM0J(n{VzrFs@ZZRWT8)o<|W3O_FWoG=iRc*UUb!RsiG=(9(@&+ zvk{6;+V-&;C%!<HRQD1dFqgKyfC~@8jG1Mf!xl;2E;9jwvF<3*ft<e;y>JPl-5dEd zPu6k|l?g3(@s@+EE#7g>ny+6!=X$~^N8x^;4e+2o`(G;}*AHD7`h;=0+UH>$x8xIU zH5#ki3k8uHpEoTYMS+}(Emblea-Gpe7(y7@zG{o73wFZq?2cR9)mkc4X;i*;hAUK3 z&r#r;iC(X~HP&o|)dM-D_Kws8*L9mC08HxFmxJ&&ZkNEnWh$||DsNcS-;K__a0Xqv zV*+(BmjO%}h*kV#)$gugljKPcf8I;>8$^;lT7L5Mgp)XnqS6<{GEz&?KKNrHicz`s z@0U<{0Y25z|L7n^c8E_XI<L-a#<7_D4-tR*Kpupn2*05h)W9o}XysLgGJbsiwnVjX z18jII(9G6^69&OxqIi4_R2@!#e<Z9_K6(m@LCT6^6^Pw>FKSp$M491leq^PcCo#|L zg?_=T^Hq)c`i;YL`f26bh9$T)CJ6usH4OE68hh-&83cBmL+Dw7Fo4aVm`r)ud8MYf z%QyMx7%1bTqp)GTmJPzrQCxWTaKDG<DNZmwHxVSTuJb4VHT36wN6&omocrC`%%)C= zD3iT}p$Ej*TIZqxrF%oQ@&5>c?_e&+SP2zak>-KA7cV~H0Bex*M?W3@95A-1`jYW` zZSjfweV>`)Yg9iG+(M>{n4tH$oYqgC;?c$tc1Ay<w4(sH{1-+Lh01D;zpQiAWw9vA z2D)rsnM8ZG8Z;AX59gnaGQzfuo%^t(EQ3$?!1!ipD1vgWx_?Ui?0k|iJ*a>!o*7;2 zYg{Ld&Yun&dSHuff!{PtSgs2+u--<IG4ctBhXg>!YnP9tE>novIm$LvqRoo6Yq0Dz zneqwlt_kN?pVG)>>L@V1QDcXz;I5pjbcGbD1KN8cTGpsK@ugMXzcMt`TC%+;!#B;j z6P)~r!T=c-fI{5sQaUo325Q;17|p{5+g^+v?QG7!$>huqif-(Ae-g^HeW7in71;B> z<e(jV;X+jAYn@LXY?Fj^Q2py?o^CltP2A=wbse=k>2i`E{f6AepQAgD$Ld^bVs5Y3 z7ef#1<M?v8sh@F=&t5L^cryESPuW+g=5t$_Ws<ZmZ@q#2KwU9pK{6qK_2T|xxmub* z@$BkHFO*gA<~tl9^?+Duz%^<1F)3T0`8f4c6%4z8FKYED`s=X5*v(JFT)%Rmt_uwV zCbnuij+9??KYI8`&4X6`B#0H~GYz^1!h&M(J#0iH1yvE1e_by<#95Z?s8kK8+UjcU zl5^z8F1{~QwonM^MI3JF-p~%L{8e;dE`M*=WbS@b>cul7rCxfglojQ}`;M!0lXqPE zI#fVX9nD=WhM4D>(A=_#(SqD#F6{2J!|pw=MX-Ljp`lPDaA026Z0QG9`K(sk4{p9q zJnQP)v<HoHhH*QxMmrlJ&{Rl(2X=vrk*eJ5Bl1GL!7~eiMLkhv2ZA1iT!G<TZ9>YF zzozqqT|}T0Lp>B-7LU2H3-(eWTmJF=@MC`B6~(u-{mTAKZA!S<*Sn}3_Rr=g9|UO6 zuXQ3j<P;i-q7#~=mM(;0i$c|3KDNK!9ClwGZ6D;)Jd_{+>+6vm`6{~631?^xWk;XB zLQC*q63?9S6ntvVNCSC?*F$HP=(8p1AIOTz0y54&mG0+MHL7x7G+K`*3`X4j?c8zy zrEuiP2A0$U;oGzfzNEf0ig~)N$^Y4MlgjqhKw~<mijb=$=J;cx&=d4c`zZHxh559- zGFm&YR)c#$Jds)efm#x`ckqzjuDwM`iPu-6p@cG0aUl1gUtR}rUb7d4aa_c*=<EA@ z>OIVRSvHQ2)kKCqp7|g@CB*#9DF6D)1&11WN)ZI2rwJy>@t2rNp-GnCVg8TK&hm0d zLFa#%LL8uTNVG+%##t)|y);Xn+-dnjf%xb*KR#-X8cVanwCg_|IReL)cVNMO`N#0a zC^BiWTj`{|%dR@Ae6Bav;(WlU&nqa!*W`9V*u$>Vqy8UFVyE`x#A2Rtl}QR-ZA1+7 z+|4$BXX9a5b-J*j+N;kr8%=7#RCIbvaYkOWVwR3?=XXAaShpcxLPpsq(ormfHSH5M zOkVJK*D<$FD^}9tLUI2X&wLQlCu&V*Sl$ewkP6WhB^ViF1fN~pGJH_2##em$$f~c> zoOJW>#Tyvyr6XNoB^Xyy@cvSfUD`V21I5cR@LS?NzLnpV{1`{vY8#}mHnhrPrqx}4 zqBmaLY%3|{UAp=)>CK!~%D7<GgRGrj*w@_uOb0lz^tQcpSW02lJf)g5BK%G*;H};7 z=_>x46rVp)IRvfP;=or~&j9Rc(N-jN9T1G{v3<TOkb>Y|t?@H%EC49QlAZDqmo^Yz z>EILWUU|M^c^}t=?V2e?Iy{@%3qRo1Bom!UQHoC#AF8^(cQ!E}aq#ZlH`UgDXjAVy z>|CaWUi}Y8zre6_-q<I8)?)s&K!S*;%!CVKD;lJ;S2fccsX6-;s=>{CCa?L;Sh=mw zOuvXJ6F3eW9lRzkqE_}8rw2pHbVR|m+^=;CYS#v@)<#x!$6SM1i@uY0wNqy-?D|Jj zl@yILko*+lNtrq<zUHx8wG=bWt(j$Al5aVn8Mnh{l_BX$p7)vdCkx%|oa0S`pQoA_ zSR6#@YQ8(;oqEzOf6f#Q412)5^Hx?sJC=HI5<mQym{(yMFFi6X*!qbGo~QWq-lMOh z@v*>>Ag(xz8me3{n7MDQ?$UOXRJgN4wsb_|zYVPF=2==oXBjr~q?q}u#ku&QDbb5> z(?~nU4ko(v1Xy|R&CSMHKZGEeJl?`Q4o=!Rj2Te;2`cDk_T-%nL79T9viW)4hvD@z zOCbl_p9mO30lEc1PII&lX1(ZFQ#R@3zm1j}?F53w!<ScZ_PU^cmsvLX494`!piec+ z@jkHxy`Hs6%g=vkp<*oQ^p_3?VEo<ol{(1@5F}-uQt-~xpw<n&ig285Fk;|bkl^x6 zY);s275j3|P8&I9O)mPX_KcU>rP$+;8^U}|(vX`1QX{Lj*w+<Rw#(0OZdhYl`Z#l3 zEEA(|^(#A(7pOe!8_Sa^8T`saGoOS3yuDx9d%x-CIhH|&-_DVqgk&giAjLPHvWcU2 z#JD$tW;V^*OYh21{rs}2%)(IB%*!IJz$CsDs$60>KLr^!jBDrf$(2!VR?|#5Q&(T! zFPV$3ATT2y#x8<-yd=9z@()JD&B>8)*zexIx`ef*L2M3k5rk9znDQlx(^C_Xwb%t= z!xq^PT2$VAwNB=@W4E~7#Y-n>(mjSahcNI|dOcu<3qZil^vCWX;FOv7nR`{?FZ82z zbkOgY@$#vl|7V(j$PGxfM4XmK^c0aY&00(eeL+8H@zwd;9(_I8Qk5E2m)aWN6qtAp zyZ50kI753wt@`FjFUZ8UFHX?TuFjQG?SRY7aH}{CXUTrD?;MFbs0+ciVP$39D?Ij5 zy=sDwn2*_@Vt9xp&YWG=t-j9Z!!vEowo-5O<+RF!TOjDC)HG8%o%yr6m^R{+G~!Qx z!q}s_R`to%hTpbvW?Y3NIYQn6TJ3*QA0Tf}`*kPJ4Onug&SR9oBMZ5DeGgET-6HF) zv(#d-EhH~W(I;mM@7TC~Fz>9pxPYA4l`JQilsN#o)FXdZ$h&L>IbSN+4VutmO>grU z{dUYfvw_F^Ab8+{y2;O$SDeZ0+FyPs3&PsO$9iPqe!9Z~xK`EpVEn&(!eAW(dPM?F z<_-5A@6rpy^sxYP(zbAzL`iGdpw~;{0^G~983aW0^3IzNd-JFH^6oI`k=vE}d*yz! zt@O++PUkthax;Z`VaCRrznV%M^6lAkLXkb)-C+fvdmmajN`lkUT5p!zgtc!)>3%Rd zo*-{5C>p$LHNXc89zxM(W(+Q~zswYgPJc*jC@3N`5IVne*g&rCWdv7#XJAT(#AYg_ zOJ|W!Ee00{P+D1i7t6EE-W-bJk#T5VPZ4QASE&6Y0;=!Ei@Xsh$WT4{sM`Ip&f~}U zWvR;hlo4D6Azq-oU5hNsY3eUV<K7W!RwD4HxGC}^%)40NtKpEMw>D0RRD!uQ<n<m* zGyd1@VOx;wygH`!L0jC6b?Sqe?2)VTnJUsz^+q7k16Y6Dv7N?v@`Ep-^h_Zk5KXTt zj44{*k<w^)(HvTVhbd5;Q*CodDxGnjUMb!r6sDkk8(%ZK$rg9JVJ~?bfT`n`qHu&a zdaC@p%U9|y|M6JhYEDqu$}p3--Hpx`p{&`}8jnLE(^p^()apI#u4+n)>TI#W!z@7{ z=fHkW-<7+;MvLhy^`v`ce-4&Gtq(`nF#k8dYOFF5Zwv(&w_l-N0L)EM9@y2dJ%0tk z!Cs&WhTWS!oM2(MV@rwdy5C6h1K}aRYfEYm8wFiauZq>PBAq2cff<v2kqVWOyMiWA z2w$}cS8=U`*&>Gn;-5mn7?&RSVu9g<AVZ#aE~eDNslM$zqTO|O9u}O7Qgy+eaSd%q z92Uw%4B*$T-Xeaa!;O0r9(ZYHf)27ar2YHnmk`Y_Es0sTV+P#59m(J~@cM^J{E5bB zmJ1!c`bm!fsBv_m8_C66p<Hjf4-sktF1QE791|emj-Ml85ZsrsO91t#AH}1L*-XdK zjGX&Q@Sh5S{hp6MJ=Dz0KsD1z*&(l5?8rx!6~9y@{_Y(Vn#HKBvLw|K5JX)elmx<3 zs3gDzDEV>!X&Kua=Q~>Pe4kC)ei`^^hnS}9*hqj$30Ce|Y%V>7k*wXB>_-vQA(I$* z<WsF$%t!Qu|BB~|#<`CFlXSr_@hr=e*<URNO>EYwdW}Tau|dJ%E7pxE-4ri2cf>dB z3$sR@BE4I9Q&X*qC^T-|1>UZd;LC2j>QgN9;>SISx-0P#b_+fo264SC0NXqjdWi|L zn&><FVVDuO_OD=mb?wW=rSi|$u4w+R1mWNmjLGg9a_xWSmU;x(d;$oWPBq31T7S$T zju>1WINY`#%dU|yM0>AaNc|>rE!ASqX!(+HD$3lxu1Wy;eF;Zu3j<FE-Kq*H4Eqbp zN`lOc6){FNcnL=2`f04^UIb;f0SV8aPN^(K%vp#Mk&w6M{@HYNZaMcr0l!qgs)N%> zh~`i6+)JJ22%VbV2VKMUu6(WMO)LGo^_Rs?qw7n>&))uzwipfG6YA-sxxF#hzU`+e zu1w2%vwPsdujj<F!<NKB*??MfFsJ#NaQGlxT5IYm3AU(?Rk4c#fQ$X^Y!Xiuu)|bT z=c~ab(zfpEOlGavBr(MhY#~pek`-cBLefPJd`NL-nkn6m8@{vFIvdlALi<a`nBT#U zOBz8|M>IjBYepUvbxjQ9_;Ylm)!l8+edg>~!f}<wYiTFK*Yko?BxmiBRDLnK3~PQ+ zD3gzhd7Ie3lv7s|???xmrHM0KziVK2v)HTd;$Gy>#GmYGg|(Y)a9Q%a^$U3pgzj(- zOqQq;NNO}LeWX%V<CLyr_?{!lSj~$!Ng_fJWwN;C*_mbelPLa?*YXUfbQF3o{j4=K zj(M=Rq^dP3ReIX@g3U&4)bFSa?YBS2*T-{ipY}JYR}6=pHIHRdS3B<<>(;Q0+^0oT z*sFVr0UUZ#Cn|<wrk_hvT#aM*U%n4YyO}mq>>t?UBQhFTXUg(D<uzWR(BSj`HtXJ} z><#&&I<^VUm<A3Z<%x1bQMKN2=GsZ9`n+;_NH`dRT;`tB-@ZizN58yGj_a7V48~~~ z7+g`H64)4b2u6gD=D8AxoimRe$T3tJWdnW<tpuc|%{y{-()X-|SC?g>Mt*FoNIj^; zsdqsiF&bAcSuEcJFYj;4%~VqGt|hj>v~q{^eA6Fhbp=XA)*2DXo7m4PD^`bD32yKB zPLyx+Zdo`f?IjqJz8-!X&;h_#LWUb43(h~lbsU5A1n2mDQ#`5aw`<!~-pWGP|J(`O z__bcWx4H$>^W4eJd#n?n^&VrXVa;zavB@eg5f1|<f<0=V%wYsabd_bJOyl5KT7;zB z>7jCvu!ZDKpsC|fc|9X8Axdq<wEOCIzM+UtSxj@pn2dJ@L@^o&E%u}pcVz%Wvx6P% zpA?PYpr*|$?G+VTt>obfHM_5>d)+3{Ze5`Ts}kpvsfeH{mj5nUWQP>~SA&{Hp!M14 z*TeO>2Ybz$PG}~dCt10u_U?%`wtoCbemPAFzD0Maw|&B>^A=VcE5h_ps%xnW`ZvVB zARFKt@|XUVe*Gj#W$l>CO`{j*#_Su2541f>NU7Iav^rKm=!fg)wFGJtzP|vZh^2oq zoF>HK+Fi5t0WVVf%fQBa{Di3{&cE91hB}7L`*hrslxH{ghAD%yj+d@@&(3a|M>uao zuQ&c|*h{rn{%FM2LtDeKlo)r3coPO-OJDYGtKr^lUqJmMcrsQ^nJ+u2+S9G%fcM!7 zGvmnjpF;7yN$Z;tNjkFi+GO?x>cbrM8oqCmV9=MwN%Rd{scyVaI^%cqcW(&w*9HXR zn$EW!87PrR{bJIrxkQ^0bL0IUE_E0Zq3fGL&^L5g8(-{-7tE8hL4^Q?qn{N62%m#K z_42oG1@?miEXteW{O6sP(hZh+3%j*8a8s_$ac$8eE-RSFq0YJ7*lr%H{QW{`pK!x2 zBzU47g<0jWBrN(UM~oT=ep*T-@4`Mh+!ix=+_^UZ7DBm6c%s0FTT2S|qIo-|PUbq? z#|^s=Oqs`EtH$cpRLgEeyOh0oI&D-`ABp`o42n(uQ}jJfa}(;41nEGS%c$oG1!F8@ z!uk+DJZ7(WtJ}5YTwB^|FEKp3*DcYXVtPSX4YB<BK~a?}zlfuFx|RE7jEGb|x4jm( zn&>jVzC;{^;#<5azlSbz7pA%XBHj~^=sy49w-**9I?hfT$B2M*rvN_gSQ4Cil9WW| zr~arIi}-&YM4cX9fZs{m&E$-1-m7;5d;xiUi0Q6!TR!8eRK7`5y9@$O2=d(6xwPRJ zK5vcSIW+DsN}d3fnK>N=P_RzA-qAGp2M{pkadr)Dfy?-4YOFJD1GWil*Gcv%h^p?n z5iDDMZeW6bB~zB2;$0o=p72x-nkf}~|I$`g_c<(7$o22$wsKB3hmYXx4BtwAE|Z2` zhCa*>ZFLTZuQ%LoG^M{|HV~~Pl6XkgpU$kpwE%|?RL*h(cXWiWq(5ahVW;%RzxGq} zzWIBJ{VBU1#^>=^Zk_RtBjgMh;T@>7F`SsORTMnlJk+&S=>Oh9>|9FzH(c#M30^FG zasVfqGt7Ee?6{HCT{zs_@2=|O|Aa)b*umP6aSO3FE9Kf~W)WdFMxl_kkw0y{^P-61 zMRXh`ylsI1;fm003IZ;9dZ{RB&fgq?hFWWg9M+y&w@0uLfcDENqfBWEpMb$(5S!UT z=XmOohmn&b<_IX!s=O)8dhRf4aPRY}i|}5>H}-al24m`hH!hs9rP}Er0y#t$vW$UK zxpvLj?{EE}qhvp)_hoajgBuL<_O_%)Gc;{R!%&H!4WAcEvFEYoCPe6j>)6%gszSjb zoT6CG&B%DG*}I!=um?PS4$DA?PIMHJiP44|$T?<Ok;<PAG9Za|yuOx`>+Le$s(x{f z9O7oL7n6~l(Qs?5{+24-X(4<E^qEosPjH^#6CvI6OT0|?V4eW4cgZU>yA5T7<=|mV zkJ9BhZVoYE&CA{3wTd;5??SqI5>RwmuD`U{{$orCjo?<vA;WFIVrG;Ep&>o)j3m`l zAWbIn<cJUK+`skseXy4jI{4iNOC{e&($x6porjV$L#=C@j!o%Tba{qU^K%I8xQk|6 zkf+aWyzrfeTE&xD;xe8g0yo0FgcA5jm#F~EK2-0Z>4tFs>d&71ngs%8y)uTZL$|W& z-}BOXe|d_ULdnn=I=x!!82Qk&a{+<wS0);~Pc+^I0K5MP$F50A!}^}Yg@H9=#LFft zyaw4~0f=tIe*qTj>a>6r0+G3mz$lp(uk!)0Htdd}vdfKn9F(&Oez%3sajKqsOr&ix zPsojXsuxUruBgWoSnw4jbYc8!7|+B50(HvcUN`d&_I92uM?l6izA=wkOgCQ}jd$AW ziB4LhC@#zx!FGQApv2*i&%b7+F>e>}5ot?<|4rxkPqBf?E2QDzcjoVGqqMR91rVa= zej5Uf)iVZ>8+L21Cg$A_fpRWwA6Uj@ho5B;bRRu<4p&<K!O*h*UlY~p!#)p3cnR7& zkk|5vpn75S^8mu*Q>87pR!IbCKTSF!Ch7OSV|^+i3_ugYa5BSw?&Y@klU9%B8$j0z z^9K3*8Gm|=MZC+o!Mm{<?F2<(O!ITR$}$CNIZB>854NA;6r?3%0#WkwhOjnDaT^|` zvY8QR(@+fWL^xTf%43dE{-#7bSt4b0C5D&qH^CqbTfo?z1r3-q*Kt~O`7SWi;b(nP zep^J9y`4228A19#a`e~KlK--Y!(N1+`@`YkEzW9_eDJCsI`m%MTC~4aU%IgQOti3T ziq9cPcj60^S=hHzGrlz#g~3VTQ3v<NL?|p`sHpo^Jd{Kvz<FcdeCrJ#QyD<qWMKNP zN+H+yCdaRTlS~Aqy0To{)RUsaWwG+_-G1GqSWf~|wD~BTj&?;$@+ZSm3z2I>@x|?a zKA?(wBMNV@;V(BRW3}hknoD$&N>L~xLah=9zup321|ttFIEZQh&Az!K-2a$Zk1UAK z9|GPLIg{;V>8PyU&s^F3z_kxzTu80vJ%_fUkvV6##a?v7s0kDYVz=Kw(<9s9&&+=b zzU<qMs==$o?UY;cg-U01Tf#TNDhvAX*no@Pse2Em)3;}cFdOfd#}A@rb_8bda~rEm zKmNoBpKo)x<2hE{4A*l9<KTvUdW5Nt!S4RNQA4=7O3Q_)ld-bCzUwVE`5F9AjlkRE zdyoYW+(AdgRDX>zf0aL?ofeJLI5W$4boSRWSUZR4T=kgv%~owWOa9})vHu&)iM=jR zwIDmV-Qr?$iutWS=XPtK`NdM?+<zk9kP!JXMt#C$wuB_F*+vMqEvx7_>vf2&%!D7T zdT_)N7?T0OSWHa{k5Ym06N|A7_n*h0vuzQWV!lgLOT4t7?Yh+>K<yHX51SKm4v}Op zfuQ8&3Tb$4m^0=FjPz@Zfsa52Kf~|o5g!}yv?I~L@!MOqLH)B8X@d;I%0%9(#dS-` zzaxbj^<J2dI1cjikT#*cayIEpo0n_3lM#tit}{q198$!c*k2lRt^R(d`1-^tD~U)6 zM#Qy8WX{x<Y<jkFZltZH5d(E*r#S}1(l|Ze=k*#J-S&}QlF?R~rl&8RFFY!`WZ(bM zZb~YdZ^zbYn-2VX?hVfbmkx>V<wS?Yi=+f~O4H=Xqs17&5puA0JtgrIp0?J~7MS7w zS`{8Z=%*?QoF~$rv{Y8N;~+hLE}3hOR4#d=v>iVicGmsR$%%K$jzCrQXt6tH0ESNr zTo~DRzpx$FME#oDi{2-zuQOUg){wIw|Jg3#Eh1dV7X@P<KONdKWoKxRk&9wDBN5tp zKcz?vJT;$gA6Harn|U<}$}mL|rWf1Rj*CUZUi<apa(nUesNZ>VTY1SRGYP_TQfpK3 zSN}wrt;!wf^HVs?{58M37>Z4bSLLgkH~i~5*+t!mg+eZwOh;l<ph`w)Pc1TEK8aP- zU}Zwm_+V<Kd1^C89|-(5pJAo1aBw@kP1HX#f9M(N1*=?dwk5oj_PTBrOBrLDF72`_ zJ#f@su?a<__=BuR1#)vjHPg4|`Lq$oa?0-RR)pyRXqpd<tOXd0!V%>z+VYQ(%6$u; zOUF-{zK5Dg9EgnmVR2^`p@&iR(Hem;gLc+eQ0x+0goN=_T$mO=WO=N%%{rPv|9JRu z%S4undPlcLbT2;u9VfxFI^9$?KWx>D=D`dx$T&C;j4j+$6PM&0@(~<z&s9U$nte&7 zf}K*uSGMi8c2{^iF9^*~srulPL8zQVYF-CgM_XH9%~s90tAL%#iPpyirkx^{+L>#y z6b)?G#F=T>t?8xa06~tt=f;1}8F~*+jrAyV2>L;v8?*SjNe(c6>D6R4{o^`3dk{fs zLR)0P=+A<$Xw=Q}pXJUeeSbAcIK8HYXGcLV#n2JG<+)F>B1(iWDXou~xX)k&QL{sU z3m?#*t)#hyua|LB4+EGG@x|#drPI?`sLo93@g4TetzNKO)*JQtb_FbwW`%1|L9gqN z#Bx>2yk5>;NRA!#)w6%?wv<$Vcg}l4KK~XPVwdf>{?%^ZV-vB>Hjj@LUvQ_%-hoU@ zC^!5m{^YAkC1O_tKd&J*pnxh2V1jgO_#ub5$mp+Tjh8drh?w(<8Ozn_X|6Z^RIO;x z=bz;u@gugLxu%?UE+S%C@V5pfxjYR#-9S90{+uv9-XxSq>2eZ2;TqNur}>9?D5&1p z78DVb+z(PKEb=z3ZjUY5-y{akf9N2lYEnjggbK&ynar9`gg^X&`Qg4^;<RKvXuKBv zk;ip{*#}y_Sik)-!pUeM^V{C(mvB*eb+ir7g_ghtKRxy9VD!3QeDUOeMC0aRc%50Y z5vV(0hW&BP9-T4L#JrUpO{O=Hj;oy-Yl4rE;d-`z#UK934~||53Q9$$Ox0gtZT#v^ z1FB$$_aq+~e)I#|s+BELw&dl1Q#2+Z77v=>u>&;G%KlatXIChsP<ca5e`tqpoA-`g zRYAy&;DWdC%?jLmYBXWO39EG7C)0^l*3IB(&du?@Yhr%R&)RtU>vH{foIX$@&qY;X z+5Hd!ow7IqBJs_}&7GF}SwEjSv=UYJZ&u@hvi&xOGioh`kF>$a7Fcdd&!ygKah3e# zb(K3q20$%RcC9yjLt8hnqKdIUqWrnn(nVAL8Egan^K&#1SjXAao{;g95*{cV;hzE( zuf8zMu#RUwh+Wag!PV3-k=X`&9WbpTtn_n8)(UYL%7}Cp$GYj4+n=;m7M<cG5dBjW z=Zhd^Cw@yo-}uqLXNLdEZ|sDec#+p9&eb03t(Bc{2d$csw;SH$2>v}yxC~zj#kmo! zQF<`=|Cl<<u&CNLT&pN0p>!jNbf>_;sH8}Ubc4juA>ArSO4pD>gLHSNz`)SmHFS-D z)UcQDckE;DpW+|ZV#TxW=eo}G#;7&|YkS>ggZAgJ&G03+_qaw|SU6aPm;OYe52fZ5 zge0KLx=D4Qo!)qVY;J+Rwr^SvdwxwM#cwMNAduhxZ<UVcF2pr5oLt?%EXwZ3%(V88 z5|WLfE_&PeB+4zhM6Wv~RZJ{M<KksSj33l?segPGXa7bM2%3Sv+S`kiKOWg^yi~B^ zN__1<E%s!xjv(J%fN+5Doo-wG?AgG>E<t0QYHU>F6{iHh;ws&Xo%PjDtQYleAjC5j zK(X<IA~9xBB3B5vZgrNHcA&_FU1M^_C)SFscAiV|9kR-8`O&oV87Mem2v4&!;SmbC zzM8YJCfxj6W#}XWEdD95zX24mLHC7!X};8vBmnHrx0PZ#D3olx5OPnm0n4S(5DSvo z5k`kN{!%5U;fo6L2+DI03azMTarDPUi*xc3q^s24zdPNp@@b0``Lkk@nn|;LbQ$f1 zarq;`Dnw|TB^X>UoFQ>NE|U1^jot3$SC;dZRYZ!gk#s2YN7s62XD!(o{q)K^Q8zQP z>XJ4XwnOf6nkNsof0+^%6hBG3he$HO^pTp8<2`llu3y_JAhvjxITwHjlbk%Hjjl{K zljV2;Y$APxE9*M8uoTzsT&TprdM%cJ8_N^O*WE|xW|k)VS>faD`sX}e@_ruVPe?RC zAus<yC7aKMV5%xEx$)V{bw)K+kz`&LfgJm6O;=6&Ol+QN)v1Zm$*u!w{r=obHiOHP z23~p92Sbd}>D)6)e?0r=8`<hxZU&qknvM?Px++&!O;K4?tL2o@X|JZ?p3Ub89YAYK z>=dL7`mh_V3?iqzr=CjA_U-;7JSGNwVa~5h`z^gMf4UWt6KAESl*+*u<%_NAax?_o zKvTaLT$=j%Ke-G}&G61{o*_R(c;2eVX*zhNL|%CWP06BLlWiAOh}-3BZTOQp{59cV zV%9MtVuWuGDzq0y_&MtAx!T1|Y1O_K5l{?Cf`Y)dU4L+PiMv$=(Th+%{-s50f!_#y zT*>%vl%P`fnn`t)#y$a|-Kv=!h9h&#eYuDI&pm`q)lykm!oga6?z6*8r(Y9bLqG2$ z*#DT(S~QBoWsZU)-Y$+A=3<ypu!zbfPjV0=r2I~SC;*pKokLat7jnQ8<h$V{t50+5 z`Qpm++pa`+$;(LLt6x$}%iTZuzM6OlD1lS^gT{{vm5rm(aH)4*zik0cOWc1WWdL%# z{qggVO%P$Eo8R#DunqoUm>tiT{}9XsAGc0`+5`7dA5akjYv@gB|5aIg_ytE&7q%MH z+=Rm$_+-o+=c7GKh7t%9Y)pe)vgtV`%-Y%$D9WVEnV9k%={y>Xt+6HQBj&iF)TQ|1 z3<=kpZ8Kr+td-opT2z(EsD$YH5xT7I7hZhoamKAh_6WqV9M<v{eq@(QWY)22?FlPM zC(Y*<ZdKF%%9-D4QK^Y*{$-J5y0VW1LhEB&;W>4wNoI+mqp5EmL)@F~O7u;<c?O%j zx^4;cNrY6vBcD3mCo8xjk_(9C23*oMXiBK#@ECOKkp1(h1;YJ{#VeWSrQugipS(F1 z^T#3wD+e=7%-_qso{!tPDoOQwAk&w1v3+>9Kb*Y$pk}T|KO<p2LYq|6&8W~n<(<C` zo{d-XAx^(S>GSY5$S=LS{)mi84h#wVNA$f}K@X<3j-a)7sAr~RN9wEZf~>XwmS}&4 zN%N%_){PO0LmwbFh)tQ)dsIDjZw-g$8<~33?0ZpUdU%v3ZD5L*bl!~Yz3Ku_EUTmK z>qdPDJ{40hS&*bEL=N&^GgH#jMv6h(yz<Us>WX|P2N4S|*7e{b4-t8NW$woeiQk(R zAv*jvQ#n}N+gjyeY6}w}s|W!r*SyQ+)nzHp_ZBX?*CU@uZ1xrwQF|DQoSm*TLZII4 z>w<9vtYT#Hi5*u>l~=oHbw>N))gfpVMXf#GU(jXyAj0`FV&LeQg6xUE(zjR%scLTL z1#3)|eSO9`6IyCYY~A$tzCXPQE3qNWdWrBKR^$#KV)!K%>DNh-pQv#;xuQ$v{QxJH zWM%5T-sqP~sbYd?X-3a+v58KfoRim=wIUBznwnSWih7e99eIshw~9i(EEz*jcH=n$ zJjb^YISqTa(GDtr>Z;W)PbeX5if<-YbsGv3RwYC_TM#ouZ7<i;M!J6&2iLJz6!?oj z89P;kyz_ggYe_u|>*XHM)ASQQ%^r+NJiaz<+_$Um0>R}&yWhXV=T1|)44*w|eb9%l zN*H9f=Xgu^q;(H&R<&eMhKJ~@JhDP5$<dn4G1YHne4(C*A5JWPIB(Pe^86gntEFdB zBgQw?VzmVkK;2eOJI52Cg2dskO+`ywNhbd8YeMCA8QdDh_$Oq0oauebiRv2@;eFJW zm&1zNt&~PlfqxQnc35VdUOJDbj0}&Bs5q!0P$ev7K^bUgL6zM5H7ljR)jMxA|7ZI8 zA1>X8hc{?rd&{Wj+STDJHnA1(RTi_;p#}udI&4Ct9)ePto|*D}ePckEK>e_4@7wb< z83j_ut+z-0tFJeE)cRjPvxIx)LXDs=tP+@fh@*<l3<}RkHjP=Gh&A1we`_^S-qN`? zx4A3xkS~K5e~(<jplzU{WK{%hEuK#DTWLhVwYb?86Rq{EXccXRDLE9zT}55IrwRlf z``G9eGySmsOj<w&p`s=y?!7whB<Zvd&o(Ph?4RkM@`(0`o^qo3Le<6Xfl(i&BTl%b z-9CBNu+3_v@Vr$2qKb7mt$aNxkCAhF&vU-DiDfLuB#5Vfs3dJ<gSW$Fyom52>pNog zdVR75(GmrbLYc<#xtL$p$)pLH*k026;G$xAQu6^FiDgola(0aP_Pez5&x@bMNoPk7 zqXimpDPauC>ccz1TS{NU`tIxOK56toB?^*@I28HzJ?CpM?Wkx9q{ERf+@S&R*LLz6 zf-d5(&xf5&I1p|K9*659_p*s|wU|I%?O+3L7B26VT;7K*R=aJJtb>V(4!TMMb;=wO z^Mx6Dx<7V2gqB>jS#lp5QmS<)ERt#<#MIK(1#7Bw`_rsGA9&NA_p$m0QIiL2=-^W4 z0BZ|cw-w9H3owm-o820miS%|p`x#`f!Phre#%f}Gy5R)hv|y?$T~l<z>ToGSUt@mq zXZ4ci^x}4!01%H3LdsAV=({PAAr%95GG7mSF*^-zDOxJ)KDR7OG16@;!sA=8nyPK{ z)`Oc(9Ti_Is=Z5O01w}tnHFPDX~z}2fcmA5wH{C(-h^;_JG;->G%gq*8ym$Dq&XAE z6yr}yRI)F&dWX|YS9qvWo9$?dR<+8gj-)w~Gp0LSCI_d9--+_8#d+10k6$jjY*dTQ z@baChr8aR<2`J)UcFR(V86MOXzJZU8v%gE2Homa2zt(6vttWO<$r8M()GMW{obyz^ zoOCALh?>`wm_;k#v5&vAkYbvL{SPXgX*(lqQ^!{Yv>}YY5d4UIGc*UDE%<+nKlbS; z!W5Az8551=*Q1Uu%!#6@>*q3##ziDH3s@((3*v*wwF`%If{GNA)-Y~BEx<+E=YbY( z^L5nGhe?x!;)W<t1|95R<EhP@9DN!qoB_;wYEKPWq2I3LlJ%tk?sxhB-j(r(UNqu* zJFmOq=WsVZ?$b22ESkQtV-vX?|8MAl&IN`ZNtb;6C~oVkMQ&nGjU+8j!fH+tSrp@% z;?QL+Yf25J+sjo{X^V^`xd0U7qk$unH|22=u!{ASpC@T#Fnn#lihnBPA^a@#!a$=F zG7~dhJ^Ua|6%;@o`TEu(MB1}dQ?WhAlQU{V=~;|r`~M^sfT7Kw!<^jl;!b+a@bRHO zD^M;5j*=Z<g$HL&Kb9Q&&PY(((|GDN<h(RA3x=^e+&}p!)~1lSHh89#cH=7fvGpR4 z5<!&bjL%LKiW?ht`mOp$-^24b4|RgA4@OMvmPOr=-R)-D?ecC_$ApIe{UYP9cM2ns z#Jkzq7&^f6{JkiZ(d}x5r-OOR32K<<?y`xrc|I!L=x_Y~*$=SX7qk6bQREQJ*}a?r zE%LA5RYZg4RQNc>ThlP_QzssP2u`>2b(15JGUsh+PgBt`7-n%O3ZDuClqv=4k3Wnt zymp`;DcG@ob(@C~!&<A*z1C;EKew$bS)j+0*Z5C5qFSaPB&K}(+8!>T)pnxN54k^V zV6UDif=|GPX)4ew;ef-UrW@ZA0izu<kK({Dcfb#Sb#rrg5~}qN)-SdSq;%3s9G->& zza5(8&bJTKPq=cVo_s&>*2ly#;nJs@?|59HOaXfACtTh3ZR?J%80FOAo2Os7b<^7J z6Nlc@Z*6huDsSJKiFPknKq`4Bp#EHWc_wOhYCT82?VBHqcoz^j7rg0{Q_*&V@`-Gr z=lJ8NSFu_sxY2ur7#qxE_11+~v6NN$9L(MfOFLv79={cN(c(cs9(wk6ARh=ijtm1R zMDcl_+X&}AyX*Gm<-aRRHed(O-aojlM~5x9m&(Ngh$ZNp=?4o0QlQyx5aeuU(NB6` z*X-=;cLMQWp|rO@I5v1$r-%RFJL7>y>=i0c!LG;EE*wxH0cY_hl$~vgYGvD00xY!p z>N3yAr~1_*=k8wSBzxMp`0<#^NOetYVVC;I56$frO=}Du1?j?!Pp$E~ffz8U%R55K zw9urbe+GrHNsje1cgz*&(95a5;BKEhx?Uq2UBJ(v`HNJc_4E1F?tdrd$)KdtulHj( zEyUYxci*2)cVLZhw)HsGz|_i{6bv#aiD>e7>8fz3kH24CPpLLsdd}@3bY#T2!>X&S z71E_TA*bdMEglnm`)(JppXxU(%e3Qp<xbv*CzXJ}!#@(vUVs5O{X5SGFjORXhDOY^ z!`VN*ffbeeD!G8`-u>@%yRx_SOftgUZ6R%LKM(F#Zb9E_G;+}Ps(NA`9{Ita$8{SD zfZYyDcyML62Fsqk)ffBU;Jpy=9rUxGlSUoMz2Z{%XZ}%9C&j*Hr}vKdC_wYO{V9$p zv%_EQr+H=Sd$M^)Jwm5Rt4F3!LE#)_lP|u`^5-3Gp|e}{()MuXq<@(xwB}7#^CtT) zU8>UOp+D`t&6_V^JRj^>Q0gcKeUkD?Xepc2{i|(wQrP#ptLg2p&}gK=Yi>yfhw-BP zNy<MRc+PkminSnl4oQvdjG43D4oh3nbY7d)w6TzN$=oJe13Qg9PoE9-)5kjlZc|@` z(fmK%W2$l4y~~H98x4QqD29r&&9k+*?r7NMVSYL(g(tR|5UEce9<UrSr)Lx2h$$Fk zPqOm5YG$ki!(d03kHY1d6q;i3VW<&w<H@g=QBd?&=m!B6z4W==M)=6S074%&=ep63 zlz`2l^5Dzm78eVNzJENqs{21A8wguuRPk4@2|1&HN0izB4YUBh7gA}BKx)CDZ_<Ua z=VS$v1bs)9xup5Io_Z@d6VX2)mC#ecZJ}|ZTiy6tJv9{y@v-Y80RNlI=<%QspE<(# z(GSaV_Syb<Nq=@Idc(k}z&oW1=QK&sYAVNxx}p7E`?(4>K9Mj(cqa_iiJlwj+oi}o zBnCEeG#jWBsN^PkKDPP*9SJ<uUn=GDk4H%dxiaoDz{r5R>X&zWo!1^$&R47=--D)= zie9Pn7WYZ^{6<L~ltC=G?oWj?^IG*L&ldHqwN1{Hv0nI(OrfvnP7Vy9yGK$*zb9Kk z%>E--H^>)2+Jwr}kP&!956ZowmW14;%iW3|E-pm+Zo}fVEZpX!JuedB+z5!9uOups zoFB1}GIzHHrz<zR@DaNCeVwxaoWMG>j5guwrR@6)kG(tgrT+ge$!uR4;5GC_6?r=D zGVK(DEI?1|rCtBl^_N(~R8xX4Tq{Gb6!2ZemkyDk5TOfE{J*vQL*rZ-yl&YlpR3si zZ8SREPU+gVDJuuL!&XKZ6o$Wvi0#>4Bg`{qy*yIBaGhkawdb2KT@i8f>*{Ewmrtg) z2rY6{R`skRu2%1X(<#{l8~V<fQINIYi<b-(G5`lDq_eh&g$!YqXF(h_L*F3w;IFgf zUw^lFKol!67-9U7etROrf!gE*6n$0j<bL_rr2CuQ4JDA3A}8^jO6A7D3q`{l8p#J& z&ShvAz1kjrUfF=1Lvbb>HgGoY5y0_gKPofpMq;D&%aaIil*DiHUw``Lxct|Y3{qzl zH|M0bos58FoOdm69FSK>aq9^*e=)m@IbRvk<5w|)&AFLx^M&*C=$=YlH`e3++fmE* zeFw~waKCb6eBSVt;mZUf^U)h#d1V_>WN(<{%yn=KEtlQ?;H&k~G6!f`VzIeGaX!*r z&lvrR8QZWLDvm!ao${5^{2?K6`p3CHE@716=r-PBOpMh6np+6kf8pS#t82CUZ%oGR z5{#4m#aLv;1K`k1-=@@dh${Vh*dm?W$#JXGNl=hH@)ef0`M!x{Xx2G?kIJIbC@tIE zH8(2ZI%ww5reQ{?JK-9i|F&=dr4NS(IcBxpe(9M1)b&$sk0FmNAc?1H8and~fzpI( z^f<GbR5e+;=gC5uwokJ6mDeXBvSX}`;{~55Pjt+Ffdlr%tk2ZZspsw@xP=jAA1cJC zjbHK2+L0Bu=S?jPYHLEnaW)#LSU*4wae`H$k72SIu22S&O)AY4H*Z=goiq>bEK{bj z^S4x`0$Bd-u1jF^DQ)UJ`z)uZO+{5V`l_nam{0du+pf0rwN>+%DtU&F#TOqf>OItJ z`~EA3$ODkkNSYAmW`{a*ww`*<^Tme=xCNzLQ+~tx>CT1r2{{doF^Q}O#q6k%UAWZG zJPSLprK5Yx1Q`_*>ry4TkOx=S137lQitONoX@KqB3sr6&`}T5KiFL5flw8{vpCiL& z>6C_a7O$K_oIodOrEl~mP1T1`bxGRY6>2E3VcPktyDVc?mrY3aS0qKw1z#TZaLLhT z0iMr|k9!7>fJK~)hd;P@-a%szBd_g2uBHDA)4~g{&cUr7fk>?})1D1rkLuR9^i<*t z-<+E|bo$tI>*|ZFxpt2()XFC$6q4%{X@Ww&`w29(c6nP%w<(5dM&}<}u3MGc9}Q7= z)CvyKc5Ok%PrcM|?s(I<dzBgqHYV-MO<b%T=7={D!%9R^W7I|kA{HOZh?OV~`I=)w zTZpdiBM-+=@MMBTr|Hohv98cGN(CWIBqFac(7BNzQixDqi<gxV)53;dbb4_GOX{BS zZ?yvjz~E3sfKvSy!bx057Ge_9ky595K5+>!;u79G-doB3IAn#%_d-bxuhyx4ZopnH z7}t}!$d;k8=eMss!wt8We}A?(6^EP#eb@(yY@2CWj12wOKH;@1;f?%!0_m3vR=ZeM zT|Hq~)a=t{;4#l671%0z-)v+$=$exN>k4!NHrN!OY7uWMxKqekHJ&1+8q9&9v%$dX zS)W?4s3QrY?2I5qo<tAF7_tDX#DLiWxAx565SU;IdUs}J<IQNPgRUby)_=Zi0Ay~u zy_+havJ&g;;z+O4o>9k!+Qd(00shBLXFCfefbcSF{;xYb&l2Aa(=!f?`!y+!<0HYl zPkF8<spl-Bexk9yxPxXi(II1VcSOJZ2zSH#5_EP#`P|~^5b81nDU`QexjJ6d8*oaq zKk-hd({Poqp%O<RC83w=!Q;{i6P@rE7P`UFt>z`HuAp*b?uEJRaC02tm?%S0Ps9H4 zX7d(TQY9fB8-!bu4abKrW@g2wMK-@aEhs{@bW}4)dn37Jb<;ba^5_A>u4-R3VvF2Q zVD@ut`-fz)qgb3BMxRT^LadYV$*or-Tlm96bo6Ig9TNwuHNBwOzEU?CM?uLtA6kz2 z)FmTHb>0`POC+A8H@1MyRt2WVf-7SOi|SJu!ai``OqINvBJAT=3T_M#c#6kSF*P+i zVMx>PLf8Dom#8!D3)~7MB>spF^LGJBg~St1CAvPgbDD!YgT-0<{8+u@*_7CCKaSjt z1~UsunH60VBLo%?+al15i-Bx%D}EuMeO{Y}O%5vcVnNeGi#X)vZxpI#Y>k0~J!nws z*5b^;lwUI`A~)bGDRLA8Cit?F<o1L?;m-e0V5I$vxZ1Ym?#EMoP!-736;EJG#|d)9 zDrF6?=F@@nj+Zty;6lrjJg(n!<hqzL(!OoXxhgT#B)p>fb63HVA^YsN=X3!^HClV% zQ)?ZL0Mr(YS+*D`vqCWM63>9D0}>-eF2Aj&k=e@|-u_wwSc#8p;1=&*Ptro(XC85i z4VVayz7cCoM^34KNjI+53j5_PV9HQDfDZ58BMjN&`g{a=m!V*{BX%3+<*`V-@E{K@ zcX5=*T>q%X--6E3q5u<4r=sV%EE{*ujOc}0lf}Y}W?QeL1`w&Ev4G`d@)Wc|uF^Au zdBb{MpKRcou>#3#RVbJ;6j$Jjh{`7S{oJ=|6J2Z?uq9WF*V`WFUC4do<+aN~=Fi=G zw<Tu1@ZN^n+<lz=Jv2s<{C-V2%T%vxbV4kY!f;D#$xua4l<hHfS`UT(kaL$i-n}^G z_VGmcNM?>E=896jg$w&J5%T;fiM)nr6A?Mj8>dnrw^gJZziyRM^(>XAer)GjGduJ% zRihoL$Njqxdi)E{L(PBgsgu23;VFofzO<HZ&`%`>Xg93YMEJQyK`#tpa=>XkpC(0k z6`yR4XQ^ADLF7QFh4BTPpS=8;Y%sG<2wc*8;@<_LJX+1Nd3n=yt^^W;<GDkX0<E3_ zpt&>@#`T&5+*P=kW@KY=0knLp40gHRdnaq@xNsZ>iddA=Yq6{C)!sH7uB@h0_RAwU z&cfPjMu|`QP*0GhKMJfQj_89$W&66$wVQ40uQ~0ge}69c^Wu8Z<L6wbf4R^|$+-MF zw@RZu15P^qFpNBQpg%(6UL2HFdp>ER>w+#pIg3WEi|>LRCj9MD;RQl!iwH&j_lvt^ zp%))s0m@4WdJ`(z)0Nf!N)fn(>s5O&&j83?!y*;QuL7)Sg$JG1ukUHAw})S9mPvlu zLiLxScXuEHga%O0$=mjckw%&Syl<pFuVCQ&KE`YAhQYOxqnXn*@MxeF{*E_H!%idv z!DD97h}ri!*fUCFPpHI5x8jX>ca>3Tud|hwW#~mFw3GPe4isSnAQh8N<Gsm~$4=9F z-esnok9t4)xi3K$yX0{}C!e8pBN`(AQAlEoN{WEqSffnn@wyYC8GN7`b34lrS{mvZ znm%ngo}wsY6%qLDz+#FwzQ{5PAHMJ+=BaiU99e|DsU0lrOU6%ji=mj%`IB(edg%4h zH*-+{;O^8N(Vq2Wp(4;T{>j<9NAdhWo46h>e_ODeyPaE`rGE>;^!hR-#D@l@;<msx zw<|+ZaVAr`Rc1bE$*G<kme3%A-=3RLwuMnmQ+2#(B|Iry*q3%QvDTedng<Wu%?iz# zSnHS+IafV>DHBZjK0vwBHg%y>+c0<81^SdSY6T#=$*1fpVX6}*CbkZs6gZP&^Qw#^ z27<t_$G7^we{)HNFFs8jZx-09X!DM4wB%ble*3hDLj-6iRJlLv*c1&)*hbKQ3=^Ln zW$VxMh_-|TZz5R6sbN_8yJ9qN65DG3R=a5|{j6b*Cg$-!8VJ04(aa*2G5u#iOf!|h zBCSnsD^2dcG31?HX25^+Wu;)z;oLm@I{K_`5|%TTtH_0c42u-3mF7pW)9KbeA>3=5 zS2Py{UwoDHig}r;*{UxsETCig{lZwXqS%!!zq&{IwC9t+_d}DFi2x7U$4{OIP&_s2 zi~q<fK>0jk*$3e6+Ur6+vmP&({P1@4kOg9`d?9Hb1O-iX#0V?D(?5KkevzR1f{BX) zxza2KYsaYw!7cWtew@Xu{E1;%tf8oBK9`o^+v1_+aM62?aIgrLjl))7!GsthSE!HJ zf<tQCg?NE&T2fwg!Vps7eO^ZI?>Bq!a;LRGWVhJhz5PQiA*6-VqlH>pMfRl8{3wAR zvaGLeuk>FZ=70#;?D?J+ZlX%-;b9NHeP}kC_^puwhP|g1Lse%qcu_5Tzs7LHSop++ zGm)N*dJ1d`fBro8CQl|XbQJ;a_$D`w<oTRWWpaw_yLEr6dY+RwVll2Q`*g2H`Bm^l zWA|Q7WKOd%AQEGDUNYtDeymE_=PJNRV|pDm3@fH0U;OZUs&w&2SKBBYd!$JS$fI)5 zzr&kvo>2^{D3cn7f!CSG!^>vVBWu1{89_?ojGz!D=%)<noKxgDNfss2;qj{Xl`{t2 zH{p|gI~OK{i;F)TONLfVSwndX*@UPmHIk1a!NBDbheS1AfWFjbq<-m%hmxfO$X!(P zzNbfX2v%L>A9x<<TfA%kf84$@&^AKYIg(nEe4lr(kj2lEpQm~&7T&F8Mpr9_+7XiM zSG7S~H@R4!H}<QiPxR0X?{PI0&2^PikBpQ!4dDG7y~wMdB>3D@gHJs~J5Cm+K|k6E zc_$&<#(B3Ob!nLBchY@vD3_I}Ngov;xcO~uPft=SnkImugN9cdZsT{s$~$jOpC{S) z=`CY?@rK_16a?2Y);k32Z(zmL>)$ChdO-!WszCbi*lID`+?K1C@q@`V<M3oj5@$&p z?b4W8gl%8X(K9lVEp2Jr{Bg{RPtZ5SgtaC4`zY&84#&F0Zv%>=V%=(-A-Vy$kjiZd zIIh6rS$o!<1$;Y}`^B_wMa*y};ewXbOEMw)3dXXxGIK!gW`E}t>N<Br9@)g)2ZO!X z^;17qCo>{0OvGYc9ah&OuQ(+8Vi?f7#6aRkO*zr@n5HHk>;nCgctcPcj#G`7QsmFR zkE1qS(_HPgKhosz&0K9hiJ>tBWJ5c^ct;GRgv`&<Okyn`vU*3{rI`H^^lS*Pv+wJ= zec5-OPI8Z#a$udJw?M6eEZ8Uvqnx~O(zJbkflz{)wK1I$1c4m_1$fN%ER|JK2ScD_ zvEa+VQm(p>8XPG%Qs8^Uu=dyXeV|j8EYiaRDbHfME6S%X!0RjjP36Y%M<rOb#?Guc zKe$zT17WVXA}<0Nv7lb3l>PYp&1l5rto(ii>D~1e=Cv~iimY1%FPQ_5q#e>;@x;rk ziobi3zcbG#C7kuw0pQvCPf+%CZn1w{lUjl??GH?MC{SgSU8eJI6YAwr80pP5Vp|R! z7RN4f)bmHooIj18I=nX_YmEry8;;I{ycoYOx==r}sQcieNzHdr|JOB_LM&BO0YR-h zY_&rR1Xm#AO+y|XmOc74$&&f5u{Z*An>xi+^k;UK`aT|4D6@-$vd54mNQVb)erBVs zD6OpBPTO9O4|}Uu%*yLwfAnHZsC;{Kt`R|s^o2!`pwguVo7%<TwxW37?q_x-Ahg=Z z10Kp8)of6rsB_T0y%H2I%`i`s{dcP`?3jAB2(G?8^%!F5J5^*(g+}a;37+p{@3T5M zsWBK$xXLB-=IzwvEhTIR{-S@S$U60kT2JDitb%uHsN{0Ht0?#CU71v=o*L<ghJgJl zp!Wq5DG5^K#J|$Ovgt}z_A@EtGf8QJ<p3WVa<$0<u*(gE+?VE+$9oQT=h-epD?cvU zRTspZX<k~gNk}8YfC@=RoTKT6+phJ|lc8kOLr?+0!;w1)X^vs32^hvN16Q94(5=}2 zlTzT8wE$q|?~#O(5L&Er|B8#adtqqOoQsnM$~>7XV;I!qT;p+ZIgh&0+Z06>3L|Id ztCx#C25i?5H_-rBUnyx$l<TtMi9r)*v&iL;gyqAjG6{AYbqG57uBH`cJwIY;*Td6T zyR!U7^lZ1`Z5Pe&y~cGQ=67?wUoN5yzXA9*!Yw;|ns<3RG_C#P79r-8LXWV0#0lem zM0g%{Cz6(xhdnf)PW33;I(1Fx9R-4=8TwUpOjAGl&-&<K-AUDv6AtFUL)GH&gpH#r zmhRF8r-*gS+H8FMX|zV7fxUYi(z^sSgNJ|t0IrgnGGQxGptP~}U}NdScFJTQryFij zM~WbWd*L}H#rrbCf&D$=wNF)9cB#ib<7ap_=Yor~rv8s!+=ZBr)Vef=0d>oFYhI07 zW<sl`;ty!$h!%uq5g>)%IXe;6p2&Kvyzq}RK&Z64<YCl<5k(6LSH7pM&75cuHfLkt z!|a7@+S<#9ns4%UOjA_LArbxrtxY%_MyXsd+7~|`38~l4-|^4;3VCSiJ=wo*96rPR zNXzjHfJ80AKs-NYYI)uMCh>O^q<~n;VmZG!<P4?D-yL)cpP9^d`A(`3HaXE+PCc4F zmWgnPD6f3S>F~KZ{w|(HyNQl~Dh0=X$L7tn*oBcY|Ime>BDt5=dRE7s&dl1@NnmJV z!Ftiye{C1{T%{S+ac8R-=1t-6;Cu3pscD6M7tQMrw?ETzP9ZYIw2!Yx?Zhaq>r)P_ z(w{hb^m*NENJk&*S{v@W#39)P2P>Ho&pAaxVtZltx%+kDepkPk5o)H}qJXKw2#}MI z6(}S@i$~UkYaUSnQ@sWG_P%}6ynx0^uD46*VN0>Gw2}jW!blzm%rtcGb`U5<T?n!4 z3e^`4JhTtt<st#z`1>AzTJVzPDWsHL)96sn$Uw?YniULysgHiodpXCSk5AJu!`}}$ ztEf|wlngDWB4I+H3zB@;pIjySY=jNB?!et$=Q=#i|9O5ZPTbKII&&Kl#b21Cv|C{M zxS7gyBXN7_n<3sp-bpv(=ulq8R{y{P4)0Wxy|gEdueclZ;~*BgL?g7$QhCn%V_@y# z;(59j3fb=o9osb0Qvwf_bq**trhpN~UG80$zi+d#_yH7`%DSNd>^*0lNuxp8k;~6o zTZ~=WZv?;z$&abb^NSYc5(9J>0{6OfGf}*5#}dO|OEX01RY*b!9v?mhMy1)wQyITY zBt)v01(NZ}Aj10V&XXzNK61%pi41!!ztI5C0oXqs`?|vaSLTp@Ja!GVIp7WPdvs*L z)*(3)j(_BoUw(Pt_aWd`+)?22Z+q_c=Vh__q0<pYiRXRKSr(;DAoXj3WxIwQ4UI%y zM2bgS$GW|mJUT6sbR`*@Yu|YQc~u;wtNAWRF$0X+yiz@*!BP*+VxR2z5;u+1-m<Iv z>nxLj5SKb|&CvQbzy6gW;Tw*dZu5H%5`W3adGFx-nZ5oZBsb#2b>$Ql{PhoV(Whg? z+%M<7OFV+Amy>1Nt$WA+nuyKPM60r*4;&Bb`S{a5r!kR-!?pYX35KWIja<r``reyA z^}u-id*S$wZMvn+VT>`pM|D=h=NjIKMM@48C2l?|-#!~O&sRuzB@yha@85*P87Ch9 zHbJipByS0$VQPd*FI3DvJ3^K>&B*wH<S?rt0heue=IbEWQ>ng%qKneghm=RgTUYcg zAv<pV32l>0e}4cOOe$In?pM0~eLW%3w~g2l`~*hjGrGr5dVp%n*NPEiAG>Uv4AYN- z)m=<6;H1EHZhpIKHl>!SbwqGX+)PJ;u7Oqh4K%)HP;HMuaFLl}Lu@0MspKpIEbd8X zdRB7jq}vog%8K@RxOI&a?gGI(;#W2ze0m}?{|*ioiJqny(uqg{U;g>9Pdu(WV5|S| z>_WW$jKI%IhSdqJAJXXZZ2-Y7yT}0)1nqVzt7qj)?M)E5DCE<(Ar5L6Dy%of0IGS5 z?vk*2ltC3h&N<W5$g!vdf?@dLca)H!V~X}uScO(Y23AE_A4}gaka|gXrWf(V5}zh$ znKxAe0CNMXXn(J5z4$xR`OkU}0Y?mV{T>8qQ9qjG*Sr+J55cq@|EI=iy@%tj8%+4S z2-%yfaUMP7060Q}-srT3`-rN540(SLDswJ*3TZyA9j&uLiKtwSD{@Y`jzv<}FU`Bj z6qJAm^(S7H|E*4yxG^zpe<q3T)s95aVb{~2iYT%9KCL-MAu-+nZ2<fEg<{i-trsTJ zqJz%pMUu}bHXH6kJJZKxq2(I_41mFc&!o&e*^Q@#J0%h`ZNywBm&d513j*Ml7oVim zz}FFjvkzbjO>sJ&t*hwBHK869CdXh12u7T=5l$f%_Tz%4SRdu_!U%csK|j9WQtdYi zW7D(vhWf`_7bYu-VQbw2p_yFLFrX-Me#$r$J%OFv>5p(Xz14RuJ9R#*89)$uO){rQ z*)(k3>rkH(eD!O2;*7oJzacW7@*(MOv`CV-j84Dnus7NV2Y4Y`T?0jqr7xMPfi!h5 z?=O=PW%#Z+@(xhDlJa!k;4wRkN}B2SaEr$J&J(26DtLw1+1EKC32f9e^4o2Xml1)S zc>kGN^GUpLKP|y|iZ#0(PWpwWwQbn@;_6c@enbj!Th<wmK&1h$ly?jWY_+U%43S*a z8Gs%n<^f*}1%$zb0CQXBVJWfBM<WxvXTVkM`byn|(vQ@6w_5!sArT9Y$G=R@-!GuA zlydey$PZ`zeZ|kR?qs~Q2r~aNMP<#2IPo{dW#$hEz7RIO+ib)qUw+E&nJVcSf?MFT zfe=F^JWS9^0kunERXlh3wvJd@lXnncfHXu&`i)5Wg!}NW-G9b)J$hk?_A&fZb4?|6 z>fC4qHy(j&0K~pNyt4kCY%%JnwN7tmg)3({H`UsiaLpqaGbN<O?v5KTPZlmSQ3{FO z{W-xE1QuC)xJz&ULn-G3$*exP5-9qb54{KsrQLUuMVfE=-iQ@#yvZTrz4~Ht*1PG6 zCn6_qLA%Z0#TiD#oO$*QJhM^9ACY`P7Iuq$Ie|1iLl(8jS4B$BO`f&$b+02d8j*Xv zSS(ZbeQb;K85U}6^BXp_LCBYnC$_wx;*%)8E7V&OH!d|fR0mpQzFO~;`&HA_l0T+^ zDw8>n9+TLEg#KGmHUQB(=jzjFb+75cSiN2X|09~5P!-u&mUEWI)^>6=EpmJ<f?B!s zpV#qKp7=8$w}tO7JUWZ{|JP3}3BNMycXf!q`*ma@i^j~nAxt1ew>WU9qG@hE?LJxq zCcqz{NvG7W-bD1h^FA`mDwx7-C!?>noos?)ZF{zG>n^v@>O=FsnYxQn2=l{8U21r> zD#rC?K=Ybz4+vX1fUO7#xI*<{HfJG^fTY-UYVlxlk`(C>vfHB%ossa}w9_?fK*fl| zk-^=MCa=20hR$3jx;W@l*;H;`+>Xtl&?pZ==U#$@{~|}H@$pQa<BZTGG_o=3-wQ#r zW1zp`gfEeO0%sJ&-&x46m=#1d!FJ=3^kd+4nEoWtnXYj<;GQnh==S$Nu|+N4p;mvr zywz87`*+7YwD6uUc>ARKc2c&bcbI;w1QynPdeqxtOO_Y%d|QiH)+Y06eBIc2>Iynp zR&xOB?@pAXY;GW`*_IIu1`_O05TS(?WegHqgO{GRn68STmb;V0TIlr=nOKKeehg2= zM=t43tgCaF`wrMWna0ri7VQ2coBNxLN}hKT@S1a?vSGw`r@2vcngy>Y8qp4yWEXE4 z=l`k)ED!}s6L594_#o)ltt<WLOd$WGMpx-WR?CRtpmVszis^s!-nG=UX!4hPmO}|( z)5|tp`QQxyTBo!{1d*5BY{brM#(xB&H=|Ox0{(!}(Q(MGO-~wiw{JJzZh6L^dB&6W zesG4D#{NtvUup)`0n1|L18%PEAnmax`m4ydMpidS)ju%3VXa5!s5dI|K*2!#y9zl5 zGAGX!(<E_J@5`{tcYsGkF)xeyF--KwdPz&I3-%%4fKG_u4Z+1@iosggSX^;qYYqwF z)#6l)Q&Xrl8+@xE`iOl9ePwMscKmgVj8PGzE%LO*{N9K3@Cd*96`)V(Z#8Da#7roy za~sr1JJlGw{>7Jk539strFsRIcZXI0D<>a*UsnO4@*7XR{1Od1G$<IK%Agp3x1MK| z>^de#4bJ<VP9B)tvN-yQ@<^)JUuW3!v=WacHY3UC4nCmNY>J!`g29Ll<=mH69a8gT z%wcCo(i7Pz<i-wsh;mgZd$V8F>XRt6k1HDp$8ZAEP1-qmz{Y;=6>&MfU2>29vwv&_ zSs`I8b(@JF^r)ZANzQ|qC3^B#10fTBmBz?Fb2HYfi>4cyeFz$>ZsalgZ`<8qbrsrs zR1FLH#D6(F)>O*0p(<SXCT{!DFwEUz{kw@ffi%vm2*}Hai#6$G0*11*1I}EL5UdL< z?~EOv?~PqO-B=RJzO9Xf307J@bZNA&*y)eb9XltvsTRf1i?o8983tLOaMj*EkDzLo zsni&o!vPdID%D;B#Kl`mCofEVHc*K}^Q#q7UMSMytsJ1)6Q1R(+do0!n{l&VZ{&Y> zo@C^Ab=ptgK6KH3+9jO|7UAdF;5lt6qSrUAywtNQoyI!#Xz8sok_bQFV1X*8nJg1< z4|L~Z<d5Jz+s6DmOH-(eW7>JnJfu><7NnXT>?yCzA~4ioO>C1)1Wiv<B(e&02ke5| zLoPtvb;s1UPCTXK`U{WZekcElE7`7-JZjm~m_EISVp<MS89xe{kBbP)*9CYdks6yg zCgV+s#oL|hVNwpVsWn|^NZgWsa^T@!plvgQofbD<l4buy#g(6cOON7mb>V?zx|KAK zzx~tbE5e_ZAg*Sp5ZblIf^X1OV95%HEK8Tbf4bbw&CK^Mrjh-f0V)Fw8(b0p^-W;- z@@p6+V);7C4UhgVt~=3xd!?@NN3t2^l0jdJ6T?OgRA;08Npj=l$NtVfdRHUOy9i1p zo-bM50xJ1g;0L4W=3ehqnV*#}-6XFL+D&V!v!3@3^^5%M8Hqk&*-bVYw^R67PifXr z+<adn{Pd(+Cs+Kokrw01MGOJ?bNiALUGmM1%hZ)D5xg%((~(;l4;GA}Q?T&EhQrP^ zSX5bCb%9gp@Fy=$>38SHln71o!>+{}Py}@r1(0FKGh;hZEAS&_E~j3+ZG23;WSc)x z4=oE$jVdACE~+yww$3L>0pGt}${;Espxwgo=T_Wac;{D?DggX6s!wbfS3lOEPRXUk z!msj)I?i^Q(&W!$O@n7>ADZO3w}fDXVj~sX&AhtY(7;to{-2WMhkL~L%t635N7Sp* z`o>;&0l%}C<6?b*I;0Xma~@wgyL(M4pj=d=W|vJ!as$EiZzn)eY__i8c~27eGB6ZJ z?o*8*O06~8n-a;3QS!Nke0#oA{f2qy-kH44Tr0)l>Gal^r9}0PK+t8zaQc{tBCxD| zooeLpsa2x%^3mS-pC5m7@C~}I2G$TNym{oIL>9R?&KCL=eDr^TSNr`8e=9i)3S(y~ zRpR!_Jgfwf){%SNaupQ95B$@soY<ljhxn9H3V4V;V<t-<Xq!fB(aPqPAtxx%2)<v5 zn+1L?4z+XLFr&3^`Y_SN4;e^i>Q4B-2L+kp$U;K}ECDvJ=|@955_m#{!S%=qNF!nc z*vlMBQHbuve@}}bLM&Ky<i!k`q^V1#cpKZbqeZ1vaxdL5r|^<%u0+Bxthr?Wyxku? zkG_ixAg3dK2t)k@+uR=P!{>+xamk(t9s~GY@;9VuV22CG){tmbc&R~_Pj{fXCBt9m zvgC{KA^c}KGNc`Ij+U<}eu5pAX(>5d3U)F{Npe-Cm?(;?P|0BA@|neByU5>7M)x6x zU{%J`1<Ju!{hj>j&4AgAOS{{m%E#t8_a05e4}8f^Mvm^5=F%kL;1phb9Zep-m8+CD z6{&ne2llrP(t*jAKb&l1y-z;gwJ>-Pd!}U!;aZ9bmN42B&y~nROawedDqB1D%G<Ms zlPW8yREX+R^6rSH?S)D}m*1^rHzALPF0k*ZrL=$FKhy}3TKf7xPqC5tW0~lirT+J2 z5<@gBhz-Szq-y07O6F4FtG!ynYB&><{Rse}VQ?kJZh7i8$`2O_VE?{<{IE{WIE-p_ zSYx|jt)#hL8~r}Ns`P{@A*b3&G<-NOkP=H+UopqXY%W*y_R3=@D!6SAQ)Rn(TLQT8 z#}THjS9m<n&7iWo_=c}zi}O=EUBge!+ETvH2-nPsz^RC3_c^_WEc(KgKlA&p3VED0 za$4vG_-azGP>I3yFUWzoYB0B8u<M_9VR0spE>Hii>|pGSP6`sF_pkqf<R>)=jvkIS zx>q)EbZ0gMZ%58b7R#?_52-|Op%?o+E_Tf4eK}uWl47a{cAY^=Hy)T5Lk0PPY4005 zBj8|x<`MRUbN(RKF2nvV#fUK=n<tgE$L!A$JUu^(DF#@gF#GGE5!B)472D^G4?N@5 zpP#d%WQ8jvpGeg5vu0v@(*5??QcP%Ca0qmLjLg;r-v6o3nHdpJ3&YU%!rC-L<1%Ku zZy&AnD0&nc!THpGl0`jNd4|@<s1XWiGI-}d#Eb8)%6m_(8!X@ldj-BeyP<py(*ept zAqP(5x`VgI1$lQ4J=haNahAZ%BW;0JIs$<o#_09z6q?GUzVNp{ay!jB>=5wa*^nmA ze+l-*Hyo;nT<&`=_evobKX-;#RYlOG%=jsP*N8xn@(T=VC1IC22*v1pFr7E{DX>K3 zOXG!6pi8g?I%&5hiJ5`V{*Y{mcg~zIv+&|78O-uYX;=B2ZH8XJK^KC-qr|v;d7D(s zCBTxKzE`?3hRJ@-<o(RrQ@p~52X<EImZh_?(-#lz&0Y5EMsKf5p(Zqdgp*@ph3>PT z-bfF$lP{yPgkul8Zyxi}Pk}A3G;FQU*`vQtkV4PC&~}?W`iZolI`uLJHbM21KY=XI z1m*@2yhK%Z4mI04K=!1Rq9O(;(`gK>BA#Q534|F%21Z_VKTUTrUqh>qHhHOKt?A+7 zuh`O?GaIV8D#z(Mr-E;K_ev)3kLw*6SDmM0M9?BNkO*5d+eVLz&ashlop#UCEQ89! zf?Lr)myhqh)%MP$!7e`YiWf4NJ{K%m*&dEz9eIjecZrQIzK>YsZxxA8Xo;FIh84cv zQu}L0%Be@i57;@E{4MTl#2<+`08j#~k{7_vu`2^k4Kn<@>UDU!f<260vEyDgGqK*X zoS63}o)&V%bxa&8a$a~YW>?J;-e@M4cH}(==)t;E+`1hCnw3IE^FV<{eG?l5rtw14 z7&07{j8OB|m-m=oEdzl87=gfV;%(8BADRM*O#6R#mHe8P(sTv_Y`EN^<T~LIk4%>x zbjXdA#vQbAh99oWfDl@n@6l`=P-T}~<W0bxP8#|*E+YZ0;+{<@6LX3{@!uQ4kEOzu zZu|mCv6@elHPtGnsN8h}hHYBvtK6u2tk)Gp41VDfLw|>{Es6Q#>`&V<@TD`x?i-t@ zFFh9nE1A6d1lwC$ldSvBGg8;2Lo7DS&H?v{l5hhz^-Lw!Ry$7#Dwf*5al)m95-q#F zVbe4*oeQxVd3P>bR3=Wg@lw0iz`o?iP#3<1_S~}aG41erE2+#VbC2@ZC(~Q=vA|=3 zSERv48e(Yj%1H#0Aw<t%YYV!Re7rYf!i;gh!f+os_y&)zKGyr`Z|6AR2$7W*x69X- z2CV63pyHpx5HEgP80K6;9-AEXONgF%mXBJ8jZy?6I)<~XmTH_bQ5AI^l?wW$g~=Rs zVQR^zj-&YJfsM5R*Cl^|)iiAu=5_(zes0~HHmLnoipD@Vo4N!?uIYVCU!Z5?rVqZ0 zYhOmbl3vr8v~TrgeK%BM1#*bFyuX}&@X*IEfQwr0#{fzu1H@x8QScUuI|=MiNSLP` z_J5S1vW!_-Hqwei<lJ#{D)wPI9eYd-qCOcCh0cz#c8xYnNdT)ltH4js-weLKoUPmt zjf2WHgWEKJqOZQ1AL<9T)7Pz!;k$bSUK48#v*3O1ziR|y<7V^j51r!;RFPHQpAj9@ zCeTtv-5*wL4$ys2=(L5LsbtHTD#OKNx$jxJ6W`?c-Wpi8344gB3JE14s$)Gy0TW6t zg2qH96?4!JZ*O4`H9V~E+JtP|fR_c}lS?f5;PS3RKYMm7zdR4!9HnM{4P*i|&uN^m zm{Cj1qPG$Weum%vY0eLL<9;ex)$pnaoP-l?lh6^`n~aA59+Z)6oaL&)+E8WJ+%?1y z)Gysgi;pRtEw2m*_2myBcn+Ww4+pReJRKhLH&50sducR8-oKXd3&e(f-u4efAIyTm zHhYlps{z%52PQNLB0O!w>&x*+<oQ%DotW=BXDBjX5_Vrq99vlAj&Glp=^xz+Mqqly z{!}vcsI#C)xnb@K$04l}pGxX&H7xBY%})DyzoFfAEpJ9SgN2N-$Zi0EQ$uWU2<>A) z3{3gBRJrL>ZKGl>C6yD&?&5uBK{bPOMB^}-UlWJ}<N1l`KC7?N%q9wA3OxHzYaOh8 z!>a!0j|Zj-#R>t+IL!|qH88XPg$QnB1#^Vb<Gb6ty^wVb%SIG(Hu*wnA@2Q3p$~s- z&v$bUEi}!Pklc$Og_*x&`yWc&@q`}Ti<VzGS0r98ScHE3ns^z(RJD(JpZR%J438O% z*8etjWco3j`BYZ_hsN65S=!oFOE}6ukW^aLL)mwq_G+6+7yqyRYYPe_TMg5IP^Djy z)rg?*3beYL1|C~V75-zM6XWUg%p#|m1E$HZ#f)eAOm8x3m5qh!hmUJ7Uz{ZtCu)@G zf*j~cI1z8hiw@owSG_N0cGXTU68}9s8?G8$%c<3^J9Dyp6p*O*^(#Ao;zvpE+^Wya zPH2Ad)*9tn==id@7hhaSnx9qR$L?gJF|<(atYM%61XQZ*Jxo)(^z{NV)MAA)kNik? zRi_HO1AgB5n0(PdO!ODU4FLP%d~f==lbk&n_E_8~N{KY@W)GKVZw<b$Cz-zx5i*(Y z_NZ?V(ZsDj1L{v~mkqCDe;j^De0ubeU5*_~?=gRR4b_R9NlI1IR?z&2iN<^xnNqa! zmU{KPfqRi`Px<}HyOHetL!YFpvCY!%dFD{6jE+~geqm$z8cVOuD^Bkhy937tu2ODy ze+s>D$Xj#}5udAgIR;6gpw^PZa2%ANZ6X2)ei<N<vrW-V+&IMb5#Leqy5L8t_L(>1 zmf!crj0UkYknbi9mE2+F#Lz#oJ!&t#K%}>4`XK_YoX3Md{x+9+YuYLhe86(k`54$y z+wjrIuwUIGkSG0xRo>N)Q~M|~7GVb>bDYHxu)>+U-G*9WSYuR@V3J5hY@zAMPWuNv zr@cqh8`y?ik%Qhx;v@1UX?jpGvZKgC2(plxD72s3+u-`Aa&dmMk}GsR$kn@h@;s1D z1zhrcmD<sYX>4)ns1|<5kuF@@uVw07;E0=G1FZmh|9f$KMlD8hvWhCJ9OJ#L9=^rD zT|+C{rpVGG9FTsF8)VZekzz798+wN_g~SqkiJ|M13j^9qtkhVfmRlhgMJA7sx@A=~ zSZcvjip5U`oG~7Gpbk=D^BIp4$?gF-i}5Sc=Qe-Sv~ESWRqYR~QUtVM&L@+X^if|C z2?e$6lWRpS>j-=87IH@KB?+l?=V#S~0fuxBOoRVXu=Qff59A>Fm4NHQG+glPX9Sb! zYuOOO%pZ4X<DLOaItE6@;dEE#R^vGUL1thtcF{xb%UDXaT(<zujz2|y<$`&a6O5m= z#Ym^&8D=aB&?*B^KlZ)|!q52Y1})*=_Z9KjAjTOktA!-O?1ZatGLv98Mq_PxRY!;i zY=$$wxXpt$8(}9T0^HZzWS>ZaF*(kS>XVK^8md39SWfQxKM?WKk^m9yJHr$(cw|P_ zN2ih>po3X-jCF+oBM#PAsTjztJLiLq8k_MWYdZnpPj&W}L8jS&h`kOdk!{S*b^U(6 zoKeb4P#Y<egdeU9eN)gBd^Pmh9H=#&K-#I;zur<FI^Fn3y7b3{f7kk0Q+|l!zie~` zC~3y1qrf7bIb6@rJE;3!{iUBh)|jLyqD6=wBaB;}9gk*0aht5y&axBCLj}{wT_GEP z841z{Y(~00JT>E8wg~;Xe{%UsQ90r9yan%H5HJ8;n`~^L@&I(rRM7$JE#k_QhSz)C z8gvf3(Z~P`AufNLn=S~!Q)&(4hE&tp15q15c*BAV2ybQ`=fGzbfJh=d3p&CCl&e@) zi-o0u9r&pis!xXHZU+;<;`79W-^p%}51wHEhHdOzIH8b__3i!+MuEvixCsV_sO>`8 zmOQ#cZX(8f<r7YB>hao>9M;9E)a2=(WPkq^;Dofl8TEVe)knAGP_NVD5nH;qwyNd7 zgBT#_V%*?EJJAFNxr*}u2Z0s;UlA{!b!+tXZvU_D@Qa4Ro=nN!8$8y@)4{)tIC$>9 zqE(VsBUgZF#?}+qyx^nlWA1<j@DB8V6UkWHI|XQe=4_AL#Tr)FK0zXM=4)BRPcjTT za|qSn@+}GnbCmfj6^z_FzxkfQVF+AZ0PHIyBo;68?w^o3c(5X)iN^GIv5ts_N=H<7 z;p)x{P%@zaEDNz3;EwccJ7QsfA@*HGFC(VEj5llz^Y&94?DeA0pNW~?nt!6B8Y&cN zZ&?c`*&%i0+y7lfc{JqYzh6FHUfO4Q8B8Q6ZW6G`>i2&bd+WHUnlE5{C8bqVKuSeP z5fJHE6A%%kyQI5278F605NU};kuK?OWI<x-?pnH*TDE={ee(N0@8|dO*K+UNGc#vS z&dfPSqQb{dh6BgYVtN>pGV$H5^8E+Vz%t(`!~4ClKrDjO(+kfggk>LDgCCDojoDFJ z(%l(s&j>uG@R496Bt9v5wND;bkd5&wJsmVz&wr5y6gctY?${%^SZL(K!}$rD^&U)W zgSx)bQ(ftM9ha<Hl*&HNM3&>y=_>k*Mt}=Lz+j);jIxBN{fY#Bbk1N$laMVu4*Tfj zqZ!nQY!E^41L}8$D*JXDG@X5w{Bn=6y>G$@M@4-OagS@6{67EKRJUTZE`KZ|r1yXY zlFQGMMw_43_hY}k)Cai|GY*#JOMs`!-!<zgSbnpISiLwN_!=;t&sO)Z-sQ@`+`p1g z8Z#6jpElb9B@8s*S?Y~brA0TTmd56%exir;#)WA9AOemlEO;Uk$Yjj9Z$uI(4^YIe zb%;(0U6|UjSE0B%iI-`EkrLLd?Jfyv5kHOLvH!+`BJLhS&F*$a8TJ!M97PQ82ck+1 zpZJF&KCL-k0@9%URs9Hv&dXMdo_Xzc>kazq<=e%jrm7t&&%%@d1o_4Q^-eR;5clu= z5mI>zFNcm+lOmus?Y=&DAE}qTa%I(Sww@EZ|NQm|XuLV~d}*O|rkY>Iz$XLgKk<8p zX6jqNGh7XKizdqJXs%_sTjVbJk0=7K>V5)wB?pH+GsFYZ>|%qi&}drcqLVa$__yYM z80~b1{FWmt&xwlq3xB(`p_>^7FV~GT*0nXMl-JcWQq|V;zr~*o^G}3+CH$S(<X7R8 zPs6J2-VK5rz-zBBwzxWOsU)mH7;{O1vwX_ev$8hln0em0y2MiDftA;FaoOg!N#*U_ z<+3^97glu7joQRcd>y(@`6Y?#FixeB>riKeN;!v|y~QW?^i$sHie~ZCzgO|r1YfN6 zfG&Ten&6@-_pp=#Fs2r+BrrI((413<JVEbV*OH9rc!#(*j~h@Fhf_VNFE-{{+K_98 zfu?n(ic&z7UEW%;ykCY|u!<}LaxLGcG0+HVwTH-ukUsua`e{`uh>x>e=hs!(za|^{ zJAG-6d3&eYpA{E`Aq^r@NtbMJzL_eK+~q|3z8_UaIfb6(B*o+^uIeN_o()+>l4rzm zyGd{`j|1g!BO5ewXkv6ShKPf~jl_-(%<lS+b0k6?lU0y!|3#=V3BNNYTbm~<{25?o zhD0c@jkEBx&t-Te>=g)n!Yek3wciG!&x?lkUM?iXSmzBb%lD{TXQ;f$U%j~rEq4e{ zk)JLY3JnJHsag}Aoa$sms9Li$Qomg1`gMu#ueH3L`HLdIeP-ZL1&*J%`pQxgwdMD- zF1dY61g-;7Fo_$DJsEaDZZFXtKNy`^sfbZ3;QFZ{3}N}0`XYc;bNyw8z4E$d2JYp$ zaE6ZaK1)UoXKb))gg*#zqrI}-G-F12{Z_`$&#UbV@rySydNtRz=ns7}glQkU0acPU za`RMn7Gg}!+l$yQcD)h&H_!foii@fH5wp1Hx4Hfk(lfNLP;`maLAzu}KlXRELtp0l zXp!H-Xvbs+fwR=cF{rQuTMl~0m}~ES!VBd6VutTxJP0i!)N{jBwj65(t|a99*@V4Z zf042MGB-TbK3@f5ER7Y&MqSC+)?BwmCO+zcmfjQ#+PP$}X&tU2*gSL=AN@Cr$?N^j z=OgPmy*W<9gnqmGu+RR8DM^(A5>Y5Q4|g*CGKWMEyj0~<xn&qJtWop&m=ssXp^63a zp%m4snVTOK^W0oDKeSkxfhM!<>(H7<q8DDwW<ziq5Pa;5=yYyi+g}M@@n9x22U#!Q z(_V~J!`0I2<*zyMO^Jdd)59nuuE_h5rElAPWlT~R%@BSyDJfE`Hoh%XgG_m7c7p7w z@@r7fp^NoSqPbW>_b=(AeD8NuI=}De1Cu1t$k_(JY7RMS`I!&t)3)RM)}!OglW)Nx zn&;ATTc8x*>neH@1@ep=7vPCLUoj+iBaD939&MU+T|@wBc+H<IDbjnqpT)6!1ZQRC z_0#k6HS2jX0h<~NjoKVAPIV##e00vvBn0hA*WpWe?!6XJn0{$2dx*V(f9z3?%2h}& zxv%)PL>$+!R?fu#AUXJV(0cOrc1C+K*0c#at%v&1@!=+e+dxcyYKdy;w`pzx@=CN4 z-S_uxI<+p8Tw5QbPIxMuvvb))lqvOiPpoO5Nu-6S$-Moj(Xq+jfEoY!;>ZCvH5U5~ ze5rh~ll&qnB;t_~cEFW1oUujb+iC=ipzfmEQs@nN!C+48%;lSf9pa3vkO=MXmR>WA zS%z~7ywL0t*bsC)BGNA?2WfxoFn+b)r>WzjrrlBUfsQ=w3LHGm0anK2(*1E<*C7o$ zIeck7k#lz!FJ+|811KpXq4NOAgENM5noJR*gPzX4<S(0nQsO-7S8^q375r`oGM}A2 zF#F2KU;g*1efqs>O^%w2h^g#iAcfR5f5q3e7LkD5y@Y@(+p^nLZ0;hY`dgO@>y5lh z-`>Nf8N?U?xzNB$kE8?BZx~7_`5WI<rM#rnbnU0mO}x<;hB63NYmL6Cc04*&pBqBS zbQKIU?qNE7uSaq9$^#d(yFw|XB%>3lUOPquZDahVQU{w(nefe-IuDMHx0&^raa;PQ zyNKyp{Y8&azV+GJVHlq7BiN9L0Y?R8Jd70&D<Z<RcQ$`qio&=uH;CE_sjX{M1IIbg z$QCnMp_fN05jL^wnL{DFh~I|fUmV8C^}7TGU^%`C=cR*7i%y_~Hbjbq%02+~GSZ@7 zr$+;mUV-~;CGwgtYl%v9%d_!~J_A>RsyRtl#DX07xWXO<r3{W|eKl%a9UDNJJ)$kX zB5IwWrF~F5B-AFjpIZl%N-jx2mMS&B<{YT-bhs~uxD&CFd_eTxfb~Wx?e_Ce+`^Cu z{qL3|BisI0vzMc9l5+9b<Zn6q@9&%Tjyc>;c;|b9WC5cQ`DM0QtUfq(h;O<u@iN?k z`|uW&g2~#S{wD<5)>2)gA`+NZ9#vXkExMXO;8pl#DC1<RiqgiSU?o{E@-Yn-ww$V< zwzwEv`S8m>Wz3}?1;0cxky$MXqr<VUXy1p3tw;)Q|LLycN}mSRs##x1AB`5*n>6OS zy7<tiE*CGnY>>$^7+QZ!VZwPWD2$q3s%(5?zgc{3<0;!fc!)#ieh0o3@6azLf9qrZ z>~?_RTc34t77UYd1=HO6+|@y8w>XLWG(-E(1`3nsug*`3p&MCtdVCT~y<Bd*=AB%0 zRl1Ca*NW)MjB4lL^BSfvCxbPcHmeg=)VpcaPaOOLTm&w-3N0>;$Ki7B?pD)l3aPJO zuamNgT{5Muvs(pI@0;G-XmOSwR^#TCQT*3jmw&6DphdX7LS4MzZ`Y2qED}vMs!i+h zRi+QnNj~LWi07t1AMnG<24DmCsDGr@8z8PdthT#<o`G;sJP=D(ykUEvm8Gx)i~J~p z5tH|dewDZZhx!$Jck2iBHHb*|lP>g;?IHBOc%{WD#pPF$G0pZy)VldhjmHiAELB?C zc@Bfiy1G-=9#OAvHUoiD@p$0;|8KDmST^Xu-$LmVSeBkk)?c1~U_SV9flJ@M0dCX0 zC$PaTArIKvDf=3@{0@ocf*jGPen+{KL0g7(p0KAk4bNf5D;gEkrf>`&WD<azC<(-+ zNG7V!2p-7Dn3o4NQ!h!E&rxb+{nVxta;ct=T@)?Lg4+}{XU5s;d6|}OJCx#q;M%{m zHsFH&VS$~e^uU4{R|$F>pqyb(x^S}sLl(yrIA5blFzE`sdTeYv=?Fgae4!Fjp~yiB zu64eAyJD_T^XpL7R#}@#DKpOJ9oaJ<6ZZz;s!_4vAMZ;6WJ`Q8DB7e>8yV@3Y8`n$ zxF=Naqk07Sx0&L4{kK&VIA2&4TEfVPPG6RDWVRAaak-~V^J~?X-EMq1(qgexH`upe z{TZ)-+qB7KoQJf=7uEE<a%l!i5Q!*Z!DtI{O5Vdg)8z9I_i+l2$cgscHcm0Jm;6eU z{?vKV3n~)d%eeOKVUvQ{UdQ&MW3GCSeQ4rkEhF(3qaKg!GPkJt{u?iW9#W}-UsJx{ zD36?_hI2t?S>^#VzeJTbdz#xoAv64zoq73j7;(d=PN?05)ekQK>GZ-nij~nd<zDyD zvu?7*&h$txWbf+UQqx$~iHm}bc{D89uqTl}e@ORmM(fd@MP9d)fG#+zzqr`@PAPJX z_(Rw$k2^{G3A{UGOnl#G(Cy98yPq%!=t$F0{una1#US01xf?B}T-qFC@`Tw~)sBlE zA}y|8{?fT)9-^k6%V`L;jag5=+?{@nbvfo#tS@3+{))NlX8hJnkkZe%d#uU4-_*#+ zlb~LfnQG&G$NGN|sB*<`(j?zq@m1lMwSQyTc%i?}u8q2s4{3pSh^w|^kM4#}?|a-% z=7$_P&D8>4liZ}1L#n%d#Qo~<6*5s<$s0?m>e3H{+@)5&YT?3<%_W#1y+3qin4b0m zSwi%q+PD)8jT-extxz3lPWu+HE5U->Wospb$!rahmd_pN&G1XhaBi4Q$W}VrIb5BX z{?@Na>7}cgWyo-q-x(I;N`Se^XK)EU%E`#-4P`=kO?^{i$S72?cFJ}6bg*cbA<XIa zK_!G+Jp%pYV#YO<F-&(mk9-RKfjiG1Zin-4f&&~l3TE`Z#q(86;XJi+Zm%Pt$K2Xd zx1DfdOi76IT^0qm_7N$AdTQ{HQy|SFqAfQ1Q=|ilk~>CU`pH7SWiOL6z3J<Sk8HFD zhtwAd-;sQb?4pc!a?=9nvz1APg@jqK&`6iYpBVW}&|AK`vW}<I^Ft$#^Xk(RqgiYg z=^e&p-?x47VBIK*F!6IZjC##awRO6L)>e5l$EoxoL3wOi3B)-99DAyegNX6g$q|V? zox$cw<22Se0Jq9ISEcgOFj2+|*I|R<oL*##d_i!CZ_ZGbe2=De(xHt8v7Orb#b`wS z<x!qP7d^7hi(3irrWe0?>h_8GYpzp>57%ebZ);dr{M=5(zi?xq6)TaEzx{LHKG#LX zD6-M&^o6`s&QPAb-v-?ZO@@J*b<G+h&Ar`5mk?CE)w)nHW{apc_U=I(*)FZikIS^r zMg+8T)U{pg?DxV{t>dmJeKaArb(iGItP76z!E`D}=;VAD_xza)P0H!yMJ0vjuhpxD z`NaR>({tAR_EjjibzjD`^?nM6y0Z&35bF7d>0Ex`uNXtadHek=MZ?iP!oiqAgv%|{ z>lj6!acUHJL~*hzn}H)V)_r?rYE52>nknKs3FJ+_NUMuDx0|Rk^O-+W5Ki&%j`BMB z9ZEyuNE!m;HK@Ppy3}sR8aq6T+l^P0^D-PW0zcT+uUe&<7i0?B@+FEutLH#41e-@) za0$I-3JfhA4wLs|kpcrb6QL$Id_z_2Uig%2<QA#8bOg|DLNKFu(WGT=O==}~@j=g} zNv*^Yjp;AIG<8yYbj<!1u8ZBrp<5pF@cu|h_Eu4Ld;UD+jfx$pYsd2uu6KKYSK(TX zLz${|whG@MuUkUnxlg*WHPKe<oUfUw+4Ntv_%`eHYv*Lj3&BF$_T;HdB{nsAG#f9$ z^|w7qT<mrSZUgCYU+jTzn?SN^hVOOCXe=MAtt*Rr<(Ay|Q>by;|DP^B_L}!{M&{N5 znq}eK3*|*M+s6ll57A(MVGQb_(cGat?>)~g<BYom40cVqjyWnO5AS<$xltQg<g!9= zWD$PX(me0>d6H_pEeZ%;cyK}KHRmkJF)!O8)k;<+f2RZu+ByYM8@rx6<R@Q$kv%j7 zs~5@gWvDvAj)OVZS0=USi}TS5al%SGw6znSEZG5%mj^Ox43|YY_yYk0@ussACAt=| zRz+?HUz<l#AF&TrX4P(HahFRuavO5F1*&X~SDf^T<B7gG(dUqcB7C}~m5yyFNIz1W zoIekVaK}VYAq(WGj6NPUTkPut)tCGfqI?88R~rO~ulkXm*9jSK{kWreoIw0wB=x3& z8SG&QDv*C;oL~?_shL}$V)Ce+c1i9g1gD)tG5*;rDy1PtWQtEdg{s}Ka7ZMlEBMcf z)IjCjzjqR}rOYg1Jl38DF73E^;)CBki_?EgYX5_ozI}Ea<E8E`%)CxvIs^EWwE><5 zJ)N_l0Bwlm+r|&g^26sEf#{?pPfbz%oJoEJIy!oSP1cciL}4R0q@z<-zMiPYH~E%p zz_`4d^13{IymTo`gg5nf0nbO3-0CcS0^Qzrcn$KC&tyo(DbK)3k2a=&VTa}x%zJ#G z?A+I3Py%6h?Uu(m7?UR9B5GYjHmp4b6UGKE(iz9`eYE3}Nm4S(Ik_L#8nJbZY{OiF z5xg`Y`F<ePvf7oU94N$p)otH}BVP0_1rx4r>b-^JQwljfe8`pMI|HB1P+Ig#OPViv zYnx&d@1NfHXMSu`@ujr>a+Of&=Q+`)xqe%94Bhh;__I8LZ&GuqEk#3Hx1xvht>)w+ zwpY6K)lNjNLJT52q9jm<!v537PfsLxzfNvEo3Odcw%TaiQb*L`7f4;&_suN?wt|Q7 z&s1w@K!M9$`f+?8Dhs-OpDMCfFQTsRqKU;B;oL%R>Vs{ZVx;;b!F;WkQO;ciUOe-) z#jtPiI=KB)I`1`@`IME?wFo;Tt1Xi+oB=ziCfrqM?0lX@>0|3W9A0AQA=0yVYY#6! zUis<}%dJ1ru**l%OL9$o!;_M3f$Ai}c*Iv?fHJ(t{s=9i*&|~2WzZY0e}qqG-zja8 zoTrYq@hMo?-`G3KM+&~qw*Ru0Qhn^^-Ni0nnQ$WwjoH{P!?7O{Z)55h1-qFKt}+9a zcz;Vl<*9#{&6~(G+V*>@ysVZsH057pi<4xRVobaX^2l#}wd<Kdt+CFZ;r&?dCjV0z zS6tn@%4xngNq$5!Cru~r=MN1~m1F#1QtaxtA^8Wckn`>A`AiU)S_$=&Q&pGYyJJrY zPdf2N@(%}U)N?)?71DeSL7g-8APz2%2y~^hgln>Q%U*|3@Zv9VaJl6aTVYt%hiS=m zE-mOs%8$gAm3GucSV)?GJ%)9|BT3GM1Noiud*JH1q(40JV>ouFn>O|wCDd|gIn8N3 z`#sur-*qZ+dH9#?g9l59Q!E?6t8M9T+(=T0t;X>sc6*oo%*oY<h!&=aJ0!_IRZJ{y zE%Di|$o}{N?cyB%v~u!kXmp|Jh)LYSS9r^259wGuyL_CmL!%gwR*~uddC-AX;1DS& zTv<tLd*9(|GO1pQy#U72n5DeMbXc9ZDPJ)!T%|l4>J_KDJew2Lsh2cd)sy|vzAVS& zf<G&-bh2mgMR;@2rW_x3*fYpeCg;Y1(lk`*TbA9sQNA8iFb>1_ScnIFWev%ih@4PA zG1el+hYp6h*+%KfzxAao^Mxwl9%=5eAM@FIv6qh9#bHZn;blg9Pb4z?dJ5T)qxZ%l zzxK0=yu%rP-Z!sg_Ghp5j*0T&rJ9cX$=6z_sxMd-vEpp;8vEv$Ad|n{Es3S8mPIgM zd%-36$ZUiuL*&9J$<ZW|vA~7Ii_>O*FeaNiokP@Lk;Uv1Bgx%{PbH(qaS6r(NN@rp zt8lb}ps%=_@qp(nIkKFidz?M&Kc&>)`<>8~)E>840x{|HEBYaJOM2(kIdPaE6^nCM ziUL!abB4IIiW@cs2)bjpERPF-(%9k8iZ7KFfU`0B`y=#ht>7N@+Tw?H1oWt%;;d-k zq-8c;(LexqZkuRm%6R;i(mC=ML>cS+MFfhFfE6t94UAUK6{9#oBOyKprIuOUY9Nd^ z{<VrA=T7|h4YQ^~lg<Qc!G}3t)r=svdWOpiqzX)pY|m>u;npXg+*j=oFsD?>{<cAQ z8}eq`iJV-?(FK;;V91xwR3e^~^V<4^U<k9zti{7YK`Dn*4j`F$;HH!u3?20|8AQdB zDgwml91b#?o|5}HU$yIpQewJEeu6N0eCKZY%jd|RLpliU<?jb+KTH_WYTV$DmdoQV z<aX8ZXk`Qn@Svo~{UvdCHIVhaw<$Z%4K-4`KtmA(Ja8o!bwg`3$3)(hXGQn1D52n{ z?T^VLV!kNkY?+S+w>oFh;6?*18s5Kzpy=hxJT@S$-g<bL`s9P{yB1A6EZLno-6zM) zr52z(=Y#uulo2dSWo$NebXmkO6_ZJ;1OGM@f2$Xpga)Zer>)@$t;PXD1-Zk&(IA&) zM|cS`a{|SW<c6ml%v4<Vy+T!->`Gc<nAX~D1~<E--(^+AtLD&jbV_=yE?RN&v&l69 zOFR;)-SCh_J@>l`X>pMNbYbJJ$n3QrtQR+Lk>?>Xcg7jp%)c^crWhuW{^h6LPW#u^ zF0jdRSrG_!_VTXqn~T4YP<zAZw9Ce&1&Qzp%%cnNV}FJApbA@cZhGWcQ5ssr#1gzS z+m$BH{D5H;#9giw`uuxOsT3ieM9k`3+&IhF^9L7jm?W>F*}aNlkOg(?!<^G@LVo0P zkQw;gh`%6YOxf?9AOhK}+A!Plp$B>>GQHgf@_BFe?1a^Eq<QG*ZpSduB5d)7i+L?f zR+jx_gYyI)%;`f!8;YQ$h3_yqxU76#)f|V>m>%Ak*nZNn8_8ch`$gS>V0-((^ZZ%B z6Ga5$10jF8N(Ol0&(*qlc*eOCnwN<+{xhv#+Ca7^U^Yfx)M&9O?wX}9r?K=`mXf>R zApV`IRwfeIh=CrvalXHJ^Fbmr%j~s{CJ%l3u$okl{_QP>3Gr^fHkWIVRZst{MmOX9 zg7iFaFRu6c`^~b^$h{UsHzx)K8R|T5v_i6h*}0r6G^sVYid34rydX(18z}qkVp)gT zwhW3k8BO1Ty(vr_T&3#!$+PzdM)YQCwefpFV#Ya&>`7M64$@@FQ0B^=>?5B98rI?& z_LJbd{bYo;7PoLsPe!BcD<=60dNvPTZ?}T!Lxd?-$=F^bjK}1GA*=k51aM2m5WKsR zIbq5diOg2{v8wFR?}L9n&gN?)sf6|T@y*a;kwW-;Z`z6rm7v~Vs*2!Wsw(p~YdCG_ zlZU`H*ulZlsC|#Q=4VDhMK_uj=i0xVxRB(RQ01@jn7kH^QVN)+@8$?L;i!wFD=um_ za1wvu!?_X<4v;V)m;$x}8|T0B1}gH&pgyM_S6w-BOE(j#dh->#AOlluPu@vC1d;RJ zI~QjZ>n%O!L7}DY^5Z;?HVCXa-xb+afblijM{;;oeb!uzuWi&gDt3BVcadH4T>2E+ z1#NG10k?_8&1uH?dGg~hQpxKq9b<`@0-u)I`^&P)tTrfRCvHi5oMb}Ec{{?onEaW* zYB!mgU5lM#(nd3m1@1c^4YMu}k6r&RrHLVJm>3SKPW3(twj#W007K<#$b}5UcI%`V zlV+ZSI%<%XKATssYv>~<W`CsE^P{C6Z_2kqH3cKQ`Dtw1S$jh~>8Ve20*`l>;gHwy zMZ3VfxqNil1AAhy4>!XjznDOb15j^3250mvWlf?ncuM@<{<~$;2WiuV>go5gjgA6i z?>R<W(b#5a@thP3?W$5oC-;M6{)AlW(s2C%={PD!a}W+gnK}0+k<2ZrA*gt7-uA+( zWRb|0P~5m~<>+YKMYmnH^N_nQV4ghQw>~6l-EDcNgFu;)J74~&htLkG?qfE;!GZ24 zgLjP9e)(;n^yAWh34)-ky2VPoY4s7-3hk-%ZrRYZopK&0<vzv_9LW#<I;nj9GX$&@ zk}XN)+i+H(hG50J_haGggXW%j9YbRN_DQNlF;@2&k|>)Xn+59!o26gwLI`+6yiSlx z*Yn?W9)+y<xL31OzUtCU3DQYebp3kT{{oTu+QT)VW(nc@0gRV>TX+8bCIPuL4F+8< zQ4Qq3&*lJUJtBsDlQs-ozaPLe0i;pdM?k}n;T+#j>Y2(;IDX*i89TIHvx=rPZv)vQ zS{{_quz#+9XKMfc1Swz0{8N@iq-GK*-6-B|cE3hMK?{eu&>NJ;Z|#ccyms+Wz>}rJ zh8jY&2nPdYhz8#F214BDKPfHdHUVs`on#Stw2Lsjo(*euo(*9E%T<%SqAgs@kb&8S zMN&)6;ElP_ME7e_GacGL(DUgYs(zm4kw~Q}?%uKc5xsFS2n=cZ=5&*NM7*1vy;ve! ziz8PLg>?OCFg~40#o0m34sT4@DU)vNcA@l<s?@z({)Y7#a8v$5<~`MnUKhbTWzPlC ze$8rE*%Um)z0jDNi$DU`vpt<Hi{ET2+OlB|*D<^U=Y4WZ<1Dc~@ldKlY+}yQ=6lIT z8>J)EyH>_-MrX|cPd#II6w&!lg`6LO95_h_whDVJg?_BB-%OKlRmY1Q@PU~8Yy#hg zCE!G;->{FnF6-NV;tQc#v6ieRB@#IoJjl@Db;T+5X<??(gA)-sq<8kjJxA5dKsRJl zMJtxc@QH-|vaW3kXo6uSf#}e=&aUp+TfMhZ71Vu<qeXsqaLHEpDq^jfLe~}<KuCB2 z|HG5gqa>&5Sg21291<AfFer1_WK+QrPS6EC4wyDycxRMtHQ0Z7oviObA&iAhP7}x~ z=@Ag}AhSSjq37}*LLGFJXWYdzwY9tpRGYsx(Z$Gq2jU;*)PJ?@^Sty`2GVQ5U5ZSn zqkZlRhu-4PB&Pf}-{(>Lp-L4OsMmM7Y*JC++~xC|KIIm{9AnYf6e}w?s-@oS(b|-) zFB*Q_)Z^d0GE#|5y_IS+wP)IMgF|rCYcbRv@Z&^4x^}aGKBYyf)5-7MBZdS$b1R;l z^eV)7U0tlF(rCVDCqC<3^5sKaxSGAuC#yFM7}yP6ZZ3=$wVL)0^^+y9!cLb>eyFPE zA4eKrMgKZ;bNt7dn+$N~=7RXCw<<IKC3c-9^EPmTd0%YPBN9Oewoi7$R8L;9RkE)V z)sd_f@!7wQ5#s~y2NXSr2R~AJgH9z`IaqnSdN?<Dm44ID5?I$&p#P8S)(YaxXhi&+ z+$c#YWCSKrb<vY34t*ox_@YvRPtyc#arBVIOiN|!eA?*T_uKFA2w4FeCZcUzyvm)| zJ5(z)ek&p!U;MocB`lfkC9TFz4opmLRFBvhZZQ>O!T7fi4=sI>(p1nP1mukbv&>{Y z!9G<7)T0^V-SpWP87&IIr3in18n^OzrMzG<aqMjbag<l1$q9!LKY`B4dvq3_L6(!% z)ACCz6dxcq+eXJ<sd}Fef@7^yhS5&ydQM@ycqJqj>F+5S`EL$&QirM4E~=YzU|)uy zT9{X~lI7}%t|VU$0P`7_n$tH>`wP|b*L)C{xCc~)bLs1!&F{jqBSeZ-U8uIroS8Ld zTI0bRi%u2c?K*7Beibx|Mud-`+Qz=xk|yK4JKy~H?h7|TYMCuDG~Xf2RP!h925WS1 z*$Z=lH@2W%_bwR<SxED<-l(4-uL$wphzx;-bdL-tZD;$N7Hui$f&4b&N5}~*X@-6B z-7#HNi?|O*&i<z%iSxo?Ga<z{uH<F_H3v1L5nmKkeeP7wL$o0<YBt=TC&>$cq{JVb zuICgJW+P#%wRE}uJ(=<}SrS*LYEnMUeK*K<4`C(2+_jxD=u4=3<MrD;s;ua+s}Br! zT!5s7Y;5~KRtq0^b&a#V--c?XDIf~RVlB&anfp>=dJ9FodS$Jq6MhD_LUN@bHG$ue z(To`T8RloX$0f_);gxs%8n!c@?)bIVVm6h~BO6;~m+|4!N`1H3Dje-a(Y-jDOYE*9 zUF2VYd}>w_nGmq&Ex8O+BqDZgyl$K5dQ;McY9-J;i5pKPt~XWC_5;L+dXc8VWAtGW z?{&!*5om;i9u~*JLwa7z+Pxj|Mj^#tj-e7>tP3L3yfg!aUbn_w$9R2JDQ}WbqCDq+ zL3)rCmk+Na4xKP*ieG^b&qoV8qLUXWzqvNpatK34t~*_Wiq%fPGL(3bc9<P)c<$vn z6f)j3n|`iBI-Ju7h<{*R-M({e!|7w%(P7O+7=hosbEEg>@bMga*;)AEj643|id**d zCtDBv(k=q>>;N3Bj9-O88#6a~jS?JIMs6%F!Z%LPWY_TpR}K9lGp#6nCtFXvFS)Gh z7I=`lCb0YFDUQOwfq<B$cN_Bu#qnX`*jcU15~&#`NQBU>f)q-;>D^I`7*%eyl=r$o z1U&}z^eF3YQ=bmh>#Dpjac0YD82dm$^Y@6^m5{)#MapM0i|%cER1T&?S#)A9Eu?LO z?aXkt&64R$19+Eb?8(F{-P{T(a5hcF@8E3s7lrFvtCy5~^m;G~4%GqkyKfD3CKHq+ z%{jK8mMVRtIH^Z1GW(x4W4@tWtWGhEzr+!WY7Qe1vq8*b0vNa6%;sSn-Hkyg#s9Sf zjjHnYT<n9pS$q)JO%p#{%7hb#gB>E;+M~3(T4M==L(eZWwozY<0i&~)LyS#Gp2hh_ zzbC_7>QF9>r7u_4w?a)ez&=1l^1wIh8#+e2!re}oaQXNRr>cvAIerV{v6UDvMDMhi zkfa^b9=c9F(DS;?H-JCXRnViVgCCDW?|^4**OPS5$m@8Z^u@WNHh#A<FD#0SGg|mA zHoOsf4_vOAOW<zP+GM8M%tqZZL2$Be=6gqv@QHU5Iqgyc>5Lx9IbA9x-Ayv&?T^;{ zt1=e0=h=TgpT^yFmI5Mbe}LeEp?LGYZQhu?l)d6zVfuA%dVP|Y%hpE9hTR>FrC(2} zvqdk!DA>;XlA5{hGbMpHOeBW=Dd>F#Jdsydv$6FZ0T>jij>U!5O`UzgD2%T;!L45C z;U2m6HL7QWTSC_scPDvajjYPy9tnng=}L-+yEX9d_tZDv*dCs($&+>P=^g@J{8Y1Q z-(SFdWpM?*ku%TC-|3`w`06FHAhSMIAfAX!kP8Gvp)FPLpxH*1t*5P^R4Wh@Aw8$i zVW`8a>&JwZg<&O1^HMljjLQob4}!5&8Sa`5aW@<!;FQPFwvf=Um+4+)JwNjbhmIpX z+n&64|M{;qq^@gaxJwf)ok-N?kmP&>f@)yh_=ii5MCx_eW%|twwftxV%l%hvvdWFO z_G{`$oY^wb7u$~-AG(qXw(7l5tK4@}=77(B*A|QcDjlcwaVe(N&CbX8h*d0@<d+=7 zoQ_p0iz2Vfs+=GzH%Ih)+XhCv-5A1-f3)M<D}D9u>Co>rp4}Hcb3H46A5zh8Tf?u7 z$Ba4eZN5oQF)Z~*>O4ksY9CY^?OBMtM1J<%rdl?$pW!#yuNd!v>emf2Iz7N`(%s>y z@i!Q<dmC!LmqcWCr7f1hP;eZSNc~NZr@tje(OOz;U-(r-zk`<5K$2Z{{<9LZ_Iym0 zQ&84wcG?)T?tO`M$whdkKV@N$mul0HPMZDIZ_96j$Od|jQjuX6JPAsX;|E)fcnlJb zra`E10T+q#4s6+x+#L&-7a8Zp8!`?JAKS*Y4C;7NV`J-yuezU**-N$&i4x~tAU|*M zO3n95T(ZNt%#|ksN?2<0C12X_jGNo|N12EGcTFu|2i9mYv&{$GvPOws@nSA4j%#l8 znj&?L;;}9lFE9Ies5M?Zk>Sx|l$+aNZ@T~eD1WMM6ZfE3@SXJqzC)T)TQ(s!@lgFY zO0U|HwZ&=}{L%K2=BJGZtGigj6X4jS{6h1i%cQs8)9#Q4U4Qj9=)%R<meOfY<>d0U z_Ph$7UL%Tfe|VvI;_Yn>jXKY(8kSVAuV1!_x!^^c9~M+>amjr%1<3DYf?yvFl{yLw zX~?qI9PL_LR~<(5=G0&%#aSh%-SYA_M!FBMJ$pH)p3)5Dj@TVyy!ah<%<_?c#N)No zN4C>pf!S_sdYTY>>?1H8IdYT{hB<UBm%NyY75tKlJv}vl+oMm_4e{sg&cJZgYvP?O zD-0>|S}(x~(s&f(#=WCiZzU;a_GSN^`k&jA8<Hm&Z<77U)<j?K<n_iY4Tcbow#v#$ zQn9+8_*M_Z?50ltan_d``1<za1B=Hsn1xf^n?~jqv_rXrqQ|B83t*ih(*2#*oqX`* zSSO-&pKDD3IqgW_NRM_|w0P`{Q88KcXyL=Rd%uCw%(hL|GyC7ZJYk&#4?+$qtPY2* zHuiabu?DBi5)3CVHO`K~XCr!kvasN9D9GV@_<O1*;D+RQEn4i>k;FVa9L$<&a16y> z$2{~X$0F8?%J6o}23mB>@z*9XIlJ39tL*Kf;P?~06Ii_Wn?{y~(4uf(Lz>pM#dSkn zoF@7-9|ob6J=rM669d)XX&~PCH|;mDosMz-ZhrXY^?HZNb}Z>R5Ic{)H$qHha@+e9 z89q}_h+eDmf;8(J19oHMB=v~Ap>eF->rJJwaNI09g_CJod3{4^3;vjoF6lnAVes4| zTR&F1-P8K$v7Haa1vh8QI#FWzZ;A`shCkCwjM~{tvL=m9O(DG(d(E-L;^Id;a0EyC za7+?bZ0p{0RIgHv_-VZMeUr*a&eO>`5qoLR-MMgtdv}2J4*d8r9@TomF}M8U_I(Y( z23GQUo{g-}i}>K6VcW~YQYY)-4#E0cbz4Rj7=EU1i7(0+(OXli`*o~A46b+wtj;Wz z(;cVKHE+yyrX}4sq+Wb=Fx~J<O#5lndL!i0s}qmb(!)+KGpXsa>O5<K_d7zuK3?@9 z)^8SfJ9hVmcCct;&C17z-sSc0pVmW<Nsf_5^@>mZfP7p0lVYj0TUg%<4NKu;H4FeA zcc(E1i`QxyBC4xX?aKXIy5`5}T2YvXw&QVuhtRy+DTa~tr?tio;B~v?5*$)u9_tTw z@9L<X4|D5<W54fhY~7BD9F_1g!(zqlp!F$}PYiiZrLf8;%xVxN2@Yhzcj)4bK;zX2 z)cxeV%9dyTImOXn%c=FdW(PFsUXrs`c*r>#fbfj!n>|{hrWmK@yXG<X<82BXepFuL zQ`^dNsgd5?Lc}fsE4sL~n}iijE(;vZZEqA8KQ%FyMv1(F`_mg>509XEMQ=Z3xpaGY zBX)Zn<8r}ir?W+s?RYP(6oh7r==6SVt@jRitX$(LWL{|pC(zihg)lWrs%)8%0D%-< z)*SS@e5;sVDO))-L8MeSPPt_FCXq|^r6KQNd<ze*XfSBK`4XMCFfkd%7q5y&Hr2HE zV4p~Rs^z6NZQ7JA&H&58wOkpZNAza6ynO3V+EGOn1zUC4l{XS-7xjd6G(#2CDDDsn zFT2~^ZY5vet<r#0EsU5kyNc(C8%gh<g<EVmNP0R#Mu}FDI7#7`^ufmT5-`#m!?@P; zbnr!Uwn%;Q#g8F}(7y@a-oY60LVCOKXlg98aAdD7xm=pn8L}->ONJG5H+sA=X;1Nn z;c2hxw`J;CG5+znX9_#;p3wS1ix5q1PeHQk$^;h?z9JENoiVQhFy3qO)_TME0m3^( zq5(-ZNoi=VtFhMyrE29j7hhkS;tLXb?JqF3;9^v6nhrj&00nf)$Ik$<eO0xIV^cn^ z%*pAMoRUg?Q9t#hqWQpJ?Njo+Z^wvv>!dNL&+|paR6LW{;Rs#3#MINZBIy$JAscCm z`SCNRey9k|PO)gGm4l+Qg}L*6J`oOKC2c(FXqyQ8?iAS(9k-tnX&>#Fc>5S(g(pu3 zGX@)*vVf^PK4N^edQK26KN$@tOX5n3?N;F+P;~6wdL&b)lgLEWB$?O*v@&P|r?-ZU zZD`>p`*82ubS0k|79lsUum-oPq}trHTJRnkyfu5h*ya(rf>@}@DH8YL^;8555%T7k zYEybF>7M@Do#l&$_-enRR$RQH5hT?&@dZjYC8o=EPItE2Y~kBZInI_oILfPzHO?DX z;K<m_7p%J(t|LC_nGGfcZGLfGOF_^_dBEvhXJVG@XzrW1_)bUI6?lWI3uAQE*CeDr zmt{X;W|fG|OBou`b&DQG6wR*B1n>_u6jmZ`c{q5``DHgA$=Xy}_`IJMEH*4b+wF=t zJhe8ik7$W8s>hbgvL4v4aR?NH9VB2mpEpeIrwDIT(yzfc=JbjtoEj=**w~L9_{L`8 zC{3Y}&-OLDxMcUl41>bf$#44R8$0F*JdveT8E{-W>kCvep*oL8Rr;T_)_UwT;7&*J zPOl*Td{Y;4A+!Rm{FJR#@AlBLvP!n-NhVOh!;I%UlCbQi+Ukrs8J|}!wjZ?28{T0s zriDDWRUzB&@H7~|`X=$JqQGJ24gJFku?GKoksX)Gh?^Vkx9Y0XrO?PZ@^P$6qNC{J zONt9sI3_Gdh}xC}O+~6z+3czxA$nT0CPKDRSax)8%!|_G_7Ngx$L6Ppv~f~d*PW6q z-O<|U6`xvhLp&;+35%+gl?69W3<0C$XX!jyl$C{;{+vAkfiCj_Bw@nn;3wNG*zZ3z z@yao&8-?oB)07X!`Hl=<>$l#xGiE;~Umd99k-j3W^PK)*#minev=Cpn@wURYV!7uj z$DPQF+COgI6BOP{^B8x#1Uo|5E5Fbro>^Qyr3=3;^c5@i`K^TROoY^A;|t^1G<0bi z>oZ892usZwpOc+ox_<W2UU_{|e7`otACOuI<7ucNX1dY2Y#VMUCGKtAr6qOvD*GG= z1ZwL3Ma0^Kj>Zgpaiu@qc@}Zhs(B(TF|B@xkXHz1$q>KoWBUp;QgyNtYldY2zPbAK zjLtZx!(4v4=lJ4QPv-m6tKl<d?%yxEw@6(`EZrtRsA@1cpr#=8UdP)X8qu1O01tye zRSLhjc%Vl#OHcD>fn66Xf6Edv=hghi_oVR;eQ&RI&dz_wwIdrfu#X@lAW%S;iEonM zN;P9%@z!|b5l<s_@OTEl(&a(YP^Wlh7K@t(pT<L~QJd@Wd8Bz3nrQ7U-kNA=_5NE{ z?9#M1n2@g$>3LvL^%6bp5`~i2&i1?ZYXWy81=K4dS_!eJB)(aO^DTLNn0}=hY$A_g z_VI{9pSpTsqkH*Y1yQ~CdQMj3CzXVdNLdI;0^=VaFWu68JN2^yr<XBjzO(gY#qcz~ zaWr{X&(1J@$vma7v0_3Utl`i#(F#ik6Lu%#D1oWR!x9qVa7mAJT%_G322s?gCA*k1 zUG;faZ>vB%32p4<309KA#^My#R`&qeBA5m6GpK1<AoHj2<AaK49nh0n{LT7fVFXx2 z_rOsrqQMpXLP->;+lm}!<Op|rsbsIWWw*DP5+YHty1hJ~VgX~7Q(EJpG-CQ=&<fb< zyPf@3-GtLs1|sRDS7p5+5%z*xp6o{mMWKjqi(^;oiKeNC#xEU6Yr?kDLueu+iXuIa zPG-j697ohn8i1vJ>IB6Nbsb!4vE{?ktf|{b#en5LKtq7$_B;BaXbPdMgPE*UoV*Ly zS~0fTAhHIG^qSaH*n)4^PTl#T=`iJ4QQ4U(0!6H91V}?{OXHE)ZRWJ&YVk+L()G-c zlAk{cIEq-O^CtG|(>IF4(dpGl@1zl)5%dsr{=u2N1vz>xt-@!0QHoOGV#UWAhgH?k zP9!vs&sJlV3?^6&J}z-mkn1d%U}CZIQ!Y<;Z<8LcP=wK=^_ah4k2nN1?V;`xE>}J( zDX|ULc;{B<O=eB!`d0MRzf4k^Oq!Muug?OvHvciDv0AXlrM=!6-2$ZK_gC#>I6a7+ zo0>_aMI%m6eNjKEN@TVg3PmGR1eXyU$F<Umj6zl1?QV~yw}s}B;SREyJjZAxs%^yp zA}wwAB2Svia2UcnH!$!UVPi#L&Bm}hx=ce|e529Pc_&kb0&F@Jk=I17Zf<f+lxZ^V zNTyC<tKYX<^i&nMx!k%o3NK9EfCt-e-PtSxGkTX`3nNQ+Yg3n|v_rfOyEK&S?~FK2 z=(dXuKz$Nx*5RW`AN=#<6Gou(0e_%wQwlFu^H6HGYA`&B$K(LEK5lMo-!S3`iRex7 zzl?;A4niFc?3u@uU_Fx*_7q(`=*#8_r%an3epB|{GSd2d6MFcP>JAx~u3m+;bbm-g zJ)qtCYBrvY9$sQS6=b^b2cb~_Mai^(PBv6bq~Rup<NCGgy_eqZ_!d$36T0NGDg!yL z7LdJDhTCFlh!=0Sg;#r2Sdz$7(jV@4_}SXu^YkgLK<*tPhXo@T^S~mS>!R?k@Zm4% z$E=(Acl3`DlN*|1`VQ&f)^q*8G3mL4t!}&{BY01way%|3a-@<k|Aj=VFSa^5G_QS1 zd#k$m#dJI)Sxx0!ySUm;O4@PVgApF1WZ3-26gWHYtbM_ECx1k9yXlH`i7Rt98e2VH zC^D(mSyQt!U*BW?k9kF5Q4eICr=}Hbx20;RVg0(7Q#n>oDbmqv?weLe0MtBzQR1r4 zh&rnu&8UICNej`+k=g8R$+72sJ$|V>-%-!84Aeotg@NqafCM~>$)lFJdT;Ku*b=f$ zg0O@{K$f+946YBWEiLv~!-qe2!?MD!*KK$9EBA!XRN!2WS>A5UO^q8sf(e~xppD+H zacSv`d8dK^XWV&m22tSVPHItf@iW*Y%W6?Yzg*YGZL!bA)s^X1M-5LDTP2sg%Mr+X zz7Dh@8_S<1a>csU%eRjZ-cKWXul0u;x_e}RTLVuzWTp2{j#(j_SXglT^GK;9I#xgw zfy@g%&y0&Jo>04jr_8n0Mz$Ze+g5sBkdnHqeFKl$*d)W%4V3f?HGS--y}sv6+>;#M zfy-_<>O%@}l*y>`puXL4xPQgL4N$rivRe>;Cz_8GURJ=ug}r)C<;ovglZQo?u6uQ9 z`Q+=h6vcXok94UA`MTOddT%|kL#2+ZY`s|-*ukBpr1T7p`mESh+2^bT{1Zqx81KrC z7xZkfJCs|iJpVEOOhI+@`ysv_Tmkfm!f|n=U;bIwe(1?roJXQB?}_{5denf!#p~K< zh*Pd%K&YLP1M|#8pTNKdrxybH?Puyx(0eEi$I^cSJ=1#Jes2M(H|V!O3+41X-(*?T zaJmlZT*4CpR`{>^eEOwRGm@MXGm7{@Afp;3|NZC;nsfA9JtDIh)<j<p&;KjXbyX<$ z8Bm8t?2)FR*KN<*|4a8$du_D8V5WG?pmf-ah<E<L=Kt9{<aF>?%lhLPv<&<3YsQ`O ze-3n!X9rLsG$M-s&>^-ii1EFUi^_i>rQ1SU^$aO95IhzkC`LWwpev<v%1dzTms{L^ zWyakn;s>BZriqv**$r|I0c|gO`Bd;uKPjv4E;@0FO4{;Y9~?{{CNG;iHFz(!m)5@! z7C=b~iEKFUeCZG#jA>{AH2>Oxh1OT}@eV{Vy7D#JE>Bjz@o9kRnGGoGJuL-qYqc>8 z!cB2^&PTP=sn=S;R>n+d|M=4PTgYwi-MNQ_IE?#l+CQ-;7g1{!UL_J=odktj$a!$P zr-Jl<PY@Z!61Un)1IB2ugDItL|2fuAi`$uuB5@88mlsdRhh4Daeb_7F*J!qVSX%}( z=|Ld=l*ohcPx7G4cn@}thsXBH92^<5Hy@M?WO$^qm2VYVaL!f<`r?~qUd-%mt|WT< zoXJV*xU-K=1)F4kNrDOYq`}V;(^Y^cc)l}<e7ff++@0}A+-3vNdXC@ECIsjW;a|p6 z6xIv&>e@81$h!43Z&$dGr0{cZE&LhC_<w<9@<>0XvL!`WK9%O{X;n>Hlwi&K%?t=O zsXNNC?*s>+fyBR-@6)1v8Ji|eA?pYDtC{Jz=u2*||1q;a2YDu3_$H@n9gOfYufsnv zX;&_;hcku`)ER`D%>EEbJutok0>yR9dTZUpG8m=*az(Cq`iM|(_UJ^|_1krYmqRNz z&A$E@=!(6H1t-^DXAVACg_Y*|oh_6CV7q`o3BCUW*Ae4y@#XJ1MBymEE1$X2G4}0Z zfYWtGHUC1@nVtC`z5RpP&z4;dLNdmAwz(rOvX~6);{axttMowYCA$r{W}zO#yKX}G zI=t!i|FE<;>zZ*W$tkj;Lvl9;M|ns0f5gZcWXme>u>`ULc4#qo@4tH3+JyHEG5NiO zklc+tqn316!QPy|=hxqaC6y=_yDhx|Zz}ok?p?CPvf3=L3|bZc^}Qoxn`3o8{LsQ^ z{4cxvANY_!BcHWMkpiRp^k1XPI6!be%(Be{6Lx9*2bSeG;Q)^sHUAgnKS}2Q5z}jM z5aTb-UNcWt{f~A3hs;IE(LDbKCbW$?^Su8Su)kL0z#<_0KhW?OnMe`=YAoTFgKxwU z;^q#8(d&gX4&5=N#a{)1+B?urmjg03+LAZXkZqL?f1Np_>7Ti0I<EuG%Y$8{0D&l? zj~6*X&$GZ;zh1Aw&s1-`?o4Dl=uQeQ`6k*b@J)FeuC8kM(Y}9|JpP0L)YP(s6(w&P zSc7wwK(C5wQEb5l$3p?_)r498*Nf9LmDaQz_y6BR1{j_NHngH2%Rh+Z12n%vFe@Xd z<HjB-{)2Een1cnf=9~;m<zUFR<L#t6MY65J*C3>^xIJP}z}wDU6GBj8_l<{28}Kz* zgBm78G2$7C^<x1q-`6A1tV4t{1Re8_rl`wGeYB^@Y?HhC5y&y*Ey8kUDKAr?DaQe# z7_#%vrrNPD`b^Nsv2@-)n@&ITQUIC)?kgE&@t;kruPF4TpCW@6@BG>Hn|4npnGS?y z7@CFES3QN%0Zt}+Ya|s&FF=J%ydJD1(K4_s8Y!i8@8$C~_}cHLO5K2uIJaPSQhY98 zsvDA8efC-qUu_GKF2(^XLwDy4f~h*cG*k;O)^mmuvoQE6vJ6O}y05f90B!(*zVkEq z+k&n`OZHHvz7S~!ukMU4Cl;Sn)3i7NfbXKw$j$_C=kwo7X?oU^!h0AZ`WY5w+8q^t z7v{C;^(j!N{Ujf}GYD1sguli22c^uzNI=dBkA0;RCxGXXjjm$7Ch%y=p?mEXST8s( zIs1>r`$as{OTYu51=|?~#m>YX0xS&*xc&1NNe)6)O~Jg5-w%F0?Bd;lDTCq^A&ODh zvZiJoz;whZqk3y0r*!@WjmzuJ!>ZUVo-@J>x&H5#uOQozK!Ih4Lt57>P)(&+aqhED z#D3HLpPk&5J(C%zGnoPkDB1UCA~sq(KwKVIqF~B@J_t=B^VZlC^Eva)K?$2*(Sl7s zxD34Wh@|oW44hespv|?6cmwYLd1l3q^$Jcu@HqPnWHkP3Ccv+`o2$QA2#~l>`=Dnw z10cdbq=C=09`Hx^5HfOR<AXqVU*rA&uSbN{{?$9E>ij8CMb>xgXMg{qrXlCa3xczj zTGz2&3K0MK^~H2u*OSlXE29;uqVFA$s|S(heoQ8jg0_(5iPLzCEWR42#tjcct6c?G z19tCk8_a63@3YS$>I{%n6$KSYI3N;0pfs?dCB$B~E5*?NNTs+9bw12{tvNg$D^}ts z(HGpKgIJk}70Al<P8|7Q>)vPAte(x{kx7bnIgo=leC_j~J%eHX5W+GDmGzmQC?BD- z4^Kch^v%c|AedncYiIgp?RaLzo&??%H)_e$Qr@v066v`~p|}R0PCt`Y0guzqhOo^r zrrq2LPghwhTnsxz*hD><lDtw&;JkEOSa-+1Q}@*6fU2lsT0F_i6f)BQtUX|T0qDsF z@>qYENtGXDU#id)wYQxy2=er8SKNlzMhebA(LXBP?xMRKZn4_7ByK<^D<Ev8M;3x< zXBZc?JVmkq`?`qgW?ZdQEPK$__SYYyg~@o2%IPB=`xYm6;c;)y9N72{yq;iseE9VI zC1*RHi&^=d(_T5v%TNH2&4V*~aO^uk0DBa2gf70cBQs-11H~{{k^L07ub{wf)W7lw z(W@FoIIFP3BHo#v1wJOg^sPjny6AGaC4s1b&zrssKv`cv3U4kq-D~C|6Y@LSN<HU2 zX&)Vz&9VwFc$-?8+U53^MQ7+$_d2{dLt5Oh&tUY{=TBKZkP3qP002;k0;J&tCpncm zNWMOHTD{XlX;KtVUk)tNVt|MHq@9w-NSWM8YFpgt*pbYBVdIxyWbD{+Hf)!lr*JZn zk)-e0PthMddLS(Iif)+0OG!r&I6c0xx^zaG*<7cMaLROVUCPU=n2kROmx&we6^W~x zoKu)=7f!dhQrRepJcaKion|QJ%nU<EeIULk4S{UH=7R2pBY6K2pA-J!*-$&4LK-@7 z$t7O<cWXU}>)bO=cdWM-hL&$H7*u&@2!5&ZQ0RnJ*Mg7ZJq_%JX3QNYJWW-cY{R2% zG=m%LCVN#zaJIjkK@jN+NW&_w&Sd(7lWMH4#O8K}aD%7&b|c;R!&9fs1B5;QHZ;5W z_`<9Op8fTP-PhR)gGwb&-C`4_8ulaoV8*l2TzvtV8HXl9&F<J3AN?XJQbm9t<1NXo zJjh_@&zjJk@%rgoLo9PTSRP_QUvVsTm2YfJSN)6?o0il6V&vvi#*x{xFV493m+uBp z#>M|vF|dRuJZ`u^PHtvz>f-8bW^8x%%i)zZIk|w?b^hyTzwYsi2?z-M{aoaa=aQ0q zYF>_Jd|FDctj$bZ`BdFrxt{(1%+A=tj8D_b)YbC3fY?2LJ~=Zh3rpAQ0{o)<e2=VL zU0#|wKX$Nlbg(zGcfBskr(kAp0W`hG55QF+=aaFrbv1M5ld&~+HG5)a;$UjV_t?SK z!CBSO*u;$QiJ7~ViJ6M*BXVhJ@;^rGnY@`o>U-G?7h+iRUg&6sV!>-B)Ekk4m6TH2 zDMD~nlzvF9zy6N%Nt4`;)DY46XXkGRUa)?&n$q`J?mE#U?;SgQ^p2@;sf6HUX>HJs z3v#ceTVe;@E3s2oi|np#yr}g5(e_?(O=fHO=$>(`h^UAtO%Vm@NbgaQ-lQ7>C{jX5 zL3$^n2ucSLkQ#am5FijbsPvZ5L#RscNUupwoY^|F|L0tsi*vZhkCbnH?^^4v&--M> zU%1NtIwR+s%Sz{dKJ0(5UfLzJ5OV|n^`a8q(-+}QcG=v8{QTUHE26|WP)U|lb6-ER zU)R%KpABnU$RPrlpP{b*Gp^D(nVHSMhDOxxKJh%Qj`aLybLC&}x8Hn2(7_;uYT)<A z=F`&Bm@PdY9bt9|ll4AY$Rws6{tK3h!T*+Y`t8B^&e1{!JkQk9Yc7!4^4!IX$r4a} zjGiJXQ;lH>RqwMOH~dkh9QcTivku93{$HXuWB!_^%Gi@K(4~tPwbj+5D2x5sp{vQ+ z)J{BbG%NMo8re|e-?Q=${7bxLZtuBR)6_qN>%M<USALrX5ET`jz0cMU$kk4`b9OF@ z62+x-_RN{Y0Oy0{@~i)vpZW8UQwKE>5qFFwq@;)lQC^)c_7Ain`?e0GVxFCNnS5Q1 z6`R4eZOE8CHT%{xnmDGGI^s(u?{{67<>FF4!j$J!RUOc#8AX{awSK$v_QS)77EUr} z(FaN#rRyQvo6GweAVFkVk?yve&QHOku)o!E?_Jy?R99Dj9>^h?^hRVkokjV~CrzGv zPeB{^G!zw8KlW0@7RIA|w>0uSG^nu@8R#&Z3_hqZZEmU8K+{XM{KLakI`~%<6Do_- z+4PZ1!E1|X)lLokr#lsR_b$Ka6a+AF`G%dqf>ktT4lg@o91k_O4mfdjsnE?3G)f9K zD6<;qsuo8Kqq7dpN2GbZ&ldU&t`AOC#j?0KeO=rcW;HSw8qiI}fgWj0Be1oBP6Q7a zcx)-jg=kqX6q^^{I3d}49sET2*J_SfYw~XqxP82<v*)lKwUomKj!X`!oil9-`>!@G zEUteroR>WS!F%rgz#jVg`udTfp`kuIi+$Nz%#iHWjDXj#vl?kzZI}Y?N#tr9kK$3M z9kEYa+?T8Ew?oBK^Ypux5_!fL?=Wo-)-f#!mg#}uODJPjx4T%|(gGcW(Rt)e62vx~ z@@V;kRdUW!Z~5?`GxLh}&Ls`vip*^#dcBY`{eeFcac+$i9H@hoDMni1l-v@3IA&~~ z|M8eYik=b8T7r@G2`0R3%Zrz$7f&$+OuIU${oJ_A7Gd0k{0F%^aO0E~by1&3ib-|0 zu8}FYdk;^h0F7In{O8Y~@4sbH<C-7=jabc?lV<IoGGKw!@904cpFdA4%$)ngUWUPi zrf*7YIX}Gxxt)`iJjlAnE1<)Bq|_y!-Y?CMelLDn?)CsI!I&-y4h@iGgm(yqK51fM zF(GX4?w26lUqlosOOB|TZWbWj{gAtF;5=k3m>bS&hl&4GC4B_`xgX8?Y^Xio)<bYi zs>5D{ucTMk;%HI8v!P-0TQXl<XwtC3GpnkqJT@lFLgOgwKkO{QV|9cRUQc6`W$!$C z^vGaZ=;5U45hf*5G}RH77isgXQj0h$;fOuw|1}Ib>|*Au)1RzQI#WI3?$T;EG~W<c zdy_5NPiHae+z^1*ouMb@hrl=}e(lzu#<ESt)5g@*5vQf+iY<HOBDV`k+cOh+!N0kO zWFonLx)8Q(w_|Wj_RGCQU&%heSYe5LcC}W#5KUS1UMs)7)Nw`91}&f$9ycX_pFBbH zC%`9NrD-(1vAF_2P7{ylR+3mg&g6cUo4c0i`ynu{{|skuR}Ug3i^=^>nk_uM06g%v zT2_tt0zl>}TNz<zO84ezQ6R6v$O`PpCS3-n#dC!QH?#H-C-i3{x<qBm-K=zv!L{Jl zwD;Z;B_WA$ahFLGryasiao=T@dsATs5HO|#%t*#6PzBB+<CNj;uO!@QD@oq`LMPn* zO8V;6tFuy9J1>l~A(i9$`={Jbuo1Th5|$liSHe!2KV8fID9}X0NamiAqK*a2)akyx zjf?q&PraTkbG2_&@JfLU@18QnyPU!iNrlzE9cdpB34e9~mTR+}D1o3Sb_tr{#>*oJ zOvx}Yv3JUSI(>{Uf|BsxK%q|ef=jpT`ZLpEMQ{L8(#vBWdy$NVQ%^eiG3^+3dDq1! z8<X|fKOAOOV-Fs91b*@)s$7GzPzZF%QW?fy-9I&R%GrK2KjKfxW7(8HyPVx+<s|fW z%K7xch@u9+VW!tT%UT<PFrh=R*6i$_QC92JXp)S>Qw8P1(<O${MG7D!T!Fn}1-B=< z%6W++v%Yxxam#A5{DO$A(AjxDxfN7w`)UMv?;+;*p!jmDGr0dz2is2ISCkBuq~`!F zj)X<dNuAfE_O!Q0opMq~-ja1yx1<G?NLpO7zg-kP<Jiuabr04yRRRE;sII&>p42QV zF*;A*^o36dZzhc{$$Ot2j?2G2R|pS8nwSzr*I)GwKI`hXNCdzx|1r`NTxCMP`VqPJ zl&k=tk{nDGAPyTh*q8Y@lBlp=WLO_tJXdt0#U>%*5AO#&IA-<n1|$y1Mi%=S!KUvQ zO#;LySn8lj-aMf3`xm<XDI_wILt!=#FXz4*H6?Z*{yxC5{e3mf<_y|msJv>g;-dB? zlBuwjiU3&+34^DMoMzS{@UyHqCiv6J+b-E_J=5^f^wZOhRW|@Y4^t17JggH^!HgQW zL+DYF6-}QIaRCH3rW<OV1rH`cziOV)uZX6c=e2fPlf8~?5;6U^H!!P24qpIcc<qnC zV@z?m4*-X=F$&&0Q9W3;Az<pB?_zKIn>T;B*xQR)7~NnGWoL&3SE%&g=jP>Elh+1k zD2$woTro2G!$J(<dmAU#i*ORzE9YiR@te4w&cW2HJKWep#zs4Nyp$|+GTkgix{JqE z%T^C;+;SxV<Ro5^EdR%Bq^D6mp1GQ-U(_Xh)E@ctET#fOtNl{{C^L@B6;FC5e4i>v zHZ_%-!lX^D>yp4R3dH=!uPTZ@U+nTw(voFrc}i^wa@Q<7j*zeKUt0mf59sz)@`n1P z_bw<A1{>$d*v!_+YL<gZ06L<pZ=Y9o4pm{A8ZIy%L4{TRA3l=mYi9+b`SM3Tzy+3} z&lm^j9BS@zZ<#|}u58yf>YnA3C~6#+W4pWAD4OPql+M-9l#oXs`9(s$B^1`jvVA5k zl0EyUWHA?AmF&!hie#|mL!-c&)@^t8vS1v)HPegH=dlQGoF&@6(lwv})CD+{e@bi_ z)%QuGaO@HGyx&=+N+#C=4!~;O4Yo+!cG#n{Iv2VmOUYRpE?W{EYbKxE|7Y#WHL0ub zED?~?I#d`D&~;%{ej9k{4?(J6Tc9N70Z-flKnuBY1ZGXYkT@d^O^J@xAC?tvBF+FC zpY>iDgZx=>xxCX%nA!NM+6AXH(LK7Mp5|&I*YYab`ifgl0#pxU$%z<#=A+3@?~+~{ zU(fO4V=k5E1lw$*RSo0lC?p%w*;RM%u1lHmvGoG5Yid;OpYc&T#3adn(~UhvwE)ZY z0;oCQtfod=@GnZ|NPJ1TQe82qxj$JQr~-r!aYQX7tG2)UO*u}9cfwyaWX3ifn^vYO zxPE%pcHn==*Z?N~Z-LC+-oWel`3}OC5g7YAj=Hjw@bW)3cL8sB<^<Xr<^DtxBYq{t z;NNx#mrR~U6mhEg#5FxidZu{4ZCa!YJX1n=6E&>r@|}*lRYx)VCud2v?FGnLTK#6z z0aHz7hDRI<<T|ah{Th!ZjXLxVg%o%}tNjZ}o9^`Z?VkeD<{Tx)jO?ujXZ#bsek{Zb z){Vt+>s<Kh+u8r~M%3_IVpwtcIMI4=W=i`~a=n4s^gi1}igTy=StJ@BS|Rn*k^G3@ z$%38(0NS@x>#y7;?@w@kdxbR>8Z80%6ZDaJMZ{6mzeP0TSKKGmbhS{I_i0&cg+byk z@Bi1v;IH`>C;op_Cj9?cf&4!Y?SwUsvGdz(apW(PcMifgZ-M?a@l>~bwWfOVrnPva zz3}dg1o(1Y*<UmL@o@I<dZwiQnsvsRy}QsB#~#@)+YU;(=B)jy77Z#b<7cY#zbF2= zsUDNT<Tln**MjYtGiq^lGVQ5|x`!<;IeRg~(QNYE;C$FlhG5_>ugAI(WNe^K5awzn zZ7%pPkNW7Z>gxeaSb6E|Y3izHgyf0K3^#K&!yg}1?!C850a8d$9!g>MD^Bm0$8P(Y z!o2@TFV3v%B)urC$-sanuO5M+0($Z8A|=67OW=PE4E?KwdNE=dp>Y<uMTo0H_?@`c zWYCf9BfofBmJ>HUsIU<u-O6;#=`8q3t$V|#qmEcZ1$3#5AS0CM$^5UOKtG29V~~5L znY%_Y%j`k7mcW30f+TdoMxO%rB+~}?lR_%J_-hGY{9RN9t=S5&4}uB}^E0_?a|Bk~ zFQI=IFi4_)v+K4zZmg1$*Y3*eD{xL)<|Y<;F{kY4@D72@u>ocz7zr1VEH@!uz=UYm zs<#l-OV&TQO#Z{fxI%r&m41yao_jU)!{D@0qQ}r$$fzQMT4h86x#{dj47R3^u5`B= zmlb{(a&wSU3bd-;a~@t@JGyMcE~Ii;+0zM1fkCp}!+SKBBd#J+pYfbv*UW&cSyN*_ z>&Pf9+h5i1#j&o_R2V0Zg+z?x33gS!@D6tQ5bV)uy0H52Kd`PB0$(0O$E#xV`#2(i zx@Naxp?7-B9<JOlt6ji5qqtXQqi>H5^RypHOSHjxUKQjds(;lr?TgO6t&_mVjjxF< z^exzYV|F$|Yv7iEYaU3=!8d(mt^3Hh%qNA`!)~1$W&cfH>JMPz3)Te#;a4e#gx1)> zu&W%>jS;lyTTwRh99zlwGf@XWP?V~tRNuhG?>6iBEx-iH<`hy*xbv>KI%Ax7s|$sc z{AyT9&gtVYy{$__af|m_vNglwGMrFvsS8+;16&l<U!WI^hQn%|6R+X#zRWd~b;H(M z5F1JBAvpg>X+Gvb<j-qdZdE=IS*#Uvg-43)evqOZ+*S@uxcCSstO_P$i!>cn&od-H zOSxhUepzA4uSJES|DPnpZlhALnyokD(6x^Ml%SPtXi4e@m?|QedG<zum@+o&R`O?w zdg~%S35l0q$MgC4$fRrR4=ul$*nn!?Nv-lQxi%iu?^0nO-9BCcxe?dwan_PIsuXJ5 zvL`0ixFi~$u&~ImGiNP#KXS?~btiPsH?kHI?WN3$9;b@!=iyiiONEG*_z0WTbK$@O z_xCIP<zEmt!>Q$kS#vB&H|-;y2!ULBb#FyjURq9+Hs_zX?pBoWOErey{sk5UnRVWy z!sHwARwvznBr*3{5y2VUXmSn2TtV*$Z2SOMR^hka-2faW^iVe@Lx<SD6ZrPwQm-ss zuQ1o9l~uZIqQV*QUR2mjRXKEAu77?MNdGZ>SpS|-&(*Sq2LJtT0)Qc;tI$!kLbbNf z!Pd^acL7BhFB)|y&3TZ|cb3OlRnkl##Q9CDK*eqhU8$khAu2Am+}s-bK1gkGI{M>2 z(Z<2p=`A!{!9O$hXS`_#zWXUX`H)cjEs_F^O$djjT)=*%%|=L#he3^y!WU`>IZ8S? zlJQu$QQ3V0Ub$A>`dq}}>M?r{Xd6|u@AOT*6tz2RTx1}w)m~FmGa;r(Jt5BJE+^_2 z^&!g5yc`ZOD5Rowr32a_+%A(*1}f$r-YOu7g$Om<&BY?kO!}RF7#~Nvw^~z?`z19; zDK{Oq;#h=|o`n3*@a3E{<1(;<3Qdo59tQYm9<aornHfKeUWRuaf@8zQ@upIj-&&o} zvts<VvyccraGdV-ODH*@I7Vazymo=eKYV8sCFoRoc#*z*=uEvo#0$3GMmy0NAdSqT z5C6<a3uRaYJ`8IV5+1UNeP*pUBv}S+1@}+!K$G-~WNsd#cTHdj%UlwB5_nZ~Ly!uD zrX)=y7kRixx5^7T>n}jjTbgEFvSvl4#v1S@SuCleUVv}fzGw&k>TP1m&%i3P{dXYg z)s|U9RkR90;zCCW&!uE~|I8j1+aVN#KoB*pHT&HfiKeFVk=|=epM&hmW!aXd+)vq7 zz0OH+#a4K&e@(jA4NctIu^G4O*|At*A!$8-kUui5J|2=<v_1IHG1g57)^JAeIIX#K zX6t)24f#lVy<gzZ_xraxP?52RF10ZFQJ3zpc>jUk+y=`Ui_Gp$iq4p>5UWk8hvDzG zwPn>yQ`g4|JKaRVCu3!)m-;>it8iR0ZGeQ^CL~JGe2(}ke#wN%Y4hcdyYfU5)}zp5 z^b~F~^4BCo|DNO%-RiF>9lMof#H>Zr?fzx;mhd^2wy7uJIdg?_iC*JM_X6Thh9YRd zyhuzmMEqMSQu1Q=*XHVh?#<Y3SEzS2J{d|jm6HAVi7zj($2a*?fz*xG&XT;u94mp^ z42q5Caob!6m&Dsq>7w&weu7J}%uRl@>IgB6eL(TpwYQ(qIDGZvUjE?*--HBD+@&L< zbf@~FwE_39&j#G>D>Z7Rlf+DX3p(pMAp$PFb}!IdBlaZ8QHh|~au<=|YH5FIZyz(` z@lrF1wJgN%@uMGq&JPm%SNxkU!Q6SX__gn$@MNaUpv!jhf~*(LMMp<RB1#Rf8F+z6 zx_;6~J?-eib?VlvwyQLU*q>{^(7GGn{?cZQ#0^fcBrVyKd{5ZYQz`7mdYuzAz3&ny zXsCEN8-EX?yRp!f9LxdH@~0J6ydYl-`kxNI8SwWi6S>2p#FE5_0O%anYZMEVOM<)b z-go*lGxYaU%<OQ=eon_N<Vk4@iz%c!IXFN)_v=g~kK>k`#IMLqZT=g>O%hSU!|>A7 z!juzO9KmiImbxGyxA5Z09~ah~?-n2#B*>W&BU2rmW<ucU8`7s3r4DLXematO$mzc) zWP5|N87+MWWxFjP2lhG<xKBGv!|Ug#&T&3wpaoJ0WP68Ujk4*I1opqCx4Y$KyNEh3 zL)W)Ua5xkocnR_Gy-&f)`_I$<{)9!T{1Q}2U^9JYZKoe2by{_bt?oDkc((Y0R<$oa z9Sz>7_nQt1RZRTqa%F9$<o=t>m={di%5mLgmT|2e1G#!Ac`s2eE-nQH@<^#Q1Omy= z&sU4&(9zJ4ah_EdmHt(2Tvif4(EM&m5?d`EnNAuWR;<e33sBw#u%nN~tJgQqvLGgn zkpsh>V|J_d)JT-yA}aJ8Cz!F!MUntFNm?+>)$N#<`S4R!INwMI6NeBOJmw;KqMK`< z=VQazv&ILF#RWMyT(Pd1!}4+g6dD;j6d?=TUwjqh<6&a)9r7|M7x_IHnW}P52Kq5y z<dil_(QmXI^7;AlV15jbUaGXy^ugxL@!s0XipWp@NK*^&4a>cng+|ex)M^q9)-UcV z=0`&Y@jAbmmJSX|EH8#6CI;M-0B~Sx;aV*!Q$3JvBgc(n@DJ?%-M+|K<glv05I;Y^ zkdP2<(>gkW-@W_prt>q-T~@-2)UCR0BstHb(9nSpXn_M1dhKw$_qk}}9=ZmHE33)L zsL3hG;1j7|$HQaUpOJfL;3x6(f6j4EW?r@raI~?rOO^N9Y7S<kEk7?WZ+d!q14qgK zjL++aA>TRC>!UxP>%d<Cy~8YYGC$_{_9DBiBjse13%R=a4XGBvq2M}FqUT*F=hyF8 z9jG!FYuu)Zrnu!%CYci8sY}YV(h<U0PLYw514W$pZq0V=?CcB<4$jWn{FB4JxeVS+ z>{D2vo+10IZtk<Lgzyy@8Vuk8)RT=yYC~PdoqKbOAYs7Ph%%Axdn6CSXC}LmLt9q} zQ^;3TXdY$kM-&=xI~8}(3}9dp&#S8&ue4j$PFEQV;rZfp(pYp-5=2YfRaILzXWD3B zjrYNKtN-)n^+jM;V$`S`54sawAf{`3f%8YZhWVK{WFStEcAEFnSf!p+@L7(7rQ8M| z2DYaxwI{9!1jN?%kylGh?TX`hfD(0;{mpOg9$CmeM%q2u3eycI2*BS3x64;hh6V<g z*kvF8Q$}B&7O)hn@t_~wHS&b(d)ay!yQ#S8P(M8rs#(0l`S|z}`#PDtF-83vfI_bC zk414#?Jw`5Of9Q-`n59S1^J5#1%!le`4{dTwUAOQDMJioY!_}=NY~cZh@P2`JG*b` z?xoe0sy)|qZ(SK<H^m4PT_ozUN13yYT4qtvCjc~Zf(!guC++g9f{Q&Apwz*3sdbwH zO-c@V_5YD_vacGRdh{*l(<xNzP^^hboUx?tE4;9P85=u!-DhLs<xIHABnCc)lbUoj z)HE~GP*HL6YDp~Y95acvJeicH?hs^kmT~+8EJn3_q9VN}=@B+Bbn|^4Zz18Uiw9XI zO~s2)>MBK}e7VCwQd1XSZ9ldIUvSAe1~2v6^(5LVUYXzR*NnVxPm)h!_R8j>9DaIr z>K}Oa94CI7J!Nb?0p-XVMPrHNWMyQOmzC9(@j1=pq}F@0>j0viwu~OnzQ#0CmRp#g z`BwPs3pX5WMXPZvjaP5KQhpoS#UIkyxxWxQRb95+ADNr{hz5WVhGhe}46W9Vz-Q-j z=`+`_tU(ZLT6!xttKmXQ`;KaS^LUL9gfE3a?5vBGqUIrkSN+V@p}d~8)Hai^s3hIr zuA_Aj*WuUkuM!Ul%U@}bNOEdwYFwQAZ2Oge>mKv>2t53FC$f^_o42qvI=yuP_^6GC z+tPQlWg*!G&!{JVxXFX^J)ZDT@b*1fw2q_^NWGNa0ZzU#+|0#hH3w$fCh3}vbAX&X zjv4W{sjDA0DpLBR3)waaIL17~(PhE)LojQC&oF?_wxJSB0j@O(E_6r=xx0Kk?Mf%X zZx2qv9o=V>xx;*dooQQ)W`_?xQIw5ol?UB>d9wm(f|1%H+`M_yj#`JL`u|&S@aFqI zzXIZ#-+PKeWpQ4ixk;~AV4%x<kI&IkE{)>ri?vzlO>dG}NaiAMep9<;yTGg-OsCnU z6lpSnOZ$343`*gpR9C~-szv**Wqi&G@BdmTrx0+09eR++CbEZ@HO3;{9hiGQpD`m3 z;B1*XPrzgs$bjw`emGy~+rwOXBP!hONko#(T7-#A?Gxp1GStE``&Vab$94%F9UcGH z5TUOUnLdt~-Tla7z<UdBetQV-eIZf_#KqZRc`KH`=}S|aUgFNQmayCENU7iPp5f~N zI!#ShvWv#jS&)NcqEp@4fS*}DQZj+5d<aSI1#~U0FY1Ew-AWPnEWQ&ijhdmCfi;#; zssNR!dTIVPt0ZNm5b3`6lC}w3`ZS=G>%!<>1J0t}f(pZ$%boA;$Qq8L;?_=Vxpe+z zZ2d}}J&R}RB)?I<#WD_?GJl9;j+GGN5!IWTDjH+=81GwqbrwM*8oNI{x492amGNHn zw1NO1K}dT8bI36GqNs1C)Ew4>j7@*Nca~b1)C$`h9HC!^2Hc7D-Ft@=a<<DTl&PQJ zIh`nQ$N7)Z2nkN3O%&4*TVAEK#RD|1EIfch%2AgZpH*k6J*+H8UZ-VvozU_Nvc000 z&;EmfE2-0cQ^-Fy!uTLZHjx9%`zZp#0)jD2uKlk940Cig4*f8ghC{n2PkI#^k0-RK zlzmFmTiV87(A3mpiu13p-b=q1yHF>dw|fMRS-Z>@QKd%m?F<4kZ<~zm_HpP(Pp+IK z?-DL)s(kA>Bshcqki~}5s_TM*0#s3NH*$FXD=g0jZRl9b+Ah700@+ira+K=!s!D0+ zNBJ%yz%!dqHdyn#51-%ux5!%4I{9Oi1Qd$RLgs$4EV@LzF{?bSyzp|WOm3QpT;px~ z?_a-hsb!-&KS*k5Svqx;WzOvjJ5<f1)rGsj8%GOvhXSA%6D{s0xP3Pf#tAM_jDW#S zd79C1<#jpBy98W470UMU9n@H(X9=20g|*rY0H6y1*4ZWd*zzx=;@9q-04Q|Y`2<`m zBllD}{X&YBs)Kl&G8h_@FWmaD%dC?hGzcIL4KXn@GfOM0s05Z<pL&`8_-B6k<}&qj zm!;I#im!+!K7SC<?=ISCue;y*#Av?1ipgj1R#XMHJh@vK=$&;^+P*Az29DV8jw~7l zB#nO{s9fqsUPsV!{f(9ALjv~NASBFTu?lI@rHB394W@+AO}d$ELLPtf`2@`Gv6jX} zj3vzLNV>anngrX<yYtN}Y4WpG7Y?@BJG>`cssKf|K2H)~H-o3znhgSI;<mN4s7N=x zI(0USePv~33H2+9pjC;sn6W)afcfTLa$|%5Qm!1)w;odX<tk9ROADc2S`O0@KDION z3E-sn_ye(i;G4Gpmjc&rRk!CLO?YU(f<;%k0DzjlnD&@?p=+H5f`bvjCuv6vxhGfz zf?JP(G})yG8TY5sj%dvEo7f>(e)@*Z=PqeaIKO6h8g4L)9kQI<AsFDVT)7g;d>S!1 z*tGt>WDiZkw$V(z>E8hvBi3@0t$X0up|Z!Yp5XVbQtd66Z0p)YJxvVL$TM@v5?Hb! z<&^i!)bats^SwOnnz+RHXbDo;#FU@NHmQq3@;fx2g-{FKi&Qv5sH^8xTFr*uQh*!f z%M0AAJxCL&LYjRAI#jYyVS#iP%mP#D>%O9-9GCS!?tiCbF%Lv4Sm=-Hm}LRn5kAKC z>QGTVMRrA`2pNksDB*YR{4fM*C_eKu!R&XIM#PdyfG(}E+~e`1rRk}Ctp*;EV+Lid zja&MZw&;6}tOhUJ(q{H4b(`Z0$X(+WnoYT<ICQNQ<J$}=z;F#Fq;fcxW;vGa=d27B z$9l|T_0skj;+q~nRS|Q)>l&1EXpu}cpZ%`IT2XF7`^Vs^<8FiG-c|&1616kEO*NPD zo_$WDH6mP>-WOPAN#KvbH}oZ<YcB{~%__o;7gyvuUsxd*R-*T?-Te&_6?vJqGRr!n zEC&-N)J?*0?oh(^H-ha=(}$IXIf9Z7i?J8}%i2&!zxcs2n4hD`P4DS8&g7_Dy;^ae z`NYSQHrazZ&4^<#^>cBjyQY0og6*G@wxKoN;2D72`+m9+kr6>t4eCbu`rwnIG>Z{p zJjII^GC`JW&ZZ7iw{o&_6&1XjpD#r=)U(8^QOahvx-NM8UcOnmGt<pT8#ep~!aRE` zTZhFs<)Ni5#GJ`1SD2BB89K>VWUtHXSdq>d{pk}NWUr#5gdAT6P^xb_4tJQgIo?gH zSRrp-{4cGh{iZ5<hd`;W67IxHnw1xM-eGH_j&+iy?s|_;`ZNJB8>KE>CoUM?c|hlO zjq$8o3?+)fOXHK^wS8pe3p)T({|PV;UwAXB^}IfPb1FLe%xH1n!cBzH)v9uRY|o39 zn`J``(yS-gN8n-LN+kH*e+wME$RcV9MZSIn27IR7j{&+!PfhN%R{MgsSl3<~bLrGQ zjNHgEvT;XCPw1F&kqymw$tejZt_OA8R2aXWPhyYV?>E5PS(b;-YE4#p3=xxdPoE~P zN6hQ!=0S$|sN>7=?%Rdm2{pf)Ii>(oIsfaNWSY{Ddu6mnNHV=AZE{P|4J%9fr_St? z?KGzxb9cxNn&u;IOiL44DrN(75rgb#%UB9t{=4gec`b#cK!(kQB~j8BqLcn8Q;38y zr70ce(u)-}mU^Wi5fW19iU0In=fv!m=P%s357n!9v}UwG+WM0X6UJ)GTU!uenSHWm z`j9`#t(N(hzptVvi_xAm&-@T)Ro}lH)Y6CWYfSE++Z#+N#l+>h8e&MLbxu0-sku!H zBijVrYrd`#qehcBT@5Ik_m>d>C_b||A;PJgQG=A6ghasIvrXEpuCR^S{f-ukrybx+ zA!Yp0<Armsy8i9U+Rja>uCfR&p$&Az>Wf^{m7wrGq}$z}(lmEzJDvH_o8KY)$Vnn+ z=&5YP%#-I*kfmeN2cgRB^>_Zplw8^u$ky}-3~ud!+6QFd6kvtaG7tP5H);UxM4!1= zT<)c}YIiTU!snn7Ih;U%aazIemPo{mtH93Y;rPZ7%`eA(9}O=ncLz?ev*rJ3>vab5 z%Mmxjf2hTIPL4KKiWe|)t9~Nu9^$Ai^XQ^t>i6;!y-*2_3DHV<1wgYHg+w|e#32ie z^GhXS{m}jzW{r7#L;yWjnL_ferESIVCaqyDin|nQHI_RnWLeP~S2`4${*6=y<CZeF zep(Y<kn^h}R+;`oEp%ymahgrh_u#TL?HmkRl-OGvtE6?u6@2zqM=PMTx*3FnkxHzT zeSJ@|G-AweRN7M68W+*sI(lOk?}-iaj(Z|Lo2WIsQH2=MSeSw}H?_rMTc5Dn*)7)W z8l@4~%Oc6x_o!2rBz^G~=mY03*VEHdQmCsoK#uQ(g0&#ye|mI3Bx*qJO?=RHR{f$l z^Sh#>xG;^2u3+7L67|_V-V6Iyhc4Bg0I20n6Wqrgn8q|>ebH%ac~^qm`bb4GMYiYX z%ZxLKRGfD!08Q)AU4S#!w(u{uE=#^ceOoG%pFs&Kg{%-i{A$jP2T>9z2?sK(VnScH zRiQFea}X#gC54@lQ4C2rIoEcMj&7{l1+1c?;^$Xy)euqt`U$a_<Q1KC6-RQ2U8D6B z9C-%Msk-?xgq|vS*+{82#tc<Fh=$+mEsvyaxVyF;Yc?>qVk+BQxJ#K*&D-KI<NgoT zhBjT=Zunn14x>A$>odax;^X2pYcUqJ?sJ{7o12?Z_S-^2h_(oJgCz+G30xU2B(=9( zch@oHCeAwsQDl*xjM;4-nSaWLv%CYI6A`55^EAL|43a4v-vge)*AVH{+wh9g1CJ~9 ziyYSjZ(KlzX6fiZO8!pJjh*A9!Vu3hz54<G?SZ@->jew|7y)nnT2K2<+6ykA^pd4Z zon~6;StVhUbzVuQU=uaQn$`Yf@1>2hGEpBAG~oNPiZG7sFEhd0c%AgL+ZvaU?tZDL zCTR4Fal*~PZVav<BW6*ms{W6-@P!6n$)%g7T}lGF$&-UH7mMW3#&0wY*dpwGiR=AG z2%0UP-QM|&4yjjuLuTeV%IP<hlo{P2n0G8i&O_*F$@8WD?9$TGE_S=V43&N%9^K@; zyu6o`fY%2Xm-T+8V~<1s0_y!UTH0@({qOR&1GH)}&l>&L$E#`CMl@c8w!?vR%pCHb zPYRxPT|CKBN&96QO67lpmON%*$xbDNsy_*=MS&;S4<HAJW!?A@+7S!+hPj<xT_F2e z9>L#!x{^1SGg|%v2LXLAX2SyhyOOgg8calE*|}IK6=(y2KsX#u7k-j;@BenU{;OsJ zTNb}fhVMKNV)$ci>j|Qn>%ctw2rx?bc_Dn*dE?gIU(ldT*WY+1uON<p@wZx*r<ya5 zwgs%)09}a$=~s0VWx9DeA@lW2kUVV11sR4=UqO#y$QiflxSP;UIR0U62Lr5bLeaXf z8OIOvlU!Z3n&3!uM|A6fkzEatl+cz-K@(3G#FzHnC)idc5+^8`8Y?!H)S<HUTKe(P zS(Ngm5oTkw0*yHf`?=(_R{X`k+J0;UFI4PQ?Dc%T9|NQk#oRb99fFfMdSCGOgJziz zi?fj?@WJTrxRwG*4M-Bz)+RSrVx*X_z4eiqqiAsqbLj+F;P};U>2fx1v=BZqpDbY7 zg%;l%p(*SLFYE}cw%X`_#+|jtj@mcee2Ac~;O7qs+f%q50`de>Bue#KjsHJ@vcG!7 zPLD(Ld2D5;Q4=Z2Xnl`M2McF8M7{^+MR{i`C>Qf;KTA!_U1b5=8o$qZUUbQ=7f{(P z;KEayX~4xLc&Wubkls6d{?V(zPsFTpm;;UOXUy-@41f;EFd>`p8t(aHtgTZeTZFL2 zN5Amb>AQdR6s6Nzy19F<RIZ9q*{)?J<#{E&Pfu?W7tn4y)%o`3Qdp;CdrO8T{t!HM z=G#lr52ZaW_9M`8vDWZJ(7-U5#&0r=)0#;A<+09jW(EGuM7}9#M-T)Bwi=V<Sgqhm zY)MzUCEG<AWZ;G@ZXcerJLQ2_64^2X9R`D@di6aL+q=CP<JYvGRKSEYmw8u`w+OiI zEL#!Vu4Q2IIVc7_df!ph;pNw4O*aU|C0b=nPL#chm%;P|tJ{3pl#JaB{JKLcjv_6R zSN9s%v;MJ^bC4^4FR*H8wIr2fwr@rT@!&D*C*WOOS)e$jOZrn_tb@@>+P4p&BuoaB zQaQuuOy6HKkAkb6F=;CsRtJWfV80WF70p=dJ{LHrUc6^Djx~}SebBgkCwZUH%0s$< zp?w1Z6tyxzA+rA)H%M*$%i6%@ANeUjLI&iE?#Kl#E8R@5-%ygyWxAhiy@Xeu(5dwF z8`C=TEFdDm%!Nf)1lKuC)1}~SM<VJ8l)?DCY<OBh;?VJpB8G=P94SWml0Fga)ItyE zT|?Owlv@%gY4GSNn>4G?5x9wxi5gr&G;W(_k9n|`_XHs?`3?|IN&ZawmD+Cx{pEKq zIXqz1?6G4ZYa}~Z<-~k>bwIcdEo4KREf!pOV1iNNPYy57`ay(yOe4abz2<I9!PXxP zEjN`(|Bk)@%*M6%MN3>d0^chM=|Rl2pMZThF%vWfoC11$e;Y-w7q6?swz21YvcMit z({aiBt4ReCkpm^>`YAmB)zN;FZ1uMb3%kDk5s7oRN!=#I32T*qw1LYxm-r)O&xhw) zLG}3!8EA?NNh|WjOcoDg-9g;|x!Kg%@$eY{`YxJr6Xo`P)SsG09<a3t+kQK%)C+6+ zV!pgru+M-;vYzo4n{oUHy!ZTl%3%_xw^z4JRjl6+_qgT1AFc-QBx5$}{i$P)Qzy=m zE~vwKfgOUN6qQtm-J3vO3POln4~vTl5q!`-j+fgMFp=4&JW^&_c{m_(E2Ok&_YD%q z>e|HTQJ)p}`*5*Gr2=WZ=0SOiQpJQYjd$=v6h3NlCH%P*=VYqZzp$F=^S<{y$H+ws zF}K`Mk`#}z>*j9WDhr*vYb#Q?d<_`r#?;ai*H6<+mAePuHkeOl&?d_$_E74o26cRg za8{gUJP3)qoD^|EwLWBYy!iNqvKDYL4=I^^6Mf90Fkud_G1(_$x%8C;T%<~7BfLC7 z`Za=ANz2#Vm3&t0re`^;MX02bD;CRp4%9H(;lRJ>s^>UUKbyX;ocgnI79*XjSQ-uq z=oO+5&Jax}A9)ccj!=<i*~sCb(h7q>Z$*N4iVH1kSPiK7WO8VmVtPh)_SNpC;pr!A zp1~-qH&(PNTgB2r53RqXRMC-Eew`NC#WUX5Mm(>Sa~V@LSQ)OoxKWr@;&7!_EN@LG z(s6S7H4-<5gb|z55mT$Eg~ovItf1W~!2dwXcWHeQ8l+6wqx#-p^hNXPix)x-%gP4& zPRHNXZuI)rUc121AmzNcVWQpON2o(P$ETRGPMK)Nu(@@J-6H2s7%G60kR~RQ)=hUo z)#56-GD|4^)IhoNt4=1;2AoX+L-(~aeI+ysCFN+$@zJ4v-vSnp8JHaa#Oz$(B6#1> zo*z07f3b2+x)(3Iw3DOEYJx9O^;XN-_kV0U50LXV@5!H7+M76o=<4a{NdK27+B`=S zU8-(pGbjqWGBaj`K~!=c)Id&cu#a!2KWik%c%MI7*PB67tOvi#mBptzhA;<q$<|YQ zu<#QifU*DL-<iVTrj)abF-7J_|4TtI{9mrOS*30jrFJr0<nNXgB=KS{D+x*7`~2H8 zfKB<ullk-x@<va%BC%YREv#x5Z>mU(@Dzr>$E3CFet8MAbB>x5ZzsL6&cLz6Dt9#Z z<mH38fCvHXnF)()6ZxFF7Z<6y5y<1Xe=^g5az-Uux2Dd{RgSVYwmVQP*%CZ4Aav{d z5E+1+?D=f_?JFp|URN!}XFy9~5fzMT`a6mK7cLxi{R>oeU(c~Y|ME~@xwer?<(LAw z%&C6;a1*&dW_iZ{@U4V3hTn3eD!$zJaLsy$&`hxUD+x;+qg0od?Hr^xSFBhk1%pyb z)*rfio0xd*eM?!9+)#}2&loqda1_5vOw{%Q@}7;k>dw(2)P)&_VTAJ9W$Ls#!AS3# zB42r33+tAMb<!2qT1_|C;M(^LbBTNoZj86IL#CYWq6Heu)9&nlFK!mB-Di(qHn%li zIASqWX$=nWk!*7We8~1_Z%EI{5tXv`n8rzTrWa3^xzix+em(}HlH$=1sN}eEPDz9@ z><gv7Lv4Hey+`p>8Psvq34ZJu6J%!C(h>7EMzV<Hejj_6;D}d&yHPr_=*N->E%QU5 zNEBaj;TA$-xqwcW8?HTC0bVKHn(mY>{D3!kw7%J-fv)66@pZyKUx+1|ptMQvtMuJ= z1)r7jS#5M=a@?=jyua1Izh+tO?V)L@T6(sCf8dEJ$jjkbXL>!q2krCqih^F$1~x-T zML{oPhmQ$D7k|I|!L7$CmO6I*!vRZU?i+-0tTWhIRWo8CsUp2N=j$SlTw7T*nv?>{ zSYDK9sZilPmUJAe=D%0eZDa|qzqRa}Rf^}iV3ub2cWzkjPt%UZqazGc=$J%vd443s z+KkU3u6#mlw`>V8u{lQEryO+LI`(yL^g5giJ?19AG@Y(Ohi1xZ@@8jC))euo7P5KW zBa3aijDXEQErieGka#}%dW2K2Fqii}8S=0<?ODLxps-YF$Xs;FTL$KwLJJXI8>ex+ zMW9)cRZgdk<|J0$0WWMAzt*F{I|Rc>>wCJw2W@y!?2_A?(&0>6W>;i)S5g~ySbLFA zqPhq3-V8x<?m!v1$j9paA$c-n9$}qM+4nK}$t;a8H5W5R*5v3|I~~ycTA`t3beeon zR<f5xcD_Af-B`;mlHr+)v~c}6RL$n0a(#YrM#k)H$A_ZxF5KO0eXd!LxN;*CVyaeb zoL*JHJmN-=I>+CqL_2Y2`XAUf|9Rd?i%~LFI<DllC;m$|$m7~a&552VCl>9T<$|*J z8LKBbF8a@G`7}psCB26~dZ8I?Zt-uM>4ZT?JcV>qG{+i*VEqEy)i)l%2Up*$Ed?H~ z<BTo*{8S*8kDO@Ge@cGwXOsS;#Eh+RGAJ`Ah;SZ-<D0YBJ)L?@T|(O1e&T(UqO~<H zMcQcE&JPx43M`XAbVv2o`>)E~w!hsPHx(3~Tm{=`HS!=BDl5a?meQ43uXo>)gdxU1 z3$_(FWV;zm-52KV?&QzUbJ|Q$_tUXZnGB}C(sf;p-m+Zk!Hb<y+bd!oCMg1OShU0t zyUd3w`=kA)JB*R*9gcjNiu+GCaX?09_=QW6q{f5F-j<bVcW~^`sEi!mq!1^+|8RA- zdVu?ct?V9eeaYc}_^}0IjMm_{f={dbwHoqES{?KtpLFEPAWN&MT$xhYYx~K0Jb!87 z?CNKzst1fZH6(zDx#DcO<4C-f<oBrQy=2b440oronDm8~$Qp<4eG6~DowuK#O)!eh z)?|ta<-K#@fyc(x9i|M2*NA$5uW$<;vmva|!qW-c-c9E3UYTBB0FF=D#JwjAvrEs4 z8H#0Di0OeBX0MsXnwkt7$6lMAWx5_8PfS>*w+K<7nm=26s>q?XM~LPGga<#ZL~1$Y zXd|pNoMKJrfkz9|t+LFTZbE$g7<93tbZVWGarePHw=y_lr+#j(CD6-`YYp_ZDaM45 zB<XCVK0dj7oD?Cx?b#pP6by<99dMoyxZPOyQtiu!beG&f!sG|H?~k4IH6U(o8jlc) zqisnG<-<0bdZaRLZ`f0%7<il?##Lx5lppFR!wAZ07&R*Qc;-7&{;f&*g$HH~tjK&U zdWi=nXYMIJ*7N%Xey#m`L5~ZcmO((T@<+@h&7LGAID5P7wEA^G8Kn?m$@LHJi4~Q$ z)GeVZTf!5hJ+@xoJ1fe7`ZV%BHrCKce|gWV09`CwYPB}0!!LyzsTD<Z?Xl+{=G3ql zww9)B_HilC#OPMrSMlqarkdSS0JuA?;sd-|P9Mh=K4YIiT4`!t=Ma?`{21b~27KT$ z;sJ;V8!tUlH@q3kv!86PU^l;&(kEx2h4sKNFn~&76T`lS(LLB1o0hTyQO5Z0Br&Uz z=6vg%)_W<^4jhmbD2sz;=++k91+CpIsh<_|`m{u*+%{2&p6+pfmR1AxdqV^2#NT@g zq!*M-EK&b>J-8+i&c`*DjhAi|DYS+gu`-&NJjOj!TuuB9H8F6Ud8~@`$o=qebOKtT zLj$rT{@(*x7hC%ZzYMT4pA83HF7;PVg)#!y4#6nS;{}=r$`#P*#F;+OqMAF@LpDMJ z!;|)&!ne*kICScPVTqN_kL+K1emR=W&~~ARUVv)$i#Zo;jTgD-LMS=eO+kdD3SY09 z{7><KZ<q%O274GF+o;Ev{*>HHm1%Nr;fbT2t1+N2rfPxO^q?fqysuf+K@utz_uBO4 zP3CJr3*#Zv@X}0fwV*=H_6JNO;>mN>3Ay`@a&e$!e^CXOjnM#}*&`Y?-7%6??B0vv zkOQ_DwI&*6W9S-cG(Op1e9cv7v$PeUJO9xEt&{(j*!E_JgB?3}@F@N<RA=(rc#4Zs zrere=e;<u0?$RD-xg{s!xk3qRy`?QaXl$HQJaUs+9`R*1eH$k<6&rB=FxIOB<Q^0e zGWycqP!;0mM#*o^I~cJwtej20zcccHID4yO>ZYia!(2Cz?y9nyY9XNNLDT1zsGo_G z2aP+zzQ3&?@ooD1EM0>Sb$_bP168h$)L!;mDc+2~*1h($F)f@|Q~Ysof61O&0D*y_ zu3=wozq2FDcHE<qsEX@358tR5J#v@i=4?*#d_loRBa4gBg2Ej=!idyL^JmXYjV+^M zQ1DbOb29@AW8#0PY|>t&^%)<%xdj`$RD5?gURdZp1`QuC!cFp_T5tBXoR%TAs}{ih ztu$<z{1u-8&CEZ>f<6kfYx?WzI>C$N`eauR!A6;vhon<tqYdjkT(q;MQL(bjOz|d6 z*XLkUH<)C1b02Io?!h&L+j)x%^U>w++WW-0YL-S=Bl+Zb8VhsEN)=d@RmHjSor1h^ zc%$NRSJI)1=5dvppOe@6<eRTn`q5o+ISE_*^aEC@C2sWmA6O*MRFo82nON%kd%@v; z#>T+W4rTs3uT^_eah^-*tK}!1Wy{M)H6ici^Zh;?5_TorhVBJcJ6qe$U1MHYVCK^o zbr=eM05G&P{8NJ7jXpe^ITazh0VK898XTL%#xmQ?+t_wu?ZmdbLiqVsRzkG4-C;m^ z4+m8AHt{Z8)-o#G#VVrxl~=`9*y8Wo(W&@OoUB29Wb8E!V)&8zio*m${F7(qz?aX- zVbS{AnekbP&irBhOG72)qjvOk+g%RO<t!H`c`@6$*PPaNI=~x#BK$Jw@>1aC=u8nF zQ%zKg#gixIoEAC;bXuqH-ja@Tntp6&H=5tA49V?u3Dx$dQ4SRCH<AliGy0d!Dl-d4 z_6XsDCIxgo4g%$>%eVW#%`#tGn2T2jxs<ut=@8=wjk8he3bAqT6TJAuw!fEl8|LZ_ z#m~=ej5Y|sI`@^EOjgHV3INb~Wi`062Y1fam{?l+8(!J%r)q|5MY+w~Y$pi6H!Iw{ zz$=5BQQv8=hQ1$W<Aq)nv`jAdAa|b6d{LP@KT9MMP2=t0$+fnJJ5d$Twjh{U!}`-$ z@w<u610LK0tg?uq)S0(kmwCwt%R12bU3!wsqEYbM`59s?$5g^qg%|6~3R*-sUi-$a z8rWEwf>*_&Q2%gHP-p9PF#-~id}YG*Pa5m4lXtX{U(sw1l^qu!glTQKS9t=-2NpOe zNCT7ps<Wd^f{0=3l_+=gIk*qsL2|>bNpcHvLqhmj<92NtVg2Lwj9YE1`89>F1<}tY zMpwwi%YXD=r3_T$yu5PDHJa#f?8&cmSxNp8vDkvXRiBk2gSqRmKbpU7BH4y4&bv=b zQJ?pZ_h|~u1+EOU(SCpKHSJJhJJM0?6}knTOBYzKUK965n9mk}Icc5P(%g2((8q1* zPXkPCu5nl}NqBXCY?Ti>d%EXY)q3v(L$}zagKzZc>kJH*@&IXR&-K|3G!{FNPz)yg zxFWmQOgg)iMOigGx%`fu_shI#)OOd_ezP7O=q79Y#~SOU5Bf96lXN0c;rK_Y=scKZ z+yPYSc-MYq@>+Bz?;Y2VuB*y@qD`&ZiH#B~53Rq3vcxPMMC+ifRq;=mD{l+H631OL zm93jRuFu9*3m)?6USqeAa9k{W*8<uzO6UxGV_I+2l$AA9z!H&q8F$YG8DZYE^PwkP zLi-&^1nF-`uNEkj)W{{5D=uNXo$>uQ0Q~_DykY5gOwTUof0$m>CfXVLez+&O@e3QZ zdfH~GR3bE>O(R^!v-zDyS3Du**2Il_Gtcp*Tfg7iyw2;SF>}SbN5D%*M+0uH9^RrH z!2I^K9!k+;@PH{vkLhkMjKqFZ9CEEd)Ya(8$o$apd;SoQq9h6T7gM*q{f4jvLgNnV zh73YwtE06Xn$gw`4QYS%uJ?F2NKZe)burJ$DoJ-8D&ODwon5W6IG96G!OF|V^I#{3 zD}`Om(dUtS@Yq5|S?QH8YWUQ~=QG88G3maK!y?F=;Sy}z#Fw)pUaVq!c3l$k(KT?m zHNAB<3;v124FwO7u8EVw^4{XRR{(|+U0G(p9zBc9%k|b+pBP$>Qp6DaR9?pO^XsKd zHMJnjxKDXQPKN!|WW_emr5hqU#AgAo&(Pm|a7X-s-##QJ0$GfCz_d1ox|}`;-g?*9 zC6(IlB4zLnP8DD>tK0Y_>yjQ56d5uRm6`<SD-@b)w9=go0lHkhdR;qNdX!DVJ3uB! zbuPa%2A!F!cSAws{vwg{(JAG5K~Qbwi;a+KM(+K!ffe+|(aE(D<d+lu(vCKln8>xT zXYzMFH^;vwh%KnA6arF{jJ;}>ZN8KN8QboR`aS6#FPZa+NMz~MX-V)Q@@U_vhxzcm zkRv87mqo0-i{y}j==2A3*~V7H=DyFc!&tJh#MBAeXz%prt?}m6Y_+0&;7_M|o0W6> zSDehNK_1-A^z4-g!ltiYGnb=?2Gdw2r`1Wj?U;c(yB@z*@TH_$@4kXrU-KGnLw%j0 zS2|X7)7_gWbXkEIu?3$huIo_4sm$Fhkjx?4NCHR=CWJ7sO_n_8J2RD*7OebMSVy}D zzxB}gZ$JT(;z?L+*xAoWSknUIZtal-QFZ>2LtBkf>xWy79>_gA(=~30jL7`&1Ll1T znR1ILi%-P<h$xfSI@CIUr{1XiCLTTD<yucjVRL6i@K|JQvQX^Mj%VJ|QUB=H>zxT7 z;^W8Nq3^=X+31Eh6rJy53d$tC2wPra-VBK%KHtXgIdx?+w+2Nd%G<7gmyu(bjg3z% z3n`NnI@IapaZ<K~L*SOfpTj|Slor$;OW859GqTEpI}(fd`{_ao81A(MY8+}O*FVR< z-(4AI=i_~lthD@}GUTPCKIqps3DGVr=sHnJ_v7N(ZgWG6B8>vollku*VqoD!MoxGL zkV6VQe6Y!NtY<mCh{A@tNUAWTmOQ7F4K3x5&17b@hTj;6e!anq8mb*;mp3+dN_%ie z4Ipzz4QRa7H*1{!z-2-EQn1A}cGg;(_4nWN4Z)bO315Nwx|#w?`(*5Pwu5%^J$B;O z$VZjZ^vqn{1hKm|Z4Jo=9@f?$vYEJrQ8M0r8C8Bu(smP%hivmZ&<g@7tfNnx?itW8 zsJzuXpIZNd#9bZ4du;NSaNz%`Ie|`z6<Q_j9%0nf`x%S7Ynz*!gBZOg;Wn*zDu^LL z#I|FU$wx1DE=8bcs?7Buix!O-T~<OIwy+GCv8#%Z;Z>D%op2eCz2@^={)tsDP3@dD zBHnxU)R@yqQ{Fmm`Z}Eyi7R406j3L;$BXZqhc?d|&~;&*`*l~tEGji=z{PY6wk_;@ zq*;T^y^WE{-O%egH)N_7gfnyBzAYXt-TRdPWh<cI9owA597Jun8zd>^YM{RQh2}!o z*sfN(T90mSC3e<)I0e-o4pV1adOsp#oufm4KCv23Si0(At^eVcunY^cETZpqwnm!{ zcR>E)oCH%_L?Jy$QrM;+RvlzzK%X1f+yYZqp^xOyewTb`@wNHp6;1>Ccufg5Ir#GG zGcb%4>m|Q?Ff17QnrEL?`lND`k-6Bc>TvN@41}o#6d%dKB=32Wl^07Fj~Mg+s%|&8 zd1}+DwBXK*FFYD5k1=`*CYJn6>05;UM!l?NVIb2Lj<VbC8exNz`d#yH1joH#9>qz~ zCbI{G%m5^-)B{mTz8t6Kcc5x-sHT6Ak^NBchc}Bu2I<kIp~ivhoifJ28bL&1Iq@J^ z-$`F9zD?*HP}KS$Dp+fQhph+Vx_`P_t#a+%IpF0|X<vQVDy=)|vY^sd^z?(Tr{R~3 z#g0tmF^;<UwS>f9iJ6Q~F!f&iew3FmwTBXi`?pWK@tfYuo=s8LnkXhIJUDu);jW^( zJbVy%Dqv<GoF&QOZ4C<_IKE2MyLkh<yI7n&z1-OpynP)L0>sK~JodG39$h>r%9c>6 z9`nG2vOaL=DYo|dXl@QI7;i+93p!3^R&w;<oiL|aA$elPIUJ-KZr9nm-LrbOALdQ} zFSgz?tjRv^9~MzTX^|4?i|$StA)s`32uMpe45pIONav)xyQRCko6$95BerK({O|jI z@w^(x*l`}`x&7k%`+PqEIWrU%WMS~xZs*bXv~Aw`a2S@s%J@ufB-AKwHAcrMCaK<A zt|w5K2Fr3hDHXVQ+34;1gAw;Yn5TLYpffX@uBe1s!)Sr^E0=0&!%}-3Oa5+hQJm;U z|Mmp7#!-C9%=-no1M@MvWcIzA=3=?q767oWBw)Bu#jzAT%i!qJVt}|gtLXu7j>e2B z_Nn9T?%CPMePr#-2N^dA?I#hm-6Qy@ttTpyW5pcgVfE?K-YCG|KttdC&<VKngFu?0 zLa6onLlX;zFv4|UCi4+pu3y$sfwPpOT(llIn;s(>KwSD>Ek>^bW%ZJfr-k9!A3P58 z{t9bGH_+hajiwr05##ijP5t@uV3GblZc8d32|HTY4@iqjAlF=Q{(^k>zfje*;Zb2= zfDMk8mOF-LMY8C2QtT!<?=2+tkOd11#pZiSIoW~Sc}|QFHuZDR`c$U%U`0<`dkhX& zApsjVSUaf>l<q1_<5M=#<}g{zK5XVl(arT(X_3soTWoPrcB=SeVrg$!#W}C3VJp&Z zcG4Py_I<M?dN;!b%6MmC6U6My%h)ShAs#==N2M<9r~S!eYb&cGXvC11u7AH!NH4uv z1h}(5aXxETQygBbaZ{E_{@{m1<DKVRPctuO=FO{6#Kd}e3;=2Aj}7|lZ<!LBrtNyJ z?eg72(hswTx_xy*M)w8zfPTTXo_<=N)YLy5U&TK9r;;8Nf-(hjJU1F;d<iuYpvF2{ zI>s^cq~EqB4mXK51NuWoV_(lxSBW5MEI#aS9apbhE1(v$_wN}*X5;6*atq|A=RQPH z627i?89hk-afn(yAWBDY=r^*T!@pb<>xlBNW`AyGJ%VrzQhsG@?lmz1jDNAXH!k$D z;-(9vTm>NKtdby(p=82tH?{Oi+#)Qz!%-EHZ+Qh!Irg(C&sHBUQ$+3A9d3GNrJG89 zQT>#g+2~#9gufr8k77_nts)Z1R<>9TyxL$k-&0yObW*onzdH{55y_nsJcesr4J%~E zkcltomy4tz=Mi+cK3IBSNdR#S6)`Q;y3GVmFsms!z7%WZ=J%I%T3Oq@$6B?EY90Dj z=4>7uae8gOjwXrDU5`!1?Q<G@l{+n*5R{e_nSyWY&%c?aWOKor-%H<n3eeYU=65)r znCwux=ijroRc<Qc%KNIau+zy~Ft(noX~1d}fk8;DjP&1sAQBbKMX5jDjjs?ld0by^ zmheRFQq)Eu4ee|rFe$j9EmZw-r`Fg-G-XAiF4n8rd#ft>Rt^RejrT(ld^Wc@c6$%_ z^)$lJTo>#hIl;5&W2#K2&qhN<#o6rKrY~8wDaVS+74_abP9H8Tm|GOwax7Oe<U8(c z?o3~Pfrw~KN9@PslTA9Pn`k7}*;sX55)cZW3LC517MGR{t+a5t^>!uG+i2<SUMC`& zI4Wp&&-<QF`{E^ch*-!a7G;$;!~XoLL*c8(!Y*t1wU0qls_pJ@*e4o7TH=#&vE<AY zZ!ZO(u39qZ7V}@PR?AucZHtr<R*<dA8J}c|W@#McdPq{Oou77``Se%q&f__ZkS$l4 zrjo8~=PRrDPZmGAs;bA{ji6W~TP6!v<K)B`k(q*aHpiVKGZFa%f1X>^CDfr72_xgw z7W3ik=WzjD+If5Fh1v#0ivYR6t2F$oi-q=;!{*?y;KMdiGunJ458cgY2ivA0fZ$$@ z`*hb}KnDT=@kf7(@%%Z?ThbY12)J(q&h7)U++53T9GE~55<39g3n%=X>Fyx|G2p%r zrOO@kT10lu<*ivxM|(uW43Q>Pylq?^b2F+YdOGb^zKRRAh&Xc;#Z$N+E4pVC;cf}b zF7qu`+{JV<N&&Ysy6jiyDJ11;LUbrmi-F|8_%^Ko#d;DWk+wzgS_7*`=aqkF)qQnT zGxO5$)GNGxR7M(r$8w$^?h~lptM?*1$2qHGG@UB1XTPwbh)t-<s`Gpyk2^eC6QY%S zY(POY<yq?X;#OeR33=N1eA+*=`Rmz1yh|EFxTKoN^S*v|m?1*1{ZSX~$CUQ0)?X)K z8B`C`J=SuMu9^eU=Gg)TXPl~IzLN46rvrMCXhJWr-!62FH*`dK_5dL1OrMOnJqJoF z2b5Y$6!V0pinBF*NunYm^;*wADmlmueXql^x+Np366Y_v_*kMei}6dFBYn>Evif~N zR3jNj)`Qolq00$^&CPI+zZ8&DN*dnTR|{d@(pIBb>l1Hsa@zBog<Q|FCsB2#4E_90 zJk|T;O6wauy6(Sm>;zj~x>={Q;-F4H2KH5Vo+ib4fTNMPkJLiMLSw{IYw-&W3)#gB zBGYcm(X@5L4@!eJZ>qRhngm)5cfqbaL(%=gI8=NCUw>j;QC%r?7<by`)Pp@Lgm>WM zgpgGF8sRB-8(HtWOE_KWtH&mt^VH|dH(H4f(d42w4o-?ARmJIHJ{m?I7Hh%#lbxnC zC9k2juP!}KjK$6Ob=I%%nJYo&50R3R-vJ0QmpheMjHoXsv(Rw`%iFi@)ECz3{(k1> z#Ai!{1&e+?wSB89XR~*Z=415dY57XV)%3R4eV3218YHFBD>23z8Ywjv##=+Zg!36o z4IU0#Lo(gkmihcjBuS~uJhZjGd^6faXOT;lE|UWmjOs2dM@rY%{1%I8U0cLKIJ&=n z{nB#S1lQO?T|Cc>s6>4Rekp}iyV$-hP?^`FT%e-j&w~u~rcK>I(u>9GXkFYUexKbx z2uU>8{`m3YhU(2i!|hB0R1oaaQ2t-1Nxe14bs2EII<jVT#MtnO40sxXY(LpXt}Goz zlCR%&h^{>(mF*7eIDVo4DtCWzHgoE~&-61Eo2<FMgD}9c4<Zi!rd-0vIC??aa7bzO zRB7Z9T}~g4el1PS1dn>*F*s-MfyaGuEj?cS<ZS{-Rvgv-cze@5uyGzlQ1$93s;C#y zQ+K9j=CD=%U7KXwXj#A=g*4Q07+S7%?hSjXF-JAR!fY=OeD-q}Ha-S}l-B-`9=3cC z5u~+*(DXjhN!oe$ld{^y+ifQ6ur-X%S0^>VJ(-KU-dV}I<I~Vv!NNg~!G(9c9#UU4 zTWLf1Q8hnBR0bKJAaF2h?``59#ZR(&7x>omkYd+i)P8IH<__AE*TNf@W*f>67_|F( z4++aIWjD~SAQj|x23ZnB<vZU#UY<tXL1ZGIde0Z_y#BydDCF%j-wcbHsH9iuGEe%z znM(4oTqqoiA}Ez^_sW@B;bn?~HtPez(8`%vKk5m%XdQPA1n>**GGokf;66G7N5<mz zR`GgD<{Mo(T!vK~BQu1Ad9u}TNe(l^FR!L@s<Nc_g4h>WW>x3n_;+RG%;n0A>#4Us zD|swV2E0^|x{C;3%>15&E)Z;|U4{~sE+<B3PPOKXwH@zY3QLoR3;lkhW}pUigYVA{ z({|&{SSA!bxN7_89Zm^%_eGLXiirx;Ggm6F3@wz&;ibFP2uExKlE6$V1_GXqn){l= zQW`f_xt#zNt&;>R;~Iey27ulDn1yRFP|!`@x(5h-^6PU{eb)6jH%(hS|22R9kCPTN z2sV7q_SU{+XO$nZsF|+sY`u9^3G+5pm=aV>sq;CzMDN9M*Ged2t^bRIqW$xI>cj@W zf_c|Xl11VWr$U)v3eR+XALl##R*&_cIj4QKg@tAE>m6P$3ylPi3?Ie}CP;g}EKcnQ zO@~BL2$w?!_|v8?!^$39=c3;KWR;CDtl`DEka!C*FQ8bgtz|~I&J7k{Ex>aaA}B>H z5}S6DDneIXzMQ@E{BiOx-)1WHB5Lg9Zp*hQfRith1m3+2!M0!LGS-Z85Je7ut1xNW zjD$G)T{kVyDBOb9mbUZK{C#gz2_-4=jKV@19<%RP?I|Bu>@F8c5PB$bGz}sYMZHEm zSoJ@+PCq~fF3`KQDMvre?`*$Eu53ZUD#t(HHHmq^r)m#>6r+r&^23I<a(uhw*fOaI zn&}z&EAqR5uaE2w?S@&44@(r>AONdlJuVgw4?RVFcmF(5#Nz1#q_z6T$*^3c376;W z(saHQ^V!nKujwOV+%)|BBk&Q6qA<B2=g+s|pC|9GR!Z--!X5&CP8V<(9gjUgs+@<- zvNh~3S@fp>X)GnfQ71-RmY;MNj+GXfn`RGPCshr!)wFc9%=nPrhAUI_3hH()tSdL; z!BB92MW|jY%-UW#X!Ze;VA^dpo|4p9R$AX!-Z{#kYI+Q2<sF*V8KdGBbvtb?v#66H z4%%D17;kFv;EaB|>TCIR>gNp0^^@!cOL9b$4FcMw7THojRkuLl%qviibI&|O>mX}k zxmyG)T%61zET}Nzv+b<kHsDPF*7ruGlM;w{0TpM4dVm`Kk-t<{W2MRGMh?lVnBi{u zX-c|D8b*yYmR*Hves?&SuinmFt^I>vA*LLyJH)5WZ!B_Wg+!6wT08qOF^hH$@w3D} zmu~+J0bA4%z`481S|aG;TQajDrB_BSnVO$L0|1RzNvAq~NU)v1&-I}ivJJR6Pm=e{ zqnK<`R^GMNr2lk$Z5F{v<*gx(BH&8ZHXeabP-Y7w0Kr}mZpxD9d7wo|eXapyn;yBM zYGHc;8@Getfr*G}EL61I_58x`Aa{2|Kf>O}vhGFPdGGfKr}5zJuo$o?Yg?XulxKgR zSw@Z&76<MeKUWaQ33h;4-CuweSi^7~lEwLK{jaj=LcI)~8b9}^I|s-{&0ml6TjbX^ z!g{gpqV;MXznH4Y$bMQHf_L|a1U9`x3e&i_ecZ`L?ew<tM}I4#1T{%?j*S|9*7m{v z<mA;f<|g&kc|0{DR`+W&ziQc5VdF2=%%x~a92T^+G}O=PL37c_Ru0>*A3wxvekjun zw0M9-D#+oaiFqKd?4K80F;27uSAojMi`Z6bzeZ?UFVxz@8N+SaZmLmxmmQQf>YXAc z-svJ}tIOzR(cw8UYMso7jZd9EGH|Srfi&Ahw=9o8>I%3$6u&<hb>=-(C{~CQ9LwOc zmq4O*M5H$C!rG<i!I7~V?MR!AhV38Sg2zSt2?Hz*S#z4LzA9To+}+xzio@(~H7~=} zS#L)1GT)NDt3pUvTKeRV6pf7RtX^P|V4sq-b9fsh)?9!a*r)(5LxsW`^*aSe<CFjP zzXNqQC^GI(K&QCCUHR+ky>KkW?!a0;Y(jqNCC!Jq`iF-4DNxCah9WAK9VHB3&%>MZ zM|&zbIBEB9UBrj*78EYuUR&Qv?YEq%Rb%x$WISW~s^#RmCHfso{aot40D#OU&h1%H z7`D)Soq~OWS~9_FzdS@%lC`~1PA0SAu)R)v6rEBSDt4*<rTsNs*yUlQ@F3Dz!Yr|W zG=<;)VE_?FVsH;>{<YLPqoiOSjF&FL=rVR_bcCD9QZ6)c3|1H}mXBtrcomr<YUT3r zID3C#fga0@wrlUhSNWB+6uaVb{yG#LF6FRT2|ie~Y@QgXf}7c99VJ{kc)80u$KasC zI>yFc!l9sK{NCzdWuosbN35NYO7UiMu7)~}ouUH_veKNL`f%)5A~5<++<EVZ&Hn+m zDklN+Gl^D~r5WvC*J?Lus<3jWk~no+t?!b-Au97=q@l%-%2J)rW)DH!9*1tDm$%#1 z7F_-zvadSI-l*MefwMDfGpod-^u1GY<-_lxk4f|K1r&O`j*BZ3pHNqG&Q+k>8;e{> zu9Op*dVBEEU<yFjC5?zR7fnLJcCT>tNZ*!=kdzSC=MiWAvek7y9$2chfJ!lpYR@}K zKb*!1NAlOA($!1kH5!7WzyRlmo}dz92XUW`FR67P0TefgQspOJxIG80txZpQAFanH znHlXgO+?cNWiilT=|MLGN2np`b|j2k9j9bU<MkeA3OmtTG6D;Z8RLh@^t*?{A1gWJ z4M8f&JQk-ji{Y9Vg4LJuHOj~OM54LKt3}fqonl%S)VbX!u85km&iS@TW3SL-z24Tu z!`Mb`ZF5u<67hGp)-_nzNmj{7%i%Dr2-=T*Ak4+)0b;1<+l#C6^;Vo{=y*1oQuQDa z1$U2A#~Aph6HM)O)J`bl5WHSEu#nLXT-d4PCm`n?;*uffOIA#P%LyDOQ;@!EWA{LE zCx9FVN;n1-lvl)2$V<wm##=g61{bBEqw;wV&3idn2l-_aLp7ba*i=$7Uf-pOm$93e z`<*cIf2+rZK2ec|(SWmh?+yFwDL5YI!x?;e-rpNBNhL~*{Z;4MfPDJ1+WU`hkW&JW z{ZT(n(vhnQ4Tf&(>%DYqsE}{eJn4DS_iz6ywa8Vc?_@>Gnx&#<t=8jEY&O63SL=yg zK@^_D9huj}%s<U6j&czXug9U}pRq?#JLa;kb%VLaaXP6DzV?;z<5BrQ7M@qp<zcB} zmWrybvKrcqRwRs6Yn8>$6*~`Zg6l(8ze=3NytjXa{{BrMIU12!BW7l0YOGhr3=js% z_0+zMBoB#r%Wu;g)&x!LiHO!sN>4J*G)e4W^w(b)`kTU}^s&X+>cd1}th!bXLz(;- zi@fq$Ba0;v*4*tKsa00OM|85-#`4ugbwc$Gj|&hM*6rO-9-W<k;rW=RP3K(R`Bp{M zx%w~r>+B-)Gy`|H{YJPb?rx$$qAKSs7qd-WQ*e%KR2r4%fFT&w#40iG8&wgCH?OiR zZDr_aWnwnndmvJ1IAw~VQh)Q&ZmwwlP41hMuyo;1w!eRO(gmyNH**Pjjg^A)dl)iM zQaWs>ukt1h^p-vvz4?k{#AHMQwsT>51|Dx_;%D*;zUmRa7hv1`JjOjU`-MfM&hsRd zS#mqKIVzQh&&yQzyp-rd-Av<CndVI5YOG|O+$Z>lD1%sFHFcBoEjRQvE{aDLcT@f= z%58n=oOviVij>!}skLZwH=k;?Sbn9}vaFS1^rWGeUoAy1v0cFD4pz12%58hI-?V&d zmB5#%YGTi_)B<R)3hu77hwV32-PcT|9=g)HFE8y+x)Nf~&1ffPe#F)jkQQl;m4phE zucR63H9Pu!><Ob!t0!VY`*UQcD06?q_#ru*RKV8ZxP5w*%pp3Ol3!5L*gQkGnNs$n zaK*==dgoAFRb8!i$L{n2qHsZZBG&3u8`gh2Rqk2c0ecRi3i9O~>(OljUx$-!S@<dz zSt^RejJ$bF7fXMRj*8kK3Kw$vU5BxvPgcl@-iYZN#{tCz;R|ChdO9f-{f2)$p<K+! zqRltC_P#3pa%iNDk&t1;xc<F|ia)zp#V3FC4TQx}5(g<kHUEKTtZ-VkdCLturGWj# z-NO65P}nt2-7e965`DS82$#sNb$!dc$K=H-Mk2Neeuveg+EKq|f?f!(;7B?}i^byU zPHHiFS{HE-yI}`Cm0Evzl+H=?tF$?x*AD_;1_G0lC!P-{VuL9<M02>)f<-hgzIT%o zE8@I*%Rz<M$dYt@opd@jRfhgAVAI3s(ctWzT>u+qgot11Cxw8$wqkuvfLAv<R4oU2 z{SLl&vA(B%ut_L#rfsyFDx9$$s&y@v>u(f*;)Q^E769{evx!MNdn6?P@U_UlI{upf z0ugw`7UONGtj%rCD$i=Ju5Dy0_+48~OpuY6d&pmRtqq^inb#sB+4*9HG6IU%P}eii zVLsEEijPhkm}O!c7#SJ*${^ZN_`9`SyI9WN!roibL3z7xT2D{7w-*i%l38>)kk1Go z+7X%8PD~{EB9K4I{x^9ewj{Movo32*Q^(ji9ZY8tBvoCF6;`I-ovv#Y$%ukfN?4dt z`EIrz#vcCO7WVJuV{CQR)Xd6FwY5Fkn}fA1=w%k+^mlf)M@KC3m#GHQhcD;sY)cM@ zur7D{Mij?CnNU$ReKzcXUla*5?%ot}Fte(QC@U*#OPcy?Q+hZa0}}HTW@a_x<9EJT zD!7jh31=82gVS^jr*yTA0*cCuOAicp-hA0MO!ln!#k%g5`}~lOoyW1unW&i1pyFbr zsj#A6j6`p$iK(QpNcyD@e`#S=p^CQu&(74~ySu}w*1meNjD!>ueM2=p6BD&m9aTeJ zeQi7Sr*{G*vGgRd7J46=EC`5yjtbAer2w1H@P8y4ZYWMp>62o0e^oYfoHr<EyO#PZ zyET1pZ**{+rMNiJ$3n|nM$*!uzBM03t#~b$TJWyO#RJ=;f>T)A=P#er75?z~cZ2=r zq%*Zy<=KU`h19I$z!%P5v%5q=dQ+sjnhqXE>Qo|ipo<kPg+#dmEeoB-W$+H|D|r@q zexsW9{OWu@&Wgg)!q)1ntf_3j!(wulT!s7#m@-&ALqjuOM|EZab9Z*=AThY&$I4zJ zfW5Bukm*154KWO5E0@&YK@{!BPI)h{*Y02l{h+cwHza*H&yV6_U&uu~Kx66T%y41^ zyxk>k`7A6fj^-=o-`Bby%@L76`}f#ojI=%>GD8<)QY59#8@{~xs-nPqX#N@{%L@t$ zYA>(874kSnS<dO!SSq35or)tbVhs($IFOgY@z#DaN@lIxS2{^05wVb1xziIh5IXTZ zT<27gl~-$Kk#j--rCO^r*l+i{7jxeEcR$3J2A+W*T`pqo+;LEJ?FRxnWO{Nk>6dS{ zgC*$A1%u<`U;+Eo(=4S-F=5tlfWR$v@xf3^3Zr^l!w3}tkHukSB?X3y{QTENvzh+C z`l6{ohcnD3^XtA}m+MDm?II{d1?cFy=iS9hVsq^ODmQ-nrjFBEu`)6)kN&HA3<GV5 z!SPz#vP0HzB0Kb>-hcN*_iwnt|G6haef?CM|L&=%tZa02boPC1dU|^5Tg1YO24Aq9 zcuKA1=$Ak{+*fz*6B`J>K9z982H}p@%KG-)(viYw{yxmXG4YZynUuD<!t(NZFqVz* z+e7jk`}j8&#F}3$kMO8vcOYMEX<Zs+yuF)NrNYC)#MFuZTXZo0QJDSjDk6m7rE!@0 z%%k-tQ_RiU=y-|9<>QkBly!%g8_WDV$)x`$P7&t)S1yP8`JI3K`a06iEdR=d&dx+Z zR7(FPN^e>AU)}!q=f^hw@#gApt<L!yVm@;_S*nZpe-}boR0aGa@u7qc`G2d(qo64Z zEH`Q){$Je<zSVz05n~H+F#RQhDfxYrjP`$w0i-aUU;OhBz>|pgKmX?fvi~RX;s5Uf zN7VnLv%}xQ{zq5_TO#v){Xb9Ow;d_itkAmFb}zcx0$Ogne_{d8^SuSPcp__C_@`3A zmHVh#NHmo<mIp|ZLP!hMzCESNHV1AUrKSh91`iuHD|d8LS@AluN-y4$=B!n&un5jT z64CWLPFFk5l`ICy2GdqsI@a6n=TX<+J4&s^pPIbxa=*x^u#>6<2C5y&MVME>n|Z9z z9XAb>sMyZ7FK?etG0yuoV*3gsmF_!MTaXpLx9zJf7{%h-?eAUNt2(}qI~)+UHtZ3m z<4d*vE7@%K=*#T+hoB&Z;wU*bALKvzY4`LgB`zi@6@E+++W{JyDEiZO%*s9Jw{Psa zZh|L0QG1FE)XR2!%!7KvMrdfrSD2(E_~%&_b}qy&G7^6R(9ld?JbShsU6bN~`V-^X zS8Pm79851h>Wvq}Wl0#%#PIRYr6vB<fBVLVZNZ5C^yb;KE9gH@T!x0Gg7FL+2NO0o z&u>GM`4Te}6LWzCpKElUpGMyp2Xg=uQ<ofnf{}WI$3$oE>&EG~Z+K6iCSpA6dGSn) z9N#HT=T#dw^~S}wZ<XJ^oqzjwl)iF%i-rb%_N){OQz#o~z8=DPGPbwPnrjYXqyDTc zA)zVpN2$FWn`Y<uUvZm>sJY74KP}NLyZQ1+^ZXufsTIZ^J{p(6Wa<yU@c~#Dk@$Ev zH*kqic3ttQuRf}w6+y6<Ezu;j2BBn94`?ZIyh+d?FYVBAXZ^gq2K=*E&UsLHI%^L& z2qqsYEOq?G>?gioAS@c+(^lP>`U44#IMG&z)Pr*9SfW85NSv<6O5QIQ+vLp_kJi&7 z2T<>wgjQ-2+cc(|LJ6?eMxX2?uu&@1GccL6hfvCJ>*x*^)56_OL2O3zqCA|fLEbM1 zqffdhDeA-RK4VXVHJ{Y+ly)fK)djaWTHg2&(LSI8%ejIfk1uuguO441V5kwt+zvDu zAIxMv(=f0jqV@D(`W{W|=_=n6uzgx#TWD(5nNIw9-^(h+P;RN#V_WUDO@j1r3AU+_ zF%qejy(1Ry?;QK?SyCgt-`BT~?rMD;@VESE1YTCDg)&~K9X;phY`Dsk>e(tu)o7*d z`HRNv-2FYif(i{nB{Yg%bv$vy4CtW%o-7$V<>U>-2mP7<JF$hTXzO<_tp=~mC&|o# znfdn-DE>?oNSwN?u1Up{hS=PD)RO05%?iAX&?{a#(dC%^dPv<9)acrQMU<E%dXa%N zw3;$3U;1Kv+SLYs-e;5hOt4$e{f|q41;J8}I)#X^$3W5|+i-f{A=5JlG6yvqQ@Km$ zN^wx{$)_Lq_X!qd_@L>+*URa2J!MkZugx;>3xb$lZ^h#;f9A@Z{HvYt5*~`r8syb| zDPGPSWf6v-mN4{{i1u9qAGo5$l=O9MzzjJ0Rh3StOeH>v?jG+V4;XWpuPmWp^4nSW zNy{hSD|>gr77cIX36z1EL)CF1nvi6}Mzlxc#A&VfiSEfMbM6{Uz@e@GH$~~`N?zKc zw^S)Xb_aQJ@%!qw&dVox-!E8ZW4wN@sVSVehGe!kek8+dGZ$FNWoO$RC1px~>uSh) z^ujU0A}LBpvdvV6Cy40{Etd3zCJmzO6Ob;r@q{!~{10IC<0`_3CRoa9(0m4$W-Aa@ zaOgb9-WZc)UK;m0muVY{ReS+AG_;UrgX(<;auAn0p|`&%B{n0;)LsusuvcB?Xf&SD znU>j~YAB>UasSZJp*6ed*e&B6^=reWwj0N1{ax-W6Z6VXBu!V6g(v>Am-)rwB(@xX zIEET<p#>hI@r4wn<&$ER?qDqLr$XvryX!-9{&>G{Y8<E$ptH?a$CTkL;5g4Z94pcw z?OB(x_f+YAU^sGL$3C9V=xXVlCl9Bh7T!e1*gi36-tm?MW+-L~!lZIC{zHKjd!y1X zyFoUWGSK_C8nC1DpMj;~Wn!h5YC5%rhH>ISBCO4#$S|sIyS4%wU-^)ekyg*JclgDu zG3kA66NTLxLvdYQonf)-wMz*x@vO5L*gW{9p}53WbmJB{FKzCpZe~Nu2+DxX9at3A zE2hg@{zEn`tGQqeuL0g<n>n6<n|omDZNS2r=G1^FbWT-D*1p19aW+K%*(}LP<+^py zxatvzckPknV3jE?$umW<>qFCCdlfP-3HHyC&q*5xXu*ZL?qi6ul219-Q~h3I@Mw(Z zEo>-{NGyLB4eD$(It*F-rqac&KS|Lb)9ZuKYhEP{jT6!>QgQS;-W-tM^Vz@9ak@F{ zF5OF+Sl!mN$t5pGi#e3mgn#XCTZqd}aK+O1%3ZVAWlMU+JzSmk35>s5$^0ZO7fNcm zsFoM*BdFaTeBV#AKO#FH)!O1QS9tFxwd*MDC`_^@t@K31`)TvzbvZH3E|SZ~DElzf z<9ESoMXtBZS>de|jepVLxt@jCjKih0$TnP=iQ`X+eq*UCcdR4sP;+z8aCLZT{Psl_ z*Av3ykWE5}b6e(vr(3ibDo+GQ9*|9?tld|rG9lO}%{grN^Wx9~D6tZNw_D}aEGV5I zn>OALbIbfKzx_sKbD#KgeXic~hVGnn`^pTwlGlKcYFcMEo+*wBv&g1y1uBfTc&e`2 zUX0Vffc>xliza&~e~d$Wo-Mr{s-HHSmsK6lN#4s{qnBIpk!%R;8uTm4r-oms@$_5@ zANwnkJ=X9lK`>QvdTXz}$yIch3J-a8HNYklFxv}Xvi8D}KEeesA9_YVoL5AG&0k`E z&1G6f>cKd4eZqSNgDGR8W1}@~`q`o)^cf}4I%Jf&5r0RDYCd-{s-N#{bGw4w|0#Zj zja5mHim>-Fg_E&E-;|y!j6F~k;r*&FF7q62MN9HGO8xM{<nMqhvEOkSmNvmb_S$<= zR&4IPCJim2?H~axgN6Ai^Sk>Y+uP(!?nIIt3i}uXdqc9#Fpz+ibyoNR_$N_046^K` za$DMF^WEVN;(DF{)1jHdN2RooVtbnz_&z)`jP!}@HspOjw=s8$p6lgN`eFPQdVA6? z6;A^$Dh6}i1{=1m3MpY$XM}n*lFFAQRWrZVn2g%+7*AhbPM+Sy^b2H~k534d=0f(t zF=_{?fwuy#STl2uLjYeoDx3b#^x(xp=wFy<axvW&*gcU8_d-+1?lSpCe2mThHBUCG zl=YmSznrKYI~Dyyr`_^)--$I%P-S6GagVMI0Xoo($jVdwk!+U{I-i=bHn1z?#!gfN z<2PRlg^(ohRj|Ta%S*jw2O+FhQAdg>vgfvW5R4L!?p=CHg@V-sHUK}<{%NN3m+d6P zQ!94KQ2CKTAVEXO33u5oi6X}8H@FvMOX}YEAR8KQXH`_ahhd#<r$vvzWh~^(%x(PU zeJf$1264rGHh+t+G&SJ*PUixXo^nzyQ70W|Y0C#h@Cd}|d)8EH+V}*ZnIG{A<=frZ zPgcw_SS3C)F1chXbVnHnuW?c{DM{r#6gs(Z+pyQtyL2wvW^<RAblehod<LM0Q3W=6 zi>y;kd_zi9BUuV6s4n4z9-yZ!&o*bkf3(>8x!^B-i-_z*cOFc%z6PqONxSOZGW+T! z%%Y>q_~w<GOxo94tnL5_o5oLs!f^1NIkzKj17Ej}xX6Doc(ww2i+-#Y;iZj$>lvzI z{SLRF?CbAjdG~w7dq~%_NWF(K`S@*~PxBSFh;BR!7_hzlnTSKSz&Ze<==}xS6``y< z?}_PBN!5W-p18}FnApd|vQlrkP;0gtXX<UI?_ayRr`L1z)?~i@?oI{w)k^lKMV8j8 zrPZ!rj5d<##69HgVi{V?oewU^eYz>eX8`()Y2R&r(e%on3Qo#qm_8SCtNLY$IR`8j z^t^I-aOk?ZWg`FRmrr^9Qf(+T@NT3lVVU?EF8bm-QH-PZwYMto1x$Vh#QYkt@C)kV zC`%<80TyEa<M|ru*`aWu>cw*SE;5P)6C{p9Q%R{Fb>tY6-E4!%g+V|s)t<M#E6$Bg zYH*Sqv@!l87cCO`aKT6Zs`>q2NKYZ9@79CT`$QM8F2YbwY?H(HWb?ZW*phyl{NB<~ z)(BTF=?$c2(2&f-bMTunWqBm;i)H^Ixi5GT0;q465-4}4r!{AiP>smfG$#?SFn7io z;zv@+&fq4(-E^`KueEmR8lYu`e-x6-E<`v?g~0{yK0*bx-mX@+cb!d^PKgDYBlU!D zqMh0Qp7y|~ioc`i99T@osmZMytRz}iWxk+1{=<j_m-lrp8WJY!7Dz00Z^jS5DCxIo zg5<WB_D8jdvo&k_Xxk#yRgvl~301MttF#}F{tzLLsZlfk$x5Dbx8RQ9$_KH$hj*7i zpmd^D?O6Y4=tzQ4;5`@e1gQ8e#gsQv(FB(MT>$ibfn<GZ*2cJ}Y(-K?i?x~6_0767 zqVV~tS?Nmku?%kzX=KF~#k-sFrjO<V3dpWDsO0e}X40nYXFi8D$6lP(ch8DG_HC7d z+6g^zE`*rRHplLyl~QjS<?hMiQZP0hoHK_24V_9WctYjkEY~y`m+!+Eu^{?u#h4G! zrz?D)D16_rC8n!5>c+Mw!htyE0@|El?LHZy8~=Tyr40d&2{gfIx~m72)5OFoDMoX5 z-q#<4aLu?u=ulnG>X$vGFS=;pji<=Km4)wwes3wwvu%%p8h^abq8mDY2Kme9-k;{? zGs6veRKgTNu@m;)g4vATp1Q>Y_ju9icXioK+2t1*_{@G!Eu}Jp)4j(w<@7Dbf>_{W z@+&~YPfo{sc5tcmewxOs{69<#fBde4kg@P5C&Xd4a%M-SH0o*%{$A&|?3eMusp`W5 zD?zLcX~p7#v=E|&M|_5D`(AzrN}Kh7sq`EjZBPVc{r9iEYGr1NlVJCY!LuR9K+B(< zc<RQ|yf-tsHqrTrxBasuR$r>}K&OFm>H)5%ln_VB)QtVGrBC-yseq3B{@?BR3OSkJ zAMJI+*OvgfLlD0mUMiiuZCA79uB=fhRf3YHX<Ot&joB|`P|0WB<K|<qN#7z{U(gL> zX%pEtlzC(Vfo+F~h|PV<-=RC$LB|0uQVqQo#uv`T`LZOm-w%+uQqti#;S&RD-a}rb z=XWrpJ}np565qLrCbq%UJMkrx->=GreLa`?4lr=8)t{;vehe<?iXF1Nq)ERp5-K}! zdX6JS&e8vb7NlvEI|H#q2MeR?jNanfX_0v0s(^Ag-=lB$4HuJc-)?_+v&Du~Ng-z& z_YjzeM}O4#9J5Ef+xP`3hE8QHYovo3_I$VI154i>K3@-9(-`_ysitxSiu*t5&Ul#J ze<Pcfm&(~Tzg6SNV5xnk^P<~b$ge>NY9SppNEnLCrm|)nUGDpF7c6S}`Qi2K$Ifp} zc-xy2z@ggyO1kk!4he-!?X8>R{_nsnvBh{O{Hb(`2v~AJ&SPeLW1d*y+}fRzB`!D- zNd$(u3?nIQvT>$rbrP<HheWbjj&yYGno3=rj!|Jue&`%={}}WF{yp17!^}NnA8R^B zK=rAGrN(;2)fJaMHC7Jk`VmU{$d$jUjG*IDXBM1ohMVS>YK7ZgLYa7vP`w|>JBXcA zhZylXAZfGZ=(Eg{VI=1th4{h_64n+s2}#H%o_nes_S8V*9+;}@1nR7KU)!~ffJ?35 zR&=pX^-qYF!yy<6@SP43?KnG{SA82CFf`4t&mE33|0rn`#v$}FC)!DG-&{0y&fGy* z&*M$eT5tV?{A`gc1T|K28*4X?#mRr>r7zzFPM;S4?DM8fhhht*fd0sMN{Dx7^&-j- z)91TM-~Gw5f!bKOb=5)HIjTg(VzXjF;@AfKZ?<lwgt}kC9FwCTYTijTVf_^>HmG+3 zUS`gcLq4^sr&vY2q-TJ#<El^`M=)w&(S&AdoXi@NfksfFM#vSioQV&ZYciy-8HE9= zNJ{n&bmDT(^6>Ixd_=9Sc)gg43q$_oS}2AJ=Qj4~A51nV+LgZei@*w}W-7Hc1@iEh zC%0z(7&NauvPui$1zP3ZEmpBoDk(ysBC<_7&P9D@uwULP%y#s(gWF6;e(4#zg=vP` zg70P=uqi+qL(NNaI?i&9@nlZ-FRkgzK)8Q?i=d-V;#hC?vLIJpWR!6pPmmYq#4uJn zNQ6HcL#IaS_ZxC9_IK=ohl3usa@L!I>`-t06yBoI{ud`)t~_te8?~Yn9--V3-Q5Jb zvdUs)M3}w8_TegpO4f;x_&YcCo^9=s4@48z72DhHEN%@EV&a^#Fao)BZ*o}qV)D%c zqt~|4zA{KsL$Uq<eD-0~a|`{WL^!(yhOZV8e{+TlyB!Fy<%|T19@bEdV=b9_#UD)@ zUE>eQ`hB_ErhO%cRf})(d&y62T<GeVtJ5!)^9O5+u~P583at!)z(?2eUFW7fuw(C& z>gR1Uhe>p(jbm(}73*$X#Y?^DdR*mC(pV3_Kj(|W5U1=jr^{P8Bj@iGy`DAq7vo7z z%F|j1I5DuA@iWYiYW@Il;Y|>Uw*_^AuYdQ;p-v1qA6zCHE`x12l<YtwU(4;I??B&) z2YiWRqxyXe#&T9ehJp|zCVh9d4>ba#DlAAK@7S1r&(J;o7@P_g8r}DqmP&_2Y*jas z6Av%D9vRXRJ^6Qu{N$e!c_pd;l&(L(!vFv{^&qJ_0+Z9%@H{p$CkD})=Ydd}s{MeL zeEWo=`KTACl{#U1nMaiQ((nlYm>yOHYR4ChAZVoUdgBSYJc)RSTTbJaqorKWi<GKa zi{LDO`O!6Cv>L@Kb@>wAaGn9eYlj$YIwRROdMvveBK~}3Ma9az+uOq7+jbcF<`PJL zp#^&8pk*whF!pD?Bg8HBC>KQR)KRe|ZY`RBq!`?!UJ~7}I;6USV-#-iwGJds^3rlk z`-o=vE7cDJ-3SA6xWJCs!z0-jUs927>^x+8xH3O_#~iZ8LL9G4n60zjLup%hKkuyA z-`%bbh;8Ii6<4-Hv6Q8?E}P`lMR@BVi|}U84SW~AN6B~pVL!;G{LV^n+c7z|V3Z2w z-(|@m12G9<Xx8TZZqM;UZRPiemAdb!<1A27FFmZq5kB9~JE@j&{c-#=wqEqK8~D=o zSH0?cv>_^!tpeh1&B?Qh0QI%+M+$34=pzNIPpz0L4kF&lcGtBRU=Nf0Zp10(*A|O( z&A>!+q2MSKbsBZ(s?{R%K0VbIJGe)GThIH8{kx*C$zT(2{4qmm)%%U3sWBexP!BkE zojb70Ta>g?tq_hDkqBytpu3W@DD}m8YFnKLatN=ocq6vlq3N4}AzAxWXRagO<f68h z==P<u9Mf2rlttjzaDZ$Vpu;+4d=&Q4s9>nSbNlXP5|nLL%!6zZ;Mm(JNHw?5AhwqJ zQbquc>eI=&WIejUEca%G4ApYrv`-t)2hMIY|JN57?>;tmcdXk4WJ74WNt|9MZDuXA zH~#n$`3TK(GO0O_FlU>Kka5JTdswOZZiRYNb)Q!ad|@r!WHPGu_*W-^xXe*6%XW>G zFiFz6ljgl75S|h^IlJO3$K>w6AQZRxk#~M=VDASASHfI5U@d*?06uQ%@CR1&X&eBE zgzVW-e|GHkqL<rox<OmaLBY@A5Q1u%Bzvew0_ZgOO!>&^)u{x*{C4=zD`1g!|9<id zRz#j8U)p^FkbxC$7{W^)(*KNvI`SBN`&&gkqJUTM^E1`{{g_AB*CS0Lks|edRB8>+ zuD~s-b9GF1!hbbAuwQV(X2QD#b(>Zle$=hWqYR!d(1G@U2QGgT_aIbRgb-hh?}bkE zYa-*39CbjN&qdWaC{uJZh8BF}A}wW|(UF}2Zb^U+`G=cIaJ1xu)eDqa=-=~-h(%&f z6|!-(uRD_D_0%NutVd_D48{P8l*IMiVy!yi<MF#7hYz0jU1G<yP@{?H<qzsiJrH;f z5ym%MK7tv#6VJzWa-N%AOiwPOip}SZvpzTl8}uv9r<%r-yO@I8kY;Ho<URW-#oe~R z4!BWHcc&GU=#4ALpTf0C=TzZ_c8bp#w4)ca*Csm-@a$_heT!t1BU%eHNI)`0?Y~x( zh?E40huwE(azRL#;3Ly8$W5|k{c}Mfr1Kwsqi@C{%dk~%ET<0~3knq%d_DvBi5vs` zsHPThq-OPp#yRf8ly$u5AS&&Z8D#>E@tg51NU!dFTPudxC(Kue#cW2ZXf-dJDCfUE zv&3rXK3||xNiue}+$;X0>h$LQjRh+C#rZpS_wk|%d*nq>Ba?uHnIWE%{!bIxLK$tV z2xY8{i}4CG1Y8~V4E|@=d&YNy+6DOYb|bY<Khd2-yqMT~4B&|xMf~lFIo#h?_P*4E zI=y@qy;p98#&pOdlpQ}0_~^h(t1ib+oMsj0P!H#oNrWDGljw4MLQqQm>RM5<<B`nr z(yTFqF(w+tGzm%lkkgAeQVbtN2)|>284oL+B)ml4vIe(`av(p~c7N;z$ZeYM(gE9( zo3OiBD0N1`lkk>}94<=6-PgcVBziQ9?2+Hz;na)7ui^+VJkh8w#yv1M?1SwVK<@Wr z%NDu=zPJ!E)1&|`KH=xuL#wCy<y{T9P2?aP<U`rzxM&8DG5;7$$4#JFJ}!~I!bHC$ zOR9WD8e-DLgyI*ZTCi_}cT?cJ&e_X3<e;F~9m4c>fku4w3&R8dZAGaBzSW3n%w7QJ z2fGJlGA>7*h{A|t@Td&}tsy;-A8h-B*S8Y@_?E3>4)a6T>B+FBFL-d3GwjW4%tz#p zylejeMRfLG*n1P<Lh!6nXW<mbr<sdJSw7s^s2JJg*GpR@^kBfI^oMrkiVxx_^<<|f zOHTfM3%U(u?_(E>nAJm0acN!5jZV&cu$(yW#iQgH#H<|@gTEyRTS7&JZ?#{$hve(v z`ACTaPPvg^yDL&ncouS971*VuhX>u(0oHH$mk8w9Yg{bWs`G>eAw_4AC=3UD2kGCi zXV@P0Fksq0b2{U~{(-9SnutXNwbXFZ&aV-~0el#nP9CO-V<y*@4R_I?a*acvM3F1$ zlD2`BQ7yt7|I|mkdvu9M=MidOiS`pSu@Q~;2{;hjn;dXX6`VOOISv2^7|efqiv&K; z4><{<_tH(7UBs2z5V$%_`m7h{jH%Lfvx0YIy$j~-AJu&A@IdA9=Xh}JfgwSlR(}Uv z?NON&jo0*i)jju6%Ywsv2h3<bHS;v$g`LwZP!3s|jbW%ksaU$`;h?oBgGSDaKi<0b zeefU<5Vi4h3Xonj>l;cYI(9i4Y$>vFm?)e4nv}AR$(jcFfGeg>VEJMQ!=JRi{;B+? zar_Yll1+4zJhEbUdBY(6F0WN$)mXMS>a!DNIOQ5;bc26y-UaoNo+ko&HsM|R0Ht4$ zxdBA8R#7i~K5ix=*?`IiW*4bCxrlezqW-zBX*W4YrPCW<8E%Ap_Z=#ZLlu89(E(`Q z0grdOH;~S6urAzD_?(I2g8XeBq1Jp|X#*ZbeE<^bt&rpM+bj!XZT&t1<O)W2#!93L zwX|!6vIJeNbLo=Q#rV=)Yql8CwKNh)LKzm>T`{|qrPJ}vkz)EnqR9vg29c^AN8_9H zz~(<RRk|79<CBZ|iW9%Lo9epx998$~>}z;M)V<<Go7<*+tnpV4hJ%9Fhp{_rq`XfX z<^X^Iym+%`If=^<{I~Vb#>)`dclJrBG3qI{%hvZ5tpq5r`Kxut6#;jI?NKMWPgIwV z!j?c(nHKR(fVEhnyZ?)gM~9lspR1ydWGkn%B8Wx#Zc4kUvdCXe`hN{MUWv}t8rQez zBag}6`;KJ(sNam_M=LD*p(C1#x9ynzckSeFG)dta4+d~b*RFYm@(3gPh=INxi_|Ek zV4rrH&6hi~#4(ZF_~FAyb&iIVJ%yELsHu7lhLP`1w06p8baahWJ=tWM?<9(lU<P$l zT$!zq<Ek3tHa;V4`+DTZK5r(a^DLF=O$zXdj_@n-zbHY^vRBZ#yr2`mJhvQ<<U<>$ zb<O>&ChaT924hC%tsR_p+7KbjZ66oDdXGNoG4h`00porClYh9Ivl|iBLE|dUaZ{E2 z%_kD-qZAnnqQnSi8cs1+ZCA;Bj)2qBTe>tVS<!ER?VQ5jOV7IA{kBU9NwP|4B#V{* z@iF2FITyb07|7WZFiY+B$rn{vM8n-3^>E*??||0>*B8S33BM-}lgod=J%d?A_piq^ z8NR%(d5sRET_}j+axdBZ!9WfDzRwcE{m1`l#qx_isDjtFqb8N<ytI^qjHpRL*mq94 zv+Ebl(^A+zm#Lf+{p}jNt`vVkh&4Z@MV|y$Q-I7Vr+{d5@c}6dDyRf&3{(=dMPz>? z_iH=}xz916zRlwL&JDsJy!X$FYq7xu0q1DVuM2(y`p^~uXA-MVtAHV6Hm4uWFRnaN zMyZ97e~cfid>eVP^vB8=N7A+j5Z)Lpj$@ljvn|YWoAc6D#ni%46WJGnhzLi+Bc~T2 z$qeZUwEAqk+Wv#MqlZ9ehVEF)rcplBaBn$(l;k*)Gi38Dni@dpW$gK4+cmGhXxji= zJmn&|(-5;V2~}tZ+@Zp}FFSBZq@HIoxpUu)gSvU|0$`b96E5%W@lD>0#+BROLkd2h z;nBM00L6B};6H@AO{J2F7Jkp%L7eTKiDrpisC)xd4n+4qjh*O06UK{1p#O?FVp01y zHhowS+&;iXb(eu6@-N~G!FbZK%v73{zZ%@7tw@JWSD6<%c2G02e!~;dL}A!3IOK+P z?ShXuWCUs<l)PJp;u<@|<zCXxzW{lvt^uq?QE*ri>J=UD&Z?<6$z}}zV?X7TEp!MO z?>tzJqOkC>TLbK~C2bEQb<?9-;zOCL8Z&@s4KMGVNkGx&O?5hJd~Spevjv@P515-P z8W-c_ngya{ai(ET(E{@Pbq5-50acB{zq~OYO~HpoF(;;6GX?i1UWo+HGw7j!9bV;x z@qlEfMm)wP0)5E`95jt36305<7gMtqBAXu~x?O3T3{W9~j9#!TueVb;6blqcVC>~n z$pZhW@;sSGSF1pfUeM{4BVTV*7)J~vSDItD??MFX=(>7L(ROkE#9={hlX9g~_=Z!` zmR$;(ddo9kknwsk2R|nU-YianLm9moz`1oLd<r(_dJ4)`x3Wd36pdRY%4IoF^*=&i zV^f1a2Rajv_pNh9yU%ywM|Dd7shF$+X*@thhBfrQ75Onze+27XdOrt?PHSoWKI=Sh zAxesFW~=Eqd=^I-)(IiE*ae-ZWRDfFihpV_TdUKkt+_>Xdhe^@N#D^+1{vjFj@wiC zB7Z9y0H@eH8ws9+_=nd<bouSMNIYrv@6mw!1Lng{Gjfy-w~|q9#oox@L}2rNH!)Dt zP<5wh^BtlSI+@YD|31}Q59N5uDlX#}wSDN6E6($1-wskWqUtZO9d?tQm!E2JirOkQ zLK|$tc1Nfdx%w()0Ay3m1*S1|P}_1q;>|e4WNT6(PY2Gt8hzC5`w*-)v~`0pu4ClO z$Y}!UqmGN?wPP^yM=aNiZrE(G$Mg-(G6HTIv8HhGUMVel<r8WwBLiuincE``b9Cme zVWlJ8f?*-tW}Y7cT0_TCQ&}o>{G#sQdb~FdG4Cu!0@aILHtJ~y1*?>g*+<>1G%C~$ zu-n&H%U*!(cMjj=jrnfp>(C#vi(sJqSRcj!Cf_(qIyOD;R16SL@4&F)cTs6ABngZB zo5>WDGAZ1%FY~W#fq0;Ix5>>mGZ&<PXJ%;m;g!YyTt^y5ajrRT-GFHFn+I2dd>bN* zJ$akXz~cc>vS=ub0?|$}eCAx^#Hl=Vf;*nk@|5COT;{oAH`%-AZRgylx#j(8$tt&m zje5o}PFyQkYPSLBN84VrBjbXau4$td?piyt7|$d~15KnuN@&-`QHTG8>OFTQ@p>E2 zz5aFleREI{gv`!~@Q@m^Jtz89V{C`R>Snz9LmMvK(_<NcB%HMHl=|HyjZ$EsGIA&} ziW;B!U3<z?CGuD3i7cXi7;3J2Nrs2zYR^HzV`ozA3b#`2=+7U;0$JKZ3A4(h*|OJz zc~bMks(m>}W(jmh!`0|9P*cNj`@)MWcexJnO3)o&97>-jZqHpaCU!j|i3Czs%l~02 z%Y1P_Z7=o~L?=OZ)Xa?VrnD53H3d4Lce)g?Kmi+FdL=#f0&)m%Qk79{>F_}@td=_b zRHMDu*aIZYa?ZRjM&6}w-D<)E_4l9=wo$bjwKDz5K_PEAbsc!_t-eogyfri<(Z7QT zkbZ}3EN(dp={Aj-&}vJ(%lwdRgFY=p7)Oc4#r7~f2woQZ*6#Ug8#z4$nSXB`b06Q= zF@c7Bcw%c%)_Q*|K3k#hFy*_piGoj9#aHV$mmKYy2Fp=rMY+5L(wDwj$mHE+C2N({ zHp}0QXE+=&A>0FBr9Iu9M9Nb_Vov0Nkg8@U;++2WC@dg#Uvom^t5cm>xNP1S=tC+` z0AB-Bzk44XLhkgkwe*n15-Elevb~WM7$uZ0Ep)cN*?EU!y-WmCOI`#Zaq(_FH_^8` zilrR?s8*bQt$&2Rhut+`;eA8c!C4~=611=5L8oES!x>x<$D@Q<f+UE4;hyo30?{t# za?0PU`hQsI_}kC@)@1j`M99*8lM?Ik+1b&q#U;RUCQ7T)nl#&UkdH~DJh*9omnD#D zYY~%)fS2~2JwS;XW66HD;FXAu8aRP!u>}u6-vV%YNsdVsx9*5;as5oon>USNEc8l0 zEK<Sod^}4FZ@)8bk!x9tbKXN-^2E`z4)(fhv9(qyJcDX70$Kt%D<8tH0ENaJXYC*d zyxq&UwNq>>i7(9HZv@|r`7d`+uutQ8lDRtNRN++LDy+EMHfa+g_4XKc2!kwRk9e_e zO{j_;N<bI@XwK#G&Cl}}%axZL!$4x)y_(n2EQaSgRvaf2t&XgmuiOr6*S=Hu=3Kv^ z2~lkvGN_zA2A4Ta13G?scMvu9dV~;PkK11q?#s9p^TTAkx!!0~b9_fR#(qJmA6+MH z<hGu6bh}Ik4FLHCgkc*SA_Lt`PF>-#_SA{%pGUqlo8_N+l>)Ky@V+a*?A=iz!$1L6 z4IqN}E-wp1KPCQ}|BtM<jEbXcqJ=|(1}C@%2@oK-JA(xY5-hm8yE6oL*C2ztB)Ait zV1v86yE8D~B+t9<y=#5H_(8Ak=|0_6b$0E&>yf`HRjK{4Z4ahyQSb<%O63w$OW_|3 zoNFS-M19N&H+w(Qr{IHl^EDc5#c#POGOQEGXvD3>g*B`yXado~^M2rV$z7EVxS-$1 z5|%ns+qqJ_PLY(Y`S{aB-`a?GsSw>IuA&JT@W`Ei3$}vQ<(2m)QT^;B$wZ-;0biQP zXNVfQK3|gQy=27tdAD=q0^qAQ%_lyYGqh7-Nk8Z9NZQVc=)VPXqf=lpUJPKV(Nq<4 z9*|vt!J9n7g}iQmQJ8yVjDDmwS<;*q;l=hUiRaYK(%wKswx;ZUgKq(e^Li}b(O0`4 z$V%^&g<mVWN>f8SH*(Z}<B$E;_#yg%eSU2MIhAS@cZ;*;YPx?7Sv4<7u)5%a5$Z$I zpJ$ooO;G}=U?Tk}(lgtDNMzOgj-p;JDUDE!(8P?2ylFv1KgKK*-o6cYE>*_@OW4cK zmG`CJbkIC+^luHr(&Nf0_R+entb%1+VsA@e`_;}4b>L4+&KRL|7)g5*>0aVoctYhR zf0P=ed%G>YqWAoGa0iUTKfpWyP0E&=m<Iz>ZfaBV3f|wbyR}C0Zh}Ug!!y2;)n<RL zxB+)J@NoZTwFsF|wR*#6bF(YPRoK$Z2YnHfJ(vwyd)O;qNB7z~J*FBh0-YD~WAVh+ z^!@n$<aiY;#6!uS$w$ALjA$8BGI>4zG_g+}mgTN$iF3g<AOGzgI4>bl^&N87ruY}r zO^1BPK+~Gx4W8YP9nAQlr7xcMNKI!?leTZ15$d*8)f}QeHpPy&ht_`=j2D3C-sRn` zB@4i5?s@-=7w05ys8BKVRunT_`LOo2I~7kkj$qhR61*CT)fDpb&+7n0w&I7;%l1Tb zOvSA_zjYIPPtrs2j-~|G@3j<F*bmISul5?N&8mmbO^PY({#1I%H@nqkjCfeRTva*@ zvk^Mf=~TdEnj*sk6bg=|?5O<8GkESBRS%jUMj6AzCYILgb@l*lkP4nZnyZ{Bi^Y*W zYKK7s%u}j23$VEK3hw9$!72MS5gw}jLxdIbBhO-ItSM`dGn;(0@~DX&W+{0AgEdcY zBtO2Lv_*@7+7I6nu;|WnAWL4KU!BjbI|j2ub459<_xl#Fn!IO#NTS8g(oO;?J3wxW z(2pbgt*Oa1{m=Z%(}q+oMcpOi2&W_`CF^+kPnNBDj+?4T9r(AqcRzfDm3Q7%r}jH$ z129kxAa+W^YfBqZXfre&@M~~hh92?FaCAan)%FTM=P-7Ws|c_AjW1cHMk+rl%?ya~ z@?W`@ae@tefg=MA@nGNk-ME~xTR$CI7AqVm*~&dp2A=n8eaV`04pPSFdrmjZUS3Pw zx8hY`gD<|cTX{-nu0(#EoFp0-iv8@jY(Bl_h729GFAu&tKdTRe^?>?BlN7x?Eo)oi z+~i0WRadyzKFvl>Ki+3pX8%shd0uS5pi}0~jHMnG6@2=61Ul<$q7lJy-Mf?3Ft*7= zHTRCOdPXP2!l&+zdKCDhI0h7I#i}POsZ*rt$Y{sF6Ir;-xOL_&St-ML=NK$p@Cf*D zw9I4ML9;_KFP8xZox|M`_~bvKi?=IJ2~`w$PU~F_nV!@zSyx;tOrnnKbQ**$MShu5 zdRVyM0t}GEV*#{YQJ}0U0H62QKuA?9P3<{9e>OCzt5;4^Op46eE#F=ebbdzhQR8_u zmxGNa)JoK`BHGZL6X7}ApJuZ7;8W*00W>yHfqNuxn*N4y)ENx3*u2jIrik<C2eTxe zTyw9430z}*WA0^AcO4IDb<p?hup-Fk-1WdnJ$hbzwDXvdQ?oo(4QN{2p;En+($E)l zPcLF`JZi_N7ScK}+u`YJ++r2b+}-lXvK=S4b<HnBx9?@+_l{&hs_7uQdk^}pdo7s- zX8XKGUb|8?#V99yyQF&JT)FeheHPNKn<14GxG=VNyn%1=2m3y~a!V(trD<Dk*Gg^s z<aWL+dUBauV}HggmX%qlii|{&M-UI%{Eqp23GLFd7*g|MwAb1~^zhmK=W&F4zHx?q z3QN~79aGlN4SgSc>h<ExJ*T1vNB5~FClPJE^UW$$1l*j*c)BOoVxVP#sXvaE7o4iC zmC_^C;tRn8T!qX>h{H&cE#FyAd-a@pk0XE0&1BOLTf3+dKY%^@vESNzX6#Uw#8W#h z`xou!EV%G3>I;_$#K{X4fFk>wbzRpNIi((WUz%<D&<UB<dvL!ft^Qn)BKlQn5gJg{ zea|w5E$vlaHr7b_-HxY2^ufP%sIY9PP`|hZ(f-%*$ZG;)jm+2i?+P+v+m>_g#DKXt z3q6SL8z^I17K*UgP3d*URc6mFb<?b_LUBS6i+P^(iNNW`$~e~-2@OhoFK;g0HmtNH zcWu_FR}@8)Wjp(TQ)qND?rK}y{OTnCdC`ro%ur!U(o#HMoZFeX<utlU>X^1c42kn) zbRX}~nE?~IF<18Rj7CEMdNWeyd#WnTY~N3D2w(wloi^BjjvT2*_U?$M8Gi51Wk>!@ zRTkdMr_;Bt%_5W8`mA~ROFyu~t8sV!MA-CwP#k{WliS^e{mY{|SS4MPHnFs*sHm;2 z?Pm!+OQ$Go9$o=Zma*^)9Y<|}$=A)=K9NSkj#EPnBV(gl@$B@t6sZA`y%N7pNOa-^ z33+d<Ht?$-a^^`JkhYS1feteK{uuEBWp7K*9?h=-IJ&^FfpWo=MJbidh1}}6>qH)N zq$}UA7vi{Os;_YnwFMW1kru3kc*?6t;?f0{2e47|jIUNVo(?qDYu=CIs*%Hl0-Lz2 zH!Uzd{pOPXK!$u#&E#a}a@%G?!dLW3S<A#EQCZp#DQ>wyHza-79B0`4fER^YpfHjO zF5<TrbuT=sC%!R~dC6zF_U}z7PCj1bl)ZF1VM^to^4AtvfG~9O-_<X32f-`v8{*eQ z=7-JV(0Lw6x^X2oY_Z*_(T2|`j-y4iN`zqwiqF=4)?e?!vp0WL0}1*2OxTm>W>aJ$ zsWOMvIA2-|Bo<XQH8j5JeuDj)c(-dOCX0Vu?<1J@j4^jXq%rtIM?WuOFf}}VXB3CI z)2A9&$O%Ib7HAv;JEU3(Vf=j%7RlhdwzFx}Rxumr4jk8l9rD{hj)HcQ-%x-hn6L*i zsde$g$M5n<diBtfJ^gKM&0NQ&>`;LWI<1POj0{X(vGtl5!38#w$g;G~a-ea|?in_2 zFDS(Cx-xrLejk+8_mAidsQrINEKp)>e#&1usHT8v>{ZoOE4&X&5j+|l77Ju<XjMFA zWP*wA_Yf05mYRcuJvOegJAAE=4i!LSx0grAzW)Rd-h`Bu@UTtg7}X;E*-Gmv6UHSI zPxsD{H=65O7oD-6^v2E5(fP83pW)P}`@(R=%lO!5cBGh<FU+cVhJGp;(u?Od;-^7} z{cTe-sTb+-Yw+%ga#tzZdBUr`S;qfl922mg_yl4BvZc#QCaaZ-hgK07S%+c_2Y)6L zXpj*z#&=2dc{wcSrEEa?wGqLnz@n|Lsz-TpKa~0g=8o9&@1|eF^rhz5Wbb2M7<;iS zW@-~}d2eHb<2q7KMAIJI0Tq(R){J)8o3=rcWQ@IM=ZEq<&8lIY$k@yhKt&kGr5evU z!tGw@MLK1GoTXRebVho3O-*ue7@qPpIF&YL3Nh<km$INW^2DOwmsfwSHTC3!$J(+@ z)SI!{Ju}Kx<r!%$94wxD`3<ACcb*|w)IPfZ1SWMDZF$a1kejKSCAYchX<Pz=xpa9? zm15boO?QxU%yqPYX>S-z6kJgtkplJ>es)R5lCfPp?%a%+JXtF2g^e+rj0x9vmq{NN zY4xxEf0n|q=tw{*RZ&ztE7&E(C!4kxhqpwO@)70Y6LD_@Gr)(smlD!;B1XyV)VdGj znImr6)hs<g$ef9b_?x%*;=o-12~@VPuE&ba8Wf-0Q7;OyMBcKYWpjv!6#@iZ8r=9& zEioSi@hW+U_sT_9-#xnD)wJt`Nnfn~=2JMGhwbrH+XU>R%7np98Wi?aBCVQ{1ET*l zNT*wPS>6lpC<f1nY<yY`l$E3ZsFD(UmH0jh?Pa&hh9z|c9(^g|PqYMw!U{4Y{Z_X> z8v44wyxr^nsDAzS4Y7cX1$fyrdkP9nh>*8pPw{%M0{iM=qMt7>4^A`H1*38VBQETW z1S_1(ZTUazozjaOPrGA%W|T3;#5h)SWt~xHU0^K)A1eOe6nYWB)fkG}a?4l>G5z8{ zaafGm_(l;}XT}QE8FkWh8t!uflpdoQrvN&QyO~!}B!3z7`@h@|qd)DA0V9jbTf<fD z(y**^#_a0TC%3LZzNa7-f2SydO#(Ctz4f=0FSNa8Z=lQgEI(U`YQKV$l*>OEg)c`L zTORPc_XZ}o0w59P{VGkzpr!ob4{t9>n86&_JkM7T_vgte<y;xtgXD{FC&V*y&!jTW zxjS;1qr=fn@==p6VwKEl9Zou?&N|8OT19gHDvcyO{)o7H@02etE(UaW=WTA*)WGH) z<S`_c@={SXs}%cY3COu~TXsIXt=EDJsvnR9TzI`!Tz8)CG}7b?gM&?Xb|#r8V<u0( z(pD~sXfK&7CE;$HHNfJ2P#w+>$W?KfzD!1{Eg%T_qAlSX=w<1K`b##f(Z>_{rCa(( z{{l^~i(Hp00j*w@dLhcd4@Nah;pt)X7%cDx{*94*C~6-VRO!-d3b^h%D;43(&vV2% zbB@GXVSB#mv@>@t#j0g$wa)vG9Nr*$TPAsTM95Q+T%9W-C*;<?I#0!Nd3x8Pt60uo zEjsQWd)()L;{h=TJ?%xZI&)$7jG>>-bcw+>s8{2-lm54p=^R$B0H*k607P36;MG<^ zU$<J!x|-ch25Y^PUvhYZ?I8HD2Tcv=HF{94Jusp??eR}B;0r@|dtp8>Sts_R7~51* zfKZ{|)JUOr&gsa_htY%Nxd5FikA^U|+-Y+_#|rMReCyi=Ue?pHw8#(nB3MSs%galc zl!`!o%OGEr@Ifxd?bPR|^IoOx(&_&6fkP<9fL%-J=6Ei<rHYu?mdQZ^jwOMmwB;Sp z=i1o%4oqaVuw0P8f<OL$p7~bOGfHpeDdloT(B|!-Q1Zh8iv-H4MG<{?;f^^(_?Z$k zy~3DD*V_XSjBIsXN(?U8W#}P$RxNa-%8e1}73@(+bG*j$yCsk23=B#OLVoqj!u(37 zR~V3_z5DL9KBq=lYVxBz7L{fgg##U<GhSPY>ZXHgvY2`}`q%(&)2}cp?`Urps^cgm zs_y_a(Z(cxpN2fHs^1REA0;BNSO9_z(jrjFFeXZF(b6o`@VoZOnLQLo_~EanqnJN? z=gMRuWL5bc0LavzvTRiEE1_-0A6Ns}YQ{nAF}`8QB<y$elJE?}S3j0pHWGk{@r<kZ zd8r9t=`tVq-D=@r>g1~jay|-|RS~%d!SGQ3Lm!N9k9)TzGfQPfPZZq{M1wnmUvu^V zQamc%us&G`dh^&WTN?*N&3#7ZAb&`D7t<mWXaFc0alPLw2S8+0oOPkga1#nIp_c7m z?|5^|z>0&1wC2Qn!lu<gdNGm5oKXs;nP!g5B&&H9R~>arzt~w1j4#hAldnY#2b1>> zMPiD*16d(v2G`_;bsNqKvzqV44`e;xnaV8q!IeJce4V{2ITWSDKz018mU1n&{6@_w zqJjSC-OjxC#@PzYTMvEgSi9`@f%K*sw-x&C<^f?1OJP&RrtT{!*3hN$(o-cFOu&1y zyC$;|*q$v-;i1Au{hZ@wTYO-jF2#H#oMHM$FhF+5(kma%y=fa{-^G{Ub!-{L+CmN* zWKT8XOr!0U&17n>p!{}K%1%4~g}T-BAh3g+3r!ha>^tv>NXg_h$}g2<Gn{PHk#6L1 zd<5T6eAHg&bCalYYX`(Pj?q2`mHMK8b&-|i)%(l9+kI>H^crU;lIL20vYuY^AJrBk z$;X{kP}AkmbtKDJ(^kyo_V#2*$Yz`1M=`bpJbZjv0ohiOt1e7f2(kY5Lkub(wq`&E zefZ+xAI@5({+Wk8y~(+G&AR^T4fA(W^03wh>6>oTv<K{6+xJ0IBteV!TG$d`D$w19 z_>1Z?-V4U$nF3`%P9VN`)Zl0LaXuwdv&b8?ZD-okyPe53{{^|Az!v11&1wLe)QgZ- zi{$6>bt?K^7;Tq495e+tWD%4NROnGDYu&JF=}EK+`2HVjcNuU(%VAH|^LF2^xC!f) z3mZ_4HY{V2{tP(oVmjhUN&<g88%vZ_!8^3+qbupL(Md)PnvbxF-Hh#!<qW@aoHllB zyR7R`a}Xm^c-*_Xm_l(CE>HFud3g}@*aA)bER75DHuUv2>^+U5{D6HVcM&w~b1cJZ zxx4mL2W5)@E%igHD{?JcXV*jW!>eM~D65xkkW%|+G%xjim~3L5n?S5jd&Zog|2I;m zCCELvB*c>>md?F3X>Au$GPL)0+AU(ok?gmHjbHy`3>FumjkICPnOWEcPC+v|o$6r< zs`4IA=CexK%hcRubD%Es?{|OnCoX8W{@4p<Lv91LPyI2MT}yJ+G@q0j?=nA@a|kzw zz_fIHxApX#Uv@y?K9%g%H2jRBYY-W4Rp`0JmU*FYpR8{T{Y|(;Y8)R@Y@L_pZtXkb zHAvK!D<$#xkrd#yefOJqSwS{7l8L!E+GVpJ&a6;~_ZLl(^6bFO&|;dvi{G%FrH9U# zwC*LCCCA=I%00QN3)<5)<kGXi)O9{1{;QWjJa(;EFvEc+S_yKcD(_@xtn_X{1gU&d zFs!2vH48QgnHY1cRg7sY;7Mc?Rw)C*@bo5{SM(lWiH@C)ho>_qhY)w8GnkLhlvd?p z{#QDgK(^IVgU3)3PGTvmz*43tU{P}MS6P|t(6-Gb`10EPuE$>R^j~rQ{bd2;1Z!?{ zt%+zkN_&@FiAZbuMbm9K-!V~`u(P}!qs)r>)bng$wBxu0^!xdka+!VD;`u6g&=5~y zbRg}}hrrD6MBEN6cHk4DeP%C&J&~G;?$XT>X`hQO#Ev>PC_)iJNE-2wNMJ;m?hg&| zToGvuG;Dq6%+>h&=B5i_UJWl+YnKXM`sDQrjbh5|4fqDI-R0{W9;y;+<S>sha|Og| zjx{jbLPSGwnxApUexVwWfkHIGiqLsAorKTmAJU$$&L+wPlpd|m?I(fed2HTB!UaCZ zn1;BEDAo4`hx4Q0_f-;45L7)mX1VO2LU>3YwqQVW<V~YdoqQ1I6Uw{3okyL*AT0Md zcSmN7+<JYfk7r_-{o)!w$}b2qm989ptBx-d5_ZXW!9HjWYX%KhsUC<Id=O_6!I#8C zh_uVG5Mdp(X!^m5?g&CNw$6mM!b7!05S;csje%NemWx*(=+CGC&{QlRn=>6tx_O^z zLgkg^b8K($Vp}vM;@&4cj~`Uz`KJHURB-ECh{_Zqk_Vm6vz5>6wK#lQ)sQyY$W1fJ zgH69P79R-6_>d;DrAN?BBLRnTB4BC+Wpg2~2hJAp*`*huGH-n0)wkb-bOhC;Y-+_d zQ%JXC&}miKy89$#JN*#>MyEiqV_&6gajZbto{6%>KWr*r?hMKDEnayJ*~<&NzK?d8 z5m}45@DYfKgn_02<O^EZo0ckaA?D}j2Xh91tWgDbFE4Mlv;-{Fa)5>IR0m=ZriuyX z<_LCo(%+@I$G<R|PCh<!6bX7WU2~kfVp10*i$agF8W}qED9|Obg7ho2CAXDeO?zYO zppBPn5UU7}xF*f}bpEv8WKER{eIxDV7aX3IK>T@AZaWWYgOusuG#M^M6r%-##(BA% zKxUkv`C_uD<t2}T%OF~YYE;69z507e2o)OH-TGxZG91?^j3?#<LFY)_aNkGag;?7Z z9lyr(9Q-XZ_q+Bc^r`(-ZPHnnWD6<nl@@PZAffV_+HDJFXTfL3NfCExGW>G0_80P# z^t?+jIB)rekiV+0wz75nQu{n;ctjE_>PY#+%KTgww%WQ^ax|0xS05LUG}v?o8qJKI zYKIGTYu|#^xh_og=Xv@YIb&jU4@As%MKx01I^bM&)C(m=*jv<I=@E60R0pHvOS(p3 zd@l}Vo4@l-HL_?F!-P;&CB^?-W}g#{wGSzK&c7^bRv?^j%o(-k92{qcb}t_g&cwU* z;kk(ZZQ6%_mVhrla)@foO{B9jYGaak=WBswzs;s5>@<C?t$fNq_?5`><;o30E+#xF z!0E`Lr&8EVu_BeRt6W$SFH0Y#eU3&C*AqG7EGq~CCvmxNh`UuM!eTit+gtIj=lv>` zxGRw)cw>hj0NW61k`qy4Sh12q?L8s^O&9$)pVET>mMyt~4<@6Jp9%{Ln>{^)8QwZM zMUW6XnUC;#b|D<>WhM&vdd2@yjms!kpgy5GX>#jP|Cm@iEFx#Z<SHWf-v(yvVUN_t zOYH{#M!+Gl3T70fcFENJiPq3;#i8Vl=1pDjw<^hZg#doCV4iz?@-3s~;j@7EUZYNj zi}e;@6O$+D&p5hJAFgW!CR+EE5H5nAmd}#7hU(vN^#wj>?pc0Ix)WlvT^$qw4=ne6 zQW8DO8HkZ;PSm*ppKg7G>L6a+gjwxKHpLOFFSa3EnGLfBE<$d9F=qKd4M+$F!C1LQ zC8omaXB0kU)Znl3_{m6n(idqqESa4TJK=86wMt(UQm!75BkY5RK0W0Es{jb(8hDR1 zW?n4fE8BpjZ{%}Gyj97Bg{G@wq_K`=J}!<^B8`1ao9~luU@qP%wpV7!wr*=8?trD) zO`r6qvRfGHz3EJYPa*2`1i>Q+69nA~7DDH5z)*nj@TaQ>mPf0g1n|*$c_Qo9O4wYS zS<NUXn3{e7=Cd?p`iu~7(y&RKM280@AotEJtJXW5d_t=3E{59ZguEVjAsbr{9ZC#v z*x#QhOJ%o6k2ROdzo`6;SObia*u8Xg?YiDYWty7)XnESz(*$=fql#+-)E-9rH{czH zo@q<nC9?o6Ei8CpBWeh?1KTPp@<Kw|G;7(JTj-x5SI*`m^e`khOV_{BN%min?_RAo zllsz3)F;tend7_CgKYVMcMmk`Hv_@HNp3<C^sd{Jyhp!`bRcVWY$XWt?s0ZR&5V88 zIc5EG85<L8ka7vF_lJ=tpY|15xh~$*iW4Ig(ZVe5$91K<C!50Kf!S!_=2ry6#PD;^ zr%dPIvwUnss#$AAG-CF#$33_6!Z+A7&2&X}KdxX5&9j~^d`kK{L0*awlnVcZ$1JL9 z7&yI0uQI#iQy~AAQnFJWCo}h@nOgn@Fyn|PcH#vCuf$i1a?qiHTIm-}K)XQD>L6GO zDCK}gR0;G$AJ7XL?B9KHM#B^~Vq4RDF^z_m+PW+tP93J<4KtR@OrW2n$}DAJ1)i+Z z&gwb%`_CqJm{z0;t8I(TQFpzf9sY?d>g-J(0>l}vrNl>P$pN3dRvw0eB<7+0tS+JQ zPWx{ts1~k0(TW1l6M7#WmASkOGXe7S^yK5?n*=&5f|yy;FU>~zJr4@$V5{K1I|6BG z(fJ@|XJ@DG=H{lL;MM=f`Q@;Eo#bT$M4^FO*ZO+#A21XE8^{VjX%=x9e5`NGFt_mT zDwpxJReDRxiLwaLUeG(LGyv<!id|E#8Z}`0_0(SQjI;$%ahLh&$cJrZ#xe`x|1zyo zMtJWEM-3Ik*f4rrKQkV0{zvk9bH739p}CamF!*;BZXH4bH$a^=BLhPsasvsG3uEzR z7n*u{8h%BTq~~B=$3aR$hwT;d3x6h<S-u|{t#kO={T|7CR(FH3N>X4x>LE8tC@saD z4e1=e{s{2pov=h%Tp)jqwA}q(tHVz&<Y3>{8oeVBG|*u8>AV@=q8XwQKKS?4P$}Uj z^h+2t?g5jz2AOv}C7%l)?${=|QdD@q35ZSu!NH^$&<Jy)qjLlqW+M#QwScZlbmmaq z{gGHgb9OD6tCG<g6KI?Gj0Uim)hX2U2S2<MPw_$cnSD!E(7zmMsoZAl0^0xheD|xd zqrAFWQ6xS-D{I9hO%XI^Z!wr5Bya@-<`ChxM}8#hYiDF6e^|2on4Z*>n=7_Bk@;s~ z8zgk~7VuvnjDqFLJx2SpM_is<fg3%El3OtQ3ac^0o9Z_AljlIEAH$qy6r5KPn@6kf zf||M|<2atzC0Xi0%W(=nBez%yl(|{Wpvx!#d-`rN7jY!F0g()S43GM9wVOrAp1whe zU-z{#UqZibT%mVXCX_TRJVvCaxL#S${*n1LT>A5s9F}_Ix!{q}PBE5~(G8k*>&pYz z$a~#DX|2msXz2KmBSRyEx$V)Tsf$}_$lk)pB@HG5$yWv`E{EB}{&B%MGcenJ|9i30 zY7e@8F`(rk_<hSukB^xEazzC>-v%OL%)<P>S_6eWipDY3xXiuZEIN=KZ*s{Bt$?7A zH$`liUxix*Hr{%ngIQp^3JRtC$cwZsoEb&SipN-8D1_-U9wb4y1B==a_reN$r4&A( zvnEg1kUC|U3y<kk<^AY{nK{JS+~ej=nZ93os;W!dt7%Gnj=Z%#Ecfi8Yd6()ppwE> zwj=Sz;S&<fM^hdKWz^B@WvD_V6fgEu+x<vb829@%$D5lqixqaJXLo}`%yfazrRCLQ z=qP`x$`aIfcX!RQg+F~r#DTJ!<kjW#?9{H^n|r?eb-VO~d#)81L<?;r=ZFIaYPLwe zI|CfSGW91D{M&YTSq8+$^0ke<^BRe_fP($LCh8RBCv(10?=Y>n@C6n1;7O5pJO@Fg zzH3I0`&qY%Bu>I!9`I3d5VudYu)wp9IY$W{vwPYDc2ArH$vL7|_W}I~=Dayy;=WuK zryXgpn?TH+h0hotAc}tmjzJWX6QMa<dcE+Lxisov#)c!%T92b7bxc*;(_9)pNww4P z3Y%51=%HKpJYEPZaz@r2IP1cInVh<Kc;!sDH}$is5jC<)!l*@_@X!xvcUS*<!7$=I z>V1#L-t!e7a%nq8z6(Jr!?Mf;goBdX^i(WW7@5V2yOBH`3Sr3OWD+k<j=n}J0agu( zKv9tDF+q+jj3Sfq@5+bkk3bZvm*L`f<D&yAFAs3=1&fi)&lGCF4w+JII#N0QkR))@ zm$QvUuw%anl*my~eJgL@s+mc0z#9+K-!Jee1*0wXauuok(M4slf>nX~-$dd#4s;e- zT}#WWL31G>nTCo=VqghzF*|$B(V<g7prY$>+C;AS?R4pan%d;h77<--ZLPJnbz$!$ zvtCs}HRNiNrrt7zPNcOOL~-}8a2?-<MN7YKB80$SWSz|~*zQ)l3!3J|Kw-=~JCGPB zdT)6XdA$#MTsp;u?d(Pa8`dzcMdku4T9yGrNB0kl0-_+2^A8b1+|arPOu_I>uxLSg z?17tju44skn6lj@M##DCj^y{$`L+CXfuF|q*SBJWl(=vDKFwR*g4LT2U}V>(ax9|& z4mGtc1Q<(uWC?VB6vF#~w%?#miV*QDj9xM#PEU`)mvNOI`gae`Z?V^mRThbj`~hp& zUe=T}s`J8KvQ(0xH8!wt8Bza^LF-sKbDvArHzap?^gg<O?gtu-2kLw-XoszH;jw+o zv7E2M((6OOY}d+wFUHD#T<&GOrK03;l*B(gfETe95v1HXYY3Apwi{vlf!X1jZvs`? z=XUkfmxE&i9g!z5@mr=0=r{S4TFsX4z^}8NdD-;~NT0sdskOkue(?<-rP)Tyw*Wtq z5}KFs^m`HwYEb$h9Whvb=D~yerC%+rK}fv1B35bE^ZuZV^}4;U%ov1DdDaB<Ln2uJ z+&({MJYFi5mkl;xzLsU0ax~j{^eOdm)3;)Ywn?bJ;CY>lOad;Qg!x>-a2&sYxtS`D z>tX4&NA8>Xi^Idi?tlOrOFkc7>;9;Uh1x<9r^_qUw{Hu+e0}{<b8E!>Y;IiRrTHK_ z&}zBiuamn+7%dc1x{4{+xN*DZ`QZR+z%8uOKCoxAj#IKi!8yTQ=TiWi7<&%8<ZFcG z;8(=uYL?x<c4gIsDXcET1H)#~IUmtZH|aiBi&FJ+W%q9-U}j$X#fs<JNU(eXI0X8o z^?M38Ac~sb%p89hNIXF5GwCyy1<u;BZ@obF<djY{!<Y=8@;VS=_z~;tH`S2AdMV&7 zX8(2K;LPeEJ1@c*Htbr?Iio4y#?YgH%7)y8k+IrCl=>x#>W3rvSpF|uE`#Af<#yn? z5B(8V6k*F*bUP8h3yNE6u~4k?Y=zi!D}yCI^{AcdF_IuJN#PyU@GDh6X4R8+WW=f> zA$Y&IvN7+t4d<~saO)6c4^NiXTIs}F)zS_S7bjV^MO<E?8QFQ(rMVPM{^Tzv#(r|1 z_+6}wpH3`W#NL_Z6WMtwKS~PMTQ62bJN1)v0jfREvM^F+2NbUZhqOuGpY>Z4YWTl_ zKP)4q3ll$y_~MKgj-FB2godE2jM~ml;wOHue?U`*QGrRzCNMEAqV7ZASi(;qMOuiL z*M#I$ME-)nDcZkF`tt5#nfo=^f^?f&N1}Q^m>&9>sOD5!^DcKEe)zFOB*(Tm{>$YQ zuiJ@6jq84<Z8E2~a=D1WItc1tZjaMpQ|EeL@^|*w=KGGHt&>it`m0dz-m^yKk_$ga zZBt&}q)Ed62tu%C>u(L$t7M?MnV|Q$5YOg+z0E%&`c)5VmKr0^t(rG>UBeeo`;1AR zO6DjhIm1<x@Ezl@E)3k+SK{%uExy4$3^ig~QcPRn#vVbJ>5sL_yUSraMzN%y__Ui5 zgsp<IMe4c`#=YEgQ&*#7e7X9OG#%>()NPY?Z-3@!Xm@yyX67z~>N7@~D4@+*m)3WY z%0whC0Z;8;sw?D_kodyN`S+|TOPTv6KT#Z@6Y}lcHtYQv|Cl;Y?#NKpn5w8<xAdhf zS6smdT|ri$FoefQr)Azil!KxsGq9yXAnBp}kkj3GN6jMd=mroroZLxt;!tJwXiD;- zrK4qxhxb8Y$vycVT&=0D{j5BL9qnA6u&zK8H<$KKKWegCD%f^Co`3j3r^@ACd!pQ4 zJegmss2MJG@58OIzs)#CyDEl1HN_M9&@b)L@15|;%D~6vaB41T2D`w98f{Rd?XENS z?7W@1^yEDK5q}}mig71=XpR6>KXupvTQ~3SqffdMB6upvRL@SySCphs85pJ?Mqc<V z>sD;_K4D5HU+}ng)U%`~df)zUv+aUc7`siDb*};Va34XpdUgu}gM9D2E#qI}UOraV z$-1T7@8Ng<R|UI5%mIU%gAeB<#zFVw3i*l8LdX{ctCI37ziv0p{-VOL7sSzrXJ8&g z@PFId-(khy<X~`E?^82_KO&_${245L|2vjq!+Pon6j`11i|*oo2#7qgWdRugUqAP4 zj@TekSL<IIChXW=>Hj24*5=1DKL55x|DqRPU^6C5J_N}~|GyJ%e)&%)SkG}w^IwYu zmhku@E%Mt0Px%o&Y5$!o2<z_rAGLYzuUTJ9D9o%6mS(n@@&d6MQ7`l<Ly#Rasu{)q zXDVsV*}>iZ()^$A-oGXy>?dVP)`<u0{Xh0+|J^%aFg^00RR+w@E>@(2vuFBq|JO$6 z%m0$(KIjY;%UuRY#57q%61-2}y8~D*ZOfJ~3dABX<ln&?`Z0{|)TADErDj<%iyZX2 zNi8|H)6hj{4#g2pZ`LgrYYx>h6pJ8VbHt_BaV0Foimum``zrpxztbKEpRTWLhh?fF zez*mpI_}7SXkNIOCwG*r6w}gI@KY}?<to9ZyPf$Axo>H?ss2gDq6<MwVM{(DvLlZ= z;(A^aM(g~3xq2%otFDLDsn#sWl8?D}-cKL|mvM0mSKr=qv%uLa+3Ao>-uc%mQR?Kf zKim}k7XtYe%->;j(d~2d$0E9{uif$gd%ktZ{~no#==)a5L|?ngmxnN!G*vmfyuR69 zotaski-z$fuU@B<B`Si0Sa_aFWMLy^iK)CrIRyi?Ivt+!WOYr1a_;u55{-zRg!_i9 zq{GdMgb!NeZEZ6xW4yP!$z6{pvmUsxziwq>E|%Be4LGBGtS5AQ%PEtRSSSiMORsrT zX=<}<81OB2XfivLW6<y?RxG`x@I(dnIYVU7eYc$S38&C?j5S99p&(-XOC6SR@V8IB zkpP{_#S27Ad}KD1v;LNEVVLNbL=iqFRk)iUDT`2ki6xu0W9gUKY#{yMdQHv(2(x$4 z>(@H9tGB^1q8*t;^3rZZW<yIfma*Q!r))uG!}-p;y#1BZO!Jn)a{46X3*0=7YccC^ z%wr2y>#s{L9bED8^ytU3wx@Qxxhwg-fPOG9b^x{%V~}=$c~Ds2WxZLV%OsShmoU@% zDt+;T1jWuYYUXq3aiOQoSrkmYaFdy^EBPg$62K&dlp;0f97OoOmw)Sp`hy;Q@0(AH zU;iz~HdFsUZOR>b4GH`Qyma}>X^|sq!&)A7&YG(3WVR(sT}+z+k@DUOzVG}Lxfft* zo9Wr9mjyr@$&zI#q_!+!6y0b_<fs8rd1@cjiHy}Agxrhs;RcflW{I;3XhTRJ*AJ7g zXx3kN@S<GBqQYY|E#NE!&=|Ox<}ic;d)$Vu-{k?qXehn9lZKohPH~J_<O6_{8e#0; zVoHB(wY+&3-imxdjWg0Gn{M}wh_ROiuuR?S>A<q+<A=3rx;;g1cHl}0m<YK_f~S6O zvf4EwN@STzN{NVakyDn?i2O@DY>n0RoNK~IfjY^#<(t}-JFBnOV?JpBJ<KCZK)XgL z+@6m@F}^_IMyM#Z<%+6%3}!oNN3GlT?%aY}+cV7xp~bNf>*LR`)SS?@@57X+U}@pL z-d$im@%L}LAAMa*%Xs{PKyqmhSy=iT36SD)*HdK5hnTW3#i09q24WeW?KRz-iW4u~ zyWAb;bd140+bx(yV!@6%Y5c=bJ4Jpkhey9T^AQE0?JbZ|?M8-k+MdvI>LSw){xaU` zzQT&-`|gRECJ0IiG=IZX-{bHpD=D8>WoqJO&p<^RLb$E(;a^XTIk#OCVmNX}*-LRA zBj@^qzMYf(3{^Q&8ja)A(jM2$o5;I3vvP(ntSt+ioXSYJ(<%$NdDkFb(=Qa9-Cq<M zUco{$ERJGq{)@OzI18pGPno||vtOS`!#>ZhAd>+$M*S0bW6cz+J#OnyzmjNq<`%2D zWw)rKiD!pIw0XZt+6@DmG?la!3e}(Xia5)}xvjS)+SSKDPCH4HI7f~0@tjq%{ZV)@ zXH2iy0>yqa-`st$z4<l(8>yRqbz4MR8u+5AF!iOjHQf)uiLCra?FrX!=hGNGH1kuh zXvWq4OO)lv0Nc(P;z+;?zLlg<V{>c*IM9pFMQX^>qQ`+=Ae}L|33Hfhh<NE`Awna` z`7zr}#h%hB_#Uq)GE+?_NN)vm_v)*n$vhmUrquq!9;f_pCrPY9%hukjjG%8Ql~#RM zvidW2>{qnx75=Ag-><OZ#E47P4UhSQ;?1c^cPWxN?SC6e_0Z|R)`c?lm-FgO@A}w@ zy{S^&sYO}5_51RJ3y_IRMa1EhxE{BrHhKM<BS*PxE$}n-9~fPfWqq%+J279}qfVo0 z$Q-Fk-&K=Ge6{STmI$0XVo6#+oh=$oV3Yy#a18tIof=48FMT8RR{4D|&J5&1E}88R zaf=hK?BALO@4er}{yOaagEJNtJKT)4N(RDH2=ysnkocF9KFh8DTSFwl8tdP}1RoGS zQu1oW0~@A0`R9>I4f$lgJwAnLfs6)v4ZL3#oC=SPow-zkGoEX|8Zu@r(?nFh_9rAL zTOAGo3g<2Hrr2&a0mo*z9=IX3(fn8lFf@snMot1Z=ICb)-u>RyFV|!&>)hB!O1nQg z5TzATxrGK`$Lmi&;SUekf@tFoUNyU9Gn_I$b2ug{03dij?3i|GT4P~uD^c{M;v1|i zy;y8;Q1q*K;L96YgR}17TVk)5qcrVSoe!VvL-AMPl_B<&<RNok27u6#Av&xF3G2%T z1sP|G$>Ux{a=+f?gQ~QJr#h@ojY-%{aNCKfMkB(7pbEd<C=0%t3pGM~6TevX6*yf8 z@nmPnV=tgmps$(UlnU`zFo3B?=~lp0MX^GMvKO_Cj^HGjt&G}CcGyy#xH#T%RAepi zyG!->gXKFI9P#(txM2U6wVGHGbYG7(%kVXFLv1vE6Ax+2X)?gT2gjeD(xvM5t(%~= z+0XX1K<<j4$AveGU9M1@_d&sv$6eg)6IbAHd+lKpX-MsgvrEcWCXo48R3#fuLcwoO zXeJUHPV}-~Z{4c;ItU@^;s`K;zxm2c5Tnn&XGWyI@dRZ5TVeqIb6bWDz64Z$xqz&< zh|_B<l%T!$h1`wx5^TMpOknse4rj!F-iPc80`upw>tFN0i0}}S%CJse=hHW=Iz#?2 z`jA#h78Q0EN!cQPVR68xCZ2vpR1#DiceN1lU3r&6_Q!_9#HGE^HWvP_kIj=g2Z8ur z)j+SMD<=*In86hN>!CA&(|o`PSusbpw0xJcV2~0e2UhhHcA;sJam&5xR?c!(GH2KA zYj=So(9R$^G<510dMryNtb+O%VD$b=HjRbVjGV;g^1j^A;c7^2#^5h5n~}=;`1P=% zyP+3N?vk1VTlW52NUa(@W^HWpFqfQ0EwF(yaYxrhzF7!rgDblja-V#qiWKiQF2a*s z660<Q7U3DqDgtu<=7Z{>o}`zxEq>GtL!&JF^z6(GnJiDsox{V}mYNCTfrDlue&m1s z-Ecq*_|OR)8=(1pnlfOD$J>Zr7rU%f%oci1x=+jDo8+Shld~o!fGgA1nsmcJNtPQ@ z9^)befDZ?=p><x_A(lRCm(TuHhTEV$<Bn7OAQwNR+8F8lWtqPYCZ4E<(Z)ISJHjk8 zx5k1TZ~GyuZlB$lnIjOwD4dAZ9*5ZHFEa>HW*!71d~U@nhacL)DeY1iXxs1=ANJ;y zL4|3)wpCzhLJjkhm|^C*jdTNE#6vg2q({T)!<e*B1l>+&upZp-`%u)l-B+tjmPt~( zzCJ!9VgvhS@`oL2T&3Cu(+N{;k$R7>YgQtOtvWUT+Ryxr5G-5&;=|J9oF}nw?IQP- z2v2_Yo8@iL=vS?Y%9fXfeOrIPiSeg5fxM@ndNo@<s10NKcOZU>)rupuLI6Dj+5Fi# zrcm4OZI=QE({pWd{wi{pYa#>4?_TER&3WGC5r%g*%FDuG(>8&@icxySJG~_y1r!G% z1pXZzwE$tS2YG@`ZkwBMU{w$G8&_YmGCh15EuO~Tj4`SR2d+dg2%IR(^E=kldA@%$ zR)O#}ScnzW@Hy<AEJ!5k=LudI14Kan0?)$+*Wb$I{rM#tY0M+vqO`0q(GMT|_aM~s zj&8uniZ4JLQ_WWp_BrxYDJFfTkZz*jXrcR!(%6-DtN-m9C2j1)5xV@U*;gJm=N|r4 z3F@;er1s-Yi3|=PK(LyiG4mfJO&R1t^q*l*O2-)0lG&Rdbds$B)!yIUk!M3~Qhqh# z6ECE|Vr!WdMLEX7a^4jvx(L6q7h--z+gz3jJr>T6g~Isy`T0Dwq-By~B9s{2q04Wf zKape)z4zY(Z^5R>oBV37I`&%w>sD2&ua}quKSp3veZHyr1P8UDrueH$Cp^%$ogD~# zX(s*N6sUINDeXB&XnB(vizH(VEBv=s+uZ*)4JK<aUxY&lu!Rp)pb+w^EE-CxBw>5K z7DjBo?H<opscEFvUiDZ|u{KkVGlmBVt4q%>;r^7mvc;@~!sa>@uolegDc@9H7+BUH zSkUfu<EdL3OD!09t6x1t_gcCIo8$M+J&8chK(wCq{K9uwBHHp?#uvOw7(NVi7cSdN z?+oSCR<rErOK*{45r<KE|Lyfm|J!aQsk^1ko`EX$s4bFycin@d>7CS`6_+kRm65e* zPfW%3To<4jwFD=(UXdl+x?0k;HsE>Ar8ks>^_K&giDWwP$-MOf#L|tr!re{Q4hL>P zt8E3Twabjh-(mI}<6KU~P41qPIhkNyJt1}WEsaZ+WX|v*v$m4;kG$;%(sDN;ue4J1 z=DPt(w_E@$#B{wfg)kv<ZQX%mkho&+phL1ZOiVulKBMZLVV=3d)1gJhX52Dr!&Rhz z=Q}!;Az(Om3wHR)$jahQ!Mr!1noIeTzkL<%D9oZ=bdZy}`$k@i9Q6~6Vv8TD_~zSa z;0y3}?9E67m32=j>vpE|n6YSASOPo(La)CGt^_VF0v;ST(HlZhNoA*mg7*yX-$s1K z>h-6J$RQjz?E?~MsG=Q}jR5z`OS2Doc}ACq&)XG6_^&Igs;bIP)BT>7r>b+_gsyiV z?Xv4g>f;g}c2*l)im_mdrd^OfU7}Q7#pZ(tx`WOn71bNeZ|QB?fUK%!ARv)s!2_r^ z_<wKpHhVaC`=93CQATM+z2Q#710((R11~&-U8~lnu}g4F+`&Agw*Ic?K%w)bqz5hK zwuFNp$}~2Iz^{e39<4U2DUh{QAw83cM}MjkJFm;*m}mgi`MM2glRwmm?~HYZwNAdr zpkBD%IQ?WcHZVxp2-b{%9YGpn3bzVwdhJ({uCSKN?){At=$l)rFA8P+kppo%o`!qo zK*?dv&RBliH^&>|B`Zo7vU`H$#jp9oM=^FyT+-<QLuYZC7VhGUXx}bw23&nq0Li(Q z0L8X{|7x=n3L+}!+2@iR+t3_*P1fR;Wj9@mOm`nCC4_K%Q}-*iv|@OgXXu*ENrFJ^ z_}a<j#AEmrB)8EuOVZThRWx8(c~?)2k|}hDC;yh5G)fxhfYBx4Lw#m=t`8nT;_&-C zVAq|1)H-_LtT*1#R=kl|0ap5<N>TPjGS>gzcc->Qi>ZuEIZ}vY1x*%E-D#5Jlt;eC z$%uDk@6`e(Te(loL+MuGccVLSjI7Zmcy<+CF0<J^KP|a`fkW{#)5}5`pY;)61L;J> za}3w*_ROrh*;UO~MWp*ZzA<AuJ10S?6md}h=lEJzqA8JLQK@JN{22YjB@uy3vx0*y zek98Hz3z}tfj)KxjaK38_LQzx)>*;7tFxUqY#FwOFC!;HttX=2Dep29@(pVhcXP8~ zd*UQm@kWe>_z2I<+=pG-e><_no5P@yk%McRf_s$wZc4q-fXz)BZRspx^(`t=RLIBb z!5oS0aj%1)u3sgdb0!a8{*1#T;EJk4A}(Y{j5Knnb3)SuJ;hL|2+vSfobJ*q-;m4D zDD`1Zh34l7UQ2eveqD4}eTTHk+o90g`mR$@B&GBagGql{Q8kKC{FOxRDoGRWla}f6 z5nKTr3LR7mTStvta`yc|Vi?YS-jGxs#3$a)L;jZkQV`rV#HllH-yO_M;WffgyQ*i# zJ4C<yz%$7T>+;B`{|8_P#hK7f6!Gw-^4@QK`vco#K=e`fk@;@DEpxUDfNr$cub!Uu ziTB-ICLYY$;G3ku^G7HQTbE!>E&)ib_eKWN8^^~z=5qkYd0=2JD+v$4kD=^6zN3)3 zmg#L%imt=QS=2E*|9Lj?d#x@Ho7$(80;8}wM_=StC$6LwQIBkI-Q1A+IQSdQu&f~u zigbOUx&1E;TYWLk6O`)djqx2hmCDYN^T(!(jcu>RrhmhzQip8qBR3QEFDFE}&c*Rt zVKE-_j+K6_xU{zM2krtzqjnN|tLW5adK(%ThV5HA+G@X5GFq{Zj&h>2%THsOjG}<} zKE*jaV+7V?zyk5e85nB;uo@*0WwAH4E~zhF`$@IwQV`@Ni<t7O%Js&<Rwpo4Sk&Tz zFkT=Yd(j6u?X~Tbzj7?Y@&dgIp_EsZwf<cY%;kW}V#dScm_d(XRJ8nSeDRJAY)acR zKQw3}+X*@Fj>*`xr(@*k@ruoFB5K;SW$W`98ss#*kI(BxhfK=wUpfF7(f!|r$bdOu zB*z-nTYj56bs86W`eqc$f%#bxJ0FOjs(0(Bo4-OX;J&v5%Hk_;hdBQ(rws2t0Lg8w zDAr#D21X!9loxOSkdwlO`n3MgCmw43pj4=7Q!e^0L|6^qef5Lp!ul*Aw)|C+mh1L_ zLxI+(ptFKGarBS$DYnpp-?%ekq2Ek@yziLc{EV;>c9;j9`8u%o>{xi6mg4A(JD&a4 zai801Sqby-5_^kJnK$j7+Lw&7CgGBT9fXTg0Xb)}%uBUg`W3vg=EIjks(uJKZ;ENo zarD88U&T>#TEB1bRtF8lU312{<n?;!+gwXG?;Xj0td&ux+C|_33PY%jtG5u>3BjSm z;=AQf$v=<SrOG_7@)zfgm7@$CA<OffLVl)JM5aR?y1=i$WK8qrIqJ$h+)fCRl&|Pg z<ahs7(m_Frd0*_Em>tgtWW@8#2`N3{i(y4}rhk(Eoj0irdD(;D;9rj8-$ZPb@Gmaq zWjPAUT%%Fb#QyEq{>j0;JY6-R`KuZFcNC83zY~VL^<U6Ta74uk{?)tC1it?4rS#`> zj@ZB5B{C(AzeL9Bwhqoo)RxSDm;GP#`+JVKFqyi8FJm7j#(1-7yh5-Oq;r56kyIYv z4XE3o<!OFI>07o@G@kSUcXZsnawIbzYF)5_p(OT6sEIx$l@Ui-c6iPO8;&_qenOy` z^&iT?oaJ|$T)n&M6x`8en134#u&dB0{{L@>6#t846@jO&Ny2AmCih4iJfawrW|{>H z8mG!Z7;DO_tv{me1N+zQY2<QQG27hHyM5EfL8*93zVYLx@h{tI@psXPA`zNeg56%k zVLH^8?A-P-I~eiq5_SZ9pI$2ehYZJU#s1%$7c?IxLp7Zm@=*UwwHfxgW$=dt&z3~+ z3m+44I2zuAtO;?qnE0?bRp>fL#)lT$-Y;+ByQo0nBa>UM)q{qF)1N^ExHx>8+m5hK z{BA_S#zapg)!v>&>sD7ORbyC`xJq%D4|NS-8?8-`mFlod1V~jQdbi=BQ+0;R_W|k0 zm;bHD09iO!`-vTR%}t`~DzvDsg?T4a3}LK|A2|GyTj){#va@(o<zomU)_t5kUhLfb zAbwfjdIEnAw#F=K<!$2bm)+u2K8<tDFiEVh82<Tgj0!dS_4G8KIDZ|Y47|)CNF`_Z z@V$9JvefVRv%I{Ecr9Y8Pg1fNb;TirY7UNfhg|Lvq`1vm1?n_6s^^x@xxd*<_d}IP zWDnUt-Z#4$K!a3b&C`phT;uz5-+yJEmYT(`4GwUhNgnXJiPsnEda`=`N0T2ZglW2P zMbd49?fa&BJTP1*R0a<_1&D!u$ESzz_VAa5jR+@)qNL{>alM-F_0K@|G(7b7uRclc zH-^+MPKKa<4ap=wmlwXelMhs9;ethTXao<jgRD_n_eodjBwP~(0gs&3=8C2&7>aI( z8=?MQ73>JCcqHD*Y;+{GJO91^fX&YVb<P{N)MX8)+O?(wEyazcE5{WKu8NgQC59k! zytB^o>zd|1J<qDalvLFA_KtI;YJ!CuuL}fc5<E*_ZC!iv3*XyKHn}2VqlE!hMco4i z1AeQ}j+j1Wdm*NSgVkX;wN24o5ls7fTaR`6StzCUN#FAD#2X@pO-ztt<xXsmGMT8n zPeu~uxb=A1+Pjsg&oToz+^|I`4|BmyXQ^5FO#M@Ho3@0e54~U7N;5PKe8@MRO-z+4 zzN1+Tbb0aosgZG3ud&JePHPq4^IJhBvx?^S>!2+=j-j@XP8=qsn_3_*T9O-&l!cEq z@B`XnCQ*ZE@lP8XUu3uD=?-EMy=Ja3Zf6wiH<@e2P0~MW>~G$GMW3<5ZI-M41KU_D z7t{~RUw3+1G*X!d=XF|tk-Q#3rOMaE(_^@Nn{uQ}apQcmVeN2y<4a7D4?K-hCBNI} znt0d~7Ir>ni$~3kAu!MqHpVPJjUGS(uOmsaRKpe`H{W|)82&UJYO}qd@qeO>PAV8- zX>GCXXdP}2gRj~(V@g4w-7tSQ)vfeylH&vPO82{d$M9XJ_(O~@<G>5$Ku5f>{-0kg z+w<m^vxf{j%uT}jOYw9;z!*(lfv_GL%_e4Xg6d4G;m%(Uxyk_4!(jJ$ZcX##i)--h zm+lWf(BtzS>8UG!U`hen_adMI^2a!^uOxn?4Yuan!psnwy4XlG(d_~wAB#tES#StK z7G({bup5?<^p@PmV|RbU_u#odL2}Yx!QbNb9dy()^u_fykFW-<k{{GkWu}G+;~ABT z-fuhG!z@kjwbj<K<LTCeDt+GPD=Y4Ivks^!8tWD%>vaOQRp48h#ScTo1~0TR2AZ_C z(Z#J98O(LwbJS>~1(%TS)K`yx*ReciRNdtv1eE{vfMoAY5#ZG|fj_<oj(4e+l(|+D ziNCu3;T+f0gpe0WP4!!ZK=ijKCg~vU{wQbG&8Ez~TltjK`r~b!viSeU*jtB1*>>y0 ziXsR~cQb?t0s=}2jM6BAG)PHzcaC(&fRw~gA{`<nrR0zU(k&rFcMUP~-Rk4B_q+H0 z9mn_o+%fB3*R|Glu5+DBgVh=h59gs!M0W{q@EY}fe3qYHHBc9RNtx)&!=S6!eHfML z*!HqBNc+;|c0S)a%Xird5z<6Xb&V<cjfUHH^E~{BRNCc-YXd_8>5gevdMo^+dPF83 zad6C{yu;{mMoyi6WIyK<CqTfaY4y%cLBm)P^Q5V`pJpbjhG94ge?t$ivzCO`j+pV} z_Ofg=)o|5vhy`r!pqSyMU>R=`x+EXN+KuM!Ml18L9M;7n4Ew5he@-Hux74PNpHGQW z8md)_U%5Q$FiI#L{nqb~f^k3Fp0!RiEmuQNW!0E`&>TA1{v?G$GM(aAU3N2uT950} zi(BhjIgO4^pxp`>V+ucrNb5;vpVBZ~gbP-!7tXqPtV@KVJeJkEbBhnuM~VlVyJ)IY z8@gGh$Q^}*bz|$_dn>LuKwINa##hA2&;~1w(X*9BhY9`Ql&5-YSWt-Mn%mfB$y!Rb z#+Xf4`>VMd7wS|C6%f6Zg~?)F&}#+)lST5~pkA&!Q)g7SEU|M9%J?y%nGz!<p-X!K zE>J&j>`#guoSWz>;|RID)mP#cA;Xmnd;J32`dV}<<M=WyL=A9wzRJy2$H&q(0xR#R zLZ~0#cQoALr#BkL+#Y^CoE5S>9o?taRm3L}-G$`1j&9&!km~=MS}x7V$+=NgDY-8f zjD)@T(bJ{~*U&)9$YS9IK+wd{J!EbpO{Cb{_pnpvGm>;jETvGyWpvT^-c7YWFyupZ zQJ8nlJ?~>~vCM|ynjSU~@8WuY68cHAba#BC&_5H?;ys~J2MwdxLi2(<^P3f|EhgQu zcGDR(2My0L;t9Kxyv|!VA}25=Op}Aj`sj`yUJc_j3>~&pD(iDz-lp~maK+JgI46so zxo33>go4p2^RCf3vOUc1zAym>Y7|Gff{l5wj~h^XdAMuveX>oB*Fu+x0<#t0Zjafj z?e<~gZ#zOPv|*>Ay<`$l$YK!bqF@S(XHB#L3=5&tU-_;8GKh2En+wD+!Qv|_!gp0| zeTe%RrIBx0*?aR0`CNEqEI!c=>*Ag}CWG<2b3VK~99+k5^@xHR%TAb}_95gmx`8a# zN!(q06tHsr9^&W2+gdqS^wEVs0?VtYh_fI(QH87b_&Rc;+Fx(gK~=sUAy9j`%id!2 zlW!ls5$cYDpvmGy7(#`3LWIO5*Z>C5ula+2vKxgL0Ik)%?vz37ay8wdWv>li`AON_ zdyORYxwxV1%HgmgCIj7^kJ0^(QT`5vu!w)Ai$CIJ^K0E&P%ZA%5XT<@%gKnDM+|0F z*=MFePMrES+=A2Wr#>p0FU5wFJPTWg5i$kHn)6-y9zD(4M^uG9-F>`Oq7l~)W^{_! zVUb|&zK#+C9Uur`myLbkCwTR`RK)g~_Eq>jjQ+C52Ay3ihlu0sIl*VLV|N}{om-GY zFK}BrF}Mf&?Dt}U!P|Q!hLV!Ce7`LD8pI1a>|&Yvz#lsY<|>ya2}*&!lNu%<?nBVp z<Q^gdD^F0bhT^6Ysk&1kEU~~9oSx4=k*6sKs<lLaji~r_tfiwzyus2%H?Wd0fn&tF zkf3IivF-P^!frsxl4|*a@Qxf##T5fD+KV*dMQeDLLg%~G*kFXqZ=Ut9xUQgRPd#_A zeT%SpJ^2MsL%v)3$>Hia`X{pOiQvTKmz=I-t&-MLP3Qtz!?UmNaczsbN#6!d<2;Ac zT04nD%PYUlUYhijiRlByMF;nHmSY!@plt^c=F95U?zzMzRjUm4Na$Cu;^n-e^18dl z+!QqTv#&0zUo(b4PF|uPOoK~OEhf!tdam~fpmmH10_JHg4a@X}oAzm7S6##43k5d> z7T;<n!CJuX57<I=*^A69Q*^`aK*@!G(7XQJbDn4Y)MvG59io?9@ychaEOK(6_$VA4 z({I<gvwuI~k+YudixCX#y?i^`+x%lmb@-l}E5na-`N2JgS=&k&BfWN9&^3%N1?c-i z&<1Z%KAjfJn~Uo#AaAn4>?wIhqn(m)mAH?P@?f#=6-<{kRje$)Mscfa=f;uZ+}G!_ zYYrga4~Ai<R$X<3{7No;;0alR7>zX!uDUL8d|;PqcO4TF<tu$w_jK=26?!_nos|}o z*a5}_MvGoWH>eOo4|A_v)*e{KX+0|M+<G0NGko1b=%0cLGpkh(cb;yA{w|MxqrT%e znbX<C^M!>&$hlR`vmkpq-)(G<xLvQ|5PFJ%;`zFTm^_C@%N6b$JdLG&`TN{BhC;4; zU!!1|bE|3HFEEF5#&#EOywm7a(q3?o@J*?1m)gR2G_{oY&&7aqyx+CO3uJ!=0*61* zK|bpM!58{;cVO^M`t|Rzo!dUkKVdf%KUoB193teH0+VOPKg>hKE|6ei&Pz5yFG`i{ z6cFcQHpljx{NrP*_n_?!?}yE+qn(o+7U%5l?paBrQM_8>hkhWp8<#FllYJh<dvw+t zQ{k<1VOs;5vTG{S74I)zzd_JD1zsRweBpjIL3a3j7io(ygzUpZSGXx)P6In*@;WMp z3zIv&icPORu}`nFD_kBfP<i(?x5iBFs_hjWAOwcf5R2J@lEn+MzxlR+dn<T5cdykp zHXEgL@obD1xgcX_YBj`8z*AQ$D5XrEX8Si0LWUJyI}P-^^&ccJ@Oiv^RX<>l(7+bH zv=2zVcLT;)8delT7&!MPEKn_eCEAVXxu{yktck1Y2=`$=+BMI?<RUHs-%q_K8A+c- zk}qjhy1^DO$PKW0_)qXZ#w5|jeRNfQ^BlSG1Gb%Cz@7%tL<!By{;;ncp^eiX8t`2F z;hc}}Pe7dC<N8Rc%NVyddjQckE)jROjd#M|n%i%iSz`1kP?Bp&EeWzr-!6Z_M{^v^ zbH`=tSp9&L4ycFOKO7x&gTE1@BexGss-XgsAe%i+>1xF@lu$yL?V&>x*C*T}bu21k zSv2y+aJz%CalVlk@q&&gDd@FR6dVG5$MSiB4Nli`OQ|su;s47;DRcd^B+B{Vnq>xq zg_nnkmh)5@gE;ZdP2&Ih=Xwt}M(_0U4raC$gTkP-7ELgTb~AWMyoL=5d03Q&>iN&E z4i2;A@9PwQ5Aq=Y;-FZi`hiPtx=4DgIEiMQTMW&Pa)SZ#VN2T=hOa-*-Tn!ivBst^ zc^iwgRYB{F;^W*+qdNxZ(|q5JNT85GqQUhO$STla{sPxE6)mFJnt6J8=tPVuod?%b zPnU^z*b+A_D(x+R3;;n9thvv(2i@@kUqs2)k4VPDiXMKE`NYd0u8BsLgED0d!WewX zs<LHb_@`PRj-*)8Pb8n~UL_*t!TY_KQg_kY2<-W<mpZ{)Bda3;@`vD(g5*;O=8aB= zl2A46R&f0G1&$EtMi(1ZRIY>xA7}`Slw(B^L6u#DD{FiMD;II3pD)*h0uOruy<9P? zU%Lm5%1hN+1}tlljzKAO_|$dgG)IhU{^_~^vU*nWhM%yKtc8o*L4Da-=hX#BZxzN& zzMIG*lbI{IPj0twvqS)m`YKHQL~J<>|Fr_N&DpxR)PM<drH-y@21d}QWWL!)*d<Pb zdG#zv2cJK-kdeNT{_bQSQJfV*Y`PFW1b))wG=G2~k-~MY_4az1opt<xt_6Y?U%#sE z#ayP@>2EZ#9wOM7#wosi<DqOIfPUy5pm^p^z@_{NXj%>E+z9lj^TV3(Pz`=kMlV{E zb79cM<4n*8hT-db-9Av-B5fGMy+?3@=-e-8!**;yF!R@@xdQ?qZEc_GosJM6piQUP z;T?=bUNgiE+1#LGL`Zf@MHklzI-=t~`L>Q)Ig!`hB5r%aynT`9Zy^LP`wp2U<FZ{s z7l~z^eDg_!wI<l)fK`;6dUy(gH$^E88GTsy#F+@@@uV<8A;&8hGAmCjh(u;*OZK|~ zcfq-Bc*CV$_^-RJcrw*R+eaMY=sOzK$uTI1pJ*jRT9#B5FalB=cG^h*b7u#7yUy$~ z`_d&$(0Pki<fO>As-a^_yn-VExeS}w5i}G@O?%6-IziMWCR1SUwXBHQO72k;IF!_7 z*NOO9`qliDeH{NT%kvgy=($DrJ+A>UgtivsPNd{{NX#g;*`V<S^00Q9g)2_3?W$Tg zNOvm`f~J;zQKh1)#hM0D3h>^*7ihrFwPFY5j!1Vs+pigA<Hq>jl9VcWs#)=kpR<i) zO?EBA6^>dJaePIQ43QwUE031GSv=tJG@bIWw-p*1M1R|+tac*?Jr$k0qVol^BZ<)- zpU#A|7kBdqlpURud$P>?fcl0ILDEVB@Aau(qnVq;_QAOR<<`o=TZ65O^AjAVZ-IvU z9jV-93#hU2CwNGC>=z0zD*x_}5p2Lw>8-?e01jjN-kveVO&^-rE7`ou@TV9(Je`*e zouRQA0!i_lD2*#9;4ou8jM+$pet0gg(Sn%5Wi<;%*0O;Xp*Kx~o(h-&!+sro4qflX z+K3Hi3+Sc)8kP0?bn6^2%l`#?dTx5DX;2wF_X>q9)BParv_A3TJLcXxxR2H*-;>Wu z-LP0QSwJb#XhOb$-`VP($cbAh1nnxduEx8mlYhkxGypdmfT<e&V&fq5D^<d|nPpm} z=G<AeBH4<mXU&j@FP{HO_0Gm!Mw^`y&Mg9NUkV<SwJBCCreIAE?3VM(U4ow{T+$}L z0f$cbUxl#tP%N~88K1Fkcz_mIVGvFAXTjUPmL=j{T-yxN9YssG<fqdC47otNfq1$& zQT(Y;s$LX?;SQtlY`D99Al2&Kp{-1)hjAs>Z7E9>QIF`YjWW(CJtlt2b;=W}3O64r zC1s~Fh<FfI-<EXn;m`6e!=lW2rU|(lekV1=jeA^&oc&((6|tf`OE7YB;utYf>p9WS z9!BfDLuThuTW_80>}|&gR7UcM4J7cUTcgBD>wo0U@WB|RBUAmUe$GUD)8v{M2Fz`5 zOp8%px-eEW>=QdT+>s(X#iDBr!du&J+%J?F?kmaC-#cv9Pp^~xIIwpf{ulX?0g^=D zZTk{OrCqZ={;NYmOtO|?k{@GVmEp=HF$!_r>zK`Jo6XCu#uwG%d(~p=X&~V*73&9G zgn5+lj{I0chfK%8m(f$q*~>q&1i}$wI##D$S=0jR{K%JCDgy@SDWl5v5cHIiEA!Ce zM-Q}MV+!Hx%bjIdXN_0FnZ+>P^avQ=Snnk!!xkk(c7MpsE!(0@@8-+BV_&YeYEVnD zVNbXVPhe8aUP8-vT%x;)dVLtZZ><A0Zs}Z;0uKv6Q1@!P^I`YkS^FF-E0`EgjW6pI z+?TZLtEVxfsIAU<;Vj$Co0O9qUm_@?bO7f1jj8Rn(}W&y#|;<Rnp$b<j&<iHW1Tr@ zWUfr*U#l&SiRIkVP&RV4mCAUqGm!WVoN@@GB_IAFDyvE#6$o!r8S~66G!#E>G7u@2 z&3AWhjd}OSnm`#$S5|9!&Y*CPn-Kh34TUsm?W<Z?nFIs^s_8DC#a_w9(kGi>5=_EY zChMHH7~xI(Npu%t?ciN)wIbCE8@1`U{!O%qTsYFU>HwUW5Bfr6Ny1!IqyQxK3M3CO zm!w#OBd$B)ht+fZ&oUw((Jv2;-ls;Sl5G7wM6p&R*q|G(3NN=EHpMQNuz3a3j%}-Z zT$CGji$=PYBwR*=EEb#%OBPQ*(`30DtU8~1)qThmIB%)mP4}J7Q&Ub8$XgGNuy|($ z{`~YpcO90;1R&xoVk#B^>`(wamnXU(K1y%1;yW4B1d<||dkFr*T-9?S8^kCR`+h0H zp6bt8E_j8{c^LenaR$GZRwef;#%!99du}IGbvrEC8eD4H<!sV(BGiyP)N7Q(|6zuZ zd&=GtfFJYc?2ZsB@oUtw&LIyIt>UQw@(gRZFC41c$>kyKta@u*_&v?t@(5pE6zSZ< zKYI#pkI6~_Bs6evVyD*EPR{(nw*6S2odmvwOwa7QUu_sfLjO>ue<Lo$iG664u+D#g z_|BI(#t9|ot(y<0IF=(7%84};KONV8qw&Nx;=5`7WL{qWFE-~P|Gz+f_HM?IH|e{s zKTR1j)<RLkb4iI_cn@6jMbc;^?~r-PtPn$2wPmB4xSeVJ{{hp964F_xkJyn3mKJo% zB;xI{fF?)ck*fkmhkXe~OSlLNGcFdWCV6nd-j$bh?^c>gz|Wzs*#+>GfC!r7fpa9B z6a<d!CsrV(<^_QLCTXGmxYa+vIU_MD4DJj~2C=b}ew4U8G=O@+H|SoohhM&(V983j zG4S^d{;7D}9_<9ca9TP&T9=Uh3~nx=o`R(P(ub%X*R0pVTyB?#Eo)q}r!L9TA0V-~ zBj9dfJQe5`z{fC_kb2=YAx9o#d&}Aiq)O}j{lSQKK8Z8EHd$bI$%<iI65?C)$Td~z z=MkgN1n7>{hZ!{}?{lkuZOQ3nSE0u4?@Af#-cjOG`L;Q^nS1cAQdf6mUfm<)c=*Q` zODUC$RcxnMkB5BjFV=MHvy<PyZ!KMJ#ErR(flmRLc<$iz$qm<)B97hHd9}rHQZBD# z<3cWKf`01bj1gUFPHLzUpIhnzNJX){7Bn+{GE!H%g|gv#Grh!5->zJCcI#*2F`Luf z&2+0S;+I6P;xr1b-Kul?L05u&|JpzJwT5JVa&ub&)dQQGbK6$If@Bf-E`PtjB8i=M zqDw@OT<onzpIhLaEHaZ1e9F)#rgQ95rrcE*$e1+r5cM}v6@R6=+p+?C!rA#VQVh-$ zCUM&C@^9igr*~y%R-XrS8A}j)G5EZ>pl_^xJU<3DcdV(Y_dx3O*R{8Q<>jAc-m{Z) zf|r=SsXiWDA_`#;>Dht#u*^KQT;DxkyTy_o@Oqvk&5qJ(0>Ee+6joSG%<P~@8T)Yz z-BR(r&%PW7U*KcVM>U`1ac&mayNtPn!LiTQo<RrW)7V3DMrE^~-Y~h+IG@D%a^hAt zQN>H#Af5kuvdnMx*C*gL)k`)dc9zR9U1(~8Q$fR|LnR{#j;4L@n-+~Rc%%&-#KKpG zDz^5fZBMi-A?2*!WlfW>t}RGL9~FJ+zc%qc(z1s$Iwfew`$1^E1kDf8!U<`Hw>rnH zvKU{!4OsSsG!k~<9n+}<m6H)&QusCkdLo@X)!iHi=PBJXD|MPMNxC0IeNcd*^U+;N zt7NH@Dzj!g$Zu}*kdckZDDOLR-Zs9Wn)xX9e|?pxm$C5*jSyE_WKARK7OciMi{{+R z+V>Ke$CY`XOzf(<PwETzhne@@XBIwbxR(O2lg!=<b-lk_e3dPHJkpltbF>Z;2%oOF zC710sdsRJ#98{S@&Rq+GoG=h$x^8-y48}L18*s7iOZgoq!CRS+iYJ47x})gGr|uv# zLfKpy94M)Suc>$HgE04;E8x^!p)uJZyAv3?dk6TBYBZGJ4<a3vSnmQ^@I@0`FE8st zWt-{I4;_vrqw>A!C6JxbM%F}b=|ik1QUhq!6~l+0HHd5N_+(eKpk<;L(lig83c1X` zDu+tlhh`C#Sswz@j8&!MHnQ#99%1`4ad!wmuG>j%w-Tj`VGZcg5DX1xeH{KEkkdh) z!{7RhVUX|qp89qYbo1LajNUctE6zu6NYC}QE%69UvzgT$WL6__VpPgQm#-!POx)Fn zv>)d&MO<Dg^$gwnd#zIU!@8~{pzEMbnR%(*$NSd44**zd)!h&}?meJG)sY;YObAPt zK}RK;W${sXL>>(hcj`L6%5iEXd;IZD^iJp05j(+4r-FI+G`PjX$v&s=ce{dlIi0b) z<~Z|KCto+4-+8WyD6c{7KV5W&hQJS++o(p?f!tsG8E&Q?<VRJT@8^^IV*HaK%XSnB zn150idEwu?C`sNy%q{W@I-mOLsI!42VH8qo{os(<Q$0*SW3B2SUP|Bkx(&?_sd8Kk zi|DHPUfwC0SBlO}S1zHJ$HT?Rr0zGx!p2L)&7V(8F{ImmuHe%xtaYBCUJjTnk+L)B zQTUWaIT<&-3KR04S(WlfPw{aq=9ve!)=QjyyhJVolT$w%#?nD|TT^yh5*=C;G9|<m zu3SWd84={Drz@3k<6xo`e!S?gyNx&nFFsV(lM}~POY?j;1Atl#j*De-L?G>}ZQu5K zJpNm*!H1=hKfZq)&ZiNMpAL8DA%x7}54sc(yyp(`+!gUOnQLX<5zS8Rq$+J?#Cqj) zAIsx(DUV|<XW0j*L1F{Dx|uw;=FxYi&w;gmw-<j#s)V;?-lQ*Hi#+kgDp}WJx5m13 zQK_FwqZ&c}0F#p+<6k_Op)P>%L~tym#g||LFPnzspE9o{vv~SC5{TJJje6ZwCiV7w zEJ1;x<F%(iDXbXX`9KR`;USfm=JJliq{>3`l1Im{CfN1)7|p5acM77iOxi)VcFdn$ zXv%N!E<GWR#Pe3PS$o{Rr?^3Eip3j#xG6!m&S}E+PwbAM{KLkYxo#2n9pNN@x&`ug zVPin+Ou_v~1wItM#Pva0d{8Je_Fqq-e?PsQNPp~UpY_Dyvl{pQq?UWatnzo!^A4#8 z4*gD;jQeBFvJVAJBKiV+&X9Y{X(pa{j&Sl>hI5Mo!)9gwGd1+SwRsP(e~%?FlToWw zUKOKv*MIAF@YB`@pKiUbDEI|dhY;JG*Tca^!rb@L903fxxPjvmndxW=i0lNuHe_?Y zOLjB>ip$B|xW={o2KJO?qHXJCXhp5#1yaDR^z4e{E&w9(`7X=7s-To=CII+^1MrL= z?tK>7Y=$7mxeCQm0O@^Y0rckShlIOwan>`jTJy04ODJOW2wavGq6ca2bgQ#`HP}My zh~wNI2<DAPExxYkV&p}m)H-Ov(a(5eJeNPlpDw5Aog&zX?_ogYH!|;_9Ab)&$F7Zl zk?msC!3t-hw?h7A_b+}E8}{qIPGu)JFr81yW6@L61Fgs;gcw^Hj5n*Q`&3{5kd8?V zjKh6W-Gh&C&My7}JvEnLEAZli#-y>yjq<QmBnv$iF6(|;J$)f-H&I4EeOaxg?K4Dh zDzo4@))pfxp7Yb~c<L7FP#JYLAI&)7$JY84Tro~7acGcmj#S-?+=x0UgMLNn<Uf8$ z`ZyIOv?J%ZDgeUI?kmk`Z&-&lGQIK=IAB<~z3<in70P>HyOJkQ^NJSQ&IxPxoLs$l z^Ehl>h`hF=Y8F4nouzm#Jf%n{72UvOy%xnY&F1W*9z(c?V3T>x<N~Lqf;J9~*~AOv zNAs9`F&oR8w?yE;mlt_Rf5E#nZCQ0oM$$KS%LE#L)mcl8QZ2}y!I+&P6L2f^Z${1I z&AaiDyvnd2T@HuXM?0ZzA!vB^rg!(3U_!Z*oWjUNM|1HIqs){|AO|W~5Hy{!q|yEk z!11^-n0tav9F9_d{W|bBTVg5OkA+3x(#yk~U@hMplP$A_o>ENzL6VTw6BC5(MsY&4 zAZ0(6X2-ucdw}r2z!O~ghTWfP5T<?dqID}1BT~GA&{Xsp-yskI&#ies%VEJ(mx)i^ zlDr5G3=3MvNP$b#A1+8fT{u+;g=j7!46l+GVTPaV-k%R$njRsJp>HLNib3Ia{#ZS1 z)697x#!Yb8P^IBg9`BD{SxKto;a{830?Ri^WnqJwN0MyjU)F7{uu3jPNfvj4xCys& zX%(%!QoDF?O$@MnyeJctFqAg$L1SI&ruE!mWORPS7EknA-|wlI4s5?!>*Wid%M4ke z`WT@XdTs7h#p_i5g68I##j~@`v9)<dnHE{|+sD(-qEs9!s~7KS_!O+4=-IzR5z9^M zdN>z$Z@lqk0YHd}wy4ATFy->?hN@Lfpvd@rk?X4b%h1=W8$re>q-ZL63Gr5Dpw2## z_YV>laz)GDt2<mXIJxLsV!V?PIs5&#8LVg&hw<?RwTTL4z<KV~p#Uxugw_~E<Jx8- z&n_S^apfYDe=r|IT5R;D#|SRfLZlTpviAwzDLi#SD<b+g(KGlHS_nVT5o->)Xu_-g z8I4Mx4eh6M@m*M`sYg;2>!_4U@J_hkSwk?kUM~=*gtyjy>g^#443F>3#*BeCPkbWH zP8pWhV0P4H`f=nBFt#-UTq!ku0*t-oQxvN<94z?3g3cavZG<_=m!E}}VYCFjFdUUt z1JtR*L7xZp)a^T}Vam#~z!ac>PXb12hf*r@x2`{?e%2Yezt<)323I)@nL!v*Pd2Va zTmY#RJ7H*UijD3qFdj$-5t+rj*)Eq+)B2iT7S_ZaDJb@KZEA5S^@+5EoOaQt@wjIn zk~^*|bvWtg9E!{a<`bzAIhRtId`6MhpAs_N(WTuH2L)caT<192-0%9*4EItU=0VC? zrP$P1P?Fi`vfK#Ok###DC~T93)(IM*QTJ|wPlpL=xkFc7+QG2A?%a<IQ8{Y?MY6Vs z^6e&Jq3innGh9q!;xI$j2nc#+XWrvShYGKSI@;^jr*C3$LDS*N4o?^W(7*mcVU;H# z;)(Ygb~3!#_<we>T&CabIc+!R4%2gsMw`J$LwtB^K&%IZ+j3khj%Z?8@5o;7gPK2| zz+Hy5$9){YM^7<eGRi#TbkTRUoUOV|ut&h@PJO^WRw^*bEe9~NnS3v^v8v;)-sRXx zh=9Ob&(e+$W&p!e#&WBvF+K;(PCM;Ri)A@d*%ZAy>>$aJ*Vd2GBl^B2+7o_+rh5Jg zFghB$&8~J{i^f`b4BgwhcR%E8yB0SjGh*mxSk8epi1urW{M~(yT+@j+9}|gr#dYp& z)<0*wP@PLnk#3POkFz=A>0%mm;W~QH=^_y9HOfN01tZtWHJX7EbbjN|^0EI`9drOx z37)m;n#nGQbIQ$6{{sA@w8RB(m$GJDA^@Q%sdU(wodMecee98_zB#MG*vEGVs%x8L zj?@0#Nx)KQrRw!MukZSi6M;9WiALS-UwN`$?M-ZSaT8?$R2;;`j6~QfO$%4SdkGys z!+p_rCSuUCk_>;hF_u5!nbkM%8yvIsI$i7XQ1&CG8=k6i^A`CeoeJ7QZW>29ff*CJ zP(n_R4eG-*sa%q|HeFVG(A5kxq(jEtMO{;$p{FJva?FYsTiU5eIpQ8~s;_j%nn{l_ zT)rS^2_@-P0F;ZgE1<Y}b0&r-k#uiWd18zUAetEg(!C2yt&vYEdrVh?G{^!@FRsyY zE+t_ag5}w$WVkkJ1P^F^W0__Oa03Wxkl=@IBbD7a@oJ|sbJvbPwWVLhiN9oQytoSD zBPoEKaFHt6BWHavKWK-NGKocX$>_O6--`5~60UZ?GT0TMFl6TW@`%A#8wG1*=J2LJ zI(XEvLV0NIn{bA-Jp_XTcC4dDEbvvM)L+I!ehYaq56w9xr<uH-+`I~!+t+{l*l}3k z;ZL#dz<<2fnEAKYrUpBx7hbard)w8kE%3D4p}b=i<|p%kh2^sp=d{+j!nD*0S$7r+ zc4O3@A7HFsc<iC%wd7!)NXW?)r#ogVZKEUlwa1yo=0nKfAUKNajYLT-)jXI()Ck@p zr9-;=(d3|K(|Lt=D$lO87t=Jto~`zgSApj@DLs7ZL%e=bm-Fqd1!t(zD~LU2mZ7Q! zBY1gutq_icf}ahOC0OIQ7J`5^OlRs~X=l1EOznfB$*sVR*0G$x8E(TKN|JIE4y$s0 zbjKZsYT9D|%cH|d-aud7+aF&iqo)?Yl$}KV0lJ!A#Zt{$bc{te2Q`&e0lqug$hyH1 zitVJzGVE+)jHvkMU5u{;$nA;AuHl=f={}Fq!Uu@wZ4*yP4vZrX5g|i^ABR>og!`1f zd;P#);!f1Gx99`c$$;MDGs9ZHNtKK=Z~i4BuKnRzvM<uor}YSavaPm}dDj70bqSW_ z=6WGJQsj-YusHgZk}tmU{L|t|PZ-vi{mupQZ3Y#?@HFX9B1Nm!D6(dQnY!VYE-_UE z?q2<w1(?v5)9EARL{w4Ec<-(GCc@adY3y1_s6$*&9JtpI(qr?b|4Rk`<skxWQ7F(U zu=}B08>)wHAd&u=_o_73VPGO?*;@zlh@sr78Y*NW2x5SBUF?$G`<BElBevoAAn{F) zEbTa-0lFa_4qD0fSFA(wtq5gVGzINi=cCWaEAUH$$QVcBn-@(As}JIH<8l>ZCq9e? zdg*=yiz;3H!q;hTIpq^)GOz<#%rz22y%4L)+tp?iG|9Jad*!J}OoCGa^8Lt$N8Pp> z3$c7Ii_!1{1oF*p(%z`a-DD?Ai`y5g3QI70fFbTETn9S-@)Jg1e|4DVJ!2;CUPanX zzJdH^V4*gO76E%7J7>J4RcW^s%YEK{+0awD22>-I9meG1I_HGvNX8cb5SQY`6n>|c zd^0PSL%ej4BBms|H(<K}n=(7IIoS=ry{t>^A?K&>G#5>fp{ks;Ga;KQT^mAJDHr18 z%1<O_+s=>YGPlEyc`4v(`F`>o@sI0^Yl}Ym3nqLFZ1q>w^$gUWaaLcmwM8=W+NLu# zQ1h^r-PWHKEIQx5GPk^iNH|NkU<_I=lv+^i>z6L%!XJi3;Zys=`nZ;gK^=|XlBgEB zseUM(oZiyx((L<u;f;;1E?0SjYdhn3bx>2deiM8W+bkX>!y`Ctl0=;|aVNA!_s*dX z@w$8W8j}U-@$enbgV*w77wiv~da7!sBxNE8AF6vvo84+FnkPxk^2oMnI$<jGVG(5p zVO>_|l89|Q_}n`^(dZdw;-hbV?Up>-xu$x@$C7yV4-e2j9|@cV@8hRP+`#+HurYPr z#b#`TDAJ$)puAp4`4(n&0`ed<QvGdn>qw18A!INFzWrh1XusHkQmM|Md|+k`wT$MV z<NPWBj!1LZ-t-gu+3+f5Jw%1UO!~=0w-hYJao(-H;~z3}yl~alh--~J45e4f#vm%f z$-f|#y0b6XW*K1@*wF*Vk)J57BRYp`5Z<ujT~CQ^Z^(fJM$Hal=;kkot_U6q;7z}1 zih{hUW^orKK#RP>(sf`yIzq%|jA`0km)mB_us`Zd>RCZIQ=?JvdxL?z+jS`9dV69Y z_~X}c&1dW@SO$z^vKiKRw%WyhR#;Vf)9`&8I}Jk3SKKws54kx(&2OJ`(&B$0zB|KO zDgMEgdh@3%c|1uz50*Xth6(Ss=t*E#6=j>IlU23MeRTucf$&^KY&vyEAI|zNuFsF8 zl%ny7YXx<ISZrNa>nHpk<T|U`^7Hs9S+#=(qtvTwn6lzTvGl??>vmSklj4sLV+)zP zrklO^&ydb&6BXjS<tC8uJdSYf9qTR|o~w-_<S}P|f;U>)qglnLA|%Zr*6L-yVu|=m zKG9X}cXF|@qUU5R|G2#HGfajaS_DV_h>XSEdBjcb<=f0ykfJEgG!pin1xMlK%a=R= zLSCzlM#*IkuzV3?XpnWe85Sp{2H>)Cxqr)*!SR41Ujc-@AyR7Fd-aBbaL+o7-byrg zu$7qm2(faOM+9=)jTVWMD<7su<t_-(h;@4Mf&RhO<ClS+n{$hVnN)Wnkt-Kx<8!36 zwBZOiaT!qMmx*Trb^UrOb^fxY^`rV*&PglEuI>LMwZYQ(SHC32Sn2+yTmgR!1aw9L zy-_3t{~aZVN@5fNqQz~T|IToi|NYj%!8iW>BfwCP{2}nY7>I$-!?`d<59P?5d1+-n z$phT~KQ~jN!E9k?9DS?d8-uRhmz8H=?gML)QL`toJG1-?l>?cG1n`I|NNkv2EDSOa z<5|!7S$QX1D<+su%M^uFhl+#NL9icx`tE+`ElW49T)v+p0Vps!$PchHtI|LHFuwz{ z^mCpIq-Nb<^GS=yjorH*)V>QDBMxaEpmU_>6ku7&rJIKi|AcVBaKC>(oQQk?Ir*kh z^1V$j%l~{ooiWvK31u;foHTf1`RCmOb{Sd!xCwA=#5+K}>O!Jnqb`rTU2nXC)(^P* z8LR&w>#*8C-35PtE1%Cg4i>Wa%{C5Uq<b;Jldf!wq0_nmtS_JOw{`f}ZzJ9T$U$7i z`EhqL(6r{=vwEnzeTV!0eMmCTmCL5)6REx!sgw{2RkQI{=Qfl@{(N|zzkT{&vr<x6 zy%i!9{Q5^T=J&HZ!hjnRR-A7;zNop3WIK}T!~=h}uNkS5_*`n}lZ&#r3GTjsSPlC9 z#*)bpd!|pXO$pI6Ov3}9zb}ugVC=jA-u1&28@Ae^HglqX)(t^g2hJQi55S)#EG*W- z7WR~nr3$~ErzkzZlm^0<i(xZeHpN@YDMv%j+P6ANWF=#{K3%$SuDE=G-#h!I7yOT( zpT%FpT%KsO`p+E*J!mz)ef28mlCTUhk18=hr5lV_NaS3)D6JuD_uq2@Yv$&?KClp( zmj-~hg@Fc0W;y@856}a39ql!v(YoV+nn5SG`j7J;wO5?wNH#DIf?a;SVSk*2O#`}< zv<Hj~_qV65C<1(6$q{%dD<}`>P{x4L>fM_8uPG6K{xvJ#Z8)asXR+bw=Sw@~zG#ep z0!j*y3@|}fz&^V^*o1+hmo9@u-BX{AEAw~bO#FiBlmS2O1=U4}vGFV9d*`Oh{Jj@Z zLI*1o+G_-OJA2g3PVzWJ>cxb6y2Dmu|M|z7QbPp{9hXx&*Nqj&FIzCux^rBS79g(I z$e2q?7_zEz{^yq<`2iC$INmHzHsS#U6(O-no-dQG)}1|VnmAcj&RF`ul!1Ze1Sq}# z{Q(iMC)?|&xUh!)Oo2?ah%AYCCvFdmDeAwiDH4W;Ef|81ukLit#XF?==w-Ug#-7&^ zqALEki~UkE`fDLpRp$|KO1(GwCE+0L6E~H!zRWmYhW()?{u@9w@!tQj0)YBmi)ViZ zrGe-EcHP1}vEXjg;b5^wiD=y5HW}TYuAKk9ZdTqy%3ZFSibgCPW@@+RJQn=!*-C~i zcyE>|jI3%k32Ie4vi6cIPhXjQ`Sz{GsZikmdU7m8X<Z2O-p3r=Y&rbJZPOqk{&;hO z*V9|2QN`u(bYL0nwf)UisETXt|Jc_Oo}f`H>8k}VvnZA#3UTd(&vVuX>@yNmu3XI5 zT#_9IM~C_F|6dm-M3mg)_CL;HQ{mm*H9WFLUTFRF!`M!nm!h0b^QpL$fFSdyUFjdk zBO<xqfI@#;wv13g$%Y8bizuBp*yVow)&BH9c4=T^wPk%PQ9n+9m;P}?mT~Y3@&DNI zMItV%lWx*<FdtE~dPn|lR{C2R1hyKob7cNLqF3BP8~FgAo)9PV|M<phFo5vXNMgTc zO2_wq8b=b7K?mTt=5j3-HT;^_{~!051Y4M`gopee#{F~sM_)lR7xP;LVeev7|6f09 zDBJ)3jJ9g}&*uF<gHse_@M){dL;D?(p#S>@ia@>nS497x#y<L0JdSt#k4>2DSL~IP z7ygfcqIjXAH~Zp0Tg?9bW_-U-(5%zc-HFnOhd^W;K0}g0RY7jj@81;hsDk9CWtD{c zy)=~b@37PUy(%I2KkCE4Vw7G68e#M}K0P&kl8hrW*q7D?C5?$q)p}C-fOMTxm3#Q* zznikye>I|Y*c9|n!FGP^jbGm{zVu|b5G~kLq0Y=|IGUpgGtc6ngKyLUy%q*@%TMBb zF;}Mxey4Ln3%=FHosr>JE^^R&(gwIMNuk4_l&DAH%__m+kH{Nd1C29^Pz{iBq^p8! z;=enY^6$#1!aFVlpP|ZBoQbXvgPsF`xfq?ZP0rC!HkEZ4%ktZ@O<Bg6D$$P+djlSp zxo5=)lJmk^d1jLfBalOsVpw==h%@MJ)jJPA(}J_g*Wb1C6Xb{Gd)1Fba%n(pSAD^F zqvZEv^n;UMC-`B=26x`H7kwnyC?b+gSKD*3^9dP{rePMHyMivXBqY1P8ghu3wJ&|Z zp(+r)%$ZOq`ws~TR|NW}iqEqoB+0&w9$x1gfy|2EU-e#otd^~FirBwk^}&AfX4A++ zBwnKgl2%G{)wc#Jepb$IS}LgJT{DxHWlPvUM#*=9WOn?h-_Eg2xoH!s+*so5yP?xn zq1|;5mO(n^WTv_1+=iq(F@P;D#(5{*v2|zH{h3VlzBmBlZ-M7O2yd-w(vzi$5trz5 zPyIUGb#f(RKt_GfSyOQ!UIJ9{2B`HG;;o$c0s<k`@Rvi;*Uf6P`xU<Q9~;OWCBvma zWo~KA2G|r4t`tR)mxRjCUtxmr5adO$xo@ExY3!f4E3>@9SsAyE*JnV4QJ=?ZG$<Ob zT|DNxe6`{xonPnSw=zG0m5Ry#kO@}<@fzLa=8P1h@YH)EofR7L?_S{i{x^<oT-O6l zu!2<w1BdO;fKy4Y!srb|f@V(;<>OtQU>}XGttj9ajrpn%<`!FdTh)O1c>S?3R@w3n zEbL6)q>u9n&5u1qY~`LUZK8_AJle}sq(O@HZr>qL!W65Rh^ANvx>BS1vW0dZliBB! zJ*(Vdg;q$Txeu<He)1mC!}H(a`b5R=Rb=0lm*XC$M3!&KK_yEK6k6p}%xifP3tU3A zPuw!#yeIrQ)<Vo*8%YfUCUifYBSq%Gyfig;-_qPIaHTrdi}CJ?yxg!p1Uiz4=1VQ_ z@spc8n&5B&3pP+-)wWhukb4`JY+V$S?bmy~Qs*}}Da@PxLA5ONWW`hGtx`3|edi=6 zJ;cWHYZJPOr~P;TjdvgaEI8Spv?9HNGiKEjUpT@i6nh52>5Mv&laH#b%_`IHepEd9 zP~B8j);tfOCTw9oZ^~aTB|zHcGF~f9((jetaWTJc;!-!KVW!AZHd<~$RHO5NJ)YVG zt`bLYCi8gaR{@gHb7qwp9V()|92N$^nJC!BM(Rondd4tta<rS6nU4PF4=^&qm&uvx zTNfo$nrt|UV;sIT`t~<VohwezK$ZIAUf(GGIoGt_-?qcxX!wUhOuBOV{bbYnq&1_q z$f<vF&Z?av#)cUhmpJtikIUn_+IkjvoeMCl6H!~TgsJP$s3=z=ktvP(u=$Cvlha!Y zR<50X+S8GvL6XW54b$$aZ<H4m0vJ;^muct@0X48cIa55Y&WY8R*Cge>iPjMVXR-m$ zFSp=lbd1;OD~d=WAcL=M3MXfe5n+Uk?lfz{XBLPXE`C(i5Y43tmg?Z%`^53YuPOHk z9**;mOFdwO|0(r-H!fVATXO!vfEMwEMbmd);<agCxhMyZN{|OZ%6a&y1D$f=ec^_F zM5q|-4NuU~t~2zI$iGyc_<krGw%HD%JQ^el^an_OYNcrC-keMv2P4DUc{eyS@&JhC zyN4ksKfaZ?B&kW^A||hZ{(IJg(+x)a|BAE`L1>Y*%WA2|7A-LkyH1IKv{rfprtdDC za&<U<T}g%R9)@lb?s;xeXF7QF8Lc!{_jd05OXnwKDA0EodRMb*e08{}*~6{J1wct* zp)(A;c?=>d=g3>QcUo8;F-s?BKMg8$H+;Tg8{T^x{=<pXICWxkh2&Uz9CX#$?m3ll z&kaf~TptZm#gy{<90j3(g{`Tz$hwb63HC=YGoSE(h7fswD!zIQr4ZSGk-Oz&JIHCq zV^^L^8TY|eC<n6Qm{706^df{_i2hfMOArPEdpp=>!WM4cyjp*ZP@>#StedLMG_<#H zP{@dZjMt>CXH+9Fw(oEczqVa+U|r6G*97Ybu%fG`YfH5FT95kXQLwz;!czB~4Ubm4 zha&)4^VJ$0V{4;a8!#l1^Mjb=1H>M?qW&)Layr*{EU$;T+1E+fE2Oe*iCMX_LQN^{ zRE*YOj1f&YHnj&nhIWOc?<O^jv_>!SKzC)#ztVm*whHvPPa)VFEtQtW;UZeP>I%(- zV*&b&Z2-05bw0s{^5f)!S4C!eAwdA05%=DX+2@AX=7E<?o<iZi><2~g5?mU>niDc8 zUOAo#Kwbukl*fYbW!%5TfFnP1J|;@Y1h-{UbQ@%K_~PF^B5P6~2GlwJdU6MV0kEQ{ z_6FWFdhDL`_7dL*P9VT%D?M)5g>~9zFK@zboP%CtY|qE8h0#SpG-telI*=wnlCF&& z=Mk_)Sq$&!KkizDb#f5Rs-)4uIVtRzT;BmI`UmEZh^d)Bkv!`}%G6xcdLI5zgzgL_ z$PfuN(thhlBHsd{^@|;bkz3ymD3<CrY0SE)%}yeH14>6<Y^RAo0BZa93MV{{Vn>&d zRY6zPjRS{U!>cm!<_*LL>UvS8>|8`dE%Pt<yVqd6((;EhC(GW9e0w`9{U3&k?Qw(W z*$%4UQl1m0Rk$AB>}|^_%SnMRnX6uW>HV)<M}h7Lp|A{_*$76gzZPX&K*9W$U@m-^ zP?cL{QCjF2;O`D%V{E&?=}{K(j<W|2^{PgNUBXzEjWi)ir6)lDXXX^gS_jG^s_%z7 zB~A-1&)fN-{28W)zltn%ckM~mD}ee&%(Wk1Bpw%D(&q42U-fb9klc1Vp?If$K@-!Q z`mAkP+P^BLfqGZ`!KQ}MTZmGKB0~w6N?)dY?C`9H@FW-m?C)blgZ2RNOs*hmGv^2# z6y?sk6g~`0iDBuUjI*I@I<+zgk=kUGQc9v6PVKuQ4Z7)Am1WX=)%TzOv}XlI@7eP1 zq4CmV4bTZ<a4cdUp_zJ!7TG^QJe&Dxi@wViyqtkSy{!n01-i{*^8}qO0qvODk(@l- z14LKoJoD7;fmS1@+mhihslf1Xj%$XZsw<>E54Ra^GBCd7u@Cehwx{qSy-&%>G_Gal z@ao(5@e3UBzLgO(vSEP5{Fb!`qo<b-s4|tYl*KS#+!0Bn-|uRO$215VFVjZNzU{_& zV&YG1<N-xOSJ{35v*Q25Nk5}S1gJzcuVw`e)Yw#i6>m5&rRmORdyDmF$gcy=z=)8k z)*yu37g1FnA0)(GXVw#iWX?L6f(vi&A;wi^6EY!#rL!a8dq-D66ynS<sl*R2f}ik& zm=X|z8f9>NBo<#VeMnh;=`tq+bQOf6z39L5l69_f>bPo{Vp$>83MzT>;3a63?M<sX zzVC4v!H?K+;yD|_#TT4;&XCnZ0lGv}Xd(u@QK_%)&rj05N3LJr<7ztZ4*d5lDZi8r zQKG<zS)K0GthTDN$7&}!e0~`X8Ba^H0|`2zr{uZl^B^Z;4=3224iMKx_{0pp)@g*& z3F1*bAHVW`R;TUW1gH&blNB~!u%&4FPp-q72}XQ_j2x>40y>oHAuXCKZk8+K#5?t$ z;2cfK_Mf@<H9yRGQg@v_+VbP`U40?X#ixSwrDFfCnx8G7wDntKMY7Mc<BhJ%{o7ZE z6%uw5S}E&TR}zeAJn8}6@qXS}aPo3Imr*dKj50xI<$PEjsP<b4mC1@N)!FgTmj8cu zF<@*2_`S~ACiYT86aNR*A|;`Fvm*Cq!MY7FZsS<LK_=kCJ;7{ssZ8$91r}7^T~NW% z_$ALmYX%IB&s#TQNG;(tK0(yh9XIT~urO-SM0lFi*|`fFac#=fK8cine!&n0CF$6P zRmZmNz{DwA@6bwJj=J8wi9+&#1S)TK2og%2tlkdyjtS@7E6kJOalZc?z`YAcH_j~N z&c?Q7V`J->nh`>R`&=dw`<wa^5|Vvkd&uOc3|Lc7=$JdEzAK!@T_gn(8;y<39S^_3 z2<l>?K$EL=+c+&ZjaGIj`3(wB-E?g2PVyglJ1g2w3C?DOj!ro+70$#FoY&9xX8y$t zdW@V0z!yEp74;#fp%!S~ck%8qaSI|KIe<b=_$zN8BMda;mSNRuefxbFI;HvByr@#g zLX)tZV|-gpylH3w3p<96D%iF;WM~9z!CoME@eKJB_pmJR8x2@25I}NFNy_P|+NK$+ zdX=AIWP_j2>0w6*<9Yh2)1E)Veo?4M&pJ}+>>BJ}9<V|?&OVh~WQjP)Nj3+?NcYm3 z(XeDX4?iUMwgKZOW@rpjMFVON4ldXxhoa>-Dxy{!)C_KJak=AV-z(`zwrhWBBkfwz zMS2rlx_scP#`^D(E)l>h(8jelAIL4Vid=0*tmAyYOlE;8BY+(xEPO(J{}jO*mEnhZ zqe@H^PglS=sIyg}7oE(6p(8*t=Y4v9U7W^>h^AwdL6YC9IIqYevgvIG=Qima>)$-I zBTDZO;loIY_*v3<?C*OKdc@mZ0C6`NI`G=*0gkQ8v){h**^D<mBXEso*_&LJ308Ot z&~t8_2zIbxy8g%6k38R1`)vp140Ly?iAq-*cP-qj=0+cXkEh;GrF(y$7|i->^vOtT zQ=bRQ)lwM$%Eh(ArWla4i5H+Z;apn*qD61O+4QdVRdw1~?(Of7Q{e8jl5Jlzw2tE+ zvc`&t|C=A4L4D9(3-MHx=g74`XK|vJ=zlZp;CRw>y(7d#SN#xJPVQgGLtZseIlod~ zr0Ml%`CM8+mYOw;Bla}n(c}3tJxVTo8nfq1G5up8)T+K2G*tV!m*4xqI;x4|DJ``t z?p9wF1~rP1y{LY%uU*3Nmwcl-*LDZXLp=Dx43#7587P^9Gxk=pAoEWib^*dBqJJQ< zU#mCaePF%OE*HN}zREuj71lMafj<HH9DR~sxpQU|<ql#DpS|~;({|ZA9nPiAvv>ZP zW<IZ3-Lwjx_Ns%zPI{iQfzd(aKGBttnd*!D6gcPdwYnc}^HpM6+-v~5Tg}tPrK++{ zl+Z4f)wyM^4mh_)M9v-}V0Xfuav-s>e_;&P1`Zx)DEuYJ3gDOD>Dtzy)=HywOVgG9 z5~VKx)I`BP-ViuHgP}h`^jjdHDlMOt!{A>X*BMoYjPzwbU}trd$x{@9Vj}yyVb_gB z7kfZ3ll7frD?8{j&&_>zxSflkzO;Y44fIK8`^X7d8uKU36@{ybzHQ+Q?RgjC^AJyp z4PUl|w|hg2z*Lpb@)j*-K}3>EPj^sAaX%BigJ4M3=Zo&6BcLvTcd6&%XeZ{L_6Lw2 z0c$;K*)B|G_axQ3zpOkGc~<;}&36Jp=pkN&-sO1kv6Wb7{uqjilq$(G5BDz()P`Q7 zFN%pz7#Hv3%2_RG#A)dIJ!;{ZUJqBfJr}Lsxx<-TjAxJ@CiuYaD5o)cY&BuAW~#Vb zoFc?=S91ztxN~AU1Abh+2@_pQ22JX-Ea!QD(FNt!!xcc)j`u7>z;<D=N{@T<r~8_2 z2zVI;`)L#Xw8^_Sz*1~`lQ_wvOa*8W5p#Vdi$F$}$MrUTDQ8~QFscZ}9#tc9X-rm5 z$2SH&CZMbMk}B}CNy092v9={^i)RG)m~yaOd_$}(k{*z(HpZb0?;j^*$z=hH76(jJ z3AIOahw=YBO8QtovHJMo(a(J;H8LL4clY1gZDv2EKeC{n(8>NDp)UPm<ISycSAAV| zf#S`$USmUztwlTR%Chqv_v5Xu=9VnxPL+>7O~pn{cyA1MoIE~PJ|r00>bbQ>=VJeE z|NWa|6$o=)mb205$Q_r`&&?3)#lkVd;?<?{vJL81z0vo@<woQan&xRsYb(<yhN{*d zW2LyPD!LtFu|LbjDCyIsDBQl|Cw1X*QnI<vxh=336Jztvf_kjP?6U7sr(>!>(=~II zyAzjuacvb02*X~s<C;M~k%5`fucjO}t=>e5&fy^jjKE>Y?b5{;m>PW6$ab_q!KY;g z3^)aP)PH$PoR3ald&N$Z@xIU$Pmb}bW_R`PiqcmEc;*E*Ma<hj9uJ5bq~=^aSg#|3 z%<Bq;O34T^KVlne{gPAet*$}1r0Y*`zV;*#T^=X-WIOyKYFk#kQQCl#I^<$%sO<Ev z!G$;eg*E;BH?8gziaMV$ld%)A7Vie>6*Eh^#OI*p%0^~K_6aXLhA){7RCUP6Zw5ZM z=i<bopOgaApoGkXqB3kt@63HKC!)4`=Tvvkl_}+iJr|uM&SMQz-8YyAZ?mkU+aUvI zme}l4W45P8NJZZwcYJS+hNwkQMWk4eL)m!}HTOX|oD6yb-6{c{`xg8n&EsSh_uX+U zD++IJ3eOZ>D@Ps@O~_s8>z~q08!nU>rEGYYpIQTx;j+C)3ODR#^@O_h56Ld%cG7Ce z#K$K#M>0WiOHFD=`__l;@iG+T*;lYnyGJZgA?cm2yx={Du<8%xa1G(F*N4Z6tow0& zPpAC07>#3(zlD6LgNyY?R&S?McCRKn-Nvg~WEMMH!xyqqp_!40vD|I|#Th-~n%TVn z)`=0zq>?BP6}~yGdXp6GA1%M;JaHpWVA`Jhd1U{yoBB@gW;eh)In<w2S6tzUp=aVo zyqCm0Tc?s+VH-_tH7Hp+d4UV<qv})BHKcCN=mQ=XKx#)Rqa<6L+-)epT)ag8*tL62 zu{~rom*aff|4OQGm2!{G&!r@8PkY1K<mH+WJoChufJY|HNj9xo1#>5lA%FqW>u<Rm z_4zTL>mf}@oTEmQY|47%@)vx{M=~N?9#HrVSq&7_^i4Ee6ngp!(M?sMP|uMR%ILED zB8mC~S3}1~apfFpf3x{cvTgjUa*imSN7yNb)mi%w-$X|FZHP>iw9l;B%u!*U^&~2O zGp+CSKW1XzKSrn^A+Z&Ztf*?Vpx)Rr_OFy12!d;{iciV-NP1z9^OS!)xD2BCnwniF zM9AmGPsIyczf@{G`s#o`pnm*1Y-F!)jXgN2z(@xxg6s>p`4wd*lQS+OwzPe4FVIk6 zJDPaQ&bdKfmpotqckUU4?Z9EyUaJaoclOze6Gw=MtT^dD!sg9mHAh6r$>S%EhS%Q( z*nE+4xX6I}KL8-Fxoh|Nq*m14*_PLp1-8y;waL|Vy&T8{wf^Y(|JZu#u%`bv{#QUc zRXPP!O1g6>C5nWAgy0APX(rvxXbhBQ2uj011V%Tg#AuL)k)vbe*v{MU=XcI^opYW4 zcI{ekuf6X3bw8hv=bRIgN6K9RH*S*X{aL%K;*8<egF24LkfucsCPK%WF%PD%y?Ba| zH<;zIw@9j{-{g7pts+hs<hyxLSrU#VBCu<j$GK`CoIRJO=qD#lGvr?11kGR|hm$2l zJavn;I8cLY?!Aa?q8DH4-#0D{Is|h`ucK+mT`}b<*#hS;cT{5yd!BsYx*LxiaV~YN z#S|M@Q_x6CaktT5FcrE<2U2a2eOUY|wSmT&rF5{`Go_T~HhC$JB?eF|`S*Q(d(0*m zR5qx$+|*UH)O+#t2_I%eGNAdjg#Aoy@v;3}n>+O3^RfP%gY3!RLyv-img#;4zdAN* z27i&uW%;?>SC~1<GSE1~QZR+Y_e9FTOL_kAYn2!?lX*TbrSwij6;+L_v2yq&gW(wu zRR@b)37-313M9n1+Yu*a|4W08x86z>CLMIHeJ+6!q>2}8W|yh0Y+(@)i+7yf53*46 zY22|Ox7b^^ULWr;I~7Wv5Bl+vMDM0O3em`hYBf!{Qm~zaLov#CDg%j|>nF(1mcFqi zzZQ<Tv#ZCy4VZMa)00v>M6#p&r|Im*FWf%+bEeg1C3-r%H%OToVP`+G(5WGejl+~X z2%)QU%cF<-+B`0T+x-aaAWC%E@KCbn<Dn}yl|0jIOHTutX;a)LFaXkxbf}~bC%NiW zphJKyWQ&wpw6h?%$y%DS*T@H1YGdIsv5FZxx$g@a%G@|qw~rMczSh7&x2AOA2728K z-J&!amh@S1+CS*@LXB!^m*`d4`eyZ3-Q`|;>hQHgEWd4UZ5yw<olFa8X4vu{{}d6U z?5Zb3G9E8mkM*Q~VoL;nptUtsYrFpn9S~5EdzKjRIP!``_tmyQZeHhQx;HE#2ukVq z{0e|FFEj5;vAPHo>7VoHd`qyX9=kYjZe&Y-5?!L#?k7D(T)Je^tBNII!q(IF&g4vM zDZ^Qk+ag4|Y4<?FLtU-o>w{JB%3dP+S~%zB#g)I@9X{25uFlUFkYN4wml}|;G+R2p z&4lB@^e6_ej6&v)%Ji~egBKHHy`SUJJO#N~kme~X{$teGgW{qrmG<h>;0*Ud=V%U0 z4>whx%@@ar#jyF|Fcr-}xAshI`Tz&SiMBINtb;#DD5jw9`ikS$#RltnV4mpHQt8hg z>awh3_Vl`p$4(YZZ8W{Cc9)2IHES@q#&tdVquR)^{j#Trh3|H@6_f3Lut&#!9@L5{ zq^2z*A<<Y*F;JNgW!lSz3gM&y!Ggh4Tfs>kA@vQ|V{J|4_11Cl4B&5PoR=7F6_u8a zUrKu{%U+uaLRr`W1$7uuDRNm_3ork2s7-&xQIGrEz6f%du@C%1{r#J*PS^h<wFq_g z?KgQ$8RXPG7PAF2&iI0}yXnhlg3>)DGL6tUfANha?Hw;pALd|Ud>^7_tpSGODsdp@ zurR;6*v%5#>PnyBaoTksA>64*5?l81ts4!K2l>7$Ln|r;%JW~H&K@rd_M#;mp6Wya zX6%AQhKxz-cP{QfJM2x+IF>i%50kR~4qJ1!TjxfI(#v*=hs0r8u%*W<Iy$*b!;e2- ztUe_xGt)o0@KBQ?>64zUVi^>B*4Ew<Bqz@m--#OR#+t=h@(XqvNXfS1IRO(3!M4Pm zYrH6PR>IEWG6(m&n|IdP=dPvIbF{3!2b@pUj20J>xm_08&cUEczCRmcw#AyZ4jVf# z25(vMH+{$dw57!q3;@+vtc>36i(3U_hG|=*AAXP(*cvd)t`{{3?m#!5w>|o+p{1RO zyE&(5@~hQPhCZsZg>LtP-l2sdVfs02-#1_9k;U*H)TbtB-4SuV(<K}vtdrP*$a}7F z{B&uoXY;4#xr3|D)>CsPP^`a%MatG^&5*cG{$_gf^Ed3?RiQq^+9^#}kOAYj2QRM7 zG9t<{yn8qk9qt=ei!zi3%jRZQbdWLjZh{hI79%T+G8C<Lz%rH4NPQ%#S5|Rm*`UWw zr}S}SZkHd$@a-a3Wx4#&yu+!j3X=G5YIbm~#7c?>zE>OW;<CEE%N8^(HAIC{3ivse zPu%0_b_n}R%gSRlqJ`}vBqLLvzvr+w%?|+Nu-v*3_0=-TP$$^^K3B7uCkK9xHpg}n zRVeyLhZY<21nd`5Gr)p4*y~fTh`%_vTS@Mm1SYV<VEW=e>`_lCtMMuDCqA2-O80I_ znqTWOlVOOzdNr`>b}G95vx6wrH%SidE~e0yFRQCo4~nco9+Il6WWRhS-Za#ieL*3K ze)+TRru~&oc}7@gij5m>pKXH8rINAk)jbys`O^g`$%)sRdjsil73l*VTEv-IZ~YV9 z9>*qjlaE1iin(3Y*w`A>D=)Z0qZHOhKe?K*dCi97u$7eQ%i!i|W8(k=GkoJfealSg z{srr`CljYlsl<H`eMtyepxB3n5wK9;)4-X2G1=T6Q<u(~kIMX^qPd?}WziX7Hj>q2 zvcuo5YF{y0jNzb*&kel-Prq*Xt^~njw@2yA|HiI~#q3)v-MP5Q;8U#^c5v<KpLpb1 z>{NVOMtvZ4aDP4=55<|eBikTfLKv1Dm=hND7e0V>FE*G)&K>gnCm<~;8HU7Z5}4+t z*HReU9XFxEjv_g;cxy)2PAx65J*XICskLbPZ>CAUXLc6#Q~B*h=g(}J)))L|49bGP zvs?w-xteh}cPPs>@sO`Q#YkMLD|Z4>iT+BP7GZzC_XgkArJI1-4Qm)4+|}E47IiW- z*_kfrAm_eE`>z@I^>vPG2eG|cbH(peWLC@clKmecLo4pWV)IAjaC5xe<pvsY-=977 zvNf@(jdYiAa14M*6x8j}00I!%9_3Cx1i@A!s2_?7Oyy0KQ?3tHp$r}1YKLvdcVBKu zjx2+h+YFYrU}fm5zn_cSitD;vAz&=|1GRJdKI*Hdhyo@|&WQ76h36j^P=w>(j&ySA z<+0Pw*>5E4zQ(DMFJ48j5%TU-+;w9}VEK9uaMIo}ukeYpO)afMN|j%@MJ>aQmroB! z$d0LFRetbqmu^5fn874pwaThm3rw;o8)zhxab~p_3QC54^H0Q9wqVDPG8jFLnVUjI zqIwh6sjEXn8wlNgny7guX<~CHpqQ`9i{Z%#`cVXEuc?n4AC}J?V}IWb59?Hd#mtNs z`~*5EzS>X~uJ|S56DNa{)dJI@u#Yn-A1CYYp}9LfIUeNxIm{{mh~DMV(ysx5J8A*^ zsvyh5B4s%!ltIhfB2AvsVVg9)ngaNw$eDhpjI7(pVRtWgUT(Np2PXw^<&-d!6`i?L z^|@S+{|3Tv!=Twz884X&<cWCPw149K<$5pe*j<A0&z=rlYy_o~_^KL-^!k04u6!0f z67J--3dC+C%RKB50KL>Ia*tW4&&APuScdB0%Z)BL(#dO*{9Goy>mS)CN6K43pS4^# zsA&iO*)}TfaX(Pp3;DS#fsOWHW>To0YQ8b=$EMpdvzeciUah=z=yvOZvyC6ANx82{ z#Muo$Vtjk?lpSs*x7WK2PBc8CMIbzPngUrHYuN+t0>Vv#F#(3YD}dLYb24Hq8DXMm z{S?{r%@~#&`G<{p@k$?eL7MoBKU;ljIVEY93LhjA64xB#x%-A)gH^XOSOkxiFErD0 z8D-0I>Ese5_Er|PHcxI3o76I{Idl&AA~MEtd_h_~r8rEq(V6ew&2%#WWm>qbW0q)W zf6M#_&6u_&+kTDKFX%oD-ckHqtE^mZx%1Qo{|TZFpT72lus<_AS@6SZY;3?%@>mKE zn~&J%HD<khGC#c^-=t=rah#rC^K&{*Iz@i={&T_vsfCeQSF#pzJ}s4*>N{}N<f7?z zPZE*)nRc>I*zv%y8h$^$vV^%~Z8~iYw!Pd~&!X(ISH{5#)<;&u4k?2L3Mb{yiQI() zwydwW0s3#m7|SsqL(!<)PJpTr_z_Rk`{rjri%i>O*59BPY%RQgxukdeGxYRAwIW&g zhQj|eO%c#g-ADR;6X#d{_1xksYXI84&W4zxK4#31(U--ZFy2k9CF>Bnm!r?J(e%y> zkXwlmiyu97D;#fG)tP&m?XE7I3E1iO0R7T|NLTp1KcKSHlMe13iK7V3C;*WbJ$qbH zrED+QAM@V+YQ(^p*T4UT_Z%)X`Te(?*yL9gkqZecDqaL`wL=mz0&$@sH<SZEOidMY z7)5(bQ^-%=ty+D;>#mtO<a<a(GIE5x51DEvQw|k*vu`t3mg_by*~$42Xm>=t*C#55 zmM4}$Ju1j`z4R)Jx_0Y%u%2;SmHi*5u!XEJV6;kz!z({`E&WC$1o~=zV@RqO%SKpZ zqz!w?(aF4NHN*3I&zl`pa(dQRV!`F<A&FD!y(U+Bh?s62<3XI6K-{v#asoDg{mz%0 ze_)F%>f{Ou-<~LV&uJ@`T>og@D<VILg`-lA)L7Y}JTC1YOTG5i=M-pFqiWH7l}9&7 zw)=fBl&FEZ<tL%T+Py$@`izGJ*Ahj+k2e6dimQ3}`}9?loZ(X|y2TEpy>jia$v(=^ z7^&)4@!9lPJa=jwa<Q@d{?i{GnXtIb$nA-NU)RSlL}Ibw{v+Gcz}p3(KC9h+rr<fo zuN$J>b{n)7(df&1?hS0s5>uaA`o%LbQ^nz#C1`)k?uBfj_3XsyIH};kIk{BR{lY&k z+3HLe;~BJVPF(GxsaMPIHJ;V&e~r!B{%E}PXR^bguKlk$)h8!GT()VXK=lpMcML1` z##JXaCl?va@OtZ*3ER|uaZ*N9!Ra*G5rvEtl$%<AbSMy-UJ+X7$M^{w05iGa)w91h zb@!d~mIJl)E-fZCG=z(2{B~WP3NBMY3&g>nA|J}^+RE-(s}$g;Lesqrt6!pxnYpZ< z;Yi0Lt$#VKyvIjBS3tkrcv|dq=Sxl1*`Ayps9j^9s$3x6(DYh{Jw9RD2s<x95zW;T z`><Q&!BXiFBG@S!1w;TH%qO&!i_ipB_qYOD+wvrBL>C}E?Tp;78HS<}j4MApc^k`w zIknp&42`c#3UrQicVWVed8-~U@QSdwd;OA>OWq<wAT?)>QW-3wHij>h7*n=gr*LaQ z66^WQLag5EU7bWO<7Y{1^AU3PFrg_tWLoM4?7{P@!q^Z}Hx1=I2h`Lx>j0gW)~(0C z;+_MG(lX7oUtVvghS4+lpvZp)#3rBLCCEkapW^NZ_P7laIzr^@YO*A=t2~$LJ)+Td zf`lIS9UCjG<dfs-WHGix9P_gDp^Gvd!sypnYWE(zR8J8bH}}~x=c>w_S9W3>o&g2f zmnT}7o--LYU?ISndGIOHh5B(lN*#GRr)Mld5#=U^j||x+Kl78n^yJ%X6Pd6Bs_vFV znW?zuL10hh@(`V)6qiryU~i>m^Dv8QGW5ILP|)XxKUPfljhzrrP<iC_JfRAlU`SD~ z+Yjk)AjsP9%yHD3Q)B2;UY7)XM0CEM`&KV39o=L2q#;EY1P?rO+CTC_QbL&zVQ98; zSZ4>$?R-Ol`Op}_r4tShBol7#ej*@AcouMc*WX-K@nM%0M&e!Yc&}LvMg2x;E-BEX z6&JByzG2#{-Hx8h=l~3xdy7{r$5oZr$?xR;JXFmX8(F`<`BSCWgn@Nw@7&I-KZNS9 zTDoOXv^a%<CxOd^6|cAJH+t3jlpbxVuD$?<p3U;GC_KsQ6-M6QVUMG63pYQUi=KDo z&!FjhzqN1?&5+n7+sq7T>?_AypLQ0!Uq`sO^(6`>NUl*>Toy9l8UaSS-r|{M;;&&{ zEqWcF(O#$*GR$rc;v$hnD=<p&V|X})P;`w88_rS1y)=rC(7m8w=<zH`M^0&gZm(2` zY1^GDkkYA8u|r;2E~Q66rG_%P^h!v<gG%b0&_b63=P&(p_Q62A%7MM)@UEWv9t_{P zun6@+yDPmu`3J_JYNMfHp87&0H?4svr0x}M#iP#`f;N+8E~6@nc=NBm4kGgk%JrA+ z5mx4HK38aoNU!ihbA`B;#97c{^apcj5g*Lv3kl4(<%8%NX|M&%R-(*d@C#{KywHV> z#fnkl3IEBm>Hs@w4<sr0=E}C+6>kmAWtN02TH0Yr;!03g`P1I?JeQo_;_#xce#;CK z-v^3!tyF1<6mh*jJn{#&%-{*fvlYkjmd2qk(^GFO@PN+Y)$$YBd|a7WJ)7<3;Nc6L zKh5c9WZ6ff^ousg%J_sG8vSjX2CqblR7|yf2vu$+3IEHwG2)lX;yhkp8V}Z16HjaG z0wJZ*21*eZ1=!=R^vCmbV&$VTb4l_tf`a(w$8G7hw*$(<O!!Q@H(^W&Aj?;5#)mg~ z?Ok?VjX{H;A!Aag{A2taP3T^0Oq)*THsWl7ITo`SZnL>jzznD9Z5{g27Fs2Y%MYO; zT|29{<D0r7?a#|i^I+M3i`C>$DSIyYvxqdao?s*GN=P?~?j7MLp!9WMbC%z(o}aX- zq{XHFKeHb|!ws^wZSCf&1TU?>y@k81b!!LK^GjuPZh)d&ADY>2W+lY>0q*?}Epf0S zVFlOZ{^qUn@>tNwEXv0*URNH$S-%^9SQ*?B{VFU>zuM}b!FEoCw&(TfN^42JGUt`9 z30KICLBCdrp7Lbb;PH=yPVYN_$@JO&_MQ1$2M-~WUQ1i%)rio&*f??0v(gf}=XzFd zF5Oc6`E6Xl$o{j3B<7ae6C}pJqeUA4bMgUFt`UlSVK>e*Ho)FT)$QfV9dGq<N25H= zyG*h3V4AC-&ptoYiP><|#Zu2*SOz|Y@%lx8$JWo6?YBS4d6UYLEV0Punj0;zKXzaq z4e^|z`-Eogrcj}zJ{MHrh89!uN%r_1g1@D9I{qNY8S8N9T!r4)qSd-2_c8g+&<nod zuotZG=&(k?vc}3Z3&mP{$6-aectg?^41Vm83r9(^*~Y-3eR51wUqWpHOs5w7E*zv^ zQ|luq5Hz5IzHLTJdolKzvjZp>N?=uKU{^s78;h-3GXaG|=cu(uiCtrVfw-dYZ-@17 zX(`0aogfnoHf(a9oU&MO7aSu)oiJyh*t2I?%4a}!jvo7mwIrk(@8a1Zl347%{nj0y zj3Kgl<XZLF-N#4fD2O)LB*Rzyg}q=L(ATs<M5sD3-zceeL5FwO%`Mm8<h<Psz}AR~ zJOtZHfYGH@--oQ4ZyQcwjYsJ_E)+fDURuObUKyTmcYdQ%K(kpOVOpC%7>*ZNrlyt8 zx9#NYuUJn!X_-f~JRTd5j10k9+@U+M!ATPNaDc%2Z0U)j4XgX(--DYs4UzW1%Cg1b zlgwPTfAM3F*EXSTV)7gklGQk~>x@ROww!0@UJ)8Vg-??%(}tQ_6lgR7-fhmo(mG!d z+u@yo-@)fsyAEER4e5@uE503S>E@HI>_E(uMLSbL0fqnW6P`olwfKvskzCP{X4-$k z@NVtOiw)i^UA;v}srgWL^O$-0=MGqm3~~&YaUn~l?E~y(NW@si_clr;_E5j95iqc^ z6d+7~pjncxT8}g{7S5Z3**XP`GtwZTjlVtm8NYitk1^7?%G~QEip_l*K5KB5>AF)E zN+tS$5(uWxFu_c<aLmQkd%23wcuL}MvTaqMNn?8{Df4d~`M_g?KU7;MFH8v|nnanF zTOTT2dj=i5TO?flEm24=mS9!lkgZ7hipv}hUbIde;Gf&RduIRW*PA9$z|m|u7bH#o zP+lSti=5|nSm;(ZXZ>RQcKIc*-Vs?&pRN4f-!opD8hA)X=E@5bWzqax*{=eE9i=S^ zH4mhlh>UJtZQyNKkz-e^kwb8|RF=yAhkd%Bt{g{D4!H9Xd3w?@w`}3^!i4}{on1Wt zqpea53uliAYyJnJuTLv~(uQXx)Vgu(VjLk#im&1W@fDlsK5rW|R<1;=^WH#2#H)x$ zuoUuUN}-Bwrte8QcX^lAd}dHez;9si%T)LQd(_x2?@5dk((1gp-a0CG5)7)=tp~!1 ziUSxo<$Z)W*^BpoX{Cmu_(}2=hH8^8Z=ZZ!hA~;O&c*A|T1$ZGDnfCvq3@Dhdi;ev z>5HNi3YvH<2#-Y)Ct}$m4=ANTo#R*5xS;stmY008KC6dMx<vb4_QK~|D<y2Xe+=-M zh2Z`Uv>mqgn>TH_0#H<9=Akq(S<W%L87sQ_mD@!#HT1nM&};R6=un#>SPbsFTlO$< zP0;HdA6a9TzF+z_x1}fh(MI|+ca)X$R?3hnVG`b|E~V?}E?`1kFv>a4XAVh^ynvs2 zbCjYTPig>GWcY{$!`IN4sZd(>WGJ`{V&R*wW~BW0a^s6!eA@`$B$vkW`9|rv-B04Q z)<(p-Qdn?Fz(+pZ#dD>n)8YOT_aTQ!CRBa<zMOa#+BRhf<lEgOe45X4#!}?Ts(TvX zF;t(ge5YCzgr6fwG0*L&l?uXJkdrnMgvQJEe6Ov;bzQMotc{A*pRF+Q{2S*?|CYwP zhzN7}^_%ltOQl>ow1&Qa|EBNkI?@fGWk9jVz!`@gXNj8PfSu^$n!U&2gy%wyw{gxI z(8+N2^V^|R|4u&6Ed~IcN`|84K9`rIjP3=@z2~}z_cZo!o$Te$R$rwV46cJ2(19AG zE^!?nHen^biv8$LWN19wccZx@sxBk{PQ(W#O4(mrY>SCBh3syDi>khsiEOj^mvsix z3z^;>fK%6N4x@5>Atcv0ig4ukdJOVat1({P_$2o^ek&lxZ{nC7?SJDql<;JR6ro-I z#@%x{8*smWXC4G7!dr5+6>LbGgZleGMzw159Mpr7?{6f-vu&n$<3YEuAK&k>qi)Wr zL-Ebp(NbqUyx)qr|NL09nTN_Ys0fCO4Vm0630PSkdaA^Lwo_VRp<2YSx*%Ja`y4kj zLamZCAQqReJI8)*+$}Ghg-KA2`zMKvJ5$&`Z6+DnxC@X*d;C62^p>#}jy3&K44_c( zsT#ruvD}-b9G39(prB9Ly^eg)!{d)%GRTo^=GW~No<0Ei0EMVRFpn;JQtlDJPcI!< zlgnqQ68C+CWjqrE-zYjz^Lv)(@XZUbFvCLdOSE#up1UQMFaH7!mOLPt6Kj5{e04=S zg?cwmTT`5Fjims5$@(K?4t>zrzl_;(%FUJDfhYTCKZ+~J9&B)=bK|2n%TN<LSj2$a zupV`8w@Lg!C4bcMp^VZ9fCbEksRsLw*qW0DYWFn<khyLr93AUV+&P_33iHZ=f|T~U z?7FeWA;is_7IMlRck=h9r<_Ib%{T90?5~`iDoE0XbF93VayBQV(`7C&tw1T@s)K8T z{NZ=DB-=P=&TggwZaj5?4e+%U>-e&4V(rR~fp2b%VOryt9<5R$yiOtp_H(y!{wgxr z$>2501N|T0OhEkaq;MCS*vcS!YLT#z%1Gy5g=E*qK#sHMvR9dlPT1p1acAL^)f5C7 zEa{Z~F-la6&lK0dfNR&s7)f)EFiM2H#QDoV_&8&rd@?FSRfhg8BWJeI4WF^Oyl!*$ zSo&w`wBh5%$zP<I2D#G_Tu3$F{8^ux{QkfBd;=Odcvx6{G}qxR_R+X-W&QdNR(y^; zx0C^=4qDVVMz?NpA^ILhuw~!*3p(qm7^FO3FUcoY-}E{8$m0vBv|@86JUV@?(kYe~ z&?>*8CJ^$}TnrM|KfXGfKZ?G-gE#K2t<hz*+NxDSXao#xCRxRI>JNs``g6*9mCR^- z%R79@>`@geLSf=5D!63>L+*OmwwgPzF@L@Gbe?<Z+quxzZ6&Rxyc>jeOsMLT-o)<3 zswhN2+HTb!yv$-_9a&-o`T*CvY9gHrw42OI8kAlJfwue4^PE5$bAbj;v73bZhbn}W zw(9d_DN$}ttfwzExck<-B)us26K(*;eCcEecVj(!)P{c0eXM+TZhR}^%{8UZ+HJC~ z=-6W{-<xEOTc&V3Izo_DkZ9f2m&*6HqO7+t=!O9j9bHla+=WpT+FPu(beL`z&upX4 zq6;t(`WTvcgLXg=S9kK@kvl7!i-^;@?gtpi9-hcy&&tvhc)#Da<r6a&ZySE+j2Z<E zpKp6<kAZ}KW925Xj%Ub=rPrmlDyfNoLB6W@nU<vRtZgGoaI^sP%J*|0RZ=*i!Ii@! z6W{Qbxd^gpLvLmuK${tqZl&z;XTNW!BAy(?VtYxUWb8T5X*~T0vwVsigp^!RNh)z! zT$<|4FPu8(1Z36_Pc^bK_f^Xo`&#WupT(^XkY1ch>6WEH$T^%-is5lYf5X~DSXZX{ z3gkvOBRUMP|Iz|Y-wVdn9*pZf&cYqfi;YUtV}clC<*YLMpa63Fe#v4nuF7f3YPhc@ z?m{586)Ij%gSPs3CZ_wMA0*lyM`w@q<i;LdQwEPxZkV`cKcD@23A9<Hy+##|k#(+J zk+gPlP0RHYHdGmcV{}DmkrTE1sav^Z_&E;GeHCV$31N{hP(pnYD^clkuYWbdP<v4H z%lZ8B1yDG@$qwUMdbsJV<WUmsY#U+}a;tEy?D9IYR*WBR0|saaET}T{mOH$tl`}^- zz&?2b8YGh|<=Qo&dF=?{u0+BMI-I~n2lLq#{}#+j6i(g@>sjbBbgBP2N%|5nTfdjP zl@SW$v%KP^uGb(+ih93?WpkwK;XUkgwVQjZL?Mli4KIg+#=$Wk%Hn6^H4trnMkW#r z_3w@oo0EatuD9mj_5DX(j+t2Z<aKl^4dI&mgpg)Ve%14LQ@Jd6?hqO6Q3GO6_M&!! z?sqAV3(n<OCd}0>dnz<;+Rb$qS!cw(>eM&~9*0JA*`HUh=kZ)9^^izLj0S;DPnngl zjJ0pg6496#qb%z&-#@m*N+A7MYjQBt=dX&dC%BS^fqr7A<@O%RC?zS<mAR}az%o$z z^DqNE-vrr7r&O`nB|W=fe};|Y2f!6Z?G-V?Ke3)d^Xs_AK@{XqTG*xj#+H%gZ{ABK zZxH1sbm{k^n4|4I(99TZ&Rj?C%7ZY8X^hJBc*Ci?Y|0p1#~T<D7<we9MDVu`O{4FX z2N5ZI5acRa#57@G9;K5JjOk>vHAp|*dz%X}n-h4e4A*b#`cmz7KAaCq6&Ck<Kz;rK zX*ck5jJF+Cj8YU11m5ljp(5-7u((3P6Fud<vn3|L8qa{U+e8K)EN(!|ntngw=G=i% zF6EJIXEHHkTr`yVwm$;dDbQ1@Fd2Cu#gazp`WWn&S<|kv0cCbLn}{hGf(~DbY;Js( zBhZV4R3ya7Qe-U>T{KfU*ht#$7ojg<F>S$Iecw;*a*F<5I&`#NqS&*E7rjYiLheP} z1NV}@mUhAK42_5rP;B!Q42b7^=BLi7q7U?EFEzyU_G~6mBX|aTh=rdQJ+E80b{{{^ zt>mLFIFN8+i(rwan`#v3rF&(#qK$nFi|Bu*C3lKn68$9I%kY5uPF~?M`L=Z`K63x2 za3@wulx$;LzEC1CwJ)QU2x_%<xtVA^11~u1FPH^E!P2lhCBgH>pv+Q3Pt)vh&JgN0 z+^E=_gev%yB_O{V;t)6FG6Kt;28n$NHbB0)9+BGo%dy!WV14D#u|Fm+H)@<-hVr;J zi!Eix`7@C`*>xkKm@9zaAawNSP4=Z&pT(Rv*$B%tXitqP-vXMFoofpV+Oy?6>}?1z zo^XqDxPRvmadH3Wo7>5D+?-mPt1uxODTgKV%iFz{Nx$yp2p7rW@*26W%o7qm&P)*w zXamTAZg>w1;!9=il%y$CRS1t|rBM&QyobA&9xD`gNin^3PTlmo7Vi3MP=f!6DGks; zE&z(ojcd<B)6-rmw^M%Rn*S&PZ!R~i&v`x5uOG~G=)*+^S`!q@MZ)cTmXm8ityS`z zvcXIZ5>BNl_DjemGy)mSTG?K@DqOzxCU%>x`4q#whapj)V9FT@V|fi%{js?UURS`@ zg643yWl1BiXM>(cRaB5UHs~xGw?xc}ANwqs&mrb_8V6G{DKXXHy~|>88oV?r@1>Q5 z`Ul6aw_9H|4*H2MNX9Bib`AWoW^DP^-yE-4(Aa7mP~d{pu?0J+=!skWxuMhiK{M4{ zBj}QcRi9CI$QMYg`y_GxmZTH2ZGE&KcF(brQmT7*R$;E{Y-~%j3GqWaRkIyUMPHoK z0!s;Pb^LjuJlEgUB{~aC!~b9mfXEC4+l6urS|WHU)J--&ht29sYhuPELy{vUSM7Z9 zs_V@g;B|%+j=pn;9%B94$eKXzObxT2lfg@Y!=)uL2{msku7=0AH0bo?Zq4ucts1a4 z`Q0KXMO#&^+eADcCJxwKy%*f0z0ux0s9~^i8x<5f#LW8X*eh#ZyuM<opzd$qHgRCp z8pCFicnsx>UT^6+Z(obD?R>TMrT8=Q@je=MM^Yt!1ITz9_YL=Qq^~u-_b_c);%RxW z;|nDJ7>C2!MQ`S(4|h<;e(Cvgqj8m){f|hJrJDnM;SfAoM311SK**~k$z1L)UB1SQ zYPFWhlrw+Ry<b&d^qsfJkC5rU^g8}KMS)USWRP4IK{bi3c{MJPCYB!Aj`uR7D!*t4 z6j^$#FEE_vWIh8leD)TF*gq~2AD!IB4H=(0QDD=JcWnLI+!_aZUWeXmP7JS1>T2L@ zTZ8{}$THDVxLF|2ai^(9FYC;zP`bWNqn>j07^-<Gkf3`xA2Dgz^I#L12EhrMZyNT- zH-flwntz${o~FF+_`LXtI{RtAx1xiUmTgr5x6iX6naq=Fh`ywl#_{sEP3U@ybI>Kl zgPIG=l;m`Sv!$&#Sg1%+a%O>$KWCd(<r#p6B5Km#{Tl&J*z4Pj^b%EeP>P0^oh@)) zhl;vXZNap@*5z(y%vwpzZXIk1oO>JUgFZ4lhZ35yN(M1%E>m4eM*AS@=AeeWZF|Ux zx1%><a{jg3#wy^@;+UF1fyVDu*99^N&V`iiQpY-Xwb=mMmua2*d2w=fDw?Ds?O$Dc zIG^K{Znbe--fTTTw_!%nCXFn{gW`ue??2w%R%wA(AlNaz(oTiJU?$WEQY29M%&{Yc z6W5*_<%YijYmF<h3AtZNvA$|!do2GJ%LDHO&g*Q{@Y(9Ph6;w0oeQ(n|E%o4PLK>= z>4X|>KstgmZNg<=3K0YX9HxaV5z2pf3-bkWg~9+D)qrcFH%XO3usrfl#na49j_*<R zaDM(IlJUC5=@@V!;bqkeE3TKZ;4Dg~TjTno-aGZW%Rl*eo?dVT-rA}B0MW;YsS50w z|0uX?WO~PTZreIV;8emmPt7<Z#-IgSdAHRD%+~T|XoFRg_4m<RRXbFjuB$N@HGdfX z<%D+b^Kq?O@2)uvy=F>@fe_Rt1Y;zF7Kpu3WL_yV)x9alU((ml!D%rR%K1|24`SBh zb$vtPUc5rDRR(J9%Z=}-G`yJslT+~1X=D~fUhN(cEs)sMNZZdMbiB=7W}Wh)&c^^8 z%4g}i(CruSg7Mk{DRiaf7|dgG<P;QAE{i-1P+1JCo7rjomg@2R{J~pSGu!4r`Ld;m z-WGz>*CY-$)<40<-V$>tsW)l?x4z<v^7#6fo|K)x(XDe5amfBva^CRc+Cn7qG(E06 z!G@xwMg^ox3jIy5Gqf@t=wHBzlm{bU7qSS7y1|P?zWk6oT{%^8No--N#cL)&z{y<# z;Y5ya!R0w$d?rwZKaoG(U7B^rEepjjC$nvd50I><0;%yfcGzvlcx&OJ4O5M58oQPd zMI-ga(wxg$d4?iW@j&RAs_KpnYTF>$7H)r{cWWLtDfz?ZGPT6&#9u8@gV-TBgG>6P zF_~dhyQadeB;tF_HbYm>$i3sda&UR{iQOdjs)!pc4wv~Zwl}d;6cb5!Ic#(v!~G6^ ze1v><w?%Ih^?KG>!FagE2z;jMk1`V88p{>DyfkAh@*zrn=;D<?Q2~#WUSAXhUhoWa z^vdaC;$AR=)*yBD=veP!jJx>2!G(e;MWzXp+LuL~fi{)8_fCI#!w;3p$BiWu82=Gw z6|A`u57-J+jNWW{r}ELlfOYV#J?M@zTGwO$nRG#ANb4O7J!#9rD3waV#>CP;?5*?z zzZ-kkCtK&D$+=g%WB#{`MQHzzT>xlGf$PrmZ@Oi3sXYv!r@i~c;ume)IJLo{Xy<_i zis4%KiSBz^?pDWNc%@EGdA+&u32k>^lTH?L?>*Etu!w$`ph7?}ib9=vi+$ob4JPNQ zcR(q!rZnan+<r{<J7E~~FUF(uAL-*=^9#bi21cW7y*BsXACXlw-_dq<|4wpGUQZ+H zV{TNRUjGN*dC4(3ad`-~=4lC}GI>5HSzWCqiOH__!%=#maN-jb?upaa1$uTmG#~=M z2M2-${%_pSufzC1difs*R`2`2oBR4s%SeOW%C0y66Z-=$2|@U{sJ>}@)M#QO^2?n* z5G;Y|MKj!!$-Qq|LTD|Kx-$G^y+28(e;;K>5nQF!wlfF#kB@Hue-RA-!HMMEenHP} zyiRGRsOKK7E!0!+vUx$`{(dJZZA@TxPJPvF6<GqS*KxFL)(?F6uIAga_k^n@oFk6u z`(f{ZGp2R)z^5k!%L+*DvY-5aaScFdkf6pv#j@rTlUG#Fj8Vej7bgkW(nH0pD7ufn z0$Txn7Oqo)R9*h{dD<%1_Pr!3S@fOTU1(cykIk%!ShS_+h~%O-GY8r=z?&!0)2A&| zOrhMDa&n}tNvOBP{+|JdegFUONuSgGz%>3M@^gOS8O7<!(7*!k5lGBB3FkRm?pgcy zVcgr*n2c+72yzHzeEsU>4F8zMoBCgtJPt7?4v(;p{fWsLhfW3QE^9|A9fj<hPQBxP zY56^xH5=hFd~iV*98i0GLzdUT^I@vS&K}_hfe$Vd<bklIG45qUwQr>F9u7>kHNmw8 z9eFmoU;fXHnC$x>7viU6GGAP-_5VmDo}V>&)HGV@{ckTa(FoJVvv;yJWp;2HF*fL~ zI(~TRBd-elB#^^5Q#khN{Y~F|{Uuvf>%gn>H=pa>vC92Xk!A%$K&2Wa^26j?q)9l* zlc!bBR*g*!J;A{mxK8Jp8Li+anOGj8yfHANKYPqeyWa@@IwzsnY`!1btAC%=p#|RQ zyeZU!M(KHf*yEX1pF}Ut%f@~~MQ1tuzhCrkaTdUOn6kC?kMnQ(cDLi?<RsD=^|Sv! zkVgitA^%X=s#dC->6u|-{+>h$B93N0?ennR<F#kYl%>xTC0>Ta9c&*y9HTcdwyR1j zJtwIyh$f7FMPOV)&lqx58V(0t?Us@I7|j^_?-*%OO>nBq3HAQV6z=sC4rF=~R%ZRJ zpx|!n*4*7HTFRxX5pVHfjTRY`{aZpQY`eX&%94S+#Ea^cNeh(;o!_g!#y#bGK`vYp z**Rh9ukoK-q~KU+HtXA|F$-qur=IXx`$UH>rA?6YETwED9$va=Y_i}yWK!Rz@cg@) z<J;7d6kds@PD{NzQiw!@@+v*$=pBrdhTfMSDH@hk(91`I1No;Fnbvk@Err>8U12W8 zdlIEhPP3nl9-S2VzfIbm_yUOW?d7oVG&2fMgG)wAQmO$U(`VzP{hhMI(!#!ecW~11 zCxTtact^uOZ8~?P3d_ZT@Jr#+Xq5DJi4D7k84Pl^b2=(l8KY^ack{?rbD|bT+5Jf4 zO<}MkVD$fTz5xtpBHklk9ZJJK*;EelRO1?yUOS$Z{*q`ZB*h+EBA)*96t1fOpWyov zFeS4cr8}NV8ps7ZMP7~FpEsp(uMKX*R2^<DCr;BX>IMIaO0QWo9^hB9Dnl0a{_s{k z#hmXAVZC%uuVz4eHRVm#o{25RdK~i%Gh^0gf5e>nTN6Y3>oZAHNc=c;-`IW3)xj$b zoHJILzkW3EQ6M&^@lSDmJSev5u?9o4MliwTzIdx&ATKs?g#;e3@K||+^ozgVn-5P+ z5amsDo1aOn-`;NY=ZczLkScE84nD=af8yNon+{I+mBYJ^E5xEWd1}yIyftp;6iIzJ zbJ7P1WaD7a-!+HZE&@TuuKd(JEzGjxC9ktUQL(ilJcf||P<fp^|GUV?5>)D7<-{`< z`ISw|4r&@GRYuBTCK=2zKT}*g)Qj4Fi0p%5qQqANKh0I2*vvk<@O2fD+8xzRzdNR_ zGH-Lu{A6EigJ}9*vEK?v9t8Ich%d5?(}^;eyQlioeEOU1y%*q<=P4o`FWvpq!Xed6 z;N2(X500RL1FfChZ?_wL6LHq0F`^T#6Que)CR@_M8VkMC(oEoTiJ~oOS8-LzJm-gk zd7wcx%IEWpn&B$13#ur0x9n2=NxOVA4P2d1R^<vxJKuKAGe@5pAhmehmju0TyLgDg zgG+$1^;4z(<`j7sV0h}q;K$YlA(pD0==9Vm?D(271yg)apbGhHqTC<c*dke33}5n+ zgYeVr*E2I^GkfCKtyeZ-w!iW0V0<%sQCHHmN%IpD;G*TX|1b!#Jpbdi%9VhlKO)}` z{SgOf@;Vn(TjhT?p5u3lJSAPf^}lFzEdp{OB+3AK`B@<2w7c|u3;a&-+umfJ1Eh+w z;~muBFXUaIE6g|fH_NH=B0x>*$OA$RxqbO{jWC<NaVA0M`y-y5zlOzb^hAQy{s%$l zZ0S;nKl#0h7nVx~zhJmnPNO;DcjHC5F^xLTEg|236^VhK9T=}Yik&IFnS;4)^cgh? zC)t~H=oB>RY*{w==}?Dn?Ty3Qh}JOowbIXYKYBJjqF>9TJ~98@N{e(!_a%h$qq~&s z<B_KwkiqWynleocPv`9eOIa3Z5ZCxh6AwPz*f}A6)N|P6$~sF}wmA20c^KJltVLdd zx4T72e|GZo*P6AZ2QPMpzHTQxA_V1K`ACyo(+6fe)&Em-=v5#Xg9&u8A=#gZ_>-P^ zK3%qSW8#r=Lhn9wQFn}2kq$b{IuY{#sT9aJ(AlkDefZT4PaP2;qLN92#EO`Y-XzX! zhn08OeD*h3m0o?~n4cy4V%66Ya6LReF?|c3_joOJTH+AdlKV;>7uMU%CTwIqJ#n|N z5Y6>i@seud%ZM~|XcFJ0CA%5$cx+uu=~mTxdX|0$Ouvx9$BS`jPj<Loc=wLu-Q>;J zI-l#S;FFr+k{E7LwJx7dWYkb{N3ZXwd#AT8#p(Crh&MG{cPW$dZz<uGo@`zC(SI)u zrt5-`=*9zFiuxVf0NLK^ipoAg$whuinz7zXnGSuE41YiL;X@I_3voWtuDfpPfkqj> z<swN?mjz_r=lBEl_EHD(T*#bDsH#3)TITQomas*ZQty5|GqG;xaEc^gdT60j3KE|? zCl<4^fnQK5t#5{VZg`yp>G7`oB&lm*)U2laL3+~ty)d;U7ptGQ@%2ok{edjv2w9Z( zQ6%7aY<Ov?*RY25e8X7I({Sk-bfsZ*g9lG%77f1X`1WgqF@)VpFZ&$*zAv9en3{Ul z!hM31Na|@y32(4E#Smp#E*qxWR}9UP5}>f%&Ey1jK-l1BANQWBfvB{M?K2DwkUejK z#J1cfh_yUZ&fgpIP$+7yp#zZoT>imQr~y5g$js!FTvOQ=@6)kon~9sQp>-3cTtAH0 z-$4Ly`=jaoT?O}EOmBve{#*sbqBJ+_WC7k@4UVARe?<5`bR}MPqAho<YD`LbuM5I0 z=q~EnS`Akm{=GkY?WvOJ0tRxfTFV_)zJzi{+0<_b=K#}W=3He<YZx@wPNeTpF!Sph z=czbtpe}lUC+R=-{<jdz^Gk<M_b|w-c|ys@57V~afB%Y+A!u5(z4J`8Oro%HZl6J~ zOomGGmrR~V9p=rSiR<LrcYdMz{wW@7@(c4#APT%o?3#S?$Cs|lsTnBmx5?}N8LRq5 z4W#^t0m!2-p*TiaL*XUO%%$8jaIE5PeuA!Q;fhq?jc*#-bG)M6mK&0>FJ2mrh;CP} zuFe;4a5iln70Ax@P|bB_T{Y4Td2;zU+3oU2a8yLrImHKJo0fw1s0W7SXzcbR|9Hjd zUD43g<zHu^z6LJCfp8VS`Rsz*GeLZ-+B;@>h92~3Z**{pS!bM@_dMO@mMh+)zu%&n zqG&n0?Y7L|U_EG36<u4kD;)baCvgZK#g*GzH5rjrnv`Boaeg5f)Oho{j_$LUganMf zLl`TFD6vO$(4Hb`M5e^QM_O`G-@afDY#ui?qhkDZ1g($9hN&r%T8@*coRV@-yt*C! zSCmI|o7v_2pKr_jld5+7n(^$95C{xoX+rffXST%sL&UO%DWW<ZCP4S`YYNTub^~$l zYAAouhe>@mJeK&WOmx#WF`yJq_4C3t@UlvBZtT3ki}n{S6=+%F{^kp<4?OhBiL}CJ z(-JoGQ5~cWPtA*25<jRS2+-*P(W)t@Fx&qg6jO4i5Rn`=E|hNlaVV|xj(PyyCr%4i zKd8%(XiYW~AC+Bdm?+SHgXXUcce8w(7O3ITs~oMxwzw=X&~tf%A?I+(w&<2tFkK9m zDe>3e^!$FY;p7nkl8P4kK^5Xp)*wx5{&$h7?HcdM1=~3A*^v#w%DTn3FO@2yLR1*i zI%vfvic~pY+vweU!M^SA*v2G$>YAfvT$72c_LzM0@|N7{@@7lRCK`PBY*~_hhE$HS zTqrcyYo?}mxh<tAzJ;1Vg|4Ogre11p*Y_o^^cLPEhl20J@(JoH9Y^woV}urkoTGM? z9ltSB_VbKC@BM6|g=8pq6&JDmypT*EK%z2sn&cjp*96|kK6vrdftXV@D8A&1Go-}0 z-F?7Ot_j?gjEfc!Cx%vWrR<9QEV3pC5<=8|3k_FO4hzQ{u}54c_wr58r&VIvc2CM~ zoT1Y8_unQ)4o7dgv!55pQ4gXT!5iQgNJ>tb*2NPN`yP|@eBxn)SHp?01F!v8I}qB+ zUZnL5fBaH}52-nZAtWU<>T6s7TOUXe?>aY1@nP0MT6<bds7OSckf!yJ>D5eR7gu3F zKfam1?PabeXdlw@p-QPzcg$lPJ=T)0VN2Ae@jtXc{(pQnUG!8>9FXI5a8jGBLim!! zsvq8XUGw8d90r-YCCVej6|+MP;2xe{wU>4Z+-VJ^*<1Jc!_MS)zJWzluo2r<Eu3=( z0|`|m_nS!0Vk+ohB~QZp`0Y*S0GT&IY{W>cOtuSIb)ko-`$}&e8O=Qfyag+?%3zh4 zL(BDpBCbKMdx%4>apo@*GUn+)2Ah}y?|X13Yr=!g>J)Bvk(f8kF`)}iHwBrr-mWRk z;q<x=2HW{zlnv&bMB>k{Hj;-e%JNwMbSkTmz&s^<T1ek@#jiO>-B^0g{NOW6R_od` zL~8nn6JP@<DTQ|IxrNP^L=pX^nf0Wpdtqm;c7HeglL6w|lTxPvY4C$5zp1`JZ)gHT zAM-OiQPcd+7GpOTj*9|Ri8=<xUR>j2YVW_;dE8bmQR@K2K!Pqu(uoF^CJ#IkvX7BZ zB^D{&WthVI?7Vm&69zpebHC*A7PpU&H3q&z(ihMhLorkji{ZADXSaYHnj2aWTKmpB zr!M68#afC`H~nv2LK>A-8-IQ{G8eAzc-=~RZA?PwN-kyj>MA@n=I(qfXJsS_Rqv`< zl7SqP`O)3eSwe?HwRFBSE8hw+Q&Fo)hEC7QE3t@O{n-@eTgR6cx07H6MEd}uD4rXh za&RsyK8&I>%b{p`)$@dUgs9D~P%Wg?);;>Tv2FxOv`mYSG*ckV5hE;wq%Xr1t(sqt zrDay0TQdzYje+pgMG8#Uo{UZ*98<7rO=VG3qqxr1MZZUH3zWQ^Id8UxU?b#}PMGuX zF?=PK#D=MDrR|Qjif_T0h}Iy|T73Y%3%JuLZO}vQJ#|Ft_4&m^4IknYPCt2c(f|Z~ zWc3j9X0Qs*jAKgEf^8OclO-(1RW-%95B@7dY@p`E57QB(coSd#BUDOLQf6tzNA^vV zpc(S5r{u{64OK?`S}QwP%{1XTy)dTLew#I5S@5!A8J3lwTdzNH6PsyxUsTNAUGL5B z=@dvaJ!(NO<?5!T=Gx?@&A8Z2rUT;BAa$T+C*#ijFN}l_v%PZj6!|y696aV+pXY|( zX|S%ma1hegNFQl#z0SK1>aLt!gQ3==x(<+g?=hSI7DFFMHu7jDCCjaU6wo$ZB0LwP zuC7^M6F&roSd&_!w$=84);GA#syuE8M47!|BS#G-NEXLyrqin@Z*SAVCj{5&Hiu%V z=AuI6esfNm-Y#gM|6>z9RN6wK@(pMb>D{`Rcm!Q|?KOO_zoSOqx1_X7PDK)2-4-#3 zCR`xW_P%qn#SqY3&X1_`5J0jy1MURH<vbbgY<G6Fd%>8SX*$l#ZZ<s%N~ve%QMSC? zpOs$eomhb`s0;Rh2tEUxiInZlnC_6pzRI%4LM?G)MU^eNkBS{CD>oSZM!s*p_r2@m z)QCOa=C7luP$1?#y7zP_We&(;htl*9KRaXL8TrI~eH?1NQQpjA=#dT`KF=RkdB)uu zgBVpw2S!eeI;f&0TG*q9dotN%C9U3XtkxG1Oj)8m+Fsuw^!M|AtuMVt_7aGwUx%m} zk}d2TL`5b;g@p2m#%Wh}#5|oXXcX(!H@f+g<&`Lj8Yy<o5|0}xQ|-l-kmiYme7wJ~ zmf1sh#Logy*vtyhOiU!&acBEQ4uSTq9hmS_n<Mwgj}-!(Cq1<*3_8D9&nFBm@K)k< zG^ZS1M~=)Tg__AU3=BcM_UkT6Q~J)0%T|lEKsY;w<(m&gLg7@I>gn@`UHVAg7&JV& zbfM$qWgu7BhWh>zd8)Y~`vWZTlPPXfd!ET_&CN}|VWKgJe-PcC*N^`R>Y@3-9Kds# z@_Nz6Oswe)U_*=V9i1WfS0wxtD)BuYzXND$-inDtT6!n8c-K0{m{s@r3BjCtkBgnE zuJav6NRsB_D=Xs?RD;#m-8(S)khoh&xPIM*Z5OD15~CCieq)EZJkr#qT7$`=PD<h; zog(D$^&UT_#*v@LZ&uYc-e~iBt<-V5?jM!&p2Gi5iQ+z8dP9Kpd1go;>VR@bwz<9_ zUGWjrw#EI_)@1nxp4}oPqh5Yib@K+T`)pcT1$93N%AM3D$h(q;|0|<;DzWfbF<YXK z$P9O}h=|(`znaWCc)lx)SS<fnnPqG}Db2Hq%480AdJeHYm)WB$yWFLYa(hpEHH89H zN%ft(SkkIOySoIHJ;GRZwGZ>eu#$yR`@OO%gA~98LnD7m;RfBdTTGIF%ycq3p^2V( zqTQj4Q4g}chL~W#<xBZgvyL7)`$e)@h*BDUZA0BvYwaQ{eQy+Q-E{Ng28-7cbL=4g zv6gHM)Sq4V2jQC;_37L|j2{Mi7&z>QGH%9t@?I~rBdeNY6q<OEVGNPJLN;L=or`rq zSdQ9pfX#`ss=iCumlBt83u;WzP14cZF|PNTH<iZ6*kLNkjt%q<hTg?fQwAx2%Z!(6 zRU&S_#LPt;Z?m2tWe=iqEO7n;kGU43!K|@(6$&nCp?7#J*a*Q!c<{nR*NRjeP`!$m zgSYnULgR_B97U$&^nOHxZxfC#zAm9R@6;tH$8yG`k4C4<l=N;{3?aM_{Zbtl&b{7& zK*U!%H{7bbtq-Bo{g7gb1cfjff?^Pt859Qh6N70sbP1l+1&aMK3GhaIoESTdb%_4( z(Naux7UD)T>TERheky6&awJ11w`&Q<H6!_gvYkhv>y$NT(T}Nen$|`zxqE4W9Q2p4 zua%<J9HK&hsn%Oh4*ZXZs)r{b)XUOWHO-%xQ*|#ZEg#2zyTRG56zf7O%d*~f>tw&o z2akmgg}{rWgpfXoR}IDZN9<FBryF-Q#OoIyZ%hFx-CSt#g1H2%Blsxp0y1!Xinyne z?AE|h<MkMbC%Q%A#wF715a1o5k%+qx1?1zDHiN7dwrmBo_|987a7v?g<SU*N<orRC zJ%>G<;cS5`OQ|UO;6^rhERj-|7`Q`IUap;HF1xHUpanGgE3?qvtvKZ|#NZKA3TO!? zLk9iU|5x*@X#Fov1M;FxWD{0!ikx{B(E1J8V(fOgL1nRjbgVe)f@<e*my~+-IT2^Z z;C1rRWN<lE`yC+7h0*bXJ6oC~0|(s1++SA4kZZE6eW*hfzKSN*T7}JH2I{mj%mLW@ zZG`_Eb!1Vi$rV5DZ|^U%;528jd&l>5*&gj}7~4wSB_#H8vzXBRSRwbpPl?;2S@iAH z=NRVbmIGUcT>&`p`nOvTH^mWY4S=3owfSdM)eKGK<&A)IPjxpi^y;kd7IXQE<g0eE z<{R39GA_s>5B-;2z}J+Z`amj*m-QxTE&Ga%viWxegUFf~cDe8EG}X8n5tQpgXdU|E zCX15K*REM!PEnr!i>|j0i|Xs*zEvbdQUs(G6p-$Qkrru?k{0RiW>mUEx<;gwhM`-! zhwiSSyJO}#_>23#pXYu3gG;Vq_Bm(owb$Nf?X|uiq}SV~HEaHkWxWKj4`%L6sM!JF zzqB(?VNF1`?hBadavjQjpdJAHg=sf;PJ!(0VuJ{xCNW||oo?qr8oozjuhG8fg+0~E zW8ysyTca!m?r8#PB#<?8d5?b3#?DyZXagvqV751O$230LBp<rAUrf^>Oh@mprg9#K zf)z9P75dH(HKpxIiiTBpiKVjliaU>U01;otZBuK1yXe%2cO3@91D#R7E-p9uyyC`0 zCDm;?=W(VeZoQ!R-W03=GF|<c`bK5)Yc3C&y;4p(_8ANnKTiPNaff3?Mj{JHxueAF z>u|UCzcn=bcnj?zIl5oOoIv_ZR;ZgF=|vIY%G49aOBpN$hj@Nu@{#yxx1BVq@vQAs zVCc$>{Q6;L@hqYSeZ7Oc7}`Cn!3PwcMc8NCz%;7g)yv*#>i9*m{kwriy>(1oh8QXL z;1fptq%75w-YEXw+D~j<t#7#x=ov-_E#De$tl9OvqywC$X<D%XYFQ*p=dGJo=ElR= zsW7r#E~ZR--vXP3_lWQ+`%L20vJ0EpsmrlDhxvHVTEE4I%C9{ccgY}Uy#DdE3jfPO z?^E8d2CrIf$ZBL>d*OP}_9?1CE)MP`i*naL{9^Y@*Rp!^3mI~ELyDJh@Eh!V{(?mO zK;X&ogE)p&mcAtOK@Zs_#`n#ubW!o@EBQ-kU}2G365q0^w_MDJ$1tK-8AsD^Fy*DO zmfoiYt*BqLS_@#e!xPQDPh4kcdYTRex03SVlgvtngvug6ZpZ*C?Py2&!hK~h!E#kD zDRnKD$&R{^N)2imJ)r&i^cIO{1(!+{&3%SzL%ynmFl7XU&=UQO*||)qX_1C<dHrlY zYV1kK&uHaGZdprCA|usuTE^?!4~)LY^@Y7zT3v9%jmWP7qlXA19euE>dN592u+WAK zc$`2+cC{XjH1_-a$X;A_WKF#}UOwDzda!<gX61uVxe?Y9QB<m*hS}n_5L$D{h&7{j zWp04E-b&-v!A_>S!4if*F&mTZs#Vf8Z8i(zTsChgUb+|?9IFlhUJ1zP`^WIFOoui( z23i9mm!`|m;p^SCZz>OA@Wm1RAzSswt%tCR=X9<goh-J`6%YY2>th_Hfcr{KXZ>*> zcj*)EbKvcRt{lmlsyd#Tv;ou@bX7soJL63B(G2oZ15hr>t|n#^T0!~&+Z|#zi-9vB z4e86>XX<g_%oi-d$3x6{B*%v@%^3d@oNW1v&IZIwiRl0ZgL<jK;x`hP5KiObgs%#* zV4kXw=YavZ5hz%_pzXIi-)RF?rG6a3Ox8pnmA1bA=EZjm(tiLeL7g_`AkR5f+gQAT zjp4CZqgGj2+vjUa<eGIwLJFg%>sDfsTDvEPe30;JI$b|OCsikjWF$WXC(U~881dVo zn!;us@`bbUz1T|U(mekS(;!2ZJDXp}*Je-0P|E2w90%|Bm;t7YqdK-5;|X|_<LzDe z-i!{fo3Jw7ShL1emGBmpOhYjfUs@V=#2eL9Rs<$2gb7tek`(>I=!4^6r~vtyHGBnb zGDhQLenFF=otVGq?eYhZv)FU_5>s4!$d9EB;K8hqFZZc#)MclSHoBSd_CZs(j`%^v zuMgOATUmhV3>Hh0Ri5eH=uj>?StRm5y!}eYE|C5!4)FJ=r`PCB?Nc5((bL(~5%$m} z2spwOVaiRkrn65q`#GZqYven<0{xJGVdtAWHrhifKtw}BM6Sv50K+8G`|@EfjOI$$ zr+sl_uLBj%30Bj75PzyRSs6Upj^@b|(31Fa<>20-S~=24NZdS9S91!42sFF7w(mI? z_azo1RN%^Ez}&5TsOtK4ey&^UizOR4U1G;x<N_&DEm6O91Y<RvpI<zETFizSJ49!G z-z(UJn(5HdES-811n)#$wYfMrtc~_R>|L|bF$F5h8|w_)d(y)=>ey`6gjd))JIHX` zLzWLmEE5A0j40QA5aGGsy-YI#b630$L%$AeUciSAjtNc|?)fVlvidCp>z3fsiGFyf zsn!ZZ;Xtw1q{Y(?rx=8w=<YVdZ8%!H|CtBo)V4A`@`kHOIV2}>e%~<r$77BM)*T9C z>%_}kT8e*p!kzyTp1#{%KDdVOEEMy0YSRj~RRH~)KqFrO9uS&LyoF90H3|Ed<PBOG znm`^lzUD~fP`)zNbuZDz$(1WxI)Ryr&pNl?Zgw8LA5U`t(r$yVN7{q-Jc+9E<xefM zLY_a)kBg;=K-8oT=-zNH{~~G$jOD-tB%vSEoY~^-<uv)yIK0f<c(e<BT**dEkF(9e z(89LE5yc#8Sk6+?Br_O!4_R=sE=ED5NdicU2wXYnN_np#7p{1a0$v`^YKQB=tf;+* z4?4EdB^q4HJ15V-I(Xe*mK?&UXb3iRz*~gC{Ln2!m3SpN`9fHqm&GoX-yB~aG^8!% zG=4VXCp^Bi;On-14pwOAGV{Ac68eS38NC2<JN-&L@NYSZUR1oss7m>~s0XD4R2<r; zxE==_v(|wJA_XiBeh`IDfvQB2u3wF>o=STpYg|4_e8vdS%9!rbhv8lVmWS#WXV-@I zYIo_wrp8Uz%k2FV7#;;*(!o!zKZHjJXu$)O{h9fJGb~e49v^INZH!2Uy$(Emla~bw zV~URBq6m$S*tg=HHlj%0<I5azd>t&vZ>^jdoH>gGPv;?J+hzLXH^2Iu$M~={tj1ui zi_1PO(u8)Xl)m{>B6oTX_NiYc4G2lSgKvYi6;oe_9#AB;lzfF5jPI6Q!<Rc!6#I*_ zgU%WXhxi#-!`C3lP+jezyx$0|!Ot)3T6&dI^4#eq*64uUBC&_hPd!I=(t3IQOw86F z;9#8c^eKR%+<=SzQ_fuM#*tV^B=G@3<8&vp>;N3R_hs{z<4Q?u*^=EBS9${ilc39o z(`anvm*<t>_^^bX>aS=97|QGFeC08^OC3g82)Mw&6)ECsTvzJ67=EW%54Njg=VTpR z@rl%Pe3kA|Fw*pHYjFqhur3pPC&T~N<u36eup80rMZ6RhcYiX23%$$dVzO_R^jesw z^dwJEKJdc|TP+~Osdm2;o-VI)acNpHzhpG$;@#A`<cao#to!F2;lQINxk|(ozK69< zoXw0fk8uP+DxwC}rZj&MVTm0-V+Yk4WdxFS_xh#9>VFnqEp@m&E@+pV%;HLHH4Lb5 zfiIM7mD(g}lj&<9pJu$1wWH(fO7E$_aO$Utf+2_YhdG=}1(5+2ti41LzS1hjdx2M) zIH*@8w+cG;C^jKT%L#7&z#bcWih7&;67lc(qQqb{)vMUsnSLXKc+xr^pcY1QNOr}p z30zS+wy9Zz?LCH8xP_j3_!zAL=LdT3kA$<u-fJR%gAU5kmD5DV;<u`kDUxPqc1#5L zfkGX<^k^6GfuEm5TrzNOlux>aHZc6xAh0jjd067v>o;kMMa&0;h_QoJ#l=VMPKm1% zY}E2j!axxX>a9y=k$aIc49!zG2h4JB&Q-X46$W4zn}OgGabtU*sy(sCuWV(hOSrm+ zzDDzJk;oVZd}*Vfl|z#^K7C)>`P}>6PC1=#d)XFTmS>f(%hE3%UYknNn00irWm2}G zL@Yf!Ik!jMz|tZG#8_7s-ioK#a$7Aa0n%iN=CBQ3ewQx|1rKkl@gi-<m&y)47r|+b z_IaDd_t?%(pMJb1&Rht|XwKZIl{%A(ms%^{emat{e04^X?o=OyQvP9H7T%_$`Xj?9 zV{78s;rf}WHSrd|%eMh^2W%Y2hUo1~^fJty&LXv>?L!#uPP+WAWh}xhW(Z5t^487r z)igf|ybDKe6JM&7`r`EP#{g|wfTb<#TV3N6^pE4hevx~kNpSnud$t#?R<}?Ci~fmA z8QMin$~TV}oG;<$cE(C`g6P;}rl~dZLkROkzgxDixMEc->?~oA4q>}&de(M)kY%|; zxwdFPQXhv>L0&5GXFUn7few-37LeJSznrD_8H6&vSQekdSg+9Zxs3m;V!W|9m;I6% zse^jjcb?bjQIvagEbEb+y_7II^X&1qjtDMl<>Yw<o~j37Uf!DX(?0>S&v%(n(4%gV zPZlPxa=g1bG)%?obKU_I?HfI~>7~qs_RZ|qQBL{tk)EslE>&9T8$dvra^Zmp1>p`v zIDvnP@EC6nIJV7ap5YMLr|OFtMsQbSyYrz$uihmE2dR*m)N8yo#+~;|SqObD5K!Cr zwh`U6j4aG-jG>xU@7}F(+*DDf93k(;#0aP)Oa)!HU50h{#T@k5qu4{l@22KM0?9H% z2@XeAKt50R>4mA}U2;eG(4!nQF||4LMrk?~o9*dUv7b#OQg5MeVs){vothZ0Y6V_4 zWA=sQ0sQ69J+>pLXkwHsr5Zo0so88D`T1bkwSA0sI5vhXK~e9mT{>r7KF3ZPf|chu z-&Pn(O5lD@BQqBoGV`-*JjGMh#d|u3H@#&(nW2bx{7Y`yy+n#3!s8x8(-`7Yo2d9j zzO$64dJAT<V*!-{FXv75tMw(?#L0JwH%2<#8WO3;4_98rc{g<2qF_)%!$=DNIlk#1 zYRC2=zrX_{bVoK_9fwkOWj`WeH9*39w%R%cfP2&@e9i`ec9s)&Q10_|=rR+WD0u!h z3vXG$1$nqvz-d+utCbTrHyMC4o!L|)!omCzJQhnrPpYrm)Vk{o#oxBw`#O>_ZW~aA zU4Gr(#y#Nne!RX*<90RJ3V%Q6i<W8ywl=f%>j!_<^g!2WK}NEtpQMGLS$$SfEg#Me zb8c_M2(is5l?sa-#S63ZeowrnvAN{);F{tw>+}M>I$px9%vsIh!v~RSu}21}HiF>~ z^6eRtV0^Wf!juOT@eXciweNAy9Wc(wbT1*uVHvT}#`!l!3S}B<7)=)@&2*s1R{d~y zW0EeL3v7;o^c#tqH9EFr;X%Uup{#EQ$C;C!m=@_@9W%Z(9GWifr2D_%q~dV-{mV6> zwAjT%Ny`1y_XuWb?~t~s_MIrgID3ehDB=5d$4t|r5}svxTR~9-#=(d^hW6l>ltZU= zwA94VutLm5Irs4(YnN}hitZ-UbT=k9zXr({rhwvFtDWuFsZOwr`zFG3?0OL%1+vC; zfMOQ3`N}EamP3Ugv$BPrO}E&d_z&5oR2)dRBc}x_CoA*3PJZoT`xebzHsshfHRS0W z!|0!W(ZcR&T2iT)Z(o<FWCg{gc_&%ja$>;4qYN9lIl8;=5^VJuNT<?6->vt2h=Ktb zknbmkvBrz)=NVA_x0~}djguE?M~BsyMpv|QUe`;LOt8oLE?91yqP1?EjVU$#7?7`- z?MD`vVFaI7FX8&We)wfY#EzSYdq+xE88e`!vcXf0a&t?QydnCl?&!#+Oo3?Cdu>!< zJ>zy6Enz*vdQyEnMfR;N4s2yd{Nfn(l)1WtRKL@(PtdR8s@Rnrl*FRnNPi3ro5|om z&G#k9;Fstme@W<$!|<9gc}O=hrKQ#+U-*>WzfX@j@|Ur?3f6H6zChOVtE><W*SI(A z`2;<eeV4Uo91%RkZ3RCgeVH?n=BF6~#(AXONxtW5FpL$Zz@){R;ygfPw4^MLeGmII z>8DHH)~_d%FrQuXPpKt)9N~5<iH>ro7R+IF?zg|p{m2te1!}gog~}NsYV*8%UIQ7x z%G&tF9tGL)(cT}}F}`d&HXPx{IiE(pgAHSN|D?}QB-!55z+@?pm}rN_Qhx0zip0$H zLYZseE?vmG_+3Cpb*4EdLR3-yu|gpvN9qgOq^@CR498?%9(dU3w;N$6R#nadzaBzs z4ZLR@<|)6Tkv_H_Qk$@q>5k22TA(@x6}}wou3*D79wNh5`cChoKKH|-Xi4Br{$Yh~ ztL}6~ag2x3Y{G*f#3jE_4PSfyn-}D=-o?53d)~iR^70}XQLPzsz9F-go8Z4eO##Bm z+GB0>vCi^7-#GX_Ikxb2SiKIQs5#G0R)&qa!8{5Oufw^=O0r0SD)DHs+V%Gnjii}J zpDl6j6w(#kHXx4kAiBR9UqFr2OU`UOFgJlYLEcr6eay&DatdL*%?8ZU2=Dq)@)!J~ zq7vOAemdwAk}=qbwyfv`FajmH+<N&#909#dK9dLLg8+#1iEXA;WvGKbjuDurk@84j z81oOtFE#4rEC_e#<X#5V6Bfu_-mJ|ABodclnQUW%Mk2ga^HCPH7-D#_!sZ0&!vDfv z6jgSjlYpLZx|XM&w<>)xl@C$FGpv&u-aMxo{cepUtM_O8ZhW*V$)h(4ywu@p0r~K# znxH><XnrqW01UKsnQyetyVKk!3xIxkBqhbwl**tm7XZ)u_BUAV^5Xk*Y6#=<<LgT( ztAYb2<ANl1(C^Q-2?S3BC8L=<;uLh6?#UQDbA~X}MF9E_<n2@&v+Xlc+kAY7lB1)N zyp3j`KFkNNlFfO?y#DJM@2xh1_l7d1CyI1OhKGq*bcP$fuV07<0M%$7CmVyLvJ%>u z0-3?UO++sOi;mtOf?rImSO$nV+UmxpK2fpZ%?Kxj0Q>7m;)B!H{I`VthYSq^Z(Y(7 z%);vBT$g1@2o411938Fn*YG^S!e`m>Gf@FQO(J%q@1FeSX16!8VAkQohw1hH6mbxj z_4Ipw_#imW5y$%zn%D@a^X<Pn?m)!q?kj##Z@cA@vzgM7XWuO+imuN9VP3m~MbS8a zniH57)Z|wdc?Q*csg3e-F2>jBw~nL#ALP1Nz<)86)JTRB^@vdkxv>E~o(%E1`USL? z0dd`%CAoU>{>|Dl#x33lk}Lj`g;~Y6XfsoC#btioJx%%)^$w_*SOnGo!17*A+(1K2 z)jevwug{<+{g}7BCouoV2|tC%-ihYhZ79hQ;!rSr|Cqr!olJaloHYl^$wgLssx;>k zHMUdJC~&UfXjRGZX!X_(VroSDOWn7yutl>HCMTU~)kc3=`{L!t|NCl=p+wB%1zH4G z`--4ju1{T2Ir1qvxw(wQ!sf$SgRl%_o)Y}-22#lw-h2QGCw1#6VRw|m6RY;J2Duw@ zC!w6~_u@>~&(?o2>Y~<@S7^<Q(to(4QRWIJfN)GT5V%uYmxuRF)dH(bRGX_lB@Tk9 zn*IZ(_?vl3DePf2U(bIcK9VC(%%bx{r@RM>f5rcvwp`={HYjawZvIX>zl|c}v=fjz z{s>4Nqw-x}nI5B1JodJ;4y%i7Wzwo<5hpHAwdidswaZWzV_frho#fG~QkvDw5qNLd z2Ivrlt^IVpYz1FzEu%;`<O>)uN+9KcdGVJy+}T7lfLPQrc2kg*Rh{DTx!TMHESiy+ z;;P1cB&UaSf3}A6#2n}@u{ApR<fja?Pk&mABZWn7p`uaXh{6((ec~%dXEvxl!c<mC zu<8iY0jE&E>dBPQ&4VlyCBzibfmbuA#XbKfnngO&<B^5eYI*;`7$ss#+C~~!ov-0- z#Zoca|JyTr7p8>6v*qR^+?M0z=zx)`lJJOS<>uxOnw_ry9)yVpU@3q7u=X{b%RJ`E z5Zw>3Liz>V-xbJ2QXDH-P9>fug!bT5d@vs)A)!QQt^SMztK$!#zrP=7p^lhhWtCPZ zJb_67>+?U8;*R<VyxJX^##xBJ8lSAWLzV(Vo+m+`!fUH;`|>^JbWc-8meU5DpdXZ9 zPQktnFi{g}uhx9G$K5aCg7v;haTYEQB~8st8DppEM5Xa;0A7@pTh3>Zys^?JL(;g_ zBG`Qt;mj+$5aR)#EBFck?fY{g@%NPEzMGP`r_;Xy`wyoS7C34B?TaoB(jMRk@DAT- z0pu)Fr`k@&OnI7L;<4R>OMs#azql~%RvDyx&7I@XWIfo*mKoE>T`Oj4{o8FFe5TOu z)oeGQ$1h-|=70OOB{2qM`UdGW3s6`8`<YiDal-1hPq1#!7k~Q#Z(JL2;QGJffbLD= zG9M<z`;ZB!V%*!rqXPodeHyqO;v!YyDPXkmd=zVSek-Kas|6)Dlkfqw{c~K8b~^2D z-lx*u^`)m@Tby8aW>=;k|ESOZZD>Fj6Cr0SEGLMVKVXq?NEkcM*Er^SzzjBM;=IIV z)&Zk~C3DN(sv3X6$*2?-U52d0p7MvfDJ1-2<n$`*IZIs&ZyjhV9oCa0JdmT`4HZOo zD8ufV#LZ6~48N1UHklbLraAGcF|0qfC7%~~9>E=>^B>9$;4D=fIzfR%gdMYg`Dps% zf--^plDj9ip0A&JhiyGH`g~&5@xiU*?3&|D>H%z-qua0nY-eGzQ|@VR^~?``jXt-T z*3g;-^<MfO;UcoA37C-IzaSmp5)J@ir3$@=AwSAw`}FG;;EIJS93RWi1GvN9ORFca z&5xI+aRNqprSoYrtuL|*XDRkxeXYXtxH4@@c;dklQH3X<M7Ev<rtJh6)&D&~QxIC& zpVjlU`~~ta;CQ;+Tc&aD;!~T0>LkBmFOI6g10>hv=tv=M#!-F%1x8@AF=--g17|8N z;IYr0KIo>{4b26MY~l5y*Q;88LX)KGXIQZtN<!^>X8!+<5;@Xp%}d>WU>wH4T3*q? zP_PUU2bq=wN2suOOxFgNCQT|+4Fzo4AJb_>+&RgI1}K;Mi{8T?H!wjt#?q<W@f1E{ zcc!4rM|{}i_R?e8@T&R_F5SpF`CJIpmwVk`vd8$Bp#(%;vH)VsfTl#OT4hU$+5z-k zwc(X1;p@V2(@*nJI&lCUl(L|_&R9`5^-|=wJf$sRUsRun=s+|8p_u{As2wPS`FGqN zFAZ76aolp2{s*yk$8y#=g=yBh>{@IZze+7!G$q`!dTn;Ppu+>>UxX0I3FU^yA(NsA zaQ}BE0t>2x<xeXZ14a4ik!W0KYYeOga&`yrUj7gJ>Cb&P0{8tnrjLk$WxD4wb*fRK z>keBQMD{=J$%KJ<h+d^KKZ&#R1=;|n+CTiLyEcF=5*<9|Zf*RV27CdxSj+nQRxLVK zqAK9edVTj})$Q}&_;3=$<*WmT=Bf?7*}v`sFNWfdqKa?VDK=Hkkxm#B#77;&Qbs$} z&!^md0PFARR*J5nHVuw_=j8kE<QI#fyn+KXz;7<d#B{{Up3Hp+DY*_=pl*kG&g_eA zo^D!8E#ePL3}u7#Z{*WBvs%TzNkk<fFFB&ksc$7o>1sv)W1cd&w~j>@@CtPK!kraJ z+8O^(tA}ky$#UFnWs!#IwZm%7PNO*96rq{(9-6}=4GAcDZD0Dpl=Bud2hGX_Nb$<) z(3*tIjF8G6DiO$sUaG)MfzOE-Jg>#SPkdKvqN^o|j){0>#c}Is)CD(>dGX`XKe!*U zw`_l^j@o{D?b2UjMHf7U7K261e4>738W9cJC%$|<VZ5;%r)qu4OT@zU&P=r70B44F zyMQAdG1Vwj?Y9r1@VPMapge%Z#J(7$iv_dzuaY^wqQRFYYz&I}xBFj4{l(|xY(xMM zU}C(9?nQ{kmVrsr4J`h<i%o?L$HZ%-6>Pdxh0*NVWeQ+sM_v1CB35w4xwi`=C@Tuf z`7E|9kpd%;QlrD<)GRLsJ+ULbB~m7x-tX1aIZ?IV)E)jZQdV=%GgpJ_8HH>0&8|f6 zU{;f*GE3{o3)3D|b?H+_Xq{4Gf?1E!x_Dy*a1s0x&e1Z|Mq(3+(J|4ypZ~qr)wUOZ z66+_!ib41n@UHjH_kezQ$I4pYIsqy^8SY}Bkv4IICV+{k?9;FT6{yxg>(_iZ$Y{ez z+*MR0(;>!}%A4bTz2V6gRaR5&=S0Yzs8%2es<PAb6$c>AlOct$I)^cqgIOLO3rVfs zul_GP{QGphR6rk87T06)V}q|6j<w7#>vR_8yj_0-jnq~zrs;F)6*1-@aFvL~5RgN9 z-Fw8v5xNA=L_Z1xM+iUkC^pnD^Z<mkf@Gbj4j=L3bT#2egIz9G7l4FS<>tATAPj)$ zD!WR20e3w~4i5k%S=YlesE?yUGvAkEKmXSzyO00M=EB|ImXtv7xBadt-RD#wXn(sX zG<G=jeqsh~jOcOr(?K7ER$*id=$aNxv<p$|<FtZKuYO)7K{BxizS+kvFCJ$hpLYv~ z`K)X}ZnJ7lzdSouKtE}AJ%H^`jb|%NAhhh0y1uy)8?O93)BBKB^mat4p=0<dW3Pl} z&cLBoj*LN)3Y}h3S*K%C%uu|!i&y+FI+X}xiFZMxA__gRRSD)^V)3timg9cmY0{ov zFsXuCIND>1<(MHHgpn|gOKPSO`VuU_++#HU!k@ZqZ_7WF;Vuu3&=T!*to#{ET1ou) zozM-`)BE1iHM}nshR*TL_HFtRj6LAZe*b_$%KhPp_FYdv`wB&_%=8P8s3^S%NthYW zp0_=RWoU=_P>($Sk-7LJI#+U@aLR}&1I+Sd(}MLlqM^_8jDxsSJtu`_WGc7sW3+5I z$Kw^{oNpRQX@&`#Hmt`k21%h_JxuI905Q2ax6jxxwnnI=@A`~`qLl^On%_ql9lN=x zYVxb0&kMq#vBg2`7I*o4heLSBcpj5!L?nQtSE7icr?0n2u5PmDWYl>2N1uylk}mxS zBc*XVdr$cx>&Of}CoiS(2hX@mJmag$UaQbbIep!Apg9<+@c=;*fq0S+ARRE%TaH=R zm!fBUWvXFPqr5(Q(9?JJn)6Kpe`kK5v|&Qcw4RBjK@!x69xAp<n%P&d)04WUwr=E^ z#Ch9`Rh}@ltY)Gl)FWgX%P$VptR-2l=;plYv8qg%^5yV#P9kEzE4$HsX{<n;w4_g~ z?_wMvp|Z{uy@@bBA~WW3kE;=><A9MFCx;5Hsjj0%Kd9~dHWkOuT_PuX=ctZ2{_#=X z!OOS40IS?>ApV~%O<XyD{0*6MC&&~6Mgf@wt%3d?z9-rkT({7NSMY^J$Zl57^sVFT z*}wrw>IjCnJ^1)^D~)aiZ<9-BgX41jl-J+uuD^tE_&VhDakIyo+c+ER^oErtkPy2k znIMc6LZy=|X;>XA6q81rlX7bGOv)Sjbk8{CZ+gpvT$4IPjM2o~+Zy^lKkG@&=;aEr zOcLBN?&z%OORAM?eb%FsfMQJA-02a|&uDKfHPt&C&SAREaq8IE$6qTa4B-%`W*uRr zG~T*O;O9N!sG8}O3$jd7ua!#!z6u;qUtPuWD<=F(+cvg=Cdh~<9Xls|s8OMXu#5m> zgS`}IUf4StRwL)5n^UEj#8WF5&en71%iQDsb-4frdF2>5!yh18gGe^m4Mue<H-QI< zXeej_5(L&#stwX~{t#B`_a<-?(t0vud6Wvqp#%IQceIS1>+Yeh^M4k~<-ZQm6a8%O z4Yh&jvcY=Q1GK4e76TzcXgsfXS0HM_k7>FZ@iV|KZY%X`kXHeC8&;=B$!t#~1Tg_A zYp|jRvfu~=HqlNHfB}kvEkcp_?r*X@%KQJz^R)iudA=QBKOY1Y&si5~NE%JRtc}vC zRiX9v!0|-y>aQgC4CZeIZ4T-NP)~ww{{Z|~3sG-xp)23&*C9>V+W3MPboG}(kr}76 z40E7oGl$V}ois~`slwmPF26y@u$$J9@R-_`HHd1IyAeG{S-Stk)}MgHU(3L^fBFvR zB;}zndzqkTT<DZYXD7(^NE6tujpsjt5-HA*E78gUSlPr^*?_<%y4N=U);yogEwuT& z580)<Va~*X?ET$!SB)eZ1l21U1h#Am6~U$UDl5L@=O%wJPTVEs(%=FhCE0H5mLdnv zDth&=?|ni0m%(p&S^I56oZB49=N!=vljs<C=O;Oh0^Y6HcXQ@V^@0SkTmaPEOfbts zft!<o1(Wk5(a;6&8)!AahCniX5Cu}+@b;%}p}>jP5B7O#E^O-Lf0sGG#DDyI3R9b7 zrRF6>Mg?CNgDW^{^gR_)=iRCtu;pouilBKlp)K|ArYENS&$s^GaJ9Z2AaEu!d-A9e zuokuGI!QDdRO#qhYoh;bFP=bmMw}{M>Ri%}{j*DZTZCuAf&BzU6gbwxtbMTRi1^=c z+(mumFdhXy|F1VKvHI`e9N?hQ59NP$fB#kN{f~{lRM`MxWiogK=Q19(Sx6=TKolN$ z026;?Ln!m`|9&N?xw#1EHu2uo%Y)tIU7fJz37@);(Sh=>+Hwi$njj8qt3M|CicY%r zLR4MUQg1|SJS*1;??9h_Roli||E@qE;pD64S=a4wtSy**c^8^#S*05RSuPda9K)`k zOw-0Z<G67=b{Kwn^6hVod~}EiM4k9`M!qcm>sKn$R)jnR<}X#Iwljmy#@+)<AW1`U z2)%ymq-RhI^{FHSi6y2%)7VgeiIiua#F3t)t7r0e_H6sE5KP1JDJYmU^S9)odEw4g zE=~k{syCr1l#B#*%TPYVUWd?$DxOQ7NUXc3NP(Vl7*7^;LVE9vO9DbXEUrXpZRyv_ z^*ZRw&m{}Zd#FRx(|V2t3|p|sIrp>3mA8b(H<7)%kpe|6db{RURKJwai8#0H3+@PW zOM#Jf!r^vG0IQ|uEZaq6Vlu&$1bxlxs)TmEM9un<+;j)RNc3-;agPNAPq|IJ;waHv zZ3NyUe!D()scY(+bS9+qX=)J{6h{gT02(*)11~+1R&k1GNUy+xnU^UAuUwGz_)@&W zCtyK>HTX$iWEl~K8@bZ3wJ&bXcBwSe{`C}4Khi{Iox(^#5ejxG?^lj1G%PYYH>=b@ zenK-3oJyL?un=4&FC>3)w%0GiadUj+P^SAS5*P$C+LLJ|h$7Wfenkxp$yKpv)Q|ag z30-K>GYujROt!&&0UsNFZ;zZy0Mz=i>)QKk;-0qF<cel9#1a8ymhVEGp4L!VPx^a^ zJarddA&q)5LM|{G`9e=#muZ+JUEV%TBgOT{WOl8bar9$}^<XQ`9xK8ct<_KOx%&~( zp1B#;WI;OH(BfCrbEiOTd5SFTLGO@x&H>igab?%1=*o_sEqeF-e1f8<?x?-bC!|qy z!?hwsihUJjLv_MSJ+TALRTMszcL74vYPw?{Dvt`&jQ4-ek!Wz&5Fns@F7Q2wt7J}4 zxvQF6l1S0E4i&bY+EHE?%E2)aAv=mVyembj6p%t%uayH&BoC_ZvS~;Mx{ikU6rI%v z%;($2Ziccq^iL+dDGa;<7v%SuBd)hrI6EoZ9~rBW37kX9sIGw`*C3$iGv;;*@9&Ae z%Iq)(f?WxaBX7=2PZ0Syv31wsH))*-wMN#L==03Ho4YGhAjTxD&9DRb&JC0y_9a5A z7yc^)lH1V<(smjB#U*?T?R{^G_7Xi=4Hs#}O7I0Nm0uRN(XnA%03jME=!YMilc29p z?1V4v1|j%)fZ;rFAmQM_?mecyE)^=C2n#r6pyLo-HI4390-JZ_CbR}I2!sgX<nwgW zbK)cG(Y{1$$c{IvZ+SNuENHl62<P|ZvcY5xh|z;n^Uk^TR$YTSm6Z}0JSy48XLEZ~ zAFkBC{p8=J6D{-em{N25ca&{=>voPkbyJYl7fKCm?T5DYPXmkj^uZ^oHpeP+>+3;J z3z>$=1O!F{d!3e~CDPwiarx%%8lS)%Yr*Oyw~pKocicVtF&m1F&9bI741b=cNRAsM z`Qjvf@fgpLGn!jh@<$S0YJS4HQu1e<ko3nT3DkeKRF*O4{rZTte2Sp}1N(RJ23|$+ z=0Uk_s7|CeAt67y1;8>5S`%V4YGDc-w(@Po4IC#)*bNJ2hb0=F8-CEEQ^CfrlV9b1 zJ5(c;RI0QgAC`x?1aaM7NzUV~dKS!IiGBKW<pXY{@KZ9PX3Y~k_Ya@GbwNF(RVC8> zzEyp?#)zib7<N2KRzi32&GTle&s3lNdZ@BnL%genPA7y#Q-l$I9Z8KFnrdmKiJEy_ zt-MYbYrfW0yfiuC;t3o*9`cMB542AT2g2W}CwUsK1lB%i|NG_hrEN42<Zoj|Uf1n@ zZFps?omRY(7*kcu;)&Gmgo1f6T0!~L=o1W<X?94fCv-?JdR-rphZ9?a83e-Wln#8F z%;xeG9$kb>UR{R9r|Q>UC;8C&e6`YR)80pds}^PrdCVisR7aC-(<ux_l<hBAzfn;c z)elL3G_|bvjxiFX!c1(xp%Si^X8xJ}mdzMZYIJlSsYR<k-fP>`&8k1y13K2*3L&h# zfq6SKndxh+5s2;j>02x<d|nD-PY-N12vrI4Qg9~R%RC>0HMPu_<Zw!`xOj8vttNH> z+4En%e~cq&K7w6FeHLp!r~FK{o#m+dRH}46x(yWR3&B$J4A2{S)N?L)!7IHNlun&L zv@RPK*N$HyNbFrb8>CVc7SDAaf@pYm4ts+PIBjk;32|aqkN-_;DbXl4dD(537mgQo zgL(zcW#RvDzJ&R6kwbIy43^C<1(lp9zT_3C&y3y>UxYLT&Vyw4EknA%2DHqeg~!X@ zj9E737?+Otvh`?19A0RmGb~&`dQjb8PLsiCZ3r&!$3ZAG)nw#aw3MomVstt|(#%9O z$}r!9j@NuefhFtiKX-n(ZLp!t6t!v6Gi<RJ7EOc&LBI&*y0xb-QQYrwgCeJX1Z9E| zk4g{k8^0GiqmE__i}Pn6L!r+9XXq89Qh}j&l}5TAeWQ9xRz|NM$o{$^C!HR_&j@m& zJcThdJ1<D!#%*mv;wH;OF0=Jr%q*%DT}D@G+;OBXOz4_{v`t2lDf{|81=ZUmP2>)~ z_1@*D7jKyEwy+rZxCGKEoHxe{4nW9=&mIWP8@Qy*Pu?CQ2eS&<Jh@AUkAP}35W^An z5sD5LT<e~3Y%&Xx48pVu%!18IoXp8e-S3~oJO%JyrF1qd=%>cd!Uo$*s-aZUyO4ZQ zm`!Knhad2<7ggecJCbe1AIrNSB^$Oa&nDX6Re_5hRtaGXA3TYdb~5zegp4)Xh?O5( zVoa)YNikj7ly5yT(~C1+<7p)e^vwki;3ir1m$CuSC32tuD4Cnu692(mGrhr;sk4sw z(gE*xk~OwR8ip7G&q0+xzFW#kuYLy9{bYO^Y+weuv`auvbqDoxDAzx3_)*L_C~)!? z+%)R8u`A{c=`+4e<wIh@Q-7r%{{#=P{fzoXnM9-mAlJtNN;?#v3Wnv^B?j*CbeSVl ztv@`{H?o3>?22H*uvb#pX{vd~ULFsQl0xejmK2?^rR}8s^%Z$0J;#<s81D&a+&H>E z?6d*0d(o&>B?uuJz3l)lz_)pQY;wi;peP<t_3D}#tkkDDs!T?*wEW(Mpmun&KY1=E z<zw|&5vfDQ$SZ!F?2i&O4VsX8Fwbn}f^Fn2zR?4Vt`dDU_zYX427{u4qC(B}5+3vH zFdG9Rg8Pdyo_fwNse1|^Is0(nj1dFoA|;$_^s)ZS+m*V(umq*=a&8nqHnPYLuy77O ztnS&Z_G5H{5+s6-sJZG0+m4>NxpCS}oWQoKX+KKIi+6bw`jy#AqQwP#v8FTxM5agh z1;lodO_R$IG9x9#mouk9V}KClI*3wBjw0|Zv%8$^uN`_6fiJM98Ef@Ke(w%|f$2ep zs=s?F`S5QX1MCN`=oPO_ITQRNjGaxp*%Ayy)7qu94FeSi`pOp}w|u#`jwQD^EOuRH zHGdTic`L~|Og;nz<*9L^>xTI4_TU&kek+hn5j^R~zEVPzK#h=HfX0g?DF!DU>$-DG zw8-;-F4G{WF0SbeVNqFqehXmN_vuHvG47`YU}43Bi~J;dY+neMVHPt7O=ORag%=x3 zNSFfA>!N_cDUIiZ{lv}gS8z0Hs^;x^W7n4Z61$M?7a46HLFbqqS6f}ArMT1esPovo zA66mHFtS5)X-WfHK@*Z+5}t$9Y{I3Z*e<E*b=v9M&IdZ&(!TH?U~xcBN>adpN`o3+ zmOjnC>qRj|x!FV5CByn;E=H-(z0$#4QglzU*-f4D+2nj@{AMd<^jj!tG3xsoZc3?q z7M=*pEM>*V53N|m;U{9I<Dbis_ek3N&Fpw-BoI&d!xYq6H?N;YUp7haK_USN^ybt9 zMS^(h*Y9kNRN99?RPD!UK4&6aO<jZc+~@Q=mUg6{or$|WaUzZRCjj|2otF33v0_sn zNOKkMbGtSO9%6-iBU6`B<Y!WeZ=t~H$r4uVX?M}$(@_Ls>PbfWJ{8trZ}%R=c}8df zv@y>B9Il?%J#QH1pu)6$UWWY?7n*Lx?m3(}v$6z1`h7*H2$t`5rCCZH6Mb>D@Y@*N z##_B4cRKNiMigNhox`pr2mDmMDS3_}-XL{w_zB{-I$&%ZVy3c`XE1cUF|Q;a>t$UQ zq!;B^A5#PEINy(a0td=8mF}@;`TEP&0sCUc`at4B#y;x7vyT`i19~T>l90)Zdm)S8 zNk8uU4i2ng1nSwYey{Fd^K^YaI^}h_SaVhFv9&@Ppe`JMP7)F=CA?K_LS58|mP`>1 zMv%ChUs)u~5WRjU5;_a2n{h-HI|TBz?N4A}nu58VR%5r^TuDPLGjYG~`o6i(U>}+E z!r5|p|MoKEfdHAQ=xP-~f8!Vw<7(Zt4df1(P(4`CNMt@tVPe0Ai*M>}ax*D!4)?}O z_jCE-cYv;Il=cH&LBW+koF+fkkr^p<fzZ-XpH&4yA&}MrI`X~_(^W7c_fSg+cx~!> z&Mphbdxq`2gJVVX(#z(aINwvlQvK&|$D)I1faKR-U9at$P@-KuNc5`CaXk^?tcNN! z!)_=Bj9Hd$58QF}0^Cll>Qmg-7Th{t<)d_^-H_?Okap4)dhUjs#4cr!4e%}frso3o z<Xg+ok~AydAQ_~BZ!lXgnW!O6Z$9kkiHMeHd~ew;`Ch8@B&Pw}@65^V^p^mBr!{rc zi=+-6qavI(tnzBCem4Sabz}7xglFnP0?J{d?ws)}-R<y=T@it~Dxk`PrO#!gIVU1W z9|1>hoiY7BPT=NK>t6{07Dv_q^YlFkJKN1z17<?=QvoW}oM5l7S=(}Lf4?|&kF4f_ zeU?WyZXAOJ^|Qed$rtkR&u*c}>m81<oLs##Osfcbq+?DI*84&JUC6Co$_722G6Mej z)6<$A2n~00{F}3`RdN~s`==5TX1QCpzF>;ce1}&^$43t-6WD|tDIQAspjyt2rr&!3 zB;S1h3jZCn_w=$If%pxJHdx|XvGxs@5DEJYf{(nYRtD043B<|--}HUhRVJhb8tVZ) z4%=WlS*m+me}I>)@orUWqfPkCn3bm<{bSSjXk-ne6*B*zRyEpS>UO@H@x&h6#rr8v zJA3ClQeky~D$6Ql$AI||4pwJntpAOy-kaz&2J(Lbq7cq@O(RiVwTXZ@y40uU>W4-j zMos0U+pceY6Fze3OL?ZZy*6*y-$zT$ReYvAyQMQ3GNjSQh;(F^+li4namE%pzr<6d zR%proC!&8u4~XC73n7A!ei7z+Y1$v56H-oVA%36tfDRODf(3i#n;QDOXL@F#6;9LZ zDg-?IH<pL&+efuvmv8VRTQ@p?w%d$caAolcK~3OJ@Kd2<kZH=;9qlUaL)*k7+mrb2 zh?Ua;<PL#(D%n2OiMh+OIFBl!j~TnFifyy3AOtg*BD#+k&jUzBZ48EjZTt%!z{zC1 z6(uKEMZ08rs~G^DA6YR^k#PFirWYY`_v(qJtvU4qCg0Z$0^?ogj)ISSLy?+J6AUoU zSR!H{KaLVIL|u+5Jo||`XC4LAWEhupll~l?iS`00h>cXy-T8xJz{Vp~JPa1tj3g^7 z=gZobkeG2952hI%#&@Sn@2rjmHb?Gk$HXi4&8C{*ko<n2s**FqaEA0tb^r5_rZ-;2 z9L>KGHP2?P%(yf@hV`vj1U^4d+khPf0N6kzmU9dFju{uNi*f-3yXxk_uq*vFb0RKw zI8j7U71$=+X5X&??5|o-!{UfadlTxmmudF-?P))sJ0YN3&O9i&8_sr3Tm8T*gkNhE z5D)w-a)W?0T;Hq8%sUrBs0#SKd>GXnO<9Y&#()|0{OfyECa2Ayr;=Icq@~X#^FBL$ z8C-oP%8L2(yC(bBP9No!`}=A_$|vdP^ZDy($B-SvvvOhQ;_iX-;{s_#lj0;TPUwKl zQSUP78PjbaM5AVP(_tHuAneX_>1ci`AJ1^<xE#7QN?|~|1{(_Ee%<BGqJHoqoeq>h zg5*gD1+JWT$yY1Ev}S9+S9Ul)s+0J7VwV)rX4Wu&!~cOcTYI{W0(><qt6eV=OtZsI z6*CZb&X+`cwl%-@6<-@kz6yhHHX*dZ*E4OQtF);_`Xa>(M12sNQ{I76ybGG)^)wOB zNzzf67Q?n{_2~HWya6K*4aX6@P!N!S(HcK5m~J*F%510{p-Tm^+7O~eKn*VUw{*%1 zn}u44g7l0xH>8=>1aqP4XS<bs+>s;9aksVY-o%=fUI~&BkP^S~^Z0?p{k^cuvw=k3 z3jCsv_E&{2xTe}~Tr*BVtv`Bs+Z2+cLAGQ369oe`BDTIKu!>m!8LBc2k4fs0W9vTs z62kgG&Dq_@a2Nt3vh*D-7+T_#EIg|?gQ2lc*&O8$!*v$HJc9QNcJfy{o~bh3(`PBS zZNG8P9U!mEawHI$OETKuJ_(*!;LGLISonB(6KGuwwet3vbgIkN-}8F93bU<T9?PG+ zCb-=e=qDO0HbOqMgBDsLW4tZ<c2c)Dl%~CO<}Qzkc+xfA?(c`ev99$JKjEIU)xFS| zu>y^!BTji13k5qbl?p05_+9*31-^;O-1Y8^L;aZ0q4k10QG$zr&a6ApHBk-AJ>Z`v z#wjP*r@h^=XARby%2&?@hb2{TtDvmMufpgyGo+ba6fAJ(V$a#4d2s_8Vt?h-gW1ZA z9Qv2`+BjY)?vdBS1rf>LDj(EaUb?PV(8UKwNN<zK_V@Y?%lND6k%~{NUR!D)W{*ov z$eEuxep&gXue5`>IOSazxlw^2OKvWU!DEw&h!Z+tq^$6h{HD_Uc6ANc;@nejHuZu< zl3oTX9MrBlO``KTr9e8X-Uyj(PuI;<%c@CfY1*`HPa>CHqAkvu_*1mXl9PS=(18cN z+V5OM>5j3cWikl6gemaJ`oz^0X>@ci53<<73lHGWJ@wm<w#claL?O1?KQ6{6Wn6b= zA#+Al6v+-nGh%7HC59mKExUxd^3A!<%aFopY%81dt!*OCqEDNLztSWJ3>l}THMHT} z%+@}$!$SrY$7n9%jUR)(Kb`LiPMq%PRS6HxSd&~<)!8mm5W&&5!*S(mL5>CL0layH zJDU&_PPVdp^T-VgZNY|!?7D@rrveumk*7O3!k>bRnxs68d!36*s|EQcT$zKh5!TE1 z$W{+C)Or|aK5Sp_K<*tKHx8wjI|=g*c(@!>mCICU!=1mW7Ql8hrhGilRp(hZ5jTSf zLK;o7Cfh4vta;|@@U-(_pzn4U^v}9(W90t~x*0I&dY7t-mr2_a{ozT9MRrS7>U_w< zUvO{7o*I3K!&&Axn8&9}&L)A)6EMVSIw3*uG{aaCF<eIHJ+$9+BHi=`q4S~Qk%}rp zD4INn$->**-TGZjQdFYLxg29B{v3M)h7|Y+eo!-vwm?|gK}?uipL0;NCq9-6Vtny6 zBJ71nhaM|cAHx)W3YylCNANHeLZ%jA=jkJdHE4tf#*Rf1H+^jZZnyB)M07<-<!o+i zd+$(vW+tC35{lOqTi4hO8j5R63-JGHw6`nzbvaNGP2pwn6Bf4jb@&_8m)YiVe>5T} z6jw`y*k;7&^bJQ_CsYrv=K3YhA<X>|S>Fd2?Ut&IxcG0<atci#_koIXY|mSzK<AIy zV(Mj&9|a!tI`1tpq^Yfq2)0MH-b9X<56Dj2^OVm}l3Q#J{GJHgrPP_goZ=OhT*lVv zWD%+^Cmexqz2kY6GXn~0E4C~hbY?d0oEo%|RMO@5(G8t}YLD1_xX`K}4j>Jqb07y7 zJJ%ukzvo`q$8Uw177ngm$W~0?^q*DKL5|8}ub~PX`k2F41ymk|t4EtK>YKv*cLV49 z6LNX{4ssz{a|)BC057zpf&|w+Lhhq{{3g${*#r6WNB0J0LC0`H)+@d4o6Bm?E{Lq7 zaQo-`q6n<JChjS{2R=3Dgq$3&-VOIw%|fEXfRRss_!`X3ZP;92Yi~3#UU2QVv0`#V zUvO)0>Ou2x=R(t{^xo+;>t%-4DlEGu{bTdz=U}uy?a}7}_k>C8lRtX}e-%;VdsD+T zp^EhkZx#0E<9m{)++Y#pp~L0zvh;!iLMM6qH5wMik?EgLKmWK&0x1fglli0zT^1C} zkIwSlF3_c&tpz8O(SgmUzBTeGJFaA&vz|s@#|!MGzeUtfqT9X#v-F=nML~Ob$@!<1 zH_E_bmYaI433SUUOs)F=xxG~=rPk^(Jjrpr9|E!+=v!4Zg@x<i%uW$1Zr*j@*Bg>Q z4SoOVvkvQp93K2g2Dzg5uELtdg8us>St|D#hukYvh$*Y%$K1u^LjqJt!p*^)tk*^n z@a#s1nV_ag<tpa0-`cIa#@G5afIIccv&w)ngZH9A8aSymI*RNDZ=ygbe=hfQ40hxG z!s3*+nN=(C7_Q$p;Z=OAykEQ>)GX%z&vogKOpoBHU69fsntysc<R<BcpYF(%X}Rm~ zArGMj+voyrmf0Wme+MVzrl#T&`pb~L{C~Q=MTf3o*D6kY;i>QuyhMRWm;Z~4aO-~= zN#b@^Ra)W4)s(z9h<bUtuSKM9>e3DWYt;Lkhi3-VnGfZq5m-z>*yk_P!*onLsf4P@ zdW{&vVNkdqNK@%^=8+}FcJk|{#Ntc6>&$um3H&eqnE#BNVbQmFmr9FZTZx;(udi93 z$!%!zd((o^EX4jX*T3$>VtwY7D}sDeOZ-eIqbNxX5hh9gzikLOEL8rqFY{W7Oh$&1 zMxryx{qIfH41{gJpLy@zgy7R}sxGQrx&N5>A1nN;JBm101je{kec1KEH&VLjC`2Ov z*sy<%g2&91j%kOp!~fe${mv#jbQ7F_$r~TRUuAU<e;5uJ56F@U55vAk^s!eaUv^td zTQ-@2dDG+V-LPA%3T#@NI;N3Kbf03Oph+a%xYw5ZI%S^tRfJ|0CX<lgW2)y#5P9V- zn#`=ry30_w{{Q<u&rOF-kxhZkPv(l|Qk=fppP0?7M(beLZ*9w)K_9WN={~n+uLxM% zZj<N*HI|*AZAK|Ue0LL7ukG$@USP}2$OQVY!+eH`hGUf=gxURBDB|ArmzCeFBeloJ z@9i@-NKbc-qv6(9>~yZ6XB}seWgYLX-#x;!XMcvRqh;~mDRn{#g#$4>!MdZ@x-d3_ zH*%}66onM}%u<<m$08q~*B~;`I}erGo))<(BIvv4;=@<N9X!+FyW5+?!^6GIzTx@< z)A1S1LsQ<)Gsbz=kK88eirVW{3$zzlI>|cnc)I4Y6{mZ;GqWe!JQ|e+dJ&Hndn?P2 z7P4ouRI{;nTD-Tl*xaOl!cfj|(TnvjGMf@+Ue&jltcNLR_fl3NXLAE8udOLO2j^Gx z>Y>+pJOnq)_xHCorm4r)t}kW@iY@29PE<&ko^Mv#zdQHR>npPC@>s7gnvltrg=Q5y ztw-`E48-dZCL3*QrhCc$gq1jjpX6jE3(dQZcowEiAaz}oLn9`pcz1TscF7OYCm47h znPzbzmsrv~-rsdu#2*u42yDck%W$wj%+4{_+1eDDK4W`Mdjzk`k&hj6qs<mJ{4$)J z;f)iuS7l}4Xxgf0;I574_2s1GBsTm^dRQZy!1~J?N97Tl1OGzVg(Y1mRl<J38X^xk zwF`*Y(cKpw9vgSG$Y#e`s~R61To)JLe@5ytF*t|={Ew2<135T26A-`?d^+o9X7+gd zW;!Dy9Qd7#blTm_tSKX-3JcqMa+9-F<hDu)q8ku^Q$o{})BJtf47={9bzs05Iq9^g znHkl!{=Q4Y7z-G?j`P~7>Kq$;SAgr}DkH<W(AO2cl8V$Lat`7wF0I#DyUWFOQk#)c zp{tX?TVfp$aQ2LJnsKvsKG8|HZmRXP=%e$@?JjU{6r>*F=gx)JieS1r6#in%%mMP5 z(Z(~E*`alq_HII>v!El>#!A}qo0Qh#a0)w4vdP~rlD6gA4I6H8-V5#v6WabfMdk~0 z`@zB^U9EHUr$6uAlX!o{$$0Pk!wDH%LGAXgsuT!=c9c~wM3uuB3GK>-!T~S5%N7ly z5|pQtfos-jT=`dc3Ti9FpCz=s5;!aQkOP;|)(|`=+XYR6#HTAq_ljd8Vr?p3B~Qo@ zPn*HwL~JBc^h_;98+@DSy>+jw;12bOg%bZD&&igS@a&NS-=_9+G}#HNGDLA%?R`Qw zFmcc=0Xbj_N`ULWXV?74fwCXT$3=qzRkl28?%Zq8ICx&sV{qDM^LmF`_qDEiP5dVN zux&Q7bg()qLCeW2G48(m_`F}WQ7+T2ihBLWkpbX+H4CKq9uY9mIG+e&6=v17BD_ab z6;lZ*kJhnx^*}vNgu#2pVJGB%-HW>g<jn}+7n|?@>6SSXJ82KZPA7~z)-%HX&b2Ai zg6DhV$@Mo`z-Qv?vR3DeS!v>G$+u=6Qwj~UZit=JS(U3~LPe1li(Q4XxJg{u$hVME zj>3r#{A>M%Z={X?xJ)xrz&G<P-ubzF5b9a>IxGWMO!B*BaONN1@U#nJs_7r{tzfd< zdfZT|!ZD$!iCxm8sv%{ccX<A+vYPAgMys;xlBcdiaeAT*6Lzhsy8+Q;-cWp7C&T!Z zTn+P&<K_wn)<|-@yA|jEaQ5C&O>Ry5upSE{3JM1iX(}SprAv*9NK;S|L8^*M6Oi7C z4UyhKS|S31(jkC!={<oUy$JyVQUZh)(tbPWQP1-{@A}sI{yFQobmhMH-m_<}x#pU= zdyf#$YIefegrTsacl+10+^HwKnD?z>Mbg7G!iG8M^WtQRV(PUk>mDrIYe1q*&5e%5 z-HGhm$ZZ}vk<8j1K){EKjQMuGSSz*-s<GbYoTFw-HCrW5_qgo9oIm%hu|-xdjO5|# z-s*()d8Nm8X(uk83y0_wPPwWWA-u!<%8l0TlT0QFMQ;222Nd?g3tWr!UcnL+pr)Eb zUo<^PTH9t>H4|}RxqEg(Si)5h>li=NLd++=>N(G8)aYIOi@oI!b}f3o-o5AjH8NHy z%_wJakhI0TZ(Y_`Wbs~&F*4SI$9i89^`wu6Cmiu$X`3TU-9pQ4ps6`sOp{GB3w&GW zKQ~G5ptt1IM=IyACgl*~5(qnNMsnVzy{5T!3X8xSm%z%xzmZ?oL@S@J61^>IzQ;;i zld`}zXdtjbsTDvQJ&|6wMOV9C#H~Wd?p`us|Ic?9+*i$h3y<B$@QxQg(DaG*-OgD@ zx576I!G{&B`mM2J`kn@!n(`mMh5AN%zg;^#Coa^_8QtE}0w<s5@K=YIo<^~02^mey zCTD+Z>O}887La#3Sun&vI?PS4;-U%-5j^`40on6x&rbN!d~W}GjZ~)l1e1<>z@fPl znt}Z)-`@V@9D#5tcH-eB-`VDw8@W|c({}8<*(npg&S+&pE*t+71?LHiCHY`RwCdbE z+9I7HTXfB&WR-v!vu8>E#ARW4+UFU<6x(7Sjx1#D)*p}-HJcM`rD2>dso!^3WF_Rl zn8@2Rw~bTrb+!3zbCLwf8&Q^&$}B&GzD2IBa$DdTxQMOk;z)Wwgf6yp8^z`<fq$1g zaQ7(rIg*3^<wp3UuX%`3a_KQ&VFX|Phbr?Gq;^Q?!5!f8=aZ!Ii;=R>(DfXHEsxzh zP@|jV5vZDHGsI@a82(r*PHR|S!EJ6E^}G?_k8lwa#?rauz%C&#{ejU+9sQ_S#3);- zW0y(_h<S1In)3rkV>6v&{_CppZrU>Z{B^moob307W`Aw}gcckJ<nY)U(t2K)4>?h9 zXkfsg9!kqeE^7Tc51IaWhh$?~><4F_VbmMMk<OoO@-RT^)>H?ahqx^Zrx5H{OU0mM zV#LOm<pnBvoNBwBCj&g9<*8r0IwLQc8#T|q|Iix=0-pKK`U4Rw6`L_07k+7plG<<x zltRdZ`D{RZO>#YmV?H=C6-Oo4e4ttbME&g8Y2e`KcAzZ{%k6m7b5W4gHzWd{hq8r* zlIP*^i)PfMWu_WG$m#|k%^zBd;KKaIsgzAGSNyiSk`^cYmsg=d#wpqrd_gL+@>|84 zQLLBb`n{(|Y-$|GENZ;R*3FcuPE00GdtS1Qt)|D9c2=)2gpq2fvXspl>Y@&GJ9WG= zkGh@*<@W4mV<K;zr`?&0i9S@~xY>h`=|#M=iaux%hkh9J?+pxx$mZOjkmk)GHN$hI zHTVuAH^^qJl4#}JC=YeS3*u5w6s@wu3FVTfvIoJc%$QfPVNB5FHm@BcH564a&1F_b z@q_j8|Jn|{1nzpYw^cT*?6q*JYnGY`)1J8&c;X!?=orr2ZIRllFixFA@wgKf>C8Ol zQ~JleTU_7@YfbZF71Wdl65*x(7%?Rg*8vVw@v{76ts^w1wQnQ>7{UG<hAqb8-Y^|- zL$!DO*a?Q07RY#6D5X+Pl0`W|Np?}TWs2gVmwd`sRNlDWSmoHN1%J~*308$Nf&izJ z2i+v)LCGY#ywAAIESwzalfp*%+V&{KXF4~|cpKRcsUpU}w+FI`%y=x*s5h2=b7XQc zF#$qdMT?x!3`kUv*tP4+vp}`Z-g+zn81}bUI|<C?k;F^|Bh$~T7QLl=Jx3U0299lb zEBIQeMoocCk5>cr)ofmQEN-_{4z}oxV%`;K6vf(YP6v%g+ZVSAuVNpwcEZD`BWz=v za~!VQ0~W4?sYewij;$5SPAlB{K8`3Gh;O&j=9w83|A<rjN3+W3w6yKs{iBRYHuP|8 z6gXOz9ba|O!9Iyc*ys%aAPiHjCG#VLG1_MJXFl4{OA(y*uVM{@)2`)5+<>oi9b3i9 z2qZvolmHty%GPv+srQ^+oX@t2zPEK)7Gz}!Wx6)T@z|GCeHTP6@WhD)|GaDMaQ=f2 zU+ueJpxVsv#9>aXo?K<NT_G~Sy|j%!`iZA3%G5t}isy{?t6*n^xhs^CE^XIkQ*&@< zW{Xa`=JNe{bTl^}IE`{iL%CEz^JDqCFmmr_-l3k(9PDk$h$z^n%G#uovSg`QEq}*t zKP=*mg>c1T9P5&dalQ^W0gr9*35C2t>~08yM0#+J8|3w@|BZ~@lUg7$;jp3Do+kpO zoLHAVp%09Xz!Hbsp4%rayHPpAf-74x#}P;TyvDu9_-mf(KcIMT)axU?NxF@Fkm1<e z7MVyve=msp6-CwD>6Ya4pNm?@-GW5k8!<agF0i;L&z`W`rV*NCee*3v+6_+H!3BE3 z-ny)<@ErT;wX$4N8CVT?#qJJH35r!3%7CAGNDO-2_+XarG-~Cfti;>yXa+dkc`8`h z1Gp@ferC15zBdGM1&m_d^EqoK0@^V_q6bit&2=sC;WSGMXKvXFY#vh5AHufa)Lup$ z_1(yLjoX?xqpqT$lzJQLRx{OOkxIcqshdzL)~05AyWe-+GJ+&`tm^fxp{40M`pE#h zIo{@;NAoPhkw-3CB+sUop4MK|<gyt`0rzVA**a?1`2)Xlb@1-xXlyw!=7PQQPztAV zzopyd3!GYK{mm<0@lK!2;hI|uzLG$0g*Tf|EV{dGv1`Zd31D||g)6RNQK<!t5ggK- z9AQwa2~2}NEUamN_#JZUtO~o9oc4(yR_AYHx8Tx4AdY!1QQ(kyvRg7`Zm^U(ErvJs zUTK6-R>G){W;!{D!{d~V{u)Z}uql{NbQiH;-`eK2$12{gme;~nXEZVk?p7!gdf`FP zm{#%K-G{+S!nVOmPVTHkx}iE?bq3X!H)KP%r}%ozcdd6l-yzM!huNN;rX~v<4620_ znUdnrTodnCRukXdpCk=t1>x6Pd2`eqQByK2W=Br*iA~CSC<<Ugl7z%ZL{AkWE3w_b z&ZGcmi{*UU98ZUoU;O5!T{cx~gaxlmI~FtQx*1h&f=R4$xz3ET%4Uy&Q%TtO1Sexd z%@MtW@?K=8T3-DQc#n4Ud8Bs*u&1?4icfR-UI0eoXJB!es@8CvL9PGoYx)j3c*}v_ znL?7|mEoM%R;V{;aODij5!xVDv;phkpu=!p9~7z<*MTd3?}YQ}%l474^&AXq;2|4W zdZkQ{IHZ<|0e<Fs;0$UafrD<uqv?_x+_R+$%n9&g5%rplEhvDX5@k2wR016ekAhH} zAryxvPfmOLPWZ72=0F)Wf^Bu3Mg`S!-N;Vp){=qKxB>9W+q@#yx!jj%zUK!{@{An+ zY)o*<nRBWlI5qNh`Hevg5Gw9o!>d@tn+ugyRD#nPCLN<RE~XHcahVH{wZ4|+2s{=Q zxDP{Uw@hQlxtya}M>K@GW`P2ZrvkF#SE0QAC7BJn5~_o$CP#{my3V~UHQneEk%i7Z zhtw?BfqkvRv%v7Aekd8s0QQ?-_antgJ&#mY@z^PbSHBhRmDZZPjY_7X3K&34#1yK` z1Rj<8oi+#&L)s!BM3e79@Y0VSb+_;SWuist*v3{*qs$9<GnA6=9ZD_8h&pD2Wxp?S z6d}=nI|@>&kwPMvQNicvsoQbtMJG7Sp}rIQaMTwsIK<vUTpog3J}bK|`h_lR);npm zH?Q&N_Z!nKs(9?utOD^0gYvAh>5db*-p(SXAMg&u(w}*f?S%am9BJ?vr2jTyP#^#5 zW8vQNSdtv&yS(3|CVZGA2Mgz~PSY7Jvjls(rTI7=lDvExi(viAH**d4^g@`spy@0q z?vNt^eyNqLNjO(~^OFbh0~U4ZDd%DHJtm2~AD?787H(=FRQ!1L+u*v|4?!v7v_d+d zkaoSZ8iOmX?rk^a$+HN+{65xg^tfHsDz*~GFZ`Y&rz>BV!v|%2kL(_ZJt-^_4GGgb zpf343ZY#2SWgxcY!f+HMtf6r5U8duMa0PBJ(G@O#^I?A#Gqo4<Tf0`(D{>K7Ey~DQ z8p<Ot+B12tXt|AhLFa(%g8ZF_x}_FSlLKt)-hDv#{mfOYgQ0A~R@yy!mZ<?-9*Nu7 z4$DEkkHu4{gVXU5$7Y=<ipMxK6klE!ddc~)%(fjKBk>KPiX3!s7|P<WCpbOue@{h6 z$b55Wjd)6oThp22K?kMS{S3gd5bB-84nS(&L6QdXJN`58uR6dPKT|#S+eRd*fX<a= zhS>MCAOuSHmgkc07F>{JPA~6-OD<hILpWq}pOT%{-NfeTuMoy(%LJENTxC&+_By=+ zWqflIYL`XY$zg6V{{BhnU9Q;?R=S?_Qv3B{>b^11f4ARBGk5K}PNQFcgG*^?r#6x2 zO&2wd6_lO=7)8tB{>)Bxz+6ItT+kO!{k3DFt`S?Nb-OQ9MrirNu3dkmu0KKM{dXZE zf)hpHmuNfuU%&JZu8s>ot7W6XVTh+>DtwG6IK2P=_&HkINKrHyx>SDCvu;QgeW&w~ z-N_x^`JELF9zCPMBN}s=q1jUp%^NXLa?0VxG|p>>Ia^=3k>h#q)x0(_#{)2$i|Os@ z#I*UesC1=t_W$)OIR)q4XOcXC!$_2roX5m<B%9O=WFf;#sw~1u?3jY(GO>M`{Hs{- zA>8QhfivkIJUId)>_gada~gAk4DZ|Tb_lw=L$8{e4Gka*3w)GJ3=KWY5RT~ceX$=5 z)|sH2(of<(mhk0ABXWJD8q14!?Ht-4Nwf7EpNb9`2j#FBA9QI6adG`X`D=|^80J}Z zM}x_HzEv#c_&mmDiv<1q_+oq6Rl}0~zMr8CFy23iHxC{Y^P|q+cFp<DIa}ciEs~$G zDvCyP$HEGW6d#$v&)Ggax)xDz-&?Ev?$Av`J;O0qYVhK!_As+S`?1Gnwn`bXT&6ky zD{Y&^wjGlv&L^^f#8?Y%)|SZD&>gd9_QY8Y5v_OrQGMC52X3~)RVhz;-r>Oem}ktL znd7wC)U3&OwYO+*MN@8lzS7K%UPpVNL6acCdhR7U2Q8fS%^@Xu+IS9wPC?J7JxZ5M zXG?ERL%F`5Sf{>rPDE7f`^uqZp>9?x;^iDl+OO3JNT@{h_UH<}(aPE<_pLViV!hb@ z)6Pl)BkVuH2u>Glmu_b9=6TL&tnYOc7LeeY8)HVrV)kXeROXE@X1i*B$<6SA9E|r6 zj}GLkx@Ioy^Hnz~pD!M1kG2AORj)FbdQ}=Vm7T`$v{rt9`hb&LubVwa9JXRm+LHOb zB`b9uz8S@hC^6esu29$4jMGqHRUB*=kyjpRb5j)ZK{}2KY;>dV+&AB0w$ia8(UekT zwE~UV&@prgZA=$goFCVSGpG&GOJ_;5HwrZoJ+6az;hgVWeYi<sLEd$P&lAV?KUtfr z6iy?Yu`a3dx)MHZn|W5T{UtEk6?ZviE^I5D1v65>=~KssMv~+TE<0X9-IKGRDE8T$ zzXZw-gO(J<gt3%tkdvC0I1}0cx5Fc0CP=<oUgruQ`G{Un>uGldAO?>GL`j-jc4gC1 zv{0JHon2Eleahw)#y0I~<CZ+VjT~c|8=;LT!_Piy*o88XI@8?yultx|J(GA=2+GL% z45pw^eWDyO^g%P=%X#6JJ(5!>c>Qy{dLD0v-V=2#V}Em_(?mx8eJvh;Z3GgWrY=}z z6*oVSwH5Az<b1kHf*&uOw-0VwLRn@*FUT;7dRHzuf4>Vg_kHp@cwGq!yB{N}UHG28 z^sYbqJ{=i7&(gJLYdpsu<i(Cj!XWL|H^v{E6JH_9ZSP(h(l1xt4p`G0t~Qc<1n(~{ z=iwhRoae}X+;TtGADh{-Q&s$vlsWNW{K_D~>BionulZ|(UuE<@i9Odgy2#N2hlH&S zi3^JtaB2iTRg3DA!3K-sr%*1fNI1(Le2eV@`;eOFhewSV0imq=JqJKa^vM<50q1Z( z@^2nbsJg?QHR~+dwjx}AIJVK&Wo772t_O=y>O|ff?GCt^RZuPuBE7|CI5uw3(<*P6 zs)^FbaE;YrlV}_>{Cv~mkneDdwzzbkhnm;nN!^m!Z5FhVh$>3)<EGp58Y&ql_80Ka zoy!!2#_vc+@5=(fgP708t%D|N`%SP<K7QV7sL?A}cd!@A*pBpNVQFvpbacg~h!E8Q zgcI!R7f-vLG*0E^Wk<Hai{_tSDeqlx`jSL&+H-IU6_s{M=$%87a~PNhk@bQ<2#XRL zQlPVsgB7^yWt?_Kk~{=BP^{=0;TP3Sj+pm(Tq7Fg8r$07#fh+(Rd@aDBH5C|Pl)O0 zO_4XssHSk=TR7ZbV`c|uK*sPNFAmBL0%$xITo!Hd(6*z_$wleF?!Oq^x}iZy(iI^T zJy4BgQF*+I4V3`bGXKfOovc9Pmap365HrnTqu7chku2q}2QN@Fq>Mb_QX+2TkU6y6 zohZU3qqk($tl*Wl7pa~x&fz)9%KTroqZlJhIp!+^^u|74*{*ah6*&NnJ8a(iwH`ng zVCFYzX8w97D>s}>6qSZ<^vtMNSwPKuca_i3>-x|;54gL94pB*R3Zka&c<g(WrIgZ( zrFh8Zp;)$QKvoLv_9;cU)kf_D1AEKXj#~BHm_BGv4AWh;p!U8JY8-=HP#qe&qdRV` z_b#mTKK0sA%5&x}$`I~wTI!SV@gfo--&pMQ85-qtF_lJvAKszB)4#~76p+gFi)X#9 zVdteqpWn$o;G}32TGJsa4n>A?f}`Dv=y_fGv=_=P%JJpHbot=(4H75*{!QdR#O4cr zeAHBZy1jbXU?e8wNst8I0#dB}wNK8A10s;~#4ptieCyo0gE%ajHLzPPJE2*DVceg) zBtNEi9HAiD<A`&4a$IX|EQUrM><XcASh7D-zQ4u~eGG8Sm~z@m-N$<2bc*x+byPfJ zN^;o!*5eB`3PoI6g3yS!5PwNjfvJY0;e+^+NjKp>ewalQ?jr1>my~Pk^g}v~xqvzM zJVjpOYj?EyW4fVKfun1dmRb~&#|3iAm2F{R0zL&)mV$&|i%j&EJR=;;+ECQp&UDUJ z?SvG|cMJ~#b$PTYB6zz9y${`sHbGaRo6~I-^c0YVnI2H9DrCg?J&qb%I%p8W`{RVF zu+0R%8=aAk7f~E9ABgxtnt~ekuBY`sE5;$Sw;i?rPHPvdaz0PMqrbx?Q`1+gmWP+> zM3SUJo0P8urI<Z?q5j5WCV`v=2Sup1qM>380JqwldRuP;%o)ei3!)hV_Ow@%5d0F$ z1bptX4b$YZ62dv567Ld($6%3mi6A?hYvIxk)e3|;!@H_B!ebt7Pz{ti10|s}t~Hi* z_H(LkYHB%a+RJp^HXeXf{=NBnlH;O;RqQKRZxNP0<XU3Gu96J*O3u9D^L=Ei2W0FD z^7ssvL8geMeP!*Tw8L$7|3I~_!_z3uz<0dOoQu*kTbPz`u9{{sMdh!x?eL5N8%iHS z49$7ZPeQcR?LchNTh%U=5@)%Q4{m~&^PbpmGsxn4dga$ekNqHOpQop}C^U*66H};c zxuIY9d^)S-=#PkfmBzSo?669-nz!Y{p=hJO7B#EZ{R=WdD(UfrFS%b}w@)D=Ln<}C z_VC^x2r&>WaAb!Qp#jdXUpr`k8S=V<jXSK^3t^zX!`ZF}|Ke<aV8!2;b_Xkdc#O2v z+#MpLE*v(3OnEQ?*ml#pPZrsHww9g5)TOkmO)|%SprGF;{*%z1X)#!8Yr3fXXw~BH zA3@{yI{rm`(uz9&x(2_fT!7eVb){XqPN)LcY_~%+(rWUbq?AaP+sxNHr0;=|68|9V z-wT#LwjY%wX%8&k>G20|MXx0i4WqWxFse+A#Sy(LW9SPf=Fdm2ooGfN8Iqs+EkiQa z2w5(~sI|&9BU_0e66jf^saY)l29N(du~XLK+d4eg76Y75&<9?0)OV8g+cU+&&$)F1 z#j|+2JkBpQzr_?RilD4mil$dMeF9DUpSBfoyKI}bv^*ijt!<`(j}?<?%h>ho_db-g zrP#maQ8tQRu;|eExcXv^kRJAcqwUlE$ghQa<pCoS*;OJ44Gn&nw%RLgo2FpPcxy7k zR3VhLBg9|V&aa;2A$6>TS_*P0w*nY6#utyy%dF}CnQ{Ey4;m>3N^%-JY5u)_UnO-w zgbr<PG#7}+8a%$Jlu&(6w)%jFqFPt-@sn8DJ~^$eElhI#RqYe>6PSMK6Z3tg&wQlt zqJ*ofkG|fo7wC_C3sK{?+q%Ll5N6Ow^*N)=$^&$L_64y2wL+luDF3QHXvWL+am!d| zmkEfw)qCX~%2q9f2epmQDlreI1JsrD^_2MKJQ##{)cNVg1oCaYgWaTiUEHyTniXZT zcml5xw-^O=q&``V#pB`%Np7XvUng$kZD6S2N-o7@+us?wc@?03nkW4)Umr%2TdjTZ zshf3N#bEe0h~x4(##hfA3Ko9Kr3JBfC5N~_O^!9~i-h>&2`BF!2KaE7Yb9~0zSXHo zPb$Nr&m{N3)$pb;{^`Ytm;UfN%Y{`8)i6aHX*N5^r@RC;q>!Bd?}u*(&LBAsnjK7h z>2|Dy51I>}E+Wc}x+blrIgN@aZmw3G_tIL%V<(orvs0eE6sa#*zMBlI4WCpEh{-#9 zRiw#tG-;xcmwpu+vGhhE5`w+U4c`*1Ux|Lt$=>v!nc(CJ5UU6En_DZK<G-8*tz4EJ zc;eF7h`2p6DeV)dYOkEpC*kKvB)sRrq9eiS$oVFt#k)%e7Vfp~FHXu{Fd5Pd_S-&l zwUb6DdikLQDMPgvw_d-}FH&2@HuUzdB%mTvVznE2izaK**+AK{ruQr@f&DMDrahUP zHJKdtQWa(UiMo&ltQoL0?uV!RPD2^%(BB*ji>6y#^$AWJ+fHTy{fzrxS8N`(HhYD~ zBGxBX79-BoI1A?9AhS>{1J>d7zjEY1ZVv4c4+0z~wdfhLJnEuN|4Kg2ruJ8p`*T0R zc{ov5#zR=DQr&QjvX1ho!;(gsRadd^I@Ez)>>%I3r;?M9y1bf*08r)muX`T5^+6~S zB4%*NMA~=k0{|+X^v+kGkDoN-3R)M4gYZ{p=AJSynEpIbTs^UkTJd)A&89d3g<X<> z&jayA(ra@Ideg=WkP>l;w*_g~<0Dal`&#RL?Fo3e=NjNQ{>z~WUakHJB+o!s(-G>L zZR%~FIE1%|xz3AmSaBDQ;R@sO_SJl}-$jgDoAcpNB&Goqtu4`vez~-~++@ziTt<3N zz>@|>h0gE}gtdrvjp`~wxiwCZEEfd!8UX;2|5(}f!4&(gt+!(Vlt%<STX_ZfV!6;- zd&d8=m{0NcaRWj7>R(KErVOE0n6g0UTySilQnSiO^Ur=SJKd+TPlKky1Csaf3eY*k zK$temGnKI@a{)|1l2DF>lP|cN-W&N1?2+#F&E{@-4dHc*W@yO*I|!&VlYcNKf1Dvm z9pa|i;i+WnRv5pOgsrCV^U#c-fbL04VFoS@CJxL|=M4>(<`Fna&O!11^ePtJ`V>hj z^V}WYK)Ne{5?a03GdUd*J&Nbhf*!d)K_ajXJ!AnjoMI8E@5Z1-Ue(4>kmJ^O{hAYl z{lm8=QyYrBsPjHtxFekW=Eps9->;oVhbCDZALL*3NT1eDaF7fd%LHF|@<x+TUy1K6 zunR=p2YJE%k>mrbI^7KwhAWTzB=WyAm1b<o`of4TJoh)4!bv@6Z#Iq+Kk}*Aww|9f zRLEDJr55XxA|h9?uY#2`X+pyvQMmVSa>-@ho)06;mS1fuhuR+geFc=lN~Te?Qe^3n zb(S9bdV*9d4?!R!iTTI-=JUh79qSLvu9bVx-kUND3XDB@zUx`$p>mH`8rjUO(qk$k z+`->1+OCv%!OwE@&vLd5WMR+yf`TIorsUNW%szH~*5k`ltRnyQ3iAmkRpY0%`y#3) zdDp6!edlb~l-oX|6=emLWl72b6<$hJltGk~WBM4Ik^)LAf!-q*(M6gg9FRc9;A{0N z<5!edkbb#97UCHQ#d!5|*Th@73BR2fgj`&`mUxKO4VMvnsF<(*jm_eh?RW5g*oMjl zlF=;`&z%XR2jiRXzd(56e8*?)>zzq~?GJ8tpAUOC4sLi~35igKg?TL$G;?c~j{6b` zyf{E9S|F3EHpjfyd-ctnI;Hc<W=`0j8KZidc^OqMj%5Ti)63IIY<!ms7Rsx1?71#$ z;yU=KDzOXy3_MXg!L_*#8|V&(Qu2B=s?GXLkkP}lKG6>89(K3A?Y4ZF-8MZv$whFh zDNUyt)Jl9fR+FI<4huVpF_z;oZcJpyvEYnnhuT9jz=>Cbc`%9buFWslwJ8fWtv8G$ zf<N~$W;1PjELuTc)z|Q?lkT%FC1IashW<M9pU8_n=SI<Az3HsyFPZ;Xs9b#!O4)1F zrQf!OydjjGU*|PW9IL=pE1*y5P!<-KxX!H9Fj9v4t2esCe4S(T?%Z6k@2XWxv@IEo zw}1gxLLC{NCFgAxmo^SB`Fvle-?kuKS2WLq)i39s_FY_YYP7$NifWp^wy?)ar<qts zOfMB*LF$*?9IU|Nbk9MxljxQ55VNEJCgIhaO=W?~pGmTU7VtNY{iaLC_iJA*c*w4f zh_70hX}unbyx&mlde5h;)CRS6%Ggd(j_E%Sa!1q#7FLo!g-T6LWm4Yy<~g5JI^x)F zThMq6tZZ{;5GqOJp|0@MY&D8iQrD}IQ4k?DMs{43!xXK~!P-PTJz#JS-vK#<`@6Q- zB1vd*!7sA)z4+rMzBuAJ)cI{VB#uL;EQU}F7cx>IICbNa1+khVRoGELJ9Co0u6jTQ zC0xUt8GZZqaaE4K#5{z{3Rmh+WmqoXBpDCt4>@J76gBgis-`I1Su*ysyDYM&-KklE z+ip^gz;h|Yf+-Y3-M?s3u~{?L&ra9jKH@Rsv`$U<II<f9EPLxr0OuKpz!~aT>*t$( z@|$$OP~k68XTudr<&ad)nH)ip2~Vk)miJrXdF9_f^;a#qw2M|OR1=qov#DX*)OB(g zl!WmC-l<)rbdAza9MYgHByVcbHelce_}|l?H-eoaAaTn3K<OrtU4P9hqpghD4d)@d zodltS6nl^9lmw6RCclKcT%xnz{B~gwdzb;oN)R~V{WnB^BW8osnzY~$pnr2VG)6%` zCGkf4m(`JiVE@Fen-sMhn8BBrt(r?-{Y$`lT$*-Ea=XC@BQTO23K5_a*>Z_F!;*qa z4(8Cybb``k3OiZHZ?q0Ho<`St?xXJ>yOe6jphZdAl5J=)J8#jMu)gG0<K@SCXW+g+ zm)+-y*A4IY!u0Okoqoll?LHNu_Clu$W(u{>d#5vHpUtkOeOt6?K`uB6`yEPI7`=vz z^_1NJq6sp)Mbc3MF0RVVlcOqZ(yiK-;M8>EWd`Q@9(xIQ-P6A3pqurK3c{c1l{VWX zt=PVk%4RpUW1RNAplA0MDn0{cgl2F)uH3U<C1imc#|e*T--F-wZhMvC;GK7GnG#VY zVuhvoJC$TMqU#0WGq#a`mz&@BL+Z_*z0GML!X!(%iB!8m9DK>+NikWM*)OZO*nF=E zlS}D5{zkD!$1nPV6->7wBg8G2R^S5Xsa-jR5J<p#@nf*oDM<2_e`P5<@+5K4UZi-P zCptGyChlwnch?syD1}tVAV!*zts!*zD<cLT1YJ*-U$4X?8I-rjHmf(mUwEX)+*zgc z=V^9JMl+n58F=pQ`3-I}_$bcAzG|J@b2i1y<xDl52yd8X1t;#p*!`-PUKz_Y|G&iT z%((x^LJaln-)-=!6pCO|#a`UygIsc`nv+vyH}CtM?rC|+;GXg3Q1<K%$=mcUl1tX^ zC3{gyh59f$ea}oQS;>{*l&($fl$8e64<R)tiyAtv%}2TGlPw~Yz9I+<K1Zp(xWPeU z3p9E~WU!wV;`kKq1ru6Hnd13gnFb$t&a8&4p7>`+8~r)PtGak+2jz%hAJweJ^8+B+ zry(pac=nB*zatR<S?09}gG#=Jrd@%}X>zSZ%_!b89zxJFz9kbKhq!{qUtI>BPEG+( zWY*DNSI*|-ewdP*Z_CJFYt>_9e1C<m_>KcQ_7ys&vK{RF4Doz^_u-@sEQ(gW-W+us zmky?y5%=?WKvAB+6d$8ti{w0NT;2@ek&MUGD{E@2DC>FSpLkawmYr{qXwhckkV3ZE zy$0eCQOaTSozwYe_wq=xDd2X7Jj^<dbDp5<zCuY_8NmZ1WAS*pn|jA4r43$R#OJ;g zQMIc08Le`?B0gZ8(XZO=U<kjcgl%PBduIniIl!$KdTdbTdLoJfE#V>1HWCAA+lpP7 z59E>ij8a0yY~5I8axq2gEL;rWwHRN%j1_cd5oFAstPjDN&K_M`F!lmhu3m6e^3>MN zZ->oGG>GETV)#UH5-;ECH4C=}odo<d2dkd57w&D~+CgacWjQ!nzkmc7H~*aDj%+f5 z_}V$WZEnTU?TYP8XZ+pusUMp+h2k*SBC%iJ+nuS`j<>+sU*m_lPp-}NRMqGtgR#yK z;vlM!xEZ`!iMc{i`MNCdg8JgZBF+-b+m=W0Vjz}>Ur%uLDQq>KvWnBqJm|1-9#p`q zQn*h<iEqK^t_2IPj%PLyllUdpsajK8#XBZwODNiWDz+4Rvn#dhWfuAI*;u}nY0{X0 z6b$CoyAH=&jQ7GIvV~&&(DN}xPHB-k8%+LzSV4r>tIZ<WRkCS+1c#D-<8#)bQKH>? zwMErkHqxtL>b-26WlGr#`-$>Z?EB_9ft5sY3U6agl46a~G%&9eEu{M~N_|M2hJYKB zq`ViCEDD~QK$9B&;1@nUu0F~_tBIH%k#h5I?+#(OJl{r-*b%7hBj6tjRXbFjJ?L-^ ztNO~t+Lp3FwW#BvEc=tGh3g|usLmpNSPj$TGq?R7gy4K|UiO|niLrMd$FKJp;o5-! z0R%f9p4X5qR`a?zmKyYBklLJomG>1gmuLPW>m1viI3ye++eQtmts1_i-}(ljEJvl7 zYH=E7>YP7hAF4W|Gnw6f+`C6bL=Z!Z3zZmmHGJqC*PueRTkH@X+n`*W5$f`&?m3t( zW>{x{6DL4yU+{R=ZhAHHHcLC?2JT_l-im^dF#YhVmC>s4zh8(qLsf*GzmQ6EH%NnC zdn3l}Dn<Bw4fIF^V+<2Xv8MMih^dE~a5{z}$%>o#YxcW+F8<ytzG}Ix`%dSgOv7c| z@&ZEF1?y=I4h=6zgBWsv%ZE*@6%Lz$sGPrlIJ|G>$9)`!Ql<NiokFDhK2HXMkI2VI zS>!1~d4ksjk|B`I5hpX^P(O%{aNz7*i#la0w!dd#>X+#toGjHzTQSE@T&1|5@lK~` zl!nshzDE(9NLM{-)?_?O8#ydQ_;}IV2ncjz#^53446;19R#xfjdx>hdPf6_xp>9&R zw__1i7%z)c(2ZW!ll{z1o?)$2D;820L-n{2w_I+3lOCr*S2LV6!BYe7I&O*l;YhF? zh2ufWo;$5pMUd|Vr;guSbod$o9>;^n;Vn2%zok>aKb>sbAv^_^JL@B-m(ep*nR0zO zdw2AeVxZa5Xmx>Hux%czntC>;6W-2eLc3GiO6y-~AfYEi2SS*N;_+F#3H92te;A>R zb8lAopq*Ua%<VPe(r?12ZK#xWNS=rxtYtuG4h-(EmV4T3^D?0b%EB1BVt2X8C4FUM z)$W}eM^&N+CPbD3A_+b8JHWiht5E>)4yATfZ!r5z>L<9%c{E|nK5p*C<ECv_cuM=5 z=i`e$X*3-+1G*1Im7LYi+0j@X4qVVZE$_!O>{m@xY(*!6QQ|dWrH#}N8`aAS{Mscz zP8R|E_<+Rgo8mLJOU5qKsM;@+ry&Pl(8X;fUQXE~-vNI~AHPD>=H3$pAy(QjExn}b zDp8^tMpXbqc`<sYGN3t@__Ag|E=j1l^p%Xh(GLOiWID-%KC5!&(%k;6M)AS*mi?*< zcr1hjzBEq3QLD#1=S8a4(DvRK4l>(kY#dhXZSAq?1IH>?6m2TSJYhnZ3jvi`_*@6S z@YX1PI_k&b&2>3!63ZcsTMf}9?YL?gsjNY%<Bn*Qz)?oFp{g~3w$XZKuNY$H+5t(a zXb2m5?4zS7PT`TC-5Apm>fh`Tjbj@mIf*(<r~;BY!A`l0-AN>F&-&{v5{jbUx}7>< zkhIw|MvTWPU7&8h_~u4uueI!TDP_-N=M5CAH@pu9>1XwyQS_Q}lyG%Rg!mJn#}D{g z#~7iLy5&~Fj{JcfK223A@jdFKtYV`{WkY{i{$oDXN@+q1Ca*Z6<wyRuvbEyHeNHKf zuuU?|M;R_I6%}m8aSk6}ix<v0m18knRZ&{)Qx*EU&&HhM-6`E)IdRzDz^-h1W6TTZ z&*SUv?2PDID#oJ5+)407kn5ph9Fne#^?LMg`GuprXC!N(){8#mR37rV<4wEiIFAT` zoSpj=6bTJ<+{|w<-2?x%MbiwUl{_aY0usKFhYTo{eTFs!h+;itzH$e_9VF+sN#^?j z^H}^cSqa}5LwVzB2{mkcYZTm#UW_vw<T{^P1kL?MbiR**^TtILczJ=C%(SOgCx_<D zAeYxzeue$4BbyuH%u=AVWXskGmkr;DQ#QZkOkbfct2G`2qnF0Tm8w^`Y!bBH;5e7f z!7@X*o9p&MG#Yzn&Ll-yc6teqDCW^}O5?XRKMyO_($_MJ;f|{o^||h;o{*kmG86-$ zg8Nc7_aV`B#G(14ZpIS8>~3Qo7ARz#sprSdnnAt;lSY-iUd@}xLh!F(57y7kq*D)z z&n_GmzM$W9L+gsgeRgP8va(P4W=)vVhQU<}oMEN%n9IIohS6SxLad1IEojB2A7o+K zXUQX7&cB-qXpOULmFV~QjJD!Z5vZu!q6cz%bXn{A*6^wKo+V(;18f+L=Qu+&x`385 z4{iN^{uR!;Np0{Yilyq<3F{Om)^c+{Zp}vZvdJ%KS2!DyOJs$+$qfblqWCh5dMth` z*{C1Y(Ng+!&i*^X;snIXYZXg^J`-?eD&jFNgG7C$^&I|SC-mNU6{W>FeW2{`as^WJ z!nLb&o<a@cqk)cpuUgODo4Y-ibVH$2ruwWJyx(=ZQZOBLs&h>)QypFeX7CjkG96qW zR3FmWe&ZbJ{KC0%?f%?>!&M(m2u{mxi1mIm>V!WJ#kQPwg9+4)xRuS?B<M5=qzuH@ zvX%EgrpF%KKl3Y{O>k#jpFv@hoRDc6Q6%b?{AVVs`U7sr<JJj|;*Y&wQJ`{5wue5w znJPm!?4bbRHSVrgT7y8~Yo>oP_~7U1T<0lfo&Nk9B(IEykc2qguq5TJrm+`nWsTnm zd=HDd=|$pbP<U6vhuZX-!+j`MZlk6OIAmIlE5OvaJ*Gf1;^VE%_9Hu(q(pNY3@xqT zf`ad|Q8U+YjD9fvr}LA0g4`H=|DK}8$72)4u`x3cs}!R+3%e<jQhJv?AFD##mgGg2 zUz~?gOr`Agjf%Y<pi{-Mn>1LIAk|aXTRNykfAjkAcL*I+%?MmknQ?D?X?n%RkPR^& z5*8ZjJ1t~3Xp>j<;yH~1qR~8RlnTo0Rcr>#^Lt^tsFBZlZ@;P6;y2~A!@MJM=9yNY zuYcvJr<pq~D)LO%fIZ@N|MnbwsKhyC6u$<9#?2O&VL~EOP>KDqptocARH43mWJ8Uc z=18Uop;`$O_OYQD%Z{ph3u&&oRJmu{Xw|zWj$&sm4@Js-Mc}wlUSoLJd|r*RGMr(w zARk~<2dE~Ku<hp7rfLeP)BgY8otwDJCp30DJDxKM-+^1NNFE+quqwzX^x9-tK@4E^ zD04bcPqYSq6~td*=`-)_0xgSudIXpHPG>0goAHXs%ATe$PVTEsdTCtz*z0d_Fjr`y ze?&L`^+_%vsjZ7m*IS%YS4TnwGg{tq_&vT1Yfg5eJUo<b0dIKTD{Y1M_PRqFYlXlZ zH!}j1{i???<1ygBHdJkawVNU;om*qAl*b)T&27n9lVkz${04<%WgEeF<FHp7ncn(r zD58Wg;^{6(yl`P&Rzr@EGx~k0Xth2pYj&_~w&+}U*(`3Rm?kRwRqg$3{3wZ>Pe?bV zXzS@ifNzu5Xo1J&w{h@9+l9-N>f=&g0D=${qK=>cvzX3Nd{QGcDEo<N_(gv`ZFnpE zdBT|~6fHue?MXXKRQ^!A(@gtkp$Ra%rIiFHgiT`|2g7Gt=b8F1FDfPYLp}3Hk({f{ z-sqoy#jj-#($~;JM^3FZpNB7hv`+s~wf<GE1HY)0rD>tzf0sTqov4rv)NlVTcl{<3 zfVe`-U~g5VA4&{|%in(hxcUF8^6li$5iyWd#{cB#f3Yrm2~Iu#NBNP~a*qA*LvZsS zMNQ2fbAtr2kY34t=HP*q<{%t;B>WjrYwigC{#8HPBfh*)hF6(EF7-+msU6j`Xvv(e zs+aC4&Lkw?ISt(yw!F@}5+)ak3C0Vpu`e!3))a6AJ>Kbr?Rh<>FVIP}yl$moH65)} z1^KT1ozsrqst^%d&iJ_iQH{_<tNDQ`28a@=VyE1g9IB9t#ilS{j!@NU#3OM9TzJTR zOqcrytXJN9H&vT6As!g*;V<&SkJOAb67GYk6}s7?*L%8ze$?Af{;s#{t__PjAu9<E z5wGOXAEgOJCk*TrlX#znOd%pNJ+ea&$TJ_{2UX+Cn50@q69V2~;p9q&WTb~xfK7{k z1y$svt<|={6U@^midGuF2@}yyjrF9KGG@3h>8#r8=q>xbV(Qdz%JHF9*||K|Drh7u z&Nu7&V_S*ETr1DZo@asD&&0f7nNC-^N`2^)6KM|3hz|KK|4kQNkEYk)Q5`BxLm6K6 zd5F#!kFtw!ollxqpT{Np%y;ecB#!ZOaSRn!BC4F9hfD}4Aj8t~H2LqotGb3BWi+~8 zep+fKBZq8|VBV?lwLd*8-9`ARvcdL?wa>Ps1n2lQ<-<8YI>z?@u9qjg9}f+%luP0l zGhk2xa{!)(Y0oY|hdz+XHb9?4e7A$5+4XDE{_P)<tGjRPSBP~?`u2DIs29-pvy7RN zWi~)lfc?GCIzaL5Yjhe&STjx6Bmh+$fYlrp8oR2?I8Ufr(+Rp(51LfWGp@fX_*Yvg z+@LwD$acIr%|?NT0AI2S^7R=un)QS`n`EN=Hrii4DPDf=IcL1-jC3*EEW3kHmz%{) zYQgNIc9b>4a{ckHsWa;Qnps1a9}U)-+qV;vmGcVUZXdIXb*_@?3H8WL@AKEli;C6q zc0Z+??sM6EBNXq%5$Og+7P`I&vDTV9H>W+vIM;&~aLu*he@{&5{2$hmC@N%bXGY03 zjJp{2nA=u3_SpVm4B=_OYBxK72oF@s>I_E1%E=Y}6y?ca*AO*zQkGF$inAi!ZxyS4 zn*+$`dS(jtgYqEMPCa-WV;)Khx~SMkiIbA`ajyZCzD>b4im1V4I4oAuK8SXTt+k8w z9Wb{ISvic>P6>$up9Vi$fF!yii=o@QHw#!B^|ch5mF0VKSD+%Rqe$d?&=n;i^u{4` zEp073r(&!?x58XtzQn3}9d*=8!>n+F($&Pe5LdJ?6jo3#YW3)%c64=iid*E40_oCk zr}<%4Hu+IU$~vk5H53c!f17;vaZ&Y_;Uo<G9&;JZ82MR=`2u#1Wo*Eiq6jOyqi8FZ z-ar0k?OF$1s0|3I)3f8lblx_c@{?_{Z-h(w_oGOId0#knJhQMUs*TF_>oo_Vl5D^b z`FFr!2ACWn+f4x(W|#MKkMO<FP<5J0?U4$1Nwk-)!b1C#UG^}8ZY2cI53l!|HM9=& z?b+&;xiyJ(ok4xFqIWh#&uRtR7KQvh&L^q>)fQG#x|0@`#{^i>#ly`M&>gZ>bKuG< z*8QT%Wx(Nz%!WcLNMNFq&l{U_(6P}wywECLQOrG|!%9`UoV@QnDWn&w)l38IoB4*F zmne#j2Vc4qDOZPvl|QLIpj2)&$Xh6#;j)jpSU0@c*G2i^b&vc;-~!v%W0RFjWuduz z%AKJ>lCf7aS{V^en(c6mbofgVbJgvw)6+pV;*nBs8!oy?Nwu^L)7Oi@AZmg7;3XsE zMFlDQ>s!PnVUFHc8`YRSIBW53a<n-_R6Y~w7452k2PaI2yT-IWKg>imZ6wsGWvj2g zNiW0>bL=s*)l266ghin=aWTpQWX<j1%_vATq^2%V2HI{dUDLNMCYtjwJ|D6reOc%| zUaJFcF~D#TSKOfB9pA$r=$lXZ4~>bmY7IT<shpDc*oP`Y(RYKngsQqSKsPVn{M<ON zkDW_R>&NODm*h+m@RpfINYdR=To9*L`EZ274d=+)K$~gNQ7y{KV_ilfP=#MmimUpT z*%?goiVw)=BM^m%YSxF!#@o@(rH$QYv5arH^1<FS%!Q!6go)&`eMoi!Udrp{x5eaI zGp<hul7AS2;p<;$9MlT0KGO3EU9+~J82iw#U5<lfDahV=Y>Qn`4j|jy)qz1kl@}L# z2dXkUoeHGJ7t0QmTaZJT!9+ok)rT+ZXGr?bzyKDr^k!iv<>sN*V_eN_GVKSIQQ;-U z(_Qf5^;VuB*2zp5gnG?0q-qX#FH3>!F}HWlZ4|T{+uB3Gr?8R`=~WTSj&n@0r*JV6 zTZg`mgAjeO{a00>1o&1_LLJuDFd34y$~?QU&0*fCzi;ytRJ2=82hQA>i`l+G9hB`G z<Wqp&xz#!g1Amkw=GUMW#&3|Z8YRo_x6WCZYRRi_Gil|>7Vbko2aQgH?R56}f?eZr zls+=0*33|tRNghbzdz3Rwhg6&NCy;;-)Q3fpPC$jZ6A%i1l0XSBwR@JIWjcp<*bCo z-`TInA;)Etc*i<=)T99#ei_VfqV-UnZ`H!@;N7)r#O4z%@E(foX_yOJ8=P!L(Mm`h zt4SewXw4m;6G?gWB`-$1Afn?C-<RqWc<i)o1ilkJo=y{bNGOb^pk<$QZdk?oikT<d zpy2xXX2?S6f#!jLScKjnzjk&Iw<rJqxYi1RX((G1Tu)BAQ?yV#_STpC7pBwvVns7r zFQ{*&T?*t7tL`q+F)R(_4dZ!u=2&Z!|7}qyqxI`xHym>rI)an_=@oFnS3>!;W8M>r zgu%E-R(b8)TI3KX;k}eM2#*XDH(CUZeKJunK5=XAtWgpvcVM^V&p~RZ@SADF!YayX zx*c~%!Bn0*BbW;eu~a)k5l#<%6wSIZ)DVwWOE+K4=aoU08kvM%X2x4UbJlO7lhItR zix~rRl^iZ1uVrZ6rMoV^{GHKU@5cS*OG^5d9xPX^g(_v;xJ^xB7kMjsc1byQ?9`ig zydtpK(A(##k3u=_eco3#@4k?_)dCv3#&c%#F?1T0&nN6aQU4n=EwTzlXVEm-c}gf# zhX5{$09nOT9x-hndkT#I()rOH@*N3xD{gGkA7(qsvrt(kHUcXwXSwvOGDzey#V)g+ zrQ}ibQeDd>!0J~tD$7gE8IKorxr4zLgC%d}^8M1Q!;D%u4NQkj%il%0&@HBQ1<sOO z5$A?&aKS!^>X;PDi^JdMSq7^`qsB5)Tz<gHKX8@GET@Dep~%|suVkNBunEvt)c|^D zB9;~dux&m3zD<U&lVk5$Fnx5UBpv@-&2gQX${8*Ry(7G$opgD6)#5IN1Vuw#d<P|= zu+uqKwwen!gtQVHhMHn4a*q%B*tWa8WaKcUpKTqr=MGM?v95NqeMkpC@m(^t;@#RA ztCrZ)HK!2{;tCa|K2=LHN_UvfgawOxsTsAtMx=z?_sP;!x~`J<L+tv;2^~&xvH`*h zLDA=o8E>XFHNqa94ZpbO{krT8S)d{Q;o*PZCmOE)_%U8ri6~O~z%{LZRsS9P|A58+ zRPVbFX2tE{J9vS=FLYOe+W*ku{i~h&{|m&g^~hGQga~ypjukys;@TxF_{+|Ap7&3Y z8Hh;U!5?=fxO9j&8-o@_{o05kr2PDHJriUhzrNC9!c%^i!R=pOYA59oydHKxP-G7S z=&}Z4!;6s41nK$gB4mPs+Y)4=g$)#?dBYS}!A}4S?~?ru8lE3_-xwjBa<brGkC(GB z%|wCb=J^W_z3jKzz4kx%<N1+&tVIE(duS*Hw0v$d%;o_J!;-={0U4uj3IyfvP`{R8 z1d=Lsx7?)2OKx;u*B^CBUyC%1y%@&N)of<ASR9cS)l?ehT#^wYxtRL7K%4qBh>5pg z*t;T$bQPa0R4`03pzz?19oL3j?z*Z{D(<BiFj|+)qQh1uSuap(qlhTLzHRn28CBm- zIjHn8zeWREtV`AKG~LdTiC3kJ2!jNH400SOq1}uo4xv%)s8lmw@W(MHloFfq)7=Eg zXUe~`Qy_<Z6F`znk`a58P*MNL-rQY<zew9uz~tiLs5DxWum)k-QW&xp;!GEI-#mU8 z&m<vYz}?xO<4NI!sKZDeiuen9pf|2Kt{u*+Gw4A{x=_1%61t?Y^CC!i6_pHR3=5uD zg2KniOKw2oAqHN6^7{o?dB?{{d*v03Hdtocgx<}^^9MxOpTZ<BNG0t>;`RdF%TwX6 z5N-ifm@SV+piWUEN&#d60rf)GQZkjn&rIgx7u7vu6D`k7|Gl!9T6K9{{Zo=SvZbdr z3bLvA7!@YbBnOkazY4^6M}D+?U4%qH6r|jijKLdf|1u!js4B)-$mW|^GO6tFJY27t zd3MF%ivl{pm3KGpDSu8#bIAl(z1%~TfrKcxFn{%vf)vu-l-^1Q&=f&|9sq3+S=A(u z>_-Hr^J$l<ieT^o9WV*NY!;~iOEad8X!*ehfCZa6<~%_bU6Bt1eITH3(-(Bq1=5jK zk@W)e;r^2Nrl;?Z(<?d!(zOTpok(bhOESV-C)lS8S*B5Nud5Zn9c{^fmzhF&xCZn7 z-03Tn1sa0W|80f69kRM+Jy;Oh0=3>XtHk(|x4wow#DJ1ld~n>tvR~AIW9^o~t(b2~ zqk(7RtpNV11>83brk^YcWwd+TbZ{crSQgD3=g|)sA|n#dQRZedQ7CsR#fb_wZ5E8W z@dpq4Ow0X$R@5@8tw_dl3f`v6-)rRoV6g6hgHNTbx%0=bMSY1_Qbk^Rbzvm={@K2V zjL_&<*^TJq!Wkkr?WCZg_NcNGa^lYpw<F=aBE;4i6dcRHZlyvoc7}yRHo1Vo_@0Kk zf{AU<gnr-J*l)7AVR~@0TcB$L=nh-pFPRVfHXR3&#&VsAn`iFMWu@YeYqeEj#1{<w zboW{tQ#oZKBWth9Pk|m)(|e$4h}+^wf9WSmkzh8IF@<uKMlt-4^D6eMIi(Gj0}7pb z_vxL(A!?tL0M2dLmut0q&fQN@QQRPuC%>B{XG`+?&f2UcO6S-&-okPT^tfQ??7<>( z)fos*;~-g`%>c5<9d3)X(u`x71l5JNqjF>X7+(H=Z{_z6=ykY_vVX7QeND0F+)VrO zCq|@`ApCuPZ{aX`P-SSAm5GDsA2O^LoI%yr9C$baCIUKnn|qH>tX=#J<c=dMXMP&S zR|<(h2id9xDzZvYW6P^pDpxp;W5C6YUB#ukQ~yz(`6hV+-Z9xdNrg#iZ7u`8gi$>M z?&vq#Jhz`9Om??xymCJbBJ@bWUI!!K<%h?vbWB#QI3vbLa^kOT&p{aj_4&EwL@ci# zqBf(8Mv@3cms_C;v^P^+5y8wAWrFGoW?ZZ=;^&!KLn+=f@fM;*9TH-|VL`UL!;~#5 z#eNhOCdoZu%%lSh3<i-g7WlVqSJ5xO*radrtA7mf4V{lL+`Iz-N#`NKp0y6Re~)DA z`*oq!<63tum16UZQf_!kO&>@ll<(_*+kNULg>+ZLMNuL)l?Y^Om%p^AXe`7YI}qni zz4sZKLW~L_mEmY+pqq%t!YOMR{7FyiXq~cp`X=kalE^JkJD9WI{Hdv1mA@ir)c~}t zm<vFZ`-Sy4IRhrhoIsH7rpI2~?0`!OdZktQ<%7j5*Uf;Df1{@z>=c2>@(4(+mv_~T zYEGd7>bNE|7{9_GaRynqf9~|x8DLX<PAOr&TlGAqj;(xIdDYwU^Vv?zwREK^3s;~0 z`#u;>4vT_*21l)T&;8hchOC}1p!(A*Qn64-+u$$=n3V$a%GG02|JUo%l>EB7k{NAn zx9*(+YDJo`ocwhNjPC&5-nkV^@{ii0likJ$CBt^aMSCa*<tq@HbrW0Wzq#P$>3H@L zim2T-ruYQfCav}8P@80{yElVo!N`n1?(5G!1MRD2hwdGT_!*&#WuVH_(Yhpf;24|V z_Fh7feX>iR-0ZuThI+2NpaA{Hp8lF2^ONtJ&3KN2Lslcg5Z}we+=f3r(XV-av^Ivz z3Bo!5(Z;Yw+m<|^MH?OYxis1-`>?x+|JzCbB0IsD8J#%SaJy(&zH0<RPx2+l0q`%k zt)79DA=bza-zjV6wOFig=Ce-Ie|^k=eQ*E50C?6vZq5$eLa!Y!IgR?!%WwzG;xa8a zF4rm7mcKiso6!BGB{o(j)-{eXswDP~77i~uw`}c`00@J3@ckE{rcm-akMGt5C`;M_ zp<N>Q>M|&E_JldGfqsiWcBt>-AzBYacv(@@b_eK-@Wq+#1A|#AE%K?P0VpC=Wd%jI z9^V3&O_sTN)jTSC#s~2M@z4^Un#P}=CHy9LbP}zJK7sy#zJ$i6^JrSAQ)9=l8`^N$ zhZ`Q6@<kOo$dznsw|m7)iQn#aXcr{79DpKTAVLAL=`yKL+mw&R1iX2el53kl#x=OI z50GiDS8olXe2@J$7@r9jMlea)0tc<iD+<HVdcOaNS%(Yk4W#t7wc}X4Iuj*}CR=UZ zp6QkB=<awKJeX1KK$IVALMsGYaLc3)8?=?pSh#8_sw)bK9z7Z649^6NPLkvNjm|3+ z?|wvp#0gZI6fV_9_}O93lcQqEqPAmSp52LNEPgty(D(>#j>e@qm4kVy=u;`mVVX`k zC=Sncxl(ru>0kvqD;=Mv?+O;@{LZ=B`Oc<Vh0%ylP|hJ5Y%~KkeQaao6q<*;)eKSo z_G}L*hUQ538DJ#ggpM%ZwNzhIRa*0Q?r&%T`ftBpDdf~nWXtvoeb_FE?ErP!BWn7L z?`Z3byGR#cIeDq>t_{Fp;>VE6Z^U$f{AW%beMv%8Ff8JRy0YOZC^ut>#Vb;oHVXk? z(Bm9AU26KrV7t-_vibhbRnrCkkFfU)YbtBsw=Lsf1IGf6(o{f1+8_wh5*3va1qBHm zl->eLF9vLgg7hXeqYzQ)5Q20YO@zRvClI8DP(lkOq4-}3>NxZK-s9zyBZrf<_s(AH zF4uitCJKN3J(3}bMPr3>>;Y+OKA!iRi7f{Hsc_^IjKU2P*?0hryXI#|e6^C^k%7R9 zOZ*iWgfh}HwouY%=F)}AJ;j~uJz4L6(TQOK3#Tz1u%ul5N8NBk3`y_tgMYo!Ibh!J z0p{$|tGt`3#7KBn_@C}7B6|GPW^A3mP2Vin?Bz4JOBZf2MKVTkRs}(A=><nr>oG#* z21f5p0n$JyFjpV9J|6%*=v+kf+a088nOv{Xn;%k^6$=bMBP156J*jsrFwNTLl1og$ z=vwnJ$^M=y9Nm$++2Li}38Pwh?YPBgsi^fn@O27RaI(L`T6Wv$Dg#LFn!*&w%i-P? zR^#ojSyE#&@4k^=_HCcO5B}JTZ4of$Sc51=1<j<h#2KL1=E%GAHh6Hie(9JZ?zoTf zORh9xvJ(2cU#9u$f<ldkMB_r3x2r@HJmTdrfiX||l;U;9=BB%FufQ(J2Cj&EtG-`Z zfV5~^qu(l7H!|TkLR1SL4-=^@E<&qOw^R30e`|bU;lgVW)f^8yo_efL80|IK_8jD4 zo0yqRAY}(<HQBkSDIO@DSu)aYpYN@{niV^VFrat~toXLR0(8<zPT2*u+y<sHKtUZ~ zcHz{&zj~k_w1?W`wk#QR+M2N6G5KUi%om>>;RA-wCdUE=Liw$Qsiueaxf5}J_`Frt zSemE!lxeT4+yc|Ave|RBnvf@6zz0r(<S1ZkmZl;)xh9=^w87Rz3W-^cPmqss$uHzh zHX$HH0~B$r%wnCTdj$R#to*|qs2EwIDDJSOpe2NB`V#P1xb%-IawZsF@m&=Oa+ImA z{|PvRmafDV7b>Q}m!w*v5GXy?h--miwi1uYjTA$&uS6$sbvRG0qaGSQK8l+)RCb&B zo8)6}bxUfFa!>C_AQ?g~!dzU1E69bNnoSXTA^@-MH3iQ%;M6W2gg6jIQzH*tsdOWf z<#>6<#|#myCu+t5YH<R!bGpvTyd8n1-3F?BQ@-zkS`GoEkAs4rR$dI;Tl)9mgj8L) zGQ{ykF<#y~dTe7J*YcU-zQz#nmx*w7W6P7Ul)U86qlAyCE<=5pyfo9pjQJa4fGrsP zD4X`_Hl!Lq;?l9YY#a^ONqRM$otZsTPs3L*VvqyA$yYCqNuqEE5#?IaMc#V_B>M86 zmw+DP7zRX>0@we2Zh_=NZkxr4XA>eps;ns>R`eKD_C&qWC{W0L_C9nwz4F+YaVI>h zTuzQL|4vNro9`Yf(#c;QUIpfx(~2i~rx5r*n170&pR+*>Z6)`;)$!9P>kK(B=$iFO zu%o4%b$9msPfpXZuitvxM-U_XZM)gD|D|QxA#M9QJ#+PE)$8;2wC%>JDvGyfIws&8 zqu#nstj7aRz#6El99x+zXaUp;RH!azw6-fld1~SQLCq|Zx^#(ti(qV(5V}z-_D)}! zsxbPR8V4)y5d5FK18}W0wJtW4I(b^Z0X!MgEvmiZ&n21b@1I^*oNWii^Bb@BruU@^ zfuirR^WQ(a@dITdyX8U~F$SJ@q%!bD+N1SjYno-PD`A(CECsI=<`M7-d#ajvF1jAc zk<L-L_QKlUm9@L5{ZE<&#*C#bm@59-Zy!|aEU<AYmuu|hOwS5UwXHIWqCb!e=nDIe zhpR|t@`vW+acTKJ+&WXgW%BEm<VK9TnoI!bsTjvKVD`jSIc5cxxZF6~Xmr$O`T)hy z|AOB&zst;Qn^wUn@_~u@;ydVd+s5bzFjuKF`PhuG?8$jd2AnvOcT)1EV2&`le%y`E zmG>jEt)-k5!Tz5Q>6LaYUz-`RbiS5_HFO7uiM^Ibirx&*hfk(*vkUhJ>J?=E4u4o+ zC8qxPw;G4O(YkOx2cbTWCw%gTXUtB3Vzl68Fsf0H8FDq-T{7<U=HN}BA~B#kIvsLK zjwsx>-;U(8>{#+5sI~+__(ar;_ZK|kJESU%B}8NsR@~`|`Ry}{h5K483iW<N#%tqd zd{>%7#@@+sR)Qhvvmmil20_m+Aq^4$660k9!@aVO`lq$j<6b|rw$1L7On{5W=hY7N zE>q`*39~M<4?gX>nsDOpbL+i+EPf*HWw97_h3|$<q;$#KVy{q=+hB2JR1L8f*=|__ z%!dDJdgGYgRk<>V<oDwSomxZhZ#8l_P#?Rye)NCR%<$e4$-{~A+zDs5?s{&&o>GTI zYV=6|GKRZRU}HX7?P0+V|2g*AB`E-kk$72i>?NDo^4|R25@10~L|tNWPJtNgKRNr) zf}6SY&fk7V0FdVnak+wc-1F1Z5oIxl50P$wz_LXL5cB~#3Ik^}=ztj^i!~1B2*}tL zY4Cp+R(=g((^*`0R$U0_L+Je8y|+b~_2mN!{dWM_^4DU_&wq1cjooplw`Cg@g#!%+ zuWQBZo2*==gHkCzgHKq8)YG3`jDO01Om=U*MTeypUY+>}pSib(Z-;lq3g8F+jR9ZE zjnVvn>U^Jv2_(R{T+-~)6h-)J$sYc*$J*f_)ew+U1f#uTUdE3Xxn~o0a_&B}4XiUD z>9kYl&Cy$Lhu~Yl<)Hr&^B#VD&yJ8Pc*@(Wil(}<Fv>zZS{@4|dk`-i3cI44wA7je zML$P}N2kT+79J@(8k5nb37R7v1jG4epJbfP3G+p!GqI1NEQZdVqPYXUUfN-0hZi+i z{VA^OPV|12P)+fkMg4NP@i}94WB>PJtQV{;MbTa0tg;W`!-B`A{8ub(#dpDnTE7d3 z@sb4-q9i$Po@U6l@PHT1tj#>cZm4Nx?C`D|TRAkA5SfT%1^H}A5NnoWhm>WOji99r z6XylD7K-V_e5*D_RvAt1p%z`##Y`hgw5C5RL>qL+nWKh$ZI;x<H8`{=r0x%bQ!aa# zB=M(Gz{A+IiSwVT8X&*}qeJ&In&y8<v+zAR-ZW3Bk`2y$R*#8DeHo)PB1Ve~xH&~` zj*r2vVQ)PNSIwA^jOZ&XxH)CDcPS3iPL-UFwbg`2hc`~TCoC{D>>9~bbT~mFI!>~D z{RKTAcWp^MOEW>sKqJ`r^3;zQGIenHNnbGXf0_s*EhPux_q4SV*66;pNxA^w+5d-& zZ25#{^ZaUwmtb_jiPWQOCU%WZ8G0H0nu0O$@#X^K^N+4#VsZ!<Q(<++7}@fb6l*k$ zOpQTB#~muY!c1IJ2Al%B@{;K+EJsEn@`d#w(iwdsqU-|GyAe|<P0oIP`hU9Oiu9=( zXyoAnAs$BZnzQ@c416K|dvu4zlfPheiXJbgTwSk-=Pq9^=DtI&pEJ)RfF}c1v1Edo zP(o`L!zi`P)z9&_T-zJMWGi~fH+){ut*CmCi84tcHat=wN_+cAH=y^LoDT@`h~ZrL zjk9S(f%8k{exyYqxw=+S0B$l`al{Sa=!n>}>na~lx~5oDX)K7c)kh`cBrDJ4B@lV( zmKpkyUrd*n9KVCJ`CyLm_GUV__SuD0o|GX|^dNV9>vT+=Ih2si-`!J~>QTyX{jE8E z1n}Q^ojDgrJLjP%7F;Nnu6xtnU&IripS#9qgOT){VZzyRfN(Cs#Z|J|$|c#Jy07)L zqdM`$b;%Ejm+-e8GYQR56Y?UXLOWOpb=?X%XX)*~WRV6_7Fl3KFC4<3K?mKjB7ewT z<5+xi&NZ@8^Z$yoa%go4a&%+x4g+8o%ZK5+HjxXh$0%?+KN9w2&*1b4(BvS#0QW-k zFlhhOX)YPQDA#|jN3%?v@y@V2KjjY^VJ@jKJ?9;>SD=_wt`d`)QA##xRQ}mhSc%tC zX+b&RBJ@gfAV80{9SvO&u~W4X&+;y@3V=?kxbA<my%M{v`DaX}GQ0SZ9aI6H$uDXG zx3Of2oN;$ily=lx^$n=|XE1*9aSPc*twv_2Z}GOGOk?Wk->J5|7QEx~J<;P<%KR`# zr-(q;X;o8w<6~GtVkc#e22-wMewm`h)EVQgng74>6@U@{(vLbyyAme=19imRI13iq z8DTLUzv$v@h<Io|zT~#zr!1biimTlD7nx#{3QI7=#JJHFOTR|GBn^)DKp>(*^(|b4 z##8r7NuyhMJOlp|PyPFP0aaBZXVhJ3+;!8GE(p=She>KLO)ievOio}?iL-TBO!tcs zR18zX1}znRDVso2LL;fPqI0^K6l5eBeoaR$FlycUv?{sN7d;@n!gTg$d?h&xlb>`Z zbS9s;b_%Bea(*BJ`$rA|U^aarnZV%VED7XHtU%}-tuu_%X)B^s2Oo0ipoRg$+i<wN z2xmM3Q}A4Ba1aYEggXq(3r@{FnBy1M6f7*`t0UFscgWGD{*Uie`SPs${cMlK)kF3P zzcQS)E~lXK2At|IA)5!Co*z75E;7|^<jO}^EG#E<l&)NsRL-x={*9jCEa`E>CTpi# z1rEK`bGpFMZw$OB;0o-2kxcM0y+DEg_p@@}n|@3fhvA{&MoAY`J;XDfI~|tS)|s!c zL#i{25Icz8nP{tjx&m)$KQxHkZ5`LW{q$_(|Ivw5q@(t-W#OQ<9FdbTuO#xfPW)o5 zt(@%JdtcYgK=}`>qUoQ;!q3Bdqh^(_)u>}wUcb*FV`J0#NA~xx0~lfW{7G>JXO3@R zdun@q_wO6%^8b)HejvCn?cKQae|Q=HX!It2u=0S4{C_42uYUXA5&R!@vG`F0sEZZb zhIL<6KPgyOJ=}Wu()H?Ao`{?s>8DlOoQI(5j6kh#W32_3*DESLN<A<hsUB<!3jJ)G zq$EmWN{atDN;0SOofz|fREwOS-hKD4@Wy1PZMzOY#lN2cpyK4eY}I!eQ(?D<#1ws7 zP5r)bal?K7O8cZ17JJwo2nmblF$MrE(&n(=MowPSfvoPNg?O~6$hNw;KSq?40yCgT zQ78F@(dNwO9*^j*oGDq-AS?hc?>~qXq|97c66h$Z7;0<8n<Rn`5ooCO9YtBDBxmaM zYDfqRO8WfPe@mCL>~n0#jJ+=A{F5~eXz!rHz133l^`Y=@?rI@VRvEdhMWnG7(Pj7> z|CzI87D{HsihHwpC-@x)@ZKSf8Fk>8q)7BK=2=7L2f-rl+WG_%S#9DCupvkbU$MG; zLelk#l%~X<J_4R)S_9Z7o|5+jrknTGMMKpp=zS4<+V$#ci44Q2-Lh57il^=l7*_E0 zpE8!{NIAQn@(Rvyr>!V%SSuLSP89oNEey*`ibkv*0>w;USnZ+uQB}l4uW4M>wF+!Z z{CFHut}z`+K2d2#G*Hs@OYkV7S9rL{GUnZ&cqkn3)JAyE1aw3A7yhDDRmcQelp&1} z%;()ln?GryUscWt)aaqm0CXu4ZCl5T%}?}5@kqj%*$=rbBBqV_ESvmydK;F%Dzbq) zP-vwrNY<uz$3C!Ub6mHiywmwR{hGVUyxnQ!HYJ_nkTmpQDCQ%;<<8a+K5E(tQmc5M zB+mF0e}YNcak=i1KA@v=%}3ws`Cq1r;{ocA5-N!*6<^Nu$_A{q(jEW~v{iw1RmidZ z%EsS(;nZ_ZE7<9xP!Fu6Hu?3}cgIPgyWmb)N&P1z_cQG|smH07hzFSu@t7X#b(N;` z?ekO1CWr|QaRfr{){D0vGt@KEb3SM$J;(@5fOTgPK2|b^XMd-rFS>G)UM}@C3zT({ zjiyXl7qn^jCN|Bga>uPLh@^u_3xqf2J3Wr*$Ps~zWW>$_C>E=heT79ZyZ4CAE^{9| z3Hl8~S?NOi8lN55XR*M~u({RngtD_AcLTWA!?bqB4>@=ZmcEhLE+}mnm=3nX1i8jz zV}LDT$#V`Ptt!sn&!3p<dKxQ@;|dMJD<r{JieE0_G*(GKBLc{GhtFK=<;bYR?$ONC zo_2q=ZK1CFKIJLQV!A^#q6sxSFDhF!GBx$w!U2)TejbLO*zPFfSMFM^`n41+mx9XH zVZ$w{q8U>?nUslbER7}hPpBCt5aM1J&3vj~ZU)+^!k5E?akE9DT&GNy5385!95%lt za7T`Bf^WCO8M(<@j{JmIANis1{Sl#At3~xbOHE&{A7QcY6ttsrV_b^3WVJY_|1e?t zhe>)a<~VUH3gj;<ya1c%nH3uJ1Yfx14qX<vYxTGoz6XFq_EJxSs5XC)B-s4rRps-5 zECY;+xkJQ|6|~Lk3x7tj6`Fk1%xS8xqj?+adA!@S;Y*RcNj(Egh+5in-19^_{<ZEj zzz*gGG`3|@m>nrVZL7<b$U}P6==AiHC3FL!#+diXYo3LvPB?rD3(CEny&@m}h^B9e zjcTQ})gY`hQ>A3SMNqoeQXU@N2HY(qF?V{;w@&0(&SdBc^<HAe(j#;F7N%@((=Sh} zduO}Xu(I6vj!R_WcKO0vo{rh`+8`X_qh8~EuF!lmt7LUfH?!FbN8c*$J4>X))V2Bx zf(8#ATHwf-UL239I|cpjg_(|~MQO7t3q|Q34~mzrD<5QC-=?h_{w0W+<obwbdW9po zz!F0@Xl&njiX>~VXoy-FnT|=71R|a`vRZ;DkbDh1ZaqFvnY>6mly^#ER_nsIDu%^V z@8(lHWw?6F$(bsL5#@b0!`-vkzFCp}iwoIlsTm-wYnbcioVw__)V;z{a`JTZA>`V! zC`3(_RM)U5(5;=QQ3AMT??Qz?1JwPFw^xbwIZ7)$eP(G;QtnYokEP=}w)VU#*Y-3E zFVIV|mlnC~9&6JsYHiyt7#q-?r6Z76ROc78jW_{BwT&D?Uhyut#VSV%ivYOk#wIpk z3Pc?Z(OED%dXCV&Tz5PGG5HCrOFmXX$L9IC0uk2j*`m3Q{_RV<KXkvGfZI7|1AgNv z#z6DMFwgKmerr9nP3G`t%+NtYdPm4W+vx;2$722}!0e@%ey}#tTH_A&Eh+i@(N1fr zr&g?>nR}jM07BtREy_cp19GddKzG$=Ege%wr@KJsc+-gfrl}%o#*kWv{9@fkht+Ao z$K$REqIThnR)%L6`KEb#YdVAbEw{b<^`!zpnI|C+3C~qea<rV*c?P=tPP;Ml5&_6? z&^DZPzZJ5)u=rGU{vr7g5L6aR=q*La5=*=Pp1iaSF)P*;1LC2*9?kcHK*;4?u&>1% z;h(@i99cO|LsCzgY+KtwJtlsRuPc~ISTCb-N;IxTODfVnhHi&Di@(z;2&!`kFFxHZ zYPYCZi}bKtYOu2Ne~I~gCv!L#xwL}cN#JMQ>AUwfkXrG}$2Ia8DbM2=?r|b5o*j1< zM~qgp`L5j}4%%6$SWF$7;mXV?Wau|wvM{QDk$n+2e2V8amVWzFr>xRS6HEvX6QYK! zDTJz!gQS)fj;;Pi%Xd<@MUVK1s$4B=Aiwvn_IQL#%?S;kP+PAEic4F6X;!>cV}kX} zh)XtF<U6Cyd@cE<xjqaYE1fPt1zQzL;!c&6J8IqqqU22J{d=b^{-ki+j$P2JyT64m z&O*)bTZ)*O(XrcMPETN;E0>J`n)zuBVW3Y4;VUGxds@KbgxMXn4j?)V5mrB7c7UHx zw1TL(uRFZfrQY5-PX(0NoWBee3_Y#oI;9KLQ)5hu8a9s@GLq96e#^nZYL|cDadiLZ zgF4g0m7w$&uBKdkN+8NSRv-rEWJFhwCWjg%1?Hw>br2Mj*{~9g#xC#Ge4A{jesjDc z<{0o26K{%_Drki3`lT<-u6tW#HQtWy5N4z{;SiHof}Wsh#W0IWn%)Oq=cCL%WRh}| zGRkH-)ys?ZfHv{m&i!uF7ApuBeJp_ruMWufWA<KHS1~?0yX$_Bk9d1s0zYr~OF_|n z{C3g-i!~8{Xx^=};y)Q*{puN9G`#eJc5?g<b=sZPIU(;Ol%&N^D||rTC;djN-D3DA zKyaI3vvO>*Q7|n(Qzg=tj+2X1)_oig<#X)^=BN5xchgC%B4MOo#fO(hN5}M%^6&$R zjzZPV=8u;7O_ryMT}@UV)wHe{Gn}Ra^P;M_odPgxa|>cO^{76L1rgfQML8Y?#eG_- z>{t8lxj{C=Es5dPm<(6nGIqF-&G_5*+#-zOPN*RO=}cNEX6wLXz<jFboz+S}hd-^> zTF>sja^jk>uQ1-K+5IBz?DM3P1Ff|auAlmI4M$MV7@~Kdj1u%RPUl?F?5Aupc{@?9 zn!j@z2i)IeaJO$eh&Z5Jtqbr4xBzcT$g2Al*DB&8I~iVvF?6W_|6J}Pt=4j}+KCwN zlYCRXzAf`%j`O*dROCUCra5T5^VBF1TY{g^?d)@&HIM^@e1Jfmi-=0vVKgTZP`fE> zdHuZ#KDv1#_Abnb*k-9C@l+nS0M#K9dXna4#oMp5w}l%~?2Bhd)j-@=Ks)Ea5Qp1| zzg^^h&|q<UO`3{<;C^(;UmMyYkl~*wJFJR8T-9;3HXtB(EJU)GV|d~xh0oD(^eHko z;Hq}1?!MbY5&@46xt?OR)t#}zt4Vv*pp3$yhbE0CViBC#IW`f+R3%~d|6%v<tPA>A zs=@yIO`&K0{R_iy6&lICmFvDcCs^V0rcL#AtQhW}e*ZXJ8p0>!mIN<fq4GG`Ih^iN z+t|pTvyG^}rxBocqktrse*EoQe7t|qpuJ#!;+aBwIP+WlI#1t!JMP!I{!s3WTa46> zZl>ZsW|SCK4hE%q?@-oMN7xxDBZ*f+RPJdmo_u!;;~hWV)^-WH=Y`3`bND4*Y++x- z-=gfN^>c10mndEGM)p&O|L+{!jQR6NC4bf)iI0#kZZ@>Q)HQXq42=Hhi=3KV*3pEQ zWG;#WhoVepl}0%)2xh457Zz069~t00MS`aAckeiQW3tLt?!YWCB@dYg=H#h|O}3-& z*bnW4#>Zt8I-}#IyrtPIF?{yJf36QuG8EuaX_DS{1Y2@SBDaqDM`5E__xkn5?TJ9c zEPH+wFucx52)Yi1rMANZUI2d<kXgJRk`<fUfjHi^d&>Q;N3};8&Q~_!tM3DBFVF}{ zRg&Wk`;V<%P-?a$1a&2&B$vz}b>+P@2WV+>+-uK*VtF~?bpgzEoUVAZow5SuJck82 zi<&veF6Os@={y8*+iDYQO6JAHbV~nc#h0qCZ2%Y|WxeehQzOfqCMFe8^%$cqeLBMg zR5PejF6v@K|H(1F(LQkb8@7I(&&b&oj$&<{8kJjfyVqJ-HDmr%?&d75WGyFe@?!-v zB?~6D=DDk+545{c)5MrNv`T-`2SeXxQc{7iYs>|~>>f!J7qi#Z;Z{rC${^Q-`+2)Y ze|Nf=wX%5CtfIqo%cbe(liY9ayJbqMe=9ZnpqN^EJF=#oeaj^r*%VihQ?Z1LX_^KW zG(J7RI}{J$n+WIGpWZ$|o0Kts;8zh7tbV@n?W{TFbB}0~y{$-C)KwR_K&ZaZsV&`K zj|>3q<f6mTLzKfiILXyhRs}ly^W=uk(dAN<9R;o&My*1}(sv5_N_aJVi)QJhnO2!P zz$Zzaxk0aVLwK)I)-pJ9rV?O8GYLk;m+?Ojp6W3-T{fc1P{aD-<T@i=qNVV1K3Y(f zVBxlsF5=$tL9?Z!@y-}0Bc>Acna5iJu-es;xs0$>$-H>&*Z?6kG{;B~UGUY<BxEX~ zVfN@|8qNJa-T9Ty(SY?k*tMbaNlPB1wMVz@;bPs2cVBO_X(Oqd>kNr}T**WCJj})u zMFB4}+%A81^_K8!9m{o<!xQ`C|D=R-PsaeXWwF2&rVX)J9e`_w_(MKp;C1Q(iNDXD zDfx80ArUUB{k&c%8RL-vrbXZ-&0u&X%ZHt#6n_4mqqxdYXIa-)k^~(z4z7t_RJ{UD zKpeE+)5z4gA;kYq=eTIU82{1A7ga-bslsdI_;8NW*(Cho)q@Zx{>+_26S9upV!d|o ziFw6|qU@U1C+GlyalLvkh#T25^p5_+8uT~zGhWDiXSS-#JFu*X6S)qoA<mS6P+u-N zEHoq3DskYstFV|AUj%BmXyw4r(@*%_2Pb1B3+4SQRuZhl?m2o{_7<&QvR+!&AMOHw z7=HA$u2%jq!do42C5{~ysH9W($fz{$+w*~d`F3&*S2R+7agG9tsEfkD`%`}6FQIt| z;yb2lc^d0I>1@<>s+&V%J<Q}Bu?q<cJm;5*GkzUoYuKfAKc!pjtc;#gML`IkV7~V@ zveh=ZJFfURLOTAozrX)i4ri?QTS9V%jv>Zh86B=conN_%Ip2vd6I3wT9S}lyad=<| z`l{?N_ZD_Q0Em4avvftnbrsRY7ax!nfh`99++#k=iGK#a?C7t56(<wjepFXn2sog8 zcuif^ekJf!R_0O8Gk64r)~^Sm=kjkpQ1P%)178$=RXHHHe)rS5KE_rCV45wJ;kiML zITm(Y)x|Zn+?;qhDb`BmHpwvTad3v3vWZvG8NZiH>B^nHN!)kV?~9Ow4_c(CTr@@y zU(H9us!`UrC)y1usgwMH?iuQ+hvYNCA?<}TgyNf{rCzwFOUlr;R4$N1M6XMrTalJJ z2&ycJ`2`OXH-7G1O$ef*cN#UHyk}}dSkesrR1&tpwocr%>Bxqs;hzj!4Y7GX3BLe` zA1;7h>@GT2XmH|_S=UQz6uH?gyPh~%`Y$#JZBKdNNO<23>9zn=yQMAp>bgpNsZ6=8 z#!+9O5B(VaX^^&RH=PLg7H63Vs(7hU&zSi7r{VOgj$Zr{$rTfDES22j_K?o)AJgXt zrsKL%6+Ju}dDh&rJ9`=y*TU(SU!ir%^!*I7=MR*Z^#Q+zOy_&EK|DvK_rqPH!GIoS zVx^CgBvJVuX$0?~&iEo00;T(0oSr3=z`of|L_UCddob_7Iw_>*Fxi|74HVQB&(<1} zYvIxkvdsjkGI{26h7f3~vmX2(8@5V_J9;&5VBUfInvxC*w{UMAQ?f%Wh_uWSYX<J# zc0LMFAO5F^hcW^m4$#j<!|N8ZtD`!PR#kE`+;8k@yzW};i5Izy$F^G(JoEN<aHn3T z!boRC+MA@yZzty5A;ZOznuqkE_t0ye+~23<5LYdd+Zng0x}i6xi`{t25m}=FLIcNn zo{OeAwOuV4!KPxZl=xvMQ)R9__J6Tj=$$K)Ll8zZKY)oEBEOkrm8P~*aE6#wuPK$b z%C?n%U&+opdKtk4l5p4Xm^13ydiG9W%V2feLS-OZA+S03U1X+?fKcktQ}6RPswZnT z{P2o50B%l~_sJZe<5A;peBCu#XZuqV^=)|zckU@MejnT>Nv*8!?EU>^_uzP5w~<zC z--%BaU6uDdaB&}&&&5a|Gd*^_Wyof60S{&7jMcqXWTwRTPzGtRph*WOVqQt0sRny& z6^zzwWY}UeSE5s-gM~Xs>YrxM1L*>Qo2v4VWOCLoSymaJ2yC9;S>cw~5Xwt?s`w{l zFB+<i(Bn8Bhy?t6gKY#btSGt`^WL!P6#o-uBz)SYV8#<~kLR0y$YER@B8pu>ZJzPM zODW|S#aRY?hMm0Tl^!XX?N*~O^~TP)lnPQKcWHkq>$t1uBCrzlG>5zg6(4A4TkM8t zu!8{nP+3kWTwI7wg~2Cidi7kuO3`T1l;vpm%Xekxogu%Mgmajynca_~0quJPYF<Wc zrPLj(yAkFQDHARdM;%Lqi#z0fy&J?F-uwE@-t77-%GzFM4_mbGzETYgm)45doo=_z zci{SyYM%V7CsIWN!!b^B@;9#w2Ws!ep#f?pSj(cAyU~QgtJ@3lV489D^cAGCrJpz1 zA4hkhR%b{DI~t`pH+nR34{G32xYy1Qkq0rZyK?$<E8N_UPMG)wMw>MQyg9OjVT+gx zK944MQQZTyFbmPlUZ^iKQo-c@8n^gZ6l*3A{M=>RrvP0WZ-;Npjmws$6sfp2%JDf$ z>tF|(J7nj66O~(B#!nUq<HFckc_eT~8`9JlJ9TPc@~&LLtHQuQM*=3!L+aaA#d$kV zDL5JYXInG(A=Y5=Gv|$C+^=B%8W@`}*d?3SY)ZNlOMmNuk8{bj?AK27Jv*5$RNg;G zDRDI#TZ?xT<xIA{HZB&XPkKzc%DjtRdVkT($|l8Nj5ZWT85l%+(ZI8@MZO)9$x=_X z4Q}o|VX(x@zKmb;AYj98I3w@@7tzQ9itkcU*E`=_f4KctNtEsaMo3jiRI*i+WawNs zxp#551|YGz1M>jN$t1YAScCM*Krw1-hVuUEl$6?&!{1XN`1)pOvYE6s>zVC@PbJ=R zGCgj}Gaw58yyJ1&^{I@Tp(eK@sH`=c5Sxnw#$K$NR2ptY@9e2HuQ=lz`mXIV?Mv8e z8v;9ofA?;qnijQ!zsP2$j=5brNy$3PFW-})9N26nPOZ@1VPAc`_Nndf!7ot~{MO=N zY>!qHeS}mdu#a`An|5vcnN9%G=%Z5u^+e(gky{H2y_-AO>~pb4KiKCym)70yK#s}1 zQd7r%m~U^AIKV#XS<Mq*{c|b#Nl=|-9N)fOuuW(K76n~PCfjD4j6Cijxx;Y(*0lox z;Z7#oBG%iFZX{hdDXfh1dly7ps(>!@)flvz*h{;y_t#$nTl)#jwXL1k*zXX}Y1Tpe z4=Lg5w?n79tIEUaF6~k5jBvNo&+CeNS$7LPk`NrTQ@Na5kZ_(J|8W4>DY}C;{B|Ph z`Vtt>muCc4-%tbXLH}Qk!=w7Te#vn(8V^nv`FmqNTA_J#5t_W3)6wCPcs%#0WJ!TX zq(=zwz1~LM=^uBLz4onaANYSH#r_`KlNIc2gZ3Mw9`$4y0F{~p>n9<CcjO!eu1U~w z2C@Q{uvq@)4`K1x5%nIeE+8zHx~WWcq>51~i+=}-07K>2RHwwNn5^-!7}O32&V{N) zYz7t^hh0z;%&{^V&pB1_4EKVQS`6KTP*6lhQHDaNU;L%YD`lO?bC^GfV|~~T|2|6b z<Z<?W%+KFAxE}k*0L`=XQDnGv3kpnX^zR$1mr11%ZVv4-S?`q>YWfl*zg#&&P%!){ z55|c)Uz-4~+<PKv3EBzr(w^fA#`o6(c12o9SDKXR19z00p~uj!V|3s0g&w`K8YW*t z4`oyvV=%(o5b1#}%w02q7I;p(3Zu_59mmp@QMc#BwfgSK>7lr1<M0oc-Kcw45(?)J zg6a5^)KD+?Em;}~S`nH36jy|TQN<qCZGQJ*qhBHE5)OpfA06iJzbf_4b>`pSsdexg z+eOmjPsaS+Lk?}0lYXlEKeKZp?q71EjlK)QhEN3kA(HJl;s2nd{YuH>g#<_hGEqaz zOG0+HC*0F=?sF|Q$m<hDufHFnH5c~_mMwmqIu%hgEtH2wmc8qAg&#pT3=XEecDSlL zw1&T><m~Gp>Y(13*e^9D&hMZK7hOw8&3&@!dx+ZP1(gsvvl~egiq)+y&Nm9_RW0bM zEO(6H_CCr3iI?mz?~R)qmA?baqXVKXs?j4#z}^tJ)2%?APgfOn8;(v@%=>%tHhJ?| zfH|BzzEerQuimz1RMzUz&Mta}Exoz9&pcR#XFUGdZgr)n`r8MB5q*h4AM(@|6h8d) z8LBGpKHS$RaXP0a7@LWTTi~LiVb<u}rb+kgk#Qi7h&^0up6Ueu3)fn%5Uf=s*#jdZ zk<uclBj_*qUg=7O{`aCrrO{caLo><c;tzKlr3F6eBXFN5>7Y&prdcNVRuz|Y8fXur z<YjVkBV!KazEVQ4K8#)2+?2afL%vj1X@pAwH02Pl>)M!!&lo3*EvfPFh}yXhA3{_t zY+xWv#Is&Q9gMQz+_|G=!EApN{~>*F9FS$*JZHI{^vz|h35ppHE<r{6zgd8mJ0i*E zkQKmnP$5%?m-Lr(Smwx>`x`R@FU;;IjQMdSb7+T2@rqw#n1yXzNWblqSwe>F9RKPF ze)qC7)f>sn=y)E{8C4}_W}P@=*_Y5}x<1*JM6T4!Wk{KLs8-J1?6;K`tjJmsxb*!n z|9#`g15$^kJdV^u@UA#mR~$Tx<{=}a%(<l-xXu;OC99$g*ZI~*?DG-^vB0NKGc-8# zI1UukKDivqYy^^S%{iaR`t*Xnx`}!W$JgQqw*yb6!3h9xBdXcelQp|oB*~p~W8^r@ zi95nO2241(=PdZz<-zu3EK$W|0?q5pot9r=->W^Jnm`D~uB(AY&=#Xpe)-nZC2D3) zPW2Clrky5U!T+4-wO^k!A?-w`+*nA2+l7`zyh27<p~Q=C4_$CbcrsgE*BPSz@9TQh ztzbr`mwvaT^h-D^YMc3F^W-gWN~^Bs@~z_4Qp*{05Nrt!*n-wz*g%#>1-W2ngwNN0 z_;T?v#(aFd4$LL=9?NGuX`lY(qF3{q5k-3<^e=KPG0tb|46dwyK)<Qj{};Fl9ly_7 zs?#>R9&OFT{k?E-5&GDLXdF?lG0D&&irw#;pK`uUugjiuzW};701tzEURfYx&uer+ z1$Y*5lt&6`MrdO2Hed2^He_jOA7~`|LPMOqPL<Wca#Z#nwrFD0_uj>LJvxRFgz>-7 z_`|N!>fJNIx{#7bE|vAVN$-?Mg$FxX#+vsgSFgK2-zV6!piroA+*}(F@mii8)FmKT zM1MC5A;x+0%%jCqRsNGUfhPLA@2VC}UGVNX*3*AHC1tkReWSztgPGYWkZ1(Rizm86 z7XzH7`{wzNp*yrL*Y#T&$^??%cOHd1oGy5<h(=JC9($%aZ}mx#d>HUq3l(TeG&IJ4 z)l`_SxH%)-SZ3kiYVee;Mflm)RBdp*9R7wtYEOZ6CBwUbZGueh<z4sc5MZ1iY7znS zQJLoucM>cfou3xun}8WyY8r<a?#73~fW%Atb-r%3vJT@~<<Y_`MKg>-ZT<)l)@A=O zUKD7HL10O3E5o3F!5fn!zwiKm-p3!|q*D|}G7*id0F`T3XQL%Cp6wh{9*7Eygm%W& zEPHe&_g2P3)!x-E?(R}qg+<Nj?*aRto7hQlSz&+voq_rL<9rJ>V96>s$Bno2(U}xR zU!PVU7*;^a-It1mbJY4>Y>{lh$Tlngsny=UebQ3o?`eEcoyg^aQwP4eNXuLnFPEv| zF$k<_jz)S}g~a_fyK-Hue6Kxy?ZG|j;+yv-*eprT^|#!w4P{^334-FM-E-#e@mNB9 zz>PiF&!OABONwW^?AA%Y{p%~?xGPZEtsQh$F2COO%J)NiF}Rh=SF)%0#OzZtfe2gT zSgv>=l4-JK*VL&LH;!Y4YJDLK3ecOtnf3RN_e~4#p0tUY_Jne=+LfUqWjaR8B&4nt z1*i~#oT$jSC+sXJ<TL@lmG}S=e%G3?gu-`=R``(sYUMV<DSf4P=8H@GCX74r`T^n6 z0Z5BEibBt9wUny0<}w~nCY2{5VpYE`F3L9;^)3Ciq0!j%*QSjU3%2^WH#4Q&YBTUa zdO>v}o*QJ?MSc#i#XqgVKdoEj+(Idc?V7R~u5<u{gs<m)W|jYfRKMQ38Cf4C6dY!u zVeO2arxehR1~r-j_fhfOz;HOt4IP_4s1;D17YP@16bY3se6v@CPiT!8-4T4=^QbnS zyXf5Juykc~m1&O7QLwM-BI}mV_+R?SlWTqhksz4=qJ=}G1Jyh#IHO{syoTnzb#>Iz z$YEDj#DGPpcg#1Jff>*Eg1}F(oW@g7GOA}D*dn1eGfea>XU>y_&FpoCyMGjt?rz?w zEXb_)y^J|2`WV?`e+>9dtSibIt7H3daz1iM95@WjyA^f!3+1Q@_i};#)IU5kbD*0B zdS42)dd+b>+rfnmsU6Nk23oxh4}4~Cx4!C>RlS!0I0?5F#=jIdscS|c>`WMg`@$y! zgwpz}Z0;?ZIF9Q{{n`K8eQG)cjf<jh-u3Xo{yrm+nyx4vnmqSBOm8Zo<hWT^#N;GL zf~r~XfzTeE*GQBQZ2{TJyheRUhmpK#^W_uD8+B&%D7&-rt25{8G&$Rhw;u~$$+!C0 zmPB={&(?Izri)z4>k<7drjpj$a#N_*GV#`<lMMIe?eCww83w-GPBo!`b+Y;t1Y)1& zC}PM^pQbO^d=5j^kVZ)jiJLYKF@~g;oqKi0J1BA6Ru1elU1{%DN06wUds1InriO4k zN8!7WyHTcJ0!qCgPn5Hr#p_AxAZWVed2!!%EiUZdV|WH*>qdd)UG4W}N9bd+>{5Ns z=6owK9SJ7!(@}m^`(!@8s}B4t4NfVDi;I{+oLyOv0=g;<2?=?894S+yOJfPZ%}{20 zcCezfyO-ECcGg%SXog(3*uok7Xjf-av(UHCQ$Zj4GpdQ43_Y#2FqM}GWeo+b4b_#z zXM71`CZhvhYDT<b-1NP#V$a5*{`6cb_U?F}<FiJYG;UMmv|e9b*~SYbs0hOyLB-kK z7c*Rb=eaV#$j9rSdR_36gSC`RlEc5`8)_zDT)iP9kHGu@`&z&E^Zv;y^4EQD6dd13 zZAX80bl7UHb8D1)#cHpP&!Zrzc58Oj_BZU`ISELgN)n_JXfe4l+HB$3Uxip~7`6}l zF(c>Tqe%~b-l->$Vyf5Musd#B(Q`92@;OKhDuxbb5Hyq%%2>ADps>Wwf&QU+KS>3B ziiC874VpJdty%V=_P^SPn&|t-ZEGzyF*VjSRwK3#wh<8U*yhOfoO|vaP9{_>-YEih zFVz52$k0LL#m7@SD5ncx@O&7YN-xbQ*Evcu`fUwGU2drr$>``9D$TR`wv)Y*O@r(W z2iR2Kj51UdF{5d}ati(1jPTcuvjFAheI@xs`s`(`d01KPv9WiXp*4sKjdJd`zev5h ztE5s7co-dDYwp}s0<3-&5Tkoy+0Bule&Mxt-F|~0CSNK<>Ci-*+o4@z13E!zVQMlU zptbWF2eN>);=^?R7N6?9R_M)6TJFBzc$<<Km%t|v9PvE|sQ_vj4QA#$e;-(TZ_r>j zM*Va%+do!9(%F5a9=AeV^#Q5Y0x;_5k;WZ#Lioh%g6fekH)C?n&MIdp7}Lt~JTmA~ zR9mVqwbyoz!kPr+$AXrz0gUKjQZxldmv8R^acKZbW?G&KYWwsa`AULO0chFS)hM{c zF78C7I9KmZTgh&A4?IHe-GeLIST4I`XHrvNq5wDLvTF=j=OaOJ*AfO<I{Rb43Zl3l zzr9R+{k7pZ2{8*}38K2qu2^!K?6^~aeXn<(L~uS8xR|^02lbBfdMDDy*GByEwS@GX zyR~*xFCf0SbOMJmI)r?y-)k{H7dH%V@>eFTMe1g<pWcmYL+l;sPsXAx!`&OtXU4Yt z3}YiC+4h~Li=PK?k8KE<oH~T%cL3Z=M{HG#k^~Qt3<5_G2e-ZGb47S-scYoDnqC$~ zq(c{><hGTRb|AC&!|caW{1zJWQ$2z_66otcHt<ace)N<Vzvg*{+ccirJXTsXl=U3p zuKMxr=4<~^9;MFxLEW1r#-F`x)^*ZN<;JY*g>;7dt;Igcp~}n56uGu>VT0^?nTy1_ z+}Tj%Me7q-0yz~{ZZOu?MqJeST|rYpBU58KUjFfq%JkoVu=g)88e102@(mlU%ThD= z%DVGF99@B>%lKRM?MHs|m307GZ5JW5mR~(tc8t_?tTT}uK{KR;Fy;?9NID3aIPv4c zB%)IfPgKNsgvzP=wO@K0Hd2W|uwqRI9*cg_J}LAO?8CX8ofNV;8ea&*=m0gj+v4Dd ztjQi#G4!eH5lU?BIH+JAWd}sY_xmrbAEsnDGq8qC?18fI-9#1_`~sMMj2<cA)dHez zwz|jj^C9RavSpdx950lSr@^85f2eyJqlI2}cT7o{NvVpcq884|kLT*8)|ul?dz7a) zQ@3IJ!FyGZ^rz|ypJC2l3(1q{``$f=U8lELB;s(%--~zW+3z<PeX!o4k5RVVrl3@F z=A?QH8!5xqZO@TRa@^c@#Gu3$3?xST%!$3{M^~JOV%c{oi)9!nd6$#u5MNj&|9XA^ z!t!*G#nB%M$Mi#gtJcezti|Fj8Jol%`4vPgFqJt3ekyv7R6Jj?sP!XK{C;BqOQi7W zOlgd~`nYOlUYyhi_HALQw^?47HW?$kjkq71<ed0Kji;MiPq?uOS{ub=x(JoS#^S=6 z8uFgyNJ%ao@dTM3^2P2VLh|HZYtWz6QEp%0$;|xTw)p<#07Gb+mzwNip23%hVuEbV zu+1E$5~y67c{<}|n;f-ztw$bDCp1Umi+WGz?g5jKNIzz>R|ol^Yh0(8{<NifR_Ux7 zHJje|0A^<}@x9`UoDkyN2r@SXZRES#02TkiuyzCG7UsKg<;Kk&{!yq+P@RCFTAs!A z%gic|`*M~0aZ+|cXSk-?Kl`x8*}m*+m&HbO6Tg-%Q<RLEIFBmsejkJ`YB(i4Hb8PM zGmb|wvrRjS%zyIl*?UQ#@og(^y~bS*$+2a}n|{2D@ynMg>9F^YZ{bp)*N)7~>$}^9 zli<@Q%}|n7sQGKq5MIf9-jPBsiSZTqgZTDE5TV4oTBgNS$B2eLJ3hNJ+4lB?81@b7 z6MvfAs4GIS<a9^XM_uNf7X}#79D+RdcYGqZqVHuTSS5igm13UzQh~h%g&t<ViXC4{ zOn@rxJSFu(u?=BA+rj$+%OE(Zb1-kqZoVT;w2J>zAR@WRTxP*1h(Sp**GmkIi>|GB z-cf8`1zH5oR(YrR@DEj*hMV0n#^VRrANRe_>^WS88es3VNvv?i!#wjhdIR3l>yqpP zHEv!6N6$FT3G0vD^;rtTKE*e&H9h~t0PG@Y>CYl4u{Q9Mj#huPON>_((p_~!tnoYB zzm*l1i2nHYh-907G)5ly-~<#NmueqreIVGQ#9!%F)^2AnZsuo5^g|oI@!{VUpFa@{ z1@$?gh>F~jCtCSoL4)V?fMOBXL;*Wm*`@fi!nt8iQOYD_X((&%(Gql1jlS5lC~sGV zT6hJQp1P#!$okNCAJ|37pURNOVB24WMj$lg2{k}z5GWFNJv7kr*Q}0}+Kw_cCTal9 z@mrkd$I>y~KFVRoIn$iN0x;A6z0~Po@Lfpqw;cPq{#0|&`oyq0*Vt?N9-mzJH9py} zH$SKZ8u%>n52u43^$67q6gV$aIXP3j3z|#Kon$7z*DmF6<;MFbUu@}**4~byr_})Y z#-6UiKr!}B{F{@#V-^2aEe*g^<khztRVnQbK)VsAL;F6%R^`N+VYAaE?vLlmJw&8z zIGMZKeUy?;f$PL@6&&d+Pif3h$Cg6AO~V8*7=|z)Lj8?c^^AT5Mfwe+$Xl@L1o{YW zmK(xCL)7^h64V6!p8Go|YXxT&*jEl_vq%?kEI@&TJ6C4oE{KvKUn3to@_h|3uOuLp zDe%gp?{Zr5!ly_~xn4uv0BY|>hmu?`ngZD9?KDU{y|*32NAt@?2E;uB<&20IiLJ;l zQf)njMIO!+H<+VciqnSjy9$az{xNhM5C?Yv#QTHj!_x^!+Pb~3@=CZ@f$N^s33n)v z_@@@IPu5WH=0+PD7f+rm^i`N?l3y+%PHdT&lSh1Yja}S<0=4oLI;2vOCA&v(d(+1U zIg4l5w-xoHnY%bD+9GWO1rU4r<wa5A@7dch3pudpQpGV9Dp%gk>}Z_47@!YwLnKp> z+IwGF%2oPo1(I1dQquSkX8iGfQ>f(WRL9rUQT#|l^C=?7)QETBc<#4J<w|FuVbzK< z6+*XdA<g(a%HYk=Ayp<FCI&c;tooW!SD-u8F38qqPc$kdZl_{DQ65r?&y~K$$agJj zaL4L%=@i-72?!t=9_%&Cy=M#8C1;!7&rz=8_?ptMsBYe{BVh$MkVNAivk^jQ&zsTt zjDC$eMBYv`E{)sqZA)QWjq^hQ$1iRUI5d!s4aWKwj}oLyW>c&Z+|MuhbQUD-6P$P| zntyeeK)!2$>mYU+myR0Yeae}}6D0t{I9-@Ta$pZGfaHQ5t7jcpUgX&WI9Q7NPD`I? zyEd!(ko_*~{0RkEWLB&>Be<~>uFG8bkfyGOmNTBH>w6yV+$AWoW>{w82LwGlP-X_j zu?d6bAo}DM-{-CJ%>G)t#zVRUsG2KR13#AFFSdvpqDKiv@c|c#L-@#>`<+4|*Zh^4 zw2U__D;w~0H{PA4FVWw5$6wR5v*L&oS5Q-`Bp4JDXOF2(&ffMH8d$)Odg%&s99}|F zV<5HXkKGJH)9tiKn$kt5S}9rtlTT}9+L)OY4k5rwG9md0;CwnuLTg$Di#`+fcFa?Z zFUNOA%TG#hEs-wq?9~bLB){j0fs3fxa$h9dD!3mqSvRY9^NJToNuldph$Kt&fA5v8 zmgyKDQ`nlEqNu5_7_zY)f~e5C<EaAfV&jtG#n2q4Li2AETET{z6j@~xu9)?{&Wm|= z)4%n;8&_Fv#^<$BL7lcDH<eij^`uIYXQ~{(l?P<IBjzalWuaCpQ!Dr?Rr3_zLbLjE z=c9Bzs12%{x)|BWqe30^3Z)eq>~yi#v1a_xaGY)2kc4fkqQ20_q_4)czJFmi4&N%N z`*M9=0Ltk+MHcMhh{<_Yn;>aTChIn}VOJ!$F_sf<7EX;3f#Q|@WW<=0RN!Lm{PA*6 z1Fu^5B%qu+$S<wm8olakCH~<~NXP7UA~im-TIx0Mm==Ljk=KV~<ToSZ;w5~bRONX) z%#Y~#pC_nC--*#%d{wsU%lqSqF$3dOeGs{$S+%LN%|)W}#pGUO4D6=nsD6A>zz5`T zu8SaJ0wW!h76-GQa9#`H%PX*0e|c}UN7k&YzSg~%e`<&a%1vx9@>{RSkQ^s};_;W( zTRh?`VK+fm$UoUxgca-tie<y+V{{r+iToe};8Xv8dO(?cq9E4yz2(@O*?IXNu?$;Z z++mVyX+gc2HGJ!GkI?0!lJ!1&n}^dS=lMuIO4gpx=nxiTOk~iskD;SI0}4QFw~czY z*{AAAs!bebe}9{SYM^<a+gCg1ZOgS_52zcJZ_Xn<fw@SBnyMQc8NZm^TvFmmEpn!M z9^O#i{CH|W7Uv7GZ9=)eIg(d#=UX=>Wx-IFprcKgbm8ZH`g~S3GV68ZeTK~tPo?>h zwJ&dYF!rHt;GFY9rVcqlQ(p0**=K6kAPg#RWD*+^>@}|K)3<JWZo*FT^ZH}@==~w1 z&pgJM{zHU@=W_=djf*4IlqgKcNmG*pDqUq>Aq*&Q$}IAVVJ+<)#}w)Th2+oOpR_OY z;N0<Yh6O%o>^~a@(A(~c^Q6fu9KEf*QX%(!XwBCki~qLgC~-7Bqi%}ZE!jZXdtrf4 zRjF(=vSKBeW0{45i>e-7tJm$1FyeobXSA%?v}J%))?Y<YsGh%vtt~RJQyJ(p$S>JX zP726<urtku)4`CLZqt`1eY!dAWw%I*rFXVRaoF1~6PrnO?0#s)xj!*@I(NE)y`#3* zvv*XrN#1DjKw7MS?rHxtcHVR>39eJ%SL0+W<*xc}e3OOC(VN^XHbtEgff!N{5ufkI z=cLI?e9~E>TPsdFNY*@<fQ;_MpZpv(>J3P5bRV9q71NlERA&ZV0c((O*iI+3=haIC z;N!i7^nWt272<$aK$H6;_xShP+35{WE?^9LpPj9;DFTph>b@3Hlh+RcxQy!%G8X1M zaslSB*?$GqYjg!228P_8FDVyKY_yrLCb3*}{uQ4A;QC^GrD(R9^%FU!v%bmw_1g}V zAnT|ZR@fwoMldUI$+)Ed?|*;mS}14EiyBsJCqdRTH1osiYZ-l6xG}e#km%{$eY%s* zzKeeo*dfZVvxV%Mz$S@}YRb=F7}|HjrEiMcc4e&=o_`pG86swDvO~fn>=@%8Auvx8 zlhBsaGOGp^G+~@t2jF$0ImhRxepaE52>uKULE}4L&f;*EUG8b8Pmh$K1b0S>4NjT@ zd_b$rJimpFzAaNh&-q+p2Gh&4r9jFvHPz((lP2)y=_!nX)`~`Tbn`A&G-$|<1{Xd= zrsfJwNu{1hZF5+!7fl#<KW~dssVMhm^}usL4_ub#+(y|WjeY6gCkR>HZ{0j#-&@&k zN1IgAHuZe8%pl+5beEi#sZ%N#Up*!>?W3y=6HwB&yl_Y{q2KRtkx<<T;a%N?Mt%dv z9q7gE)+?yECv&@!S!AlySP``qJ{xh{JU}FH{Q!8q8}uz63|VUJs*;+YnqZw?GaibQ zCt^tR3sMwbC==VI(de<nxVOO2%p{2Pq45o^pw0xi)OdPp%cXDJ!9DI)k}C%62e)ZM zVSoo#@={TBMMVqkvDkfjKf21olUKfA)T6fyq}d5-D&1H;Gh0ytME`t1A5!i;ofs7U zG9r_3iC9@x8N@;t9RF;u5(8C4<Q8mKy7gTpJhFH6U^6CDGuUtwjdSP}^_oL&&Sn>Y z|8a#{LGPY~?IJ<5$r%_e5UgmA&nr#1r_+mQuw>xclio&2X9<PvmgYn8;Y#@-9<S*> z%--c+OJqR_Y~v`$QC?Yp7lZDKBM#a`9^vL)@#hV+S==m^Df=#w+@VAU7!{G8xBdX; z`qruU^*_JY9T>=P3A(@ok9c&fw}8)ROv6@yY&T4}2j;Q>J4-k7>8}N~i&ghn-~$eF z*;k)cw?pNm%?6X}_J#TZKEXL}%#Pzmx|{z35;O<JB5(2!wAL~}YYAq!CpTac;_#7P zxKOjIxz?AYB-FPnfuSbv{PA=rL~F^FX?J85?AuMxYxpZ?P_Cq&Dg`b7V0piY8`70> z3bgSrVI1e(hmI&Kv!B=Z<PwaZaDXD)2w@jAN)u@f5H>5=t*$zsL5@8o6sSFsaukgF zoe?Y6{$d;otZZutv*|W=&jU`vjO7EhO$7y}|AG{2eC)di$`8Ob))z=47n-A&>FVXd zQO_hPRN0gv(*b413Q+zm#R%Z=7ED;V;cReYMrvVr%8kOx8Cnq_qw$uDU(CKKeoq>o z;T=-kglddQ#p214w8-^#vu{1#mtq+6JAsCe;kBBRGc)%Y`Rs+1y3yt^0x>9)aU)Zw zmXpvX`q69gY#t71-saPqd(ULFZ{$0F3bX4*z|-4xN2!}zyR(US?%iCww04tiN`dPs zqOD=l0oo>=%5Y>!sXY)=>M|7X;GVYrp6R3%C@{h0@F4GjKSWsdJu`A)ua#nLOeVoT zJT!#PNT3ryxwA6EC|;i@OzB|JcIF+bQP%MS&9U?aNk>ot^y%}$>o@fm<9eh|-+4;c zr%Iy<n1e;eZT`l%6%=q!*iPkM;QuD<f9qh+$q6}8EyBpe{OlLlA$&}3K6f+6OMpAy z*vvLki|D174R?zF{&rKsAzU&>>N);(^s}+}m{j;4yO*(hpX99~5Z*(G*Ski*Z0Gr* zNicak04)E6AYgm-^?fQ`u-8XIWm;z~Y@l0gF!9!^Sx9<;q%ZT+F8ovBwepXvw3Tl$ z08aO-5_qEiHCL2CK@#*nq~9~=Slw2hDQ0;5sD`)6%mfKSs>A!2Ru%sopvBLcpG0dX zIe12kBZr?^)=1?RylEuA4?ek+h}v_aKu5<3F<rEc^4}`scl|54F6w7Yx=~T}sv@wl z$8Tckorm^~od;F~epVtjZ^m;^r=rOPy`s9|`AR~80@^#Z0mrEByeOyATcGG3R5&>s zb<xpjczS=Laa5r9pI6Gp{U%(U#n4~KmzExO1d@T;*K_zfNdprt5Y08^+|xAJ2I`b9 z)Dh%yrm0Djf0@4GVi4fEUz1^t(u<(ljqImNzSk|&Jwk1UB8d9VR=(4a{N#DS8?d~H zcTIpr>YneJD2iKP+_A+-0);cKtYt*PPFkwsbJ}zaBpNfW0eD%gx9q#h^|8PEm~iWJ zQ{S8Q7<~(5V)c5hkL{_Hx64L0K+|xZ^Bx!yiUYn(-qR$H^~s2vZ&#v<6@i=bz9?sa zyk}4)yJco&I+B5?H`^14dZ_}9_ewr1xxE2pPQ1#>Mwzoad9t%e!dp$8Hfyr$RTqu! zAQeb%=v)iP)UzkL0#lUY1l~)R3xeL4lSs_8=rnxyophRUr*8!zUatRGCA{))j}{8h zqfa-ribg1SlK=9F?)zqNTyhF9LRgpb{fYgtG`gQN{{J!d-f>NBTi39iqX-;DLAr{F zNE49~T2z!OAkqW`6eOV|gx+EUM4Cv4kRZ~l7<yHt2&B*<RH>l^5JC$jyqloj=iGar z@A>$XUv{$g+H0>h$CzV|$r`Z9k?nZgB?zcTb<=#boqG`w$~3+o8~mO@=m50HZ|mim z7v)$|_UxML=!D>mq$dPY-iNVs{`X4wD$NT2a`*Pe|A_DKEpd8#v^>$MaB@V2uFw0p zFLn}N@OgSmm;Ui9w}iCZ0stP>*OArp{w|W5(&`&}sAqJ2eI~un|B;Pg4AZB&-XPz# z5(W2_Sy<4jCtU4+k>)mglY?p;Kg|PK=dRNREG?+c+e1YSc(rgn@t6ltlpubL7&64V zv<)&{Oqp556E@?)i{?NU9f!G!W-#;*G|v0+Z6;>S^yzW541f<}sfsc^HEV*-RXsf> zyN%jAQ26}%u@3Ey*i@b<-&3PcXR!L-6UdeK?2+~o%dbG2KFwDh_fqbCoto~|4Ku%k z*}rHUC(xL$T<FTzQ!R;+ho&d)S0pF!-xF3(R?me4MakB|C|~QZc5XchEa!=a+lWH% z!HaruUhb`oNqo>^1ZUPDzq!!NlvETT$Q>o`333tE`l4f(1tolHkA5F8OwZQr-`1YV zV98$~sHSSYuMynAY6CTkE+1Ajg2TX<tM!aBbgP58(h~O!I5QTJ8F*P4UtE^H8}FxA zc_5S}p6@p!dyvN50L<@K3<y?t;WJ85`TgWkj#u3{`irw~b5KCVkDl_ggb1*5m|V=~ z6bXwZm`Bt3wUfj3tY-2YAV`%Kt^sfK7nwL3HNXLWJk#E|=reXu*@E}@tZT@b8S&Et zr|rVmj|Z$kXHWpK^h<~f<pQ+=1g}1b0_|8&W41f$D1FDb(#3y8!drf%9B^^FxU%D> zO(e7~mlQogSYYSYQdZ*lGNEcbg~eZ84SVW{v`R+xzyZA`TVCSIL4YHH8&M))GV^C< zhCUo(_uS-cpCK;-I(<*{QPMD5_#YL<FWEF;tvgrc^hw>$1jZl3n1xV~0!$dEj8Af& zy3`yb?EDjX_UdO=@YYyU5PzoU=2KBWTz+0eNn<4+1?@ce;w@mwb`{L8uvs5*2kD1Y zuof4t8I-ZweLuwlWYeSbOJWL3C|72jjFT!ok+RVazf`$1`s|yq4(7Fl+JgS<aVDcK zpIl*-LVd~%)O=pKhqBXsjHTqI%cr}Qe0!vF3_vOyAAMg6S@Z1JwCkLKS%m??4ur3O z2OUkccALh8I=j}=D9~RABH+?^?}m|PPFDL_T?3)2!kd5=_6~czIN-Ood!>UPe|>x@ zYD3Ikcd4w5I7alBhwIy6fWD5iet%Qt+0@y6+ORxOIb$3FD&6$zFR)j1cCFZ5qt5=Q z6<@}85cgs3hyL#UtGRjSwycf|HWkL`4fpl+tS}mW2wD|BV!D@R9T+}#&f1T-aZueD zgOjLEzs@Si7wV~)<6G@BM3e5iOWV;`?MrvlG-*Tsa(=(|=U>v@iV4H*N3miV2K_ol zcfyYWl(<~U=Zok3jsrqZ3DO@0Z%!qk;Efb{SK|7Md}cZEC+!T_r4<W}2w&J8BhD@x z_$?&<^bdCvbyWHWWW_u4&U_2i=NvySc%&Ne;Z^M1CT^sz2<JdQ2mir2pYGGtpnHyF zU0oP9Y_4cKg5vvVTW+|fyMbUC+Mary0xOel4A5t@c))9+I9`W$vKOrQ!)gZ~`hz_H zGQdWnKPOj=9WX2W@7y+Ezq_{+AGja)PjvPxS#iMspB(u=Kc2VWb>Ink3WHgYad*?; zciYP+{@aJrr`P!+RtUXZVt7E^y7TP>E!*%*;&$N7ei|8QkJ3ykH}PD4DZQCyPhSTe z_yGqTo{Q*zC2wv%p@m&QBNrFHVFW@9I1KIg?05b(_B^0(l7?FykVq-o>%hJD_pggY zOjeW79hQJUR_HJG<iH6UF9)=*aSN(4dj=5J0$f0MI?0Q_Ch7`}r`Ok6Nlb~nlX0gF zVC*;mQyAL!{u#3dQMs-8;0?eYP3fN#2DC>KfBG8p-!CdnK0-$k|J3$NM|R-PPjSS7 zpqkQ}Ys^zcA$wjwyuS*Xp4ZV(9MA~p1&)KR@-_2RJtLREq5!6Oj}87MqWXQeEiYiY z&<5CpH95e%+G?+d!QS7muZaFU731`u&*)#M{GYe+Ck67)NBVz${C}8M+p8o1mOSjE z41RBmkSiy8d2hk$$S^MJY<YLuz-<1f7z9YX0xVQT(JPmaD}c*jYF+}{BWC>wxA)vp z3KL$JtZ)Nqc-4^-x4;$6ErWgS{C~Or9|CgmSGIM6Y1OG_YOF3Lxq`nybD+9oM2x#c zeL}8qwYtm&7ZYU_<ALSH7o`!uax2eW{EHHQF%QQ=XfW<yi#=q0ug6A#NW-e5NRmq= zw{KDB!pw;0i<(~o^7O~Q1>}F6sZFN=ll4+U@%H`A@*5X{u22;&g)3LB<9(VQ-8NE` zUl=v&c+k<&(bBOAXkQD3HFN{}8l8K2`doMF^XE7Ke$p0Z)_b6@=i;=ZC%9RW1K@LF zCBOTa+75i9RUw=YrHv7AdQ`vUyM|2~LaQ^dxu7n0q^-ZMgVxG-MO&O9lY$e#;4Uik zA`?*e5^jQ`E^$O8F}oQ)!+dXqR^m@9bV;p%$sbWl{kz+Ra~t$ZXJs9qWkRFdMn*Qw z3t(8d*e<qJ#^~wEuYD=&*IW?OB4Y4u6t`li+Z9*s1&x0RP`v9-S4jZWz`kqsf?eNa z1DOa%-`UyGF9OJJ#1@1;1#EuGg*!(T6~V1l8wlj`KKb`>sPVk3Vc(n<8ThPr*q|cb zrAYYju&Gy4QDF2vN_^fMKi9(<wi)(mf@z{^$^nx3LcTI&PhaDT2A2JTgm;ZJx=ex` z8ZTce2=ttkP%icFoWdDRFTAUGU32fFI_p!Ml<R3?B6q^Zq@q-`w7w8?*wg5sClG@( zgP^+Lp=Rq#@Gzyph}R_^RL+w^36pM&(QyWqK#J!Q_<G4tr_VsI<H{&EC<}F)(r3-Q zo9!I--yMXe?l*9xji-tWT@rc<l=%uKI6W_Vu&x}LW|GQfe|GMAlCZ3LlbZ<fqg!M7 zhiy+iYaQc7nFjqv%~)J<cU^4%=`p!<wXNwiZx44O_b^XIVBo;~=BFEW^JvNEIe9Ym zuR6Y#T#*6lo>+Y|j<!Y^T+#g8(IabQSCeb<25zD=U!fm?dr$pllTjr+QeMaEQD*Wz zP}t7#<@%>#yH{}AytB7Uis!1e`=tP7x%MKxe1WVi-d1|0im{M`mK?pgpC_j2WlV6m zm>q>^gPZFXEEH?9e5{*&RnzGib!K;!v#;?>{w*<j$2@1yg(jwIi71UQ<4RzXB$|Ph z5mmNIF!jvh`q{u5S>b=X|Je;L9Ey3fsaKmA0~`9h{dA+Diz**J4&7)cZ4xE`!;+xY zx=VXvoM1(sBGC?#xh>!qT!emWkvgKbYvJj5p>=@%?}FmnY>uS-%Y^~{p{&O5LEY~$ z`v5<0I1O;J(zycH<m?l7+jfsCyJ~DUKl1IcB8R~z6>@M#f$(8?F<&!>in#C`P?nkE zdGE7pzrjGoig0Ctuf&%73w0q!vkTTEOhy;N=H7zKiqjU=$ig*#ieG(U3Ff79KHee& zJq9sPjT1A6U3}fWQ1UYPxt}c=v{OMyhPFuqHp0m5Nqn`wB(XUYHr*to7Lowa{!(YN zzmC#H2iZFLie47E=2s&7xx|c$-@Wtk$Lnnnym3Gfz82XBWfnJ<?R~lQ8aJ%~_j9}D zu*gJh=wsaLmJ)U<_!+H?_`19SV0BcIO_7_C>R1}myWWEyJI-o^ERPHQ32D{D&qb}t z8+koUh>ZuMF7B9a#^rq%z90toOADPiE?8C=KiMdX_8%NDGT+vj!T8X@%T2ZnOI~lK zE~v5F8u}B%-Sg!aj?94OKHdE)I188sGkDxJ?wyadMOs>Wt`_$U7@Z<j+WC9_ru>i7 z&Sk(JJ|#bveo7^p?B7)_0S?scP*m+k?)08gVz~>Qjjv1({9>XygQoAmsXXM$s$DYo z8Vb6d;WuL?>V`WV^mHe!9WV0c$*XV#P~Hzgy1B}SM}FdzZ%&B?B>1TdmyB<EC%VRI z&kxe_burw<W!K+)?Jd@pe|$FDS6LNY^77o*<zC@bEyI(EabT@tHTK^ATf=&iyFgdO z-WYDQTf&Vq{WUd5^J+`tT)G#4t~wsIT(d^T!3)MsN`5F4=fN`^-Q68_-ft9DeXrlM zub~Dw+E>o=KU|9Bm`5E5`*ih6nxJzoU$yckqF85sj=|!04vlXgaY1TSE0&2!SBY6Q z)K&!8EMdFk78ova|4=`ZxcH&b5JtbKiu0o+zy*f&kkT?SKla?(NpCcn2vz*Lj4nLv zwoFXE_8tA<;Eh<YvN7qoXh8lIrzf6BPFbJ)BLBALRTOLf82)M$*wNba$9Tz`buZ(3 z*{txxq24(wsxud6KH*|agu{>m_PvHCKKUzEcLxjRR)PR|=ryd`jS--rwvZ@j&gHBI zG#gX_7qu@8nV`MCUv=CbH1$~bvM%?@@CaTxKBN92)t5i`BN*by5%TaWa!6j^V?xE< zGL+w#z3K_{LdA&WXAH<xxW4jjVrqsEq_&=WTF}0Iqm>@%0unq+Wt&L^7Ltx?altPw z=dZcRs4<jLbul_p{e!&MQ->uF;F1n(Y1@<~D_?@I-A!rlLPLRkuka<wb|ERC2Tm+^ zfQ_MSD+)EQ7Q!qDV$B|pSc>^}R}{!cKA8z9v7&J2SQYB+HpV|T$;sTlm+9Q_q@#AA zVtQ4kJG$VVA9SF1W~KQ%YQ03NZOE=bBKLt$8Q>)C4x&?q-A+@l%AqE>Sao=x9I<uH za4cNvdZ1g5n73CYm&*E=?W`R(R_77L$q_^*l2{ag9ICzN*5x(RhTFqelI$JN$u)dl zFfdyBx#vX;{N3DN{eXx}Xl9WmH*1!xo`6zx?H<YW-9gWjJG_qp4G(c2%)IVCUOoWW z+QUawKFs`dx(#%dnJF6B<nX)9=^JXXu1c<LdiGV!^j=spYxO1vK;|0f%@ejauHP#$ zXE!T(=efsh%;-Ni7ZmLM6tZGue0tkBN54=BT2R03nSHikV|RXtu8h-?u)Ab@UPa@4 zQQM`JoA<R-RmD_9I}%;8I)q#VPQN`Bo&DfQR9Mk{^J#gPgBRW&JQZ@zLQ&(!c5|@( zuD2fyvV3nKi4ZR@PDCscz4F&(0Mq_>D1^V<2Tq(q2J2C(YRBd-ZYJ+G-cMSrhQv~c zR0)3~>Ue4Px%9HFi)fy?i@BzxsuM;!tP^Kem;P$BZoz=r5~~7CYwx!&nOt=l(Z~Z| zH${CZp;lLDZF2saLb_~CuQ`w!JzR%xz4wZ|4|it)5*&Bt#pQe72Y1WYwfvf$a<&O3 zU@<2RuuEpRvU#<WG@P;G<-NRXaJS{P@6U9`swilF>fg<`5MajwmbOyC0U`6Uj$R3R zmx_l<mW5JR0^~Ko@K!s|>d9`fSqCh3AT|o>#RXDG2UB~RQGr?V4TohuUbL4wWa3MG z{8+$spzM}Ol2&gJs^A#wiw_WvD<8Sd%H|uZvdg&hp88P_%@q|V*K~Gw8$3-RsC)fA zs(my;b1}8ERwk?dx4dxrX1A)NymCCnF{Pe`V{+BUZMDH<;x0Dg0kQsmMd+{+Lmm&A zRqHzM*VV2G&ec~;{eczj*+0HtcrO_<_^56^kQ0Y`74GxSEq8&4&x-fl-~?WXYTLV1 zA#Z`~YPFr1;Jzl(6ITQ2^v<&Zg5%YVq@#Mx$PY?i6<1?o7q~O5+^fcvMI#hcBcUJ) zxkN1ho*o|CfxHOR_~;JZ_Dgv{9LFlmE<zCmV~BeWy|PGf+<ZpUY;|%te8`Tz`dpuy za1=cK`uIy?aqjFpGjZ=WyS%;oMiM~Tr{On)Hlfkptb}cr>=(5fJF35{s%7rGb{ONe z9S#jLOKG|3Sc+PO-N6p2qP8x>7wiwt>&lvW!*NsiYJ_H8J9i!0Yq{^dbf{$5v%|xC zHVqC8(5?vL<Xxme+^0ey{%SQ+RQDuXP+-BGC#T#c;K=B*n$Da{<1&kv?{1>m+ihjv zkco;IZZTOctvSK5a}rG(U#!g$y*^h_3cVzT?iOSw3yXt(dHJT1Ty`Tn)EXaqHH%sq z3HF{BrKVtDxnNCw_Xr%j6JU+VqtCDw+s*e8l;3qsM5<C*y!KsJX}N^sS9G`RCf{oD zo1#VON5oa=YCR)v?#$gKPY$Qt%)oUCjGsk`0}c<lQA-He6cN!q;_Hzcs{-xmb@jVx zpzw?6N<OT|U%kp{3H?H4rc-?X7B$|%{UFYeXGq2LxQkW2%xx&Mcbv&38O>ZNM!qkF z+n%_LItpyy*qL^dhGpXSNIDZ(-GB#`RHT-F9<JFkJY;g$NUt<ALNjlN(JYgN59sh7 z6*h&Jy>h0y$`TL{LbT=z9p+eN-Ig|?_+dXkkDH{tv@ULnvW?GDwmI1`o2}vFY~3hG zZu^d$qg>AB0PfJ5{kCnH4k=H2R%q!BEZKOq<pCGh_Z7RZTiZuu$KIuqy-cg4nkM90 zmai64gFi25xmI-d1W<-PgbTF+1sBY-Av<x!o9^DQ-L3xWs&N`7IaZY&IqVf?9_0Aa zs)AD#wy;P+Q<ykOT<&L#TYcY~R9yyjC|oS$QeJ6Dy)TtekiNd7(u#tn!EJCle?=}s zZ6i**gWwJk@yassMOc(@R<yF*1MXxB`5OA{4WlUJLcws=h+dKLoh2&%t4xlK5R13% zn|`Md-Jg}|jHS7opxh}=m*cLIVIkVHeO1qtw~ptJUMwt~B8PKxW<G`o-Q9ti$*uK_ zO(yl;KG6+N9+CB_>dY&VEUl?I#aDduxLx*I|N3++qjkXMNN>s{7tLJo+7G>?l^)m` zb)UJkS=p24&ZkgdEF3xWuX+#l&*>DZxl0BnoXdA!QeS=Z?QG8QJr>)I?k<DOp%y9K z2^w8-Gl;g~W#d9xbyvBLo%}lqC@NX8tF-Ov8e@~t8!nSgRMZga?qsaZxX|p@k}~H= zFJa=TIo<@3&0g5|q&rO;f^HI9Y!+<@GR>%=be4}%B;l^;>JK6TnMYTgZG^9Dbtg90 zRf7#4@J5~X_M)Nf#}j}@@qz0zwC<b0f6h((+hDrDOg0PaWhpI*S<L$!eK74IW{Zzs z*YgcLc=*T;icVtD+h>?$h)%?mNExTk3e(86Hc{QZiTTH<N^flC6OteX@kw?iIfSd0 zj<%L)6O86{j=69}tfZK68R_t9wg2jwT8nM+=6hrqE9Dr=^#MsaXhzsnQE@uq79=BX z=L^XJy(sW<pT7c{D+52`a^V<KI&U-q<oU=4SJo`97@4jiH2THYS9xfuOx{n~jOWaB z4d75PKPo@Zs+18jWh@wno%5NxqK7d}KVP9P*}GW~x6@+x7TEo?5|RpbFeAmU)?OUN zDnQ))37wDv>#E0Y=#<sFbubYoJjJO5lqdspCOkT|0)sTkih6}}+4(w#+(;}y+tTj+ zCS0Gk@!ckIu&AP#$0w~e5l9_k2Y+e1s@v}Pn#Z-bM7$2v@Z)F*lihprLaMvsVvVf8 z^62aEm3%f&C!38c3lAbmuas7XzHj^(YTK-?e9I;E&?cJ?vu=v$UU(R47@t2-$x~#k zJfJT9$Zp3_)qAamb-kgB7c%e+-Vq5Nk*UfEZL}2_XPZnDltvLoNFwM?OwVF}NsnHO z?{fkR1f?6ax(cbivGvv*PqkG<qcINRvR}iWCB`oCp*b*aZc`x)c#wo7^e`M3ghRw) z9bBd+#*R|KVzL-dCjoSD(i>R?q~2Cow~Wk1+G5%<qMdPHze_oc72WR}<WLSgJna;j zQT_zx$Y~<|e1R%I5r}6s);gji4G*)di;xo+`+4&2SLz9L-RM5hrcUnwUDH8*4{tE7 z$Esm+<^V&M_poJRCKABcqc9nh5GijRi>lq0X2_O5hb+n5t(ZW_F2PzVNci*_(u=V8 z*=EXs?dA=nMeR#U$aktvL5OiX{iKU%yo=vwZTbZJrzILZZfkuy_97y%{zs(8ZaG)0 z!?jSI+oLR4&{w!+_{qHoE3cO?HZb5>NJ%42y4))7u9aGFS_pl0Mu!INuJzHDHt^1i z|E!yo+>wZSu>NYBpa)oGCm{USs`BN;GkuWkTi+2y1l3PNsW+m)8C{oZw{EROw<QQ) z*Ateu)$h2$-{SVsS_-Zi$5ZeTCn}~0$eBhyR8~Ktz-~D6yi3_ZtxHsDS&XdU?Ht{* z2z;|(MC*O|p9^YeeoPO&d&kBbLNSE(3Ilh{3PCh}=eGRCk`~W4mIR{jr}y*dsI-Eo zC9lU87C<c|Jv0#f%k$_lkR7o#AAS7tQ$e;A7;c@&nFWFd5D{%;11}unkz_BcSC(Hn zz^?BOOG^{SXwUSd9POxTI6YEQwM^`pLC4-_b*vRjcU;VPNkOwhlxAO>pik3>WCZZq z?kv4xO3{9Hn~IPhw~qzWeYLx7mt(QI&;&9M1!CRZ34ET*d+=f!jwyDp9j5*f-!Suz z@w%iN`Z`)Oj#hPpswnwxy99!CG4e{Q93(iWyeZno*C&`T3Q><K^&3=$)EdlqyyGZH zw)rWA^~)UlNs)k7<iD4NnqessQ$oqoGETSx1gPB3Va-=hnkP;n@K+VZe(=?fky6d9 zh8eAq)`CPXcrUb<uIqf*F1KGu;64;s*O65nWOXSwY-J=ax{H}tuX5WnW;Z{!Ex-uw zk=Cx`{jvW?o)J*PdoF$(bXA#J_4ciW*7Zs?-+=XQK`!Y&lGtk0a3kE(((=>#6~NJ| z%Z^7+VZ^@VBjGw1SCM~o_vwi{XAkVEoLYZkGWXr-H35%ZxPO=dACT>X%x5j_>O35N zKdn?2dKm3!i}QfvMg?Ggi<oB1yQ@28`eGXbkjnTx?!@1AJIS-DrO1yVgHl(QJ-$x3 zfR+(;k_<rK=z*;)6)I`6Q25X&3-j&CN}#OC^ZesWa7Ow1PxgHSGH~SVkyafG`b`R~ z?cCFB^b45@{9>aGx>F&sc$fUemTFhNObo@;WM#C=f288);)J`}FEnK;*Y7|AHwt_- zomR@Gz(a-2-@1QN8~`7yNl{I1h-8Ny!|ny&;fIP&a~BJn2WABVBeC4QjEP&1B(+58 z7ax8!;<n|mtP+h&n$waVB$=XX=Lqo1Ss!NNy)Hyh0y>V}(i>J2p}-$|wEOtPb>CXN z;OP+|$$vh*rLNMm;2;OXA0+;Ef8Oc3(l@LEP0HrqAK6n$m%o^@%uBAk0opyO_#}9( z!~llN(V>#Zj{_~bKLl!u&Yd6=zsDtvq9^c#WukvnQ`q&bw^tqUk^^NQ74yyAG6|ws zO|ltikaSDF*`d2{0-vaHty1%7M{tgXlE}a;S~RYDDufm5aBV<9(lZX{0F@6~JbU&W zT=C%Y_L6Jlk@7<C+}OG%cAJv?>|E43|6s1}?m9#&E5P#!mJ&7l?iC2UMjYf!BqPM3 z2&1UM+=SVxh5?QZt#fj!tWU~Q0sAo8!SUDr#uDN)(AqTwQcs*-I{{b~UV(>of#<|w zNb$Hh@RmB>^UmYtV@81Z8Oj@)KIDqnCLmlYlz<2^=CZ=3;{<89D)@Rghc0yB#fPhD ze)q)|V<2;hNl)A|OkGfN)5Sw&ccSrIe0Mtyb1m17q6-8bF*IhW-3KFYP(C4R7v#lA z9>wTBg53;8>k?<)U-C;2ZDl)IBnNP$bMU$)NJe7y$F)|h1vUpnF92eiLL}!>xmE`q z#E4ye2$I{+TEMu9_}f+~Q)VWQcqL{7((WF9o&+q<`@2LB;@kS;@mt_^YO^TFAsSpc z#}BES31nPddZxT#7#LB4$GT_eCxO@XgYjw#62R`S3CQ5O4{ff+7+Tu4W`Fy}V6*Wo z;r%dK7shceeQcJ_HHxv{VPdS?wZOrx$mmJcAeQbFqZ7NAj|$ik;`SlI&qw$hLdO_a zeqN40)<mz<uNc_pe)}WsZw?>6NCgkGaORPrfT8Xk;Pt?KShb*zSwk<CA=#5Uw=%!( zL9*dv&Xf3NhAZrv;CIicoIVq;iY)ZHc0ms|lFkX?-`a<4ms<j?ocU;u?u~)?se??q zrEiJYg$D<JPGtu(+GXft3a0b+#=30nn(v_omDik4H@I$m5k`QCsDl{f6>{4uJ?ne* zwyVm;q1c}Y#|>D?UwFftVEi23lNT6#9wz@rrN)T*FS_l(A=>ure`w^$_+>4($f=28 z95a8VDlGkSyWz_Gj_x%$<JEWLSu>SrFLQiypN9>J7j|e5U1i(>A++%)czBnq>RyKe zbbMB`u&h_?@>J6@ktKr-v)H-~@@N=(x@~hwUo8?`ia{}ndEYtPn&{@$MLB~C(|Nl2 z-b*>;FJiTFVzvDmE1C{r%EF&>uN1As8N{O78U9hv#3$@To>cP)2o&2LHH=E_1oe`f zSM6&wRjHqG2>BflF%@GdVU1fI1-9(WBU`s5R{r>j?Qd`o$2f?A%@^9opx|h?vzn-_ zi*SYJ1ueV3^PF~zJ!4^?3H5F)L92})j!4IV@f2NYfa-15wo#*UE-Igji(G0X6VJEi zX;3*`zJ&FLDl4t5ADWpQIV`-7jxbff&{1MiRuA?rX`C3p)ik_mz9HZ@?4kc*{c;22 zEPMWy)u?>efj1nMZm&DGex&B#=OEtw220rTl-@<m*TI|(l|yBb_rbF_j4A6%P~Trk za1~k{{T5Oq)@}#NT2i`^N;`3OyfY`Z4PSal8kGt~#Iy#@OQ(ol_OCGH{zlA?AG`#b z)PW&y$3=mSy`&#$Q0-tBr#*7s)jM8zQum_;6&RnFEGD!gzLlu4g5rKy|EzmSvdO%# zG^TBQ`=UjZ*Bwz^QgXg$*Pz9n-U|DAY=%YN6e7w!i?~pSc+@!kHJDlV2ojPBcNFTF z(Wag5=dRI)+49|YF6Cd~B{6Bf^!b{Xd2UA%_QOEW4Ox}5Kfu>2b%bw8=6I>oE?l9f ztvfwvqh<Cc<Kbg(fH(A%O~bQLf;c--AVLW~;Tw+6DQ(t(3?vHctj5qTnr8hsZ~-74 z#jdwcQrXQzIu0+Yk%C^-O!$QhX1`J%S=ko}C)eieZ6KL4;vzcT?&q%E1OkZtoa;&F ze~#d<Sybis%KJHS!iKAwZ<CeS_kQwu*?)kQN-F_$9(F-u%eh-t;9>`_7oFD~+Be>$ z0;%Hjk-&`zV{2^PG6;GQ{>1t0(<9Ep_G@hDaZKapxH<$SZk+lNWEP4wEFv-R8{zD< z&}Q+z-{6*f=p?MB%Ni_>ke)4;pC^H3ye`{7I)Sdl)?_rDq2b?a-~Sz~#LRSFW>I)X zyR(%Eye-qBb>1}@%Nrv`U+qkZ;>ua<YuAsqn=FeRZN&>zC7G|q5ON@;ae0d?n{V*( z2zy*!0{U66B+nZnJ~7_JW=$Llj>L#`DG(Q_ekV3_2}~|x;qIoK<|S3d<#440tU-4= z?U<Pkqs>d*2S?pYz79plV_(exsc92n2&IgR)*qLQT0E5e3;y7Ss4=%@75@S61p6mz zs?iTeo~{|+ElzwIhqgw7hM0kt#g=YGgcmqJK#p#5fudYli+ZV$V<xkGM`GYb8b(CY zTV{vqsXs5PpJUTWTL~`8G^8-vCS?O4h4+J>D?A4$;@K|FVzO%h!9WT>T*0j@X`=Mi zImfm1MvvX-NbH(8%-Cf=-X98i7MPvw=DBO_&Wpi`ZG{qCAp?Bacx70EaYBNpX5;14 zJd(!W?D)}#F)@GD7Jp(a3MCjp=%oud$IU9nqdRtS&8S3<hXe4pBXTDk@i)8&NT;Kf zV$;gwwQMaW-PSg8H}fA^l$4UqVLR1!xE)vye0Oks5KK37k2Zbh_TTOkfi?3UY_JCv zq}uVjU3(LFXA8V&>xOEqnL!auH7<#W4U}wc*(MlYAU4}1EpcT~K?+2`2hjW)(o%Eq zc6M@29Z3MqP-k*IMtmzmEvr<obLI(TZZ?{@(=oE8=dhC>32x%DTvJC2o@I@-JaxB* zXyv1%kr8`8#H<avnr4=5b~BZLt%WlR`0SU7&F0bq!)Mb2MqVYkD~8n{01bl|0Plxe zNs^QAd?Uf4b|uj-2L-O4HofAD3!SxWH^;>!kOQWkl6K`{AIzaK!(y_x(r_=LyAczK zYDl8~bDul{J%qTK7ao4yyUz~Nx=p!+o`Ddv%*%zaSfO+}F0c6nM~STzwE}uz$*mXn zznFpj3TIy3`Td+<4CwRn8R$<9Zn03r?~8(#iF&#lUhfHdYED4>JS48`-_vyUM|HQ| zOTy$Vaq#Qj)|!8xF60s8b?-+`4s8SrKC~}pLBD9un)(xlmc_WOn-T8&_jKwk6Q9^T zb@G?Fx@cEohZ8O?PU#OoBvUcqjv1c(?8PTXSq61>r2MSbB<^B!nx=kRDFyw0176;z z4jNBzc0@|!J%NsmnX#M{vQo=6lz#hSH)Jj~img=Qp6V34U&JS=p0?m%=}x7%BnP*G z7Ual-j;*s;7p4l`7a+Ddlzie<)f%l+`B3kM_K~j0BjBf!C>hXhGwG!K!!~9(KqPBR zoMtPiSm0eQRp!o)^VO}iohGR5<eN!&*O3lIi;3ni;G@aO^s^U&VrRKMZn0h(Mknk8 zm}@HgaUr9x@p9z!{Ubw>QkB*~pF`S2`bQauJ@E4m<en&XQVtw6b(*I4i+t)>W#v{) zAR??4F)@<HdQJ=ZS1Wymdv-zBiORESoHO$XY2r45N$U}TL=UOG|D6PSSS^vT>n<Vx z@tG@nF@DGN;HnxG!9pP;uX@)E!*ibuPhpI6dYj0jwj1wfJKV!GxU=WyQx~uW(?U3L z<4!ol+-+`aFQ7GCcUEOn_+{nuZa)I#+$<Tt+tzMFJhSv*MsEKtkEG%&<A#z8ZIuJJ zGd~X&2w+Y&W_c}*tC9mVSvCbBkzMXyrKuqDYa$8x1jp^UCa259Q)Sj&YkW0GUN5aH zF%#jfFu#2QZ9UtybZS>8hysIAiQUZO5cJMjGxx_uj4o;$?8tOEpZUHCU_+Lu{7zy) z%VKNtL>;Wro-l3~?_KW^Szn+_=H9OK_}5T*%^idv4DS_SoA3k0xHboUy<0gyCtuKf z^`?A<ykMgzW@-{U4pTUTL^~ouY@ye-Vmf+TqgVXYZ{@Q}c(3AF6L)$@t=SA~VXI=R zNz~9tFq59n^p@Vu;adZtk63i8y<ir~2^u%N%YVN5%e}p%poi(VUh~%r!*(2|UM(zb zRMeZid+fd_a87y)_|&x61?Jn^zJ4%BSta|}Y&z8tbh}T&MXYgw5=2=lf@=q)?oZ6k z2h}p*o2|50TgsG@6c;47DhN|l^mbJdMG)e6g)lq>?g>heYXy8zv=<{#S>eib_EOG- zFQi9jy+;ZHI1;nOR3ctESi7aEH8I^o{kDs`L_4~H9q-g$ocZc$ZGX95#oipL19Nl% z5`Luv(|sEhtCeZ9exo>A+JLW#X|B+nE+-Q96@;HYqpu-tC&;58<r{W;Di))uPfst^ zx|3^k6P*2QOUMMJ-n}^Hs7dvCO&EZ{CB55b5}n?f59~4VMqfysGE4Nuqu*9F7zC?G z0WuMEm@w7<GOj%;-3ZzWY{S)nOpohKhw1QVK=;^C1<ht~j<tI#si}ONJKw!FrQZ^U zqZCcaokhZ8WW?PeqF}So-UFhRCH@4a;xvPuH`Kp&ep<qDA4d6)d5wdLmpATZ7{4{H zUt}~%9Z(wN?_S+>LXUS6?Pf;6Nvp?b9yZCfzn8hv-7VQtJm6mQ!VBoI@C~EiW~D7s zS-W{0Zt%n+R%l{fgnK?*4;yp5mxDDva=qRA#i-E-5KC~i#GUyh<!t8f3E5Cn{T-16 zu+R+NaFC#SO-X>stgKVG0h>1;dZn_V3EDO8^^)*p1{Scnj{i+VKWERTAuZ0$9u-<R z0nCArq@?VCBhc3Ms)@l2Zt6ar?dBf!ob+9)OKm?qx|L5mE@m-h_w+`dd^ymrN|md# z69m95TPQh7#UgpRW{!wON>r+b8pdS(iv4u|^CFUD!nrgNW_njk$IPSam8ROEhH9jl zeJT{JN25Z4I{ftP#cPkBPyc^%&0UhTV5}|vKLR(pViiZ?{LK75X)gIE`n&4leearW z9QF#)^zdf!zlCo$C2E8LBZ3_(I&v?5yN}kuu!wBk^tF3UNQaoY;^x#LvIz`Kc)}$~ zXhtf?%o@ZW{3~>$gSaR9YMr`43s|gjXcI**_Osrap%>FU-j9p0W~S#Zo94Q1a%$!E z=>>^ov$<weFZXb#-xHS>tD54Mgen{~>_G#`@<dAIQ&`^aTS5UQJ+9hvEtNp&$8Vd+ zTJdaTzMO<6krV9P5(xpCMO1Ad&a=Xa?tn@IiMi1?h>U10clLJ2{J%Cq=<y`hz&K$? z`-RX52-(#`j5e<6rv3L)sm4jQ*;&pg-;!#V7IPEdWApWmC`bI?@gUww6ZfZL^50~b zx4&tqZjxMx(M2X$oTrl!$;NB5Xrtg*`qPb;&zR%sM|qtEAf=Bkc(~uLB%io^=bjej z_Bg9t!S|+J=$aXNH*RMjo{S`b6?tZxQI1^0kxy%4t|vH}eE3V|Q!T*+k`bSWf=9CD z<wR{AKnr6OvQE#<oh|aaTL|4PetCOKK8alMmBfV(#wtYKATm?ScQs*+sTcyEwWf&a zk6mW;Hw0^J$4jk@5e|H|Z<7rd*Qvc*eD0S=oBGES98yk3SCkhR5<U_>n~HEsD@Q$x zjCyb=iRHE?lNK-B!8iJJfz||jOf;Au8M_rh5XOsfi<V+hy!@x}sEpLy&docg*Lw`9 zKBS+ZB$39%>MXHg_~cXcPF*OMn^<K($*%bQ_y3bf=FbpzxP=bIl+1j?aVzR+S5@I` zxsO&s6L$1xmKbMXHAs7$tQy)~MaIE6F(;!%0^%L$UK!hYbW(qJxU8vMim{`8KZvy3 z$6gxGnL`rg&^(j)9_@NoF<w3apo~o%GE{!KbZ8*Tt^knXFNG7&nt_~Nax@?FBt`WF z9|anKPySeL)EQ%&d9nLC%J%(6bos&JEq#FKOTT-2Q6OmwpT{?aci1KRVi!95q<kah zu_6+c^>zaYS<Y;_VH4}M*95OoO?Do!${y08w6EXZD{S$h%>bfLAH>vun_R`D|JgU@ z^GY-(=KkQ2)Kte&&@hQ;Bm6!thYsfV0c6pSEl<9=L+0Bwa#uy6E8&iugY6e+OY&E6 z+yeAR0~lkEwnyXJ<sQdf8sEiim*1swYFS~K-a?y91>(SXO_?l}k0;mj-&9HPP3Blf zfbn5TDwp8Mp@q$-y->g+z{b$Wn!4@jz?Vjh(~yuA8C129SdF3vT*f4=5OlEV@uA`a z=ZUwB<C^T8B+AMj<b^wm$qw2zFZVdwUvR~jnaU$dRRq2;PF2M#KySfu1>I2}$EkS0 z+lu_JAa$Q}i%LA;UG<(AW0GWx02_~<p7xk`xCmIB`V`+aM?5@Z0u1Z#;FpINBv4}r zk5p4HwHEiGi*V#=`s$%=P@b|2v?2*ykTTX6iOIiSsm-iEV}+tilut)?3~UtS=7w?p zU!?F5>3jPlH(9g=K)zPFztps!{E6_7n&<h5^?>Eufru>F^6XB>`mWihTG7e7ZKN~k zA&h=FtyLy4?dN|d+DXSJ@u7{t24${u8_#nup)IJxA$p9j&7o<is7SJ~*2(BzzZ3;F zW;L)2awJ357kA|vJf*~vkf&-G0TPI1QPaKT##che%FpO{<b@i>BNW)*=9Nt?eh&zD z^FQ_OQmTI<E&>7a+k2=U=HmsD#>%Ix=o&Ml|C1n&8~X=A+-*c>!O)NwTz}ay=jvE9 zBzy}i5~GKoEnnue)vdG;{$R8aw7E9&V3w+fF0ONOzebEr5Wh7!wgfT@#!{>@3Mnr) zNtT;_D5<S50;CZ1OPG9w_7bTb_tT-Mx(Gc1iVTHkQ(*#R2LbK_jVK;gpntj(m6KG< zv`l==@fDBWvB&%@joMi1p`iU)gNXQr87<Lg#g$25(NsCND1rfIp^Z!@g)3LYUxfr- zm5|56C!e9|RxefRSww;h1U-{Zq_P?`g*+<hhMHaT#<Gddf_!BgE;Dr!=5zU%s#Dxr zM(#hCgZm6!8p!mMcFv78Z%R<sGO#m!t(Cpn)Lp?K^4B_?amweS9Q2+C?k{-Q`kn8+ zSP@duF8LUh`IuJ6-G?FqO~31*_MfWsihWaXvT?NZmZ8h&kqS&@8t^`S!P=RujHt}j zYJb~=k}aTQGsLL!SF}z^za(68H$Sc|pIYug9W)ZyLAh(Ed%a3&XFRDVu=?t)XXy>& z5z<Mt?CRJxXhN^s_-Q?b#n>|%(83r3t1iD>4_n67TRR>d6W=f*`X^<FNdqk@vAFF! zb?tB4n8S<RI<`GAF&(h8{8^|q<P0oK!dnftHtV8kEW0r>GyDho{b91jRlJWp83xTq z`+Pei`ogUNbp_}c7QPAgh9l<X?5}Mw-0eTw{2r{e9*!*Bg(Z;zrq^cU{~yy!sD_BT zlW)CNL<Dg2bl@wmKIU;Ofo~#AWD+7<^RumMjpkB+7dh@vrO*;Kx%8+q7=uz5dQp;^ z4)}jqQ_vv)ulWLn2LO$)U7_+pudxe1Pr~u&q~pR4?}aF^YxZs%579bnkBHlzq78Kh zSym<D*u&hJ4rlR+LzZqpc>V9xZZXntkJ|OUrvJcwGQ<*JE;M;#W#iNBMaOsm88m5z zhfN_QzQJ(f-pVjH#(jDhQ{E6C*{bhVKWe{e`ddHq_iy^VF*H$*pb??tWqS`nS{t8E z(%leyJvkztC*E-b9eKM>N$sZ!b<q5FRTs#4<pHqPf#c!WD6Hx@*$$fJ;XrDM16TUi z@pg_~@BwBR(8y^2D7VIO9h=hek-?D|TvZfq<%JAYty`f>u~hT5=bf!%PorntdfxE1 zzXXs*QU7Js$J=unGQNIhO16nyS?Qb>Se!)VAn5`c>N?&1ehLwJoj9%vL(=1$Efpmy z{n|)zEB|~)-}2Qs0WrEU*!UWC<LlTAOlp}p!}htdte%d(k+-eLItT>I1M2!B1fv`h z!Nx7CK|YtL@0vFJK4Vnn3fKgiPOSYMB|>*OmB+S1{DO1d%a2e{@xmk?Yrox13YR~N z{^&?g1T-)Ih1Fe(Ic0Vd+<@o6UtJka?Ym|2?Q9ydqu7DN$rK~o49ePCz0?%`nuy>) zlAqs(xZ{qoO-+0b>mc!C!n9E6Xt<+G&#xu~FH&j2h}9Gab7)LtqRne)^gH?W=@$D= z$;%oy<XJe<?*e5#_8G-xLYBa}ZN1bP|Mx)S%ENm@hE%&50jKSkL}3L{J~%g|<YnWh zmAh+FiPK>DPj5!ALL9;x%pHY4G*Rw0URix(nh6Y(oLS!VW{-R}Zd;V#Lg<oLVzrq< z$6zr4z_SeDu9CiWwhIuWtT$dv;-+=-e17mFZG0hvr6Lv111|c97*?R|R1QPC-1jC0 zM~ixyEut6f7>7y#DMj{y-4}$U?5yG3|038hcGraRwcV`k1^~hBymR?t-b&+gd>zx_ zRf|iWtCHo-cHU==Xp#E!650;DCtvBxlZASzR*OFOONrd}d}AaQqN^C9ZL@XXT<hct z-@5lBZ4HCX^nL%)13M-(YN$KjDgGB5@VmpnJAm>Pz7DC8+DdjDQUkUy8lJhoE0?Lg zyC3{RvvKc&LtfRm+J0=GRytzx2U{fXl9QEo_bXgvbX)@-;s2`G12_H-;m2*3<vt?3 z8K!#yb<Dr%P)zy=J`mf4c{?Bxn0}a#)kGEQl0tY0=S)X)^tU6Jjd0B=p8iaGgzmqi zf&=BqQ!cFLKY}{h^W!6%EaRo@%|{QjRx5ho&Yzd3ko&)R_lt&TvSCa0uO;?UFxuI1 z)%R|>%uI<H50ZExwu0={1QHa;srhEpH_dtjEN-^=W;Edpx)gIc-o$E63{Ck4Gwnf` zZNfxO;MpRdXo@5XzVyS9Jctb!Ag#uU-WI8TI<&y+%VQl^uf02dHqCKX6{S-*`PwiG z<O<;%yp$GuQ|d<grD_RT#la-YFl#&mv@E^o(TCN_{NvQIph(^=1oyDk1n+QVXJk)! zRh%VQSm{%L)X%vfGi6)*aEXsY`7d92!5~oS${tvMLc6oSJC>ToGc4sTx;ZtSsLWLB z>Y>FE+WSC>oF{nZ7TuauWh?0hdNtTyw%r^OcxBLmd+aozTky-+9DWf2mcox&p$}tA zu5G2NH5EvB50RwN;g_+L*He!y)|5POGNYi%4Oo~v@D`TmQ?zuIxgNHV%+VR0i=j~0 z!ETvq8hSmjVy36uv>K9351=3B4F9^R;bhQCKOp}Z4<gq$yM9Nt3co;}X5{B>X+arh zB<UDk&hNDFbfxdqx!pc9s)%u5J8Fy~;>F(&w`>^)_$7c#H=LpIJ9ojUllUga(#UN| z#&PU$*SW=7=g$N`h(mCg2_|1s)|i3E`M8k{DFZ=}&`shgku=tdpH+aE-56*l$)Ldr zN!>}?o-~LcHc)RjDw4}1b=!4lIFdT0{lz<-Frd~irH&%6+QIxj)?7*C<1DGht`cl9 zYi_1?egfVEg!lM=A_W}a33`haNDGteAX4zPi!)=BII+n=ey-P%)>VhPicXeCZF?#S zWuCMNuhuHYxf;iQPoHnnK=b;dUwx!YuRqiW913p)1k47bes*8uzqqjRP`GaN^XEz6 z-#xYWD5V71O`yY{+aLZqaKIGH1Mt_9M1{cF7w!hx*`C$UGTww|p5EAl3y5C)G=w@R zxA+Q+Yu`-F&RRZgBhwxm_TX@+pzD}**b1?z?1$l0(Wmm7Hucq3{~MKC>y2NzxM+Eh z=fE!7RtCH`1h!|dV<q@?@5Ht(fYK3Lskx`8&)?SwG0qDCya<IztM`}!3m5R>b&2sw z;&$OYPHr3Fp{Wd7$1}2g<H1dbVd}LGY^$+A_l3=cq-FU{iUZJMtrrjMyx#Fc>ABY( zyFjHEr(u}%?8JI2VqSNb&L&5~wNkQ|0U27*yORIb9wlDcKzfGet9+KsqS-OxPsS)D zDG=|V!A}#(c`-1fzCqGf_A`ZRzd6DKFS41(y_DJ}Grqt!Z7-Ghtqtq0qC1aNL`hc^ z8K*@7<8RVzJsnKMTQ|E+yg`2hS3;#^;S+NK0}(h5>kFU!$-@e*DC5*JHV#|<Sy2kw zTlLlVo!HIsp%&C)2OdCndb*t6051-avZ=euHNW;4-PENcleuAH$OT%^-sWiU2AV!^ z;#wR<#Q=;ey?S%uRT$^DF4EWuR}%+^$AmiA<ym?)L}$-ih<Empoj^b_HxDWCvin7H z0yi)|b}Ip_ENj0K1J+{1XSI^)<kO;VHtCEA6dnhDpG~#3g2yGplYR7x^!#|<(VZKo zjp3Id-^CHkGiU(9aVu1J!b(p9#^v?0F)O#IcDNZjUlnRTxF&s@Fg}Uj?ZVVv?e%R^ z8i@hHhrg2&z1WAuXLqZ@2)DWHT|)>I$od@U6%sF?z}35*AuCz_m@0>{OC_*p7c(}p zzcpqJ(irX`d7%M_U>j%=HHm{t8Yl-k*lXV%9LG9bm%W(g?+n8=Cct2=APx$wCbOn3 z$?!gtNY%ZOMKWYWb(U9SzYg?f@@!dIz$h$snFu<Kym9V~JYK+a4SH7ir3e5I9v<RS z)yd!&?xUli6W0?Wn=1SXT=gU!#MAB_kAZDZwap^6Wg?ETHykL%sBJm9%X)EfF1)rA zm@QzEeo06OTwc^4jlgZ4MJwtdeG_(DMj=eIs%|-rmsv5W(r)IHX7?F+_JkvC-xzoU zW=L*5ksGFBTmG9ba!)Pjn8e8Ib@)^h4$f#~yaLgs;|aXq5JHkaQGhXmNS(9l<jB8J zPKfO}1$TKkH}h=ig=z{++IB%Bnf_Rt<*@Kk^<?O4FtYDi8GaU(u@QW)caC{mOGBXT zu&2@kKlL40-lk(5*{7M{C%C*j6AqW~?nUY7?-EU-MuwAd&0OcQ-w)B9B|BJ`)ZCr| zP{F6ZiI)_z5yb4;Rzh9(V?_3m)p6BGCh^LLfG`B@C>U&7LE=9xiC-eiv|u4yIZLi% zh-wL9)BMz<R1jS%rrCjRS9a(Rtq!a>#c}okyf09;kCHlv{WxS`3naJ;Pfyoh>{Izc zfbO7P5!;S-e;Urx5PkRTveL*3JpT!G@UPv*QF!*MuNGe$^7H?$|LCRLK~+~QbYsIL zD|<<k4hnCcWfB5r<(-wi)I&dHE7gd8LwH9=vRVV)2zr5)Mz#OyS(ZFIxVJvcCh&zF z5Yh0kBW+%VR&>+v9pl2(lL4ncyhF-EIiS5sPRYZ{@bmo)r^ng+ScaUwAoabt99y0g zYPJU%Iz_ykD3TCPBfIsxwq^n(PG?fVFd2-thU{wd9M>`gNQ@Jxf(Pw((10AX`eGXi zpIE{SBvDW&bnewQrPD@!Ckj_V`3A-4U+rm4@we|{nt(!}={y%(5qUcx3-$h4eTYHA zQ2OE@lY|%9ANQuy<U6WK14&{L+ZsX+wM-4)@zU()^!}g-fPy5w37lrLBrm~kX`8Uk zDNX(R%l8a+Rjv<E)=VkQR#Zk)%Fy{xcYbBl_;*FbM;(A^ePQ$~3s;{7KxxGIe)n<K zI+luBCRQR0)SCauJ}L$%m>%7}tpI{Lgg^6TFTFOaE^nCPwkcb97JQXiO&Nb}D|^<j zb&PAy3Qdp2X_G@W-fwcpPXD!sDRS3%Eq0vV5*#!ShXRJ2>qNOIK<>rRO{(y$x9IpE zav}NrCmVy&+nx~K%l!tt)(=Kk$~h?Hm8eVQ{w%(iF8cCAp!pFF^88M>FR?N9EM0=s zl>^7MwYMhe%#fF+h_DeHqavf<<Ui8WPNo~82v6O^i}P>k50Q5&3Giqz-RB9sY@A7c zdkT;nKxgPBRr(>h8t3<<AF`q%=|3syKba3#FTHhM+|lW6wJ%HQ(y8bH1nq5r;$4$V zMWNFfM@|rLM8Q-7K;^j~OZv3pxKIjE!QJ8M+{JxM-NUNg2b~$d5k)5Ow;BMoAws&~ z@i@`cq}+b_vY&8;+ns)esA#aUka=k0DS8w79*)xQC}9>+er~>wwAArSgC@eldLru& zfoD<DC$Rf~g65Eh0#zyd;*XoZ#2<Iap8$dTRF!l%VGJTD>CVDon_cE!*tP0R4wFc+ z9g-Yl(UK|9p7pJMMu0i9eQe^=yno6g;RCh0P(?YA7B4<NpCzLxvKMGqa*Xbwu@kP7 zB{RuK*r$m~;fzGQp`D#u$;hG2r+VLj?y~<=3DQY=gvMqM?-yL}-0o&`mRH^j<SSf> zXY3dbu1M`k*t_12vZJ9la5@)5so%G_QBvOe@>>6kJ{*7>!7=P#Zgv51<4)c=rR-5f zn2>GBeS@`td{}MM*>0CK$IbmN&TS+ADR!svsRxdg|69)Bch$ecpIiY=tMaQ>>%jBD zKgeZYc>lZBz5L&08gs{miBsA%asEF)bLMygGhaY!=jD>52ToMEZgvJ+pU08!hY>3d z_{znA5%2X^NLH|il&AC4Dh^|SzwV#NLa+4XM%gPX^%rf-*~h98wB8=RTs;7km3r!p zRT@;YRrSh>-CBf3UapdzdH(vS4vUq9xF@{5+dR;=a^~RcUnuE(DeY!oTEhnGtv`G! zm$GG~YYXCOy`EESzTPBcnTJllT-D7ip<Fkhx^{~f^jVWWhF6f-f`U>U@4Cmbuq(TD zD^t)s?Tsk|-13zCT_t4-OlSt6o-G2kkY~d}bo5VX{q{b%xv%yCRAxer8c2eIp$M-p zkf6%wIVWhNc`qD_Rbz-5s+jJIPFn3$D_Es~n%>43H@&h1pF{O~8MSElW2^<`pSz6{ zhpmIeT>D=Szv&D0s*W8r7(3cm%>&b4wwM5k^2ORqnP~u#x}Dd7U!=`}@4vbKfiMH= z;AKPoJ0{Y;B7?givGUc<@$bRts!T}%bSM#DE$E&AUe`5~8qq++6df!OQ;`5}ZbM1O z$g;G(UJAH)>%rVMNJb#-g382X$k*$?*2V#&-+8;sKh==l#n|XpHI%vsH92-rX*M33 zrpx8s32C@E_j<eBwFr>U_EZkr46ofDx@IoO-)pq~go-$KQ?SDI!4Dws<N@rzd`7%U zUU5Jh_KPzi-t3=#drLUeR7_Vctc3#ftUdSD%<=|q*>hKXf>+j_BG3BrbsQk%y+N|u z2A{&Bc4}IJlG0XR=u^;@FE-XrCra{jX5QQ-k^tY?r33w*%gOv{(aQ*d_S{~_w!xBJ zSl#Q?1x&MRM`(<g%YX*c`F}3asEDm}a^!T^^KwKZzWVJ5uOEHbd6)Tl-&075R;+V| z5^6nm<MCIkqpsV@0u-3l;U&fkK_8ravJ|i=3(N0?8z5UM=P8B&W)%CmMYbd)nE#A* zsWj)m%^yF-{%de@<l*TDoy6<QL=|~-CzQ8sYvLBM!Eh8Ii3FDhJu?QnEq)}p7AdL- zJzTr2+qYY;oLTFfx{4P6V80v6^5j{#RTZbtcens-2i9N6%znQUzAyDUuwNn5(&E>d zrtq>&J-sy;)fDBND7}ga(&9dOXt?ME@&0b;!&|N|SGLPb<6%B`vI_<j4ituyp;FH^ z-vUO3@C6fLNqGTN&5g%fRJ>}+-NE0pWR(RlCQ*g6qp{rH1NbHdayS~f3+Eq^az%?f zqHM{Lwtx_|<j0#POiP;j>^4bYMrkGwip+i}{l00_(|PRY``IEY-g+Jd+#b3kyqm*{ zKcI1mbqkPMGv5?!47DsNM}g02y%J8V0<D;5{w@2&eO?Q2;-GE82MD@cT&z4C2r+6a ze%pP(d$)A{aOga@m7S~OcybffeZ#&0k6z6xZl)dfm$9Zxu-n^%*}}>hY8Bdp+2i&6 zOpU?uLnY^ymdA&~I0d+noxno;$mGuC5cp2Tie#VOu}OS(IMf4|C<{a~FEziTEYM!B zY>5_B+(p>M#C!kaNnVj<P?$C@m1GZHNW*d<-C99f)R}Dq>gsABe7#+C=UJZut3B9h z&5cRY%{Qg6S0}U@<v^l7wFnI47#Lo!6&vx)RicnF8@&Bv4fvrqz%z2qIC2-42WXC+ z>jqx0vEE9b_mNx@^LLm|+L-<Z8Xym=d0IVo-X*4<vgaGB7*gi`+If(<B}9jNQi}io zG4`EdO>FJjZp&t40UILHR79kSih$JE5CH+{O+W=fx)K6}78Mog(rXC47cms+TdF`v z=n$&Z00{&L1VY+3fcl>IT<6F4#~+wvX4b4(^Q`;1%c=&-^ArMbMRaYNF<y@9gP4F2 z*C12-e&sdn`)tbDfO{~whI<iKMNUy+)V7(0U`Bg~T&9?zu;mHU@mmmom2=fvb_A05 z^czmEmO6=>WRJX(vBnTbAyhKVUve=V#KM88Yhs|y0)UfsFTNCY+;naFp99}@|2ajn zIdbtONXID>Bx)5ZG38WjBLqAa3S~tXVVcYFlM7<7@`tkE=T1py5Bb|%Ub<3lVA3u9 z`>8k?&8y^I%zze&Yi`f5!|L1Kx5ThZmwRQD&@DrF`Roa_CZ?NLRmmnP#K*#cXT=3G zM9ge4$H=&Orj=0WA<<#gWtS=754*_NuWYG(=PSN8;^r`B?Fdfn2B4T?5^adi4x1j9 zt=Z?~6~~4s3oTbMH{HC7N?MPE)cOt&QJa&yY0oxs-13V3LyMCwan+0obD6r5CcbH4 zVLJWWF6Xl;b`pFE##gCzmt6fL)Pnf)N~0Th#rRlAC!d`I6}Z3I+z78McfytfW@w?Z z1%0lQKLIw%$ZatQlaj8jFBvxrxksc@SIjViu)iPwv7d1|^xUSR-~PB#HHGxUr$u>u ztzj{q*tvZE-S|A-y}%s<lkv$Zp_~dSyew7jX@?$?Q%E2>QLLtsVKUOtoDzoCIsWR} z)k;wzz})A`e@5XsKy)7z$m|XWS@Yu&p7=ATn41A!=eQNRhPJ|6E(7PJ!Ih{$F5ckt z+=$!+eM8f=ikUxA5Tc_u0o{`A#Kc^zP6GCbDVD$2fJ%rg%uNy(+K9Vgidf6VGwOyN zL&C;;x0-xHv=oPoHdEiP=K3>gx8IA#)In-9os2vA?SpHkMeRo^t<la-V&JAS;J4%+ z{4yZ=Y`O^$kKZkec{_y)ve&p$@XU%H$B=%aQvoHiW!{V1z8Uz}Mgm5CtGT9N6a4K3 zeb(92r(3`YX#8|t|83DTx_ysP^CMLz_*+p4tuQ2fnp<>i%!rcwzGQUC=F&$@?R2Z< zM?P=cObV&V)(MDw2HJinF9V%|UieMN=d3J605iAU?cWUdM3~|@-1YVZU(BEC0Z<V) zQ=P?JS0IhWwqj7Q<-*9hj?r!-Yj20q)kNS56|X~;mS({+wa(RZ>__-2bUy%^3Lnkj zSR`uUcE7vP!sS}~PI<A{-YZV+GwcpJ-l@5s_6F6{8X<hMW2%mqGtiG_59Ni(6svh} z=E?YNdJ0`$0p+&|6F;1BkP&`ny~cR%6{u-nzmW9%CAl4R6^F@GfW4}Nw~BlBGe4RQ z8m(uwteBn)l4>nXE!h%}75a$5)p;_Q=a^oWbBXE`U$<9?u)H3c?CDFJ4?36aYcnxm zbG5kM@I2y|p4oQ91pU0?VKk6b4v+Ru$z6pUp2hgyPduATw)&UB4WGqyN9)erXG186 z@^EDngldledVc>+(FgnlzlFOrVh}3Jl0_%f6BA)clyQQx8_hG+GDOyiQKCCnUsdvN zS;(PcXEBd^mfyMWS#EU-dAuc=Yw^@9Zb3#@D8<apiq2)`6H=J^_^rGKnrypz;xq+J zh@Mg6h3fhEN25Cs)7s!3J!;A`q;=*D%8_K_qmUpi+6yexBLmtMF?_eHSHT}=`qe|= zPi3CX4kf+cPZ(dvQsVdp<RzeyX(N@3of)*srf);0Um91cz<(w*peN}KOae4%K`GND z(g#du36>S?2;Tne%!DTM-~9Nb|Evqd@(24p%W!V5H5{C83}?ZlZ_d=$N-v@}E>40w z*KCSQWh?0qR_s()NpU;l`2vHeU7XFeMn*iJDFDLZiJ?#MR*^}wB6e`na~2Ais9s3I zz064LIeux|rQt5?@B8|9;Z8+xaA^*c8PXZb?6Rp-7<?<^JD;!RJHM5!<Vw5bF1A%T z9aHt9Y}Uz)G;Yf-9mdGsWb&{g64Qqn+?E$HXC4vqPTYKxEPdVl*jUN0ld++ceBr#0 z2|U=v<uYw7?5Ma_6sfASuP{T(0F@*G3x!>l&aN1eJqZ%xxxDt#;^dgz;j8s#AA3(! zv;Q{knlUiH&vU=atPR0&XT+w?ft%lvo1cRV><s%E0a|8_kFA7+$iw7ID&Icb8s#~{ zQvnVEylmR7-8ES=F*+N(235ejKVa2`7^E8s@b)jru<?o(9+%5xg2{83I*)z49mcvQ z!mVjDFE4<Bx??qPq3Ml`i6@VVh~NpQ`h}X`L$n>BBk)|pd)a_7>LTVn7h{gDSr<<) z@|aF|xK*>IZx4HkFV;&0VJ5Rtlkc%!Ww<g~VOK6L*PZ9^#vJAj=@_QK<8o4^ldQ+5 zXKT7_>K!|^+iIMYJ!4dEQ6s50>yFCH1K}of^Pb`Ce;D*8FL3{w6~LSn%N3l$Nir^y zxTj*TJ55Lg-}^=VJLF~*YvMhLTgPN*);xgXYIoQd>nF>c+`hh$2xapTah^EJeEnW| z(Dp)~g>26@HomKl`2Zg$b54TguM(yXc^g-1S>d!#M{hnp*yoqr26&Ctu?JSmNP~Re z7B81JN%0?xzzI5=_{>)(c9u1kKx0J!wa^LZ!Dm52C(j&9$**fvixq@v=7+Owbj^#& zkn`c$56p!HVQvTJGqz-%nYfpCAU#PL(MU4P>GfgsFB^${Z|>x;b$weeX<j7}AoKq0 z<IdxBw(YKRi)DxKyKkM()QU@+;4mc@7eaTQ#H;EIo`tyZ(X8~|(IL|sc?v0Mp9$A% zG0RRm?YqZ09z^8IUhO81xlpySM#9<s_N$vQfIfNBp?zgV<C@c&m5d45%O2I17-@2M z6CL=zrxMUeM;G}p6r`Ycowe5sx=IZySNmR>FJ0BC36%>00*8}Hb7(-y{*T-RSm<nD zEh4b_$Fh2W;P7hW?@4;pWOx4xNHD+2YMpj{?>E~d+}w-%9tToMR+vwiEk{3uI{i#S z$@<)F03SW2qLS*`r7W9@x;3lqt0|T=ZfdEyKWU5heW*3UrkPv5!YqfLMOq!i<5`aX zo(eO2a^;((kX6xS)7JKI<7Om|51<5Q+5@vrjotU2)&++|5KDepXjBIp(OV_GIlof? zStrJc2|f5e86WR<+Txd7Z{O3dJu0HWW?|4S<L|ex-LKu;AGYCd6S>c(|J@4w&#V6b zZ$tmd7hu>*a@&@F#75{7n<Vd>nv}^?DW8F+o_c(tb-6W3y@%<@sPW(o{qV1X^^wFv z2kEp$_)+Obh<|Yg|4t?Ti@*6FoymG44Jwbsqs*_#moLISVs4DI0J=p9_h+l@iG@yN z4x~TI*P5IF$T7m=d{U3J-hCP{$Mm>XJwnLHbH6bJ$l*DV{E16u8=5;mf4=(9m2gxk zUXGJOSx143|Dv0Wk#MQj_VIw%p&D}4dg8_i(2Rw~NRIRpG?31&&sLjH+gn%yT9k^; zmIU}SvOd5EoHY7J%(5Jbl|Wt1@f7mwtg^->jHP)o?$cx0c8>KJwmV(SKD`yvwEt$U z$v5cKQyP%T^FOJIibO*`Wd8Vrh;g7#8!;Yko!+<fojX7OqN^`#@g&-G+(<us?6cFd zvj&HPmb91Jb;4I!5Z?spC4AatvGnnMLlTZd&)BE_@M}`C%hONj*B^%5t1?LN27M?) zAq*S1ZGY<#$gobc#WJMNC}XH3VRP}dHG5+1i}F~;+)fYZcIPg}5_OVRb#Vc#^RI%_ z8fqwbCQ1%*(kWs)>Ncj!+9V911gLAU*548&KOa7UWXU+CBYhk+wH_lBE&c3n&%5yO ztqo;s&9-YozTa3EyfmMDDcr_k1W@JD0H=)$;<eH;ZLK0)y3VsuGaEuhq4n$r6<MxC zR5cTRhJIZZc<$vCYNM}GYg-Zmk%F1G5umdemec=C#puZd<aZ{!q3Oc<2C!08CmT;R z4%1mo_#4Teu=KcK(4CZAX^!_UqAE6W_SSQQdP)M{w}A7rHAuw15bMo(3%;G(kh6zI z0TP?OJ%A?E%^a_Rz#T-FaLVa7Xy_nL&R?W}XHIX6!K5{u=5Jh1*8ZYrLjhYg0z7u_ z#sHiY&<uF^S!rkuC*?oF2=qzrWAf&|PQ^A4khZVD7UQj%Hv!=Q%XZjo@#7n`sDzWn zJs;qm*;BY9(JXvLCU~|aCuwyYBok)d`T8ri2>mWG4xUoZXBy9IMV9K6)eqQgg=d~I zU|+PPDTm6)cM{wwBpYYAPqa9H=Hjv+$3N`7L#9%g*f{!k!l1SL6%qb?OR4Na_|kFG zmG%+S3p1ze^6^WQ{Yc^>kBWRG=Zz5qDt2N5b72^Bk?}sHG_$j_yw65!Rf~BF&7-Ta z@v(}lWt+3I65ZMWHnE6N>~!l*<vdzHD;Sw*`<mGH=E&lp;COOaUov}tEC-MMJ;$d< zmMFJjm`-OXe8u-nmz)aKOX-fywi}uTeKw{}&3pa6LX-5$|HGzb6=HDkkSngBP?m%r zw|AQM9@DPZ&W|T<^(JJ0@h*pd!`GxkmisUPc<)=~h{iI6GM)9vLJgS}VR+3(N!%lf zOff~~qD$(s9L0zQNHqtzfGbnXPMg2mai#R!YwwyBSjNsx-DkE(X1=!Oh*6Kl0Sa71 z<1=uNJ?|Bql4^cx;Q%4(sY0@N>#3iBir+@t?y09|*5b0Ar{^QM^s@(q{P>ezg63~{ zt@=(q2WMr&+E2*_^-NEltKcEFA>6sgNiXYd4~w|3Oq@+kv2_HkO3q?nkG)Gnd$P5y zCuFGLEnUHLMKfQZ3+4t#=Fv$`WFaK7|EYARtu;(PiJ^$BMw#EBMjuW@=zfuXM8RDv zd==6jQG0ia3iQpqWPqrK9PHoLu_Cy7ld!5pD{`D1dx2wlDS4$dRLQgrN>Yd3^Y>DX zE|Is9Z{Kf?xL(~(2(zw;Uz)0~%V5I)7Q_dMyr(6T!O>(=#zlJxb8=FK>86@SbuU4g z{=riPx^<Y5bf|OS8h17rY6|0m6>U=_MBkyGbLm%36x??ehWOcDt^3;Uj_Vb7FG~J* z>-rMZ?9hUYEympzqa~uq$f!2~Gnri+jH0hkoH4zpb;H(iNBc9k-qyV&%KJPHpd(!7 zFzHcQ<C)z3rZ{E&mF1~*P2<OKE%bG-zDlLYzFsfKF*Bh>1LtuMCWfGhoS;rn!E&)> z$R(?|s|^Qzq`#s`laMoy%e~95+I~S~yYl}%L0we)(JGJYuVICyO`H(R&UdfTBpu`Z zp*V14_`w&nT@@i5ayenC2r_kM5N5O**RT})eK*}eFKw4<V>C4qW5^&F+;6qu(lyv; zhV}uT?3adQpo5r6L1x}8{`91u4ZvhfxG{*%`p4m*2bv-$Z`mA;VKHTRH?Jh~GK|71 zxaaDx-@nkmU$f(g3@lka_h*0_itll*<3db#`sT9!%_^7dAS)Dt3FvH<KdFfDGYZ~) z6Rx^El6MzkD#hh-M>uEjA>~Rm41)q}#d8xU?KnWiDOFu`jw;Q8W}dWdjJEa2{JfTM z>&QcY(|f!=oNaDVf+)0(^eyu{t}D4)?p6L|(miGRxG!0^NZwdEFF6v$NY5C<2d>zT zu}awD?l5ZV8gPTB-HECBV^3D(#<(p|<+#k#9TOSTSBr;DB-lZElS^)S2kMPEZ46-; zixtU5A4p_PULFLq%19Q<;qwp}V+HjVJ=g|I8xDTLm44lX^A#OqirX-}zo@NC7z{pl zhHLZ%KR3q7!PMN*Rz3oqUQZRxYV9H4EZ2{Oo~YWgEN#Q-*VN`t<a-PIyfF6oFf}eG zLBV@pwuM7Zf7BXKtdAuli^<^n<c$T}@w9rqH}w@@b9s@Q$%C>3S?wbhU7Rv4^@d}X zhw$Fx7B-eh__{bI(e+Hw%e4ble+{5W$~#Z^ZT>y1_ViZPKO64AgVEK25YPtKsH+I6 zRqNZu9k#|GdPV%HVzA`!C~*v%MbFON9p-@v>IjToydL@l^PrkuYF=n5Rnwax1oL(B z(8^teF7ZJ)b7AJagp2x%$;G#GT|0z7^Aw-1n!fQPm_qUrNm10E9NM3^G-~9SMtm$+ z5$CdiNE|Cl)4+U`TLoF65w*!@Z59LJ3j`a%Lvi&6uQyD5?JB+oDiaOY2k$V)XX$xA zk0gDQdJVD|OvUKzUoh6@_~9&~Xs(VWs)}U6Gv0K2%|@1tpQ{$W=54~d($mfX%3`m} zYepJ9k#z3Tm{o3<NT@CHW7F^RetY-}sPJA*A<^{!6Dh!ft1AlgT9OZy@v``fF-S91 zI)U$AJ#=VpIy%TR!J=J8e;6(bQ_^83KYHw48@z2IMqnNvQk}2{gKV~(3o|tsV%|)# zbo;Fw-y_#9dM5G23~cs4hx5|uNee`qQeWI!1cP^lCu@W%BzMOdeYb>kV@z2q=Lr<X zE3^C<22Wp?2(CbXErIMmf)}kbtEZ=G%L2FQjohEx^hv?unykHB!`#pC50Ey5z0rR7 zbr{?5<=B2^rQbJ*8o_VXGPBG*^idq2`Gt}m`5RNGP97Lv5FRXS7S7&)U5ywTl!Y-G zSCU1#bcdDAZSo#&-QalTlv33>!U0|~5))MiSPe2)?h>|6_-E%=w9INcE?(j2tilf3 zw&!42ZTdtPrN7;oocXFY#>`l`Hox+Dlj29Rr|0+mbSJ*jsZbMhyc!28&N#oS?08GO z3ZbQ3X_)8Opfo93lcq#{gZ5!<{z1&EfzsCn_)^ujfOs;GL8v6MIIcER0qV<vswmG< z@+#D6-6;JjnkTAcMwQi%U&%e}B4KC|PH(KgO8F!b&)-uimiuy(csNq#q1=GK>$XsS zAH~6pMau@mKWaSDXSq0B8)RTA6;sStU^>gE&*?R26O7(8w0nN)2?8Lb)B|Q$kGkAv zmT;2o{uYC?8)RfU%zUCBT9~hSu45LE_~MF5wJUO@Ob6c!IL*C^{;|z&r3ti!%4wJ6 zc<!)3NlEWLU33gXYual}7tb6mM<Yyy(tH3uy#u%8^RZ~jIZXJ8TrEu$V!F~j2*^Un z7@K-Eg9$*dQ}t>JpZ`RN#H}^pE{KDM;(?C;Q;azgYs0a>cpha72l1yQj1Wb$6(4mw zeE~djNDYe-K8bE$pKS%|M}Q=(%4@NOo-U&;lXTb5AbuRvpPjfhNHJ6!W@<tD?5*d| zPb$Jz?2tC61Cw(Ou9+);XIa=lmQMPdR%d8B@{cM4oiYC_`xPx@TCSseB>`_e&Tdwx zY&Pyly)}9YTWy3S&d4l~Yq-+gXS}N{p)f`uovw0~42Vfww|#vJh6x{B&FynYC|Q#w z4zqFR*5rc#4V!I1cEkertPp9^KDXz9xz4$_m0O!V8eu9gFW94)3Wftz=tYD5a79>X zM>L3&SpSUCPm1VgRW){MVQ?>hLU<{dC-c_*gT*7voX|YZx6M46Ap;s9k)9FQG_+sQ zH)FO>5@6#MES#Cm(WP702f5kUyx5qC%hWt=nD-G{kY~Qh?q3C9Gk$$++bo`*V{g%d z?TH|XoQR*?u4Cn|w;fD50kntNa>Op8My);Rkls5l_{kqjjqptQABeDSDR1TY$)S~@ ze&UbrgiTaa2gIi?TVnR8&&I^#BI+A+V`HDx;%<vf-bOEUGzez&ea?Mj9n}awBM2aD zS=K+)7paP9q8Tl1*dTaK$XmPBQy=DjanQy+J69Poi}9yYE2YX2ig3CIZi5RxC|GsD z!oY2*`~|=Q28d;2kY(NJa7*1``Mq|~ZJ741p6tp>=cU!Re!M8#;u-ENgR)%XZRba- z0Vz}^m>d5}Y}^cPk*RP&@Ew3yPV=LBn6g)Wum5`Gz9+LDx*vqE58ABy%Y&UO7zBIe zMVHyox-v))y_-P+^KCS?pHva$)u3WlsB08IM<9^nI<*iRtKYT&ao&pa6n@m11d`E$ zLZs5S3eWK#Y(^Z(<Jrck1y^h|(g0heP1^TXjy9)U(BBga{xqVi`O@TFfKvF<`Md9c z?hR;|ou|J|2ZH_asE_~D_A|SyOMIe1PeDXsgo5s!dB(Pzlim|(AP6^-r_79qT)vu< zJR_0cwnAPUgl94+BftuxS6N)q-+ed`7A*@SE0ui#x06I})ZVY(_@)ihP@vA&bDk}( z!!B=7UTtlQ71kSs<yfeg#3VNVbEqNA4i5Alev%lzY`Ve3WgBy*{|9)*$9WOx1iEwa z-AN-IZr?}QXKc?S%F&d?E567c#y4dT#`&E!*Y|hHlX%BD6P)iL+Zgpot?rqf{(g8q z6MRWP<EWQS(-|>f^_Au!9vXYDE`Isa13a*unQ6wV3Q1kCEi2Xi<efK4t1R+d!;O91 zw0Z$Ecs-XIxKZ=SLy6AQr}a05^tXs7Eolln7}Xw%hW16DuBglU_f>zCY@@!j!kx+~ z6FB?{7X=9@QS$8`Uo-E|Gmr32J2_|^4;Z)P(*n`kRBO|%V&|Nru&T6$XL+~E8YoCZ zb(+9NU7cBNlpot!^Y_)k^$3Z0x(;N{bQ@tdK`=e+A+Z|SBSs-f=Nb5@GY8cR$1Gn= zF5&F0nNo?liei}p$(h$^$7V6(N$Kl@v>V7mI;JQ)d#*P92!2Ucorz1=tMiSmdoB^q z2s}xJ0k3QS`DNa8v`7#on=p%!j2>{B!i?(pNRRiyZhY}$!r4~km04nX6v<zf+rqKr z&o5Pdi0src<g~P*0z;JE{u4Y&7sDkD;?_Hk0Pbh71hax_(J$XL7f<x(7oS#YSJ*z( zdzK@=8lO}QspB?pHCs_SG_1n0#l8n-u>W=uvIN@ogq9zx{>L6<U#j@D{E)Kw$fsQw zSckuhI*D)>^J@l!J30|#f1g{GBF$l9P8SNzVUW7-@IOcW@=wH{!dlT@`H92K!5&(v z3n6(nPRUe`MUQI+7ly*~#5N9600vn2gDXQxDX(iT&J*;z>~p3nQgQH1x)7NpELHoM zew<A!EY~z>bK-1%3L*cnuOhGv)t(l2D#|(@miLk*mI;qd7|UfDdVxYHB6MES4~V<G zIawYANx`Gsz*!t91Wr2wOCxOLWy5m>eDC3WtJtcNK}d>za*8v}frFbr^Q`wfrEk?B zA$3Mg8k>xH$t16cI3M03rxv*}vBHz~nXFN!x{99iXwHxj7TNT^>s9x}0?VjUmgtkX zQDoRwnhjwPuzDxv8@J1XD*B0{<#hEq8dg0q>@gzJc`*v3ea$zv-F@@bR4>PR>xipQ z3toop`v!J!!M)^DU5eLwp;>`!_M)G?)ri*96Fyz0xQGmhLD!~Ne&7sI?>rB|2BbWJ zpO-LuWp0E2Sg+2jNj}`#aBsuZ&uhJcaFRI@qPP(|sGi8)TYMJ{9;nof^&w__1o3y< zAPi!o!}8sBsm^wL@>4)|FniN2S>Opa>1O7uC2-gpF@Aw7&x-nhOv66sDwu^ndNwsL z7R9E-7fYsne>x&=SMK+(>?+02w$jt;TP`FBGI}H#_@B^w3k#~%h5mpg;?_#?HK@HJ z3D3oZS`{zgoEIlulLev;cma3T;#^LC-K<i`x9r#U#)}9=mMzxQLDlm_Ken(}nnGub z^PZ4y15Rau=+I+^#uE8A*Af>4N<O{o5<lIlxCEmqh%-L5*Mp7kKKnWAnKeEpvQcwK zs?n+b!z{;p^GVm4`F|r8pZJuKd6KB4!=Tn%y=M%4Jt~KJJ*btcW@7KEX8p<<V*6b( zK0K?+81yeDrJE@1kX23Xgkt4wX--wDzNgVRf6){&*&DcAOAhScWlb!LcOotHKgL_L z_D`6nA`=S=eO3P2IuJODTv>b{HgJH&!cCLrR(sa=LCKf2F?+b}_#G|xWYDepgog+s z3ab5V>&&WU#Z3zbcx+TpHC`-do|-V^i@s)RI{jk^8Zu}RIcwQ^E?phRhrj3(ZB7S! z!{s+d-ap(@s9?k_<yyQSOSkv{td)NduH)2?6b?*b1R&?r`HJHMSYUR5W>pl>fK?0Q z*VnE3&GG=#<_8Y!wux<VAQpR1sPk@9S*z`pocMk_%y|^TKPU8c#yO{8a_f~BFON`k zV;@fh2*TxXl=UgQz=)6AwE|y%^f0l=tc%5M)>^r~F4&mJ>6o26WN(KF%0$Epo6tV7 z$vnc%n)4H<JGOCkR%r3g^c?7+5dG6ni*nMxb#K=M&Ktgxb8&t8=>~@5`NV?D<kudk zUi<iSP!L{My*%F;VH)e&JOtrOWk*LlV(!u52Xm=u!~H*Au@RS{FP5N!^n~+6r02sV z9q~<tFqn_QW<^z!rdvM>!ys*Yh~<VAOeSr$dtP6wK1tjT4mLw%!ts)^<)wfj+OgT% zd&niB&oAJWr>BLMZT<=o)Ir;iqgvOtK{iipo+-jto<Uw?JBWk3L@&r5Sgo^edIT8F zMO{GS5<O0<EdQ7%Mp3s*xo+<GR%XYisJ*PnlQEj+NjMd>QMcn3`bJ6jj}+Z$Ojb(x z?cdvK00R53n_UF$U3=<ZM=t>^HDwJwa*?Od&OQA6AB_q?ZF{6;YxLLA$MnlEzO1|- zQfr&l`yPWE`{|Z~^qmjyqbvV6jGgwIy}NH?uVncnQ<?V!Xl|Ju`EJ=xSg(DfI-X9$ z396Vg_hnG&b))(7?Yp#>Yq$Ov(G6Jm!mf>s6MT`DRbRIJJ0HaR^b?+Kg!yy=4v#7* zw)uvV<3>FW>KnpxMT_v=Q+gcz2Y22zYrQ{6!p(M)uX}Y63a*OPy}#IHk7`Nu>2N5( zas{T#?Eb=lgA7u*YHs)YM>Y4b<YVsvt||8Aj=$=nSF-J?j$2RmJd5Tq>N!wlt6-g; zZ;wk3xbEVpcaT(+<~7r*UgeKDiA@jT&aam9^V{7SCpYEZ=p}>LyAA8#nN*{69pD@t zMncq*2jsSr-J|*ZaWz!_e65v)12i?-0T&=jd)5SrApXobj_}oBtW2l$Rkt@qbC~@2 zS}V6=K$;QcUiCxA+BA;-7{{GNjkIn}DAb>`W(jR4;W9gY9o(W#s!uO$C^itXZVa?N zR|V`%i=;<V|E)c|bKIP;-9bu=cNP(P9{Ql8*7=Y`g-9eieb*7olY}eTL0U%%EQ`-4 zLn2Xb-Ij9-i0ks>4#C)gU6S-%QXT>{S8(f*?RW{}Vr#t57-5qF0Q)937E)j(wIjZF zqT4z*IQ6r}M#nc%3@dULcF7k=di7<Krh1g$L!}>d;XmZ3btQ0}?EMxiD7Tz|p83#O zeuRj7dZ@3F#+sOOl!~+laN8LR#N0yh63TYR6=S==y&!Ufq|yjBd8s)v;$X<@`F3bQ z4B#7K-!gjncHmgA@reo21-XHX3>E2~7o(#SB;jElk}2c8WUHwSH)Mqmuk{k0lpqN+ zH`1S_;y-<_<j+fNRUDvMb1znhVvHYej(1ygE{1xV`WV(tYmGEGR658T|7&bxQVp5Y zm5=qK(Qj(eu8lqYp3FHgEtSYgY08j2GC#~$n7HU}UH>{15;*))V!{bt);P$rGt`ey z?d^X~PUr>3*=Q!`SjqB;ZDw^&#&DZoGW&8&Wp`Gg+7Q{IYbHWI0LBfwUX3D90V{@D z2eN1gF3OQjD$#Ud{%`BScts-T$%$;8{`y&9i4@JK9VI-74j#9ZR%Jg!3w&NXi@K^` zxmMh1o!F@pxK+irnTFl4mbaE~zZ=*K%K+E+I|wm1GEZ+8F0HShEqc6u0|s)p2ZiMh zt`9SkbRh|bS2*g`KVV^x$30T8Dm2+6A~H%^+RPD=3&{@ToQTOV>k-nLb%iZA%M~lW zJo1VBoD4T#q*i>0u2zIpbWd@ygy;|{Qm%+o!b?*+@tIpD**m+)oTNiDSS12LX=;^d z(E#U?Pd1QX$poWmm6e$ii}~JI3!Ji9&fE)&mP#f2IG=liP1Q=E!Q#K`3Wz@6q-m$d zAVdJv<n}FO7)mn7pJ~7Nd8!o6l=Q+F<FG4oM?@q+GBpUH#tG^bq=4(iW$0M?#F$wA z{8m$xr6P{$+0d)dHMxD}BA$>3*|{P6AbU$9(7sH+St<00FZMG?NTsv(EhP0Y(C`K9 zI)220n5HMzJq`un^PR{ZhwNqYQu^|}>(GR3wZz&7?X6d27%FHQg`_rKWMCN*-fqaQ z7fJ^!yOBh?c{3a7YS5pn?fELAwNI{tYv=z_4%)oZJ=R3&J04wlHHBZnOZ0Ay$!xXx zxYrwO=P-s97<xJ$9E%Na&&Ld84z;!+Wc0QangQRQF%C}HowpRfJlD?WT%Z_`YRSxi zZ#nG{N7wRGvg3!w{Dh@cMdssJ^a#l}Z#B8#^dR8r3$iBKeMombhS77WLqvj{GldkC zimgVdnu!yPdxwj_!1i;&#muTayB?i2ymA8#G1pR|d^kLuNVPB=q{s=5t88y9=I7jp ze*HQXx!w$|ZI5jqE%tJP!RL<A@_;X)<?cMAR2^<i9I3lEVy-3gZ`m-Wn~~&KHW}1O zUc=;9W?~jbxTbjQC6NeWu#)Vo5sNUm?vgDWN_w)ZQ@lN~$3TtPysSGnns`ZQ2BRA8 zy5dr@|3Ble+nm!X%9CgjU6Pnkn?iHbiq7Usf4U;g;pi!?6YB@E1~wd5ise<L(rm7z zZWI*kBgrfd$Pa6sGaQ^;-Uv$`d?;9|mBZg~SQuP`B8eRuvoJirV66ImdPD?4HhGqm zw>TigVeMJ$Ei#a9sihpNCHnq}N#)eA9dZQ>cQ~WII5nE$%O(JD<#L9Jr=k%21^GS! zd0q8I+bbn%8j7MKGv2zac@>S3`cd+#Adh128w2Un*Jkr~Ai@E|HH96JH#ot1G~M^y zc%{S+KG<Kcl)dfj^Jt^7SOmrHeIL4Yubmu=Li&H2<xm0@Kw{Jqz96x5Ypr;AQIfa0 zS^TM}O9(thRtM&OImfe77S|{zL1Y>HDp#!1_ssHsPf6&?plsT#+|HDKlkjImwL^KD zey~168Zwe1K%Am)b{J8Af0Ct;Ec*JMv)7YdqAnWCa4YB@6Kwe?xfspCG|ztJ!lj(v z%fVN)r1gVJ`+g`Ymho`u!{#fwr*Y*su?}gG(txtZQ1=T(7unlm%7ZFKQS6ZJuA$4m z22x(i#~zS%s6o2@5mP)u>7nv!mD^_9->cCGedSHP7e7hyo&8Rjpm-luPTFOk6Dqds z#kpha?SZNiT^RYi{1&3VYF#jCH9E==lrk9mm_RF1^B&X!@VwH@URUQ}NZlqn8T2jj z>u9Uq{#s-MMc=Zy)?XA?Z~Cmv-AB5YQkS`ZnnK6-0@fK90`bIdz8ZS4HZn@4zocmd zgJwX@(vrEqLuWe??rVdTq5)&WO&jlB2l?9?dppKYUZ>VGemH#ujGfl+fdNp+y=lZ3 z0O9)DhYAln!9m30xs$N~2xpX8o?HX??!U;Mj=oofbG7~wxQ0tzeEZ5@^O@g@uiOuW zmQLd$SC!g0gb{r>0Q5LLSW43M^VzIM`a|VPi=KCbw(Pk4L#<)!QjW#;zWMFVGKYz> zh75(`tKH2a79gF8vTP&`sy$mVlHb^J$&A7RnGZ)N6<;<(OvKX>n&8rj!ZgepPGX@; zvXsRc<UEhV+P%GDax9Iro3jEglIBO+&bnHb@5taO0EgD2?=22|b?LF%nH{%hcUk|3 zn`*DuYMpu1ZF*XRc`RjlZUzvpH7@w3yoVON>!dfNI^k)Q+tF+0g*xN(C<1hC4s*m7 zp12-fn1tpS_&|eZ4D;5cB=d=8qKqF3ev=XD7?Z0(0IdMPM_v_C)mD%GJ|s90e6jnT z$oE>Edf~022vTuAjwExFPfsRH-*ur#H?Z358@F2#jnZfbd!1Xic`wQ0folvXF(F<o zlep>8&ko87g1xU(!E{$C73U4Q&ukOs-2eTeghGV%xo_ufLsZDf>Ruj8Cr3-k=&vxt z*iB_0w<x6E2u;?=Cb%9=Uu^b?s!G@`CKt1In^h0Txub<)a}>YZW3zbXXgPyIZMO~6 zUXzZklJS0$ikFWk0lNw;QN)6tcEcQV*P2_DRMY6d4PpThY%dJI_ucP5=h`iIP!xQ? zg~MkJ4edYVs_i!flS#H5P2;xZg*V0l80Gt6O=rW2xo7R%0FH8kfJ4Zw7UM@Z4RIlf zQ4WZd&u$Q@cMN!4(D^a5$Fih+yH_Rf!x6|nkVVSjrD;7l-Vq{h7FcluhZ)a4Ga!ta zMl`pczQep1W-&UBfWA4oAg|ZK`zX``F{{s@e;zi@eo<*GmaR7J5Bb&vA?rhFyxUV# z)Br^6;Q1=b5~_zNri2qK3tlc&Dedc-O!xjlB=Z>KE*63#89_T!V&Cntz3JcPHKH!& zrg=Ce^4>zyo+`bRhQ%|z(~>{9`}1AG3APD|e)p09GYFXjt@v>73Ejd18-YWqFg?V~ z`AYFPz(vHQ7vJYGBQ3>m-bj2i*<7Pe<(f9!I9fO7TfPFSPIX&jX|5Uf1yo2Qxe>r? zD{w^QFSoGh4;2VW6vI+lw^r;y&h;O%hhrulGYFlOh^bZe&hm9o^;?llSaHm`@nqyW zOvymw+H#*EL9nM)Sea=9z!lU!>-Knm>JHch)5U!bp~sshjuo_C9-n$dR$6u|F@K;K z&##w_53?G%mzLQdL`_|Xl=sPO*h@)b?{rpZv>^v4vD9b5B!kZ&OkYSz0J85NNHp}J zAYPzR<@KQP=<aZZC$F*Y3|CI#Zov$&s7%{BrE9)G(H*sr-b48a!1OF4gA8CjpGo<e zH?VRr^2wj#`upi|I@QQ1E%Q9Pk$M|6LJ^<$*Qbj31A2~L0iG|OWVhBHIy{FVUEvsQ zCH&o=#kenCT%YQfT;%85j>QBFV~iQTSIL{m{9TMEg3UelYWGr=l4aQ(l+k!>gbbiO zMJhjQb4#)IcCRCJregaV8jzvnQH6A*{&}CM2o!6c%=j3h7dV?>ZP{&s#ehl24IO&m z<QR&AjFslk<r|!KZSTx?jdu#By8abQvMI{Jzw$4_@TztA;YrYJX3KLCT5^g!`C=y} zLDNoeYO?p(pvH0`_;rt*0K|T*h#oxX%=3;;NOvF9W`5?+n*_fych5c4%BRVBu9tXD zbFd_NB@B``7rfRx*9eE8-3G9dHM?A$l*_w|5nzq6l%c5qMds~}$??u8uFqjqC}D=+ zR#7{RF9^`a!)8|%e2M+r*$ve9*S^j(Cl(dFL-;J_eY}&Dw&Kp+nYnQnIySo~>=X8` z9p49SEIh@RTQ%AN59Q%CQq%7Q^(Fg(VFr_VrT|Sx#ITk=T1X#FIXCwd<ewYgSYoHu z-H^6Oe&q))FpOSKPFkY)B^Q=OcEE4?vcE_K9mbJ@L?1&oz0(&1{Y<9r^?A*7w1axZ zaz)lfrFuseD_p;_=N^|kQv8Nu<TGP~4w%UD642RFe8kG!K$ikKUXj9Mz<cY>cIK0L z6!Z?H5210(L-feJz_J`Dq!9U~hl+nrwH-fdZ_iVxMu>&8R^Xd|oD#<w9@;vDF6G>4 z?WAwx(x2l;Q|qNVc7+oup?l+IU00Yni?O`enRY~ad|rQ7p;b#EojkmG(Nd%NW6%y( zQo9;48SH8<b=7FVA!l3mXg9lne*c1xx3SNwG8!g;JI%`FP+@uC{wfX*%_^Tapo0B` zuv@&cazB@4Z*6L~)6ckNbxsp)K19*Ql3jhK<_1t4mV?muy*^cisSM3Cs}{z3)#tc; zhf@rHj(K9zhnJvyX8s&WL|0kh08uvNW~h%sOrOettERW$7<YKfAQ&GLWP!*mQzdSr zGR4J-C}RP#&x`OEyv`tjNHX$GOGMQd`&*|B27>NIgqA%a7~P{YFzOivktLUQnMGZD zo^Ss#ZT2MXR+9VnSsDJpH~v3~cXJQP<wBQPLINfd7=z7jN|KHyU@PNS#YkswCX=x- z#oa4slnq^<;~Qn!kczdtYGefhIL0P_7=7a4Em{~;#;fnn1nbuckAu8c4P2yg&WX5z zBpwU`S<pMG3I<sgd*w85LpK30$&^EX$n9TeOIj@$r(_(-YO!NmgGVA2oyHT-7<h>` zk#NCyAm68V0FZ%oasBy%%il;R%InW~&&gM$u<z`EQ#-NQE1B|w#H^x#$q=#}wWXd( zqBniyE*!i7L)*MFZghAcyLs+f>(McjUV!b!_lF)0i2}9a5dz<x@nK$L3epO5)Nq<C zRSp2BYp4s;v>h{I#TQsfp)mFMYbDukUc*fhY=-M>@kL3m?y_#4>#_`7&iVT{S^RvL zHiJ;^hfdu58(St*325XguQw<CY%%u=EE%JTN&u4a^O%<7noYh1>$-!`zpg4@REx{q z+z5W*DDZ<0<*aO;W?tAD>>&zgg9}@pW;yn#?F&L!HNUy|UW|aIDrNi>d*64~@^O9f z-;~gq7?3yl>qOJz3deE0HClPi#@(aywj8>VDh*4%l`Rgr0$V<Y;E?kIFGhg|3lGX! zGI+4y&l5mH*6-y_b%w$P#c4pwm93#r{B#y5TCixP>C2@GbO4ETyLA#{f474U#6$fG zO?Hy?GbUF0+6Fj{)KpMb&tJJJ3M)4PEe_9N)M9ov@n2-im=EY{Hlk$*<^EAVQq*;^ zF=-O>dPE)-y1|otqQk-TV8&`&IK64G4bq&IF*9TfY3Q{SI(vd};kA&{77tWW9JZX2 zB!AI2b(`bQ?Y^P%)x3quVAAuI2WJPM#34MN3&{LABdJ`k7Leo@lD_%IfntsJkI4Wz zBzIUQmkxp`4scL*?a&ki{B`sP8(0<Z9-igMP-vXEH`TA%k=aY`om!Vn=&~4bI{2G; z?b2~dDZ9+rDSXqj_-1P!6_!tdaSLAzyWvox8Ki_MLnESPHy@zs*J0&rYAFEg!%dR3 zpn2BR6R0dfjTBjDJ?{5IT%aMK+e?o8Mk=@X9_1!F)9=<;rt(J&Qm!ztl-O;|;K77| z`#}`|nZxGXz&GZ{leqKR%h?pLPt|Q9vZ@>MHIQid^I$TP&I(LKu7&RoBS)nlhRGML z!NXnT0!&&fb(6+gDxxw6<l-dLGe$igI4&bJ|1%{jw`A1=6Ge&QJ+SEn7W1Rq9;G>* zMXHR^9kXCCs1s4xceP6ypb>TEMzJ*v0fB1#0bI5_RtFs%J;~N*F%W@MCWcS4n;QT= zxqIhRLo5kbKJuf;gF2u0pQFgaLS;HX8Q$MCW{i4wjH$L_?h%4^8YaD$nov?`ggt<6 zmoPudX4c<13kW8iPPADs-04o!yX6HqMW9Ws>c!V^TfOW8+#UK%9zw>?P0e59bnTzn zqt+~KSA@5t-va&sifSoH9OlfC7}L#(mlwPkPipjTT~n-0Q~`Jc;`mU7kP;w6{7s^E z?8!U5zjT66kM9wWg|{`jVN_=$;3t3$e)ywrupMtjM$!=Cl8%~Ux*1~eVTkMMKM6SY zT|1I}NAK>UQi96$!rKsr!w20a01b6U7JR-A3(au^B%TD!Ly22jLE!9+8YRV=zJo$h zq5ORjp01CC$;}!sV?A&t*^a!v0*#YjQLq2Q3*TLfb=DIvUVu4aGX$h^(HS%^Yfr9) z*TSMr{+yZQ2_WFMG>#t=Z<7JL^mX`sjLIXz3A1bOlFc6Y-1`0Wfpm6%=hkzl+<F|w zpx|HvO;$tUxYO%!K<RhpJ0UnDtO@L_H7t49@1H8a-lXG<1i4?Pz5BYt_UhWuIQtCI z3XSh4Umi8-1!vc7{2$Eg9qqR8+m@%&f~IfX>Hq60c93fTF%Q6W9Jrz8@VAchpOy4~ zVbp&ft6g@^|DaRPVDM}e-7Qc1d<v|kVg0aYJB8%FmEH6EPed5d6;^FrlCr$EsKh5t zHTpk3*0pr~j)ter9(!7gLGzyk^Ckay+V@PslFW<5p~fNR-mMPwJZ8i00e<H0xZ=*+ zo!=oCKj;MnQaa-c(brN>DHD$;OAggPQdP^bHmuG6D^&)@2*Y|=*Gp2Pb)AN36rwf% z7ANfhy&Jw_O6S9Y(6MW=MxBd0{=`(n4%yDtk5~kXVS$cXW1_}yBxbQQDmnt@S$sUi zTHH}FHvy|@2o6}6ch2Ir&+cXJC~^O}G54}Y;kAiC(fgxS?-Mhw9|z1kE(yx6#wh}S zOq#!pW-T&$ex8R*mzD(c+?v;2v!I>vPwaBhY`Ldmp47E$bl{;gLjho10)Yh5?!!w? z&)o9w&Yh>*GhVCPG)!7=zITr9c&_NRd5v0kasDZKR<+PaMyk4t(4QnctG5%jcFjwb z0yR9<JqH=;BzTzRIPnMlnhw7x%ez3h6(B(xi=`!b4mZ8?7n{7y^;xh>Ql}w_3!7C2 zq+iQM1Ie`#`6tY4nq!9fs=~!#WKFxL3vCDsey8cqP(1^hGP2~HP(0j;oPs6lZv&o< z`qorC9(%WsSi=pHZ`G4t8ornI^BQsqE?YexHVv1xkp%+|z4D98^5XRNYReexDZu!G z*Rnhcu<qZnA{nUsmym4@J2p`QlBsS3b$tMW5a=xgA6Nrbu3A3IEp&sEb*{#SoDteT zy7Z6oEQ@Tb=XY5HJmjlNF){zR;#YK-zA9gzKM+<>hb5uAv-545>67*U0Oqzwkcn`- zf~Kj+t=18YDcaW>U(L-w0v?f-@y8vUX0f(UG*jDKrE>Cjw?6N}ozG<gz7kq`rK9Dg z&?n`#OHp9NjK&?j^8+yfIA4eDsq7cVA`f3or}{icCy_k?c~qLPDj=E)R*?4z6<YNR zXYfh>J#`FVmTj^VSzQdZo3_8fx~)Z)y#RAUJvd3pb9*Et?;s-<%O7<KrWd}^sL80Q z5lNa@$0a$CPedOB&CXyt@^!X56><yY8F}{zxr&(Vn_hsA&S8I0{t&4`GlptEn<SqI z2q3bsfNl23=_6j?@g5a6gJb1}!E`QUdY|_<3WV7SgjCd`3_^JAC7ZK#8}U3R&2bNr zHodUK$XnwEG;U*D&?KbJw!9SU-e1w=HLHwtP6YG{nz+#kgQ4nlvVxj=VZN@{`Nkw_ zBlxQHNPqoD?)i5f;ooF%GI=4OJ}j8zFMvvRBh$Fe$c+tPHg*i_15$%iz6JExDzmsF z!A?#$no7L80M-Jg!BcFaf&aD*_b0)wfbVNjMhU~f%Vx@NXU-KDE0^;;5{&=})eSK> zW-vnR#DK$LQeIdBg26!zYflDsvDfQnt`=Ea82rR~ufhUjEw0I{q^`S1tl2oDUsxjy zs=S<`6jFWv{cT5NfZF{EscOx{RZjzE=YlaE%%K3&DZw>b7v~gh-2`mp5uV_yx_J~w zq(9BN52SCqIssY!Ub3vOP#uCT6K<_~g7;Qeo(71ha(F9HwJ2)99vFBUMe0KfLTBW& zeQASz)p?NqXKqyGC21U|DtJIY97;M#f8>8_jIa;MO_MdW4R;p7vXN;?MHtu`>X-Au zFQV8Xfr*2MBfSK04gljNFZ~rwA#2BF>U^nE&)Ot*GRJM-45rsoUe$D9>;MJ)NQ+Uk zx{~ZNpx$7XFt(bteV3RTH|XfN>ZQL}lwr*)8GSJn0)Tq<tz3by`b<Ja0ZsO-^A-BI zsrU^>{LN=+I=vX-z74l6`$L7?B83}s-iBr0RN}^#FwhC+1(y>824l`7BPKvF+|=V9 zb%U2rQ}c?IMhREPVweMFIQnrE;Nv+_44%-2%Vp*HKe(r*N%QX|0#-IGG}(#Giq&$U z1Cto%)7XYm5uV{k)ZxUy?_MM2N=N6KejfX^R>JpQS)JbLQMXvMT>#VIg7r$EE`1Yy zJA1ZKG6Kjyedr)_U68CMu<#A2lbWulH|i3u%iD6>V!w`LrBBmjU(TKYwfYtb!T6MF zvI{mpzA7h#T8N~MwL0kBnxiK+wDs%B(?j>;O6(%MKjwX~(DC)i`HB~cYLceWWaCH) z77rCVg)gC%fCASr-qFgf6kzDJdKyR+y>ts~M>4a&dGJF>x3o0wn(GUNfbeGSx#bj+ zB6h%5{<4)3Kt%BlIrk)~@Z5B%rCIvf%8ev@jzRuhl<c>UgY#aX@%oRa=!#*z8WG=c zO|mexN+lV5#owLPc(Y#vAin!bJ+0+qrU(Voy5B7T%F1+>j(-4!dK_R(ELLhTmHK)L zFB!2P(L|HI&J%<OlA5l2m%C9&!7<=-z#<a>NWcM!+J(RehEmk`CRdUQ{~cH=c@-ns zia$_Oi49m>3m46HwEBU-NSgj|P(6emFL@AO_>}w%ayq_95%YK-qhR<x(W*QYyDVbO zu=LouyrZ432eBF_R{6ondQ)<-Iq`1ScCPfTiJV17vBZ)Q=e*sMAs6(As*mdLizgpK z8X0M@V>a7fbq@>6L77hCocVW^jD(bIIO#NMhTkvUncbd~eALehL+6B~i)U`c_H95z zZxCbN>g`v&hl?m-0OYEW;01dGKxd3_NjcNu_Jqm9bzqt;U}34g#19+4P%rVLA7&XR zC&ZJNbu67j`$5Abk|x_~$1oC1a?h!MU6fQFegVcPO4h#hAdJM#&36hucb3_W!Q_el zP;FPP=#TN`toz3vh_~{CB$EcQ`t&qs41b{)@3k6;=75}Oew>1lP%;RV8@QaF1nlgv zVWMxD#@lbN_8xLj#JM1&H;y*>Sq{E>*L%BhghWb!eZ4^{boHt^B`@KQjwz8H->SSg zUy&qz{=esU)EP!-TP!G+Pbo}T23EfR^~*8TL)Mtu^{k~*F?GR3;2Orsl}lfj15Ph6 z6>e`R!CtXP4=ZKke?s(LZm}OH5GZ~UdG1Xyi`+C`$WgXo`=}u%MME*qnIEa5b7PV} zzpuP<32~*3=Dbx?!$0mmz8$Mcz7_olk$387jAw_#0VD=5`%$t{Mb#AN5q%7i*Cf@k za1dX^X^uNsNRrA{Z=q;9l3-<s#HbMdDIgbUL7pCQ&aZ}3ev<%p+Qf|($}&|eKYll5 z>c{};JZE~DKGL@6dMVs#<Rl|WZ19&D@G<{xY5iiZ{<SS#rX5cqh)_OqT?5v2z)Qh( zsh$EpBK~#uyqDI|m}#kgfNE9;^U!ji2)klcXX?Ypm}LooJua8+b#|g%M{;-i;_D$X zSQY(A+AA@buh|AFa(!8jk*x;UyXT2epZ2$3mS&I7xCRw3d*iE3$>#KBbW4oV)72dP zD&EncT$$Cn4U;%?k;OXU(bH)s%xw&A!OW}7+=ImMNhzUN&RclekA)=#b$BWJHB(JP zfgcD&Hw!3F<szfc;@T~DcXaC-iel3vMf<RWlS<@TDAvT>6#9XPUHR=_wH>=#9=M$P z3B-I=$}fNy00~G_HeFNUCfnT%R&k&x$ot?42zEW@ou0Z8q8|_*0i0CY_ABmU7Sz%+ zw-msDTGKGXJK6JbO>WPu`}$Cwk5p)X?}7R}#Afeo!kG@l#CoFk=nQO8O}UHz(#FKg zQ1C`>EO-tB(~g{!$oWCJR7i6CFnI?NIFXNOd25&Z`m@@nR=We8x?T_YnIV9~Xfe#p z`4A5B20K0Zh-xPFj2sF{gBAF@ib)9836yJ+rU=etBTvhvA1_PLzLSvTE_}6!7s#}G zJ+>e_p#6>}W3;A?IQX#^3~H9$6lw&sX(o{Ff0Q+c&E?9y^v0N*ZCCqV<V7IsC568I zV;&ajPv00D;Mv<SyxHDs&B-5NQ%50cw`8x<uYceIbSoaJwlEn1!NG(G#{_v~GKEA~ z$7rg`rgL#+DbF1(r%~7&z1~f6>Tgz8GJ`9-^S;#nAm|IxtM$dD-m&`UUmdQ6U+q0y zajPFq%xP<kX?L*DiC>*XAO60TQT5kEvLwvcB79>o2_mh1mKrFD;}1*;JIZfw*t|e| z`6Qc#&9^=NRnFqSOg{MmOy47cxbl+ir!`Z9n^}dV3RL!VA=t+Oeh;;LxOlp`a%6EV zMDMP*Utn7OLSLE;t!F+Ro~e|2meNYWjmF-@u`r}+wCih(2IF6SaoaM))l7lwexd@N zyg$+@eUloq{0q>!eQa-?SN9%S0CKQ1FXhnH6^t~GYO`noJ5^mlAlGxNoaGsV#xK~o zvnffq;4ys+2@-bSxZ1}OXf?)K-|xQ4k9*EgKE;@G^&%^6WL?xPR$Q}4;&^vm`B)4| z>D@}b32C!Lu^NEN+P_Q$@Z!yumJZA!oEMsZK<V<Nk{U(}*P!k7caU+mVo9lTG>hk~ zMlH3feAN)%&EM$rg~=_yX<-)$6SYNK(CoJ=V!X)c{Eeg^%3G0We3%04_|E3$vEgq@ zhv!1OqvSQUl(z~1XXZ(+gr9cXFPyM%FYfD?McB=480*c?EELJ~iKG9uLE7C1n!1M? z?uQSR{&n`#4+Iz8`ge`EXKegGw8N-*8NWR{i(iY(f5PY<QAo^qy4*tQ+oKOGLj60H z3^pvz?wstty)@hZ`lP9~yma=Bv(cgbsJY^8iCu@`eaXAe@lMF~j$ZeQPNFut_V0Cj z09&56w$ue&ZY@OUd*(!MvUiKu{I@HB@hrE-4rT}yx(3*9_=|e_uO!_$YErQnD*=<D zT58=J1LU?2+ce2NF~Gik4ZA3|+9#jhgIr)SSZEfe4e25}c{%l<=T5xki|2tLo4ead z*m(A+Z$E-FWLKqt-~@--NrJgF)#etgF66hJNA~YsNmW2^Pvq=Q=CVX)tSU~oLE|p# z`cFMaz)o=j0{B*bbeeuLuFIfRF<TLT#NT_UvDm6c<~nq4CO|D_gr%dlHy?utIXQm^ z6ZC4j=lSH5lbp8i*%M@7ZW@^Swu)#F^XmHWJdk*@=e_2#hrGmWWj#(B?d^d+iJ{5% zW{9;{YF&BDH?yq-lde74XTsTr=rwnk3~NVN9Ich!zOi@r_q|E_jpn}&jP&ZAIn({M z7m*%Js8q47I4s!ZXDmn|oyHa60busy8qV}yafnjve_#0x7mL`Fxa1z3EX)o8l1U0X z{dl+#xbmk100Ko_|97D0>ny9_EQZ%%!RPluZ|oJCyLA>aQQF3?aB??T_6G5cS_(@c zkQj><$60wZo{k>|u-o0)^Z!_T>#(T0sBska6%+(4Ktd7e7Lbk+2}Md;T5`ytOJY!@ zOGH3&knS2fq@*N<?yjL5h9PEtNAcD7d+v9Cf86KJ<1=#RoPGA%Yp=EUs=b!C@<p2v z4~g1RLHS%)AiYNLuN<78pAu_D9n3H(V>iN>(G`+d!vE1g)}vVn0qX>k8g%gA07j%j z4;&IW4O;~|*uW-`A*lcP^*GZ-1mV|)iu}B)5)G^l{4DnNN@MmXz$|-g8oUjhdghb_ zQZnjuokC3qo)v}yHO(&)Nj<!vfS)coW*{3(#}=#Cm}B3un;a1E{pwRtV`}(5U@|R@ zXGa9oaSN|P*yy2rK&sX!?o-%>V7?Q+e+T$`CVu*(fK-<An}Yb6h^cm1X3Xd9uge)} zBAtlMEFDA4<k8o6fdljYfF;;#%qn_J4qhL7o}EehyIdKN<KY)U0+s|zX0$`8lH>I; zhwy?)J^)R)L(2$rVnRnGUHKzURw$&pdxP2(%6|$U+qOP1`=4-Vi9Ej9fU^%mZ$q)C zFzgwSqvT`+kJ{t0`_Tq!28yjiO`o=bFuSOF>^UbC-FdJ&U{kaCXD}YW$jUT&%>;+{ z=u<5d=zLXC-*wIxndH6|3r=!7S<PgWk30B&M^WTtC6!q0c$Pj!=h?qzTg9KzoWLse z*cEU{AYo9<7#QZc477W@mdyzB*eh;(;J)(J|9@J%fCUdX91zQy-i0kA!huTXi2@H8 zp%<m<udPQ4ROIpH16$$Cm}n3leXpX(?)PS5kVgl7OrEgk)DWgjD|h$ABG<a&BEdC| zh-Wlt#P}9~6+3YZl}+PZ)Kd@uY77oeuRjC_r@>D9_3Anl{FLdu1c&J=8mI{8?Rvcw zb+-usm9HH}{dVQ+=~m4)@bB9~m@uU7a5&!P8@iR!#tOswwr(2;m-(^Jgo6`C*7Q;z zyLaj9LFeV<yNd__!bv~?y*h5$xZ6$}E^<8UbB9r(7QkC;I5qTivtq`1!n#7h>jutK zw<KJghFuE)46N<HU^qmap&tU6>xI@W27i8vrz^k!p!s+q{3q<hB0CM9s3}w=>}(O3 zhpM0OeG<Ne!!#j_<NbDYNNJAGizNEoha9DU2u;)vYl<O%N||^b36wXm!z6Hd02z|j zIFA{*^e%5o^(unS57J~JlU(NmpHq7t%=uG$?KI+T*JClK9;nMWugXVoaLS7PQ*%UX z??msajJbGCc)vR4zG7DB1HIh=1CDvY{ejUwt?zyGo`^ymbU3J@D27hcxHfeVAOehz z?2H2E6{EW_%UA=fxx|BRBx#%CCceHYPVC}2W5ijN51_vv{|uHP*n-}>9hf{NO(l-M z>DGh-sxhXYu;V0~9@!n7_hBClJ9|w}VT_+LdBk2aj#{TC-$T}-9j13;&&XFe`yZ{m z;3VP<I8vQ#q{ew{dwvP$73fs(<hXa+w=8M0QH=WDuTBMxv6+5AkC;jEU!9Ug9368C zy}v7TEkzV@38(iyKxl*gn6PgmTUg(+FJogw)ECgAjnDA>e>Rjm=XqSzLfucH_;ren z0>_)fjST1tPXOo&i*G4f<>M*F{qXL$E*$%Ij3OZbATUHAgT5r;Q=;8#LJuSv8TxT> zKCcu4F;;@TeW>SHm)8?$H<#0uUs!Et83A!GBJM8&rHWT_7M|c#0mnKn;jDZDYT~Ya zm)8QY2yOa>MQY0bVi8bwG=L=jA90f<%*%Qu2XMS0r@}bNe3NPEIihF$Yzvts+h@C% zzV4Xd_Uhqb={|v65<uYa<lL}coX@mIRD?KB?EqiZ;VcG(A%QGF4aPuU?67K#ZA(mV zqb`*WjDZ3d5mI}|ker?_V4dwnd_Dy|zXVhupv^ltgx$OOvYrj+rTEYCuR!ovH8Tnt zb{XeHcn`_;f4|WOBx^W;{Xm%(dLB#d#&(m%+q59vf2{|P@BQxLKH7maU7r*ueFZMb z&t2fTlkWP@CXkM)B4?cBmxX^V8OUadkF&Df4uk*VVkuv88@l%eia%!<0LLQg0@gn- z%Hmrle6*tFi%3Tzer*~!_t%|)N2gTW`q!m;%kY8tfr~vECpmdUA6mDUHWHj{Ng@U$ zQM-8lsW>liN>(5TV|sColMJPW{;oI!^ay$Q|MLZKj&H{6<5=~Am-<}H#YP7N%ilyh zB%Ptb3&Wct!4R)X1}^8*#1%>6>M5)dg8qfbt}9=mqL9`DCi^dG2s{E;_x4)H;e{&3 zd&3EBg}>b30H}}JVW)J^EqOJ|k0z!QGJtRJ=9J$REqQ``k5ln{qCuV+-F{)Ym4^<b z0j7=9fpoqdv5KslB9CD0E*D}R4vyF!QUvY5IN3jLv5%w@mT89(3#}x(POt055876= za3xqzCKY*%f4$8gyZaHnhg{+Kja*}(ip|oQU^^!(G57uk9W(TsD9t11LirjT!MU3b zrWJ@!DnK!lJLWy|`KCRwpiIt-O#mmEa1RM2hj_>K(<i$H-7rp{BW;m-`^+%`)OKg4 z_b{MhroA@sMtaw-EDU4vIS!<O3I08C$@Pz*96)@oXc-6Z{hqiJKf{@6SZW7^ZFTd9 z!aR_^^<CIvIfjq>d)e0j0a^Xc_ODvyP!3*b2Hr&xJDgscJ>+Gy1IMPyOleD`9%ANH z0HM&ok8Ibzt{tz^Ftv8C3P>Dv%RP7X{u06<A}ju~*#(I_1nnWm7ZH$lN>5Qt<K;_^ z#b<(pD}sk_kC`2FGf3U4L5yW50Ui%0tLV61ZslQOiF$w28n_*{{t1NamL8a2n->nW zVR)POM%LP4qO^iml$~2=Bu$;#9H|e%{x**QnRs{>5m)z+$~7FwF6rih(>yHv)XO21 zugdPNu7e}-=9QJv5Yp?8=<`2x?tRt{BUnUKmCAED_@)jWLY={RHIQ{A?s7oDgxLGX zUL^gXrhUANdGi)}2rZDuY-n)R6c?i4BVz)V`+?lf{bJCt3Rj2%KEk}ui`MSW^s2vp z?Rm0#jM%0SFb66>dGY7RG2pC98V!d6DObtoGS^9dNXY(xrM|PP#e0Dlt{noB?1e?T zt{QcCSY8ijIuM&!bKk7(<GX14xIF>{l%wmrf1a9ub?7(qK5c6U29n!Poic?fdVcX> za)BQ7{IHp`*5?+r8kEOJJR+0n$oKN5`o(RWkD$N2tkDbg!BGCb(M$Mi@4mSD|8zl* zrLNEVl8<i!F?MjYH!-mO`In8M1wKCa<A;wQ{``wefKPx=@bB;3zke4I;gmChfE~>q za`ON`DRWAjTREE8b4ptoIGRYB7}*$`h>79<eyeLjl)AhnCD+ZmQ;ij!qLe;V)1#s~ zzS0Wsum1fi@ptjfWjM}H6APpGF)8#nYx`Ha<N0k$*V(>+ay1r0;5{0Ve#V|M8PY|( zK5p(>o|rdYGXG%e&R<)H=YF>4P5(!Du#u`h-v7$Io#o>*lN)2g^{A^B+RZDT`>Fec z(mRluVK>Ji@!U$dwI#@6us}TOz6ZYWv|y>Kd0Y6m{`a{C76u1I3{33nIn@8$Es-T$ zxWkFt5l`m;S?4~HdvPfx*9(;C&Cae&glVy&V*kutO(++9;Pvb>C9Y#+@IUpLGuIRb z5nKerF|D(TQq_b>xdqoGKYp4Nf3*T5E+{W-Q_MZLJ9Jgs*<jPTrVypi8Lvd+zo|R; zx@aNB+Iabz?~f8kh{eZj$80U~)Aqf6Eww;JHIhw_5$auT2&4M@_&QY|sVKFeg|_!a z%2coz-lpb5LY6$fxb7xCi&xR|qRG0C8H}@KC{(mw(5iG)@C3wcU+%ea^P|WkWZK5V zGIJV~HYLxfYu`Vgug4R#hgIb~d~}ppu0oeI`*x>Dh`0Lm#<QZsPwyQ4-U;{XET>y( z3AsP@{3K%-dn>J6<>)r-iI-o>tNCzbWRBl$x{BtiZkI6$s=S&fy9$Sa`yoywRhM-& zxz)%}=mbfrOn92FODZb5y_<AL@6k671ha|mt2BApt5{Fm>4;CO1I~CW_AFUM$QBX- zz=?G0@HTJrD{E<XxV*t*oH3$~r$xtNuI}6j>YmS;JN6PMtkVy5Q?xX7ng$1i^>fwe zym`}f>qI;%%`d;;&)R7T9eMzr=2NV6zLKMz{%)#Z+w>L1BcD0NjiIV-Yu}Me@*5q2 z{asb*LF<CB%a0co9M;)q$v*Xlw2fUGg}lwkfahJ-QQ+v;=+b<~zN0FED!<u^G9gvJ zZU5=nwf2P@)jPI~<0@H}nS#w;-|~qhkAv<P3y!K}IX~rJHk=aWdC7QQW_cGkjuGdF z%Zfh3*{8Nn%7;gt=YBN}3o$)vwjQ}IV9_`YAGVS}UWYe%59$jZfAuwZ?IF{Gf9?5B zslS@tS4Wn)Y#Yv8|8P#RxYY_x@Au!%u*9Dge0#+QZk&*19#gaYZ~Xa_>3;I301ww+ z=H&g$oT_fNCY-Mo4J}NJ9642-3>|-7%UBzLO*l2ojRCgh66Ai&`NG5;Z07io>#@LN z&S&P14zEn?C2Xv1Z6GEP$A<!cIGpb%hvWY*EY2xmV`XEnVryVz!YOIuY;I(t{QMdI ze;I!x@v7@xjR`;E(ihrH=WFaFEWP~)h2kVk>TA9Iq@2o=?<H(W3AXOWykb(YL(M|o zJr()xTghmQ9dmK!htt-;KTXk#pqx0Wg&meh6Xd^bPxEgV;rfsVrJ4QSnlIMBQU6Z) zLU&S)8PeaY<FEf*XYHz1oe=YD6Bn@`zwZ%?aPZe{Y3g`t|M%h9cWp}<Bcj2%HU$6u zS!Abj@}L@ATnW)7d_r4ErckN*-`hJlbM^!4Nm9=Ft`i%Zn^To`MqBz@`7tqMsPU}i zcyil4`G2LLU(NWx|LVl?YaFlTFz|4w^uhu>L)-^fx5jyC`mLLr-Sdz~KudC?p8BZ& zb~LO03yuhmyW7#c6y3!}ZIxt0xf;ks9u((xLX}F>Q#0hu%m22pWz~Vaoq}JB$<l<I z5(cz}Ql6fkI&eOE^yrw4YI33_m~3B0u#(I}+ALJsNbbj6&cv@1a=%|u^sa@)_VC_N z6Cp1RO`{=ifx@o*kEINa?7{W=l@TSeI5j-=ts2_{i&yq<qj{cN>QIXnRY`|Z)cS@6 z1k7TV!qPG__#l&C+&y>arM9kWyhF4!*3A;x7gj+d0<Pe^0nzv$&sh0C(-FO>EC6&n zYtWDq=;?jt@a$Prze#5os~NA;M&nXa)k{m8E&Xf@=S{Ov(Y@WST0KZ_@}-KJN@!Ju zn3(0U2xaa2<>s$daUKFsG~R{#s_!6hVRQxqOKB-uGBNzj%#7bIMUHbL<qOl7jZZ(_ zcwTJqjWE(#o->-fph$n|7HcWvL{4Q;sfszRUlK`75|A@r3-Ynm-C#MRUH-N6@KK1q zTa;sd)|bRdJKuNvo?2!DXDs(}Mr$^lzt-*#=~{jBQd;j<ER+}hQC3)l`zfDcMbSX# z&r}qBpTE5bD~mp`x9bGwJDl%7*98x)*S~<T;b?^E5mw*6XF}yu6FNL<6iUJCyfNB% z9v>GsUS>J6Hk9jt=SH@<x!GN}j9HRM^z<0s5#&F{F`owULndDXUL;Z(kqCv(jyT5s zOA)yHs*cfX@lUAj+Xq1e3O`<$4nVGER#r=Gf8Hpa3pk@QIeAr(3X2<zi_?1qk%YV~ z(NpxjrdG@B7x{_)V_yFG0)PF>;T{D`bN?^qDwkH(i%s4foq~Dyl_jASY^Pu)LN!WV z`eBZDX6`>ienm9@8e$34Rm63!VaLr^`BF06!s23<i6)K`MqSr$qELwLI9_4rjeDq+ zw})%MRJoFMBgba-9Gof_CbhRdOQ+5`J%LsFpoU15o_u?$7Zzrtd{ZSY;R7Q(Gn)+O z9;WNwtL(|oS&TAmEXHwya0^3tcj8CBN1J1&w{irYwaf{6oe>=&*61?dl31AL3JifJ zyy_mmnRtoa_>yehvfTaXRLSqRK?Z<zFj;H^{cazjB{;M}g$B+Y^_2<WR#4>IiFo*d zL#3O+6EEcD5BK)wb)TTB0f1}4-&}Vexs(G`t>bB9V^d)7^u9j&bfhWo^Fk=e;jO}0 zj!vzb6bFV5;=EmiJ$@*)OaL#7_E(_1j>1@8T;1>iw=cQo@P{19tTXvy0p90fGmV(B z6u}CSOG=_G`SYsSJcu6mJ)2?^C~JWMpV)L*M3(qC|Jg+-CIE19^ruZ&Sw_>C`JN^L z*2=lT<AuZF+K|h}XrK2E3Wemc+EI@s4qb+cwAXEom$7nYp>=wvr>AQJ_(05ov^+|o zdzcs7>x-p{dg8HPn9Ofqt{P?w3lx4Mel0Fc-Q3mG^GiNgHN!{;qCLe(gZ0@GB*^n* zY<yQ(2<zv2Kg9w!MGL<yF&-+>QY+`c6f6uM2Wi&=v1gwt-!WO1r~7`?W<UNNjSK`n zvC~h3EU%9L2DSsV-vL9bQhFGM29t5xb5ig_x)|pL0Aj#OKGPGY+_%|Lj&rwe1a)5H zj(w#;ub-JP`^+(_(U@7fK8}!(<E@R<jlv=30Cv?P+jJQl3vR6m`e*d~E%rb3{ljMF z(6H|9n>^Mm!*&2-4D{xG2?dP{p?o2)lf&4z@Qc4ir(x8AL*`_+Fc&sc06s25LERD@ z4dP*LVjt+R5dU5*9%if-3K`BL$Bv3ap-@gv&MhfP$$wDeD+yH<03IiqG5O&Lih`Z- z*i_uFA~b3SncSDhv*L_zbL@9_=&0UZVO~>WC|3uneBn1f8el-(<%>UqGkZA6vMA5n zuuFxp5GmdQN{zC>%Z%DM?`LY&K(<&~?x)y?MVAMWT!Gu}=Si6Bu^2|>A0qs^Hr6ml zPa!x#)aC^3$aC-i&~3>v%?=^}>Kxfe(bha+gpqkaS%2%+EssY;TV?h2AZU^0NC5z@ z@U^XLFsKjl$K}T`XtRA6TlgT`_1dUc2G?0wOuzD03KZLtzTu`*p|n;P-;<A*#j;Tq zm``6x@6{h@wGN_Ie{tCg{IJ06-4Gh=A3C$Ui%5}OO3O|c%o%4P3WlnWf_}VMPG?Yo zvtu;nQ^<@=WCOns;T!vQH2iC9z`?O#-o=okVN>8zxtrL@O1lLLUJJ*~@hHTa2e1ub z1brr%#n8B%v30ezm7#6*OYo--J0mQupm_I<WI46KyV1r0(f8!`JN&v$D5E#q1<YiX zYEKA)Xs~{v=tvXJGK~*f@u-on3!DmAox$`tZ|9cQDLSlQ7n7RwAm#HnvKT@;*l^ls zF7!suo%SGycmF}6a>+SdRX|u?ycrZv{g}FSGFjZGK(}UZITo?j<u3~Cjnu-<U0*21 zUpQTQ=}??ZD}PIy?v7o$i(<ckoMnmV7nyKNHT8cqc?v{s?GwI0WOa$Mn@cWh)ktMY zTrG`S;B?038BeN7)3Vx-ke!0ds=9oK^1U$0o|v)dV=x@Lg>zBR^5>$NB_0apn@^w- z#HR<AqN|%vQcvHIESx-f=$hN*|Adm7v%P*96E)Psd!xOuM(s$`vcrkuQ%~H;o1k;; zuk`sp4B4=6BnU(`J*1O#wxbX8o}BxhKT>@{=@kCZvFkW^29(QtG#uJ+h|zq^S%y$4 z{Q>F(#VIer$l60*Mm<%>ls5lo%9N<FXKxJjfTdepSQE(-+L$lRx`*(<H`C+Y|Jvhm z#`E0h%9*9uKCVq>Rc?+(Vb8tDcz<*o(GPdIJ1ula>K?e@bmW3vp~(YsGvBVeq4`<G zA0_&kbeAf1)%g0(-bgZMkPvn78EzE^k-BT#s~$bwMTv`$7N<Hl9N*u7v2WgN;p+xG z?mGwz=WnaP$*KE3H$G8hSQ=vD89KUSR5fTnc5mSRkA<cml-t+YlAk;WV?O}{iwP|Z zE!hje$XU7@P|Qt@?W&7DM3^d*++DJZ7NU(%iWcH*X<G<{ab~qTvpghypOUepbxT$0 zl!}*xrhi#D%KCeC8|@DrR-;=cmle}1Gz#trw{g~`TMX#5>zSDQGnKDmFk|zza%(S6 zN*Y0y@+j{Xd7Em3#ki8*59zf`JHPdNz)D4tHZB>I+h)c)`DG};1Q43KiGY^g<VLk> ze181<jR=n>!mrR}+H~~7q^0jHIKKF!@|DWVlb`+XqxfpKM1LJ>{YfG?BL6gia;a<= zT0=wM#*+24&Vt1T$Fh>q(EM+ASiEKJC2Un5*iX7&sYI>(dj99v&P^O_o_&J{givgP z2Szl0ydy3~=C35in(2v)^Z7|oKe#dm=`>>ZM|Pg2xq{I=_a<+YHKp~?Ddj@)=(kn7 z|9RifKj?2AgDG*l8VSI(EuU?FTc<9bc%U;WjuZ>{v&8=T)!Qv0)dAT5=^y(3<v!q! z_b2~>5DpEoHKANRtP~(VR@xs}^hPx>E!>;5E^R5FzIf-w_fFBQ9F|Qxr}StUv-#M> z$8_jjKI1tcE!q3`30VU+^S__uw0V2r(IgA*YT&)f%!Gg0?B_$o_#7JD|94?u<lf!C z`T^6zPkFv&NE#0ZXY!f`HsjB&2A`k{C8HBCN!oIeLOmyeXMTT*K3v=j29h$_5)R`d z|1`tFG5IBjSB~Rc!to|3%1TVHm)!e1g3lK^ip6z6Pf(Dmb0)>$cKpTi<KT<;<~{`8 z`@nP&t}09k^<2bn|NDZE&A(KNL~dkUcqTIKyqM^g1hFBu<>~c=Pbv-7mw3MryGIZ8 zwCX<^yIk^Fu)Y+p_@H(#0`J<?Y}@7yhr`GJjsXXCp#i02^sS0;iH%g=DL!Q+2^4FS z1;u)0YcGxaVdQa5`3K{0GPC9V*_iWFHmb=H0?t)=6kpg(w@TKcgAIh{FHH!`<>#vF zU8e}WVtV*AnPEe4yMIqlQc-ll#gA-kS?&rs{s$}SiMrEyxM{dR6g;@bg}O#m(q8AV z=<{z^7yyy?wU~H46kAY+v=UOV5tM7w7XlqlEK$mhaCk!gofn4J31Y=xNm(c;PYydu z3Y!T!DSY_BXpvZRBGinv8VGK1b3KETquFk__taJ9fe|KTOyh#G)YT%8=UI9JnUpUg z8C~Nu+)+~Ct_OA;U{a^;f-zDy!GgCsFE8A=Ke6)kVpgRzQx%X^kx;%C=lo?u8e}qk z6j|>NyFP`ssdM<evSyv%mbL4YyJMK-8cb?W6J{-egvBH=qU9obPLA~>oE4%NZP&j* zjLLE2MCWxB*f$s^>LEH)q)8=pf2T3P_NT6z!eseC54&Obd_9XkD&CKB70i!9m_7%a zX#DQtdy2;}quaNl(&ypn$Qv?z{R7Mx7t5PicRJq}>We+meY($Ws*H{T90aS9bFHw| zc22ss{YSs;(ZG-%HvOWOlsqM8t0ta#t){$=@{Xqj5XHfFGS&-}!VX6-2W(#7^F6yB z>2+wd@Lb(7P|nj+evW)%BUzO%z92u&ol*O_Z3B@TvrG1BsLD&~NBZJVR3qcm!+V=* z>CE*ja~LZ6U9&gTKX2J}?%#gGIUaY^J=mqnZf&|m6HD~+KrqUgNhoEsFg==HgFvC( zboyoo_}u3zf_-(`bC(?7X}D_H8{6u*Sv@P+FM1yn|J-Sn8|(V)Rs~<!#-!Uc*Hov` zz7WA2(aZ2_9Q{1@3+xiw)oYX57?x(cNWKvEtmiXXi<NI?bEHk|BZ_j^eg1IbOS)fr z|J}0BgqSf&g>egp?ql#Y8%bF<zmhW6N)g)>twz_tx7kW3U-~^X*f`EnNLr9NDax8d zpDo$sMt+Ms_-*L)rXXEM`7v%Fk~y}*7yo_4OYV2tqLREb?^h^!j}>-V0zGnUuk~+V zV(XGEp}vtn22xof4r=LU1JMP;RAe!lRr<l8OI;p(QSV{Cd$Ed@5niTt6%YbN<&XPy z?wELKr&W<{R}T*l9UUF3jnG3{A*Tcf0U;rwmx!{mW+CSU&lkteqvMuJQZK@KN&ILT zVyNS$l>E&t-v<+Sa|oqV=%!}SDpOVNWyvWx-sNkjF8-^EKJB<zDpI0v<3WB1gNqMT z%B?ISjx5boGDKC*mj$p^R!=Ry=6}g>{o2*K9!C|^N+tX-vaC|V38ldH!1Kt#$+zPB zFfSiSK!(tgWt4|4wm25V>73Hv7dOS7vz%T@y^)l?wn;zM6{J1bj~p~SgO7RTTWH$8 z>jklPfHAx8nKMb9SNna#H#P^eRocRuNAyC2LPA0U0xI26dlrR6_f0nlfX|S_9E@gj zLUD%GLwFHJ@Kq`xEMU#wZ!2+n+Ex#xY_D)UO`4@de<M_zBFf;hs-g&;!LOR=Kbdyc zp!FAtv&^KmUeg3eeOB7gIQrm$A)IiJc^C#M6OkX-xD>P|*GKh(5nRL`8~9r7rF8QA z^mW`Hb%S7$S>hFou>||E6kWbM{?-OwXY56^<fQ`L0aeAFkSCEo%cWUr`=9h6C^>eI zSE>-xV4e~dte<jyv=-k)5!10|oSOt0Iw2|P)2B}>!u1ZwD*u!ez~<7_+$_O)##8Be z>I~RGuU@^1o21EAWIfR#yfs<nppEEQx`H`#=y#r*xYVgQ&CzrakX5}Ju^EYZQun1N za2!r5lgdr2B+6ngmG1L%ls`WW5&^$<2Pt-wNNDt4@+sJ;*&>7a$Ced`ql%kr*a6}_ zqzfnuGEMHuQwR&jSjKp%FTk#DO&DIS+IYkV5pNzEUV^G8B^+YLx@yy&Z^UQME0h}Y z2oHi-QMrK72r-IkL}X`Yqqe4kg@r2A^QpC+*;70R{D9h~R^!t<%5O_n0=C%o)iBr8 zVw(7S_u8~lf)DY0qw=K6mHHag!e0tO|5tFKXK?GvR4C~a(+threl~#)5anrvxx{AO zohM3kml=1%VQ~J|O4oT<3$K;@mDEzYX#O}ja5XaeSOpz#W72ce9}UhO`C)YizZ3zD zRy+j|o{&IAO-=1&=A5quiqq!4K+(@{!C(6?Q$b7_W=yF`qgcNx;aWzZSug@bV3lTH zQxYg}H!3l<?VDgfX#I3I!u;7`-GbD<7xf(<Gy8_4cO<eHu!@zAnA8<^A({$Kd88>6 z1CBav%!tj|M=bNhjXATi2^5N*(Ap3AnpT>2l(LaF_s)4ZVLaU2{r&v_9n8<qZ$0>O z{Xc>U<;7xOsi%Gl&MvN5HcCBGsSLq(dZ^@QZj@P-mrwd;5OoeFF)I!%eh_1QPu|TG zM}(R-Ou3=`kuA~+Zn}LRZA!Fo%QOCH1zgPb`NMY5bK~syGRb)za#r`V<RpvdX?9<9 ziKQr?NCj5Ak#x$Dq~$xsYgWf}c__$Fkmkdxyz;FyEhk$`I`}0U5!GFYz(6i8E`w9k z|7dd!xc_2~5TnW3C1t6xtc#ZXt~GGCu-YqX-{x9;352TuR(p;%L38|fP!>YxOKv4i zy4;;3G`Qva4fRQ3nMLNA4BfdUZXgcL+=YcT;5P3U>o$DJ8gVWSzm8ry0;6h@C7(HV zMDA--mPlUBk5N)frqS}8v}WCtZs+4Nc_pR#yzBrSrY}-9%_0{U7e9RXkd>A7QFOp! zD97ad*`LLI*5I%CmY9!7{y<r|PiAgjlU9wr^8~zLgf}oSprWFJUZjkOh-hqV1njNs zVa0!%Cma8g`v5!c_uY?|gAN~5<>*Hl*)Bic_<qKwBXFyNBIGuyhN8e8-Z)6u+<lb1 z(Z;1y8QaA;Gs|O>mY$xTkuhE4!pX;XR9KI(7%8|v|F2^n2j|U|KlWzVBDdso2fGIL zfG0G55*zSt_TUF%Omg2E0oL6^?(FP%d*gintDF6vfXb6{oSipUux!!^O5=7Bi1Ko_ z14Ppz!ebdZIH)Ryc5rlbeEoVfQP^enf9(|~`5qVSEEa{3k&)Tm-BnUj`ug>2h0V-= zY-8SpfO*+IT{ZP<_}Sx}L6>IDW*QFa8-Oh;`FrXj3_u&O3@|e@*FwWWLT+5YzKcTn z{}u0n*1fyYmO{lrrfrn6g(BMy`z=oI5c#`M^P$5W0tNN8y^2mLM?kv!tfL(G`SWLB zBGb~++)-Qf3=9l(bl+QATE2gml#&9>FCYB<@$m3wzImRW9Ilgb=&Xzur{+TS{|HL6 zjm>KBQNH5q(^HXJOD{0s%za_>3^ln{@4iA~1wX+|rAPgbs*MT_9ghQlC5{6GGZ43G zFT?O*Sx`(&j}9gwA#vr(6`QGQC%}~Efb41fFS-*7oc%@mtk$skH?r*HgnPF!+3r^b z-O%W(S9LmAncBM%#NF*M63v~%?j~Z6CDo0pQUGNfy9lwLooJfBX$d0f3^eJCX4kED z+?{U;CS}*Ew4Hl@m0%f2s}1f+h~)t*Bnk~pOq{k+LmdydS^q3kBCY~s>*{8Fhv(1* zFOfK?NWnu|#mvO*J6Bcr@EwJOSUI=VwWfE9-d7+@)hH@6R3$i(r{G^64<_j}G|a)? zK7^Qh@k-jAJ9mtXjA$P{dhg?7GhG{a_D4I#DZ0eyJ{3-icjm|hqT}Uc1c49_VFUza zZwcgSddI5VG^^Y?GzH^!-n;aGW30tG(3r6yC>1ddPD_9lCUkUkbY*3wy}iB0W!ul+ z-~YphfByMr2hHD;Bx<RRA>7J*YhhvWiPzY~#GKG?vaf#k&)8<I5}2J>-66+@&*zG> z&hjQ}<+0}@&<1a2mCOR&dM`}ZoUU+1qM-ZHp!q<x%Vv?sT-t}l&s`e{y$1;l7!+uf zT6e9+;HREF%apJT0~i^#IZ@F^0hzAt(0!pV-}HA9iA5B6s+XX#J99yUjhXn$CH7Z* zBv@3l9=q<$cID+YG$ezdg(|3h4f0)y^9pVLe9!fsM4+dGjg9W&s%^dDZ`_a?*|Yr* z*Y9xi@aX0SKDZm?ly6HrxPY--!q9r$vyFo;SC0a=t@8Xhp3E98wzjYX-7<?Fz@bw1 z*AnnlrqNs)wJ9zvg6RM~h>eVmq`XDaeb4=Dw+(7NesC}bk15o<&t>>pK1>mGU(o*h zVLZRf<``w<$B#*giJxPKW`CUX^8+>jVZ03Q7J@n0)ITVF)+pLii&M?ujC<oAMYbhS zF^6hP`*{to5idew>(5bok*t%!vdDM>0v9@=l0Lt~NT69{!<atTuv2)h|Gz9W`>q)P zZR&aqC8S-kqpPQ@qx(lUWh%LLwlaO|XsXE%kDWRH`@&9u?d~9rSp}DveD68j6d|(T z6*g5f0Eesa@MQV}74g^$Cb#cQ^@1j>EZGg!R9-e08NAWCA1j|SuXQ*+;5Vnar0Tnw zRZm7#A9(a6efe2BoW21hi`@Ds{7AC-%krFhZx0Fqz<!R-T!4cWmd|;9`U&0`%!R#P zhjj$tqb;11Wqd_-<q@)*%=!`@iO03GLIVu!>#rlZ;*MxV=<mOqNOYpcvVF@Ro+NhJ zl6Au=@mxiGA^)m^d+j&vMcak-un*aqk#u(_o#OYy;XEZyG`*-#D&?D_eRGBNdhX{= zeOMC~-RgsNwVZ$aKBSqLq??-F59{_ieRHA$?RHSavcc0nh*|{5+{i)WR>3Jks}zQw z80Ikx(_-{_$a07+)Fy)pju1yPl6?xxaa^UUAIdhF64k1Y#8HUJK|qoZ;cs$H5H>@$ z1wEHo9(%oEvva9s41-o3kp;(VK>1z2_qNP6hMFS2bk*JClGIomtUjKE%jgPQk5}Ys zALs&Byhnac{{MVaEmZO)IhM$19eTLEXp+*{LV>Wy3$oY)cbmP)NuDj2FHK2H5l#Xy zq5~v-T+BhUUN>8{bE%d1jf>=FK_OJcwsf5+hizA1ZE0Q}K=WN2R5L1>c!cD)?|Sh+ z;<i}G01~hqo*$0r$5)umt&U{^%hk`&Re9`0cC02dd8}7p>^4=qTgJpZUOUK=eM~F2 zXoY>~7#y{yVlGXpUGxJaE0S-tSYAvpHe!KmijZI2ejgrA4CM@gFY52K4ause^H#W0 z%X&kHXD+j(s5m=Y-|Zo;@=&n*1{Lc&>}TFXNRU$M8#4@dz0B*Vo1M1Ds~YK}3FXTh zI7L2t_El}^%PU!u?~IPy^(QaICssX@=4B+V#w)z+iKTLV+EaZAu<ommc5y$S+9mo; z@!mwpmC624zk1#u(BA2@!7esEaq7cE&$aB#A2FQz^<F-ZsT$&Y0)QPIqCb*<3Pi6u zU}0-O3~N|G;1UaCCO9FiBd3~i6M7%(<$VTM`!?bs&nut3i&$p8W*IlZ4#+z^p~Ax; z9*NqDGK}U*v;2awQ;Q*i*axdj>8sZH1Ef9Ax<jmX5NpVlj|ANzA7P2=hDlN+R?;i5 zP4mouX05OudFw4k-MRI5L=1c9WzT}&1;bM;O<M*R!)$G;d?wddgaHf;oq~B@4_cYB zezfDmJ>1(ib%_dA;SkCk9eXfF5Sp3yYT&)ZmfJA<=CZ^b%;ak6B-ejuUq-rO?qg1K z!TFJm_)BSq!sI)Vkt2D!6In{B_#`a%=(S_HO#pl#>Q*MxWhd+C3hb5Nwyq^7RPZyZ znF(%+?;@luEj#SEJcDrapUC=@Z5>?NL!<~=sNHk7Ok`0>w2^$mH_%}rY16H(ZW;iM zu8%R@EJd5<kKbnD%a=aZdcu6jp!xP|mI<YFI~5XULMFf8YYC?9IYRi?_~}EQSWYh9 zIwuRiSL7-=({eiO)QMl%L9+GY(4vuym=CG<e8#GDPCpnkCU(wd-+IDt|3H)TBfFci z(tG@7Z5~rCjBy_qO2kq}J@|Txys}=Wxr(m?-^02g{M0*>;DPJe)FJmh$vH^6^pelm ziJ!8>n^chf>uPJzwTtUJf72dF0pG^^ZnA?P$10O;&Zr2hx<gfqYIx^F$=9V{xigX> z5A5uxE2-fedeu*u*>#byfqvn{?!uBsd5)<D^n)PFP<*X}LbaT3K}_uPqi62JLDwCN zHy&E=AXu#P&0M?wDTXd%c?aHeb@;_X^C_YT2b30IXicVWsnGX)(0n%yn?6wd=E$?F zM!b+R^vH5z{jvdXKY$^;YE#^yF8mz96d;^I&4+W-Jc<0ZitFOM-c-a&E<hT^i?D8b zwPmhcFRAFBR~mwcA4;I4C|au65WCWkGGn80?n&(S=_zhs=-T+S#T}7Hj!u<OzEyF1 zm=w_noo=PCs1aCyUS$5Ptf`BG)Va)R{2u!G^FRA)!VMK4c*xcOJGOvJ^mO}9mCR}^ zGkLW=zfgvBcid2pS}uAuQ!Q8B^TVw4!KTa1RbM~)OfX$KSSO(4%vjOja5Xc58J4&X zBOxh$tJD$H4eA``iW8+FjXa5?k$MO-!82D;xE|}=H4-x^7CKBv>)+~8aGjwYYxSy| zqRQ~FLDJIXK@?^z?}dg)dPZ2wQSbzar}54WG_CU0e7BW5b^;Ti?e#dfTm}v411+8N z&Dmh#xP2R`=P8^|wCc5@pyjk@n$w`pv6hsqH!9ZV$4}z+qx@?7TUl4RBNC$Z<}esd zhNLmcrnu}k9G@noyBM=b53RY3D%~zwKi5~TVVfkfz<o0gd#3xZBf`68UL<?MwjED` z6H~H*32pCMJh-7Ju3zJ3xm&X2gG;<RQIGw{W*ddw#>Qce;%7D|WLC*#%vY5<R?mAD zfe_LfkAds-BOuG}%-L5958U=UC`~m(!0cMg47-S?+~bkq6L6GrgdlKSTc045H|BK! zlyp)ZZ5m65(HwtYmi<YpV)~44R%sg+%#0a(fK5oL)gJUn{=jY~AL)9naOm0tv8;Dc z=P>B>6z~39`GO7YY3t#l4udv|T^so@om_Iy^1c%&)dDOZa7KADtET@L{*21s6O}nn zN!CX_>B>2SAJ?}0(>H(CADt4?V$Rids=7Z#5cY+qTzc>n%zDbLt-BjwxcxGR;$IKI zY=MBvn%K!y7A_plxX~FZuTUQoo%A^=LM};Aj9G9??-OdVV*uQPA0D)<U`NlzYwhyN zG&J9r6E(GHjNZ_}>d?X5WZAU4_)RccQK9WU?XHid-s}Jir^U^q^lx^)4|thbF55}@ ze4hN4atx-`f@3r(uz9^1<22Vbq+NTv)YQ@7)fZMhSgT@_C|cw9gXGecQYtVZZ7um@ zgTXIh%JM$+w;4~7soJN~Fo<#Sq~PA^xY_{Q614nYwgt_w8V8oAj;~cj_C}eZQBZ-l z!qw_Ynwn7%<@kbK0ArLRr&P!F__X)se3-Ex->7C`SCJ(C`2Xtlwi*c=PB2JS>2hhF z44(ZJ!vQx$S5#5fitg!={$WjrCAdIxT6Tiuqo#`rr0hEQ0UF{Oc!barUUCQuItH7% zU<l{RhytNUTo3b7pF9KheI`&SzN+ri!mc=GVCILvJUfFI3+4yWJ?P(UPvUm?N?7$$ zj<VwMV@ivlSNp}cdz5lx5IMu_Qierkw_WnxD!X~YBhUA9NF0W-JY$BMH5TI~=>%+O zu<+H=)ggxM15D3B_WNbHG*g(=a!E>chUmRh(f~b_@cKP0n}~(r-SJ1HHT)0bbG2!p zeyOMSAy7UUW)6_@e^|h{Q2QkQE22VM#og4jX6UMRp>YdC=5A9g=XK_69YM0BKJ1%m zF!rwcKmzkAycNASR)rbULnjyxg9unhH(;?-yNG_DyT|#gtwJxWhddTC?wfz$%-chh z<eT5Wk7XOBT=t`@^XbQbIWoQqOY~l=VU~<Elz&>IByLH#r|C#?26s4f@bdD~(V6T? z6dozmuUERiKAd0UxT>tKK74+PBAHM_U3;c^2RtVZ@hk04kyu`UMZpx9ZiO_RJz%)= z*sgxdO&v0nE*R0R_AxJf>hidUf+<g3;JVhdaye@0AvUkDPt9%Wk7m6Uv_AyN_R|aJ zO*%L{7}bIkKsDp|k*|B^yhAJ_$TKDSM|66&s(7|@qkNszjWv!Y585j@0z8~cpym2v znF8Y=0$s}>pFL16jg)3?buXxM>gUv^AA{$bat;uDH)_5ggKzOMnO(9deCui(231g0 zL{bRaFSftCf*1Bc^sVI8)1%EAATotNq_$SXK|Z*IaV7lvbf@I#kE>Hbx->Hd0*}j? z$o#AP+XJaGR<#9ptuf}#Th7BD9iDxblkfy2>Zq3b&~_8l<5fwe<9O8}@YUibkoFLe z;u~)FE~@p9p~_Z6hu&3|pW;XzVND(OZT}m?)<X6wuc@&YH_s+EgHA2}=22soO8B`* zpV}4pFi6`mr^ThJ=>Bswm_|z+Lr61xg1jrsO#4L>ZB=Y1E=;islw(b0iZ6~EB>%Kj z!G#f&I+UPH|E!8lFjUd9nJatM`z&DrR^<%HoKAa-9Xx=-tkGEIfUJyTR7jZB0~;H^ zw$O|Fpuyo@j6-h2NV#X(A0k5qAHz-ODs8&;Qkd*X#$)aZA=Y+<NA<JOEMGX1&i6D~ z!8-E7Tvc}VU&mUDU&lb30nS~7v8S{Di4Le_Ef}iRaoa!!D)Pfn9`P-R^0S(Gn*m_x z%X>80D8$wk75}pC6Q+mxnt27&<7Ws93!zIqxHZSPtC;xVq+9qTrGz8Zh-q6vg&l;> zX$*(%c&*z$5M6MzF$UM*)vkanam=-TjEYi|t3Q5fhjacbwI(2zKPCO;<*H4wgGM36 z?yhUiNoTd4kNm(e(mkV{2)}dYASwAh@D3y995oY4$qy;<J6s>Z0>|NW>L;%SBT)~S zNdFKfPW${%*QKw<ldZzNNxWk)e<Sdw^XJEpXaB)=@lsMzd2}!o=+{3WA!*r+G(2g+ z3%c?zC*$Ch{0c9$E2FxM<8Ao;Iz~`fSeTcWw~?Vz$;8-r5s4%l;1qjB_18N1vE`SQ zJ$DH>8GM(v$L&|upbJgI`?sHz1_y^p`Y(Jqvs4$JP%S_(f68_F-*ppcgq-~ix(g8X zL}wolL^st-O#(Osq85MhG!Tuo)EUDG7**z)d;y~kKp$(zy9@qA_s8qpUE=wyb<R)! zMlTXS_+@Yl!HhZW2F||w$GsJ|$gBr%_pc$umgv_Lu7FJ!H}C52`~U7@06aa7KL<xp zXqMdKUG@esibL9s{yTJ>2Ekw0nj;}By;nrKK~C9_B1rugmpB4=zo+#b>6PL4qDEI< zKS5sk--g?3*q~Jew!#Ts_V|C|X(tF*>&9z>qY%P3eF?<>%Blc#2|m9Ntk?H6_>yH~ zQt>6WxcxuG47g4mep#2BSSi{piskR$>obVFLU}fLTH>R1h3FE?(4&6h%l|Lq34O`# zJa(!QOz|am;pu*tQ6p$SPO<7TblOqwiQFYA4a&5yUCg&UC>b{6^w{7xn!MyGqYtzP zy$?Q9j=BcBw;Bg_6TkN0XVan4BkmAdACIh>cC-o7=Bj#XN7*^afS%%*c%Lo>uY}S$ zQEyq>IETmT&3L6|L&Z|FX)MlZ3+tq@ll?>Wg%@-LeDBQuim&zM=VdvAPanL#4I}D9 z2-(qDNkl>U)-TETD0@a8@i{#vv3noMUEW=)-N;-3=@X`x2MatyUcDb1n|Azp?@K}e zTGXhT_`5??F1rxB?o>*&9Pz$C-O=kPsQTnx({nh*Dd&uLixf`{G>z6RtD+7qYDyKw zaf0rboJ!y1zjn4?59J;<EmJ;oFw($&`(rh3@VSUPo*w!#V%Q|`j2AODJ*yK~tuhA# zovSvI^?L)MjO6w*;Jv-Udv3o&8I|wnD1RqW{9G0F`c-y3U#wiqnKy}Z==U#iU*u%u z2hz*?LBZ-{G#E`SM9vu{DP&Kgep79WOAOm8mG}-)|KLAl+T!<{5WWl<N=Ih2ve$Hh z+}%6XS%ko5ulfvFoEa9%j?Ez@t*gwXhTI(Mk_ncPwy$G<jBbdkPV)BmYNjtm=N<ZN z!`Kget!>bk@1L9@C?|N-9h$ECK*e~<adWwr)7}Fa?Hc~KInj8sR{Dj$g6+o$%SQ#% zz2>#V2%6Y@ph$v;uIGJ&5)E=YCNS(EtWT2n<^IhV91$`~tYnSmG#P`Ab)Wsf0;W*` zJYWWShqE{$#G-USUBN6J^rd;@^>x)8`CSAvgJmHD)$18QAli%}-X|ZUiS~KpbOvuJ z)GgYiU$~=m7n?VL_-k*&VdD6;xa<VAa$z*Tg^jugPIoS%qe7vidUOLHwi5UBPl8ob z8;M!`CgVKs>h`%GUaG=(vc6-t%yWex^5kV&UPn&sF}OH9n!)BKVNXOh-Dj8R*=GdH z8l%2|D28STw$%c<4=dV~SE7jS5wjWO<(*5JMf+gOdC_6B3lVs}n5tbQe!cWodW*iu z2`aB8?h%7rJbdR(L%O&3VuO+Pa>4XBWdG1zYtwiAoGCi_d}lqy67I`ZVz)ltji48V zkwn~fwCb$oop6b_X`5TLyF#!tRV|Ym`{>J5ioAdL2Xhq%V^->MQOkwEi9nZasSI4| z86jwQxh`2jni-Fz5l8!QhE9Do6bXX!Jy>Fq&D@|Uap-?mV542+9Bq)pquxDfI|ibm z9l(_Da|2oA6|MDi$U&O$H#1=i;789qE7;ClCc+$IBFk3MM=ozzQ4WA>96~i-W^qzY z%fHY>^;pgSV`4n{R)xdv$(Wxzm*-MxS<IQ?K!R|?Ms41;dR<v(U~{S`i!|y#KK;JA z9PrVh%~}3@1oc+VjEjhgo^hddHHsjbK+JQYHuJ3R^d$S{sr!=YEplfARG5s4bHcT{ z2T1R^y}QfEw5f52vlYnpeJ@65HW8>H^4lBhXBo)@!EG+`TAS{?EOgDb@-JTxZ%*YB z>FdIc5c#^1<;QxWnvOjNlZehRk$uGU{anUPLZTotwl@kokgkrp&Jmk2$9a!WeDsPQ ziRzRjUL7tmC{SCWB(AX6MZEUx*M{E<e-HxHxk}$LGZTM$>S1)hBeFe>+1P{|v8NHJ z!k%_lMx$d#l9n`FF;9@>N{Cc<&TYGlFDK4uZ!OttZ$E1O)7UFXoN-6->09c2)ofFj zu&Y=$7l$QFt#z15jJB4V2pNe>votoZ61tdcI1wN6)KuYwk5NzVWwndqEX>F#H8qu% z7JUrV1*?9^PD-)_-OAdrq<eU>d^@yF*a_xUWzQS#GP6IMwR=ch-@P;CG0DI8{c<67 zO=wc3n|mprW*%=ynq?WIbLjmww0dqwjgP`iWP)N9sguRm5ydHK`N`659bqCyAIj0K z>xo)1*{YjmIX1QHjr(oMg8Lk1M&BR!xkK$yALi<EpTJ6KXN}uKzwi+F^KOaRPx|F6 zp(5>h2JXzKY)jImEv=oodByRWj+AG|^~@Z=pmYcJB?G2uPYvGjanjQtwK~o42D^KV z99f>riGG8q6}IiM^BbmqFPYM^C+L56r~F22@7G57(6^jn;~y(hSRK*&(OmQJTd5<E zz<!2BA!7;)ra=p!yM+{+8Tl98eN(~jZ&+_6O~G58^40}iptHVonW2*A-l#ISY-T%t zn<TyZuKmm-Cqh(;La<h1j8!ESiNSVVJ8Qe5{I$S<P&v6D1IuJ_xmq9ZM^cqQ&wKUp z06EQhdUb$?`9L0@|2_Qqa@Zz%5^-llPmsa}>DqNOnzRD)woZ{!?d{xB&V!+x_2{`~ z#d-^F1LO~fqv_11Q$fwZ=iwX=1a=1EJTs|YyK~WMR2*oMqvli3o983p+*YRwi(bxp zFGtm2?~Hhx#VFw5VvVV*Dk9kNI6Kj3EIx}yJan&ph8CN1aM&xw=rTQovI8Bw*vQ}j zg=n6)C3E3Dp>`f&OQ=5YsnfBZ_7ny)Q@vJz*ta(_ht^b_?jCNfm+J<y#Jzd@bUB|S za{P##+jh13nzdv3%FBXj^c`77=fY95rXV=pea5w4cF_h2-;3R2@NPUbIvjHMC37qV z%N{76>XxAT*Rk7<DS3LagSE`&GAis~^*|tESdqy}_F-1K<hLgC*siBf9x7Q!k`7TR zt-=Tc)w&>*yt{~KWxWY9EE`dwljj+He)AJ~hs3wd?rkpJvwixh0X+FVn=i-6osS<$ z*zcY8S{CACH&S<x%N5s)r}54ebaxjjorE7U@rg2vigJpIJ$lH-BE&4HsGV$9&4xz4 zXDdi-e;T|gKs5~_-cmxJibJ<G9e#u}GCkq|()Rhuojd5L>-pJrX`+2&JY%|IN6i|P zr}-kc<--E;YaIB)`1=d!LAsQ1%eI3pYs;Z6E|b%}^OM*U-BG92(LJYc#Yl;bjfal} z4fj8_!VV$R@ZfOlJ60~G-9Sz9-CN>w5lW~}?3%CqKcx=oiEi>hpVf)U9^vW9EqmI$ zd}-ylvRPwS8{y1;HFkWo&K-GhvcHdTceT+g8FA%2(h(~+_OTg^eIqO!@G^X+B4x87 zwpraeXs|W5Y|I>!xqT)KImDzA#N@x`E!_uY0y&DEGN97}b$TiY7+&buw#)G+2svbW zk2pj@rnHZUEFvb>ZVEj24QiTSSL%Lr;G|ui5Zb$JVp*vFy54LuW{PyX(oOxu=LO-a zOFtx^YQpA6dxtjhhc@XA$~xQWQU2$Nf)76C3A=-yQ&xETyG)!Y)*fs&5IQKVoxZ5A zT3DU|mBGH596-T$E?4Al%z&4_x2&6}7Tr(7Gd|{|o~i*4oYa?LvWG&ZG<xnax`L2i z&d=o9rvd{05nTN@29xSS6VU4u7y||0k6k!}uQuP7f1lS4CW^L^&q%SqSAO>^x6_+P zm*Kcti}Q;dBzTde@lf@pB*J`FB$V`pI_n;&Q<WEcCf->gI~jVYQbJ>1ZU`PdYE3oW z4#1#&$QXy|uH?_c!ilf}#iqfk$4E7baE4~lm;(F}hVk3&79F6P8vwm*pG)t{2wzd8 z*UDqtK?KgLxHI%;Z@MUGnYE#fk#wi}`a_<>$zj&+2t7NIHTCzqa;geVOY1b`bJv#( zG{kKUS1h&_Em7wVO{J{kFElXMq0#E@Ck+REb$XZ~_sAJLcjS_7iNk=;8D^8m#@2s$ z3d|<#F@i92fu}m$;XwOl_>Ql;H!G*`E96gknAOC}J}Zkbb*NAKa55uUG-vpF11La+ zamR?+v(IM~xPVWP@&oH-2PY0E^EdP5Odm{ibRYuj%C?V(c#zwR-*qQl=6}Re(u_~C zZB`i(w4#n@P<PbzMXUyD?VG}VtvAO!zaT1y_&@Ez_s#%Eqd@lpg3!HS74s(LF(>Wj zMhG^e)M8I%pgL(i!;0Xm_gU%A0v57~-rR}u$5z>Kf>`H=`wjLP6;F(Gcb3fj>G?aV z*4<sSQAy2Umkkj|w{RQWLXpz7>K_Q2--?MX4xmJ*Q{H&H8<Rv`y0xR`KdkR!p>|rR z&O2V_zJMwS_Z-2}93WcAuvWFNPi{Vm%BKA6`^EfKF|+Aq9{Ql(QYr0!l1qZriXEj? zl*-G(b`YeIkN~ZiTnm;r>~CH6l`7_2K0@#t-70nv%fij&8Wn8^7(sKR)A>V06<V-k zSA5P+%C7V3RkziSTbB%64#X21t6$F_oSiPhW~{{A*3(7348*;>D$dTfK1e;MLoTgx zM3$xo2ZV**sFm+NK1EN32FP{}PS+Q9%LRvr?hyx8Q{JYcdT{SvOro`7IS~-N#~)JJ z-XQGaNHe4H-Vl{XK4-E6^j*cgEAFz8VswW)#pp8s@xkW!$<p>o_e9-^vgA{px6XP( zCX1E1i1x4H0Ype-LHy9BcMYmU#cAD5KZg5#u7~gw8U}6=kuUl}5YH|9btCACt+<tP z`xZSrh+6E$f~Ov3M8PY0YR0_vB<eZ#scUd1;&Ouzm<-w*q1EvTk&&>7B-^dlciC5F zYzEP&TX%?N1Syl=a`NOp<fNxLhU9T!svfd}XgOG3RD9t-Kld>-Y-&z*T2Bp@>ETu9 zOAERAfVqovFnutfI=yC_hGwo}`#Xc_Qbr~t!}H^-)5GCI+Ym!Ji?`x>R?pfqczxVU z-xe6u$4;p0R=P9tC9dIf+wbs%-sw3|a5ZG;R*m^aOWP+faMLTJLV~tA^8e6v)&Ws% zUH`WO1;n7^B2v;VITsO7Qb4-Y0ft5yx<*kzq@<exX(?goAyhht8oI-w2N-(lcf9vL z&*S@hpZEOXKMwosz0X;Dul+r1eb$~U^DCjn;k(quwuX>L%`cYv?UeNTro%=?YLUtu z`(qKp%Ag;`;jPEE<QvZKJ+Tz3NwMkh=-1dl@*sl++;6U~>qeg<nd9tL5#BXFmB@n3 zPo15grfN8TfOSPFuyo70DwpQ=XPU{~x#|G{5a(kS1(+DGxC$RoNoMKlelttzr(_40 zyc^d@$ubdR?(1b(aW3|E8{*i20Q;A=j~pKZ!IoBkeq%{4SPOjL5YA_antrgcf$<~; z&qZIGc5c-FM9*69zQlt{&>r0uvs>E3E!2R4xYHrA?Kah!>!CyP(GmoJ+@q}3Pu#>C z?+&t`J$pNP3)A6*j=OH|iXprYOVx^W8QH+jK(%MHZ87r51eD$BR-7i};r7otp-#0c zg#593yDc9<vtwwDL@b?U=X}6D`<7Bi6S-WE*g9E3R%AZ<C&XR|Wm)}vPhH*vdlUxf z=KF+JbyKY<eBKcu{Z>NBuH~LXO&1f__7zlaRB3`~d0=Jh*AGTu0z%=gjPRc|Ze!=O zsU6eh4d&t3s!j^+uF|x}V-h$O<U8JepZx2*ow>Yl|2w`@>K&t-UAZHPoIXc**-PTC z(3bNdKP!}*8|qT+Il+4QOzqVmsfg8!)c)!PFoQ($L^R2me5e<CNs41pqanfMJCD>; z1csAR-8##JCZC>x4?pl=!l19-08d1u@U!QY@EN(f&(4_Dzl>G;DH#;R+))u>B+bdR z2){$On>BZM|0qeAR7dm)A~30{2INSRgJWP+QPh)7^NF+2k9(l}oJZ-?3kTqu;M1Jy zzDuZ7n25Y!ECJ^L(z1|o*qL{3_VpUs*|8n4UYy^OY3r_vy-@-FUY3D~IDxw}WI?=% z&!SRJ027#-uTvGYM~GG?Mhd0no_wy#v)uUECl5Qdn@yK3_aFpUF2nW8I?^)ai(mUY z)5AwdU)CyLvyfJSNEA<O(3aW0FMMJtPY8tQLcUIiXTY}CM75iCCZ}8oGCLu4O*Jq5 ze)%CgnlOJADu0z#R+yL9NKX7o!z{HwxzU~HnL0Z%QJX(qEXyM#cQ_buLSroJPt)5E z=NRw!pteW43dde*^>3LYhUeKGJgjZ8yt!%UmDTY^u#eEv6%hV(N}-5IwW<rXa;P%Y z5`@bx6dkJPU*AF(#Rt4+>DZsS$(-i3z3f_cR^QV5sGJ*4oKx4gm$a2TnV$@kisA4S za++{S5FtaqSQ1XWvr__wJ6o2PgqjKN-EkI;?OFwMkhSlbVO=!5I=*i4szis!w0&%A z+N!QMUCYu;q_uH&4iS(IgAyO~iOncz?5@8y-jQu_SC56UJKtSS&QNm(n|ia+-MHwI zriI`3nkrw@&ia&o%D&Ts;UkmxWr7^4<|s}-5~TY|BcvK4wk=a%Z?hE)@DsL&Ih!)~ zS&Du}kw4GGJh8~gC^<<UbpU-n`q}x$3mN2)V!3#7a^BvZVZdc2^14%?uIQ&gey7b@ ze<=PH2O<2@)1@MxMnj9qA}0148ADVl$(I1xO7QYMSQ`#zdoknD;_FON$KtuYnG*eO z&Kte7%MJHmZ%YIne=$Mbnf3KM31?2RG@)jhEOj<7o1OLTr?tv$-<}fdz>R&;2bEaN zv@FeNHyu|@#axr!wzVce6{{sZ=1AWDsT&=*9y&{H)7K*WowF;#8*nVdVd;?V7|Axa zhN;&|^|SC@ufS!!om}nBIj;bt%s7Fdl*59FJ4*84(bYTcX^d+%L#3!;aeUK)EGsM4 ze^aN#VQlc)5!Y4*dN*Xw!iTh`dSA}+r0+iHus{NR<oE#_bPy)aRx`TqI8*I}LfLB? z`$*msCTi8sEryoB2wG#<4pvtA`luOi6<?4s6Q<eWBqnc8bJoo!QLqO3RuZ(cm>0Cf zNZdWz=HtfZ0!Q!ZCA2kZmGxGX%lhCeLJlbvWs8fcO4JrK6`o(o;5)>dcjdQTH*L1t z?KO!=#MaU;d;ncuP#Ah$b5v@!=aAjSq~(nC+n!x}ozaMiO7g!Os8Da>q@i`1g*I=n zp$Gii%QmwnGKE{(bG}}FJ6#<S9aK(pg|KK?6Ffgc*3GT!Tf%<JSj!TI5w2<CCd%{e ztkU1{-JG<BS7!&8>}RGdNlh-iTTi$If|~g8<JsJ!O?#tk=4v^xguL=Q#vIb*dkQw` zuu<}pCZp%q9;NmohM!#(sq0G7P`<Aoe^5BSXw12&F?rKOI#kapP>-VV&O2E3OB%|O zo+Op9=qZ~o9}VZk8xdK-w#xh}Pfb7G5|jZ0zo>=vMlHXXI{c|>CVqbiRX-1TLBfcE zr|h+o6<|Br3%-;nHphv1Xpkkx*+Hp92RQ|YUE|n1qPUWZ{R1vkTJ!G1=`G*4G7?0E zvb<|Ip?Y@($u*uCn0bYa^Ovp<-UyRolV(iFNbr3*Hl6{K$GupJ<fxBI68Ap-Rt`hs zbM2x`%&WJkHPuEgwI7qk4#@!wv%aC)Ud|7ly}mW+I{*OC9p*u}gU#_{%?=9=NE!UK zgeVtoy!3UWi~{aETY88aQ`O7a29EM_HTE3)c_I|soUvy+-Hph0?u->rp-iR1huGm< zD;Lh<F=cB94jmrvklyy~kxbIwK2cO4l5UwAZcv8Ie4Fm84MDXTC<rZ2-ka!yUZS!y z!XWbHnieLL>+H6pQ$=_~+!>@TTvQmOV?=LivB8JD{SqVlWNm}558F1>U*9<JEjk?L z#+%i~#3V<<T+3=89puKj+Tnr7Y%V*M>!WUt1N$}3aAK9U=e)cx&ikJEhrRUKtnW$D zv-r}XG;2O<u8f29QR{P{A6e5^kW?E7ra*&SB@bZI(tPsdktSY$S%sCsWudZWHxA~{ zYa=@~bM+&RH369P9*Fj7@%EALQex2<X}M!AxG$-CW3=v7bL&9WES#uNjB8lQ@)nu! zd`Bf<HdXWlbNH@)e>9w>N5BRZsTn}5cO8y4bw1^Ke=oRXSbw`!f3$ryE_u5%2Sv{0 zFcz7}r`FgQTkBefxzP_;k5m+jQD=l|P+d{*cMr3feYRbCaIj~8)F(x}tZf3lzqvRY zWYN-8g12k)WRk?5jO`zYQO|ySEc3aib9YE6E}BD{?}QM_Fw=;1vmLb%Gm;v1Zt<0H znhEG`wT1|BLh><ig$Lk2^FN|fE7_)Bj9B$O7ShajAsv?tcfgz{J@{s4{aCvamr%W{ zhs30;6!XNYN%0`H30^ww{&kT$^$^gc!zFJ!aV2ELD$ybJFt$TT8p<opEkN#Fm^d%1 z?{$>uao+B|l0-U_1io=8q-2zY@m!mpkZ`yx>2R8&x<%dWAZNSx2Bx)D_nMv4XJ$m^ zfK1rOfK+;!#eG`p<++J^LM$mW4z6Q|u*xOms>0_ZAv3xqT6j}ZT5O8YKFTc7P`i&o zwgX`~)|B#sLp&wmU56Wkuwzf#R+dLz)D`uxDd9$o76UdvJk(N?Oj8f1zs03#?kl?Q z<EQ3)S~U#q=sVan9kIiZS|lyUX<hjQ0$RdPDNWJGYZw}_(<s)mwXyF-`dg@gjB$tA ziRbCasO$3OFA$Kitc;dZs!>~&h*7s~dDo%d=#Hq8j17s?{8PBXp~t&C^C?ZDXLr*S z`&HE_ft_`N5!%M-)Qz!f#J79<7P}z|K3%KqdGeIFVlJnuWumbC(C=yY0knuN(x-Xr zv;0{9y29i7X-3aOfjzquQY$5QO;D?KF019Xw9oeViR_P3fpt0C@2eM?ZX&Xkq+E<2 zAe@O8$?4bf=NHYKCcpcKVXFOLgwtD!hc*^t5=r@*vKZtcmUV95*n9Qofv=|+);V<o zdVHbp3-QV1g_*HHPlRrDKdHL!)6ZDi3v<*x;nzWp_Uc%;kNfIa`Q@7BY;MhsnZ`D( z<ugZdBMe**hamO~COv?go+zYbO?Mx$iT)HqEim;vQ+Zgw{HtE*nfaeUWO9Q2gW7er zbWcHl^^G2is6;i{r-HUPa-;xksW};20w;XWD<s#zbkIc(mKx(kFVf(US-Pw#>Bu}0 z#A^4TAm;?q^8Idal9gVc)rg(JDP$e>s5<mf+7*fOx@pCaUfi$ZE4(Y?l>6b9t)U){ z*T``@=>e?54BNI0UwQh$Aiit&`8I8V5hU5ibz$J+J3Z#;>E7jxC|h*`V$%B#Iv}a0 zF-V?^72O&JB&(?N@1Z2#LqM$F;(z=xZx9VTe0nT#^M*e(w0$YPUc1?>E~NvBU0Yme zBIG?GAG}p<xj>TUmlbItkIxZ<C69C3dRrXI@~)W7<3MC|{bDMbQIoNpWbbBUHk-Sq zCwt(9oyo!pDIe2aAwZ3M9=0!RflodCRzluhJ6zAW>a~zG2WsT*%{bZ^DmuFx;t{cN zJQl_pA#vHjTtkQctB)6Xy3jpY4Q)|$+KyzsZ9CyIkk&#+F)X$hxw*4FTE1@h&YwW_ z-X1sn`K8Ap%Rz^fi@x2q^&*_E^m@++6wL}u((3(BB6K=^+%!zpfB(f%^%9r)fQsuz zv=7JW@^pZu<oY0Fd+}TE_-3qcBeL>jZVKyWCh{6qAStWk>pfarDnI899Y{mGklOOI zvKR^~h!vA1NLp`hW}m(7D4?YHCm}r-Z0|SSSY>k;p3Q+4I^1tKTh+8N=rH=@P4Q~6 z9zM?vk1Ld#-TLY{J$u9HP<|_Z0_wA0e0uuLIR7DmBGA41L~mBo0qp+b2m3j48bfS= zBWgc`W$xH*V5nyreZsISg1j8*aH1LCt$Dfd05v14Ks1P5kWI``AB~chk{6P`Yn1o~ zOfGykjE4>6xOCL@JVbm(D4)O)2Mk%>WM(EeA+NStAZgr1<RwAc$tcAj)kADydhXo@ zX`m6mfAQ>uj&VM9|LS1%q62zLh!r7glp6cFQO4yh1SQ3Hl)BC2)za@9?I%r|?sXQ( zi%juZjWpnMak&;4+hPz&-a~A|uCsV1xVq(>%pq&P6@8DIsn<$|adY3r0qbJpq`ucm zWA!!F?dzjI^X$v|El2V(OhSjrKKuO#=j=$3?apSsjS*Y)SBD}PhfC}7EAyObbBXd% z%uE2A=wY$s`})WA4X<ol;Pvhqa#*eY8I8BFNJ^~;Be8OiSXRy8a6t20j)Bj;y^~Mt zW-H>4$~iA`D4=R&GF`uRpy2duEhw?b=UGuHeqyhS&fP~)wi&PW*kq(RwuzJ*vOD<x zvSEhtKofd@=GGBhGt3f{P0F7O7@7tzCdYo~om|zsDtk%%q!x#rG1%(r)9jS@_S)W| z0*<&K?<H4DP%|HfI7*oz22pF29zzAOi1d-uiqO{Yx2NiU^fX_e6xKef{buGw>f*qu zt_s2*C0aJl*EnDC^fs?29RFzc1r5W{>@ZLZ^Jnd{2df7v<Xk+k+$Xa(Iy=tgirFw< z>(Y>yM?w4iu)K7!+ncGC$Jnd!jgf41eV1i14!n2k$?Ed^G=m<xpVHZCeR>w{<_IKI zzk2jh<ysvB$v4C^Rm5*P>Dt;^-ivu8X(9fDk@DPkGIFL)-!{SIi?&#dbvp~A7;?Bq zNZ)b9w{7B`$P44E8~GBajd)L@$~I2+)gTHx0HUKMO?aGo^kwiMJN}LzP~+D+tS^(; z^4J4tpHT_j^81}#xn=xJ<nPOhaBb$Dps!xkgqNfO?P`rO+M1%kLmu^6^HMMwt6o<I zyOeq5pI`tb66RhOEMXZ&MRN*4oJjeJv(6pb$&cbQ=L-4akjGl{GrrPxb?3;;acT6` z)_tE|^nq4okDl$I`Lptuh`3DFGAV}2#UHZ+y$$%npk%yc1pPE=>rn3~Bu$;>7?ZjD z{_6qxy5p(-gjyL+tM*iu)kV&-PA4&ni@AZO%5$t%QND;E>e|xBG3fE-&yw%|mdpq1 zoWZ4Qgk`)4lYusTWD{dYHjk`NEfU~=+^0TK_xjOXwSJ2B*HKW2*+)5r#;^{{^Os6y z(z7({%hbPq@;F-TSA=UFvdSO2{hX-;7MBn=*h;>lLgJxo`i%CN&Gy`vUHc=SR9@uy z{(DnWJvrBORP#LwL~J`dxAH4ZPP}$UdIq^6Zum?vnH0>-a?yA#+R%gY<Yjj&O^TlJ zLSg=)Cc`9gh3!)5gJy0yRbP-&s`qpJ@e3zQJ8AEZt>G>kBJ`<=#`w<z1h*71U@s5n zSyyxo3t7(HBxw(mQQevyMF*%BpN8X^4=_Qt58~5Dox_7uA(bPX^985QRZ^B-#qCk{ z1ZXF^79r*vFkR?^)t42m4817hpGe~mMtz;s>+p?`NoI+0J)I9<n1Q>9zgkN+e=%)@ zs7wy=&}7}ksP}O>HF}G7HT|`Gj8r;XQnCtr^;|76ATh;NI)q{%2c;8r+EMXSC%_0N zlFOxzA`4{Qr!%9uT?1oL%o*|(crnULf(lg}aZE3&B{z1qc{wKK$jGCg8{9EgL|ky8 zd%)UUx9@30!_NLgr^y3fI>^CEF#=MvVn(++qHNGWo{c`pi(nD{A;ryOJP%hY<u*?l zI)X+~!+msILW}ghYbKerYcj@Q!%p}F4t@dWrF|bw`G^?f#I;iouZJpXKO&a-^zi<> zFg6CX_?R7f4DKwEj}1O=x0`A+Lhi$P_SJ?lC>CCvZ1^_vl&x>f>9i`n>aLuusNYoe zRoJL^&X3gix#G_~%{ntneRP&3Q;X=VkjR+{ZVbG`t!)2br!C)&SHkTHs2aQDjIUbV zD>H2n-5(f~#peJ9yZUEqvlEOJSxs(0Ke-%2679`Lb@Lfd6tZu~CHAo%ObwahX%9_A zeV4}&E^x|~rI5Onyzqf4#tpHDQys+V@Y==}gMJ3I?Os)^qTMtzMFsX^$>BchOwHu@ zaL2h=4FdGJv(akgOix~br9&?$<a{91ZFl^n@bVFgb+Y1Rwg_K8>-DC1Z|KkYGSKO9 z7oEjW8G#8s=W~)wD^^eT?V0^MIq*$P7!X1k{zL-Hc3<BsiN)x+z4a_SV&kYzmtl^K zQwA$M9^Xwm6h>C<!m#2S7s%JA+5TArRPm5p0tzs3FCmc~_=>-Zc&UO7I)Z0dBdY<% z`k(Kztbjd#^S%1E$Z&t-_yFOadO$y4DDu@7*T5kK)}zKUN);ca3UFg7<hI_l7IvS& zaWR#iW5>No=*l|O!kgnq{wuNd-9YHZD9{d$CM2&CR)(5iFpXlk{>sK|zH65am7(Cc zT;97g0@$nS>U|faW+KEjaU-(fFl6Bai`C^0OH(n@RJ+n;ltkx?tIGvspJvpbWdf>{ z7UF#D%OkBR&^$_p0C7I?72s6G;oG=}&mlXf4@7XQ7v*xq!?HO5n|yAsF%N_u^x6}q z_J~qoo}i%ZJ))lK!I$X~(-IhKu3mR4(eIX<w)Sw|Y;C#S8sSjh=Q_)*`jUj>(;AS% zNgn>p9g_5pZW?x^pY31^^n8h?L^9bjD+ig+4U_g<KU2mr@x2S!(CKGzZI%sEv%(eu zuYS^#Iz?n}y|N17!k48^*RFjE7*2d|n{5SOP4JUm04x)}zcuAae6ig>P@cA2Ag1Sl zN*(g-TuA$tBNhU2aC7w{N-$E_Oe?EKw)dQ3BJ?&Y=Og*4vN(7RZ)$6ASRgFfQ0~g+ zIqhl5CJ>SpN-+d_Zu=?$Iv?)~;W{|p55X$nv(r_U+F-2Q8l%PXb$FEq|DLQgvh<4m zUfmOU5P27=4a3NwA-H7W&<(e-gKL0+K}K9w&^D8IiTVr5s^<`Q&q+BA?iUb`6Pv5B zGsDN{t(rupf=576*xk5=$AGltiW_|`?*QVe_oFlq&{&68y~e~uMc7Yx>O_&iWySXB zfZ2@D%S#kE(V_nSW6zV;OD&Qp?1T@gwcMZj-i+EjTS7`1`V?-7upRMrqTQ<V8J$g| zEv#cOq`Ho;I`XWVJ1um<1k~T-%2uUf8dwaw<PIw^I>N?7ek=l(q-8V@lTGNeAF%yC z3VreVbT<uD?)F)M44sb%2i6d@9bt=GbIM-)-N{;1YNj#N508Ez`>*{}xIeBQPM+ZM z^;~Q4k7734Ny$S&>_4L3AL)9;@lAKMN1S}#lsZ2Tf1CR5??}0&b7V(pk})9ObbzQ& zs_f?`xC2YAD5eJ2UUHvc2v$zz9U#j|>4MQpUcl?^4A%f?P{o>>QPNdKu#!QdkEi9W zSCagE=z`2^72BA5`BuviuFiIl<&4Dg##(H<h8)~os*mc|J){X1$9Ze+jMN)4;1_Qs zKRU=Bc@X+?TkIvb_%`4;-70o6LCn#r(LUQSjrtnT2lcC<hE3FHtjfeK^7QlIqYt~7 ziWc3lVUWYH=q;hmgD+)k!&SKZ&R{EwZRJB^TFyu~A^gI`F~-za)lUrkW8gIe`cQZ4 z5Vg09syT{u6o(Q%l|!I`dXIKd0Qq<}7m}FE6yplUQEZu=JKIf?-cs3%pCC4^4rLF& zEFDggThJ40={v=2egMb;T;a#0wMe~cbLmue4VM>R`)mNIpOlOwly#YwrHRzZX(vj7 z*8<PR`<6a<h5NFrQ4gE!YqKzK_aK+d5TfTOXS`lCg8Y?#R3Tn;OEpt&?yd+eHQMk; z4X9W#O?H9Yt#;?kEe=imm#dr8)syJbXx79?_<BkUuf{JSs_sOn<s5FO;BeHz@|kxQ zaXj5nXxWH~Ea$m1Hd9YJIhypX)A3eA@%^paeY=p)FjFyi{XzLA=azzp^#pY3bd(;A z%<JBpTdt`sdRZ-JkZWgn44MD=Pq=06H;`#Rxws#+fdhFGaJkwkT5^>?KYnH5KE?cS zb1KKcEXJ`t{Vggaq%4QnT0r?JCNOaSL!7x%0}uwTi$k&&5vUm9-U;i8tc1C3XlP=f z6%HiC__PQ&@S@1m+G>XHYs;@&q$M%>+v=yLaNwz!pt?*6U(hPdNMzxW6xJV~T@35j z8nQ@IfQ)>VYO?&g;PcFJ@}L%h!26%5A8ktlosg?_9%ENB*y`-m;^#3So4o>wNxEY{ ztj#broazuudxWr*l4(zn@pmfhuyx0{vlS=sL@$X|Nw4|tEe7eU7d`Nh69P&-L~>KI zmh4&@c6?5Ugwem{0Gs`+gYsbFATFO@byAuD(Y?=6CW@_X2$=>9H*N)gVB$(oIY51{ zqbcO3Mr{pOFETY#PBrWl?{vJUAQz*^(=|>(QUOf$c5k~@f*Tmz1Co(AU7gu*{8i(t z9ptqG|DvNJgQ8P&ESm06nQ78k@++EbaZs=WMP%@KV(gc^<BRl$Wj*+liQx1J)Ba$U zsk-+f5WPcc`^lG`F2sZ_91gkK0i8i%J4e0WH8y$q55#aVoiFYqH#nPQ%Lr_EIMxX+ zR``VjsnNf#muWU`&9=ibcIw7k&IyR6XuckJy3{gpLEb(|XbJD<=e5mONM0*lRD+*& zU-%!Z0kg%Yq|}?QPv*?Urrd$J3{!5RWv|ez-?FWdk4dRLnK>i%6BFxKmkjNrcFhzw z2e57a1Dwk~X@fVay+lryu|8!NRjO&YcuVZzxoXV=JKTY`(`n8ANH~j>>)t*qO8_C) zBK~J~8{n5Ha1*8}`rezc_R08or2R|C3?o2a>Z<%$Thfz>!VZ;tUk3bj#)z?R(HZ`} zUZob*Eg+55<ZJ;0axwa+wLSJU!wlqMRAy;X#Wqq^!(R05{gYW-qKh2c2K-Z8ve&4m zN#a$)m5@D-&Ea9_!O&LC!z$wm6JG+<LgR2I(_GB3rf@h%bM9xO1h~UBYyts}wQMe( zcFXApK`{5`>P4Cl-dprJ)Qs(~_#Cl{Ta8#!TDpuIjDj!_TkQ6%sOLE9Ak}S6>Q(1^ zofcI}M{^u<ww}OrGC1KWRGP6$L?Z=A>;I7%b(i6{Vh}MXc+%huQa!|GOXA&u*umyn zo&7FMN~vmMV)EqyYI+_~MZ=A9Oc8GIT$0?n?6Ga#KsS2}BRKI&a^1$y)uX#D7U83@ zJ+u&Yn4)OG*f*e<E$4f*zi(XICiEyZHdg`*j}^PwUy9vVYKH%&7b<STtGc8M6Sexb zCF&gTph*VgD!OMF@;#4fB<LHcgBz1$E+dgYmQ*dUA-O#T`E~`eJU5WHoM)*ZUsIE3 z9##)J+8TzvpCmA`U!*aP&f+$3Ts;8y<fW(9F!6Ub)7*%;@ycm9yvwp-rrvzaL+>Jk z^hW~ptpO8*himTgo`l}v#h`nw!EC08Dojm_Uu1F93yrks*hCsvk9KThGrr=pswGyw zW;MJteZ#a}yI|L=igCtNOOD>rZ`vv#VHDPuqC7n7fOvsI+sY2R<XFu4Seuks;`_Id z>pnMwY;OgbI8B<*<(k$vO}!-4?_L(7AmE5!dpmcs!=$QC8oX02G<{cx+%-~0k-lMb z%?0DOJ3y4yk}eKW1~(sY@x%Xg4_F^gz3KA@`EQKV*AK(t&T|1(h-!J=TEqx3J+~5R zG<!H?m?($zv#NSRRG^<F#=e+wpzkq4MbT3Ek9p3j7n*jvO4P+PXIFY~%L?Nz{<hLS z7y*TJTy`QOpJ1hLNx4Lgasi1D0>{c;_vL^(WPz595@TeBT2;h%+)vBi@SX-Y$A#k1 zIcf_Jf}pYr#J=hW$HG;1Sz5xnwC`e`lb<Z_*k`T2z0*PqB_&x_*maV36E@vwZfRP7 zj?%<~pYV~;GF5yxj42qqxNu%xu4#|wvm)m8`5NUQ&K1CRf}L28@t#$+@8Bb)Gj5ZW zv-0g4j^fYP2EX=n{pX{rq+`U8?hI$@WgkBjn&>}I4fS_vJ3bXm7F$RqsYkuH&>98Q zvq}+UwdU4tNQkPYIro7BY#7D}Q<Dns;ZD$9X(2>AcG0MQTBq}L-tM$y3IM0s6C){4 zNuE6SbjFkd>LqQCBG($jIS5}A=L$m}3a)iPSC;qcZZYng`v@CtKYrx83`A(0_Axek zsNW`Y25ol^C7g0xosRyX7j1fZc<G$H0%;Ft$$g!SFfJ2}H`SV1fPHij=2rH#Uh5t# z*+1_vxj+1!LvF(@O=5jcKu7v&ouO7qnpBnrobz&^;E++(WKt>;(&zGXw=bWS^&ll+ z(&s&7BN9PdI(QJD9U-@c@c+<(GBeb~OQx;)3j8>#L=mpK%O`G9H+;%L(^}brk2aIH zCVE?z^vod#O$8g$c9w6p<N8-D<Qwft$MubgS0d9yq!+IYIdhtmOoun8Tq2G>Ti|6H zB>@mm*+$kM>P$$_xoL&zE1==@BD{CH#jLM0d@Ow_VQ(D(LqwGgLqmT=PwyWW@l8fL zEiLFQ@kLqiH5?u1bzn^gJ?48~6iF)EFC9O9X-<bfL~Tq>541t5e6^;b__U_)4j7WT zaFYj$6G?PerKr&4gTh0EY7@9OsVZFVd=}f@I$9I9%^T~Eh>q!9u75_4rzXrqZR|t+ z^WnbxW|9GkE;d7F;mwy&%oQ({F2DukO#JQ<JtiaCZkZ5w(qDV0?iWZL^iF(QUcI() zbRBnGq5y0C=WA)Z|DgMBWUBJ_ejqrGNUQBg1P`u6AjeW%e`-8-ttXeJs;77)H`oo8 zBBw<e?xqYcQE8Zo4{n5&Zq(r0=u<=MYG1>D4$n!bi_4ymK-}-u)RGsrTS$9?4F_#8 z#W~KMvj+=0$%t<w*u!cB<T*$W1?A^E1>jUp`Nb@V7AbDxz`CG?*d;-8x~z!)QS*c* z*rP-c<0~=ze5^KO6w4Gi^QaajBQ)uwdDJ*dlyjQS%2vNry}xrD2q%R|$khumR>}YA z@lTx!+w@g9Ci0}Y!72AH$=k0Z$56>opMTmy4Vk{;!pBl~x|@x#NE53){Upeyy^SaJ z^OjuzXx3FLG~4`!H^&lX6*hucV)^JC`R>$I^Ap5gLH|ifVP1zranP8h^DRrCV`FfY z7lUH-6o2SVN9P=8%6>luoj<x3`5~;Q0S*I+2`EU){Bf6EAW>9iZp=PN_1@NPtCidi zl}octONJv)pZ^Mjs<)H%_{^l@<7f3A4sW)k@%-_bBL?S+yH-`VR`-NP@oar;jq@DU z#|TR5sE<uxdZ@FS-+*~Q?=vZO-XGeAQapFx1gB)&p!3I+1{4GV%0%39(#{{Hyz9${ z>B#axv~VFmw3P<9FQirZ(hRQ&S~kmbn=Ak4@`evj11dt8Q&MhR_#s)=6RZnuU5W<9 zn0`u(x#1@zxz5_mIIVSqtqVX+L|&n4=#%irwYO#R@zL%xjV@Q64b!?bH$TQL#x8RI z5$J1XrYTLdr%Q-yBKOLjpL8~P-0jM9l85~giHYeqndmk>Lzp(UGELc|J(V7Um+HC+ zjgK`VcZS{XxE*OZ`WQIZcdZaKmcqpvw_sBb^h#HHubZ#zT&Uw<phD73oFwn+d_Q}( z-S@TZzK55tTJ^3)PG0-Wop50}E>2k`PzDex<u&7VJMuQ|GKBN}BdCLS&zz7PI~Ql; zA0P?#dv_&8MV`Pst?GeLS~-*Pd3i;;#qQIDY`x9iwrEcfNJ1p;QbJL@6=R;(l6(4T zs#{8F^Zg%Q`WeTM6+ILU{M<e~_deg^(gEar-CnkyRuA33R^P(*1l9RutZxLwuOMB- zGl2sFonm^3YkT;sbhor3vFHt~4pduZU`&|s@@KwEhpOsn2q!0Gg(0=8M?)>5{?6_A z8~T+`*Xq`4s3O-TAiY+7LE+zS`yR!XhOL^?>~>w{D*R%1Q`&AKG>cv2=yS|4mM(`g z`1MBYt0+r&LvP?n=hx>m+JUJx&KFfwLsVNI&4~&=%#s922(W*)U2&P+yA~CtrXu(^ zlspsI9=E$g(buF94%f(1wK!FddRVPrt7$Y@&Z0KnuBIZ8tY+=vbI(gTXxZHwR}(ih z^u1U!YCHXKuhs(V>waQ;_|3DHVtPf3X$$xQ##1-VMIaJgXrus|&g-RiAOo+=qS5DM zZ$%wQ^aJQV0Ke@QB_n`voTU`vft{Vn(`1^kysH|;ist#2?z$}`emOQN3Haf|iNd~g zSt%~AcJz7v@?}Wt%nTax5Oc@|6LIQ`|KOgl#k(aE3DEkLRaEMII{TM^>_Hm?@ag{A z!oor+>yna&mZL#yIc2PBREBUf)}Wb2Y#H{3r`(1#;E;;n-;(xfEhY=zv(ww-_q1i* z4ykL?0$AY-ACmv(i9V+S&S2izv#6<W&O%=vd|e75l21PX$e17t7xN5qa}KO$cFs%< z8Fa__#o7idrHRRlcR%&Z1le}bwW2Q1(FD!hB}349<zT(c1DZ2uKGIxn2a$oqL{^Gk zIB2e`d5~EhpisFq6S-uo*kFXgxw$!DoFc0~;t}Bs-2nlKS}YdB*di){0N{L*;IDX9 z%&_#?B$ye%-q(9<r4;4Q%NdkeIN3-5;Cs)tAx^`n-K=0#b@?mOqo@VE+<FiBjLv6Y zF!d7^D&%;jU2L0HM>xaMr>4J-7iWau0gwGnh6KVOG19~&;1T9XZYtn8KXH-__bjt_ z2yS-u*2-mBvPhdaDq&}le}AX8;)Rv<)+LV-WX!ONY1xJE08r2QzF{dpUj3ee!mRe& z+S<$b*U#$e>J$|fEA*~izuw#5&Xy`mVP0?3Y%Yc&Dz2r-%YA9a4>Ac6rW>#^XwTTY z&^_?2Tk(fUg4CVqvc|^739`Jr_e@M8dV4j1;Vb~dp`qKNOJ4U>C0+h-^TpeMm~du~ z=(sqm^5KF4o{;^&Ps?u@(jacB0jU*xgZuGOS{ny8M+Vq1wWv|-ksaQmOp<j-&#X>5 z|MQ`xWU;ygz~_BcRdw!6+=VzG7S{u6S)>_JAF$JTw~yaNf%D7}{D6sS`nrV8z`qcQ zJKq)o;<V9>-~yCY$gGXTviEX~7VGZ3omJ7hesby$*9{G0^~R;nvEC#%@C72pXpqb! zDMclBfZWWdb*?M;zi0f{zXm`{rup7s@0)vah5TBPI0u#h-<rmH(emMqU1$%jAUGCj zz&rL0@dyvWI`IB*x%4Z~(fQFzcl^IG_h-%&w*q9E!Qk_TKHk%o&+fn41E<4$kyC6g zly<~Zc=I!d;a0P?VM5=0*UB}za%5~zz&;UGOv;SefFJB7=ZFP?egUngL%ZYo^8cNj zcg83b>Q>rO2D_*opeqZXNhR45MpUn15StUZV@KZgmWVMEGQj}HHb<L43u;7H*~LF$ zv1r;bPe9&t_pw9KV&hNiYlfE*d<4V|Ai49+lnyZVe}RR7vGW0Jp@Z!cZ_@R=bSGU3 zNO@AIwU)QO(d1fkxqt;Tp`(W*wOPDq3yQ?+Q;fv*r0RSux+Pxk7>1qmuQZ^8bVGin zjNbUws=)6v%A77cA9W<&XK^E;CF4%jFufr~et83LZUt9-f7-JYycEQ>5U<AoTTd{o zOR+@rnCFMYu892#!~RfUR=4+Cy^&u%6gV&r(S=vvO5j#-o?gOyQ9XTjh0#LNj=&)u zt7gZIn7+#I?zpzIVC^r@2YgSm$&G5Vc27I%Rs7Ytr=ML{x=Vok<$p*zKsTRL3YH`5 zbzwJ((8O|-sR8**08xgGaO#f!>0TsWg7?Ul!NPXXV|SWtb=HfVi%EYPQlb>s$0YxH z@T$OrFM3wE_fL^BpuIN|wY?xF^~STs&LD%DvaJ1KmO@ZxRkrJ=(<;h;O}q6>*}sao z0e@2Tst)GSv-rn>1Jkbrz?$>Fr9@WG+yCM>|NDlQf6JS7{Eq%r;pN>(nbWUi-f5~| zL;U9&4=nmsLFRIy<$;%_`r!Q-*S@L9JoCmDfPj7WfB!DT+q&wnHW>fw|4DsA%U(b8 z^yY6A|2G1)ll%3M*HvO3_ey7906gq7|GR5N>E#@+52(%qw)|T@@bhb>lD`VpY=yIg z7J1SGR`?rB{*39XDgYe3Xb;(ZZ1#V3*H9L$y134A=?u@+-_w|B&76P=F}0HnvNsK} z!e{<`a^`=}r1F<>yvfJv4{;8&k+viM=dj)%RVA3ynDA1)8t`z59&pP;tEtuRR&F~5 zmJPL?BATv>M(|izU$t|{QpOmSx>e?JN-36Bnc0XkA8ft9Z}8PS@JubsZ|R(0FB<;h zKS%C#jaKmeXq9AonZ@BTF;O~W`e+u!6eKV)w*U0R!Mlp-J|z6)vs)I!P1pF#EsndW z_Dh;>BEZZ({NEF}`K&4Ot<->r>Yr1M%3fs0yB{f?4KRjlRh_FTX6iOcN2nk6J|*db zu&h1X<(Kgc>WR!Eg)Vt?jIjE)?@4wYFX_(2o%!F*GIM;|dJjMXZj$*ap3$;u(2X0C zY6rzO9)_*Ojes^dtDOMGx_-hs?mX2BguQnutBK_pvLpOop5YCcBe$P|E%E>=kF5Ei zOfHV?4c-C!3toE{zB0SlZ`=-=%5$R38neIUX|&$PgR;&q{PKUbbp__g7FmI6TZBh2 zWGP*AIT>5aqrRXaWyW)e3Qp^iT!u+@sX7gwrX;rfSVmJM%k$S{e<Cw<!4*T#{q`0} zem$&C5E3*568AQ1nhrBz`<Wce(8ia3q|CuGMmEucvAQ*`!mJbf3KZM3ZpM;ex8Xd; zP*X_>OuOVtBk&-+I)6`1r~C#&roud)j$-a^&T@#7jB{Qn9n|Y{Cqt8k$d8(z5?{}5 zs}T|4ea8aMi%#uK>NlT;#TXVjT|SZe*783L<_u|~gn(#Sfi^C7lO0WzEWaODDk>CK zSg7jVi6t-vGxtY+yfND2G%>=^?P?@>Zz|Yh9{yeF?JNk?krZO*omhT9T)xYQp}kx5 zP{uHRR^g?Ozg>H`*x@<-`7ckV3cJU9Mn34rWi@>n5DwRD>@bpOw}_MFWRa7~a1Fc! z&x?Mw!Z2)Mp*I%kW<i)Rq%X4VsrcK^0#+1inH`k#GMpt5XZ&Htx3vPs1y4(T8n<Qa z`9x6tu~0>Y+6lY_Aj@gjAIut&3m(<o6*C6jiBH)_D0v2)m_R-~?!~6;USpX^^#>6b zAJeY=)4iM*mqn|So;guJk@cl#Qre!pU#rC=QXLrl!f~Af974~;@2U1oORV~Rxzq*9 z>YV6Tx#_R=!ii3W>DJ+mT}Fm=2nc=Z4<qv_T7X~w_vQ5!00c3S&EyUz0EAE`OnD*$ z3JrUY7zd?Nn-~N)tKEK3g1YfCo|!6MyDEz<{-Hn6$(_$fD8}|7dRa9_V<l@!u<Bz} zfcjle7BE?OG~({tpl4RaXTie^rrH@E*N?#O%E2T37b-?CGsu27QvE1zfRYODd$9>> zPhf0si4WbcJ`YASIH1OFwCwhUUwnFkdes_MUL7v4t{I>I&CXevJ-kg!GPykQ`tG>4 z$f(*tKbMlM>BX(eY~HBn{O`(_a;hW(5zRV}|EaqO5Ce7=7|CX^8|2T=(k)PutGWp9 zW)+qY*C5~TjVn|izsTPvC6A$WbxXac#=g$@J_6uJ?Kd|Zf<B%P%_Su#AGK5PaP>W< z$Tj%X@|l~O;z^<t@WF-pq1wBf%F(dMyZI(9uNJA>J%l|{%Sqvl-Q#8yA*^b9)i-mS zy;5C`2~p*v;eA$)tU*trUht<(7TR5j_!-#|olcrad2#UB7PAsg<auBeZB-kRQ{m`{ zh|XU-7Ht=Vf`;f#`;3&j=h<_EveFM@^f+v3ml*IPDgUW9#z|+`21+cNS*e*#;m8-f z$H|SsU~pgJfpN*Zt`o2s;5v%Z7$7A+uV5FY8=K~wvS2(4qBFPEzg@}hUs>J>5_vlJ zw&AjtVM5EEHv4<nC2Hx9q!T_hL7MO5Jg)uOo%e906Yin9DF%FOIp)bzl#QeKiZ|^k zL_uQzkM?ch>ZrRBXpRjy8@mf3DW}4l+#6wk{{(k6e2c44A?R7%?f-0re@Y1Mpbk#Q zNYJOx+=>l~`g(eL02f&6$&-e});rr5j}l}%(?5nsu6%hN&qhl&bFB3VD{R$xj<}Dy zeul@uiU4I$Yo5+1j|evh7gKXqtagv{t6A()fEy|6_!~O6wLa_l*;DBdaK3K$-;^_i zqswiKG<lXfMAXiUrVV+HWa)G%bPR;U0%FQh3{!t9eNi&;l?Pwu5jLgx&!(Hn2#}z3 zEq$qy9#|HkZF2HExbNlV<>smbWy<nvDa<5FMLn+)5c0qJb^%xtYw|il9eULmo19Eo z{zxAk4+e*d<36Et?NkW&?;JN$3r<tgzDEGH8|acEEDI*-yI+^TDgSvdz*kS#+ENA| zBhm6jD@s&OqkNcjTR}b}XP>MyL``Euz?sHfNs&dzmb->GD%s__h#9~uygvwI;n=~H z%FGLYuv&e!%$NL^3-%`DCgucl`p#%3Kq+5v)V?bD<b=UY<O)XPZ2gg)-E`q*U|{96 z*{{xfX2n7kk$-LPE+WA8p4kb)#0FB?Y|?@i!_DuW5IC)U0|LuY^r<RmyBb&97``Cl z_;+=DNb{IyPT`s98{z5st#q1kN{R72+JhtL)rH{nLZarrT&w?bta8#W%Kb@<5P-r2 z=N3$yy*<*Wx!~}`8b_LVAOyOf&wI5ibyVZuR2CjZfbtzHUy8&0QDTtF%;cG4jQAD= zz-K4-D=Uk8HO$%F&dG3aaLA|2y1)MR2I_xmrDMNZMrO8hyg-^TF>7oCJh8WT$!RKF z-XghQ=09>PD;R!O12V#{#ytVk##hBX_NKY0JjV{yVEic(o*SEIp=~VmkT+CS%;!p` zliU+(nc@y3&-Mgi+Q(}O7NS)XHUy};?kG0{eoVM*CeCg-$qeYbG_a<KUut3zvR{xk z#r*5UbVhFefdHw_Y)f#ke0RdwxPwV@x_8{5{UNPjLmAp8FV~uZoorTswqO!p1$}&p zlzI6mKv7XcBQ2Iqb@gx0>{s{CwqdB%7@pKgRO>y)d39fGd{gdp`;J`q(~cza3FLl9 z=Y&@F`#VFJODS3B<R`uceiJif7hu-7R9kQ7P(ezD8NC3tJ2T!*h*+Tw-PN%gW1}$( z{14vujXi+IC9jGZ6ruC1Fc-AbeFDp&*4>-d{9fB;je&VQwvB$<Q=V)@iNh`oJZhp* zmQySY`PCTydIwd#urBb+J2YB=<3(r{tG#)1M^@X%ZA6ErzmtMxRLBHQu#oU*QaL)u z4<8d~pe;c0t(2pak$4uY#DG-aMXfOK2^8>e!1+W+Kin^~-ZWJjvS}iG8>gh`C1to8 zF#YBPJX>NWn|<*>-NKYDudD#%Y+Bo@Q1t{e$fnxK9-jVMn#fX<L27hDdk>~a-j~&C z)1**000n{vESxix=Hv`Q4jfHem;NeC^Xh>1m#bX7gG%Rty3(%9dA(zORQqAp6?BB8 zU#BNRHI+sqo#P7M@x3b!4J5@^XqRPjGuapP=H;^q=Ih-BBCT*EOBxlULaC!=50@6! zsm0{2^+}YJ%1@8DhyRw7fSpp#??DF$WZHa-oTfN4d{Iw#uX1t(T|@+`(657|SgiP8 z?JeU?oZcGvRzWc>;WJ*#(Xv8~aqcT>r3R@9X=#eD=oH2>p-+xbvtzoI5AS+NXX+UK zWsrYj;l8?iknOpnxFS;P`2ACk1dCt}`PD5@oPCSeGQGaAifps$<*26>kzC>aFBw1b z3%KZc;i5*yq!ow4huxNa6(3bbv(cMA&JCTPzZNIls(y31_pxSF&MBC|SGhFZ@}9X{ z{Jq`zZvA$ut}gq3ZT$1>-=s-(Hi)K^lanW1UA%>b3=9l*yu8vTPV4Ovp55`t-PT(n z4A+vy*KEoxR2h)^c^U(JWmcyr)^=5EU0n>x$<v(ELDMT{9Gp|2ur0A@;JDOpWB!+s zo^6B$M3#H5+WFWl#`5WmL*4gk<WPfCQrDw+m!le#?u2i}<-bGI`$m*U@$4AgcMY=U z2J07ozduqtsNU?bT5$bV3yWWRw_e~o>&|D*JWuu<<ql*nf)cAnB41nR>XTUeHW*g! z{M*@56YSqbfjk&W(e_KXZtCgk4h^~IaB%`XwVSHBEWg`Y!kzKJuztVIb;UW6_m)Yn zT0%4IlIMNiCv^Pj3GL=T%sb6VN{I`cGa%I~)(8vLDS^y?kHmutrORL0?zkqfGxe|8 zI|GpZmf)~;nTJK__BQTS0^)64YpX_yq(7OogULYRe_UJ8mcOG@V)8Rxb}cBVFf`OG z=-C(GP3Zk~EA#v;VA9mb@0<mYP_L-d)&WK2pX;gaD+5x5!o<YH?$xVDF)_NKw@;-2 zZn;vCCLkQvJ5Ce~<?7K1X${-QE-i-Nc~Glfdkp}8*Q&5`k$XcxQ}BT7jG~(V|Afc{ zP~-wi1M+|I);T$M$$9jTwH`kf;CXCPb^o-y<8ya{rb(0B0g1TW`Ure+iF3Lcc&u|E zy-q}nF6dV2?92cEu=?xec~-I=qMfFxt*!l7Lxc9yZ8o@xQPS6!%2sV37gl<>`7JX( zqq#WmUD<e*_==8I+B?!=d0`L5OoQBX8A6->|A%8rz`~%p#_;l>prB}-!K<zEcSR&6 zbH54?c5r{z&E286bJL*s@#1WI8|R>L6Bn?xv3u72(q@QInoGBwY63m}UJ8Ccot@Xh zp;qkOuOpdg;Gb^XVoFU)qGw}65mRs6ip@cDogP0@!1d0k#osh2Z7_WL>3PAYPoHiu z(b3Vdv9Zz^H&x?eTxvsLrI4oshZMGd+w1S=W6Ak@zx>Q2ml@FI*=87s;QYwUENxb} zqjj2(U&9QT+7k>1JV0i)17i^o@X(PTsGnwUw({f0!|jJ)4(eE#M=!^ff8MkIcur@= z-wZFp-4Bm96qLC7Fn1~iDP-8$CGX!?0D)c~tdAR7M)<7dzK4-Qd%6~=0CxVPj@DP` z+HR$M{&_*SJU_sl@9p?Y4m0~58Rq!So0P0pDARaJGc6IQPOEJ!0aPVfq@Y+#6pXlU zD*0I>xt3FX5qOo}y`YJH{rWYqFqm0y--M(<=uR=_WAF2lsRODlL1WPWHqVEs`aO3z zuvgz;W=u#;O-+lt-4Q=k12!!FU|#jnmj;Hl(AB-^`LXDm{;;xwthoZfsoH=);AwTn zU;kwT7k)qZpQSs7+>b)9AFE<TE=R#5LnF2Ny1Pg1>wf$VgVr;<n3x3g3Zm4CI6s4+ z`fpE$k?i>Rr&+y04Q9i$_(T<pmA(Fx;waF!hvl}u?_&Z~<e%;CcQNFW*&Xuc&o*@b zcr@Vgojs#=?tk>^_%F5Y>y`ibk7pc#*WuSung4f`9n%}wUv(A2{zu#M@CCrizuo=4 z$-fnjQjhk?*8fvhsS+zSbTNEypxP>kG<E&Ilp*FnK5ad8fvbOkQ4NTeWZpYYNjuQI zk*4{4D`|S-%y9OW(K$4=(HGEH@ozcT{AtYE3~#viMQOS{9U0O6Ug*)}+L%N;=Rs>v zfxM-UlSr3?8OYhB_zr&0-P_1Z4ceX8z1DK(&)+=fGyf=Q=WkbR{Zh;9fkg0xu^%cf zjsu+)6p0<S`PTAZ0p!sQL_5U~kEB-6<s^oZY$77m%dmPF;L1M#q<jq^fcBJLI`cap z@E@Iv`FXTcPz{O(d3?iGY7cdm;%wKt$bCz@HzGpnx#fMj>b>YEk8j}h)5WO<?2Mve zlCQsBs_VP9a97cZQB7bUbt)6c%Op`zHhsU-&E6*~nH~)8Q8rZ9sL&@F--`v3b>Gy| z$YO<fCVqcHe@kHxzHv-ln!o^BSMY6S&Q4J3x+O#Jy+~oon?EfsUpe44Uqz0@z$E26 z@#7bs6ubiNecdQ0_TaNo+?hvpdJFo1OZjGVF{w1vhn)6@!yZsyN(_AF&3{n=-#n?l z=-ThIVm3rTD4#9janZEq#llaz)g$O!v+W^aFlX-QSpX3A;Q6e2PszJ2lCk0yv6c!U ziQx}vutO*Agf4pkM&^5g)#mpV?{A%OGoh(EQ>_2?siPmpfHa|XJk4nH(xLC!l^e$v zvmo51c&SDouwxe}OxK&<pMS1Qr=F3BU`Xz@ybJCYIDzCo8?tE?n#&UotyCiyV|9|S zlQBRjrWPQvOaIrKjb`Ke9!^~csPn>?jIi(s-N{T-Ya(K3_)PLZM+(;^fKZ&PB%nZc zEKLc7+2q-qH^LGqTQ2>+mj0vKI<GkhG&mV#^6*U30$S$&g9oGu9`G#<@d|0O;}`uP z1%sraIwOGJ`Y<evgEZmwk?sB>{B8Pwd5*n&MY+p($RPMa{QZJna&gNahCwcU08+*i zl5&__X8CdtbS<Q{s<<6wY9_uTy!4!G7F^EFQ1oLQ8SYKrEgLS68V3i<tT6aSmfHtX zxQHI|gQJEffCHLxVzX9R#H++-kWI?=jGN56!U9;`AT{ypV3zH9zHt2;;`#~oUbCBC z8Dio;i1?H>x197nC4YnMP2Z6{vGvnMZ-a`LgrvF@p)2b<xG%QVk!=V6-v1rj|5B)1 z8Y;HpDhW&~=EVh4oKfdS*d*_aDU*zEi#ow!l7|_YckoU+Oh2C6B}+QtP#T2VKL-nX zy}(T?pS2P{PA!-UQrtGQ4N0zdKJ)0oIH<XEye7QFYV$TYAlNm$++rEzJqs?r3|75x zXH;Y~NSvQTu|B?hI9woWOr>7T<83*N-huzYBE&>XF9^%v+x0Y`i6!mF_*h_`1;p_h z*#Ejqk)B@2g{@*pagpNF=H79?;kC!I<|+@7Vbc>uBd)$mme`?B@BN)JIfSkRk0qDi z5^o^iV)lzK*9<?9YS?NWH*U`pHPC*FxzjG0G8#?gP6-AL=KRYCIwSk~FG2eZ%u&c0 z1NWBZWjZQ~`J6_77dH`k@l(=@f5lGmYS!D{5l|Roc@K!mm(J*=KQ_?5UA(`-`{5=a z0Vjl&TG+>Mq;UV~)++8@wR?YI=cBH6>MlyX4SM;{_v0W~zY(ZiCFP^0L>&7Gft#U! zDV*4o6x^-RZX-6DAnxKFgE~(?rD!bzz6JQ!Wu9x*@<nRFhcaN}aP#GWXq~TuusdT~ z_X;<wgIQHY60}qk=ub`h#&z0hg%8uSsHCDD?OzE$u~XQtVYFMg8k~S<Xh*aPXKaOU z*%Y6T!0@)4h)4ou9{`@Nnsw2_2f7G?bbGK^f+9evQdN4li5gG5{YPKPpO$q^hr)++ z5g#G+;9a*vvG03LZR4EnTnw{Rx!yCGbV54IV%hVUut1sVZ=!YZH}&xIr{9b3BKl@h zK*bGp|C-S^xBt@8sdhRJb<YvS^aA)Zd6tdVvfdUyAR-=QU8cz-4E&ipG4T_g{O6mV z;&40JpX<OTsnc_p%rD@z_s3I}O}IS6H3)yATdqDJ?<s&4tU|}GevY%W+T^$|q{H~J zKgR?6DgNM(^8~>*?#rTwY~bc=1RN#B!_w~Y;oG2w@W4+;sizpD_IA<3!i7$k94L{2 z$?Ab<O!>q1J=@2Wyi!+g9b@u&AA8XqD7+~@>blviL?QL*I$~tF`VaF4)f+>ORu90h z!z1XzRXfS_8=d1??STwTkIVb~EN8<nid09G{|rvKPZR@{QHJ}2JD=P=KwTZ_#{_fC z4b`02*^l@J?fmgCEBmJK*JqFMvZ$>*t5Zm9-tF5(p~3NPhT$aR?>GM+TVEZ}WZU+Q zfq@7r-HOs64Uz+CkS=L);7C!rrywBRAUV22T3SIyGrFZ=bd4H}?YnNh@B4Y)_x<+w zw)4Es>p1H;ei52lpL9g(dJbV8>OG9K6{zW4+Fij^J%iMwLWNLPig;hHU7~u!RCBuK zj>E<tSXe)8pIp}I(J);X%!!_eiS`Yv7|zLPHMb*D+AzO?>x*B_(W24l)uu{Ov2lwv zz+v#gvDO&)kH{xVG&1JjwOM2Nfk&TUwKyjYN0U&ivr(&G<EyTtqIr~**N;V$5r8D+ z;NJo>%Fo0486lEA8rr$gfqaj&S9YRYoPf|MEQd){s-aQLNARE5jW-$gyOwovTye4R zr|9#H69+dUo%D_q*yA8@DT?Nncy4pV^y9#dRoa=-VBPZx*iDlVMSp&JN7+_9_QC5C z&3!~<jH<ng>uJ%$n|#92UZnBOX{1LE7FFR`G?#MX`?xp<%aQjd7M!1QPF3>Ww+US! zg;{mGc#D`fi*Mq~A%rc4H8x<eY*WWVa5b$|S4%Q%lBVEW!INQ6f)U$)?{4Euzsq%h z4qbpljq+6@FYGIqo-gkcjy6<!T*_jN-m2AehczjSB>1oY2*89gg<bYcsvdU#V%rH6 zUOn39Jw^n_J+H@?<HpG+!O##=A>L7{?w71C!r{qj>J|O+xW3j&RW9+zln4&zCm$M? z4Sk=#>uG|vbWSoBEt|8Bv640sf*tr>lYTm=z|+Z$b&~?!f&%+bbB93+gNCZi>R929 zsNw?zcg)JXjEafw;=h?VJe&VhdJ{fI#466wzuKn0Y)r10bHs|kbnJP+b?ZgFqz}3J zu)Hw>he*;#O#uRXQA<Y%_`w-fkNJZQZa{s4C@)DUH}y$fq1%6M0|P&Q?+5=?7NlK+ zp)oWNHoP;J0MSj9Ls&Ke38k35`#p0X5nQSo6<2~r8>H+gQ&j!7A-&Su6B%mLoA5G? z&5e(7j~kvHI#_7<!w;<1D*_pK^$IBu9j<HAZwR}1EVxX2T(hLR4XAei6Gj7V|GVv< zShO`?)*kOkYW&>;1cSJmb;6eBX9o|@ric9E7K24d;s|gFBY2)qD6%3=AV(jVHtT4A ztuWxt-|4mfM4?F9xP!XsAt9MoAsYDDxF%AGPo0OB_Z%WW?s>a^OZ>Kn0j}@#m@pmm zPnG@q`~O`u{V)ltGv9vLar?BoGBYGcOF!1%1o4uhr&co^uvsm}JU}A`NSS?t{9Ggm z^YeJfyC$Jwmq0Q)lIP?J+frR&@+CHj#{6;2_oT32EWEw_jU=nrZs$m?o>Flr{Fsbg z@6zj;e$@5`2c&UDV^oNl+cD6<mZt6}4%wWv;!rKc6KGt>C#1=6N4}C6>eeNS<jKB% zj81F$0<1TteNPGt3fVq)%6tFopHci!^PeY(nB|i3o*e3ru)FtCjt^`Icm3u``JKs% zsiR&Dz(Gr}oe3p6D!i1V3dz5WB}Be|P#UV}Yr`7yjir0|kkmlp!&+B-hmQH9<~cc! zCq)F9s#_PAsBD2Y-#C;=Y{OdT2!bb_De%CKMQKj@sZ3=*wx0Gjy2a7wed(o~@0U*h zinrBas0{#B_6q&ru-lAk^VTK5a5+W6G?~`mb6l#@;<}2p&YcafkEKVfaECbke@pHf z!M3Unm(sa_W=A!U!LDhDLsu?8hShMJRB`F27mS^3oR^xO)gE(z>O5-R&mes_4U4ef zgT90ILI#yTPg+8<iKba)Cg-xZ3o5q9BvMt3I}|joBsaJZ#su6Tezdy=vyXtTc|^y& zDanx~fkXD+m$TfdRBBS7ij2I)UXtx@ExFuDv!W=mYFMVgTwAfI==R`OGuvB(;I|gF z^Y>}dA<rY!H7c#rH%CVw{cs=GhHoHOsWIuYPxXDHQ#YSiPK<23&*eV4eK9SiV9HZ^ zLOZoxb7P`8h%cy#t6(tL5ulnrJH)?jZ$`i=Jbu8>b)hKBVTt_LHMgWqZo1ys-<R9x z*V<Te_}p2}?$(|Uc8P|eMYGgq3otpNG_c;O>^!w&hkCnBRbBL$Na|pF04(~`V!ak= z20aHnOx4|IuM_*oKU?Cri+fe&_zh}?9@R)hObdUst~q3iE5Ba^O<AyYG`A9^Ls+)t zjpZ;&=;T8j$p)xZ-ukJMd<|u-Bm6igo!#Sl%u^Cj_l=lw>g@u|egM~}9T@XQ=h4un zIqTjqc#oZOGcF%qe4D*V37y4|TeZ4w;H7nH6!^eOhg{rrU*thALi?#DQ#yan9*@>X zY7d3MfNl4<VQn2o=taYZHjziVE-!t&kA(7u@>~v{U5id;{QVQ%vFdCVLX@YpMrV7q zPOhkBe9+B*BD|n;;}AV`<C>(+Y`sZ-Sxsx%#X%=br}Siq8`N6wWYXcq8)@+~t|#=V zE@cP7US-=mJ<2u$|Cft&uAUd6>cZQ4MW(o*HqZ=Ls@$_zv1i+38%zCFfK=$&*)1E& z>otgbu_`CjTV3an5tY%bIZ!C(T|@2lGss%PqrrWI8l3LGZsZ@RQ#oK}XPIUQ>BoS5 z;6%Ytotd|0l}D9Z<gS-iN_TZ(2~Rp1oG;Bgf)Py%C-65gf5_3)U$%`li)RoMp9YG` z<g{OvglPPd;txSI_%&xm*)O1Br-(cQF(De#>J68Kh07|DQ<c{u!ulD>clC4gQ)mTZ zo{moR*xQVhQd{#bM%`OCx*D0rskm`3cQ8%w2M?roHQ=5QQ*j<z$l-Rxt>W8WFKTt9 zMPG$J;fOSNa^le4-zC)N_LGoAKwJ8A2~;higgutiw^F(u!mHQy@_I87gfp^&R3;72 z)2H_xyC3~0w^&^){(qI|$CqW%7>jn(YYJh2^Mz5ieE8=0r8g=M=@g?v_U3Eb6FqkX zaA^b?cP~$jThbf>GDcT!+C4Dkz97^*LZqw;@WG;G80I*Uuq3~4wI7smsZp<D{2o8j zheXP#05`UXTOWnak#<!fx_aD3C9fi(YI=iTmC178V~p&VRd#|jubUj$j+m-DH3?ke zzK(!cV!hXTeBf_+64bFGK`|oyAE9bFohMY6P5{5_pQyom899P+x|A*z^*Y%YLCyfM z!L#Lav04eUC=+GCK)37^F)f=H4w-(Lmy4k>Ec?V~&ogr4>xX6aajUs3T1=HHFr6qX zA=|$=kT9}YKHRhC%|?0!+3K_Ax{OxwSdq8~R_nz>TStQrmSH=@A6uAMp37lH45Yi2 z+duTL%mY4Uq27+QKS81FiV9X_Z)o?pl+56d_2i^!g1D$xxPDabMOBwL$KMyb<kzp| zCs)GOe;_^5J4F1@2|7h|ufW3p`_?IxYUvCsoUd2dYXMyzjZC=EaGITX${W`6cbXnZ zob?=B#&f4Wg^}s+p6%*;yR|raUvTJ0=zMN5T>J@*_YrP&v}?ERoQS^z($3T?p6?Z2 zztA{?Tw|MPq8l#o7Ycd!5oI@2I2DtB_fY@rmX;I;8iM_H7i++a=I1|yNUkN>@k5nZ zIe4*2Q*>8-dP{r+T^}97#roDF-hGDZ#cWoRZTE@UzrnXK+2z`54Apv{pS4nbLR8gW zH3CApxa0a%-V{P3c<qq|KS4AMDE;p3ZK?MfA@mw&oM7%{wvWUN>O<EUi|?dUpa~>i zS5_C_{AX=ce%8C*V$eE<2u~5PJNq?RK`%0u>oD(I5AHNg6BDGB04zb~eNl*|9((Ne zs^ESj)@Mf0{=Dk6AUUn^XdN>Vxs^C-BAl<ag6`b9L~nubo{Q^Xlio@3R6lmR1Ji0> z`Qg`hA8X(_OSpMiC5dz@kVN0$(8Nv+0P`%NsX%M|mcf-RR-B#uPLCd|B#x8Ay<g1y zc;|D}F&w_wZE6dc^}g9h2(Q-w*Tw1Rb0h^-G2)9b7?hGm$4b=0dqM<;@(QI_Oc+a0 zE?D@Q+kwD|lqmi<DvM0myW{VFhpW_WB;~Jj|Dy5B%f`J{++vVCi@K!#m(DU1=-R~| zbmLGzfF#KDa<f=o=3H_nV^Q6y31%j;mnLck9m(JF0<1f*RjVrKp-9qMHZqs<gL8YR zPsv9JP!W1g_;mX1wVkeCd|p)pEU2mU&={eaSZMp&8Kf62yq>GZiQJ5J`1)WKmgMu- zde>L-LQhne7Hd!#kz{KE)Z2LUQYx;5m4dg~!A8z7@OWHB9sV%~?+FPwJ<PhmJtogr z+4}Z}c=4XeJ7F&7c4Xk1dw$rcgGXQ=Dw-dY&gX=1zS`)D<S>bi&5ud>gy6Atq?FtF z=BBQG<ljsD!i&^Z*nB}Y3SmDp9vsO5Jhxgp=S3escazahG(#%~?!*Ye2{X!Dibbf? z8@OTyJ7IveAosk!`$jIZxJC1=jzhu*f>9kbl(EAdIR-7jI7#^X)#^)$Io9oClMaY! zNxLjkU?8gpk4qmEW2)4i*{aSb&;pk1xBf~&4Lc-?<HF7$OgIcBc#l^oz9Kd*`*8rh zhI?Rz!AhJvJCB|}F9UpldWpZD0vE+t{Hg$z`p^r{Y|gTTK%|;anS&{)ny#f#zo7iD z{EdTI{zO}G5&ub`RB&%CxI{a!Eo?r%7`&}H8bETERDmB>lP|W!9A~+$Y8ayYq?_SZ z4?sfr3hzTb0IO0q?#^NB1;FYfok160s?F{2FYS_~=2QNT6MA}JsLYB+HX9jycPCD( zF3=@B>MV33lDIhg+3#g$uY+p0=G3Tv1bS?m3Y2v8B!U?{zwU4t4A{G#j*^(wS)WIB z06BJB+;-K3>@!qRJu71}PxLSWHp!v0Gh~|v&`pXKerf<r^ZQrrHMxye4NH#^Q*Qxo z-Kry>0vQAg(WFD&ZqPl4Shv{#heNNh<ILg{9-;7x<}eT5ll!OIDUQR3qf5TY{H`I4 zFb@f_Kp^p>n)ls0o!)QzinoZ|P}6*@uC}_Hl9+E`%VyLdHgfLiqfV<F8Zd=ou<(7_ z=-T!%1Jw;8cK#FLa1F!G$z?vR@_|oA`vC04yd=r#LhxFh#uk-P-(;i(9m6eC3p*~b z3fpTOl|C_?o&FXMbKM$Qe}uA;1YfWsF*^Tj2=siw3d%9MF}Xj(%>Txnl$;ceoQIlE zd#8<xeN#Pkg})Sfld+4x2Wu_tC1^KTv?q5iX`|rs<u+SdhPj!LNIGi3KD6(4-kWZg zdqd#?22zYYD^ur9gYvO`p{rTn-)u0!Z&Dk^d;1$~!Q>#y$<T;OKH7=T$@^;-`1tHz z@ky^thS<RL#EF0*_YGl36+Xq~Xx933WlF&o=asrAE?G|$;@(D;K*>F}S?kMoP7#8X zG;$Dq4eTOR>1q6<U`XH9q2P+;II0XFzfpd4@+>!OfvVkSn^H`^OiRX6Q1_)wi@roQ z;SMKnb@n4BEX~H08)YN>B{@^Cz0_k)^`SO?E1z%0(^S*w>33YG*EWQbAa8BjskRh1 zh|*t|kmXV>ZrNq&5@fjWpG-#h6{K~?hWWHjGM>vXFp1I2z6`DSQ7t*oH~z6AQy}|F zn2%jD-zqP>B?o_qGOzE~Ixbt3Y(3O}uE7kyA>eM7WvcR6;Gi2x{M~SG%V&oni(NEN zij6efvP8pK8&Vh$50kgG-)x0tJo3qUJFd=iLI-Z9Oi|*+{D@O}lWcA?e@njW;F<1P zt*6oX=FeEy!=Ul}xW(Feis~+E87d`knfdfYT}+E)%vNt06q`Dp6aBEiV=K_5Oo?IA zjn%hBxYU$eX4S!p#%oBJni~+ohs0=OzKCgy*|4hkTX(-yKmWKd3@(fl`3rXQ*XKhJ z0fg$8!X|Nn=0%WhanT`mY9dkB-S2WL#v1iSD4cHUN4k5eu2*RD(bbD1@OafVuXDDO z-qRAE7f6@`L&=f(2>B|_5!VLR;P6cPVy6m>L1`v2hPVnzCVwsHntsFYqLX!m`N7Cm zIt&V8uZ?}$JgIugUp4pnu;4{`rY@^iC6h}`yn4M7Hr%57drr~#3;cLi%VBagkaA|k zgG#`WFIwQ$%%cNDGb<X-IQ-gHDUOOwHPBxCcJmcdbRX)G0q5?5Y>`GX#z~-_GrQxw zJF3r>9gHX%_{0-3{2@&Dt2vOUP_5#i+Q?V>#+ChQ?GjKy$YBD{0QtvCwP12mY;#bu zBNu{SC_)@9>}v7x<TYn-%dIa8i%S$%$WKG3cgkrt#ii$bAAl9CV6%)n9&w|mH=SF* zT{OlDsgwIWz9&sRA6ctxR@Bb_rOm9lTj@~XAq$$p`XxAxlt3|^gA!q)HLpwPazklz z)|@knubEIIQEAzlZ&GaI`Op`2{&AQP7eYJCNBR94PAk%ABlLk8HRLWooua#+(2D!{ zQv2it+2I_Vcu0G6&2FScZBQfEC+Ps;W9^d{Q-DM#w?)<s!U)CHD4ymz5S$Ep?+pt- z<ENU*xUkQ+jcVk^J-$d&GZX61v_*`3t#^@Bm|0`n;!imG$D@29^QVD)ozCS)gzuEi zj$t!YEd+9L%8#Qd;qfP9uJX#X!>PHxVwq`8!#8_vo;dk~Ya4!Fk1_{^&_9tlK8dvN z6<XJCyR1@_68kQ(^{!8H%5F2<lK;(qcWPvhykIXH68%H(4yKB&HbAOaeUCQR@Oy}O z)z|k!t8bTJNwR#Q$qh_H^+Mn`@7-Nr7Cp3ArM7?CWPmvoodtp9>Fq#rqzsv@c|fi7 zFz&X;Bc-Bp*4GL71RdUiQ8i_1V>#IR2W*wuIrR+%5lni^u<}@`6xqc}?%22#73y~* zfCCTgRms!tZtJW1c3h@mWIW{RBzsE2YBKVt>e4A@gIDLCfTqH{?Yw#tD`8rR;>uU{ z9kdsA?>Y|nvrQ1ds4hHyr~&D=`h$0%{<@JwI<p~@7TJUEf4xqs&2661LiNfc(O=^* z9Sa;!MExWCn33u*7ecV_$0uCs+QXy0cb{Xql)WkgM-Oh<j-$1Ey!yiT@0Fq_Mkj(u z4K7<U2g*k$2x4};%}UqRuaylleg=;DIF-}a^i0K5Qo^TZ$<w0erq(=nzsLG2zuRg` zF`dY}9QUv2tu~@IVn7l9ZGH8<J-90DX)&n4?y^N2($aH*Y_rq*(m^m{U{1~P;&s63 zOY^H7Vc>wF5}pvUx!gXQM<qNONEl+<9gDt^)+4ZPHhk$+vC#GFbsr$JLm)QBipO4H zoP^<jTs0Bs$HL9Crv5Ry<}NXLiK37LU46+ZJ_Sh0b6<$*=37Mv0NfdEf=O)JC6%7T zLje%UMn(PIN4X~=-3>`A?Gxf>ShOZzu8AW4M5W;M>ClQ71nb9HjVI51I$rga{y^RI znRpkol!`WHV9>g>btVaKl73Wq(UshjtOQ&(Lj8P$hAGoC;;7TuK2JYOmktzdCv;(t zS&)#gD;HF9h;LFR9u$A*Huku>sePk3_Tb5)M^RL2tDMp2J(IhwS}jK;0++;u3`q(F zBl(2ffm&w=*Ogt`P@+DwZ(~TXQv27{-_$`*G8NZOMzPNctka(>dp|uEj5tj48Wz^h zXGPwa_rh1c;TR>U2Q^G8P5Z~xe*f!|0H9RzZsW!^=sxEC>bM(4In-ggk{FJ=?EY#E zyPJ-Yn?I-#?;JlI9UV^`s<~;?azu^mIJ0Izq+b3Q4jAivfjKI?Awh4=1Kf>o07W^e z1F#dh6`qdv3d|!pW<8YUjzsrDUV7GcKTZjNZT9SX#a=CiX4+I@(YkQ*s0kC!&(4Af zR)PWJu9r^jRYdblmiiF`hggr>E}pRhCT;{%X|kCqlEf|0H9+IJR3f+Q>lJRp_S;uk zICF2V7EUVvfMY}_ASDdJQ%QlT?0xUC2098o4~zJf7Cuqo*Euk|ZL;EwBXlrVmG6wG zMRg==x~`Apn9oFI>&dX36TA`m#m(kzhN241=2rOR)BIu$cMm;Bf#11vgb1}F5L8va zjC{QjfECd_{PrDL(01dW6A6H(TZb83N&}=T{Y>fdeCneDoz{!kyPo1x84x*>4c!W9 z2c<=#la);!o5AeYm-MUDN8sa|Kpx`*z|nX|z#eOj_ln~+4nxFb`b<T6hjOZIn)KE= z6_|qwi<Uba`$(F1A)@P)0UcnuOaEfZ8NJf1qWFo=ADS-Pa)j3`sW?R_u95&PQ{HtZ zQgWx!SccuyWTe;)dhyLXZBJu(fz}XyN;t)?`~~XkSNp?IdBQldMV|MyKXg}y#^r`3 zI;xFpftVD>AZN?CednKS!G6Z_3)~BW24Ee{-8`O%Kfgw3nejZcN@pbL@Hdn}_VXpG zI47=d1h!b7DbQrEnB1%w$o0v1y*IFDFUE}kVn?pax;%)X*?96jQNxzHvJg5<a`5E` zC^B1(CCVO^ee?b}w*eNd)T2@HnUDoW+s;0E1~?mD^A7l#4X?&9uaDlqVIKcFqI<gm zV|Xmw=$E?B?YGU)$Bdixm%Iw)A6MM9^VqZ%S&g-}nNF0!pxgpo{@DZYo-qK3-J3c8 zMOXm<biGkco~g4sBq5OW-bt$-o0(n>7aob98k9(bl&}#xtu*oHIOF7%nW~Nx%#ZhR zv}Z=1qtj2}MbYA%O2C@%j7}l4{Q`c@IS6RN-RvQ5O3E`1jv;f3%c5Zk8!dfa?{}&x zXuu)%VV7c$zg|8)v;10wwic;A8mZ5EdVIyRX(2Q(zi04mk}|fQ!6&>8b$vCqUJ*fn zNqUnRDD(tbH&}(wp}G5(`DHsFX{Th8B*o<hZyLNsGV6|;wi$weT3{LGH6oFw1S=dC zXp8tCPy4%U_g?^!!3!iscc70f!V{1PRPMoiRe1<biAfPvLxe4F$T|pXlmO~IphT9c ziC}tTN|nkj1OK$D&&oK=t*QD6O0Sd#4i7B)HheRtK23h3y!3fE6#H>k?Ot#vL$?-R zh({UoXGaLBN)zA%O2Jhb_x5PAC3jSj$?&`V=*8^`G&0eO@M1$VuskV!Y4x2tHGdsb zi!d!Nu3^nTiKB3?IGpvW$Op+=^0xi9$ezHKh7o=ViXlJLXin~}>?@zo`Icc~TCY>d zbTY37FL8za%6?|^?_5LuDf#}*VWNM>e9m8*U_CM^>*@6@c}{+2EU)E0JC=lww<qY@ zWpl;@pUJW8ifg`%#M7ilShPuu7nm)<oer$ehJPgL=*&P_)YAXb=rGEbkd1mgD&ws} zzB`=q@C_$3s{XU{IC)Q#=6tfb63W49{S}liRvyRsd=u6xWZana^B2BWKzsMH4?z08 z3*^>G9cBYs?iW~E-m0d?VQwU$ag<`uRRrS4Z8$r&YDrh--6M9liHd|`HwnSpZVmUv zy+f9>t08dBD9jClB*_I)97e$Y3!OlbK_D;g(Pvlemj<J*N%!eV2`d{hs*503KhGkb z@vsWj>SsoZC>uiC$)6g?$M74;CxY#R`YKBP064tvD05lVP~GH3K1IHDTG}?Oci6|y z;mms{FLg1Wb)?HGB&giBpZag!BfZ8SPL~D+kb5Tpa_?^bK-nQBvNAh`ZYtv<+b#XZ zVqfvH0Ca}tNS!05U>~6en6kLe;ZGb&T_8^t9m{e*;Vm9XiGm&&WPO=Q?AqAj6)%2E zY^`LTVMpA~1{x8KFQwJ{>wXxQcXn^1kv->y1e1QVRAg)l>%Q-=mFapZVh)U)BbwOa z7DZ2*BNu4o8tu%;wJT#I!EKQjJSWgM#RrQ$#rRuJ@#7u^fPtPm&v;bDl%FWF3qswh z?H+W3xblN-_b{6DxkFeuE)-({`XNlMCE7LS5pn%c2ky&QToTi{;Q{5x2TQ8A)qczv zz){jXck^Zg8(Ei^<@bYkTuT*a9OE;}ZD-5Ll%Ky|VdL9xYY`e$i#<7}<=Td>6i8Sd zgzMy5&Vnc5{8niSgQeDLAIFb3mTLo_mOOfP{N(n2;ZdPS{0pps=wZc%&5K+in&Pfl z)O99$1GZCigIZuyP`vHmMJo4uzk~O6-BHb5?b8=I#;DpV&BnT}d$p&mVm6#77sz%` zDC@Wbi9zzXEDyo8$o|nd&n_!#vAp}ejJG+p!!GHC>QjY-PQD<lrs`AZS_{Ntf2fQr zP#W8F4)0nNvpxMr5XaaqcXi%^e8^F-pJ-+<=~~vH$!D=MWWjU2mjzy)$u__&;8l(| zxPhLT1FkXBPhfJ0CJq^b2KFf~V$Xw0>#PMNVZM0WR)O?%#LbOCo4EN5TChWRKwH8i zl9vYial%usMI$d@F~+9Bd6<S-wh68HPm8n<f;T-9s`pVx-z50=H<IV0N>HII{3_aM z!%uk31WnrYt!g~ZWar1O=bPq~9u_^yzX?ir+Yr0Tzw9AjHjq6!z%jn^bD`6CX!{Gg zzSZj6hQp9(tCHLN^iEH?IaxQgB*aj`(kycL;e6JR<eP8!;;U9v#ngGIq76}$wr|qz z8rWhXJfA*O*C*ga#$fmiBMN#e+NNJ1p8GmYMf<UC94McizxnTCGQHLB$ba^e*(mt5 zhP3egoJ)TPcIqJv!f)anCxfXP@(#I7DS;-qD;DO)8ER7jtg%i4+>2~>zVAUhf<Z%X zItpXR$4?8s%C<eU$t9QlI8JnmfD2O0>q602K4Ypdbei;GXiH}&dMljWic(C1Di?nL zRY=>fICWOq=E#RE|KvpR77YI&3<|yNKSui0f@Tf;mQO<bF;3M9xpJ`zWK$i%d^fY@ zHisX+3fO&W_+XJUf>+2mH*UMl_(dgvlT)i^x6;ifA;%YY>O|8Y#|Rm&#kA)se0sc6 z9#gxah~L8<YU~)3wRh(Q#C{1z+&i;o#f0N*VB1`D^Q-(8A!M&-vC(m%@D;4uLas@0 zRoKoX<+AFimm-PF{+uab_>?GM1-3U2!N=zW!B$r*Qh88mp_lyc)YG%8$9`QG;r%<C zg@-rsr#wGIG|AWG>nha%xg9aX0XQ=?Nugi`iCN5!F9txUhQ61oY?qaa+A2Pk1$0xr zX(SOnk+ON*Dlx`N!y)6c@|+A$U2!Fen~rW8unO6w@0OUVbN4r5E%=`kuGfXmQK!U* zX9*j~x36NeUOA2gzx-^i53-(e<y_^t?{XbyyyOwb2!oNV{QS3D#-YCf4xL7??(BC9 zvz{A7U7vm=I{n_O<34tZ@{%J~(cm@rF`w!?StZg?yQ1pkuwC*6ZyYCGa7W*82z*j! zPPw?dc3Tn0`B^@pjDP;Z+}}jl)oKa0+BV(qVx@p3@ck5oze5_n`EF<-{%Wsf_CbLE zePm6-i~h;Nn&re_xg@GBrS~HZHpK3%ea6uI+p&KT0eCyMbm#j>+jH8%x5pUi$0rvM z^XcosQE{qo?MyW&%&C`XxOCIVV{eP~f;f&X=b}=|ABJs^1zYAG^&bAH7GeTOY1I@i z6kL*CFAqOFkIomQitLcGvMjZ^pNT`7q6%M~t@07Yv&}NUKWpxYatZkCGlTJ{X0qkF z0P;F@cRoUEKOU0m8;8>ypFN9D9FwS559W)js3(wE+A-<o-}^xIY3t2QHr}r*%h#@( zIUg%3Q|7MU4nqu)Py$JQ7gitALY0MGFZ}5`ZX+jM5l{EknXu+JXK2*b{#`kX=|4ys z;;X-D$+Syxr9UW-j7bme-03r$r3Zl!0YvRG3oLH%>#dBC(wDK2kM>}v*10VCS-w>G zsO=-3x3U-C+c`!A9`uG-T1OHcA(*L3nans8bKhz{wGD<u)C$-=&I;?%d)W2szAE>( z=zZUpb<9J428wzzb`$+}iq|UL`h{?usg-uAO&G8+8KDSJU)6z>h=GHg-O_zzEeXM$ zR49vWpA>5Ej}?JoT#)T2;6L=oAfj*AM?P1?S6dky^u7dh=%%Oa)1J2epq%OXl31*u z)#e^2&UI@23jqMFFqDl0llS4C^`5W95q~Ax?;c%~m2lu2PpF^^>*vQ{sJ>6iO^XYL zKvMsNz_WY5k8CHK7R5ss5bcQ)fNe}*)wx5~c<EHF_p~{%vY!MZ{uSW8`iR>r0aU#M z1bIhe`=Ntkj7n&W-o0~(`D`VSWURHG<C@upg-f3uJ!kl0PZ{IOsEjTkHkz!^qFslD zdg^?u2f*!-nmmi;VJ>e<h%9M*6${`m)#1-6Q+g+hb@CiJx?e&K@6lL&pQMG?^3;Y^ zWQG9_i+F;-AW3jdGs0_mg<ush6Nx7@3zA~3QPgRxo6&JR=@|;|92tst!unsmXrHvI ztT{H8;7O;TyhyLOQ|%=;nt=@RRgfNFEaEv~0Z&j~OzfjNLo1wPCK<?ZU;aeJSCZdD z;CkE4=-vu6ftHI6i~gELJ0d1vkitSSX{QV1sHbll%s#>e4ri0ek(Kn~I8|@iRS0ru zdVWiPFV2jeS^(EuC!-L4clrYwXGlx?&y4P=?%dIeW)S)$qdmV%iL;xQjs7eo1RfKr z?FZ?58A9YF-)wWk$2DIq-fEQDOV4YKE?4IL$e5lDN~K6}qw-3tsPq$sr&7X2|3Y%& zOC?+9vj_AZQqlCpY<lQxDU4c+^h6G&R-}Z53s(23;+_U;6mn|GP{0THYojdUZkgK< zEi1~_OIjeYsn*OPkkvKQDd)SnF5=t0HxEJW5<Ys4n+95)SqZ&^U1mH@t5sS}Z$;fC zp=~MxK8sFdTd_aI`X?Wz1a2A{@51VHef?_<m_{PQirwRGXa_tfn&hY7&F}I2#Z8dr z>f6gJ<Mado5(~rmtU;sEjhkZAn|BBm8u$|6FU{&wAODFo#y>j@lefJe@dxtTR-#r8 zH~tE=3rtm30jcFD@+t8Vf8`jVX@M?nAzT$z%@z@Yp&COdiNC>aNCGHM66j9>zR&R4 z5KPtkWa|VBf9&->iW+lR>ncg$nL>)4IIjJue1kluKbI4b;cNqi25#cvIIWC%Gs6w+ zPzZn6c=vEAX^mHE#XEv#pp01e#*R3?Hb(o`1~D>Vl@zR^s7_Tl@RIm}DqM7{YfI9h zHm#ZTfkDzhOWWl9XeI2qNdKhPuyeV_=Sps{|6Q(`4VaO(_nIQSB`)<r-WpHDr>zEJ zFb-0HdV0IS-;aQ%%dGjKRer36=mjN>gXk-3y0TPDyX4Y?EGXr!wL*7cE2WqM*8~M^ z$qP68jKv+)=-z{odb8|C@l@Gro*8?e1|Ko&C1TpArw9b^39)?@+|i8u87!X)mD$Ix zYGo(X-oJ_mR@iV5FnvF|KpO<0XYPX=sZuPS{e$kOfB5g1%fRfiyM$DTCO-rFx&$^! z*hTsFU3Y&L2<qohuOqNu$5_a0#`c36`_b5`7ixq_Ry)C*$*K8R=@7@r9Wgsk*=O2Q zx84N-MXgA7ou$_}PGMEe*YEh-g;J|*_u*G=U0WL&wn)%CQ5<@vdj<ig-#ZxLu~#;- zcMLe%2nr%Il;j+lDAh@WMpQqS+QK-+<{QxPJy8WX#HBO_#wnLh9*)6taYKyhIX$6y z6^+>&<-L)-wO>SsHHt!FEd-0HpYEyO)^v+1OO>klIYTugr}nKVGfgwlHOz&GU>eN; zE~TV-z3vC-J4vmA+V68aE+e$099`hkx1Hb9QGX92m9)90s(2YLJk}H$V`U@9;T;x3 zgKGaG?E#t|Dd`<jJSSL_oZ~r_SaA>c5D$zQIAjVKm=KW?iEX^K>3)0DiZB3i^DrWw zpIt#OwNd;_#WQM@N?ygdKUJ^!_KhTq<wEu+x%t$aqhpt~L%%++`W=MjTf0UJyo4oK zGL?SO)yc6sneRq|%sn^nH{c&zGoe|oNvdV$+gq_5WrWR}thazHzpdOcggXGo@caqt zWV^f4bS-HPY<GA;h0;1KUCKD)=o5RI20idM0~6NU{$IIwO}z(R-jq%&(?LQ>Wd?}B zqCTOd&l`OjG7TU1>|~@PC~4&H`pUqFe0LvrU;45a=%pKymzfKngF|psYR5Se_uwxJ zUWt46vbWAJt{u~G_3GHjP7bhkyY~!zn9<O>v+ORJd9Xhkm(#XjijkUG<5x-x6gYhZ zT$FEZ@=RCUwf3WKhp%^DK8->lX4isq4pc7rab0Z*adkoYH%bu{e!PDUx(l_x5oHx4 zOf!LtAN`+i*CI~Nk&o>5G=~QqEz2XP-&o*3R@WrVZ$sUbqaYx`k&|iPWL=KUtsL;a zeBHic?eicm>!<4TpZ#T#B`*`?Kcw7N(BG3ILo(j0(!%vUF{A35*X9@Q_|iVbOq%v} z_GwJ({TS<H;Ns8<p#GFMY*$+JG@R6l<u(8v%ZrkX539(kCh>&W0+Po)pJAYaiWv|{ z)zMA_oJggT@vQF#5CUO&PvJ2uY^pIf_X>OEa&poiWmcyczlSOhX{4_pN#R%76ffLl z#Ih+vb6q6`Zw-rBG)=@_As-sP*ElmU?oo*J3i-8q0~NclK$4T4I5aD)k#3((K}byJ z73{37KyZFHPY?}Co)9~F_48p*(CqBHF^%Mn>y_q~g#$0(52$8Xt)@c9p;tGQ#R_Es z5YFnG;QWF$`8+LW9&kX|DsOGD+QD2&NFj9h#iJjRd2Yz}eC`a2o+avc&V+*%irs@} zv4;K@zA=2hO>$-eaoHvk>5OF_-59pxLvFV7Qc}#G?O?C?EYXYHMxn$OCJ}XV-WYKU zGMTiH(P_p*oVUiQFI<n89GnaF4SI114P@CuYd+a=HT>A)w^{_BeCBD)T&MJQC?-AQ zy{~MYHQ-b8KBdL8D<gAG=w~x=H6QFNOU>7q1S|gjOCg^dh@lg&kQObE5FHeuVLMZG zVCTBnLvF*FkhoM2F_SOmqUlc60}RD9N=)ZxFdlm(QH@i8E0{yNKT=V(Jof;juq+}c zI<X$^HF&DWzi#kRyk>n0I!o(C6X6Wu41K#~C+Zu~K$Jz%e%Gm7YM!b;yESKFZ$cWb zH#iBDF_<ntr?4XbW-Pi#8F(4>QjB}zhg3ZK&O8%{75QYClz)FZ#E0gmG<GV?nX9L; z_@TZfXPUKYt~2e@op=)CXJWXj2IM1l)j>)r4uDrG^3{M;YzGf#r+1acNg9B8CEdg* z?Y4L{m%O1Oi?-lfyveqsS*^Up%{_{SFgICVWpQx9)LI0u7)9x5dlsx_vQk_idsd)p zQFc=@LUu75483<Q`S%i#0FU|6h*=buu}qH@-9}+2VMN2D8jm2I2Y=<rvP7?S8SZ7T zE8HJALO`PeO<rxn%pTf*OH=dVimJ0zWS3OqW{*vmkfW|=?oWg1`|u@UtDS*VV&BAu ziqkx|qWh8*4kP|6&EtuKn^ux^p-LFx8%|i*mXhc(GhInm8z_-k4ns+z4WpO*_OYe+ zt7`#DF^DMp+qeVa+xj~``1_9m9JsA6q=Ze?LL|v%PO~nr*)8C~*Zm_%$%lmZEFEMM zS=#zmIzSDFI>tp@hJQ8I&@EHd9ifby{YcAP*KI^OT_|%~;FEQ;?J(CjdA`)hiObjo zXNHZ}lHV`v&-0cUMIhV+Vn~#4>#O9&pNz)-ryDBazm6J&1jqba^rz*oc|~A<DUIye zy=*5xiXX8&r+Q7RPUpCRw4NW&KG4Z`xTzC?ynlY>kSKhSwuZlNaKNj2Dh%}9H>)+~ zrF7i~26ZQD1e2jKeLOY^c468RjuMP769`R<GhX!&tqhYat-5<!e63Vh{BMAs`{xf( zS8kj!;a~JR?bMA1dw5t{?V}eBlyDZ3^E)9_H!qMZ-H#ly2#3vL5eDi+`N<g(Jh&S$ zVK7~Q0ai+#xJ3D5go2W8Gv~KWx(6T3pRAiQ8gU#UyvHM`NMR!W4djd0aTw+fdg45f z(#OP{smEJSV3E<OP?O96c7X%%6OjOT3;XSgS0OjoP&xqk6;=ag*Zsnzc)kdf5Tb?J zTSs;5dxZA6!%?{FF5e9DHEg0wNr|RY;btA9Al$2O@90#&lAvE`PTzg(0Hp0?mmFil zp#=j}hlD%LW7X<&%(>nlM=yD%Q|YX{`XJjJ1QvH6aiIeir`dCy9HIl(M%<1doGCfy z??kmew%N*wh>AuDV<XR(3Y8ip`+)ZvUcq|al1H<HajZVX+<DwOn7?t|=kuBN-pIt$ z#OqW3RHa4S0UkK(E`itA(&MyONmpmjKCBI><1!wR3<NpPw_8`5QI&ayOWICsH2M?Y zMPz%YyB=$vYcyGGxl>Z@Js#B&8(|;{Yw2=Nf8De<tWPLkhoRnq7az$4GeiQwKb3j5 zFkWNbj|raKmxR{pW(3t)rIo7tWZeo!%dCn&KxX-?=UovSe{V#--~S?-=D&WFGcNHC zP_t1UF?Yh=eMLfaf^dkXo>qzJq@3}N&9TClNgE>Npm9)q_#Kk4?$G6Q@iaKu#3KCq z@-VtjPsf9)Lk^^d6^TA_xuaFm%xZUbT|~5S+0hS*jaj1cQTl!!MODW7>_P}X!1Q5C z{?U4Mo#K<-+#v!68vP`TZMxwi*q}0zC1<d#o67K>gwknR=E@U!ZX{E|viU8)($|~( zWBWIf#?nY%n<V6%6E?Wb-)4UHW!9QTD>~Czn_3Bj5+h}5gfTm&n7+tLInJErKTOZK zf?zrIipcS~rbK6uo|U#BbLUW`qr^0GaAZgz-CW>oadhwMIW{ZpVIzLFkyA3MEltR; z9d+Ah2D_RuefK;hKW&ClSUjrTLHjouNj|TaOxCg;v$AWu7>jN(pHe&ZYt28lYH_m? z#W39A=|m%SJo7BLe*A#2)pW?8pD!rHV1kbfzvX(&c+0*@Ndv&;gOLGKVN4?w*V_)n zRaDHIlmQk<MygQTyVZQwI8Tz>Na4F^rMz1wfk{Z>+9x;X@FPk82*EJ{B5G%l1-nnK z6B3tIUW`YGval9k#rI#KWePVO@5=#;u9%si&;GboNUw=hAeuxgk3%WrQUyBT5Dyjd z+}=9UN23&%g6ZA5mVso<N4rI_Cwa9R)$dGx7z6<fyIEYGAk=`zjk|~L$HXFPBt7r* zQqgckzg9}q`E!EjYvIK#HA1nK7W;&G@8(4X0#!*J#Fdv|y(2kA!@6`EXEz*UF1l1g z&%&Oo3lDM@jfCjNjYj7(mX7fy+d-+n5L?Q9Q8F*?Wxdm*ZZSHcHJ<31*Vw@h(Dm~8 z(@vZmezZ-m!C+aGSOz7_i{bn=JQps3gl0Bok)$kdw3lZJV^o#3=pGGy{rYv>Y=FQv z=t#WBLDhfK1n9yL1!Hkn5Y$1GKIj4&aYR8rds94|u`E0q{Wnc_VG)p)`_1rOdWD-! zc3x8Id6kh_nL^*?5~o8M$%AvEIt2e>r9Qa<zAWi${ee7qsh-6bHyYJtNb~*;7Rmf1 zL_hYHU>kD&nF4`Mx3q2rGftja1b!Sh!1yJsuFKGiYLioN_71n>SA>yB8i?@JximA4 z&iQ6!?B`{w7h5<se3d#ThL-5p&i;T1ilQ6=L#fJ-?mJx>12IpQ&W64QmOe>LLGn8K z-?1+4%a5m(1Mf4Ne~ZN6j7Za){a)8Xd3~a?bg}iEOsfkp&neZY`_n?WKGvZFRL;+v z8l*?2%FDB{gyQPLht2vMEw(RI_@yg}Sk90GqstE*_xcIdQ&-*xL!YWhdfd<b_4chO zeJHm6(Ph(g*)+(FaaA&YJU?<_*$xhBRk!zjEz0xfYD(|@58Igt$Wdtc{<;!p-;SuB zWfT$dV;6tD3G<MAEKDg^Q79x1-G_u&Nhr%Zi!w1qNg@W4uxPJC$CT?mX;kST_qd}q zfJW3qQ^~Y1-BBw6{mL8QL;qy{S?J*rHS#S0?8Gj9XeQmYzQyI6i-YWmf8Q?X>AbxC ziTuIyTla274L-OEjlbph`p#s0LBT`1T-gx6hfxnZ2K|nnHv2n&V$zbm^^lQ(AoKd? zhgQZ?kKf|)g0`@b)~O^3w}HM{>(lh9lvAI9s@XL3T3-@BaxUuB7cFnW)(#3KK%kCI zF@_|vGB|M^i4~s5^ONOdnAE(|x1(nQ4cvvAt+Fe<BAv8)w>%UscL-~u8?E}oZ3UV! z@94g})4i<oU9HIEZBr`p-W!ywajeB4V~>7>1{Hyi_9o!$Apqb3HczJGb;6>3waO<j zdDu3bMQFF6$}@Cxo@Wv?TYZ{6HZqrQc28E^-gWpAB|O@no*{|3*X$$NyCp836^p|+ zL1uxVc{0<*71K(lS{RhpxjJFQh#<6J&hMQ#&4#|=>AJh#n1cj1kAXSXB_MKij(+rm zF&fcXv?clcPS;u8E19%}{N+Czw^WcH6b|Sm3gq(P#EqS<LNgk+Nu=K!w%TW3MR^M5 za=_8ZNZW{AGo6i+l9)}vA8!<EPdgedsl+jleYxdw_6dvjFN&|#3`dtxci<p*%hRyv z;&TTy_xO{^sLajAr}`k*?DOv6j~u4*RgL-+vt1H8zAZUwd%u2^k@&Gs&D?Abz@lZ? zS0&3OK;>h2ZJk#WP7yN4<Ea@Nt1$bfeAuWXW1UsjVV68^o57`!x(P>#^|;gj8T-YY zNO+u^({#A9*?i|UOx<dAlO{Z<(ekJ8_c;tkpCQ=2G8xAOm{b*NJG<Yjf*Bs6jxVml zPHmMoL00MY4sKPW&^i5yP5Wfb9?izJ8uHVWq{}MksD(+p?+veY7{w-H-y<2O5h|(9 zwI26y5+ttm5zTz5x1<Pou*x?;=TuS6r{iqR8u}TCJob;!@-3+Bt1kU<8Q;9UDVNX) z1+B{}hYzQt-Svu)VMvT`QB%R4VFtugYNr75DO0t0Y`AA4L$?7AP1E4qcr?K@=DU}V zd$Hi~r*Qf*>^o=~IEp6^BVnyPmFnn$K_Me2JxH;(sPd(eyjOj)<mVmdvGi!@VQc!h z6E=9)(B!hpOnA9%A%~(6UawVUnmFd&;qR=HxGQSPw74_fy(=I8YY^0GRx@l>V~*7f zGBg+jfD&f<Dz25(9Z|W?A+Dpz4~W-mj5BQ90+rh?kJuA5*?cnI?{wl%_~xIN9Y{N5 zLg&QSJrD~8)<yG)k;SdNkH6*TX}&PexdAJCY+U?)f-)ZAhTr%Cw;c(Al8rjhV9`!R zdr!49H;LDr$37%dn@X%)ldccDR(V&jjee67xgpC{xGeHA775KB+2U7X!l6aG8;j&6 zO;&Nb=dvm=XWTaGzG~iOp>Mlm*bP{*GKw2`Ne(Ibn>wil{7xl$%;<`N?<eq;$T0`u zx1;#3#XXBuKa|{rHXXtM9NLUaZdxwy{0KW0$?`zDYy<R!!@5a<<s_&f=2Apl7rAd! zbMUBL_hP=x8jf|37~GmxJd9p~`OK9ri>P;2g+?GreacPjG2l<7V~g|o`tQSt&Kfe- zmF00wjb%9E^~+|Xy1qf9cM-0~HrY_q=RucBKKb7LihaM!MeDcr5jBAO&)O;T*LMSb z4=x)_U*iqlK0+g96i!5PAtfiDM3YRC-G)1@TvCGYl?G1AP{+ZJ;L#mfwWB-n2pF$T zyPA%hGwi-o+NNcd>w#oZRg0yCnEGh=DZWza<FEz9CL9&6b)yvQFlNyCQ>k~%Z+0Ol zT;(EHd3xVGfTk#<Y2wy5X;iL0|M`@*3IXja3$Y*tlZ-q!rtpfrjo9SCh9FUd3ypU2 z&WUt$NW1?NNNl|BPI`HQdr89qOeinSA=C6!TDAKGox^O6t2}6f=6E#Ks-))h9Qo@0 z#6OdL*Vt}{wjT>M&BF>=Fqu>!i?eVQ%GfQJfKP&qu6NSGXLBn~rCI21igmiA?A|?{ zw8h3Fjt`t?xBD)vZ-1VrL@k5vb01dskR5S(1l(VP9kDK>{eAlrw8Ou2j^+6>&bWKK z4m+*}tvBDI%CtQeXtwpWzuUSwfIfE#1_cRk*rl|a%D0A!)V~*pthavY>QMH)$xX~| z{j<_<jvFdox9R?N-11%oM1ri#ZJozAyZ&^<r6SGz8EU5{3}tRuA!6~(SL|INwlPpw zx5J@u0R5=+*r#=OTGb2N@_sbN6YhV!^@Ts&!t1a7??VJ0E)04D&q^5vr3dku%Dv6G zUB?00vidx|JR}_r@tSx!7AB)(B&SxLsdt<5t<DWoy>>Va?^e;iLC?A?S*dD8Q8bd4 zzNS|6of9R;CLUZ!d4s$nme~tNf=muvw~QE35#olba^Yy|2~gAeyvz#D>@j6NcJFqw zWA-*!bxVYQ-nOawl@E8U*0g!{Q~eo3@g-*|-P^%0?<95HRC%gBwgbwG(}<&48FW+J z8beO65)!|4JNs65-|&&S@$$8W1j4e{CCY7goy8xA9h8*#8<$oHxqQk!nhPHbJ<fOQ zfAySC@&Zv#R}n(bH}nN|d_>Oui?ZocgiWdoAkuI1g)>veaO87RfzoJuRd^>Phn}qd zgsEmmFnpTY*Rx(CXzlB~Zil-p;+fjaEnDe8PV;bxMDxa?d&1Cd<9SNBRa$dR7`K7m zut|2QEkm|Bb}CV8qPh0{`~-ogP^<cZ!>$dr_Cn0>YQyGTY`qXxgvezW1&QBmKYnoS zgW5ww997S9{@wY4NJL6med2No!{}RitCpj%QP)?&`4eQ|thGF~3FjrFnvk~fzZBko ze=Kg`jKMhL0H3k}5MnFdw4BRIL01Q_faVOj$s1~i(SoI(Rjl2VW-t$rh#RK;^CJyn zVD=s(_>r6?-z9;iID=pxF$N}|`aC-R!MV>PG_LK>_dX;K0hH2Af9@&Nx6s!2cH^}Z z?<rdMzN=6u;EdyafZbJ!>|bq-3_SZ2#E4q`S>P7*-HbgyUoA(u_|^v!ZbJ-Uc8qk4 zq$7Oa{1Y#O<X;Ao)Rk!fLF(mt0c~nFfV-ZWjF1EWtGbBvHRk5UTmO%|js{*G)}!rH zqCVAeonlI5|FzIMXxZpLJ^#~JJPo{?SoFruyur6AP_-%=bBzH#xNJ(pw=&OBb~dg6 zI{G$oGJmQt_Y}0YD@GxPE6EjRA4SBP{O_iKf9c-ARlMSFZO-oZs^}?b^*NG>RH*gZ z*)<4FfsU^rL)bwV-+r%m|Ml<yw%!R^bt(2Mr5R;ob`f-1)wqXb=fLe`GkDK>9S~oR zK^O67eL9y`VV5gN<zv)JQ9@6X>BjN&)v3}V`YW&Yc@|*$_ovh?0=uy1)PFzJLn@#< zLp$>xmQ_$IFNKuT*P}hqi}joIP?pKF$c$e;7q3@gMwu`c{TdzM^dHK94eJ4phRAx# zrH@Vg{U3PU&-M|-4!D7)ek`v;m7D2gpVvV|3#H(p1H%;N{ay#C&xG5~^)!-#1vmTP zQoOz>*AIH*W$Hg@OgyP8w4+epcNcEyQ`-y(yYW-h6qdpVi@uC(MQy){c0J_^jfK9w zOIDT;M6S5kL~wEKgY>my;lG>Dz#}?@L4f8{f#xAq`}q@jcE{hbVmMZepq<-%7;sLv zw6zpA800`bEh_=xQOfRPr2qac>xXMN@A;EG@ru9VL-h<<sZ*n~cHH9^RJ2KmcZ2F5 zBo-d46hIrXOiXoJwS-vOB^qO7FiuMUJBmI4Z2$gNr|t*^vnH9fT2xr*{KXC+0%-Z} zcU)5LBYHoVl&jMlo0<I$&cJ&zqK0c~+fDS@x|vAtyQVueb2`v)F2-Uax&+Lyr9V+X zc!oTddrRRV4=vmCeEE0RH5{flU?AbkB_oH+gX~Dj^WHwprhaR~PVJ1OSm`gOXU1a7 z?0+T%&@fH0_b!=--hZ_#gcILQNlZt#htm6=Et=uZCt7>LC@@`*Bm2aWmAWT(wq!*5 zW$tUK0nIm15Z%H2Ev6fIY2QCU=cHEXqwyKlL+n=Eb^hs$)ATYdXxnjWBC>wHr?{+P ztE_RiultwVybn5F-`-`NNo9L>5$iFIF-<unnEt&Wz4{I+XRQqHvSb92Q2meRT87PE zma4o-b&Tko3fLz~bsZ)ap2jVyoggj?5!YJk%@h*J2g?#E@tm&$;V2lr7m~`tH!`#N z-(#~313}w%_{&?6Ikp6KjghUJ=?HqL5%K~uBD9qd;PfV8d-9)dM3U7@t)lYf0vqYc z|9+s+6jw>;yL&Y;J$3hnypbVCD2oXdLOjurS8z?$?CZSjutaAG&cDB0Abf_LK7(ZA z9bpVyg`Ca*#Knz&3Aj=K(@yXZVSe8#*KZWk@w?go$Xw%p2Tj017rXTcQR0{D?6lRt z2l_uUKm;G4Wx>!|g16T@o+)!!{qDw<fB%~l4`)n_+n!ldY=%I=23K}GgRe-j{41^W z;pzg+b{lq+-7)UR|EJw{&`l<o>eQ^+$H$DhPRsxIw_A%a78+tYyNr_mvl^cv8vqEa zAB0G6E&bw8g#XvdyN_@=L~#9o+WdVo2j>5uvHPok2Y^_;>VFo4`?ZpBZ-gfXz9}1* z^Zbuh`uap(U3x#D{q<mi19%tzH3&ayHcBB*J7L8?j|qUi?mvSo_s-sPYwEA5P-v5D zEM6|$<`?8zT!i}Z!j}0>&kSE_UF!};1Hawa*xlpR9Feg`OQS32#V>lpdlKDEp&XJ5 z`2SggZ<VP!NThJ+i`%wjW~?EKau7v&1Xz)e<S+ULaI{ecXGrg+Sss^>xu;WfSP{VT z_V4ic(+BqZts+Sx5Oba9$4^uFtDIYPOG(MzR~Yu`IakCyg;yF>a*4dj=v?{o@Fzo* z;HQ@UHTbvpokt@_Z6)=r_N@6uVremtnAs*KUcmkzXKx)Ab=SR*T8IfE(xoV(ga`;Y z#0*GFNjFHx&_hVgC<YCp(lK;*DJ>!;F?0(e14GwP!_@C%JkR@nf8TSi>s*IF{bT&> zz1QArt^2;$TD1*f>yeSl7uKNU57hMar6ekTZbB=?&NN<<Fzp^w(6))W0V@Cc<n+7v zCTqj6$++t8-2X_OPl!|e+QpJnsVVQ_c**N2C70!atwCc^kF7i#h*cs}j|ni7&cQmM z<dvIy^R~l$fdES|_m<kqjd%8@b%?a2>yffWtW45hA&Ns^lBse9*vTgU^-cyshmBEs zz^t^6kA0DqAQ$74g+_P#2vv2wo-Vl-Sh3uONj|~8EXqdrwr2}OSlCL>GmEhsu_JRz zSMoAwYiZL0+h#bPvbs#0LOLD{HBUvVWs0^v&WIJvZDxaIz9?SmD010G33N^`6?DG= znJ(Df9EDK7ZFIx(JN$bmJQ*Q=&Eu~9v92XXpatU-E!(i{pD>YA^@Ta_fZ3@|B8|rW zL~Ibn#muwyz#L+Ki?RM8(j-HRU@R9Q>FQm&jF-=k&MZiGbc8I%8*d`<IesRFmk`e= zji@9$Aa;k{ewjnj*S|u7|6>{_jxgdlOo-zqg4v=Qb49O4XZP4nrLkrb0;x9Exu%as zYEv5KAZoc_EqQ9*g`p=S$HwV<Dk$|<ke6B3F-FPy7-V1=7m9@dD;HaP_A|l{zKy!^ zAMbO5RL4#Nx%ItqqN=@QL}vA>IRDy>B}#=Sj-_lN37C5>R+R$79-|cGIxhBn;-ypu zL=An;udZ3Gb4YOA<0~L|1Q0Qg=wgZ5N5p9jmi0r_*y#&5_mM0e!w+c0Z_r6{)8R11 zDt>N97%sUuIzw6Og>>gzLT1)B<Fdu4Z+h{F3f;DgP#?c4FTu(wWMZAt^=4}98k63< zn*=j#c8rcG<Go>o&x#tWa|up!G;+-DRo7Wg+DKYopMbinYkvx6(}5W$(4WZ5bF4r{ zm-4BQ)wjU0;MyMQ^z<~)32jhXe+{X<l$nnZB|3)5-djKtt*qKB19e`L>M}BGY~IL{ z`Cj-RQqu0AEYD<X=s*OhU(u<(>VO0T-qA*PnT>Z>bs+6ZoxU~0uTPd(){(SO?N=QQ z?V;On6N!lqH{skZ?-Gz#r^gw@E^JtXZ+O(HCykfV;)37|Pa<wOCR2;Ktg*)6<qk?c z8Uq8A0Vg-d$StnRzc)~*@dq;=Q23pczJD2nYI@<xKC_Rc-9=6tAlgC(2X%E3SvEM7 z^ES$sR5fY&{uOUgi$(00ZAx0@&uNxt@Rj0YkmNv7&4K+LRH`n*$~Q)BB!nc7mW*NI zR19UkRrz}Q<k-u@@Bl@$Qfge4ycuns7CMlNFt5jH7dn$k3pPdb@;th6kyhS&T)9CS zEgA!puf01pD#W=p#&VoH8v^`HI4j?7%&Nj#RcO}>PQ~TB>a@75uFIUsF?)Y{_Pzwn zE0q9yH4%JuDHpg4(-1|mh8>he61FkCXcy(sSyM}TBk+p1luYo*3@ZHw>BMNVh&*5h zhKA=g6)9m+9WQq7PSzB*3}%pUhJC%&hVA+6KR#Zrx%$N|>qHRSLU1IF;SG`7T5C5& zZ8N*XjlNxv*x}WGB^A!xzAvZeEXrOrE5GjL%WWi>QQmeo>73~hWQ%_nDw2<^@V-1) z5jkw}N;WB-fiBlrps0=A^-OV*aqr3K%2Md*CK{EzjtT7h@Yp>*mannpj5$8{hp<=J zaE`5IDl4-Uk>i_Xk)tI+bjB-Zz?>fT85v>oNb;Q>@(JrjwAUvs#|X%h?$2Y^Eak1g zw~CPfnBy7}|30H<71OQDAKOTpoLc<`p_DZ&e=5U80_~TNff406;iIeB&}=ktf$VyI z>MbJkI=<Ou{qzK`zrOoZVe-tJZ!u7!^OEj;8)OTrL%lsMpwk97;$6Poeq;f;@A3FB zG<*jdxSqs}P3Y1UD$hL7JY3!<Xj;8pkaMBKd2g?YEgbJeiFZGAbToPHlZh(CRu_DQ zY~Ar_uuX7v*bq{Iy^=ky>pID!5-2)iF$X;}lTIr%wQQ%cR=-IPQr~cS95K#L2a?}# zIoZtVkyk5KVmfyP7dwh&Hj-U<`(s>J{&u*@#Ip^!TEx~$rOE6=Z(g;L7FmHtMl~YV z#T|<^j)BV8szmN|N{W<f{Cz_`FZ}lIiLj+!Aq1A!{R4lq;AA9%iicOsK+K0Uncr$W z1nD$O@KOSrN95dA=skVJ{;uF+#0lB%sc44kb`NwbLfL|18<nPGGIiLdNoMs)T%x@+ z9Q-}{u@eF2h2BQZG5D&WPmaD6t~R~7n@%ER(qO%<BF1w=0}N|QP=oG*@RDfiGlCqK zYv=fO8<Q~55$VkvyR+9jB&=h?nq_sb;R{-5J$u|`dSm?VxxQuKipHFaX%Xu%`TlX> zn02An9s48{aWKmezxq&(so}#n44c;p0NlL8h;mp}@)<9lvUxy0kdC?M%mC%a6!kT$ zu(=v^wl(zn>^=ID;9qUKtCPwlaXW>hg}v)ccju5}dsCbFRa{lqil26`33N-8i0m5n z<7hLrI(>HoD;OiZpKI<Ifq7`k<6l%PDlzjoZ_y(r)q_eTy8uCwzW-*;iw#^V5T(=5 z>~ID4wzMty<pp-(2yu3f$Tix(kwWUDX#!T8fe-s_@#^%Zq}S*?67;za=Dmq*n?l{l zfg$nvjs*{}DAAZ7*_0KD-uD`^)Ym$8QKu<I5Tta$y$A-|K6wZ7%yu<6Jllgl0~*;U zR_hG=dOlcJASvxm{0H?$`m9?a8%WC1%t1(JZT1Bg?e`;|R9ZwBHs{mPF-Cv1<n_`9 zHmUKrK9@FHE0DRvDK6k!mdH}VNWxpTnvN|TC$h?$jcXSYgIHk%m)c0*>W8$HQtJjF zcJD?FBrHTEpbGJUYVBJ*dUR2b3D`UlpTpvgsdic2&t{oe*h_GAznw^vNOJyjQ)Mn# zyyL8_4)R`!eqc~nxVZi_rJ@?`&g@|)lwvDqR0Vl&S3ia&GL4u(TbREqWx}EB8w0l4 z5?FPBI9w~ZvX3GW>$@lDc2NFdl3X6IcOu^`f7{#K@-G%X7O6&Q8=FPsl0aw`aSQ{a zHiO4orRZh~A@CQv|JrNVyMWTXpi*i4Qm4Qn>yuFb%`D(i>;b}_pxo*DI2`5^Fm@Va z%U)4`j51tR|JrSb3=xlFoXY-cYc8Ys&GW-9szAAGUi+LC5r(jEgs}(Jvoaxh5=wWf zULdIME+X|uE}<y*Kz{y3h0aw7QoQ&6+o_fsPb)6cWJ4*n1M!uyi1D-0jw4{F^mW=u z<%5v2LfIx$+UF2koqG06A3NVbL52Nw0iBz!xm+=GIg9BZwVDVi>SfU@NMgcixusBo zj*3EpVC<3I)+Xv2NYQQ=7^UgpjCm_7Pb$$PTd)<j@P-4}s?>(ZRU6*GqaT-f(Bc2I zoWCOjm|Hl5@?(Fz80B8G$D^$t;de%;E%?L^sZJiqgN5ih4SF4b)?`rm$B#S|ATvhH z9CZdCY6b9A`>4$QI7Ie7Tw_SF2Z(Z7G8P$J##fo99sS&Z)mb_72f61J0x$ZG4FOxv zbDw%N=<2vb)7nnQY|XwU#}k;uy$niMJdqjpO8pb4(ADw6p0AA8#bF3uS3-TLctyCT zqf$ec<eSjnQR7!n4P|oM+F$R;w%ID28!;qS=uOO;b#m;Wke8_%)dk!%_P1jyS(bF1 zxIGeU+vJ-IDWpCA$0}#4Zq*V=t6mJ?dW|iW;KSx}gc05pj}|6@=p~pwRoiY{GP*Aq z^K~HssMC9%bc~5->3pJ0jHDO9Cp=hH-$OwQSevz9uNp)eraLrEL%CUsuCh)qQ%BcY zit1gK_)_S3qmO{?alEdfx#bttHRevjmH8cwGj~=+3~Cf3*t6<td{$p2C^u^LLl94F zwq$vpmOWX6GI#A)KWn!VUl*bEGtelyGRIZ<a!gW?lAv3n8BjyzMB&wg7{*t=G@F7O z(JsU@*DAP;Jn+h6a8P{+SzyL+UtC*Gt(Qeh$dp8Dk9r|GK7E$;BCcmT3<<2M;XW)P zn@%4NiH`~_*AR5ja(%Dit_$tQmqt$_v&0Ye{W?luR1G|2LL7bZY_|c5w)%5OQyRrT z*F$!i0NYXlnu=i#`-Zkr?ZC_P14(P&_ch@{eHy7Qx6!182*h4GTS#)rBEtNtufnu| z=lH{gw^=2OW#5aU(Z=7!9qJKj+?90~MvX@d*y%CIn;1ViWX;E@K@ABa_Q}R13;Ls1 zZzmM)s<cSLL0W4dT)R-UNYcA+n1S$P!HdiojK{)!1QYJ9-#&JK?L^C1=f~=g!;zGH z>^!@aG11G6E<;*36b(tfhE4gG_wuFW)b%tZjL|OpLo}k}``%4v?Q*FVjp849$m^*2 zt;l^K_z4qqH~rOd8u&}swnrl1E{@%A5cl5vPPwJ`_r+$%R<AHPqAz*9YzQfKV)dw| z6PCr=&SkxhznP84VD|I(t50pyiocT`;YuRmoJ;!MV+7MoS^AtM)?8ny4w8T&gba6N zh>_+FLK}YPDWiI{5esa6HO*!{hK<>a#XbX%`fgbCws#QLU1A$uzUk}GK#I9{@hd~4 zyXj*C+aMh@U2MnN^1GuNqvg|Hy?F*~RN5P4!IBoDY}25f!Rv=$mfm@FkRpp#EW#{% z93EPcMm_qmJLFU8Uv7TjZuKB!%dm1D89x6zoqsX_5unK~tPdppz{<RyuNj#H=hw9& z1T@Jw(^jvVW86!m9vA%mx9uxr+{-GF^SJlo$evXlmHXwED2|lOyas(KER#`>WnD*t z&_1$h{xZX)d3>L6q;qNR8IB@zUOt;6yXeuqG;lusF@GC`dQ_Rw*4n<Tq(7ik{ivh< zv21hx#jUF~bM5J*Kcfw$&re~H7<iU-8-(ExG@YJ~Fw?t8u~mR8Eh`FO$%z__MX=|# zzbYGXnkB~psF}Tcgw%uBW063rAAo0>`}JPRxr`Mr2r#n*J9ca>8dV)D^x4hcacd`i z9vdk9GWUex_}y*)7Gv!o?tEFeCWc2fpNfbL-sAa2m2$A!bbQ!B%_cxf?dmjX--(G% zao41DmH2Hb01dqs_w!ZudV+pYrLew`G$)<>Sp$kP^2FE0Q!HE9^J*C_n%vope}l;9 zSF2GFNQ3cz84(y5p7=y;;hC4anEk0$Wu8lIj19FNnybs;D_^aF_K=sOnhaxCtT@L* z0yO%z{a-Q;Lj<^ljKZHu7F-a|At^je8=z;;pdX0_nVBA5c2v_)f0ky-Me_CG&vLKS zWS?va8`Y^ZFM&N&$=f-@hK)Hs(b}h*sIH?towH%tWZ>HS5vsZDx_pxm@QB<fKY(R# z)toIQ=lRT(w$SvWf-6nClrDo!6+h`MlnVOcH^)q&V#js}$yqw0p6iokB!t@|w#z0d zZv$W*`wp9{E1ra+=>5FR$duMBg=*Sl!i%Sj<7<}wCg!XKbB(Wb?f=?c`KKXZ<-Pq} z#)?OnL>T?S0f2G{dm%m(40Th6enU^!gAudiJmqeA7ce4PR%x2X{$-l>mK?D~c<vOg zhzh)~>LU8uP20E(W2xF}i3J{8)2(r?9sAhqF4V{gylTy<O)aUky)&PI<DWIMUSMQ{ zz4}Ai-H<A*^z*n<l|h9!yZPg6>f1pDi2thgHr4&gRPJR>h;9iHq?R))><d2_=w1E8 z*`54{vm13q0-Rk6z}Ydsr12W;EWkl-P3$VG4UuvL6U-f>h#xv^08ui^za?qI^1(i; zp}h~~DqlL<dGU?l>~(6<W+r9Ie_qW;cmj4<;?)M)pPl?|6k$KrcpsbJx{kE#+Y(XQ zMMY{BWPtu4WnJ?~{fe1|vyK$O*&R;B^0zuzqOY6C%P$uy(Ea4YOc`L|<AP}`OYOyF zvC@z9p45r8=1-)!OID2AfLHsofdQmhT^e%zG`NTwXozFCJ5OTU4d;BY<VbAKYI!Hi z$u*;#M+$~mR(26RsE|N`pfXnYF*o-3;YnyMzM86IIlZeY6!`(Hhc`5mV4Zt59K0&2 z@nmsRSaS2r_-HbFK@exsEySDK@U8d$$9RWTq`taYFfWrJ%PJQi$N0<3f6*lI*T99@ zXgerSF`wNH77%eZOYj{@-$ym;>Ahdi6YEr2gyUH^*EL?>b58%mgIE%<=5qbQtM{*! zUYb#EG!OS@Eg1HwjeBzs0JHNQ+QgP$X^eXe{3WN-4kAVlQa|;g<AgL}<9Seu1mha8 zvQy#*K0rI6)<h#*{jj%{lcT`x)3@73LW}35+8qjkg!VV?cK^r$c;8ofEqXYSL|b+d zdt#MLC1MjmrMScbxJ)ZA1^)wRA8_1#R;(*#^*?|Ex{SMbXI2vAMd1ZCB4EA6XA+4T zXGFvaL#*Zl5kD<2X>K4sxf^5b6%J>0qdrCpgwAAXSY6WaEX>tnAd&u59jBiKUI!FT zYr^BmZXv(_0JT$S_%W{cx%WSGfJ%Ol+08oj_Mg2<sbP^3-Aq}-HFASg!HhMxIcr3& zv%zNHJ%(AMP5o#UJ4e|I;%JO&Z8F_6MfQ8bzx<1;{Ca_Kugjf%XTvRoKjv+1*ppMr z+vZH}o%|PP|A%d`&IMSNP*m{7OFIaID9rzOHtGPS5V@?n^Vcl@3%~^)X%4c%MD0T> z^@-k%75^Pn`~L!Y0gaizZA;l<{MP>TQl2Dxt((=c+157jqa$-Co*TXV56WBJ2T69W zqUAVmJln(uNS#R6PmD1C3)o%z9EvDK@GkfdD;4C?aHlWic&h*3<jM&G%#;9YabllX z>5S`x|KHr;5oQdJfmg6bC(f|a8ch8!?v4P9Bw*3^S3ut8GXD=hy#@?d{NMj94A^=4 z-T#K+n1HK3aP2=I{{I1Zc5nLfKS)U$ljK=H(f=R#HZ<{48UP@>ZhZj>YrnMZ+uGPj zg%o9K*PB@Y(un_nk-u?jWBFAvxkwMCMueV-lr+#E!nbJ%T1`PMvL0yvqQd9J`t5Fi zT1&}$X?CxfS{tN3l#km}Z;Uk}zYZt*3%I~beHjirr%pFaJPdCU6EdAmq@Q3B-W!v= z?Te;PWGFiw(v%V)_{8<^;}1;4{f*6+aPF@y^w`DrH(N#RpoqJMIaM5Ui6oFR=3rW> zM{BB9xC7FeIO=_j@vS(C{gPq5kJ^d1O}P_{P*3PSD>(b$_Dh6%k}@{VCiKPef2@b| zlW5bv6J3FMxE$F@OPef-qE7&wH+7MV^P6Tlv)-5>`>1KXGhx-k%miG5c-nDm`ooW0 z;$F|FZ%j$$Q!}Fg)%xA`oneWx=LpfSyX`Su<sbP389Ggkte?5xo=kp#KbzAjP5dtg z;@1h)hK-c9|6E6&o=>!AqdimX`dqff5pOs5t$rU>u_&<HZuhnc=-t^;t+BzQqUudf z0rweNrj!2nF^pRZ9-!2uoHJLPtJ7-{QBvj3BoLogj9{{uJNqdJa@xz7R42p@(4o_J z*V_MIe&RkJ^KN4Hq5o&eHh;x0>!;XaHbO_EOMYA<r_4qheynrg^b8AjeW;&O(uYP0 zD=nxBaw-Gx?xv=dYU4ov)zdZq_^1;n{?ZXzE%Zm2FC@@*Tm|(?RkULsVzbRJ&U`3V zwC{AZWZwX*E*r6mgE2AZQ(Dzm>3>`2oRI!)zrS{ef>f7Dzz97C>ARJ}Zw0VgR0j1M z2~4@Q%ujwl!boO5GdtUq!gbd1+`rsI*pI2bu`1ncI6u7=nbkMqsg`u<F^X6zrY_U4 zi(1kIIojX4QukSv1nT;#&f*crc=so=uYdT0rCsQYB+Uv0`(NytlZDbbsH>2(heEI? zte8`1_MCyf^@lDk1xOL2Ke6^j7xNV2ac_s;tcbkc6+<KIjSh>67%TZW<qbQ7RWIjk zeL-=T`0vvXrS$zEv%P#7+BAuRgFQR84kA{PZJva?*c2{Xoi|W(o>HV+Z_i3X)!!Ox zX}g^)j6ZS71UFXrcNH@PoF7AH4?5&iR2kU`r1g<hN48YK+d1?Sqv*cCgO|?XF}L=W zV+<`X9Anb4o*#ehh<rQAx4J7&?j8f~b(gS=zqB=i?j4vVbe-3ug~lzlYj*X8?1A9H z@y5Lvrdc;_tHy(nE^0Y&;o1GhUn`l#L)l^q&iiW&!2|SYaj&{^IH_3#HNpt0=<-jd z-mYe!{iaZzw8x3L!c{3<W}FZPkTm*xM|&xk$NMgsj%SVVdk*W|9wUXE#+~h~_FvbT z#HJMG)oCURE0EzoJ0wjz8yh>E=onzgu6dciES4wzksSf1u#_{_(Dg-{;z!8PjM`E` z^hQ~Upup1GCuLJM;sk!0tZ7m5I;Gq}Csj9hHv~U@6FgSChUKJ!h{jCZQE>Ko=6;X> zz%uXroY_aG-7;?r-e(Ls#_-EE-}K1tLZ`4@*2Fc2cZqOPhnW=BPeAj+Q|?w4b;<Q@ zeOE$1{e{(qu?l!JH>Zt$%s+mY5*T&W*SLLOUZ%HcRrF9PB$1}tfzx~}Ay&>?2ej_m zGU=b}&@dV@qf7fd`U<Wg3RKI1j1EuX@(5p@xxe&G%9^^V`g;WI`?Zv{P6gM7f~Rvl zHONsB6wWQCWx1m-a>Y~wEyl_1n7iZX=b*n<L%y?&eh^ayAn;5FR^C_Y9$S?{BXIRQ zrq9L7eHx=hb$8~U<%S2y3+DvhUSn&Nukp3+^{22R8N6ZqLj^ALZKFyKQOz3a>E^<C zOYs-Co9oX5(DN?I@Etpb;aGX?F1+@7BtI=%O=UNCSZsG4(EW4oJ>%Q^nkytwt?3LO zpMocMueGeJn$^`b$iwS7@BPa!`^K@H^tuhSYT*acVniXNxBY%>k$wn4`8DRlQ@nkQ zT6M|2%F3xOWJqIrK_g31%<L24NJO6P5pS!eVrb)SkBBZ?nchi9n=&!K152~<ghM;V zSt?E+$Evx{iuRDsoP(+|TddjbU0<t(3!KPnIE3Ezco1yEWn+qa*)F*Q4z@tw%EMza zc>D!ue09+ZF#;4Pizu*-Z*H?7RAYCc%vH`;stRcqgw?EHbe%tLlD+C5-a9CPr?6Uh z;<dYV9=`9grrl@xXOGgWeyKNwwL%dt%RDkjQAvvdanm6yAZPF%6(twTfO;K`h?iAH zJAzG9woH_H8hll?$;H;boYozA3Xf6?dLd;Q%vCCMJHc`aXQqSmsZ7nxBZk+P&F#lF zZ_60|uo-Pm%h5XC{&5FDn*`@ZpEt;R3t7$_W4NjlupWADW@OeC?(YB+7a!1I>xtmA zNYg)W>7pF9b9Wti(<*8orHuU>PO+UN)$Nle1^*}!Vn^o;G-#9UphDQB^MVUCq-|oM zl)hN4#=xn;vi#TVCEgF-ksD*ic8*f@-X1Br=>Q<eHLoRVd()ULhmwfsWv)x17u9!A z(+0$V5gv`0P2~7kB|G)9PJ{~Mh7mLNsbho&J(&Pv!#WXtU&Te#b`lJmGAEOcH#-9& zD*yIcV2gs0B}JY}wENGS{0f0iaOwcvokBS^*0R>9Ts?bY67s4?um_w=pz)!g4uRE| z7r7mRHZ@n}QR7|wBkFV6o5$e_7_(k;ktL|nH!CatVL?6X#829Jc)K#>MJ@b}0!c0K z=j=sJlmqj@PSP5louB9GjdqCZ!~{xe6@HVLjknusU*L>h@i_zK>c!T}^lEksf`{e& zsvl#iI%=Y!jR)tGP7$@)uvqb>M8BJ}MWa<!oqtYV+HU?U1Yhe5$jY^IRd?WiE$Ydl zeg14b%NxMVvBf`Hmi#gV>7(OB{N7u0C=nxYW)kR-(knd0t{GdeK2tDEton{>cXXGH z8_lF&kgpvxqRq26U7X~}bnZ?8d<p!(X&tjBqnb>_B6RkX$KiE5Kjaa;S)RSdD+wB+ z9gT_}y_aQr(+d6`@pBm!JQ3?X?JQ>V?E{mrt%-ZPh_P$a{z!p#lX;$6@{;p;dC&ZG z{F@NOz2F79vnSYOY)F%3Ej#(QuSTndbn7A(oJ)k<o059tMaaGl3Q)EVlkCw#JNu6f zw{Okl;xR4InlL2@AX^YNDf6t<^Jspe5|rXZm!!0V@`lWfFeT^Ro7&=50RW{?6P`-= zBMj6gWM`*zk1Zy6<YVx7bAw)DEmLmWQ9=|hK+Ox>SASsP*wU0xz>ICASI@Zehk2Fe z9)gqC8y0~DNN#^VJsTcM%YEEGiC>YhbB#|t7m2tR`Ue0Tfkf-5G-?I~s<k3WKVI?( za~GX4(?d#gx1K%|E`@Mo2}I91ZQykHuT-Sa4A&l`c=O+xwstkM7eyWWaK_u4eZ+le zx(0~<@l0bAsC%nOfl&u@b!7DsWz$6Y(0*kSJ?Yb9hu=7pChomo@)uvY{(V%@8Nn9S zsGV*t@+3QUDyfXr2zGP3*{81&=BtkWcKxqXL_8b_8v${X3luntyC|u{ltW7r0SBj} z+8Vzo&^RFQZN6!n_Yo>V@Fw547l?Zi|14>X&!eo1mJ`3YZl5q__Q?p1N~&)BXf$c# zHC}0?`^<~qy)iylx#haY+i%v0ab+G4S32C|0b>9P$+v{D#1zS;joRIGarz3RFs^rZ zH-6OlgSY5Gs`5MCZ@%v<131zm>(hN${t_H{b+0PCaKU(V?${}RWh^>GReu;S$RD$# z-*=vzYvB_=rn)P#r!TNn`6^+DdEtFK#J_=RgsLrzgnYa^2X(0;a|N+gRdh7o@=&<) z*8o%HrwLWaiN=-O<YRh2V7;>%u06@F%^;g^*S7W-q9L12+ouRdtg{zgvks^5lcYzi zrK#?*I&~&g4UcT+Ol*Qr+*blzEHImjm=|Z+)qaIPwIba1A>@una9r#|Gd$>#^Fi*a zzSvceLAJ{DYi2jVyXM$F<da}M#`FcH<(*YzyJ{^ny)S0F-0@Nl{PePbJ~6T!Nqtt( z{K-jp;*<{L$E7|}lMcE^FZeFW_pt{g!+*{ovO+8pv$}CqdpsXLLg#w7@<W$nVQ$$N z6qz&pEXdm{yC1tG(@W)7n$5`3KvH<N!EwP7jFem|J1dA(iJI(B`a`&%SUv}&n8W~E za{=JejWL)#%Qzgy?}zc0?yNZ-U6|4cKHwyJ+6#O}z20Pj0tGt%0#7!sN|pv-9;3U# z-KJGG-V>XvJ<H*5Of1f%7c5L}WKhgDnQp(`s6FAR29WmPEO~IwWL?X-G`quyX3`5y zHOreZfi)LA8QoHsRFdf+2b%83{5Pk4Guge6UDWd6o0XXzl2$d`@^E_YL?8vj2Z(gj z<lY7(neIn)Mw&RL1yG>=nm67e9C^Nfzx|VG1u>wsg2R=kIZyZT<|U)-cUVVGj`1N5 zY8F$e!tROpFB5e4?*@DK-c{&L>mFwZ8xOQ(M2kk@jMN@eSEWJ{uL!q?{OKd|yg$>K z<U6b;wz0ap3vb3PC2QxYr#^JIbagG;%CzfGS!p_e9~boNo47}s!`d|79uTn~?rNW{ zLZpebd@L|<i74oo(XUYLfAG~K$O4SD<-OjoncS3W`1BSv|J&JFdpst{c89#)GaWv^ zXs>^f-SO&M#zY!|@FgvtBJ#Sh9I{wUT}8o(^}*IYBY)a@Rk1htSNOdqFJQA*6&Cl- zU^KtzmrVN`hHHO3vZOYqquA-PlYB|_dJWB3DIc*opFyNzCv$9YL$;VoyPr-1<PA|N zh%(cs{X$$~t5IE$q#o9mt2fgAXcx^C8?Z5N#aa~sTJZX_d}&HRG2Hmwds^zBhs+Fk zlAFU1)|{S|H8Hw292R|qc0@2WM;%=Bc{WX1f;eceOafY^fd(PT5<w=*xT?o#%|W^z z?WTeCM@zyitF9*QuW4xREb>x8AEHZnzutZ@Y8G4<x{nIn*f=_(AghkF3$(D!jrLrY z0e}Fm|4gM78ek`{>px2qw0dLiywE2$mm=z%w3XR3PRp&nCx!iWH#fd}4y!dCB?{a5 zwbIg&4Yn{p_E2XXfQi{|LUhINl3!XcWgnw5(xcev;?e8QEo-(VOEDj=rv_~yS+1s; ztM|LXl}MAkt}Sfb`Cj@XqD5suT7BN5;aoE!&BxtK>Qptwf1rqTDbl2dLmFTT`ugKz z-(V;yjQ+&-^2Wx#b{3JF+OG_-lhuokE%bXp*;XJ;)5BxTF&bj-ZjgzH((Qw%Vd)~n zCd+6xoG;;f6(fL--V&`4JX5~_{v^%lIv$f<&wAPv$Zr1&{782uO$w0K<EOSSLM2H@ z3$x*OwR4YNKV*OQ<0LusRdW#4n(L9)lz-DFoL!5Pq5~lP4YRo_8L(a2@RNYG*y-+V zc8t0uf9Qa@A1j_At;k#p6qz`Eje8E4c+%M%0>|4xT^%><r79iCd<>{INZZr@i0UZp zlM%Bn4I6|`D)8Y9Y&cg9Yu1Z|%=xp4+ii{i+VKX0dD*9*%w@Q#Nh@s|!CjQ@BnFrc zdFjq_!aHWW4v6#pj{8t<qHz#aR#OhGF&Wf+4cqeu7F9GjIH0>kc`c5IG($;ZI?Js| zUWZh>M1Vp6OuoMU;^4?`jvcRYbr0ST{GS3}=bPZ0br?eAue%6>*~b5L-T{_=euzC> zml#P>q}ICuD5#f^vD<?$F6)7+5LDr=M_=_KT^<pzlncA>+kUcuUAdnvY@dAHRIxGu z*cmb(!OmY9+oc-gJQI2TPkeO3QDb@+nWvgq33vnbRPoWWRl?CiG#<sY=Z$L@3+R?~ zo~r)k3dy5or#9v}8WPYDeVu*Z=REN}iDHL1>y|0(bFqFC#KKa?eaQ9NbWcuiV&q3F z+63Zm|C{&&FHg&w$RF;ncBsXQ>q#BIgp%co&%J-i#;@SYyIMKNLnZHesLa_tcjB#V zrfJIT!pJxC3&~D@)YXo5yT5LPrHPRRVy*`sf4=uQRSsa1P&hMo%-B`RYgK1X5|~a( ztj1u{{5M}vvY%6t4OV?%pB&)5jO2|+y*HjmwhMJ90u_$7h|TKnoRqmVc!EqrBP<}v zbC{Cq>}0=yVl7~S$3(0LCrfAwA0X(0a$b~Q3MXixFR29|7|K{{$MDLr)A=eSAO7Tt z>GRZo6~oD5Z(KJ}u17QZslxe=(64az#|PMD8m4<f>eSQ?yQQ9uwtfP<m2xw6gyE8c z9Hk4}QZbNlR_<NWqu{?@_|jRx4Sm!LC|b{Z5FE|0XYLQNs=?--Ox;2j72%w;7Cp`b z1!Uq2s#XoA%7Bu#ZHmpiXXn}%19HmVlP?qWz85UckUs-c3ZAzrw;*Pf&?jQ@<TtN@ z<k9zH95|Ch0!*4pQNeQR*Kn_G!T5Ivc+Th$f;4U3&Gl?kU+3{hZByJ&W-PGko-tkG z?yVAMFqJJQjMUKYIpbH#+e*`};Sz0qG(LcLz@y^vi2C<(U?cnOe^5(<OZIt)0~Kj} z;iQJw0TwBhd*-N&_>HAG^&o0h1%9yXMxJ5Do4i1PVb@3N<{;A)VnH)YO3s**73&<9 z@l#6qY^h4c2)G1ioOzT$%^>m`@jzPjtNbBl0%+)$rNYUL1znn)Fx^qOEZQh0RmAsM z_0IJ#Qu6F0tE|&!jhnMu{8$b}{Y>;|BkaNmW@v%JVnwKa-S*jqCJ4t9jHK*zUs7^Y z@O)bvjEy5@jgqrSENyM!m+Xzl!+ijCDY8XLV3->G2)*S;$G{{wEZ02qtaP3AmXHSU zLj5@*Y0S_P0aLzIg~YHnAFMqJHvaMyLZ0;hE;iP>iVUnskzP)IpP3|8Tz)raT<OvG z2&Gz>s$Z4vDlY6{&wBFegsGtQ-C`Qw-SqBh3*X3Blou6{{0Xdjs*kr022M4VNIt)E zmgO`Kg)jQiByF=BJpu{l%g8-^$p6i~95}H?ed~G`$s74LH;gVXtZ~MN5%jEI&@WFI zg+E3Ayu*LmBZB^L8$~izLp47^Ybzx9lzx}LcfQ}N=7Js81n*Fbwc$hxi&70|FOwMv zey_ULVsm-7Ztf;@#r$)M%hrGe;*&yLW83y@A-G9_PZq~^5bdeCS$$vGDIP#WEjTl? z9B1X_PR5?G>y*?j*AU{q1;Y4WuxLcM=(M_W_sn-`pPO?j1enhg;L`w;8;$mtgWvRM z>G~cCQ0OJW0nJ@lPGiTu3rP3EBt+SmU*?-ou;-RepEy_sYU$~4VJ`_3Y;$Z!Ubib+ zPP@B%@}|?}62rjSv^8$O()V&>LZ>W=*mtY>ZAJgG2<W^LlHoKEegOFFMa+F1V1ZP0 z)#R$ar8){Aan`*TUk;GMe71W)!Mw@O)Ef16D^65_G|6rIX{$w&en4thmBLhce*5>w zIeYsuKX=^r+r%6kmZQT0RD8bYpzuAf4G{~^bmwL#1@t2u-?$&}%ejm^W|*(rq)B|b zho$ISgiG^=1!(m61bi(V9K1j#sPu8q<!4g;2_{agD&m2AYur|Lupa-CiUYhn{`1@- z4BzuRb+%;MMuDfpW^!vja11vt9_9zJ-`JHe$z<I@$;#bc>EM7qXQ*ukpV___6Zo=m z5%%DzM|!2O$A_*KFGc|e-BkuJ9m<uPG>T^g*H+ptZ;jl-*zB3u6@ccxJsg*-X*~>W zOmEoKOD0k@mBzkIxG6^}ygOrlF|BCXOGFRP*8w)_wpNU(2|xJz_&@Onika|9KUJ2l zKm^2#aWfDw!|pFS;>wLxBzH)FHd?dK5iY%E8em|Z-?fwk2fj0FRG+Mleyk?XUYO>a zTR$T};gw81c!7}{`qSMzYRIo26YeCi3l6;YV{!Fu8C~MluK|1y<Hg?itkhA_C*Jf3 z%az4HW6>X6Un`M67%~+L?bV}c^1lLmHD8Y$JP28OQI_m4g#YIfeztthLUwv!{xJ9x z&!=Dd8ztb&#<f!Y8@l*npw*eX{Ye-}BlH9Q{l+HElUA}Nemj&g!Vf-QoK_wMu;=wl z&JY^hd!9Md-Ag^i<aK0V;n>(SBS7BL8`WA@D$+k%f|=@Db^ElWqM-*0$PmZA4|>F^ z7(y^b%arWT9}24p7wLD4#GFlb$cQF$S6U9T|Km5KVPq53(iD^a-#oVkK$0sPYrSeD z+hdQPv}DP{OT8ijspt~(=*4@jN#$V2Z3?<tk}Q#GjCIA1d3vT<5q{t>JI@?P0f0u0 z<|=lc;jAnvYw2hhTfwG}GXK|#Leiy+;Am|LVrCbYQL0rP{m4J$m%*if%8|E_icp6| zwUO3i63&A^PqHUpyP~A)auRo=ez}bXasO;dw4e!En-enNgw{Co`U9~xGVJG?JUA7^ zHF1FA7*AqEXp$vWQC^u~<L&p6nBx>9dsijo;NwB#umFi?OX(<oIVwQ&y95y^l7I9s zH-l>h05zD~1f39miAUm<$zI5wW5#KNODi=-{`!vqfAmDfjx{U#Vxu~*D5Ox}K-*%i zs#z~*S;!G;k`?49_Pr*_@B6R_gP-RDXl%F~xm-HRMGF9jB^3E>NsJ6D1!W`OhKd{w z9kxt{BQ39k*Ft78FuOj1nrNPwo(B_Km`i|DzNeeIX*E8Vka7B<68dG`l9u(|)L`em zb@Rdc;lIbkc7asaMDqPrany7X)2liOy^qkN$SbzbVZH6s7dL6qP=vZJFI#&5)WAqd zhCcrTzBeOZA+EP7KjzYsjn+Vi_VhaxoK`GZ`uc+Yc2Cy7`0o%upNJka4Q}TG;T!tL ze+W*#sfpG#SfBw4ga-wSbLm8LSIS~wxQ2fH;Ktl8yZwA~kpoz)3$@yj&YB4-{{=ZQ z2A>*Zvv)E|5ePD{MUXhG+uz`(^)#uDAE;;w(B=ga&-_63@ID#39<-_~A2;KYuxsrp zRYkVJaU0fs*^Aj9#hRPe6&q*BYeB)xQ~@~W?<5W1e8FB9SARCCTV&M<mRiKUJDw+V zmP>6ec*aLL#;jSO+dqDK86&?*0D_&Y2foiL!CKqiYWLZBD?P3Du8h{QoN2!&`UEHW zbwWhEw5zHGT1+$ZL6^D6(Ww|EZldUny|Q4!o0|r8xXhU6m1c!k7LOkn9a>+Eh4n8r zROfaw`^AaWsQ+!&ES>lB7c&#9(;RuUYbak?mOx9y2EY_sqVDmh^BUaJpBc>ycLi5v zkUHq}8EIamH~%buBfELQ%903MxMA46iM$Cv+L)!<Mrrk2vnRlk-ItNFZ=h$lYB{%D z*8VoYIPvuD{O|uoxVby~*zO|TxEC;ijIz5IV5($g*rXh5_gt|=nAK=h@@b0i&rE~^ z$SF&3T|P1v`Nokd$`8NsCh~@B^09awYW5>6vRYo}-6^T@?FlIb<>1X%!~3@xm*m~O zZuFK~j#kfMOsvA0Y||?844+H=$lbdY4dOh&beL)i4r$zKrN}*#@bwtO4%KT<BBV*z zk!8^cPVD|Zha8Ek@_tBSUK!?WLt{exG5f`bOW~3K@>ka{{we`71}!A3Qjt?Mbn~9H za_;Q!(gkxJW0DshRGP<RL7G7Q5S5@$E{}jh_op(l=c6cqsa2f<K0$~$9<6j)a^oG{ zijLLA+><s0m`2bWwF~8uP;H@O%tZMq&@7C$-)3rI^HsvF$H3>sqRjARUBjGYJu(5o zsbR0Wj3o2y*3TpJe*V$0oj7qF^81SnG0Ae;1y1x~rJtn^HQRa47uwBu>8Bvn-Fiq1 z=kVV>9;qVcqfB0>3j^B5n&%3Lgl0H?5lAK%wbL;jp#vd^P30$*-pp=~iIFBG(9ib_ zh9uC{r_uKr?ne2PdX>7Vl=3aRO~lCbi{v)-tb$hZ-@YT&>92{Bm46|rGGqfHR)u*1 zk73{c@3NIQzl(uhA4cAcM;s(TiU=THqdN*GF~T<+`m57KmpR;DYn~GSMHF2;!hHRS zx_V>>!59Ks*{+@;L6YI)JZY3#P1*ci&e>1AHQsW7C||j-^X!LWiBzG}7598xNW)%s zpR~Wb8#VBHJ>vrC$_2cgxzIETSJMHvH75CnfJIy*z!}t25#*yUnyqcL78RDSzyrep zdP_+|hffE%OsN0RTi4J3E{ba0kK|U=jQlJYuQ#AuO5c*L(Dsrd=K|TuRpUkjVzUfK z@IdTbUIDsd2~qgD2n!_Xh;ZtC28sf-M_inKHJmK|q2}{t5+8bHEwXLCo!z*ZRCNZJ z4jkx=$0$K+|4r$%%BYN5g^ss7T|-#8D{I$UrIT@)T~eGaG`_d(^9o+Gulhax^UNs! zroOpiT{$VzAO=R#`gKPAjddt){Ae0wm}q=Ki{?XeoiFin;3Rh(dD1*UR{R@8r4G1) zRoUOr*`_7iC}qLBod9Lc8xmjuP-ts%Y1is<wgUO4!-`$MmfhL)jd2a{9XN0v9l7}~ z_k_nUppMf&+~n@=4XptN;aOgf^e!6CyjA~guNW42QCg-=zo#pgXqd{7r}4}B`p`Od z>faw)P5XNTQ+CvDBN3%bG_Qc|n}dXtKg-D8W`L8P%0_uAc;GPL`I+e>DCP(wbawzC z&lOs}`;rm~m|Nt=lr9BM?r_Os5pnv}(-#nTJ>H0OA?f5q>FOS#2d_hh{oP}ED(Qj} zbR$+z!l$2Dr-)bIP!^^G3JT^%ll)3;<i>{0J6ECD{7}v{#>bMi$osY-xlFE%476#2 z9$}*8kpOPzJuaa|8%J-bpJyo_i+&k&!!Mq4JRwkz0T<Mzy?=mG35gi_7=0)@X^0jg zI)Thu#D2$#&)X?~FYd#(T80t{#!tl3`G}meGZ&$@mgBvwB@VzOM3b1TV+D0G>rO}N zA~Hwrf~R&<N>9zwJ}TUC3+eyUQOM_GB?)%xc9XP^0@;b7_}&&0fLx`c>$TC>VjARf zL!CHx-Ak0$us338<>48LsOB_cbJtBE6!_|Z42%TUjDKy5g)5X8c^_09``&&yuBc-_ zSJ+~f9VLiP=8P`5N)D=M-|P&pGwNZBpaE$p+IPOPYm^&>O6=SY;Et)1tA%d)YH#0O z^^3VE56&BNe{$alt;op$?I3+CrF<VQGmi`|^adM4%KGW*jG_I=U(FhTKZD-i6_k(9 z&t20ZVv9jb-jM1>c$$e{XbR{@BoIFHzelZ?U1UqLHs_<hB|07aiuysXZh-9WF{UdG zXvX{<H0&;0nJspB>(0PLmexD3n+;#Y+53rAC9SecMlUaY^z3Zsrg04L2YOv3xIk5g zE{E--XrjNf`K$uNaI|BxJhyC&5JyI_DzZ91U+Z2!xaRwW_p}p>6Yd@9I6W?68`peT zOY19bx_HT1ANpBj)xQd+Gk}tpfe7n_A`JJ}&%}T@$pe;k#%t%|N1f(}J>iX6-WQK? z_HM<8FZLRf?6!uQxhsR?Bp7d0X2mh>Sh)-tCgox2)7-_>GF`aa<Y&1(Uchgb`-M`{ zz?INXQjr>=0jAdVW`nJq@0nF{`M7swQr|MQa`}rLe`l@=g1c{*G(#>N-#(B}?RYP; zexK-KsXEXd*BU4Cl7B6~n3R-u?<!WgZ}XrN7Gky@GLmr9Q)#QmdsJ2)%wO5kwUX3E zey8^i#Pz9KgYo8`f!WKZoaQ39*RHc^_g0^|R);a1V?a5LruwE=Z?b6Gn)X<oXsCpK z7-IGj2K`<k5tw)<>6+_0aXtw`=1*-RzWkxFER>czXJ4FwBN!Vr5Cpe!h}ISk8`hLD z#J$t=k}+a69)BeoPb<FsDx~GL3%Gek<7z~E{w6Df{uEe$0cqD+4W!IR_FrDmLzA^F zh28<<6i(hv9fY)`OrWL@T1ECz@8&{|t@+9ZlLwsW4F#pT8yvL|S)I%YC63ysgx&%A z)JDQD$7V^a3gncqXn04!5NnP)C<@!**_nLS=S7@43kD<%gn<q+Mf5$>&w|eK0aa$Y zUWOU%#{o}z53FM}6M1j2=GaI_DVJMhAP(-q3Yk}8cxLVmS}*xuBC}S$>~iMB6cwxd zgeH*!^Sl@1bmgOTHAtaXb<^`g32H6p9x4vEa}38~!{9CVMMIbhXGwA~c(2r6-3^fO z=%N1}-1qR1%2bj(;Cg1Mr~{!8|Lq0y0xUnbrC*18rK(1}+gP{ljo?L*8#pH`Nq|3; zx)%ca8s;m5_Ay#n{NWV)K%ua;S(Z8?0!I_`(sS@Q;)-v}Qlfd09ialQx%)N>HvECs z;L<3CZwh>eCT;Ef{_K3R{i_3C+l4xKsca1@78qJEf&&@KH=z_oh)489?$bSMFBsOu zD127;Nt!LKAXD_4X2`~|_}*sEV?V^)m_Ty>kQJh&?O+L~U+<)VE;HEW|APpBwhaAK ziHj3`I|`v>LebS@z=ej~Vq$&^6JbnnLCj=@VV^q*WLaJngmB3=xZruP+y6b0!s)AU za;hR#Stx>DMM$we3A!@#C0jL0L%-@ogP6qhOrs%bPj3?$uTAY8ZF_C5jGQ#Phw5?U zLSuEcoC}z$zzYvB*h9w>ZpVZTq`r>4sIkcSY$7bQ>Ijpklb)KtQVGrfAYm->L+#}p zgqjYQ@U2_>l733O11FgV7jAY0_gk>dAN=0Fj6E&>0#%5dQ4d_-G!j^3=QpkVaQkyv zS!jbs5e%#YEjfy<&==7I;;i+^PW*!w)0XuKt*u?x2OQ5#uE3P84AXse$|?AwvEob& zc(cke56Hd4(KM+Y(Pym8)VNAewS@%&mtPV5j1JJux}A#XM9d-dyOrxJ$S{bUpSISN zWJn|jB?zq4-P4}jL_!sbc_%fNZ^_+RL6(jByGPL%)ycSS*7!M$uN*!OUOhoIpmE+c z4UsvFw=i|Z0|=0Q&j$jC{0G2!-u}lwUf42bC^X@>All{AagE-QKHCwYN#=7r@E${V zcgm#=f9;~Cq^4)h72Oi|G9;rOKKr!Vim7?H-MOzn4b16nhmNkLS&v*+;tofo<<#%0 z>pB|e7fYB19*F>(DUg%v>8jhx!IN}KN)64Xww#*l<LpZeyHQ*+kJTlX&Rg`s4xoXJ z`U{w4wM&MI+SXfoP-f_DASOiE4{dp}wLRf4sEEI<8N2|x6#|kBVag3UJlPZ|QLxwF zWpsR^581(11GFDI+$(y&pz{SEp$&rQ$G=4!@C7KZ<&aGT$WpDww#rf~AwSwZ)gWLq zmDHn%(T~$rtFPv)BwMu~<1xGs-uwD&kOR~lz{;^llYXUEHEFn$$9*FL)k|*>2Xxhp zT}{WeQ(Sg6-hWXAzS7?j&@WQ+lbOYU-v#{_XS;fzBMv6@<mb#s9w8Y&70?(p;q-bS z)Pt+dD96lw1`)n7NEz3z?0!81b7JWVYfg6}0CaFjuDQwTdiN}w%|XnwxdZh?zJrr0 z{WEi2%mj~!RVYz$*9K^4#3|KbkmRh}7g4-pY8VH!vI2rK4h>LjUtf_?qbul#C|WvE z4JOcD=H^S9fmhWJ7ZR{Sg+CGbHWuE(g$Chz!EiZ|_5RiTs`5NI1*~9JfQ4*=2_qP` zunMAT-XxKc1zT*+P68`PfdQ3?V)yaKNh+?#7_pL0iqg!JVt?g>*LnY~U{8YDnQ#FT zlj_$I?GH|bUEK#tb+*4`6^^h!F+Q?TJM-NH?a>2?)-xwcs11LA)W)-iBI{iyz0(`s z4?i@^=F~Yw4#+$nLawg)*Ce%m1SV^^rf=@?#coq{0ng3gqkFT#y&OTlaGCJ4WTg6n zf=o>q(4SD&i;1ArBcd@@ruhh{1wHMVk(R3qc4|CNC|)A_tfeGizWjk+KVPT(+t+CX zQkL@==S{Rb8n<VfP1Q|`)N4EN_sW2tX=N$&Ieyv2#C$({=$OT|=tPT>e{zPX7egRt z8W0{ENUiKRPNxl0(zuKQ)jXf{@;^yCXPC3zWH2OPPbQrvyb9}NirnbwPzJID)QZ|x zVGhDf{rkGj>Z=xe9rD{pBwzEuiz(c@-JgKmr0(9RpU|{uTG3T9VdZJsUp4rE_cjW+ ziqCWR@Ia5{vN(OQeTqIiurb=c#IXT!#V;THb)XkZC}+-N(D6D>0LJjex@H*x+8Hb0 z_T}wqLaXFDiX_)>k@<MkqenaE133|N%X}o<ni0p5Z4;WV#-O6JVXq@Gv3{XiZ~Hql zJ=BJJ48Mq1EqfokzxJH6=1v$dxiNRFnN$EabMss%y-{zZ4y1K#MCNw8{IU1GCP=zZ zk!JGr-g+QJIM~=tzT`W92P@T}<N?Pr{^#{TRl8@UYI~oN%XJD&Y`I4m*A*!#(>ZOG z<#UJUmVUv2zy6&6IST;bDiL*}4IE3}LJEw3qprHd)KF4iK)Ijj4)$Ly6SFTZ25Jc7 zb*nz+fj@0~#hPZFk{JIGLGo3ufkDHI%ktJF0Tl<@%F#t*aCf{8uoOs<4@RCY8mX;v zHwh~_+vUN~$F-?NmQ>@OTuMHkXb!J=Pv>>Yb-0Q=lZr4i?R1L<e{<XDFl}a?)#zO3 z4@I4so-4~cc%P`>+o%UAVCur|MP4z2noC5V@2`ml4`WZIx*_{KdCUe+%Jl<|@NnSE z!+3|!7kI*4X?$gW4W|6P!awJzwD1a({ZZd<?j7ykINog3+}ul&=lR$Wmz31*c+0`0 zWb_tECoRyscSP!#fPKSr7zMz~K<YDcbzr<8%U{E7@0hcpFu3vdok6$A3#;Ef<57n% z>zNn|agEYmWBf+GRz;FGYt~$Q2O=p85-$;9XQm;D2M-Ty>3pIKcnE2JjfY0T<3M3m z4z9z0P3#oMx5QJa?U1r8Taq3SQG}_F)rl)$y?pMkx)x{p)T*?pk0$_iiJ4+wItAP% zjmLW{fa;2uxvJ!mR0Mm$#atCdFNOO{Wz3WP@Ao`0;jDQV{mq-ICFDwnV&A5^b54iO zWWR@nJI*q-vchkKOn&um5J_9B{$V0v@XHi5R+9TA2KW8KwD;R@ilcxoSt@IRGg8kG zL^<di@+00z))L${M~`su?;X7V&>;_DhRer~HEz>2MArQ{w1OY~WX2F(_F?7*#C425 zXi-eI+3%Z&d5it%@KUkIDs559?sQD2<Om?}_y?VHVtxoz?r{M9#lSYPJ&Q||zrn>~ z2$2N3(%+1LuYvNcPUQz}lDiS)Y5mWlXXhX-L)<@a?V%bDahOOQ50cWwQv?|frNfA@ zVx@jS&9Jw5DNWZW&rw-e(|hjexNxMPm4{h7SPz1-PyC52XlBX#wl_VdS+uf%R=?jk z2b9hGs&eQZ$**mr3U5e4T;h#u2Pq$JmQtVT?N3XB2R!d;&~77mE*3@Ne6=vX^*e;t z3{DOP&~OMY_PBRj;`RA@INWi4mkOe#z1%i)<eHBpL;+>Qed7z3dYUf+D!VYFJa*Q; zfwOZf9SMk%FW%6bwp=l7dr{_myH=(}<7+>=8%%;%DjSC$j<aq>)A2vLD)i`bqi-pT zXU-(XNS^yZ&ufHb4IS*1KK#tCJVImG7yQVz?;y#(DYp50>ELNG5%0_TC*hUN(6OPU z8_}zA%8^y>l?Na$+0>MbsqRJht+Kq4w_C}uKYYd0D?>oDs3ly>R^R7C+m`xWYIxHK zLllSmk!hAXsW1OM`yreSO{$x_eK<S=3ElzFwZG~YV5BU5WclELnA7lr7F{w+GCj?& zB&i-+?Yv#&4T)sxK{eS>+)6!ce$y7nX4(N!?4VyMw0JsJ(|Jk41%CX#T3Fpym@sP= zIa?C<1nzf3!hwXlgUgynF0KOokW%P74S;^GANO!CgYyHTB(W|bJj<6yT%3yq#_aj7 zH9jtfE}#?mCWubO;+~CTVg?G<O`mioZaALmWYq8t->}OxTRFG3O}GE9vtz@f=l?MF zmSItD?fbCJmQ<9IQY54W1RQD%LZlP~q(w?v8M;PA=@980m6np07*LRoQ91{a7`ho^ z>c0T@<9_z@dynJgiyxf1XWgr=I<NCQmAK~>8~klCR8z3#qnv~A$vVRgseYLV9Yp1; zCV}_IVEIiDLoKV3X5md)^q{zYT$}z)H5#}K^Ss*$-bp=(kR|VuRi})&2wsFng|!5} zl;)RIo7%Ne<+;5fqzk8R)`NY%Yo^)+6U^{4)KIE6d`jUR`@?$l;^*YD3z(t0De+AQ zp{!GKqh;w`^NCe#u{vQZsEzfo%Z6Gbfs`9HuUtiic6}0yx}^`!6Q$)az`1#Ig}{j` zBu_Ww(sZQKc-=Rvhzq`hc`+LJt(JrcYD)m9F^}m=B#w4KaW}=+P%pgYwDyYA_|{PG zS;P1`ACl}6=83PS9+X^|L@=8<?O3t)JwJ;q{2Z#*T~9!A84_VlueqpjwRSx9P(S5F zIF{ZZ0>3r%Gj64=5W!l~tnNbubc}b~?UT4VZ%MB?wBfF?5{{&C|4p-`WiyMAB@zos z>b2g>pH|Ss0u6O`*On!IR#M9&Eb0^!zJy&A9_yH&g0qSW#&6^z*ZXtl^)E|pzKRbk zRAjNcXsyP&_c3MyZ}Y9~l#*=RJCn4v{%o+ZzMoc_`dBfxl0Pn3cL8?CT>{!v6RbO_ z>MP!~Q+pz4tk<3Ad~>)j?<0RM_|~KGvQppmGcmg}_0__eR-_ANv2Vohi-;kh+}PzI zliI<_R@%uP41xh0lMt4X1NZkV4vx(yX5K&dyAuC}cWV>HR){1Nx*>2Q(^<w_1sbaC z#SIA|A#k>Anz8qQ7SRlqawbg^H08_hamAQ~Kd~9%;c07lwG(X3{RKCc7K31^H1_Jo z?>a9a%!)hB>h$iMZ3oFH|MP31-z-~bIv!e*SP(XB75)_8%%yZkFZP(->L!#l#*3J( zqWqp`T-)%V`{%?iAY^B1h}+^Cp3ZYADEks`R}7*LvdxbHUGhGsv^xz{GfuWcx2>Em z7`&B#_U-eqsYunxyFOy2wO)|C+31y9OSyrvpN4~(=8(I$MTI-ZA2;zB5l^44tX4i3 zgG6wDo16CcE#Adk?YS;RLh0FFR|!R~Gn1XEzI%Bfm5bYaIqB~r@sTIufR)y)SQh?$ z3O!D+pI$*3+l-uJAR~=hC6fWv9bCdz??h#uYYb&c2F3i*W!t~PAATm@rD*MoFjzwL zEV+4p$!%)6Z0h<VyaijDJk^oDYefo|mtXez!EA-=<17XpBMh`mro*hL8H9b0LzFBx z?fOTTjG{6f4)dVXU!fQay-t3%LK-1M<B<zPsiS09@0>=Meb)Ijqtq-LdFJ52T#Nxg zPI2Fz$Ht_^XT-D(-FR$N*EY(hcBr&7WfrlIg}E;tchBe&Uv?A$c7@U`mp}b_Wfczd z$gT*`8b#P7!NcM7=7yaCx+P<QnL)ppaMr<)s35MC9s;b*CK@ktT5zs4N$tFkjp|=S zi10ZD?AcwtakVJ5QXiA4n;_qbhYpw>e{ymm#QXM?dSs8EI6S^3jUymX)k#+3V2F$| zr9IF>-{qQPfXiSoa@!TK-`c~D<)HZO?z)6zl)}T)ofShU9~KL3W)r%Ft%$I<6k+TS zQ$X>82-C_KE#G4vB9uJTk?9YY*g`SkT5mb8&OEoBLzwxQIjF=kW}u)XUJLWHr$BLM z&#qcHXpw9EY`#QI{8eLfXykZEa{k;qV`;r~gQ<%tXP)0|qvz;Rkjqh#s;}ZOVertI zT7T5Z&effU`s}TNBO^Z;vR_R39;O5#JcH2PLCb=5dQkBY)DWgHLtD6_hk6WggUPu> zSY3gt_V;`&N;yI;^u*LhQnF^~hfX4-@F?|3Csi(t3~T0QRLIe@tU>^Tf~gsr^EX$o zL3KU`5y0AI3;Rwlynl-e$WlXYnfDl8u3*d|RgK&78&v-R*H~ZX&I>x*l$T3)JofIA z)p5ZT5&3OTWPZM^WAb-=l+fkk%ognYukh2JSRqmbN3|`@&{~(Yp}FCt@?{s9$Az{r zk2>ViXbWuTdKpQ<HMUH#Rvkq7{9LV~4=ryY5uNRzs-+@M6QId*vG`t{>QMJ^SyhV! zM?_HaS-aix7Un&L4yh#;j>DVT0Wc&gA-3{Xv~(d`t=j6lOTb2&?2<*~d;cm_OkHh{ z2`4oMPO`B*>$uI|<^E`A+e!()@O{qBr3zj?_j!+bP2rL%oRR<61xfCpQC(&V-f#VI z2mQYHE=0(+7eVSfweATlmFS&4)ait#C3oVZ`cGoc7oh8-x1`@AM&<jB4J#tWx%>Ly z<z8KPdTRDUMTTZKPyyl58w$PxPO<$dJAU-<Kt92(8$PyDW|VJ)3zX>@^u6R1nK<$$ zhy#ZmD|!*XAdl6FOX@}$afp?MmShLXYIyl_znA53DjJp$Ugzha31YdhX$ZO=xYtid zswl8YbgkbrV~wCvsLd&ptAEby+-?K9q4jPf4fe=C#`_J4EeEq{4_$|#;uW&mnHyen zAkOLWVv0QUZm*=d6+#Qg@7+*Q-bSI9YMXbu{^o<&-S-)nLbF1qp~6smdSd0(KEYT~ zA_RNWrTfa&Nj&U9Q4^S<{JqoV8tQN%gLXnm&iLi1r!Q+hR+ZJ2H|2^1$jevd-?&^~ z4%o{Cqq^^Om#`wdTpoomoRhBSUbwVusE1R|Sjld>{h@U#GQjLY(6^bXfS{hp`yL}J z{O8XVeM4hk2yW}CTw~O(jsFFBpoK%DQ~F-|-kh>o2}`4|_yi~f+I2d5gX!UCA@|ws zEoZjb1lP-3j?c?jJ*iemSz=3^U10Zpb0@AmL_R!DPSzKo5?tz;PY_t>HqSMU+HRJ- zZ3)-!>xaJHJ}s#+lK(Z<dcH}?x_ezda!g*1aT9-*^^2Fdnk0ov&JDD(6^a=Z@lq=} zQ(V?{fL~t`<@9LOWh^HFGwFw>X7Es|`|I<avJ!?3t+Ht^W|1E8nM>NUVlO3(6!vyz zXMgG4oGRfMpU0hhS2)<R;tb*i-x_6{`@1!t*q+v*hWIMkvU?4I7azr2dal^0er6JT zFeT<$ASO@bT>s!wAkK^%$|yo0FQ8&xn@Z8RLRZB1cHcSRUp>P<v$3e-UYASbcf9F) zBUiiQui;2f>!g{8q58mt0!innCdg+0QrDjBodVDzU<P;lX%ANz4=RTn-^8uyEH=Ls zOj<BR)@_a7JUBoAYzrLDd23kkE@ql~=|Tq)QdX|`;Sr#tlv7<!%pZmnjJYWEJ8)>Q zU1NIsvGw&+vka5lw%1}s<RIGL%DzHXoKCsl-gBETYn~|{wvpxPs|kz_=TD{;ydCMO z^q4(~5ib18lcG5}4Y5gaHy#l$EFRkKvD_CA<8pB^>589;i+xbrBxI1nc5Yp4cbqg; zM~bm3mV1765C4@ZgRpTY#_kYm)uPQ|kUL2Q(bsqedYL#>vg4%Xr>r9><mEE9q_DKR zK~=x}O7p%ICrWs~mFi~CeY^#^JLR&3A=tP{_Trc70u2i}Wb3JK%3&Q83i)5ZPjvCl zF&?1eFrh3jq?Z}Bcj@!=3LL$({<g(U0iAD_`p$DzA#$YjR3K`?ldd_JcGFCKAfe`d zE)1tC`8ZhQuEsSL%r3jlIwnM>(4&_omxpHI2n|*3z0W3OP~9os$e~1I<|e!J-T4aJ zHF_u$PDGnv(wmHl>D%-iAii`dFbVW-o^6KHPuYhN@YiQ~q|a^PqVGT}=1%w<6COp@ z1>wK!piPTgDy0^YVYY~O8~EoUGd!EjQ7IS9!b3uahJq_m@eKjauN`T>sopd5ww;Ve z0x4RNnZbCWu+xH`ffc=o^AL%y-{`pqH>C+1d|7f6(gU@L%wp_DbFY+iq?RYnHWR%Y z&Dadra3ulkKBP}+zUB32p+*y4ZZxv^g6S-R`EJAV>SP>Y*&Z02XoHJ@L{JVH`=(dw zjd9W=(Ih!j!5kK)?vfEZvJp0tT`IrzDivF|I-h!W#;T2(E*;J)=xmbOHM^1kn#`ER zPq8->^@Z>4H9&*51Qmy)h{mkfUFfaY#9H+p=P5hvt$uyUv!3$;&UV@9<Hw)pdbeGz z$xC^g0bzdiH0;4>XD?@W5ywDwY>m2#rZB_x`3PHtaJKlC2w|i8+RUS}95-gPaC!#d zi!Jl62pQ#Ezkk`lC9q|E*ngJNFlWHUuWQNaYkWm_-cQV?lQ(#3GfVb>OT_(-^cuMF z-Hq-6UCfF!1{7(4goA{wj^lf`@4|G&DP7oQPr>c%$*my+^Kj4gCBMhL?0w`7zL4cr zL&SrXJqp<YrI)aL%Vb+es_U2EBNi7k#-Ah)4Wgo(e1SW)y&&p)S0$4rGsP}XxfdZ} z^RdRn@fEw6;3Z43u!J;CPcNh`I=|-Dz<kBa_(GuDlyQ2H7!Unm#%2~x3=iAAWd?j4 zri0U}uL@Q%I|{BPK=MfNb7bxKPiq<-4l^<T#<82cn_auY6&Y(G5ppYjOA>$K{6LUl z!Su!c@5M);1DnHhVZ4Rs<go*u$E>WS*4}``y6)0-HCVbvkCxJt95`Fn`cU-;tzJZP zari0sC9kjy!6w_8RTUdKUEL7IR(NW52A{Dezcl3f#~Qc<88$xnJL{HmpoB>ul4jux z{%ozT#UhIlkKA~-;~597wS{I%3gdY9s11I)0cr8rb?PA#3g^*+Q`Z-*!md{)cKIqo zZ8<kVmkeB4cLlZ89_a=e31_t~=!(}`Ts1?dWe6_D3!f5En!6f%Uz}h>kUTcwW-{J; z>x$7{eFPJI&6&$HeU>7Zs;v_@Zz_614sW!Kea8;(*G#^LSs4Y?(7(HcKtHZenXy}r z78NWB0kUGZ&cI4r>a-Dium8f&pCdcz;vm`k0MrG!ZR9>UsL`bhf6PfuS8h}a!fS7B z4O~-lgXiB{gSq(R8XULH0Sw6szY4d$zIJ6gf!GqC5n^q<VuoWxb~BXTYsK|GWh*e= zycITTs69`mPugwwe}i!NX2-%w8=<oLW)3in;AU4HdYG`NvKabKcja@bgcDnZvl(NB zZ}BRL%hfjxH664_ELfPO8Pub2p`B^36=chLdpA|Y$)tm1%VrckJJ=Gx`c~5mu3?@Q z-^DR(h7wtPMHn}RI7a3x_$Kp3nw#<x77^?{(bjCdhX5cTuS4{h>QM4Q$ov{aL|mVF zPiH0bb6}LwbqdMvy^{JqU|igJFQuJb!nX2ub*%Ih)`Et(CQ3H;t6A9ROBgu)hfLKE z77;wQ^s^`V2=&8V8aAg^lwQWCl_jpx^i|ht#7s`}{VM3QIbMl}%@!dv30~pkRX?7U zT{sm74>ug}kV0541<omknvm_Bjcnf(@Bq9cb^OJ5(v_xYzE;-!Al{!MmA?F@=qaqD znYHJE#L>*L)*1AaG=t7i0LUdIpV@>(U=s%36{H`>8QMViv&T}cSr>8#nj#>A;xi*s zMzT_lL>9TijmkT5geK2%r4wdyLW~<4F769V1R#2`b9Lr)7$ir8`|myj!AvkO8Ryt| zV@Wbo1_KiaibIa%dqr?GZ+73)Fjvvr2+kdz{H!9CGiLp8whvW1Ngv4&{dvQN;DAZ7 z4cPjxw(D<Sew=@M_#S*xmxF;P{zfZ6t+GavZB-TY7*#w8udvR~vhBF-*~B!QX{|T& zFegbJ@a)*<!`5GIL+QU()?+QwTADQVTRm*I`Y^LpJ`YwFPo(97KI%m){w0hZ6)~ny zgFY5?Hadv!;$|6G<jUd1yy2fhfRQpccE>Q^Fy$3H%-AN>4GqoJtVJg_6ka%a4gZlf z%EiuVp@J^L_89(K(*n6!*WJK1k3zY;r{~Jn4vxza!FTz@-Om9byO<1Y9X-jA@sI?& z4ZrbLAHVx3zkE&AEGgG%=P#;<#Xq1pyMoH%vAw*~V<`4fMKMdO+!9&s66LrO{{ept zjoiBi;w$}83ztD!nH!%5H^{OAy%iBQ+i#j`nm-qiFF+%DM(3)dwzigSo;&ud4%79~ zBn?d0F<LI_D+YKLwA@mgCno>s8{QlHCOh0`6K176k6{7DYXr)wI(g6+oiDX57?~T! z$3*t=oSZhIYF4m4rp$fIPpalSbS1BU&r<N6sYx{xOvR={9kh6ciL{@9eO8@}kLwpf zydVE$n5)4U8nz1$`z`anlmV9hn+VOWoX5_O?XAAi>%X$VQCJ2Rvd6a=Z|b($H@dSN z5eJ#=x2T1|zCnd6SNi@Ogc(FYi1*zR<w9+;>Y^XzKn(`jlGT?wMBJTBY{oH^eXc!) z59)81y+gCTa0ii&qQ@8YFRY#>Y>;UuJEXnb)>HdHg!ixN&m#hC<mT!0b*B{7q*53^ z|FXFD%+00q=Gg5i>P{<S!LR~+pyS;!EcQTQMpGM$DVu89n8%K@etR&B80fw~me15% z)OcGiZTw_SHWbQ`9w(fiFk*W`xLni~$OloCRkMp$T}T^h+@9STu#r(2L}8e55T%l6 zAC=^jC5RY5UvCm#GXL#aY)Rbxks$+Q_5A!^?uGU5P`Kv6#>%FFpZ!bffD?V`o$($+ zj~#mB?}v#HLt2{(Kzh6v!7lzdlTifZgT;RLuRRe4DGCs5y?aO$BUVx#_D%y<8j8y} z!%<565^*)>a=DS^E8<@a%om=BgLLZ)=bqAZ|5i_Z)Gkkzt;-h5cPx~`FUmMwfBkO0 zQ%#=ESJ^ui&T|EmTbKMQY<a44UvGeE#ED;aF15K$%D$a1FdMsPRcHQ9J<%BVJbdF= zzRaT0aHKx-1i|Jek4;y;j}bb%_I-aZ=4pc<PIiTfMO-ara{U=-c|5Ug+n(%aq7Z?+ zjj(a6s!c6;3(a#Y3hzP-UU*s(yPo>Khj@IfHrzMjQ(+6&e7DsT>tF02?~{V)XRoGU z+c?GtC=&A9oc)a#b+-&_?a@lFSA)U`qdAkxe0i*2D>{n^qkV&@tiIDIokHJGJ_iyc z0xFK*xK1$s$&GY%Jf$vD;1hhd#ORi4e3XoinL}vEke=7zgSzs+n!WSFcboT+U$FD@ zJ|is5FpV?kehtj-l+t?*2^C!X-S<letQ`$>kJyNYqLNEKRk%$gC#-o{byf)b67$|> zIUn#49fYKd{7bmdKER(mkUf&z^<)e2TT`b`HvGOMBjkth139?jQYlJaJ8_#yWFUv` z8io8~S|9D-nmTipa%nWS6uWs2GIcQ)<T^dyR#e1aNU&gq#bG$Jn;ri8Z97(qU#O}Y z1r&?obiT-aX>mp0Yn()WEQ99e^m;Xo74no}9H&^Y_gJwBiqMFU7suKH_3n3)wEHVF zZ9OK`N)<OXwvL9FehKp=({+>?SWjH=^*@W{mmTQ8iFUGs;>2~1X*92340NE9dW6sc z>l%Y?qCR26IiD7m$+z~#H1UE@#*aQ0BQvdy=EV=n>yh!7{UD<nYU_@n&y%)pd7Ca{ zpjpkYcE0wM7H`ja!Vh}{^lt#K>eJ;FBSQi#?IB<t`tm3Z1&v_mU69b}SRGNEpVjH= z|8XWJEX|Jtg)JzuA^AV4x1W+{wz;tMG|hOq_<{sFP*1m=TEN1&I(VkDz-9^(pp>8A z*2~fqEcLu7OtVVgf0iq>r(HzYUd<(fcc3iz*~Evq1ZN{Nzl94i-gO<#=PgZ7vtspI z&0^oltV{J*D&}e$8!Jg0OJ*ACE>?1%!mLwpTP^au{)C{qfYU?GTj{0bQiYm^_P?&u znLLie+p=33;rQqp^Vm8j_@v^4!pw}t-D}cJND$ek<X0A(PTcd;lqeam!#m#t^a~lg zB5eKHmKnTL%SPYd{EG3zk;@7D{8YP5{n@moqQJn0#4cDlF0QidRW^h!YxnRQg5q=l z+fOD`at)R78g}B)PCOx49X|8ObISd#_(3QCDBB~zWdq2F7RpWv<^+=;5&y$X1C$T| z^TWTjK|tXa6AJ3$^j7~twBG|{P)m4NPuBUFZ~up?K|hqAj`Mc)zZ6ssX_2hwl5U(M z+0lNU?LIa9e~Ja%<r|lG+QGEGcqzpH&glP=Ajk(W$5Wu>>UZu>_vHZ*6aY>|f!s;S zOuY0S#nWhCN>goq3**8~Px}{(I@%FOuDSy$j@-aS9?{$8a38AQbMxkqGrwy`@e^Q= zU48yF{!2G@zoe@TTJI$3JrvV*r}X~)>3)Fg8G<Tt@IOWQJSfuyQxhWgpFHrD!zaGp z&ZnRg`oBd}4#f=iu>~=LF=OU83p=Vm7ZZ;>I`egd?00v}yFZ`N&X4v$7XN(zQ3^<} zoca$Q`jF43(zQwZm*?yMlASoDZ2FDb0PIxzB<=G313WYZg@wN#e?;>?+6;#jSzvA! zLPmwwLy3mtTc3VU&byg^;y(_b6s9e=9W0akuLtRK`&o7A4USX;y|Af3y$vs_85Ez- z-2<tJec6r|0ANc2;IBh1YuSH4eEHzv85xeR6mybi5zGzUW@3{Eud?6ucz#H6N;DD? z6k51`ej%@<>+pc+2W^v*wTZ$4M~;{uu6m9)^ICp!u(=w*TelHwThMwiupal0gY>Qq z$2c8C!#uO1tW8Tb@mlL1`9TxuySwO()a?hmb>KDM911d|ud8u3LYZT$^bch(z?UCJ zQh;k0uvEol9kx{6$lXW9T>r8U(#st_O2!G`&QRTZ%R}`CI~gdd2<MY~hJx1XT$z)H ztE9ir)%WG-0ZM#}evsz}lvz5I<9p2PlfNfsRP^v%eYe^Fm-=8)_`cT`aqeM=n-~Z| z{2kfPUB4su$bNt9=sre;<$%cv^a})CTSFl&+hD6Q^~K8H3v~BISq}H%?2$juYhxNW zPu#^Q4vad!Qz1Y6>EH4l&PVn?PIkBuuN=ws=Ai}#pxXbF<?wL*`~QQ8mC&P7#Y&Q~ z`A3%ivFn~w@2h_NJn}bG_tFrQtWn|=R*#wdpPTc)K9;-|c1F(NDv+O6T>Wx0>i4NT z6i@lD59V#yU(AJ<KUSglU2gv8t--pl)AD<I>ChEI0HXx<Xm2yLZnxinMrLP2G(RgV zs}Y{Rzv-VR?(3dBeZCLOJM2aRj3FsEeDE8`X^8ka2IE%rvhV8Joob|Qe;skFP>0la zP`^81&^r8)qyse2!7P`pql9aA*4yjgIS)6&k#n)^q;V3#B$s4!P%9JPk6{j{<Bw#@ z3;kWp00VvrPQp3b;Kt#&orv)cBXrThial?n2UGt1_`mq+=4TM_?O%8%hEZ6@>unaV zA7jnNPTSAo#$51pZmCcEG%St97S>0WNp&QH%`Ry;X~BeHr_+m2M<Td^IG_llZ1nr_ zO#dH`H}RY+<5e=my-q72c8loRd)3pKK<0{<)RE3OF=6z?D1}DlGtfhfWST^1%nxtZ z7#wcJ!yE5#>+D}O(fVvg97qn?zC7_eX$DzUBU@LG&}IYS#oceru8`@yF?G_9Wh)b0 z*hT?*qn>~J^G>m>aNSfM`#9YKVq114_IN>!Tpx5CqHR8((nqAr>XY4{${V1q<?n;> z&r2rWsAPtRaFmH15mU_nZTo`}9r)ejq{UZkDXuLy^6?ugaPOszIOCD+QG;!1(hL&r zJ~q%*Go_M+sOV&}@|{@hsdGl>@Sxpo^Wbtn+ZJdlcllNZ<w^Kzu?o9LE(fCn%*z|H z|4dssZIxuKVuj3Se942jW5_$z!S;S*jw5lg1Dq8-P*hlTmTv*>LpkNUzH3N^NL)-t z)F;6L63aV(;_lCOhY{kY3e@Wt1Oc7S<F!g&YlNwfU<0zeck82kpKf#(5qIAt6-wd5 zfnwGE{rJz><#H|z6OPs9u-$`EBk}^e5Zd#bbOLWbYQ9@T@%}{cn>y4VOS1hYAPV}k z#k6jd@EK9U_)%pmN7!(JR+khZ1e02|w95mZ{=jbMHrEm5fE4M6vimk?jMr_~aFRxK zFE(&SH+~Gq4Xt;KC#<0hiKc{+&hIbS+O}B+ZPR$_&Xok5uV!`QfG0hB<BGPk+aI7G z>z|3yte1T4O{^rx8TM_E@&9lL5zU^tn#nJIyNqA^w7&u!J(FgI^w&b{gQYK8s!n%@ z^F5-O`eVenDTW9z^VB8g$ZJQcNtHQ-oy}{~Mp~*BEZz3@BF#ga0<zD1gnWBJu(Lc> zQUO8M%{0XcU*FATKzt@x@GL%^F3K8py`2Xq5|Nlr@10)nT~t-Z%^}6SVkRHVgAoqh zZrDXXKQ&^JfdkVR?LttG#`(o3j1KFU{`~@P+ax1ph<au!BbbkP7#Ht%Ffg}|0j1lD zk3El(tTXGHGVAYF<4XjcF8j@?e_lm@PStu`{08v&&(JEJa9M2ZDw`RiZ^yoB&TPi0 z{e>!SQe8zQ<h%zZUkC54x993ych{tiT{^l3d`Z0p3uw=UP7-k&YK%j{iA!bRKG;_P zgRXe3eZ?6kr!+$i=KDUChRxNB3@TPUMU@-%Guo<zK3A9i@kQ$_?gMReVy`%Og)aw; z48Jek(oMCC)$oEgIbF~K5qy4jkvJry>y~zDvADxL&LuD>`nG|zWMJr(PV5dwA-2Y- z_X<=kmxXpAyT`2f%^1|p;Amvfd~wsHN#amMiU-=B>SE5G5<00n>bnN*4yFSvLXx;- zt!v{m0C?>Xf=YQ-Fo$3F=`VAvtz2EI7&rd(=&MQeYYHzSal5W=tKR^PWg$W?Sr3iB zo$<Q;Hrb&oRjc7#g?aFXdiiv3j)8<mANTQn9XzSyfA$f1siS}%p`<CsYw^(?3zZCS za%W9~l{7ckg1Bt;VDowZ%=yqQRE$}~RpkPq;--XDqhu~_3T1`2Nr@waj%PTygcp^K z&tu##V}fHwP6kdTNG?&4k`v@eHBEPzxQeS<-oz$z6z(s|qH|}cQK7WWHgnx}SW*_^ z8K#ed0b8@xp9J4+HzAHTFF4k$H36!hIeYxbI5BnrI>M><%U|>R+%5{@1?Y04)X$4` z*#+!xBue8yH`K?~+GpmQsJ`>Q%UNxGnxZGAs^RKC{FOz&Z-&Y07#Fdx09}_E=77mX z_3Lfucrf}t(5lh5bq(E<UVj;zzaml|7mXZC5GFqy_w=11m8mD%-vuuo4%?FuX;L@0 zD(jF?K42e^>@uJ&D+@RH{0W1C`;JYP4Hz2$`4kNegtzZxnB?7QDDyX)5&1%cOpMJ2 zViL@JtX}iJQM)?$4_BrMKWx5^iW$b(5MZt6XAM#89n6m$3X|aKn%`!ypcEZQqj9&p zJmcA7&nd64EX71wt8LWdptVJdYi}R+=JDfUmH_9cc-g`vQboS}43jZ|7c?7TQsKMl z298p@<;?0x!d}nv=jBbkfz-7q+pe08`I6<T`8LETu|g8PGct~L&yUcRC9cOo>(-i> z;o5im;1W+}5X`m`adVZSaEHfHetW2|a50vBX5Xuy|1tJ9f@14W1mVs6=EhVogKEP0 z*}Hf#AOy65lGQ;eyYaBxu5fXCTk0BnR_DVzF7d1jU|NZLsFC30%YfSOmD5-l?a;lX z0hD_rm3)7kGJ6-$t=X<4)q;%>nJF&eNyIiWqv7>0nH{gdsqSo`%J;(LC|0|2zAkUx ztD_G%doL4HL#({-lLaV4l+56*hZ_RGUH>*&d{K306LD5*z6IIqB^r$snX2T@K%>Fe zIfb#RyEz|T?qaccdoTS*NPj1EB%$N2w_67%CY^Hrm@Rh*OV>;LMp()*QXas~p5{ZK zBIV8+`O7N!@&fJ+KaTC7Q9-9_)nT4oII&Yq7#s8RN^gzXK58R8O;jS?6!xv{LQE7= z_Q!Kt*|>GoX`XI-#d}llUKQ<oLzMp*<HwS^FraLrhtP-*m>*CzeQgi~r`EQrDC3IG z0NG-V(>D`EYX$>01&hn&oAlU8G6PN}ruU~Go~v%D62`tT>c<LAy2u-j9B;YR?ZP!? zvcDk+8&3smp9O8w{bDrwb@Nq^0x?~3`h29H0`>VJ6K)?!6r6|~C;8%7p_RaQVsH?y z-T4J4ZXo)JjfY;>=|8UB>%9tS1|-P;7IXf0R8+2s*qB0zCO?p(+UdAMVO;`WE>e6f zJ(w=q^1d%G2_F0EC=VATYvEVAl13sCB5`p=l2!S5d2Zk}WI=j->MVre+#Ufo&L5e; z_ojlLNvBkLWfh}9ea>U$OL^!Pz-bXy;3SjNZw}3{;2-~3dvAP^Sjn~L;iM9)c2wj_ z->y}WvxEF;(BH=^c1{GrExw7OmDHDx9HCTyRuXANF`PL}eZ^I2vG6#@PXvX?PeeeD zN2-w1hpO4f(HjSkKhn4#TKo<v9vqR*<Z91+N`B3m&w|{q;Sq=^XnwRY<AM!8mR<K} zn5PClCHNEi^PPRsy>xB<tcTz`oJEyA-}NYWtPu7JU42$()vxr9IY%;-?QAf}H-*?; zEUs1EI|C*a{OMEtXL1i*S|HRmRsHfBef7gd#P@+AdBVntNF({K`)7@w&w;4T7$_RG z_;9#^@GuJd?VxOV!}iZ1{H^@w7oJJBTk{!c!!#&JFjUG@JPYmrz)~46w9Z2~w(w`^ z&mO)-{yw_le>~)DIQHRf^UTDl{H^z|D&HN77JU8_Tl~YBW(3Xnog2=P=a6HN>V|_+ zJ*W6{@b*;)dCO$*n6|A4CH)^w?-Q$fV15_QKFD2W?5OJT^`k!rL^GdEhxsT7(GA@) zZ<HB3)Ta1y^3ReBMtub`x{FIj*R3pvmyZJ3!Jp9<x_8D>#RB2}3bEdqM_d+y*7k`i zlKH`X;_p#4qGcXSOuqVw>i1jjXDWVM=wnMGU-EWm*xgSPD@C#q>*Q506*NuBoxicr z&z3)jJJ84iieh5iu`zqdz-Z$17q`gOMSppc%uREKNZ12;E34?1Q+u$X7xo7ZJ%F42 z8K*^x<MCQuow-GfWHSgHdof4HM+?(bC}zp&m4P>7^bC@Fl9P|9w~DHwe1`<F<pf6( z&}1t{#7;75;?Mu@1NVDg)d(flNlCr)EqBEi(raEU25Du&m@5VyhJ<dgHg%}wBfr}R zEpwVxUh$(ei5~46JyFP(ls1wg^HYEmf*+jc7=sj!QL8|7&G9g;!r^O8Gui6}+0knP z#q}I%^}2D~KcHTDLQbVE#`-VKhIZZv9Cly4>-+BrH+{#7f4q_duvaCzXv&?G0y257 zB)f&_K&h@@2s0N44S&XsTk`<i#m}kqgfAAf)1+GZohHCIi!+Fo(vTzMk)Rlm{Sq5u zEpY$;dQ&iUwARF-D@SDEu_;tW@olkpkD5NA-TQLB7-yw*9cAAS(`@wToE)~W4`Lai z<9So^7xpa?(ygIc?iwL(Evw_LsZE9B_ut%O9_z<D8?0qY&<K0q|1sTLN>nT?yXCox zqI)xg;6L_%Z3t$SD!@i{gP$&4jvr)#)_K1xpDw*LMA#U$Buo5up}q1Md4;r41thJi z;};^AV+`6%zR_|`A_g1T!l_$x<x<Ho%MC!^lrs!^0V^<y0_p&oBd&<$f)pBmY=MzS zajSV^Qryr7H|i5AG|7Iyb^S1Vpv~cH1`OJ9+$jNPI_jzeXGQ<lN9}k3OtX8t>}wWg zVb}MUw4+3IYhDmsJ%@}o;b@7XQZN%>NuAre!C|UxanWiMbx+)f=+PeOqmUY*b8_q$ zw_4&9A>+}3gMGtxmFT!Huk{ZPbqHzz7>*vZWY9Us<nH@-cQlfL)}<BDR1naKoO;*_ z8eaiE&+(cjmabCXoFa0f5Al2E1P?BZQ~&971{JSzh~~=B_(Po=x;2m5vTh^^*lcD4 zrRKRR_tia2&33l5-c89Zlv<-GvGVe4A*m+61;SAsta@c&>`bI72WYhr1|o}owG2^m zhyAwC=?_u_eh0mKcXu-1prDeu^eJJ$vv|$>{V|<s`B*XGYBeC1Dqt}S%NT=oub$E+ zU<y7QlW1MYq*%(Fme%wXIz=2hOCWl@Y{P)!y?mUh_=*Pm5{4Rx8!ppV8gVZjQmg;Z zZ#{|jdyASWAd<73<xNQfcKGeCs@45uu|<35a@l9o!k~3?PR1)SVT#i%A$o1ZtZ`7T zC-sHEt?H4gsmJLdYpJh9wy)KOQ<h1;M>)SAOL_OMI!qA6F}mw&LEnBNM$|!DN<pKf zP-N{bmNXTaz^D9??16^7PKkh9j4XIjII1@Ipy~L(1_siifAK+@X@{p@1W-4v2&-<{ zW>&u$7elzlJ%D{48BU4@C`S81ZrKt^pF7H2;r1k!ktBNyV4RE6L~)_4B@h+a(?^Sr ztJLAsrC-9A1%8`ejvnzB9uI#k*Yd8vY0(>2{*u1EPnZjYfnM()|Ixz)mrE^``36cP za(WELE~qC_bgZ1W+_-!}V)NQ^SU%u#V7%=pQIy~yz`&K%H+Vn8*@AzTe%C5U>wBbJ zbyC<+Eh}&Of*Y=W>HRMR83c$G$KRct<KX!iBBTf?wb*~#!hHnC7pj94-F^<K)O_f? z$_rP8vaNul^eP|^cqYH5sIVnNKg7)a{jywP!1yJn)Rqc`TE2C;gwntBe19JDw?S>x zd^d7i*X-9b4WtsqRYs6r-M13CD30WN+0|4E*fW)CQw$s>3PLL--=pMS|IgI#r>K;3 zb=2K%9SxH@W58CKdix|J=RZxeg@R%bkS{tLnIcck0J+V*^nX7jXn}4fFtsBl?C8bg zfWXGk92TikdZzh_VB7srQ;tb_xr@bqs>7!buP4ESyw$-W`-iFhZI$H$pW61dR5J1v z2NNk9w-^&PJwWUR{z}j6$8gO5N?if9k*ngU9tCy4z_GjYyal}nD|^&_BB509e`fw* z(lTNLOzu=>C6=8!;ui<3yF9-mpk&W!q37VAnR8$UfU+)nh$5g-IF6ISrW@^>`Xfia zA297W9OO;^nI3vIRx-0q4Jd55vIMGc&Eu1AUb#KR8#bo%W%P6Nb?%ciQXS+I%Hy8~ z8H{JD<2NfbH8R8&$Ezz_kCM*pB3j@I#LMf>nL=jx5>z<{CU}vr*fjO5ul|&Gq?ZEQ z`AUr`he+GQOwD)w{gE7w0LToVqB4ejh2|!Pzp?vRqV<&{hx4T8{p3#m@%J#1W!naY zer%%G@WYClE4NkA3-fnB4~(fJD69(=anyH#nj=T7nXcX91BUCmZe}#ffaGHu253hF z*8^sJc=j--IjRGb(>SE08x)#?LkAj=2<E`N%TeXOeKLxDpX~EtR$S0W&3iYGZ^*6V znNH=n9L-{}#Q6;1Zzz*H=fQ={p4d(!E?-VC*qhhy995hg?(2Byzd5zpWOQ0<;yXwN z)O*~o@8lzOszm&NwFRe)T;G`3YgMQa`I$OZJ-4!_w7OtFk05b5sYERUu9~NjoeDxg z+`j!8Wzgx?mUQLc4#k0nuH->-dEcQ3B0?OLiu1Y@_Wg;#l4%2tmm8|W@@HCCRW(eF zqDLcqsvh%I^K=;t*_@9knhY9jbWnK^%cOm@O3SJ>%UYW(so<3@;0EQLtA<6DL~r;) z9}71YOmSl0w#yM})cov4g$6iDEJ@+S(mf2+;43PyMo83TDz$c;mQd0>4<uR_Gq|qD zs<A%g`#rz|b&<mXPKP>*2HhP(MTS4{E>OIoTcQpuN^@I<gUVWCrZTFG8sK57e;s>l z^w@*6$UnQfX!JE+ErnT{ZKL}Z!M3?HV42dv<GwFD^T)9ks$v3cF<(+6&N*p4oX=Iq zY#@uDlx!XWu<NNwPw$gx^`6*wEbqG|Y#HkwLA@_B4kfvt$Nsnd`3_{BT{m^Zgmzi# zfnTD`5XU*rA$s+#-*A*S+BwN8WP#IGHwb9<dOy)oBiT_5DufL<Bx0g-pRlSKxfKO7 zy$>@vj~Tg~lH~S&q{<sNLVo&{O@SAKSG8GIRSFTZPNhK0MSy9>;tV)QR{KNx+fDhW zu?5T<mmp~n_gfRs?WhrY4;l6eSfrF|x%!w^mG2Iy&fUu!HA4vOB2TUoU~$iyuChvw zzI}lH`k>hL{^M4ib7{1iv<^O1!Qr6&EHbg_EGd~wR<7Lj+lS9VYFW+mJfn|sm`^cv z6d=?@hXlWIzU>9LE;_A^u>a-D{O^iofO>^Bo%pSPNE$npMJto3ZKISm3*zC+)(<@T z^yP7evSE{_ktXg{>A6=e9_86MM8J)sfAXn$l5;^-CSPqbZkz$;O1aLp6Vq~!!eFiC z<HP8Sc7V9me{oB4(Qdb<v<2!2DK2c;`0??b!Eb4JeeyqMgLfk7R#b2oarx?8rTP}a zr!D=46$)N%dy$5m#M0Ki>eM~vWL^z+Kq`D$>t~VQC8Mxr>?ya-O_cKP1Qr|EDs0!- zm<^}h-MbhRoe{qfS_#-@b`Z>*yBL6Dx-hqaVh)Q2Vaiz$rnvto;`;4C{A;tkL0xH< zi@qvJCmdf-F4Ui;a3am<(R)=Q%&U!io3SC}N*g#7R*|TohQ~oWm`@#ditw1L#r*C@ zihqra#YQM!iqjOT^pB!OZQ;Kv?kzwa`JKXB3OLRMhj)U=!+*HO_aKT4R~@GPA6v0s zljV+pFKhS<<pQqNnn&bWH?q#}P!Vh*=(IYZ&2rfV3Y!n-K3f(P>XC+Y;*g5oI6y$t zz+|8*Ep61VSO1F^+27Ri$n)2-*>xT+ink*^5=K`6Rz)xPL;4#h*ix=L023gRoQGBr zJlWoIN_+CoOxW|g87&P!tzwkNsiLJ!)SBUctWo)XVi!=N!@837etcPPl;qZ3Mr34% zl}?XvsJs>|mReC0dNmRy^)}t+w6b!`Yc)%a;)-hlR=S&EhQ7w6Q3LgW%s|3lTogA4 zi5?E4KdbYr&o~6#>Ah+tXKiZE^mZuAXZ~sOOl&Hx)uuA3>03I_?u?~j0WWcAd@JJT zz=%8%Ah_uH*O?**08#2_&$hw8ov^AF#3rBmS;)hw8<FfS>B#@JYHd>Er}D@s5?{@A zDlS=hSuuSC36R&N7>)+1#LnI)uG3Z}3g-HDPg_P`sT=NM3M?7=EJ>qLS5sRm-|~rB zHDgh4f9jg)-dP+KDz+^A@}^rij#J=$O$euTYSgCJ-WyJr%FH^S4)>J-k~JW_g7-p6 zpdp}$Sh)fSaOqkMLMYoImoA|vP$4Yb>*z=A&F0+>|9ijFJsCd=+N7QsaxGUz#0n&F z@+Q8tXE5vgF!#OVS8I_}7rnzAPZ%rA3lCd#R|Syvddur+a3PZ;oc&OhdP4B%cTS{? z<izUYCg=EHUT-WirPAQ#Ms7XS?K@UK@R;vVXv)(9&c8$cJ_UvbEULl0yMGJR;p*_~ zuNjPY{3!8@R)9Np!JhXMKXwtVu~No*1{)<BDxiDcol#lVib-)#Imy_%C@NFc5*^f5 zE71{US(k+l$^1IEq4hI6I_a%1MX~UYK|Mi8LJVadzSBOK(1a3&V*l!a-Y6DMdU%%& zt!^XQn@HJ^S$^F1ICY`y<cQexan1quynBrQae;t3kE7s|)?(h+V^n>`*@l*)H`xB| zN7|7D%Djj_0Zlb=f(GthX0G$l^ffUzK~B~wuOj1%P?Qq8k8=Z+<Ys*h0&NQ$*sl*T zn0T)ljPLbpstAhP^j>k~+<(K0#*yWvuq7T!YGugBxvRv@ENEw<xGiC8V4M5Bb%5p5 z*eGs*4J-JonH}yub;auynqo!QF|C4s`fiD8G*SW|KiGi0BP>TqRV?WB`f<(Obo6eE zQ$}UKMvuW8r-D$)f+_Q15!a^$w!#vrnS+krE5l2zs)<EUUuVIeo9jvNM$6Qs^qOaj zGx@98ll7lsG4^U35yR4SwvgQ^fIfT=@=-^Q99r1@B4Me`bhK*7>$lF&DBk7&SFXwk zlyM#*LGNQ>?cSH;G@~&cUD7L~aPg%r6wtvQG7Vtu*SF0tGHW(|`t>CG&i=GGhE$A= zFpp?3vb=SA&|{kHhW1FZD{ftH7hX}j)kEF+Q-DV;QDnpLY^v|xT+4mzUq}XYAzIN< zw=Kpp;fk02j!02}SERA`o@|(*H6Vs6d?lcpXiK<;Jjsh`bDzAcp2=!PhN;3np0oxV zVY^@~wIiL0LiajxD2w}ce(O~`8|hCH_cTZ>xB$zk!(DLdKfB;SV@$uysY<0c@A*0> z-PNN{sDS(ZJDJ1q=;{vUys_`@bO^|NMj`N1clq;60kir(XL;mv0pgJK=mIC!glybx z+-IDy?51mAFJ44E#kxEUJ`f=_pAG2vzmCijHjTXuYL?K(!rY-6yGibC_tgR>j9&XJ zVJjDdY&<oSLYw3`=a$`tYfO+~MPeqFAG&E!Y*Fpd=7Lw5x`}Rt!Q&x|Ktl@69Ov^v zv`PMo>r!Kv1+7p^W=W()6Np*FnQYYjO|?c|lpW<6NL`n3+=EhHDq2}?+|?<k{_mGP zL{5AF91<-vK#t;4_z(T)%M5<+iHfviV`E@(FsGR9t~$?t7pxdvFKT8p$R-u+C))`% z9vfge7X*lUqV9L3xic`6;nEJ;jb3LRI;LexXd0vy+?RMUccr|9#1eGPG7X)IjP(3} z_>v6mWEw>`_@TN|g6k-cacPS#IxqL0p(lXh8(QXFqfs8+aQW+ml@a4lRyJ&uukpE! z?3S!2pWEeh_hKYiKl->P4d%9pn>BXD*wXSbJ&a{isjMujE*^hLj$*@3l8!DJRd4rr zrF5INEp=6=YN2O_RuoK0$reL{A)Iq>OGZBnz#a;Gmi-g3{=wpaEGV08V8?@~nlfOM z88U$kv^i5`jLkOwE2r;H1G{?SHS68!xN+;O6iZa<5@~WME7jAcnbi&dJwR>>tg1AS zw(x*|a2Ku*122c>t+&;HFc2$Oc~?<fJU!eiURfQLk7*pGm;vFyL{@CXc5AGYJLh$L z9>wvRh6dkml<i|Sy4~|sZbO*6b={eO-^k&d7hR=g-e9GZ+AXf*?V@J9l9H~vSc7{L zLk+%o=sTqCwy$TQmXvDcn8!eg!T-<q1Ub|k4=l0V`9p=Yl^b|ZMRVE6!j|;0QvvX< zb;)ncppM3GvfBo>_hycU&wRIvaG2oTpGCtqxvWktm$t{@@XrGwo4=50_3<qx5G~K} zjQA!ysnAf2O&uJ|-IJv0_;`G~cAM2>D$-Ir__e+r*!4@rR<#a9h(-3q*jnt13dR~P zQ@3gM+5uy)*HPa$vjsw2?|}x&l@w77`Duo!F99a9_>x`qA(b^L%76=yQR;GC%eF5y z@mh2+rV*vre%oHya?X_f8<EoG{g&%s`$g->sYH<|Lrk0aX)ZFI*3L3Fi<*-$2wD91 z4XeHpMs@e@=0|NyLRgIY;z$h@v2w0>4ei5|{Is5kTVeNVRaUt+>BTb*6W4uuK$3kJ zll{(<AAhcXvFY!`K40<cmSB&n4Py8fkKjdku>S0%f_jv4^}yIcDXg$&z3nI&%crTg zD&dSGzXr`BsN7_+gJ$gbpJYm57p4iDxtiBvoQ_AG-InY;gDXrXR>qq6?ovq%{w%0o z_7u5@g*@SfyQo#M6tWi@6v9@{qg@>x7bi@gUVpxty%_bT9qM)4=SO|@iIrPUTglri zJG|Sn?Gvu5Q%$ekvjQpeK80U_)Guzg8wyVNM6kq6H_@@#belKTvN|E%oWh#9i|z2Q zI*##+@p8NB5WFJgdegTSk)Os_)clY}#Qf5Vbd$I-*maZ|iq1=`n8w9)l*jeXi_{(- znSuRn*!m)-rV=|*>2R~>=Vrv$Xd`7HWki$PVs&fh{!c2iXj<G0#I=AT$Bk&3T!EEn zLqtGiE2Xq52?m)vkL8?7Y}ovH%mkzTC;4JPacwnk7kO&Ks!^#EU~WC`$sOKGkN=M2 z=RrTehMQL~AgwozBvV*ES7|VHEMYSSbU5#yz^oKkeS<Ypnd9enoL4_#dmL)pFR+qD ziYx2~&De&(?$munuK29rp59o5K2h7vwe6k;(iaYdW0!$F`q#`}-u?92O=?52v>uu@ zx-AeeA`;2W@JpkNl8<Cp5W8Bd6yD}ENlqhfEowGSU5S>iY%)8iCxKpg{NM9QDj~Gs zkk+39;QUL1a|0IJEM2f3SR*=m@wO4;b`Y!PJIv;3luLnO)IFz1T#f}k?ga+luYGm` zcFB}(SM@I_d5vj@=3BYU$C#^F`_y&QnCX<a3maEO6HEi<;6gkp^{KB6VexGHInakJ z&+I)HhCmtn6p%{L6PDz&u>i1T3ytLiu-BVeKz6;z;S?S`3m76yknh>#jLnZn7KzRs zFT<kH<MGt8o8Nz=DS5#WQojN(r^1Q5n>(3&s0E&Nn){tvuShSi&#gR>M7vL>9_1yy z6KC-s$RF6XKBXKNl}r9?@9M`b6#CwF=^ZBT9%?gEIKt<{V+<sOW0k~J>?4Tg<v5<3 z1jjloTZg5e-)wQ2<U@1}7IVrmjf1J{+00%q6Xy^qDjD8{T_!jchvbBQjl3&2$4<?K zidk6w3vJ~%MKIPz3CilWzL=I8^{Vh((R1v3jd+74Gt>6lM$y&2&INV^^oz$<cytG7 zUr#V~p(s(j*T!Kj6<V`#Zg&zT6s2iLt@RSg-?>h@pMQKmw|$t9&f5t4jzOr6j0z_* zPdhoA)s^mx?jFEbY5yxf!s{EX9Az_)Aiy7a{d_^TM=IWmHw$lddJtPjlZo#WkL!0| zENYfpeL*8oG3vx@_v!1H+c;s^ws5Fnm8`D#wFd+nGjl=Fwc(L*4!k=~pg#8scP<6a z%IgCjPPwe6qRn;r?PF0Q0ZGf6$j{B<U(v*|z~kDNL0Q{(yHllY-)z+Q)}U+Tkf}%_ zvgE-s!pw}XB3v6X@#f<RCoa+cYBge(+Rl51+Hn=ET~9D9hUFpSq_FSC<bVkhJAq~= zpNL<Ao`Jc<`^@u!MrFZ3{If}W-c{3>HTzT*Y8>JYmi-17w5q51oG<0@M%05#ob4?1 z#LMrf{+P)av0A28i;{_SoIT7;y_8P-#333|p0rq0)$)VG%UW)uxKZQ20SVu$rLk1p zE@ajmZsfI826U%JA+Q;92w(d+*=3Q}gne((bKGZp>GNcGJBR}^lN>yWyO<F$SK}6@ z#^F90mHv@N5%Ie7h|M(m3GLD$=*YQg!o2-vW+Sr|7uV%eg>Y>DLvzBnf~x4R6`t81 z${s7xkhp<}fuw<~fs%nbH+p=DMn1m8EeWrYw0c|EyDn~VD3cDu2l;fh$pk;sTv+G1 z)PRJZuNN7CU!0l0itE*0Mj#E&>`pd~X#Q;An;emeW5Gfr7opGZ`Z{Mt@ZcFsF+A&8 z#s!f5wB3#Kzaf*IFB2`q${@z#2Bs&U9*EY0>dfs2HzPE6Yvk9odi$XaVn%?u06!7H zzHHPx`y&k~ph<XP?cmkBlErsAvY>>yvzHa^s+Y<oN1xt)5f$qeWBLi2+M@v-!_AS} z$6K`1*;Cu0xTsYs3P)Pa0{+u0R~(Natv9(hfX57<j?wKv?z_jZ)DqPP-TA6@*kdBt zm?mTO*tH$q`LVByN*)IIk)=lWNT%Gxbk&`At0+Bx{h7{Lwf4E-ZI02$g&hJ7**4kv zV#(MG8)h|v#H3-b39@FPa=<vzqVz(tJlZt6w<cd&SDOf7iC3FSyIAwA2!3U1{`-44 zHG_E@LRzn7M*_taVBc1g1M7@%TbhvBLCj-~y2Jzaqlmymmh3eo(`r<TTA`hzh(w$U zkaOM__yu!CcVB~q-&-gofe>iyksnp8k?Ro91sa7v_i`;ZFZDOz^n1A4v{C#E`NXpz z+V}BVL05HC45dE}I~!5Uc4aG+Nvz%!zZL-xJ)d@E20_tbD%F^*dK8kpuv(vWMIzv2 zIA3}0>R(z<BH>*)G%rkOC8b#NGMX$99vrRl_A4OazKrj3tDS_qCn8)9<BS5D+%`hV zxlZZ8Q<jrH!(ND8bl3(-;4hN%YWXYBU_5`7YY?itBbPr4)y=pqR@<o(p4E{rfQO$X zk|<xrX$fRNxUOU2mxd3(5QjAirty*J>jR5fP{4ccbow{uHzXfk`|~9Q8i2}ZSf!i; zSY1DFqrIxDt6{9hm2hm+Bp^W$PE6&`Ks>C;-6&X-@Pl<hc<@>M=mj2xw<t>!@D?uc zDuSc(6H$WrFvvoG{o^D7hTc|BfPn)sa$!yG23{-O`>k_4oK4apnKWVT+wTFCMUY07 za(Ts+c2{lC!_*y3xYBL84J0#$q<4lm_tX9~NuZ_A^zJ8k!K#lw@F>^pjh$pH94sbC z{Hr9Zi#5q@AWurVRl1MlKP(>rjAg~?(;xQn_hptMo2Y#Uh)&mVEdk|i`7Q9Q$zFF{ zK^<`~^Q#q*RM-|no_K+5To_symu}}yvJ*90xG$heWPZ%JNF^Yn+jfs4TP!NNt}mQT zb{Mw{g39z0UIV`x-3RDSVG{e&nN*tPa_YvsCTK>IF(4Rv#t3SMMf~sQVrGn>76nKL zV&!0&6(mk_!isNZ<kBq<pdQQJUV6>PFTL*d<*&T9s-@I^kX+vCZZd=da^`|f0c<+4 z$WSsPT~i41DZPO~AO4}S>%EUVmb!!zO}s3MO)==RvYZl3o>sHhs-)2%ndJ`hF8*93 z9gni5?r}6MBJt#q|8puN!={|N4#d1m822!%D^DhyBkI7ylHPPI6xO8@9O1lh_Kx`X zn+qU6un$`iZ5KF4-GKutWaaK7NMw=j{d_o($Z8_z&-+Q5TzJa%*5CA07NvO5;|o1( z?@7YV$S_m7NCDjoBNGUaI>;<jB2VUUEJ#Gs78_a@Y(<HFN~d0ei#rO@;*eU8KG0iw zc@0<Od?~YH((oE}ij7}fal=vla+!5(UH28nJAAa!#YSWfzUM}|$t>4_%?Mm2tY??F z8Fyuu_9I_%8iBc|IG@Pk`9-7GB<B{Fy84_FGE1@m_LD<Uu@FM#Ij;u=G&YXO=qF;n z@d44Bs7l3$qMyHzj+Y+$GcBUEl0lnRr`Pc}k7SF5l)%}foM-6`?224OK}c*W4S<_& z+rUn2lok32vc!V`ZpnVFT#0A|55aGo(~x=AuV<BC)~^p*3e>ODC^ua7)ACQ07om9+ z@!e};-!iyb)O8P1gRpx$3*jp@FroK&eb35^%e=DNaDm6-kus~NV?fLO8IGcH>66?x zrsWk`K1t+;Ua@PGAcatOvxb@=sE1y8J+20rUYG(BH_>Z5^SX7Otz2<~3y^`(gefWA z7rVSNV1q1eD+rMccQgVFxA~K$ydJqe-MRmUAXajVl)T_K%$y}T9Lhd(2_)zX&c;#- zt&)!99{^zvJ&w?oundn&Vb_nc3TMC$G4`LpCfQea`qV%@B6xhj$jyjx5rmQfDel$v z@#%sSm5YL|0j{W-tC|HIIf&4xN9?KBpmPm(f|NO2o1CcRI4x+4RUgC-U4aEhmqprw zR~};;&}jRT*z}D$@1sJ}^pf5>GRjA$aVCpSq!PV?tri`?A=lmR78u1)icce>h?X6q zAe`3zf4qHVT$J7Rwh0y>poEl?A|>67N=b_-9n#&MBhpgRATbI^NHf%s(#;UkokQ19 z!@%&~qt7{y=Q-#7`kznyn3;R_z3;WxUi(_tx|V~_tvjqPZM36lrR$~gvD5me<It(1 z*vZ&?Da*Q<dTJ_M5lqXnj&%c@8Kv5iLvyvq>CfzDK)o#3YNWp+s@UD~&Npr23B6a9 zG0%;mK#!eEudauF{hcSp|0DDQ$_NH+qpfL^de3ntGRwSyDzRtxvBAcrOYe%YP`Taj zd_GXK6Fm%)7MCNLS^bYHg5ON$U)jrwC$+XZzjxo?H6K6T{XL|=6QX|=PyFW4{m%Sh z=|+F{n*YD~B0zAemhh1D_^x5e*)xnGT?S=3i(h#!@Eb+`&GP(x__XxJ0a_4_zQg33 ze9a|ve_ZpTdidDoZShF@0ZsuR=&I!^Nw<eiNuCd@V=$<uF!a#kE4jpmwKw4P=L`Yh z=8qo1+n(06fr3PDC@xspI{3G{9=@YX<4gbS`TbQt;Umfo2=wJ*m;vm`#gw75!E7ol zH-RKsd}jDW=h<rukI3?p?gvWIol5B}^V$_Xktr-k+mkVr<gYhfuZfPNv>X|>v3{%> zE366+{XAU+bdQ*AhlO(<rAY9d>R${U=|x=xpJ^@W(OzVG+7h|T8R_@j{qOtDdwGs? zkZU}|bc}exk-|L`b|VwoP^pN4?cZCK%v~Ql$}3TYvgmtCRpSwpu^jiPIPp@KKQ;}6 z)t&JGs!=7xW^G2t@S`#bpsm0gxMva|QML(-jwsb~eNm|ocZ41i134o;ADhJ@X1~st z03#{yP#ch|@;x=(*!ru4r4j${6p`dQe-cl-Ht2#?GKSA^O>wJ$>3RQQ3u^w#a)yec z#qlf^f3&211yB+gmR~U!XdNwXOPQ9_{do}E4}zNxBRIl$T=oOh?lXNiZ#L#&Ki&WR zn6O!NnFxsnF-tsnJ7mMlCiEOC`luw^Q}rCFSFnZr32Gpj{)^Z0kD-t|_ef!&<wd{_ z_rmqThKcv4_CgjttWlfZnW#oIodw#GNC8NaseF8Kz(~Vz6XPCrpL_!%7u^bK|EL|J z^;AaiN1c5URHToq6~s}Ba~F885T5B{bwL@yWU%IlG6kCU9lBUIS8&$+=G48j`(q(S zohmdHRYZM(Y^*`PrQchnA6gyaAs#ld`D%efIC$=8wYHWf!YO9G3uhj(w739>>=>zs z3lQt)Ish&zDC0DF%w7ZTqlFkM%|l<hI=4@Mcv>awz69&ohHQcFz4`&Vc<$+$r9YYY zS2E={Vfgnl0L-E-#s;#n0bv=)UaJ;h;1vpS`kER=-)J`a48QVVDP%7smZQ)gX73kr z|GP=ZV#m<UUK5~y#NNkXaGF-DB*T3fe6&2Q`{-k-G!cwy{=BQo0nn!#|EiABcu@4s zj@HQqU^00hUcsP7eKiSS;%)L&+z#PUT(U;aQI8}!=mYe*%;kXH40!!Po51D_?$m25 z#=~QPv3>g}KYDNnQH?^_C5&&L4r>_DZ|}J?3{@~RfVcUYxK2&Y50XUfp;Sq}wV{AQ z3LiYtM<*Jbqi~MYw#+F>uL{e71NnW8jq7L7+2qO%L}O9In~U0ik;&tboJnO^3MlZ> z`~y4zj8s;081eFr=(!{6-s*D%<l6v+ToZ#)NJw}QJw&7i$X-*%zX6NifiU012xcaJ zu+ao(Ji|c8X<hj?`4%fLDV#f!4W-UO=ydMC>W7^{d3>(E?g7DvbvRZxLQg-S*Z*X8 z335CN(Wj;O=%uqnmQ*JEzs6JPYqjt0P;d^7RrFOXY8Z&=#r<5?2qL}FN2Ky)tXzR& z9fUr(76kOYE{V2<_6MHA*QT>(0{}CrU5Am|oTr~viWPz5+xG75!bjH%M-LC_09A{e zLrCR)L1`nksGII>kS4b%+u$i?hjRH-Y)<#T=EU{A2`@xpeG4L&^(=eCKxM%=^BbUq zx7PKAAKLO#5;MMSq&!tF5%}f@C{(#4J$Gxz+!w5PYSZL04P>-WEW5%10pHfgvC~d$ z_tncv@))?_gaCz_OzASvW$VB>YMhoM<V+PSMK1Du87Vl(ln%J1D4LKIwteHIgTJ<# zf0)WMYP7cN1?#s0bC0O-;%C0r(uPW(S)2t!VikL0To|glSUF|%8KiAoxkg`?9(@AR zZN(-X>22b)Y8E8oeJ@EaD1{A6<QRadF*&Bq0OO-M{S2MGeYI>&<0g?)hN+gy-*s%) zArN3pdgn+gK=$X~%&~6KU^{Y!bTQQ>Q(8S@a+Vmz-%I>Y;?~<tAN1a#<DIJ!f}ELa zL${J&pMPHKGbc49*pb0s<rGO9w+bRLaU-FYdVQO1mew*sbf1-Tym=pga+}`eN^h|N z@cjIP!4cNimn^Em5p_qb(&H^S^qpI=No9bE=h2|ENb3(vDxGZ%pBeEPG~n%_QILv@ zk7v?Lv$PjPsD`STK#azfi>YH-qpS|6ok)U$8STV4372~?*-+d3*~-hm_q9J+4p-K! z`pq#K(cDkCqrYLSRZ!Yo0YHW_Ejb@euN3CpCL5TV$vG7CW(@Fw3&93#yUx#~E?DFD zB6MD~o<Y@BG=G5Pv`fqC25%)40sb9GyAr8Y0iAbzo}VL$y*Y6IMTUAqs*^a(i$ZAv zT|q|HC;!?j{><h3Iu+spY&Qm#FEz3?RcUXo-n{gd8z7JW<|+?sQa0Z{e(dnwWnXmb z?qB!ui)H+8)>gD?LCXGir8*!qGal-NV@7%vGj6IC<#?#!Pkie*2Q$90q(z%|Wc^oJ ztK8qTp?~qoYqS|IL#|v;F|?Gv^ei;w-^`=xcaeXkep&uAulKw15@4tOq5=&748!ur z(%aOz4cIX3lJ(!z&A)>v-#=Jo-jDTl-7pU?2`qmNq81`u_jTpa=D@wAu8key|3c4I zkRm!u5(*}L-Lka8AGH}AvO7+_DS$AbU(p6A+_ClE&;p>`34%sKAdz}7<GE7@BnRA& zn+_c=y>G>~?frwTCd(Gd{*mqKGa62yXVFOSn3|=T)uU2_KI()4+QIgZXYxyyw1z<V z*{_PdbVj5YwiEcpb?GVlb}IBH6b@WH9E|h60^4-&cdR*b1y97%r>OBv!=4l1kMkIi z^d)JuhIAKxl1<~jamg=*4CqQ#ASQ077KL~Fu%@mf5}>xBO65<n<dTV?9SCr8zW|Vk z+RIzZ!)kix!$m&MK>7?=XkU8&hSA>6d*eN*bNJwAbMNP{;9pel(1p`IKtGm`e>?N& z2-bL%Y0tP-x^{D+*MxwMFJFy=NqBm^?>@zdB?>Ien#lqSDt4wAN)$^Qd&(_v<P?>( zCYx9&+18e2xNYv@>=;wi<(w`5x{X-(MZDv<{)(h=<eE&C!k~a)iQauS*_pV$+q6i@ zv{lcfzk%T^VWg<Q__-=gMsMt6-=aH!+X9`kvFA%QJ?}$aGtvh1^o|YiFChC(4Sd4- zZ|g1iH;!5a;HagQ15<YeHcsT%DBl#nd?Mqk`*U@>C(SyKkH4=0b&zQT7wbqf5=~~v zuLV~K142xOlE!07<QG<Yo}3qyu<kw}X1mh;qRZ{|wq((;lII!p+D3cY`gS_^++H=% zitALD@jsaG(a3wvJocv>wCzCt3j4st03ot-Z2i}YheRkL_-v8J7PgEn(=DU<w+R6h zlS;vQUq#pMdSCX`%R0S6Yiy}k>K=cx%EH}HD7Fxlsx651EZA~fJTMnJa<5rrhvpu1 zzo_J`z1PUz+2>+Y+8u6e)5N^FC9}>&Ka$@T!R_D*Xp?1m^G(Nb^-0>_X1raJV0CQe zLa|W|U7|J(=`6jsRjHmtv>llP_5p&uO{0I|rnxe@75y*~F~%5d1BYkmA0S~Pz*d2! zYIg;&tiM>UKm)bQ04w@u=?-M$(*^6>%x4^>*LJ3U#I-(vZVOmjQk!{nWN8kzRk)XA z6-r_>!mM<Yoi0+Q8BC7huT#O>xk+IBpxBL#kjz4PD|5<Z^C`s(D~|7yy@j;bcN{Pe z9g<EFvstHzN8i6l=X&X;udW4lX0rX7&s{h^FtGP5*m(W-xe3sFFfr<~>WijL4FD)^ zo%hUULC0i#JxUJSvK`{vvWMYW%A1{Y+tD7u^oH#w29+J4Y^OA*dFJI(L!j|p^7rX5 z%y?f$p&z)<;a%IW0eOl~0)ge8RvK3ve<3j{uOsHv!$yzfAd!O+jrf?zgQdD|0hPj7 z(rOi!T>ftiU*TK95$wgU{$hai<rt|!eRMfc1i`rFaYZaEgpIMy^8<BHJSS^Wr~E!# z#-ljbZKu~|7&saTBr%gWG3)XV8VuF49Kc<m4HCgrV9tvahYh;HDyI3(lJZo~{dS{^ zCoNu<_k7M4v=8BGYa7x(L14q4j^B*^w1y5xzF!{fzh|jSYnI-tD1{w@rV&*S@JiGE z3XXSR?hn1fy(U}&3zzBp`t~-qsr85vpDVAzYXw?WR;F){D}RC}C%H}N+Ha}H01wbc z*bq)8+~*XoM{|+lnhKODMwx)05BXe(@H>l;yZ5Rmk>-NagiMy=>ChiVXbNssUk9Ac z7a*LY!qO7e{_s4sKGqZJ*xuG^azM#lKPZUdfma;q9$Yj$`z3QUYv=fYM(|i|;ou-g zz%3+1LB5wvxCyA8TDzWgV(OS88h?~8evZd{Q1D#Em@2AG=DZSy2_#RcTypLxDi1OZ zV{3SOQ9JN*Ty2RcicKPrbV~$Vybi#GP;p>_=KjFQx|WK3iBTdj%?nm?BIB4F=Z={Z z;w_+d##Bc0O4bqf5cTAQl5|_$=rhN`6USke3OV*5qx^;_$>%`rf(rr=X>a{l2FwIz zOAdA$|J-rj8I8L&Uqo9J+B1qEI7Pwfq`LtAZ}8?5uCHc@Zh&nIR1C01eGA{BGad~3 zWz#qTU~Kzwe6f=`Dm*OBVy)3dzKfj+n64l9|K26vp6Y$;1p>(@x=#aCzL1h%87Z^Q z0!I|wj*8aSgn=vgEBZhQ_X-#RxaTDNS(iMp*p8&oV}(YKrfywmZ!)gz!{;?NLmvQb zBJ@kaX<znHlxxHTt?JS=Hg1s}<ln!D*E7b{hX5PVkuvz=EP3{9rEEx1%M!r4fZBZ} z=D&D9-4Wn}0cmW8VCU*E02D@SnF3iAuhX^cNjJj1e~fwf!MlVbm;-QVz0kQx_s@_A zIQKBO7x}4qBcOJRF%lrGbaS?X%cS$FVwlX8IyWJ$PcLM!=VrG}w$Nxb<z<ZEGCI@= z0MKNr3W4(kA{Xq#Qw`fe`O!%q#Z8aBkh9xl;i~TUyTN3J0Op(oRXnl>DAapLnRBgO z!anoJQ#2wYLdXKP9Is^%!cY%v9rfRT(^+QNg~d8S$>+646PC_Zum7={HLp$q0X2mR zANq7WE2P{;5nH*Cln@H&ns3XxM7wXO8GU7XG*Hc?rOpl;P3;$Vttj4opmN0k@G1<2 zA0%Xjs=-?_1lPi*V#kW<A87+B9420cD4Fc{VEo9>mI2@3uj3PAznQ7DfjI7>9D7zc z_1^pua7O8)&;;j54xTs<ohU+DJwic6Muk?aQ_g|@wim&rPp-gDh~+y)NmHYckc+9= z?Ydo`Lq3n1+V?LR@Fqb_hl^Mpjz66g7VW}@sgm}$fWwxoab#xpU7#V<79n6hrguVL zzMO2#nhFM>2+H^5ssLbMfHRhjpF0I2^}*5OykH%1$4vm&%Pg@)Aq<bg$cax7`W9)~ zp(#1+LLBvAOaRHAfUL?F=}^j<QAY3kSVx)BhY@6s5gaX?#T-?drr5UuEUfbF>J6Vo zirF0T@$i3o(UiRcQXqN-${#Mj>*oT()*Q|mwWZeut(+pJ()HkaU7-Csg~SoDJEQ|f z8`PNz2kJh)cstdCj|y!7MvNZtkg-b%2o=gzNrV5>?_l{ggWuy+7@_wr0Ug1yQEgmX z&3C1~fE@_@E~*x2*+*)@r1p{W@vn*sU?l)4#0;8qvt;WE4g1#npko+Z$FY|e3@~th zC%bGDNaq6F8|MMNG;|GC6(+y_bX}U#zD1ls^yg8i8Ft$Qy0iZ)u=`h0hAiyPrBwld z>hz(5T~pj}GKC5S^kj$%p{@Kl#j#HpH6-Bzbm)1el?%Y{V&2sk?rU`&_lZwUA<m;Z z#{gLGQP5@M|BuD?w_MLZ!e}Y43lW`2p%+H+9dL>Ikx>e4kSNoRM)=_i<*1Gt|HC=| z|42x5K-V_>aakGzx1^3SF)D1x>N2>8L1F0(0K4vJ$`M{}{1XL4+<)%Rf8(0Ld+_F; zB1&pOB8-mGU%|SsJ$Lbe{+T@3(J0`e5nsiFY)V>5uu?sMi8uo=yXamEu{F6HR>0#A zpZ$v%hmE<}_NP>OHLt#JlnVo-8+mzvimx|7#n*kP^Sx8V4Zw4naZqhS+9PSeJ9WoC z2;o@`hfW4HfG0`LZBk}9<^GS6YJTxG?cL!`1hKH2VEd%>W;ncd3D`|(JX*B8*nU#I zuyHjf_*dW!7+%dsD>5i|ptD3F@%ZF~m@K0;c0PXD3y>$0hlqI}tPTKV!jR(y6avD3 z?C~qtrThN4={CM=0A?KUoQgZ`*y3P2Yzfd`k=6ByQTp|`#VrS`pG|_?a%r_d!NrWe zOSa2khNm~lnq|!)Jua*479T@C)4X<Fu6{`>fO5WnmNw~@-h_d%=&xUr{exk_%9?S@ z<Gv;OHJ3T}FIPBmiU^38VXxiD%}$#DEU7)5q7v|Z5FnSQB!)5)E~3SrZ2t5Xnfu{` zrtttR0dkwlzMC7-!_R-Pu{wAKTX_o9Qu3siq$U=YzXwMQH?5_f7y*!`C!)<c+Cf<( z(emZ~HW3EaO$OIK<9;KR4yI-=g>^8{qRj;(9<?fQniF9keEY&2WY%pl9E916^m!C9 z-yAfWeHRya=Z{6B+IM2|gTG&4-O}t86`-B+m6Mb~U>Fvz>!Hj&YK=RlD8M&e&4MC| z7O{?u6PUIRIp_yT<8#FP&~5`I&q2Nl{YUi%n-6yTFN+aEBh+-=mx0tZHsLF3&=PE2 zIeipJVY6H5`HSs1!_M*JHg}}#>mjHqJdMwK0!W$HMUFQUfNJprun74dHd*1&#(%YU zxD<lXu0LyAvKWy8@Gn?=_o2qms*?BMZN**q__=j{_Ll5RtB8&*YC48V%BvW1p->*6 zOzHl?<2bn7JrLFqCS+29W@doNG^}MMvjfCr;q5BJgoVG{`sPXO&s8kVC_%@CT-aq3 zpmlfyp+jF1ceV~GA;CYU4M<o#8fQyZV$R356&`=hY|FJpM5z;B!8Ql+%vW4#OJxaA zS4yV$t$83>y#ukXi2w)o(e{GWuKgOw`8m?EsLthh+SRtW5vLm<U3PsuZbA=Z>2r%J zXGknFuZyLK(rwOHjvclXOh^|YxRU6iBO&q+tG++OA63?4G6dr1=#L5kf^=YRsO9pG z)Ni(xET?+rU#d9^pg$gZv()CHsbwiGM9@q^PSNZ*5BUmRMZzt^Hsu_2>)u2m01OT| zp0DpfM6tYAIgYvmo~r;C+0eu8bq~O_+HnOk^Lsy%v53eYv1VLlz0Ao6L2(Pmcj<C0 zt3bpllO#Cm(CQKd#NC;#ntO#-`mcY2T(9egK2RFHul)dcEWv={$8twKEnGV9gUw~E zCt>ny0=Z(Ve*RppGRw&leYm$wJYMRn0DS?0Zp@_QulXw~!w&hIOh{uZ)@-uAuyg|O z;b8xX=_>0#MJ|5b&i{zj$!Fahx)7ajML!fTTvr)1{T%3`+_ZQDItt$I%m2c#+gakr z0jU3F@)wW%y6hjN7A`yzMrA;^KWIrrd*(6ryzl+r(RUnCz5Tt{ok^C?nXmUgFehD^ z9`5O1@y5LS_%=e++2w)~pZA5Up<N3oh=8^QByKwJcg+N+Dsd8{Lp6qSy4ZAZ1v@b` zC#FIF*oeOQ7b)<eMJyx8=V(-PK}v-_y|HgHOfH9K)&YGrS~_RamY9gzB1Afej?_`Z z`pg6>@1==~n{QhIXG1<7pIaxUIT662LOaw}o7Ou(AphEmeEyStDqz>QA<-z(hi4K1 zRmlJI#<=U1uf$mms80yGEqswNM+1@XRO*)qZX&UOrz4?lV!Hir>PtQd(HeRZc?1V9 zWESh@Azmg=j>%+BKD8H00KhsCvPtgj6H|0<s0j;11uvB4{C6Eg)Y=RU4Q=zjD~~)u zt;CXY6q{rq&SXNA49%~Y3^*ub3m*&rhMQP6yeK+XAsPDjs}N$ErB<?^dt#@i4KNz4 z4Hg^PXeW&`D3yt;0qGa^SI>ZC<e|wA5c-OHbw|j0I<hqL$nH}IT++mhuN>~dWsZfF zCvY+2*mAf(?eDL0(^z?5ocE1wKoXATVHHqmY7rSkx^5#3bbKx(MOhRZ%O#ZozUF^j z;a|0;^g~xz75{@xKaI<SLR~JnE~;&W5+f8fC&2nlg8w={{hOqoEc*EFC86LPaN5Jt z&<?>T>9?Q0xql!|OZw4E)+na_19i;NFGS%6P=#}GhA@SAAGMO|or#u(0!i|TWH9#f ze`6xQF8e1P{FJQGyPUH9)0t>t#vy;<@aw^vkd$YDx<gqUP}y;QFa#v4rw{w3YHv2| zcd=lPRX)J#`U@iXBLq1$jpUUu`7S!6NyD6&Fbs5<z3{5*8247<PAQ|p&QW_fASjc% z<AuQP3)sqvJ5_W2;sn@-ocy0KXUi`kIV=+wz!K|}sJat@!O@py0No7WA!kxZ2q*#@ z5!eGdI@@)}Gr)0*|M;@28!{3bH~n3v_lJ@kHj0Vk|5p^_cvKZe5(U8I=7(@x0RO;x z3o$H!SQlH@NQGeoOzqj^-}d%*e%5MUVe#{C8N|Db5buinfP%s=oDglS;9D=hberq1 ztv5x`(I&`aZu<6U_vK3@q<>GCtlX@W2_VL38M6>Cu7M3~H2(-Iu7vgD5=LxzVxw9> z74J{vS@V={5MVLJOcf=N_9Z3VOBGbA7W}O$81fgbKX@~HSs?KDW`|9c{80vHzBYMh z_F4P5@vIme5=R+D{7+Wj%?RVr|5eRjc3>Siv7C5jS`M$K0+t~!u!#{UUl)~KMiR9u z{m*e`Eg}RaPc>2<8yv9t{%|b+>wkYR$^?R2fps`ifSUtG{2!bE%~Qq&%jLu_3UA>} z(|g!Yk^Ik3wZ*(S6fEw&*+Lyf{_C#(2LnKMbw(n38EFJ8g`a<^C;mwg0N!?swh&_i zfR9T#gn%aiUSyltU;C@rJ-$ACsS?{JGv^m-@L%uZotz2=^3(ts-S-dvy463^y1?vX z(PJFp|9NTN-x`(wozMScsbUT2U(!(j#N7WcznJ-Rf0bzM{#vd{L3un(=qKzOdXEEE z^MUZK((#4qj>wN~#=f$11FI<(98$ZlWRr>SZ`M)VU^|$}Q)oZXRUnez0sgMxWH=!4 zxWx2M_QlH=waoOKHS`<C$FqlEuSn^zh)hSPE>kMt94<#X8q{ZI!t-EFy>bTmJpesI z(qlHrS<u6(X)m|&YBrajdn|$ZkncQce3ZGF{esp1?u#3bR$P}L0e92MKJwKSz{&t- z#p&|qdyZ^X4wYOZJRTu&6P}gQt{dm-@!Q=hjGg&+G}Q7E(q!Itc4c5PRe9?Q#YR5@ z`ngG>O8DATJll{BY9W;ABkYw26r;c-FM<soPaIUN41U>XGu<yMiZKvuWv$EvSF8j) zgUhbgXVPM?df-nFQBDX>j#d>Ihj3jLp(~JAX!G&V#Or+i32ei@ZO25zUv>o#bMPf9 z_jL+b*CO{DAZiKrru%gV5|gh^M@`mdQ>;&IHG!XIzGv;B<!Js270=xc3Zix|G{tyK zEV&7e@Uy0Ln>Ep!tKK-sulo5p$>d@`R;ECZ$C>+zD?gMZDCv$5`^Jx0e_h4GB;}gn zSg@k;%n4$I5{`53NLQnp0^H7xU$^#1LO9cGX!5h1Bc9!@zGn$}E2@X^5fhCsNP5v6 zO-AxF%IH}TlOH5Ivs_G6>_M)go2p@(7|=I!qxsq1&%mafO-*sHye@d@_S*<Pg66R1 z=+0Bq78aR9ICt`Ao{YT^oe@ZW($jAf^NB<>N!VXs>j$I|J)s=EV*Kci_%T(C#$O}x zzgw<Swr1V?4Td9dT^{KLC=&PfU7?DS4p(K1i9?M?{T_&^z>i|N+(Uk{9PMEcQ$|Mj zO9jK%#GN@ir5E8Yg5?Ev{pr1?CJ7}xB`Ia&xz@ZyKSc6M&M4jvwf1xg7#X9}?qAZY z1luh6ho2#5doYwI2tTaZ{52oS!jj1|Bif%W-xF7P_1`?7>cWgqJiI0pnOUHjWszd4 zc#-nC=waTWhHqbLlB$Ub_mX}*m_4Rb29abXS{@U3^VnXhcHrrp$f=oZy4}xjPfPjB zMr5R^NIJeV<%UwYvvRSBB|2MCM^mC+zLI9iW{P<ChV=<IL&@8M9;-1B94IaC0Nwum zX#DS{i~X`?p3zGQQO1z&8Bn6?7wXS^Z$DF9Nkt6Xx_7+^*Xvz_m}a?muv$}OjV7k` zXAV)s2gRKu^DP2mjMrbT+`ZM4w5Oj!81~j8D~g<)ue@nVhHAa^jKY0AHzcb8{FMAD zh{d|03&+|c24ABi42RDZgHqay;{e1tj-eP6zaF9C$r5*QX=rQD>1SuYjea}P^9P05 z;g7fGUYmq|c4n?-vhHm%5$y>aPgxsvQE=kd`tV4n&FbOB<gKa*JmV)T?OWZ0tl~W$ z!=8OdS%HJat_7CJ7puL5+E(@Jj?@$FK5X(Aa*hsr>7Il4rnc`aRF~wBzk{Ypx^~VB zRb-C8*Q{87pnWxnb6NAO#>Xd{*iXb?f2T{?QfOKr_S;pVCJyV-c;NXd$E7RSTCyt; zHslJlrp(71V%%K-8F3-A6)Rw!IDNOvtC2UZOlb$1*5$KBf+Ic#$k83a_m{zani}(O z1D$J$2EvokhViz>CdHPWuXN=oYf|8Zr6Mj|Wu7h(hMGy=$Dtc^-Jk?s<qEFDV!l-f zo0ux^mf<=Y7wGO=15tP?95cD4YQhPn>v0jk!LwjO`Ymmm0+_0?;mym?^ByUZ>6nTv zr-vh)H3OSJDy$6fpq+Qt3{A2>7fhR24@-cc<vl(YE-%@%;)KBU<KiX+$vVar%u;pu z72KZw`ZOw|D*?s4(z_3#_djmSIHDe@?GN&t=njaQ``4Sy^4Cmlj$x<pG_k<UrFz`k zL@6m%r#kORwOquE(<Tu##$w!pq0sl(9%tI9g01j%8P!$6BDsXs+f{8x7JiJX%dg_` zSK((4grjXU*8P9XD4yJ`(;!q#?eXNDtJ6K>gRys4*90A&FEJaUqK{Yh;JJ<Pc#aEz z6B=D&oq7Rl>M}tgIy#m1gn5TX?}n`2y2&}w0b+73u3udSGJ9RH)X5~UZaswRBaU{) zJjFNTs!Gw3O&)DM^YKwDg(hvfKu1fLs&RYP_Vf>GkqI(`e#xu1bL{L562mX85UN*+ zu6m_?DyE)lfJDxPudn&)jzRij<FEGc$xOAwxX^D|hweo@MgQ28fR<Rla+gyU($z|= zdyg=ulZ7s@LN}`TIq){)MV!p8lbB*e<c{}Mgc@A<gzqFfLB|E(yvF@Dj^<=qvv9W7 zy@BpWa3k`>5c*2&eWvz!Dd08R3TizWQs6me?TSLVdkQ&ger}pUt$U>IPcyWqdqKqf z*WvJJ6X8TEt0P0GR&U?3rDhqGxIhu41y$5Gl$6Dt0uHBaY$%mwnufc#RX<ST16)tA zyV5{bC2s;wob8kH4#d0A!0S#iO!9t;`62s)O1scyfYT4mF$vH?{ktgg<<2c&ccKuK zA}mZJ_c6^VqnI!3T|7Y;u{g7=rcmWoyH}wLh%ctxFyR37T?DbVb@?_vgV#P~BOz*= zq`>V7-&8YEa)b*%3Fgs-OnxKn(dG9X-o$&s3C~=+HP9iKyk&MoJmoBHQyTxU)JzSU z*PGTz6xKV?{0&CTF$|5<8%oXjD%X?MNB&8$n^=O~8}w@78&|hs0nP0$?QpIx^G)G_ zdE@ckpT-(Cnxve`9aX7D6%O^E5qdawJbEt<%Lr?@u5#p$4pmTHb+g$Q`5Nb3oHg#Q zt;9G|j&g%44PcN_-P1)nZWHvLdr!uo?y6iD3ulgNL>~6x6fQp^@U0&v$)_>m>~1n{ zObA~|9%UOd;_mB}<Ak%drk~j?5Z0S+ypya)Q-^`}wI0u&l)YR@Hz1GY@a=r)Q?#d& z)ql&H_=0j^)at&(vA8zHWFLsY;K70NJ_+D<&42H>J%GwoDiU^uZ4E+k)7M6|&r~{X z&b0gM2j~X~l}v-?+g-+TqXM1<2!*YvK|EOQ9od$MsMuwbZ+JUBCwG^R;l_t=j^GhE zt`$+o1by-;w}Ey*rR2k3z=}s~Aiz7nTyk8CcR_ogSJcC4qIb+I9-TS~H+`S25ZoKi z@J`yvXmF8~C<?}{$0787CyA~TRMx7o<CqG1k3imBKE27mxRaa;$Y9w9RyiI@c#Fj; zi;mCQ(1<S$l25Hk8!PhE`1TLw^l(33?L~(7JTp+G;rC=PbpPNv{H-Tq;c05=r4xkj zHTnik!#j2gR)#K2`bPzf$2d>#>n*IwQ{}g=+2Ka@IKL7a^=TG|pgNYfXW2!pqXz?y zUFH3FL$_t<4iFxgd!!|wSGyL!=DFV+mV#vnJ0AM*peN8gdJKks3T=-LWM^+vlqn>v zn<z)`inIj}H_Cb$&NNlZOGx_+AkB_W&cgCmy$<rfZwVxWaje8;cW*f@=rK3DWlfC; zCZVH47cXNTl}TxxBDmvfC2u^E;QO^RKj5yv=`exF9cm(SB(~!@d(gB3PZDYD%+0K> z66#Xlo-@q@WZkZTf|3&g_TvwqPKi8u<+_h&*#px0<n}d8)7a#V64{nEqm?N=j**l> zo(RTWDjg0bI_!D*hD+2?2^oWAmKv!rrh|mF_bmc(&(_+eNeiel0KDCr+8rLe;EUH% zdFKT)!SUr6SF21>3|+2NdL|DEpErB`m|UnDsf2MT_V#XcZJN4VKh~(b@kT4vZuR`- zoZWr&Ti$n7bcdUvCVFf)WG3*~yu|Mk){&D_P-pnGyO>lO)`I6ot-9>$T7s9qlG=|F zb3S5<7MW*@pFI0ax7L|{%>n%3bS#xudT)*M@$plnwc3$E<U6Ej)R~}ofk&x|R*B4b zD0~V{KALgZsy>w3ag@4yggcgEHSbAucV^PI^g&I9*bL)3QeQrB=6UaQj_HRTq<*Xy z+$x%*-%nsS)z4Qb`qIGihJte`=TMeS<j>~pT7jlx#AE;Y#4n({!A`uhdK#G$L-O>v z58tczUzyYvA?((@g3R@B`#^d!v+HxuptI@ct_Yb|KM{3TZjYvBKN4;`_NHOfr|Ii5 z7QB5VyA;0D^XlxqvO~i|b^mO|n(K#~av%M~$`4>Xd-YGzQ9H<%Fpt-hnw-ie%Wg^M z3&w2@4{SPOXNKWzivkC;Mc?3U&kE!jm`=atrwx9>_?j2vBGkr4p47{`vL{ZqN4EON z7q4cYvpB?!1&f&uFP=iFxn_qK_is>9f+I$v2!l_(c$U>ZW)nUhhT6P>6Q+z7eb$Nh zRG(VOw%@yWe|t0XTx5#Op7h96rw}9z9VK2p8k;i56S9{9O}QRgfVb*E^?v%Hmb>K+ zLKGv<`7I_H%?`}^&g1;VIN$@Q%Rz>wdi&Q_#LYZ}cgw3FMW(bm-cdmn&c#GBp6uDt z#UTnG3U$}o5shw$AcST5L4bpZTA;Jvxlmd=%lw{ZFt=;=mynzCKXbx7dlyvqI9XY^ zKN3#HsvJJMMc*x;`m(ItqLs^Ld=zwFGp0ewC=eVR4%zIsYJ;t*fBYPYZ!yL<)AF=h z$ahvht^@}$C)@be>^ge`(}@^OVw7$M#|F)k9xIR}N+qvS*3>QKEGt*>>N717Li=1% zq7~z+5gt44O}c-(_4ZCnDMyW9<FWhK{0U%#DkJ?JhnjeG+n)*sl=iPIZQxQ=!mZ~a zraz6(XglMzEuJjq<m1IKyEik$I&eE~%9REJ#~&8uFE-X>M-4U?DH8}G5$kwjb_&$e zc0%~GzQm)S_KM}DaRkx|Jlk$ilF=;@Ak?0_ACIExr_bGlgeS&#wp_CHPq8AAPOJ;P zIwerk^T>#!)?W)sKMfNH-O`DF;N~dOc}=l!1ybWE?RBrhQD%hIpG7#Nwv^cK#?~^Y zLqn#KsSRAN(uc$Gc7;QF&v?DOf>qFY70ue4HqNR>xq)fdPdQ6e@uuWCy4O^k7e~<Y zHiEO<o-t^HW0#6$r1QJG%66lMNRq{1g83{rWfxQ9sc!Kw85$b|yuDMeui*Gi*!lcp zj&_NuIb#vCs#Hj!lBwO%oozc$2S;x~`$d3_-N6wHl6)c*FCI1(^3L8k&GfF1`cCK( z-$Nu4c1?4%@!7S3auYZTQ!AO!hP#IhS|BJgnzdaVs!Rej_E_tRO+~#T63k|4njU(8 z!2j-7KAwAfqj%Axcs$_%H6;Owd{N-qqG=VJfBX2H;X*i|FGV3n1N!`oP>LpS;Yu3b zAtK|OpeT)gVf+*K@Mq(8n5C~gE8rzr2R`HxIY^WdC#`|y)@r7kmXhQB@44~-h(&>G z#<hr~Ttwc+2#iE3QCBaRD$-XS(Df~h3clUBp?K!qi)o=umcO?RtuH{pN)M$V?169V zKPY7w?rEO6GN50<l~_iGQr$h-2@49-q!V!(ZtdT6eMHf=SG&md0AiX%HZWWytVF}e zZKEuz_6mL<C6&cZyoO(>qqpBn77mxwzM4_tacVh@r+wdcQSM04LtRf|8wWGtsqT{W z7G{&8wu4N?q<o!6VMsiMINcTjbseyAcHjK#vpek@q7kFa7(ylfmGwwJd!Ml9C-1N7 z;2H{AklGpd8R&q-q(_EZB22(^uZ}3Gp_nj^4<Jr({GPFpqq%5w&h+s)rDv33^>+?# z|MthDs5d%AD(`OTsf&9jZS`XMhUY};qjmQgly0rB^?b83s4Yl1;Zurt54J6I^%8YO zyDn}wx3CnTMAZU|dt@2`u)P?CKsgC9*oNngzI7)P3J)4EM#(EK$WKLpmz-8KP=u5L z$BATx@WKMFgvrRb$fs8<_wlv`5~Y_w3c?C)+-CgCXtvI@%~m)nsSR?{{<>@@`(es7 z$fw#q6%=K`p&!$}iZpMb{&`A34}>pBs^6QWbG`lkDT3?r^tEG=Aig9%=a&sY=>6S> zEgM|;;Ea;+$%s+S&`^sZ9S}*fao%v2Kq)F&B|-~I33HgUWydCsFyU+C(op<;rT45& zR1m@)eFY3G|2s1tV%E%P^gE#Dnuv%gAyzo^UhX^_yx9C$IOir5e`r$TTh(v4hm&h? zcI{|8*5Yf(RiZ<uwl?h!>$QpJM{AE-r0Uzx=U$G`G+U46J}2(v;w=%aY$nJ=Aq-() z4!j8+e}aMtAJ9E-``f-2-efs4`LHD6k+@t$_T!B6edl+Vk~E8$iY=Z7VQ$$}9xv3p zai{DahQTXLj*0N9ggxu-tt{be2S@IeQ-$E3Ol?x1*5bH!ad1jRfoJZ1J*I>cN|kIX z1%XMIzKkW*OgNI$sF_%Q$X}1>ym%yb77fS&X}&3~-+`A*h3HXAG|{XapX;7oe7=!# zl^i0x<^|$wco1?-rw6aEir^R<7gDDPapE2*aJCB`2dyH{%|7xfUt0{Zt4S6+Hk}=9 zd1O0>_PRGd!J+Tr^z1uLql74@O*9&5H2-49yxn1;R;pL{-8&blO0h(A<<*G6+S8AM zU_w#tBouc*_9JCc7JDkUIQP|wi4cwBcMmDlGJ9BJ$2oOZ?DSSHwIM3=Mf?X`ICD50 zV!^9m(pPai_Lseqyu{k=X(JbI4g@yZk{=<hMemiBb4+ZBt!yo@ZmWkO+naRmvYUQ0 zoOKi3cm)?5E6z#d73_tq*hlA?x{94U&xNb)GVOSW!7aj;c(wB*_Knj$*mn;%S2jA6 z5~{8mR^3zknJqxcbdB5k*{5)Kag(+39wpcF@z0oAGLg#fA@;x`b#qBN6maJd_Z@i- z4m5Kt%(IEaZ<)}MK~UA~arkodI|U6ae5Q<m*uR|$B(}SMI#>F+%ELt;$LC{WfnQ0^ z1O-d=vGe%}Wt>jd72!RO@L7~;?1tkCCYqe04n3^%64Ls4yXm-f#H)3xeag`)!lWUE z(;i(fq$kykI{#pZJ8^n_$WZv!W|y1da;>98XDM|?0dGjIi?yV2JkmJLaJj9%74M86 zlP+JYoT6>p)_v#BiiImg%G0o`Hl!Ti*`7ZFt@jC;*AA+V-#PZ#oW4<?0B$?9Ry(a_ zh-qK;XLf|0=d3Hgb_>9`b4%?Y-*rh=W&e;aU3{w%%Sj`-VLRlj@WDHh^>n?b2f|ez z$f=z?*bnWQuLi$n^1o}~^Ys_r#$9Wh*UvbVReyKYWZ-3=|EHvY?SRKAX9iyNbQ?0y zud<f-AH!3tk_CQBxAI`xQhcTah3rd=7o<-k#HNUJLvByd7RW2vTq<hW#OtUE6(qdr zVj+1kMXc|9{ZN7nD(u?MpB|+aMyi{jRWMmXQ&;8Z<99LLm!OfV)d9aTKUsV<KjAAp z9yGYnAF+rzVBUU~z~o=b)GO*2H4}nv+=4lR18Yuvr%HSxg;)7Mc&>LHFg;zv0mSKS zKI$=EIWjAopYiY1d0E3We_0XFrxkQ(`kWfy=+5y^=>bIcTBH^<8a~`VX<N>5yy!|> zPMNp+Zej5uZtHXZYqO!Tj_6@O4Z@p2DR(4^6qovr`EUf`;V#kC{#_j8o2`m>&|AKV zLMZ}mrfy-SS7N^7rkOtB->jKCKce5>E_|5cU@USbz4}Fn?88UcN92avN^^%MALv>F zniUbT;pnR9+b*ExdT7wN<w?^pd}QT-izqh~#y@@AXgLv|X;^uULu%>@<cK?e=N<KF zm_fg8A?NX-Zy1v9Y<^uMMDXl^OJBiwPo?u`J#HeJ{nvL*>&-Qj#F@Fr6UgD*4@pB# zMe%byudX$xKt11dV;+=**lqxl8KOt)KgLPJ*D)ducGfVi=@1K_Pu9no1xqDkL~1Tf zrb&hk5~9;%ya{A3N@-7Q;DSC%yJHKUv0%_{8wE5HwCFqcE-gQNuEmRba&s)gV;gT> z!`EZRkn5*}>u1kECOx?}kY=#2(2W9b{86L!clQ?LQuJ7ceYU3i^*keAdhsN#**}I0 zY%i9A7{7g3cS5$abnO=3yy`}((p^HaeZZj0Q%s~rM!MxidJ#At<me?Acu@ba7j4!z zUI}v=ZG6}l6*_iiRA|CN-<6MON32$V2E_DtQl?E&=bG_B+Icv+k4C;>vIQ684?r>k z?``YMFjnC$KCvtzEJMQ=ge7#=q9L-*G~r9atL|yNFy4)mioQe3K*vE*@}+*=$po0c zoGVR3y&mmsYk>&Mc!MTiw0^96fbGXpyXC{RnL}-<De0>MYlQ|aDO$QQLr2VM#4s^} z#oJC#K2)+Mmm%SiCDNAHG45pCsN3~5YWvn~idqDA`;5@oH!F<n6}g?_Q=lU;MCWFp z4+qI2s{2jLi3M*31F+`mGk&ePlC~;X*>I0}#dMe4@EjtAhZ_B4;<9n4_=>9upYT1< zobbiwSQ;A8T>7aYb4n<D@bt*mORDOfo{jSkLe(DpMm*XWrquBGuC|OK?fOoc+vg!8 z(VExripH)q^{$%TyszNx79CXbfi=Y`jJfcTA*IJGes8LzZ%)-Fd19x)<((aMTXn3x z$nmr(P6Ixlc1zvVC7}xuU$I%gP{(r(n$-PAt_L~}XH(@IMEf3Z=8toCoy*!na^3@a zI3Q}c<Mq$pqbEbY`ecF9gx}9O?}H!G3-f;PepKyr#TZzG8ld2>p8R%xlM7vGEl$=7 z?eTlj#f+*9Bj@HHUfM3W)Juo+O0b5}s82*9zvjT&uh2PN8=7n1o8{t&aIXp<7mnRS z(Y5n@PQMx@XRA-P{)Iy7{DuE63uXS#DP9fAE{<F<5g4HZW^CR%aQ`xU-0J5I>exYF zYv{BPd0qv&!7zO(29@y;vYVD^Tm|uUILw#BYj`MBXt@nBNys{dj1QHceZJhmL#k1C zi`v0;cBI8kYiBU8aC5*W*8QQbiHLFGzA@vj$a1Zl)ai_Rjc^@tUvr^^kFMI@zVjvB z^D{TCy0LZkLW07A$L|EHF;#|ytv)+SqNLZ7j>63^RN72!D?~pb@Ig0Mz9W@6aAs_o z*y#xNUv-u*8#K(O%T23mvz{(}No!5?<ru-})^2O#Kr(`i0qSmHGsvU?KLYXHdF0ex z#Clxy?KrTgm>9)0)8ruC6m}d9_Bm+5{20W*-UM#D7{iSxGpV*maxf=p)+QNyj#7J# zic=vm{!?xp$b5-8mD4h3i-vq!rP+B<2-gN`PY}BxW9tbqez@Sp(r&9xkRkOvOIvtk z=($f4GLIt2N9T0+8n>gT$;6G7XO&;lsCw)5Thc2?zI|sJNVDAC`NZbdg1Vvi41j^` zgLjSq_fl!sq`KnbqicUjy5dSRGxAA|$_hjpX&YDLwmrx0%>s=?6bl#bW{G_EiUm)y z!Wk|5D@jiVcL>$`frd`@^*b*vtSGw><4aE)I@JsPBORvMkz;RRNnrZSQ-rce-^u6a z)YP-f$z$t3$_jwwR2kE+BjCOKuw+@S-V|~?Q&3K%$@Tm`3(|UJp1ypSbx5+eO*|SA zMHa~dTeS3_hPA_z9zrnWYp-2f9i~=iYZ5d~Shk~%^H-adq{h;82SB!+RC{Stk0qT9 zV=Oz`fin44^W&?h4MLTkb&uVt_&XZj!R~YJ3-TA_jizyWO1B{f%Fb@~4W-5H!WDn+ z^r%xc+iqR75R~YEv-Cqu)03szZ3k7>Ld>e;(L>E4<TbvSl%RvEc+aI?K`B=|+j>Qj z6E8CUQI+7GEhR7}G1a*B{L9G|{2|}xB>m5CAoQ-;XM3-nt>kQ)a?-2hxVV*1GiM0L zaY#EJD^FHEunb;po)cMZM{yq=0DMfP1NO=u(5!F%7=<fO5`E=7M}I2Vhbfr3AY{jI z-&Q;!{6*t1&sBov<uu|d?L~o^_2y)NiW9=_`C|v2eRg~PI)r%m)rPR=<?XSX32yH` zC7e9VT85AbsljpI91=`uiXCV8`VlFP0o~~cS^Ged*#)5X$y5IybHd(QxJC)E?gs7w z)G%_9y^^0aum7f+G05d?;bT#Q$b0n-F59V4Q}I5Enu=<Nw3!|B*-hRCGWyqJ5D)e{ z3;yABZd8j<8m@Jxqm9HlhiZZN!{s?|7xc*<%Gtncdr=5ROB&R$Cl{VWO}cU7u(i{= z(P+#xOz(Oi<B9qBg8+POfGXqUN?L{LMQv2W5hIeq)p&)Yo4>U=<zX^Y*HR`i_mM6r zkcK;x1NV8W=iM4l4KEwkri7hy%3i$w$csL31~eDczNb;9OBJ?)US?zu$v|nYr9Ot% z(?AS2EYc6cca_pKRo!S;9GuRQXxJqkt%PD6KY}f-mGE2Iv=@BZlswa<c#G~8A@su3 ze~zSU52fvQK0ZZJQt4~$pev}4t*zlH4S`P&yQZFFzNG--L)z>>gYHY3NlnUj7<W2$ zgLWL{u1PyUDgENd;|(P7$-3C{fIg6taqLJ08nOKJ431ph#(48a;JT>o5(lObU}$aT zzj~eEQJ3Ho95>9fvU{p~acfb<R>T4L{gK2k{Qg6ny$Z8O;LS%9SC=s`Qoche?eQPg zrALR0eWzSYlhi=?(bcuNqW2oA^>F!xkbSnxLu!-5vdN`jmAe(DEdkaN((6e-*v200 zc}z*iaI)!p?c8YE68jo7@bI8TlJaA-AXT{Ct;({5Q+Yz(5@KbS$ZseFF=tB50=w&t z2fHNO+oTM!2L!9*lV0F-<4LdcwUrp6nrRVoh#>j6Cm%nQ$)UN5v$C_{k$j<2G3u#} zA&u$OspHO>twdecDWdPJ=YmUjrVPA$l=FP*dIJsIcZ!gy;xe7rO;Pu_W;MMl;k{&K zT8SnAoK@pO5z~*iLzRPpTyMw#4c1I?U3f7C96#sKZsAP58+_m^vgk&tua291az0V# zF@8_G?^EZ^3onXk7mT~4#4=lofX%F};Vk4iqkxB<(av)R%zNa)<2#*<jT~2wOlN1m zu9U*6RoEK0a6OqQQHXiBCcUSUI-=;)if!4lawrE>DS`_(U8_6Ajz+s{y8HxDcXEy% zzR$bjracs3UWlgNfwVs@=7$bCACl1KK@^tq>mScUY<F*3`~0ATHte;~f0T5>px#mo z3LecdH`i>MkDqLIb=Gj1p3WwrqEs9(sNsp(&{4ncxlnS9J0ANLFydKI1Ls=AL+@PO zi_OA1Y2yTqNr)bCY4@9V^nPA+K|OfW3KG*G(rfp3<_%rD&ya7m*9qq6h5WeMuj@sf zd%xOXb9S~;Xwbt2zBwBSw|C}M{!D*C?%E_%vAEXhnRrwxSYayC*_Php+bp<8V{j*u z;NC%>!~^a7WxR>DKN6U0>Gd2ZRW0)<>W`HuGq%2OO{Z2Z><OMB-7avNxh^&xpxVuc zrrZ(1-9JklKW!Mw^)((R-Zb`}5hlF0eTIzD#_KwBr0E;+Jjt5*P=UWtZBM55zBJ<P zvMQ!C$|72Aeqx`)LYGGu$!6tTd<F%)zUyzVzZI4&Gr%o>V}SbcF}#gx%E*67syyiM zXl46^93sNayCr3Nr!!`X#Q59F)7ln+59NKiCS-~XRR=wHE~fk_&WOiyADLf|U=-L& zpL6ZEBs4*>+<|7OeEQjB95Z&;_<%aC0^enSCu53fZ$M_sGc9!&PVnfGPVHX(>Z~WB zcHKFFxlX%-7?&MqC+T87HImCt$pz&?WKT)c!gfJ&^)C6`_MJmv{~I=q=R5XO4Hslr zlZHo7Eg%|kvhN$~WDf7WddzBgMbG6nSc^x%i`0B5;XM(no>Yuzm^#&FBm{iR8{tvK zqVE=oYq0)!$Dvu9<myubS9`Bfef$gGM^xgXspS4Q>4mCt3L~sT6k+Tyvvi21pMFQQ zIf}6cK5d}j<_k^(clAXad(U+4pc@-i>q?9&Is3ASaeXw-MsEod*SLYulkGIxYWfOF z*7%R4_MSxK8X7Cc5L^jr00QUt&-yG_l#=|+@>t`m2#~uo4;f)kCeao621rG7YlVkm z&>o88w!rCjWwM^37`WTIeekRoMMUe*har1z>##%?I|(J$oX~6?2;HGtdV<>iA#3|~ zErr{nb%>hRr;2EAT{6ezg&cVBD3o;6e`7yfUV?x&NzW)aunn~SepxsU<{|qjckJ73 zp9k|5)@{kxpA?rg98st0nBbXA=$H$pBa21hJdizRF(F5kLp#f@Co{x)u99cj<e|G| z3y&gJ1nRX-_E{Z_^&;h79^!Bn<Bu$M%)Hw3sPd(OECMdwDd3Dl$~I$@D|zoe@+m32 zzR^|HN!Q85-~dlCW;xM$cJN|Vf1xiQCg@g|FL!NE>Ml(^aIRW)3z!!?@!RAwR%*9t ze?pVC*DqoqfH+LnW`E7QBk{dD4P2SB3^u=CLfCgiSkI2Wey%~kWu7W0xPMQHe?+F+ z(1pZtN3}kXz1jKViva>!m846RMDpfotmx_Ijf*aygqmGSq>q%<Xc*Z0<|BVI{$B|| z<_U8Cm~_*`yXm5z79gGuXh$v&i;xF-lSIUa)F0_sw%Q0__fN0OKFSNzzwhH8Hl3qM z)TeUOOoXKwq*h>RDbkF5{&KAT<df$W82@_;Ez;O!qi(^D=5Cf5W3_jtA~TET)N`3- z>I+|IKs9cQ0EO)|)^m)_%V>_)i8Y(tk?-)$_UuKQ_2Q-cZhHJ)=?+}A6+7Cj!aF|6 zwL*@Iw+$Ln*~KEr<{(BVrfP8gvkxcFT^h;PGEM^aL9d2vdIhqAk|TknOj`UfA869< z!c(-NsnCzk>|D&`1(Syx(GWVR3XJ)98Q|%760!K){e1rDrw!9otHcM%i@>M(e)iY$ zXZ+OiZ5uFY9kzh`6&19^|LRHbR84pgv3OGz%(xAy*^^(&?ueJZ+mzgDxXZWX1?lr0 zn*iCazZB3`h{_Avt-&BZ=*;+LKh;<CvoAX&oSykSH)Etlam~0QBq8KZ=W}z#s>owF zda3?tA)JwhYpYUUHBqffS&O)%#LhktJd;py)GjV2Z&p2d_P7NNwZAyqk+_|JLL`%+ zyvHqUMUFB=l<W^FTP|UEciT2-Kl?~JPU0l}NLYEYWQEi{8J1pCe*>4Je+d(t?T~QF zh9MFKJ7)!)R$@_ijH?UuU{{{((-r!7TU<o-wE?)5lS`7l82_7n)H~{<hq(KORzO=E z{WF(2*bmUo@}htHbqe+-$CMzlF~Ss$hUeF5IyyKcwGTqIt!xYO4D%K$cfOOM>i}y9 z2<bLn+1fgL$@aW$M^}AVN-{vnBrhiMk>LDp=>hYNGbEV1kq^n@s^81<{K-!EIq$rD zgUMS)I9g<XhB?QMOb){p!IFEXU7!5qX$tbR!0MuwVK!~Y&JJ#B6O<6U<0w`i#6Kfg zrFuusNR4j?0$G`Tnu~F#kU}f<{J=eN9bJ`3647pZ1))*$T~POjAiY+=11r?Q9NnNh zGsZNyKQR=XSg@G%7g+q!rL8yf>l$Z(L@9SN_h<`c7SFCt6*+P@HDri%Qyf&Ilj&!3 zOD|e;mriTpi$8eV-%;S6eTh_S3#m-RoDYg)s$F5fTc*WNl9M}VksZ@hhe+}f<kZa~ zt@IzYpG=d#I!I;f@_zP6!)W04%i^JuTb9=j^P5hal`V3!49J}tn>+Z`=B;P$NS|v& zXiXEN4x}+87!xD&f{!yL+$DA@Lubg&sV9u*$mSCg1SDaFedoD<+j+1AsT6OL4}O<- zk?TX<1H(6d-BLg{Eu_+K_OPf&XNi}xt1gj@G$YLh@9b=k@__YXQyoGv2H|un%v0+} zfgI&FtdNav?;Xcdp*Pb#6O|{v9_ft>yO<hi-@Vp5(!$r{pHNb&4B2U-nCglwCpD}; zXX^#cE*gg5&b?-rB%C7t>BvFwU>yn1JLO?+f5Va7BvA$)1kK72q=ILncghpg9kYN$ zMNhb}0Bzrt%fhBWfH@MMAt4xd4e#6T^lB8YAc^Vetz+4Hg+IP7(N;y`>EQ7@*eTti z7QtKQTA*eUy=QA_JFBXZbbF|aGOSzS6rtrU@6ZSJxe@dK*m?`UCcp51_@k&OA|Qyg zG$=@S&Oi`}iAZ;YbT^ZbP(r$yg3>)YrE4%6NB8I&HCE5m@2_63=MUI+pR;q$eVun* z>mxOFxx{S5t2~J~l=Wdu>T;mvf$ls)qCKmm!+>;8ow4H1Wa18(`N)??+oB-n$EJwX z7=M93=r#tKpo*T`Ms_6uCTP5}w^w(4*^FUK9KVaE0N&3B<ilp0LS_wf;~vlYidLVJ zocjUEh8v@M_jOODfB!b|=gpEaIP%#NF4bpp*h>5?yWEEm=88kJ{wgP3GhUB<eFh^( z?u$p;AKvsh>-a{nP@Q`l7%?$)9mzwr9)G!qxy*X2L)E+z#*0QgmwnM1g}l(<aun_3 za+!{{3UE3%akLTcIOyVIrm&2A5(vkVha<&J_ULmRVWc@aWZgPTY17le@~NMA-Cydb zx30<oqAjl6>D{c(Un8qjG*EM=Qd0nd;hXywIp@Zmub!wD34PSW`Q?vV1b8c8r5<Y# zE>qw!6d`oy!Sf-|s<*1Q%gMP)(m+>7&{D-27M{pn`*kU=>v!s1T@VF6JpIL&2%88x zf<EzoUJG_a_hiq8;MYvl9cv7o=(AZxNc>=?{;zPpZQmMkzSc+jzeuJ=Mvl*a={--E z&VQ>m|LM4dU=^9Oz@NvqS61*uQ0`rnT%OSPvQ)E0Pyh|;l9CB)K5a<EIP`biQKihp zjxRY=tM^;jqe)FEjHfGGaKY7^ELrkT2-|~#oO|?5;WAtDwWR9(){`!36q7VUk5;6F z9+`>VCUSoi(`1W~-}*L3g$`nCWNP9pR<oj7irL3xFg32UK9N7c`bN6k^X`sY&OYb{ zDppOSzsJQ!xA#^>_XzRLXq*H>QK-GWiAzVCmcSbqV~4k7Jed=DY~Fe&1iH!tVuxBW z(a*ePUjYrl0;a=>9{$yFPq0$_yfqYG*tYmBlODd>FNgitwzu2(RSIL-iZakP@3QgL z*C6)4lrS!1EZrNr-*_8QM>}SZzDn#oL$S4Q(!B|9?_B(>cYMRfJHbizcEc0NQs!?G zuxBFY{WA!oJ5};I`9_>D7s<g8>t^#`369xxHOX3=Pt}_q$v*PCi$BMH+cai8RtYKG zmTk!5li-^Dyqe<OshLd+3j9ExvuW6QX7=BNgMd2J7O8^GuyLKqlX73$l)bmRJ+j_D zIkWbDYNOCW2PT$PcX$&8zDLx4SDJqZDM|t!zOy(q<4$+h5XW!vuJOOijIDkveAcDs zo*SvlZ*bT44p68HI6BH76~H8=H)L|k(=G1YmDOIksCu(2&6ND+OYcu6YdGV0&0g%= z#{t$eQBi(3O>{%0ICVB!{Dlf_bZ)K8H%W^pbYUe;IQ2?5`wH5Yv>iGorP*`H0Rt}r zwhbBZS3&Vu`k`ux)INz&ATvVrjypPO^A~<ixg+uUy_s&HL0?^|fc>s4{f=f8^vSW` z^!k6FtlqVEr>?iOrD{q}0T@h_HPfL5mPzniF#x_r@ZI0dZO^L~_Xy<2WbR&G<nV1$ zpE%y%opjiuL3-JiOO`EIEk@@1%eU4bfbYS@(rq-`FUYOu1m#WhKgyzOTw-M1&IG2O z;4$QSL23fboHt!lOXIj(9g%hM{wtKw;fI<7DSHmnTs;>vw64|5qjqp1^r0%P$>!1Q zD{2N$4h;y4P=dM0;YofG$1gERC3n04CqCSQBWP`qlqjpmTtPRPFYornj)qFQqn#g^ z6uoetz3IKa+|XKHE*S3|`f90QmRwzi)hG2VIeK}K(DdNoMSbdBdisYP#^s^Lxcb&W zO6D`0BO3C>j&(oDq~_Veu}|>fpOk2M!Pi<wN)lJXWL;}ayRU1@*M*~D?@l>Bb05Ou zd3N3Dn4)?a6_sbEIN>fgtf3oQx>;vK#4@#_>?XUwJ$A3nhnItXYqZUmk7AWieZ%6C zjgsW(DZFt^Pa1!~fRy{_eg!$A-JRdkx_wF^f@c|9sndv0fnfBgS-rg#`e3@Dy{lnE zK1lVUihVf|9~lrj^;|VA%e|J_=J;8LS8{`s$H2_A>8!q_NqSpbS@p4A$j1Ts+AyS5 zEj8WVWS#U4N6(W!bGRvzH7Ew%tkUKuZT=(T2GS+)k!LFfO~PG`xys9*VvOL*9HBOH z>=v*r?(@Ud>UM>Ifbd?BH-w^#+8C4)gXk%XI%q3?1sQS}46U>m%JQtdy<pILIQIIy zzf3Q-z1dA61wrr;Iy6uaNlx0lI_MvZ?v*MfEYF2f=vpQ*rM?&kJ=l`N@sVG_z79_y zrMm+MdMc*J=z}6Ln18o@fz3+{ZE}6+BAVRu<k+5hI<>ZzgOjFQH~(p~k2hX^)Rr#e zoU`q=lFRmI<v9OJCH88nG{iRK*joaek!R4`u3X3NJ7y&NbI`X{Z9Ka?d}*YMvZ)z_ zk!9*|g`)1#{3%<+{&C#z+cu!bu<wpJyXk9AaFw0kvqcm79RS`Ne#UJ0c^t;wHo+!; zf3oz_76{yZ1`i*L{KRct+)(aMO2Fy75Aar32;*+6g|zr<dHXJK02!;a>o7e86eelq zC)mDXR1)mh9WcBTR<h8gD*q|1CSw(45ECDkn7t1A0a9;0PB-uP(G2`{zv^21cb{11 zkCBmwLM-)b;xG=6Mz^-5hc=SH#5nGND_3*ddj2LAwGI@*epjuc=3^!0$`;7%`qR9( zmW0tbzWiU(PtUAib?NQiu52n%n;cP<S0m8a#ppCj?>J4$GT6y%nW{clx>i|PmQ{6{ zhS0sv(`V#dp{7HHET(yHUf^YUkL}dn+uHk$`bzAHP=WIg>^>1`Bx8h{L{4trNj>8! z^|d~4gO%zkLmUF&kJW&47u7cRG{<|zQPC_<%5A3QUoNsLpQyS`Z4R`XbvI=x%lB$T zv2@kt-5rkMCQ=M!HI5zWZz7^h7wx{@vr1dH`}*iayxnrCaEo88Q&Be6H~R<M#r>&i zLNCvUqPG%>Y&KXzT-g9e?Go__uWJR&c8~d4%|=9no>f_m8GQ(wYP{736+3bj{z=M9 zm>e@52%eqy3&x%DA}3O4{eDyGJQF?VpXpKhJ3ZDi%Qt>+z7^;G<N>iAk+pks+apKe z#zaX}M_~?KlrU?Nw72!X6_1D<{~enjSm)`sRE<QC`oqFx3{DD;thW1F>~5dUBZYO} zdB7uM37JqVlE-H;?&RM9r=D?(mA39xsc1|3xs6)i;^YM|59E^J_p0BWR&at}u6Z0O zli!kf=+XN2Eie!;@o@j6;Bk*_j>75FCY6}c#J9Z~PgRgaj>C@e;QK8P9eLVAT!&<C z4=`)1DpvjXE~U_ND*$&l<Df&VGJcY?EF9y0vp3OpL&wsgEw!pxz@&+wT#t|Vt6U$h z|0QHt9P<`HY#+igsx~&JmdR7w1m~bu(EI&nYc-#{``b-QVST!c#mb!RD6!;3>d77T zAr3RWho92vUes0#m1ltR9FXhA>jfWhG1b@7legxgNi+3#-w&*TZ8)w(*wHNE*wVFU z9K6a0c7YsmhtOztTJcmdUhALxFCN1fq-@+bm;U%&a<*V9-DC(IRwt?O2Yq^Uwx4VX zZD&SC%Y10L2X!Mb7B=x-76s8YzX`4h1;{^J%#Hm_wQ+f+71#u&0FOh|1-W!a&P{1v z|7Yn!Lxb%atdyR9`oYz@qq0^f6mL4=i=2vB)mqR!f*?GK{sUVasN7I~2sFK82kC52 zbW9%p^}}jdV7=rDVac{ZLd;KIlo6<12a3(e)Efh&#wdI2(bsG!<7FF`7zKoEA949Q zEhz}_8s?Ud9#3A7*WLGBWcY2Y9O%3p()D7!Q17YFK&n5h(aFt_u`jnHIE-n2b05c6 zTG9!@T>5H2t7-hkffMFiFUg5FeRQ&K3Y;;}x4fxlqS&9QWJGUVhotg6K30cyqvW5W zv%T+)XI>#&`YLZmEdnH4%8$2ue1#-^*a>La?XlH=^5M5AZ5H-n_XnpKqkag8*(~q* z=x`R_y>QKx_@wlrtNIr>#8YeQerR>t?_$Dq+(A5^bDyk#dUuu}5cb@3TnF1|8|q2f zyjEK$sOzV=61fr1t;L`b6M1q%tMamY829&W+c@9-Aom1WaM9xiE}_p2c?c+%dx>$$ zEFaSso#EIlZs!(yp!s^<CbHgss!yKdoqYI=2;WDK7o1EV&P5<5E_!L!=d$*Ly3-B- z2>0uV<`;%h4onUQDJoP}-Le*DqMN}4k@zP8rdX4V)?Yn8#Ndm2a>k@hA7VSZhR;R) z!&05gBlGN;Nk!%s_E_JER=npMQ!=5{TypYSl-)6kcC`k^LpY_EoCO)?#0Qk?SiHN_ zTf%+XER-SH%3~mr?P>I61Bz=8&0(BfI&+hRH7rfw-$F_|9_ENYlfo%C+UMARV|egq z>S7|EaZ~Mthq!JA5Zu2)=_@kZAJP&Qlu-x{Eu^z0_3LtHHGCGm^Wp34^M^|n87IzR zHhS!LN)mCts37+r6EPUk=7sr5n%CPwNDl}gZNd5+JKI&SE`%<D1AXk?8@MOHb*vFC zTQs7vVrXJ|o3h>=I;XlAxa)KE(9rv0fvY`D>5lY2<RxbvA`~iJXBe$AUIE`D)vV)A z^m~;Hb1Zy~Ea)sQZ(i6~QW^0DMd`*z&=hEN8Cipb{RK4?p(0IeVCUt#rwPkxb$c=r z<br4c2=BPHQ9^tR-?7emg)tS?oIGvE6a2Lg-fHIGc`Iox&OXDLkooSeDQkMYMb<Q? z+8~>A(ivD?|8i|696wUun4Kyt6A7|vefB6?Ke6Pnzs)2rGUbo6OUUHyUn3RkO6K#r zfJdo0iCq<rtat}_Q#Fq!<rTl3WF{eL)yA}6lZ$*JP!7_v>ux8JKeHvyz9~cS4ZK;; z()t-Y7jPeM_*~uqvIL-Yq|J8q1PHzv#<#S>ldb*T;{@n`xM7fNxPs|ck)V`01$@hG zz_s$x>6TL%Hq^vX>B|uLX#2g4-LM-j=tZHjXAlgs>2{5`U=4FRHvH=eukR^^)%n(l zYD4edJ!XkZ@nSFRvnj8k$B=7Q(x%a=mR@Hu?eeAU{?fAkKutYTFoqHKCZ$-n`US?l z`&o5m+fpx~d33WBV?DUG;4b3v#M4bH1K-E@(AkeGAXOQ!#)2oWu}_S6*GF&C|1MJ` z*xrv}uh59dacX}#Na_Yyq>vs@0Mmy9MT~De`C}jaUlM_rof0t~?TlYDQuA`FM^p$d zj0M(F5h@1jjiuLTC1NOqth2E_X5S(9NgGTf)!K(9+e&jT22>Y*&qm=9!5da!ZmpPl zBIt~95B$C`(3RmJcSifEhd#i@ycqN-DxfWaS>emAqAa}c<Jf}&Oq--wSVa`B(Ie3x zpuZMD=Qyl_Zvh>Z?Ay9ZF>}>CcPAP?;CkpW6nz9CcxtM`1P)ZT+_n$*ZBHel_jOII zwIIytt*__5X}WNKD-|Hy8!Wc%dY688&5B<LeGMoi&H=p?gBY#BO=#9GE+yjcv9}K} ze=H2hVSF0On^O7}FJ(?}1-4yg8QhkH5o{ZS^ZHe)kgeg$CF?pz`*q!eE{hNyADmcC zgHsaMK-{+CNr3l|!Pc~v{V8k^?{ES`-qAt=OuBWD{D$un|N7R_4*zZ9uSaU{rsS2Z zLS95sdyZqIG{O6-ZK5t-FJfQa&y2SqIK?K{!F-M-g`F9L>t<etSFi3j>YcrxPSev1 z`E$StKW;5$(89VW?XaTse`WmeAWW`<y`p)iE?<fy@3EUU=NaL@nDErruW{Ei5LtVf zM8B97FsONEl}$|mAzB5$N}MEOg739Nj<!nJ03cL>WWk9PaTcp)My*vLRDtPtd=9CE z9AeK<1E6h?gauMFKsu!QsPX{Q;2F?UmtaN45-svnGg$scfg_B|N}zbRU)NEUYo%xO zi4v8X^nk!hj60Cy=)QGoV*c`s0yqa)MRge*VEKR@-vVIw6}D2(o3lWkH4?iuPflA| z;}s3a&E<^@7>FGS?S$degU>%1#gh`>u#n85=$1!atvwdQf`8PtvC`&>^#5vcdRr<( z90+_A$=J)0PT_3NCtWFYv5CHtPqiN6Npj6(j;+Iv@42had}^Bm{2Gv9BmC%DmO}aj zy!LRW+JuO<<fmPrnXF}zO1ngJ#v^GjtG+{#xvmO$(%UJTbP<j8na2>D7U*444esl2 z;_`C*(-LEoC0+9?*?Bi#x6I#bbiHozZfD(j_|Z8^Lfxh?Pql>?HBX<2sea{EOR%r7 z$*RI<X558CJT~T^Jdk!@CbJ*|bx@w69w^$`zTFHU!Nfk()7gBVudro7^F7fFM7Hux z3A-IkJ|7eOCPgo7+nd$`XRtKgL+9w3TNYS7r{CjTE98z-Xg5J=s(Ne|DHW9<PL|g$ z*55b&2AdGy0;V>JXn4mQ&U`=p9!27MKMZr+7Bz>m`(<PKGiUwcfWpIm9ZYVz1U!;@ zNk*DO5_3-2KPam?g)a;D1DkKe<aA!sFYCp=DMPrJ0EvU{R!WJbVl7S0-W@pflpZjZ zKFJ>PuYyp8`Z4BFqLZ(V>WMm06egPru`}pk&_VC(1I9z-{Vdno{6O7E+#$8c_EYsK zPfAYSON0{?pS_Ar@8>YANfC|*$$vDHmEQth23Ap+eDT+Iu)j^yT3t6?Y86noJl^_d z_DSPoEw%MK3)L9cH-aCVyYE)0;9;v^v!4~4eW;6%yp3XreD)KV(^B5LdW7Jf@HnBu z(*OFmJdB}Ra>Hcap!$*TA3IhV=yVq^o5z1Q6^dcxS6*S{^Xvu~m>vzLq>H5tyiAwP zqCAyN9;A1FbABnh05H%uC@;>!!7&HisrhI`Y2Dye;u0k{x4~pE;b57}OD`?xd=B(t z@vUT}KJl6KlVmKy!Cev($L=$*s_a_ac3YNzN8IqX9$5K-_(nVN;V^dA(c1Y+7??YW zQ;#lOBW>BLwbohjT0DE?S@CQCbh*rzhUGY@>z6t^_}5CqY9$m!J@nq1_BxX6^fgEt z5IqNdRaITG@-0UpVeiBF(~1cmu~QldzIRvgY50e<&k;}5`kgEDz?JBV?j>;_65~_p z&as6y(4e;SDv>|pHf9&dSzd;Zu0Q*LaSY{lZ8HQKkW)D_)Otq45Tn^PB#HOGgGIvI zEoI{rd^Qm`Anh8!PrAEpwu!v2xdMpj_pMUah`0@#=<pf9ile}s4l?y$OlL30WJh9? z_Wj{=x8lUm-Z_ni9jrl_YC*$o%sLkQUxdlNy`uTrLLqd-E!YYq&tZw)d=}74df4kG z+b5^DsrkO{uB>q~F;)BK*L$2!C_(GUFYzNUO`yn<(<2jWyeK-48GI2*yEK(L-`j3* zG-D{#X7#PQa2ed}+Lkp8*T?`ci-3$RzUqvW3Mi73O<SBI!EG?`)dNm$K?y$>7sy~1 zEfnn3umM@cqI?5lW0r-wi8@NCmpE&F_wafliaPQf(7<q^54%jW`kc1*c40dr&kZUj z5QWg^h7?W+yD=iwb^$3(u5p;GhmCg23+z%iTC-_>VaRHt>M79R;KG^P1AQi1E+9q* zdEzigeKN4Dq0)T~S|a1?_;c<8NLyGh^(?URBJ+|UvCrW4#=i>ir&B>*?k$?O2X&+! zYFIE{uJ$j2Z%MhxZ+`ZcooV`X9D#71bz%VSEv28$Bvu9rB0-`vP5y=Zto&(*f>hJz znGWkq8y9p-PEKS=W7$$J_mLB4h?{NnZ3LwHo$Nw`3_*^K{3KSI5_mY+eoftc-g>lz ze4q}iJ1e71*nYU^@u_1WOj1Uk{h`a|y3w(G`!DwID{ZQF>NsY6N<$dFZDjtEk6j!N zxV6)%k_a^A0PVsmE-o)#o=$g~)p**pl+mOMcJT?M9y#-Ir)M9T^tM;{lIj$Y`-as# zBG3tRt#kp`<S1r(sC1F6CT5TjSDYZOj*yzjy!>Rml@S{U@9;+TL38Q!WC${;$m>u3 zh6EHMV-hC-FtY>y+YtHkKN9@2J21LC&f;=vwZoCT4Np7?DUFuJr6onGR@PkNrSo0I z^dffb1TUgNZkaw7@-rQyKd=qvJ7!^58Q=V&`kZD1+;zpfyQ)WrHfBwJqaE$1RgG~6 z9z+7UBAud0=5#D?e;=B=f3@Lu8xuL#Iuz<{>KGLe#K5^R$QVq8yCBeg%$*;Zxi)Ro zZVWNZCo0ODF|8x}=KT)WLBoME-rZ|~>9rz*n5W(&5u6Q6?TMN59XHw+BK>A*1}eqG z55>FH0d7uDVZ&?Gg$aaS^y^-pdTd4c?El5t(DYKwH2Hkxx_Z!l7-vc|!$yX&b-TNi znqAA@ebZWCi0N3Vp>56e`aqq!Fd9^dQ?j#noR$8p>;||thaK%fRBy`X?ins`IYzH^ zpn6B+`v8ai0d04rmJg0EERO)Dx{Q4&dEkmvr!+Lh#K-&oKDxKRe&#rMx9Tu2QY$v( zcih>T?7=Qw-}|g^g@xktt&Yej#<nkZ^;CnaFCI*6KHq&w3pHUi>#a8Ym33$6DP0m> zX!K66d*YKcaEXhD4)Gs$TW~7YGSPb=%taW~Y&fq%%u_@z#~kya`Rn5)0-?u~HNz~} z=e4nQ_&g}OU_8uH8%*q?I`gy3S%j_^rP@hEmqOMCl}_^IE{nFXDwjQEo%YHDG$&51 zJ;@KVAXgtRx$H8^o3>&MHx0_Io8HVl<&R4dSGBi)s=rOcSiR5?`^u3CF~k^Vf5nh; z_P89}H+I$0h;=9C*JLlkBSgLFXXduj6h(Y>I2Na}w4K_gS@*nj4d}}TaVWfxD3TN$ zyOt#NQ6unk>^*b-M&AZbojBMy1{qu0{&0eJe}>GE;=^o358TE6hxh5i>75zOzH6wQ zr18>dq9EX%4u4v`o9jV$58@8)LJ-6>M^J=|r`}WowwnOf=k^mt@h#Fz@)axuq20M9 zKbFw!bndttDIEskg@_YXzmGx7hudMeW}qV2+oiwSN)sL%!T}Y-Q>L0r;FlPUIe02O zqkweAeay>hdiAc~_BUAbF)S0b{4>r%zM|_m@Md!x)lAh`)@B9rsT~lI?z{@$)oaV) z6RMZ!o|{b%O#lUqoVM%e#}~Yxar-Wl94Ed!fw;_z0OV()SP;Vad9YWXU@KttMNQ-3 z)bjESFCnt^9Lw3(4Epu;AW9q*1!>sNc}O7lDb6(h-izoK>$PkX?KDkpdjzUF|E?fm zrT=sBx#RBkxZc@*GP9$W##`}a$lk-XMza>M0Z)Wx0QoX8<F1Piu7I$QdY1xXj^lf+ z8pXW&ez%1GW>moIY^EHsgDh<4ySRq3I%8JsQ0KNRZp&m3<^@}}WEw)&8n$zuSx$aB zeho>EGRG2x%1Teap#46#odJ1WNbW}qu&W!5#~IHHw};2TW_gl-hF<pejFV(37*rfZ z*q3lW+|}B<IB=*<WbV?W?Rph35@FX+iy>HynOyw}RyczmB<Yb<oZN|6_Luy<7Vs!e z6O)lFMZw#H3?}U`Z=~&?oNwuS2eXGh)Byr>-nK-h&nMz0-;hIlr=ow4oPNKnc+B<U zT^G2jxo)w8%dyXm-6V2A*x90A;^JYIjM6$+PI1ex(>d0)Wo>JgKJ3k;kzb!V`&{UQ zv@1Z18E_mA#Oe;)t5j}n6jPGF+Ec{{6Sie{7sYhk)F5W`0-@9f;2)9o2t~U}`GpWu zskl)1UjklStz;W3I{uW0%yrhES+q9}aUDM-9&x2;Pxc8trW+b9`&g}ltpZtH9lhVu zx@x!74{k--^-{^Qxnj3->P&`zRuhi2EJR$u=I4XR(<fPt=svl**G<?G!g7@X2IQ<t z@^4?*56oVaG~;of!*<A}M9GO^vvto-mM95EY3O?UJ@Q5hk)yZ0D9UKR_tp&Or%^0Q z5f(Ql_Cg6?!581988Y2>v~i-b4EEk+ot?<iR5>w%592kc7~G<bj}O)NyWZ5x3~;+r zW85VG;bYpF)oTZ?#TLYEcY}I+0wNEQUwyzv7^I9W)&mi8SGEnTavB^UR(gmIxRcoo zW?<~z2IW=Q_~SpW`IzKq;@JUIbVo9m=Cf%FsD2Z2Z<bSR?B&JmJCC)6Fi>nmDndaI zmX-zb8XGAQZZX<M8bza68^Nl77B({aZ;ALyX3ctBTcjW+%SG=$8+JHR7{&0~Ur~Eu zdut=SB2Ha*@P3EPr12`D_w?#%(>Ho+Q~JIuwQv@SAgT)(h)vpdYA-xiK}8-q+-7gj zejtSZg*Bzg$V}7TlzjIi2Yl}Kiv#OQU+*5;D4e?-czQOFwk~q%da6O#7_q&C4mVVX z%#3d?x3V3V!R>EaKrYIL9Y%`)<`5#^q(E<rt<@?3qP*QcR>&i38EL(Du<LsKo8P?h zZo-QGYS=|=X4m)mLnSVhWI$(Qhd`+&0k=#fd|~8LLjga2KEkXe_1SS(>({;T$|l|w zu*@oju~O&Wkef{>Ai~P)+`o!q@YE-y9uJir0NsAEnNE<9X!?@`L77hPNir8uP3dVO zGFQPDxqvv4Yq>ba=(kNB?f;EP?I3)UDv4}X-R$Hc#h}H+2@VJQ!0yS4Ba8B~P@h{K zPhM0!zj}{^WumZ6xB6;tp~Zf@#bZne5U1DL@gO@vd&qo=y|N2v|KM5Ki>gf{f5)^2 z2Fp`*_r`7f@aOOeX?&=Jyq^Dt_=P2mv!Xx#7?EHkd3W*Kh)W=$N6;QNKvLqNN(*Sz zcMWledoikH)eT1-BUZ&^CwD;VHl*_{1QdHk7qik9L<&3sI}to(L^^e1QVlQH)P3q} z2oJHm#2x34Z=p8X03MSHefD4af{-D<qQRFP&Nao?O~0`(;qe!4f!$YYWm;Np&*ct` z-$^|IrV8fiXkw6Ogkc!>BEMkTqX_^e>n7d*(S(#)k3`pvb&5;~Q~$80rg#B;IY>w@ za9S#d`p~?4bj#cde57};or7}Es(AkeS(tr;4I^_)CjnUxC<ZZa9R?bJ$LH(kr(!p6 zVUqTQ3DjHi_8LeSPjbG-u{xi_v5ER`8a%+{^mu+Y9VE~1NQ(a`*_5n1oh5O?eHlOl zM*GQkQyoNd@5P=rM`%ySwO?}&Iwrh%nh)pF=f0qgwxV^~c~-zQU3`*e&8$OOckqnK zzL97A*5jO~4Ih_(;qx1*SBq@jg<%-vch%%{XgYbI`sI>H(Lo+kPS~EW;0X@Ja)tD4 z0kk6r^xKs{e(pbKv(na6;T1N%<DxvqT3UG7j`}mJ+%jUj5=09DRlo#gZ(Qt3Wf-@u z<ns!WW84Mg7or7XQyYKD1IG)fDLG53Zz~>~fm(u;%nK!m@GUpup#tBDnGEjBf}&yf zTkpdKt<6HaNXZF6(x(PLaIaL5zRSl1TqAd<ujc30?zZ+{J(fS|y#pljH#|u#w0O`6 zGRg4>3~i9vIkV(SKcIP@J@bU~;0nWr7raf?i8zMIAhmE}Iy2;f<=aaM$ygiNCtGWC zvta_-Gt(-vTbLleP{_@K0VP8UE@41{;59Gn3?tRxBOac=px5(%zL>F*hV%z=T^|Zm z<+-UaB&?fKf8@)vNX62zUk$gQT|4s|3vt(Sx=&cV9bw-ao7_}<h$Mda6FYq;{MWKp zi(N_Tp9SVn4h(%8k2TXDHFPjk=BK*Gfw;~O8Q&>4q?JE+g^iA2kP52~OWYCXKQ60Z znlJIXgupUgU%u@+#?>z_9P!kfQr1P;jN1m{_r{$Jp>^m!zKzZr`KSUx;v4QkbhrzP z5wQ#RGl=BDfbhf^Q>X?!oL(;7;`l}=>c)O-|H70D5D^2)`4yzrB@X;7(0oZsD`oc? zw77JEz$t*d?p;j;Z%+5|8i&hcKSoXqJ=fC0A_+_@F{R`FCY1?P1<$xY)AV~;B^}Ui z$-MivRw|v44H+<hA|2G8Z_XZfcd<4jV$30km&b>4$WhkGU+M_9&`97Xsog}%A4RzG zIKl#S({{(L_GWOdLI#PTgI`wb4j5!q$DN#0*e1lXbXdTZ|2ZrOdgj%me;&x)cGqbo zvx<irgLLy)d*~+_wehh0QN<0MRIw%BNYNL%bl}?IW9S;#$SH<AoiA~9NdB0E;ftH0 zp+VdjSTn@LRLe@NEgnA-AQ`hEn=;|^-c^t7oBp3Pt?m%Tzoc1iwyVhhmZQVJiYK}n zGTfJWPo?BegA(1TCi0#qrjWjTPk|5My#Iy@HJ7Xxbq{2c2a>1YL;WXqvDv%Sptnn@ zyKzTq@O{3>;u;TILp~eW`*{vHmM8$=6Q`?Sg>NB^HwC(eX6=M!Zh=!@c+18Rt9VxW zVvub(1Qab4&h$icf>xRb0W!Yf>dJ~k^*>wj;tsl`x&4{%K9dv{nSfJTLfc$U5m1Pn z$EQkkHC-aI>m4`V8NbT?ukQmXS|C)}jiTU}mSjXFRP+|#2Yc!)1Q9eW&+Z~l_I9C| z&XFt<)|}9N#_ClG6a-1n;6|EpjH5JC6%fo$Zjx`*?#mD9+1qhLTbX-t=scSv4JF0p z>p3~|40yBG0QK@zJNwtUtX=G_YbLp~eP97XJlF(4Ai9RJt0<mYXpwsk5P_Z=&}ooG zjDdQPNQTsnV#kewGORm1$nzOH{)Ri6C3P3G*9{q?X}HmtQNQZpFMR~-t&)i<sq#-c zr^3<h8kl5ME;?UUN0PeegrCw`50M>nvs15vfm}%!ee$~XBA+fy-z}`noE|-ip4T4H z#{)(h7Cyi)_<RJf9-lWjyEp>nfP|Z_W5aaoRy&;xmGfcm(T`~PILlI8T<9aKDMCt# z#F+r4TsTQykYZr$>}PrUfqJCFxd&`MR3z)L0&XY*L(o@q%lJ^C;>%yZ-YmwU)X7%k z>Eg&X{sf;vz5o9tujV;GMYSJ;H6&T;SqQoLI`89)PUdgl@-VPIs_ZkC`jv91GA0NG z7P~@}MHXWCyjL^PdpEL+T;3|C%eO)MeR?-ZB*&zqWUeYS?hy%r5tSz3=>u>?o_P*i zF`uUoVYx)CLKk8{#b1U913-Mlh2wFfCASK`K+NB267nAwB$?G~Fk&6fzjT!D<AeJi zjszi2VWG5DV4<9s6C|QT0B6;YOU<Nft90r?B0B*>Z(W*CcDjhK6Ias#MUA_EN_rhz zouAl?uM(fsvzemDy7C0OE~d8N4v(%7F_LKcSCNiu;6@LQNYNoyn=x`CjBFjx(69G= zBC)uDkcW%YfK*p3-75Y!3oafB!&_21(Y~LGczJ%kYIi8Vw)Wb)V+-{{M{KlyTI?%p zu>yj#XC3pE`;EO-(strL*eH*IVu9YX3x&Y1N6$TeJRfRz&Ptv$U8QKJiQfx2yppA% zU7wM}WBATbh_#9QU7zNkj1Eu9#=H6m9e`!V=ci<8G6%&hOO`oypvlPkQ+MKax0`Jb z^4*KiV@x=C)<KKZ%m+z%BI8t&j`&_i<J+*t9H5z{D?UJu9Sj!RKB~BMnjHg4G;)P= zlIR=}Hi`ebGFkZ?<}LWc_K$BcnVV{aUvJ0ITDqG6AK_c*H8)aK(b*wVfUF*D)uSfK ztA4_>Ti8g{w|H#6kjv~N@pikRV=dp_2RDiUwPo0&Z_?Sl`<tBie=nf${Jx~kpC&m8 zDZd+a6R_#;JW@|YesUrc71*UpwsJ&A0;&WY$68^d1yR1qt6&*d-oVG+UiLl}nTZRH z#{n_^HIS$WP4wR{uGOa)n7t1A#kYQ!cBBx>-v28DgA|^pln=M}`{>7oBJn<N6f;a$ zqOuz4n%Nj=Uy)3@h9SK>7Jn>7_vwtEIavb^AUBm@E>KAw1t&Hx8II7{=7Nl)vjeln z$mZy`?-Hn0m9edt?@w6jp@|sU18oaj3<(Z?9QYnlOFFiQsa(KjVa|V5Y!Vo)v{#xg zN~z-rO_v86mYxJIE2tmU?(&Qqweg<IY;s!g3jgeD=<35qgNzRZAnuCkW4FJGNd}O! zcqyXGw9Pk$vP>AJDR0UV3X!+@^R0}L5d*n<=LfQ6u4*U=ziLR_7?QVeUG$b0N+Ded zGDO-#($se??#Lfg2td0$(C#={fMzJG_LOX++;7-~!-SiV51u&edSDEa@+@xWo*YEi zeHd&XBc4IvHtLkU(n)Z>zTj&4CQ{=bUo4wDi$`>;kF8kdWM8IUUQI3N(J+qdVrb(P zow16J#Oep6a3*k-&7Cv<f)D>Clrtc2=p<`PgmnF8wAUq1u!bycQv(0~t5dXZT9-_^ zzLh1)X3fv%{>zKXLm2fbf*ey%bZ>u%sOT<cvgxz?k(i=$5#jA77)Rs$>H%Q0BE5V} zj`9=X_&USVh6lFAFtf=)Jw2(oK)(^Zbc-`<&Y$|%z{Hewfg*u9AvrNudqD|;DPL5p z%OoTzRAz+b4K6`M4MWShjBpe8u}s5ekbJb%`7N0(={oLK&rkpN`SpLanPu--)_3g^ z8EhNI=!El>&9!ljjWrn{ewntiJqP#kckW_e%&`y)f2Y%P^%l1h;h{AP6PCs8z&*HS z`=)a4jnw5FS51!&SYWz}#wU}vzg%y7Cn<G9%DA>8IvRL=zzf8-xl|$Ecde79gqF~R z>W<}A1!v?~6|YU7T1Q5t#yqQhM96DGY~A2cD6XYr!PU}~%k*n(v<*Mgx?}IdTFKsn z-?*WWx<!t@9!V2Z+5FW)9|NMTMbz^ecju>l`%yx&jVTx82eA8qCVlPkAl+m8sPlj% zJNG#F^z+iQwzizf{;Ei)-#=7B<lAGQQLC~S9X^ay6$OAy!$>tF(WRh$D$)COp04v* zr)K)<$2W7HD<|89EyAt*zR7U88xGd#N54d}AXIRXt2hTw5eoxURB!cVEBDtO>JM`t z<qb2=-*h-VF3k)*Msd!BiP#6=O>OiWSqc#}H4S#TP}H$-YLDCpot!cbw8)*CqAAD= zyHkz#%lFk2tDlX&vfXX@_S?UPx>w7q<HthM^z=pLhRnpMvd<yOdKBT9gfz+Bc8hg6 zh7og}?`o(A3v0mVFA=ra9{0m;r8yDvf^M*gR}aeMQJAPq_}bQ^6}Vy8mv{0X3m074 z^N+q2YpY2_N9`EPU-CjR)T+r5QkFX16^RV~6*-tY(Z`lZ!Skzvv|jG*@dLZ6?k-(C z#dJ+{TQsz1%WwwFi=Fs|40w7Rw1<}IXakH`{fNyvVj=)&6PG{tINNv=nG9}L>{7;s zkrzdrY+OF8L}}r+=e{V+I>W?TN@1FIR+evJ5BE;ej}g&#k0rNvSY~}$t<kkn^58?* zMj$PwJ`@OE_9)qA7Vm}pClNz_YCoN~Ij5(|mHtPU8CRlN3^Gmx?PGYhrfT;hd0Xx< ztF5Y%O90Z%n=LKT_X#&Jl7D%uL`@Pg0~2lPV}n*?O<Gupn81yu(vcK5Kggy8e*S~1 zbEfY&NzKW8;T!-T%A69EcCJx|^W|vU9rS6NDE8<G=Zlaq&H<zx*(-jdkf}O-!4-XC zCI0+*3)OtTfFkk3ip>ZawzibqMxp0<MBB;{^H#;<3@U<8eFTgFE%Qg0nJ0s{Sj9Hn zh`m6sN5LBN<%&gh=z@KJ?t|S_(rR4<E6^Zse3pK7Zl^!vQ+!pC#c#0-+NQc&>yr6I zSX+Uv8a?UP2Omy3fO1T~hh3JG`Yz;(xla*HRA}SmSD{>kvm{*~X{_5*&TcCH_=HPI z*5k)Xx4c3vaZ(w0u8%(La)p95;ErOluRXF}*<?J@5VBHJx;6bX`L%i!S(ZQ-71HJ{ zAF}VQkQ`mGOIAd8pA;~?6h~?;?6HPn>Il~eo?P*C<hx(N4Kgs2S`D<bHLXQR`knxq zg;jcBsf8ukQp7{&_Im2UgjBxoMJTZU<%AUKSpj*T&{u9Nv)xd--s)D}uy{kR_`1jV zAT7=hom#>PP7Pv1s79u-FN#W*n78Jv)*3!c1}Vh}Hn!72bOl-xvrOA)5m94FX^Elp zK+}En!PYK0HqDeGp*>DFE%si4OZ}zJJ2%pZcl*M)LwR`M0p;XG=2_^fdzY?=XwG;e zP#>Inig2qgyB}3Ys0Nsax9p6_i}iW-Q44IRF53<o^V!Oe&ZRIjuLMTEbVNa%P0g47 z#792-r_Z%$lImc@GtO={7B@EO<eR=J_23gVOAzI~A+3OG%ob`*4ynpiF@WN&$4ChG zI~21MN2I-JjB`ebYK6k5Im)#wVY3Lr3j7;I{J-TmUyp`EMMkxtZX$c`kVU}n)6r?d zr=KRi)NY29P-n(hJW{%e&w?@v=b39MTmNtr<F&ZKb2wA_!I!mDay|Wd)q4>`ZBuKa zT+cT~>>?(DkQEzF5#AB7?ZGDzz9F7e>cS}i@FEk>JcK{F`i>VuJ6GFFzxbbsU@)@0 zp0jTF2&VXLEd56)t(Je~+neEuY;HeUP7tagU}tXXkAGl`zmL3m_g_j`VL(Z!emNsv zbv!nF-yK58bbk3qe-a&LqLz}CqrtVe2(7tJy=R*O8u?Jd<#vUbd;qs<9Xtdlat@vI z>#@}81{J@-p_24sHgwgQ5Zh7L2hvT%)AT0t_WyTea5dJQ`+)~u|K$C;8K-b;8!hln z0Jq%>v}gtO|I8o3Jo)6GP&K73*%kGTcL!k&M_8k5?CXqFJqzN^GUIhcMEqkc{0Qh3 zUM4T2Xy^ncG7%DCFIFRkb^lOBGOTq3v*PmA&fTPo8n)rAD^Auo+QPgDMQhdVL%a8~ zlhej0Cddw;3c#Hs*nNTy3Q9;1CSbyj-7Lnlo~59DG{<6XeeL=mW!m3|5;FORf8Uvv z$ZR=ptePQH6m={XmAD~2m7P!W`^j;q$d2%eCOr~%@AE|l#yu!o7Y^Xo;mWpw<3=2o zDeBP|<l?-wp3_zRZw6P=5?mVyd=>sl+sP{oayiI7B#T&#eZU>CI8hVu)xaXkIsyor z!4^er$%XTc+g!vpnyp(r@lRdCygsFbYDDQU*4-Xc!6qEyKYR_cJ2ZY!7VRHwdTHLh z0WopQ_~cK${5lpV>=&Q@_wj9S{hiE=mB0ztC~!&P#wJHlj*5tl3e`=EVpWxU;;|$$ zG&)OPuJ4}1eBYgDbAoUP!HO4JJcM9W7a#cG<U$b)Ff)ljCG{enDU8@$v*LxE2F;-m z)f1yAL@jz)`6Pggr0My&p#St9mZiQou8LDlmDz}@ne)n>47;uW7WBb93I6;PZ)m8w z5@_6V3cL&19X1y6AKH5Xx%cJZ9lL{r7X;4m^dikM6yf~jp+y+8xJ)Bl>`-|;a}BEP z<Tacdqf2XH*u*01c+Q_%{YO_9r*r~|h2P6+cNVVj5@#6K#!~<NukMok8?8kU)q4Mx zZ27=>V<WCHigmQ8Nm%82#4Zwzu-w^{CNwg(tC^%HF_=IT+w{&Ae}yy=lJ>0DHoy?u zQGm|KzAQ5ev4Mtvx0c8#d;Zpzz0}F82EJ{bnkM%e<kag*O>Nz%KME#>;+(vAvD?Of z##josYk7J?205&M2JTBYvOfO`SF<ii+kefnff=%e1P&8Oydt=TwNCBgt^l!FPl3?h z@WyKhNTT^a)+d{Hn=+XCwfsnQAj+~rvMEY0P<qo2&Je2Ma&iCpJ$gv?Y+>`?5t;}8 zJG3D4&adTBvJx^%$Wvqk7ckBG)3bU{406w>s%Z_Z`DLp3oBavwethJ}yHUPXFmKJA zye$V_QP{aRfa!nIZ8<;W>M6S3t{Mf??1R};MCYdVW{}AsCju}_1YHzr9@&d{b@8Jy z`sH&xqrl9&$$hX)2Hz{M_(e>%rSTOa==pi3t!pFu!@JV+T@H_Dz}3Q`=_sZ`8_}ZI zB<*PrUI-YEUtQnyRp_cM8z4&6fd)<b!2TXM-63j!ftLIM6JTr>EH*2p=~jlUSqAm> z>>YJYcbQa9(UC;Fui^_@@gac0xxsb&Sq|Q8XS(E{P763G`#E?F(|nVW?U#xEAkO3< zLOXeQjPD^>i49y)BgNMAq#q!mUa|pNOfK?QY`&Ypq$Fu;H$z6q+qNPML1kjot8=ox zPO4}jkpNz`D1F6p=^GwIb_Jxr<DS`g+>-IwJq1qkdwT)8C@vGcbp7eaQz8HHJ*ymL zu^dqgwes`0giu1P>L1Qp@t<Z(7JavI-~Av&Y?PqaDhV7e=GX?X^UAPSSzDVAmv-01 z3uUH%zvQ`Ge2UK^4Nwa-Ftj3Qx6){Tlx|jkNR)XuUEhR7LVZ#@MP~?cx3>t`eMEDc z@U(7Iw6L|<TcBGVhfGQzK#4(7OU>DV86OG4`OhjPW8DQ3oab%bDP2h&dcXW8K%R@% z1_@za%#4!?5Nwps9#hhGEF%MuK*XtY-tgu$`IZX&?vg9u@=jkamT+O4f&g1`h$@W- z{CFyJ;Kvw7`8Vt>qRoxG>7u!Hia%@5TECTP1&(~R?E`(awKq~QEGknQK4%9UaU^&$ zQq)-KHuFJakIongnb_H?+G!DdQW=2qV{UvIOcKHibu#OnehysKxLA)=HJ3_%e}{L4 zl*!)hn}pf=#m1pB<LdaSF=t^hFY&313G8?hwL6cKn#Hh<*I`l^+i6hzj+8z_{eVN5 zL-dtM@HS1=?bJ`$5Uh0Mo$30N<0oqEc(xV{;Z5B<e}63?y*4mB%OFG;z{ZaiR4*LC z95Y+fh@cqEw8}X$?>p_&4%$`U-411xdtKLJfJu84az%F0N<|lRUZl%K{^e^-i|D8G zRT9~FKke^1<FU?45+fUK`qHIwg0~ZWC_Pw+3(4M4ow%tZjy)au|E^z!f3X!@J4>#M zJOyuatn&B>dytT)OE=tqnrRi9nC_OynHZIA)A!0%J6JfB=3NIsXCJ7Q&mj&@PXSqI zD;ns%Xt<Bh+8ZzJJ#kjG>kW;XK81-eq#fxYrLw9Bud(W4x_f(TN|y+{7#d`aw>V!) z0~4bPt3l!%Fv|ynijQk=6)l6&tSJ>6h;@kszYA&z0vby)??w)xKDMaH2(&vFI{tc? zvEW=6Dgfaa`+h-5y?vbvpy(b0L<joa#J5}@JaC0v1jsq(b=H+0e~K>1z}}Q=&M<-8 zVa<;F#>iwbYWuS;Xl2eXf~ZDobei89Hk!Wlb_JA|Gbov^d$D`lJRt3j{02q)fZ+M2 zqgCr$M~UMgxtVFrXq3tDNQqTDn>ef4-Ug|^zd56frx;z?u4yHFvzwuv8rtP8HJTTg zp66O1!P>-Z9unB;5OBBlcjk=;a_M-$z1SHT)JX(gKaXpa81y4a#t-d*Wxrm970=Jz z>bpu%$_VUg^!3dJaDN|`aT`e)$%9Bq0Bj0^22ef@G0uFlA%X3M=A~!GhRp|&1?&gV z?@_tgnHykotEDc#=@nVOujSH;E_A*ul0X&W(>o)>{VU#U*Cx`l%Em5RMy?tCY#DxY zx~cE|9lnq?_HzQox%sQ8VdJ1h_>6i7AKrDPq<;P`RepJ=UdJf3k}Gj%$4`Rh@6pVb z`!Asm>l}oi=eqJW%v8<nRkOJH#UNi1BDz-kxhJ1n{>?2NZhIB2ie!etfzt-@8d1DM zR4Tc)_7}p|uM98zu82XNUb26@vQ@*+n~tQ@MZIKJ3(vqndTiq7>f!@2g~o)iI%I%w zoqN=YzI}cOXpsmJz)p~i`EpJNSznks$DUbDKbHqZ3(KV(^$Y!m3`a40J+-To?+9kN z3ad&ydZk05s;hVtAJ70tUsh!Y$T55+#4k%8$>LCNOUHVs=XO*^Vm8LUr{*zhVv%^$ z1m>QhvK|)3p0V~g5;P@=Kd+)|we#*<LpanAi#&(^w4ciZwS9J-YcC%rrn+k5D~Mx2 zB&I`WD71DZGc-?lAIUKWqZs>w(f=(qP~UkhzG~@9M7_O}ZhBq=UvfhuJ`LY;c@fi< z+7_j{__0{=Si^(<(SX(}Z`O{&73A8)nw<6IwB?cRr`zk~X}_9RUtCx!%JrxY0T*z- zto&~@z=)rq#ZZ+EEzC-6PZQ%RYd4RK_GSq3(F}5d7Q7I(6ja>%<Ka(b;pBVd;tY!O zXCt!SJ~YVr;F9Cl(Z{=`vQw~{jr+@Arp0dCyJfdTlz{)0eKG&E;6>LPOlK`;MLBQi z*U)R3MCk^5;c*>JSa*N3D9#pwsr#l}(&J&V$Q;M8_xQbxOCfWDG3bp8UC?XXC-^;| z<npwvf?;EJ^e!!aN3P!2xm`;@pN_H=4!(q<*B%aObO4y`&xtwaa5q@Jb2p#Ya<dZ1 z+qiQ_re{=NF6$mDm$*EAA{GQ*0pnl2UsvvS_Rh<xrLBsnGQ%n-AMuvX@&}cORb7Ef z#{dEw5HCZemW{Sye`TvLf?0RmMTVYW<cfF1ugPI$_ts|i6d7?u&t1013|)-ZK9;}s z0Rh?k!3fG48Y+Ji#=S0E<Gx~9nakXB3@kK_0fx><WZZT)&pJR)grd%$@_Pt;_)VXD z#e-Nj&5c*FSrvLbinQNWC19XcpvJ{OLpnkNS<laf$h1_PF8~5yMUY>>X9$7?wxF#( zL?141EDcrP&zTTG=7Y<V;)Efdgj?KBJd)$;(gi&^=<3ST*)mvz5ii6kmA~=;kJP$; z3g3P3uc+htTh#sa+m~6Zud$BiKFgm>vzI1EvDYK+4kj2qJqkb&+`?36_1;~vLIguL zd)E%1W&VOx&Vu;^);!JlpV%Xd_7^@*`c=v5?}a=29zTKsXTV(S_H+au$;sj5`kN01 zrI)wE42r4BpAkl+!si%Mwgtw2I8S7;C==R@TRuKF1py17dcg>j>lJ6NF@$IvdcX9e zp}DI0m;xKSCrwmu{5biK9aZhh?v&FgBKda_D+=MeHnP`U7>8e71}F-cyL#-lW;u1G zwTi6u)f`-q6IwtFT#)lCl0>3gK#OrmE0XLu^D}Y_941NW1=ES==568N`4_bo7~#(o zvKi+?qx0{_KL&)~YX4|IHW-~?VSHtSNC6`-3&HHwjEMJJ;EVOEb4l{bdG#_NDKY}n zkjD$j6=ss^6WG*cWCWF%E`>QBOb~h-BqQF?yj?+KM$EtLF#M505Uf-${x|hySCT$q z`tG{M(*X<&lIi+v?kC8J7(Gt<hr|{gOYR3N{t=2F+mTzOYkwi8B?L=oDx+o7zb=rF z{;HN=ajyxAx)#)^h@X%9-CkB%U6J5I5d1Cj>#gw<XxG4r*(;4Bo|>;!XIF?ojSs2u z&1<IXIeGH<`30N*B(p5M$*PL>qoyiPFNBNpqz-CH&gCt!*{g^Z=GPg=`c4GFc2xyU z<y1F|zi$-|C20P`rdr0SUEWN5Bp1d@L75f7-hXy1ks}?rl{$lpdFk=llPj*f`tboa z4SX>&KqlI^qI8FC^C#$FnA*-=*r6r*dteGNm6<6fI2tx%=#_hn%7%m9O<lM_b6+(m z%y+Ul(}8YJP2+qy%lW*kLWlZ5uh{+-0c!sb{bQ?TUDF(CHI|ZuMi@UHW~dUa<$6X& z$O+-^IbHBsR$J}Og94a==_<z>dZmhWVd$-Wjuhen)1!bG9Q?Mz)BQbi+Y269;Iuy} z@7Gh<TqQ*FI(~1K{#j@6T9q+ud6kUgS9SECS;H3M>C11SsSI`tVE`ou<?uzBNLpv0 z!^(wyT$4ESmw>j+BKfF|N4HR)=5eV1HWz<#SjwmUdap#7uV<UTMW<E&u)NWXzLK4Y ztA;0qD;)U*6WGe5J)GZ<<p#<k|1x0rm=_Lih4*=S1lvrsC<PA24?%O*?Z)D}rDV>L zYshEj0bVK`yRUyzt%2@Q`d?hy{=vr)2+U=83FW^%EBSx+>=qqYm@Rn{+NSHNTCa=K z<g@%wghhB07QnenPPXSnZaC_3<7Crko5<HcW9Zx55I&)mNKD}k=5<gpUK9{!5*c^S zu6kTFkApi-B|bEwGKwN?8QDAR=5*2?;s=Kv%8~aq2-2mIbNZavVce_B_-j1N2*JWr zn^7cv;t%lwcj8O>D3-SL@sGmyB?uF!1}*1qJ#U*D%Abgm$d7qm=k2&AjDq*>vF4cX z>CSAf(T&@T^*d#Gi}=U->S_`?XgtQl_Y}w`UeL~L6s@eyVv*1GE|4B}F8aZQHV6{c z@v_|mzatP_n=;y(A2MW7gp8NB`8IEnl$aZ9L|1F(Wq+!V)#zqM;<?}gBlKm!6QxV0 zJ-R(NCF|LnH^i41FoKrc5bw)ZzgW*=VVxLpGfJJz#1K;GLW6o6^v7&$e3dmCp|*um zd;Zz&A560I|0oc`DE5ON;P-NqfQpe*eA4f*5UTz@s-1vWU#+~EYR17({?j^N-j)ex zWyzMtxFoMD=|TEH9<p;|jG2vmMp&gEe?90xRX-}mHkaI<4UeI5PC&X#u4K$;8kqc8 zec*RV(kcG`5%<<%QLb(K=rTbm0Tq!FQ4m48Ya}G3L<B)f1O|{!B}W>hyBQjh5{8sg zItE7Cp?l~W1{h*yKZ@&p*Z1lA?c><T-pBsOzYy+vuKT{O^SsXUwFS|X<~$Vte&U6w z+RXR19T0>09&4OAmG5_ZaJwM}pQVql6DK3Iw!9_S{qmI$s3qHjQ!eouZx`{7Nm>s_ zG&EFrcHg06Wm<lGN1CuxMNC6Dks9Y7iiMJaJtex(SDz!)TG}9bwGjOjQ$a*jDmcIV ztjjSh_%bfWr-2`OGtNmSG~ayZ0JRzY$R#U%QO)vzJD_bL$vO@)8I01b;t8E70Bnrq z8&!hoJZ?r<d8{mVfbh|#rfNHhcDkt&i`l`KIpK@a{iDjW#u!i9eVXbp;kGDzyI$ep z0gJUq(h78hF=*dI(v|Yx7kNDBpi??1OebryE*;?dmx@THjbsJyOS0*OeXI|C32Nst z%WRK$OLl96dB(Vx>{Zm81-b2#$kss*M}FCbbFK|e$NOu*e?%@e+kK2SpJgGOY1gXk z38d?J#kM=4xQmhtEIU#V-Qqol!FmFKG)zb|&GE6(Dh5$Y?jcU9w@3SN&oTu)WY*s} zv<lt7eRtEZqA`v0RRU6H{=%VN9m>RHa@S<I;~wu|Jl3Ovc*ez+Q_KDGln%jIl-IF_ zQW*`Z;0D?tV(O(Ee7*1539LJ+l!K*-w=iU-1}euGKlD9ELM+uK1o>7tdi~ktf$%65 zfHVb=U-4uhI59lGb0-dc?}<7t6ad2ss>hR&>LXpPDIX2rSuc-cuPf3nZVUM+(G}!q zCViDnVM6d$nhun@ec00mROOzade)Zj^ez-od!edxALWk**xGJ_-RU!$`wrHkIRQC? z3!d4w{PBME)m!=xnKMOa5q*bzL!j`Sf^c5$pE1|h%=af>&nn$3&r?`*x;sDLk6HCd zL@s~y-l={dE3hTvhZdU$Y*jnF5sqI~qsd$xrCNz)X!U|aJcvWxX$+fvym^A7#HWj= zQ%yFr-tFyOkVSXzqp(ZoBt%9^TrSsA$eNSh+B#6shYF6eSOL;$?dfTgWH&#@cMP>! zj4!D9ev*(QvAIQ~%KR6`{%VfJs@a`>H%XoS(xG=Dm&r11+V4o*4Brytp?@S6@nPp_ zEvTiQGwgLO`J>G?l)d9X3AL|?(7TgEyGM~)iNhff{Y05r&MmEMQduq@)jp`XQe*IO zl4(M;BCq+>t(G^IpJp;+>H=A)PCP1SEQHGp#Z`GCUuO~-ex|xGu%@?Ddi;gzJEa$d z_K3cZ3hiQdWqmv~s_HzZIxJPY`-otFI-_}eyRz&1Uj@hLbjEm3z#x}>^1%UL9rL&} zv4dyajLWw<OB_+ierF0*e7^=2-koct_>GT0{mgdDr?(m$BVEdpr3O5a%nNS#mokF) z8{=MX1_;k`q)3EhZ7787T1m==$=+!0gWRnBl^rvkHuHM#k+2SQQ9BD;e@M<v4^A@# z^d2APLg*E^CSx(oI!iLsyMzn`-x;^_i9XSWty4?Jz0=<wp>vk$df<28u6yTBq}CwS zlJ{L5jsvqxjo|Y)9U|WbcjBro>(6~R#-?ZF<mU~);q*VD_7kM(uqI`6E)A>9yd3>G zA4Fib{dR9orMx0rm3!inDSt?B^)~WG>mhhuVqoTMZ%LEQh@8bDM4xQ`;077zN;*-1 zkqj4E{H}%U!5h?rF0~t1@Qe@T9)F%2ip(Ksw=m938+=2knSL(7v-4$ADA;;;=fYtQ z#?){MDj|_vsu(UNW=Bf8Bh0<?Equ6p^nMmVX1{#%rr*5{8h{hvt=f!Z?~%jW1sEY; zYGtC!p@^W;8_g0TW@gkXRb?%`+H<@K+uA~J;zgcdx#CRBK3h(Oj{4h)uMK>$Fl5r4 z+Xlcmv(tcd^R)Jt)ms%Jj1#`v>7a}r8DMVjZgEGCOOX&Q{Zd|AhPp*E&d7T1NqnMi zlZG3)z8aG9tH?oId1}x<!cVwX7yb^RF5k;lMt#EmzOUtLn#}ESxem`yc71vjnabL6 zPmU=S_PPD09$Tt8#{c~AT8>qIz7GMXEvFP+(up!OB8Z<`PLJvlf{Rhc?bZN@W^YI7 zX+~IAYWK5pQt3|Ar>9p^T<%{Y*eDdtodAf1X}<I}k%X?zD>M}xG|_YWBynzUk96kD zoq!hkVaA|#i(|rB!>8UTca6-`{7d^kE#U-s+Be+`+r7&Dh`INt$LKDgGhn={s+i9B z0(wpU%87eK%H9K+)r-fzjie$MFNw=We_(|8k6q7>M_{?$(~^2zo#z}CRr8KF{$H^j zSjx*B!@@IhS?9kQs3^-yk0_t&HGY_fwz~H`<e_0u?kBFIZB4%7R1RQ9KMQ|+em|p- z^0x-0@psgwL{ci8bmFhmrFi%cUq;Mn3duSvc#Uc<WihUCpnpnx2`uz$pKkr~-vm}T z(Dk&G_-R*}<?bqsCDOK;WzI}Xl1jW8xZBVC^3(ir2nJ7eFWN$EM6S)ls(MVYX)vQ4 zi;UAp);~QE=}%FeJMIG?BGA-NPaG;jchq)?DW%E@{%PDu_Vb~3lcGW4W3VxFN0^;g z@SI#?OmX7rVfw=$6Sg0qYWFY2k$+qWkqR9(1x6>s8}ScoO!3pL8^pGCE<jP!Q^Mc* z06UF;{e8rnWA_0X<)0_|4>H~k;&l0eJ@{~{{P2Uf{q*0a^fO=lw`IBdUuDkUNB$2L z!{4X>w4B$P`Cs>%gl}t*)0DtnxWY9fgs0+P2bXl)v(X4}Lp5b#MR%L~HKYmD%(R`x z$ag;kM1P($LdKQT5B`UO5N*W|gwn7#Lodw&+Ncw&rN;TMqmW$Cp)*Zybm;FDXg6^f z{Vek9cKm$>f#yisY3R8M-Hoga;j^FrZMpdFxEDlU?FJe|@)v8&MQ*y28J>P7zb~G- z{DCGDf1yjU1*tL2fC)I`_vn8=zy7{9kDi`O^-(<wO#Q(FHo2mIJpsUv3M^<tyX_+T z)V{%X0GH1f7ykGQFAmK+v|SJN2ZghpJ_i0c-K#5vCTTRp6CXV3pa0v@xd~|G%$Fjf z^OTcs;-*GmFp5Vb^8Y$v;GAFT7iq`xv<jJe=nMYqt^n}it$4`Za$53A8tTcv{q3Y| zPaW@n`&RzXhtJG(T<J7G{^1P$A}jxY@|6K9h^>~DNcbYWqS8b}FI7Ty)V`U=D6L$h zf(C6_f)eMoU(-wDaY@i0=MD`ss)nDF;5jmY;Z67Ci)Vk|rC-mxA7rF~$I5AYm^UU3 zDWf6&G^vceo66=*y4^Y`cy(ZR{&~|JmmO_M@%;DpV7(O^W`35=%`c|>&CXpQ6niuQ z7WMiM0kQe0?H&xV>?xe{#6P##k69@SfX?DOC!gWP#CuvbtUO#__;tEQIhT^+#qKhS znYIX)tVo#}@0-%|)>q7pQC-37wgK!}{@cHY?+<8YE=+fVWtv6O!0@9s7wdbD%@;pk ziq2*Q#1PIk3KnES(&+J1Vj>*W$7@N!nK4;c23XBoUuUu(xX7m4nl9RAWW3}Y2Zj&0 z**=&4{VL&}OFqXEe-1A;BG4|KnHpuyMIz_0sNnFx1mF^ARG;mfMzNYxa1K=ruRx=} zB05L!*FG_AH664NRiA5)zL0yw48AZyD#xm=fIC<}yk~J2vxEqI!!+~&#makEPRE4o z?9FY2Ml&Yw8Cyi*167^QJ6tow@SA6<7V%oRku@mN>ZE540X9hTkYLenr#R~Vhv%;I z-}g;H^la>a2CoH8$UAF5bIAJo5}+m&-lu#KWa@`uj@1MBHelIB)TheJ^`S`?7I-mU z4)f?m2LMtWJZ|eWgeGQzT)N;LrRw=6D?+#P1F|fwO)Fv_4d=OxCN1x0N+klNYW<J* z(SQ;C?|**Q4ff&SwdB5G6CX=c_G-Ghdd}-{uqObIv10jBnJ}>sZD&F1$9mC_w5Q5y zntO<h=8`c`eB=UDZ=p~A^Ep8_Mg&S37s?vM9Hk<J<!Gf2;&<t~Ls_Y$>bCI&oSerp zJU?E7G(RUKo-n3P!Eb7%F<e!M;ia@_(o0U%N=&*rv8`1J!TEla2q{v>k(@r<{(EuD zy4zgm#_Mh*=^Z%uL#)~V`V5Q^0H}e^hRfS+af{C$q*;8nujO?RG!`~?x`5Y>tIjF{ z;KB614-eIF!V323Psy~ktwWDZx^gv<4gu8WZhCUK&_UOy-7y-;Nes-lF<F-xPiAnv zg$wThPwH)J#5Tg`NE-r^1gGxst6fc9GR`m1gNwkUE3YTBSZQpuJ%N#fn|nm4MnVNL zv$Q#3COsGVG?`6x#PdyG8es<I7)WQ$VBDVC{e>1Zsztpi>^aT><sLfZ)+zBbyFaK` z!0gK1PIo`u&0$*EaXJ=70Ju;)#9{$*#YZ!LbsuPvJ^+4pk>uYzw!8*N+Z|L|0c2l> z+!iuzK+<xMRc$d29g~<^AEPi@*8D60(#snP%WYX(vr<2CSct&!oTTykJidUp+&-q^ zY6q1}Aea+Ukvm;x=>RHEFuVP^(oQEhITh^uP0YODYz~us4l)`nIHNK~og;}mgX-SC z)@=zdEPevueQJm-FpGeus)wcN4?Ul))pJ$4zJ42%aiMX{aGX+_B3#pKuJZO_a*@s6 zt-SElt2lGw)MES0L~^)&sTgQ}>JwmJKC+GbI@ko*_-ZQRLL(BXS2&N$d9?R9+0NOT z%%uikJ3xq!)pP4ZAk*0VPgW~;;7Kn`RsjNcXgR_Vhw_M9s&WU34z9_<_yhT^A~?X^ zOykT6MWzBmYA+*@7s2gGfIe&_Scj77h1b(|P2SqCYg@OT)t1{U!h)`?Y7eeOq!;zu zM<GdD{4~uhG+?XnFv8K5kl@MdXBrxi6xRe9q)YZ%j+_dr4PvR^^PE&5(Syj|8*s0K zj<u%uCY2>WHhGNElhe8|?eK<$^VP?Dw_$EVXEu$(FqYl2iVmCSnGq)`qM^`Hmm3|d zSP6tOu+u-bdp+$`S>a&PJ*Ls-(-0ta(|1)*I~vma^flnPtI4e`xp0R@+iKyGXYnWO z*$rs4%l%OiTn*2Ai1RZHf_#%;lVP0Rpu7s%;a+rSS$=8m$+IyW_zmT{%gv~wkXU#a zuiL<yy7P)4m|@GhWvIv1c%(4}sSkeslASK6i7k0TN`oVJ_W?|l0uz#rYrL3|SCX6> zE)59jq?K1hBbz)MA5Tmo)>PWoiGB62XGJ0!@9sJZ3X~)R=sFd*&ZuRAwvBW4kd`eV zi*t+K@Yp`>03|gG{mF|3Ca9Hu`Wz43>}egpO6z5#Liug^>1Wv=Bn67IdUD4OPxDPK zfJDn$EKNpU2zQm=$F5JEjfF7fp8&L}6}LNig1WgOiRM02xmaj-*ByhX8&QX9D>_%R z#QI~UYhfLmP(`tgA9l9r*y@HutwGB=WCb`pLC<<G3c1<S`xuRA?h)W0i*+ZQ5*#Df zJ`ru1c12=rESzJJ65y=kBqum?ay@vD397zN3=^cVMgsb*7xUl9MS4_uAC8T#y&k=3 zHB1%shQzKT=fw5vT6nqESI}nAC44S5uIB48LXqOgH5EyQjMS9I)hM4hFk*k3JD@~k zxKnPPA>*uH17}C*Q9lwzXbh6bf&>9s4Bi%VAT(*B;qOI?y-ky;_nj2f<1MXSWfN1r zA_N!!aWc*(BDTWXs?JE&B3s!^7PW@3<%*cZG%d;^)i~CH%8Cu6a*Iy2)U<oNOr^|< zx~6oI^O~K*K%o>L^<kc56UboQ=VX(k1C3tlao%1ttmIh1yaWuRtp$$+qx9|o<OkpH zSG?^-`^LkAt~Xp$PHKr2Zdn7v_>o<ujYzihDw|6qmOfpcK@u_mU4PEqtuL~Yl)2E= zYILQI!R?!ul{TL0wIT*lytSO&ec*$X26P2-xN}%q(9tnT8|`@<Bpm|tjL3Lm#+)dc zjNN@+QEDAg@12}*j=6isN$z!2Plhg;;V*YeuVm%*c=+1AikLU9L%!d3yf@J!kY`j3 zw{tuQuGZm*MY8KJ-pQ5I$_+-oP<r>F=+gNQ0ai{~Y0VyqbIW4@feOU||9s-zY$sA% z`M9n~Iq}%d;iB>#h3?1ZtR}#%Rcww40Sv8t$j5x^kVj>6(ceond{9JeSX~CSfGT;% zEP`m`@Rv!cN|or+ZPeA^Z?m4)x*an>0T<@n*+EtSNszONlWLD-R3w2xNX9C*w_5!M zAa88BBm-FjT*8H8d1wesRKnu9RWcd4dfl*g627K}YKa>8rZ5?Ci+Rtmfk^VnsKh#k zIZBNsmFNi}lG-QLl;Tq?-}j{xUaIMcSF^8O2k93pfedm*O`JpHh0FJNia|7`ld-}f zbizs9D%Cy(Wt_!u)))i+$>FEvPVUasKQF~T($kMDVOx22O6Ud?`N&#@<HP2?ng;;q z(EaNd6Pfp%POJrWmihb#$jCw#b1LA5(6)oHp@uu&Z(Eb&Ern&%CGnQ#iBNSikJqYQ zVV-F`+Pn{_ty2s0hCNc!vWg0+qkw0Fww0fQB^Z5-hEJdP04xeYVrm|0x>7aXCLRQQ z55Y*3m8Hs)?0-u+6tZDh$p|z?yolE#v~duSn-Q`n64K26&TtReO5iTLjp&ZnG75U% zdGE1RXftW5>a<;yIt*Ym^5`iw#i%f|b<hFF2r#4feu4kCMhR<lSjsx4sSl)XxYjBd ztLdp&zLz7v2>P}Z7V>a;00GBE%dc_fe|$Dm(9yXG6kb2Fdu4o%{$dk9KW~JS5b9X! zCu)6jj(epTKCrvT>80arQe2{yD@wkGx`hRq+In_M2V|+0sEHfRVU9ygZ$pavKyUK! zpbVTD@f51FiM~OJVRym={HF9xctSmVMwD^m10B$F{aU=lwSG<LeU=Mv#zBrmoiZP; zk-JwB%QJTHh7RX{auU~M64GJ`qOGIY)+-hkrQqFM@|S#&YJ%YIWf)k0-q+1`#3P=l z_&j=`Z3s<_Far-RL2J3|SrWx*$}u-h_xC*#o8h=tcw<UF?z-GOXQ6?J+G1Hc+`xsH zJa)NfygJZSV}zHGvk$NSZ7@t)$j&-=1bvN1_+uVVsxVWr$(uB=0oeAsfzsJ6g!w+f zv1K+*`-YM~$LRiu@J8P;D@pH}<G7iL>9^v36Le2Y;RCwfnLOvJ>!z;Ev)lL3QR+T& z;}Yi}3R`v%OFBM>cXC{yqRwkSI%bZaGArh2rp!E=Jz?#EPw;XS{k+azN#y)wZe;Ze zO4hvS?aC*o93o+!Oi%;}93o13ao5;kRtlYQ*{`=8WIj-<cO&4ME@2<PBG9#vN*QP} zU<K-VYdit2wCes0j^SO7bBIffntSLQATio=xK|1XBb2TtJS}=CPcKRr_D~*n42xX6 zy^GjHQYgL!$Q=B3WyqSI!0;ZRY)4V}R?tn5g9(qmb$*)Fm-O?S4^C|l^_7h`KX+Vd zw|zwjlKT|0w+eKVG2D9Ed-r^msw_m8YcIciNVMqT1-#h1gEl$pW(|b~H7I1G_aOX^ zMu(8)Jo*y;_#G13vFdgP0`cA*3uxTDGre^bGZg~AR#FPqyU(ss`<Clf&#Oymbe7#$ z?G;p1jJ}l29*78RcYa1-Oi0`0PMB=F)e_NV-GyQ9xND-dFf!VDk|E~=PV~7u>ok($ z1X$PCJBWh5Va`NhmZ%XE;y5?hmk}#LmhhgG#XZ!S7M>fGqV8#1JOHoM%0rys&Wi9r zyl~eVo>3}qR%*mVN+k;bYxcj=)V?v%m${je4fLP~*<C;ngd$u6SMLT%I~Pi&C6aN? z)KVPQvb^4B{XBD{9qyj0=7b3`U4&?4L2wdQ^@!!U(NUkot*hbJXanp_j%YBd+086G zB+M-*FgEnn#+$Y#5;B!?CY8p!)`mGWD7^$w<Fv?}&>elmp_uYPp!Tz92#3ZI|8-ZM zQLJ>>5l2e)zP+-}O=^jt;XGTR;rYg@Ps#1rQRg|@#w0_#xjIrx8#CLwOdhw3CY9mw z)L&AN{**nj!bujJ82I&e5nYghk!v;25!WlorDODac;_4K&BHo2^?ikl<E6Zaj$(yf zQ>||d|05j!sD_nymgfU~3)=ISJgu+u5={(zeC8Z0#TUML3{!NlyC-E%V&l4+TL#$( zO-T%VU&pX*|3Lq?0w?V>i42!)kfiIh@Mcq0;SJ8ZGa?I~#MzV`!LOp38RLuF@#Bv( z!@rta6+Nz;XWH`3SC9wxBlOc(s_CkL?OW**cv>DpqFv)A(3D^IC`sg7@!LysGC8=b z6;A%)Z*@fiy>tt`te@rNA@cj%OOQl<n7=57xX<VuT>02lD&l$2{pCUUzKL^iJQh&H zCSZ8tdXvD8T*_AUi@vP3Ch1G}CRa_PvXcf`d>!4z9e}X2f6R7#y=`WH8<HY*ITHGE zhPK((dcfsV*{kFH#~&fin3VZdZ8m*Gzz0PD90cPR_9u$8Ss$<fP?7(_h&j-Qu7YS6 zo+4mU{J}G++&l7&!<!L%m2K{<{?)Fpg_P@Pp4RfyJFo)i8f;U;chXE87e_A3CD&8Z z?l%W6c&1u(KbF}2%q}OVNgc0~b#BhR5Fga?*|Q)+Xoif?$ytX^O5EntrghKdAX>Uu zI~-P)9;^J4USHWSev7!{k)-M(6?O8F2R;bV!F_r8gc<bOcCA^unWdT!@UisSr86;M z2FEXNAO`N8YZD+Ikxp?9OARvh42kY2y*;<3Jq;CH$lSeLJDqexVQP|)c`Qx$KGfJC zZudl+XYzlXil22KD}IM0iUu75tPhkX@AVeCjwSJXhCNr&73JBVS``UH^*-g7Fh3gj zS|TOB!to@M;c`YPQNXn|Q(gQ;M0QsySuAD?ks9%+Q7X+cp6ii#&|xhJlcV8FXjA20 zc2R2CJ{#~}2r-tp%=!62SSgTqDxZH;@-Ss@=r|4nk;T0CK89fjk=+;VVmT@8#U@dT z!m;oA6(lviwoZJ0T=Bx92?7A8g+B1I+f~Hk=;)R91sMy$xadxuovgRwV?#LH*X`=+ z<SW?<A~4S9ym$9P@vqZ&_Ypx!lhNq|fdDOly42;G+Tl^_Ds@Prdm8NJEr&IWG`qso zEHuE>5fDO9C2)=LCdN0D_ya7X%G9O|$GN&Q-up)M4%K!NZEI7J5f%qU7l$#puO8K; zN*PTbill2KbWsLrTCWd5LhhZsg0oyZ(Z;dMzJ(1jB_lrGN=$9)A5n>=M_h{mTa;0X z_Z!G7cmNBSo=epN-LVJjLAndf1UMHm&$4ZyzFzC8kvzA?SF=tFJ7pKzS6%Lpdj;@x z+l2*iym2sCyt(rsJC2)kCjOEq)z)RyvRaByDs?k{-Z6Ob`>d|;6!9^-SnO3o7a3dT z0e0JWc53CQE`JkIv1>{)1<l1DoaWM375~Y_;mvyG8C1!{zy6Shy8x3JY|0Ynk~Q0U zR<#BY#$5hP!8Sw)aDiE5#tF;E!j8WmONYqy?^y=Nj|C)r0h--nlPPg7e}!%Hwrt+K zl)P@Q%n;&C#AL)&DZ9BQz2VIc-~tA_n^>9e94JajPBWZ~TH)rL#K<axeACu_&DZ4q z3r}Zx$uOd??C@({x>AYFvnGHcT%T^UDFu9O^e|=-7fg&W(&pIHhBUiY7EFK`6vU}a z-ga0Aeyu&29Ot6vGKdB~<nc~cn3|ZVBn=iNp|r!m6Kx<#1!_J|PaY#2!kF6m-E#>R ziBJ35I1-Mo$>tMIGC~357KW&aVUIQWaPR@DSH4fjrLFXldkWDmVh*`qf@OSIzS$^! z79?}*tm@gteYsgINTmTW`1y`!&ik&EYcVx^cKoYdg`O={7*YQdlHB2@x682343Af~ zoq!|AN!igc;mEu`J5%Q~2j&x(aPkIX?FT>8+fmB@L0w6Dto?b}WfR}({kR6Q;Wt`O zt}4XEMDU2-ei7oV01A`zo(Kr$I9j?QhECeHgmVn;NrkjqOEQN>-fN%AFoaQ<t@-zQ zM7<j-yG+*RTap@yMMkbb37F#bAAZt>>l?g}Nc4X;&i2Wnf~WBZwLxN*UPK^hL4rQB z{+<46NYv-|DMOUrGHe+T;Q6;};!p5n{S9fo$;_;ux+5b=o}19(q_Q2g5Y9j@AzhmO zd}b=j@$NGW^I@HySpHkUf1C(29_ThDp|47VHAO3c1a2|3F8F@Lc@MDk#}dp==JgFJ zY@1MBbiQ^Gy}2#;*Dwm&Zdz4QfavI}hUoiVZ2{#VYTF<TYUz;402clMc}?}o&Dsl> z_(W_kmjtXghA@OH8A%jg;Y(siE8@bsLS}5IdJzwGDc{)UxOM`jfG)XPs>Pk%2Srgh z7tX_D#k~)Oh*|;#f$N!|)&2m*pm^LhI>IABOcpr)i+?gs^Y=_tVqcZr-p?A6xd7-* ziS~Ilif--qo{yAhQSD=Ly`t_)k@zAYo8OMsdYytc$%u}9fkkVUF#dZ+G~USl#jyj~ zWVZ8d#&l`6jprBe$4O)t9La0&UiVYNNXBjze16RbXfWI^+cq~onx$4|_ZFj-UbC10 zg@O`{wuu2z&&h!`?LzQXyn7^)!6WL-bMOV<nG&A^)DM4|$4YMV(0u_nqU{Qh>Sd8K z9+9r%G@=C0b^=U@<b6-gEC|PX>sYzd!xuWKH_FlGt4p`^%SB!2Cnf)~_8SWUsC30? z4%^?`&tI&j;cm0Rx*iHPgKBAs#7oENJXYCk=})44hx*)>oQ<X!q-6Fl?bY-8j7Lg9 zeFP=^ObLjvbv=}C^`AsTCjDky6CAH}R?>zZp~6yRKy9gMH_p#G8^H}s&f0V*@^GG@ zNj;|k60~URzPOlv>ajjMLSwt}n77tA(T~!Ewl-35&V`<@x~Ou2wR1r77_AL2<xO-e zhRff<5_mx-!%kd%&umhPEeD4^F9T&IKA1Wj@t1X+_8Po#IlBR(d0GbijrNs&@YD02 z{FS1yrDiP9Vtwo5*9#pr@m6~9<dKcr=VXDVs}85j@A)w%fn!kw(<bwIMi2%$I%ZpE zoN)wxE~@+(ajx`fUcaW_v}reRd3_qra=$;wU3ao|Axe$bXS_gXP7u&Upl~?gy9wzG zVUBy*B5{Yn^2heYCG-<4CG&pCBZp#jBk)+l@?$1>uIGz4yzk?gI`HmqUnC03^8hwo z%6-|5i%T}k>&0w!z9lHGXJ{rFBj?$yEDv#@E~}gn*9Z>09lhpgH#nS;Ez=M;ND!u> z7TjoLVq8QAaCx*Fd^}z+Jeb9}e|`L1bq<Gg@}xz*fHbyYQ4kh00awj3Zii*{!sTHJ z&q;ICT@NT(Hm?2cz3H_LnX`?i!%I-XU9W1g$Yhb%7RZ;A0vk|0K$F#4mtlTaKk?a2 z<4oRl53@Hwc^q>|9+wcaICf~}lII<801|kJCEaSC9p8aaBsQwONc8jJd9L183YtUT zI0LsXFbY)g<nF-Nk%b-FUF?b#J}-<9{{kwJJCAYnEU2J+PTzcovzfpBq*UVT@i`Aj z3IxZg@;=nZYo%=$7ZE_`6khqW+IR0%M)e<9>r>zv>TY*0$|3Z%gg_=iuc<fw+8$A0 zSo~X$@6=jh{2rZ~>R9uuN0&rqwY>w#2>TIxQd^VnBH)kDl@VWG;3l5AgV)(%A^b|R zN*%mk4MgZ0-2#%sVfuj$t5>o+3+X0o<>ovn5sbO|Z3Z<bFW8D~9z@|?xXWrJdS|MA zaZn{L;{*H79KyzwP{)rzJ^HLD*G|c+p<Y>cy-)_vaL3v)Lu<iwH^fDg;-(IdYt;*4 zCjQZ4Gm;GLo{UEemp6M2_0I1vtkej8K%Mb+0{WzyFZFobDk@si?$kP4S+bDdG6`P~ zrbdqq*oWjDnzlb~NQ2&4K~BU2!Z`X~Tyx29zwlkcxRMm(s4of}7JcQ)?egg847g+f zZLz0EO}x}y7`?X&O`O;SeSWWu)6Ig=Ki1g?#4p~UcWi_j+UKGQYS`C+9`+8SBvG?& zZs60rq7qSy+?R7d%TTp>WPh~*fkA<Xm0lg{^;o)l9UL1@$}>DnM9-P%8#82u2qu^1 zl^p0Yp!y3$?Hc#FhX^7e%M_k9TQ8q1T9^3(wn_@Q+o^;24~>=8O-FWojfiW@ap|Dv zebD$D^B+KMW@4QfRPuCZ@X!5C06eR9D;N7O-h8_f50m}@Mcemr<_YA_{GyZ00@P|F zV!(*$pyX`uZG{a|`zJEpM+sj#)(d@d31J#yL0N=GMe)+fx?bN4zx)Lo;D#2b<xyaW zznF_rmphT|JOC^mXm6t4za4b+b*q|AH9x|f5pkU=FVd9_Lz~sBE_f9L0xsp0x0jx- z?cJ(Al$(?<=_J$*Yg$pQKEQtGrE>nB+7y4m!;^AMfWs`4bsNES$<L#WtQ#%Ve=Z*l z=(XCmxzkSK_@%P+5--IF1NsPEy3b2P7-#kw&+?9PK0kQooKcIgq#br(M56(GY*0ou z*Sf3-AcA>t)sO77%#$yU)f0Z6M-W_Rx-rD6IWiP68RWV#*CC5pYb6&WUDk^=N&KwJ z!**L2xO<70IlWU|3He{dE#->lwLJ&|>@6B8KY?=hU(<^#H3#a4c)5EMDDn4&?urT$ zSe-;&M(kMCxZh%#7JzlAw|!VQYs0#RwMJJD)A>xi!9G+e)KtANE*&u->}{m2a+hEy zZEaaisUyq7bBAO1IJcz%x?Uw7n15vbWV-LA167Xu%NL18Z@*kEje&qsNpB;AeRSsZ zHLJy*@9@`T*Ud_2l`O>iG1y8yas<a%6DK+NLFSLd82bQUSG=MQaqB5&2H!j-X+#~K zgz+2!E%l2)*L*MT)0tlk8-S=46kkn2o*EF=@gc{X_G(|5SeRg!_t-h;b#TEAuTLcB z!m9umarGY0H%;HdI*RisRcvIw4fhLu;kw&2Ojz#WU02IUgqkcV3nMWRbW@j}5W>5Y zX|{Kkl71ig`XR6PMw6ubV0+^uI|b)Y>QCOve?zHVC2Y1%j>6XvWtHo4u`8B=eN{DP zcrNbW*|mF?skH0gAZ8N6sK@8|M0ZAVO)B6$hPcpfL|3Po((1u=PTq(`f5WqKT-hG| zvwM2&aTy>zkL$Z1F*3ptR3_mUU#@@b7q*Jm3-fE$0*QRjH;LE_Zn3!MRAMmN5HL6H zlP|$@1NA81{Ye=8qPfK<n*s(pdM&#tbc~%9NnkjdN6h@abE8cI&@Fd`!1apUCz@bU z)uX<{S>nOJre67Zycx@-FF8Z|7!CMhwDN@Y(x#gDF#8|yZ)|eV4s0BYN4?^Z?vNSZ zxv)*QwyG{Dr}!OZ42e_TZI8hN(o=wtJ}&QP4JvwY^NrF8&tf!cWodJ`Cl*m?%h2_M z^AM<n9}i}DH6{PSSo2~?<rfpYkgt3Pzk@0M0~w1Y8FQ1vx_~tssQ!tDiqZqg`Sn!X zJ-}onxj(gACH`g4;T;y2hP?#mpQVP<Tc^Y%g%v>>RPq2FP?5TlxzMqT@V_7)4OI(& zzZxjeS|4faemh!LXL?fp?O%-!2v_l`I@7B&Qw3KjtI4r1N|?gsrZPnVX7@fZGeK{c z<oJ$ERKYmS{F74x_^)QD=s}z7u_UK|0H9RqIS1o}W=NMGC8-iX;fA(j1bUoT%PZtD zv*<wa&fFs})v6;NPFYK?@PI2)^M>d1v-2*xBu~viAPJEc@;{##?9+cA+)(oFP2En8 z9~ktDu*W#<t4$y4wAUPOe^F%;bF=&^P9ep9Z&y&q#}^cRY)@QrvyeZd>Sx5$dUzV~ z?qF!L)=s<uL#`CHCji*qXa5JffWiqFKs5cme>g;x)Ba9YP=4Bo6uOYgk^TcbdJynC zc?Vd63-{%L26jf7ZpPm^19vdVJpjf8{Nh0Dx!-v$%=uG+oddakB1q~*_I7sQ|C<T_ zPTvAZBTUCM1V+C8!WHjW=EVJke+iiVK3)<cl)Zb4Ly}vX&yQ`-iTs_o)xlqN<6l`U z|G$w;{*9aTf24B#Qnz9JvB&JZE~6tu?+1J9k`-AdUvoAr#S@_PYNY}z<$h;cP)`cV zCVDsnM6TD7%tA{pe32Y(ToDLsmoAmU+RvN~rAV01f{xqWgWcGYS5QyPV`Lj^GQ0?8 zxj?n8+4NDr)W$R(@}koHNTU!}Q~$V}Mg!xQ6Z3|xF@Jb?&1Q#ek_4Kgbhq79FeY{a z6<e}ch+m2IC|gmmeA+vH|32UC(R06VU8u;^dG*GS&c&MI8h1UjWDj;n-KQg8#S&%X zdz^Z!T<6?Z)g5sA`9Nm~+l+7b`L*X$n(AL0{B35Ns^Fk_HtR<C#0O_QtyAH6z|qI2 z9!{k=Vf%LTvmyZym1@-5Xp4K;@5k4tt4gGo<GFKpu~IYnH}tFP!ehtNCZ(}tud+E6 zCvHW{OR$`aCI6&0kERMzZh-Z8eI+Gvgo8|5?m#eB*d(pgYj?P=d7_nHls+^GcrCJv zU|oo|8+7TUuCjE%Y@0$&VoLPG+0?9)Z4Q)hHFSSq)g){ey(fYcUq`02tD#=%!!w@^ zt?}58zfdP7rIOOU&O*DRoaRe&yje9BS1^4QpE9+riAHcF9TH77Curmr)tp><!9EF6 z|MZN*$fpjcjTN{~`1=<GP`>h8^f?lm@1vpzhs=+J9W%va<JOV&VV~IVeZH+xZ&7(Z zOnZuRQDlWjTQ3eWmt3B5BN0$HojOoW4Ghb{*=F<^z$;e!<ou3IOQ5jI5BlM%jg05& z|N5Om*bnf8m=>W0i$i8{9%)oKY}sxVi3na-`m!0yh>dXO@`V&kYC%#xgu{*TWg;Z3 zzU9-$wW2j>BVmjE&U(NkNG?dSfl%Zd7+3T9>Eh<DgY4~4F?!MAI6g-=+24<{-Kx$d zn@rf%-El-RBeea27EYM&OYftAOX6L}u&gyJ|HPu_y9l)%5;>Qshz^h(r#P{_Hq|0j z`Xq%T-J*Mrk!+&(4^iU%L6OW}?S<qR3|4g1la!wgFFP;?MK0Fv6Xzb98era(5Gri~ zpu}3`14TZ%VafwjqBX}1tf1~<NV?Mdcg4cB4$~Pq>0@*i*dMLyNy>c5El&@P*kBS? z!@@uBsUQE8v;VBdBr!vH6%ZwTj#x4423Pz`9*0M-y~eRn6b?!zTs#kGysM|$IuDeJ z(a%soMhvw_QT=%aSC^n3vy1N~`!V%;w$?)nNC|+)OoFQkK;8#eCDjAUa*E60V?CM+ zS;vk%t0n^DmNCd1jUjwG<AnvB1Fe?aum$h4ipdzk)f<Db8~p6lHuW$h&ohmTqJ?~y zm!onfipyDsgVbs_Ka#TtGw&5NZmJ?)F5GSa<)jf84G(X<)w#9=)$|!F!38yWctE2W zY9s=fpxI1reC$TViZsq0Bc^}PbNy6^xM#O9KRfrknSL)S!i76H<uwP9lS*vAMnW=4 z){X_PY4Ca&kKM^5m&BTqo5z)(2c76Xbb{hdwg}^EdWAQjS;`GPuM5^s9CAIwte!(5 zX|<`x4sKZ&@pWOy8Zd}u2dU5jgX;^5A}l9fB+;5x<|7|G!(<rf^N6O1&}H?I^1Dgg zvkgajd1-Oj1=@I=yj-w_1zdtV6LXEVtS!FPVMq`cL{ZW2`LqC&&&ScIO_A3oiFcOS zyaEUpZp~}%FcR-rX~hvGSQh+ZvYz?gi`GhO9vy+H8)2#iU)M)~g%CZGV2IE}SU7IF zA+2KD+?imjbE$8vQbPha;!6I*@EtwX(@nB?hgw=R&(LtrtWn~x3iU`6#JN~sUb;1k z9nO2LgcFPBY>2Khd9_zyvv~0R-uHvx7Uro-lfDofhm7#XhsK~PwY`R>n6SGiXsTsa z(M8RLE|y~lzlo5psvJn~l@^C0M{Sj*%a~7+D;6ZN@3KzRd?55Tdpz`S-5SB7xP6mB z3wjYo=sr(vbkW9+ix>xY?YN~)xdT<qA~#rFt61<T=m&8lQMvUnY^x&GP@vl~33&<Z z^I<$Ni=zlz$_eA<2k9n#X(&>7_EtR2neSTK(g^6~9(6a9XOBY8fY(C{CLR|)e*ExS z37G19sEA4qs4=@qQbvMC0xJ%4kk>17tEk+=SZOR6!yr91xh;FE#BEmV=?SZ7Bp8}} z(z=$JZWQ)3%b>5GzijNLAgbUCy;OL7=!~z7-)S|OknuY0DK~5E%#k2zn>>-HN)#rl zX&jyvG%uBIq<EXjQKF%PkY!IofPYd5{EiZbtu30x2|KZp6_a)Y%Y{rPkZw@C6a~Zx z%?Q9q>bS=TsROQS->RiR8V;5r*28siHRoO&v;(|AIvN?)5?{g-3NPecIePyzFbxIv zSgr*#?0NDKR?6<vVZr@%?b7%fclnSXoD7wGa#N=^YiflUhUY!9`8b+jd^2tf5kQ{r z21Am~O?+>$^pn{KTw-ao+4sKgHw3`ygJs<aE~sEmYT`Ry@2ky2yT7+qRTxxADlQn) z9;m`KOSB3FEAg%{gC{t8kztm55$zy`j)=+EmCB#WL~9#g>7|}F>jS29693^JWQ=pL zG^e26;4N`}J`V8&GzDz^um!vBCvo<|{B&~IF24LD<wW=1-Xnk~*w{I_Qd@N;7i-Ga zt*uv7Q1PS{WV(tftGWWv?HuHV%<fK_<<0LPdjB%8*t;}Sp;kOSvotW3bTSyg@f^(c z5zS4!F5*SFE<+k%eas!Qv;<{Re7?8rS9>78sM@2lt&{4tb|TpH4k1X>)CKex8X7zC z%-NaX#UeC|zZ^<PTJBxQ9tjj0T7$rG#(N);erti()}d4^CS9?_9nWCxm%Q}v-+KZy z^hI#{|L-FJcGn61mDP8H_GR#sMtf>vmeo|-aOiY&7UBG5cApC#+}~OiWT$NmWJ*a% zhr{nk?rwhi#<AT>4Ti8J9dehsSgK-q@O7cci97KPL?HKfNY|h`YI1;Bz^SxZKVPO5 zo)#lJr(NhKlaGTWOvpm?@2a>3Nu4;T>XWz#W|eZ>$5}sp9U#XQ4#6?fG;}~znMk@1 zAJ_gJ3Z-z`Kkl%P(ZC3~$Ku$#OmH=nj9m<o*Nw*Bz6y9I8x4SPuM!AMVyGV_=HD3o zWS|%Y!U__iVlTx>81<6fSgh0Clo~eZwAcYE<!1Wo2V!0W49Vi5unGSb@?hqq;%R6+ zV`M8OST5q3%N^E8P)2K713VwxC^!~cy@co~ZtAQ`h2R2^PJDuGoZWVWw<{XTk@O++ zk=3&c9k3G%ecTO<a5&J(M7YZvVrU)@0ShEH*GFmNKZ|hwV#sBBoTga+eJwu(l-N^+ z#&jrv5~x~xBlFT5lJ^?9%Q!5rNF}9B`%z5QQ7jh4QP*c9EVF%H33JYOM<SIu@rMLt zWI2d`?5ic?NAV<2ed9_mPKWywI>8+%f@MUf)iM+xa0M8(#BMi{1mSoo$GU#^LA3<X zoXG|YcF9R+3WscXo9c&Y?Qeg_9G%>tfASplcOy$V+0V%Ej~8^u0#r03iIaH<&EYje z`$%kSvxg(+;p?ZtSK=Xa$}$^UAw2vGQwP5Ci%%<#lIvBy1Lt~hR}N5t`d4Y>gm#^T z&}hmaAplg?>nkdWY&W7%G?xQMAervF-<NPVIUBye5DVGg`rI~E5emUk1(n!rog~WW zuo0BVjCby1tqopYUM@2LSJS#2JIJWE*`9;>^o>G!?#2X4|4jaXV5aqlA=9x;Kj&mV zQ)Z-h_8sVv(c;&7$d*aVvcJrb^Nh0dq5+TA>JdRIM4(JzN~UKs>4bL+A^w)YAp8q2 znc!H!!v&h4cG9Wz_!a0x@Lt&My`$y>p49WVOf%i7NCC127JKm!9flM{i{W9bXmV-~ z+yjo$9|vHg_r@M^o9(^QCFs`EriGwKe}@*p!1SkK#y@tS1n1%gJF@*qd7QL;yy;<_ z(;=-|j-~@c3=7V2f6+VmK-4$rBi}9NrPK{gq?3MOwBLt4{{STAOeD7ib&DE45Xkh# z3vMASl9hKiX&npYlfpnx42>Is`ZMsJVFsgSn*~Xt9>m8zkpH^<7i2f+$h2yxsACJC zio(^@BFW6k`8tx@kLp;xX34fSzcyfx(Kna&NxW@$uffBbjSOZPuKZeIU#-7>dhz_D z*B~8uK@=h<=WVM8P!846d{>XQ)aZ5T!|T6qnZVi=TI@(Q0Pbx9@}tnq0yhG<7u(D9 zE%t6$tt)zy0>c-5itYmgBFKQpTM=>{ENJvt56bz7Xv$ZGlL^3^{VnQ!t5@&NE(8oT zvz*9fKsYd_e_`XM<RlSB__}*FLL7$A;zJ;OzWeeLCe9)dXiQxD93O>f$(kUtKYS)9 zh<iN0xR>Zx{4irUtq+`9&i^;@E0qG==cSs_uCn3>ne_+Lb=J=a``QMlp`rI?c|YZH zBuX!b!)CRU&|DGs#&zV&$QS(HPOR14g0-8$q<hlHE{{vs?aoSy2fWOVCmJra5=abb zr#wk|K=|I1ZSvcCp=!flc0@A!6<Vu-t=pw6*juKG?#}?6L3hK;*D9R!a-pA#r{BR0 zkHEf_RlLo&t{bXxYfL>2@q6Zwn1fD<4q<FxMfIxTAlmSiOFY4OHKkfnEt|IXEe=@G zYtZiBf&3RZnUwA^7lTAStJk%L!o;1F;nC(mzJkfDzwrQoe|}}BW5TbQXaApMr}m*^ zK;~Ewu#v+T{{f#|E>Sy2Q4F`_HV9~Sm$m|;@u;(}>LS<KbJ~~+pU%gw<YHp?JBYa7 zUzr6cXH;jy<B2Y_hl;NMcr@FM=y~&te=s&q&vzU6w)9q7u~Y)NK6wvmXonb&)T3Xb zWY(F@G9+%g?Pw!Yfs@&NY{3RP@u<)nkZ|go*7l&6uT?yd2v=awqR#waluy8BLHu{{ zVi!8y=qFg_#6uG$0mM+B-5GJ0(fAC@w1O;}>))(E0d?*Tg}eJEz?%3{a-b9Qn|O1* zJxHcn7R(bN9M8u+6KmDhal$KFHDvo5IfpBn+lWgJ9C-FugNr{DzJGlXw5J_%ybZ#( z_BD?^N!T&&(@^P~7=%G~?Kk1o?ZkiPzRKqRBlk_Y|9kFR5xo+jK72&)KT!ZY-r3&t z;r`G?1wYVi^#eVxMD#upO!G7vuS-=WIW%SA?Vk0OZcrfM!rd+|#7@~XK6w6>6(`&{ zSF{La;!e)AGPkgXcwg7)03G4FLBUFYNOYYV%v<_JO>0nGs*aT7Xxhbfcc4w?Ii?s% zA;hfMm|!8(ZS16t3$^LDe`Wl%2Lzb|Ir$639X9*PLb#s~$ud;LKvZ4>ddB2`Xixzx zf>O#xh;qjk%J#2nDtwC!b`gaFJte*Enpc{xU2bW5^QWwKhbriDJtU06$DQ0U9pHI9 z5Bk1VXoX&cXzrl){!mhz8?K_5lzC2UyT|<5@WRB_RlCQ+HQA3BU!6FZy-N)yrF4zK zn#v_g^jOwsLO5V$3kp)V@wD~3TpcEQ=@1T`hK|yrW3+ehpQ{};WuhnrO1)J7ybgEZ zfjRqsm(vnqQ6E{A#kv|xr=KQ6HeOZMA)UdL@L^t>aeq3>zfX~j;%N&3(83eovVXbh z$GUU@0-(B)FK)fTp=$6b=`c3H+zj`OC1t{qJzTE3Wy(n_Zm(u{nF_FAt?8Sc%H9No zpaLViL2vk0Z3G4_O<*TI8{9{JNON$(;1D1op%3(N$R>tvcgw?Cdp;lX=)te^>Tulq z#OJYen!%b6Gif1_mee0VejDBy6ysXYD$CjJ<5~&1M>0eh_lWXnXlg&t^pidL6jX)y z<wB)@`&ie_dPeNZGW6iX;QHOAr`piw$TuDwp?mMrmC9oKg2YdS7o`YG(@#Y*0rT8| z8djnEN2aI`RJZW7cO5<)CpBiTvr~>3#Kb2aef(-upr|+E1?XhDo_&v$l!&N?gb82; z3W~gUK=Btm^WHDmP|!s~^q&B4kt512_aY<{I6k@Fa?cG0TfrdC0mS&))-@EE;c($D zteHGHtPdQJB+hWPx_#}-L-u%~mNh3B8a_;>Nh;{}-7*tDbq1WAFhOgxdJd3CQ{g+3 zoCPNR3?JI@Jy5SF%@`?IYLK&0Z|K~By!f>%1Dr#IQfql{@OSE3Il4r`Q=9ohTu>cx z&?2Xrd~zd;o;&U1<B22vPxhB!NANHV-tFNFHk(8}vr5B?Nx+f$XXG$zKMhav2f17> zqvhZD@=(rcA`kd_YNBLNhLgQ{7f&3ndZm=-8hG%^xygQQGq@vwRoP-bM!#X~vXeVe zt_v;Ozn1IBz6@=YS4DDH-G44I17%wSKl22jU^C_Ko%3edvX8q#ocDlaLmWQLKQ^%T zgCf7dbtDK=0LUOJ9jJQvhRmy}M|X1;D9ZOH%}nEG=Wf7Q*+-I3&SOpzkk1M?2@S@m z!7zAkV(Pot^_H&4!e2?NrL&KX1;sUe)m!^!_r>~3AYaya<K&K$qTzdt-$n!P(JS{f z@&hi=7bLU7)Rz&Q`L+>cy!yjyK++0#O<vb8D)R8qxpr>|rt<`G(vT)Mhhgt!z$ZCO zB*Hd9U}A_rBPdYKKBmk4(f%-Dl2+Fmoy_OCmh?0;VpZ-j?hkUmVsFb?`JZGcpx>E- zGukMI0OZC-*Z=8f)lA0iKEEViw|dp^3%zNu`ha$J8%;a0Z4(Gmr7;f5<5<4W-wa|w ztI4>d-bMqJ&YA~v&@AHboz>fAIma~*oe!$A9cwew_Q}#TN+25wEo%?JkUMEE7LA_i zNUb=@`HF;>d*@X!H*ROvMlj8~!wifp-t6k68ty^Bcx4TmXr*QfK!GST)kfgRu#P4< zp(tWW-|zb(g@;|A;B+)Vv9k#w2@@LHN9o@#n2?Kva2Qcd4STv=<Va5S5I<s(u(!st zR4+V|7q$;VPCXeOYwZSlV{&++=S+Sj5mJGtZ8kvJcfnft!M1Eowzaogn)DbVgZaob zaM#jhoF^tnS4Fv9t${~*WzmJiK+DuMYCfc>!Hvi;2~ue(tQ!KU+`Q_@qanYdCeL~c zKOUBthjaOrgn~Ve4^_YuS|X8jvnuwl#-%?m7lY}ZeB+41s^7MuGri@85B)Zd?tE_v zycU}}R=DO$v&ta!@@&svIzn#=9G&gAkV$#H2l`>w9Xo!NqvuiZ0m|=2GgIjy;#Pk% z&wne}E9s}wcy%@fzZzc`^C9~Fv^O~~eirH^JhsY*cOI++M&1d;(On<C+aT1uwke|y zk`)MFXEj)aR&m!R&-cHX2_WOr;fxey%Jhb8m{f|49$UT^q7}!nQw!gIjKMdr2^^yD z+l?xghd`V=r5`uruqlp@1vvEoTN9O``}tA+qrsbN1hn5K62?6Bs5}I0ve_cwbcE{5 zmh+6hu_#GxBC7_z?=P@B`@b_x!tX@d5R>I#&Kam2I;jbDDFv56wRLiywf=UHL>FL9 z8qa8j0TRq<d%0J3zw*nvI6J}FOpsvh`-JsZCuk77I7_jB{IVw}7W(FLi>C@+EII^P zdlba|eqYSlyb$&G#qm2ODq$5`#Zx=6W(6bjS+LTyj{TnNbc{Cjy}N0=cf}vu;tSbm zqB)6^zN-4=8R(%cX23kE#v7u~pm3xPqjTp7&RRx20@EDu<n`BA1iE`h;8JwUAvj3g z{cVTOFGP}_M`K-Vui#P#KzPu5j}4Z#Ra(D=o2xay9z=oI)St)lAB2#_L)0cCm+II1 za^3lby4<D8K3Ks?nR!ygJ#|1TMs;bDXBX}9)QZ+-FW?JEZa4G0P*X<9oQ6M&g~IL` z;IWZeXuuTSekZO!41NnH_w3-A`#~325w=4$za$hV0a$qAAK9<DEq9{8WRyhpT6KWv z+}cXb*UcjZN4JMY;(w=I+>NJK>_5`3Gn)+V)QL42+K{tBqFa$}oiB?v8ID_4w;92L zYUo-po){p9!CJ94^N9iIz51zy33)N+gX>KI6ZOm+j~Jxf_ViZ&&txzv(|G0!h$azg zlMdQU@KATep^AD0m~@=XzjN~Iuzp`P`i7yRoL*m&@~ToeSbKu|Pi;5<w=<^-6hnR{ zf84c*wTHx?6q&~T;52`ye};1H2jRUeW?1qv9U&>a?nf8($&-Cf7@p)9Jqo5g5hb8w zyZsFR&@b}DIr|Vr4_t4l!DLf>X$)>eJ1@k(FnG)YQdv%HJjamWJ;dr2blqJAUI|8- zW48u4y>Ai-&JY#}CYZxBAvpg7N8XP8-+OA01%C5trXNdbo!K5kc3L&*C3hujUSy}` zEzX_V=<m}%^FF7vHliKP)=QkKsXx-b^dD&-E9c%_$pEHZ1YJJX3`X|kTO?#M?&`2$ zvfivHg!RP%Gi;r50_eR8PNZvJ%)2r~%acMcu?)I=;vm<rPOG2^yoT4IBU>lJU&3E6 zXI<;as28ims!YZSMJ~{`9UB)`FeO5aqCgv~cW(aY@iBc`ZaI}-2yhp-vQL`@^1bT6 zIV?aeNls!aRsP{NqbEi?#@_QHg}ghFWF^DJl5)}ThbF%#dCgVRMal^q7H^-mUqAn- z@tVz&^Dv9SyXp&>M=uJUT4t-aqunE5cO~w};>j;PB)wzl=J@301IG=v?9F>d4pYO< z*ozN>d&*X+RhieBe9Tb5k|&Bc`}i;<VN6UQ$JmKUBT#1sHTj^!!%;i@mo;IDQ{WtU zNqsr39vCj`s3dx%={@3*YyAl>O9CY%a>bfwVn@C@aqWL`zEF%#?f4*;Qg~BMJd2QV zW2W1YaqDeO`j`IQ45KHi`G6dsM?e-qYzQ%*lg-VWbT($J!vQw*fJl+iGUe31q>w}W zJd%QegsBAc-}I}1^#0($lpvjnTbQhq)+bR8M|W0{&A1tG>Kw+HZXXxwr2qHb?0zca z?4M&J48W3!^Y8n5qVqgbrPWZmr(o@1^eMUFXDB;WM{Vw}y4lN}2dK*hsSo}Dz2p9% zm;%f^(XuMUgITcr2S)Aphx|zEF!xICP{&r65UPgZM<4hL!r#GjU}TrM@nV7<!fmv3 z#}hApVDLnLz~Dda76l6SabFN`7YwNUQGM)_`U4Yy-J@XUs-sJ}!^O@g%P;;_QlsYy zJeHNn<|ki(@4r{z-<l;oT<~j&$=+E~t|SXn0KRqQ_a7lqoZ?|tO}_r#m|^{Ig2SI@ zM~w^h;l5vM^6wLSkSEsY;8gOHIKcRaY%s3jfy}=tTm0ji{2j#nM|tQEJNVxa{QtTX zMgO<mgjWJ%mSBg)B!D*a=y$;LA5mb4XKP{bB8|19Km4JjDj*#}DFtu*!`^;ykIqh9 z$bMn1fVWg8@k)DS)fZJ*S@=-9^Z%mjJ)@e6x^7`RiUKMk9h4#h0@6ECL69!JgBW^; zP^5&Yh;&eT3!!%iNDWm*Kx*hn2PpwU51|B-e8=Z`-*4O>_vRlXgL6*KUVHDg=bCHI zG)BZ{bvC<|V*5yUw}9z-(U0OLt?35Ki~8&1(OYkOR4$J~SiZ^G=Dr=)mAF^KH*p&( zQ!pL;@@jADSI=h&mo54I*R(aoi(<8ZA1W!*QKo!_G|AZ6ZE0!!GbgmO(nBxwlU$Ap z0FMLqsk{F-Ndw^7{xO2SVj|bP8u~Xshe8-NQ@J#6d>D-XBKo&;1;HPuyLplrWBsr9 zI5;$;zqBz<wKa1b$IB=S6m3+aGPVrZ4*C)2qmBV}Zek)v75B-R1fAev*Z(8*93=i* zXLWwBmnyf71$x)bEFzK7X^e${1RKVCPMofCx*@+1KrAM0PIXl$GEE;GCXbG?fb{^u z;>JI<V(N0DX1Q8D3<+b365LBVthOX+KEp??MUz+rv(R$thC$G#OJ-8NvtblWOTx&y z>2ruEXWqtn(0f=gbP&<o{{O@O|Eq;$emV1dD2V4J<mMTsOEDXwW(r6okfg`CwX}`9 z3r{d6j<N>Hk2y2xY}qxDkHLUgarrH%X}xRcevdXS5qEE)Y^+0)Q!`ca)n-sxW=H-` zm<s#<Ir75)t%^-vkTw4e=`0@<*g{k+-CnoZa^pKdn*`T=6xO1Obo&L;?x`<aO4X+E zZFyoD5YSZ(ln;t{^8MBkHRn!Hv0;$PT?L;ZUGd<MmCWQ=$}ka{|Hob4lKhXhkVTqW z_aa(hPb;3u|MQSwyCg4b{4LttDR}vbri?o<fV$#j2y2%R|G@6y;;6o?yr=>-0AEoe z2Cp}Xaj%a=pZxCsorB~A@C?<hs)}>jB*d6!R+3>MpY`3Xd{?(z(YROeN;<ZW{Z835 z?7xVB!NkOZ%NLWP0RI1~=>lu<{~8?@hA(KeL})RrrNSz2^H|UhWD3OG{JwIw-1`Mq zIRjE5A}9cGO!@Hm$wEw8n|eux(GmJSl4}FeF^3rb?jYF*(vCRhOWVpVpZ;bfJR#|W z#i8+a_~*0#BhV1>@&5lNv7dhbSGNjSk;OAVR^I!&W${lMC9S4l|Mq(L(A4M0WMxBA z%>8JX1QI@g%-rz7mPc0t1-1K)Q@#6W;0<*3CB_7asJ@ya-(N>ymqUQwgf;}LlW*P> zlU?g(h2H<7*SBxp`!8On-zNP#;Hq_nZRzOB4Lt*w38jM=uLCqrhh&eN;>m5GQr3R# z6xk`j&)!-iWKY6e0?b2Le9{oer*-M;2#g5{vprBLHZ$X5)9NE5V_g-N5hKF9oU%HQ zEXw?5qO&|?>g^AeVO_rVPbM@qFZ(}tNopsv*iE2JwGSq17y?@xO(x$61!Tm$Dc~$a ztEc13ZG#9!<I7$4I#z`@2L$Nv8K;ZG|Kbzz(sdQ3woR{}lvRwt!m8p5hSwPuJRa6t zWP<0o!R^W!0=5&9>*)1g;Xb*Y7k{Kv-(%1~Cew7;-<BQ8`MG%QNxJ+XF+?QKp~)<k z^6V+Q@>40*T!pwd?9ST|mCv>|ov5aJ20n#k&W~})OOKz#yBn)L$!x9&j)+SJ&+Lt1 zyGhA0)+%<L+1VPKvkbb+qm^R;vr;M;M|*1QH@a>f=k}&Ck<T5B#Rbc<^C_e!nzVET z(FgO0Hb)}k-CgZ((KE*nGc)|xzf0XxA9Km<gQCux;tpz)#xZ-kqdeQ$LbUAFgV6?3 z3Vk99ODz1FMLYVI5{@b(m`avd8?#EZA|x&je1}k@(MdYYS$lrS$1<ODX#cSCGTk6@ zcx*}@9F$yedH8T0J~8p)xmn0T-MEzW%;wh#OsMpFhjd>qQLVxzZIQ55uVz`U{Oud_ z)l!j9u`$`;JFRzJUmosFo_^TJLm6<wjw$7&L;E)Z^tXYfCYShMv<g7uLIAXCO_4nN z>$Zcsdg%jl<|;yf)4@03#Z!QZFQAzDh<i_C0b}y~17!kN94t06>FUm4?>a<>B%P-5 zh%pY1pB^YY!#n{2j?%ic>|E#nQFV||QIdSIA?Tu4W7Z$+c9df^FA4agyxX~=e(Vr- zh5e;^i6|zmqPt>Ne19N;8>#Zupimz@KE8?i5I`*wIOUQ%MHxJE(atPY-r6_c3i8^N z$~_hCUjJNRS@dB=7EOPa=nOiA@g)R(?dp!GtdyW*cSft)aa+oqVU|e2G5}zR0)mu~ z_tyxXjnU9^>+CU>s5hChE5<3LKOookU~Au^DeB+^-L!^&L9v;q#r9QG^8GR4Zg$KW za82ZVUY4UBIs@Lj4P!Ghf4fjiY7C%0v^}z>W&zjh#!@zj2F9;u*J?K>lZI_2dbaGh ze8wg=4pF6KK$L`o+Hk@g8uFDTgkcKdro=Aq;H&h&w{#>$@inTVS&IJXRgk_62mMf3 zxV%(hK}UmE)i*H%H*r~k#|bX07B%W9!xj66+JIokqmNTdZT%uFgp%hU!qN&lJ_h(| z>K{B=Mv#Zi+-oxW=U0BQFqbc+K~Q3d<3s0UyL8PP(*eJ>9L&ud4NPEaMj=rsQ^Uu& zhxXm8<|PM1NuG_#*6gh0Vo~q`t%B*iOLuMkd|X4FV(xdGIe*ucaW}+cy>vdBv<jv~ z#zA9wrbPe#E#oeMTy{`DFMc~I`wz0;QtYgHD)RA<ZIQ~d0{2=0TudC8VHCfV9nY(= zYa1dm^BUq9fMjFuDC>U&v6hPxN-W1=1&*p~Rm_T@hmBJ^KfLE6`Fl3@>+f5)4=yjw zrP0j<WRQ?1eb;S<hqt1gT$5zlC9LkZ=YyS3T-7HtcOjaM-;t-*rc?!B!UZd{B}4j0 zOwb5qeznw6?~`A({u#&vpAdY;DL>{zgysZp@>K6HwqY5;&Hl}mk;1D!tDpWK=k<S& z6hOG!{1f$fIrzIm*vB+A4(yim*-G&bU|cfw)lQgS^X}l_?YILp9p$H3&wyzLiB6D; zI8TB)SHe>?WvN=g@|R4Kw0^T~XZ+o^$K=eq3|slkBndaoV?e6a<FQ>nm62x9mpycA zqgl)F8rNTjKi{LSOFq|=i=KwBq(Dv<h(QAdvZL;eQ7wXxA$PUFSN!0Csqpp56t}w| zu)ow}l%MH}E+Z866|IMMw1X+zmajEf+<k~+)augV!)d#HLTVrSqfEOniM0WP-#=Ey z{9<tRy{F<!X&W3Z5)du>ml#s7=GP1>2rRRg5HAX}(y@!F)wVEGA=JC=xym~oB~D#j zZ~U>o+PoKNi~7<0a30-JB%qC%Yn!z{y5YOecFi^D%_HrnXF^;ZC1Y!E&p-R~ZZpIz zw$f1rCrqKn{3WQ8CXjb&z-8Y(?Z^?ft-`{C*i(`2bYe*QWU28uM|kK+JwVF|-H?}J zqmhp6rfhhi-Af31T3_MxDafw|&cHs24m>x9&LXAL!Y(nVv#!M%IkpFXy6b-h8u0oB zpWQIk4~9CQ26tztp^107{5)PQ!Gl`F@FHn#>q#0+xNPjxGryH>ndh`o5ML|C#E8wb zm6Va$KitJUGzCy{a+#qqI*p~<^Q3x}fm>2R@=O5~ovk3|fPHPHt-q!!7@^XIcf3l- z30IfJn_a6xx)U|*emmc?P^q+|xJs0sImWy^;&v+2Uuz#G>7?;g#j4mQMjR2n1@-vz zy`P2(_IFWKPhh)1n}aAAt$nwy#v1uY<pR*Bd6L~fRXkaeIo*B5mipBggyPz+aqpAp zG5BIPPbuc19PZ8!y&8l4z=E57uFqkEYj1rLY0MYUTVzje6nAjjuHpWM*((YH<ozzX zq76jzDC_TbM|GnJiKT+yY_7|5fys88;E@4p4_=$h{5fnD>5d?G#?Ehonz9swXy<&l zIvFfk-OEIcHe?w(Dn8b`;a%lvYkeA1PH*Z}Fel4sI8tZ?k4*@)RoI8r$1YwR+S!_{ zlT-FSwC`>GHQrVIq9yAXP|WST7xM^X+(y4+tIcz@Puv^)s&fG^b^mX=xy%%~tD)#D zba<qHq+L|Bj|(?)YZ5s?`t|bNtG!0Zlesh5$)<JYd?72<Ne@G}uh-N5<v#Zx|2N6B z3raYVq&5t0cyoXciJ8IF@1aG#8k@OlF8MPEisI<heH;W<5qc@<`Q8R(7sh41dezXz zSwJyIbq<-v==u^G{vw65(56A0^YLp5LmjNYZ^iaGWa7F;kAiW}aw<#>^U%4;PJHZl z!dIHRq^YM`3Dw%n<EeTaHXL8QBs=pC0`9Ccpb|v~NHNW426}vt?fux}YW-R*ytdY` zQ#|`RTIBPTcWDHv&dG$$m@|%NY$`r%ar^7h6bjv2l2Tz7K|NhW2)kQP(c+L+wgCOe zIjt!y@ecF*i;Yya!imdL{bUyuJsfr2{_Zu3op1p%ug*u?MAK8y*uZ7EA`gG*&;I1C zy8&A<A5I09+RO;q&Xd*Eb-zIDVP*;qZ?~+p$g>F)9H5t_<g3DMCA$E-Eh|$E0XC{X zNY0}rc)GNmU_|Qi5d7jBTbgSa>%m#Qk|}Y|<SBZVZi3dA3aDAwBZc&Ev$op}TP{u; zggtTSpYfC)fEvT8Q%FsnmlZ`z7#ohcy#HV_Su{Lz>v#VXII6uPb_b)*){7G|isQ$D zoq`j~G}$s?f>3#4R+_|T$12gRJ)h`VrIkNB{mCFmwBhp$f*o{=$A|VXtC{C^WRBMm zc`LiSME~fBlqY)Z1ykP?<j<My-Q3&TM6<T3?M@>5k8W&D+a{vl%GnBH9wuUOX>ukR zA4LHBq(o1u?M_E8S#aI;nsv)c9njzA?8}#`ypv8Y(~3lD3RvhWtgTSSX{k_Kd5h1- zbzd~v<I3IHpSp@Y@vHn$c1mLDW~3+W<$ME*3Sd|;E8@h#ee=fLL4Zaojnq(VF9{V* z1vTTz-(KX9nx8uPv&|QyB-nLYucZ-`2v|wEJmZ!ugbKO$811$0$KC(y1sBbgJw)3R z5PU8jv%w*Hjr}0^Z4iMI;ntVe<&k3bcWNIM<S+1(vqF{Sn`$jLP@s77`@i+AvC~J7 zjrulJ#s3zhFJ@te9*q{3KGL*RrY1ikoBO=6*Jn-!Ov-JlS9Ua1y*bnNaumoeQ^``& zi*<YxKum?QaO#b0YEz%|*Sg|f{{Wf2^<Y{F5&N&nO@op8m>C4H{$v2;r}%q7_NN%` zaO*SahT1Zbw}T#T;a^Wub0A_n2#PZ?UYaUB9kb<rL2I_GP&N4*qkqqFg`ZSGktUmc z)oqD{u&d*M+8<fbVai!-DffVbyv2p{&kS+H%`0rwVvQS24?vQ`pyTCt7NOi3AEjIR zG1==Y0O@*fZ$@GQ^G})pv2gP|bIBqso&Kj%MK^L9);T!wTnjL1khu*zF<<;^+6_A1 zKlLr-(8}94$xu9hejChAus2$}&~6pBf{nnT5ro7`W;pLfZ;pp(rEi)mk$zW+{_zmL zO|&UX$??W}PVc_T{$RO}{#h1U$t7{2>nj&O`B}1>BP<^5B&>*epc0*dc42fNj%DR4 zbprsf4z6bXxYNQUIu#T39erbh_yMLons#$q`qPvOj%OUyJQtC*wKZ7<lmqUZO2^Si z#2jOI<N}+fQ(R=pEpn4HG>sy%D~MgqpfS#4T6qit)@^L@3l|!CJ-97a<y}KJ5ppt2 zJfB#uKbgeF%Srlwu(i*ccIj*wmmY6>4#YtC)erxHjR*GHDqa9$IfNJ4p|^1Y3#S;Z z^Y@3ZxAvLD+nAobm3{Hs@=-8e|LysNCfA|Eb3oLPcKPj&8Cd~M#CZf~knawJGD20} zbSbDPHTKg1hdt}-l_~pniho^Mqw|}R6RE?VGHKDXuR~sIyx`4@F_+=UN(U-YBtQM{ zoN{M>LZQ(Bir<30+#dsVR&~f!1Aq|i+%>nNQXeVVoyFsm1<dHq)*3XrheUNO%`pz5 z;S%U@zD3ggL9lfQkZHfjp1ItbX}fZWhKF~M?^Kr<-D%r#U<J5Gw7Wi9l}{hQc(qQg zyl$tw3F`feNLkkDW3TS+S*a`mq{Z$wA3YU_?aCo0VhkmpdP7gwskFYYesm4vq$~0a zHNUiNa-S@BNgJE>(`Bc@X%-|a0lqK)e2uc3sd$azqqxs6P~2iXp676m2AX#HuC&Y! z$1|wWAb~AY%H7j0bmPHiuL{ytMAIx2)^jThJR`~&$<8%TkFx3@q4-O2u7cOCO;dBs zOXjV^lk<(ufbv^ouG>J?=hJZD49nc#uG7^RNjfDnR6n-ry=o3`D;@?RpHrc)l}Jkr zr1*0FJjM8(tTlzXSLbMKnVp998hn85tbv+7Blxz^8l)#AhF0bZtDh-r_iAyWnTyR= zcB%ift^E%P&p8_KMIFeL``QF(yZ`k2r@en{8#s9&QTb(cSXSsZi`3kf<4XTTzF+vx z@Zhf~%Z`{ChGZRvh?gULnUbVa*boYFCdmR-3p#1=B%k~3ru<ZxEIrfO#{=6EV@TF! z$X~N-`v><BpKnyAJXqY+%j`JTkp$wSpivl>e#i33eDY1H7Fy{l{-Z^=U(M>4M6215 zxD{%m7iE|QFn7sRc_NJTo&pLF575vXpukWM@yVsoG*R_a9j5zA^hT>vE$cBhPs6+X zxhj<6UI5k-OVQuK`hOxgeH7$p<0-_TRlY)Cp-F0j+-!qXOR|CrP;dG1ZWqJ&{ps-f zgF&RDf?eB0w{j9t&ifh`D2%1HQ)}t|qFg9n1dH8_7=#x%@4t%e@Th9=;$@)KACFU4 z0qnGeJU@oDr?ZDE1<*6MFoi9@-bBR&7<OsS{kX8h3cIa$5rbg=KGfEAqnRdoOD$+w z{FVg>5M7bexB=4=xp3p0n$pvU0J$xA?90a(MQUZWZgU?(RB1?kmL45eD*v^5EUs^6 zRmmm$)Q$dXsp}=o39I)5C+D<xX3HTW{QK<%%LjM<x)lpSF0dW!W^S?Xzrr#K<~u`T z4{at|yB;l72@Nu|J!d&%^7fKSGhlmIeeN!GRd7wFMr}`Rg6M(rI{<t%9SE5qyr!gS z5ZsN1YC<S>(#Lblc?9u@fFUo9G=WaPG`#2}N7DKOs&Em2jd*m~I>H{}Nc;&y1iz3Y zgPaf1iYN3xF9+l3(`scQNquRK|0E1O(?OjneS+cZ8L6M>DM(Wm+-{fyHx1PCDaH4b zUuM(|%a36l?YFarohkm&v$X$14R{;l2?0Ed^d6Gm-_D)W*+Hmyp#!-&ny8x|h^8#J zojt4Vx_lB-booP&-OpoE=AY#yN4h~~@_9p}+5Gi|ljcU4AQp$66&JDqOKPc(;T|g6 z$|}7rJH`0y-NIx?#J-4YiB)Mz3OTz)@~>#bm2V+n+G5MT{gH7IzseR7fsiV<<2-NZ zmpe^--TMmPkhkfFrP_ZwlQ<Yt0j1K;9jm@s4_<NV)gQgK{d)>GfJ`SMpv-;0>j9^C zFtBBig^Ie|hu^y6ep&Ohygn>`{4aDoI}RS*cj#nl4lvHmqPdea7&Zy?xDW%v!dKxn z>>s!RDI#)%ADf4-zAd}Lmrq=Yw=d;fRlV-`{@(LQwHp@c@83TVzoPVdL*Ou+;pJ_e z4?}^w<*MrfhaBuW#$WD>3v#&TT{MiG-Q9utKC<70r^z-${Eq#DF+~|^qL@r+$j+0q z{=fy4QUWaD>`t2{zZ?Qa9gWeA_;zRF9d%@Shgo?_V4+R++oau;#F>{-M>g_w(*wQN zq1i3_XUU)-<?3#%@ixmFl&yV#%7*B-c=5Fek$16qmUEhwXOb4-&~Ly(C6>mIov21C z#7$yfER@N9?zrMCH=pW`KJZBb1P0{SCh<c{Y|!&oS!GE)nymNqRO$G5<Fm|^y(j_r z=NV2P_bD@)Z%7F8EZ;lC`y5vhaLcoLXC}_!4NoXQA;Yi6;%0Bj5%K10?u6*w6?aG# zY1E-Gnb_IXdh6+h3m0BDZMgR9RtgIye=}mZaCqe-$^T3F?}Be)A6gjG81mhJxR?40 z8qQ7&&0f<sI2qy`F-b6pon%k_nqKL70HW~nW<eHy{%oqg_UW~30{4r_crxSgn^VcQ zT(8LT$z43fna{|Rl*d|Iwyq|F?%VN1oR#=uk~a$B(~c*929di!-dk^Y;qI@r;dwE~ zJz|1zx2!mcHQF09>J|P9%G9n^W;`*ldDXbfYzcK9Oej77Yj(Zg15YJMCFvon91>rs z&gygx<g$kbZ2!*0<$E5upBt@hKa!6=iJFgQtXkkD){G9??yzXZuhdq!Fa>iVPV>hH zZ3GVRD<vYU3m(%bRc5R4U)RcgL}FoCrB^*N6>4Ck@iYAg=(Gd(pu%)XXE|i!#qp!_ zcRqp*YkOhAdg<|<_o7JImD6{cG=xq@16UkZ2RsNe&yU%gk(Xy>B-NW_tbEcI+nqHJ zG2v`{B?=ZOB<w3U`Exf%le25_RWkFy(yAN$M!@`GG^{`Dm)vM{e&RVZSuf7WwEcS9 zE}~-xi@>7ETT5JRCxvV_nFV#8&?Y68SXi45=v=A&`TQg-*oEx?&Fsh^N@oW$Sv8es zdM9%j`yvnG$){Z+4vgyidBv&1hAffey!spVKqHV=;TGMs3-TYbVG;*V^;RS$63T!7 z%KfGtW%@VZ)0s>~)FFKRB2^kW?U;r-I)I!VlA!M2l-P$}i5iq#lTe-9V_$RxIN<Sc zzB6KZJR!>#pq3+<PGu%C&I}VNes3bM{p6PH`(&DeDXW7Ny9x|Ky`&;n^`yCSYqCO^ zW^@)nt5f)Pi6OF11{!+1^y^}+`nM<?8PDgvG>Q1@%Xh9e%Xn*&Fh8aiK#d7@=;{gj zO>n#jJQRbVkAHSnK$v?*KaE36&x0Ckv<7-&gTFGFOX(L4o}-mrvx-%2#I4uB>IR`c zWiJZP(X!5;-4mGGl|X^KLN4U3s#3A7zJQNkNW_rK_}}0!_)KSM+q7WQNjIwP^r29I z2+_8~OmD)det+Z(=>a?216vYC%6GCXOsM{wlTf~`Zwek*{cOlB?=!cZnkY?R6=94E zrzHPp>rJxN`=WH0S`8nIDl?!#%+Q@jSOrv4mcbOs{|<4QasgvCBDw&yhX%z_%|Srb z6Trw^2%xc*T?y#@B<fzO&j-)RRyXVl)jguT{66d1Czz$int!~U>I6flyQ-wCO>2Ui zrntCDy4(9L7LxQJNa&#>j)FK97@hwbW~+3H`uJ&ApDRm|Nb;}xc|9XvH_pH+_M(Df z>p}@5M9Mg2*W%^zc6Q?e^Y}q#@t>+hpo=E$lR6z0DRed)+<yGk@}1IApuuE&(q9C{ zrk+PrTU#qU$>W{4f0n&Zy6pPpZz-~C2qz@ClJXcG<>ciyS&Mi~9MLX37K6gtd3Pze zfSIYp4{?@mnA)6EKiji_pRk&$Q|BGxI?`prD)-SholD)vTUYNDlx&p!$jmp89Ox~< zo?`Y1_guJ*jwGRX-fVkw?w{i>HJMTCUD@RbCd<7(uFUXpm)1n<5gr=@{5<i2bYZlB zd#TWK7haxIzd4@C8{;Jlpkt%ENm#Ko_RVQmEZNxh0G-iu+wGynY_2GNXVaQ|?gRgs zae%(L!G@hx)taoln&h%%3_rUyXU}3dIpCqre<3jOkxlZ-=`+o(Pk@ajNK$%_qKTps z8;fy({<SMs39G;_ZfSvox7-*j%|_=$HZN`-qRlquy^0i+sQH`PY0*>$T1RN27)WSi zs@rZ~zR)HJbA~ZE<acrA4~KGFtYZ#^t&At-8D~I3r7D$Wj;L$rILX7aF_aN<O=wh{ z+<Y1`vX2G=!n)V@cT7okpLkcN?&N`kZaik<?F7>WZ!3;-2&j{ll|#L%Es0)?O1AHY zd1d=Ap0doc)cHP}ah9K_l8@9GSs86_GIxW*aCTB)t>5#vA5DRdC)wx1u=nTk+ky*0 zE4w4Vj~m*4gH#oq3g1$<?q_mgYLd+`CnqvikTaS7ZS36!q%61YBU7R5S+k`)cE{c8 zS6N7g^%(BH$e>YI@*{4scb1PZT>gA$gJ}{9X)_mhI7jw3blK#SS@GM%(#K1Lsof%} z?!0x57!u1rL?a&Og~IceZK&S3ruB5xMr%_+qhKcRwbq?V&-BU#LU&O7qitny8(hY| zP9-0<Q^bG3c^qKD=j`|4e2EwjF0<L{d<ZngB<rI`2)ATf5xKTi#rIb(65eYY5Ebhp z1(VYD%fV9QE*s4`9Y$AcKmoGs2g_FMp4R~SROE<eW2+^fG7C2UI@Z&%M-fvzde~BK z=Ut3JT>b+*eik*0O$?@J=N;Pws(g*jwt4j`ojw_QT--yDqKWKnUmCDBO!=d7S=J;M zf7znknj}WQbk3Y0E~;XpynmrjKo&ed$BNUQ6V|>}2g&+%R@an-|EjDoB)>_?`Y!85 ziM`XnyN6TE{FA>{n*^k`Gb_0LP^)`9p8(Apu!5<Z9Mw%HIoi2>^Nm=HVZnlQKT}-7 z@akPU`vGmk_M%tu6vd+;WWEzUR^%#SnonPP3M7;t`0{0sy>F>BYaN3X0!AtgjHw*j zouU`3ANB6WDa<jiH(BMVFl(*W%wpXZ7-*}AH8DUd+-uV~$RS!>Q5;reMZlc+Eg>#m zxbQPk;0v?fbH9(*vLuS$iuz3?is9EZ%9@u0jIQr8UU~ltSTAcxgn6E2>|BFh;#SRs zq%mSB+1>2UFog<q7*Eb0{u%FYM&y<?$Sr59_nf)Wy~>u~E=)7d-bvk8O!9W5Kx)0~ z7gAH)PO)X6=&fYgB>xP2@42}XT$Yz{NZ-J!9QbVPT~^A>6z@wod`<>DCwU`)&TZoA zH^{jg_l>>UD~TOS(B~x6&~}+E_Hm=eK`4pVO1tSmr#;j2MILOE6a(rYfMIoGjCYUp z?uKyYC4TH~(*XxR&&g?4^JXv7>JYkZ{^E0Y^#EsG=Z)kn7A9Pep^|ri1Y~ma_(ij_ zGn2jX<u-$FZlU3Jy2A6@&c{QQ^4y29)maas<JU6;uhxcSoCkfm-&HqZvas0R8>l>h zL*$3T5^akE*Sox2-X<ROHXV+Z$GS}xy=yeE_p5_sjt};l-hzFZn-+c<P5kS%QS`Z9 zh}Y5g+a+FB<<iwh&T@W_u?N?&#dC)xa`TbCY#XJdvO`ZxWuL!mdruR>D(0em-Z@MP z>OhGm)92S42L13G3O^!!EmiHIMVU*3O&_*coK_g&q~r2eYj<{ZEaA<ynaZZir=PEE zfl0nQV?Kw|Q@p|bDrvW*zV<hm#fWWiKJB%tKqT*oPo%ett~ozqZbTq&<XFhAOaAVO zSg;lj_~IF!wHW}Nqr(}y$~Pd1c}GX1mlymF_qfm1pYmgypqjU~rw#dW`pz$shwQi2 zY$*>ml`N5Fht7RVSOVJsr(vkQ4{l1<$8`7Vp)qD_=;%jN5o_53^yWGY#zg7md-5SL z{Yc*4)o+>R1s;gJ00G;X<u3gpAN7R?7tdHYQ#hSE12)I*RlTC5`A}Ibrn2p%p3^)! zCd>rs<dYbP5a8OabM#`4D`#P_kAlg4P|R!<(AlPtC}h-rv2W^p<Q~_;(lfSIRyR@H zq6L?6<sB46X=$3$n(ZBZo{Ww#edj8Sp__U+8yaqou3!{WQ$OdTNX{HRNZ|vr=sy@r zWIEQp$^^OSud=`!TqBRME{Cy|fewS+QN3bM1n*Qw;;AM)3C^BhlI{dJteaJ8>Glfi zARm~UYrT0FX%i<-aes2~HGFGi;w+j_LUQO+vSor?QV%6iiawi*sg_|X5jbjokP^v+ z=1V{SVX}Gab=^waHIz<UpRqvEuJetuK?ZV!Q0}f$9KH;HmF|60%i4lqpUG5`^S6B2 z#ZUg0BA)%wm7(NOwRJ3LXi9t*im=cD9~t*slr6p4C8c)_PrNsp@G^Z2reA9NdHnui zdW`K8%z{;dgelg#N>%`>Z_kY_S0NNZU!B|AJ0$1GESpH|Gky~NsS|;tb?cVxRX|=L z6t8*ZY(wkvQ)(WGddc;jbk``Izsrm>28~B#bR;r5Ub^KaWO%aoyUkF~s?XRbQ#cT9 zNWhkF3j=Cu9u-^YLM-d*IAeh&!ED(?9}6jOhwI1;IrGe>=ylok2iJT_w~+Rf>w>~_ zTi1+Y{rhXf&rT`H=?vxkjph{?y`?tg@lEHF;?|pd#>6KDUX<Nh_S`whPDRYPigVy6 z?sxQYC`*1bD#5!xb1Ke{Mi+M4?%F27_n%;o>Jr`N)Rn}W6aN!rOTYZDUAV9gPppUq z7PrZgpbm|U<%9v&+^GiF-g1=nvYe|S=LzPmVz&G?<3?@N0lKHYMp|d5P6^d5W%@P< z9MvB6N@wbB=>pJYD{e_&RFpx$e2SV`i$&=c!(uaCcMq9|KxFmtOQh593}m@i`}!$- zL(V4cU#<YT_Rb4-sQ98E<(&4(H6YM0JfrSC>H>CjtbSXar%lZ^f|c6>)(8oIJE2M~ z&8SlL$t+V*@E54zGs~MOs~_Bfa}&|=H3IpR8Rw#F_?_V`$uEUK$4IvH+D~!7E!H?v z%FpVCSL5Rb^Kh6}aO&TIXKG{?2MMnuQ}9}S-D@(-l;g_MU}eg398^n?fcP;`O`3ZA zX+ystngOGIn-X}SxzIMi=``!0>=u9Ezcb%Z$73@l$-<9<(-$c`%ppoj-WNBr6z|n& zMN)n^`s9>}EL#9ccK+_T-yU5DbHmdV3go%a9RFD(+jBd89|+EvP9jM^>DN4ODada= z!8}_JJSkDCsgr+3P0q~B;m(;F0Zw@#8DN|{L#Lcjkx&}-?<_^&wilQ_Ts@o#ddZ!> zIHLjl`TB`1^S>3L(`@ndRGdQ(Br8itbm9IWsH8$)uTOd7!;zeCrh54Th$rJ2vRi_T zKANhtHEOG$rM8(5Px#&?B;DK(;xV30jHu(>5F|}y>1tC;nvuP=+JU0%ZF=~uO9bik z(J98THD!RK2Xy)0BLJUYI`x7(1tjTI$2`t+|KxV9ycXC{&X?QkRd`ow17Q2*NtKj+ zf*L2F{vOAiwjk_9F2~l|*?lfNae^-)XoKFVvkul2!l+X`y5a@*&|NabXM6{1#oTuU z)6O9Tyg4LNL}wI4aR4HBTVdP{N%oWa4S@b<SS^LLkc#oW|31Wp{6ZIt+4l#igmYXF z$Gq73Re3axzpwK+^A(E~rxMXCGH>+Ea+$U+kzLL#!KcQuPi4dG++%eT#fcC|P@V2M zq;03^E9~f?thR|pDO19%yekj|^S#~z^FUiGwn^v9_uxu&hyLeg7aSkYFi2(x?Rb;r z=2P4iy-)1hop+uN`B1KN7^%Y_4popkIBBW<OwJ)SGvQ#?*4g%foQDNP;%YDMl4oC^ zN=D;@dnEYjP&IQI$$PzGr~~&EOZ1ICDJtM`UXWrg&@_`yv#k{kS>I9%ujzs(B<)_$ zSO1#}z~>n<*TwPQPvt*{>_J1Gv%9*xJ|Men-u$3NyE0{aifBC^@*l1mEU6o_mf|d6 zKScm@&FF<TOFGfN9hj<L<G4n|W~4|{OV+2Dhl>4!UFY+u&}haCKbMQ28AMHOdxk1= zHf<fj*SgrV3I{J3FoXM@+!#v)pmlx^Tb&(Kg`=29yJ3r$WPBOHpP5J7Cn64qnHh{m zP`CDWH_O8J>Bbz}Pxk+qXeLL>AVc*bX{MZ>#q~#Y;4YKaD{4NI*WpI#`}amBFTjo7 z?ee8(c9uifi$*mX3)KsY6Ev)1{I6OZw~;IceXLB4An(T~e@;}74_CVMf17y6fp+F@ z?dnr-YOE}m7xnFPB$WDF@}D$cw~9&<b60%Zbxw!f(5<U`iN9FQY;I6yiz>G8gch*) zH~uj2{(CcwPiSXe^7Ch3stB1<q~W611Za8C*`KOWyXn+~V>8ic;wW?kj{msn@QK=- ztJc}kV!(FH6ebX-V`#<ioC0+=<=C7(a~Kz32dxRqlzg`+djzah$WQm*i-tw5hsc>@ z>KxAf@p10<<uh9Ej20uy%bh~<jw(ybS{h|6hD*1EjeV4riI*a6F2?W;yt_Y=WHB`@ z&gb1avKZ|l?fhpjx+34o?Bab0h<<6N^Y4VqpQ4)F%FuyanV{Oi&gT0awZ)g(IsV0g zh)%tv+q2VII>4}Vdh2BU{rico0MTdkEpNQSp3Q9VUh0&H#Ghe)S2?+_RFIr}f4P@o zb0Ig6q&AEqm^>cndFS(2@;s2P)TB-Dmvx)h9f>)IMEPv6^5v8W_JSxZJsDIRfVqfA zgSinf_vx4354RlqZzVxrG*e5g-2n%ex5Jh_HqW`L2l+~mvW10EtJlEP@t1`Oqh~?j zVC(({d`g=pj5r6)7fxA^BibZCwS$2x#qF9BqcrRC5~5EFWGs{eVGjM5C*HY@-8Xx} z?$ECRrWUvJabAw>ntj`Ur%w5ARi-eIY<ZTYJo6t(?JH2~a(Z)Y*6cPCU2rc;nG@7t zXl3+DW1GG1m=QcEVyD+o=LF~RPIvxwEcNgu+~zYABv!ax#IE^Ez-Cd7A^rGxlku6; z`M7OWq0g3G*Q{f|=T0&-ZxDMGTq$ZNi7k$aK@FvLm&<4~LK20YQ9egETp3H#P;;rv zqi`d<`QVY?oyXdaNroVyz?a)l%h7M4<7diU=8Ntg$qJf9O52o)MKP%PRAeFZscx4` zF-_jw8y{B|=l;nTNezCx%pl6`>5f!;pRwtQF7DcC?Ro+sSs1gSw}!{_fZ0UW#Hils zfPLd+@<2`{?%Vaa)?&T3@l*>N&C#dNF1Kl5{V$U%Lt~`P*<(1lidCHa#Y~`cOFIXD zG>xj7^e3t%1Pf*V*c>C8KX;k8(i4@Bdo-SuTqI9`!eA3dc3P5a*ro`JQvOEk^+cL+ zf7XHord&X=vK}Y8Ei>89A9P$CEHfc)S5(|8wAnCTA5i#oymYHNp)wF3+hEmHQ%TZ2 zDG`o)6pPUUPb37A+nR8`2FN+#rd7MQ6!6X-r%~&0ttBS_q^T-7LrF>0ItRix{GEpK z5Nj9>=f00!L3--zZs0743MrgmI=Wl=FNnYC*30}0;u|FY-f|P)+cg>6Q?V{PPe*XB z5C=uANGs7(4zHQFvv%JHCUy}q&VPOiUA)C&5Yc;m&QPVrGxN~-#%cfBV*$oLBlpDD zG=808)?W8nTA|RbfF?EiJW#VP^uB=(X{xb|Bj{oJEFoqMVI^u;d8=YTuM)<__0Xfl zQTtc53si`MCEKH%x2wgrznOrO7+NgpYN-GnwX-e!=IuHcZHpc4{Oaa(92Fz2c>k{; zxKLFpI+?q1BGuW({Bllb)F%4Ws)rC;=_7L!i#~E%Myjb-uDT(!#w2ug?HOwd>~_P8 z_xr!-u`aXud=w_f2b-Wb-zFYTCIaiCvAHEy%D>17Wny$Bj=E#tw?8tN!2n5>%~Bs* z)*naBq(+qF%~GgN_(SJbj(k$aC$DJkR(AzG$?%S7cK)X2YgC2=Cj|yYuJOf!^)d7h zZBw#rxrmi1ls7-!p-z09l`DN(`eZ6BAZU-O;pf4KAxvUzawnN;7J|~bx#&;y_$Ey8 z`^wR<X!u+-O3iRvx#3`H<oTJIHe>7%&!I*cay9xi_Sdlc2z-(wy&pU$=;nd!WS<pC z5G!5vnIrRW`=|K`XpKq9)1h(*tuNzfT4cswdVSrwkcU72jl~8uARP^@D3o71Uh}y0 z)=zj%jd3xf;uQ5P&tkN6)`&e}Gu>bD#-`BgGhdC3xWpmSWbn4Mz5rsEgkv7r`hb(M z(5499k}#J4p*`0vW(iMN$!smMpeP&EGi2@NT42CG6NnG?ifGp@B#u^~o53XHNNU5x zdm1lLQ3^KJuWfd%L&nNoj$#9cXJ*9;|4BXbZty($AdEnPeW%kZulg!&@?53HI>x(C z7~s}0MNJ=A3ePq_6UJ)S1u;-9RvZjf>Y4+qEc106>G?ckqI#SRp4~QTcHUyc?s!&l zos$Ameu$Es10vl*%CHb&i<>0&k)MjSo5~w|$KFYCYJL;YRrl6?^VL|4rL!DpqD0dh zIhiB_#~qq23d8jai|o$U1K{rRIn1SJN8og-xU2V^p^d^wEX1>ptzz0r{*Rdu^d#zj zMuYRixoxBmHu|-np7<EQ!KieJmBXKfp_YFWX{FF5@Lxs%u;ypg!rxfN6s!5nU<UWl z0y<8DX@&1(>2LeFmVomUuu6v4*QJoGVXt^HBd%=FORxRb81C^A`TB*BCtiyDoz7db zfk+TCc>zy;;xj@su3+UZA*V~gh^Y_%>h}fun_1qG7wrih=VbjK`{;_CV;ULK)T=>_ zuO`#|y=h-U9(u*6@M;{&6I)x-Ko#BqkgB?Y+#n>JznV%SMLG}*>SrJ7Noq8$siifn z7PyA>sXyU$#{tZ|o9E9z-`J{nU7bd7hI&SH$K=x%IdUm-ag!eS_}0p1RTHozs+jJm zq>2R)#h-zgsF{UnDPywB2<LmSjpP0JSy{zpl-?Q-Me~17+G@+m&0QdxaUajbNe_XR zrMpt<8>kMq085V&JI)x`(H~Wue@^foL$U2sgULffn9`vsUsjHMt{a)<jmoj<`O{kL zQ|Jh+0Q1OG%5%<0ojUN=Q@bF2jRR^ot1ufD8<-^1sl4>K{Oq<m3J1ne7#sI_m3|am z&>^~)6{;|iTT-%qSb!~V+B0Mr>x_=qq|!U_eE-oE#FeytIv=wNvRAJbgv;FQrrv=r zb3yseHmW-rn|N3%ZjjqFc4aBizF7|C<r#Ym-Y}ek11}NRP02U^#}y+6->^teJ`6&q z8r@rJ538$2G#%}9%`{<rN&_veMqRgkvCWs8o3?`%oQja`tZ@Jl*w@Bkl0*<VlC}8t zGz;c7+)`2bBgkmDU3+7OotFrCFEG3RC+v89#oWE0qA48P;}bVlkeR0vxI_cK1bojv z2MOl6Os+parzY)IZB<wi5&W}rGqz_K5<%oQnBe~Y5p)H9HgYL|vg-bS;MdoZwl`O< zC8FVrh}Lk7)G><*a_|?L)w}mwkJI_xZ@yxu7FNKT{3+imb>fS6#jiL~s-D58*(scX zH*9!&D%iIt{+4@HLwz{OE-#8^S(t)=<CmML+?p~Dt^6bKBKf?EQKBDc^HaU29ZxJ{ zoJ#%vv{RBak&3|X9zPOyh$<uyagl^R!i|?7f;E|jRJWT^hkaHnnJHg!r>#JX>sOx^ z^)*-C)9(wfbSiI;2d5e&HZ0lV8)FjtatKF<cSP8%zU~FR_z{dXUY^ouZE;$qSO*5Q z<<}W4<rQL+c$Q|tSh~**uOYxt?6!}07I4YeuZ~#1K|<($oG@4PCq?d|6>DGbjx|mH zMBE9mrW4vChwm&R=*Ki4WF|;Az}WJ&7gz%{YU=2~8w2PUq~0R6Zq12At<jgYqVp?9 z=$j{Kegw=?A8|M%P7~(rSYVyc)+L`8rYE~uSlf_w5uVT7`Su`EyLe!qY3b6p(1jtD zMY7n1uyWFrqdiFeL%>tMG}TLAN&XiH-lvqj<CcUD+=6l>C)ot68x1vsRS1}8vTQyC zjHEY(g8FG50UOAu=QG(_|C&5&)jpl|Wn->aK8h51sGw*S+xS489*6?a+>qed#%$?B zi#6@%%fCSFWm{tNf@qLz{HgIAZRNPQ#m^=oydNlH1qR>-?*kssJe<^91DKJF2Pn~V zNW{OvzjKM|!d%)Z355{*`H;Zu3x)mi3b@w8GM_ut9JA`;uK(r_Lzxz^VkExUWlI*Y znx9rM{J4*drz`7ek}7#`G=_HHj60<DNe87AOLO7P$k%!p79OWT5|~i0-@0<XjE&J3 zTjU(+t8Ze@6P!=HW~HT-?R<{&P(`T}pj>_^m^K~w_{Xp6c6$VP-vl6suHDIiOCoBD z&`~(<p=olvj~;}@wx6fh4O)^!|M!}K)&?SF{B3FpJ~{LE>UH@ql*f22Rg%AYPjQ$S zDS@t|y+lEcn8$}XLaVER6dv_R2v)D<5+=T{G95{J>l&%fOsjJP^_+frWQGro^lP(A z{&EMW_IcU_f3@Ep)^9Bd-~B5%UY=LY;%x+yDDHt;K3zH3rW_@r$kfs=boXBl%s-Wv z?!7~nGc`JLjq%O!&hz=Bbcy_Yu1njXCZoAy&sgbl+iQ$ZnA;d;6T@0wbc?wsPvNoi zW?jvT{<GWIL$vn#xB1*|)jV%lv(j<d&6|MA#bFxMkS5-+t{(Psgk%EWpe$MFL&as? z139lspC-NCA_JtlP<-F29Pyfo5wEl0Fm3Wch40bC^4g4ez0u*6Ne@s2a&i+&!Yasg zo>2o^&jqj7^@?u&y7i)h@q?z)(jT=hX3vN$fMmDI+kKB!;T%%mA9r@n2{1o>HnMR{ z2=s5!kN#I+E1yr2(1hV<BKVD72Td{)qJmq370h6LFim(cSDa_z?67UTw5*wMnYhVM zO{d{f<kEsuE7qenKBoWmrHiuQ@03hSR$QYK$$T43WI5d*?~Wa=ZSCKJgxp2yoUG>l z=yLk9g)l4l*@oP(&`b&bv>@&i1G7}}+SN!K$0t#}$-*L)`S}ixWxnQ!s9QZ2|7Er_ z(^zV>xm%h!0zy96$A7%<^zDx{$Jk`qT}@Z`G6K`Hx?^h*m2__El6b%W7S*zN0k4!E zdsv;A=tVDpJA{9|_VQ&|Wu`IYrA6Y*p;8I*v)|{P3$i9OKSxe5Npy#@12Rafjh42x zVEvfEzhEfWarK&gJ}j7nh<i{m&uD7uT#$7I^YYWUBB_F(M1h_AsP6DdRNU?iH7-I) z4>R<{V|zr44$-azhuyMhN{USutC8i@#9a+<V^uYr;J_00+iJU^a#S5r8%w~h`GyQ) zcjLdSI5NpAJ6xSF@tyw?POAI6JsA<OnX-idC8@y|Es+M^Iq*GjH)x@t`#z1c!f|4F z7M~Td`2`X8%%ZKx`?C4)w1R$|JKLmC8<j3uYf8nlkA1x%!cRN3;^y`#W)&as1B>@G zel{wrir9fxL^B5V39#p6V49oO7wXO->=mDy#lvJvNSBzFJp4pd2%Ne9@)aOv{;?$f zCuVN&ieJd?zH^8M<Bzv?xm~@UT1Ivad*AGBW#PPt=kLq({#U%Z1}Xgc9+rDijvMZk zwlWeDug+}aSp{A3q8V-&gx|ZbI0u^9M|U>`<25G><VuX&gh?_MiwKHFUSC9FUwSUP z<tQ(E_Tu;g|I>G00Jb$9V`EX-+b(`F0)B8GO&*?}>D$Eem@)&H)aA-E-j^fO51WZ~ zPnG+Iw~@ue%muqUG4cJt1t<03H^o3&JK>jsju;-%jW1n5@pK6P7(RJLAfI^_N2oT# z-0p<8xeuU64?3Jp2Y^yN{g}KH`)N;#7|C`P$#!oC0mr3Ru!x`?TcO%)QlpZrEz+~b zS&+!{BGE7v<8hW4R8gQM#_11{xP41UmbnCu=&oG`;`wsc5o73CWmzl0T>uJx%4iw( zk(Y=u)^i*tJ%KnE`17-AEv)t&mmc81>Q9hj(A?NDZJ^)O+o)=oJ#b^{s3Q!VoGFoK zRX!3p{6yTVL|*&@@mBI&MrTqBT<p!cY>`hdtlzjotVwYAt80>OTNCzjn|J%Pk#qnr z7nw_iy^`J9p4dn~XSULjwvZv1m*is$ZVTzYJ}lE6?Xv~_m|NA(+H00NaA)BMN$6S8 zAj-X3%zH)tGZJUTqqKFm1`~Fgwb*v=ni#4i3IH@45V<A+wrp~mYj9V^M`>~mMnWd9 z+wRn*aviq?6&C^rlO!7^nlbOzaxxXy-(pd67lg20k!1`C<o(tyh8RqB*Yk?+E}!iL z_!Lk}P8$W9p}9qF3t65!-4DGywfU5SzR7|>dobO9rO4_Stvyfts&M1_IWwZ9E(8A^ zONVc?+PrsceSa8kqX?ZxkDInWNel<`AOD0W=E8|Slr>|6lsUe4fmiG`Xw*1~y<+j} zj@$BRU0J)rFwJI4AD3<M<5>`W7A((>gwYiLoaT0r+{5%eu&KAZ(T9cHlE?f6ib!4$ z4!FYjyWKNeA^zqj_Cg>wWtl(y&t<*#FnVAF9>jmsbO$GYgL{5WZ2fs5o9Ff+S{c@* zHH_HH*q}1u-B|8QY}>kK=wD!x<IGd?0#ONYN;+;Fq-lzL2PL@3S=~@47j!|Ynz7tR zH4=p|^5QUonlzQH!jwI<juCHR*(3dU75ilu{?Phe6O){_@4D;DpR!}Sh%kp7h2n0C z8C7<w#ChSJPm)__6!ggjR{a6jsz3gGV80=XH-NbW!2!LCXMA{B%CLG&QG0;Zvks{T zn{E5wUdW^49k%(~fy3|eeYZ0rK(Ku1*wu(*DpWuESY8gXG{J#{7C#@Xy(4FLOYE?) zIk{?(Nk53TtU|B<y6w)YypquJX?O=nl}r@)^&fRQ37l*7T)E~%O<@9Q%>1=h(*&tp zf{DM!#KgUt9Q3`L<=54aAVkK|nLcFhT>%wgc-8#?(U!l*G=im8l3x)~lH(}}k{v*% zn6L+t_YX3c9C5BVrm5eYKhwmzh7i4<y8^V6;FO9-%~>QP5b)-o0kj@r^{K(eSG|_j z7lvrV_kheYQ!D<mD!Fd<IdE`EiJY4GNqkYQS3im9m)ulejiO&dq>Lf@N9lS4^J{fs z+@AkE)ogkc3qum=a3YLVA^A27qg`M<M7m}^jE#f)jH1(&eLL2^{Lvm&jJ;&T+C1e< zo2Gv}YZppdJ{B#W^@=R_N7I0q9KExt`wYybI{)Q-O5Vt7?l*}1Oxkf_+~~k>2!x#U zA%`U=|JyvX&sRFVWE=RO`H4@e;q_`!$NSQ`KhAM7ghdyptKG4qACSHF0m*+J0(z}T zF)6(y%nJ1?^L~GQ!ixXZaYp3#L0KQ&BPduA)wYpdoRfa4GB$Y8?Tnwli}YN;C9KZJ zM6zbE?^H{vMsW05S_6<-GHzzYXV%b(w|XD#QY#TK7n^8ipCE(N1=ZN$V_fnD>2A;= z-!J+tiu_a7+}w4IRyY6rz@alXB$^A%i7a#OlRYA1;&|cNpS?`mLGFLi0j1(Ybt%*U z@<Y|YDrC_4xK31E8~b;<2Pm`;jW89ub3B=l2G|9EGm%CjUqlaClds}eQ}V>oekxD~ z+E+l9yjcUuZPTu8CPS)|IWpNtF6XThNmJ6BEERj`RYZ)!+Zo<)f{wtM_}uKUHF<WD z`0aa?=}Tb9FYxlt97@>n&M?xePVwKm5OC=Zkd)rN$--gZ+=kD}vq>Iqo*(?GVlmO~ zY`f}|RcX=J6V{)g*7TdGwQobrX>CvXh`-k`*h!M1HL!nwsWvw8u8S^QG#|C2t8%8A zDzzmvw_i;vXUhQ#4Vg8Oo^&RLyaICTk>&ruKpeO>^Y(N?tCrLH>m=Uvuw`0TYam;n zVnkc-yc5*%!0Yq20edDGf=}WFC>a*NI9C;0WDvhA|M+OdYnjhfKr|v{9RKJo<>AB{ zItqRcel74<{ZU5kc#gZa!{C;f0ks5WmhVf|dpKHrEITx|ZfeT-n{^gfksS9}9JnBK zJyzGexWmxPJVo6|hHmhyMT>?W{euQT8Vy$yWg7fSz`Q){W`Z~fG(2srKTl!_EurvI zqWSu)d0|dm`Q|RA{8bMHS&-h_545&btP*}`Y{QN}(X`ddZIyfjv#__;E&AafKvN27 z;##62Jcj2LIZB5gqM_bJGQWwLmX$ni7_3QG$IkMtFdf2stHP^mnP(dWjA}B^;W@4= z{WM37yi+S@GBOe?sr9BMYx)o5UA=4=?TaK@;OqVEE%wsPe=lZ(kY^hq57hNU0nNRp z+q82gt-6zar*AvKgxQL(1yMHSStH3b$l(LtFI%<`=la<vDv`j^@KP_ft*8*II0<4V z?#!rIaW}qFVMTI#f5HdZOB+C<y<c9Q;T;VEvXp1Lh5y+XX~p(xrRg$IHHBP8ugWt* z|I6#-IIrm#B=iNaUsW!&Hjyq^o_&DXt1OAX*0JJiNtuK>RB1TYDiHHA^jzRtH)wn= zV((anbzQlJsIEoRj1P+Muy2_FoijF0V@u0pC;vgglWot(Kli3u>=I%a4_@VYQFS@g z!}quDO^X}Wc(#jYWr%_MKAWj_8@gF7P;F0xHUnCV%OKC*!a-{BTYo3gzT|2#)qhzF z=#BJRFxob^@9f&ew&e{4ZVKy5>}m;s0V0W<P%(V2JWnF|9<;v{SKg0VbAv<0QuE4> zC!}|uG|Risp4sixome_dTIzta3Y?eZAyfKgJE~<L6C~eZioJg<&$S(d4hR*zTE-D^ zIN(rhNNFIirnYdytKLMvxv)1Q#<PK?q;nDK>$a!fu4$8xsFDdV4e+4<|5$tLuqeMZ zY!q9OPys<wMd^@k20;ZuP`W|7bLbkB5~MpFkZvU%QbC6r7^EA?p%I2=;=F*rz4zzd z*SW6qUFZErfth#Jv!3<TeXrF9x2RMos3RKxy%gQ}D(E=(rRo$>tL=Qxj6s$@W3_l{ zNz+C&4ed<1;HxO5HE{FO(GYRB!4jp4j~SY==?x0C-5JtCABCH8^Fez*yx`bdZDGm@ z8R#+Qs?{`}bsz4c42Qb)HJY(%)q&lk%8P3;sfmU1qBmc^>oZRO1$mYHfp}sokd&dU zV0XOq8~^e*?IG_2k~*0WwvE@n-a!v~J?qybm1nAd+#}diRw&O_ok#x;1AX{8!l#-{ z*f+1*>9OMW*3gktCwIv^%h{9CpSuiZX;W|x*QF`T`wQFYRszNGYfy_c`5$VMcBC5D z`OuAfjhl!2jr&%|@R!r?%V=3PgT^9CZfkn(iLa+p@~ugQ7T=ySs4Pt0`u=GXu|HNm zYm@Y3qj6rq!BF<cRnf?ZqTf>pUq<S1tGk8fI|pw|gX)S!ESFfnAE7=wQ#L2X%FBR$ zyy9GC@+8@$E^E#{?%*xG%~sr=NaRNPT-CzADB?3)_&{Ql#_)TExf0{&%UM}&yq~`) znR*P&IL%#anEh04ZjvL-kipx6ud97QROBrlv{S7%u&blq$ep0o2D`2B#WnGTGV{VK z+4kFB6}}w>P4MTPo}*63@*!nwprS>O^z7hOMw4OfZ(+iU{hCa-!R1dqbb`MdzRwz( z>A`qVz^y!qB0D)|b}3w;1&W5Aa}+XYG{wHb=WxlJ0a&Qs+y=FMV{y-DMeOeAon^?R z?!0GdiS~96yOCc*{r6j0geKDEh_3G+x4<KYT_*8^!=0ktUnRa>V<Jtj&lvH%*1b|O z^sL+r<(9M^&}?bR6M}l=W1x^{X_26}P83;ZP+YiR#?Q(AY$0@|xOd4coBBoT{jE7| zIZ7upn+Mq+%QO`)+YEA|%-6Qy4Y5iV=X`aN+~dT@h3kV?zh7C=RJp5<mJ$#X-QloO zR&2L~+%Y!`WWw_SXUHF$S!tZse2f-qyW!aFcaF|eD^;gspjL9Rqq--J?sKuez?J#+ z7ig=8I@)ca3sPMv7__*%rlX5fpYWq1u5D!5N8-Y9w=ry4J!2AtBxOntPrD*nmuPsW zt!lm;pj#6FR{C*RSDl*S1;ZK=t7|8R7w|}&S&Man4%B&wRNZk7N+am%F7h)ET%|i^ z&ts}V>$7d!)3zGhY6eQL(mB*V1yL=@do#^&q*B@KeuW58fl$ic8o!N#+l7U5Y%VOu zy1SxjYn(F#Ymu!biFy&@5LK5EH&+{gkd=ymhuj!j=>!&FC^)E{cmp}>0YNY0=^0w6 zdN|Z_4N_*5m|L(~gLFkfBKd2}BuH%2Q3Ycx7BqWEI!@Fsa{cG<U}MbS$IHJSTxM+p z)wc*)S}oWIz=h%<8zaD`2}m%$_4cA*K6%#x%0MO-;<jzh@$j(W^)SixKkZScpBl(@ zxegbV+QC-@8l9E*VE#b#c~S5NQk<J<Wu#D$JEw#Z1FjfT+(VA7RxJ`ClZY7yoLx#> zDUVQc=Qv$$w10`?L~PS!bl>vyeV)AN78sDD8hOo&={fGspJwhxo;Gv7%Hb*$Qnsb? zc(8P{I)L7lJ0>z6fqtud{#x|<yQR^rDyql$wMF$v1V`zGSO8Vv|NHm-I6+w#HCY^L zrvs|ra(>JUohkEzZQ)S;ZP~D5uO1&B{3NJg4e`^dFX0KXKDf76_3J+s6jJn^f{hW{ zVZWQUzA%YuJfe&{fCU^4ze{`D8dpXK<Hl4kj&ixX{q}{#aNj0+_9{dyVhh=HE|4$q ziTs?Ss{RU8#;E-sHhl<m<!abWd+p_5@UymK)VsUufg1p7{xar7U{9X;tkVOH3Z3Sk zotb^fC2J3M6;J!lqGsFH!==HqcT5<$X$3&Qf?E`SBP#<oM3e75c#xPu_;3+o-<D)3 z5`8pU^okGv>@AT!b3syLz=UGq9CYp|Qcg+{7hyo~uW8&qbMNDiBbfIn0wYtnlt5A3 zrYTxmh!_X@or?~7ftB3&XDpebZ-JZYV-O;G=YI|h82XR=z>VJSRX!3i!J#6DqzAKi zoWH-RMuTK;63qfm_Wdy|+FAzT*l7I;3NbWn^l?n)={j~N<}t78jLljMrmjqF4kw|b zFH_|#rmBqP36LQ+U$IHI0>$8Pq9zgAW65u}RBwoUuvTTKs?@?L3;GIpx4PzCKXl*y zyy$ojt5;d>nDH|!vDLLGBK$Y>m>^?}s<=na?sNH5(5{$Xi1(nzpmJB;W=1$InoWE0 z%GsQHJpfJt>CUBq9?;GrNYQV08svL4H)nyE+NsjLJ%Kq01~vh!a7(JTL0u*SNpguZ zKGI`xw6EnH!|Ks|`)u;c7Yx#A844IT4F^r4fo?hcBo1rVcyU81g}LB#yTyIdV7pJD z*Btijb}kvqhL`QJ0_Y&db=={^J@X=-eEE-K9A=0&a7;^bKc;?<-#oZ;Dr*s_8hHpw z$!ZPJb|oPhEKEd&!^V>7q>25e*KMG^WsYJmsllJcYuZR7JO`4YROrD2R$&%v@xi<v ze)GA5Y}-V^#V7reA^9|D3Vhka@KHnX(wgX_qVoLk!vvnRFCl@e6D9~`xb{!$J^zAp zhV}@S;vTJxF|0;L8oyQ7k!+Lpu97igPNSMK!t-nL^IJc!)9~?FBal?!M4q&~G={Ue zTZ#b+%vQN+(w)a=USb^5mJRK}FU`ii*>n}lUwABa1=#!LZVoXEhC@E^+9cYgX8b~3 z#iqw6GIC$yBo|u|-tG>Vd2KGn`Ait|g^^MAMKDSjPph<J6!op=#;s_0&ue)g)x+F- z)q4to6XCro+5!r(c712F`pDh%jp&=l&s;(P9b0vbG9=;YpZAbG-Y;dz7gc}e!fJQt zF0;sw<l1mgO%TUwRK7%a@(OC@rU@7CB9RGKJl^L8NxzK`nF&+zgf*g=7dhNHz2SgJ z)lgM31i2p{JuN6#ooM2!q4sH+9`1lQFz(meW60A@5wd*)24aKG4LsAtigL6v5h7#B zOc`rMIQ=dfw0CzaX@oXBne5|HswsktP{gfZ=y0SI&DV|h?dt-4T6v+8k)qP3#3<Bd zBIbI;E_wKfxbV4ay4wc-qJ1|~t2Sc`o^FG%gX>vGpom<3GwDS+Oc735O-we?^;+v^ zGcLuQV@V@EgGggbkVlO!I;6YIA?bZlYxv`}fn$8rkx>$76Uw0`ZK!6wF=10uWfc3l zlRiq*&9|xoi%qaI_YuLBgiyDGki^X&IcYHycaA)Ll-Yk=cUJO4XGT19VC*yWP#PB% z+!hF`*@^Voox#kA)EgU6Q)S>qiY}@?XU;!vf4lGY_1&YnWX;2Fp{AHJq3y<C<pZzq zGBeFkJLW@d;AaY;Y;^;=Pi1WXXc0-cuRk!!)0<o!0n?22Ot<}{d@KAKT+bYFeeh)| zk0z^^TlC<B6}*8Hbm&UQtF*Uk2%oS->}56W$KTAbMhGf1(ikKBwm&Kv4pUXan#)z^ z6CrH14gPgv@>wv-JC)VC%()Oh*<iseCEmg3<0_0k>H#|yDrzBB!B+0a&9OJ=S?rFv zcdHG2Y?#|?p;@BX1rOv;q6u4sl6}T=4LZ~WsnDXC=bT+U+!T_6stp%`ClBVvv=!iJ zQqhx>ZX~?si9DJIj7Ulz^Xm~4Gs3$D`j=Nx8UNY>E^mFxTv8$Qd)e&F;=d1{xvL4n ziYpeXxTE}5(46HNjo1qb`W6~{K6MqF;B~Wd3$}U*jnO?^r=X(Ug<4Q952liGYwcFb zG)#2|eK0#D|K#fDP(Qk?kp0^&a(G+uOY3Y4)Hv-}k%@N_4SO-bk@2aTs}&@RLO8ag zpg>Maq>o0n=ryFf;AYTR*!3|$)1C)3?Yn#HJ!pKqld+6@TM-<iWpyXg4NX9ki;);l zp6-0s6Fq|o67(9uc|NA|2<L$)Uk=?2IRX$IT?*qkrF*^ogTvg|QBGUH?=7nr{RFYJ zrTOAo2M1`Sc?=}_K~{bZFR16@H)oZfs)~V=2SMKUhXNAUf5%1xZ@f3G++50jpr|;R zKzOP7DW!4dcu!u@P>CKp3E(G-&~cjx{&UpaXVsB(Hvk+!UE10`GyF(FVZ}mYf*nJF z?fxsX;}AA6iR}fhD9t^Ox{6_Nf-io=V9&3q;<!J7j-k-j&)sYx+ur&HUhn={+!Ig* zKs}s+bHiXoQoV_dNe|y5iA~pClcsyQo<;X_As>BO+;yMdd%=S9R5$TsbU(5&5hUCN z5}j8%?oF5Er8n8ff3G2v961!~c_k(!mut^{ZnakcD75q5pxr>(k4l3*>Z>2hV$f{c zza6ZZ+Ui}`Ff<@A5^H@ag|z?pB17!HWCz~mbyc5#gFWJsy?w-bILrX-(a834z?K^Y z8NT<Q<JN?1Jiv<|)PoH1HF!HWceC*j_G!<Oin+Oj4Epjl%oDSud_Y!IN3o-w^vLR@ z71DZ1{n4$@of`X^@ae6sjo~Iyms-{X3m{>)^czXT=CX%>0J_3{q4jZ?qhxE?J9;xj z)2*H>^)P`R)t(T=k`lW74t0aOcj}uOwmAE8#DWd%EpK7bongDBB)??s4VzVeZRBYf z=2M|zYU^oZ3#N&}eaY1>gd{)$`&j;GLp@J%VR&52I@F1+Im_}ls1qp$7FO=@38T2F zpD{%`Fifvu$cXV(U-c>AxbH3Z7%%q$|9l~Pui@yy>V)ACOo&y**UnX<FBvtsOK(4G zA7TVwvqrGXQ&dEnJC~?Do6e`&)tq!;7h}6w>;B6LUM0T`nFcMMyMy}YtfqR}h4P2c zf3^rbro&{Yf_EwoxKxMgD=U_L6YS_qZSfvvA<Uwk?jLNq#U#~7pXVOQ>_W$Z?Y5HD z33t~Vs?T=*6;2xBvrh!rR8sb$81zR%A8cidrF;AyrqpHUS>h%gw}@vJn=niuQUJ&Y zp}ZoG_`BZYI+86GBAUs(Tr*|fLZ-g2+c4LbXD6`Ea<E4pk$cV+Zo_R9kOo{)UKw64 za?8+0p5~nGoY^p0^YqTAxtWI1&ePA2u*24NeC&)n*OYzrnQ9$At_XuYnyB@rQd^%V zX5&(M#MqVhR_lDk%(jph)QrNv<IdH^3(=rIMP@9~1C{26OP}9LEV5&qHqVZN-s^=j zV&jDd5{I_OsGHtO*Vdd(cPFC8oLQC}GQ3v3+_4UG$82dJl~HSRv*NbJq*82doqLxo zdzysa=u%VX5u~8RNx>}Sy~PO-#<_n68WGEf=<V9}%lfjwPO&0BR#cZ?H9rT}E3Tr7 zQ^zy(B^X3T_D`f!39(tb*Z3^jd!@WizKF+QUm5mKHZ{<;yWvnxDifer7dN34m)4{E zK#&|;3d(w4x^jcyyyPYV#&DQI|F(h&NrIN2)N?s;rFSbfh7dz$mRfjrYAcPYuS1+k ztztz69_F>t)lNU14F)kO;E1Dskb|2-*<K{T@zuI0VfNt=p~Y(}f9i(4_;wFbspA*2 ze!hX^aj!x>`fv9)VaD_mh&Kvt52VbpL)d8A;v?vfY#Waa^o}>YhhfKCyPFyH8#|rU zwVF+SU6cXtl5}_?g6OD2+^A>mFBcQ~_`?RB`(DXxyUNmw+3_ng4<S~Grjp7OM_Px_ zT20R<w|6)m+EG!hi1mTQeCh6-*a#eD)-@0}EzOQ--JNC<{S^FY`y0Fp_#k@ccu;hI zMkDA25F~%JIL<r5mw@pkwjr?tfJKpc*v&fYWdP#&jz>X3(mQ65eWk9U=(dJ{xzY9? z??Q?wV-0GDO4pU#ANT4TE<bWabSDgM7WvpcTUg!K7;5DH=!0!Swh8KgnNVEi1kX{` zmhjFFF>1hoN)JOrZCr@vNwi~|XBxy^m^lQZLNhF|G)>6U^2n7lVsbym)H=oyh?#jG zB52f&oVq{|nXS)aEQ75IaN4rYbN8{}>bBAc%H@3K3IM-NVPTr787063md5&Qe{vgx zzD1bcqzXRB;?cCKyIsp>x{aJx)7x>AciSq$;8*N3K0)ZqU1;$G1H^*n5VJr(g_+)B z_HfVe6*27!clW3<sU&kU_R1a2gq3;Dl$CSxes50-5P-*DPIMaNO(+WWDND@V7sIn_ zLPWL~J4eLWi*Z>MV>_LiGG^7wc7`xBP?tE8yKCwTPP5G0ER?|@3V1_%n-74T+$uxK zOKNr@OLMxr<fK1jf4|;!6lJJA)6_qy{{e!li`3URq)k<ebjr>Ya_SeJU@JXJui6V$ z$+Kaj-PhU`=!pGD!kF8ZUth1}1oriSad2tKYO*p^w00Dkpz4!LnwW~XLmY7tKwXTS z_RfnPA#;kL7%}ic@vGGLjyU4-at9sP7MMV~h`52Dhf%lGU1s>x4cO)^$=sv;0tM5C z{7&)dQZNGm-e`PV#jWX6-QVLte(00J`&29t?cia8(|{kIWLtsR`0&L2H!^^<!F;rs z%@9_|J6qG)F2>G2O`)vuWg%Yfa6;Lh3S>EZn0th>0<ZauCIHdSCu*s@Hf8!&JyqvL zxx9nUk#{%oO&9x#Po=>eMlUR@BleLb-mJb`MC`ehF;67a>78vL{N*u5l27f?{30_l z4+0^!PsPfMB1l<LpTGy-vc6MucSswSdRXNHVZ^&ADMRMs@(y{TTlT2u0^4@PBQqg9 zzWUj<ETXjJ>Zqp=n?|^Y(>FGHj1GQZm^)5=J?QyjZ{)ojeg5OAa!OwNY?jpvAA7Jm zmlVAF{7SszHBn58so0A~?3Xk_>kcSUh#1*ioA}Su@dL5kTr?JpJruf~;V~G^&ZYoJ z_Qqo8cCAKYGpCxpuT2U~+p|<u9L@s{=c_5jeQH-0OI(6p*b`CV&M%A$sL<4!LHHom zG__0*cN&vBp*3yumr_dg(bl^{Vk2GNd^T$DO7Fa9RAVpKzXjWm9d7WYqhNH5QeQ~+ zZMtlu9#(KiqNz9e?VvTOC;*({y?TVY=cO=diKn@6+_A(3gzyBj^jmY;k68`BYyEiS zof3A%a*pcZZ8s8z6=cy&yn49y^H4_KT?$LnbZYI1PV@8$P3a7EfyIa5?n0rEnbsuv zpTjC!VBv{wUpjkcpN%O1)D|<=honZ{ZRB&(GZwpMQezl;^=vj8BLG7!2!J+xRZ_iO zKi~DEyokd|->f|%;bHLtlcDwsyf9|_Fq{&JtJq#B1{>;bz(33M9D5bwMww&9)G8ZG z8FxH!dGADFEZ#vBN=$gnRQ?v5a1i8!1b1Eb=#1OSNo*@Zt!SNOWHJT`x}qCdNVaqq z*$Qu)zJY_u0twEuz7P;t6(B+0Bl57>qmyH(Fc7%F7YYVh(*OrF-;MyT;7wfG6$2gZ zgU-(Tnwqy^c@^!|O}z6*CbTmR$BbmM(>0Nt&}sbUm9(iw;IvjS6f1jzr~Ur9+XzoP zb}J*F@w!?0rxqs+SW7@wT>z?qXz=9u0Lz06%{(6G$fuiu+Q5~W$+$D^u<0!gqC+FM z>Thy}tUS5++I_@g^^qo{Zd$thw;8={op=b>D@rlq#rWZ9vi}IFkl<-4=huLXfgXpf zTErm-E0%e#`yJ2wH6LkCzh}d874Fnm^=<MR-tn=khfHmKlK>r0qbemmtR~i1FU^Ak z4lS6gL`1Q{wbggA;!SH58p6xiO0q`r@nlbBYLQY%Bw{kAFvI0Zy<XwaAr1Hd6{*;P z6De>p0YYX%vi#)dfZ6o_qxA^<#mRy41;R04c@q?)3|_~zQci4+U5fN^d6Uhc`)eu1 zO?w`Zod|P65DJxw`t~#qPE8-q8=gDV<6Kyrreg4@eQl~i%zbVr-D<{iX#z+_6EZhK zKA^0PWS=0fUtJ=f@-TRz6IHUFb6;Mnt19?yO64KyH&2!*-M5}|SlXY8uR~~VWt6;q z|1!zQ?0az8dEj6?dpuc`Zh8~esbVV0t48M?D`%p*gF%GxlH=>OJH+d;o`-3`iBsNR zbm3|{%3AxNAOr9++nxxHyAodYy?wHRp<Q^|!Xz=lo=C6jMuZM)tL$7iM49m5qj@Bk z(K)*95}v|%88#8Bc0DmXSlC!p<@aToC||`NR5N1%J%l*e#ox%@?4|sD=3v8QIo6tR z0rQ!P@)K?c0)lv@tgw+7WX1xNtjjpxZrNjT!JgKArdadhJX$5Gr26ZSZ2T$|HK$|V zY~)r`<B;Z%_1>}fq*KoUTWy|(1l^(}>^f1gf2(z=mi9Jq$FWhnQFrPPh`D&GT~y$f z%faOv@61SQD1~p}Cm6qiWTK2kOv;27AIdW)$wp}Buh|fv_9Iud>dMCV1Jr!Qf^q;7 zm$;tZ$h#9(zBjoWlA=?rdo*O+WV>hg>6ZPM4&fDzvkoLcTAxqa!pvl4k0U!%g<5^- zj2hP;{OT&FmBZSq7i2&fwb7S%E12I+DlVS{>y(rTRJfbmd8LQ_A;Hh))8Mogh(&lw z^ww932+z*sFdiTpl+2Sv&8NL!Yhus8XgIczfQ(2nLA1j4Y!D0)p2+55Ry^P0G+f*S z@f7|-SrsI-cv)n`ap40%z`JN{;y0s|$rmyhdi0)$fd(DPLqqA)eR>LI9{=3^_yyg$ zD9i0LA1PC=HOYrmFcfm@y_3fE1)HUvR)jpryZ4*0B~a+r5PN2qfl*K#9Mtwh?%3IK z9u2pzLa%*Il*UwYW@hhzhcL)*{woEd%AEP#_;g1?4LS@sD)TWG-CIzODYr&YnIsaa zmytlK<UNL8JtWjR3I6%+@|j2TFoxfuT(QwMxlC308sP!&h~!G#2tQ)ucmKlEMN=6K z(PW75Nv^jkB=-$k4cEBt)-@wK=aPyo6}_Nl7p`uRqf`Th%)hsqk3sXjLX(Lss#hRh z`kRD%8g7FF!mo(pU|wte@N^?Y<i=|NPoepA9j7brS;pg_kUM38*n-;{BZA-!x12v2 z0+y7?hewMqOlnlWZ(1Ks2SlWN__5H$Kp~B(;Bm0j%yf1QbSMmTZ!CYTf!}Z5^7Xy9 zk0UiPxW2nv#sj^B&gEfv5|OVB-i{gXA%>TjAv8;`*ER7>C-gz?{MmLNU99vxMrW6r z>KR5Lvs2gCC5+zKksycV^jn08=~xA0v0xTCQOZ+Eo`YVv!}qb@Wquc~G<Q<(cHL5B zHrk{cgZuW0m}EF~Wa;|%NGknVk&7V)4Uphlmap(Wj`0k~AQSpW=FnFQ65%OXw+!Bc z;+-*}{5rH<RFy$INzeJbd>adzBIBOWSt1@Q&w0x0ILEnI@DC)DMWk3Gmf=1>nr*I` zFtu0XUL5UwEok~6xTpyacPACOt2RTw??`5ddTzp%RJccFgCL!M-6$$#vz=7E!l94l zCJbtkq)&yO#uh6fKopZ_k;6n#Q3!OxETJhctVsj=LHEM7>k07zebDAqDNyLZ{w1WW z9j1&s1i{6*LmO*-*7&SfkZ^Gugkj|YsyG{i(Sfg-A_THJ2XAiVI=fm93xp9hw<HVA z9Unzq_KfAx)%GndZ0bo$!j-oqx6Wz5JU4}`TYoV)7hqFz-7ATQnF`Hm;urQu8!Ojw z*|)1C{f>AIpj&Em+`u-7{cdH}EHUd#IWFcvy-ASjI0zY8)_ap&0;$Q_L4({owyuvk znk$(56!$Ph!oeJG`|)iikkn{bb*H81Yv0Rjzp?J<et@EX9B_nE4KMWDqmS83UrStp zGh(Hk{V}LJgtvW%lMUJ6BaxF5+8@_kM%#r2g%)e!6Xpxn$t8l^i5jld;?JG3qK?|Y z4K0t`a>TN8!%xDHR^#f}`a~h%TA*eLEndvUYkg9Nz|BEFR%~Kd)EqRE+Ow4sWc=iL zM~lG?>TOo@=7S<~W3c9dBO_{+xWS$b=Snj5Hlv1#H9M7^H-{oXEkQI-Tkuh83EAkN zH8U9~(HN`khHnTjn-hTp_3OH>O{6qv8i|^N;2e9`TapQi8RiIexVR}|#!K|~DhnP{ zk-qMx<2@)aloz4&EHVmMpy~ELhg|gbVtyS5cW>OK^3*ued7r1$QGFD)gU`xaU}1Y8 zh0mQ%zF6g{CNHz7Pe-DPQ6PIa8cgYjBHLvKB)P=*l=Yf9amj<?!R=z8gb2pK{^uZ% zxAUT@9I)_dML@DMgA6%jH43LC_n!f92Xtn)xR~oRg!cuM80vuV<|a=#2P~&5>8Z$l zgz%!eU*hdZWGT-yfov1xk&Bi~siQF}m3WZeMQ~!z<D5}a-xu5=l&})xWn8`TbwAF* z=W&O3dCUuXQ+2sHD5*04=0aaM{rip{Pvw4QR@dLiTjS5ol?6Pioh5DU&2p(;BdDFT znq!krf{<kwH@&t>6)RRa9<+H!o)31=NG@*ON{!=tz(@H?HspDM2I%!T6`z({<8z%| zEfWn*F%vbsqV|%+gqz=M1ji3jNE`Ln`=aj!CIDdmRDMCZw6GNYZq*vj(~0<iHi*5J z<<icBls>1rRBy|$^DTSBTew5|pgep#v50+Q05*+2(kJF8-~?hiu1$UU*l>r`5@w$r z$V|q64d1Z@b<k)y>hSWJv%{!SZV~T8o7D%f+B&3G@J*I|RJDiS#~=R~DFKiTYW&($ zab}wZsnVlKu-J+E0bnPnAMXvPb+6hSS(I0s<^p#|MRtu%C;_~l=X(VEI8H;9YK(-n zz}IiOH~<CtRqLBO@?VxK3N4N*b%DBh-}%ptB|ibs<E6o0KjE0?^v-1N$HGApAU4I7 z`P7~jC|#}3mu>8n%>wghY~@@cQu*yPUqY*qr^q04d=_wpcVT~zhq_JTu`5uma{UOE z?}R}U{1CzGnfR$9nbLPSUa|&yt31Q|yjS~uP4wHQRZW|MEXW)Y0t5i@b_mZfgC;qn z6;Lk{!U<d!#|m3FivSuOuc}f~rH?&!Ej>j?5D>injntoqD&(9INZGFe!9%yHl7VwH z>>TK4+Pq>jG632jfM-}?NI#$U5?O-L-RQP#Km6Kn3D50iLOa(Hz0NH+8wCygnrYub zg3GEy3GL6e5NDT(OoBDKoxGMAxH!wEZ^iUTlt$m$u=;dI>F3f#lo59GId3aXeZ9D7 zD+pBVzaIE~GG<4aFp{j=&s@HWK0n1%VOcm5xdi3@8Mv1BtY<)4^qKhqbDimrBa~nS zno8YUd!4}wQJb(Q9tZK0juLVE873;DxqkSHKI#PyChF?W0zw=fg=17{{yor>*y0#} z8N}};;g0vv@lQC5O<;bIrbfvo(U0ss&AVF;xi^H=E3N|-^_~<@?}9QBROKuSEqB6p z^<{c`XC9bHM!y}Oq(ca^PT=k!S82j5UGIBeVSoPvx8eju4SnAl+i<J=DjOcY3Nef; z5nZ*uY_IZelZ(*SP1r!>{#3%Ck2Z`l)s$&iW0?I8I=v3pv{u~qNMJk6K)E*3yw6*9 z#xUM@)*!-7wz1Eib-%#GOqg54W-s}QX*xsH1sBodf*4xb(kcoe`4Iza#Pr}8@?jO< zAqwn5NYj2z%wfZ3h?k}`Pf}ISNggk*RXJeV*i$Z=0xlJ&-&}F}N?MI*>aCNINm{mF zpntgu)eS!k;EIlOHgzCA;K`UgPK3C9+}f<Tj2065R!t{>P0<-w$dI&JZ#fIy_<sY< z0g)H$en5qQhcmpIHvFt+7A8c~<N^&W5k2-B@3P}vXE?gTbAf<g4nrG@&9^tA81tax zsqFba66PQ{I_LXhdpN54o$2Cr`L$1RAA^t@Hg3<BfD9ABw3dTTHXS^SlMX^^26XBA z;XJyOA&QkQq36>adXdXmG=b+L&#mJtEWKlC(9jL#Hu;n$6a$)~(6EOpPYUl7BmK@n zwRij5C{Vq=ynm<6&YllQ)`)?=3iO@8hD;I%pYD9fw|!8%wy@>#{5(D>RZA9QV221E z+t#~{$D~y4t)_ludOFNdiW2rNdJJGm-po#U2>w(J|4JlGjd@XuF5a<!@<%<7oa*QJ z_3-z9whaJGM#lqeuermHoj1c^`V*yS-;}zx1hTJ%kMzGmNonR57+%gnB`&k(c{Ok> zJmvMUs0$TVQXyK&9`cCP<d(7Fzw^!UQbtd-rns8%;kj#4QDpH#jJ?BtxF#kTOu#<= zrJt&wD=GWk(E~JSKfyM=;LdTJ%hvCKLm~0o{TSPigsK!ISex3O&l+W<4hXUVE6Jgu zN`C=z!Sv7|@_p~3^IjSI3v?eZIezGLlh1RCG|Xi}O>3!l2+>yy_9&lU$BrA`x<N#x z^c#7drZRyCR5OIucJ5)Qcct&WG^UJRR2xzB^U%~^*ujmm+sRX-KMui7IRoY<p3pX{ zZ)|XuZl#yLpu_Lf{%Uaheb4s>&XkzqkI_eRT9#xcHg}&Dh}uZK%yc^86tF-o_{*}D zepkTtaj<(-@Vi1?aGuI0i9>j=nAX;XL_^I$G#jt$(*=ki;ahC3+M$ems#CSgtm7F4 z993oY{Z<Qk=Q5*4vfe!;$!a@4PVs^qP|W+3AM{=uUHNeyU+l#?Q^Z>wgo5;R--R6+ zS{hrhJ8c=Tp;+lXEDCYm6wFXK05q`t-MSk<iO0lBCy{ng;nSn>qn;wacAbxHw9oY^ zX{)BlNUHE}!&oukG~*)BXI^igyO5^HbQs@a$tD94<sXrt!tepfkW9hJJ`i`_t3E@y zQM=_N*Kv8$sT|5$VkH!`xlnjMq7*@2%&xNIKzL018u2y=pjnk?cgnx@#D_((E{I~l zj`s-V(2-%!oPsIh<t*74x^|4(3R}hHW6-Zh+nE~mH?-)gqx;O#vn*G{C=}N}HC<d| z(lB2xFUqbpExKauN8JYE&d$Hg%)ZdR(Alt+D8HLy5Le^-JZ2o4gGLS>HTOTKvs!>O zNp-Cu!Vgc9{P|%jABrsJy|GADdgY$q5)qy{S?#F2-^g-HEWV?2ZOdK4OiO=V%mjX> z1*Go%TlUKqe&#eY=)TvsA?Wp8PQ-aynMB55(oLT$ha~LORV{Cn#U-@ODMRR^$P$)b zEAB^c%AGgldcLG~5OLp|TlGtc%n8XC@wVLZw--B_FLt%V<grqqi+y@0;X+^E{!+dU z=K&@Ahzl+z4zX^yBIDR7(uMC|<S5EC<gZvzg}`L>@7GJJFCL!eo6FZ{Q5KrDO2YVH zp+yI?bOw}5&7k<2H8JBucDWg)I6jaPWzQW%g7Z(b-t=+ocA{{7&5(;7r^GSe@<P6T z*I3cSSP0A1v17Gccu|JU2@4%0hlmEXbiVq)y|I|RKEHld?;2i;K8nwU3*tuVsltwt z(<jew>ChpPr2-f0GN(gKD(L&uHz6IrDCGrt6-hbhhk@hu)R%s(dIB-&yGHFXmLAqU zp{;7Ip2}Am9l5H1uZIDqc&S7HIGJFEL?M^60k82}7zPsx;;CrkEmJwJ0XdJ13#d!l zT{2_yV^#aWw@CeP%ys0M^Y)$MmN?$BaV>zn>uELmqx0TI((1+LeDYqt_%)%gfQPxh zIVAEmxy>}H(GulEJ&*OeH&+v8FL4*3(Dy3-<(62*P@J?nX)y@Xj%zLv_)to&hplSP zSPdVYvbMk{^MDGBOk1wCN<P<|w{0ZnC1Ynp!Xe}Y;vIxhpclkAS)q?n3nQe&W_4PM z%iL~#9G)Ks3w@GxjT%UNI8Ca44{ra~WFZo3*ayWPCcz%}ywOjx;lb;iI~;xz;YsJK zV*VvWyfg~Vq!F}LmlvgT^XKrh>dHJxa!u_<NZyl&`K!4pgGLQ+{<troQ#}&&&M?j2 zH}V!j)x4W{@LkQoD9h^@ex<7}Het=vb45=D2iK-YXve6AO}rkDk@NXGMsbERQ)p(f z7JZWnZSZ-M+ReHWSZ@=?05%N}_y!VUBVK`q$VYJ5neo*uGxIf+q|J*o*nAmSlD1}E z8`V%w-g&(rZOzD7^|Sbq62<LWUV7P@%Ayy`u`ngaYmLheE(0?PKlZER)tMiGF7UVW zh`L+ow5$grZBEJ^SHjiAuq9hWeVA|sTjuU$)!CdZ10_w<OA9(3fpgI2SHTewIdU;x z%%(lzLYP6Zkfv@+55`P;h_poP1DZs#e7pEaWWnZ2<91V@aRWmf_tAATc~2y@(QD23 zKAZX0_rw>?3zuOV_ZXJH8&<QaL2$*!&FkU4PAFW{V0~QjksUEk0{`pZ29W+D)VBgA zBda?ux`y_dp&g4(I)D55T%go2;BM#lngQGdgdZO+hBxGGAELhc&sF$dzD(<BP|CWZ zh5@{R#^B4lNP<I0446seMThb~qJ3&X1_--(HbLBQ>q*_p<Ib-TqJ{h~u2x0NxwaZN z2+V_8FAM9neLqI|unlHEoGKj4w!TKpTaocwdn74Or0OB9|GLOZ-m8qngKXOK7Rq0^ zm=-*;-$H`vFX3P|gn!b^L^v2Zek~9*e)H!H=iK{Sy+2Cg;Md;NJl_N^BXJg}h+O8! z+fFopzaT@5um<9wHPuGI&!L1EK1Y>vGwCY8tvcSs2Np}pzo7MbzfNjq2?)Ld|L*}E zZ;M@-=3F{J`CF4%EVs)TDde6jeeDH=Qbi_CD5LlZvbV-nQ(HkHc3=;MVu-?99ukB_ z?vO{UZkOVPGJYV2MtT81A#mx>nRgkl7Ym65cPHBJ8EB8N;9%!uGF6W(xb2*k524_t zp~c=eGflI7VprIz4s;8iJoUOF|3%tn;I6LmBIiu}+%{;~WNj|^N-nSM$S2ofefR1o z&myP?n<4lLS;FYI3*j)yl?AVOW8m6?64kxx(-f0`-&qNy!okpYfuDYt)(;mCgS|A= zG$KpLVLH@`L`=shQ^ql%rY$h|=Zbq5Q#FJnUdqQg2SVb#c@a-b(x<dUf}gOV60{vb zr0^Na&zIG2PzzYAjWS-6dkiws;58Qj;)9>z9D0AXh~&<{D_UJiaetC4gN7AfDU%%} zmA{WP;ypwi0US~8d$g5f<O|NKi_@PJ4klW?VBMf=K<v-X7D=llrSE}@n9pH&b-6W| z*!y_BmOZoqv)xr(TB8HBd#X7J{GWY1trO&$NegSIBv~v_O?ylELgq(aUPtp!+U(5w zDbP6g!F&G06yS1$A1q69jkJ=F0J7OfGacVS`_zA=lz<>Q<g}XdDBOWi^nOO%gmV~M zA&bX1ezmJE0ITddS!z~qT^V8k9@ls-1pJtph&4+(M<;3r`6j|nnR$?WP-lYmVkFxT zNCwE6pJnxc`1YBnUg#t9B1NEUsC_1h_;T@+{C7Q1w`}s9T2z5WcX)4S*1FXiBU%ga z0|3=uwJC$3G?r@mW$3u^_iFczDcg%H7cbx0IGOyvYcN+_n;w^Z??G?L3d*V%itWKN zW`|!Wgt3g4-D`vh-n(K`(UAA3Vm_{KYQ|`G3baHlcF%mAtS4rZAsoH(##nbX&~5En zlsEphJ?rEx0Ub+%zbE5-RXKyutVjpP@hbW3hw<fjv;MpHdQ&i!n$tBUoLlCD_C->7 z+Q{#bG%w`wYt_pKQ*sWpg>TbT)0N(4x_$j0)BAS7L8h0rE6+(f^IWFF-vjD&gFo%l zX3u~8|N7U5Oh%UocAos**?;5F{_)-aS%80=;^+P&74jF1@XwA1D&<N4GD!*kY+C{X zPnHub&a&D)akHTbH`NmY%@JP`a2~}^{WEM1;6k1~?I#S(JPJ3bgf1f=g<#QDBKI=L zSPLtaPq}{otN64W9q~g2@wj^8bJut}Ia9_T*v8*O1cZ}A1p&5DjMLtGzd$m+_7XP3 zvMk!~c!tCKd)xyLedeMS?UOoG0W#St>x~;ju1}?sP9b~$_0c)+>=^LIqmG+65&7rd zX{*=$PqL^|FaI8VVcY(*dr`oR23JP`UE6kmIy!$6{06{i|4TLepIek<lIC&!(;7Nn zKx5a@09#tuebQA^!E~TN8GF3X?Va;y@_OaY_Dz<zj7x*|qu|I)%WVe&DH%RM-`$f5 zj+Z#0wL5v1?9V<p=N*u<jckD2AfTrHdxhzzb<^5kqgc+-apv-!Q7!-1^e6o;eeP00 zEGvkdp13KbZ?SV?t%v>B(2)m2_cu!4(p?_Qvp)`pT=u{Jw*Uh>vI8LY*?MF8)0Jsz zDf2XJ@?S!Cb#t8Mf3Mj8S4k~QSnG~LY~Lbl{<)2d70bA-S*kNjT}ZDkG357ciW!f! z-S02o1&;nQdnY&S@m!4)Sx@IrrEY^0$x8W;-m7$3ATNu#36*3@tfu{f7IUhNr}zx| z#&{QxueU<IU6s<`D%mr8as%^nm;FDaT$I6kX8<%(Ga9N=b7>P?-m~>K!VXUxJ$TK0 zq)^+AIWs0>s1JyOk-Yj_@S_!wW9B1qt%DFR5HMwvFPryT@jkaw2pQL^=t|dV)0#3; zy|<8eEP3;cU)b>25Wkiz)zRTJBh9Y=<#TJiE~i`sju2Q3{$>8}6~CACA;RTH%{wLG zM{$rEv|o-8f_MX(k4PP-XOaXqYcgT~m`Mlf1$#lgm!{nN@0zOTY=|>6%u5S^OI5Ec z4&}IhLubO^7=bUu|K9WMxfXL(j*378%Olb!DvM0j4mJH~i#3yMtPoZU;I@pQt+>(g znchdZQGSD~E@=z1Y{~{@0!&)`zr=OPXskk)e{gMn0X;c7tXW%;oG6q9hi&o8RwvT( z(+rz{5w1~dEN$1^6j>ZdThkhQaN<oxTxDpx);|?71XA=BU8t|R=lKpT>V;cIhq?wY z6mxpt>+J!}89YwzRXPIvK4^aT%eZwkl5ShOZ?v#q4hQ=w4OkSYugMaSv^A)NKq?$K z`^2Ua*FFetH#8&yd09c5bfZ*bYOBh+>mEIV&9{*9s<R$<AHFf0c&^5cO=|)yp|d?k z&@S`raIL}OQO_fbZ6s5?tmut8y-9jXOa01>9q;-+P!|U>LqM@YL=gXM?$AQjvOSmi z>8kC$Z$>qBuC}tnw>w29sGV!Bz2(;vdGx_iEXBM;1a8vy<67-NZ1fb>eOY5*czeS5 zbjEZsDUXkLuPC}g-uAs}e6dLb-o^Z9H>@A7YE8Vv9cxP)EC3+SLWXwO&E83?3X2D| zs+CCqLd8G_#X8vwqNF-M3Dhwv_kL)wbMCgNfJBZbf0}%9_?6bF#p#f1wqO~mJIV8; z$1Oc6lICU0a()i`bms6}q37=P8DA3|FW&G!#(w)yPxVp=wzBf!##jES5vx+1oBSTq zxreS3CU#_@s&~~T>Cj?4rB;i##t}FIr>(K+>Vsal#1`HN5a$SeXpb3gxY%8-(=I>E z(r+LgNpMWtkVAw@a>rc%w}i=|Oy;I8Xyrquusb%O!%YjPt-iSOI^=5A2e;ULw@^r; z(_XkUa05g{+$B-omlf-?wD<|rYe>Ob=?aK_1ZAZFU5P~$SoW|6p04zuL$r33+Rj7H z%DA*qwDgka+)%JKNFsns?wip()NteA=6^Iyhe?M|4<VYJen=oam&ICm2KNk@Z&vMd zwM?w%gimY$H$H8o*^N&qVk?(pqq|P{z2RZ;d#1J{pb&)|#?obI8kz1p?=+*4)yr%T zWcAvtW;B}9iNe_$A!Q=rI|ES3x^to46y~aMQ4xTb2J?{z91i<}mHm$`TMa1-yej)- zcn3MC?{@u7>fY46<Lb`(g9gse?=h7oX>;#-5yWdyng<s}&2YpfK{&5Gu2B#(%P7AH z%Pr}k{$mT12=Q-NrUR6tbMV)%ygxufl=BK($jP4|nnM)c1`qj<#<G*wALicOW%r7O z2u9pIpD_hWi`F7JM#aZ8E&~-eSuOOOTchH)FyQo6l7<MLQG>C_x*L}!$H=e%Eldi; zZz@?RLWJR869_xC2Uz8>@LpfELo)p8o1S^-1*I?EhZb>NptegBV<t8c4x{&OFzPqI zUBm`l>J!*x*zxF3&j0tx{{GbL1neTB$uUq`9jCGGWL6r$CF&o%i;OXD7BJw0FHbBc zuXEz^QaM=ZHU^$7ELoOqwg?RJPNj?$S{bsl)+wmw^DG;u;7yNpul{l8{$<dfycsyu zd7jIb6e^wAow--N_2jNQiMZC6Ln1k@?Y3U75Wq!C*(ioeJX?HMruw*+;wD2RL@7=( z*U><*b??W&G?CjW@@GW@5$fU&P<Xy?{0?fndAsFW94!h;_TAQI;GWUu`i=ca>6edD z!re@Gv(76x*y7j{5xrn5$)7kefK>h0YlxrZbEJvNWM&Qb_1Tp=F!sjwG`f@g$L9MN z++EaW!NvC?(+*K;|0R!r2s#?WV4pH++*u(40idG(^OH}SxJmCmjOmcN8~Jf+O6$sr zU2yjNf%=><d7R;5|Gf-n*8l&t4e81mmB%~newiTR!XI~(fZ(jPzCvjafQ2}L4KUk6 zNBbW?2@)Tum-axu-v6jQ%>GK=*MV+_=<j~qZ*U;`U_!F8U<GC~B6RG%#1Tt>=lmq~ zf>mp(M1{`RrDsE1<{T<lugF)f9_nHmg)E?$z>U;ft2t|;pFS6A82&e43ouPSYsHGR zfX37GUP@T#Wa!`iB<E#%)g@iaUQx3&53;usKMTD;$^JT-ELg2_H6AElXI*;yw^{7U zHZ5!lMfIdIRqOFpdCJ#WSF@OB>@?h18j5DL3k|zSqN&gyZ(-KjC)vl>W`~@CGFn9f zG_KSz&ZbD2`8RJc^raF`-*&wI9x`Ct5>+7AXArDEDpX5v&O#Mm61|Be@9O6H+^vlT zx4g+cKz&_MaO^Uu_QHVYpDiu^kFH&P5GNK77R9gStQ6=1FfQA|olozEgh3OFn$;3t zLA8O;ZVi`602s4_Z~v0&Gd$agFJ+o8k&q4tQJO)o?;s^OE{gV$);>E#wSVuqrsydf z^n4E)lS_}ExGfMaTsxr`2-#Ed3`E|n<NI4;u|vaolR_beoK%}oF#`#$Kp%QT;O-R( z_KTvUAfaP?3j9QS7H<Mf&a6;HPW(iw7IPnnautzv@9%CA-fX6G8JVY&j)i5GAknPO z)jK&imR@Wjt+pL<s><~fA=x5%*@5QZHc<Y}&ED?+`hHyV98mPsvVcASkde!evr3(e zMWTfm8zD+%b3cLm>C^XM=9PP)19A8}UibeVNDNNsg&r<q)>(3#yy3Oii>odG-b-N^ zxS@tj&avx*cNBToOtLiwTz>9fD)G!kVjUv561s=XFo9m*N9N@>=x}jFH1bm`h7R`e zCrFtbp%x30F4qLrs7YId0jQ?GSMsUYYXAo~`V(n1Yp9wWd*an1bl2-BXL7oYV5zUV z%SMxNFizaaVltn#qB7^JEC0(m=4+~6+Q5zOyaTwMwIbsS8i7k67uBvc7(5cU{U2Q} zL>>s<&Zw~UdUlncAm{Sm13KYfuqaKZzX1?~75+WT|M;yBC9N(H><IrY+W*&D<qYWY z_w1Y`OA2i~`B^)_Cw4JG9rxesmQOgtTDhoEgvbzhXdcy;Zgt5;bCYmJBB0mC=|i(e zu6w{=Aqw(L-?`tk;C9fJb+Ah*0-)u;`eq}8|9HJvKXp=6am#f~#hrXq&PFZ6G0iS3 zqT_<n%lT#ZzJTN!a_~s%tn<KktDJ{bSUwYTT|DN!HITt?4hO2R(%=oY!E}NDYHaPF zc*tCeAoCQ*%M^jODRKs;jEM8MuifiyjC00<zwQq$Lm6{zc;95}@P1HZssk(y6Id(G zvkYJ*KglqjK6fckee~Ts(^_ZBs8Uat!(EMg8bl+V=`G=Ojb*mVk?B6oHPc4mdLldL zg1N*3f$3D8y_&_aFMCH3Y75KWFTbLZ3`eyPbA(|jL=<;uW=H{enP<-*kn0Lx6OSBo zZNAHgSU4!ZC_dPD=%k<NW&22Y1fhMIdVb!CaVeFvW~X#hc2Y$aPTKzvH<~iYjr9`w z1<<!HPJe6qTN(fYO{(R2lC<>9#8M3H(=RADLS42%seN<#EoApl(W)_^VRpafvTmuq z&S&qi3k9el#bmJG$0GkVjY?+`udACjjB^w8N8)(HYApDNXb#Dr7XgJ*UrfE!ZlV&? z2)B_U!D^xVNT<1yesQsZ9pp^xGUMn<WV7PEUhu>^^cag?g=5+j&tW5r8h?JkdrrCz z)BQu19v#$o!t`@gTCP~{P-6!!8lWx<Ez^B$A^7^*jq{T>tUp1u4~L!~;=YyK90L-m zZx%<hx-j5447hp%z^U0Irc10NA-LMUC(Sm9@pU(^k;kozmH1D4kPS;afMqVdq8xJk zW&<f!M{$2t$fcz1gT|cOC{K|ytrFvv;2P!~08!mbRq`25ZAN;IfEV2R_=+M&d;mtR zHr_W3sKsTS1i~=@toz8(7EJrx3o!Y23734RIj8|4;LM$$E?~yNRG@d1;vm^t=(S#f zLm^t+Jv`=(AISkq2rz~t98f$a29FjsY`PfX;zo$MG1rj#Egd|lSiFD}NH=)O7F2}v z_e@@6PJC-v6m!MoD1!DDV8NLDt}gd2UAsphWlrzC_Su_ofd@3mX$HMdAZ2}KBk?u) zZ6BkI4IXR#etYj?ox4gHq{hrP;}BYTi`BbzlVR=X0CgT)83VyVc_6^~hz>tg@DYnz z*$sLbTr+Kq0K*ZE_`_)29WK(R)grBslJ4#;S+ka934gwJ@QOVx0YPTJmPLkZC;fQ> z(?uBSgZGzLAJD3kDtoNwPuS&8D6+U_bmOWFMnfU?kMMx%-pnD#(_WP(iMqEP<R5eZ zsNlpoB1g?d2-gs(nFEiB;W0eGqSM9>bbQ1p*=1#`TU_vaVi753hzlDaiyukTL1R8& zA+}#e+f>tE^F|eCh+%0mwt)S@|7f+W-hNbuz#oA~6<7_GPFcvW%Ux5wNFb+pYM1G^ z)H3nlJjXb^-_r={m;2EhVp2oVCcOd6#`v{6`r`z(!8KJ+OW{Dd<Z$G$he9cz9aoFA z`)5em_GfaJ5fFr<HT^3eydgK0Tbl+z`G$SWj=<F(p{oimG>QsF!EJ@C=PBs4n3Vvu z>YMt79|uZ+nxGEe9nvj7T_Xd}g#?T13l#sgM%C}oNN~%t$Vv?oAX3vM-1hGMH6ks* zmF@fnC!#l|qITU~KOPb(j!lihbHd17bi?i}J;3`UtwQnkc0OInFLN?ctT%V`=m3)5 z%|n?W!^CP_F;AsFB{sOEn(W<Htf8W}UXJLD{!6X4%U@*c?{{6-R+=vG%M5CNd>)v% zTdU>Gey0=HfIC{{ChuJJE7I+hd`jRyaHc6&ed0p5kl&vCyacETQL|BC)6uXDgW5th z>XmGKf~2n!aY&R-wt+NL$hMJ{>g!}?Ggn!bK9y!<o6z0FYSQU0s9=A)ARZYEP90-u zppl??zx6N<5fuw@{plHC>GXRp)7ZY+yFqZ5uhIgEQ_Vu`{U0*)a3<&tK;aO;{R97< z($HrMcCc27l*I1z<8k}Vc6N3Q5X_b=gD=0sR09NmJPk(mV1Kugf)0KK>`z1RlkU^l z;bz=!kJu&#4aNHa0eoE@9o)UeQzh%~0kdpbPjWUOAP`|W*~lrnERc%?mf|1Ww+udF zPZ~la_+Gxx|KPRK!3_184P~aM<g@7U+4(8UaFbMGr#E2s%@z7Dc---3{brN*If6_} z10X5z$z%NG%=+{YBa4p?LFNs4A%Lv_(80ZPK)U?mC2aC1&K;nOw(l+5o?al3Qf>fv zAzyECgMw-yvQe48t<L#NpY{eg<E5fdp4Z0#V9pV163~IZ(6?^nE?=d^?vH^1q{geO z4uF_xHK6i;?`^K!B$wm_ex;uce&4BaQd7wi{pH4z+@<w}*-s`}5;xajmIMSWfz80O zYxyhzU%~hO>0liKBqYapa)d{<-&pd0yT`E;*P_%m6KcuLLQOyrHoFN-*X?u2S02ax z-WP*jUMC<wk2|TEZA=u#+p;e?-mNmpx-bLW_V9`W4}A2~K@_xQ9QyOm>whDGS1)xx zU|ISiWvTnbn`^B9tn+}9*YcS^>HPAa&L5z>FzAcd0e{&=RfWxx`?jdk6JUzoV90>& z6yVDtPYY-E>tjfE#_aE1UHM>6Q1G}(_dX6_iB)2S0)A)jFL8$ZJ<=ghU9@C@@7==y z>YMuVcx}8uF#hPdr`l1>^fY6Ecj~!JK@t1V1C$R=q|pbc9FUq*RecPi`2jFL^jb9l z@W+VnO}BH2e(`~<NILizuXtT_eaT0VbAOfdCO*9tWD$EhB(6YC7x|lj3mAl!1ojeD zjl=TM6lh<y(r@Ue<j83|cR5q+c@Iz}IFaJhc7*P$JZ^iqAO-Z!g&x2(OU-?TKBaWW z20`aLMc{|8qB1wEF8dSZG!OoQ0+my=+b7dJ8FTSwMrJl3UM!Lq3H*b<?{VsnZsIWy z1`t9m72Qre17ckS(J}Etv_Rq${{oo39ck;jlhsbwAOOVK_FnG~eaJF1%sJ9Ya)PnI zJ@MS#>&p%Tr~L|f%cV<qj=<%%+3Fnve|m*s%pkCY%dE<hwdOm>(otF68WFBwFN-?_ zDsjt90g#><XeHZH1@_dVb>Zu~C<2TkDTbTI;*A<6N8~|&GQ;xC0g(=Z=-86lCm66K zKHaLQ3x_^Umet*{!hr!OVO?<F0(wFZ=V_l9lVlh9KC9>XWq<zpFAry-;A7MdnZX{E z`(%sucFP??vw?p{`QQ3{NE-$r6(w+|BL*6H73Xu(fCNtDp&9-V5NqJ3nQ&wL>HEcC zSg?GjVB3#Z2UUO^{5lbillNJYAD_N&@*5~W>vXGqJ*^r8PP3mZdmve0j_U&;N-{J3 z=Lv#<e6xs0F{Z$-G{BFnOnXvmlA>($EN|gICG{CE0%QRufkJv}Lg;N^XL0e>y>VV> zM21jQF+z*$JE<wo9C7M5|8(jA#ecR*ABs--zqO}51VZ>gul$`^|8DwK+2Ss_i%bWq z1^W*h34os+2V6!M`rI@F*~dchC-QVMrqgGjgT1^#rEb~v<VzO+iZ=mElfnNEV*gcT zF9A>$f1ahOf9B)t7a8YHck@4g?!EK>^Pd6qP?OnPo>e8!tncrE8;kxty~N)@7F$T} z7urI_@9jZel4SPR)->L8MHs<~WwwdG3q4Wwt}6O}D0>T_wzjo@_?$XWpcE?(r9g`o zcT&8?H8>OvZow@rTD*AC;O_3UxTm-liUu!UBqaZR&OOq5=bLxt%Ve04?5wQy*!n%P z*8{>xrDJ_4q&&a+lJOWx|5b7Q^|yN{Qo3ag*;5ES6K*X^t@rnczkP=bPl2@XKUJ_& ziCVu<=olZSYrrY!`aVrAeH|}VG<#`x=LRa}+mWfsYt+%8@S0r4@qrS5yV55ABbP5( zEHVDTtx$sF=k(QobPW5?<7>_5KW2IM*zps`qVo_AR!a+sa0LIQi;cqTKv>30V~N?H z^CM=WC+AnwkL*J&#XP&`3WQo<cu@dO`_Ch@0qEx~htV%7dkp3CD6h@uQGDo^L9q{a z2vzAmADDjJPhfCob&wE0>Ie~2pi@RcF_Jb0>f`?_i3^A=3owUcge&$cxqU<Z>obTz zeev{b?r$5W4=<6GM`t7E0yi={bomd=@r>#(aC8b`jJE*8{hx;ypyxs;=wvGLG0K6> z(?Bx!UL46XSJoObvjw+lQDIF1od4pEPXr8)Z0nW!0j>I$F8rxd9G~!4O_M96#0|G# z=HJA~)Cz!=cYz8_+EHccnu5yqQHA?w&tjEM5p~WEQZDv1s|&=OhnFkg>O_3=50M|= zDHmr9fv&L%?Qi`%MgwpHr7cE;rmwtLaGe~tFL`;3V2Um?F2aiZCT$(=8=7H?9IyNO z<_%l587xZfj6mQseCC-N12P=Oc$??%Rh?P@RUJq;Qid`7^-2cPq5)o{;AE>jmh<LC z9pOz4@As4?K6`iC0_iZD#|b<12U1}p9e-Eq02;Rh)M^0jqBt?o#`mWc--awfH&Zx+ zn6z=LnL|WIK*dVrnw`62VBKApLK*+}>|&Td@^OC?l;ux?x;<@m9DKf^a8;vz3@X4a zD&K$`+-|c!_P)*id^M$l_8~$QMfY#y4=~<`i1cl^L-M1j=CcrGi1jc{wa?HUBvM6p zn^jj>Aq}P^IzJD@Lspw~2aK3FUy7J~P}Nb`MEFh4u2~eRU=%L?HU+<(TK_p#Kr%-* z7YH)2v;yibM#5l*2EE)e$@%z2N^9_dP5}{OLBrlBexaFqOvlwd9e7;m+U(v>wT#CF zEB}br*6-ipKnb~}NVBXiPWIp4?QfY$0kB?>yKHm7{63!PKRUam@CT9&7;Q>;%x-Q( z_Bubqoz?B`S$pxnvVQ%?7ymU(F89`#X)*u&+;6WS@BZiWi~llL|35!|jKSZ;-0Q+N zw>N{jIGY>W{qf4d#2Oo$i;wmt?H{i=1-STl`Tu>N=dbrgL^w1&9nCqkl})V8O<g$D zT}@p6`2UTaF~poh%gW5fl9p4D>m|o)b1R6Y3oYkMftMT-RxVH#b7x5hJ4Xk5b9)zB z0S*OodkAnT7e6qr8a9WFm92}pGlz_=v5UEsxv7JhIftZ!t%I|=qp_(uhm^USm8rR! ztOT~081`Q?_DI`HzwbjLebvY0a+lcD;e&RSclMGe1T^aG1svI0UlYFXAp4Q}cgY`Y zbnzeWjML>3(0+X6h4XCk(c=g2PnWK*mr;x@d)EgC3n%Rk{U>cV9>(r&7H)2COYR-Q zKWg?ajmX%-q-7u75&!i$8$6*{VZ%Nu#`fRuKcb>8NHv_%PxIA%;7|MOQ%FRKzpcDU z;JWtLae&t@9%=So22iJSE4p8=f8f7$DDdsHdDEo&TX0zG-9QkfWA%SuKr8g<&oK+@ zi5o^TGBPUK&QlJJfRL?B#3OVf(W%~3Jh9OKnIHRyKPNsI?6q6gVCcQii;s_QwEPYU zhxu)N&FTcnMm(V_jghL&%_K980ww(Kw}bxr_Nx6{R~J1er|O02_s{Pa1#vJNqdK$C z;1BjM)ZhH~0$0@jT*gy}?1m+;UC+aLn+htBpZ*2CuyCsE$|Lml{{BdS^8?u7hp*Js z)M_etkaX~Wldkmh!oxHJStvoVuC}%%SMtaF8@$2od@UQ#bEb-!zALZN#m1-hMx9ye zc?rBxrDc<1J|-tQ(PD#aE^co1hepPVo}QOB6>W^DHW<cl1)uKs=pH&0T`3Wo1TFtw z;DLW-`mhIjfCRq1m-6r2r68YkL-${yn<^{6Lblb`u;<fw>c6`n7BQmAD;;uEdyDgO z49Azl`Wzq(>O|tlV>AnDVut@+-`scX6y*>Swd3ut61T)ib-O^}VsFGPod<$67zVO* z2SXv5NxJ4O==Of4I#y{{9_~%gt&Nh78adaE4eJ?gdeD?UZrpPmO^c_ArE{kuNz)_N z3Gt&rF>%>$pNnPf<ZtTqig-!6qm=C0WO_W48IO6EuuUH8rG8_q^=|hRrcj2_xo=F_ zXogx}+SI<!E*Th{C?x$wdh-w4KcH$x;|=W{E=!@MFh7s2JqYahSi4D8`!Qa+&?i5` z;((GVF!K@MsYOOa5TW%94aHoxzP`VGADg8q{QUIv56TS{2wh*@JN!i9<InRG@rUer z%HGq-J(McbRhkkZgFkwaQh=iuW5{tm?BR=HT_}8-d={Qy_jug!A}KMQWTucNSB`An zY93F~O7YB{b69Hsqefc>*;9>^+z%AQikX&r3%d@j39O<*=|$8g&y;cF4SG_-<__Q^ zg6xX(qls1++mD?<Cs)QqzW3rkHHxTySz@uJVn!T&o{POEo3uQa@GG%hN^=)wBsn2% z`49LqAo|_iQY+EGdakbSIg*a7**<{bSOuPSf`SwQ8Pu0O`AoH_l`1uHVeKhcia+&8 zT}A0QGM^|ho5&T$s8~2TI+*!P`in(BkEw+w!h&KUb685Jdg`f0O>oLo4eVxr4?Yr? zwppS=Z_ty4p1Zo)AgpIQMVu$smL<2TYH$E8um4pnW4uje?*m7)PC<SO6+PTFimRD% z_q$qM!cG^xh_{Ewp(Vw}#s;9%-`RC9y#LTP?jOq?MzdF2InmhLqN1Wf-M4>V*1D(& z%^A;dC@qR^w2%YWxsldy-vw26gGyfT7{)2cYt+lI_kK&O*WqohK--hcn&}dzFi1=( zhYd*9K>nDpVhVKP{@agAH6;R*pj3B#=GO(YwH>?)#x8!XxV)VA&F9wPSpVo{r#`zq zrgVaI6fX`Tbc~Q;87|<#rxbX}#dYlIh`Mm1HV)7;7voLo@Km|*1`Lb7%8B+@z(naw zQGlKY(NCyH?w|`tW{Rv@`0nOGvg5@cOgeMxFc}A7(G?o$mF<w78BdRnO)V(jd{7W_ zgGv|9zo}9L>FL6}`<7phNe&C$3eX@gqN0FxMXZfSXW43h0%{-ElgA2kb#WhNTclb) zsGEL@QTSJzH=W0>A?XUj!U|%${UD&dxX1-Je%+VbHhTaqFV^a24A<TZJSHT(q`+$O zPh53ye8GmY>jafN;7TYe*KJo4{v7nhFneG;?Z(>0`Y;Hl_cCN=^-(wD<4?2d6+F<V zx(m-Fh?#m^`i)wqmk*BMkv|{Nds^o^VPR}n8y`~eaW8=}tkc^0QHtl-lD=gRZtOB% zf$gMz5d<k=6CwTThY+o4p7bxET}t7TWJ#c87v={T>I<9u(KH}2lkNvA(R+KgD-HvI z#XSY|knacvi0}iPnbBL(xAt#y*~}M(y-U=HllyF*kv^zI%IHNNU&z$}{w7v}{RJmq zai7f=d<pUOa8_qlTX9evp`0qsU<|%Bo83QsUe-~au{rN*>TPxYh&y^rL#ry&gi$HO z+>$DZ44S}phA=U6JMr_*1phuFKYwS(3DgfF{6~xfn>^faVH8f_2D$ZWzKx=r4v&e@ zsp;t>x1AoqXh42x6_i3Qg#`tWXOE^2F94fS`|jw1A|E;I9B=Vvvuqt(K2e1myKHOq zVNlJ(Hs<XG%N*=jh#f1crnULX3BNWUy#ukILK#QWe&$o^=Cyo#f~xtp<AAwD+-oU* zqpsd(3D&AwKtUqWIgzW4!=aP5kuW}{ui^2t8njN(yVbp4KEfFP-9DjBTQ}T2Ft_x1 zt~nHP2G|GzTSq12@;rJ62!;8fGsKMv@!P*JoO~dl4~*)=4CK7RIrQa4f+)QAGv(BR zh`>@Gz)uv`z63`~Q-IlC7uOc)wAu;RN}_OC)|g5TtV<r$@f=hb>@H`ZFC}6&6)b0l z7o}Gn3Ma>h$<EYpOG7)1weuP1%umY=MzCx9Ux+<g-Kcw!BQ3rg{PA|rAnreey(9kQ z`^JX3#jUs(1|R+X{Tal>I$@EeR!sdMii(%;UKHvCflnnAp9-O#N>=t3^Fw)<m}C=? z>zZUfEHmZIqCew|SMgdcR`h&<G}e8*|K+uZet7oN!W5_d+ngEiox_u>3W$>n_iSn& z)RnxeuSD-3!0RGfl51k>TEgOPYMQEsHwM`JFqw8}9UF8_m6M2RTrNEI?D;&+Dsgp3 zVe&61N8Q8IGg*Ol<rDK<I0}XObE+fy4n~v~F2d7Kn=+BVHw^m7)tq{XqZ<y5H1|=3 zADU~c`^8G+*}GuDDdTTbHuN$X*uqRo(I%3F49PyS8M@o~XQf=Ip#7(l-z|r|?`HY# zEThqL`lb##xM@G&=6&V|*F<c`h@Fajo)hF<<~r+}0_R&bUtanZYl7gbF#c`TMv#Zo zA-a?CALHdut5D@}WI{pM$mr?mxg?+X08?jDV&GUgs@Y?9%TuoJ8bW<5rNlyPDj5MI z@lXuJjL<tc3bXC;I(~oE`zg_Fyk2*QT3y+O%!`Hki_Y$iN9Qtg#lzZH7UYxr5*Eov zgF4OgCvGFvp}j1ok4$t;6Ra6~4NEMmT_TGqnq~Z`AMToL74ECRgs&m$qEg(-^rPR1 zQ8j|1MjfD3kKRoGr$K(HPhjJ@0+;s&aBo@mr`OmLf$E%`O3dsvvfdhfUCs2pYn}S9 zH2Z%wJzDMIV{{aEhC<ttSP9TJrsR4+pVn~@^e)?o&*uBg%ViPv+FBX8VI&9#R&oWQ z&%$Q!b^;4=+|DU=F-)oG<M!#u6s%XjElFqju}+u0`q^f?>`26m@m?Iwk?!gl`r^G3 z69UcrWESNLT{^yLBTu;zTxeEvQW14_a>4F3B(5(nNk%o17}&>_?<=@@-Qdy7<83T% z!V@+xJ82CoIV{JrahWJ4`<E$dpIbV#@9_P?k9AhA+mM+tlRzQl=4OflW3E+44$zaU zx-){)J|S;=#OIhBzme`I!Y7}{hyzu|c{yjT5I9Mj_IrB#XcQTzd8s(>eDI>k$?vU( zGU?c!-nU5a9So>1Nd0U7@2ork%)ZVFpz4a_L;3>paqvqG$Q$t!jP73QaAvv!sWFa= znvmfBK3sF8MqgkiY_jlUjm?z5W{dMAAHgr`C~)f-VFCWsH~oDq!&AU=dm})EB;*;q zu1k#Yj#HHrolo!$Yi*)W;-<*ZNDa>?t#FMxXM5StB1)g5pqjso^GL}bRdY#f@lM_X zON>J|>~eTQoAD2(npqA&tmbQS)1?>mHL;j~VKc4%!(#+kL;D>LB-9PNQT&k<L{jil zCl(RwnYbwkMe5@XzIyQs3<_jf!4_(uzk>MFemMV3c{x17?LO-BjN`?N7x$!pol1G2 zsmsB(zUh0_fj?}zqsC2*zSxN%!ra_^QSc<DwX(AExAg##UpV$)=CiSkmNqrD(DfX= zRRnBLlo%*kfR_(Pwg;iOfjP(?BaR0U&X>bT5mHi8D3bNzT2oV#pr9b~i{MAaUl~I# zFb*nVzga#ZLSG+EzKu?xn6U@NI&Q@ia7&_-X+MNh1Pmb5)^Vxba$12qv1@q(e=#}P z0pDFPrOl@|GmQX-Rg<&&V@K8RE>!X>FDZ#r_G4#eejIEMnTh}9JDsd)<tcx8T-n^& zr@-J4vCF31+}zB}cYjX)ZyHkF{nwk@ig<DX@jS$}I))k=QeOfz{f9F`*#G)=V`QpV z5a1eVX=y7fD`R70dwcf(<Kh^=)}VCAeAZBxC%*zL|E=eLx=pKl6A}QMrG`LSV6ZbL z4GxDLEDHVt8vqBA=wAmioBQb{1Q1DHUS73B<m&1wKrsL?{2$k6Z@^iYnSr#}`JT@I zaoJPYW#)SrI~yAtGxOlc2*a<~O6q>+cK!@6DTN+y&(D@0j1K)ZLu5N2HX3e|uFwhI zv2KV8Du$I87sp;BOG{b*zkX!QwgQ|E`QQ*%N$1eDj+2c*k1OZt6P2XvvKm#G@C7WI z2`Jdj=e-#VE8b_ct8#$qXmDyqq?y-1?L)daODoH!CIw42>R#FHIcg+I07CN*Yd(ZO z{F8+|3-ann!Ox&ncn$$(v3WqQ>>jdEE0kzCY6H%D_cZ8iv_A9vJmdUFm|ZmOy6bug zD_d_Si%`qP8Qrf-y<<%JC$YzDIZj+MSO6$hI%7Th*x7Ej=*`sK+VfV+khLAOPE8T3 zy(E+SbHe`u9sZR#f69qvy%um#xsqG$xwTqd7jPQ%-YR;|a-Wqo3{^w^UqaB>?+ApY zN2F`oYN=9v!i||dC(U-vGO-#UD(?)fw`ur#_cVi-U#jAq;d*V<Pesn`b+QB4No}w} z8*)FPTBpNqM9{t1%8bSKW0G~t4qTw@kZuR-VR3QN_$qmd0K4=oDP7T0QM{Yxe%PRx z{Z*sc9EFSGLeyk`R?5!syykdC{1?}GaON-w9-e%<&oBQo9DS*AaghZi6MG<V-}9qB z8W@*Xd!FnwS~I{)G&I4I*cQ@u`kh7Y**`3J;Q#j`N)HiU&f~h=R^1@zvMU{euP^Tu zQ6JBNn2Y#r_Nr$qC=}f2bX&Aggz}9NIdy_7`?AWbk|(-xNF^AYZ_P4^b|ILl|4@Lq z&+h5_()_U3-$}H_(h6wplEX-*D-+n`i?+fBk-srU$&b-=FWQ3C_Hla5AmEDFf!)b? z*wQwy7%Eo)BWQoh1lRVGx&?SuPEJmAiH@gRs>ZTea{op7O1!_sX2@|hzZuFG?>C<~ zq94Bz=2^U6P_ev+gy%hsCz<!};<0_6bK-h7&4Q#{po^_De!rP6EP1rmBL12M#4uf7 zbu{=wO*{5;qIJ>a$c3BaLUC!?7`y4TlhyhC)ac2*gS@Tb6obi0S8Hc<jUg)XG6y)j zfq{X6j*gDNM$~Pe(%SjW;&Int0`%vP<qG;=Wib%<PYaPfXP7t&16#B1wia156;n*E zIcOU--|Ctx%g0v-S-;P>nB)oB`9fBTV_{OrOw9XoZE=8^88t^D|GvUf(cHD)JkD*d zU&NNMuTS|s?w3s5u81ckE!MIVdRD_AJs17KZ+2p8grs4~>2vD@Iz+IX?AlYaEp1M8 zu;vN83AR)RwX_<GlT|ZB2#Gf4JAbTv0Hd6}uJ<9BUQeT-q~r-g)!3-TQts?i0r3^< ze+_@2;NQ~+JQ4<~Zy<THROqLBW9f?b2JPK3tSr6S^}UGn_0%T6_CpNcHUx^Q8TL(8 z$fUx|r6^^lm6y-j@_dbmM9=j*y_lJG%S{m-^B=X<!n9884rNJ(MB$2BT%(W%!Xeae zJa498_UYU<*gp}SG`H_t^phG#=Ap@CG?XlzLk<0hJ#O~pya&~v96%Zk>fwHg`L3mg zRA)mm4r)M;#rozb7@tU4Vj8{{yL`*7V)HsXPBqC8jgNm@nNDe^zqHgAj<KaG--4Sb zlMPH~zr?{iMyLrgdw%jhFw@ajiHN)0McSsDE{dJNan-dc?#YzAQE=yx9f9#J_Jz@F zf-XsVA6BKpM)i?L8%g2y3ry(Vaw<vuJwNa7qGUO+lhMH^B9Kj@mFTf9y`%zkGbW`( zKG=_hob<+gROjTTM&e;ZdF<slUnH~gXRU1tE!Cx>A*rz*IlUlaQnlkU8J=g4EgS7b z%L-p_h3Ogefs8)KxH?ZC*<e|2cxj19{(}gVy8g81Bj?qVpauC0>%<ZgLUGU|yX#9x za^&Qw7Vo2w{A%vwd4BIJWWBSGX7$VKMW?aWFIouNowCYyll{jS9U7KY<%w57dBSee zRiA}73c`IIpebve0pnXrCiWeO*yZ`@4^uKcFH3}py}b0MK%LZQ-3M+u!~dCxE@UUy zQ0IAlA$d_ysdgdE1a)+Ln+mi4oxI5!fyJBf*->)0LsF8r)}RD2vG|;^(mKZ^btw$5 zdg|`hL$po~cS)&h5BERdZ-wV?lO29jGd`Plp<8sr<F-cd`)OT9KCFIe9$R>4SHRah z-}jRj#eDYDCu0%!Lg-NoW|<FdRCwa7>tzsBJ~i)Z^VyWWd#S(*%e<vAMR&Z^9nYe= z^S9=hm2oG*WYgVSEX)b`a>K&qZh~r&5d1_}3v(kb=k(({EO<^BAF=ajhmHgkbjrSh zql2>9QW&V|;<gLNqzSmdRu^vn7=0o-eEl0{jr2!KnmBJ$Kp-y=j7sQS7PJZo&}z7Z zn0ls++sY7r27s&AWk>AV)aDDL*?b-C{GF(AMx4o7+XNeX*EcP5FHkkb@4$M<Fvy30 z#M9~@MZ18ci;$El#<)-2CfGftCvHeAp@K<fB$%J6Ouy3nmQuK6hRzl<ozTbS9uMO& zPK8ZB9De(yNqyLA!*iaeO~1#xxMP2G_|82#+K5fl-|w}FbAy8or-*QKmWijBx>Cjd zSbW0w<?2FK3pb0YL$2z@$p#FKc19_1c!Ro4A3oJp4{6yC8p;*e=llzb)DQ~>{0vd! z!7X^JEM`yi>i&<$&m1<@_prh%ExsF&UGulGq0*r)j)%-~=sCU{+wTzz=&a3{g*(+R zqHP~#N}vh|xXap)I)!EynR!bFejD?mtC*@Sx_SDXMY&F9-wdgPc{f}UfomSxG8ko; zk5bfn^&(ZXh4dFdM)nVMlj`d&e{aYRR`VgYdlrsaoc;P$MN4aD6TnAu@*LeTJS?oL z>{dQZtCQtfkvMO`y-4(u_xE(N`zFifN;J=mYGA&*DQS`c0k;(Zeu*at%1l+f&m)|$ z4#@ycu?XJix5+o5RFqOnbcT+Uk?I$HaoW1u$CvW?`>=WM!Z*-vLZ$%X9-bD5eq*SZ zsi{t|Q}<>2aX&kwSDp1NaM-kL>^}jF&MzK%{`4%HE)%;c;nsR&qapEQ<;Z@WjTD{x zvfwV62$~>5{O&yFoS=c}xS3YTYsh_9{5mpJ)FHx2vLqV!apKsr7k(?fDQtZK1;1zG ze2$BE%s&KLczL7q4OBAMgHz*wR+l#zuXWc%-^xmP&w{of!Mm{?22MtlG8socd&w8K zC>L?Rknj0|S-0cbt@+^UcsHFTs^Ow{exBr3e>xHWvGo4|Fg<exL9{}ARP&&Q`w{_L zO%?%%+fRYna7vb_-^Y?)tmc43r#Uk^y~GqOrNoO1w%oseIoAi$6T;|Vl$)5R>hl*H zij#6r!>gSQCSIm)z;PQ=A3m~sVl+R=YT8x#q}R9jXw}>%f=sXO3HdqOkfrkoZ%Up` zk@YWNlj|Rp{2>bW5+eDKUall0&+Q#dN&8xIbo2{jQZ1W9xuM`U4HP7fTT^k^RWlqj zyvsc534UTdGR$Mpkb>>fEa_GaBRS#jVo43p_F&Le(&iwl%{zg!u@2#(b?Oajihn^7 zX1^l%?%&a#8^=xJe(DPBC0a^GJ2n0BuzJ;3yFbc)R`9_JFktaDReGM??COP}+AD_F z=0j2yyLNTau*3>pQR4Y$jNzoJkyB*^pspozfHb>7L|PRu{zr~GSNSd)$~mH4y`6}> zjT<Le{_vk3K*s#gI{hy}AP_S%^YiD=yG3r@z6}IxX*FII##*#*w)v|}btikoq&}&i zdz)}{iI{g_(s&@_>4V>P`zy4gyh*ccDuFX5l0l_5dgRu;hk^xt9$7x`x4cr0Atj)Y zTe{V)CFUR5^#8ab)wggG3A*x@TH1sj>MrNZ+|M^6bVLOw6uGm{`}L6Gq_bzU0Pv7f z2?)RF=;#1`(wjGL04%1eswyrnZf}2Zd4jB|sX?R(#${yqoo<c2d-t1s$kpKB;PCJ; zn_j)`Vk0LVopCr>cTdm$atDZssUR!si}v)rF~a%j0dyHx7uasREQ@9Rl3XdG?NNBw zto-^z%6v3vs=MK+VXkQ&%()pT{u1|u(5%-c9LAy=evqa0A^&hjex8K5`xeGlRmTn3 zxo_J{#r^9J20nyfE$s&1T_V(5g2}I~2~&WCmqY*^<hN492+TX{IYTj`b?&Uo%ljKu zKvv%z*iP|e?K5zI2R8Qc@v*bBb2YH4>S``-?g^md9Hrpuj~@=(DzNjtIVxc{+vRrO znQ{Z~k++BpQHepjg?cQQmZoO%pdneH7MoYq(a)hGrOT-y83*c`v4;sz%MD%)680g5 z91He3O_Fq}wl9hdUmZjiHfoec8h1#u-B%~`E#zIRSkb{j=5qs}RBXLpJR^zVuBn5= zB?m?Cw><;0gsvTwR!gdj8Z%#KXD6Sr;wmbhMMf5skVD`$URRbw0rz*<uY3FK4jq($ zZa{x5402Z+FA-pc%eEQ~4UL0?0|!TibT|o{cIDfH#U`N6k5bgDR(j3H%4!=(vvhWL zX6NLXnwrj}j?CBD1R0EGi0Y}UPbk5~rMzEV#r?fi`8!fk?zvvK^6sNGFDst$*pE0A zTU$<zj$~rVORASdm0MW~fX80$C`?eb*py!|eBKWti28~6GY#t^Gyeh&b#ptfw_5<0 z=`!p+vBm<V$!5A#&~5LNiq|zI=NS91{+Ry#``+I|+LX~inRrcWR(VyGcszoQt(gxe z^2OJ>GhE&?+&o@aY8^%QA7%ST=Vm}y5Q4#m(|#CzE!?yG$a$#0U*IiqQBe^R0k0@8 zw=Y1@W{cAPg3ufBqT-wReMwQs{>1K+NMO7yn`zYP2|~R<QICqK_U&|G798U+ohCSu zuZ*$Y>Kh_aW@lw9DK8T?(D_-hHiB>8@8s?D><=wx_nIF7%}h@xCMA*T2B{<$7Z>;T z_PSj?d^&&o7b6$A`~79k!tQb$wXPw0H!8n6<?1wISj_hdb+ubD#ml?BT_EOhQUu9p z40@jgZ&_>ON4v4Il{MFwSJ(5gR-iM?zKsx03-*ANQ+SG+o9COvigUh}+etHZ`sjC* z>30Mx<=!lTUjK{Y@2n63(cK?UNIc<2YtvBIDc7?(B=m`ClA+f&kiM&e{ybQh43UYZ z7JU7^s;@VKEZytW(q->zv9oh<em-_51&Pmx|3K^wdXDoYuEN1<^qjQgO+8mlFo`Qj z{>U;!WdGJLMh>6@*B?KZ9FLN4G}Upnb2ac)^zHJ9Uan|d#qQN^IQT~6vz4U`y0+b$ zb&4xcx^cZY#I&DHYibz~lM$-x=;;|6h_1P;u@PK~E~C2c-qcLhPd_6u&(p+ZVP?!# z-F{}VXVZROo9#s+sOc%T3CC%HOX*c}L1fFyNZ-T2)GY?1A1LvAMfBCg<NmdIv=3IF zc5w>L><2Ahc~jmnmKRmm*B95jV!Jq5=}4Ka_W|XnKc@9?TaA*~4ea-qL89C>+4=dc z%@$C@eX3OEYd@}K-kTb^xcR-o_<K{iVW)>L!G(g!uU}|Jf56Q2M{O!wPwj<`o+Ikv zQUMvPX7rn8$>Dq%OCDl?<Af8kxx34f{=llOa-1DIB^6>-B`SISi?RdZzwn2BTZ`o! zQEjFYR~Lc7VJRs9`FG}<bE$+waB2LQcWuv`PUy0XLFkJvpsX2v{*i9k_vekevglNc z`;VMH<#?@`cuh^37sc(~rr$J;yxeIqrQGH=Y@KOEm5etv$;T5PR2#z2<H=>0C+21C z<)sVJc1k_Af}tqZi>s?+C><38CZK}fDBHTOY2d_z-~w5%{;ub3T%@#o=N#__l<dFR zEJT?DZFxxTdOf?=HO-%>H3J-=_A!34!C~33%}ey>;)#*p*%YD!#pSY<qzpP4&Py^J zeB!+xBU=qU3GB{G&=iK+97L2g9!~^O^@H@*y(0^Fm{<T8^61WSe6Lry9eVEd=J^>y zA?=4<5iIfA@y4^dEPQ~{=e>1StbhHa)lhV28hv#qC>0jrHaGSf_i}8TXmgJC{Z#)= z4clcc%`f}>1Aib+^Ks1A_#&NN9bHpgR9c+EvXwnP{%)$|K0ftgfilgTYS$l2ZCVwE zoiuRRk+h#v=*Py~>OqXgH!5QW-=*XwRn$pPJ?}=Nw%&((>0ELFc?Y$(FChV@lgY+= zY_7$zuzE|<o-bZcP!o;j=Bp^k8PsZ0i2^a5&2B7HaP|>n=cuxoYPJz|Pf$-)(gK7j zowuYeFHUFpHAi>HDQ4wm&h__0yXa9Xv1Fqj;@ZmicrDxICKfh&)0^JN_g}u?kZ}0j zMDlw9n{JsNzXJ_CHf#`#(O12kJLp9ZAza8rj-Q?(gx-i#pl0sgaLc;N>dniQhikG} z1;O|xrpYywm(R$rAZR0c!Pnw^5vUn8jP3Tyr#1McswGvpAol!4d#^#;8;otOJ|R}F znS{+rN2D-Ji+lWk>G^5Q6$V+!;kG8VFX1REWiPQd7~NbK6SDkj;QozwtE%sy^<=dC z9p`y8sga25m4cPI<{R^=_Qf4gPyNHRs;-#hxhk}dx_FB}46I0>EGozta7CV_zzE-8 zg%7bNKWE9)N)y9RH<ZG|U#nvL#EPydOc9+V31_kR3hw2c08tQcr=$+QG3COXpCc5` z?@6}H6lF5(EBqQ<e2{J6lr{<QJ)mPB^K*Q&3t24BQqt(JB<MBly<KhGfrnWsfHQh} zEnz<2c0eIPvPx;si%OY`3Pp@`FW1U@nWm@Cy-de@cHyqQl8&F&sGBa=gLR0lO5WV` z5TSM2Nihom{qi-;&eJf%3!PoD1`5Nl#B}hPZL$fvhU>n(Bm+g7*V?ytrtL8Mf=fg_ zaNPg?lF8^@284J4O}AuwMabSp0QG;-mUf;{R_>cUN0hIh(td8^RqOcRYS>`xV6mFV zrhn`>YV|SVg}TLXO1i6<?CdjE=?!Aef?^tj1?M&VEWAWS)ER<wox7pCIQ*zI;)jg| zW3lYBGS)aU5f&hW)jz}qf<`_T9UT7j!A9jx&vwg8jE)3k62yW8*{oaHC&YKo<@(q6 zgIH`#TmhIZn5rYmh?7o7#{;zDtw|VIC(Q}*V;dRx8uRN${fBY=VmNa{1s9*NVRR@3 zC2I|c)>Nhm!U?GwR=&pM=nLZvHLZqi#Z4gsr<ZxHv}Q<U4JOe#kQ^U&Zc{XOjUYPM z$Eal(c1|2qFjky(iPm8UG2FFY3N%dMn-D15Y2u6o63GYi3M}Q!@H|Bsx7w%RP`^z^ zW(#S#+rv$z>wSebaR`e#z2wffyF>@`yd&Hp{~|*G50R4Loi`hx(F=7n_fU4=vk<hR z4gU0c0@!h7IH|MR*?2Ba^K2qNxbH^y;COawO%uOw2-0^2(c6F~t72G{-`2q__z*B~ zd3X1ZX=%BfJiSOrxzWcE6h3ely|ulNHv*P;hHI*+mLYC_tIXH#6oL17ujWNx&TuT& zeysm==<(cJj$d#9Fr}z3N7lfGM3B_VcezdG2}_?ic7O*rg}SCHgY(i#=96{EKI&g9 zYIMc1=w|2|dQZ4#8DLfdlM#5pE;EGW^1g;N*|629qae`d6Vt^2qO~s26y>+DM%T0& zkDLN|sO#(_#69h-O!H4INfZASChwLGuDRoo^o8C5!?>E|WcAZ~9mG|3JeE8KOVK>~ zJQ>@<nC|Jg7bS0a)1^aP0~DON6z?~*h|mDH-U|xppl}5fuaI2obo8H8FKxM?I%3p= zpwjxNdt(tJSm{}oet<Y7CEtw8Fp!qO*lU<e8+?}WvNC^hJ0JaF>-0xhSd&_>LarB1 zDtwo(cic&U(s(k1d(kdl2|z=U@_;u9b}?TQ52s!wR~s0#<sHFC-faIC@nrA3BzM<c zSI_#n)>rV}u8^-J&VP|s|38jhr@_bF5|NoKgM~1qz{^HIy*YHS)XYpj_)o9v@AS~$ z35Z4<XWs;*&_|dX!Cy!!@P8!eKY@q^34%LgWL0w@t!Z$EU`DOE-rn8SRl)}95yaq7 z$tcL_?QVI1Y|SWmcPF(@jF8;5IlJ}L^hM}>rA;m38J7B)q)DQ**CfY+u?gm^G%XX8 zx>f2S=Y75Qu~Y_X&htkS28ub>tEMlou9Y`6iM0|Zi85X*&HEl6l4Xs$-gC9L|2ky` z7j?7L>TF;0v<}&$Bqz7VsljL5|HevfjXGevu6AbG-BbCJ?`7bmYcY5}+o)I-Dyuf3 zL`<4THCrz%$a@k|?MwMaKBs(hv5D}7F#iwH40Y9YE@XC9`-T4Cxi9HxPx*x?WHf1J zTCkp6@r(hf=9c@6W**wy+**&t5>%rJSRyGoR7UNIdC<Og)=uvgbh{<at-rkejDn9L zKSS6&L`^R``}ywSm&l|06XDfE`zi)X^6IAhmtEU^>ipCqNq&xc7V|M(cbf;jbh025 zcy@~ki3Yl~R8oqnl1hUaraIpE)B}RGN3V3<yx!lW*5wsttxqn|-~VYZH^Nc+(e*U= zxVQSWtL2>fwGyIqT$7*dAVdgmTXr%R>-JAET`lSVund{7X&-rr^4<I}X3FTHbk(K) zb|+0boIgXvaaGFdDzUQ1kHG1EtbBs5WVTX)yl}0U$oHQNoJDuH6T<d+A@a(0SU(>h z&pGe_eABIp$3@HgQJ!BnVy!WGIwuA)^+I+AABsjC{)l@)(RsVqTe@I9owc7G@mhOr zzk|<h`Tcleaqrdq;Bhr7Hf+8Z3|rDDVG(w5oM=wK@#lv>A1rp8C9wKBUTRZZR3zZe z?yGF_xs#Y1NcTXetDAm*Gk_eFe`wy4$HO;60;YTrd6Igw@PnI)H6mPT(dpd9<dgE} zlr7O~d6$IxO$RYHAp>6nO=%rJr-dfV@`;4JT>H?|^cEqsC3>4VWJ;<fxD2_9x*Yb^ zyG?p6hcww7pJO5XX`Vo`Fb`H78R1QkX4n95nqqT4iRqhEios%>=shf>$CQs+UDU6N z{K-XLJhFD&xtMnKqen{bi+Z<q_Fg^7Dy%nAUR*4K21k>Net|yiO&pkju!X((7Gu2Y zX>DayS|Q@+<E{Pmbh~6VYG2G?=6NaMm5i&jm7%J%Vn6~yDup7&I&9P)KQ#0Kyqb^q zh1qE0r;o(<cSaLV_Q+ionWCA>49<5?zvilkge?qOvWpnD&$y4xr;B}2m3_*1Eo&Po z{7Gxda&=Ezx2kuiGpEY1B$1tRw?UYp<h1km>CGwRv!3#Y5A|y7+^foKzr0m8{yZYm z#O<|FsS_j29X+c&`B%-9l=s@7;kz0(BJoG*1l||OeS!=q_*$lqdT5}Z#BF3?gyZ@1 z3cwk(D=vBd;yE*0MY;VruT3+NI=ZQ8snur>?<XS5&vY}`R<v4}K15wxSJkjUL-GpU z)LJ*1Cy_o>T%5X-syCXuKTA|cYsS(rQr6x8s95c5uJO^kVj>KFXX83GH>+w5R93>{ zY1}U$%Fp)Supn4#tKO~djNgPVO@P^O4V$=s%+4KGhYem`g~fK7)JD@Ita6l+6573? z>#d)=`4)zKD;(LwhHNO(1qo9p^eb58MbjQNy7WHmm<`awmq)HTo`-g~G07=!ENH*7 zvfEgB*6|T{*X@99EP-NBM${Urv~du&=p<k#KORMu#p0feG^?-wM1OO#)Yudb_6#Z$ zPJynn_9nKr`d6pOr6SbTeZS4^>#4chFS_!%nl2vrUUP@JD&jWpP27L{6mrRwo7OPy zII}sOu}nfnL_y&FU0c<2V8wM|mA<dyjWVK3GC%R2f#-1+E=xX!%No3ezKF9kpUe<; zVfQ--JG=k%Cq!eDW|4%lk<MZ_!^9wYtj5&1=Xl3CcDf8tTflcLwn=_fZ8RfRW_~j` zF?g^#do^}kj(1z}Z)CVt_@B6+Esivhx$mY%d&&kPQI#L<7Q#zY`>h8-!oaCkU4Z_| z7ObZhe`<%7^DM?U8!PVSOWsS>e;*vYv$&UD!XJEjeTT_jo@FS;dRAp#B__c@Ma#@4 z9fvvGT}ByRHSd0N#cB}B4eMOaoXDe@qg(-b8K1sCVVWOH*OiqtwL>?3`*O76Cx5Hq z8PF$?X{s`-v}$#@sdHXJZ&zPiy`A5!UaN39zx$R!sA`vv!KXNHvme`?$E8pm!6Ln= z^o=v8T-XvR|BP_AyQIYX(Q;#J@)Ytx1dY;=P(t#8ieK|tH1uwBua`k@sGX`G{if8u z7<8C<Y+l7B`|#B}*u{CF!JOvEnWEqu@5d%gS9^l7->w2e6Z4zrBXIAp`fPHXrqp{O zuGViU^jEOSE%<(hxm}#E3D>Zs?uH|nf|$B{S?3HK>nH8|7FB$zFWxN|A4anHbj6|| zLAJv6^b5ngAOGG!$5j7Jzy-Br@&McJedpEg(6#TgRi?7h)S^BYj@H&YKt3=wF7D_4 zLWB3u1K=;yvuCV^t=gti{Ht(^RPquQ?C>FuVLf|$`{EMz7tcqNHXmz&Cuex;K7+hH zdMHKWyxJRSnV9&Qm^vC;bDN8*TpM~V0(^8KQb|cf>-4FuX=$tDVe>*LpZ5CdR-TH= z+D4#erZF?KwQ4NUk}4m?U91{ry}oHq8eeb_hE04^qm8US9&8@3_V*R;yh(~kril0O za0kB;_q3B#FEf;iswW$>>s#{DxV+n=iCb5;KS$1$&Ff@nEbR$IO6eS$QL9{4zP33{ zt<5ia#~@xFmI^NU<&9u&s!c44=}MVWV;dEm8}d!!1Y#|IKE9bLP4f)lcDiop`CuNw zSl<bExJ}8<ZfdGEb6DUx0TRT|&oiYJPjcKl%<`OrgPol?$Bbu?(A1C7NZp^8O_8lE zFKM$r{bwucm^sULx42l|8T;7zqI528wfHz?el!1gF#D#39?V82$YKc{9OY)X6d+ZT z!W%Bx;LZk)ni?4y;ulcMiq?!zh>!1&t}Plncf=am02-7wu)&F`iJI6YwX|~*l*)n= z&SY$~b@iuazdlO~=N8<i=*k~GJ2NEoWaVJ1sIJp_6q8e%sqz{QH&RnGq}NxJz`?nj zOC_4(dv2?ww0W7fmW(XH8FH}($}WAsF5UIKG*38-1P<8bJb>%rlqHa+%;;JMd=(Gu zdcppJgSq@sJ;{2>aEg7oW$}<us*@PEC==30X*6^~5D7)_YmpE${Rqc8MZ4;L55B#i zOo~jHn&zLbmsx)`0|e9US+aF5jHGo4s_jK@_w<-cgx49;5f}V~N2JwRLkBnGG|RGj zhSb#>?DPeM-Hc?!ouE*tulZ7xX3Gr6$wIYx#`5Typ7IQqWOn(>-B%{VwU?=Q>4K_3 zueTwq?)IT%`|ev8m)OE1eGbJUP+C#v&EgBmF+KN<XY7a3a}?0RLV|D7v-9I>3-c!9 zDC9ICGWS2Fdbelpy>^z!9R}gBaXd6C^9^tCDgVmq8tIl+`gh@#+m}BxyaOO%ho{fR z=(5C2?@n4i-WS9)6=olPPh=?JH~fInS65H*due-AENH^I!K=p)FK4L;fKl`FTP*Z` z<Sl6v5iRiY8r2~tP0`m~Y}QjXAN#^4CLv~mLZ<AEtEYChZI0TFm<AU>zNVD*Devy= zx<Hg{mx(yLn4b3c^+6Jnw0!*9*(S~ufUcN()e(v|t$HP#uIHsa6xoTF7vbop#^MW= z&hgKYRZefnu5;QT98b;`4rxLnDfx|CwJuf_tvn@YY$N*#7D-}q*q*v%I_^z;<(fdU z<ITsp*YX}p2PnC3u8&?6>I^mX2Hm~KzM;t92jaVU^~N}1B(`GHcCJXVq~J1GYEMj~ zpk(~9;fMsTy4tEaZ(7YuNB7Z~TZUbwrv_!b3K2jA-@0VQ7V|0d=JIX=*>=nHJ>@6d zD@bGd;Am=oyCwg#zMpBM<?Qlv%}*@@h%il?`WxFL1Y##ay=h#~&DFDAt-I3oG6Mo& z$L3}!g;u@S`eR<*+G|5IJQ_Up!IK|8Z4we})!5Dz&*AXx2^qyEwqL(3M6S*i4%W_P zyl+{>FPMsFayUzGusn6>f<57L-utme8Z^56(XE_!f3v@-WZ|hZ?bFj0wl7PoF-obT zAV*|VSDEZQdHdRA#z+izB11VoE}r4ETP{lu_y@~CMdhXbWIdn6VQGT6v2g6JOUf|; zr%=?h+G$6jij`8&5_hwL%@gvBk=d5Ky5K4a+@x^c2>rSS+6obRQzNtf?kYkU!Dvt6 zSVj$F`Fs^8Z(05EAz#PG2ORLqN^|ID;5`Qg(Wylhb+-#giLcpMg!wl|AqB|XB5ueP zlR4G!R1t83#XW<$75Y#*6W>;gQJs!8+nBN#iHK`R*4N`M*#@~F_6$y8H*c_UdwFg9 zRsZ?Buej~MhlU!5lZ?b<%Qz&NSWjkDh?3GY*{-C8W@Nw=&eFCTge>H(6?cL)aoS{} zDbZaV^nD%?Mo)Nz`Sulz=eKWT5vcn<1z(nG6VMV>0dE=F*?(*5ezGim@@Ri)0;>7_ zO0vL(ZL0Y=ZPG3j2id(h^vV`#VW7UWeS;NKL*k$$=v`f0Uv=&ycQJVJ08?1o<_D$E z>H3+sn^LS-alrOI=O!)+j<D`^B0doO_=MjMJuL|d+b4)_m1fe|J3Q~cTVryb&jcSR zm5Y9;Pu$_AuFJ`8kX~Mzb+9%1xl#Z~U>F$sj!w@egd=ej`CWH93wei7{_GdXL`H+l zF~Wte#J7iMr}{j0GA?Q|ei>B7a({*5&%6Ir=mY=P;RJ~izP;FmW6$<h;0@9qN(NkA zL&B_lPldp5*AjDm3s{_4no<mZ<Nc;Tr)?1H`qCBpx_{^6*RLP6EBC(-tVz4pMOuYS zR~U+!jCUs3fXl-5Xqp(OVf9Hri^+b!A4Q_6wR1dp>{gn}x*k{CR#;VC_526W0*VeT zP8U-)CneK!b-#3>6(R|KqjPf<-}s6SF3r+)Yuaw1`OHH)Xp=~d`#W0D@$xVfM=S7N zE!fl4cCUTCHci4nJx8ffrnCHQ1u@Iay}$>l+0%V@FW9wT+O%p(mB2<hIA+NN&5gBH z6nwzF?SY4fm)r#p;R0IyOk$q9RVN#~vU>E+5o-j3#XHQ(d3MLqy2Rf%NL%>0_}sn~ zyMB>REM0ukvg-nN^))ydn2Z#c;3c`l?yD2yv$iY6q%kc0u6}b)!(Ld+%O|60VKsk6 z44p2I6iy2=1uJS8CB%@>JZc;4s0-c=BrlJ8cz&+aL}$TNVSKf6@qMF1NxSyxFz_Kk z)$bCxHw705N&|?&{@EsOpMh*nLJI|htv36i;K{||Y-mDHOAdq;&!CQ>sIsUuO90b7 z{q0M*uU7e)gUzre3n^Qgpv73qdRlGREzYCOvLKP?<vxnOI+9m0BXlgmH|>_vA27|i z7lAosc~hQulOg!s_TQeZlaLTpIUg*3KRjz04_7L%*K2WGDSgr92d`nBg-xK@WD!YV znmFn8Li@r|ktR>qVP;H^UzN>#)Z|bf2fLT-X7Wz(eEw;Up33yG3gve5?7JrUqzljT zS?}i!ozvPxQxImQo=b!g1xdQIOu@vbFvD*uKs&_5&!49J!nKac?_u-m?~sz#iQeWF zab@Ln>EWObPYk)h;*B7&7I4^(O@Og3r>8*~*M>8`+4#2hDyDIIe#z!do!%32J=M2R zyv#U*T3jpWR0{a4rEIlbM`a8bi9&hkUV_0=8iyuXANuXc3Q8z~o|>U`E`H9P2D+w7 z_}_Gz%t&MHQ&AH>YTW$19T3DPqq}khM_wpobUf$b6DfA>{;=?*gQ-nG?|JQkt(S>e ztBR$iZD8rwb^nvP1n;#?EN?b#B5G3VHZi_ohi}JZ>ZH>588VnHU4JqJ6`UX7AK~DH zJ}{)9prE2^v350E46d_ca$_uyJWT-(m^gy^+|sgNB!vkS6dqrM+O4qoQFnM)eKhKx zj!ab>4<EI#*i+xjAo6T}+QBGns@$0pDuyLn&8>^y##=9Qu##)HM3{4)CddA~qCzyL zR>(wsax*|0LWq*Amtx#2vVG37=<aB<I6Rjcr%Y<>?37b}-XCL^+R7+%AednERu89s zd_1>gM4$;$gDIU_h)PG4vzBv+RXS;UXskzdX*P#V_xbmn@!scSKgH6aZV~LrD{Rkw z4xK@N4Eo*Am?a>PF<OVFLFhANY|^+!LhlBusNU5Sk-IfQ_l3oCC?ursqD;5t$0Yg| z<lgk(H>WcE8S`)?mC}u<B--Hyzlvlu#>cescAor9rk9CM{w}zUKm0o52UTmscaNB1 z5GkL=bUG;J5jh{UcqW+8dlWq6{QU@illYM02PYGsvjf=5*K=a~EcF(OQ4xE=x&B#! z4v==UVcCtMioi7#b2B`g&hh4Qb{<U|o~sjbo7j{N)wv{=Ra-?RMqZg3u2-cOl<+d! ziY<b!IWC=Mf2=V^z$f`;ghY<CE#wUhCaMB}8+0(f;KQgi`k?0g`SEc{aaA$yzUZIW z6DNq!1?*jBa@<u=I6+nuj2*#-_}1(eRsjETwWSa!TRy-pzf8nqS`X{r3~aqR4vs6L zxa||{jXG#C?OKsAkjy(64rVL4Vf47u2WJ;@SW`YN;gX+N1G7d&Mu0MA_-NF`p@!0a zYTdO1ek>;09uZL~&<(PqFEyJN_xl_MN;pcCL6jYX$eANTu&o|kH`AtY+}uv#;pxc} zn%WmN-}Sj&j!va3M^NeRcS%uDabKPN(8-I>8*BM@9fnBG?aND^%VUKa@YyVWlFr(^ zLQW0IdJG$-ro_`_{LF98--*qh{*6+WTgmo8Mm6orSFab}bst|Kt_ZS*PD-#F%2GL9 zH>wN!9~!9c#$;3sFH#BtQRnZyBTcvrXWOz3rG`Sbdx0BoI9~vc9=QS7N39ZbQT3i; z;-tn-gcL9dT!DC`6jdvh<w^zAs0P7~W)JVlQY)6Ea+~lm)l_v?3!o=}r(X$wcf<7I zWL0-&UPnYmBP-{XN_%+~*xl`<{t?D0N2@1&Sa_i{0>fH5*XB1$^rNXHX^&Zusn!AN zr#KK*I5z>ll9EarC(it^QyO^ad4dA>^dR|2W(H7D9dX5h(XBb0o3^fnrN<t&vND~{ z@W#nASvfnKsO<SLQ734@D4Ce`=^aGq6TSS=v>Iz~u$;ZP-FEq>CY+l*Ekf$$<m5^p zD}A}W7<IrTtZpi%a(iyms1|Tx7rW+dYlhrv%P-Y_TuYx<rP}x;nxS0he780e_kMi= z4*j>}w6-k0)fvQWyl?Z?CqEQY#=u5u>mzYTgzlr}4&L10%KYv1qcR(gJwJ99h=ca- z0YwdW(6<H$ybCr*Z{1PBqbG98`$CU}!~~AErcX~?&0BJA5%SxLsHzyHQg?Vkd~El& zix($9?Wg9*gk-!P+K5X}b+O~lzL~d>T6hhWR9_ms9l8r)pLg0)c#~INU&YSk8i@(! zRo&&<JuXf?yMd~!Dqe+B84t-QJP1=>h8Nga6?1@^?ZcP%RJ$z7mXbYlHJ%LqEH$c} zbujLqrx)z2c6L_U8<o><7CCsUAy+iw%J5euxA*EF0V^DL@!XyV@_%^@=ZA;|dJ$yl zd1RDmVqDBO60*kJ;;MSpP54O(3(n6Uh7_9{WQ{L!zT37f7CT}nSNZLY`=cg8aCTF5 zt#x<Qf64~2Ui*6PRdq&KC&TPVAc#?3Lv=rt>s})kb)1MOlj12QX5mxQ?{W0e>+$*d z-9bQC^hS&2%eB1vaEb%C<W27|?wpsIdob&?i@K})c7_3k2?@unBW+1-qw37K{(^?D zrIE(>@gqZ3Af@2XoyW8WMpr%c*w2u3ZMMGCSk5*oL?pz<DCA|}<?FN$-~wYmQ)I}V z2(<C_^HL=(n1CRk?VJF7w#&1?mS|ryIgiOiO92-<QckRBq6k4+A*k-gJPJDw%XH+F zk%day4a`XzbDQMkJXM+|oyw(&!v9Gjsw@ytWXCJw{F2>vdlrcIHf>MI+&~TOfcEZf zN1Qmw@@4ntJK|QmDb{MSrU5>^tYJJeppfgx6pD71-PfTWOY-AG_`z58_r8C6X|;M0 z1Hx2&ro`ww);~4vDlTe&pCybxz0K^D>uQcvpBWB|4AX{IX8~FHtwdfH*-^Z?#F%lf z+_UDZoEH=`tW^8N&@I#(iY^8Xc+qR4A0Tc4k9{=HicztZH3FQmROyxSW9R$69j8zV z#m*2^ZDv%5rU|Hj&dR(3RJe`>mP(xFvZIov(seH@xF~h{B0`@s-G{wQZVL262Lv(x zemvW_*PGo;VqoVsm5lp-!dL6A!Sn2_r=-%QSjslT6^WNf|GgdVs`uQCim|Lmfk$zE zH2jMY`HOb_g_HmU%&=B2c33TUcW`f~^h}%^7n@3W5dxiE>Z(h)UfpCf+#n=&Z7$Eu z*O`eo(yJA9j#AEC&d<#bj?G>V*iBNtUP*E?73pp0UH-Jb&1t<?YHlhKoiQx0d4kvl z<G~3MU6}J4o9Z}+;_!Q3xWSuhU4JfW<iYF*LAuq@qM7DzD@Ve`(Sht(3na~=C0SYZ zZ-4IOMiPYAXMkGGHOG7FCiwp!V{aK2W&5>#tB9z8h)B1JAl)DgjI;;{(v5WIkP;)^ zpwc<g-ObQ7ba(gA9RmzA?_Br)y6@-S-sk=Beuwki<~Y|;Ywi1QZJX38kdh|r0N+&G zR`X8B<ptTV)Vrz=&RzJ;o9Tf-5^AX7w)z@hqUoGGxZ3^=ys0O%!@pp`2rjQzckZq) zCb569n>(K+^QxmccqnWZGYMC{?r-ojKmf*jA*ad5YvX4Zse(R#U^|3z{7(*r?5*|w z^<H<B{#SCbL+_;}SBG-`h~`7SWJ%8+FlJDj3j3R=7sNZ^irP?-JXN4F)Ah*O!&Z(^ zS+>t*s-?eg%r~n<2HkG$tGxVX0=mN9G1!avlxA*Qe9?9P8C;&AU2hgX7KL6^En%5& zFzyTrTwaLUQd6yE5Do1DpsE;9A33Tv-3QNr>VcBfg6tHlw_$!Uzf}ZEqw#?H2C5)# zm#o*t62YMrCDuq78_CS<CkY>^tI~WAT!~I1$&bZ<nX3*Y51x;xweMdU<Qtlf_2utU z&d3B%mvIz-#q5I9;DgK^|Bsfod|k<0UXhNN{6l=5ryDZpCj3v-X6%}Uwi~d+O<)FC zW=q`L2cKYm+5Q((V%jWu=7aLxpT>rjhU-G-&Cd>gD)Ase%SmT36)bth&$X+r6D@vH z7JeBwHnR=WBl=OC@mB~lHJ+ls;by)_jd2Ag(-{~KG%ytpFA+g|S$MP6UL+Kzhwl~l zt5l#=G;o3r39WiBO(b0A3TEd{xeV!H6lX<WspWLx0!}`YEjCS5<$StTHj#zkWvEZo zbs*oAmRjC4j=T;vS>s*4rlhgLO~EB--B{c|ntxjjvuWw8t4TYzUEF}o5ycUawz$Pa zbzH6^1zB(#n-_<Okty>c9%J>Pm(TSw4J>YdAIKx%43*7c*?c-@6k+FA)FICjZwGko z(ZA>{AIQdL+A`gPVpkj-6+r%_CI(J6ZIcju*A-~!ap}oO<5@)VhIKsl`{Eb62{lU# z0-`SWV`u-#!9rs)%>xb>4vwon3NfF2R{P2T*0QSlnh?{#XgKs3!WKM|Udfj$rC_W# z{rhQI+YJwl4Ns4HnxgC7dm*QxO3QPzAzFUx^WnivCoFVo9a?ETD5;8{wpSAHYx-t3 ziP25Et{XfotdT%W$?Lh6YPsB^JW#gs5_)H{r={a}_-`2`;Qrs#E#0_LK#mfm;*k~a zGn^aqiF3%%`H1Z~M1oZQ>7sifo!sx}4I~IU0v7dTa-P1Oy&OxrWN<m$g}Ct5Y~{Vc z9*KDR{B%X{*SATfw`pD5LEAlh$&K5$&!=ui=7KxSVBI~ErqiS|^B6MqFqplNd9Kdq z%CB54rFL`gOJEZvh}o&GG^vGCX$mMXwe#HdK$}$5xMSW{E6`(Ti?18@C!Q@ds@xQH z-c+BM-y0E>nS6CI(l~!xI8k5-n!$cjx|jsf*W>__vPG)#xhS|0Yo9~lFsU+~gfS&e z<0|lUD!S>rgsNm$L60AW|IG*`mU%IrW?FS!VMS9xchCD@8HW(-s-i0XCqufstycT# zg+1KO;^CNY-+@`xI^hwTgegw^SzkqehSbhspkyiNCNtOlBdxp(SDD2KYMn<g#D4cs z{!oDk<Yf!@IC!j*&DuQpP^5}cX3*UJpje6?r9vVZXfMw^O)L;{!<z<Z@vb`F`ITnb z@R6V2P({pp_bNZI$~>A%pnU?Qyx?hoKDkIm+|^rdNVA6vrKZh&-$lX|GC)YAy4{@K zl&00l#Q!7{d;ag-1Jx!(0S4wD0b+vSN{9PLe@Eg5v<mOs@fX;xV4}to31<`I@#@TS zr7bKfv$E4bFD~lpD1(@sCE5-uCP=Uk20v;u*%f@$NNEK!WSz;kSRvs7t6D6b(}&{t zwkIRG8<+xlEcHT*jkdee=6p<uyRK8F3Aha@TSbz83lCz}Gt(89oJBOGT&J<H74?<& zE|T#Y`x^Y6I)xBPz!8C^OCIH=8I=us_aKm*w}--BGGYqUBcBeh6S;F}sn6lhYx!<q zB`sx^j(Ky}NrO*@buHrzpDORd0c2_eXpawplfGhqJ;wApgBI-}b8)b%f9@B5$o8>J z)OT5^8uL`lA#*sfK|I4(?wSO`Vm-Pr5CR^yXD$8c!OAsjK8ujD{zJsGxyCklGGcoQ z30#7)X@lt2V!hnDhGrpTJhtt*5?Z9|X1p4c8o7s>H4eK0r$j!G<{#HdojFFL!s5+f zYMxX0jcEG<0pA{TeZQ^cWE?FZw%YONA`*uiSI*X^qcS47Q%qD&+*`bsdZ@3je=T*S zPgXdw{Jl+o{c4G&=Q(R6y2<n2PiwgftI3VjykKOE@!!*4Lfil6M-5MAp)8WCyrP+} z9-m=!SNpVZTw6yC@My{}tsS#L>rQIUX~w$Q3|zH!<C2u=vu{tNp9(xmAb`|6Nad@l zB9GqQRWTRtJwH?CKhWf|ZVx*#EphzxzcM`m8DP6Y3)cQwa%w)~^*=vHe<C(ZU>LCg zRr4x@rRe`k?dWN$e*XTccQ|_zlR@&%D%HEM`Z}Xp#`1Mwmb8X_cEEgV{=tXhzS~R6 z+INSTW+xbNURnR=aDov1trhJ~m!_biKngpBj~tWbV&?u}b{l4EreR={B|MBgTs?rz z_J5^h)X|HhnrSi3rdor0IXp<C&VccmV5wp~ez$`N)4g-ZzH|47zEf+GA>Afs8-=dh z-rf*8E|j#jR^D}SbUF$e4K7FL-s?oAbCig_=NX^EpGsmBD2vkCYMte9#gF0@GMOs; zMI9O(@YeQaRJF)G&l|vN2*8`}J-2&B^a=&~`&>ha;$q6TANu)*L%T6LkBrst*z`Y? ztz8B9!=GzgTPy-KX4K3MP7PjGTl}BgN^S;tT1{X&T~_gFM6;5lyYuHy)`WfHgprp* zN#N4eQ2*&0_LLSTR%eCSx9j##`HBa=DB@|?DKqi%zSCu%R7FPmZLi<{=}-~AdctvW zrC(#RrLBdGY|89!s_IKI%8N3n<#yPT){>0EMKx&Uv3%&aSn>{a`)PCCobm!rsuoY2 zHtRz7{h#6<v@)lS9ACjDkeo99@lcwOjnVgm-&8i1LyUK;w@f1t@HL)h3(CUxqER*j zYZFtA4oO?Bf}hNBQ+C=<n$Qkv1D9AFK)q21%<^MTF!}@A)4szyjUNcfqeu}a?QMuo z*q&V2_@Aqi#6}aTayRRM--(xwMOa=W3e@~8&gR>{&ysV44kEHg^W)_5*zoYBKM{nr z{_FLwfB$b{!^D7%<dzGIHh7+^69$MmjHNUr{hX65=|QiQB|Ccn31@yzV5eVcWxVLS zsjTM`vzE&yr#`?>toHhFq0+=xabcuQB%ye&@y6NPV`-OYfnS>K`O=R{GM?mp7onTv z%>GP&9j^edtGX?f7`-1>D)lpq4e6xZXHkj+9E!pf-YWb0mfc$XEpdvlBFFc(u*R2) zBT4C`iA3e1o1ZMdsb!T4mbim^#{)|!^M=!#-8+NSie{wPp3Wt!$ExY+s(CRPTCVoY zdgFX?`3&9o6aw$i5?AXawf{0ebh{d*@D10mE}hA$#7d>4^kB4I!B;;$eL|_X7`vVF z>+3X2k+7iYmCNG@nRW3<zN^36x>9Dyd4_ZL>OCs-jo4i@sd{bvDC;CA1A~6y+JV-& z|9X_%W#5+-Vp={R)2X}fa<Ye)f}@Mpm-Vo}_+y?|2`9m?89I_n&iEL1P5UxfNO18t zKbmewbdOnkc|G!ixx;cdb2aLo2u_>YE>YJMml!QCPe^oPncvxkEH}4iXJm4*cwcY# zdiaLIo`20M71Eo#nPf|87J=isq#cS3nJfH_J`Q?JUs0O*jmhe|T}iQQPFytOTp&A* zMb>)B`)IE#>n5)#pm{&wtw<BYtPWs238Ya5Ptn%1n=TNk?6S44J>g5@Z)GcuoKGz* zX8S!rG8i-5eGmsyKNS9>F{UjJYA$8H{48#bpJ%)f@v+D#degLa3U1T0%=R0k&R|t+ zSzH20*(Ak4Bbv0*i`;DF6^cp#O+y?eosDUpa$OHrhwvLKJ7r!;WWUKB(I@s4ycQ3- z!zdNXzHD0K5#i2s%G1N~Kio*a7{mLrUr1n2@O0^Ag+#t)QoFp)e`+E9xM^z*R-U?F zw7oA04{E&axmJo)wX1^53WiEV638~7JL2c;FOsP}_v8&-c6YG~*3v~mh~#RXK+8OW zcf~2YkY7%y4&B}PMWN0mtiUBjQq`I5>~uNZdTuj=gN$`)cYSIw*6Qy>+c86)`>X6! zj+n|1!f9TDMz`Z3wiUtIA&4Qi$SFP<qd)voiV^a_IQ#t?J=g8kF&CbWS1)XZO%aKO z{Kt~RSHvvFZZIl&>wMux9!^%fq1vVH5Fvfn+@sI#tK-wZzn@JO;AUkaJB_A?G?N@S zp?oR-Q`m6-F}xZKG)*@Dq<qm1m=gN8un|!8U+(chC>>9YW+mMCJzx2+o~Z34;|?Hb zC@<}&{Y)8A;fIZm<xF1HIg<w?5*!BiX==%0`lUWSVNM(-e-}3&@h_V|#;lDti1`7O z@2@y*2&9DTw(}}meO7n}rR;Hr?24U|Cq1E7FLEh{Owix556hQYhJZNWYzxJ!bPi<I z$ji0kyCbNgv826?RdFd3D?7)3iE--4R=Q?3No()%0D0xrm6<I$1v&rJ|BL@-SJn~| zrUho7@kI_jx#67=n2N*b1mJMp-u%CrwG{>N$7*Bo(UB)svGJRmn_Iect@XtiS;4n_ z8Dm>x7g<BG{hmdP;N|RWeSN&rOTQ7L7GTzg_ssY2{Yjm!4rIXIs=;q6yfISKNp?|~ zn%e5d7FTC_$I+U-_?Iuci`n`>43ituld{YxRyz+r3oo*!O!?-g)R~<8ydVez!|Ohy zm{wDZ-6GY<FSE3<D=c7Y9HkIf<kX$eoKe+N?xN&jETXg45x1B{I*L6b$A-J#O=_sd zg;MAJr7O#>7A$)Tt-GSVAIDCnuwrI@?sOK|xJ|rC5>G-(5~ooeKQ)<YU07r#Op5)F z3}F1orRl6hM*9tLoZFHpsz^0`)*;e+SPImPYUm{zmQquYAo`+IWT@b;?|l}=!aH5f zD=?!$Qd4Vcr~lQ_)I-4*1X3{lChLKbcxQdZ+wsf@0q9Gn`w&juO6@SjJK0SNiJn_n z5i+aWC~<{Oi(9KbFHt+l>6Niq4hpNx^ury}QA*WN*WkG5Z`@1%liK0cl3UwSK_a95 zj;6rfmDkn2R8Y@@+i9wBh%iNwWP=OOYJOZ*MO{n%kH)(+F)Dp;7X{07&L{C|a&~$< z67Xor;`wSjZxb^;pU9H?P||P8-&6{Al85kX@Z+SUOw~-MYS`FnejHAyt|-6N<t~9G zq@?I5sjI6hPtQM{x?JBS2`c;3fy)MAsct%8`uDii!SJ6j->1jiT~oxk8AJ~=Av!Mc z0D>xH)i;9tI^x~SGu(SkgRVaQ!dd=%Bh!?CYEo2A&TbdqEIUhYuNZ~hcxen4*RuJ= zo$p#jVGjRnvCR_h$KA5+qSsfmtmxvo4-vQKpo7*QPu^1wS)jj7XJff}CV^>q9n0pC zaCJ0t^!j`f4uk+axYe-?WBh@-2Xbm^Qy4pyDuM0(bjjA%h4J}SW<hBtLg{ny%JUJ+ z3TTzwm8qH4C6{kNz~c-8VT{Xm<6?J0THE-1d#GdU;6TXLh@zh|Oz|KxG9+T2D%p$O zs_OPZX7_TJi}`hM5F%L02JlNOr^u39@2?}q6lPsH+8Io+u+jV9>5i@c42vB7hPJ#Y zbc_mZv%jeu*vQif1YRWuaYzPkQYw%;Ng3{)sV0vVq{WHJhWW(_P0FJeMXLtcx&pr7 z<4*~{-XNad;d^deXwFUi;WA}j9Bnh&?|M4Y?@ZFY!s+-&*uAc949Lj9;9*5)<8%@n z?)`zCUBA(}U@rsXP<&RhdGK6czBiWzzL`4od4ZaDV#KrWqU~M=ms#L=xnv6Vn1of+ z0fqE1pILD{Sc1-cwjN9oP^@=K(}R7*kFNdwn)Z;~XBJc%{W~V-okK<5n>WD<Q~>u; zlMF5{F4qs?|JvVl@&AiCQU8j&u=`z%S(J`zGWhC3Rl(UXB{3tnbCOkFYU#8Sucm9) zax+tdV*ptN@^{cA>!02EIC;R=Ur?nzRAR9obqrC6ooa`AhhQXN7_*_we}7Ai{m#%Z zV=v=b$>iuKAb%Zc$y)MAj?MBxpaX^;3YJgi_Sy8y$<T2l)=1#z*HBfnysVfeqrbUH z+tXD|vWmRD{V~z-@=!(&WL+H@R+;)IIo0d(p=9{FAC;8ki<JD*Qhu%c6RqzF|BWf_ znEKDhqohBtPW(`3^HN;>eOg3Uux*T*5vPvgJ-~gwmiLUVl6hTeXu9U3w8&I`gv8%j zDF*JU`7To;(3i^vxuPHILKq1=7f%80hDPg;AB-KN`~Cc93flNDSXBzthrsL;)}EkT zthz13NU(Y+nNbONy5%KnI@;!}LN5653QSdwk%b2gRqr_S<-nt8S16#SSOm}LkSohr zuo2QPgwFp9YWV8EEW&Hzy`m^Bk;sf|ZbaReR0B)~;VezH(&9eB^(QXY6w|HP(1$u{ z11Yz)m2Jh|sn6DFV162MO`1s!decj7g%Kd-t%d2y6aW4>p4b4_kw1qP9mxLh@<pIE z!~~0qA3bLxM%}cKg6V7he_riJC-mq)=TG`cj9Ygo^Fzm1GF&<OoNrA(70EwpF`Tik z3~)}0&tdNt=BJBA;_sX1f8=8%qcpLO2T#ka)D<b_^92?^j+6eSHniI99E9^15KU63 znk51Y0ILf(?0vxS`wE9j<gMIU%~J7M?yJnu-xTM4q0NK9{qww29ZVA<SB&9H?SGT5 zoFD%?9{Eeis@r#88)B7Z4W*Ih&3sRy)YzR(11*X)a(V5wwUrG9$kj3d)*BB4OOntw z%)iQz<rh(Hf5o2^TsrZZM<$`P@QRJ97ZQ2UbE>`83)?`-VP-cJ(tKzlM>!^H_HYP- z*8TeLhL5o>JRT$bPvqdz<J_4`$o%7HLRU&Q%TD*a#VLa4{!#LzsD0JIU1N;I&w4W7 zc3pV*JfbJLJO<1^AQIkS4Fku^s^hK$i{9~}P+}8#1Lb4`1btzD=aK_mPVDSkz{CFw z1?ac)R8ZsG)x&4@5{=q!zZUg5+qh0g9W1qapB-h<`nWHoNN{+Z=6&6PEZC!}s;kZz zEX;!JMoAoRW5O=SdKbHdPcPK9=pNLl6_YEtttnO8mWUv$`u<WrX((ctA}xR43_aDV z3yRD*cwKqOz6OaToo<KT`znL(L4yAcn!@~ONtre+zq<XEU=eipuN+*OSxQ&$qoC!Q zg+{((2kXy!%E_bW?%AGQmBK-&tLOoJ)EdT!wcQP_%>&!r!Hu8e+evoqhAM!tv$Ulm z?KHeQQ(9OtWd!Tt2sLlZRI5^Hy`n?ZTq+a&ZG*L@(|HrL!lC;|XoSmiBCaSko{E!S z#fg|bA_Nnf3CV{L#{X9!Fu21M5Z0$b`a`mIjfe6L)$c0iyX+R!SG?}Pt@TXzRooFJ zzRarU`a%1wn7o}KEgp8Qe04#S@DM9Ov1|E{;LO;Z`P<3Sb*)Xv<=G!k?LZZiN(G9X z8h>!@U&8K1wa3uDqy_0e6tyir?&e&9V&RFYVzyT4CxLA02=kbGn7e|IW}Uzau=RS` zQ{wS5HTPx~y@U@9w~1dpQq-h(mR_QT+$f~n43A_=!MGwTHuTpTtT&ZTkQR^p?4wYR z#&D@D<0iH4c8AL?E^24ci|K`Ft5L)cMKFtfK6-+7v<IL3EDgjg=lpq@mV0vo^K2^a zO&#-@?6j9rc7mnh2B~^P;(erKHPVJup0K&NT|BR!_Iz(Eyut=n9zKQWLRPt{>}~`O z(U|94{-Vzc#ykDx-E+U_*iz9NJYu&-<Q1?^l!`GA`}#MRF5tE<->i&edD+b{RK%Cq z5mS1mKZkNV&e>X<Em87rwU1g7*qk(;kM8Z`8nfHV@4U&D#ce(7=0Gi61{#v4fa6nR z0tjP@%ZlHnnPq^bJ$_UUed;3r{xy)7Ks|%A=1lD!*Q`wjINnmj`}~8ojbWN0(xhg5 zp$}M;!DX$^(BogB@?BcEC|f1vMTyqOAq+}2Y5tDzpUHdVsP}mZvo74A8o+4O(IbII zC~)_vrEN(>Mz?ZtiJ%?|hTHX`8=%LS8qe+n*H~_?5F2~d>~}(J*Y!~Jz>;?h^bY=C zqpj_B4O?1jb#uFJr%g)|J30b3LXREXuHD?g^GnST)U@^D5-rFLJ+$Oq2K9U&R0%pd z3SL}-eax$r4Bm9b{M*sd#Nraz)m33WlyqrH0`qz(l*7eU;VFYX6lxBI+B>?@?jHHn zRIyBu*Uv27^SE7WvT`&)SJr-s+q<}dr<X)Vmqccl?#*zoy?dALS=_Emj*b|+?GJ)a zbC$-vQUe_hM(UwB_0V7_^xDnU6vL`|f^l-)FC(0wD+)u;>@H9B>h2bsoY(zTf<#VX z7#kKxdMnbSeHIuvQqKZxjAr+Z>$yN)<RvWX&H#zJu>UQ|q=4DkG3+^JR@L(nOG}w3 zs?+Ohd+KIvcGCmHo_KEcwpsBW02$@LtYU;nhC9s(xiPfDD`WOT&=|<g{{+hMofT5C z6(Qm`7#bx<+oNxEfOgOhG<|GL%j251b)(xcYe07ATk)Xh1!rwk#qWswgbFC}2M%K! zI^z}2D_{@J_u@K~`Wl3T`>I5fmcDa_9I74vDSu(5d|4uX8~>gcZ)u#4)-*XhqBKHp zU^X}co9l|oSVIUZ`gK!3!k&>#$KQAV`F)A_3R&2x(oRm*s7Mdj6%R!uo&0!U1(55C zLG)qZNI(7#@R<AR@0%RX<V*7dq8?EgyEpL-pmSDZo$Qi_yFn}d6XL>0KK>J5Bsauh zay&8G!DTT_(f1~zo0C7GLZD=*p9>HOTJx1cjNU|52&d{X;BdZd9)?t?37*`g=|RHN zeImU3XTSEia$W&Mt*G1L5b-oanyf8_T3tF3Y-X&_4Q52j@r(~vA}%e0f7If5pU$y) zN!#x&8kjxJ<k`?H69%3A-FB~wAF|n4UqB&lPM-lqGiv0KyU)r_2}q>%GZzM<0(CvE zbs!jqg)Z&Cik4=uX#cFYbnq>Ggw%Hrm<9LRGQ4~UrIkOQrdg_Nvo}1uRS#;#A>JNX zLJWgL87xbG+y067bg=hHa;2bew{=ios<@co5Kq#~mry)^abuNbDr<=s<+m1Z_){J? zB_=xQ@`ln*@fEr78+IMCJE(XZSstlz9S=XIdKR(8t==>1(R0=Dy(#~*m%!$^Y!5&8 zRXWOB*Pbd|z!=)qe_+T;hGBxwG;`v~_KNL{<dMml+OV;9ncm*G@4|^PA=^f#oD?T2 z_1=`bK`m^@W^UmlxQ(F+%Mb3O_M(V*AAp^^16}LJtYP2XJROArUat@4u)>7h*34Y_ zj8n)d?fnb)f^6<~Y5#I^>T^)ODpM7<%J4o?o*>l-*~l;+42pF2&1u5N3Y0RAaxuLG zscOC7^(Eqcr2a0rLb>OR^D&#@0Whqq&M0Id*ms8qsUp5}RmaJXFBBgA?T$R$_yAG~ zW59BtFN0|^zWYoHgU^_3oHNw-=kCF)9^PD-PLC28V6BtO^-SyqSB&G=P>1YG`S9ua zvWtAWvM9r8yg#gb0mfku(>L<79({2?+4AuzamzR380Mx6+5AJoxwDpH(F7LuHsAHS z7rQD@mM^L=)CHJnqUVRV$Q}+Bj3{8PEM)znolF`b(UX)8$@6i`f+=o=ai(9>pqWq# zMNm?vH^PbKHZCR6?5{SZK3naYi!{*9eSLrpa7F3hi}T&%5v{|EHWD-dUlC@uPOdJK z&4Dqn?_3Bf?TMbY-_>yGQLH!GX-|%9+`)#lycm~sNam^-q7=x`a2hZ=3CXjz{-0u3 zsO!Z@hr<3F)-nnOGg35?y+svfL{t25Mk0$XVM&G7cL52U13>l%Kl7-fF|0gc$2wHC zYjRqm`UUrqpk09EQfYj2tUI|~-Ow7SW+`wXNki$SOnug3&+PRr>cnhk0%BsRdVZ6~ zN((}~uI!+lSh^{hyLO;snbZv<JnF%#zOPqF^jpYrOvFb3sInePIOwRBZbJeWB0~j3 zRl05?e!|jyiv{aGMYjf4p*hX?%6=ZDbI842bWr%I3Sk~Fr#<RUHz)mwHQG@%$<89z z5XNP2Zx`P+i@8d{-md|k?769~Wr~Kx9j~GsnT4vRYdYODhAC>&(({qjJ8TJUp1qDT zjEa(Vt=;o)0+0~NGPyt0V?GzvGTprP1=KFguh*}`@C;tTB(~m@VtR5PBQ_p2wWJL+ zJ|?<(q%@6xs2eX^ul%(wxZ|;WIV4Ik)qLv58E{l2Y!X?;$rLFLym$r6FB=sg`NRP# z?R39<FG_a=3qAt?mUP(VvIgODUP2tPITazK4$g*&Y#$0%OWk9uNNdk!wbnJ1)S059 z-X5IsPk*M?M+lO!qh99XiaL;P2=~0b-D+GzepOw_?w0EXzMkl~sQ^D9rKY=kI1?U* z>rjR$$!bl^<q-Xny9W#w@%xYkuE^dUH00El*Mbn726QW^Lq3GvBBOc|!dHq;rA!&p z+oHbVIlIC+b{<q99_k6)D`;?Dy)=#)^Vq~;N*!%oZ<4bFMCN+DAP|l1%oSjNtiMwg z#(Q^yk&b&IUD_2Nyn20T^9ylILgVR{ny^rQp-$x^Y#0u{>T&1B6K#Dvo`A8-IRC(a z@I8_Da9cV1(e4U=xw52_&MafJ{ja2f<PUYYo?Af%<LJl?jANWM_%?zVlk%?40=HmY zJ98u@lUQVdj{?iOz?|`+zvyBNIT2m8c8ELg#K@9$dpVKSiS2b7+rK`^k~O^J*N0;f zYV;6>N(g84Pu*q};Yiv_y#Uu8+#G)0#n)j47L1Ni#;q&*ZRe!U&pn02rVMK@vsVPs zLHtPp$IGv<{?@(^M^pKF1yFl;d8ua(htoeE^bH<J456%0bj(KglzibdhONRx`8a5Y zB`h*uQ}yC-#y~cB_40r?(WFAp!{~4)4)BrZo}+Q?mAls*^dpaxVxf4$CnTGT#8OYm z(*r^7dh+L`i6hYUWYTUgpYqLmp*P+Rkt4<j8h{8+kXZ|J^C^!PfqQMBd(ZD^gIk`| z8p$3jF2-}0MH<)6>g5$KYG>i?4Lv{HLyd~?Qj)SX3&$b*QAvTmFJ2EAEqK$jHGQk0 z!S%i8yV&iQERr#tXQ}OK0F?-ti$D~yc>sI;vVjb6C4$R0fsdMW6}}$(?a9>igX?-- zbq1P!2^3W}OHh^pR}zqb^irYnCUbiNUlB(%Hm*Bbj>fz|ILwE3W>*98p?&7%_PBG4 z%;-;!w{z&O34s?kNOCAJSP$U1H?q#W%_ZOSouk3%Ff0|#7#?|oZ^aaMSzezYrX|6p z<V-Yhi?t-Jr4AlQ>2*Eo`eqXx;z?xgMHag{b*u6QO1Ih*O@^^BcJZ8yaIE<~_h;V* zghu--2!0yQS=V%n)9lhnJfL9rY`l0Qq*>1jX<gm;PQ)%9?$GH!X^6lyo%^PjNh$9s z!tc#G9n8qy;h#;oo*YdU-c|VuhntqP_bUM4{dDMz>(S#hB_wYTKD9kVrLwfG@);-Z z2D`2TQf|Ple)Q{ljAM4<fo+d7;zIYsl>~>Xd*E!4M#g)&Qvk2HJP)yT%eNHa9~?dc zhDgs?!T`~Uh+9OcDVwynm*bYJm^aE->^s(GikLTzhCHC<#bvbgI&1-?e`LF3%y>eS z$LYoRyX8&~I}Q5SB}x)@{u5{r_EJ+Z1a|56`P&pPnB@Mvm8{5L|B7_tWD84I2{2@h z*!i8eMytq@@fRv~hW4A-^o<8Z>Hq%80iZ#2oQSl@CQE?v#NL|nc_^N;MCd2dpV(_< zG=;RT$8?O#?t<ID3x7q1P=$^4v;kM5k3Somn%*n0?jIZR{W<lZ4!8a_gS3vwU%EUe ze<M9b$u<yNcYc`PMwwW0%Fb?>K7wnOeFJ5Uw9*2uURyk|OmC}*CXT+B(;dLf+02P` zrmQ>o^$N?g<BV`am*08>?9d;mlRFvj`}|YW_3LPxbT`mV@^o{+)*S?b@$A<NPMR10 zq)^DD#xPuFcOXlS35~B;e&IS2o%$g_y`qSqLG$V-Yi0o;>KAK<gW!GtXPg6(xoZ(Y zBS{t)q#;?SY<lV2E{pxt{wjRmLj+|`-ws44ud(;Ev4J>}J7=l9h>z`R!R(S0eXRGm z*Tb-K=ttd1O5cz59<9^@&JUj|{|@R_MtcbyQM__c7Hv<vgop7iIYjf5#3V7U**Vq> z0-<Z~j|8Y@J}2F-`g$p@^>r}Z)-mIuoA3k_#9`_9;oaxt4_Uaife>25!R>-A&~HcV zC~vAC3EcIO#Llpx4S7CvYABI2M~^SP!v|qQr<QLfXNB&EOaih^(RkLYM8&I+UzB%_ znV>Z;lD=B~C>Ew?LYdDM9fmXNXblfuni;j4>wggW`y8GbE%kRewW#Y<CRs(~b<SW< zWG&&3H_Er-g8_qqsUF=2GTN^aKE*`@zDkH<!H&{vjOT!Pq=w0jP)c(V9$E7u3E(`{ zDZoPNuo6bHflo_4Ywar|y((l@%$EzC<QhkGTHbb2!<6NBj`BSV{?@t_mO$TeJS7%u zK+icuNw%Q)+(-+@P%rfidZv@1m3iVH>oywE`P#BEqX69H7}-M}I(j`K;;2mFz@F{s z^I)9nlZNWod2__--Oq{%&it~_o2Rz3AuIDh`T@AgCQ(4qIPznK-s-3qp=#Inqv}Oq zG_k^2s{`?YpB@}_qmVk}q-z20NnYR-g~0F*?JKr9$YiaQ&RdL7A`UmKzT#f95xw+w zzbwx)XlZ?Sbl&UFC%GdqqBAx@g>kQ$*3~hSN<l$D5DrxwS#q}4gm<@fLu=*^`b}ru zkhL<yB9O!P?Uvcuv(!_Q)alZCzxNsVGo7uc(S<Bsw~M)JJP8|xH)@ACGFR)wfP2EA zYnup4`+lPcU>MQ2uqtGYpg`h?Yy2LPG5f>VXP!?0_9IBbMyFiSz7vM0an2M}e82PL zNwhAcZHg2($5Lu%1ID>{S|$zWdM?G%a<LpR(n6f5<t<5tS7(Hz{oa>=PZI;fqE1v? zUJfet)ZK=78huC7Onrv^^dQ?<ll1C$?kw+w`y~8j0Cm@k$T-lggevlTh^`ni#lU%< z-8jhHzwxoHcoD6xk;R>4aRWRF9nnG2ekLmTotsizjF!-1#7y&t)<Xk(fyT5f!dHj& z@=+L~W60NttcW85AgbhjrnOwG4k$K-J(;g~-^rqHYM^J4?*@h=<9(U;+dzbwtrdKI zvc7U8n+%rla3`S8Dd&}T9h0hvtSZHDf&XVBcizD%9a{keD?sCuC6_QJTe~*WRTrbl zm6mn(rEjA-2#NIV50Si7`^a;mdT&vGOURSiC7?mn!kR+8)a|PuFd;OuUJ!yLIJa^l zl5E#q#0Cb1*|ym(f$A;K>PCU*&khOe^FFuX=Z*sn!t?M9PnHQbF8c041cT{mp`Ht^ z14fTl9`%9nzTSyS@ea$ar6zRtHQ|viQQr*yB)JPN1}#4_c6c3}I|zT1#aNmKaSUBD zjmE1%o<Ex{w0zl`&`HkT1;$F-gm^sN^8H2T^`~kP=te9NjUpbmp>4be8Od)yG*hHL zh-6f;rVG*keK@5+1%5YRm<v9N{ANM;_*fe+G@Ok#pH_U}I5?0pa(`V^{wXbMO7sw1 zwzQ3RUgvamS0T0ip3L_nM68V1_!Ht`-ra}O=IV;XQ52o47gZ)5xoI<9?b>A}%f47| zfVW_(8&`jGq#PefCn=n$qBwH&{YYl9qND3{mR(b^m|(s?nGlLS-o-zrbe+cG!@$}V z(b$(S=z}ORmyb^}eJs|VCV^cg%qj7OFVYW~5R%h}78Sv-Iff4We1vhLzlwI{(bPe+ z{sykhjF^`Tnky$o6E+%co4o6B@TVELKevqN<awzX#CRo+jdc79T_v(&Ox_}{5EYR+ zt;gZ{M$S7AMY!udS{hp006p%APTUw=T7{|`&7VWoB4ftVP+_?z+<TB?=^=tutPrvA zzzqLpws49iwWj#ER@w?ExP|C)E*Orj#|1dM#rrK1z^zO>?5-=>ZsF^?F0AUwyGI_J zPKV8S^L!+_c75;*j}QJHGDkXD?jm|X2<;{O<k!+p&XZQEiZS4|^fuNQxaa$8<y$y> zRZe4-0{jwdl1OmOO$%|Cb?4w~-|ki=b2=j6@U_YW<?%ptj))8C6SjW=K{SPQ;hg5w zBab^;)?N;zBR03jEbU-80@rJGYr8bjZ!gHtJg^~Ri|@{{Hc<_)NiUg@=U@akzxEm= z&a$T$d2TBxtn-rP7$gW!I3=VFZ4aQG`2<)Bfh7dPzAb<^jwk-v9*H)XvV`rCSonl? zb3O^uUt6{=`UkY98+NBFdP3OYNDhTW@B2jqoEPZz-yeXBw0xJ_Dgzuv&yJaGh~qQ= zrt6p+kbd0C&3#&joD#vHwb)-=lC%7kj@g+--8e0B2CcfTS}xw7E|8;Q78W>V-aK5% zsS&SQ4&o>c{X8*Zp%s5?PBXWG<pl=@9N+vi?RW$$;!fCjxEA`A(Sx13O~Gb>5OSq$ z2bPw-k*<>d1&h8d#2x+TJT;PA^C#DL{73#*hK*6AgK@gv0DtA&HM^bni$<6jVfbAB zs7_mP$NcW`qWEJwTZC<I4&qLy_v({#(3TOp;c=SPN1qZj>Ae?CFi11lTOqkee<z1_ zz{kb9-0PX%^h}4k6Q15!A#J7{z&zShfDPS*t?UQOY@i)#dHTb!pawP9gP?rnHIICT z>E-1}EQD6)9aFG+76HPJSa;=GFC`p29r5Ngb$oWza#I$q@i$9*@3(#zStWknuHh;C zo!;Lci`~E$m?B&5K<3H{UQQG34C%@~&tTpXzIpG=g*5)#HEkea@YaCRqU#(5){_lg zMzNoZ5x9Hox>dqlwsD>Cqoej1%rUpT`L_+V$$XyCaC3%<n^ENHLxZ@|Tf<MW19kZ& zH$=nGj-Nx)L(xXn$Y39;3}C47lJH9<eGC-?w<mt?#0LH6(B;G9u_wA(=vUzG32co; z4MA#@Ag*;6VI?jq5gUzc^bxIFd+SofO3M>%jmK_oFb8nOpf)@?kFeV*E@2xb#7ZW( zr@tqOX-)1b)M$uM?=LFS1WW2dB%JX`c4fQX3jX?D1#aC4%G7w<Ipgrk_+-@fK`9-r zE!vBCF@Yo9aj-MlW9JZc3lWwsF9Wwcf9{RFSM|WQ_fGBS0pqjn6MStBbt=f=07HF% z`QQ2Ije!xPh*IU_v=7ravWN0!bVJN4Z&Qd-bJURyuYXJ|ET2OdZVi!h1=|pujfNYu zr?U%O`llgO@uGB|6b8b^rvN`4XS<Z^KIA!_m)m@piUVm_J+^@=|EgRKKpLj3d3wy3 zIfs-TgvkxU%~IzC0q^VaEbGCd0irkW(uXfPpVCE-wcmrD4>kZI0ku64r8>zAh^NxD z0+Y4KyN~F2gof8%_ZlUueI2TN+7mM?BpG|YNxOB^V(D~f_OG*m?~!X`1|roq7l&{p zyRFuMv$fU)Mcw>pDfz%%?2{`CJhur$Qw58<%L)6`lf(PBE$;5a9B#PJ0+y)N7ycnS z1cUzn5*=oV@6QjF9_mV5cFc@<ByyZmwE$Kk%PKuj6j0KUR7X7;MjMubS*Mg99PY-V zSerDTf2QABhIR9TJJQa?PfNVe>L#-^sGBF%pICi_egw~<8XnhaAFsY{^3|EaT4!k- zT;oUTx-lPt!9C5L?u$W4qU)#DY}X^H8V)KkSVW>k*IyFWUYs(2PFJv4rkp~8><=jO zPeuTRCp3$NNDXI64Wma^uW!#kEE2r%|JW)&XkOC+bnE1;TB>iqDI+i4<-Qn?n?D}L z?IhGP<e={Pe(_83Qty|G#SNTpuxcq%<%AG9P8AEC)kfQJ%ufNKS&Vrd#S{>I(bwr+ z1lUWA>{#C(_602ZS@S=x3WOTDQ$^>=*=uow;tZJt18MGZ=cn!JKjj)<9SGd^Ae?kx zFVJ(@`Mxjd=6JjLrbs|Kk1rkpuj4`kC`5f}1tButPw_i8<h&lu@G7<z%bk3ynf5_7 z2vdMUuWG15A8x+Dt-5FFS(sSgs5N(NS>zOI4yNBXKCQxBZQQ!mHgZlzmQDaH&nXVE zPG_O?nqq=`Nl`w+BxaQyi^HH^80N2}6yA&(p{ugH>%lLAp8F_)RRkP6&{>)Ew0;9C zIES2a7b9y3&6`IMj#nBInhdLjH@HIRPhPLzuV(9pj@&1l<{L%Lo0l@%m79nmHi!-c zDItmA_En<75HywFRVx9lL(EA#;d|+Yr(*IyKUPAXF*VSv2)PTO2vIlYrw}(C#8-KY zkBEyfcE<e8S3AL=aCXE?d5rNmgkjDnr09LFH<AaE)cT0Ak+SiWfK0ZfV;9sJ_{$gm zCECh-og<e#J1r;_<$<rg@zAlYNrg9)>Ijm<%hAb}_kBnpY<2L($w+j@jyqoK@mg3t zWr@je@R4s({i~VDmF}cY4d!Jag0+RszGDsGcXflCe)E1kX{n}?^ex5ph+=pKn-A&v z4UecK!sQ3`*&1q&V5Ois`H0pm+k@g7H{~StRI#$M_S5{z&nqwDo8q=>oODHlA85M& zq<P@c&8_r_X(x>b35vA0yD`CmQV8SIkcAjhU9HMO8Bk&hdumNURezgZp4aVT&qeO_ za2yYA!zA=TT4aXab0qX*aqVzAwk!r>lWjZ#_Ia}0gKJO={UnC=^9<g7`P%h*ByzNY zJkx46wCoy-cbv+<Q?`dSt+imt&V?Gi_-^_pUlabRx}<Wrkm>&X-QuNJcuEbK_5C?@ z`9s;K@%7X^4<NyKH!p!Fkf`(ty&>RrN6EfXAh?BOqEp%MS^8^p7uUd-^;pff_?pwa zR2}E#BGDZ}6bQJr15cbEC7N-F({nNDI>A!HKM);T11<1M?S0@pqgAO9rxh6wzUs&> z;EZ^Z;y8sAM``sa)#tuR)a-LT`aLK0gp!AFq)F7TZ#NY9bv<-^AbxU>s4F6^3~eS6 zdQ{&SNSOO5NQV762DuA<9IYCZ<cn-mY@43`^Z^j!M7;rNAZk&&({90P>CQCh=b1cI zP(66}1n#l3wshjYPoPT?ot35r2LgW%8?Qpjy4V-d0G1v<ht63SVfHqS?x#|6e^=c_ z!I%?F+>WZwXdfi5JC-w4789@MEw5=~pN+O=6`zeXJ1j}9Qh4F&fW?mQdk;o9a=_{S z((bf#(kw{Ovo}5t!C*4B^W0hPZ3O%`*^#?|XgFSuep-mM15eq!{KZKBZ4-kiv5Oem zi-0C<2v#=Ln5oekWKTVC@~OdE7y(zV9{I*QCW^;*W*B*A{$WV=-2z^YN94M$U>oqd zhxqmpjj?Tq{7>8Z&*;qb7&Fw$`Zc%8Y4NX-d-Yp5>8Y=B)c46I@2D(8mXpQ3vdR@# z^6L@*)7UDiDr~&7xlp+?=DQns>qZI|$9|%Z7WAYBZ3r01e+h2tB>rK5;pvU-I>wIO z-=v7~q4b9DE-3DAnpf_R#Vl`5vv2^d%`D$1hx$NeA*l}c#k6*`s9o=~#~rT#+wb)_ z<xZM93~Riv-gL}~M9@7I24RE?4VhpcjY;Z<>mv~3mn8xZGb3Otvyt}4b(WiL8}<iW z$w536RnE0<7&xpSe`)BkNIrHX%D#=9aap%ll{mi*aX~%gfyoEO{i-J~{r>*TjquUm zw+{A#VqPCth2$@|ORwV=1D@&8Tf70AoRRBp*&u#BMy~lfMR%;0NXsopLQD4P)}1P( ze^iW7my=um8Wdo*b3o`DY`Ai~=1(b0`dQCHyAMAn$D4gs;}z??gP=?mt)GP(KH7_n z-{<?Njq(s>eUreGm*E9DevG<#&SmCQ{>{956+-C{-mE(flFqc2?HrIZT8vQQ5@VA7 zc}NyA2nW|g4KfKEvngqytZm3ff(x8547U8Z(>{CsG$0stmQMD&lM6L>bSfY?6O!S> zZ}h+b_ihp^mz{>)f}R@^QtI>w>p<hA(T)?c(n*PaclQ*E{mO}8{>DrT&+Em?zKC-k zAK3*W`FIrO^Lq=#^A2vODw`C28pKTlHs%}m!g;IuGijD%=gypG!~Ud_<ojY`AkJSN zuHIG)SG6Th1Y&JaG?=-2mB;9n=qG{o*AXzmw)=CR$sw!(j-6CxndIQSIxcDd&8CRv z9^>opj^cbHwq%1THxB3~+PDNKcY`at{yD^@QZei2sE^gw$jH`J${F?4_LXnuK<A$# zJ6KB&x9(|>iD8o`<HZ8Wm}U4Q`3kMOR+dA>;#;}S`zpXt8QHXIE51-05VXiecuNT| zH}IG90o>-Pzb3>wY712IXZ(UybAP^a8i68fVN{%?g^9vQr7Xv59MMR?!9ABrX<T$O z@*L#;XkZ{Y+hCeh>6&1j(uTq8!=l_jyf4CF@+AS(x7tjdtuVWZR_c=}=rtv)L8}}3 z8V$W(xIR{~dljDr;+QBgdfQr$5i$`ALW2n(8=C751Kk4m5wfXv^afGw29fO=TYc*b zYU!|h7Y?qFR7%tldkc8fonqLcXc=hnSoqdlf2xT1m=;NXP0C|h*V*iFdu1py{IvTH zhi!|(>jn}$;TTOu$UssTQ?|yx_Vj4|Sb(F>ZapRFc0=9!!{PwbQ@CL!c$r;z$ubd7 zCCIaSuChR3<uB!+|MV)r7v-RN#olYjNp?1I&jA>C8a%x273sA-aOOcpgaPDArgTcZ z1pBwgM)l|%>IXR2B&Q1!o}Z?MxXJYauLFW1L3#B4qrSGMBN`zbFROPL55Hi}CfCx4 z1cjZiXfYMtH+zpneYG0#X{~rsRg{f$GFBUF-xkY9dPM4zKnE*7C$+=3<F5YfO{hg2 zd<*;bxv`W(%%Ac5)hebj%k~|dDWc7wZ!#$r9DaGDj%M0C#PDwQgCB0PL~zC%tsp4J zHQk8t)^q`nk%ZKql{=8SJxKp6`9on`vD?DL5go*$*87x4-oT(0k$SI9Q(06YqkI(b z2?Wv=hwe5H13>OhWE*kLOW87u3a$xCrK5km8t1@fKEPO#kBpY@a6amt$kx5skQPM7 zl@%maU~YP(ZiL!*TwXgT6{b)2I$?*Mzl`l!FdwQ7Z3trpfE)B%+dVb!Q0<~SU$LfW zhMEf8(SIMV{1r8Ka7k3bT(7f^X=7(#$b$LQ<sI!0R;0rpQfsW~KN>5+N4kaFR3>la zvOn7L;#XbW`%7EcqZhG;Jabsjg&nA;*4=?z&`}@6vT~3idc-1?hD;mnZ+`s;jAD`Q zV8YuF=$%)X6NtEjw|>8f>bd4M6>W-{9RQ-qC5(7mA{X=3r`Zt2tQ`Vjj9f<7pZuGm zM*eC0HfD)gjGH%;I4ZaG=PUn|Q25-B(qH?auDs3It6Cds=4MKIi}ruEqVr-9@Ex19 zuL;z)d5ft_otWm?JnV1?M`yxRA0iF){oddcn#dr|-w|}(C<uK|R`vEt7*Fnxj@ad& z$7>_&G%9?N0Gce8J4`q$j#7L?+#mBH*6&5_&@<l)Dd9AW(8FKNDSfVJuMepsk5XX< zC)a73G#x`7{(>Lel11E(w4KX?rHIR4n>+AdbR^WrG-Aupryao^s;ICI&;PPkZww$V z9sO*!;hvQZL&{p$p-x%CkLct($};>-f7=_pI=>OqJuiJjyWxC@I29nfon2Y=*tT2@ zNS38t{1N=UpZwVA4|x04rP=1nf*BgAD48Jgz}F1-a1Y|SO5-7#y)JYyh0`TE$XE6* z4Kv6`FB3QDh)`K8Pz1gw)sxQs!J;V@vRBbrU&=Nld-pq~E`pV$<xIc1(grjLJu8|c zRpXw(?5=$2KXD`q_4e%@RA8$-D=+sauzB{g3-Ziv;c~y#-bh>C@P6iTtg=SpyEzt9 zzQb@G5>LsZPUrCbw(PXFqgOlT-t^eUzd-{+^UO|1jZzc7*G+$_0+n|C^a^x;U1!+F z+V%k@86Vy1Bg)ag{aHtn)EUnJknOGjj@g8eOZ!tghU%3bLzXxn;jGTBn^3WqonMC# zzYJz1d}YTO$-=o?@wl_2l@-}AWW3`E=Ry&X09%h_`~j@|s4X)D9HzAJ<8;ZKV8CZ; z+~Ck7_#^7Z9^t$YZrvJ=dLM)Gcu5mCZS;;R3iY<H4rQS@)f}HyZ@|a?i;=7MK+25| zBvjf()a&}T<(y1ckZ`Bsc>NJ1q{8lPsh^CgON(0ZIpkOFm$yR?PV0qI!AHSzs|s2g zzmcE^FJOZl&qN#qVUEk-cK=Hsiv@hdx5P~dZCmHPiPtBjqPhhT@A7QeY!SE;Tn6rQ ze{cc3H!xgeuPwx^;ogXPzylB}Lt9J4!Gp%viUw0@{|%lS{s&x~MkYhPl($TyTwiX! zwO*PIxxPaHuf0r`&tT?tB!l~7m9Yxs^R4jn6%1B-jweT+(f=Rz;9h+y=CmrnUFC3X z=#cmE!L<xmy)5|gi)mVe@+{8KeS$^dh@b|F0ME7kZr;#a%bpNR!Twna8m4tdEelbc zJGfPaC{f0)-*@fYzN4sP|0?{prFJ(>)Ti4O6OM$sC7_$XlLwA=A8B0<jb=+beqheZ z)v@G2M5mtg13TU;@hhKb=vM}T59>hC?OTWgFK$^h$5E?j!jd}h0g&el()R9+yMME$ zN3@Tq;q8r0SJrbDq#7)TCHY$7RLYkmZ5mp>@w9sR-R3HR#>WRb3}~C5k*FK*!Ml=n zwpzC8BJh!)j8s{cifs=^zxUsAfWtE+?Ew+29^CRc&6R}x1bQK$7d5z1(Km>LBOpOj z>PHmysg_3beP^QMQK$S8w&u;lFOcVH>(PA>DxQ0u=!I62FNVH?r7dq$w7hv1!&|kz zMJqT_(ux3yHB+|OI0k~VRZhG1PQTw4nOjdmjt?MWou(UAsp(;ekyJ`Ysba~ZAK$h7 zf+K+aMjR`??3nUj`2%cf7;MMC(hC*3T&XU<jW2hV^(LrFcJZ%&{W=ZSB^#z~tP>vc z{19OhfvG#jB}EhXrPb4HkvAH?yTRr_vq`r$cmGkM$J02K+lgoC(qHq<^3g+Q^6x^* z{LFR22tpze#)Yh}W^ltUFemMV6H3SzDrgSshS}@!-KxL++ZRguv|IW!8K^OL=F@s< zywY|uJQjyn&;ka|4jjSOs!7p)^Ywxws!g;T)#Q`ejxEHO4SMM(cfkn2^|2tK^f+e? zf|AB4_K!w4FZ&kcxJ|SAHRxER3lfL@cB^i7Uh1s`gWE=yYZ@6*Cz1c)^De9e<T;;3 zPxndBSbd9oMml1rVd(%tsqq#fC4F9z0B)g}856H4#;&Yvks!Kkck6w&J|OenaDs}; zlj0wZN|&G{+|_d}f%xr_^_7zx#HkOCZrB(=FN-3Zb%2O#y<_yi?AiSS7I*H2)v1wr z-i13NM`I4u$*zxHd=H^d<GRP_SHxaY{1g2&%ikX#4VNm}Q2299(bRivl30H{g5}V9 z9!WY2eqdU6p|H&DAIDR>8{44|NsBhI{By!Lo2p5~k?|+ol;|njI!MZN-63mC5je+p zLRlnbKpNf|iv}Qh7O%bSt9%<sw4Fj(1%m{R-l`rOMz%3J-L?0mwtLlXD7|sB%x)!7 zwxbvf71KJ}q5o#&&A<9}lV8gZ<_P)2WG!Jz5kwikHcF?Q+;@ANb^yTZvAiGbSUzK& z#A&Tp=JW+ol@j`p9z>lBYgf!nxmWVMsM~x3c&jhmukh+B8I##wbb9@Siov@Z#*Ur_ zBMk{PLaYA9nCNklyA5%KS}u#@g%MJeZ8bh#H!YrjXWnATRXy^ls%VlZS}(qTFQyR9 z^5Dt-9ktU{P()Z@otGT{<9nP#pfZrGgMln}yWfo4&0qC8HqPbcx)cp=9S(0=H0zMz zq<JO+)sAU}oOJ=YzwE#s9%vL}-M3ddJ>&9fk<Q+~+E#b|Zm&y`cbamF$Mm*D##f}v zt**JieQzFLCAPEMf8Ni;N!F8=g7K^Cs?K+N8s-0ouD6bgI_lbnO+e`$T0%j(n;DUk zPz00?>5xVNsR3yiKtwu*?vQSfZiZ5Z?(Sw_nE3|1pZodV_gmjutoet<@LT(w-`V@@ z>$>)}dJ@YCeNZj9esa$l$Ny-D)u+X+iz+eqmDkgj`*=Nv?OVYy^z210f+YD$KP@{6 z>lP+zlCpV}pwF&FapWyqbmG?KiW#C1aQWjefCX9-^WVU)1FN6qmci*XtyWbgu%)6` z^gcnR=?vJWZiJ8+-3(rL?_9R+mB8?qEt9`5M@N+OyG*OhcLgp(U>)zgly6S*>OL%J z;x?lSM6*GW4xb2@WQ6Zxv;Cf;k%DSL@{R<P*2N%?`pfL}oJi`IyeO=nEl&k2qLEL! zpQ2t(#4T{l`IhtD8Lo-9^#<YL5Qp$Gqu=m%AD3CiXVs8)oh!DxRk~#?H=njzw|?~( zXXD^|q_s&}!Shakqs8I$DTXD<V-5s&W6v5LMcDHPd6eXOs;it-6|AqBKi!EJQuSip zGPf#S;OopW8CQSj^AuG#i<D=<m=LrxieI!$g8CAi>+SDyq>Yw*(5;PoSnT>HKK)=0 z>{YbjSvHS4=Wy$dXGAx7Z_?bbg1uIBVD#<WYXS`z9-m=t9vWtRJVk}lA;7$dPasRq zsKj9V7J8#+jfHj%<ZhdD<@%92#mDLR7mF<wQMQyNg6fjNA18e5ym^{7-&Y8_g-h$d zc7DkIrKp-Gtx;DkQR25@@Faf8r{v4zWeKMQsk0Nl)?xY0pqhsFe}Zb40bI>;YktKJ z9a6noj+9wy8-~<djm9-ILpJ6|rmZr6fFfHAo(^3+v$56y@q{BUal-rQPc4@%Yt~&7 zcbAvr2k|R<XXbvsr^>0PDIKAipf}ckW+)+_W)J5;xv1(dx>>D`zek#T8x1rzJOGXP zTp1i0ezM)NKq%1;oKgFmQR=sg<Ujnfo@_5?uS*$CB2u+i5?20ZAD)xq5SY_SijKwR ziQS&n1DDaLCAL)bj(I!2?i<+7Lw`^cI_#Q*hbs*3hd0~*RL~*F3WoQB+XM)}?gJ91 zgwh02y`zM$M-9risH;Gr{Kju8z-*(h-Srx-i~WMShy--K?F$ed<q@wOZkLE{Lnw32 zT?4g|GXPpl$}zikVA~6uB;R#q0JGh9N($L|ZY-vRL|?QD2<SsDmdLD9pZxZ^98=x% zM>+FV1QYMKk*08sq+ww|p3`|6^98f2ZI_r#U_TE%bm_Ss<LWm4^vi2*0BYzkF)q?w zE2~DUaLB${msZh(rsO2nq^luw2g50(npQwm@7ceTQ4)A-D^ns9SNFi+LQ|jl87WPM z1T|Xt^f5wg?S4C5{&%EAAATHIO27)**cCM}a~Rw-!tpl3^K52=A_Zp)IUk~1PjfTv z^6-4DKabGk__h4ZREpsGkFKa2`P1K?<URJ*BLIw55&><di&X2EOs8k#L!)}S78o40 z;Q%n&vr$>(!{B^VhHiEmoDmsBEeP>}45Rl)D~)rLzpYQy(aRV%<jokhI%a!4!xTpW z99hdyT(edqRA2ihe$+}&iD@Upy$!v6XlOY7J}D}P*wx?hvA1KH2qkEywY*Zv{p(Mj zW=46#F`ULxr+TuUGrni0Js)P>$EV(JJ4yzP+-<=z{}6s6*!}`J*vXKgEU9wiv7_dt zchcpM`)ci0ctCeAcyktt_AKkso9v4pS}@2>9uCMc7yp>Bttn8ie74Hn4&KSF6H+zx z8ZRf7!j?i<#pkuS{`}ALy0l?>iDZF~u3BT~1A2YdPv~8v(drIN_Fo5~X$nLE8g;Z8 znrKyu7yeIh+Hs<mw9tCL+wF<EmoUzh_JX}Z5lA}Y$L&WoI5EVSDcsl!i&3tHgtt-+ zIA!prer*rP)pJ({F?Jn2+2V6H%(ZYKCRC`<*ID{GX6}=Q_6>_B$}_%LP3n8g&dC7H z{ZjW!hTZ2q%`SiERnvXN$mDT3k0Pe|*aq7Skme~r`d;_`LDm)#VZ5{&nA#7kEACKZ zVj#ar+H|0a+b9jlivoPkzM(%q5~Z(YE)L+B2)-4J?S>2N+V33C@}5tYaerA(^-~32 z%xVy}piWaAK;!5L%Y6WH;)W22_yh$JI(Z%|pU?6P7pA37lzqN6S7`@O-X`%|wawq3 zfbbPgG$$7fHJFBomOAmTL&6)@>y3v?V*mFq{z9lr&sy9L*5A;sCW^EREqmg<Uuf%z zo>y}ZzZ93GS>my!_BBcpeahgotCj4uE9_ifjI;IH&eghO80#S5xVvd)I{rxUP^9gw z)@I(>bD}32?!5c=3F-*mT)?>N;fgo9nE5Z5(@`4JU=b&tV~hlTuw}2Z*~q4eyix96 z2Fyh9o)tjsq<25w$KpL_Y|k7v-M!l+J}zHsvRejuC?Gsfk9e?DZ9*|h-r9qHiH4H` zuG?y^*bu?RI4zuJyVCB~?OwAZk3bf-Ql{4<kYJ}4pK7idj-!_PSO7L>3Cs@S%~BNg zlZDCNQ6Yn8KC~&NJaM@6(cduDEZW|hZvI~}86_7m00lI75l|PBj?o-{d2YJ1n2w?M z_rPIRME9}y&q+;tsPqQlD-Z)?m(fYSbEeMJ_#p(+zq}d3Rqohh_zebx$ngs+yYBM9 zH5r~>@SjVWW&x53V2MN8f~KmU{%~6g%{_s}r=P7adPVejzC;`A)lBl93(nI3J}gBV zV1BhY_r=Bh?8|7)l_&{n*8-RR{$B~tsFPC-#zMU7&Gw}Dtr?UtL>TQAv8y#U#!n=W z%CeT3)E(wVW>~CWVwK`~$ZYiGhrgj!ccYm#)`!<_8i+&EQ99HiJM!cWGQr@D2omSY zLN4fm@vjfvO;p!pE*^H-G~)G5jq~_z9Ci)ZsrvI;bA0xAzZeWgO%F6_^s<LRFGhdc z$+C%jD<67mSxfWU`T_yNEOflI*fZX92`naTM=n#arEPo==CVNvp9|6{pfjJ?{;JJX zyQDqcI4pITZpL8>UMwu9)V$uX-*i@lyzX9`BEDrCv;~*_oK1&!GJCRNSJ9aBoC&ZF ztzGdr#l`74C0gZBh3FbQ^;xT%->mB=odKrbh9iLVztQlL)ad_|^drZ8`df9SCqSCW zHFpREX1<QCs@gRlj4Ida$~G#>5$lCNL#9A4Uyh1OQ0e9J)a|!*4!G+ieJHMf6SwYC z?R5{}`LH(Mn~!do0R$EvA=VNQCTYz>70Sr1u+YNpbO(L7+Cke6Z?kuMoi%<WG4=o1 zN0;m>bKWm^(FhO;h&@OL;YztCPs7_OTdw_uC&$x=X@~?DaW(ip?9rpAwlK}$LH*b5 zKgVG;;t8P`C*kKwF99R-o1$5os+}Y{U2w2%<ci%Joh7SghYwAAfm|rD2U=^jxoLBC zoWfTdd4TXPex>pP9#cZo7s?Y1osxj-@GsW0-z<1Di`lScc=VsCC%wBVxjrmelsP38 zk(E`Ppx64cY*}n`_twJ3kvPT9!@#9HSxcA_(<hQnP)-K>P}G9x>wZf`dXj=?4ZWEJ zKr2*5zvv=r6STFvmoK(dMRWEEmejk`%yys7me4>sSp>Dn_c!B1B1j*9MvARdop(aA z7!E5hUS%hC!cAoFgvd!KyAUhzYnDKx7`#T=yXVPvD!-KrcKdXsa&CCIb7gc=<+DH3 zc?uc9)>vF;4BL&UX%6`*LLcJJD|~lOee)2J`KOMeLypUI3(`z*1joNYx^*7|W(aaz zAF<4rnP?de!4)}2my;GgggShWy}VPJH43>IZ!a{w=Xt`hs`|{-lIXo@u4trpBo0l= zbr+Ll=h}NYdw<8i){tIu27Y1v!3|s;Al``<#xncZ%SUdwhw}pV5(ryiOqYaaVb}#U zHfI^dTP^YlMsB+(@$;lX`19@xKsXVmF)prb>h5q^#8?r-uO3IZK`b~tknpXqo(k=i zTn^%}Dcy!PGEVnRCj8;}6jfPq1(DXg;j&H%?rJuq@b`hpCWD?8xj3vopKwgrt-~9W z4EW>z@b!%!{GKWA>T&%QY<X**1+R4q&}<oQcNrG=*`oJto%+0j&dZtw>1`l)+!=eJ zcyu`_BsC`XsTUEUTr6iMZvT~%<oVL&b$ScfwIlK7#UCI#_)0%;4jqbNq&whj96lFT zD2B!JHeex|cm_5kQarZY)GtiSv_`S#DPg^$`35W2-8*?p=2Es*oWmOVEUE(c@aq=X z(UNyIUTv1w;~0O!1xAZ$84GIn!{t*r4gb6=M#$5Ws$du^I+y7V^7uDqGT*QXPKb4q zo^=!Sj&XLo+%<ySF?c(|W5q`(iLKgE*Fa@Ca(}Y-BJ%3t-~3QTIxO5=S`SxXZ^Rnj zH^wAms*Xzx+Hs%rtCP@+y6C>P)PXF5qEuYRr>lpuv(-{16x=c<WP>xZIQSv~)0b*w zvOJ7X)gu`c-Yhxr&X${qY1)W1F%dKE5<$bAFqsN%o|nLlMIUH9ihj_Lgm!}b8#&n2 z_VF>p^gP!~eKP&KfuaP>1KdY04Kh?i7+F`MyV7SK{UIXv@2R}J3vB#f-lyp0&$1i= z`HTJbYeEK$jbfgh7XD1}j}vQ$GY(exsHz~sF83w5leXVl-fwwHr@35+XKG7WAr%Oc z4<BW@TFl>Aaz|8kympkHqPW@sUTy_QLf!co`anjH9V996lkX}fJl>I@Wp;JId#<Q$ z6w0bUR-X4OTd~!+o}e3s%^e>9nYNM-+>TiD3K|#J5(Xc`@(tOrr0&1FaZ#-ss(yQf zb*9)2xJ-Ducfx0S#_NE4xXP`Av>RsA0ZwMt%wP3<Cd(>6g`6>WQ}e=yyEzvOh*rp7 zxnRG^AK{uzA0`*Q-Y~zhtU|e9$LI&Keg~(od|B#qxR-{E^w-;uB%CeD&ydy$R;yLz zd|o61tj`swk&!&-ViVL@hw`*(q!A}jBtJig-iVg69yWa_)`mKl16jMS0y32yJ(i;X zINo>>yjW3&iO!oBKWw(AU^#pvNmS59O4=9F;xE`HKYsd>2x4?Lpd|l3XX8oy^7B42 z$;0KIG~WTlkM}5q&}oFhW@)?7rNh*NOKH($azIN^SX>>?>1D@q<)anrY{VXhbK1sY zDH4(7h~8yZJ`ufA=NGSU;}J^hbo19vc{l^^{F~&tzgE63`^Y`)+I`;n4`P%-O+7Fm zo?HgiQOySGt!KQYQd&hNHm-@)DMG(4{GP{qUw!|gDQejQDzUxc2=b(@9i+_xx6q2& zwih5sG*S=RIEy=a_sH2&9h`P<Dy5jNNK*aM+%1j-sxk~L+N=>9q(uJXyx?PJJZ9XZ zg%`os8>PIqZl<N{_H`}Mb$1S8y0X^w{TB1@XCz;mS-(fm4r&w6PF}c+o(W<Fd%u-J z2laYC7NDs$Wm`1X0?A*7-^0bgT2GQ{R?LpPfFvi;$P*c>-#2VGbeAGatsEl>9lQ+R z8LmkIfds!efIJeeTU4E&t)Sqxk4F`k0eeqH*&;D&Vf-D39;?I$*1}k%U0=LQDP=;E z`+7tvdq$@nGJmM1W0R(H<k%p|S>K75qDkGp$f%qUr&#h~%|Ll)5T26$m!L~a5lIv& zhNSyxR|Zgp=Kh1g!rehi4yW@3?dwJF?LfE`RALj^cH~pa6c)oY-v0S8g=m=mUO^um zqw=zBr3Xd7zOasA_cdSQ%tVX`9<*t<gj&+_i3-_^{%Ty>UOCbcARzv*Pr6{@SnUIB zJfscSIAP#p*b>+`=>7zWT^#WtW<7_>Z$w{PnkNZdSz|4e%!i(w0f!H0*f^*s?`^2j zo@u678O|_XvPe0^f>Fd=VvnQl{8<q&xJp1#z%srcvLUFQo<^N}6<pH9I1Ik(C_aO^ znMf`KuQ2_!`u&9UH$ghp2-L9t=U6(1SvWOb?wpCeeUNt9)gUcP@CAuaug6Suk%taI z)Z_Ov5%;aOJ=kxz`;29=Kj#bW<G2y%;O21ZkRTN(;O<c={B1%sFk07Th)wtDAv4bS zr@-iIqNsOi8nSEE_im|qtszF?87n^e!0;#Oak@LulE_v@Cn2BUw2%%F`c}6mlB-Vm z=-E3kVfy_G{z3H?2Ffjugu&#+kw|0N8|~R0W8`<HxtD0k2cJW}4S9Iu>?Lxaz<4rd z?EvET?Uf~-Bgc(L0m{pdak}mDzuWBY%!jZ$h7We5al?3M8I?q9t}R1>qH{A&R<#KW zOjkHPV>mol_X!Fq#rw4D>d2R=*PNQa>Xx+0NDV7EdUzfJj)<#%zi^lP0wD;>3s!?) zXy`m3IdPI9L{e+@b86cUM~tjArrV%dTC7W1vCikLTsZodk+?2-S!N0z45jH={AeWS z8(9)2(K(1|)BRLQMdB56{G?5n2zO>!@9~n_xPwBy9;33D7wQCvr1xXkG6<`qI_Mpf z471O|w05-raPpCL-;unp)OpzcMGmrYQc|~0@70^Dy9woyBd+8llMLJ6jz}@0ARX+o zJ{F;lw2h>)PI!+>R5;i6LskAW8X6UI{98#+4a3v^gW_VO?hoOoHM?BfZcEP$gy_5E z`jl~M6TT*X7I1_OzgMLUS(6u3!^$3i?(Pp=;=5Wl1X6w7q`N8jD3T#H{%sHXMDg9t z3I2#gdBW^x>_4Z0pNYfRI*NZfdh9(h7V|e&16KD`ec?jW2GoZ)X7~bMMy2{YQ|j$N z?RpGR^^cc#o=^32I5Gw=P1E{*seGRx&DHF^D~`JW+Qhn#;9`2GG7jrmyzxIUSq<$r zQv-^EB6`dU98qHfq_3|mgGM2$7{?s1yIr-?>v0AnpvjDTu>Qy1^a9PMZ$<nSCy{l) z4kx=#wjl(LlOzTUR_l^S&pxaSky86ZcqQgI)1+*XY===CjMhYm8mSw-Zvh`JT+)Vi zVG}t(TbJ%FomlgbUq@jYcRZ_=h9D?9qbw){(S+OD01%k3cE`4Eg5-W7mlpf8(h(nj zrX~A*%KzgxRdy7E<hhrQQFDLc1)*V-Dmu0fk1FzpGNldH#rm*qWYoos$NVixfTg_4 zVaYF?Sx_*Oi;w<&zGejfjo|B7Cl9ga!A$qi#$KeCB;G22`)oMNnVnO)lR}i15~iNZ zyY%uz0jcGKAZ4HT9^qH=v-e%;_r5&z@kfg5_ejs~e_5VCB$>TOx#IH$M};3fdZak0 zj&j2gW=iX#P>(f8qm22pH9y#V9WlAnu*0cMO*487GdxT&uG1D~uG{BH{RIMt$tQ$p zmv!)3IdY!C43?BxnO+_9s?7a3<~xKz+uPz8*#sF<RDV7A^FmSTNk7Jw*oDWbUmT{; zn@y&Es=z0WeFl^IaE!5iF2b{!Y(v#^Y_CTMBYA9|8oQx)gP`+=mRY96wEkJAu!BYT z0MV58HYo3Ck(uIT55e<M<!Xb`24S{rqC+U+8F+&{(F?1H3^%tU@@J3o1)uwNt!ZyS z5BwJmd_#BeEcfu?4h&ulANCfZ$|G_Jr@by6cX`n37|z!XqQ6?6hVL@oUc)gC$87&D zPXFiTC;uiqUqM-c4k^%2WnJ&^t~*Hcr|A<)czhNFzyLz%dYT8L8}8v##+Ufl-3#B` zapiWu-P9#K8O$SWIF;;-t5>7&op@Y@Jn;$$rwVOVmDvC;JVKsW9(HIPRn#0TeY^Dm zwRa5CScHN{U>Ld}ZjXA%)Nn?{Q6kSl7-;+h28_IR?DYXSUhbpZU&L8WfI#<S>W9sd zE+Cx2n*^7E6$d=oInCvfOQ(`fC%ezx7!%$VnQQ{FUS`j#U~mgI_KfdaxLepxEJpD1 zKmY`R2@&3`flXuyEP}u&!eg<_Xu_yoV;(dTD-A(U+;QC-PpI~%<L5pXjxdwd{fc1_ z8Xv}Avy4l^!*nO-pnGvWXn>I_74dveWj(|?O<0%W0(Ncg{h2H%y76>eknvmN4+}s` zYk@1t?PZFnQ!e!XQ)ysaNHe1@&r2N~Nj+Zd$ptv02dM(6G^X6wnm->ftXh|9Hi6$R zbB#`Vx8t-^m-?nqVe@#zZmlMr1{kD7)rZXfdWEWI4VV`UkN^Y_*oK4S3<=!*tKWZy zBR3X|^SeJ>u|;J&5t>;S2A)8rct@Q$y^@kIJ;tMmab6w69A0Rbbe$BpEUPlQn;`J? zVo(UW!6$PN1zoQTFmsi2${-gQudL;c{RqAiLP`!o@F)f)MskMe54!AT=%C?=^|qA? zAuRT<a7FRZgKhnKOhrqzx>hho+GSmYsx96Aa>`p@7w90J0)bBXg+J^-RZE)iE}AZn zX&@RQqGFoH;^TVJNq$O@X7mb$FwY;wkzB7+Ki8o4N12X+S_8Z;V{l5mcGsY2#<(-m z{_n@}{o8~bdcjY|{5xOQu81f!avs5&mwrd}`yifjQEj^K=gV+f$bun^`|62XdyJmw zC#ol*uGAKL*Vqv+{*SG#SO~`;yKa6JWU8KK+y9OUMzk%3YCEGt2i|HQukwAeBkmt4 zgxKuMb>jt&jO<Lu#w%PO0@%~<tW0tWi;)S;7cj{o))3uq{!<!Qff#v@Z8mG}`3+<% z%Psj$sUpMaArXKP<;v9uYGl0Z80u}U9YP_Xj-Rj>)r&ifkD#FLGx|_aogxa$#ao#Z z<A|_!Qjh?fGy#4G`%ud<1V?((k!B|*XamdO*<jRz9`aDp2CoYSJ}zO*2_F1m;@E#; zFSMM4$e74gXCLah(x!h;{!LNiLQe=!G)uSqhfS8o5n1LgA+*1LM7!b!)}_Q{$Af_z z7oLEL`7kw)^!McZ&plA&M9C@Fqd8G+;Y#a&xR0O<@;`zApLFfBK{7YE<|xD?+6iN? z?&jyHSHY}t@gK)PAntY2;QfrGTdI^P&a2ok?i(W=@IKF<64uD4xHA2<%ektKdz9MC zQ1n+(`lC9w{c)qr(WCk9`{{j-bM1bFlnd7%-a@5KlJIS;vn{DGeMU_0p`G?$>mm4} z`Ui$`LLwn*mE737rIb7VJWk2lWe0>CQ{`$ulk_hCd+54h?%Q?Ot9D_{vf>hyx>0_d zp450zBm$B0N9DuWU6KI4Y2-=evZ`o@G4J`3$Yhpd-m{_M?GzM3eYVjXcT|x0;OdJm zTIdBy)}md_a?R-da1p^_B|uObFFEMLYnCyUcKl26QF>)i3Ed;r_LIaALFoj05q#>N zJIAnqh);ox$hTf<i?O*Eb-xVYP7ge;F`#;spUIsXCDha%nwyhrA~zujS5<bQGwmW2 z^!3ZNfX^HeYj<bD*FQL&FKlwb>ymz7m%mm1fZ41vBQ}yVQnjS><)09RVaN5Em=8i) zj|kNY0>c_%!8x<IMi;`myVfb2Lnhw2S+fS05#3Q?coEkdhVJyW6s7KWooR3{tVVJ9 zKtbU%tl@Ht{&)%l^YF`iWV4#(!^k?MlYR#8wn*Y0)H7YHxa&ZNf~nTYv5=5@Zot>` z(218pS{L}jE$N;d?VV~4<3_N>VT!;vgzgc1Bcr6k3`36ZHZ&fjoa_=m)g$CP+KB61 zSVR=R07ko8u)}&<jzmg(s`l1w%)R|8xVuydbF&WQdLzA`1~eg12xfiX$_Wz*m|R{` zphrtc{RmAtXGh}N8Nv{`+tUAz+Wvd&k%(j`4oz9_*gp$!aj}2b{ti|>rB5|!b`%>g zEfr=G%7zSN=RnHs6zA2)RaY(gduf^i-Cm>9qd0+Q)3L^XE-jzSNEu+<+8uQ;D=%UL z;+zYgf!_A?I&8f-Jfl=C7nSno7RW}0e|TkB{YpK={KtC_XZ`O`A5{ppX}hFyLSf{H zPHEW-4USW}*)ARmBR^T9KYV~FWnksVwG?h(#r<Z%hi&-X#?+P!wx5HCsY~GDJuy_+ zU1q-oOu(A<-+y|ePGa+Gc$ky{t@+r$)D$vmu$u6f#Prc$X3dH8E2B?7kGxiG=X+)x zw@zVu#h^dsuFUR5u4|jd2^BK|(pQ*CEvd!#2N9%Qx=meUU%$|~Htu}u?XYV%lCkqs z0(vf~rC&*P)~c#P>L-Y;R=#k!Xj?NK&N-)sc>lJVkO@$iVo!9LRw2&tGN?>@49F0E z0u>2Kw3V+uh|k%Idcye8yhlh?zw#k?A*#}qNa~y~;;X2^QH-Brg?QeJv{su>JWuD2 z3K{@$LbM*dkL@-06Fr}7{H_S0)pUI7v4xi~*736%cjSHhBIs$uqFO;bDo>TEq3RUX zR%!)*F*R%P)PR>tI}t{9bmL!^PQ7yID<2*|^r|D>&`5!X`iBs?`B~R7PTKsluw;s* zdOMu7(S$zAx{!HwTs2gnsF_q)1-<-e=+#*?_yvvPNs!fd>=k&dQD04_i!1SXcBZCk z(h`)R?RPD}NVp-vd*Zf9w6rWbbK0<Ol6727IQwEo^8WNXcl%9c8XLu&ZIMye0+zg% zgHeL<K6I^by2>@@DssA7ExBk=JI5r#(1STA9ToeG!;}T%lSLHZZG8fpWW$t*4C|=5 zXP&i-LYLmB)ytCkZ(eF`R_u`b@%+HF%zt@yV*PO44fNXoo}<=%^mg5abx?*dmS4|& zxJ3JEdd(_yxc|;&exeO(1Sej4XU^ZygGc-vAHYzzyctx|&o(soLE2#ie1b9TIe=k! z2Q@w5eRdR63lF<#K$>H#TYl{4r`x~$>-t?<9(^z5;kNO~zTtH~KChP>9AS!w<2$k2 z^Tn!CR_TGKM%qXhLSn|=7cZ3n;;(G*ti~8mXjjeWo(>zu=G9YjlqrzTWm3FM(LxDV zbvzB*inlkxOejvh*13E$6V-+3q-|>Hq11lgk8o*BShQzZ{FvS8t#*Z<|C4xE-7*a( zWD?v;*L+3rt{~Va$)`@TOz`ZkSwQJ#j^rHz(7DfYInAJ7D@klL_-ZzSIhKjMF{4D~ zPhQ!mSLrY6l|9=x)Xe5{oN+lGyIRXc?>5jy&O+Ro9KV5qWfZW*oUn@Q9O&+SU5*H( z4AS|OZB45JGp3JN)g|llCrmUxlb|-U^|pQADd+#UUOFf46~?S<(I8kjA)nJo=XqtB z7lys4mq%e5GX|<vwB12gB0Lk7U>sga41to7!3YHAG@*qUBQd~|IHUKX$U6TyM~b}a zxF=CS(IKD7_OJlC2nG$jZF$#O{k!LJqu}!Hl2*xQCzZl(#4)J)_x$1GQ8OkwA^e(` ztZu{Xs3~zfjyKK1B96fY>MUPMJrXR|Fy8NuytnzwYRy@8`39tO2mk9Pkr(D5`upXX zF-w2(BPnFL9ee;-i>c0-UP9w;V$cQ!=$F5goD^ixoZTulOsGmjNt>8IlXbLl*kyl0 zc8$duA}(QM$V4liTNGzhNh^S}Me`QH6o0@FgTeD|pM2Bo-}Y}js}8KuBAk{1f@UHy zOjBgx>Gw9_RJ{U9>LgYTZ*;omgq2JF1gt;l%fQvTe!s>X4dyHKvH#Yjve@g!O^{>r z&X)fS$rHc-?*x`Z>ISD~0*!vHb7w9?@dbCcgy*K&6L)k-z*!4hHD|N?>^GI(r@Ph~ zkEcUKG#{i3<6!(1fn;F+zY)nK#UO{0`xcLnRsI7x%J%%bmNoVn;g&ag`P4KogLd+) zl%F))eZzilKR)^@lM*ZgS+XsoYPWON6Z#ZXL#vtk-A)dO39tet(zoy+Rbxy!At1RQ zPB&bN_qTh8*(U+y{{o?k{s=q|M{xG6bDK<qI#?$u4MWan8<eFuikm)|S1*I~=utYU zN(0SKGeso7DPsMfVuaKLe__s1a^f_Q8D~iO2B2|l>g<2)&%R=)r^$ws`nw-}hqAnP zD`k+C`C$A^smVzrqTwLa)Md80-K8NGY2FM|fHq68YEkgCRZ*<G2c}9;9@&O6xLRJ| zfUP;(bM>fp+TcQvIj)v8$arcw2XE@JuG5eZwb*Q@HiHhezYt!=9sBsT6&owM$sveA zP<*w)Fq{iA*QISF7%odlJ6U3tkD1+NC&=)|4LJwhN+t7;Yt=0eiWj<5_H8G!9{|d` z8C_qW2(G&X3?_(}Lix{qhjc#67&WN2mYv68z`8m0c{NP<C^_bw)Mg<Dkkj}6a}ulu ze302(fbn$H0AI~QC}Wqey=YhMCRB7O#gHe>Lty;$y~N7PBp(28^%!2~gtr^Sy&dkE zHHs1-!ssRB|E;Y4J5jkqpa=xLbUsn51wwbF*Me!0TMq3^NJgZFw)MASjZ4c?XzVTc z7FRxG&`FEt9C~W6{CV1useBA1urjZGe<+<wSEE2^^=Df$_S(C`bqfp-uc$=2Csza} zaJ7^GNMx4dBsZl4TP!&J${n0EVD)L`V1A0=*pxCM=Y)2+hDlNx*+)QAzixMn%ZQrZ z;M?kz>A)vguou~c7Pj=JN08=WIDQ4)H6KMc+@y)7h{qKAaa8~x;aF<A`w%mtt;QhE zg2r@Vz;?+pObCyjC!ieaXt=(0VE=R1%=Y2nn5B)Ln}9G~jA>|i>|F@Hu`Puux>BsD z2ypWI0Hg@PZ-3@yOVXf`?xWxxU+%AsAm9!w*c{aLjy*u751s99>USp)n)(2Yf4r=d za*r<8<^-_|KVrRsL58~O<A&eyn=*H4z#Pw^ys_)})dD^^9g`d;Nt5J{&Uq>P2sk07 z&4A=zaLqjwGmBvd+;neR{Wbw&wtk1x_r*O#Ef4AhOt0s<%kiAc&enFd@cpF>#zmCQ za{;;U#^_hMEsxS+a6wj%v1n~8xNDxlC|#?pD5?NJUEPTV09@0z0lRb}u4CJQk>&Q4 zC_y14+=Ns32sxJ^shuR;rBr@a<@=BbOHS;M^yF?Wf#nx~fnQ3I-{dz7LK6(O7zdU> zKT}hjAisIz+Tpwj>cIE|`fhb&68#v=T%a~*PBq#|gM?R--^$fq{d~+J=KqsFu6%*2 z5n8UiWcUMt?1m@z=Ftp}H9`<s_*&tQEME3{1tj{>8pq%3e#UoRSN#1xU<L*^Q=#(; zHW1BYTo#M?_8ZBp0;NFZ2R%7fo7mVtw^ePgKW)=s$<Vk7+sdkG!T^S*3|TWclm{;* zr+X<Ga`nUQ^#`=YIhSKMm)w?|dpk~|9eB$Tp!^{0xZfs55pieTJclliLa_nYcjH$< zB_%F|IDJuOa$a3<sM+W%EJieAg{56>dL8TxI`ByW$Y8UPrNYc<>LfcBd(9>vN_hlP zW#2LHo)2mzFT9eZw&9nb=9J7!4)qG4Zef`T&-jA9HM#L|)xp{~rxZ{c7~}ld(gs5_ zrWF3%7A1`e#MVA?uj?L2isS>cnMN(r#UBeU*;tE0`Tv9{;BlPJY|u^J4_EzW5ycrn z*f6CosOCl{s4}~XX?Tk|4ZRY43C7j){g=`looF50pf_6%40saIn7r{VYHI4jq9Wyi z{;)9R06EOo$or`d|HRFz`sx|WJ}1UH-qDp%fRvdudFXiX!RQxW2pZWUy0Pair;g$A zstUX+Z|oH9)&+d@E%d(IdTc@02HFr19^I5|X#GHaLZyP(3Dy|_$&~bN2uG2fe9`9$ zo_|$OW(UAC@2QV04=$f&E5-P6<GU+M=0VwnBR;4A9;1D?n8eAo(zT-e5l#K{RIWWT zahS46jCB0?po=+y@lx#9n{MHkMbw9daIM&6mU)FBp^-UF$LII>ahQKUgBbMiVVs{j zkTD7CQlf*eE>}4+c8uEH$%Dgn`z`NKJ7#f0Q%7o|*vD)wc4<wm6QYyv1tZH7EZEZS z4#nNj%K{YFW%hiqLFoHwv~)dL%{Dr~Yp0w3fd>3zO+%=GJHgW&z8HG<d)2-e&c+%) z#lwqXf9B6JXBK>#?QroaB%-L3uMp}=?WRLLoCo>6Bo-q0k{ux%y{^;!augy!7K-LR zheFAd|IPaj34he%VNjdbdX0#BD4tqcSW%JwGruV_Q{4}<5G*W2-yekr8uWr@zE*lB zB;MYHT%01o_Ae?}WS8owIC$=%XR-A}_-Y<rS<x=X6}J=q&e87gzB#G3^85T&74}5% zZl1*ISWZP<877(0Z1uqx(zn))-&E{jbi||~?R@wIC(d}pw@4E!Vnc!Vt^^h3w8SRj zz{GyfBeAN9RM(wV_6Q8{Brz1hMc>45G7zqk7W8gV@(p#oa=8Qg0tl=hzc98q_|Q#H zG7h+a8H_+`O#xG(#q!4Tf>E|!Qb7+fW4V6cjC375xsk|M<(z1c)BmbYVN9ggp^X<* zf!+DK<EQg|)3Uxa{ZFJl`Sc0ThsJFu-gJ}?V`d`x36hg$;6M3`uV97&D>^1jc-sR! z*LxOnzwCT!*zWFTHzp2rsfPRkYrVrswn<K6-`)xAZ0Bx|B#3;tXKQJz`X6Zu#un}I z4V=32iJ}q)u$LoZj_%$2tg_RLgB0-R^NBByh0t|DdaN()>X1E`-8U{El}{=GojVRy zPySu&;mB|0Puxd2ULP3$1zzYsa|JzQY;z77a^r(7h@)*ykr7(yA+^R;^@@0DC->K{ zhRMcH+idL^WSgRVH_v;ra<t6wpRNh0;i<NrO!@mopHw7RVCf5@ORx!z8P`l_LCU9r z!*fBQ<HuGkBs`(!uSs@X2%X^(gF|^DX$tNuY-um@zpaH#-u!^`5AYgzg}T1opEsdq z(C}--jC7W)=xKElKVLq|xqDl5-oEYPj|gI5F!a>~cE=}i18YN6T<yG)QB$2<UQuy= zenF|d!HXi_(!#>RVlv@9G-5+)0c_+yGNKCRRp}2vR_6RKv=K3qMzvg&ItCc9C^lRG zQMU6mM^JfOwE4}lCm(h%LIoJ*ESY$By*7C!FJN5>4@70rb$ItS8l<legZjH@+YLuv zlQ4IA%}1||8x3x_4m!;CzyVIWbrhJ9hdFN*3(pw2J+L|ieG1V&FLp+bVbTd@jWmp@ zp!VVwF*dhy%*+XS;0x^)Ha4aCjlgN2P)m7W!om!BA9tG^anL1Wef}8XRa@Lb&nq_A zhV`n;1Dn*16JU_2k&cS{({qdvG7~tO;LY`W0~b;>VBTZ?J^4t57jXZx7M{`yuMNKR zVBCOlebld;`K;&;^H(lp4sjDo9SAZ8hP#`9i_n+`hxpgq7JzE^q^MD4Bbl0l{H5S9 zJj^ihzj^i($?YIL)LwW>)7R;wq!OMcq9ALb#BfTHoln2X$%RM`VHks&{-4Gli8%I0 zHb)~~zpk%G5ctq#RHl|oIk^%t<FpTJV~lQ3=Z<l4T$4%;p!l?B1URLr3a{=ZRs^Q` zc05T(u!Dn|TCBUo{fV{7x)VBiK16w6-%}<}pGlcloeOFXne!`oa|C<sZuX=M_IPT5 zDKtF!?qOJ^nY2fV`~b)^LjZT-H^GX+-J&P2Qa7Q&CO|tXQ_C(O_@431$HUi0cU6we z-ECJRZOoVtkDX~Fkz&)7CcvpMul8>+b9W=-=j;2xyyD<uAZA!T)Mk=Zzc@-vGK^{t zcPU_wH}{5+!kaPIWo8ak`@$YdvD1X@C$S2GB4p#%*=)Xl{r04+u#1cJf8Sz^-1p$3 z74rgDOgBKR#{+m)JR967Ted9*lP7c2`EVOv1JQ>vv_3htH`5<oOilU=KL*e(T>0EX zSngo*(QU-wAe2jv4<wQ}!I6#f;R-+ki@{j}*}=$GV3gsnKLyfa4A~)>a`Fyg@E@pu zgJ(-~UxTbGA#c}Q4-Yl<3Mh%{rUz`zMEvQAMAcLK)p?tpAzpb+0-Q$2u?fGgFWqYz zt@(0rtH#Y<dxi9-=3(-hFF+wk^(CG|0z<qFb%R2P#V(g5gOnjXNs*Sjts%9XN975s z`Akr^P8>jc&L?{RC64JcHO%}Q-Z{6_Komko@|Dv2B3Pq|_u!IT6<Sya$S68SmvDC& zqe>2@pY$j(b`ThI1a_U&&AG344N!-=0sA)+!CwVE&8&U86C2dHWd2^uFuN}G!7cl= z)w|N}pe-mU==k{fS!$_OAIZ|rd7EMLGC&zBR;iO$RG7bbj2IDFuqCl4n4OK(_q1DU z@qW3Cu>vse$(HJS`D_(h^6MY1VI}2)ke(ELus}$PTl-S;U40E$m<o+}+%#f`Jv-`o zXv>!{ck_Ms_1E<#Fz?-%Z`d+Q%1aXNW`tWe{-6~*D*^N2LdtuC`~G|azRMs|`MP^^ zp0u4=&MylPr?NarFt}K`o)St2e#+UN!D?()H;>^SK3v}*G~2~0+D1@t#|VYQj#Bb; znJ&v3S$nvs4o=bIVmIDBaVA`G_K~NcUT!r38d-0g<oYD-+gJlTve&+h9D9wOVFO4+ z*pM!q)Q)UehEE+nkYQ#RPfnXt_27FTWK;xznXR;4q995;AjvZ%K=)Yurk7sI{D6UM zjCK-}V)ikj%Kuk#2^ns_s)t>AV(Be#Yis^VACJAhW;pn>H}W*z)`Zi$|A$3tsbZeQ zDW)qMC=pa@Fm7L$vA)>mky@HrRrMH0!teySLD>jCS9w0(*B4nMllvbU0PFR}0N@(i z@Y(wzZ5Qkd7>{vg7LQNqKEcj04c?$l6K^=?^uGu))$zL!2>KN@#}Ra}7%i3k9DE?7 zQ6_!uvM+r_$2M`>UncfguJ41r^>Ul}rpmA>o3ZdLd`|HgW?whvAdhOcJBOhIlBIlk zg)|R2u~JCuyii<k&JKbAqTeU!e672Y_#XF(UEnlo>4D`tsuf;HN58Vzwej~LsO9On zK5K5hLEO5O4rJ3XL4ppFPbYD9bF$|Cv-)9Hk&SywURT8*M&C*so$jqjY;03v*{j!l zy(C8TJq5GAZL9bpo9xJz6@@0_w;pB7d+ynAd`8)It8A(#*NQl|B;MO<r(GPwL&t7D zlff8JC|X<VeEIVJ{d+kbozyp4^d#T^RBkNIH;V|wiG4X9b!a8GABy^X;IqA+TogrH zFuKLAtXx!B6lf4Y7dRKF!flVXwSr3Pgyls{iT@K)PfMYKumiePAvZcI82Dw5G0W#A zS)|S6ISk85K(ce?3O834_=u*4`WV6OR3`nZk~BjDN|8lmwRXbNH1zqhya_bTOFeXn zJqGcMjwwF#{yB6P!sVNNMbH=b0thO|Z<0F_$-YAVF2#RU$7!(i21I5==AQHPdOna& zA$>;WB>@WXz+L}SABg5d7TCuK5?Vg;y-?}Ye+$2pG^P5I*bh7IxhMrac*VS%sod+n zxd*;Vfg@v2AG<5A%C60xmj~7BliUPYrB&5X!p9p4Q-N=WY#(D<z%68a>P$pbrY)k+ z@T3Px3BV4E>_5mEIX?2Y`zDZrvnb_bbwa4k4p}k@eex@)gur3t;3YmC$z{pw4>{Oa z=je_X8$lE?W1U-h2m*}m5F;|%1hxKRak=du{k<wGVb;Y6Ve;cm9tRsII|oNmzHLrZ zcD8(8k#_C=yMy^2kBj;7oB>ptl<KDgp9U~GX{Dzq;Pum|B{4Z1>;Zq*#0X_F(X|h) zT&t*mtuVuxp88J`9E3u=chBg$?C>o!7H$bduIgiuNhj^+IbxaG1noJmcto!sn<xMS z56XDyXU@FCmHFQ7)e*FndOa||cq9pX(Dkmv2j?sGgK`(Td4=3qSkE%|<Wg6p@+d~l zHHTw#Sj@Tc@k6Cnc*|3YubTwb{b(7<JO?&m?_2|@s-3-H=6yZ@p#+eW0WYzyGUT-J z{@k;Nl`cJPA;(&m^`^Q9R$Yc#D+NQMgJ(jEROMytB8qTPbmEf8!-Hjy=qs;6(dvX& z@S$Dj5P&;*4~f%cC0WSTmdC*}-n+q{Wu0Aaf2X_qm90|u#PR}wCNN~=IM{bC!;W>} zcq!B<E@$fzbMrg3KL_j0;GdK>LKO7Z9@VeI)rzi(^44H%Qi|XdC~HxaL~dJAZgi$` zYlbk2wi|m$6?40H%FcqI&SjT*Owfp4Naw$0lI`ij2#=sL3Yg4^{MxRG=2X{w_pW68 zy*>Qf=OH1>vPSMAhlSn7{lYiOMYh(@dDuxvelY7;TNnJy`gt7=y>WHAwtP4`bz305 z{jdow`_%}w?_$8x_g8e93?pU){J@Fo@+jdP@(x=w9E@pFid!eR>2vqyl{%oO^w~>2 zTG@V_<4U@03JB2M^IOO!d_gc5J!p3QDfszz6jt=utUn^c*?$5*a#OepWOVhh3AFEg zlyd&wmR}uOv^Qca8*F@MVohbrg~{cc+q-$pJi^Og{&8*{n&v++?6y@0-^_Owz1M}# zF#!=r&_sX*W=JG#flZ#hg#=;56MpXXyk<VfD8J7Ok{#XMkXCnoKqNBv)!E?}!?FA# zpNjn$Y=h#)Z#v});1Ksw?URvC{ue~9p4#$LQUB(ni@E8uQKfO!xZJYoOBV*$Thg}S zL}6{gl|c5=O;6mb^?xxA*jXV;mDnsf`1tW7?ql3=Wu<;;DwLk?+qXI6v9RR$@vI&M zw?Th%GsmZfF{IaXKi{9>KTQn`Qoku$9>ct@D)*K|(mwyIQ2<x}X)@oeGxc^vP!sb1 zyYpc__3vVIEg#dai|gv@va<uwwJO<FKYunA6qv2`rzmraEo3S5RhX|04duwmso%4v zTxxy!jItHn{ll^`(C2?xueaqum9yCLJ_^d|i}l}@C+;#)>JCN=BJ40@prfOs{q7xm zR(5)NQ%;T};@BnLAntdO)>4JJxwwI%afW0B=J{9R_B;br#N)vfy^%Fi%9a<r7*z@0 z?Xj)96_$=Y*?-UKKb_hK(sfTF`5PR((Voi61NA3jf$0FUwYAvlDl){Cg^`n-CKMPr z5Fd|&9)$6<X{M>e<=|@YIpg=AbHOdXR+)C1Bmd>b{R{Zt&rg8AMfBOYfMq2n>Mke8 zVPRp9A3qL2Q>?GYZGMt#Y1t@k*xn`AA}iHao1J*a_Kb~_b8r9#<6-OV2TtxdMB=tA zQKJw#YSJ_8|8w@NVh9wJhELon=h2@FF8TTWYxzh@Wq6uEM{k;{qM>CwM@daPW)43D zNJUm%o0n7VC##gZ_Ffnroq4GTI+WWe34nR#Q{e_S9e$eCjQ@=<ofBl#+dkoN!4i0x zQ(rH(W9#bU<CAPWJj7*h{am-6e`ES1tiF-*@`^%4m|}g+NrH=ol%%$*3P(aI@zXQ3 zEmVu>KRK%xl-%{AyTyz%jZd|kzMDU?oTa-(=BIx9@4E1E7$Dr#w!ytcp1&rh918I4 zZ7*(M7BRkHUjE(=x9AS4k*VHmZw1W!g5T8%w9JS<ui=GC0In0t0lO&PxFyJ*u`R$f z3f}tXzkyy~{;Ajn!#7n0gS?LKm8R=iN>fs-r-F<|;M%JPP`3fD4Trjn5g1Qv=^Jew zZS91ZWDd-uqlG_5|IA`us~otr1m2FUmnQP~1{Mx)1Y9STt8}lMis%1SG3Uevo)}tA zM!a>#HiZhrbtlxiw>;z3#PPS;I{8Wuk@^MK@9wA4>rcR@mqHH0HTKjTJP(OXLA=7$ z?^D~fDNGq5QbCirx}A3}H?kllL^F<@ra6!ZlifDgeBu8FKM^xm|8e+?#sa~$sgI0| z%-u|z6xi^vgAM!P(d}E~da;jCj$57l{fGl*2E}X;2U}Y*65K}7y6?lsu+itv<AbcA znNle9KksN=K6szN;12^IX*TaYtRrrWeZ%rVDo*%lGu^g}fGHX_|HW5F&CKrdo6E4G zvvB$cS;enkznZ-0d(8AW>}!~BKIHCTNN5VnbLoe&ZN3lG$oSH6Lhc%9A`M*S%wHGr zqf^UrJqlN5M+7d051Um%;-@90rKN@Yi9Xk}<MC}>b0w3r&nk>oA4i*-6y#N?CWm9i zS%><BRAoT8H6DN_@pqwC+ee(^`q{uSQ8M}dz=mFNlbW}Or435jWx(SiR(GSJCt?F@ zzrM*eROR&syQ`$vDXw}(7x5LCv>(Hwmw+8bFN~!qUhf54tQX|3>Sop0gwVUbrLW8^ z*9wbLDh1kpeS<OQy`&Bqi-Lg^YNU)-rJ@zil8Bkm#8i=L;b~z&mn?#$ciPZ({M`au z_T|1e_mM<zqu%Ed<(g=e@vobi*3iDhVGJO8d3?9N)HP=gfA4DHbgiWfeYp}P1415p zn@v@2px1|QTJxZh$ip%;awC|*C&Y{FInnbtVnoU{mr5LX*lQ(SvHd&|mH5p|A?#{n zo5?_SJ*>$*n;6dKEcNdDvhE6Vb+O!_WeKg7s$Fz=#<BhHkIN@8nWky4+GY~B#NOk` zUVkRKPl+~6mdvzn;cDxzqiLQflWQR+PQIx{Stjl=g*!II%5{gSkk(WB{LZG0^!|>r z`lcmyU}8jf_H3VDPcAOx)R&teJ}KX|xp&Xw^)O<CooP=tHw!%^)A&e?gY3Tk$HH{W zG)k(K!o!!*@#Xp}SNW|)ghqj;4x8hb4{lsUvXASO%R*tGi?c-2sIZj#pCt*$kEuMh zKQl-I-LXJy9-hBVV?$}@Zq6AUVMt3;Sj)fA;V4RfH+ExI4z2O$Y4&OVm^_c#|K$hu zxjCynJ?$kyFdoBt`+F6l@AcW}RUj)P-3dmeEWhni$>Tgq{BZ)4djh=<<s_S8sQ@U6 z;VW7(kWz*8Dt6H^1vBPYwtsy?`UM~8%4?#~k;8dTGj+Y?F{C4&=vc44O~ra_L>vEm zT`M~N(&j;huDQ>s`PeDH<|@gL=Xi)&?3+qrlqR{m?5dNfF$Y60V4_mTEUqXmw?Rd( z*(b4={y`(R^mb5N?~xvHPo2^#zRX7sCcA{MyA&Ny*cCkYIGmrvQ(uSuK#&KGu%8HG zW+;}g5xgOxdgST#hI8(t8kYBOqg9pW^-nC^_7R)Q2{?zaKqAL^T<nUw9s;i|o83uT z=C-S%d-ace`M@?$)J}TjKb3zt7U@z0Khi@zkZquv@yhBwNLZ~rf}60X8QBJt+H=#h zEJKx<BNUCI&pn2oC%lU;WbagmomrjeF}XnM`RM)U@6iFa8Wv=Ml=V15l-=;Tr^jH? zv7Jv+tUGp;%$5DFw3Br1hA#Z~l6ksmEBkl5j=%Grly&>F{9CJ6hOE!OYO%U-!_Sin z>9A|-Pp?X~A|pAY8JN(J;!k7}N=O%i=>M)w4l$*;>ME4TL+bQu`|7Ec&}ovyhy4Ao z-t0jKlb~nEJhq>u`E}{>R~E?+{Q5btrY_lzNqA%?ir%jq{T$D8|NZtc&{4QTl}9G- zk(|&RNR#sjFhN_eF~LUt2RH3YL-URjW4}jBFD26kb)sNc2W{zBD?7gwk}Nq?gyW{K zcm2R8KRGn3>_>7>ipV0_b7^HDncRxYk2`4ndr^$J#wuFrgyio}wY4)YnX^t{IY(y3 z;;V&)C;H5H1Al?gA+Ih4Mhqh4_GN}(U&Oo=2SLGIXG|c|!m6{YiDQ`2mMvz!Ycp;0 zm2ldy{>JpGS2X3(r*(C7YFe3T?_4tJe~t$6zHq)bYfq<!MOD5_b>J{E#yF$ugL-A_ zhH`KWxymLf{WdtQwUx#}l)hxmkBFmoh=8d{2`HWFFD%o@$LfOG=J${;?`e<Od;8A) zZer@d+&I=^N~@%uP`yOKq%gcdVOl~xZC*pPK1EL*K_k5dtUa0)=_04n9%}`*WM;4X z`H@pzegn$!q!6KqcVrVS1a~0K^4)^sE)sVOxr-lCxBJemlB1ijqr~U~M7YC6B!N%) z@74=#LLc3pZ8(es-|aj!Toh{r2x81&yf0t%W~YGd@9fpw<u82mL2(>Z6f&!D$c0k) z79}F&)Cm#^Ho74psc2Sv_6x+oe0-1JLGrr+`%33c<+3^ppZg<4F)}*ha%4*RGa#B1 z=OYyN;Z43&sMA-3$V--AAgvya??b&_Bq_({Ecy-o$<etkpCtVs*&;UhU-=>hj{#7> z({<c(#gAF^3P=|X$N`9#HnsUYSqpiB#S-sxS8AL@!-Sm#2+IXO`}_0(b+2l+UJw0W z3qbYt<w9T(z7N+N-C^SRq1}xJV^SO=^e|99GV+}%?fjxJo&6qJ_MSo5L>(oKUE~kM z-GW%pj;?B1=*0LJUm7N{4o}C*HXk3A4^jm8kS7HpufT+bt&-oJ_5FPJt|1|tqag>W zp{K;_Enzfg?pGUyz05cK?MBH;>?DiOkEXl87qAJ!VzcaCBX`=vSRcB1`e=tIIb3Lc zN-;sr%&g*BYV?c8)XH=VAt@U!#7hg*ZLn~;d4*a}3*k4!Xrz(Z#FoQg1Xf52<sOvT zQku0X(+S^VQfV-3ShR8L|99n9?a)Zpmw~OF&t`}odN5|Hhd;1SknOIYMzT1IP6|%j z#;KJa+ch<o5CbFnK<KqX%Tm>BdtWg3L(h8ryRhiow4lqGx!!qO^8osio5K3CFXyww z3iV(Vl|Nin0!~0w38g|I1Rn^f2CCFJf7~5=rs<TmR1RuOSLwlhx|5!2uigp5n5)#z zUQ2}B0O_F^y&PR?JuP-Mz50#CmF2&8CWNq0xVfO7WriwPvBDC-$YQ2G3@Sp>96WIp zfp5+EX^%v>FD<HP;~GZdjJ*@5W?dn|ZFpqoLs4@s*6E;C6OVXkZn3S8|NpS|)&Ws= zLHn>xNQX4Yl1d4PG%M0l(%miH?Sdd(3(~P5APNZ59g+(IE8QTuba(9jZXbQ(eZTk5 z?>|L$J@>h1=3H~lHFL}eNObSQ3V{z&N>9adf3m88v-^r_G+|?$Sp`x>Rl0KUkjFlM zM`a9LmEpU+`LdC8ke%2c6+J>feML1b`QTyV%Nq>2aI_!2&zYh^)Khk7APUd6WYEHa z<eWxM5Oiq}+_zA)P+4@j#V>VrxJz*CdgL4}RsH(dMS2AWlRWHNbeju(zXb5ke_Tn7 zar)@vYP_8lHFHmvNpM`8oFKY*4qQt(^@X^@&be_xX>WefaF=ciZ?^L0z=_G7<fJg? z0x5d1UfbFOM6=hG_BqTq%#GNa#>a`rR9v3iqTC<-^WGhD&%pQ97X<-LkhWfQv4;>A z;_h6)xqiUb@ak}&_93|FqvinwZG5*wspc!yR$d$+{T*kx-E~eLNhD^*&GQ3HCdqjI z3aacL{I$w2;_JetWbZ;%h$aeoA9}USRJ+Ckjm*u{T2ku(TcxAV<vM&lTXUMi$21H6 zcCxcLyW#XS`SMKXP(0g{0;{hO#Wp@B-w?tVFPK-ZTy4Ut?mB&ymnxAq|LjuH3C(Qp zO#oba*rcp}Y1SUrc1%OHq_i1P9I)ey)c_Y{NBiA#TRDddm+37tGh_%%fRo$Ov60_a zIAzT3?r+mZg5JHeaF#eiti&~*dWUt;5qMAEt;^;xJw{07B$u|bouI-y9%*dpsBsc{ zlYZuK2>-Az_%Z+zqwu}r;S2m6*N`Pb=|_HfL;~YOOfvT_kVGkmo(%BD2BjY+`RiU} z;sdk$>|F<lZR3^((_JHam)b<FrNcM~=M5|)D%V<)Yu?|Hu>)qFJ~yIIlmtlAY+#2) zkhyfu^)45uitXWkjA&*2-sk%lZl(U)&jrH{e61`>QmV$QBl|ihUXnU(=~nfZ4XKQ> zFXaZNH=URoJ;U$&m{%t(Q`UbHqy-b2jxs~&3Vv^x=ZR_46=X}dj3Z$IHj?mD!J8)u z=?~LBGJu2>%|%Fzs0@Y<5G)K&D}~IDU$f_$MZI+Z9puOg9qd>41_qUXy*hkk?aIdp zdS%~CI@Oq`g#s=<07mdDS8324A*4GP5kIb7g)h3x$9Ar$G)0rJ?25*@+Nt*Eh;`n+ zp=EdZFt}y<;{gBXN;q14&lT6V&BPOhd)f@Lcq8Su$$r$T&Y0#UzDy5w)u(YMJ$P~z zqMRTP#EU!rQ}^-3p8Z_t#KAmyN`2`bVoyu42Kx>w>M^%lgA1yWevUU9q|-s2<20QH z`k-cFSTBZ7`T+wIK5&#w65j924_biH)LtL<_)K>SDAz32?zB?4mD{@h9V8C8{|XYp z*>Ou&Losy2!-t<CCu40%{9}}pY739qg}2uOEA|l~DOK1h$6?>WySUc&6R1h%x$A8= zb=0J_xn}5{3oFFj!_RWP=T=hgk`n{(s;6ukhj!jbW;`x=m)A5G=HU>NxS8{%e(JVc zP*2qvl726cA<7zQ8D{bZH?4{4Kncg0$s~-Oj$WtxVUq?Qv_i^~;kr#}smcMrZT(RR zFptN{ICVSBsd-}bOulNEYU{!}4$(YjM)t<SFi@}*IjZ6fLg}d79fS|(jD3-qz9$c< z=Hz{D&K70MW>ypvmPQ-2cQE(^HM^bKdY5kY?YSRVwd1Ipb>41dn4IR4XUhS9eD(8B z*riW@bS(6{g}{ee<iZ4vdPq?VajY&$Q`5#d!JFn-+e44FN*hBu!hayiU*VM#x+Fb` zytY-xbi+PJHi_Nr88mxj<QY&FpT9F<S;G|bUeN2ux)yKV{u~bO<{si1M$t+&QJc=& zDcYCz7sx)IE_yvm?+Pt0udR`0ljl)o8m?nwoC(wk5D&OHKDu#SNAB&Cyh}6*;Fa0m zH^dRTb(m=jo9CLrR-}F!Ero<geQLJ!pG^KM1P>{h>XOiP<&gBvjb~cbR>rU7@4qkG zG9_eW`?NU<wuth#&;v4=Rm>`m-PeA1fyP|U9*Wau^^k}UB~y&C%MeYHF|)yuxzH-y z6+Nt6wSM?eF_7-baJ<`_rxfa`kfXQLAfwUfE6Ormo9GhInMp5r3n^Ix^A~1+JC4c| zdhibVE;nRfNTtPx(yPfuJz92l<PFuM-(Jor_7?!c`o_?Wv2_?L%)CxQeGUi{j!Q9a zhBIu5w?Sd2X%{3^4q1trkm^!(v6E~zb%F2T&3nRbE+1Jv7;o&)f3DLAfXr=93Z96C z&w=TVo}S-C31;Im9?Pnr6=Wlf&yg?!r>u{zG8u{6Npg#K^47^?KZ>y*D3<>nYl4I2 z%M~48bJC|Qdj+@-s1Ka?gRR(%{a3yiBt1qKV<XC+MOD5w7D0Ju%lqh|CTqU+%KIKm zT%jgqFe7(PbZ#bkog@2iXYvSAqBFM1p(KGo#`!Sfp{i#F^w0$3AOc6xqy4J(M!4b} zKcxtT;Om!64JN-46af+T?*p0Le~G?bfZ=HJLhI!@@{UR!-z`(y+t^!tex(P9-t5Q2 z={8Xnhlm(;+N4;G%c{Jh71(X_@~MvY_f|;QwW=IOn2|<7s-)0MbVi*F@4UMQN|4th z4JEje17T(iy9I};&a!z*zE-7O7f7SREeZ1Dx|=Zj<hRvgV!iu2*p?+Mq$^G<pflc4 z+|F2saXk9sUQ_@%@ukX65gW@QXY@gDIlKmP*lbha7VE9oqQKuNLKIc8{|+5M&c00X z8`NrFbVZc+i<#e*>Xs<C(q^Xb2I~RWc`7mh16Ud~`TUDhhXiGoVAn4qT|ubH3t7Iz zeZ)D|g;o6NEAAe?t9kd7*Y7<$8OLMTm?wRvjqMxXer3E>LF35C_<QT(t`z@zYdPL4 z);(y{<UXZ%%Po~v$iVaO8i%lN=djF%iUNPll|x08RfQZhEq5O==|L$+xCWD(%Vo7Y zv@gl%lZc;v0`{qQ;Q`~^r?FL9?E(c!8b0ur%p*<W2JME;ME#8}maQL7e&pv%{?X`i zwOn&WmBe{6nqH!H)3T&Ga+4jsg_)|<2iEfir|cX}#|ZTq+r$bj9U>O}46<`IZq8|s zW>gL94EU(`>jW-}9f!@jC#Z*@QkO*|!l}6qYT>aI$q(g->m<zI!&7@4Qs}-&I*?ER zMhZH>hvtLqC3`!xl>vdB0l;yO3YIGnoZl>!5fQ^kQ~Zk}!K8mA``docmLz|np5;8N z8OQhLD;-WLh`@3(Q_XYpL$z-C+dwIWCXo>+&^A#e3ApY`bF)QPSY^dYURC@GFBNuz zA4q*^Y`1!fzI^FhwaCu`rps4kbStT*s-GfA2@ffB9@mK#nws;zlIMli$0b;%egtVi zH(NijiWq93eTx0?b~5k1lFTcX6@A*SqU?UH!U1&wz1yNHv?CgQ)oSN=*MDoLk|?n$ zrb+BE7m>T|=0y5N$ya(xeL8zqlljIcc!ke=N@d-)os(_C-;-3Cjekvoprn_dmfm`& zVr6i7Q|Lfl-Q|ml9$!a}AZuxN+x679mnA{3qu#KsKK>l$SIGoqY7%*&a1U9#&S((& zLEVEU8c|aJt`B(3uT4awH>bOsK&!5QGfnquY<^PP{!G(-BdM#QyG-u;uAf_b46}ZE z_>Mg*tvvEqeg;^YYQ|r_@nWw#JRbkL;;iMt4?>r%)1l`*a_B9EwVNjwEl+>!t^u@> zDW+3wR@peQde;i9;<d+_)oB|){wksBEcjHsIuOp&dOTPq{p@yCBL~kgCvd6BB%@0c zysWFY9)t*=$wmu~XegVX%PzY^*-UL-^FaqN6=oL;k($to{lRO{>_c9~2=UL+l7Z4) z7vGP{@LjeyAD5aLF}gI%_J7j5OlkVOgAF4~Wi7u^#}HHHXeei148IL(e<+3FZQo2@ zKJq%YLBZTxYdHr_hd)>~xm9M2*4M~ug5zA?Y>p;hCw5B>EaB7m5uZrTg&}&ZjpOeB z^oRSa(uf(1iVeB9sB@7Ku=sBliZXH=lpt0AQ|{X^2;jFSx<$)JL$xP`ztR>dc=yHe zUn3`kK?q5jIvN`dJt)gIsRJ<uhf6%?@N`w=c-%&w4SS}<Z^M;y{uBP`SYD!z5Y>f# zBt?qt^&ZJVsL5_3;SBHRJ`s1WD{7C*Pd6#IPbTVwxzJmEI@>_(GsKlsjUG8hbP~!6 zsw}fXA>wNqH5jLJ^e)=w3>mJJNu(gha2)9yg^R#+F5)`9WplH3<{xdR8;}^XbFQaV z8p>${NGBh5+?_kQml<%o+$>*}ZR4jubyyb{O7^ByK{Uo2S;HTS$!`fW^rKXleaWXN zF{i7^*$(8Fi9S{+=Y1oRsW+v(GJpD>w2u0NhJ7=;3wLMv%TkKlH8aFrj$Aw<8J}vR zE78<;2bfPC1qGhV_-08bD}@qiN%mf0dkcJDgUMDUca>n=zH+7ibo~8C0PdP=Rc@&B z!yud-A7UP@8OJCWMe1D^fSt;oPB#(zROW@#**CEY7dgj$Daf;P8m2(1!*W3DQ<|!^ zM7)o%cv5p2UO8;5)cLSlywdL|ir}1v<vX<*y94ohK0^fmLN;jW4gG7*x7_tqR>SE6 zPdgv^Of!LC-;B9B<@oOqHwVL+$UTdq(#&j+(#lwM*c!$jbliRyDYeS*{glT{p<q!b z>i7=5i_3LjH@55GRKXtnr-X>zYeISS->#DSx2rq?BK}{=<v3VN@@(G@iZ6*5!7hpE ztdrYH^VP)jo7-oS2mJJl&LQx+dIg~C5p9gu&*SXGQJ85<t|i_T!0D95N1%W4G)<if zLzQfBAn~W8Z@ahBxOl}1;jZX?$Kp$}4g)Ka3i8O~(-$`$b4vc);q)WHXma!0H6E8~ zGO6a5s7#We46gnGv`97Tb5p9+CS*&HivGw_HsQPO?N9`O^i6(Y8nb$8l$wfE%U48s zCZMa~2|LKdtGf_gMhZ&b!WOTgZd(c(Ua+Cc9gy%!`|-VKKl}{&m7M+{0UkvDk{^gp z*e2&3aX%MbL}tCH2FKg=(~nyHQcT=x(|3GgaAV7=qy`6AoM^mm&WFEJA2ZX{E2W6B zQjL8`>}8T+box_Pi&F1@A;<qD=HuY;U^-uF`X5~3#UW!wW+YFpUAa5b#F!71$(6p# zG0%d@f?spqM0-<FryU>+a>leG^s(;x2f=f#3xrx<3rutm!ug)~;(yc91Hk?xA<Zkp z@X#CR8ItCGvrprP*@mGKLvwcKN=^+c34`%mgta?b%nkq}mdCp**<B(jSx-u;Pfk>o zNBDv+A5s!lx6deT#TQ~0L1@h7fiBJplC*3igI_uQ%HJX&b3tB97~E?s1ddlE2X90Y zHc@pri_1o>?%753=r7z=&6LI$$Xh8aLEKnI-PwN(<^bdW!$ypNliz8n8&x`n-WfoE zz67Rz`qtOt%=MNRMwp6WV7Wp)popHK3GAhUo}N7mE3JrXq#!kBU}3O%ZXk(Q<cH_k z`fUDok)VFd=dZXiD-PC`o3FNg8WsB6ju7uuB*1Qip`e<M(KCRkl+NSh32h7{tfMh# zq7;<q-Q@YGr@6fzbmA8vLc7C*^@~gbZF%$3N<TfA6G}*r!#9tFa;=!SU7m(OID_`4 z?tWdfUwA?Wy4fiwEgEx%{79bcxK|7`lw7X@oF8qhlxCYCT_o@3Bb?0)ec%M;zOH^a zEq&M;5Bx5(^%b~mp)Qb$=uhH6@PF(CzvM0K{K5!^>T_qt<h8J<2NA-OsNj%mB0B$@ zTF<cCzBY0a=R;8ZMC|%_-9<^vpE?xyGdcQ=6OCj*GqYb;pa%Lk)O4{vmI=3|kbN_p zi^&^qF;jHSn@V|$Q$q@Un@hK7C$pwStRy`)GZ0cj9XT;eAsgfT0WO94!=EnkG^(mp zJOJ__xWzDV=UQdi);#G|DNQ9gE`~7i8`UZ#)@)W}G!J-D_Hs=r=15yK%CY#)8PaTT zvGH^vVbjN<xK3`FE6?rhWlIq!j}y8zTN_nJYuWkuj&IQnC4M%>0Ke)t$&WLLujT&q z8>O9xZ@0-Q5q({c7Gd}dnk_Bd4~_{xaZQ22K{pOOA10MbvWP^O^9;Mrg0;jS@6rh5 zP+}xe$A~N+Iv)!Vaz*NgCHMzGbAx`HR{Xf!|E4BCpz1_#SroK?d=UJhk>b_{{T))a zodEu<dlFtmB1nDKj?S;m5v<o0D`lP=EAHm%&q!^nNkUm|Z`pd1rq$!j+0iW9V^uDQ zNg`qbx@I092)4aUta?N8xC#f)2^6zQl!;i7W_;&GPTw6-CY=s`=Zn74_BC^1&I~jG zCVTs$<(^~l^t%iejV+fql^%7PzGA_q+s5XtPriRrn#0zZU_2QMS%E=b?713k8w(p- zi}7C_uKTcaj+=4gh(75Iv!}K2+JZl^Z*Oe6(>8o~E){WxY}wxNXH%m7ixVrLr|NSR z_;h@BwA%O+hVHTukM8vKnj5^&n`8Ym<PT&Pk^BoN_IPxe#Q!cP02!ozwtdaRfM>Yh z<<DrZ?*;Qb?z=*~qwg<y;C*+_=KWtL#uYrR&{X<##OdvIB4kkQ!TvN20k$wr&UgG5 zE2HAi0=S@*raT|awag0e=?yRFGmDpa{I??A%?wG-AEb(wj5Lr(3LyG_*cSHT60ADM zntz38>PLh$y>ny5lWv%DWyqpYFHb%vy_kK>drwB4<7CV-9b!ghcs#-WHQxFFEQ6|h zVE;z5#ycPGDKJ#zo~q)d0aNXb%qi9SW^+lS1#HDU_xoQAVW$K!>DMn;hf66vH49e9 zpf)8y%JvxD<?Gev;%D3=+YkB46fRE)++tipbvr6p<j=nNJ^yE4h*s_D+?(yR2`%3- zGUJ8kNkE{vaT1t>SDX^_Rr*P$s5*k;an|6$ol33-pz!f1S%P~Q%%&s_T5;Sr>ijaX zOurnYK@xg;d4uXPz!>W5<~@%3Kzgi8c8)716KC%l{9I=0kS?X3<!kq4oZ9K#*&D~@ zZB$pWqKb44m)Aj9MEQ^tHey8w<cuHsC)JO{Spp%wTQqD!0fN1!_zyZ>87}cYFrw$I zr>6A-7)!3_ua0!rR#*rUjE0K#0oSSMM_&ol7u{BZDavxFGRUEHnjm}b!Ou@SbSz_R zxJys*PdYqrYPL%$x4%E6zW+P=$Qm-%eXLpHxGNmR?l<-oWM9hZa`E#;fxgPu{s6dY z;dVd-&850<f#deh^~MqTtCg#qyFzn*Bxgvz%VC2pqXgr8dd2s87TfnGjX7+2GomWs zez`aJ+y~<D>|eyZP@M!P6AEIOdT^U-$(sq%oj87$)%pakf$RiNOhG76-VfE6UE#27 zYdpCsQXzH1B#0P|ZfPd8YDr*g#Wt*Y@rfnWU{~foQd|qKbAh^}m;1>?rinGIb91QA z3`}-le>dax-3u!SP<)bja^FE`<#WuD;UhowJ2|_WN~-|Qy*0e<aCCltQnnU$wxK~# zn23Y+djN88FxfRSey-=uCx(A+#k63{faTq@e2)BJja0KfeEAfmor%%>WRAyX#iRPl z6@&4EAjZKtl}M#fPlLmseVb#Do2t_;fbvZp7Y%=uzfPDMw|9Phe8Do}I8^Ic`uKFt z(4l85o{NjCc|HHbZZX@*x6MwlU(-nAq+*0;y|~bfB$^t-q%Zzai1rD0pPFVZc1p}t zPAReTNIL#YpZe2s<;02Pb3{<OJ=KnI)G-8Z>C1fzTwc@VS%uy^AJIh#kdNPF?5KG} zajS{)%LT_|e^{a$yLViYylNj<>)odeoX(B2F~8daCCNuJo~?ZLPY*2nI<CAacU#n` z?`u_)?|)+Ws_>SH%1pZ(;4|-n?#BgPsLW=`K<B+;_VJq8;x3lR8acnxs``lpPNJ|z zbeLoZd#vM^+-<sB8^4Uwt*D^4;4RP)acT?60vR~~Rt0yEC7V#%wc4cyhUAOCFtmD) ze}Y&c3=^Xm968=<_=M+s6@h{uAPUTOHTFl$_>%Umt!yq=0o$cH=O1zs;HN*XU-^rl z{Dn_tJ<4dhN!O9|hE{4bsJe$f$EF#In=0)JA|GD1U)9ZhT?4E|&2dyKwlh;;Hhy&B zk4F>qxS#9S4l91~!J+UP{lPn31>WySpyao4H#xn>C8o9to+rK7^}LJn%x;A`uE4>| zaDJC%Ho=2;)aMFwh8j(alj9_7Pd0$-^|0<+VbCkYpWE`f?MFPSzM?urQZZF#XF-bW z6RI>Rl+kwcjJh9A5qMxf0a3a$E4dy5>kH%z6Tm6E3*>VP!6)|zw=u01f;t+;63G|r z$$yrdoZi!H*Oafk^r1jiG^-f1+D&6#A5_(@V}nmhnndqQ4e(BxB~pAI#|f;`!#vcv zyYA7w@z9F+c<`y$fmvMPsUqgk5|M4iy9km@%TEU>y*O{xnz#W?-NSLOZOK=sK5j1* z?wnakX?TrLSSMDM+IxkXu^3oByeG?ap{Wjt4WZ2Ww@|+6crMRA-$)k2#jd=$F^TPJ zJ334r@rL7|q?TX#E_!Ah!X6T?9@5m(U!{=;83=%H(`X|?1!jF3o;j8xV=r^9Kj9#* z7%iKtN>BISBdHBO@=JSH5^m2B;QJePczfPtzW0abD@|xPsMD>1wmVXQU6$dT1_OfI zmCuroUsszLOdc6AUb6@ua0wnj;^|>6@BC1@F@BF^#F80&m)n!sMuc~J+kiUH5`C~- z`3nr*%N0oVohsKN-1s`Bb1UDm7*bvF>6-6&E3lv$u8spb2zjB7qx;!c`}|H5HKWV% z)HebjlU50Gf}ij5h@8;dn+~hgA$NxSaSk233Sy)*Rz82!$ZUw>v*dP-4J~K;>EKjN zec)Ijv9)_3^x+J14!U+*1awdXH<I1`soZ;x1bwX<g<{pkjmx+b7U<r2R-Er|bFWN) z0KRW)KYBy+6^A?h6OO`%O#v?-r(>=V;7+rD6}51u*j#Z-gc9Y6-Ez3UX~u;VI%(@F zBkR=6shs@4{<t*KvP0z~58mTi(L{qKQXSogEYd6Fdg)&voH$i_<6_kPghCFF=3n|e zd^uI~I*gt*7(MnwE=zGl#@!@7(tA`5M`ncFY<o_G6ev%l%RarmH(mkmP$7|K_f%Zs zOMY|wbkB#>l0p=+*f960i7qJBF~)|bPoYS(pIc~ETm3~$jL!uL!*ADFc6U(`OBTJX zPw$@h@8=tLTOZ2zzf{v=FTJ?Txg~>QlX(-zfW|sNG>j+PPF6S$Dlx3XmL3MneK<O} z((}JQ#O8`F=5a9(;r9jZKqMTWB*=$|dHqOwyY!Qe;>647%^reC8nY6>I``F!vwQ@n zZvjb_gjm*CX+Un4b=VNt_dz5>mv1tnxsL@iNu}oM5C%dYe&JcU;-#N7Jx9{HKZ`v( z@LHz)LO?A>tLQJeOxJUQ_`P<5c+Va_^vr&en1u9<Q#&p)!*w8>#Y4ZTe8Z@P6dvX$ z29TP=XpVJs{1H0AZFyccmi?0PT3&9R&6hvX-hXnX6EHMTl+K3=t73!A6`21_xetxW zN4=9r38}RVA0>YPNus}OHdF@(OgES8c;&iC|D&N%@>4sQ?m(q{=gH52D=O}Dt59WB zKM=$2&TvFw)hN|WtV|_WF@I#WE}GndZ;Y1kX!f&JK~QrIn!o5y)(F|zX`+E8sO^zt z^V(_jJ+NIPIrLA8Bzv@+H27u28UA(CQ3QQ;I9;{-)XHNPjncQ<?3zk9Dr#C!)ZJ|| zxEkM$wD<XZvPx#_sH<_=&i|6`?9)*?VtlIc!%0_ux1G<&34T5Knr&CPeI<TcQk2f& zQjA=VI^~cgH<5s{v)|Ls<7)A$PCtgbl`x3r=F%Rbxd$e7X+?U7GhO^_lI6S$7>EKq z?5*vhs{5h*hBPU{AQJQz%c$sm#uQJXYz#baDb3vof6sYoZq<1on{6^+tk&t=+g~&% zb{L7w+ps%_z)M?!#^lxw{+xnqs6Ls*{bO=*A~FsXv-fB&-FBV7O<KWx#|=0j=r2FB zMENlAn;qa9R`cH7E6A*2?{87M*B3_otE;XuvjTe`BI}jwbNl0pLUAeF<|=rn!H3#) z5C^u&90-Ca(?Ou{iWiffT&QpIgX-%ELv~gZfRnqp0fg#QLD;DU^L(7&3XB*ha4s>E z?D#w7!XxAM1H{eO;}y>VhI_uT-qZaj^WgYW>#%#|3BnNH>YrM3FhRT(oF;dAKdEb* zOR&av++nufZc=pxjyCV^POSH6+S?G%pZ9ATps;eQJMQYu91ug7$!Q=(2ak$9G9AgM zKFGw<Ui*%p9X`)#5o6oio@NrpThsY49Coz>Q>=_sns^>6sQ0lLzSr}3+EsICRr0{G zg9e@9kHWo5p-)1?6`JYKd%^Oi^goUeM63zdV!c@CEv;3n|I+aOF5ki9V77KJKDpCa zOEZ_pGNjx>e(+^tA)l@4TBB<u|7&fVfhDQl_g{R_+fus}dgXR?y<{F72D#FsUB{8L z&P`Y4dZ=@c&q}vB*$4MO9Uy2b-zus9TH1TagX1=F3Fhu=l(=4$+xw1X7;ms^{Wa{o z8_Ys<izXiuGvtT_qx;VO=neqBFYXl_&|oYTiy=KW#SXgEP$;#SD=rBkX@O&NooaQl zH%5j=KndWo>w7IB1vq0?GlDFEShu&(`{0uHyjw4S>bPNzH4?HDH-z#=>83kr77DU~ zC@1nNV<DQyeX;bH(ov|%h3La%NYb4b*%hPTx$DNXuMZs`?ZWWASIkk*SPsF$y?$+1 zf5(a!m_1~Gb8+~O{j5OL{e;Ts(w?(@2OGKM<e^jPj}7%w_YpEX@mTy;SJ_vt$P<@k zD#3D@<_YbK%I{o{vUZnX<6BRR1XEH27#79}m_?*MntLxPptq8G)OZeG=rQYruN1dh zo-&W!$2EJ|OkZ|k)y)D_mLOEX)H1233;m&fIA4&OHy!ca{LEMOW$PgxwoZ`-CDOXK z&Bu>-L-Y4%Ip$X$n~gTAE-RlQcbjbU|CR(0ypYYJuZeQViQ%sjtC${E=GR1dA6h;# zczJP}bcB|>Kpb?vex#wA_VhjF=<+hL#aW_iS)=}hMvPzP0_?O=b0;{GlWT6h3oti> zQaXhhvCt(LzZZLqwbkZmuuf!wJsvAD)0<tozWAYE0k8R(+QTv914_q~|3d`pu<coX zfX5*)+J+t-tICM(qStDFbN}jTv;Vop&@+6rUeiGsd>#a`L2upur^E&*IdSSN-0r(I z)*Y<-C$aY&A;4GihTc*h5YVqP1+NEk(!<8pTg27NR<!*6bY=5&r3$&6z`qP919UI# z?kiN8{Mpt8(DNCv@EteI9l;={)gJ5y{*%6xoOnUUy{OkfS0-K%4aX6}WAT1qj9AlQ zjmmxPP^)Kbo_1M4Em%K(QYBG>rhDO><Cc(2+0+i~_Tr@?T3^b%RyGapewO+t;$qS> zj>0)|*=QUeP3?DKu#Bsq&f$(O%UXgi+A&w`f1Q3%28<Q>smpQz^|@xu)$LUN=6D8} z)fw_jQIY1hn+8-V_n-kXK-iYSp^37JS7rPpEoYc(A-@gNi`eS8b4CLGBVhyFB9F3e z6($_bIkCR#z%Y=0`l5mYQSD`YvVSV#K2#g3MB$IN;h!7!=rFLC$;(WwoAF-lw<(CN zLst6I3OOIVU$RoP6*F1vSrNu%8(C+*Knlp7;4la(&*)^!%>|?WeJbw|{UgNCeo`Ba zOwx{<!MRd<uX|&)U4e;(FfLa@nZDM?;o}mfau=^Wg*xEh+^98+hh^8jc&}Zl8GS>b z`t-f#l#E7kE3j0^ACd(~f*vV3Tv)NL-J)^i{9&TrHMGy%G_zIlQ|*19;<*A^0aMPR z95}ZB9L_IfBND!&1Y_C%<sT^i8?pWr4*yld{rGpE7!m)-U{ZkPtT;38BptcQp>>!S zVVn3rVHiY(ycI<34J;vpy}3bsWvwp8{^fcJH#VLV2?VpF^%e36=R_tj|NTN><9}0b zDrBXTFo$2N8qyF!Jx#kfT(-92C&xW*S-Jvj?pKF9XKXXqu1S(WOv4%mvj|}KFiE0k zWX%)dN>?>1*0_Jlk%0AJMgQTy;rqs(h@agw2}H$D7aqA370*7TDrRy<H;N6@2^~*M zo(s-0llQkS1;jhxd$$_IikeQ+2Z}zhZP~O>XLC&nI~V!sy%o6axiv86rG-xUHafOA zmuba4j~9EZ1@08uT0_%$vot=ie@ys3J+^3g@ET0-g;+tPU&P<#N?^lP|174ghnvTy zJJw;T(NZS<x*`do1_CQ%0kzoG;q`fu>x%CZ^&I)rX+CFGzNzF_yt;`N0pl!bR}0Ux z1&)W?QhkrsLA+s8rT1jA-Pcf)8?MMtJ0}hS?O@;7Fo@aP2JTL*K`{RVZ>i;MxD1G+ z?KR!MZ`<p)BrE$M8iVvQ!>hI;a&Pq|FnIBK{gvMh+EEiS7N25~pRba2Thn%S0@&In zDa?v%4&*%uNfM~5Ap-<o#B@hp+F}BbaG$Df1v%eVvxMUlKFj-~nma<oA_TtfpZeJZ z<;D(gU8+o99r`#<`?Vs#!uObbMilnQ#xb@=h1i>1QRKX1C)yocnEJ}I01bZj<zUwH zpr4;3nd3Vka+0i%>?8Fy$dl_k{zJqAF1al5mt_QR2UN(cBMF8?8!#P9f)`+k-qWJo zY7tYxS;-L1TR$GJCcl}?`8+E&sS=A^tvi$!9wmzPw_xeHX8e+?EYfjsK@A`c)mhs+ zyu3-Z)U~0I7_ltDz=9hX`ro!=AiASI(u33WDvr(5gbEJeI6Kp+T+30~^V610R9zap zAEX?vK=heZ#`B-J6ukW8_re?lE5w=RpC45~?+B65(9G#$wS)BrTWG`I8=Ua)z8=wD zVu_%6Hfqo(;Yqa&OyRF#obDTH?wa6qob42`#Ty1w4Z?TcX!;tJZr4{yq(e@yZSki} zZk@BK-yf$sHm`c^ueo%6>$_;~et(z1p>6|S|CCMf_Pi@=JD3Y`#?6M7Hh`|jA&?R8 zqrZs#rb2!l@H4+_<OG$DcIF}AU3lNkOx0bwO4%83x(%`Ziy_`R=dalVZM2KNtzU#H z6qz#sErp}ew-Axq0E*#Fg70tElbeEEmR_RlIxDTVcLEN9fJ8<jB=Y5p=;XZ@m%(pk zg4WRt;3D-Wg$>0YBM?sn+jlE)fonJ?Vi7Pl^p#3T0ML&im6L5NE=Csdf2{0Ph6}s4 zI6{XWap4~veos7<UyJAj@$nN0hk6Bj2IBj1#@nfRu-@Dduj`9|?eBNdb{87T`zfCw zW80@B-*-eq)?oG&UkqYNXH@ywlB>S+(!on6AH+oUavLx22n5i9I8@#U<SOHl%Pef* z78u~C#8DztA`#&EG7dI$*N4wQC&E83ld<zRL#>iY&6^6`qnyTz>-P4RP-9*ESBO~L zPNHG^{Hh=?Z3j7;+F!&TNSaR0kanHE*5~~CJ^3`TqzY)eE)L%dtBL{R8tN8E_1nFD z2}|Q@2i4WUvz1&!Sbvl|@dwC&aigCD0tm!^du9CMZ>Nmgi^gC;SJ>LW*+*<<8jd`Y z6}8XOGImushtb&3iO9XXqIy%R=|&R9fj;!{#g|dji#lu4N4$>h2iww73HCii+u4zm z?9ggeR)3-w2)Kw=U*2>VczTi<v5&aNp%;_=AFML>+b)8G9rZumunrCA>Xqbu{%h|K z5zQZlpoCK<hg)pdjN3PTDGd=<00QSHodc&_3!nMr73C^79)d6J5^I4LXm?ZTFTz(9 z?kQkE^U_KB1g0Tliqd4lne=acw(n8e4cS(Mb1MvllT<-Gp7Py6&&2;{zrBNgYg~w$ z_o1nF4BwwMXm-eXxiS%=ixo1BUfj0WYqZPa^_i3(qIF`Lbh=!=9r&96^xE~g5>Bl3 zcDT!p0p3HY2*c8CJx3!m+Rs*ZyjW3_h}^W7GwZM>ykRK0NcQAKMKGl!Un@=u`rInk z;YdGWbb$4$B9W!z{8^v&H2MRz5F?j4D(Jtf3i-XN>Yn{<BLQn*tfSHhc>b|1|8rqq z4qK#*UUY%6x;Yc;o;Nz%OoDgcam>^+fL2ULD{K4m(uHz*`a=IqDt!7y$L-5*HTDLE z*4u4^xu+kRyG_G%Y9J2)CF(9WE;$KXsH^^&kV&b|vM51GJ5H+sVn<*RwgCHbiqC`o z_k2FUlt0NUlDZgJG378>Tdsxs;hWTVPh&1Im0=OZL-68CbOhb~mkUGlE0T}oyBB7D zfWJvOAR#e3{$X!0tndD)PyBp_@l4pXKw=LONHozays!=vHQYl|UK=-2EAn3~_L_g7 zT%XI$P0qmQ`T$5K@KP6+&0^-8C7S;cl>^|GHV7qH1vEUwZ9S6STK>2hlYT>(Mkd7# zuM&}88q1mT9{}PF5WheYU1UzInogPb5#o`z9wv;Io(ui&Cjb7O=@buszH8UlrWZ(a zX(JZ8|3VMaHP|m{xA*=3e}Aaf1qQ&yPCKA%V|wLSUhu0X{@*N8D;x6bxtBTq*AJB_ z&|7yij!=A9qflTEFtPpzP68IIHUSPbfwdnZe21At%c<W7nvBX~hX3!?tBrw`r}oV- zf44wk{1=R4*KNV3=bl~``dZ@F3r|_VMJtr*od*WjVD06IBSi4B@c&p6+yX7Knxi8R zYl5uwR<b4+z}{?yTw2olqbN=U%f|6^8GR!FK{6m}`X|77zneKlG=Q77#@p>b=#PD& zaeaD$bRq&<#s42q6u${ee>SU?e}Es8FLN3#Qv<;p6&nT<$M1%9gUJXVv8gKOQ6%Yt z@?G=nmp`><XyHosnw9@^WT!EnA(c5VSGu3In65jcx+<m|V%eo4u5?Of5Zk~0JdUeJ zbS|5yb9$hHgh726B(G=aC)J_|h<NtTfW9zfSRb+X{qNTxt5t<1_@FddU(pwBpmU4h zbLtlJ-~WpoQ#>$Tw|;9p$bRJDei9sC<1zY2$+k!L1-#s$e{dB>ctx$cY9;miH81WX z3?ymEybaBh;N;LqDaw_<zS$MZCJD5Qk?A}-$df%a=MVq0U$T#(mniS?%jD|=`*b5b zbM_W#)TMnFq)7cDXLfy>0elq!DWn749c%J(JGUaeqAq;1LolX338<o>E7>?WMba;1 z_07+anxwo#G?hm>Ai7b~N3ZR8^_OX&p9u!TU#aAAC%r6*?IWSnluwILCw)XHpZZu# zMqMv23X&=tcmZ1Z8VPraGM@)`mJ3f<Z+s5*c`P%y3OcJRX=-}_QY6USLBSo39?8qF zuGL66aBDtz@R_*NnN(Rb_m2V}z)f;{h+X}Y@8kAwI{(_CM7HZ6JC)llYl$rz7PE!9 zy<lYUU+ey*N|b`{A>`RC^9Co@D;n<-YmZM@2EgxwmZX#v?dJWZ47&iul!`liyUx^h zLK?c6Lvg#;?nSDZd#Y_?%$hwELvm`JN1_RvonW0=_4YYk*86N!I7t@A(36Is=#j%< zcv7p+>ce=yu<?T3FcH=v@o`PXWxK8M;yniFI3aYd=NRg1bZCrHONs%YR$~}p<tNaA z^-pJeQg6x!X@9>KF(xdO_jikyE&IdGxo0hYW6THbTxU5hopb|27QV}&M*Xp3wiP?? za(lqYu>bLB43B%ifNZq0A~RsxS;MwnVMj8><(*PL(mkoL`86XLv_0eDS|Bu09X^jv zlT8Wcn;n*N0v_)&hc0tyH{(+LAhq+?$t0B-P8V{Z<$}jX$STajs5|m%+>lvy``#Td z&rY_z3t6CHfBgFJt;+QCPlLw2QYr}2PgWUlu99c5q;+=|`XgdMYEPsqqIphD6N(-h z1H<NYKb}?%HJ280$EIU2Nh-<6RCRNQNXaaFrG_e1urj!$I_o1gmUQi@#~=3L{*CR< z-!m>l=G-Q^gr~3SD-^pR;QlN6b}+2*I$3#IAjus;qlgl;!gQ{-6JuTXl_-uSAi^KG zLR`BkxPa0212T3SW?=*|u@QSPS4lAf!7$^c3aA3Z3!B<*ZxA}zcq@nhGv^StJZ^4Z z4XbM)r&>R2Zmq#GI=ff-#IeuoeO))JD-`}1Y5>YLc*iw<?JCvST~ezs?wY@u>+E!J z8j-Qsa?S@5{&CyVXIT}LDHY>Nx|4s($6EHxR~65|89xaRgq!^%l2PAYM&WD0US4Z# z<gqiZoR{a{ndt$hTo`1|33$M%tNPsN<9YZ{?o!w01xFdmhGSFn2bkrhwW~!owL)@J z#fu`~@#uiK@tsihQvDXHE(tC{5JfCy_~L5g8t%ycs+%|mk{po{zGo&y2#wc{$nI;J zOjPMW!jz?CPsTx>-ZZ|w7s$6xXH5F<Tt~oUFD`cOOIberB4cif!+Qmpag&@%$Tz$; z6aNRd$<P6wwaIn4(*8_^b2AA@LtkpESvb~H&roYx1jn6)e*^QsFy8wDs*rq;^E|iK zLq~J@X;?27{HL?1Y0CKeG7+xi*u(42Ag{>`mSZS|Ky4IA6J5;XdlY(pCA-Y5wLr3u zK+3#X0@0rkRYIQll!sjNK_3Wiz(|jCvK_@W<GjC~N)UgCtI+jlMLs;24b_j}mlyg6 z<i+L20>R$Z3cP<b)BQo;5|IYzkRSGBnF4({z}jlwY0bP%-tT{46D>mS`~wp!VI1_T zS|FYj9B58P^U4IcWj(U-{-*YDLCD82RP_70{+1{}w+D$-2;z4L&!?En*Y0EGrM38& z+b8!mO--tr;r`LP5^O*@CkXZV)RJHJH1s9M?qljL805KtvtuqW0n^^$-nYv%xE07( z(op<|S6)?jq`HSjN;ZU(>btW$VJg=F{mhwpp2p|sxUIL`JC!6S2aKzF=Gk;z@}xBX z@DA`n8O}?jn)JYqE3$Y_h3k6AGV_Tk-nA>}_j$*B53Nt>&6^e;MWPd!y~w*XWr5M? z?Nl$TY~8aMmOdM3yjtM`G(3hoEpkbDn0iy~Paj9~EJgD)NH#y$+~_>%qkV7_xPoJ3 zv%yE^_5R_+H`L_ps^E$B;i7EC%pLE?B`<gqEHE*RkW8t>M+oG@ymOjM=cZV4FHe`% za_iB%n8B!5%fwKOy^@}I?wuo&;BKx?w!7&PrpeBUK#cuu-oM@sFchsc#rOK!wM$Wl z;M!%{?7ocHlY*;<7sxZY6QJ}HtRMoY3Erw1ke@l!-ne+4;1JlV(0)KP_pDajJYb+@ zAMaMc=H*B>&_dGNcf|F}J-@=4->Y9z1~sLKw=GGbY`I)-&-rS9D{2EYW<)&R86}b& zHS~hgY+4J(=&Q)0ey!&M4UgD{2vRvq0*BBzoKw&+266Pvt!QdnaLNAO9E%TWOfiH+ zP{Z)K8Rv;I4pFPOPt5T?m&AYEpl%(8pc39ZM;dt{Gd-)N`x|zf8(da;9n4&W@5%r@ zQUE#h3y3h&qW#2Pge5bGODd4O<)UFa_$->@!E!71RGf^zy#bRyqA~pa{Y1jeqH_LE z#x|SRL0J~qYdjHWb71o45z7!xCRI}UZ)4E0&N%;&jGh>;C4D$rAG>T{QL3bKDQFw3 zCG2Yf+*S6FXfNttJRc+G(hnYQupD^*nYYGnvfO^U+B26~^=!LlKI^Ds=CRhw>jyFB zb&GPsZxr|^T9|`{5=1+JzE$E_;5M%V?<Cn%a!<_%J=8lg9+3kler-sJmt39ct3DCz z0YTAMhp+RDSOfbt%GW62cZLQF6u1qfp+?t-Hkd;Wj(K!~4{Q`p=rvrNeVbSG_Yegi zZu8TZU*8lVu?`5>22DC{C|ccV<vQG;`xhk&UchP4`g!OXw%xSzqqlc$$4mSLrN_SL z@$atRrIA5!PH@34e`!2s8B4PNUFyqack5*j?w#T^xOHQaLlhg2X8x=fR@a&2mOs7U zYNRY1w+hmaoO4Jz@2l+bRxj(!IX~z-P1rXvgJd~zz!sF#5kD;IC0Y<tAMb1YR56ET zF}Q>mwNW1<n0_R*KPf)_`6X<7|8dtHLEL+9Xr49z?NomPwaXDy7<FE|X;mP4BpKYj z1S(%h!T4BR>!A7O1d*D9&}kM_lVM^1v)H90#H`du6D&YH6|>b(OmIv|Ji4IL9hR}F z`hFwV=GEt_Jp|`okt2nm&|Juo*!PK!(kP~`QfH<Mp!4V(Oz)OAtNAWwFoBi4)+~5O z3%e^=Ls@xTM&fGP4r|%fBz?Y&?hF(RZ7_m+#mtRMg;z}`xUBV*g<DKJxq?)!S^~2j zz(Si#E^MCv9;7ospjFoAvsqxnXOHmJ@!Wl@RX^LngTAyHerDGHD^bvP{*53rP<7Ni zSmU@jCNu%sE8RH|vlsaeB{7oJ?;6Dl@B8cCk<U{QWgPzM;wJf~Bzl=@jCnHYvnk>r zCkcRSl8-4Y(m<Im;jDPyHed(bv<*S!sAKgLM^_88L!Xk{rLn7ZYKC{V*qpI*Sc+JZ z?AsNECEZHfi0^=lmk#{Y82=CkaaXbq&5$Sf99WO%Yn{4;L-Sz5zg?_r9hSSGV6LwD zD7*V1?u*<E8*0HR>yq5h1(71L8ILpLXaDrJW72;H#u)UTSuxxMGMXLhwc5WU4ysN_ zRj5y5F|sCZcd_rUFIao)T}Aqx2uf?XF8McULEZTSTo4DTj(-ji&oJ?S@U`V)q^0b* zzR<KiX80{vL%!#2aRjbDe<vV4m%yi@AeuXZ?Lt;MYfq@%{`uhFr#>cqPXJ0#>Z*cm zAw;PQ`t_~SU!f2ONR$}!A3ao6$O9R2=!#561Dg>q@xJX+GL33ivm`e0T{Mryp7d&3 zncrbanyeYSMUxoE+Zyum(@8DYYmSy%&a`R|r1m5GL|Q)z#JvSnGnl&rV)u4UW16#u za%jougBh_dkRyAD-e<xGqD6_}*lXs>+(7&HuY*T5t*zE%m*pT%Ho=@f1jvT*oYMg8 z<0<8_VG#)L*=v75BPB*qCzEGC(sgVJOpM6bKDJS8l<_TtzksS`hjC0rHgdUe&AF(u zqS||x$)R%~w&>e4!Q<X62l`dT@O_Z-!k2!g+_?>fN|SiFj>o(bCcQWI1(M_hp+g}^ z^d~PmLNHdbGP#t%j{y+d6^8R|Tf<u`b<-`CO3EifUFn6HoWrYEd4;kNphG2d8}t@f zXmifZHx;q%kzcGL{pb&v8J$RT`|g5TfVNE7O%<VqP)V`wq2bNpdQi~**iy~Intp$G zvUAc>sU6CYf+l_QG&m)c<=BX;=BE>pH$rNeZ1MA_!ximYZ49A@74Tuu>{${nzzu|; z1o^Hil+NvXSNm|N@gC9e{>B+VMM)#dQMeF*3wN}}&W0<on;&bF&L1DP8z{@8JxMf2 z=EI7YFW`QiIU36MCBd39#j@gP|IwI>*gX)YjLoV>tcIS%(`K=$^)Qw2nW&N0ox<$G zUc+>mXY5u-ISo;xt2{vCL}9n+11aZS&3=f{&WZUn*u8uc=ChWxIAK7%lzXpU&-BB4 zco~S-iN*RIxals<>=5hlkm0I9N)NBuR(l((5t*nBtqLDQ*r#~g=&3^b)tsOMA2BUw zfAyYG_h|0Y2yZ_2?5wtw>F%@2x+l!4!>#*;v4U!Yo5QQ*4x5`jJ3NZ7AZ1%qxdX$L z6DlAhHV>z2xWe@lkQnxdTuK00-tU`;U{zBw@_y-UZ%8F!gav*ov+zMW^~FRrE%t~6 zB*`=L?&C~Z(#kwqOJkbxDk;9)B-E!{CmOS~bDEgbg}V;py$&-}8x*S8?)BY8%w0tU zCo8m`GWR1FZuDo_1rKl|rM*kB#t4qd_%=S1ONnwk>F%ApM3PfiU5JnB_f~1#UP_MC zRcq%fUYzP>SHsTKA4kc*+#YeZw%9s8>n{s9`84=Bc8TXvbdIAPdf*L*sNss=y{6C3 z(Fg3gK2?p7)Kzjk*ATKc_QLHn@T$t$=+e1-T~zZ}9aq75`cw)I>6RA0sVZUFkIfec z2<L8a=q7Me$2<oVU9D96_}AeESHS^jo--s~mpq0&<Lh6{PLHSg1#%%|ry_6O@5<Y8 zmK=|GGT_JiB-ALb>u7FaJ>C3)>kqAYLL4W5l1Uq~8KXvvk;5GLCMee#OjUQ>JZ5X; zXlAtiLHJDfY-mx>@L0P_G_=%^lgJy3vOBL3?zQE>n$a@~7>k3|Ks%7KhK(D7P8skQ z@z{Jy+7u^oLERK=3^kSCC8a4WX12qr;per}5g~AKMZ!s<3GiWdLE7S;5uccDNY5*V zY5xhqyGDhx!G;<;ronJF5aOp^(Ho1dFgs#z?L0O1%fh!}Fb8mJ&0rwQ8qaM5+d^Y5 zF5?0`pADc(=Xmgj)_7CI3IEaSiFfr`w!kc#2e&@WJuURX;2;0uG=BB<n&DJIFN$^( zdA#lc?Ge}|@o$>CdT0)nvam)MYzbd$FXKXm_gU#LrWfo!bGcC9IT<(dNmB9>&HH=M zUCN}G`8%7eGw@(kEIz$l&Hs8XQF}*fYVQWE-%(I{6>F$HOuF*K4l2W)HoA38(pHQA zjyolG(67VY{!t7TgiD&yrEc@xAca}Y0}Dw@`nM${FC9+kPT@E@^e#lpR?FG6HDoAq zvXch-69#v~#VJ2gyu5e*>=)C%JO_u0uU<bOtK0A<V;Qjckrm;y_PioXqr}I@)Ge#^ z-N=VK7u$x{5_zl0eI|d`qS$@y4Qw;TWq!E*i76hZWa_?j>hLS{(_Gp>T1f93>)lAV zC)oNw`LOAh3cd0<hi`Yg3v*gWL`>}7f?h@yVuN~GwV_p@-JC4tCx!`5DvvS1t8>YZ zd3Cj1nw5RCUhrP^+O?BxV_cVf3eY)v!r5Xe>e(9bXyEWO5~mc;v9#3P>>7i~=->%+ zyTwTn1~=9?xH}UK+|VOJWp&+OTNrv5IA@kwfq15I<$CWTGbpDHi4*@9AWQ&MN_#bH z_kt5Yn&{jKC#eIA%8+F~bh$xySJFYUm-@k^^+>`!dzUf;J<`zruo-a((*f6vgH{b1 zcSdKKoAsTJv?$OL#Ad=5`7=vv+t%`D^DS2Vakrv5k2<&^I~RGC!Tm?vistw)tB0mF zyXUvre&$Xsd|Z77MK5;Eyhhx5>i8Hnq7~(uDA)ewl!=?UnkMp1!?+XKEt`s2Co*Uk z`qrTN@xrh*;%P$<RyKPx=j&qx(CAhag`$Y?Z6^d3mG!-)&cZIJ#KUW}VecL#?DwU4 zZQxA%e*N_)Un!%RI8MGOH?8-R#&)C%^fS?hA$Z|-$Hih9q5EGZ#0d%_R6yY8B(Re4 zk&)N7<tiqG)RyKi-aI-Gy)snv#X-tK=d+($ZK8BSzfn4n#TI5wyNfE51IBg;3~^lL zcRJHdhqZZz#&$;^=Eo^*<XRnhHCgvn7QI5^)<Pin%bzN8)qHc+J?&(O;_)=&vR#-g z;Z<LzSPNaL6|LE*qtb+=u(e)#nZKl<J3exKMS1B@Qc;qmyyo?!)5(Ow!LiWi*75z1 zJ9Xr56P#7i63d)RSA}nfuWb6_T<N79Is(LO&-TprEjAL#Ni@73*}eAn<&9`%{b<tS z>Wn+NQ|_AYT$dh{s)lbh$tB=%*rV$$LYNZ1v|$r<`9gHZHrl!6-q<Ng?T*FXoF>c6 zy99?jK2-urmEfFW<U%fs$uqI8Iw$s36SMa!$Oes7LH)53{(;PI(xR_rDxBaI-2K=f z=CO*b{!iUL<qrhu&}}QHVoP`5=kGmtDnZfnsG!3my`>CXmtXo4;Kw=)9qT_jz!><9 zhvHqv&Q+kl`bZV|Y~Dft<{iqy(w%x1=btT<AT8sN;Ugwbu7Nb<o}}d`?jN@$QK9SO zDy1sQ9djLAcvAi(=`nIVbjlF*s?!A$G2HHHqh&_{LstcsR_Dy3&2^;4s?t%)vHe>( zA&q!yfqNhYd9#IAwe}7C^nvyazy34Q^M@gP2YThvB?b5!-iS{uJhiZe%BrkItjBg? zI;VAT&)R_TGDv0tR?Pmh+;3w%1n&@?l0xHb9`&Ro7GRo>VmD>RUqW<gT6pd)@Ynuq z@#h}f=@8rS?#H|$b;En(gtl>JKFNRP80dfegf{z=|M3uF9?_91a8nm`qogl(J&32~ zap3Jn@*n|mqYTGZ#^U1dPrETsTJ^U>;|sG+O4QYnl*cmxOHD))Is~w15~5^lx2dh> zlg};dt0z>z)NPpTmZ_F!xL!9Ye~eors<hPz66)?NZGRIWWF~*-*yc1+0cl}iM(a~S z@Q)<qsy;rBSramwit6eyHH_X|8viDct6-FDUVU|_@d?dr;6m;*$L=Q-v#FFxyd|>L z#Kn1*c}(CJHowKS1Tq^P9yCNa3nU3gIfIEqjar*ai;kPSOk4EyQRmvZw5~=QT=syH z>74_G#e8xaRp-9^!Y%5mH1Lvv1t4$v3;^SJK%Vj^)~vu<sv1`0bMBsy?^mi^SZREW zhEROV>?EyCxW18Oe6yLvrYm1R6g+~Q(9ocmd8Iu#4s9ty<KKJuFpGnkbG%Gjt5$3S z-?f1P;+x!#JD`IZpl{|iIPGNR96Okm^{T2N+lh3^EfvTqJ{%!1Q~>(B;f9NyR^vCz z<P8*sT`_xT`Xt<Br`?1$mWzb{8~2;=<EHDv!$lH>Eac#e#PelU%p!_cM|Yhho<8X2 z8~94W@kG9*waM?PAl?6C>aC-q>c6mW3y|(^Q0W*N1O}xPNonbjl<pWt8c9(R1Y`(l zBm|_plp2tf9tIe?hK8AWj=%eP*8BcDYq8cDW`EDwXYcF!TpFE7t$`cUa0}kDPQ5y@ zb{tzFRG4%}j1_}Z2;FTuJ2*_Hk&Pnsk=w^I0Vclcmu)vYrZ$uMEYc8t&_4W0&f_`r zdA|($&7<b&Q$2eo+`WLw>5g=@++k&2eFnFj2glrMC~u1*u*%?_#AH>_LI!NJtQwpn zjUjqX&;DBUirVwQT=shPuPy`8IZK@*`Dm~J-O(LL`*Ms}wAYgs`ni$gFFdQOwag8N z1J<@AU3hLpnZ`^oVU=RZF7S@6hVfMMMOa1~Ww54*<nap{Wklat_W+_K5>p#l8N9HV zVkfK|Nk0!C<Z8?`HQwb6G!nzRewjBHuv+@pCD9s`h^=)(Tg+;tHPQBCA0mTg7*6FK zLTd}SwUbyg3{?FT2##oSNww$kJymc@$f{{GQmW^%gO;%j7POlCXYgfPcb3?mCWc@~ z0Zr#nY!mY%<!_)Do+BqM=JZkct@G<Jp;0xoL*5RH{SGXl3(`iY+(J~GakZpzJFwPB z4%-Bl8>kr20)P6#bU~Whet6^X<)as3G2z{-yJ$q1IrTI{#~uF7ofKN`MS{wZOl@CX zlJv$Z(9RV@i@@93H$*h&4L~g0Y)8ff8@cXJMz6_bYu~UZ9@%m3P<%%ilKkx*neTLV z{$Jx|(X<YeT25}x!)MVZ;<uxD?A%j2?Gip*$s1~4o4h&Y(^!hcH{Tyz_NL#k5z)-B z^gIwx^hnKqJK@h)`2f$;UvQx2CaxA~=36D#EOFznn|#DTGVql3sGXYrbJFJ7RrBye zhN|_z{1d^P51~oeCRTEg;g>%$C0jC4Uo)N^Y*(cz6e{egW-!BT1*KL@e`|m0V1{cD zF`a5E)ojgfF+2Tfn-e0gbjI}@6vg_5_!poWkfBu(JAZmiYT1UKkSs?AK04;(-?f3= z8ox$qFs!eaxMZA_Cml*0sxF4(VzH)<@D8uCFxnMIh6F3UrBo~JOBDUsg=22e6fp4n zqR*NxcG|k)E^$h|>n>i@#g;Aj5R@RbQlQLmewTrGsv3n@OW68Y$W%G+s%uS-{c}O# zbD+6bGS&Vk5z_V!vL^+&{NY25*{`mH2_gAx2tM2m3!Cp~&+bd4A|X%QcF*x<e(Vv4 z&Ymm1i@x!0Z$TF!=L4Jnw-&YfhYk80=47cF2Y9jEpR@JA+C>oi2VpHrXuw&yQu4he z5|}ZLc%>Zjxhpjz;K!5~Z0paswc&d(oj!K-^&zU6s|kBa<9lIz;lTn>yO^%R{PDI$ z@`Sty7U-ezzbO<7J$u^k>~G>h98b!^cCy9hQ><V4OF2Acy{NM|loGm&ZsF&DTKc`$ z`zPg@5ko`#!zA4sUSJnMa`Z7HsoV=K)5pdq{pS#l=NS?x6m{tur}(2}r3?jPWw2t) zQx~XdPcY6(XeJX^!BxzKO6Ksjx<6nzI)UTmYQAXZ*IWS8tJ<mM#q@S`m@`VxmFG6~ zbA-XSdt%0N4xXx;-*=Y3b-suM;sW)klxy!a;B;(qz~OU~1$8es*Ldooip23NK_@PR zCu{bCJj&1aRG;sdQIS$0n&_x?)-Oi%aOStByO~4)q?;Fe?)ULinM!r9_KpZ{p~9i; z_}bIE!zR)5VD^NBH6AA)LKdvq)vgih4G5AH%>K2M;a>5%2+4pZX7V=z*6}tr^uE}4 z1~nfhm4*C34ElcJ=?j_J7;O5dY#=aPl+-=C#60e(%-TFX-llbO;g>8hw{$a!(hti{ z)?U8f=AnS$TWiJw7`)PBGZ3`{)6s0%j(f~73%O4tU3xGY9wT=4X+|iIuA}RqF=YH_ z!XbV46Z1_?qTDiRJt+0X8aAV?s*@b{Zgvuiq+fUD4dr3-1c#+Hs0|sf1mg90@sQ!< zvp+yP`@Xs_FHVeoryalh_X;(bp)KUq3R{(1He|QZ;ts4AC^~tg`Ra6QtE4scsEr)3 z11Mc!oU&Dnkts=8q(Hfay=#s4*^^;WWzw!(6vo}i7X4kH{YEbJ_bu3fXeZdRw~poA zZMV2Ght-)A5{n|94K%rKRYN|(Xy><ADRgIDHS*!&uQ|29;5q$%rOD&x);hq($=(KS zrz()5{r+P$D&cP}1{}p5{C6Mr0%4L_aK7JZ<r{{*q{sx}!v%C^Eb3Gpi)HDof`jkI z`g8dQfO6(S3ot&CU&SzZ=6gI(Gs<I1f!1Jz6coxl9vgXRR`8f?PZiUmRQ;P~*Oju! z^+n>!%iW=4IH~92d>ot9`4nZ6NCj#Zei7ZypugjL6W)N|c9M(r)3pS5ZN*$pP!<0n z+YPohw|c@A^}agq|0)CI0W#G+KlAVoSO5bRH=tysYoHy{ZDh^vuWcL>rPejSHPJ!| z-CV*?^ZG2HuI_$?`a!`BUv<z}e4#z?z1LK2G9LgEB9jZiL{KN0_x6{LQ#tK2QRGRj zxgbEDk<zty=`hPCp7z@AS#8^92~$n$>ry&*99aF?AAgmB?|+^gJoIFjBX4+B%#`)1 z3k-gnqcF4MI!WfDB=aVQ#g)dy`%|hkw-%};5I+*g{}F3+wS1cczWXD9bKg)$Y@5+J z1?nE}b%}qDbYwndA<y#a(1X)KnhpEHr0uBDnuHwxJC4#3r8yG28jfE}9Qht~QY;{* zkDJ7`L~${lriN3+hA3WqxeT(n^bpp8zz7V+i+^T7a3K*K>jh;YCmyXmsFT^p7-rAo zYZhC|dH=Yl-4H8^GwWs#3*VWtf0k0iFp$OR)BIGgJ&MdYJGtyLvnznH-2;_Q7aTw4 zs2H7gmKJ0=f+vCOmk~;%$|6ENrn0|t<cfr|hY1?HO9UB<06dw9FXvf1siOuT$!g2R z-wG7N$<+0Q!Ib!YOIN(<&<K>|DbRZf{d)eIlDSJ|r2Et*co%!AW3Dz?8qfinQg}WF ze(Y^4Un1g8JcdTC{6G^_K0U?EzxTnK9ws1f58tRVRD5@GJM39kJiB4mv7R?Pn<U^L zzVMQ0AuSrz%vM2NO`6{7a5?A^`4ob9ulnLARGG5j&%^SbwC~aIH%Ybi4<1d?+{o52 z>D#iAt%>!Hlv!^@Z=&@@Ee|?L$_IGq?Z^as)xTCxP4vSEro1Xg!dLaNqGq@^M}m(o zB^9e~ZH6x|Ry|!~D}YH()_^DVv6m3dEUD^x(xaKlt*b4ihr^eVPUyaj^0cuYA1@9v zTq_||baE<X%DwN#Dw(r9QW?vZ<vTt;YN$7bFIa4Qpx~7g_BLVZw~79p;_53m84~&$ zzKfRE5=1)val-?`k5<Z#GaxRiNLW?h;bKxp#VB!TP2WiP0eeNl^Tw%VFf@)}xj3JE z%4=lcHA>Fcm_YtR7-MnSmA?9ywY@p8*|73&O2v-edFv(jZs*x&9Rg<>@^V2&U_4g> z9jw^4@r;`vS1TaOmTI(i?_PW3Dlb&#bP==;TkaOwSG%&A;DuyL^klAHu{Ii>G{R!6 z&dWi{EUc>cIiKfEI0^6n|FM=pB6#$5f@Py?%e@BY14L0pi!c-5YKjBrh)ht@j~q6% zm9jH$ZMNH7T>oTr*9$;+1PWk_Wfd*R37eSDInGy#kTN%zs>ZwLITI^MBalAUG|Cki zUcisY!`O396~^zK7z4usr8Rssc(Y*$!6u>xbsxaYL^lu1SQIskZv@vg$ZFtj?(Rp2 za6dwEW%Qie+!c=Z3Lw(KnUfQ((>f8L$!h2v#*5=Bomo#^y#`mOo%!5lt$H@tS4ZoJ z_wzImY-q-GsBmISQvj$`xL&&Fqg>;}&8?43me#-Z8VA5}7doe;(+Zx|9gKiWUoG_E zK0(6f0@E^w%P$Q+ajNrRAC8Du%8v!RtWTx9A(MTkwNwqLvYhMcDz=j1M^|gg3$D^} zmEw^Yw9P`tx%7q&<eGK;zP&|8tQb$;NWz#iB&mvDqI>b^#pdTWh93l?E!v5;G^-nL zX3IF$w&zUvqTJbIKRRWmobrc{o8lAVNLzc8)IQvfCc?C_aUF%k<x<UU)AW36qrW@H z_L|IYZdmO=As%zqU+~_j@lAU)qv37G!H10}3U5?YV%K3ib`r)mt%|WBPzK|&kBKk- zQZ#;zZY0Th3mqL8?x5nY5FGs>bWwcSTFReuzcn&hj@FHtB%o|tmTcnU2}Zl~w#;z4 z9-PBi!4Y|49vM7ocuw!TV&Zfd)R--IgXVW?Ak7GeAV!Mv=Gjvg!MNzQ4)QID&cN2q zf2f@MVXV92l|t8^)x@4!%n??h9Xl6GcQ%unucF*?x%00JM&P*x6}kwzM(bA{{?}V# zk$&MDujEWGE>ZKKm##-A_T&!Ehe0z0moLM{22N!k)do+$394pl{2<c%P`mG0iW)mv z_pp~P(afwmN4w<@u-HyT2cOSZ052?DTeUJNzV&Vq6OKM1#XtzA$}yf)r5vaP&v)1N z(BJNSxC@RyGW_Z<oug*D?BEg!QHa`sHe#EEl6@7nJ4k$5_+pk=MAl)BHdc78{LX~p zIBD(dt7c8eSKmbh%n=b3>zznjGhoaqI**WVzWchL@syViY5YfYxG)F6MI{B(q*!Bl zaW@=AV|e!&jGUGCds&!S)1j6{R>L4d1*2c()PhteaJ2aWdnkol3)z4-NPGTEiFsP- z+x`xk0_c7mIKZmU>d|-Kg%Ea<Ubz#c=O<{JL}N!gt71T#J9`_dCo=Hl665xF>J-~` zT!K<H?{8t~pyWrmOx)Sqir#38K@VYQc>r?{<UbDC|7Rz#zeIs;?Am+TE3H;GoNi;U z>fJjFPT)og+c{T43&~UBgT9@ZZr>YD3ksqux_hs{CClU7CZ>4M{DAJgKRt5mD{>1z z1@=AncH9>3+>46GquzxPBhG>t&VCS|YZ>ky%{DY$9o}{7uT2cu_Of)#`Dj5?nZ=7i zTLoLew$J1v&6<w)nF=`QZ+z%A6HOb9-3Z4|WH$PPH6vHAuE)u6=CsoK?8ulC5*YnL z7T~FZb}RT<edmx{+3>1Dz;p(bG^gnDWkL^xdxK3Inz>0+FoeNx<gSW;f}*u2PEW>d z(M%RPD3(JwbiVD%C~>kz?F%I@8qh<CixO-zSe7%mYct!uv>-gf3QDX9$mn~=U3rR; zGmBso(tgNjSt_G^&%TJ_aVp_=riR5Y8u~>a(E|>E6m8v`3hfy|hH0ZlHMfB;f%My# zn)5UC<6j)NE{2OT5IZZN(a!pHSO(j4y|f^%qQ9JSyXnph0vNk3mJE@ED_=|BAb0|a zWC?s)*vP;@TEXR%4uUg4>4UF2v+XfF*5<by()+3=nNu2remdEt%ku$(Z~W^5aDKkR zV8~Z7p}1~96^*4<2Mku?<G;=!05VDQ9phD$MZWmc^MIh;uW|2N2LsLjzzrRk)dn>m zQszUk%&2Z_bDid%F)TH?ZRMZW$rJBlD!af5i0)&_M`%DkGQUaEFCgkSV)bx@GP{E| z-KkHuu^JrRA*?xAP|)6WdLtVpYzD$DdL}Kt>#$U_{#m64K98V;+~YCuW8J$cJM#Y} zJUipWeI*BUWlZXGcoTtlHQZHrGJ>Vda0_H;oX4=si>Lhvn1~wqCi?f*`!Byw;oI=Z zwv6UNh+G#J>c+=WGi&*9=OA#g{OA%@8R&_oZcn=4+gNkI!JLW9AxMVnb`D!sZfgp; zT9M&Gg@sp$$Msa({2$a@pl&mivO2-jot6lI<@ozgod3hq**`{#J_qbSfSdz>6EOzJ ziJt_7tFMrIh+he4;6fSBHH;MOJeQ4s^G*;z8$6!K6!N2~_I0Eg+yNJ|yPI5R-bhq$ zBl)<#>Wcqly93iT)BDbZ-w~Kv!wp)Dp9et$r={=5@f_yE^N!1Cj8~<YUGBIoDP7VZ zFfJmIwDzRky>}7P$8i1{=q!6iI=pE29g8<*@?D$`4HoJY<F9s<&LOcNu>#Mkn1!s{ zoFDhv4X{aWjh8NTCf)`#0D$-DXzRO>Itf9M+~}+%`QO}rY$=6}j>`#gBVkvsUE+x$ z+d<Ts`TP}gQrVJ1wU3olfwEwo__uvG@eLCy7`|`ez~_I(xUYG=b3;X@(eox7uj%OC z{#V$sPH!p)zifX&2EuDMAH>vjr)=%zHASPW&dxN*685>fwzjYFd^xc)Op~WbIPPOG zjb=9qZ=)*1NmE8AyKQ0GMSgZFq5Xr_1^<w2M-%MdH$e*b;axI|ifSGuXC&b%!31iX z&X`l`9p3~#Tuhl`PL7>4qU(v);@eHM2TQ-wWOvg~ORES)u^Y6!W@Ogk)@{v=TI4Al zH__y~u}auSa}Ry3`h;f_hC{({P482ocA{b7bSfFa&|#Ru=4`pIx1Bm$io}ig8`qn; zJrut<8P`zg2U;y`(z(U-oEH1_HGx2nXFGstDiNMwi)>^}mzm1x6Lm1#<9T)47wdKv z5tQU=MQbf+od2=q>6k@IcaH`6)+@w&@PK(R0jqZ+cGLdB*af-6b)ew69b?Ld*7!RS zjn!Dw44jLVaY5NoQkefW>LVyq!0rSduL0m%4-Z{wlXs+i<H~q|ddF8klD_J_D&S?p zncwY5ltTP5W}nHvt`;%W+3p2*yi+GM164KihyWzH8@dZp9tR)DE>QHsfen4a5=b_r zuXfMxrCXzykLnz`&el<|$4I>)@y5?;2e9&0YpWjE>WG)Kf*KBiA*u9s&X{jGBu)jy z#vi!;vorj|KHH3ZG7Xtv1vGI15A?&h9Oa4zY#2Z0G@Z<|JQWAt2w$JhClOFr2}>7Y zI!6fn*42|)F0T(da96JI#7?2mW$@-B;EVujEg#N{H9fhy9&>+Ai5-6$-l&fJ^3@I_ zUnhlM;UY%^o<0lQ3#kd0umV1xEI>Kr-XHx5cll_+O5Qew!6VvQbth!N4tTz4QUKi< z_vATw@>859Xvx%wJuHme{nM+}&yF%hgUJ4*wbI5X*xm~VUr}1G`D^^<9r=aX&tnZq zWk=H$#Ak54JY?n37r0f|cv_Fv&a<z$%R3Tgs$q)n^h>{0I+hqK!18mhMR7bzRgkw? zy=7-o^h3YT$t~l?%_H@4;`Qg7j|2&!X8p4vZoNa0dkvly3MMt#VR<G=yZF3jgPkDl zPA%UPc$UF4AF%w>V5WRQv(X7iVB1c?pZmyA#t+-x@(ZTn#ZTLk)a8{|S}ddYnwXIn z_kuUrP3-iD(%b2eB-~`9rVOt2W1h%WjmrjWfi&M4b6&9k5GX2!svrG<Q@y@(F|7py z1$MEUH*oqVKNQG?#EFZQN_&^Un@+#iN|wQaCMXh-@Q+^9Qa3;!MIWOLi~HEjs{Q`r zrk39al<dU#W_XXHqp)?5zMJpn))LhwBOhx6R5*7Td~ug-n<T^~J<T6?<46W5w(zT_ zI<eR;zebkR0YQFe1|Z$<fZaf%>+cbz?N2-&ZILS1MQzM=+Z`8y<ljL84!^*hSKC37 zEgV44v{j6+W80i*p+|#4js)f(iFM0>qp$WW2kO|)J|qX7-kO^xUq`LXKTnwtkf!?M zM}|FYBuJ-38(%&=%&$e9+|!8*wzaBizCm+oPBQOSmDV$vzY2($3UA0WHny9inY<=C zgZqIlas7M+6@GfzNIS1%ppWD-M-gu?CiUGji?E9J^P23)h3Wjc=1(R_g(LrrGw1(s zth`1w&3f{OrNMiYe~VdSa(|6qpnzwBw-}T8eT+Hz%zIMM6-pemZrQtKG?H;k_0(?K zZtNp?l`E8KPM;>JgW)Rx!2Nk~S9wamCs4&~^1}2IRhaS2MV)l)g_&qY8P7bzK8U)* z<;C_nuChNIkla6g8TCI;%7^v%nO$l58LVX9B;&MZ9`uZpK(1(+-IOW~D=T&Ox7mFd zaj(1pI(o>4T5)#*VVyjj1yM-y#lnm7Mi%TK>+L3&QhvYX6Y>Q+x&hMB@m<(8VtOO! z*<DrfxUq(@7x91;YMsO1sEcqp-iALuq&$R!+6b{B5p3}5<V8%SGcoO%&W$nSjJq5V zVLfxTO6S}(&fN8>Gige&@hi$xdFEwH9G6ooEk2<8e9<|zkfhN(kMdDp$f)}B7hlZ< zcmy|0S=5}1fK0yY>Zrql<v4adCFMGJ@>9rc7OHxLTBkPp)g&5K0W6t<{ja9kYem+` zVy7hGZTsCeMuR=J-nR7Wgt+}fwgc{J(I=BhhrF9b8+smwcf8*S%lF`oLnt{q!3{m2 zQT219s6&>Rswk0xt<ufd7t`m}0w`sMQT1#TnA1lvz9(2HoZ{j(G9+iQ;p8n#NLO5m zG5ob<&zdjA3QR|-#L^L2PLwo`)!|V4gs8jm;W4ji=^VgP&zwn((Wfi3V2Edyq-MWy zj$)uI!>swPWM}YylYJ0+-nvZUt?m^86SQ8~`O5L(7xtb^@E*45*1`*+;aD-kYt(4T z+MDbRE2MNL%CPNzOdzP8b?k4s(gN0WY--U)M4I!?**(^nuf)LLJTei<J`MqexLS9E zqd*YGoU%0c6#h5sSDx1>qsGb57)Hxm!Vs1sclPUgZH1A)QLYwliAb63GBeQmt4kGc zy0@VrOvO_?jZw+9>XS2F;jJ+p!c54S0sCwx^3Ih~>@GRbf$$OYuUttHk?Z@n-1v}J zT;A#_%Nd!HP*h;AU1u~fxn;b2IXfej4h<v9KX^h?9vPgm)|U7Y2n9iVa;Y%l%xOA8 zaZh0<{g;OHjuU3O7+?%RYgaa1r#}C4r7Kn}n|`HX>M6+={t1TS?byxOGTsSs;DwfF zV@W~uMub570GN>u*uI3sEW1nR2_$#@J>hR}r}+p~B;#2jkRiTeBsWj)s;}YT2h&d+ z(_*k)cA~sh)>Z&xhzwc2&1hX!oX7UHGT0$`A~uvMN5ZXZN)6*YjyHpv8Mm&l3cqk4 z{TH?HZ16v`GViLi+M~UTap&eg&;<}5BDg1$kHRa&@e=Z(?VGq@R%FF1%#i)mrj;7K z9;vq^r(J#1pYlbvQ~MC>%Jyfox@6IhPj4Jb3KFd<su&gbDhH2B9T_`p8Hd>ahNe%X z3=>&sUz|iP?TE|Y*!=SYkJ{HRWGLxNVka!~zr>GgIh%dWYA2ru<KDo(r^d|ZKLJc4 z0RW{wZdLCB`IE_A;*oNaoGl0Q3i)Ze^_t7dPutu3B9C@7idKx=lT&BLze0N!j9J!_ zq5f;j)pMb0f?95+%LL~S+)33|jJzHN!^?OAZhZ6>c2nMRTO`dRLOjXqsRA60IUC$g zvZI892^$WbO^T48J#V)+Rh7i*1&;pG2eF@9DgSs;WTSUq|47Uvfpm6}<f2m|vCpsn zh7bTn<y}0oo13XU$Y=5$5V$Hxodd&?+l>1l+1oWo)uhN1gDQ`zV*ch;+7m#16j6K{ z(&#WZzncRFtuH@|Bx?L!9sL>VUOq3c)No0beO%}TEgPNSYyO~q60{vgH^$!evBUPy zqi0X*iotSCwF-S&x7KTR7OP8Z_m<t+s;s_jcLH%SU9yTy`4=vB<#sj4q$iz!1NS{C z_ot!VrNJb1ohq|Ai~T-aPtK*(s;~q@n%t7H`IN%7KB9V4mtoRa*`*gvz!Q+{{WG7u z;K^`s;`FGbuoG}i#kFzfl>->zn+T`x9o-%GFhTU#YZhVG8D_rTNQ}=DmPrZ=w0r@u zw@1lX`~mh7V>#htk79SRf5VHRSYjQYjlZZHUF2>%uu8_Gc(u%mX}!a<@=mn!6m+C! zhi>73rLSndvDwAkv%mr3kppDoWP1f#!VD)kJ98^LQhcSwy>Be#>HD=8GF`4Jd$2`W zxkpMiU(1J1RQKcDoP3z%Y(Qtn3<ky9N$4@=Dnz^lGku-JSE;|5u@GH&NOO)vV)u&@ zH{N~-MWr7(vvLJ*6k#<bJ8O#T&|?|a_CAs?wsoN#3l-~x%+{Z9kq7sLI&UOI?mKSD z7Kw!zbbo25jkR9C+KjQ8D=#<~$eRbpT1mpFOCc7;;LLn|ACv4vwlLZb>>p8k;_9jy z3v5v1C@aW<-2lv5xNr{)A80JzsxgV_Rvv!~KpI!hw**<XG=`^+8nMIbhGe)KPW)$k z?o31rg;lriI0vyNpW6&KxE==dF}?9_t1NZ|+HT+u&)CSe-~Z(D;VQ5dS-1z+c(m$; zPH_7DfMqCDJ~{C>*tp9{yQls{HL-;$^|_pxHs8$?KasO~eENs=RY4gaKSL`ctP&<X zg)Ho<9OKBsjesChmbj~v=QqzqDUGR4X{$dTGW$omTA97idhNL@A`F<K$NsbV+H5h4 ze>szVAp_V>UzmtLl){nh7W&MCTV658L(j@)|I+7OIN~}jz(VrAu$m@Z@oh<&JKvSh z;mVM2HLufHNj)zd)lC9_CjI7xRbkMcH>t7<Vbpup88h?_4G6OG5bH1GUITKstY%y9 zN<&c1VlHJVMF{xHt4274sj{<d&8=d~C2q&H?d+6t|8(`SYjfW1iB`*S`|+uc;i(H( zXcXq5J6X&{!{s1@nHk<6?|1Fx!Hf-d8+)CGjb1HXep&3&s7<?$*;74z7HoO{6QLga zIPQt3hM^6<2}hQ#jud_lF<%UO1%vg{gYW{>P9fzdYJYRK`r9W%!)87C?gB;1sOMsM zxJB%wgts8GTojqDHHa*5zCYvf_IC&Ehi_@ZV+;)*u3kM$R>jPF`-6}4$ZnTU=;m^s zh0$Rzi^ez3Jw*=4I(AD2cEo1XF|8X2vbA%DqM?&M!oUOoI(EPI<l%4~o0BHNMM*=V z#?q5phpLuGvz+~4fzg;U)(?xs<AVIT_4{|1-x+Cv%(GP=FUA&WizEkjzuWX5;7;+L z?IV6Bqe~ts$xQtwLU`;256>2lb~E0Fn{c=sJtOMc+s;XIbkfa#VBu$U%A75G6>6{R zb9%0HKa=n?#u-D;83nKJl__Ljq6L<Ub=l3lzI{DfQ|;5Uin`V6rMMieH>nJ+keI6_ zDt>;qKvO3>&5_YHSy?;Lc*RCz<rz=2OXYn=nbE^-g|>c--F>?9;phuD$)&&;6Ut>n z)B98YAYrFsn`yWH4cN;0h6=ZgsaH6>{WIgtC0hnz1M_lpX~_iMvZH|^MS;{bLqNUe zpT~R2;^$|b2b0+c;(OAoV(Z2ZcRv{j6yy-;z9jESG3`?fKW|Y=mxb@7M5T+4`FY9A ztTfydp1nbDKZ~`MD7Li?Ks%$ghwF^a8aDl7L$SY}fnSdsc9@L?m(7x3E~!SXR9zv1 zCVJ<Nc^~N+Tzj$OLygCeOOo`ROWjctyH0}s5|i%lbd*0Tg2-H$w7=Yu;kzmbnorcR z>bIBb*crzY-xi)V2II`hSS4Q=AG3s|m?P70K?44HbG3vWbc-qD1Ur_m+~uRIs?L`P zF;M9_yDQXq$)5Mg@QCOaR=<mro(n&H6YvKHN9Y|BGVxG+HH7`Ocyw~(&xJ_+g4}($ zq0^sxFqxqGois%&Xvw?U5Kwbr2BzSwk!>kqr_A}MhuZv=wNZNCLGC-5*NRUFMtkzy z`q{K_@{}E{SNQE07xE0ql*IAnL~y)z-@~VSJ8W%LBftwrm!wNG#0rHNhsT};?~g}d zG;hLSQSP`~u=aPQwqXy;<b<<`lSUl#j)+@{sGmN2`Cm}hlXd3DgHrRaYiF8e?z<M* zqhKQ`f+z<jsd};55jFis*MCfxW~VJZaJvT|3KT?V9_6hqA5s>7ruHY07wE}0?VMe3 z3ovAycqUN4!>Hm$_u{^NKSS`Wow}*s$XUV9OB7`3XHZFp4cYX?IFNHtdkAZ+(b}55 z@uB7I<*%G2|HyylF;rG4>#j72_t`nzIz=O{v?RR4d8pae06@ukaqHfromO5qdN^{D z9Iw()CBqwwKUu##t7cUsc2(_S&2B_iH4<Ha-=!iw_{^->X^xuuH72D^#($<)rUaiM zmuvskj{;Ex6LGr*X6qEy-PdKxv1MXO$Y62{o6x>?;o#rd@cJZ)4{2j>UHaX=0`g}j z-TS!jc^~DoN>aABW14pOV%YQxj41nVwo4r*^%-t!4>Zo16BHnG6WK%p0zFl6K_-2? z6AM!t8qFi?e#VpH_(Lor4flBIEwPTOkdo8bg0Lln```W81C`i6PeV+`O-yykP2EC1 z{isifxq7_if_CVi_(-&g!ngbj9^9gCDl<kB+qMO@OCMh1*G)N`KP;?s?Un{22N{rt zx7+j<CHIr6&yQuO6Y?-+Wylpan3B{tdWvnReDDwX<ho{^4g2zq`2KebRAA#;*wFeo zn|Nv<p(dx_G=1;Zis+Y!-=;(%RrZreSrqf^P@U3x;qK|=z{}eMmV-;NS~cfXXUk56 z`$Jwbg<c#<dkOUu-hk@o6Z*@UR?^J7<{=5y<xHOn3ash8V)UzglOSAhrk#nvwyY6e zu`*uOGMV96gG+IkoBKQcif?T_A)Flkc}J(b12r=eSH+F{Iy;P}&mn^bQdg~@{`?=c z?ZYWdAr=Gi+u!~gH5d%MoIj06yma~yq&qD#oqr|fip5MYoMsqj{a`rHJk#%a!U=II z`w&CXWE^sdQhmQPu<cc~Bl(qo#}d$R=6>)h`+VfA;|IZ1ywz`^)Swe@R*jyX>0&~A zq&>ZGv`Bo)ckQ8e-ma0i(QmTljP&SlU?{o_Wv#fMY0R!{G=|k<BvBFC9ja)`RIJQz zF0DTa8mCdb;g{!vIf6@GZMMZLelXV~8*#D$Q}1kQdmg-yENBmFr#9EovM8!ktlVx+ zEE{BL=gRnanl$nq(nJg#Gcl7NJQhOFjobO^A2@^}l^%xq+lP{=E5%A0+8)78T}cl< zw_q<<x+1mjvPMA9<V9y<39lU=hAD`>D9NU}&6wwR`{0(Hkex#Bar=Ml76G9cm!%|O zf_((6;QaTjUUwCTrt?2PT2R8DMz1iMn$3D!=&dJD^Ee*-!HbKB-i|?ORBZ-4^^Ul6 z|42(2i%LEF6|`E^t{n^j^=i$7#E<13deZ(7yt;Sq*)rwQOqXW-{Q1MUg`9T>PMZD- z1prKlitPkmx&~t{lSR8l5w^#QR+LheL;c@1n4iJ32;@|~o?&IHQ*Evs8|+6<>af~V z4R05(n)`mBVt~(j@XJkH(VLS?A&qNIBj6pK0=JZOy%g4eSOdb3e|{zBe^?Tw6L@Fv z)M?%A*{cw0Nsiw^WgMSQOyt8}#kcP4eO&xDiP}7Z^B49r%J~QIQ<0v6EI%=FrHP)u zVovS9`+jmYXw8l6z8~N%{J;QQDFRmSDrH}5`Oy(mJJEObpu64;l`c4AcFO??^K)~M zL+zr$%n$SBt9ilkw>!?sn@7G!-m<IsxrZ<u7Qy@oz@i$(_{%Lyt`<F*hfm=DfG@}3 z`MHm79CbRpfr(LTu!65ZHyrgoG<i@b|HJSaPtXUHZWFf)2U#_f-S~4d{acJ_#+&rK zf@)8l)fOFx#*r|1Co$jBOjE*g_l{WkMj~lt(#gh)B+a1%<ZB{Gje5uK0^k6m0)*Fq z^#_q93ErPYq@{5ib!YN>U7;#Yn+{-o?zugu@Y@i|DyS63<*l-IFSy)Iq3=gXIR&Ox zsGxp`#0+a%7h;^`b>Rpix))&Z==w)|AM<^!|GbJHDDV#1I$hrzBOFwkr;nb;YHJQ6 zNk2diz2#nKWxZQ?cOy%RPUricLhq8I?EYDzwX!*Kr=HtJkIZAZRpUT_)WdieUKI{_ zYLb<4*<#qHNbQU4%0i!|QQR&yE<52;I#JBY!sJrgTM#Qte^bkddn26lq&shY*|V@) zH_7Xs^|>gKfa%^AY(%bBZ>$svK)bj_^jVgf+#`JJAJ$BYE>W2%b^NM&)KUBVKIdh+ zSY^QQlwaF`Xl4L$Ce4_K!<)6*=X$M*6`W^=Vl@yv{ozw81++!%QQlIKu}Hs+<M}lK zvM0E~S^?A2qVY`fAJ6Q8Fu<kw4SswW%4ahi1su6E_~_K{Be+opddbuV$PC)^mcqqQ zb#tPiOQ`Z(fVH^fHK|5MngyNqm-D81g8e%?_V~f$!efsyFzR(Cr~Qs!>h<CDH>3Ls zbAsM?Efe%fq_-kf_PY{>2mwgb3%Pd{v_bHTQ7lR8&x&llqLyD|sq?DZ?<z;TFQSjd zs06b&3^|Tn3#I=U4g2oxgr=q(Mf}u9f{QeXIId2Ju5Y`m<Zq~yyq#SP;vygTVQ9Py ziO`8v0g`|%f7OT@<M!L}C5xZSFC+g^DxY-&qS*@QC`pXA0XX2kYgz9$%)<5KI?PX> zj7^>)9!j<#=(zm<s5RW{Kw&$k_mK{P$xlDQ)%u-dp+A#X`*&}A9M*HNUk=zGaE`0k zXZ%X%(pkOkPF)X6y&Gs}OgtOu!eyKwFZ5?xnBX6Xia8TegLLB}j~}ML#Q%9F(aU3Y zqVB#_tRkmo>`0mF%mqu>rP|sx%%%K570P=|R8iVg)y@S)NV<JpReYe;^~;KVY)j;w zJic=I5BuyallnB(QJTLT$8QA9EQGyP?3@36U!l|-E;E(s&E>_J_;1MQEFK=C{~=*k zBmOxP(BD`ePiNp>evzTlY9Hs61%!%5KTR9fE*-fEJR-1v(Vga5z#+ZsZ5!D7)}xk0 z!HGunQ^oaZgnP|y;1SHKMn*T}{DtuMo9YR02y4+Le$R@7<DGY3J1{=9NV85C=R}du zbfEa=p}Jlz-?jFNI$>%)D>^G(H-}F($1hZ@{$-QJmGP&vO?FDhu?o@fE)14v6jmS3 z8@q*K0DRO)b%A%~AayaFZHYfuw<$>5zT;O~zw6%?<vZrLxmnqxkF-!~;SiJi%PEy9 z;lhaerr;ElhYL>9s=HtQGOHeHtu=4%UGbWeF=v+eav6?)2<9~(N;6iGETE%1P1|#r zt@`_*zRIPfBN^h-L{Q1*|B3-=He=a{cLOEG0EyX_KJA||Q_lRX8g>Pm$}FjWY4?LO z^SaiPZ2LmD`CO`sWrKfIKm@n#WG2a796ncjOx+O>*p#I8W5>5w_Dk1WG@PmYMpOVE zQFe8y`k6n&Ti1y&mKc<1ICznyt(+LGdb^^+Ce+a?$yiIlGVIzVB8S9D$44{k2ljPl z9*8y(!JFth4wA8~&DrkPGdN@nfV+#tB3<4{oI2%lI2b^#o0M1#o;b`&_Z-6C^@3wJ zVZ_Rc9{n?+$y$w432Rp<jljZ1fz%L-wj%l)^j@RJKmX)|833bub97>B1*e9uug8{u z-V0X#^VR1MrZ(;RFBf7KMFQL`|6V#uCwGU5*oyC&pCrqbFr`CB=XkHr$(giLjyugE zsnyV*ZQtS1R&vBc^}+qjEpD|vgl489KNj^gU(TJIB!1#>$7TD`_~Uk)E?&<vY!?^V zag2c-!L&ZpU~=hpyo%51l(qIm`8Jhe+uv8uk(Ii7tR8x>*we>JB1@J8;DW~K@|*@e zxM}!nAXJfq(awNW8Ztp)VmK5gpPF^v)wrh>IoQ(gXhj}ZH<3kh%1`lEPx=}W`&6ja zJ?!I=mVE=%orLy~!QBH{AXa99^xK_RrOP8-&uye%jcG2N*&yez{oe75X5rY1gxZPi zSM7U}$T4H`Rft-$%vHW;BsYihhHdMkZpX|L2hDEv({b|DFXAuP0t+<lX>ur=@bWkG zRC1eAUI>{{$}N$6u2RT!q+1F%{*y9r^!aI2jvd-q)Mq#VU$Xy2^fcq^&vs&2wWAhr zBj3?zwVM8n&#p;g0xFdaJYst(jM%uvj|Qse$y4AreTVgR9;dfI{dyg&1x^hR_5a>W zUq1XUSc`yUOk$HML1R+~J;tTqP_LI;HNzVkcXlE**qVT-Ju_r<T=oVk3RH*CPVBxe zLD{8Bd(z6$Ni{aiv>O24&WAa#mj+mV+KPw-&;}Cpco9m}Pj!o{<h)fDuL3u4-F>?% zRu%mD$~Q#XT+gb1%kxB+Xvu?9ScY%|J2C)J2&sSLSSq2G@e>HST>-(DU0@MadcOa0 zgx-Jq;EMgLqgY%NLH6XjKUw3vg0N4)5g^#S`whM(h`^t3W<kR(4F{00T67#@9h&^; zASyl7NM^F8XY2}3N&s)~*+lAlC>hDqpG!|Sw_xJb`dOG<w71HoQI~ZRJ1gHFY(gch z|EtBfleR|F5YqkE6#MqH)VdDbgWtAZlMLH)M>QA@V2-(-mGw1u+W&&xj$<=e;Paj> z&gpN~eB2fm{fjLFrg~9!Y^~yE7(E(HSvKgkW6T_|GhvffzPfZMIww8>wfZ0Dpq65w zonfx`3G?juvwBCz8BETnXjay^$EJN>p0$q;-d7bM9*|^R9<8LDNx1)_C&0pk<yb*C zVO|A$w|x3GsIa)8>a1JJ%w1REi3vXC9A1;sz~)k;LAoqqR%?`tA);^gtMW{G)V+3{ z^F4l&tD`e9!@N(9t6OSXBs(27?-*MHNDTUw<5Jp4$aGmJYn^T^FZLu9enfiS-_v!o zKOU|L=qAx5p=D;@I<w*|aYPoB9uCiseQ@9%Bf;8B0+R(|t|~5d4e`ZRJ+6+e;K}5T zyaBH3=36LLeORz%?Tk;sFZQvFfc$8Fl9orklQbA*dv#de+;Q{9ufJE&i_KRSI`(rn zaXfdXS$wGZ(A0x<eaYH=e=+!1Ka=z-Xs*P)RRZkFT9Y94;zZf`<bXx;Cu`UvZ+{X{ z`^PYaN@j99tN86_QrEYCjPYi6qT%76auU?_%I2;?EIi0>49VD_dBvgtTb9S0!4+aY z051dNR^dTS;*<6zvX~9NDrQLGbIkQk#U$mdM2s9k!W6NS!u1D%>!H3~o}(Jr?-hx; z{lv!Hg-aYwe6mC$pT_G>BSWVQUUI6gKj~Ngf?nx|$K0k48R0>K)J3v`dGb&q(p=iE zcJt-dGznZGo$HO0pXz7yDTq!qPnQ19uDvqGUUHRuYgxKck!Z|1nyiq*1~HB<a2*!* z9GY+Wq(b8=dPO26>c$qzXvhw|voE&a59Berk&w=7cuW!Am3Wm>$_-JW%%(R|nAx&B zcr)oku)S48ZB+vKx*LCa@RmRVGfvK}n`XLkZ_<ZtZo;YorEP99s^lp3bQD1;6Hw_# zyPwi7*3nJz5n7q@^Hh9vKl3W?&k2<*_th-SO>!#sO<I#lwh1;!^eiM{G|MZ=YlDa; z;4w>j87jE#{DtQ(%C4v7{jD`v<EqwC6-tHWSti>#Wg~^*k966g*_rQ~Yv=#AMruD{ zUQRAn)8bx0+oD!ucG9jber8Ao&k?SHE5pU;k%6>Ax<9_|^!`JhKC681ioHzuLRHNY zhKo6=;wd_Kfi@$9C`vA0qgc3rmzLLD5e3=V5S+CJCB=J|LiSP9-753MbaU7lu(I^< z5}#sn|Hil<)S<rM9AM#lM~t@k?_Ca|!4<Y3#eF$gY6YLMMMuTJhmQgIIW4<ILn(@$ z^b?-M9{W2iGVsOO(zN;l8UH%ExiZ=PBac{g(_>L(<o{4X6QqiJk7Z_oSx2(^esl-j zCF@bMth!;{rPQyFy|qg8U3%H<Um_ZV4qmH>orhB|k(64JAw1p2Lqt~TEWP-rL-EW4 zNq)9bQhq1TLzl0{7K17VI<=-$hs|E!gfc2xM1^IgXf!i@(TPXWg*{v_AYND@xOOC< z-^uvHS($>L5E`Li=~N*|NNj)Elcf^YnfEnW*yRrUbtGA|P-N#W{rhx3!JjW*|M8?L z&l965P$A<qUuXubkE8*spZFpNNJToklX`9h?{La;B5N|f=P)ClV`IBfE~M*caI0K< zpT?G@Lw*nCcLOL`OD-s2CEH>b_xh6S!s*8l*zBY;8wm3Ap#YR=N^h;m?%q5+ImOGU zyhA;EU!iCf7F&>`PExz(Ad@4Fm(IAsKS7p4(jN1?GRYLfuz?_c?;SsQCFjuh%qjt8 z^fB+(q@Fq9qTI6Zc|0;PgeXO-y+=O-eR7+>8PPT1&z&3$Cb@)yxQcD!g}am<s}(<} zJF}Iz4%CckV~Do-Mf#G7{<mt$4c(0o-Nu=uOrFLLx{m+q@}4<9xYGd2aC{gV!j<~c z1k6g+BG<a_u~~T5tn}?`it<cKFK3F<!QNA2T!a-73^AtIX=-h8$(%otBT0sX$Q$n3 z-9LP?nWP$+U&oRj0ku9$7RyQctcnt(xTG0EWoV;4zXU6#H&OA-Ol0_FjeYpFuh{+i z%)TIpZfpZ?Ee4Kt{4wttVd8kMB!lR4f{V$&osBHLW(zAd?DrVv@$~PAXN9Ej9f^|J zh_KCnwbSVVLV1MWen`)?L*<##2zlM#e#`{34X|oH_VAsoy0egA)!vZ@BIDA>c(7d9 zXUA-KEtaE2N>O;^Ov@g@cWYM#G{>KAmS{Qk>jXBR3!ODm8za{<q~cc_a~I={AkoW6 zcDqdv=}ZeEtIt857i2^DHxCaB5wHa0LHu}z_;kDf>S64T*dSP>zbdVG9RAqC<3UAK z`2@9$%juTzaK2agGS@#|$Fr9}+t#`RIx=s6HM=qpP^pFUHotP5!4ra^azcxsXT7W> z+0_ms>}yH`GIvrGELAe@d@F%2IeIAb0`HQ6bIdlA|EXdcZ+xCCOee*FOdLZ~6lZ}X zx(^mfAw56i;083|1H8^A3%wX0&bSCroK)y93fmEc<x+2wn-|M7z(mGEX4CcyEtfpU z1uO^o;=Y=B`TEt0<d7O7#I1TZ6IH?pT?I4q1{A|RWyn9+$Y6s$QkIw#<)yiLUE}V> zcrdA5lKh&|V2I<XgYMrMsi!K-yR(2SIFuc*nR(19U18Gx=>Dyxw>B?j!~VguR3e4S zft_nwS+LCRzN_bBLoW`GuCwgq?*?D|b)P>**weV<7MS$+eLhu0Z0<LV@i=Y<$3J<c z7^U`#dP}XB9m`GxE<&PNu|d+46L;T#UiYF>C{^wP(p&l892+L;L5v@HCIDMw4Y6fX z4=LvGfptGFuPMEUr~h--;G@xa!-Yo~OWP>-7!tvXD!b`(N==;keRVH-hi>HA8^S_R zTk-0>pxakoWeQ5o*{R2`grs{c+X*m+Y<Ju!B`gT8!#_oGSfsF3#^RH7t(iva$=rSA z4L+M^ay+`5!4qH;;07{*+fCE<`Ba98MzHG5r!Y{Wugvk2V1;)N0H0tyr$^l3g*0dk zNol%B<=@bp%9KwZHl*37&)~P~=4Ck}c@;!)gMf;@P|v4U>y{vs26TssGv!w=C+>nn z<IsI4aA;5Is2VOiKGSO8)G=ER{-V*HWF`#DmF;z4b4LJw`>Zv_2k@?Trfpstd#XfM zCs-XWzY~Q$9t)u_*jNWH$Mvz^6{<U<dBU@1k7WEiZ=R2PU9al(a~YdhsBi(wM4IHp zogG(^?5a?i^wl$hM5V`4Ic2K5>erU&u=q*fX<z8$TeylJPzhCW%bvbH?O*<eKf=d1 z=r+;c8N_IZAfWb`YWytTxlPE(q~uAz;fYxfSXy1dqo9oNLb6yR$8C6NDD|P8NdM8( z#1N>$KD94nnpr`MUXQMMC+aVn@*l$SLE0}#TsC%nuYD-TW?b+DendHK@K4p^DA#W= zR=Ne#{{%tI9mpeLh6dX-3qKUzm}FYx7AOMtnLRtK=F8uzt^zT|n-2wzMEtuJ&(Zyv zfJmt`NH}W3lVRl^+C$~J&01qS)6pw8YO?VCm|vZwo3VC#Hc78VGZXRzKW|mcl_Qh~ znfnG;r9u_+yQl4pPA0A7gbDs$-<S8f%TO(XpfcoLv3PGVqYSgm9~g>{*twN{oL%!s z5Vt@}P=6Z{iqwOKeD&`Eq73=x`ya@g2eL$(QIlIO_4<Byd^1H+zZa9BZz}e$`Zo4} zh+4>QGk)ElEE&l5{0?Jcumcdu7e#N8NESqITbw)u?nt&37%xMDxODQ@7G^PM=+T%B zVel54@`K<HxqzzDe{?VlxCNqbF<IT2a|HFy=o-%vd<0HHg!2u}4MIGwZ!v;8uh4^) zG2>Etzkegai^{@<Mb(-2hpEikgy&ndUdQqnP4szIqUYG-l|iDdTc;SA$HNOu^gW|O ze`G-#He~S5x0Na(bgQlVWQC?w@LIb3POtl7%P|u{TpO0`*;eAG>Smt0>CD&7x{gXO z?_E14h-KWE<=XGW5nw#O2QpIskP18f^apH05)lcZ{~F4rR@RhSpsb2#75hb&8ZJ4R zN$goY|Idd5!7sI7iA{!(N4_K&@|;A+<z2bvl?8y>rj`g+Wyf0r?-WjdiXeot{qf`d zycOryK_++Qb<$~I&UO&{81hT8KK}^bGp2gJ+H@$3^{5fdUc4q?MlgU+&f)W(jPist zxDSo?LIZ+K5kuDGtact2Zm+D3b|sbui!+Z{%9w0BHcji)xupxrcUHK@C{i!8JQWPG zJ$lgspWLv$hwwdL1sw#vDPCLqhg53iOH>l@qpjp-a*pEMvUmMXd>%^PuJ}IMFY=W> z`A5{=zdL;n*ExWu&m$BD>i9oI>=!}YjmSdpX*Xo&^rGnO(SnE3j4Ds=u)zaEUC`5! zM5X$TMo=h0K%C^w89tZvF9OVt7oa~fEQ%wy)*1q)CDCRV?_#)GSQYi#3`Z7>K?Q7p zev#OF_w@pq^sjbipQ!!KLV?7|`kI&b&L^pll1>NAk3Pl&Yg7JbLsbaUO20Ni&1h_L zEXgGqcgfS2crkmS&vG2c!tFSvps~sBMC53OZ2Q;0>fTi=1ne9!-9iR*9QBu1-}q2t zmOA0pt?_apT=2KFkpa}UZyl9e>$>zro}h&XHfLgT14-j6GWC44Cea|4XUq&g^$zoW zbaezm<?trFL8C>lbgQZg*lLYkJ6$0pgcaLOl&G1sO_;|DVGAJ1vyD=8kF;Wn!fD5( zWKy;OrA@p4_Ezgy8ujcGz^&myvSWPJvKQj{wgW*UkaWi*myuPsorA_)0n$A^K{?(- zsV~PqQB>$9XDlJix-T~3iOuv{%)vGZI{X@9ID*=lKeDC6^Zf2*&X4MmGskE~mr(T! z4>alD|F9>VcwA`7T4{f3Airwr@Xel{WXw!PnqWtg-|^Ru+HU2h=A$7{BQEwV@z0&= z#?k7wS14&Lh4Jn+h*sUk(<2i0Cdtl<(CWJkF%jlAa{eALMfK6ORuCTNf7JAj?gL$< zr%cMVJQrUS0qC52zUMUN(&G;1Iv#MO<kc<<l&ub;>H0AwlTdK-4*s>zd#a3ij{<Z` zI26mi4Juejusg1r#9o4i(b|m<6l2_*@M?XZnqz}*<GV`>w-yKbMW_P*ACZ}B0%E%n z7jwI;d~#ej<<~-DgMN6H?FpQIC1B*$u%*C0<d&3aW%Qv^wv`S8efD7GIk~^O!iz+C zS$E-pHmL6F`M|r>2P8eR#{G<CbK(@Qt__i2i2pS#FB5@G3gd^3W8eYx|L9yl0MS1M zw^esrYeL8{vGr1gIVp9b*dTXXbe20U8_P$i|BUzq+iMrVKJ@~*;YC1_b7i?_e^c9* zN_pi!)4mk*0^|`7aF3<?-A?T&PLK3hmp1(5wVYfZSW59lF(0~$61A)hl+Ef}5)VJ8 zHW}mg6sh%Vb_fr2zH4(zN3spsM8GMVAd>sb?8?^F@$fgKJ%{oS_MEE~LRNAsVxre! z3CfQoVz`+|2<mB8ZCPIxHWCW2a{&GZr&)<fQ|4IqkI<jnmo$v>iYl=IPvtE&v6pYd zhUQ-;_Wd)l(r7o(kFA`JjZ63Kz@SeQJf7z03<MC|c{T>d(f_FH@PE9=86I$Xf%+hq zZ}zns?W?wl5Kd{MMhrlbM9dq9S|d~Cx}0?4u$RWe=y2U!`pz^+Qr<!FP+eE_I^QS0 zTpyK#zVHA)!@x%pNXyB;omhovBN@>0fE{a}YNLiujTJ*$a|b>=D=a3qst8t3+o$Ty z&(E0f{4u?9(JHEV_0Z6WfY!9FFYvLw&Iy`S?Zgj|M+#PKG+h+tdW%&JJoyqV1>~8k zm23+R*CZtJP}W?beg^W2Qlt7Fp2g+?4hNvL2^xQzJAD&AdVsn?PsuEK@%qFbJ(Ezx zh06A?sz1PQ$axNleqvrs{XM0tMo08&a1Rz@<34;Wmo*Fl?1028491&hq0!~NQvaiI zKk)mlfNOQtjUdMOg#KT=;}95Efu<EyJ{vD=WUsQO`TACj*{k4d%xe<&_fvaWg8;A6 z{Uk!4Zu#Bg#~s0dB-yd6Z7*T=08?$^!^tu{nb}}x#UJ~vzUsCbMMZB0lv|oF;oyl* z>}4r}nw?FFxFm+2lR~)8l~lUT6N#hyKcu~9R8&j%?kfnQAQ>cs1VyssOp8PTK}0~5 zj7<;}$(fd%a}LrHB<Gxi<k%nrl0ia~Q<EB+?z7nLcfb38&OLYBF>ZfwI0V<~RjX=N z)vRa!p2o4~;Nw-njV;lbZwRcb<|p6q8yFnc?^w2UA5d}{A89G8799%P`Lz)-&3~4i zwq#39JU~?`(BwCtMnBael@n87|6P9v{V7ac?oizPjnUQoY4VXRDiD~I#YKQ>H2i_y zc*x4z;F!kb)3<;bt`h2$LQX!ZH+()^iBt6Hy>2*^I2*(Cc~?J5aKm+_Bf>9z5M#5p zcrN<T1o!SRM{qxcB<?+HxDlb+I_N7_i4>!i*cT0cUM-!JhQ{{SmJbA3UkD*Z7yMS< zuPyqR!Z7+Ioh1U;UjAVrS!s+{YmL%e#xr%lG^$zZ&*uo)G3hZfeOUtQ2iCt(`ck7b z5ex=aZ4#7$hrlebLPcFWcs$<Dl1v=6MANILmO0CRah9pg$FlvD=L=Rg$4GGANvq<L zt{m|S?eA0AZl;hfV5+8&Hz-C<ClhKtsGgqIyNNyB1L*oRAhK<GJmEbcrkmmo4B1+` zZ7xT;@j_*ZKsSOcAA4dEy53;-xB*~jo3gGT%juPj!vIB>PqFpO7qL>IO92wCHF^5J z#nHC)R(c>sqc6I?f(M!d00jeW0Vdi=QQDPQF{=5jRDLQAUy*BRGk_vg-9y4P@E-mv z<fJ2^upo<HIJ*cE`rH%kjU^OJn3TW%PMr<Ir=r*Td6tiYp(W8Xl5zu>V&{wd=`i=X zINo-KMh*$nVT}Hhppn`WH;l0YAU8gMwbSrwkDVXZyF|(mRO4GQVrTO69W2acB{?_v z889UTEKlDRp2BN9QSc9P61A6K^w%HY>v*(4Sa3o?(dBYJoh9(FpEkMT8+BR#>A?|Q zH2hSvQ<yRcIfpO11*naad@1?Nh8iVENSh8`XFkB6%RzvQKJRH~?c5Q=#D=s$MsrlS z_nA;SsxvAZ{m)7ELDN?bcEM#q%O>i+2H`Le#$SLct2SvgBHLiIgC}(P5?902QA&%e zcNa>qeMamZR&_$bTBAxyzoOU)!q7XTErjn;8UVF=gmMm~xw3cCUt|%yjq*{$6pP)H zK?(MiVkdj+{w5t#zdYhlhbkR6p<X4<OWJiHhm0l?1HoRnwI5iV4^yS-<oMNM4_!Z> z<IiC3WMn#i=Pll0!pI4sTg28bvpW!(`0TXW37?(c`WHyb?(d0Zw<jcnG+0jSZ=fJX z`YeWa01SiQw(P_`RQE3Kz;;|UNvpgdX`-umYTj+2Qo;_afm{YfG~Z`>zGlx}Dwqq= zS)4C71xLxH5cAt=ORw<v?mcD<O=w@q)8!}T>ya9|0*b6<kt0utHM)_%sc^rHAHvL* z;Otv%SfQEU7jAb)^@CixH{0;3VE8@SZ@w7emQPrQZ?avv_|8m$FX#wE9RRpl%~bXa zG}1~xn_`&1WwBF5!Q~y!Oz@Y&VOWP%W#nHh{AULCFwp)^(o!tn^-&rqHxE;9_HqfH zdS(6n7x+J*Poz+A6JtH-3MXTrQ45fFgFitUNyfZjznyCuydz%Oy)&tawFeUHTw8P9 zAl8icGM>RHuZ49m`gbcJes-c)4D>OqG~H{XGECp^tz&;PHc;%P4m4n_1T%+EPM?b2 zxd5iigoX67PVAygX^*eje3Rgxx@gQdTSQq;9$qHb@a0*h^78|!o^3q&7UzoIUuS{# zo{Ya0#&Bv{LQL$hW$He7+n-;EDiDZ;^4+hzmZ>B34qE1ya$7%}iDMy<_+tIG_aW-- zLYBTr45fc~f*JEKP?Ar%JJyvT5p#_K$wyJFjuvxipp@RH%Iel#xREmugq$XO<atuc zAs?gA`}l*^cuMYBy2u~N)PvD2%dg6??JnWi64r<2=cgVfcG}d=yyq6+w##My;i=p1 z#Ss}0vdcFCkrL|gAk6?C@tspx-cu28!nbcJqB!@uNQ~aG6@M&%t``TO$^toJ0wd@B z(YDKo=Rv>gsb&1C)E+Q2_Vb=?WoIvRX$twhObaZsqb>ba2o37&zVeUaT)~&Rr&~1- zd`pTIF~W)tPN56WOY*uwyIk&emv^BZ_%eQabrS$Pg2q-xxGj-o=B!o@p5H74)ZH;O z)n;h}JM*tta?AcnUq!SLkAnv^c7dhTG3s&4x|EP>SgRtXpWhW3gQawp<UI*@QKA<q zKXT6Dd#;`bkJZjOnd-R3fhsVn+%we;IdDkX_hxD8Y={i*m*R{l{lc;zh2P!J8>lBC z5oR=z!Y6ijW`e!+(8zb5bid7{&g*}kr^-pMsB$H(T>0732qJ8x_gprGlYSTUzPT#O zVI0}hsF3_KvuXn~E9#l8wcA0$ZW1@@;p~H#Lvx&be=&avQNXI|mGKz0@?TKY@NrOG z50A6c9HgYjUhre0sw*J4?rcFm3Z|;jhRpr?=v$Laloo%>L2Rykat}qPBR$FEAi1)= z<v~(decQ#?Z?`}{Om0dF8;N4N;^onzYC_n)zO1xac6DXbUN_8-`u5^0@yvb~<<#%o zbC;&le(_h%VMWVMvx*GZ2IP(Bg2_Mfb^whwLDkQnH6eLGH!`G+y1e2FFH!$Kz_U?w zYN-toi@=zUZZo@o!gse~Z*8{Kq%hy{mNtxPJPH*GYSH^_9@Q>DYS(Ah5^nk#vKOeb zZc4S)&YrEY{zT~!H^x(9PFI+kQy6aB>G&a{?4Zn-9YU}1DEB*CTPUej?lz!KR~WUO z+DrvN7R}~my#V*->t(4=A_^dgFaSiG#pSm{Qj~SsNi)>octC@G=5&XC$Kg={nVnF; zdpf`2{cif#!EsaJx*&zAHXOtU$q|MczU>eVzzki;$J~=baLZe2iP}dN!le88WArzG z#H9pi^{bH&JMR$*4$MWQoQ8YHnYsKLEF6tO9G;u=@DiMDx|fQcdh<xF>X;d6FxNtu zFG|?()fA_MD?}^lIUxpl$*m+)bxemjE4cJuCyo{**aK6^B2Eaj+j@fQDnZtgO0bG; zCz)t2yX5U~eWsRZZDT&?k^y}`h_~^X&3mKl6Q#It^G7qAy>GcjM}j^@+H}V=T2XLC z8Zq&0*!-}nKRpfnsa@+vVm^QKe1kXMjVS3iRv>6-5=4+Yss9D~4m)y9rutJFkZuU# z^4nU_v;5_{GV~$x6y)>l7Za;1$Z?xx<$E#(W{z}af-$HH&mz=<B@zHZpB#MJVs;E3 zNV8+=0b}KUR6{r1Qr~hr7c>^;wYF;fUUWk6=&gy7_0FX`ZQSA!Y(f*JU*=v6cOL+? z<>%?qdOvINt0*5?6Vx=0^D;v4f78t>G;59oFtq^R;Q`eZ0z7FylI~@pb|vtq)59(- zz9pE%YP(j|y&9>8O$Mc8j^3gBo6CC*4-I}v_pw=58BDzJIc?E_St78ZRk@YirLv4> ztZ>54NQ(GkkQ0#@DWI*tZ3O$=E}+72Ov2t$6XXbg-qKT)5p^F@ItmVK#4irGTd-UB z++G^3H^xA=gm32PTM+R=`^;zmXGpwcy@)v8mTfBO4{j2$ZoAC<c4%uU?w#_xRav*b zC&M$3(wux`ql3bBC^>oW49)73jyP2CA_UU?-X;^UuxY2w^VfZ0eo#AO^y=*H%MY(f z$8MUy6=^htQtzkRGIYIi!BG$mtaYb#-q7mu<cxEESR50Y%@{mjTM44E8>L3SFB!|A zEcacf-;Np|z6<*3=T?vPu$J>7=C$syHVIs+!}S>$RAz^{;oHZZeQR4jJA=q_LO<Pf z3+iwj(tNY>kO<Hvk4?e#4SlPAa3Xk7X*Fd7B*}xj{JY)dy^;}jx`Q|^;|q`9WFMY) zMlBfbBB|Y|OUJ>yz<D#F`&_zN!dQ{Uef>$!QyHA8hQ=YVA^Vg=a)cAfg$Jwq&eO|F zF5LGQibJzX2gjL7u!2T%La`C_%&5%mG|Y{PV<O%F43o9grX;X#Bvg4mrUMn2q`cIB z)Qaq(<(GLW_xQ(&rdPaCLC~e$jthPB#*OUPCi<uB)9{{^+fq8319G1lKZxQNe=m3^ zv$9ce;@a-=n)5f!hN<+ND)X;-Boy=G+0&n`3s1}<Yjm|K+Rk%3*g-*^MgeYMnm&R9 zx_8ae$PoL%C^I3COfH?wXT87S{l7d&f1(}(=lQ2S(C{jcTY*EKeZLs;7Iu4DCAMT~ zb|;7jKxG~MPNBL!W}mpZ!ar7sF&Vf7T@erkRIEQ6+Ikaw19T^-{0>7ssfI;qcSu9~ zuR@ZMc#DW%=AyU<@fM9<-)*~~_$3El7;4Ib!o8#cTBJCw@#Hx9%36MJ<16Rx)H`AX z#Tt3je5_87-w%dkYn{-#m;i&oKj&5h913dfdXp6cd(U4tP=%guUj$jqn0pKme#;?O z>-;;d1mqKOFTRDw>^AtnE0wx+)Ifrs{!vr?xuz(mj??%1$&z+4kP{()Z&hTub;vzV zzmVO$P0jgzU-;DB&&2cceX)@yJlAw@9f)#)T^>URK^+tU?RHG{v|%&O+20-!bm~tn zv~Wf_@^D8kJn}UV8bv-UmaTjB7A$Q@+4T%p+AyJo)`(hze`{MHLes&nELJCNzUd&{ zpD_Ggm9Lx@VXXiol~No)_p`TrW=ByJM4m}0-^<NLsYjIXlPq=2AS%tY(Y#2SkUwC^ zu*AOrtn-o#QGQ1v=kY~OqpnMWB7YG%=fx26;#43~gsP|5GT4u&3}bbYDFJ>@-Jjxj zHqm~2r8qccsiBNkQ5(0sGLU~S;v^;Cxp1q1@fXZ{*UB`#9H26PdYSB?cCy7!?Si<_ z>b)&qy5wXp{L{@+o8F1=GF}VNH)qxU2Drh4{EDYm-Nrbju+sshR~-`|PH9#0<IJpT z8E|otkzW0%yCD^<(*1T}gA8ZjQH0~!WQVu)5?)mX_AfJ@%h&YTltoT2g+%d%zVC(7 zB*gdX2&3W{33`es%<F}()X$D!oEQgNv$<{RwxePZ-LaORB*WJJ;$~k8Gj=&XtIOQV zeu338b{kh^$zp=1aDArqW;LzRl<?e|{v~HNUbhzq$u2Z$rN8^o5I6MqYg%_{1E+me z23<lgeTC85SP7(tD(Xz_9IjiT<WM9*9e`ijZ~Kxl$VUA<H<^dipuxkakcLn{;;guL z3u^ybi(FMTn-d}M^3~MbkD9XFe5s{WIiTxBv&DFz-IO$}0dEkxw`+jjy(G0lq~rEK z(bgh%AYK7A;h6J0f0?!CnR>Rp<MGp+GnFoh)03AD{;N0vqz^7{*fZ!esEV9t$2~Me zBZ)145cOMYtAAxHsoYQ?d5ogZf~38xGDyF)r@kCNIEkK$(Fy)b+eCG}=o!PEwC~X} zdL7mvb3X353-ywDQAAGg`9A=7hlQ{Btv=p_Pk&N}CCC@vU*#h-+?K%DCXtijbG~k5 z&UjKVIw?HX(s1(VS}p4ov;JEMXD{RPD^A#b1I1yRy6`XWm2cR`l3EoD=<_J8vs{n3 zXni&yX&VH8JGdFOUwhBN>mUy~1ELep%I0Lc`3GX22^pcIP+WDO^fYNRKJ9*{ZnD;t zPsmSwuxtO6EDtAEq3mbKHk|p+-R!-pHQ>eu(b?xWzcjfL*fZd<w+5$OZ1hlts}0V^ zcxLBm2t4@fuJo+HT~ALZ?YFWei@WuiP#pi{QU3DldKsU^@+H~^rQV#Z(eh+mkU@gK zz@O^iq_;?!vgClX<)gCm7pP@uvs&G<Dh>I8#Jr%rjS(fO2ZZqSTVh&FV7_|f?q7E0 zT|xQ?Sdd71eCr8LP5RNOvvq~eEeP$jl+mTd`r>_mc>(}<3}pR)rU2}K@d4l4;cvrU zwr^F7q3c?hp)+E#r&$62!$AyK68|(JJ8Y4~Ssgzh8(nxQq4)<{`d?2F|LA7yD~G~! zxY~63NhW8S<*^`e7bMYN3*0|9TLlc$92P(pp<vsgCG#lXJG0kD*+&fjxJm%97%o8G z84cMp#+CN)zQ_Kbm+`lO3XpF%^g)ZmuN-3kSQlJ71pN0wj;{^VqMNUA&j0WKc=wOv z>?}>tvr3Eq-3!j*PmRd*h?rWebSK~n^6zJqlB;}f`=0mzhjDIX|I)SXhz7>4H>drn z^=V#S-o6p}58k-{+r5|zj0mW~1h$yF!e0~scMZU4ZvHjV$6BvO<k!PZS(-;^=tX?U zW9zb_WKGv4bErlH7}377eK`LGxmmn(R^y^$uIJKePUE2om1yLu%=6nz(EOR`MT1GS z6(MFMJdjHNH4vTuk4eq-nZ_T8N%YUMr~MYn7Hi4UD2H6nKu4W5L>}aHydg#82bg2N zb{sIDO_=~_lOECpJ2k0fC6H4YAu}cZa|>ujb;zO3p!_oQ%KZm@rR6|0VEFUjclh7y z6BuD^Vzbb0Wp9mpg4gUBDupT+9vYvy+n8>GwR>JAd9?htnh4aqHGPX>q&7pXp>e80 zhiH$GbDy+SYOu-U41l^2R!9wM{wU;06{u<^8XlA4i=*EZI=g|J#LWL+-zNX)zh4~C zm{dwtkjd}kQxX@qUxPpMv~8Wj1_mBZfjn~Cf=fIpDn$XyB#zyiMWMNB$7u2Tv}_JJ zQ{R7&hCf!3PhYn2Mw(*MOY%;HTbv1it7Oovrvl~}ujFZlw`YlGV7)ty25501cKQH_ zb5L=wZeSPAzkBANPUxTGZLkUkOqxF0(tG)|1fDrlIIwSgDn1+b-r=NQg8FUqBSb9d zZZj+`f4DrVtkFcmALZD+0?VTSb$(BuVb5DjC9S|N?EmL01Nr=2XieR*=QF5B5%8vH z>KE4FE;-XZK9UROmbILeS5=%F8xP7-frrfcpC;9Ru?Manasw(C3Q?Em=zS%Y>)z$g zklE%NDPmN;>|N5r-V5qw2|ZKHOalJDZ~p;Im`ep5L(8HNJ5T#3x?D%w8-MYi?mW9{ z6brqoS`qg3#x)%P+SsFo!m$!n)u4S>T*&hiz40rwo{}k^uz0EfSrkNsi&!O?;W^E3 zjX;P@cGg|e26FuWn85*O$l7}URG3`1AbmGl{PJvj_$aZT$Zq!wW_nFIZW}5{EMkJ; zKK*5@!CcHK^fq~#-N!aGJXb9pt*6VllL&lg6kvVF!#VIcW|}20H2%4>-(Ml|uRlDm zEg>UgTYQkbS<GBF%jK+y;#&?XQW}8u6wp1jT~di^dQ2Q0hCxNxkud4BoC5^xeM@I= z<L-rFQ0LiQHj!A(Ca!c!uN0fBD%RtfInMdoY@2~->i!{&XG|YC%T4*zhfT8o2~@Y4 zWdOB(Gek#bI!JA}xT~6Y`h3d<(6_VgLA&>zyc400E!{94W$AHw$&zABq!ieGXrD=F z>yT$@ToZ7sa!5%q;3pp29gnM>spMHfpgXuZc8&aIqm=|n*i;0r9JKo2>}+!K*SXg} z_sn6tj+dHbp^#ebwQP+Kw$zThBm2Su9=qCWsSw3X>Y?{9(1b~aC%htDwO+`Aot;4d zJ}fI_>mPnp67$zJ_1G4Zd1yk!3K0ta|2)Vug}<Uad&(ax6=2JDyGH(DNI2yt+slX3 z!z};&qFsz5M(Wi#fxNeJBOr=-=$|8?hi<q#gm@iuxs(Nz7W_R!y$sI*@=a;%&r^S9 zD@FA|STXd1=4z`Js<LN407E$S{~TC3kiJ`>ekg#~AU5!@3H+b`eVf_Yei3xGHBqD# z#b{+^g@E&I{VW(C&6N9dop%urvUqU6jLBcXyOfWvkxkDNAv*eOM{ElUzl2J+210&P zSuqw&y-qa)BdG^}4yJ)qaT7T_juQ%^lLq5M>eRxT^>Tfb6%t7~cwUM|#TUHe8$ZtH z*4o<O(h@IM8w7r85)M|$HB2${9C+2A2FCAto%_s~26z!{uYj+{RhOQaSZlY^(?>j< zCaOCkeq^+k&dQYHGkOfW^S4K59wc(k^q9&Gn?-_Xgv#yByR<%avk;Vnk20}Gipwr| zp(;t7uR?%oLtx%>fSaOW^pPMaT)?1Zz$U6uO#}E9?7{SHE%O-7b@~`L88B~X)=)Q~ z)vin0By&nBF$D95d{eW43WV)~*DvB500r!9(GZ?y(k7S>;cT3uekWd!#Xd#TT-_Ng z@la<S;Bem@Xa;`9Ja9~uJtU}@a*76D0PcuEnz>(eQ=(qvmbDBex&o&Y;E^K^M6u@j zP&lB|Fv^7(r!brfe8}cS<m#qiO(*ERj~8cc6c7Z8SNADp=8J}UHIo{?8=5;9r;L+5 zs#053$sP*d8A#vKUMKfR(LxR0txTF;)i(dc4OTzpsG2i0Z`4RB`p!Fk3oJ4-xFes! z+^DvVGf+&@Adx7*9-@Ze)4JazAZNzmkk$7JBY+zrK-WB=A7_vP4;Ltr&p6_6C{boM zSnmgJLGn7c{JOto#-*Vfbju9CJc(kIcHUoLK$>9CSDXY&t58Anp%>4@SwQ*Wqd-5> zc}a8u|Jy+c$jK#jw`|$4{mzffq35@w-wW#v$)Oqi@Y>Cj0<1m?jy&NI6tfu6PkEA} zqoW)6#=N*?=p3j+Jm7OMr3ROVwhU3qfYpD1Q{nC@{HFqSvx7nizHx~if#+TWcYQ+d zv<$W545R}j{5v&6C8q)|{%_VP407$T!KEWU0uf7Q(u3)#%>voG;63@2amSQEaieud zgIphtl+22xO(w;Z3p98nxMhgvRDk>`&$v!fLDG{HYx`U^5LCcoOTfvYWoY<R!0M4h zBCms5DR6o@cznX?@WBxbID0yg@oK$D+Fa4fZQ<3D3>5&zm2&=SDn!R;xa4h}&OLXa zd15e%lc?iy4Qcn|U{tf$<!K*r3^pf~(rQrOKp!jyv+m6jd5uK7<Ip%KVI)#~yXxsv z<sGpr2me%-xTQUb<)*Fw4%Y(NQovXhR(x!qr~bu!D47&#y9xzH?MpY2cwe36(U@3H zdWn}$x}RE93xm$#|173HYw&o6bt@_huIcDC$%?!loC&w2w}?S1V!eNFd+VbNHO;JF z8lJgPJP8xP@})_JSFoIg{8V{a^`C%9@>Cyqu8;GLCqS@Z#awOXK?8{xW}4j)$H$Iq zSwQ@uKmvo4a!U$=W=U|6!&T<O%mERpc?UYRqXE<5o*nduf9*_usCBnu$1FLo_!H%U z{ZI1`TE8v(*ZpEM_Vm$W$p%P}K<uGgIZSV&V|be4fQRM*;P7O3O&12DS73N?-tQXs z|27846TtV-u*LnuTs{Ah9AbSK4l~NpuO6r(MT)<CSSfP^>r(<cql!{d7ema6+a!pq z;%;0qcDmP971Ad%V4>|{$9&LZ)%CLB(QdBXUq`k>P}}%X6*qKA?eobID$&G($XC>Y z8EA1c@f`#75>soV>!Qhi;psH~7%1*%XD5h@_xtR-TlbxK{t3s*_|cMRJ+P~~s;bts zi1)>29=}=7BPs@DgBxOfK+txvRr<(kd$NRe?YhM{=IHZ3uwsVO(9`$(K<qldpd{w~ z_zXikNtkJ}pCcvBzUi#nQ>9Nth}&*#-iU|P;!5o!qCPEfLvjX}I}LqlnZ!Q`de#I% zPGe>dzoLK&w&e-sNEuIHLTgsoxD#yo&wLh5ao+`1g>Ut7p&1FhKuMqZCYPeSbfiDV z$F(i1-4VvC@JzWNPT3NBS&dYoXCWKeW1u{B6aw`YXso>VI(8$7-B7)?;K<_Yt#CqO z47dHSUQp3(xL4t4Ibkl$PErzU5k6pX?S2lRomujNhwjltI?^lHxBQQ(23QWP!Z;@a zRf;SA8VA6Tco8Bd@^LPIK{=nIIsqd0Y_kuhlm^kUk|djiF?>&cc(LYZJ>`yszishL zNqFy!qhMia!4*HlE~`ZH5%31Jan1cKQ#?^YHWqZ&AVWCB5W&-V3KOvAyApgxVuYd3 z4D9>DA{XtO?Ybut_V<)|o4HG&6nWio3Z{tm7Fs-plKEqpPWKm?kkj@fF%b1sA&#S% z3pffH#uD~pg!GMHb{{AR4DCFG#eVxL{qnuqq4(_9AQQz0Db|hwBQw5-LztZ}p>ELS z^cH)^UxlF;xB+(_Kt?{JQ`pp^A-veQ1~f+v#{csR>;bcO)I=H%D`vh8(x%cyigY{M zn}5FsOuazQsHT;l%tz62K9TsYnE+u$O!%4f!HF`F7RD_Sqvi?Or!bu(!T^iO4VwdR z%vW8{$^=h2yI;L@Z}}dno!t!r)(afU(f{34+<x}Jo(J6k%<(`}Vw7;qAJ_r{k@HDL zN1qZWGB9??tS3B$-z@MVZvdM?7AQmqO0eQj#KRuv4aQT_$moGRMvi(k;ft?L_;T@G zAI6_{e}Sx&TimEp*|%}E`j+ig^<iU*)V*!)@eYa(Pn7s>g`)k>e{V3FpYEN*`?9_# zOFC@{Ic~fFXK3qKP@Xn>ob5%>iM}bw<VmGlP4!gIf)E+Vxb)q@aP!8|Ph8^Vz3WkL zqUsHlb!~-=ep#57RFjycBHFTqdqoNZk>T6FH%^AkQvj9fYjGvMRjnakzIP;QN=veC zautH1Hyp8udz=@x2G!mQ=jd^Fc}N%(Uu*ADpG5svna-7=%0`12@Yg3FlH<@R(f<G5 z?->HT&ngwHl2=vuPCAD$Qg_RrFiu2Z<#<eqfG?DF)d7<(cq)#Ak$S-OQ+yoMME-H( zm$}kMICn*{h+W>yK|jN8SRO=Xhh*@wS?j~QTMA4goGYKkQgDZ;0UB1U@4IU|>~DIj z?9c~Cng%ghEZUwjB@bS{(bbjDDOQ%Q(Ejx_Cq!AeEXs67clEb{QBL!ME@gb#haKss z{4s$n+7ZG5<%@4D<p{E+C(PW+vYMoaN0aTv-YKj-n%S8KJs(>lJ3mg|xyWOT<WKdY zRH{m&#-%lWPP$Uhxh=zOR?Hn5JE8yOg)HE_Jy04ow`&zH!&evtfQ%<`f~;Or-_)F) zD8GT9UE|cU{+jTo5lItbhp9J)bKsIGsfp1^zq@&6{HM&z7$R<~pDVAkYu^WVMlrg0 zq%M6OI(_B1tGZj-TEPbsAmY3@HenbtDVq6_T>bp2_pc)kAd)|QkhB6VNr!QcOke1& z1=LQy4$ww9tir=<*R?UlU6sU%wx?VP^Mm+R50=G$$BA~5?(UE-?5LbbEe;BBY3(9o z@W$9CKQ+6Ju9hblcEY=TM_dRlsKPW<i03>>ItQpoVsZX*@E&-}BI%Xbr!<~96^Qh7 zZ|h5GZ2V)X{x*OqwE3ZZ*pyP_+J~5w7sXTVUKbgC*fEUmMpIdy@Ah}YS3+zqoBM8? zJ*SD`WjV_tWXj5jk~f68Mkg?j(@Xq}$~1g#@aP9&#&f$G-L$%Fz|u@jIHpQrJ=lhS zK%SReG?+f9Fryr@x?uHgR*^*)xnmuptkF`IYk6v|=<{tuNXu1m%S~yOIfkfb;LRhq zxFT|1N;jH8<0&OS{Rq7vnX({_!4Q3)3J*%)m1w>T@4K07Ae>DXR%p3<*F$NSM32v& z4rRfyGcpgFm1m4Zow{hd#>kWw888t#Y9EF6c^x3`X+OTn3hzr(tSH%N*J&KOF_qe< z!@#fGEAR3%6kU4S9J*j_8NV6C-!lCx=}C#w1tc9P*F#@!Z4353T=B0gj7Y!Kn2x#v zs`2FaD8whxHh<+QfmitbJ}~Zj$QnZYwQIkpX&+Rn)B`pClpH0K7Vj3K^%H=76k~CD z6IjC_9Vyd6$Y@JB6g?y(J5tdSFggpG)jlwRi0`-(EHB$62mn!A7JwiHhtjaWqD_R$ zpPIU<m(kqZ*4BLI+XrKz%S8VO*We2z)pjIxyQ}jdQPZ3S?e+khwJf^Wt7P=jeWA5X zg~VMaMfx!;%$N!<EdA@5Q&68RNmRDUN9|)9t>OlyB=LJaPCk7Cz^*p#1>B%~Qttku zio(=$plFV(@{YT{unku8p(%aqZ|<ux`}y^500lt8@#c9Bv7=)Sani>3s9>qck5*V3 zv$Gq}wMK{z?Ue&A&Q6N^us}=M1IwHlUH<$NI(Z$llmMcXK=;WkHLdw|<$$&@PZoiD zUise>wzI$Eg?I7=ewyyvYo$OkeyGLgVv#!_kdWWC=9Jo%WSKHH0xZvi-eBk%OvPdE zlOL;Q3eBz@WM>-m#0`aq@b@O0of*F|Bn&a2Fh9{%9-CH7v3s#G99|gu8|t#PlA0x2 zM;#zui+hs4@&+$T`YzqQ@2`)^fNhaqUzNKOahTK{cH92b7?z;XZ+Y9oF+|Nb3Qxy2 zBH!4t_NdmtKUQ1tq#t|=uV)e11BFUGvJb2<aS9(XQ%r%r$SuLNDjFNvPG7o7Mb-uI zI^62{D4xNk2i^;eU;>J{*#9ieq96BZW5T}yvrVF*&i842Z=KAML|+}uFc^`36D{8F zFK$qb0&<b7%R`tsjb7hV2g+;LIPZcQh!ZP`nG~K+$2~A9a_)zAec6I81cQIso~lkR z4m%lRU{R7svmf2{4b@h^F$ki1f{jnP*hK7ITr~1r^KSQ>ZZeD%qqo4z-G2Ayx{nt3 zmlo+8Sb3@R0z{y;#oPh;^V1uh-xTBRg{yNCNR>X=rR+gv(S+LpUeBpEKNfRGJ=Y2I z3@AseEWJv*e;-M33}0(prJfHO{OUVs_H7oF)JZ)|;bydIv~j?zm_-aIR7H=`1@1<~ zVJJNFA4iB5<^@r?twg_Q(9MdjqGir(i^tWwo~(uX(Mnlyhc>^>W0+nbt$ef-I@r>& z0xqQ`mg%M5S5ODI?*)nS`mVU&u+H!s;PnY28ZY0)4-d!+WgLIwKHPVJLPX8*P{|5J zU%o&%B=dxlTp=`qBZwbm|E{14);BHY4lH0K(R=>)QvFW!C0cK7^2Kz9wuI&Onja@s z&;zIgX!knf%y!aG2&|eOH$AugjYdK&f0!q?NW8W}0#ru!Fi$_!4S0v!y{9zaa#ed` zG1I%y!H&TaDmN@E-XWWQKuk>g`>C#Me{Ge8KW|9)mn*T47=3d0Q=Xk7LU%(3dnLy{ zUU?K}PcZ6E82Vwjoma8rCA{#{pvG4`!>*%X-r~nsRWnm3!Oq^4ShJzI!3v8$I$wx~ ziz<ufY+P3?4*;4Rb6kn|y>F0G!0`kyuzB;2@ab1N8eBlg6=_XPkG8f{R8ae#K<zuy z7gh3Thju(hd<jZm9BY(4D=44ztPv=Gs<_?9{qKelH^Wj9c$;5u$pv>Xzl>$Rw%KGZ zQ0oI|i@s)}n~pSo(HvQgu%b1xGZ;qJ7{R%7$l|Iy2uhM${qSzKjMR+|{LutZ>**Oc zQ?X!um+OoA08pd1P1h7H4XZxg0JJ}i%I!^ehD(9s&$|Y|4oD;)ht_O~lj>{s!qX2m z`asG?(Ubps9!$P4s9Rao#N6Jw3nc1Sb%p=EDq9owEScK&{*QBKp%n#+M@$Amj~cgb zN%`Gu#&3|McM}BU{9ux-<{QHw2`ZXzGcMen6TYgFC=E&0)VROeD)Dq$l+{mVrClUS z=*Tr^lb#{w6k`M+WS;Xs!aVVi*cJeM$R)S23_`IOe8=9+5dPT=D67ZPV{Eup#NM)T zE#JEC6J;c65HwZ#GFUlxj7*}mbpEpDbFYWos$kc2sbAGDmabmEw#jd_8&mwI+-)o` zY#M5A00JKpzo_W`j?(Zgb(v~W866~?l=KS^&_^CVwJ-{NC1i91z6qrZ@w`#y(KLSt zj|3=U|Ljk;eSd+AZrhsKy6dAQV$xM~jyeWndOw~wBeaVaAj>o18v3JNH3&1xeqVLS z1e|$E7bVG8oCMa}1^YaI41PpUgx%JC8tom?yx7@H7KJm8lYyWds*t{2(Mnt~%1({v zAvm{bQ$3ejbVAy0qe*;Kg<pnyeLeZ25y437cufs!92-7a__3nJWMDPs22J;{<tI^A z1vHs>u(}T4=B!^IYSHuz7NoHL``9KT?@m|@#kVN_f~UtYOgG{S8c5-{^^M+kn>YHt zyrV#UdefE6ktH_z?|p?bQM4l_JyrEz2Ja#m6g$On(oAMcz+8j5kgc6--os#`7FyYi z!OZNbkh`C>lj|W1T=w|sTMp$hb+<0yp?xXkuSLC6V@M_59#udVg7VkHj;+aUU661= z(ql=&*+O~>)={6hh+petGiBZ(bu=IS23l`>2+1uHEc1807)m$TfN{!H9AZ)Q$_n=^ z;AMYNB_(PZ>65jq8a(@`kY9y7>JU7(GboL+7JGB@i1FPcMH*nLNR6z&n6Y#Qgy0sd z-!}6MKH}v(LUIGpgO9KWx4Y{YZw3I+Z^hS5(?O~S>Kb9D)T2GOW!uO!_%pg+H<OvE z+y1@P457WaKDSa{U;&<8P(XQTR2--02}9G(G~7E-x(*T|xz{^Xw_iH3{Z^g>?URZ# z?zxa0sq=MgpQ24*ZHEsGIdzF_Z`g!65=OD^cc_v?Wkk4;>!2fC3@Rl)&-J$*QrgQ; z_1^S7i>5JS(|LnNzRaKJ*;o+bE{X{OlOLCvR`>BePKU7^AqjH2_jbu~JnnFM65JCa z9cZtv3mVP9FO#{JIqR+JvW+Ky7@Ckx_PIxuNn@MUQ8=WM^L-&)i9J+P!nWt7RKq!a z%e-#hr4CZGw!=o0*k-Hm;0S~%ovpeJGtyakB^<>ik3mTWT1D<bD;}e2n(>o*C?p7Q zGl2TeXHzM`fDQO{M2@{V3K|FXwwEBlouQAp*!b;~*%<bG=>zDWzFu*mp}Fyfmp~Zf zV1>h&BqHS?jicy|Ydt@gaf6u~!~LSe!C1bI)#@`6-2sa+UY1|^;P+f!Mx`A@HOgFX z*9`e|^J%4|+|Zj{P0EJ=<a+=_5WaEucv*za&Gp7G7nePQ<8SrLN&>nC+zO*#eVDnM zwHQj*c@E|B9q;|s2N(5$^)jJ>FO$u{;fzH$r&<UY>mT6bz#%$(T+Nf1`n`!>@EWA` z2J@BmvN!Yz%XaL=mEU#@){1Ai)g3551I_6r9$%MbtN*D~h}IAH#l;#i4JOg7`iX{e zn(VUMTo{LEYC8geI{$;z8S=IUOJw)A&wr1VrvYejm#hD3P22NsT~7Iz4@R30lvFzV z*_0>N&=|$J+)J^g_?kOH^CMHfPg8jWfJFCkeoBn_d4}Wvd@m@yI=qNQ9;1J224N+? zj3(49##z!H{YZBx(6v4j@Nff~Fihv~y0pJ^O#h5c>dJv5M?X1e_0AwkkWGz}_J+D2 zJwWLOCVjbY3%;wfoVJLTU^T;#dz^rn1mDz?7YDr<{q5U*19p~~+B9|g%tYQk$wT^{ zZ&}Mwn12e0IO?WM=f#S_2lY`96q|6i<962vEKL;dZ;u2lKpp#F*_<`I0o&{yqplK; zPnkSK2UytZom=FPo0}+^J+4qSzEVqn0b}(Fs$BF%j{dS-?km4?kaYCW-MQjQH!X2Y zQGL8@)b7Bfz$#y8+tpumdk|EoNaZB(eJ5=hzZ}n@(*MfypB2|v$Ot8-*}SbF!3$M2 zE`yg4;qy4RpF)oNl6swkOCMKFX?JugL~Lsq?}7BZ$8?^`&L9fjF<eV{#?W&CdRNtw z>>=LFC-?bk8BtJ!vU^;5Q#sgHO901R_|3`N$~020&DTfwd6L+oA*_UCuJL^ZjYA5- zvR??eityEBx%cShZ6t036=KKhTuYS;a<x9QU&nyVF3^zFG`AF=a$~S-^2P3T^lPwy zI@v7yN%M8O2b>j?t%bsa66SH{UHImXUOwu@GqI$!*c9QL`e0Z*JBQCxeCtaqiC6tC z-;XQ<i$qRtmDYJ!Xrx+88Q9%ObyT^g%rtsdbjjuoA=sUGrkRYi*)Ow+5>Qq1G&82C zp$YWfkorl|@D!WbKH=$u*Icj;f}n-lG&yH7_pqDeD?a$58`3h&qPEnN0mCzJW4I(n zF*T#eq64-VT(T$c+4{`MaZ}<dW(}&LbhP!}6_O=UI!p3u@kZ2*48?bss$#+qH@yrj zeyzutT*3uMGYVO5I(dBTZFoWJCyB!#Kv?C4qX-e9ol~E3@Z+jeq<v4F#qM{lN0qCa z^G|0F<#p%I-N268sMw$zw7ahT1Xj<=$A6pxz8=+NuL{anz8q>ryR{)@b0gJXKM8vL z?0-vD`nvy>s(b^Mx~lSuvkX}PNumybl7uDbg9mb7H=zzxd5}G#55mKY8b#FWDmvxl zrANYY_o2j8b;FMi?oB$Lgzifl?H2`YXJ0c{8Q<v=XAjZ(pS(%Ox~#+98p^uMJ>4?n z_GYj|5y!svu9L7i&yiK~bVAwbdxZ0Ci@_FMzp@NJ#W&#E?~iI-cB_l_pc$o6rAO0K zEZLv5gf4}%+h01qaq^HZyZ?Ub_p9THhn779<-IG8(N)hLcnT2)Y<~y5ZW(H_zNBTz z8TwSX*eob8O+A=)YGVIFs@OWQ-~)RCe{<NQ>v{qsS{(?kF2q*EhzvbZy3u@LNo$%% z*S^<ENbo`W#4=p{EkSmXX--l5wtCQB?P(3+!%24${u>d^{lPCweP3_G4{zUhXJMa_ zEZ^3Vju=DonY}z2ElcAL5(tZ!Zv7=QaMgSPzbVySZn|;_REnH@>>&EJ|5nk*<p8yo zm2XrD0LcE@-BiTdjHjiln)XaVpI~;de@jrJ5dX^9iYTv3tU-76By}utKP>V}#zTng z+eii>D3g5imWk!g+Jt*S&%JhyEH0Ll-=xa<lVP_E9{dWb4tcJ$meHho#y`|X1C_X^ zosgHR<FqF*ncO`j%{Wl{xv68?zOQYVsG@CfJNP%Nt5O#6!R^XNr~rRrG;mZPzR}fa z=+mLSlY;;A2llP{*a|l<SA(J_f?Y9*Cj+)NyG5Rkm+vD72I;`G)8r~ifj%~&^)JGn z{_@~SmT)N88^9y`+$0@wQnbg-sWi6EVyPzW7&fg?v)s=Rf3gp?Jk_Qj{%A^Jxuin* zk_OLI<@{wManWY}(Ut^FWynQ7FFut5kapVD(e8Fyb23PK+pEo7Kkjv~(|$|r)AlGQ z5;ifAOg3@&q{~Y`Abf>05P(l{74Hn}t#F1{6osh^_GXEszOU)kjG8ITys~>zTffbb zJF5i~qo*u1SWMnM+0E7;%Y)ETYv7{>g!m1)^m-uNLt1~&uuq?|{pBmu6<!A7KZpN% z<#dBtjqF<zd~s_Vs_Sa?E+K|huz7kA6c$xK5(qdQb@<g%(BonH%6l)5{2+;spMK@R z02RBYCqD<L?<seIn2rvsy>aPJ<mKYg(^aqO`4^fzPXY33d3Yn>u?9H6*e0m|LFoON z;Vb_P+I++b>)QgGhoM9r05qtFdu&>8vh?H#Ci79RCGzn&&t-hS+8n7C%LecjWY|Xg zxC5cY`-1?C`;cVAz>wwVGL#tkNY91((-U+=GODVR9kYG}i^Sf$*W>>-@9mEL?%*48 zEsE+18zoj3n)%ilZG_4$wC$`k;s4ZMd_QP41gx1@cZ}lBW#m#HDPqGpBBOHa7ew-F zlWlW8p9076Ui9c`QDl`Rrr0#YByHm1CEMb;#WOJ+cipdEHO|WiJw-Pil>C1~uW}kK zd~guzc*pI`Wqn%)75jU$j}*7w@|9d+qY(QGZ%6;CS^8^qu)+Q?<$q63rBTPew<P~k z?n~rQn;%bGOGThUjh=3i`Mh!EU_Ju(O6eD6GeW{~<i5Iq;R;ukimv#-fHK?9Gbh}D z-yl-7Y|nt9{@L+~*n#7G)>YM1C(XabQZ#>TvtA%C$a*jF$nTAsj3jb!33yfxoTevK zi^rho?0P{KP{>V?dGH!YAkJ2~^#~UG`nJ$j70$rBwkZ4Wpvweg%D-C<`j@DKOt2N* zwGQoc!!=2+Qb1a0^3e;uv!B~%s_s@+dZvaJmlMmI#iT$`4lK;008il2l`|Rv3;$QH z{Z7E23z4;AbpaT}ShO4ZP1+}&LUAq@+Fv=<Q4pPzp(y4{#c=fWas(m?l8E#4Yt_Uc zf5YVKD}*h_K9tyP?HyW#9RZRY@ca%WO8#Cl-R`IQ)6b$02mt_D*|bTit^)ZKjDakJ zMXR#eE*IiFxXO{@mdO)W+-0w0T;)N&9T3R>U@`hNAS{VPtwY-)`01xuQV-VUWCAB0 ziayujNyt<lxw6fJnuP1Sd39M!gcsct&N_db?<MZrCse#Q<TzqSA<h<Re*B-W7>IyA z-f>^q6`d{0?C;FNKcNt}qPj_UZCX+vTOU>rV}Y}}_OJZ(UP`E7nqhSroqG{lKS8QH zimyn)?u2a=qaVE;62w<AnxU(UVyo|e+4?|x>iF8!X4aP>MY@cn$hWI}fa3Ar8UDYe zQSx8PA}p_}B3+5bfN?e=rDt;1lR+c+N&rrnp*d`bo;E4Z4nR+<doquX<+-3m-eYYa z44JP*4r_IR!c+w$3+?k)#H893p1>dJ%w9P>@dW)_A4Kw({LO#aODo{9MOXqRC5Pfp zp=Ruq<#g=7d&}SUBfH_9Y}10_t5S9rJ`df<|J_9?6L+5Js{Tl@RpI%gh~rSS4|o)3 z73~RB8~t-&c!dA|S(x{K|4p{wkfsOH20tK)A?NUmo9A#Jwz^RI`F{`0vS{Gw{s+Uh zHSBz*<!35dyQIMAr{@-eR>NCo<xpCi5lD%DBTlHdH=j^)e&u%F$w}<>;;?iW*$vW| zIW%*>h?0B=e*0+{eSG({?3rtliFy(x-Mi}@jhdIhRn@(b0T8BHvfu-YlH~tTEUxB4 zN~L#;jvv*3==4!Jv*q&aXj$tmDM2k=CNTYCL|QPO!BRxT<94p9v}J&~^zYSw*A>E@ zdj7Z%v#S;l9Tx-*ym4Hzd-AM~P-dyLm$9Px(n1%j?W(lyL#d-93wnA?L`l0gupx3j zd)n|SjwXizY+)W$xck|m+TOpb>1+cyiu=zfVs;DAKY<ChM)rU(UTj|N174K-p4rBA zk^>8kxj(#SIn~|S`2gN-9P<}abov*FPQc49kTp{3!4V?<6RHZV^hISHIOb7vGJj(K zRqx~gb}9gf`l>kxgG-}~dM>P%hh{v9Aa!=e-ou7W^N|}+fbaFMG0c_o6%u){h`E|K zStu0{E#n*o+oZhJ(XKz+1&+!IvkqW|eQ4o<H|+DEYhopF&L9kL=?#N~V^;6LO(MLa z2PFk^#Puxc#A3z83-9ZqyqywVYB=pMHsU5h`VqytHQ>gzn~Z6%J+#0>*<wrJqfY*w zZ7(+G+MZc<@mfUYXT2fJn4iZ_->nebydhEc1^1}b34V7qW?dz>W6z)9NcxyIOkx{4 zR<~tF%Dc$(?29Mj`5<`kFF@YkJ6d+-=NS6srcR9HUO%x4k->|vh+ix%dGtJJaW0Uf z3{YL&?sV3LvDlYcD$d_K^#PTAX1Tu<N~(ZMLBSl7uW1%yx|5|TbVtM{zrvdPvuQ_Q zOBkUCUU#Kwm~c;`rBJ?}s?fd4)U1Y_X5ehR7BjuLa~D36BIq*Ea5lsXJ9Cg}9Flff z9~zn_kn%Wxt`<+522y$o(n78&tChg}dk#iN7c1Xjxmw5+lxRezmwAt&wl_r}k$N8( zFXICIjm5#}bkh)5l?tv^Dx->@NC(tQM7?-=rA9Icvu)&hSzKr)jbdy?#Uces|9qTy zz70dA3A{09+I+4~n_i_KKb`OJLK24>1nu{7kq%0}oc(XrzTxsf_PA>@ZTNA!W4g5W z?~%K3ZG8bvadVldg%|m~xZ*Zlw5&5#JX%087v!zmYF?(PWAt~O*^Kg!FAJD?4NGS< z8d2ihxa2M9{r3)H&zZm((5vl86cP&6Zdq$lQ9^qf^(Ga!$;$uv7$~qJ;LMvDpnUf& zQHbGkINV)b%=TFyRFVwd&F3_T(klUz7K0~>-sSU%e>L1mDIAHBYN-0*+i+pmf`G3c zOEz@E2l`m&kFgnIcAr_tYN-xDuO!Lt*h51W#H5XcpT&XTGBJI(<Mvz|QF<CPPMeqV zjoc_IG?MZs<)}9rRTOz6^}nq|88HOaZCLLtMpnURbg53$E-cSrP{|{6;SYO}NQc*+ zom3I)cPA*buxi91L^nHsZQ<V`HJ(PmjcqDmOg|SV%25EiHF}qSc^AI<QGPh!H^-S) zocn`_2Vde4aR2FG0DhZ0xp)o-9s2(`tTy5<ZL@<54?#nM|N7*sTE0U!A5Ac=_Cciw zzg)a>fkCgTr|%!S1qe^4aR(sau-TOXYkv;ty~zOa_ZAyTc2`v#1QATHQxNd26PPgT zTHwT@G881I+HEGco{DrBxXK}AXqH%dxejB<T@iKL2AyGF-0b|U`6KYgRpsvI;QUL3 z40X^gXq+|n;7!#gMzZVvqB%7+ib4*Y9j(Ex)ZJo{4j)e+s&=5JQBqAKmVzS1VQ+t> z7oZ(1^i!y1rz9aF(jxpnn6<9p{-zX!Bhadc?Ixe;wfe;eiO5gm`hVY-NN0<HL90sC znFQB2hL8wjW67m^OAoBzH`6R;u}C$~&KQ;ymlT$?jTsNTjD@G<Sgt=?7qmc*qV@Nb zcShsy?zT6FS)#WL4leNFZMEOsK(-QR32QJntEFi^A}K@wmSDy{q{kr!RkL5++vI^R z-gZ6_{T=o+A8BGkqT4b?vFdGTpv+v0b{H-sIvIp^3YYe%ou`~X7PoIbJb@B&MbI6h zWIM~Xc7(iFQ*M6f^cDykYN?-BT&LcdfJ~n0t7crlX0dg#iEmW-6twTP2ir(~rA@?| z#B#<Z!mW*_Tqm`@(S*g0E$HhUe7sY3Ov8ORWv2o)14D~zpIY6;b;gR+U5A;pyMRe; zH>}%p+s9O(E1#v`HI*_wCOaqnbfcWNT>ne2(X9pK9-bPOIabt-slIOJ>xRfO1sbBv zae5Xx2|7!Wfc|+MF(~m<S*LuW$16v0%Pv}~RqxUXjZwrZjC^IW5e|EgVr;k#|LqX+ zR?^zqlM#`q99^pPHKu*?BbuHk?&a{YO|J{csJVNaT=F|Df_d+?)mdEriot|!2=Buv zDS9oAm`p>|r)9@?uNF=%>`y}EM=e?+aF=i1W|IBpizf*givdM_*gA(Vo8A2o&!)Kr zq60lmL>REjR=<^Ivtz(6#tly#i%cxTyV>IN?K9<yx`o)|CxyZ1wnonv1YXqoCniGp z+8U2{#@fgAWQiJi%R!&m54e^bjaf_JV$Z6*?=%ymXwOMpvFh)hKP<Nyg>RGHYRx&; zyWz^znC5h~Vap*Npv|_ZwSPHaf1%nB{<(ii+hK6JxHo@R^WeGmz6W0lqug5SnWMYm z_B*MvZ+>-UoOEf0Z5AE_ZiI0e958FGCHy6LJ6;FM?OE$~8}9L)i||+tKX|;1Ef(TI z?q1pMC!9~^j))75*tj?LHk^y)pqnEvM0g(nKx%gH)6z`+57#e;g$xK8ZO;9^o=8L` zyRgd|U=Cgz$ZyR13@wEl1!Avo(Dy)1RyT!6xxJ_n(-M|~j8a@^*KBnOJk%g^Hbl@s zPR!n58P=dA59iDV<+sP&zrRFCWjg9F$6L~bc1e<5{^~mSAg!zWG(>Y6=lL{nn;aoW zxaPQUCAI!K*FZY1Lc{fa%mobS4xZ?xxrXNssS>f@T<#8gY)U*^eHu4PYNUZDGU8mb z^H!bHC;g@rZZk*r73G1@r`Rr+!2#33zRl*lb3{9j4yWup-t6UpP0DG52@~>9-)xGP zYvu{QNDLgoW{lO8CaA`?=v{-+-B40dY#}UXd@MVV*^HNd!;^KRsxf_@c&*KwX}=2; z_rgv;dn8}|;>O#X7T6%Hh3MJFuPfuYdCKpnbW7D%TidYbZhC5vwaJi08**k|5f>&U zmEp`iAh>i%EU)WmrfEu$kJlI=ruvSM5Ed)*S{bp9<PJ2__Fn(pa%IYK{#dit|5pEe z+p|O=VinP3+glDc9!Q_yGeUdmg9`oC6JMF4fx9T5AH7YEZK9}8??sW13%CoA2<;;; zuk^|arpH<jGdHWww3lSo-jiR)x|r*b`@7rrBE?#1I3lHt7qT}v2)+8<Uga&aGz29Q zTWLV&ftu#5G|tk{ao%}SV`r<qmug<suy`dDx<$h^7#NS;4}-s<8dwblx!)T!H%~^t z>tV~Ckbb@<mSrnM)nTcIE@m7QIxh^?HhN{_s<sTDXsS#Hu|D)ICGDJaKR15aPxOJ7 zO<`MH1#*rz<{fI1%Co#FzYWTx`xGbxlSjbWSsBzj*;UY<j#|BKBv9rL8Qfshlh%Ve zwS=FlJTs4FLsK&z;4+2&QvQ*w^+0HFdHW^F5|MFfjv;)&5{APY4NlyCW(eO!*|ux= z(D{xx$YDd9R=M2=FMep{__cM{W#(*0sbb1RKV6wH^%tBbB4#M-Y0k5Aw%yTE)YNp` zt9u*;o15*n4{C_`a@)FGYK;4f7U5bA*iG-~e?2MK=a=JjEq=LrxBH^QYms+qb}FW0 zj`Qs5;ZpNbE0k|dMI@RWgmn(7oICDWYF*?k*qJ9A;^pB|)rciR-&=GSm}QD-I3`R1 zMO4=g&89uD4^N*msobh>)5k#iLj2)QVW=ZUV?Mp+mfG}7m@iMO(>EOXs-3O00_eR9 z;fDLxePoA>N2<2$1ZzP8vv^(?xDMPq4zZ}w)r_sD<f?=887v^ab81&1TlAdL(E*Kp zyvg)ph9V#GbWzs3-Q*CD1Z`@+zs{I%qpv7{jPrf#W^pim`MMmOio*He<k5NmdZcgN zyPl9550Zd5%;$i*X&?@99s)ofEQ47m(6gB16@KLRcg@9PEl($JQQ5_JWn$Qw-#)~! zjvaPX${d)5EICKB-6Pu!kF}XJ!gv-I_eiM<JXnk*6Zgi_XPFRpR}pfI3177jao0)2 z*{AHUAh@-I`^9Di>J+33_M^Ki3g&pm7lpTwNY0dG$JXg%bYqvy&h~Ya2O-`dz{nrW z_+Ny5cU)6j)3u6-h`<F!MA}uFbOiwsAu38o6cD6?l+dI_dWi^vNbjA9Ql$6ZL3)YO zYXB($0t5*yAtc`kdLMnt_j~h?1#-^bvuDq&wPyA?LC{&A?rVFqN`?|LXDQ?3?l748 zIkzHM@nsLIXK4_16#^#+sVXxJehH3QF(K8DHxKzlt{O$7Ff*;lgx&hMNSKrxayQby zN{S*c##2!+Y^y$u{L)Fro{U|0*#_0P3L~B$=)tIF7{|@!^||``njf|K`-rUZ+q4n7 zLK3~S@~?b$!`sYR39&smWSU5^m6HirL0m?{o>2c0|LL_0wy|qpHZLhIcA6m2y;c=_ z?XFQ?p;;6>Yx{?Y@@8pwSPK~a?Jcc52^tO;h=~Ar5I^R$4DXzQ<0U1=G(z49^hSf! zVoqDd)!`>-6NRIzjHuT$G_CeHdSvb&fu*5rf0IYRB9T07eDmrcN;g=PC5lgn)2qQO znYpeoI)xW1LwTStf>B*C+~A*Bc-d@kHsUyn;Zr262lgR*&rP8+66Bs|O4g%&Qq82H zo5CDW{kW6tS95HQbS~dzcQds3#-uLxqVR5cNz48WZ6Z9DJ$U+Wn-?P(T{%f%X{h1j z(P+>$9;cX#UsgDR_t@i}9TD97qo4!D=K8A3D)p$nOt0COO#9aM*qRP%5n5M`Ffj$6 zFi5x;b0J4wU2h6Vn2R`SDqmwMtdO2=nwLkrRF-45y{{l+--=HpA;jyca?5a4QKMbV zqA&Q!b}mu)e8P`<BZz5@25il>C)!)hryc-6IF-bvb;bVPv;zn90=xclCk9VYW*3bI zB2{7bWjdX>t5CM9418H#wLMaqZSP)m4j4d9U*l1Pz}IT8r7!S5Siy>#JzYt43S%TE zR(gLB@TfP4`wJw9MF^>@Hy6ZUF(+!yjwzm!Os`FH1W{ImMZIm@SK7HFHD<v4JPgNt zWVW=S-)*&DRA|qVj)X^?<CHk5)-`xU*FppRo619vbG-hcka5p;*QMP^fg{73845*7 zsteN4fb$1uB#ZJmVSx`(o(iF1u1oboWG?aS6&IQ2*`h3n4}I_%VZ~MX7i1oAug!>b zZbqEATb^_N;6Y6#ze0NQG!{a(W`Cd+&9wrGd$ds16YfkStQBcm@!|Defe41D=gr>P zW%x1kSiJ?f7hyUcQvls`9+vKdK_JrY@48CQV=)%=D-G9a>FS;m5}`d0N=LDomcW}S zSBa_<gBt49^HFOdk(v`mbgaoB+Q|0MaK+0~`jrQHVDJfIlr1L47+bDqwT)a_YV3<% zLEp%sD!9Tal_*?;3yh*>6OIj?DMSstbPqah6yb~}lnHw(a9&32r?>RXkK^4R1zli| zcAooW77U%uK1Gakcd{t%t8O`?P>iq7M<G-y1-Ou60=J7yTHM<KH`tDj>0Hd_^T}N; zN|L#Hy9g4TI(9EdW&_zFZ}X$tXl!ZTI82&*4B|bpS;QstQ0v7ZTvi|fq*s!n4}aQH zu{&j%^J*r;8S%i!;zv>pb&c+|?<0#Z_PX4@%Bc4&yhv=YR}c(iEtmO4PX?_l30`}_ z*llE*Jfi(yJ2C>aAHC=jBVgEI^kAl+Sz>_CgD}lWC67LZhy<RQFGZ$-g!gv&O%<LY zP~kP=cyUXgW|X2q#Cz7l(?X~RN2MLPX;BK{5ft635g2c6k#R?7R@a#oECgx{>W)4- zl#%*;HdO?=$wd_)OtX1da6fVB%n%0Yv;7sW=ZC4~J^tw)m52UcDe+BzOYXY^d%)i@ z@Z#fd!B_Vq-Y#)uBy<;Ur|zcbe?e$H7;9J((ifV|R*vU@0u%SzQ+IfIw8zgImd*&? z<f-}LR<mrcgx%qX9GwQ|dtI90TJn}tepfK|z=WVea-5jQ0Ack7H_joukJO-9pO!mz zU^`MvL19VE8tfaQOOe1|c<xsBg|k0ju0G_zLc-h7#)On)6tCRFxTPH8-TSSdr54$D zrRV?_s9=5je1z>wQRC9nMokoK<UZF;w0m&O{ECUwo@NWdQ7dW5&(EaajKYAM);r8a z){ow_QgKT!v4o#XBZ!v>Efmxh6Xf#zKa!d6Zddt|aXmM@K5}(0F65T^Q7E?#%BM;t z0jAjF5xE#jeF?Z-gBOH4hW(wb0Q|7-dFvjSGmI^zme6rR#~(Q2K(#%q%oRCsvsl{f z{C=;**qxwM&#qX|!$!Z&cuC18B3odyBMiefnyTKYk&8bQ*+nA{W><IQFt^n(yK5q) zI_P}F{4!(uZSZ2<x=BsQg(ZsT4Wev2buHj!-{s#fWJb7a+<^fSs3=sZ^*DEKFTxkh z(^tKtpqIXJI!>&t$6B=^X$f+dz7%H1^gd^PZrlYsdO_t^j-;iDkRNCeNZ&z}%A$8> zX|<k6#Q@$HZ?^k1r#?M?W@}enC>XkVVUY!?NQmnmR8KVy`Qq3f|5liNdOx<5whc;{ z<B2M=`w$cRoYk#80(6LMe6xpdAvl@9q6J<F>x>YK{Tu4U>vvoa@GWnhhMF={#`x$% zI+x)-k)aI00EBq7mviQ%cAmSxL!dbo2VNQWc1JC{JL&9{GB>96JURNY&Iwuf!7g99 z?u&uPn0KIi4v6&mkpsFX>cLN<%{J}`YoIx_eFTGolQRi&EfjQi!tA#t+67B!ZbG?9 z7(*#L5(^;?!3@4*kcm{6DyoEaZ-^2`uvELzMz@>ht{SM_yjCipM!5U*W5I;_g%9r< zxVStuoXS-24}TczOkwK<OsIR!ITuMI_A@hBVcagRVc_~U`ShIKG`HBvB+iS{I&2EA z@ed<uxEA44y{~}|fn<*f>e(^Qg$)j)!0wIg(gByM5DunmXb%dvQrtHu?E2OFB@zc0 zL>s>~p`+g%`UI#8aa@J&1>3IkJX7-FA-{&_uXNtJTkQw@tR6qzA~l3&l<CYzR)mC1 zgNn*xFiOA*4tqrP`NJ1a#`rjf6uiOQxqZ9H^ffJ~1<@q#X(*KvJB(f1rA<O%+0Tfg zF*~0Rb~SGZ9j_L|78O`j5Tk?8blT>Lx$-ShK$tezOTJKXTUL@vSIuH<X#1pdj#piQ zRpVJJFL}GKEbd|Hlo&9{lpkLKa81~CO+(q5pwB8G3g!NI3UIb)u0%;AzMM-x0UF#J zz{;f^+tzbejI$nw$@doOaz;+cT@r_#!>baoL~8m)Lw>riWTgU_y89zxL!6Om85ggQ zKj|rN6p)(z=&Oc8ah#mFe_!<k`Wmt5yieu%?M|hUx3ZagUF@8WsdVL5^cw+hZ;!?n zqb|Cy+Dh*8aAinqUTaYaAZt1?={u{XEz*rNo-_TR+H+;GIIORke<@@j`maOFnr~E# zGIqkenG#F{SVoLQPmK{r&bF-6mkqyMRvu;EaI!bLUn7Qpm{Ix`#qT&9&x`hdA<lO# zIT<1;kk0S%uPwszJB;pcBcTeu!OUD)dvKHqZ)Az-lM2&ZyxYp(nfe{IA`(7)=t;g^ zz7@q%rHN!yI3L8eHim^3Wf5}Hhm-MTKnOT4{{~dHvBK2G=3+jv{^R*910SKXXM0uI z-;^y5u5QEm2O`lQ3e3mJ3wYu!8>i1+_#?k=dXJ}itL;(Az>W4YKFnc$u#&^#W%e2k zJNs6FoGTq(U)M?Jx_28-Q*i`uEUR@QtY`Po-|5{(Uco}<n<an7hmTmy06o+oxw;a2 zR<U{DY}(0qz0F;C`qCn73wB{q+(e4^Io;8xwd{}v4(xbhslbI64Jx=srGG%rl>tw` zE3Bb6pM3u+RetjjF7K(!%O)jR2+u1Oanb*ZoN_WZd~)aRRTJB=E2r`l-45k-*zg6d z*@>P<kk8>6Z@||3M={1rTZGAWcXc0yd63;8)OudU%0?6I&PAz!CJT#sHcMTZ|0Ne} ziFCGhFg&zI?q0x}yf-SF1b(rm)coOY8b$Xu`mjIt)+^7>{*p0s>8;B9FltUMZ@Ja2 z7?lSa1*^UymCBij-S-nkYSH+2^R%U3JbKsd)l7AGJ46beS5VK4nOA~%CC1D!b7d0q zVCXS^86L;iP>I!1ZoL3l2;l?khT);cGGE3+GwoXd3eM?$0#K1CfyFxYp!Dr-1ES=x zZ0VP)QLZ^J9iHIa9xcrh!YTPK7t!OTaA{G!)BvZBi&L?uhBya%tX$<6474$2<IuJe zWGb+Kq7Qp|A8TY}Bw10B2lrMeymIQu>}X?m8xrVD1+&=1!P7GrZ)tzqJnXqI`JLhW z=HXvDS3~CR&;r-==-%BA7QD6I$S7G<v6v-%p?(Hb^sEB2mXo60L;3ZhMCWMa!JYhM zx>3cjkj@=9nWk%<*7Ohe`+U6PBB5grvG}jn(IivwO8#hR&waTf9w)X&tCZ*%?b8Cb zkFKF5@prnLPzyrJ6%6=e)VpQ4m8}qQ6d`<4nqk~P&sK3pC3^U;G%lt|hcUl&E-fQ0 zBek~j>4wJ}o139Av3nYeo=6kkyiz~Z)#FP!d-uT-LD^sMiJv)vP~n%k)-KqrJU9^l zFsZgA7I@SudGlla6vfT+5o*j$Uh-|Z-!J}P&8a#1INXuQ1Fulg!TTTUxP1wrcp+#Z zHl{U1|5w1CRwkSz+yL|oB|-zVsWv3E=VSb$MV``$gip4oA{nF?hqzs_VI3G{>jOZG zRa#;S7Lz`{R-9%ZOgR}uMHQU>Pw+oRB7hq#`lB+cQVJYaY@TpHwa9f|&7Yp!JrD5F z1kkax0SLMA^LJJS!Tgu8SIoO$o#b?{zMc60{7T$G5|D#{6Hfp6UEl{?NH~V^v+%1+ zbJy{gALxlL`MH#PZm5mJN7;g|GydB00BJL?e(cdZ@t&)Z4yQp*O?x?H_4#dY3xdk< z#*Lrp4T#D@ZO(&w16sE*1yOgPVLRm!(yql~8o*s+PydYDK<Hi*(dTJcvK4olEiJyS zV|Z|35>#9by4K_OTd8L%j7B(#k0q9<j%M}v9B4?%B)ohHeHcUgpBE_<HBGkdkD;CX zk<Dnk5%O-^^e2)7>}L=_vR}Wmg>5v73BYH+a`3+fxqL^ovipA;6q3p`wdfH*7is=m zyYF>K-H9u!83=jlB;EF|OXNSzvUceVT)+5pgZH;LiOXyl#!CK61HxVkW1;}B{m(H0 zYs&nTm5&)v_3gU7H6Wx5mTo42XpaTqT+kSFo$H$J_OZFo0ewbzO`SJpIt1IUn4__4 zMFU370A0*=Ucl=d(y@>{J5rT2PL|^lGK6@A(r<&gGAn!koZC_x@SU!cV~X~Y$s6Zy z8xO#a4kjMdfJ6T@O-~@O0+D3Lwm;-8h9`jdg|9#QQ1InjAsFD59luyAJ8AAT$D<SY z(pVCLg&?<)<f&pG7#A=ULD%2>T*jxzu<-YwtQX-MYf;EKcmGF>_v_M39-1-z%H&=o zr<9yKc4fdFM|xm+Wy=GnYmHBA94~_VHq!7O)cEoZrKJ79O&@0_J-VOk@)_~RH!mJ= zD`*gPrh0%;Y64$rX?AHo-rf}AMew<E#y|aHmo$l=cF;?2mhim^-PAw9>i$UlQo--L zz4YbxrFcEjtZD3O{LuT1_KBYZ&6W5)@pI&jlzmvp6I;_CHj@DW<+^dLG@k>?HZ}ZI z&NL+5U6`6YP747!y~XDcdioo7C*m9%0ya8!O0M^*T<@5lFQQq!`MqP?Wt#I5YwUz6 zZ8EttdJhn{wJEeZBGP}&uJMoA#U04`!!Lz=x;S>0?e=HB6d3^UthwCTMoOx(n%_d) zyoJt0alWBZJ;io9i;Nj5Z4J$ta}?UTxRu4Sq>9CH8nXs{pv_}zn-U4p^WBgtH5Z_; zCDT9GN8u7Re5d@1gP_BifDrRvHfsNEqi=mxN|SgUlwR=`gy-0qQC+ZbyVi@w0p;$^ z6obp;dReCqPgw_rQ8tG*>oi}gp}|tmIgr#z&8^$oVNTo*CvPx4r(GdSIfJKmW2?S; zxnpBn8QoN;bgzNt2K51@!-ZnyVq{74P4xtv!g(gry@AhK@NZXSuCdptCOM2wIRPWn zY&y7ivk83n237T`@tX@RaZxJ=fAP-#xalBT?050&Yg=}%lch}r?5#N}%FHH)dRLw~ zyE#{SjiR$Vr^O@JaRzgDjh`8F1y!)i$;S~2%6DPJ?Xe~q0F^UX#VTbEKnqB_@MF{q zz!;0K|2>2(b;Edi2A6auFkp~bBg?_*YFz}v=)EMzyR5_0yRcon`-v^qIjcFDIpd%Y zhbNhpD8nq~9?U(QyQbJawlS{OgU4cFg!PSmkm79G!73_p&jEvn5-_k`LLN0~C&&Ip zay5$M_(%$E$9^RsOSt=h&t4_+Ba^FAARQB}_+R6)ao34j57wXcN$=vB)ctTSbCJd^ zWle4Dr^d*NPSAGMRmQ3?Gi@XHLHL7(S)Z69cXWe2!jE{+30gbSW+owMzN^38Ss&aX zUUO{X0KB^>rH@gJ{7J-F+rRlEM0FH%6`M|#D==6pFooW4cCcp|)S}gT2+*dyQ`(9I zFToosmH6=dcp35ojx8HrLVbt;Y#<6mB&b0NXecpyoNx%EAp*75sC~nqK{IpdsAOw* z%&2IhAGNUCR|5Ut<EUZ3@$j4_3&pfBoPGN4Ldy=`o!otS&Y)Rpu#l4PL3ST3{^aN> zp)&-5BjFgXi3Tad?idhpx$UiJq33oV3U(J2z%x+$BdE;Y2cM$HF15cW4@O85;{wx; zIzf|!eJGKz6c61_-rt214`JO%kO=mT#m^C%@8M8I`?^`KPN!3|!jBopf3Atz5t6c* zb<hRwR_uHKD0EgKJ>=v)BONVioi|G$g_}tBQ>r;A`+Uw|n0=JTaClEd)(OAk5khyq zG1jRxp**u^N~RL4)Nb#ON()tEDHvyW+Iqog_uXB_{#4>v6M>5x+V}yxrGp`b0l+o% zo$B>Dz3jjwzdVKpq|~O7zWVKaIT?c#Bs8kLC)3VZ`uy5C66wx7z2n`S#zcEb2D;@v z*V#NiXXO{MVb8P;CVulL(e1tXbsW>&nYqK}`O+|)`)Z~BGTt4ASzh=2)^KRxu}{!O zIM3xvaT`IW?w8r8dG&^B-#u`%C3qd=yLV2z*uNm)$J3kB!<P>8R7!Chq+R=&S>$aW zc^lG&WW~qF3F6PRcvHCF$Pz~_(g@Xk1bzn#7S~I#iSfslU0|qLH&9K(yMOd=F7r(l zW$ROmqCIIC@!`PCICa2@NfBEH(^WgOdB%rA|L=K-nz5&jn0G@6*nPt7{1%G?Q}MF^ zJoXd3@nGeXFijKAm!q(O7-6%S=!OlgGq_`e>=hy+V&gZ(QQtAkGJhq5*dbF5JP2sr zzM&}rpWG`^prNGSBu%ohvxdj8{@p)qTySriIq#0%rY=@=UC`Gq+MvC%FwGv79Vez} zXGWN&cU3#8*nCONbgyBgo-y(;)`G``zXe3m1t{5Z&Rs|{y~R6=60c=_^D-wfDs!jj zEQ69}$?eE1<KFgXpM*w-;LgmkthyInOqHR%%=1i2JhF#bLiwQH0*HwBU#@A~Tx6cu zMlRU<tOUj*$`{<VLz`CK8wl0ej^zm@I`luPGlI5Y_h;FYK`=Ms1`o*T!f~qlSonZC zrNAG)LCPd4KXJi3PiLQEfvcqg(18e^UOmPE;a6@{(O*XCEtlbxfNuEhMS`)Q5=`7& zdA|$h8kc?elav94`}4*N_3|6EwiGGMW;4fx%=`J)!v{?bf<<XpY47<9L?DdVUf*VY zp6LP4Q+n=A7hoGD2t{nPqFig|dQydJyyE$VW_H(tdGtN!*(6eke#sVwTg}tsc<iFQ z-JOLToh*FKr+Wc>=YzTKY?iMsH9bA_Y}%O}tuffBb)#+HXUQ1rNyDdp_Eb=)TA*39 z*FbPe6^V(H!t@y`Q!xKLM2a+Rp5w6j_SEd@iES|RYFPo2RySy7QvG4S32gZbLvDXi zr15jjbX7`cJ!-6VyUUrh2u>b>x@WVQE;a+>JfS;S$l@K8MC+{+-bBHm!ynJASqr(v z^k^!q^@bfs?<#TG!5%-tAWv>5G^KC9?dIf-am>6cdjrNsf8P_T%dRtXhJqnodq+-d zMowvXS{Z@3@ch0{jZ-mK`K@9P`E$}{Zk2fVY^tJZ?BGBWbDfdv{5}}A-<AxY!BmzB zd00LMHdlv6nMI?UW92TqG?TA1G^58F-AOZ|VaD%C(>iAyO+=_lgxUr52Sw9ftbZb= zkI^F~%Pa5~2h#(jq)kZzczP{eW7m}l0^U^F@XBp4zw(D6B)lL<GJ{~9p~lq(8d)kT zQ8xMZ8Lva@#NlTpmg43)opu425h(%<Gf-xs{A{XL`KWHdqd4DaYkcX44x@i|qG|4C zBq+P2CSQ6_`JNiN3x(V;*n!-vfS5lzeLx6Bs@5;1G}wV4u)2ZjYHV5)VON-lg*P?q z0V$x@hKL&j0ska=F1NvCF!K<dZLpxnGxf=}rPiA}4<+`~c3<h>EcITTTFD?2^x=CU zFTC(vwT>j2S)V8bxWyXH&!v?$^4r0d73@rC5zaFoPiw72H}68Lg<zuXDB`1BkBROS z{Z7ckq|k2IRQXnA!5zG&#?lj8xzy?7<;@$t>Xe>T@#7#nYg69H9g$1jta-$NQq8%% zXIi>QqJ$nDzbIj?S?My|x<53iDy?Ck6};)Wzk1l8=(CEiBW%Y%f*wxI5_YmdM^6QG zHL-`YL;?`7N2b!QLd6Ai_o_IT8m?+&B|E}{W<vGUcQG`TtLcGux}G`W+V_As^K_wv zAWHXC;+Vaa{dL%(lnhdCdJ)cgUMHEaJ^o(u8VKc0uhqa^B(#^~n|{T)V;MfW%5m#$ z-pk3`(b|mJtI+{D3Qqlt;(I)2Bcm8`kL-eb-8eemQ&&OW<%<^8RB`bDlKO~fz{yV; z?$DJ@?f4RgNHM6EjorF8GDLAdrII+UK~oQ%G!LICv3$Bz1U>3yCt-tE2S?gQ-n;Ql z`1UEFjfp5}L&z7+{PHaGL-ZI3JPiT5gkF6B3XGmqK(u^Hw&GhBdzRE-^@}tBNG&A> zTb9}i2P&I!Z;n@pvLv1Nye6jOeP!V|8qEi|m_18a*~pfVw`r1$)p$RQ1FW6Xn4Q(i zfh#DwK1CJKP>`c$-Q5kVdjs@o=|W5g8?xCPX1gi+lRdU%c?^FXY{d4!7zK0j^R!L- zUO(Cyp|~L!Uu@VGHm|6WubiMm$2@ffGIPzdvW_6RX`F1A<YG%wRYFbPCk4xY{Y{l7 z6n&g?w!wL;Wi$AiIr<e9ID6mZ{Tahb{KQ4NyeVcFNPgR4=-Nx^TVdXl#&z4n3eNCV z4A`>84JUGi`(=eoJHAFmWC@OL-2XvNJMB6z3lZ`;Kq#}-AP2Fo274>1@gSE@hVWUR zsZX>-U~~jLvZ!%os|Fbk#kY~{oOxZ7sPmK`T39%tZw7w^NMlw`Pl%ES(Dzk;0R|p1 zaO%>(@dlvS{~%GVJ?7YJ(7n3xU|6S4+KoqX_w>49HG~=yEacHt+3KdhspZIK81Lv~ z(Fgo=x9G<-0U<tG1&bje9MYbQ<Q5a>gA&&G(NL3?(4sH#z8QF(aGy``Q(o&|=av== zeFSMTWh14*{jj`G=tVN;#wQJ+pFw6#P!+%*e-1|XfcdEuG_D;U#|JtTP)oR`{GnhG zj{AiA@FiBJ3R}je-64}fJ5pl_gkx_m(LPssgGF22`>Cb_8I*xTUp0QH1R4{judiZ| zMvWK~dCD;Te$OJH@y>6-@-lPoB#WYXY)?0W{~HbYp8j>HIEz9hZ|XIBk&sXl)IijO zJToZc8e|ONEQiOK=qFY;#OW1i5mNTB{yO6@(HahYek|m&bEUOjYw;}&f<EtG5!~m6 z_pW-soQ&(b4HTTKEGKNAYf6d-y&T#MCUjW5^eo$U=Bys2hzMA%SJ?-Os)-qWFd|{U z354(ZwBPS}!}V~hjh1+Xh9VE9&H<}L=j{C3r*uM~Qt`KvH5n#9%j5435K^rA>-a{L z2<N%rA>~i}Fv$1f^wNG}vG-{-`b(GKH_nfjcS%YLiA#H^_rpx3%#IWTt(rX;B9oBj zYZ^gpWj}y-;7nkE{fS~Hzu`rSh`KLGLWWZ_NoTPTC91+eV_ZIL+VNJ=9GCqY@JzZX z%t5DTfSj()9p#m)lmOzeE5|*stAIQZXLhgrkfw=Z-JYR4>O2XM=w3eWpOo*Xu<{e* zYLOXtu8F*K686p7%vCUP=y~_wgr1~><c{@qSDj9(%^a^7(v<kgS>J7wDrvuIlSYFD z%~&0MZm>bjDy8=f^G_oE@ejuTOKW*rrDbxk{)=e;kDve6V*cX}|EBHyDPWMqqqkXs zME#ogsWlezdV94)g7-tuYUOQ;57!R)=tcb!t^W8<W$oJ*QAPo4d!uq=i^1Mt!4&)X zh(}<Bi8RqJeBxyJmOCZ?z5bsB_4>c7AkUVCHKA>yi|~=uI}G6;1XbvRl|OKFn}p3Q zcfpuH4K`mKCZ^xBkqsMBFBRMBSN{G6`A@MLOB%?}^(5(L-;sbyeuzpo#UKYV;lY^Y zf!nnXCtjLFJ=Zxk!%}4-CjYJn&(sGqzar4`lNr$cA?}cJ|7QzAepbJjwR46!IPId^ z-~5h|R?54Vr1eIro&<X9(%T4^Ti>tZEwNRm3#dwT9eL3;Vmh``nM9Eiz}psHAT*ft zV|v$)vh#gN6W5RYkuT3#pN%rb-bfQK&@<DV;V&Y^BjEF=&yaH%ee%ca=%H<Seb~Uj zU5!qqTDUvlfZ!6(@y#&_FDX7ykg@V9O+gZa96#4hC+4>lgN0;{8n@yl2g?evkh~h% zvCjWC?R$$xZUFzQpYWLX@)mn#H=3ms*8GHF*_Uz<=z^S^R=0s?y{FFlQlT?N?`{v# zf1Sc@ESvz6-!s)MF!&~<`v_&9o10F2ceMtnrMh_QRuHUh+0xwf5UZMH1i3nKS-w74 z-I<@PPZM~++CMUy&O2{YKo>QkvotYTEh`p(_FmXmT<`;RCLE?`-SCtl`FZ7+N7V(6 zHpv=t@mAYly(nN_&3B!cYy$Qo)3Wlb`-@9;S?>Y3I%g87Z`<{SI%F^-;l#rx;-Lhv zi?4meZ4t`5Nto@YC>J{?A*W8LKd5NuEe}0Exopc@efo;y2%l!+8YnNSY<B#MNTs!Z zqn)^Slui_0GM!Cf@!V&zJM>ZW{&>k6HieAj0){SL4AQOuxDCSS+$B<Eq8ka^&sP0S zug?WGo>|80@K@7aT)571e=0=~KpTO4j`z7R$e8>^_}BNGodJD7T*&5t8fH@Zy^i%Y zER;9>rMl+wldfd<j|yzjfuB%I=GaX;3VlRo*?S@DfZp<%o^#mb0Un5Go3&WTsOPYC z*aw?sxR{^$GQ84x5uPkQZ#?%Z=tCXVFOzGNOg{aSp`7!&VAcz>c^3S*bKAcJn7%HZ z1>m&o7L3Ut9{I46pv*?_&{nP15pucyWIpehDowdf99m%<0w|3~c=uNqXejJXi=V;O zu|;tG3`d^}Njs$Gr%Db8gg3Z*?stQCGY8JGL_WDAdI;%=@#3}#?ma)1Cpx91j}0Ej z>-68{uZS|!cwwdcL+=}I#XZZ1eDL&S!6Yv-nk7X0ylJ5(l$FUk&ji-(>ymf%joq`# z3^**gUxI5e5DU?`z<omdWc2F_1KKY7|1m{nFOD}#10}7m+<(YYEEvK2NeLnrougJK zI>KT%VklMsef(KGU)gXX`7WnMkf}5@Y$iFaN4FbhDxbM2>e9FNEcf!AFEj$!9aUF< zEM(@@GTcV_z>DF|n-x3XpK*GGffQvWjuG=C(OJILZDc}Pdl{0(IZ?diq^+t)eg4?X z&zenF^oTWrmt{R`jYTC(Y(;tUN<Jx#$FkiY<AuuUpJtr^+Z5bHRdL*R!WY7-Wi*%J zd%(?(G7maJSFV4#SuJ(<UBrLikR<AV?kxur!z4r9ZeWl;st+cOfTe;@4b`hT8B30} z@rC^Nw@6agniymoVAvtcYi~Paox<a;e`?2KoTBckkqtx()CT|3(4CL9N$O)A8`U?S z<<Xy_C3`Yd<egx+{y;jtdDU$I_{K^Ao)D$Wa%2#mfBC;x;g^Wdl9N$rt1>(yFaYzu z@H%fv$KM7yIdj7Jc5zshQDy-LGlj*vXucMV(ENlcyUIJ}78*s@Y|Uy@lX$GhJT*AZ z!^icG-=zego;lgv*!+zCA@T-WHT41cR@h*@5rSr2eFljf@ixrcEYom?Rb{$2)iaDs zu9QhTkZrMS@okB0UE9)_dph^R_;`~&e5h&kduRNs>QHJ)m}Vb8TmAH$<N3IcEQwxZ zxBt4$l#pJoVYVQlv7;lgf^jZ@Gi@t7gFcz3?opO{U%5eko9_0NgZuLDNdyu2ti1>9 zAIbc$0t=8MjTCBLfD7p&8NT5s%Ff-;pr1ka$WqpE|F`Kz1kb0{7(ewq{75cJEetmr zZyayMYSHMt3W&i<`e{B~<P9y*4UDVqyq$E%Rnq#c!;sqZoeRR-WeJP+T+q8jasnBi z`9Q!*?dCsgOIEwi{`tQxYQc5zOmnFx0I&0L^(;g^HSMk93v<d>diqJ)UV#ICjv#T{ zq00EX*`fV$Q|de29)|q^o-=DZH4!-5Vf5buOYlf}la7J$E%iVwrs*~4iYrqzXg{il zIgm`^By;bl6Lo+8_v9F8yr20T2s|x?-R#WlNnOQ!k1wZo*Gb^iin|BMosZ}z)q(3q zmS2>q^RUTztlt(>ojJ<P&jeYpXv=g+099H0LXzh#7>M1<k0v0kAun?px6uj&yxM}H z={9)w^qe(s@!j0652?SpjsEauQrhlH0ChGP)8vVkh^oD(aP&CPx@ndc`{i}*Nd0wf zqt;0aM7U42*HafRp$6ML8aC6;3yMa16(35wK08^e)+;r}y<)1!op2B;0c4EjTng)( zMd|}M44pThcrs%NW6EB4r|Oo3ECJ89#oN&*wg|T&I|KyWzh=mP7REl-9xL9*MYDqE z-)$^HVvfWHBj3YaPFYG}G7jih#<vQd1s}YKSFEzM&q)MHbUMH5rw>NLeNMBoHAr4A zyMpWplb5czK^Qr_C1>;AwnosCjajZPk~sqjFR3z=PFWQ<XMMK*EHo8XxQ!GxKf>ra z3Ij>@$T##gvoA*mi+s@wGP~RVV_|^IFx&;>5Pqc<Ds;f|z(ym}_!9Ws>@^c(GivL0 zuj$2GYP5x_tC_Jt_(rywJ?n?<o~SIqO^+-}&I_z%Ta2a_y^u@jsA^x@h)m6MO@Aik zeU!~`)`_69FSO^<X}Bi03@5xjhXN&YBH?MVzC*r#nWyE^t)_MY|9dnE+P5gwuIsai z2f_selnMF{l;yl$Hp(hudQO0gRCG4pLU}^AFv#V#H73IAHo>fI8f(rxMlQM9q{~{G z)&?od^&FHKWHEQ8a1<z8hmHO4dRt{RRdW8vjqDc#ur@8ckXa9m7+20?dIauDLdN>u zr<W0a=I|x-R}t=yU0nIV*Zxh$`zt00mgnWh_w}EJ<pbpVTJQa63|QlOyfCy-lPAzc z<KfZs*tH-2H!a+559w&e$do*Vm~JC0t5?K6Mpe<j^SD1evJM<GaM`Ue#7K$^Pv^Lq zX_Yh4yLl5XMm7>UW-|#LMxjMKOK^i<b-O>|0I3{it@&!th=x%*K8H|N)J4CtgM#f| z=`y$mrD+@7dKFc+)a9a$g>2&>Mq!;a0ZDnYQ*6^>Vo>n{+OaD6DExHJ?HC+SBs+To zr%JnueBTbf#r=n{2!M@&PY)@#{R~>i)3pt9T9>61ExT*tB=1l%ug7UTOeJtphd7;3 z+Rb3@7Wu9ekAe;P!&mFt-!H;V5+l7(u(q`Rma#{tOuVbw4>`MlQi0+&(x|-&K=!1t zc%6c@(!art&NgzO{p+Izq+=Y9$|l!WN^+kzuZoYm-SMDKna_of`6iw8oePR|i8|pz zQ?Uf#1e8YBPDy+Dkj-cqz0CU(gQ?3*DqNc~0b?1)_no|9VmvB9Z(-A~B6KM!3I3YT zo5-T44+wW5EpM>j!rFuFL(0-X9QIdo0_|Vwei+NzsGoU~cyc5-(3HYT*NLSLHmzvU zo}!oAW;67d(+Q`8LGHb9w0uy^9?2^<vWkT$PtWO9)cs`_<Ucr{<UaI8L6p-OhD&dA z%+=!~4_i?t1O=@r=MeGm>NNC8*o(gDo2sVCH_lx)wL~b(`eynvP#1Xsk`d#28RJ*> z%K^EpVP{59X}$O49V!_;89+wnXG$G4;~|gEONrS>jQIYOB>qTO4E<htmb8~N-}WZQ zPQr1)j{qWGQ1b#V&gHC`e5G?W7B+IJ`>Lr_pze7o$5;^1jhJ%=31?_?yVfc4%;K>c z95w<xD+8>sUh#6M&@k*O7hLFa){{}i7qtUf2S-iK(AQ990$yvHrVa1@_=4f7U)9e` zGSgdY*yiOH849wglT{zA1MN?#o#g3gxM(FzCZQnb{d{+?D)We?8c4jiM_Zc9niHF| zdK3%J>65LKs^g^GcwBY-nH#A}&@TY!WC`M*fCSd6Fl$^-x~Ily`stC_Gp%5rPHumX z)2Uux$8Sn-L&I3Z`HToDQcRB%L5#vD=#xQh4o%l2hA#?NT}GrCwtI2x+`m*a450I^ zkXHNzXWxHUP+jt`cQ7>@`67K$e(`v1R|>h)htrp;Pr02)DA<wI_HlnL;E!Mr4tIt+ z<WuB^SDY$-JJ`vL6n-uBI@*`a*ZxfBwhxwJ>zqS~K;b4A^Vn%N@-QI-0{%xQyAkwg z7n!{UJmOm(fqL2fLw)^Q1JT0>#oBtrd7h(RXOS(y3T_n;>Gd@UoP_>B$ta3?s|1o5 z_RDI@Mlgy=@fg8a&`Q<3-Bo`dT?}o=B^S<$^<`+P5nG)-uqq6fX<ej^*csy1YN?V? zR}9dNGFefQDn4VmSd)$QzHwwPgq5-4{bO?pJZj2(0;m=Cl(!~Ev~0~qoOQn8;D;x| z6{qA;9%r^{%vzZfTwTlaT^cFJpH7S$X~~3tyMtzBu`$BX>;s3Dxca56gi{4F3y1=N zQ}oXt18qZ4pQGI|iCHg9Y#(kHCGbMz<z#u6XM>=mp?U*uE$@?D=yt6;ako*+2)ErU z48m`<eG0pi3x=opouS^A`+hWbI63wG<-TF)jM}(l%vNDi+rbRlM*>Q~({aeTF{Urm zj0{-OSl7N-E4elxiA?FL+oAI?a%<WV_Ymevu}Y%Kgi|-Etxq+i84?#guSja3gOgGj z+xz`*fs?EV!}a8pol5Qt=L}UE!V!`~HArSPRh&el>n5)KmO+U_01xzaMxr?7xyFV_ zC6VE%^Rn8LzGC;<2BeqJepw*p6{x=gp-+WqB`fytkTb_nG<&Y}Ip62RD&y{vclesX zhhKZGQ-PEm{2F);Q153v=n%j^)=NDw5D||-!k`4lGVi_B`tQIwPDX*}#mF?z!pcc& z*+80x&017_q#IzPy-K&K25r;*3obNV^?A!TEc%ngT-L{Bym9|w2!zk!#{XrAAwUh5 zxiFYwm4(&7T;gQmUkc@SySXdlfmA`J+219(5TXXfIP|K$m1zJ!p&gYTXLh-EkS71+ z6_-t3DEqA=od-mYhudHaoEmd((7%G_acj_Sl4Jq7wbm2ItW(_Or;AfS=rhw~_>0vS zZa?ZVw-tJn?%D1vlm-$$T^P$Db1o#F>@61a70Az&GK7PLi88Q#-9}}va1)-^XUp$! zvrc&Msw!c<VP;Bk9hB|8oCtn=d)_}*OP6wT_Cs5|__(p(&||5Mqy5=^agTr5sX@ks z=-(8?L$XwT*;lv$D9$I{noToaq=YtcGi?9uzOudPdaSThdem%Mqgob_V7Z6y4&`Iy z*`F_F`kR_JIIaq7_Q=p-2c&09H0S;E-Ngp=Z!W_dqs~`wwtbCtF{b`n3<*E7P=UTW z+Nc4E^8UfXf0ykm@z`*Ba^jQsR&Fn2?#4S<Wx_4pRp!f@57mQklykPmjC0KDBa$E8 z2<xmb-mrWRoxAzYgmAasW)WUcP!KM?H{KP=ak#fpx0;pQxHoANyg0i{+^cFjn)9Qr z2ckuGHw<_r>+m7xI(EGbPDt8nJS$<*b9acgP3ocBCS|7xtMt%pX&E8*?tBcUA;#h| zkPtDUJhMGss7@uVY`i3D|8b;gdt<}$h@}I8#m5?3uU6?_C4VOn=4?WN-kA4^3eQuY zWx!sfHX00%^~w?p%w;!V^t_Z<_`K27y!NctnYiWmT+`Fz@q@Fcg5_!V7l>yzQtS4O z&?tXa?&-~27)e*cI_>Vtr|`{*vh4lNnk`eFeXvE6)h9LjA>Qm7N2@}U#(~fllH~F) z{>XjY($X6TA}U{734iUH(ZC76#*(|UN}Yc;pWK$3<&^&UX&%R&3(cG_1KTl3^3uzm z+H)?z$<jyzVQAxWlFg`|eFLyJ)*JQ_aOwRNBHCou169xfn6Rv0978~PZ*W5Q!VW)^ z3^vLO-J_vP^K30i0M4zS#vtD?YQ*n)W_Ojmm^H*$-?|N@0abV*c=TGQI8xi-wZ(q> zdk&!P&SyF3_g?P<gjYM2WQLMtN5Tt(rGr(p1!hY`3{LZtDMQ-n?d;Z-SM7b<KLsBC zfcotX%p4Z&JGatYuyakqrbt2e0&8olfibm}ECG>3^yQA?i#toVB!v3K`o?N*{uW7o zcfJ8-=cZF|<>kAwlbS(cyKnm=-oQCt7nn)zP&WrQyX#&J`;NsVH;?(wi%cRjFLj2$ zhB;^An5_sslCGQ6fIpdHm*Qvb>Nf0ZSF^@Ho=yXH((0EBYF>L2;5Ka_P(slLCa|tq zlM8z+{6--<kjuQ`BM112x&#E*uFyKre*s;~$<BSodr7f`-2T&kl+O~dOg!hs>ZK63 zwz&NyxONP%_Mn3~zqa5f7y~Qrm+`>abRYCZNv-QC5%X2*ire5_sU_q2jT<c1iyIzb zZwv18eJDuDlk5^gp~Ds-twAu$loY(vg$5g0X|xi!6|?xWdS2zLFs9En=TGY&WyVxB z<G!`gN)vNEnA@oAaF<o8XKI?5g1x-nO6_z&9L0_X+c&@7dRZ@>;<;HP&*pBn&YPTN z*@I5?hmWYFGXF=sI&Pw~s3AZ=b2i(vH^6LXSWe)z)KSi6zOTA~il+O)97D5TX;oG4 z0sj6BsXo-r17m^o-2~o4aQU{woDMjZp>b!@rs!p9H#aGB5m4HhpRtU6Pu7hLWO1`5 zN2a^0L*T`($Z!zhAkcT5=K>erVEok`girm9htxjJJSoL_dyY%8+&d`TVZ5qASf}2V z4Rt+-2r`?5jDG!lzA@Xq4#DHJ@Bnf38d-0u{Y4fN++pTG+*YGJB6hiBi7j{aMTd`+ z84l5Xi_O4n@_<SN(x;*U8_!#t4PH!7S}xmvOE@wtE8CBP^6v_EBQw#G^#fwz44xW; zw9Zebd0eh{rbP?8Ws$ZtIfd5N@|r#T6_vHiW5Q(>x9%Nk=0g((tjbx?xq6fH^d;;E zICn0*%;m^s(IHQ(C(S!AGeuOHodYSGgp&&seCR|B+7<^SeNw=5za=l{cfLqrTWx_9 z_F0?dH;*c$%omQk2;(rw{@0&gqfhWt=#B0Ygm`GrrSQ&U)Rn-&SO`eR#+z&F<Q8)` zEHFkI>Vqn%+CzBS6KDHy#7POS?nBSfGPsNsl;DMKA{aHU#e)tzNx*^H4gemrcmF!1 z)xGdhbZFJh$g^&jDg^kWsH0JOorUIaFKt|K1hDVrN^3f#Qam`;B0)UU`?u`J4j<a- zcQp;KsAJ3S=(QfQxoame$9sOx3T8Uoh*<UH8FG6SX|>>;YHyK*`(pTvXvj%Batn3@ ztz^gg6irMl%qn>+Z@aI0(iB1ZP1_MMJF*5B_k&n_N|1|GX{*l@g&wr{GSt`LrbK7n zB&8Mr6r5cv67IkCshPRM%LJG3K1I6~?MG)NBiazZOrbKX#Wz&`)HPx2uypnPD&y55 zF_q0eAXZu`E|MBE%OVf?a@EZt_4=$&gC9{@T#~Ln?i^*vZJMtbdd*J8OySL~z`LC6 ztL#S;PgZqGLNRvvoj=|^cy42#41Kcc#AZY@_TF6beReVECNHXxmOL${br_J-8=7vW zz8X~YqoCa*$cTC4cJ>jT!ZpzT>+mVHMfQ)mfoF;2C97yl2y!5mMd5&=VEzWlo0}e* z+(}h=_AWZmL;|`Oa7QQl#zB%)NT|S|(dThg3b)8Ek*m~4h~&rodW7|vY2{q5i#uJf z7V?ey#!ERHV`iliJ2Wr`?KU<K0sD?5!I-<Vqh%75CM4Cnd9ZEib0s1T(yfQ<p<Yc> zlMsXOXAZ`Rh)wS*kJ&OrJ{9QdF0GuN-+nlQ57kr;tZXxzd$($Rhn<(Q^BgE?I9!;Y zeWrViXM4)%K|#36*bS`85MDCZ=Xa##Pr}N*T7+9qPBY!o4($CFnwswXPlGq<P=xv; ztS<K2_pP}SKWonmZc3C9on%#t`uMQzkO%g?G(GPvucscFZhUNb^?dg!B5n^7RNCgt zDzLh9cFBNQNpY=)b>7_y117>K**(`w2u-%qm_E^=dj9@diVO6)DkU8@MGbo!_E66W z^LSQCr^O3ucY#v6(MsDEMbjHOY1ShZQECqF)(>ep(68aQ=5-dS@*qe!?(H@aTjr`` z8yj+CR}s7K%I|2IB?GL8<fTMVNtuwz)-Id17Uiteqp+oo&Z*=oHG4RM(D3Ow9A<j> zT#famdFxfZlcljYM(b1w*{TQWj6O|_(`AKhoqV^8i^D<Kk#HmE-kSZskH*=~d}2U? zRp6>{>MoEL$RlU%>IEfb^0&QZz(>aA+uu^}wr-g|X_Cp(y#u87&Dm2|UjGXpR=x<b zKj$-^Z#I}}1=&rqEYM~<j=q=rVH781GpWDU7Ow1$PFflZF46guEn2-sU1yb3q+B74 zsIi5x*cjKE7H~+>O3|Jg{Va5SMw`uX<)tm3Jpm77`;9tuBLJ8Uymv>68gXmnRF^V< zt=mK^hg%#thS}gWcMHI_YeU)aGt9OQ8x><~fKg}jpQ_1&hE&=V*uy`A*VtcCsk&VP zVE8W8($V15ioqrO6fGsW3^-R$9LN(QAOd{>HfWtgNe}1KH@d!O>75F%lCXy%(i)CD z<xL3dWek7oQJOYPEkY;#**)g>JzJzvYmWJE$fynvqK%FYcELpi7qrA%hd!MByF`}+ z!k`YY)%5<tZgfmVEwtrMEyCwJKlpfGYeJdV29TuY>pjPv``5QrWuwfUtsq{*`Odv9 z$35g9u@Kj%lXyv^!CizWI@N2t8;FmHxfVa*B~Q3%2pl^#(iHg!XWMkNM@B)Da>JxG zMH1q~Qtqb3<g(WZS<Q?G05j3uZBYOK!9Xk&ZuPx_zQ&mnAG9xoKIIYrtuCQz+NqZZ z=Jm004Y0;%L*y;So>%<QaA|q=BNbCMo_;sH=<cR5&edHHKee&@!y_x-I?AD??ja$? z;`5_MriNap8~|Zet%!>D->{{w@S)6>>BP$*E)kO_4_nbJQWL;wF?pGD^(9>AKN<Jw zHJMKIz}kFQud$QQhXx<1ULB%gU53y5s~mXqgyuIPx$$RWKAgms!I{<ESn+DkM?&C# zvl1s-wZ&*Xf4K*D$sAHb{`FUXd`+Ye5oiWl<N+~BI+>vn4HA=<pT;{UcofP$icP<{ z*z!gqE&T2NqkdDab)Gm^7lfox(aLNS^gykkp$H7TE{kRXNHf6~KXt`}kktX*+vXyY zt@A4OaPN0sV>deMwi{wR{VCUCK;R<;uaf{;${cHrpm+y;=dTu3m<E!UbDMVT#ImQY zfl~qA@o8T@i<TdSEsIX5qM}wodQW=7u!v9$RQN2^b*s|9iP3D*<N=uYe11O%*kW2N zNxS>gNn<=q_W89c*(nx*1oktnY6V`(Nf+*Prde_PCZAfI=mK6Lo4t4t^EUDY)dvGo z`#W$BfWyFb#+li!+GMuTdmnI&>@<(uiVCrzDIonI-0*N0fERZvjjIWu*Xto(3XUVs zwBHhkCl7JjO}J;bLlmRAAH9E?5iXwq$_CD++9WI(%*a3oa19!Z&k?RYvLp4he-Zzp zgmKOYK-t7?6NvLUKBMl(EZiJdtRz}oco`GtVtfZZggETmw@V><-an}GtKz~p{5?c- z;m%>_xhA#v6ujiWPf!qrg{&uv)BlDL<lhlj&fgaW{zD1C2Bv_&^Hd=`P&88OHyq}g zXI!Q>fNfAPfd#aLeL}MSn|rh0HzuZ<Tw_X1J0C}TTnz4m%AS|<B%=zCy)n%4Es<~D zzT!B)9pW)?o>zMV?Wl!R?QzMWXJQ5=X1M!D8wf^1@d!#EqoP6c=?5?zmCx>3I!Luh zh_D_Z1wB2)(pxtdPqjOB^`l#5N|stuuR4aA6RUT7P|_sq{@RVt+G6vWi!IqfhN9GB zLjWr%QIW_r&d_%-&Z-g~^pOv42*6DZp>Ooh?ap2^ZGyb?wvcOl3xR4dcEdCX9l88~ z!HHxlSvCn?3)@GDUoQRDLeG6^Q0!Yu(SiEC8+<{SzC1tsZB*B$09e^IjWVF`ZGV-x z7r(XN5(5o9Y8Un?nGawVD(e%OZzi!uPrdpLL|zFPNYQCGP34+=j_^<~Rzr%R8^Z&X zvSQtgrfVEK#HH%0oB7wGmQ_q$59(%*2EKzLAIl7>h+geav`7L`l8J6SA!=jRIKMTy zI_ZCYwAv`WI~B7qJrt6CbHXV}X0>T{*Zwd2KtkNDS#(WPvTZ{Q;S;aR=PWcU9N0~D z1RM&5ksM;sFu$V}hKlwCY=W9)q%3<3<=scqByMWEt?u})rnZH@*?}cmH8P2&TD7wF zHMAvpKE`?~Wz8y`a~b#ne(gazL9+O>JfeWGiNXuqmw`sSQ~zZY9KfA_bTC85NYuq1 zXbqm6#4SdvJx;lOlO+LQsW$e(RnpsN94ZFXgk4V7)^}{T&MOf2I@sE}lMs;Z^7wMD zVk2IMJ^ffR0JbhpG<0U3aEK=EP1%DzJd<Q}Fko-)49OuC43CL%7OTfBO{8m1^g|+| z+cEu8=HcG3y+#;BO*9Rtd820kM$jAyS~bo>pb{fe(8rRRL;GP!QlDa|1mZIssiLhC zyZT(RP;JvU5m5*=0*Va~;%3CE&)fLN><I`-{B;FlV&Zc0&7nl@>6U4!{2F9TQ??nd zAj25R0zLEj4?XYwVnc~F<KR204-2xZA;$+6fJk6k4=5@cSt=94Zvkq=v%U^!Y<H%E z_SMHb%en5xH9ne6Zv;DErUaWzs`UhaXqtKD9Tgb)wUcx2z4;Zd>+{z#YMxjX%0<d@ z_Jxu>VdJqRl>UrXnc8}@t?J~h*);Md*THa}+1(s@n93{~=W3pXc16wdCK{HC4Ev)~ z7wtQ4kqGiRLl_HLaKnp8h+2ZPl~7D$+v2C}8Y9Z8?qSLP1_hZSmUy8`NSIos7wl=G zk6QPRo?^>@4pgEl>^GKp;9Dg0j0p^~HJt8+YJ3}k1L?9BNEf6gn1_<b-8(-|y$SpX zT~mp2j*RV3r7X{NzybLA^VC0&79jf_Ux2E-wG{?wIriqQ#GT_~7ylfEV)+da0mL2m z_TNrt{jPx=%U}O?ChLy{`Ijj4KQ8*4-~Vioc<1!ntN-hy+#f}k|MP|nNo@W1q@I+B zjsb5tAWW4uW%|fo<CFd$Mhd*_Mrd_uZ^c&Ba_@D0TsdzQTVFNNsvm4ks~d)&urG*{ z`;IQ-YNwl`+OaCw95Sq;Ql4QY84qZh`O`iZkIq;KJs&O%=Io1noY@U~8o1lh&wFZI z;W2Yi62JJh6@|Z9l0n&&p&Dm;E4PvFD=!>vmUE`*u3y<+UW1V*#ARuhhxSjpsVFuo zmd!u+NMM)LTAvvcb}~~a0dah`9OHBWS;H!;qhE$ijccKNMs^bGQA-0xze+fNT1WYt z{Ra+REzIIT#n<3VeVU%9)60m~iQ8b5@`ow<Po~mFp{ioZ)KePP&!U>&n}Fu80_Crf zxRUVNh6D5bL{O*Uy$Us;S*l3@sKAM9!ab6JTEVz!A|kU&tIe)Wx+-HzjT0KCx}cW} zO}vp1L-G>f!*G0<?WdTPxiTieYbs<!2&oSiH?82_EO>Eth0hV|5Vrk|l44|k_KHMQ zWp%k^P59)HT?@6eA`N6=>t6pPSAPsh{^O(qfhAd7do2RgNvOUm?jzCO`!ay0#Px}J z65Gqkw{PP>+TUFeK(7|t&xQE2_6G?17Ew3(QLu_J0K4k-JvJ@Vfi=ceb8Cnv1X=Nv zOmR4xC&{dJcp%}FkFHMkqu*SG+6{ShEW^oxRWtR||Du{Oel>^L#_&Br7;99S@7V$c zRi9tS2qVdV_d)2q_ff@LGY1^hq+mq_1bxN1LK~C#pE?WH<T5=3Dz_z>+59@VgDVjr z9(_ZxJvA5z1)_Vm2=};`Dw_l}^}a&w3waY#xV^%p{fkr$twZa`O^{lcF413mRP*xh zJsS6M)~$OL;*J6H|FCk>Pbt1N$tn5uarea=Yhn>?g0TYLUXk1FTIFA;xy7G6Q)ZD* z0~&XLcAbkwzzqe(ANOc-N=}1Y4MxE+GErR{XVKa{iP0&bJSqP;&?lU}ld%7<HoE_~ z>1Cg4TN+qrtOPV5G`6stKLt>|0)=x_i;PmUXuq?;v>hhIOM!NNrK%XLXfBLVC#Y^R zl0U*Z>LO4!<KTudmeN*O5T-v;iw){D&FTDd*5js|Urir?vudi3AQg&$hc5x`U#>NH zrjeSP^fppF`#~G_=F;vsd`<gwzb2GSN#?vPfu)D>{#brfq$%)rq-(C?(=U5qr-u7r zZ88M`c*)W{7P?nI@HM1T;hB)A<)idEqmG-y?ElkCo(;Z*FDRvgK5fyjEaI4BU%7wC zJ&A>c4Orn8ue%i3+&cmrak(iw5kjh?zKMx_AV9Y5qR|h4=E1wDxQkVdf`<jdX&~A& zm1K4&4WnHCA6;J^7G>7|O(Q6<Ae|y0QUWR+qtdN(g90LrARR-fC?yS2qf*k{HG+~7 z(j|h#&>)@TduG7ceSYs;`-j)=I&<!GpZLZnB#S&M7;gUJX8u(b2MaP}Fy|nT(+$;_ zf8u1A_uQRhaOWVfW}f`V!$irV7|61iRft%8TZGeW&s{>j0p%kumo}IRB&oM_P5Hoi zzw;?w<Q3?1^{ch>h8_G?-{Q^c`ww!(54I}cv2bj-ttn@b7~kb_V)aF$P&`*`V!R3r zZT@W<+!dS^eA~+(+);@r`23B;0_*8k+;;WK!41N!%yt>UCM;Y}QChEFWu<r(GS_#E zWup;VnTuvi+K#h_s`_Q}+Dz&V$0B(&ecC5+ZLcdHVLGT-Z6ZdvD8;k@G2y)nuR6$A zd<VLVANzzGK;*)A*c=U73jratScQROjaq8Un3j+`e`WgIl-3k2!Mprrf(uyM_$^rY z7;e}O7+F}~a@I<*ifA`fOqqZ>XBM1bGY%f1bq2&?_!H_s<TzZNZSCQwwEWz1O#r5? z8+{_upIGmikK7HemXc}zF_6h#!-E^_u%L#mX^>D`Va2=1qSnvuQ<>L1<VNO&IcR^d ziP#{&eBf-`NnVf%c6^USSM8Hx2IXnjrr3ck1f?D1P^HIb84`JXaDGZ7^tD)~m8ymu zP1vc-;mbEt(SG>;i}03F5~F@XxH&;(y_6xQI4`c$Lrp}F3LLq)R1bd!_ohL_EFF8G zxA5i5IV^udSnj9Y!E14l<_Ns3_)Mf-*9HLle+TGOr5#YE&R9%i`qELP!vAnH!U-H9 zw;!`U==w3^2X<H4M=@8zxlY(yqdxkB8{a9FmT&O59VEKN93L!XhHtq3&45*$rAxe| z6y6h6LOryDD~P>|M~v+nD>G*D=)l<|yMq6oqH}1x`>_uVV&s$2^SobJEEKf*Y+Igx z>ufb(F-C5P_0>=~B$xF{g!EVae-U1l;+WQTfBs0JjEBf2lgC3!0f_{)%FvvzQ@r09 zkS^G=@j&}?4wn~=WIq`P(32re0Ca%UO{uT`=jEbsYp5n-xh@-~NjO$_aXHJ2I98fX z1gW}*86h8Cm4;~O`=9%#*UdeSfB(f(?)-HC>cm7~@^)M#aKI77I2?p}pN1Ci(YMqo z_VQ2I0lwSUZx6A25B?Z_vU&WWYZ)R5-qZj^-A2=S9Ssrpy{4Tfm)^1A{yB;N@L+#& zE(_5^x~IbjIt`$ayA-8#t@=5=$jNp;iO6h3Ac^EiEmc7lHYpFspKuB_1kFdDH%mvZ z-&>q*hqWpZEFAes{QCLNDPnt|LvB*#I1O!!1f~4hqGn>T*$64{4fmS=it&DjFOPjd z^Z_JG%S<!Fu&Gj*wNr1%OYeejW>?%7ryHq8&Y&QRM*c8JWkm(D@#o&phIcK8AOS@2 zeR~oGP*4Mbzb+g>CleW$0^7DXx!BfTG-YRaw+Y|lok3%pmtyZ5>e)u@X|opDjMx?m z1%0TCzmCm4>9bLB%Nwy@)khY(ofk;j`=>&C?)sHi>=j94BD;=}T>Z9HhISn-iDm@@ zqP3J;1=qiFXf?SvX~;Ws*C%<ZM@pU{@~Ae{rbrZFYJR-_RH8uJ45EgYir0-_(dHr$ zwG)fapc?mi)TRduik*sGfUg?c*H5PeQ}M(0TZD5s2~l-GdGW$=iLr)0MGS%y<lfBF zgDn$4llpeD<_3Ds2UG)B8xOi1)*62zox4R)A_IRvIEaQ{gdgjvB#EWXFFB5mzqdbk zeR)5&k46`bysOl*bX!Wj=rm9Gj`QVsKS>`scV*_Xwm5XiEeb#{h;B5WkhjBjoO{5o zSS#5A4c35+NWRpkUSA4UvoJv=6<*#)HYCV|S$8g(`CgF=m;Amr6+mTznyJzhJG{Y9 zX!6A0z;D>k1fvj(w==?*P@Lmgc4H88GwRjPygw-2`-UQ~708w0pn9M4T}ddMI_<09 zTel)0(!tIbD<zrdh~UXIMX&3;g4Z-#uifpo%q#w@x8Zaz@wpVC66*HD6_p=9Wwme5 zRJ5c#T-hkG9(*4EPf>I7XhlNlgf7o>sfBR^n`cYK?ba*8EN<*7NJD3sfQcftrNP8g z1(w~I9f{o9u&x@FeqkG!8c<rsFnwQ!IbW%UHIJ=>HGYMW4VDVOWLhP3JwFU@D9W!U z>)4IDNVQj1!GMmMW1Zmzb1r~Wy=wvG!``N6=fRtby!a=$qEPbIh&Zm6En7kKSm^#l z@$1IR{3_YbEnki_a*h~UD$YNY6$r|sQCiwI71_NX;?e<on>RlQ0DOzke<CEI&+Ct? z)k}^==+!fs)Dm1X`lM#G<qn)_ldvsu+1_Mf)nc=htiHk2{Rt-T<w2<w_~|x^Kc_Sh zx+qWAA5DJv@(C?K`F~&o`rU^2u1i28olEaCI5|I<e19c4mV7kD3JCL!6mu1WOqzXV z;>mY{xe_zbN3fBt<p3Eng9|ufZaOGebHy^!wodj&0al;?YWndfw9re9IqIc?N|r0? z<gG^OE}k}n4ZeI9x+m3->IH#cwo{zD4|%i2q9*~>j#j8Q4^mTku!TDlTNPEuQEQ=c zT?LeAob=MqO^)}cxO5zg)FlvbJ-z7kRX)UM-i{wSl!TOeI`RY23A<?T!+NuTI-C(; ztsg9;4MCA+E-<y=xt@AIq&l*x&~q9UF`b1m)~xeAXr(ZnKgSkV>S5x3wUg8S#KFRC zy6G)paBKtvnDqH51;|I6Y~xva*%$YJ5SiGjJlx4h4AE415NOd)Hdiy>bGRFm8)=5E ztL21DPJYqC$nTom&hP87iOAbxwLsEa9g;j!jDonK!t3{u2@o+Li}S(|6$qc!IJy)! za&1fp5uZ?4LZvs&K==L2l$=K-c*j03o?dR}D-2gnBa8Q1{$QE`XTC!@49Oj!7IA&L zxP?e$Pl$lz&Rm!|R3C)O7Qko+Li1QYlvw>_%WnLz1JdTf|KsQM_j4V|Bwv*#LDJx4 z3w+RUO)n5g7l){-U|J;(bh8TTs_K0a;?h9c(n2#mKY6y#-34NLR+kq5!lYpf+(HMz zWq_!4G9K?p1)d9aH{L71771wtb%<6b=&>>3di-R|Y_})uX?!v&=`Hwkr~?`m1yR94 zUI~B`^7`9rVCf3jX@CT*<{yF(B~ZFNY&o3k!41^b`fx0A{PI>)tTM<f=yvu5ldz{f z!7tlC0JskEU|)5%c335D0S+U^Lu?KIul}T?t`Uk*Q*p<ed{Sfl@NPJKNwO1j92<g_ ziK*ciXkmLIW{jHgFiqs~0pMKDvBevfjDfOH^?c$u!TNbHV%c@J`k#Q;C~7@$b$w<4 z)zx3|y`q+S45~sx8?4_^SMp!Wr8EhnRv89{%*Q>KpWU@_O#o_tgG%j%3Swoxr<mV1 zWfM{4?y{1qa@)ps-yv8cQWW|;>Np877<PUv7>s=`ZSzDXZ)}B_gJKhPcdqKe)<|af zby_nZIBj*csBCkW#ZSlIhIJ)B+86E#Cn{+;WSFv>q5yIq8f*c(hu#`d8!!xBY+kHa zoxDN|Z5gQBfF%|Jm0T_Bk27)|&4|-qdU{cH-_ZRGJ+*kEa!^_W<89b~cfk@R-SYPm zw8xq_5Wk&5D|qyyv_RI{C<%m~`dslLS~sBff|gNw%R1@z__@mp(wE~nV(bN0-U=91 zZqQ#8{iq0ouoMJHH#t4|IiW&=6FLzyVxM_SxOEGE5c#@5t%M%L_yv^t2Af*JKFBGE zKNMpR-$(La@u%fyy79XBg6MOiHwoPTNg%dOUbapzrg5ZnWODTWClH2rOkbs?efvld zQ#JPP;rlma<--TR;QIr2ExKXfeD=Pgnrd|4_FFo*3cUfE0l8uc*{bw9dvp(m%dt1N zk4MXx5MaMYa{cQlPOC9MUU0sf{069B-5qV-Ccgvf_>xUv9dgvl1Sm=bs#KAJ`hp9F zbtQNh?(#t2g@~PFkyd>l7aaoSeqN^u(YYQuAs6z(1ZF$N4gWHa4{_PxveSQOhUJ(x z+iWmfe@S4KjdYLOwAHk8&rbwSr~aaOPio3|O5K8HcejMoOR@-+##z6=j_ApZ{ruY4 zb0$paTJ1{7ptgZsn81+m1{}Ndt}Dxb&J6$^H@F6vCI@l1E=CglLiV*Dr~Zh#VDk29 z^AH2ey{&9`WdP5&7}jI6DZ@8HMKLj$9ts_jg-qKtJao{Z;(t8btWn3(;~F32N{SIo z(kD*eI(r778n${Myn_TNQ1D-i9v#{hzSc0e;2@=lV27rj`<!o_Z2Of1Zdr0D`WY7F zl4rf9o8XfYGp4H@h1komOn?;Pc{8~a3tyBPLZ#th8e_)?Yqjf>9*7kD3)Dpb==Bx+ z5$1cCeVBvpq(lvWSe|zwHX#Hp)eHyUtt76(y3OsyeiQfUXU}2MME|+WP&K$gn|aol z&P(q+J0c*jB0A_afTB=J-+k$?&s|uHZY@F98Er?E3B`UASK*J)E|46{bKd#JoFU>( zhn3Y?O3M2w!UY{m#Rx)E1?>`lVlMhbW&;b5qaj_hFl=JsH<}hgcm9u`{UhTtB|asS z?fICc2(y=Wm>D0V+217q|NNmH!>BOdLg__Ex{dSM*H_(yl~Z~4**5%ex;ufvHk}`0 zPT>V|3x5ya9)A+2pe2F`9S1!*IzDKHARlLUE1@Vje{a*@3R@O!up>+<)_Dn4Mhkb! zB98*8@Oaw;1YAtfOXb~+QGg`2Uzopv1%K(@(s;@DLvK@N$MZ#z7cv{U-5ZGA@!a(S ze%Pebw{kH^1cjo{#s1YTgv+pzTSpAXdc%>ulxzwSSdvc9eurLv>XLC;$SoZ3v_b0h zEYS`a_*m>p9*Clp%XGt9H9PU?hYN3-f55HaS#S$@$1UE)(&W4VBq^T?VIVy*Jy&O` z+J^{%)90Kyu6Fp=K<7~RV`I8m$H1<ftDx$8m(VxcHu#PI+#BfhsdxKP+~ppW0LzO! zAp7wuo~(Bd(`(31x84tkJZ<iPe}<yOe-a8a7xetZ=*0Mj*&XqL31@vB3$?`W*E~kn zfrg62&VWWMgPY+iMhSpm6*6lHl?@d`k>qB<iu=Xp`U7nlwgk|Y)p9Qj%_q+{L;}MQ zt;l>q*H27LPvpQ2|B_6y2hX)&ya-Q8X2D`^c~X6Q#yh*|u?XL_g;KI2*Ir8+Q&vaL zjb!lvM>ACRbr;yjpaONP{!Ai9arc#x;z_FY`n}XYi~p!;nZAL1zGo6zUl_eNL;0WA zaK5;ZGm)z`tFySCk|#lLV~X;M!jB830*~1#JO+oam@MZ%SnG|e8h>g}(Of)svG&uN zbWgA|P8-i4en$#Ki0&GL3l$i6JG`IloWs4!`}sT^dz#sGkHg7b8|bQNMo4wp7D_3L z@Hfmj=J*+^bggfjaANKZqu!WQtRU1lovppv1mNx}uc##6v>hoL)G;~9$t^e>Ec6|0 zE0sqHrv0^I^G#>z1|zw1t(+113-T2JdVj}7%97ql*sp?50T4ZjFMb(Gd9P;^4vMjq zs*^8yRgm;Y)=CqqWU8EDlx(aHJP{Bft{JQQ$O#D`2$JG&lfjl}CwYf)*X_CZ<s#Lg z$Oqj$IBM+PbO~%3srXlYWHIrvx8`V`fo;VbvEfl2PKCZ0c?b@+P%y7iOW46P;lsUk zlhix(|Jl+&ZjWQ1;7QmaZD00<gB!LV6YQQVmuHB^+vmo*EHi8?3%gdklpc^Pi`dB+ z2!GANUA&K^_wWK`Q<+Um3cv^D1iEq<&lTxReS26Hd<t<Y^2dujvAH@35&X9ej8f%C z(rS7xnLd3wn3hfyxuJIm!lHMwoX*H&06qgvd7g2H#uK<dHoI~HpJg{aP|ZO>S^*vp z9Eh0>o#ZMI(CF33Qe_Z#-vBSb4fIOm-~NOD@AZL(W0a>^Ko6XMY|_oFe2)IE^v0l! zdw5v8o?i|*VciDnM^qMz*p=SD@60+;a8;>fke?5lS@RO5`AD2h5#yIixN?ozvHjQR zR%!v7Q3zmiQP|7!VdJi*qo$*b$}e6D>#(AmhX9^1=Jw4eh?t=U;J?8X51yywel(!) z5tWnw75SkE*B_F3a@9D{N`-*t%l_IEh<5Q*bVWjR%2LWcGH~6tRkb1XPs$B^0)Y<o zyUh1!3W25iTV5_+`YfpcVGi<p2yd$U_m`0@a;Te<>)h`c4tfW93>Kvin4VTfFI%w9 z@rdc&0mxWz>3@T`$Rk>|d|T};#2BuqdNG=NT=1yaTE@VX-e9u&ol9@03A_%Lc-!7q zHMeyvG9~EiSWMV70F`Qd1@#9n1&+}Bii07)g!0};0{FKV3iF%<u$W|MM6#2m2Fw!X zGxY7{o=gh9F{(H9*Qr|ZJ-hHF6JM6@7(MHkXDpABN;6CoM&DU{IwaPZ?}?;L3Kq&* zeqMLr?A)85f9TltA)6nXc?b@_vuvV98aaVxNB(t51Ch!^bMH5%IYHz@=FSy>ApSM; zX-%=0k{*=B*7LTNkxl-&v5rGa&G_fwMs{gN<q4nuk36mTqmXgShDUO~+&}uMe7IZ6 z0&neZh==p}oFIk<NN)y+i@0ulT80FT1r7jVl0l+n&?=#5Jsw4go&9~50+}G;>UXmP z<)UOjNCP+ime8=`qf$vIAG21t#FImi##&3;xFA4ZL=wew9YpC<8B8foVVVl^QH(H9 z-wTS|!IQ<V1v}dSBiGzZ2u$JsnZS|nFZE@h1U4Ct_sCztT1R0waMSLU`#oPA+y+&} zrpe%gmrsjXgyza9?0j5wJEVx<Ea!`wFXovbCvraS18F8V4Tk^5;i;!__=}1HcD{4E z4Akf8F(!!WFp~+rxyJ2Lr{e#W;)1E;d=Vuun2{35PMkxS)w9zEGa&l%SaDk8oSE~N zk=FA$kq)-E7zoU`o=ZpvJkY3gwd;u-Qm>D0vu}RZ|9TTaxn;VYEW!*Og4MjQ_->Pv zjr0FgARNAbiwh%~ZDN=BG46)=1`Qud+%p#FxCVjI{VUc5WTA}Du(Yq-<~<BRc7pKA zYXTd$t+}4wO)ZJ;L6Z0@(4pEzu`lQEBCfsx;BECY{lRwkdO?!?TVr*motma5w|Ktr zV^)z0D|I|DCyN^x(Q$gH1ro0!i6YV>q9P$j>LM->?x2c_oMQi*WTRTGGDevyAoG{j zy!G#zD<%7S!VlAvxew2T+H&T@{48SQwejt7uVK1k;9VV8L)Z8~58}U%btaH8{XqY+ z+$L~s@~<Yl4MbJE<Z*liH~1av$m5Cg*#t6rVu>YUP%2&TxlEBODDl6)w&8D*LpdY4 zy!1{a%GM!PC=*yzp==!tgT&9dYg;R>|6{AC!RaJ^fj-9t70Vjk1~zfiB+&gGpc*nA z#Dt8aom;K^wp#!}tx)kl1()A_Vm*}RA1YY%xI7&O$Gg>N7(|b6ctQMH56$-K<;UB~ z>q4aYC^XCxVbk#e_^t-P8(GW1+q|}KSNRpygZ!%)_E$v43|+%_hc+<c(w}Mg4KvGO z;A1!9W#StU<EG*eW5`;kpe{mmA$KNRY%R{f9;CiD-K<oqqKlv!B0XRV=H^Tv;13I0 zd<Vvk;U+&WG0c3_slLPx<T~yA!`RGyZwV6jilU^z3ryE0s)OjA+Fto?r!}`RtRJHO zt?VC$>z`&f&~!Yj1#dA99yuS%M46hf<i6p>>BiR%TSh4~)C5#JBN(}fnca>JP>}@f z^WX7jh3H54sn)C7aQ(x^u~WT9lz@8^Viex(@oI^|5jv#}dN8-AG)-;vsPfSZ=0gDP zdB#kqjkRaXi?^he2>-kkpwKXg?rJNw#Wfe9q?KgA0NJtCI)mqUHW|x>`1Bct_Zc@t z9WV1yFR=0M#NMHgW^>*hD}{gaL-;MTWlE|pxum0piQ=>U;d)mzy>%!@m06?2X668Z zH_<c8nB6D|4KVmChQV?t6=ty`w=Hvva8XkiEVwki1q2rry$r^9{b3kKnPaGP4t)M@ z0E01?gAm2AW+kiVJR-@<{8T&l3sA%4(@aEOh4-?W`fhB)FV{7P$5aHA6oWI1dM!-Z zCe6P*M=S|d!T_!Pzv;)03kD(So&3u%HlH}u?zn1v6RK+FJeBtbXZydRtbaBBz(CrM z1-d<txnDb5&Z5xE-@)Xe*?<_l3SuT?i&1Bt-oL5W)4f6p>W6jiT;R!q<AHD%?l%74 z!dWQB$p6e`VI&h*tLEf_`)#N!GwLsPoZWul|NNKg1pQ&l4J{wyzK4M$Zt3%AB)Z|x zQ~i{`5FxnVjai)c#ZjP>jMl^dMV4Gz3$x5Qux&Y{lP2d?L)P&)vTb1S(IpVB5Qi2? z<O%o_z{yQzdx`NHu({)1@ll)Rf5xHRnTk@4y&N5W>|u-Qukk;hufIvItMAc63eSZL zkVy}>50(5B^565PoDza>!DZl&Oh+}vP)QH?{CmnOgP9<$@`~}O?OO-F@c(SsxzG(g zk8)ZEO0#*qN_h_0lX&5==R|Q)s~rd&{4M=K?30Ts$Ay6FBrS<jrzQd4`;wh;kp*WF z@0+-V1dNGu$+)(WKTPY{Bqmi{tM2S5o%sKN@0NV`)HAg(<>sTOzVu3ro;%2ksfu;= zHW(D>i~TLope?-3LyG45gbYC^@!gfjB<J@+@gHL9V2C{w*M)jGP7|pso24x&(&l1U zD%RBnns?Wj`QgILtwMZJBm4IP{nzQij^)f2(47d`i#T^^J7qTIuD3+5uVk$V<6`jq zSifgJr7@LUCIbQY-hT%5M>PVJFImzzTgXiX9kZTLM=nR;WA-SjEHVV}*eJ?`2l-3Q z9P*N^@SHH=xMFH6xcu|KGx+ClM0wo6J>Vgm(oJ;!M1H>2#3IC1)b8{N^tPii-{)RW zI$YMbba-T-xap1W$hT2mhX22NA_+)qoKd5I1qXH=#N-uLIQCjRK9+szas&&j0#bla zV#Mj{2CE|mpZangRWEnO+dW)7Oo@KRr(g|(&)>c8e|PXoXh&^o5u)Z$J;f7N#|&|0 zN3*G$Q<$UgB|Un1Yac%wI2;kWmZ*xVEB$-hp|6%_nQ}LJi8WU~mmgY3zO5jid<E^u zr<64}v3c35O_CqCW>q3668x=W=Jpf}&h*^`^s>%U@_B}+J;Zhh>xTwe?b{~jl1cJ% zo={&3$%VzF(MP>qY5C4__M$!iTod`k{2Ry5R)e2y+3YDSy}td0=DVd|7v;QuP;k`F z>+cOWeV*7oPZqbiW)x|(C`QtHu{Jl((5yT7pwwlRsQR%8z`e68a)WlD$a+K__8PC2 zfN|_}3ZX5}@;fOp%t~yB4kf(~`=|fAHnjOR!xF1aBN@3{Svx^|bl-vCNfPDW;^Kou z$r?%?R)?-Cd=qCwOCRw_oGO6=wakwVZ1yCFGNwq|cxdeolTeI5P$Ry+QI@AWd3im; z6FY6rKX4th5Stw<(BD`wh{gYv9|TJc<3@m>j3P9h>*Mr^(G>J25XF^6Z%(F3m>_B! zoyl@jAIJjr9_#Rl*EfJ=2`Jdw^3n^-fd*Yg+%3?cdl_4`&8q?%k;o<R$c=ifQ(~TQ z_#M%Pky!4o_pL8cV$d8(pUZ#XEK+EhdF)|1rEf)Glk^J17^gd;uS;fy!Tf7<Sv)cJ zWVXEnHZLY(&S&9%9#UP&++@m2-M$9%IaV!JeCLvVW6C*iI^BYrS3;?sC3~akHELIE zI*qD0i!(c9oyZIAUhiE+4IX@Ot5H(*D_7wB$2g+20`US+*{?abvN$~NmcDA(*Nc^e z4p9LC3x@iPL+g(Zo9sT3d1-X#+3QdRw=&8b#iqEtbm*%27CFsUD5w)plPj@vQmMVp zDhMsm<w?Bf{Xnk8ERmqA+&<{rG>VSSdt<%_n{}LC|KuwCg#!F|YSCZjX8VJOh52vl z%if{daZ$8iPJ$UU2eGNI%9%*2y?iAe7iX4FoJU#~I~N+4BL!0y#8Ab!hU<D`Z;?w* zuliPp%ISk>MxYg_?Xl>kqUNuaB55jeZw2*9rwJS-0MR|5fd%H7Qc5zLn8WoaE*0nS zXV}i*7t&%2<?CN`eB^v-Qk_<c2SO+t>L08HR+;Llm72ZMGRJf_C_bbU==@YhW3M+m z(Tuy{i#&FiGSLH_GeP`rLd8>sPxEoi*iW=2j9%9rYw|KB2}gQ&B2Zfre8|uuP+)#( z8yU+eA@L$mS%$b<Sp-%#yV(cs9{{+*mIJT<%Xo}%CE0M6`ic|i5=Qdr^@#7JwGv-{ z?HQgwh_6MJ9K<VNlhVwbtppt$(C>LaNSt}H@c3~gQ%ISX$!B^8okbnV3-6o5c*Ynm z)IRfJ%mG5!)FZ@IGK3H6Sf9P&8T$A}c1$_P@!R<cY(v&(0uA$?@~6`#O@Nj^a=kcp zPUDc?18EAP<vbONTA)ZNe#oN&OI+3gnQUwoeINOF&YXaLSwfji2z{wyH*DP6W$0)i zFY9gYRfKMKLuh_Sd2s&CK7AkIdg+Qq$Kr#=R5KwbvWM?@6C6Us3fp9CUedJ$R%{`R z)kQoK$Ukn3{gW%e|330iLE&O!Kx>Y=ZW_OfJbKbzyx4q<G7-=t@HIOiEoC++=zxvS za7rUgohwH4u^8y8=GLN<c>vW`rRS|uG-zQsO4}6M#AYH(t<0LzE;x&meQC5uQrUgD z$Jvp+sO0hXYb^lp@y(4K_SyTiyJ-vLS|ZFkU@So|Y(wkwhfX6kRJ3-cj4Soc{f8Fp z;^CP58@p~wpbKlDJ`f<^kG~kahr;DhL0F7Vh{`RgTZU?p&P}og2hIuYLip@j1iSy> zeIdZ*2gHMA_5_EW65tP3UE%DpX;}cxJO^diIcJsom_Yz_?1O_p47FlWB{nXl{k*y~ zpk3$D1W+w@{NAdi`!pPzmi^x?Kk``a42DYdKb<59M)YXMWgi_`5vdAt*S<~F4;+Rp z%e6Dy&Z5`ts?5zYncwNj`>9N7&^B`((WwdIfb)5?zuxlz4|=16A{qZ@0ocWu>(FZ@ zIAhvfmL`dxdgMuQlPDoa+ur35;km6*dKB%j5GIKMN^!QkMynI*5}0G(uQ_BKl7Z$i z%aH<5fx=a*XxqZ)8r!=AV3^m_@_--nA5Y+tC4u_C;w+Ysho!rt6hK^wL0Dz%_U0{# zay6>*n|x#=m<c$xSa~a+;sW`&D+KgBB>Z(0!XzUtzc$Z%11Hof0R46Wj()_!`2ofh zTwy}U^Il|fyOG{y!H~``_}NsDG@xQxw6EvmWzOMX{&Z=)nYcQ{;f*fxLWaDP^pMOK z0R9^6j)Yfe)n3XUtL+0k?y-dNvXe4vF)RLLD^Ct+@O@8**^cGq;{Ms5uCdp?c*nWg zNb!p7w9pnbJdE?@qlGhcnDYp26{Y({caxR_W*|fLKxC*y5oTk(b8yX3V50`;M7vYD z>r<M&(mrHeX47Jk#d{{bEvTNO;ErgxP!zyAIjtmRp;Tz715d~AWtF03d0gNYn;P%u z<C80wox6?^kMRmyj+4$yAu?`uxvs|09JMAvL}iW=p+eOLV?Z$Zg4=G038E|RQveEr ziCjO<O9|FnEX^o|6YWIRS!*=IXFv5w`jCL@PGvblU@?pVx(2WwpGBPXHLlQCZyqkn z72N6&SS=nFiGsAIYDT_qZ0k}?eTXaqkAL?a@+a0$Oe7EK6DOp27HSH_K=At{<zxO^ zg_2B9(W1u%(O>1sR!&&WjhRNUtFZS49P?%i8i)cV$K_#P{l_zU9uN8u$A54?(jyrm zs#3VToE9tDt{t~iqlUptHx^ye=arDRE`i}L@6j$cgoFoI7x=Yfm^#q(rI4jVxGRw{ z*J2?K%#bTpa@SNJ$>@=uR2_)^l+JNA*OyT{J+qXqpv9Yk<AVO!u?X2MgSJ#L00^5s zcLGF+1gIcD@ZRQ{FL5?$uJ1(K#UD=bKH;H_^2iITmuGe7#^2TR&lO+Rxul^&;Zo*# zLUghiER)KZ;ER>;o_$hZq6xqntGFOg->WhwVgCuS3-daOR50vux}%EtgJS(%{HMt( zccZNPEU_CSv6>7xeOg*}st0<rvbIH}K;*=o>)5|Bx$o0nuNLP@x1nU^hHDTWP4A*X zP_rKEitCtjVTRGP;NvF_jeZNia{m;+dcWI)ygSjcv*Q?a7&CrM^30JbtWhU-i7Ri{ zNSXH;`2JHArpdkN;7~akQ*~<y&=E$fl0U!R5dB7Gi13P8t`ky{Ma9k_q$fnJ7(tXF z1Zrjsu<Vo~6A5yH`%5n&2qmGtDUVJNK7Os~t7g7E?k{BvF<i@TzA*Ezw20ktotJD) zUvOsK$i;egdpBahC)NDz+d0tc^nqhdUFBFS4jl+dU^ZBbGZzSJfNMt;|CA0eDZkUk zsV+b3O|yH;;)nq5kWt_wv57!BC1xp(8xFaXl-yG_SDL!R@!^MrGt4M(xvufdwTSc{ z_umqA0q5nMl}rvq^nR2V4iHHP2R$JLCFGYS+ir37#~z|Z|0EE2k53?C$bB*~VHk*6 zo(m;G;+jAFmz+(s7)$rd$T4WRs(<`!`##NM@pe6_L{dB~!<=TL9qu(4D|<<)3Kq39 zdy;|kWI<XarQhFSPBg{bH-FJ69o}}s$rXQG*S{`<o48TpF>;005P?m|6n=Ui#oa_t zCrT+5rKRyKmuc3_=7Y6?P6u6f_*jh#u$>q>RE-qhRb9MWXS%*wLb!*QeX%4Y4@YpP z+W64BXTp-#!}MF={K>$!kH=A<x&!M?Lv3ydX0m4ecqE*8vp-iUW4pEQOUkElIae2f zqQH`$FX8l~1|JpFYmY(?XL}m%!@Jdy-!JPK_{PN`_f`Fa>6=+w8jaUJDO|rl)OWZ- z3C6q0`0Q-Fy1&PZCO-h9(@Evj%X{y{BR6C@2)`7L6epQiuQW$JWP0Ep2m6M2`=)33 zf=@++_!hA<?56LfK#wX>C?n>vA>Kyd(&Z5;)<R#oYo9#Tjai6((s~A=Ql#73QLxn$ zyd0O*%SsKFvt6*GP7RjfxJ2grbZn$QZsl(YI$dszh#jF)q*-Dv`RtV)ioeRGR9lFV zitBrYy*6XW@{VH)$!BN%(@k9_?Tk9?|4z@GA?>Vk?M|ad7WpglpTg@ak8^{@XLSQ- zX##5M10;_Uk5)MD&*zuGD2ROe_WkKQZK7ksSp0^~e@^CdT^&C;J{X2~flzH)UFDD{ zduc`NmbNt0)$=(lnH`NpA{R&ah8JzQA~!?SFN)a~c6^%9TAnb$D+-CR_f=U6{){t( zd1x-aAnRo9rt~A?o>OdG|Dp1^g00&k-N9$GZ2O;CMs-&8tX9guZZVcCG$FVGL>WD| zgWs$?|7Q8^qhvhWuEKf{oTYEz*rSSj&PTs*in+seT^E8S89`bAEGT86*($3H-#PW1 z>LLg7QrX#f@gAkrv-n;Ufi@g_FtpcX$>S~-rEtI88>#BXSKRlG2hQ}~)t!qyTxDs; zm!`B2-ukt#eLxpC(UYo&zVlJ#OTaooN*!{#&eOU)B32|qxIcYhgAIE<Qeyt?&?!E! z`z-fkdl*W9CqHp`(c{J2>=j^%X?T)O|4CEb%rB<Y{m!oQBmWY*w@g@D8LL^ghAMpn zFwDI+QN+eUpn-z^k&Or6gDZg+RzK|2U1!X*?>_b?@90&*ZMYf%$@-#mXQ$k+d3I}- z3SJ+TOVVB2Y&7ROap^}nYQU+sYf`7HfV>mUt^JK1l{w1Le)7D^v)j}SXoxEnB|&sz z<mj)g40$b{%3Ix^)n&p)iF2(SY)QX-X4#px>_km6agBm8GfByMg?w8?KnB(y9Q*Yg z$||-*xl%7q^e6ScXi+G+Rw{?VyaGkIGG2%JYLcIhAHMm9K`W2%bM7!?ea!R8t9u-S zn|7l=o#AOE^B(j?&ka8td$?7FiF<EMF4<6@Rl8oia6&I!poy5<1$?cHvMf6XM@xag z+`|un1_`W6PQ;_`1k9xXbHZ$H?}(f*OzF+Z&$q`{kq_jV@38}o--AUd_rv?hW8Ntq zI~|jbu`%z1E%R)-#|`2;yg_MxsQmL)XY<anpw@%-BEOc%+c5Uvop$qgAB&8~!3_{P zkSQ$aZa%p~He$@8#+uAq&OOxOP7V#S#9CL(nB!1<9U=+OBy)o?uX0SS!?#M3_cb|c z>#Yj5g3Gy!UUGXiNXO|iT_zz64f}B8K+rLKVl?fu&n{T%AI@B;rKOc<&-@aEa)8BJ z|9p3HwWtB{ou!=oEvgu1=sej1C>c+jY+4G~6?{z5G}syRl>?rO+It7mn}}Cp4WUEd zMrf+E^_#}#S!T0cE#*08=!v86$&7W9J%YBX!@NK2hm&!eT-<YSa7pL<qyZnlU7Mx* z<rNbi%?f5mi~nZlcx>9!RTYs#e-Dx@x=Z{=H>*RdbL|#};saQFI=1jtDu@cU7<a>! z&O!uW%Z&DSs1$_w58YV&-kBocI{z~N>UH%Omjo5<3c4A0Xb0?WGcpqJxY(74$CkWO zuzA1+de)W0R3Btnaf+r@2LQ#!OCb8GS^3q#Jzg&vFM(a<i}ungUD;{#Lm!`gyxa07 zT=A>(C-1e`k0~RHGb}pUY-<yc=;MQ#sd(qv1rt{!s-+yE|555<e3NQaMx%~mL_%}$ z<h^o1MMBcO+(FC1P@n4rJw9)C)g448^gH|shq85zDXqNha4pP84(2whwrF|em}2%E zMStoBhNL{RSMs2rZ6@nZ+9oO3+WgPc0=qI@7OPTP!Dat49`LZSY`s>5q-6tyc+DW# z_0cSTY|rKeGv^u1cCne@RY5RDazKZ~%uy-69OG*|@SlgWqkywT%AH7qAx5{@&AFb# zjEa(d@$0E07ONzR$m5`?_`>!P$)#g0bd@=KWGdcociAYkO~`ZUnrvsssukQtec;g0 zLy`p@g^)(Npijsn4o8Z{f#<XkE`ylMz1rU&*=VrY2<C>Qhs1u|=p81D=dZA$8%)>v zsuog_Az}tIk1QXJ<Rqk!dXtz;4Jb9F9<{!di-X_~)tBtXM)ZlStie#PK<x)x`mGyY zE(tqNobzEnd_AA`?OX6PG4kTR(#FnF-)c&?$-m3mR{BwPTwBvx*-$5{qVq+;XMTsI z_bN}dJN`LJTwHXnI`;72ebb~a4(+w9CoE(1ZE1O%c}PdVb<g0tsI;|3I&hUpRH(q$ zdm!9BLR|r*`QvJ!DALI+((W-LiX}^c=jYHXir4<06Dg7rg|8u%AMLm=3qEwX0d%d; zH6ZiADWIfy^+NOms>m9eGIMoAvtzdTgW^p5(^<RMhCT%OHdRcoZqZ-!G_IQ!ac8{$ zMW$EKQt1a<FQ>%k&@kx5B}kIyXIx7C(rpEn3(3vaJ<}t~9FG9<Qt(D05b#%+NHDy? z8hsNWaP4=#w=cdjz5!MJ1_>Jx?RlhmTB!zm<;*(~$e5;U`4srFB?`D*>BYrHb+Um< zb^V(HT0ZR>QzX4{^pI%;k}<I>&>WeUs|Rf!xc$wz8{`%B^}McQ&8{az1<*CJsw?PH z<ck+IOz8dh7CsE8mwXjc*iLH8a}ODcrSvALd|y>fcy+#~or1b=TOo~YM9m=L+M$Jz z{`H4RZ?DAzUBH*gPC7<zC(d{FLuDnP5j(Kjr>ilEpWU!#^rC-#zvS8X3#ocH<h{u6 zjHK4fvhZk{HO4afGWjT{ku<6BVF#>V9E<mx+2)h34++i8<#>8!94f1V2R8zoIgBa9 z0anEz>s?fVvRqyZz^2BzLa!WbwRTXh(>JahU;j_<psgZM6VwL%zxoCG^VHmNt$7~0 z%Zh3wL`LovO2KZ{<+@?;5mhm|pQ|Dq;TZNfeUqfILFgR+?o@8>Ysny=7*$|_x6<?4 z+bRp$3wPylJwGfTL}SJV#?W<4^LU-mEg@Ttc6G4byz26B8ElriUz3d*5UzG)79;PY zxMTsGhh~^Jp7jAC^%LFvv8T7=Vn#IGN6VtU51bPh$FzO!f5Sww9h5FzY=^N$t^u!0 zL6?|Eza%STE18&ctqUVBjn$y=?=Gf!AG3auoSKVQ#t0MG(tJ!FHU+`Y!!zJQeik-6 z2bn{N_&&t&ZCGc{k$FkEbZ;R>D;J#?X71Y-AEql1+)Jk^Dklm0g`hg;?on^9R7^O> zHZ3}X9AL<hBiZ;s&(3p-zJh)kM#`GunQOihEz2ryt1ZjOCDIbgle1#Nv<y1@;dASp z7Rb=4?VX1bP(cQ+>#5ru#gd~<m?Isqi;Cv0u1CBZOjF;YAdMNTt4dS<9|}}@X6qBv znb53=mcJ-a%axW-o*f?;M15W-K{Z)An;dW_V+Zz@6=5tyJ`JS9mJ*B3=QoU9V9FJ7 z%Lgy=(ung}<M(8?e4u*awc3-pw@>dCO%l|BR`Kq&Lpdnj1$86-Ni^<GyVifjWGY*> z*Sd{HFEGc|rd{i&NZ$>oUV5J>tumo2uZkXqW(URX0D=?)mkl88u|jgUGtv!a3POEF zIb<$B0&1^SKlz}(y+zHh0s&|0iZX$s#Aj^D2tnSF>l7nYca@$fqtniJ|Ga+6Ca@cu ztT$*vNbW#l%UZoW3BM07fZIhy!}MUs)x1SCMc5k*rqxYeblf%-C+sIXF@A2(2SyvP zs4dr=WqU2ToMHXtlCN!fJ_*@lUg4xW>f~)ck`$_1C*j)jfr^Npok1Sx!lmtOgT+0x z2IUjU_8xl{{Y~j*$U3(86+5OauNEc$7hHY}HyHC8#mU$4^akthxd^-*v|!s{i^3zh zTLIJVIUW^T5A-Xw_-P<NJx7tj_l!qQ5i^W#HeESf{tIH`joQ%pwQ+s>A#Mevitj%Y zdx1_20jI(Bdwz6b@{Fgo6hk04H1xbvE(9_i{=OFF8WuBGQd-jbR)RG^(jd;5iC5;i zl#PPQqH~56iG`OD@QNSWUL#v=z?wKuPw3q>iOlL?A3uO!nU~ZEkW5NEO2+Xv&Q%M@ z_s{hgf&2cpW`FTs>9>C=@a?e5SL4o$pAF;Lzg33Q`EPh?ffOT-IF~?1Gesl1`NW0{ zdvAlJXY>(jcQ3@S$9t%lG8;f4f`{SNE+TnZOZqwW;R?<6X#Oo&;`7c|7wmEE0lM7_ z!^Xzvw5tKK_IR|n=NSpig3919;RP1WCXnOWntkcQt8jw&)21>^y|FMZb9o5era}au zI4;yh;d$l6<Dz8k!~>%1=O&1`F;b&R!=vjeg^Dy=0tFSkPcR&*Hdv$x=H@bb>hygC z<0ajaj?%yAFdDjtP1Nf6hs1aepv?|Zt9^hCy#)S7KUBkJi_`pO{Ep@h0+SG;v*)Hv zIUb4s)!;JZgHGN{HQjffV#uh+n_%vYV!>-0UBxpbs3WN3*|{~8U7(TDBCS`j!r&HF z{brjaqi0q9V%kI4NeD$IvO-+VF+A_buBzi;RmRuT-Yn?O{&^#4N7)h-szKh@D@aqd z`)wn4hOhdA$-htyRG(pu#PsKqxiM`=R3l?tzE*VyVZ<wGijh>^Em?>y#c9OOSZSFn zdEgO6UOq%5KWwSC==`c$%~K42&*okAZ{yr0vfm4kQ03J_uetc78A7qzj8|FbCFY8% zV|EmpxJKtaSwF?@8v@`8+D9-7=&woV+?rsPVa`<Q^J>WJ90cs#(#8TWyD51fS|9Jh zBrSX^m1Mt)n^-8ebAh+#a^5KL-#$-vXkJpgvLySmU*$iGAy?{xIP`w)gXv>h22DVj z=XRWWcjM!bGu~^+xK_onh!eCke)OSsPPIPI8JeP`NDy`<o8xhA42$nS!W1L=;5NnH zM5ttJZ}-gR)$>;147F*kKfuqf{(<LMbFg|Jb_118h)v;{77QHnoi#auEpPz(?gGAk zC=4xsu@h_HH5=pwFJRYl#I2P%JT$n8D6z`!5$6cp><R;%U-Ky|z2Z8V$+TTOS*4Mq zQ|yKCIsGF==J590`JtBnjhH=30iLuQW_onCA<#S)e<gnqXSBF|w`KwD+zrwVd=8%L zERXvABx0~=AteLs(JJW?JJC*=SN^jYC_<717!FDk1>I!3%AGA1sY|s*&!3v~p`e_Z z8OkBWt2wR5yjKz->lX~Uc<$S6k-|etMBQc{v`&h(iL-Oi=|pTC6fCjh9j>ah*R#{? z#p^|X%<p&78t-Kw6PnlYJ8!O1zHTZ7J8!e&p>-JADNsa|-qyYa|1mE)j=LveqT+CR z^}TEP<;u~&adCmRy(DaVbZ84dpVv+WNU_J#E4SJe4(1Dd_4Ot=C^Z&I7kI2wGgReP zPE&Ae)1!Pa=lt6Ose-FtA4E^f2Pyi$DHj=zT_odt2Gv$qNQO*LY>h$ve`5TM+i5Ot zz>xfuP(ApI&&IEeHIJ`G!rdgcB5%cYmCg$*&~F+}ogWs53+JNVi+>Hx`w-V*cp;c> z>uR=5ee$a0>(FR98bPHy_I;45b!_MVoVB<t-^N(=RgHgg%ZLHc8*s#1R=NckT)A<D zOA-bbd<LeqzKgP^r)2_fvpi)$t1f0MVMzlNl4S`N%PhASt8uA2OzJVx2E|T8#lzJy z%TsE=I|xa&(Ykapf$ePtu&X2V!dzD|CA73ZhhKG6*JMxg$2ND_+kuNuCD(Okp|BX> z({U;iBD}3KKOCqU3bV^Vjb%iY%B-}X&(ChKLi4kMH;+Ct57|euN2V?fg58$};>iMU zRe(T*tCFzc9VER%)OeXhrL}`Y|75JzCdFC}VXDq-J%!zFg_Xu3Lp$uJ-bo8kia=J) zbUr!>yNRb%{oKGWK0Sr^<;~bI=qqDfW4tw-7VO+AMzXUD@isb@0r+jbvF+*+GkmF` z%;2wVy~U$ewix4vU#kUl$R-WBq1UMEEJ5HYm(mXCR`+_uSr7&sjv=)tTljXd6@p(w z+P3$TW_z{*Ou8d0y+=`8d1qdZVLs*HJMMPp0R3P;yI{cUrXgVtc_IIu)1YHE4&B<6 zU8C#aJvL;~uh7`9j_w+Lz;7DbrD{e+7nE{hc=KBz7Lc8@RtcR5G3_6Qs$R`|t5nb! zS;xQo1SE2=TP9>EVAyYCAm;&DtgzhxmBgi<0tdj1pV}cNrOfI?zgyZ8?nD{AjeZA4 z2339JSd~B(d8e;S1jvLA7Fie(CM_NW#x9w$4divFK$800=X<UIykLEf$IKSuT0OEl zJ`abHz`JWlKJMmHvR>eF@#$;5N`;CLlk!(|Vy}6x<#pfZ1qMhSO`xA=w7%1`I{4M8 z5E{N3ClJsb0|{!nG)8_qo)xMpY`=Fm9VuJtnq-&{UF+L{>0r6yFk**4mH_hB71u3| zBRvP)uxpDL&zfo$2($<zB@$14z<W1CIr~PD_<dU*|8Ou<Hezywv{~6dCvtF~g9ViU zBTHE1@#LoA5*gspg-Sskyo!@-GQ?#FC`5QA`hefS&w?!-P=5ZG%XI}qRT(EA={}KT zcuBEP5i!6^o-2|`asFbF^GYB+wUsmW3mgf*IVC#9JY{WaIV^Q{NL*`0`;hUTP-OQb z1{iJ>K`cu$3o}y|4lENofa@CPSe)Q${rxFJeraz4k3x`|Q#G_m@?6tX+VLA~x)doP z=b8(XH@B_cLMZM;3|t=uCU^nBIAA=bkR&*^^Ti{sA|{`T1#DD1)EzmM#9-n&+hdj_ zs(3jR<$3)U-q$e>fCRV&k(X*Z?`<JY698^U499rG=zc$<WycA|55+^V)Vr!vI`Bof ztc$RAyN}N0g?Rsqv0;<-x<mr=(|iXCn5Wx;ryYGeQqFvPd^?ApMc*Qg@yC|%k#pvt zY=(&jZJtiYpx4r~l=0la2O2@HJQpso&GrbiYG{=1?kXCdgb6kmEBiY}0vRWDRENDw z(3kICH(*SfHYLrMikg9z^E#+E;GzsT82WFX^`Um7(w|Ai0v7L?bvIQIDA5oI%LhDJ ze^P*vicN`SImiw*W)%J>flUco2$Xc$7A$$Qfea%9Bc^Y<?J=z*&Bi+qMi3L?<*nKd zoQ3qKt&*ez2O#Hh?Z;MCjdId=1+zQBbT4I9_{|I+R8p?8`8+Ofs2o`kIJm`;J!7Ti zN_X$e^=TYH9B?6-_6NoZJcAIdwyb2piA}tbKbB9zE|qyqQ*wComw^4v!tq}g;EI}b zi5L@CMOG<2)IL^{I?_9G7HPEz?Z!PIu2mqDe1DjMgu9#K>+#px7Fn=QElfR8jbOPJ za~j$UIfBl46~%tNc@yw6C`xbfg$EDv^03Q&yRGU<H>WFv4UOOj@`~~J#IZL-DRo8G zRiiwp952!w$8A>KGHBo;IOc&HcgU{aIr%39F`aD6D4F-U89QTF_+PK}%-JrF+ds1; z`#}C9&R66?;3u2Z@r(IC>t2Z`t@9r=nb+l+)Zby8)%kdj0aF-BB79?pE<PInk}=7# z=H@sG{Tpw(MW&#FuV`IUZ0jMQD|?h6e!SMXblB6d=&^<HRS%vOow6hw$(f<Sn!qvS z9JYQ_ax&X=u$2g3zMdk9CD>LQZH}F;**4nOf@vdPGnu<#-^dkh8K+4sG%Ar0gij?& ze>!Rx_TPng(4GNOEzwe4G&U+(k-l@T@&9DU-n#;J@k_X2JBiU;kA%6_mL8lP{sTT7 z8!xN)_PH~g*eWwi9nt=?C%c{Jm<Ysixl0luylgYCnX{Z9?6?m_B$6R;X9!$g9*@#( z5SHj4dFt^&bSNFDOl(e!fEF=*cC{UfAdUV!_+4`cv^H{X#as4^JFs!PiC+8Hkoa}O z-vG7>aY+ZJQFZCHL%Ig+j0amTiWeF(LznJn6m5{g4d6a-#t(5S{vrN7`9R|Q#6o;n z=>yR>T6M>n+b``{02F}eed9FUHPY>u@HutCS#c5j$YA<OV(6uiK8L8~jgzXJ?q4C( z)zj<ajC^J>IJT<I&C3r4lBBS^kM0QRIgc0mV-MO97~+T*NXLjN(Mwz$q1|WVxagA^ zQ!PoM%e#;U0RQhyk#)~P5&SPLeP-CgCDk|~azINbe}Uuzwk&Q)^GQXx^hfOS?(y~q zn?nAGjCXBra}Ta@bvE7rNS)Vg&Wi}AFAcdnzvIi|-|_V?^Y#g~9GX{AGM#%$G9g`b zLfzChSojJGi2eW`d~8Uh%NLfp*M2riDM3BvN3^$LfZ}P>@%9^5_qhu9W-onYZQM{b z>%o@m;HTn~-I_dy;gB19@fSz6DDN~9)Dan8A_-WD{_%#clP!_u6}h3@TAPzT+L{n` z44n2I{@@HZ2cW4K6U;o*2akz*O@gh&nVGjLqO4W%86z~k{qj1EbmEwxge&YlY}<pp z(A}0TyXq&U0Y8$l#95c$?Wj|*wZr6;NawB8TUl)T*>0Hd7J%sZ`jjyTr&FXdFpJB$ z!T2N#0NE|p&I~nPy!f+lPKk+tMo|~z*FZ8-ifYzLtUj8u@z^UObbQPDdRX4t^KD+6 zk&5x=FvJAY`vN`7vh7JQ{kIqsU-h8l(HqplCN0kSE2~%pRzWR0+(6o&C#0se?ZLXm z)*5SAL&=(tUG@VBru_`@7aJQ`GN1@FuRsw06lQV?>;s4cbOZ4ZX#3UbP3I5q$m>fU zOEkY|D*?g2Gy%*~sebPAE?#PsBC*`uSE*?6opnkMmg6_%-$(R^m|5hLUg1y1mN~z= z6q$NC<)=36*u%qAoi8=WuRmkcdByn<tm0e+;^Xi<45kz}b}L)%nd5Bw1uPHUSz37T zt-?C73GE>O{LdKv9sQpz<vT06!5=%GKdBadTS0ldHub)=xgMCVk{AI=6HX=a$1&us z`w$OBQ^|TZPYHZ?wH!(qYlzdJ;S-ze?jIK%<LT$TIl_Nj+OYJ{G4Xi+efG`T)8W;1 zva-ob_jX_Tt6UGaq|tli<I0zst>_Ufsm?R|W=dDhrgiM*Oz}{RR2eo?d+DX+`+C(_ zL7n}0J#h$5d#e}yHx4QckJ-(cYY2Y9iGt@)vB)p|;)sdYH_?zlHLb~s(QHSIRW!yK zfWIxX86Mkx2b~c=syR|8Iw~>OA3Hq_5`lS6kkyP>^YYa$xDvdObw@&NNnV^~+A<oa z$xR#L)8pWaIB^cMe89)Jv)b9&Pq5C%wCoour^oOJ56P;xcUaw`*N-9c%*yGLlg@Z= zK5uL>3|sZ)-l$+gkk^RVwX?Gm8(q;tD|1xkJ?!*F=GkR;ymvl*(T|Ygx0WbKR1D`u z6_zkeIGFE~qBuiGG#qxgs~N`X;bzo)io|7cG1ranHEa-%U8Kgj5YO2WIqx>)mf$5W zVat@uRFuXIL(*)78P4Qo2ZdTY7F*NR@XRqkC&7kX-&<t*+&s6+5Py1j)}SpOfyY;+ zU^^_gbZ)^D6uh^DPw~iq7;c;yWGGkd7*pIST@H4qNSu{9AyHiwABGJK$AUdey#EAU zXzrTHa-K!!eawYtTRVfj)xWnGUr~y<#X6f6Lg}&!QAG*&?M94|>=16UN$vU1T<}i# zSNJtJXF<?us32_=j*i6dtk^u1hfy^S6zBw9gQJyyK?T72UdTQ5FYio@T4WXKYKv%# zax@her#<<s-a9`eqN(_l$awlKWlz!hA{yLglRQ&0_o;aMJNcL_-syq>V6oGX@ozL5 zzZMKz|3latYPsoiW9T2O`Fw~lE_vW;J{?36rC9%}x%yY_U9kt<J^&hv@&8ETTREps zmU`qrp+o}#hAfsKByo3I0nBLlr>+w5Pss*Of!FI;Eu~k`U}RF#*rc<HH68og`O+6% zFq?V~hEwy0Xov%sT7wrx0+I5WuX&D^f4v`xe`!ouz5f?bg=B_P8ZnC*VUG|A6C{w{ zgwCEg?}+dhtI<vlieV(+8Ip+O7_yPxJY9MBtk72_aKx$^yX|y$Q*X6j&!2@%(ef1h ze@f-rJpWr#A(h4a(+U9J3xxs*ISw9XF18t)Wc_(}Y*6DU@}Ft9<T8y5-Sv4Rql&<t zQlCnKmkj#&a`^Z%Y***i^i+}iTp!iHyrAQEF(wSjLL7}~;XB~KI2(%DFR#vfAux98 zx3ZnjRb~1u0ebwas@%VDP}03`72ttzP+`U+*6e~M`316K>^%q6E&8InLm2UZ*+}Wg zS_A=Hss?U`MhbT-Va9z~L)cDw4-deg_z1pVyTQER9MH!eoj>O(d3pK06c=VZHg6)L zrPFDmeAAfdEM3S$UydmK%j``A@rN7u`4&A4=zB7c1u9uXpb>DLc*~C@z3Y61GVX3{ zo6t?ns(VgTJl7dN^Trn^tvEhgia%7E3tF|%S}o~_OAEZ8jFEgrq||Mq0sasUYR2l` zGlEll@Yg%-up^8lEU~usYdY=@ffijAKhqmi$u?3ky;(U9wdW<XvX-|DvO`L=KHs+) z*Prw{UzAnyr55*MvAg|eg87!_jtSvg;i{)gdw?1ph@oIdRp?XsFN#<lIkXCEgn#D4 zVJG&wJw__NU`_#faZMghgLKp+W}jdjPa&R?T|M(xY;QfIpQCQp5?hEl;Mnx9;;}rc zc>Ga?nB<VvaO0*AnJtgdlelBY53@%fCWNmJGoKzKFM|JrB|+U+rUmA)dTHH^WVc~N z-rR$%EmwK-+3sys_kCEdh|aS{K1=WN&7My4%kpo$DGps@F3)s}f3!ydbRO<b+3fB@ za3A4z$7>B;VaJ4JEj!<S0K+lB*6AcfoOJ!J-$pwBjzfRJZWx(E%(DJNL<{2b9gYd6 zCs8U}79-Qem|*`<=x{@i;Y6l+3*q>*R-wg9#PJ57#u6)4UK{_dU?W3zt@!#B5{?PW zhKV;Lk^)5dzE{t8JN&nL{D1uV<ON~1RN1|#0q7*gLi}>Xj9-X<tAG24I3rfcl*N-P zSlnzD?|Nbe>-sY~iq(9OrqUl!T%-%S?7ELuD_vNl7~Z=~VpbWI{6Nfdw<t`G8$3^G z--NrRx9u9iUtM5}sh3Prg4JF;vZdS>QC_-(=sztbe*>lD?@RJ15)Jx;_&-9uk|DIT zSroPdiYeh2n4$Y)+qCm7JbIJ0HZp21JPK$yD&CS1U(jeg_K?%tJKB2FTlUQudo3b} zPWD2?vk$fH{fCn{lW`;7DNFi8R>yaNtTFM5<+ZB}yQAMG5cnL2=|5Jd2m=2fV_zK? z<<_-rpr|M)V9-hm2na|FH3lKAq|youg7ioWqZo*EH-mH|4ALnb!_Y9&5<?6*)DXjW zGvGPTIq&m(-;Y1fL3Z40@4eP_t#vK+shvF9;=-7ta*HchKtzb(7-R?9WxLFSRRb+I z$x}pS+4oIbmO>~ethrG%5|^BTD!IU$PTADD1d>SBBUg`5COyWXc!I7-oz+xddqG0> zC$25!a-ql!*|bIW#XE63wx_40c_Xg2g(R;ySi&V!P?A4(^w`}u1=r<mFyrw{=6`#9 zvH#ObojFgs8@|+vvizdqT=M9Glu`us)?4|=E7`Cr%55Io!ncdsQ_r;f^<lr$0a$qx zfR)c3!^(q9gVGiO!#2DbU4~jL;P6CLlA24>W3*rAl6?ssn~KO^es>4)+MU0A8t6)z z`%JXjk>e3O`ycgq1+NYf<m&)}OzZLF)Km_ex=f%j{6q!!#Qf3&X2~-^vsNcLJTA4S zv<Ag0CPgtw`HV%o(ud*Q&^wWLg6%e{J!ZQJDBqWW?#56{G_KU%Q0Wh<eQc!MwaYIL z8;Aoa#&n6wA*}t@_Rk{&D5`~DZPT5Sw6HNM)KKxDaApvFs<o1NYhJjfuSRgqxk~Uo zSu*qbhZ;B=Y>B%;jGgp{K!r6RxfVgPac{h-KzJ}*ic*T{yxxV_OZ3cUIRmmPb8<Cu zHB8BS&AtiBr#GKmc$GW{ebtHKm;s0|=9A@4^+3kUKc{$92KeewZ7l+nHD_-I6uyNN z-QxS>i-?~dP*8j}^p<2LF}q`=WH5h=e63ynm*R(%d+UI|wia2PX4<zpK`F$<)0RdN z{A!0GXJ0{VS=-Vm6S&pbej%S)J#w-gjx-Fqz^co>d5AER?I@{qafDn-p4z|_tPPu# z8(B|f?f$86h$X(uMpL>m@cVon$@_(+VwV0x;UE4KCZ4Q$Vt%@PIf|s6BA)TtN2kG{ zZmmv(dA4cM&+^lLT?MI5U#O#>DLx!0N}owwy4$_iu|p1BxYa~!nbF>mP{JP&{A-{M zy%f?S>N5NSac4ysaL)YRmy-YCK96Sb?01ak6iT6x9+~th?!=KZ0`xtgjZwUEu^Om4 ze11thQR+jIE8Qjfn_1;~q>LvzP8QiqvK~KdBt&-;=)`H|`W+BZ3ra6VD9P1gE|>lB z;=hN!ERp$Yd|0<2l7|{kAKlyC=2|J}6{Mla{{1JN{kUuas7=>-86o5ZK`IQ=TOL}t z=Ak2I=lfKRCh5=-b4VL)noxU_;_P?jc>En=Wx-XTQECJ48!dyUcXYnr%;l2PI=Zkq z{@hs1_CJYU)a?}^A1!zPHEmfhpZMp1BHPP9Arf;U?-5Q7{7U*&DZ0_8Z}7*i>S5{X z(U1OT;#Yh2n~tSPZRWU7CUL0a_N2grRd$g`o!2&ta4GK)yIaoZUHcJpLB{N;JoHZ- z|0TWch-d%`!8uLivUq&uW0mtTN8ZxEe+g*IeiiT>5{40d*wP~#IVv9ow&8f<fM6-l z8KOD=d%k~H?fv`T{2d|xIV}KbN$eW__kH^Bsr;4FDR5Mc2kcC*=|8E(V*zepZu0_v zJr#$nTLMG+VASi4KITVO=FRzgZQZ{Djr-_j>pIF-b<|_^qovFXOUlzG+}DptlH67D ze~)o|&*=d9czStJWY>6>5VloB9ZHX?0m~P;DI;bw-jm&Oo>q1smzV<h;1>b=JJo#} zL6QsIX5&`E-6}IE&fVm{vi-iKGZJSA^zY^hS_erP`p=ns$v}L+D}RVGf2;(W3M=Z} z)Wgm4*opUUC8ha*)-VvB70VnCH{_kdK8g6VuQ|7NHrW7`>f?G*U_VB@iDvR@CM&A? zJD25>QuJieCvPZ5ZT9E+V}VPVmaSiuI86AwVQS0AjRq89;-_Zo1ZB@miFK6pHE=Q4 z6>Bz`Yrldcy+m%{Foy;5#|H0uWHf+i;Yyt;aA7LNWJO5t2EC~jpa+t~MnVN{!Gs-D z68Jo<{S|YJ5&hW!Z?XM+OxOO}eA@3Em!6KnjR{w;@bSx5t>62yl9yTccNX6=%XwGs z=JeHlL5BCNo2%GmH&dJfU{Ilm1(AXI1fV*onn+dsZ3;erII`D1En$;M5VVf%nZh`i zm&F$jB_xy+v-muOc^0e&=7oXcf9}t%sQFP!SvtntQ9Lw7EV(ZP1vDN;em*Uuq2|k> z4DYArxH`nq#Nb`Y5L9X<7VganBY;-e{#x|B#gY5GW)M;@N4CRfA&)3h5+eoLA<vW{ z*Mos}!*BTG_%?%Jsc*Cm72-Hy*11=ovIF$VXSg`b|L!!3&{4-dH&!CdBVnVo?+01D z?8=@ER?OEN3Qi3$_@2VHgdq<qER`7wUaR;u$!p{zP#p6^GG_Fuz%&Xdo*7%%4&D$s z_C^1k+7>tEOrT3@Kb8+BJcVkwc3(G!>srKpfGncwr(@w&mvP9Mo0`;8V>-wAa~_cQ z2JwpK7y`nM<g|{qVc>;zva4=w%s+&>x4e~dno$folO1Am`+kG_^_$*U;UX!e+rlsp zW%Bi>n7n@<P43HEsh3&16mo~J0yJ71SI@xMD@CQxhh<DQglxW6%|5+7-}=4MoSn*z z4){L*J?*gqK+7y&ojI5%ZLY`KdV<avXqm7FLf#Wr_IAX%8RIZprrOJI2!~bk$1nm7 z@m@b=XCu~SRLb2u_O6nx6BG}=F$8j46)fl-d!qUK_i%Goi_(jvj8nGuzvE=D14Uhw zsukrks8p%*%YH~WIOIk3@DU@H0KR+i2HPPaHbkzsb{2f%29Z%p_vpo!p1u2IN&I-! zBk+RR1sD}`DSRLQ;TE@@DZo!s&qrSa*U@LO-$_xC(gI4H&f6IN1V}0snaTk$hpxcD zztpiy3Ms#{tlY5mT?l%zZ+Uw7Vg>Ue<G9<JI_1$Rnm>DNP@@`Rinh01pn4}5m=w%R zTz)=#eku-7{Ei=w0xGDKYAx;iEfmOl?s%v;ms@*hR)1?E0FsBBpkSU)yV4rJc|G(O zz;ZjY6!IEuy)c44CJ%V8{-buP=8L7ct+}QV^9tQ~tWjHZjdhKDjc)?OskfxhI{Gg2 z(2!#<#HPm%e5<)uuvb2$OFGB|gw>=H7xgY-|9TuvKK%*djb}X1SbV`^T7yhVp~fY@ zN(B>nOLow%go|{w<^W5IhBgHDvfc5}8oSXLKS4FN-iHWspLbW|^^gV9C_<P%rY+sw zdbPpLR9>fL#rmSsKm3lnP9e{PW2I^`vs^#)qN;LrCXWtW%gTqd#2*RYf8cSxVqn!2 zh?#-%DW%#!>e?0i$MsX?^pY?_ZfqM}fxvM2FQ!vqKp&)v{7#HDyz*V&(@9$L)8Qup z&81VXIr(yK>CQi8co{pDTOEqq`4Kxn1}Ku1WuUU?1{DrjDbCi$_!^6vU*21<ONQ?p zeI_ot<194o>k@X~zZT_!zNB3J)Pn)ECv)bmotFD}#n93RE74uR>#;ev+tt%>&pr4$ zm}8*-Zq6#NJi(V*JHZIZ&uRs_uuD0z29?881I$zB+HyAbO(dJbshb3lm#NeVd(f8S z`^`9d=AJ`nmvd96K`@C;`r76(HsFhScGi`!$0Ogn6_R*qq0N42XsY1g8T0Htt&_Q@ z4DK1$MZAwO`L=O;T&||4RS{~^rr;pjbLkz6Da}d|pchHP8MPLl{e>XQK(4K#dlK<Z z?p<A|ANQ#U_R&1;cSELEj@izzqY^^k-SC!eOO2-0eBe;~lP(TWhp}gM07PCTJ9~h$ zO>ZG6?V0*?&dv_mfYO(QeHMlQ>2{emA7RQ|b{{Cp@squX=}`A*_2F|H{a$HN%k(Vf zjxr0KdRZS@L&3X%lnJ2X-S<r}8TnsQ(q59wSd!3_#&X?y!47~xYWIvO@BYPMHI)4) zho!Lwv}eyR7<G7;?aOd6mNV-UUj$pd`9+e=pTA!_8`@rC(#V~-WnbzaCO-Rv&g8^^ zg2R`lcc)FCzM*Y<%)29bKAa`s36>)z$0=~IA|Un)%;5BNh1Mw*QV;GQ>QymI&*slF zGIQ8xe_Y%cAIVk*viWs#E*FHwF7wok5-G1IrG{H)x3Zp>8j`l0IdVu73yA(8y4k%g z5lG`3qkN^?eaE9H<@dVMYXt*&#Sx7|2!ql~irp~MH$o^y`|+>mM}(K^+Ne_aA>YOK zNdSN{*z?Oi`b9hr20aOG_cLwFs_oWV?p+F>9>YX#@}72++pKo?M+9&55rl?;oc#*v z=ztSU@@EN`<bwx*OtJp`K-NU_^$>?&1FdE2$V`;`ReWiUX>c(g)7EHR%H<|3R>WF# zg$)08o9FwB#;w$Q_rnw5JX@yRZl>}@!QS)A1Cs6T>?B(Yfj_-ih=(E3^{?;}NMy?| zcq`(y?gRG$s;f$0tp6l$@iEU32edd;NoEvMF<b!Pkrj<PC3Vt2FE^N9?JGwtw+n=V zX2L2sF8*rhrX;2Fg=c_HxoQYTFrI_k9tr@1+F?NztY<`o1BbU^Cbzb<f^Srl#fDpB z6kAH+yox1h8rt1A*ssR(o$JtdVqPhIGk9;3M(8GN^K6A@_QGbH5Gt&&Vq0e+C;8ka z{qq;re;BlMGU69G^coKn@RYOpo`M%I>Fo_`RrNKvdIvO0uWGOZNpV+#dzFLE6gnw* zU1{)-D<^zjzCRA~=B~T(R+*-+PVFh$iDV_5y8c{5we<zPJN%ZG1c@hH=6ZbMXdxQ{ zO$?ZVG(N)d!d+=}RX9lwle|)y{RWhg3d>PmX3(Fw+aDMNzL}OycQdK%S|p!{-D5pC z$>{|{Se=L-@2<Dn-qbbxm6~sAXV{!%{9n{;y^l$WyJHy8eJBb?-2M57fBCUMXkEYs zROhea!D06g6@*$&8-~hMh_o_~dR(GUw^kfy9=97GH)`vkltYmek!xLtbDHL=hLNt| z*D(~Iqm!j^A8Pa|-8_JDPBmZ^r<@<jmYX>s=WnUGOuD;_kL=tZd*iiDZhLDbJ-BfB zw%xkRT4C*%>FLoCzE5)GQ0@Mb>g3ua&rh=+x^e<$l{#OXt`(oMQE2yw8t&9I?b=qO zq4=e(@X7GZo>I82A-(qQp_<O&&(rI_4;hTVU3*~LJt)Kd|3T3y$V@whwq8AE=swK1 zYM+L;Yzlcw0h)dBYwD3hQ~94|zEX$)UtR@s!sxwPS-tpz*}E1y6#w4)-nc6LM&p!p zd#Rz;;2CYthr=GbDcLDU)Ez$lBg*EKjpC@3Y<yN^i);<e+Q(Y+V23=ehB}r%PL9K^ ze_?KiMOfqH=H&yhx94{h`TaOpO-2F9c~SifPb_(-X~WO-hq2Yd6@Gl}```rB1f5QC zZkR4ua|x~=khzxt)L?<e<levb1R9<G#PMV)YF-R1*%cUPEIs%7x_F+aY}=VAb_a={ z!ukTZjUOEg&6|pBVjfSfl`Y>&0jn9nJN;|*MuvtDmD~U81_C_vs@ka?sTN_MSHbHJ zZ{90h&uT6h6leV$$7^VKBAcBLzW~oWA$8V2NTMgNc~u!d&7lBrFs<qmx6Cw>v9js8 zD5i@!tbM{uftej?t=@)r&hS3me{Z8GE174D_DeBs*tj7-6T$Nx9=+2lsjmwZvXL4@ zkX~VYnlQVbYriAX$dgZ$&OWr#V<SCQ%jD6yD_FYl6CX~FB{EaMT)ip#I>KGsWU!Yc z*!r&ex0ZXcw>aCJ^x(}hQ4M)myFbka9+5Oi9C4up?|83M&+Un@0r{W76CzWKTCM8! zGblhPHBinZ19!eg#B;TsM2dtln2SCNxbee)oG`sn53%olmKUu!*h0qwO&iakUVq7c z<U#68x$XLXzqjy;ZBaHQ>>=gGvci(S$;wbO?RKdey#81><&SkDsP}oV$-~|IuHf3w z__Xs~8~-zVKqRvUzgAeq3}A^j4$`RkJ2H#!z@-2}u)j5)mF-S%w*Bjj*Q>tN{i5oP z5{kj|U~W9ZknlSo*rns#FO3Y|;JnLnmV^r5>{=<UOcUqDvotk7YU;XiH6>-pmOX}e zwjW7`5oOnc))>56UG^VXy!65dDJO1ce-i!NR=4}>{n#lw$XgqQwo@_9l_eU?vyXo0 zFyk%n4B*d~uKmSnmR%<1MWxI-<>Se+)}}f{T~~`bR-OxQ^Bs!NJ0B8+=VkJg^@v!L zM86e~!N^-hKo^?@GA*T576ymPRXx98xTo+EhfBWEAgK1K&gs<#)#~16L3TCr`uF9_ zdUg6gB4p)Fz0<-@BZGLjr^PN$p*;i6oOi6BD#5vGT5txmIfwR{cyBPVEfBOuzp>NZ zEVhZ3?j#mig|rT$TFab5az5;CxVts69X&2$#7i3JGlbl$07)4i>Z!>C-B=HW_CKbi zg(M3vhfywGds;z&mcai5h*}ZXAs3OJ2W6+wzmdtXq&H7Weu=X$ZKN`&d;d$Z@<Wmr zDc3W@m-z8vQggmb1x^P0tQyq@9!uY?fmtowDz^EaLV5cePjba(-P$A45JK&~&giJ! zQG!{z3h~MfPc#gf`WOYAKsKT%Ca)>e9%ZLT+}A4`H1uK8A$P9B*#boAmjGfeo25ZD z6`&kT!=R=?$B~Q!F{BU%djEuF?sUk{2>?N*LNEu6@eZn}T;{7z1*=RL5tm}sI>ieV zpNY#~)Aty9+!dys3@{g}{gqTlCtrk^$_*H&mbZkVZI@@%XMZ3XzAYcW_ngOqUm>^> zP@SX;li}k$S(zDnZEo(6C&WQ7aen-}4hVEqltjHxOCn!*%agdrK)7%WElH~oF_gom zQXV7>O!p6U+gSAuDx}qyCvBgPwmbYh`b7;0@qz>v<oPj>xGgXCF>KK=Cd0!V$5a2v zaXfWwiUZjQl0#+E);s?ygZa0Fmf7xozv5VlhUN6}3jd(ANtvblV56pasq&e5^`2Mb zCyZ!qC08!nhDmoG&pL(3i38j684zzvXl(KLY1tZisErkTB({bB^dDkd1ur*&jyww{ zuh9oFHM{r8R*0GlG^hdx@mHtU&s3e)Bds`B!Lo>{8KKOf$X<e4Il$ezH_#8~LR$JM zA5@=;O|V>N5|5M+`Fyexr%y&SUFJmWv7L-PS*fq(viM0qbj!$D<%Pl#LmC7|na|%& zTJ`@{$?7uqWLomLsm{MNx=4Yyn<L+B;KzAe_Pf_b`M=m!wrz{ql75frHj{OLs~1X* zk?+JNujAQl)4DmRz$-8kQE7AurEMvt-NK?N=UBd0F3WLl=`_(+xB;P{Gu-i$1sL)} zOUdy+^t&6vcxO&BJ&w6<8Fc}xt3UYSlr4*Gcy<voxtRLx;IYD2%39rK?S(_<x|M46 z>}f!b;3V(qqIOupQ}_4CcMP=8(34(jGrwt5+8a7*=%3HIdzJ=lHB@$E>W$hc)Ye-} zUT0+3AMtveRAF4Vp`N9y-vva-10$o4K#b#Jj86qK!N++4{~;e>bj|itFH=WywZzKO z*>M-6V{Ncg5szslZZ1_eov=~#`?4s&c<;T_D5-pbd#cIY>l54x!}?&k6V<0wB6_ym zANAjbozi2)@2T0jS23=aiq1ky)<J;Yu6Iq70{mcX)V-$dY1jc1OvAI6<e?3v>&<J_ z=G~s>9tZK>)K9+Ma7v9Ntdm*mzDywV&4kd8l&8;e-HZdLORuVtur$8*u}@kxlkVDI z-tUNOi7FEmM>x%}!?zYH-m;aOp<<&LUT%+inO#6XFq~!EnRpnzzvnjD?CEp*1n~1D ztSn>{;$J2>$<^oXbu#^#2p)HGe$Q5Zbq{~(YXVAB$yKc+q;Y4S)4htl;?^9(ED|XY zlig3H`Me%TdfO_|%L%Z#C*Ek;Fy9{_-iLMKVxX{}6w<sz@I-5JksInkcO1foL8Pxc zitm}7Z|L%d#yibW7koeuXimI!-l1PJJDkP+#d#Ii7|?u&Z<fXu!`XzFXVx$dn)Gg& z=&SRBZ@(MN{S1O^Wu&dU?Q8cxJ?rN6d#uD1Nv<}HTZFhp=KSh=AefyLelsoo#J29& zl7OY>a{k6h4{KqWOZOynGuKKD`IgetNEx#fY@9l-K@2-%GYGN9YBPHsQR>Y)^SgF_ zFIReyn?gf3g}wG@h`Un$uU&b+=faIZ&6&RmNI$@_Llhkxn!V?**cGF__OwUSL|yH7 z52Rm)G-XcU78NQ2cnxAD8ZBedpMje6iu`ZC`%PblICZI$n?;V~F%)f;>I4~F8_jPt zV_c|gb%x&+N5O4<(Q%NxSu|{S_AM1gX&`nk8WBrt>IUslg{wCQ&y%cOa<2~HrW}*{ z-=@epoj-|`%55EjwihkU2QEZ2m~JW}1oyT5`OD>03v~H}@uwj@?YWxo*VpDFpEmRE zV5uM|(Mfs4Li?t#GGh{ANKy6oZqx-|l=iy{=eHxQ53I3_3mGf<vN2YfTnkP6=f|FA z9*868H0mk}XDZYknrma1cc4{NF}O%UvjUyaw{k*#GCsw{EAYF{nY=&e<+%gFL_4$4 zcIqB#f9eF$ODS8vd*bRs>H%)FRU=P5&g!~sR_G36Lxp&>mGveKLU$u^cj`gjVq-(* zTPaq~=#EJwgz4UH=+8c**l#2oR`MYM!sU<ou^K-RgKd^!!$3uN!a2#+XLRB{;le|G zSQ6OJ76@F}?fGKFP?L@ZG+fP|u^pdWuoKY-6*umn$p_&Vmtbk6si<49vxgtMH+Lzy zI4WtWy+pxb?8OPLeq};MjL!YB;3!Rqt}+8-u6mu9VA#4rLiAA0jjP&YNl9<I9Fs2R z<+`0lO!i%v<fwdmdE$23x2A>lg+*jlVk#57l^^5V4l*Q1ahfpo6&hwR@h1OsFjD@N z_2)bTu{0r*P<B*gkGX<fofBW2tKSH$8k~A@%<lasrNfi>^;6!HE=#9hq!M}~T#O>+ z%4cfC(|N_dXX)@CDA_mw^9XdxfHpi5TWGNmsVqWYC~b=;d){I`yDIx>bdg0W>o<lW z7DV?66T6IZQFZR1+}TJZ#A1FzFQ8kn_K28`%70Dl>#zuGu#_7_d08~Y^P+2{b+S*Y z=mbJ!i4m*tD<uk=(`Vn9wV8lh`ha+}+~IL|ZQ^6V#T*(JJIMC!B{hm)Svj-iL96rF z&Yef)Ul~N6S){VHZyCf6%{|L0#q$~TTLejxxcL}7GK-s)dkN^IzR2o2uOCM}v%n4` z1fnT4^DC^1<@A+S=S*Z$RWqFGTPG^EoDmW21j|kLw1@_CuAar*D{_f!ee09Xn%Ci3 z4;QSyI;rrQxTkET&A;goEZ1<4$<qw3jute7!8%Ggq5X={xW$#&heaBm?g6x}|5~o) z44t66)@@71*65_XQgehM83TDn`Q1CkT{4fNa6%rx-y%moR9Egs^Y(u={TY-kz~6pR zrj~F4TGwI@FdVYOK_82p3G|kCqNjHh*=G7SW>61;nb0xiDu8H{eOPzyMLbjp@Eeyd z2=XBTW%v&43k0IKtkn0zo&>IQP?w1u+<>AB;94I|9e$v1d^IJ06k$zgH;MGubY+U| zHMN+muyj^&1A}i%nGFD|5Pmx8Pud$GhEyR`cIl7V9NO=R)-3TktC`z0c*mKPHZ;0G zB<;<ab=zSXgI^NUiJd;`p^ptix8G|#*rw;x(9)urN)a?>ih>KHl>Buc;h_r3Ygldd z-~CZ>Yic~APS)M`IFcQb%tc@-kxY3>9Xw_u1uiWs!@YQhfmMOMSB{c`AehRXd|44- zSvL?uLXF9=nJ0)jLeJ^88(Ctbo6mSR`!Bf08k+cO2h66lGW7oV677~fe7G#1xn~RF z9Mk&qBI`yfx2QJ8f$w=rRq$7}Nci05ZQ@!&HHh~F@9JVRH*84*9m|o_@j`Sdu|6HW z&}^stjgj8qNz^l+g{YWkMiPSb&ligGs%ZT@sn#%iG&X5_XvLRi?2sa{{!WirmVP)G zMc=wuiA4Fi-!vo89~hC~p$!0+%cvU@H(C5{)AeQcPz>_hfUto0!>i+C_sTVS9u(!d zDH3O5l776a>=z{U?#gAx@+B{2Z*6sEI6A2nn=RXY3`(3;Vt@{;Ult7w?Vwi>XL;d} ze9$<&UPbkZToU%9l<<@}C|jFW5_<ddrO`}D7`Xth5V26A@(|=o33Q=#2m$A1YhBci zkxaCEPigKeJ-W4B;u<q-R1|~Gbg(&pIEi-`9XKkH^rnJitl#!ZjSc-WyD<~Za6Sc( zUkN}Z`KyzQpQ32q+cuK$DKIFA?(c!t?$-c9<*r{|G<_ElhsDp4v<VuM?ckxEH%w9y z??<OmT~~B%bD^@{pQc^xEw`STf9h=6hno|Ie^{?!o?0~ARk_69xbWWT>Sle7t$lUV zkKS5i=bb>}hIGaeAH}r{n`>Zi6`usJ(LCn2@g=s?DC<*LnGEYk0gnk-Z|S5AIiN2x z<~pU~y|znhnDK93DtrsS)-X}u>P7QIpx>kzX;eY1fPkV1UXb{A@AD8Jf3EW$h-9$t z_rzQjZiB#>nRy^Py@3K+Cu1(M&!7n1IHoI+74Lob(7Tq&U4`ZTA>f!0m4P8xUE9Z` z0K1D!_YR;Jz4{|#=pXdJl3w-#Dy&Z5`h|4!m*PSn_}x1kDFJje5E)FJZEGN1;%&TW zVmvsK`aQc+^T>hAtdmEJofZL`3y&;GWfJRcV#yyBjRlkHKY;WDeX3mCOiDQIy7tgi zurI8D9nBsLKjMyBv~)~EH_eaA(*!YgmG`jF9uD*bPTVOj+?cdCk8tJ!9!u+A-s}_2 zlG5S*?G5Q8KiUE&+;vp}mfDT>Df*2*ZE>%%uFUb~TfxHN!+Jj#z34mO9|9_(9kWL< zsEjC=ZTj*yc;#yu!tkS!DU^7$dmmN{!QHMRI3&kb)u+>7DUJwfXU7Ay<FcS`Y8D9o z1^K*a{t}1Ih$RexL3V5zJ|D8=L#W5@(_0ngSoqStW<jvDtB91hV;vEBbNrtUCw-zf zk@yb&B5}TJ9Y2xUYS2mV9qkq(MFG@Z_MZBc;aD}Z<cWlPiN<|QlKhAvpUHn<OKU|x zake6V&&6Yywj-Sd)#f9SclU+y>K-Wk$LH|1nWi<2Z_mY<t$VQen3AfVELMydB7}Lr zG-vh)8!UGaNVs1etnI%*r6#+ZBZR!>AO(%hd{O=FW|`b*rV*b1Q?WaQFIv*dF$q1R zk{7TYOM{;oP6jD%S>oP16DlgvY!I-+W=~aEb)q}(=<a^#x;4UP{$)J2LbTNqDET?? z71YhnRVI2M*X|I{lBQV=fr|7|@K^X`H=|nQ(A|;82It?rsuz2Rp>m7VXBAV)79nS= z0hUBa`-z7(ou%&5Z&<@Lhmh*y>V}*N*g}QeTQHT@(Gh(a9Zj>|$7%f@UVIv|-lE^$ zh@8b?Vj9Vdx}4cfB@%xQ2*si3EgWOeQ3`f$Cb2&k_mQK<o8)27#*8-UWPS`yMIx+% zK$TP|_?Wq41$v^xBbVPz>lR+uwHh8gn!_aaR#j-|eb`wT<P}BQ7&su)y=lk6ifCcq zjWUS0Q^Yp=m(;dZ0ZdRlIOd?H_8Wi7u+CBl_P0<=(B>8IMbSh)_D^M9Z-pwC<#Y%V zBKzt%_`}Fhu&%7a@Z=tdMKIuvz+5C)SB*QsIa!IImtVVwuh0Jg9*aum@57$)%OG&4 z0rA63(d^(5RsjKZrJ3;8(p;n^^ekx!iw|H2AOq2h(f7=*AVFp;MQ!37W>nrH(N?dD z($Fs;+#knubVyzE&@sqxTLVyS^&1ZEl!KfQFi@|Ze?VO=Lp>UAx*3da;PT5=a1&ha zZp>W7u3B&Cm;S=u$24s2kPhzcV%QG|rFEq+|IVmWhgSN;U_{<VP_DGT`1yQQ-3g65 zzYg$5i1K^nDhKV>7R+|}Xx_>(!y!6q`}ov;8pAj9@JXo328Q+Qq{~b_Ps)Y)wsuB= zA?9H=V+VvyMyTs`p*Tikp!ccEFyDTq?sPvQZV$91iZG1U&n+q8YP-EAsckGS6ld^& z-$Q=6Kf=S?<3td|@PL4SGFNx<a6*^=?b))!q-wB`>A<=WFrQUXi081>)$@E|QW)2b zg62p>(u_nJ2($~XHptjOL-=Cc)lxd%JM_j*K^5Z15>DW05ghFuI9(<tv(3{8P!t}Q z0ojLKPk&j;wTQfvM#|v27;Pi4`&}VV(X|*o@Z;CS9JCouoQR|*@#%z`=w%RHY{2!- z%lbK>j?8`X)eVTD;<~sBrJkN#Rt7=<UQIBDcLqxv4~-HtqPG8t-v0{y(82gRhQY+K zJW*eD7ZAmbd07NMXbtBoTv7#;@zaAEOy|=pBG49RihH|sEa=wcH_Qm(DhD?--2*uD z#|iV*c46o=Y9X7;F^>or4|irZ<G(~vrjZm`vs(%XWwlmcaoQwS=%eb#gLHKB4W_Z? z+%fLIuqt7a)#=GwlhJdGZ&E0s_WfYDBF*5p5zKlh>#s@RG>-FC9hUqK_Jky~*}BmK z)jj-&_ojW1O)}@p0(eFlT?$`ruEynlGvnAO_xOc9iQvofbrG`K-Z(>1mdqIJ?7j4! z<IRKLl36YP*tNd`6JXc)Qikm-)`mD;1IPOH8SF(GzNv022Uo5pql=NF7$rK>qOWMz zuh6Zh=taSN0xAeJrp7n@*alM%GUVD`sds3XdbLURsXd;hPd915dSQX)6J4Y`66<s! zeP9z~GKJdB!s3Sr#+Q7A%|@SBN-<Ix)}?7gRB2nTy|S`Vb+92sb^Jbs@Y^$EpD8Xq z_*knR=8zX3IuUXdNx5eJJ6t)yR3dYG2Gg=0RmnVGN~4CHoxE7NU6hPZ(jeQnLy-14 zxsD}+d_H2Z5yl<6K3JDRMk(jwOqi1frQ2tPjN+%Dt(U*>rVvDL#-uVK4amaT+@nb6 zXmn~P*L*wj>AYCy+{A0=)U_2q;}8)6@mB0Z1Rc^^XxFo<M6>-Gk8|h9-tvCUI%o=Y z_|@OVXC7Wn>EeR9Y9mfJ-W@tR%c<8oi%n(%+5GHjr7H}oM^$sUQZpCq-*znggp%_L zaHNGHrSjG{)YvNF+JOr)NP~Tx45XTWH`3xmrE#UEdm3zU3YFAHy<>ef(CIMhVbjbT z9UYWwPmS46UjJ}ztG_6(m#_Oc*gW2%e+5}o(f3}vo*`vi61QmGcRUE4kh=Z-?i_Gh z?@!>aLdv%+b-B44^!2I@l$60$Cc^4Mb<05PAdAE&g3Tyk9SRd5x>p@GKcV(IT9pF1 zTA08gq}1!84+nREV@@bRLlug)Z~+cq*-;K_n61pMX4Sr?B%dO>PnItn<G)reYt{KJ z_T5Nsf8cblTrXwPEA3DGxvoLH(az-CJY#iN@r_8DgSx8dH-8_NP5U*nHMC!Q8}MUe zU+07i8ZaoCoTBI;uN2>{ZT6y)5-5aBHAGD$l_*NS$}37-mTk;JJX)Yw<Z>J~%7_ZT zJLYC*oo4)FW~R&<VYpc6Uld_mGPnZ`*~Gf@E%{`~wHLp5lN7Uue*^(*BtK98WPi&> zyKgDVg4-@$!5@~;G|G^n(!qw2NK}8uH}U=XX!`A4y-)3`QE{o)u33lgTK{-Q2>Q8* zaB$~+TJ2LUhR5YY_@ee(u#9OojdNeE%3s$9y*iI@nyar)yu_4bW1%!>THNdXb`1OR zU&aE&E{)3Ys~2Lte$U#TkaTIhBVx(;HA#`Qv$EQ2Zw1dxx0i=j1X6aCM1#%P&&Ged zJ!tsCT2#Vs3f1*xi0Kg%S3H=M&Sz$Vpyuu3puUEAX0HM$(E-$g)2G4+2+;I5EpqG5 zj|WRZIqmEVw`=P*mb5g=b!tJ&-LYOjp&eRgGfVX2n5<RW@v!z$W5=+f^+KjDrYu9C zg*8-T+xz{fvr>*k(SoC*UEB7^x3)J!U);RP49096?RR1s_IK0DN5>Cs|Afg=C>F6j zGybWKVdwSj6vmTyL>9nm3WCTO-s-zRp5P?}H-qrzh!CT4dGp&al??g#eT((5&S;vb z%xkgYBIeOlrsZ9QF<_4NfPtsiBO-5cR4grbju?E~1JRZyr5%S|0<ESLn&62%E=z1s z%HC)L)n0x)I&;ExQULl@%9Zb~7I$HjeSWcQMkP+v;S~DuMtfGqn9S~V?j2~jlOv_? zYHMA@60jbd&P}b{vW6zdc{@oYb{0S-_jk?E^ZsOq%ekLGyleD+4+UuxV&kOT&O6{Y z>8QN6Jh-C3ZZ9CoDuY5I`8CcE(Sm*(Lw6zCGaP`@l;Efe9(uW*z5X~36TS`G+yb0P z0cjjYqDWZ0$>yYcG?)IsB66magbv@=8<7#$jJIIBL>%%c8fb-7$v<3->nSiRR(*2@ zjZ2uQgey#=j^Zuqa3J22K90AN<8NdDEiR$^PL&^pdw1%%{o+B?eP?ZixM2QG&4A)@ zAAsi+pjBKc$5?2u-wtZ@Y~9Ue5^?Lro)v;T|FOhFd_1q|9C?RRRZoMO$k@}`f-uyM zuR4R;Rz_7#*Ub0=kmo)MvVUxK`agp#_9+y?_y^h?jvP9Onn6hd!()Y`Z{+b(DQ=k9 zydv2uH&FC@&V`*Lj(h(WaolP3u{$1=anHxG99=0av)#pCu5&iYy=>OAApqLy2G<sa z*8yFF_{VRfUDw<9K*6oDF&}|ocBS)CT7-ii9%|CwzWRI(BRk7}glU~fmmyv%EzQLU zy^%Ovq4!euI*)+o8s_mnLQ3!e^Z{tRT)n<0N5XD%lLfXZMQ46*F?VtbHIv+PsTD3> zbZ@l_mUJZ@W|01Li1?V_cuowSTG^^xE{?IBJ2Zj51JGzGv)#ib0_ssUPSGE+X6CeC zuOzzP2?Tjd=fDehyEjYsm)gs4m~R%Vr7dZ)z?obJ{-lhn__D0c5%P=Zi(40lhF*A! zyJ1lq6bE*r*?1TVCPmT{LnQIT5NS5{o7|<UU!dL%;U~a>vA*ABzw`bh4l~Y@m&%Zp z3cSESm+OsOtSya!3{7AMM!T?Ckm6|l7mm?rDae9WWsXDprm%RQWiZ%ZV5re@E|cP3 zyO!`!KbES)#l6>(0+Bxf8mgbcM%}|qMnTsGo3ZB*J;*9^$8z)l^#fw`(D{t`ol;JX zk%XAF+lI_cjdt{ymB>SL*}GgWF7Imyz{t4*Co|@NY~*~iCzixRe$wU+EZ#7Yz9Sv; zIpB(m!Hb`bzwx;Csc?oziY_=~JhajLEY3?1Ms8pyLQ_ra9o7vj;6^)Kgi(CZ<Hf_) zSJgjK(TN>q{^|`_5o+nJW^$baGYBeXBdYS%rZIxg9PG1&O{g2^xe(6e(DC{+8VS)A z>)O$!z5`AKRj*@)DdTZ7$)H8>ov}VE>FN*6vrX+Pjt2CmMV}o?L>i-b`llNX&)kWG z??g|{-rFXYiQP-u2fnZIOH<695uj)^%Ej{^6gG|wQ0sTJK&XbEv-Z<@QI0<&NF1n7 z?1Ai9<uW+&&<Z9QBacQp6#T=TVxYZ4=Sgt`5k{IWI9YN8j7njv)rj!6XRwwP7Zuv& zu^=GR`Th~oT2Q>l5*Kd;B&`m6MO8Lo8MyKZMV|cu+?({J{Ti>TtDy!1QI!(gJ;Fo0 z<{d-((1V;AC8a2YQ+MpcikbsAh@3cIZt@u>m1+@2&0YVEaxrG&V)T!In;3kfG-5ir zk*+JS%oFSKWO@19SDe}T-{@B(1=2da97U5~sv@c9XIw7A%OUn5Q=zIz*o7Br1k1Sz zTS+_u8IUlU^N_Oo)5r5us5;}jFey9ip2~G~q(Nuoe6@Wv`qo4vxm%3Bxud_1Jas`N ztrRxpOaxiAkWL(v<0f~kHviC|3-f3z1QWdvcuX8=JT~%(oc2+1-#AIxtVHKaaRba3 zoKXV1e%+HJJ(#z`W3drokmdL{!~Tv>RKv26<QJDWPo$BxDibR0yr4Gp-;#)icvpgW z4l|qGV-lCdFWzrR+=o*Lmn%+=ucNRKM{jfkq?}q}@Rj7sl0Aa7U6{<N+c^X+1Toa2 zm0+JkFbVB`a+StvtR&F<!nh{~FCxNH@~nzHe=kj}y6OjpAU$&XnY~M0?_#b;3+DI4 z@<pV>s-77xjLtzfam#)z<zghnO`awm+uk@D?F`~9%39zQPuhMf0yWPzPt;tO#$l(8 zI6jG+XXnLtV_yHH12E;!=sSoOh%U9ntIsm+;o2X3+WL03Wf8{hTG`h7mWml}jm3R+ zcuCGPgSD~OyD@j>Q24ND`!^#8_=QYcDG7J-BfKcVk$4gv%o;T_cgasb$v=h1m2vq? z_F*p|7KC1m<dVB2quu8@_YDrh9D0K$$s4Ne+M*efTQNh(&AYlkvOYkb$?-f;d3tiC znA(nMq|Kjx(bP#uycP>>bxWJ;?LUutu7D<-|K%%!S!)N0Sae(+@nA{S;@Hh1+2;c8 zh5wT%l1Zgl@cyVBZIyVgkc_HN;kPw{0-sl*YPUYMdEi~o9-wLbbtuf4NxwqW#TPA# zxTN`-!S~YDVqU743ZKj`086wiQvOU?GRx3#>e-|?!|OAB_NpQaf^JVUb~)Nd>HW(; zfU0|A&AF}zpzs=&9lB+H$cSFE>Tk<ib_l*`E2cjISh_y(5g3WG3nRwL+4l(*p=*Py z5GIkBL=1)XNZ+jiA#sI_xhMj6Q{+ez2Ri3^%-%`1tbxq?t}YJkw@t3QZ=Oe(#jYmD z_Y|91uHA?mF#z6CRIdvD?U`nurUB(OgFXs5{|yc7GoRVHuZun_<Ua@{Y7f>U>h|Fu zKsFSps2lN!0&tTX^ArMNI9GIlyGEcotJ){?Op>$d__6w*1Pl<-gk>0{y(%P2(o}E{ zcsa^|6c*X_Md!G7xvwP*I8MIQlwt~|R>rJC5EPjz&cT8mPds;ul3V0r^pkHmW}>f$ z%H##_dVi#%{>H)hdNLXB6Pc5Y;gU-C__dpc0(D_;Awda4Acp@RCg{@t9}|RJy0<IO z2k4)*0_=;}zAMuitU8ih8IEw$2G|xkp+#+rxO>MT(l6raS-*KUUMg!kTF}@&eh!fu zA!Yj~USdjkwte9$(lO1wrmipNw;f`rUCOHH!+hfD^31C^)VkJnE0GH>5jv{iWJG+n z)Q#6!<@Ox~n1@>Sw5}CTzinZV9>$ycX>xLI9kLUk>yee&Ah%DLJKqfX=G#lV0M=8* zwSEG*WAG<nI%em@*8RRFqjJb6?C-|y(cISn7$~oHkMtVokaa*=<nNvq2rA>z8b@F2 zAkr;B#H|I3f{Z!2K95Zm7+IpVW7Sbp2K#FdO+htZRVo*wmfOsY5drC(O{@r9JFigr z0QM<^>wYo_liKd0+a23<NJ6P0bC>zWZ~g0Rr#u=<pF=#9w}&|3rf8t{(!Hfe<n%q* zsQ!zYl&BxbrYK2E$8a5y2)jVIS);D(ThTpgu#H4!r(29Yse_+psH-cg%&OjnfB8d) z{74Q5sEShpQ?U}e%x&U`u?#X+xfOF8=~087S_g^aw`85%tBLN|?L4Bx`(}2?JA$7h zrHvqNAgxTecoPsh4&c{SH&)s)BNvKU0!x1P&F6wx2TZ@T$w_F!%QQM~d@;xbC>)>k z(xz6)g`z9P$z!j@L^C$$@-i7|r!m>r;?<j_C7tb}xzc-lH<$fP%Oo!lZ&J1+2Z-Dq zkz&@S0PmxV2DZN76(P2%p9{UAbKgypzyHuveoYs}@a@8iP4q}+^!(z&C?)Y<(-2<+ z1+S{}!$q{5r9fT7w_*SfVg>j#gXcLna)sTbCr`0;-|((jUbWj0F0Hi`xvKLIkLJ-B z$+tb1^k$IBUAy=LF1+A7698mR>izm6miDEu_K?>Fx0gnurDKyi7G(kw?vIJX&Z-b^ zmbp%m5V*7#^K5MeS~&(lR1U`_lB$0k(7DcHDn3ttE%CH35enCz63P8uFkf%_(XaU) zgR;`?Xy$1oa5~l!4{#6t2uDalPzv#DeEkUOc|zvzyGgq~b|Nr41}K+B<VBBIIDSH# zLv|x`hCamcK#GFU1`xR@tMY`Y#McYHD*Q210Z9&yN#)VFmUfU!VcyCWNLq}0&mrQ? z=}DYpLjIr4yK?B$eK4v11>)8R77%C&$UHh@jdnks=S<q~kB0b&!9gll5o1p->z4v= zmxx;ky78-QwehApLN%rmLE1#?F%+YpDCjzxjl#+xNRd@9H?<HAbx;qYAEtLBUXZ^j z_MzhwlKn_@ONUQVd;fRxtwz!PWa4hVn|Mlu?tt^R0vEjz9LED-J&%PW!DIIvzxy=` z9!|paYr<)-=n;rxDtbn8u+tvGq*gK_Ro?)ih}_rOs3Ze?Ybl>eB)N!N09sr_%)<|j zfN(@rvH_lx5XJ%lP`<+FQRpE!v_LQ|kl_uoI!$c8Mgej?N;1|1I5(5IV~c&n$t0u` zeZlT;HX4Q1P>f#Gp*a#^VaLp|#uu4rGFtV0Z52WB`gW_X{9<$%1d~4T=+*;8zek~h z<+540x(-MTr@CY_whrPJt^azH6oGI9piuLoFti)8h+nsibfGCHyUco79_Dj<T(S+z z#<n<=hQeD`fvU9(Ll>#YhtT9Z*ggoU7++C!=xIy90SbZH3{MQx$<59Z=Xf#T&m2GW z60=qc4{)^*Cv*B(Lexm_-o#6U{sl(MLPlq&(#&WPGN-T3AzbgPv+p_k;&#kj0l{k2 z?qdY>2cgI!v%)i4<zm`o@BK;pIOphqZKwdRb3BN~vGcmCw?|1J1bi?mT9EaKIP5X@ z{P%kbU?(RKF=3k5{KUo*&h6+SqUPE8Yh7NuZ-h!2QjLyRjP~rI7lbMUUJf<2TNBe{ z80l}<5h2~kN^bWKPDnLM1cQr$3Sf;k9W+Im;-&tV6cqidP4S0TzY+c2TH8ya8!NRD zO3vjm@KnxUoccg^{T__mzbayF$Ol<vD*RkB(CZsZ(+#2W5+(hJA-ZQd>#=h?o|Kq3 zh2dxd*MsU->>GqTQuqt<pQ#Cd<w0oOgpIahp{}$eEb|8y-e@%d3r$2vv@ZeToRZ7x zZ^cUYVa)k0Y&Z-*WU^gYBgf&cu*PtilI0pNWK1~bg=4j&=+oy*K=-rd`A&4WW<B7d zokbX{>)bBJSmuDnT4E7lU`*XS*+?AQ#`sU0*<JTxtdG2V@-Z^|gNUX4jU!%dhDWF| zijQI^A?oXUwK?TtQ)LjjjOVNW>AmO)z(!?M@4o$sr7@E*cZ_4SzQHeRRvZyuza@w; zOlNBTJR#Mmi8f?IjtPt3shoRr7qhYsT1N461n}%}T#V23`R=NQKc*)ChpTD5176PA z+Z1z9S^D`Z3_F?>=_H3hUKJS2yxvsL9?=dTv)p`uQ03IS)JUW7WGwt1{uRQ9x=sba zN(*K+Gd-AJ?9zi1lHN99p9oc{#6lBh-WK=7k_lnHhyE{FDJj+g<`5pldy6HZ6Jdw( ztujx7O-nl$A}5ucVjyFpE=s|b?+Mas`0hGvbG}UEF0e-`2>ANigO5qbB8}xB&N&_- z*(_RoE<JQfL&YF<QPzlwVM$@%_SU6;_|%eL-lw4~N@v<5hwc2^qYc(-OqT;aWIB7e zN(N47BpzD(CzN*jt0HmZKEB_yKWM9v*dB=ZZFN7o&wF@%3(5V!j<S89#rA&Qfi~tk zw?2xgG>BOW6Ei9{ZXXoF^=n=Q5)m_!z0CH{aoJeLN|H@Lj65O&up$M;1dRC)qxuLx zr7!LDk6i{BT-Gtq%%Wi>RmrGL@x0_k3xispko+vdy7?;8rS<9U*0uKYsb^U1IcH3B zFIR}?^tha%V%|}&>fAoV$A#Kge>GjdFgfqTaNF3vKChjSiy-*ek3?AgL^j|s6jA$6 zuC@)$NLkmvgwSzf-8-<H2-Qr_0kWqN8Z7=4_)38#!I;;Z@4CBCk?s#2sx?>r9V*b; z?H!spKday!M(x>Whv_NFn=B!Fc4g=)mD7F_Q2$lTaEw%1AWt8*%)Oqf8}rXBD1kM< z7%A>h7K$^-F3ab95#+HfTqW{cobOf0Ztd3fG{X^jYQHzU_3D6v%6gnVSbz^lKe=k( z1gPOM1Jr8#??$IExgU6_VVYHFsWy)sp`sj}LQ6yRin8a2kx(X)t_L3RF6p@6_7~tb z=fM1(bYS%*_gC|-pZ;=<7{cBd1Z13Uag2g84#avBVkxF0)tlKZeD>d=TjrpSYs-F1 zJ03(=;rQMIQb9di1ZR8`_RwWtx0%nX1$Wo)fz0~#U)eWRHY_|Pn?~W=p7+#itHh4a zgg;nAUw6v~`aNdT>y0`qNCYw_swkGSdmBd4Jt?;V)E$j<Sl5>pgkikkCc$yJRd1)s ziez;JGag#c_wujQlKJD*l2=TQl77>%*RS*Ij#}~{&gbU`eRYda)X%%S{ET}mdq{S8 zO&%j;P?;Bz>w1`4Qd0MKYRUX%;_V%JMATWGqMr-{H+`5ni$P5*CO|(IPN8V<(3igG z>pmvjEpQB5oJR7~&u-e%qw{SSjj3=LmwYO3K+;r9AHK)c4o}0EE9~v;gq*?!|NbkL zL`u2u`+`;(_r(~$cK;`5wnYGbL>y(gTUJaAm+yZjzE>7hMgiJuvFN_iT0A0*_r3qX z5<4?YrA=Fqa<V>gRsfGHT<`6zoN@2)mYYx6RjXR?1!NJgxt8OhIsvmw8j)bqTW^2M zDEh7{&h!2k{|+J7hcgjDX#UeV%v63S31pA-9mW}!3bXhR@>FF{(K%{WBxTdSh0?tF z)pj~cVt`KT@7ckFQlH>~LITRYquhIL{r<LCC<-n(y69AN4~bTTZMUvtzT};LK%oCP zxRk#J*YNNja53nP^&e&*TrDj9*)GwkPmoZ^xzU(0@yIP3Ql!yGSGQt&m`3u(^j~Qt z3Z7#c9+V7<kw6NPY}}h$nxj0^r)#!xlg!QVav=R-pW+daSH-fuApxU1O$et1$H#$n zor3@ZKHdZ7ou#iykl?AvA`CkC+@W)!Hg+nucKT;N3E&gQIbV6B<&A*LM5rWWRp_=x z+$SAw@0U67D<sfe%7zJp9fc1XPJ*rDA`1Ha@dyyw(s3V(-z(jVZ4L_%Iq$s}ev}S+ z;*RB!rzl$mN|yBeJ{#M?RrNybY|N*6_-&vT)N=<MGv?0h{L5&C>T4kxkWEh>kB&eb zKmla-C4&Pi998n;n53;abrfOf{f?;veA+9KVC`q8tmKt}$E|10Op!Bs(dW$fX`Gqj zd6mgqEAOf?E*&3zV^~!Q^hz<;rTQyEB?kcGjcKU|y7@7d%O4S~C$3Q*p~#eDB`t!G z5>9&s8^1ZhVGsI8AqwEn-*?>D#aWaE`8ZiEQ%C{;bEo>9(h-!T9SkPrZi-Q?kGYG2 zhJVF0=EmX?bc?d74Ue|V)-Z)VzF1p>ZU>fQkDkn%XvBvg;X!>Z){LwX=+Y<Uz67MD zz*)+D6yJU~k~pOt6Mmx~fZkQ;KRuiS_B2Hg-Yh3DZ@>GsU0x#ZeW>vnw{r>+r+c~s z`j(Zx=w*%1x~Swh;i12-evxqLyn4Wh8|!vCzAfKfNhbRLK$0GnUwBB2#YZ#EKuL=E z7ONh9cI93;3ycM}<ose+Tt6JRD7Oo@=ahV`lEBy0og%=xt_t+k<1#*|HVleJQkGIz zvx#r}ezzI!=J9G+9up&&tED#T>r+K@xg@mrud*xs^?#-RLQY&AFmJR^T}rrjl&XB< z?#tdo#F_|wX*;RN9-KT;DSiAMWPOQS^j9|ZjboF%!4KF^n=j}f(y1O}!wl=tA_hW7 zXut`h`gHL}yn_DQd&)UlS=X<;`OCrdJ+?pJ8xCg8NZ*8o!vyL1&B#=C)akzA*C)6h z{5|mLDTr+6-!FKq*=Y7$3WeS#`2^_0{kp%lG-+wQB<ji=AadghmP-5Bb{?SyogY4Y ze)!&7o3FD~3h~Je$C>$?qj=0pb_BGWJqCo3h7xx6Ch+}<eQBxRl|%4CkEsTU-Ig1* z7VZ-RRMq~L3;{x&=GwInDnU5=SpCgd|FZ(x=SKa;1jFA<A{9Y-^^cO>uXu0aED^96 z$+!yTzqgWsK}67#_b>X-6NqzxSj?LP0N3x`g5?&Gl=0E4$ZCXv&C=rBqr6|k)PU84 z*=(>BOw9c0*Z?F`(VolAxtv6>>5XpypdKNP8iN8)<L^Fl75JaiTQlF`7en(P!uPE> z?k7Y9w#huVHr>JBH_V~`F~q!rvZwH3X)y3-!cU(4(KMP?03E?nq6_y+%pH?$9AS4* zSTc@4t)~R~u86gUjZb->L09Ysnp)3!WwnL_4+a7jNvZc9(8e`E*Jp_Y+FOzSIqMG- zmO2kNyN|~9V}uZghO~C)5-2r#H#w7X_U04iwuM#<sz>c-9l`d-0>SlWKgG8vgN)$c z6)QHn@^njNX&H5Z;P+{$Vzo8MFLV#2w!?UkAq~g5N?*rA9lgSRO^-e08qaS_^@js( zaIWkTXuWgbl_Hw^*n97DS^aadS{cbCV$JzI1@&vdKcl=sZ)dPQu!Kf(Gvdo89FuXf zI_E4W0-=LIsus0~nen1D3meRl&-^m^7N~kdr8;vDl*B9M_WbypeK$%M=QVhY!@NrK z`?iLmnE)xf5E9aYDQBJMhpxvw5r8p1*6H6*5J&c0!1$Rnp{}t;1^E^ln|(H)>v0VN zn@vsZkHnWxH^V1cM)OT>teHVoz};Uf_~ydD1U$q;3A<>z1Hs)q^lQk$abR+S>|@#F z@3Ws#lC5xzqI0*=lXZ#eDKuQO=v-NAd5X#TH>}Ewsyep7-x66C;s|gcLzI6(@2WAk z`U5`FPNB{kW{F$`;Jy;7Ti+d=zG8#)Fta;e&O3$PxEmsO-!8cjB=~!69(`WJ*!D|= z-jBF=_+lu8->3Kpjvusj9-N2o?#Wd2^3U!MT^~~OI4ysRbpz!$U;Uy3$A$srG*=FM zXrrta%*i6q>5riRpn~{A_POlQBrx;3Ag~-<<OVWnM4JxCzAB}hE%a0qS)nf?plYGB zo)*uRdv_FBW4*gX_ThAq;Nq8HyIHcW{aoN8-3yYA|IZIST=ISbXFG+;?}qRN_>*+H z=3A1^ezl3rRZJM!qz;;3|2mDs)ECSfVNOq&TQ@AfgUdKEd`}BA;MlbK^5&~b``0#V z*0daR&bZ>9TwN8G+ps04Dpyr*$BZnXV{m||(x1!hnvsKC)1`}Ww?MFJJbxX}%gu7h z@-XBh@AbVx(B{L4%xbf;tme3gU@O@I^co(42ifl3dKaYnBUtPqiu<WeY&dwUX|25~ z`I*34YhkkF^<dyXG-#3g_idC0B<z766Gr4-$XaJ+u9@MMzt%roC#?VHI@f`9LRHs* zy^VZj=$9;?(t|OWLhZ|U=@t1(Q3j27xL?zC^n0@zTYo;t#MwX;qSXG8Ouh}?vl%<c zDdwhfizWwrHrT(<VWQY!WAA~JM`J938M<cECpk85L1I6Ha<P_CEd9mv$F47@i{H04 z+8+L}2TFHVX^W@Agjw!MBy$x1Ki0l8tf{SO+hap)91DWd&Jhs-5d{T8iw%`xkd9Op z1?eS(7D((U2#9n@2#E9&G4vJ@0ci;xLzNmJfdC<akoIl#d7t|C`^hDjtUY_}HM8a} zbG!SSQl{I@kBisLS-7UF_{yhNb3^*$&XUK0A17zNWnQn2^FzO=Dagud>z8!fIYT_A zIaB{*wxAO;dT9#&e+{vHpQ=@+l^qG-S;ol_AZglWrj4lD#a-T!yXRk7g7EIQ3Z}0> zGbiGM={EC!CZrqxo{%1v_HFAj__y@&AB3Bj-$bD&hcbVq&wpO%Z~QA+{D<b}KeE)n zt8o7F56oTJuN7+1e#yCcnktwKjmX_XUoQOXDF21y3Z@*9dDV`~4nUbed0M^Jif(nT zLZ|CkKdB7?&SB%J+=ZVJSOO$X{5Z~$avEZgss$|`OG*8_`2AMuF=XA8i5y$c=f`uL z0KQ42_*TezxX82hSEo;lZo2opAPGq(e7e`R{jN&vx`>^ke`Qqa4WWNaY+EXhheP6O z{~+`?{^2(X?7udPC0<fNA#ADRMaAyS*;|3^^tvJasKVZ7GvC`@u9B;GHr=CHFPmfR z4w&+&H%m+A{JZYeQ}Es9JaL0yp#1+a5$pU?dMYmdYwULn<???9(d4O@B#^M?QD-e< zbP_u;rfzSAFUe-NK*`y=+db|47TO4#E?I+{9FC)Id(l+GXQ{Wuj<f{dxPwp)eWCQx zjiATY4-C<&_s^X4&$Oq>tj7ob!R%^5#dAc1cm}PHh8HbkfrI&W=0B6l>)*XX<<-S+ z07L%WS%nYh&^n1rd{olN=Dg2zQ<c40Y8<H<z}(|&IxzwT*kKwF=b<Nqq94;ZB%zQ@ zxuVa*k0));ASHw405>3rzRRA&K_KT(0R2<ozuxA-&?A8|#A_O}ZRS}-VPIaIfu}U1 z18SNdRp$bAjDcO{p(GZa$i(15o6ceTT(KMOGt<_T`yH4gJ09y+K=zIRGsuim9kJKl zKAH+036i!yg@zi<0h1Pf9ghE~q|E+gH@^T(K!t?+Mtq|s_Q%!hz6w?*M%Ev8c|x_g zPJCO|^m>+vaG3c<=-Ips5VSr2s;~Q&-6<#_-^~Xh>CO&XPyExg=JZ^$w2=B2DGafT z0aQNf{NH(+P+zp4g37C<N|&{5|N6+bq-Fqq+RM`ObNym_dy4$`4DAqp*Udkx4>Ica z5K|~lRVtZ8_Ete#`b-1S1*G26r-5PbzICbB_k9A!f+$a0aZqZ=sMot2-xwWuyZ#nJ z!~liA%E6oe6GF3Cj??nVx#?}yJ!@6rKn^ET*GPNzYX@}&`FN`5M3RXTCr93Lf}Aea zMEUP|v#WjV#R)c8XfMMusubaW+K-BlIka0Syt%z0jFad)2+onv%=qIHSMAl{Yk-uQ z6sa=Y<=#{sFnK&nv1l-rTMJMlaq%4kYQwo)nR(<e-o9R-<?6jdxU9~B3pQ0t=(Fz4 z3kMx+@LMn7iTkfxgZU%;youD6Iho%6CgKr=s@tgG*>AE!yZ`XAehJOx-zZGixDpId zz&n5`PyK@uQcu)7fNR2K*(TyHV5LRJQqztq$%cG_^2w*VPXaQ6;I~PfAWNKEXWDs9 zfPEimp$x|Y>NY7#!=%^6;V(e@ZaszDM?H?q=|ntcHb{!^dn!DHjJ!}YO6{u-`230W zghcG9ck{nDs=0;9bcFz`jDO3Bs+#_miqx5p!K1kwe6;^y$0D(MhM|cXm;>O8T{pFy zEY8^(lbwxp)!Oc8(+!)x#%K)?V~>O-n&mK%5H~&wP`=&<58O#di=Jq45MKgF>)VP% z)e=a@5WIU@2g>7CXS*UYu2Nr&!gO}6l2a~eBPBhUPPph4J5SYqD&1*#uug`!;KWX? zyXTJ(I_3Z=VfF(&lh6kD_ax^Io%_t<t!FXsWGb^?k`gIntzVr?0qD!KPa7G|GZ5Gc z`7P4`KU;+RN^+hQd>UUf!ou6tj}I}}Md&4W37>I(R27S)>#vh}fdv3xDkC3B3JAz+ z3~tERui%4NQ;`NFWc6Nc63HXtkP=vO;d@Na1V|AXrMBt4{u9_eFPg`kT#Jwg)w*7j zYhMCYz{$B6z_>)WGnM{2v$V6yvY%UD0F}t#ec;>A`WS#B1;XIV&AapW*o|PSpV1T4 z223BS<tMU-Z|x$gbV!=)2PksUE$doW$d%O^igDe&oS@t07UM-%M?U0;i)KM>Rha1F zxsV+1e!zkKL3sl2f_SFGU_FH37};x;JyJ5XzM$s>J`eAvZsW%OB9y(!hdht|ea{JS zp(i+x1ujMNH?lBXHV(Y8XrmL{pY;6Ph{tBF9nEEtewp$l%vwNaWQf*MG>YsRnknYr z=1hhH1SRq}sqSM+h$UT)R!P35%o$$-Vl};8(Cf&M!_MS#I_X=>(dvwV$xI=#7ZI*7 zlkpT#xy0Tmjra4fi9Y!(XUFNd<2hPwUWm!mB*tl-!Si}^uUl~=a(R@8V9a^gN%@O$ zV61yN4&Y5h=MFztTT;`6WMq-02{vPu?bNeb{&mo#lX+sDQB-+~j%qoX8E6LU8%`Lu zGNO~qIwdW6Ay#kx^3;XJR`yWulSiaX9x-h4N2t#-nVc$ayq&XuJZWhrIJAP6?B#}D zXVg1y_-;a{Y&0yAyEYCixb*Uz7lLt`YqCOHd*;-_m5q^wyS&;VpF#1JM!q}L#;r!v zS`)$_Z;j?Uw@{pyc#Q)Hq4I;lwXh$t&!>LMTGNoZWfURn8pG6zjU|lB4W77}7W*(; zbNv(|&1$sn{hh1st<lo^cN+a|*nv@eozA^gb&Xf}4pjfTrmg{f>Q(bfUo~KeR^|LE zr-lPSa~*H0d>$MXPfIS%{9)~)I}A`_+yIR1aiK*14|2=qxZVke3pL+&J4n%t06>QZ zfKs8R{1VP1{Z~>Zrjs!ECtQ;mha)`mv?X_-dLPD<-<m<M9sy&S>YeUV&J7+NI(g-i zn#mIPnR1<=Yj4(vQCSHVLJLPYx)4>(UTQ@X-PsHMJYG>MXJJWNcu#b<`khNekyP#& z)zZoIXuMHR$xyE<A>g&{(HV){KUe=K>t`@Ik8s!paar})MCD;!HmGl$7*>jT#1XV{ zG0;p}%q6BRVR*x6;6ApX2vad!Rq}<SD_)TwIwWvAnf)1w`|&d}vBPdYwALpE3oSBZ zY2XjqQdvq0>H`TwU*M(WMy_@Re&+U9_T8%#aT<*ktI?adca~^CvDdJQl&*yhg=uQk zO7(JUtInlsIy-jWwOzM|i#ha2Fx<*g08VjH=w7$!;Wssec5AW)7x0@<Yi2^<GI53A z`*K`p=$(z)XP^j|hN)8G_<r8_Fvl@ef7nVIigtwY&$=0V^>{3QI^k1Ww1)hJA>Mmx z2HO~^*(49*$$bH~j2e&ZGXL5fU=!HXj1CTQ>j!|jC0^rUHUc_h8XK(x_rb@-!?gM} zey$9p36=U+)|3(S)Gh(CEaP7sgaflgc9cX&>G;`Q@ilC(!oqYHNAQZu3=wY`Qu?MR zXT`}ujcvMNDtw|~+B=10)VIA_6Qjz`B!OJdr_LJU@Mj?W6q1LNQL;An>uk$W_b6i? z=!SxA(dUQQcN?BKu?{D|fGzRT@K@^L8II+Gaez?DXbxeASZdJ+ZLPvgqN(o~&m^sP zBF*Fx)t(jg`31?}$uf!CKy|{^aR)8e@V)5|L+`$P=g^BN?m{36zYj$uYUiXJIP-;{ zqTDRoxhd==nKvt$Cex{UF|`mH)CvHz<a`W2>ExW2MStX)gv<wpJTXJ~3e2p&Cdspk zzP7Wu!j+gRe+z#FUVj_TE9sdE*eEDl=d0NPB-?fdQ_J82Lmf$YY!~je5W%ePg~$Ei zm)zrN*}E)wR2$d9(#&?z#vrsfnSR!^ElvtFNWQ{Y8?y=+l&kI^RvY6da~r7vymej@ z;n7rx=JCvk^S3dPh4jEcv`kzwCez>qmHhW;Si^e#)5EKIgrG97ue5pRoduKybYX7@ zM8G$i@uK`tA+G)${2_YYiS2@}oMA{=jO2K0Iximtj){92CcqBh!J=2mkC;GNl*bQU zA1$(@c`dHoaU+J=z_mw)*f9h3(Pd-&>y#(_L5=0shHhRHBD#VZl3Ug*WPQYojo(p> z^nAH)1YBA^eF2z=N@AKxcS9|sE5xSo7xe$`KMZN#r-nq-nKYQjC51X<mB-tdM~~H* zcF$>yo_nu?<VBM(!ha*KvzBXwzcJ=hs2}$B+x0#CDVUXRFFiA5#?uC-g4E(C8x+hr zwb=_-h0NzPu8Bb77J!~+o#jpBEzp>S#>lIMxf;Xz%))#A<)0h!_I`M7)P(O{cLQ6> zEvz%4uYE_4%bPGzuFRD8{#b>tHGZ;MS!e+keReMfV?4q|*ex=j4K9prc-L!VKT0`| zq)!!R3|T7)f%PXAi}QEzqs|d@cxm7{=RN_-=^$%!N?I&e+sIUV*`oRgBHu2OPNt?8 zABuK)MAOv1A;xn9!0%h}a}FPio5nPTbB{N<5@3j&CDifF8$;_~oT`Hd=e%X-1jH36 zlSX}~r7TyN<p}I*{963Xgm5^VqBVoX+4X3op4pGdfb+I3lJ6~&J+&#lz4f}tylwo; z<XYyP$F;f8LXY?gaE6lS2PC$-W$ys%37#<E1YfYRzc_z3p?jJ}+5IE;yU12WbnkCt z*oHVz{z=5W<DSE{IM=ARC56g*`NQ4VaGM%VWf{A%XkA<RA~Vp>o653sQ;K9N4dF)@ zGX@~*W#x4>Wh9TH%%$K*R2?#KSF}36f0h^>DRI`kF1<H%=_G?FmTZ@+KdK~mCx2ui z|43T?(Q1nFcNB{bHoFWD|5_qrHe6LUblu2UqXOkSk4YW<@ZmNwL1Sf{Ou*Eoi8{}R zqi3kj9=nq8CO(W*Zl9-waKu>A95#Yi=eA+q;NU+w@QoW{5vF4!_|aL>{4ad^+D2y^ z!pQu>;`6<tb(Uj?C`BdM?Tuma+pr&OSBf@&_F8L2&%oU5a#GtO;xHHC76KAQxvX~i zFNnm0EAQ)j6*<HxQxv;UXQ_;)PNHJ=E`w+At4yotC?Watn0(v5UY?0gPS4U+7X7A~ zt@iB|M*f0ZNhv?#OWLODFq`$3Kag71ig`uDn8OYrKVr5QifcpuD41inSpm`yurrID zoQ|o|$^r{$-J~#iX^^f|oEf#&Fra&fyrqs=OQdF-16iFbI8}tRc1M5d*$nsUHbOo& z+xjm5D!xvomIojB>a2#84CtEvZewqyO_ripzfP~%q{ekFZP3cs%l!k>%X*&|p(Rtm z{s*I(HJZFi#uD3Rcw~5p123u=>j@s8Q33jjXGH;x;drz};dbph(`i^j_zQf-c7mc= zMNq_pV(qp^k6dawEDhb)cHqh7-i0EcJkwMSdtIC-6PB&K0Bt<Zu+~3{HC3-l`OpoP z*V?b4bu^UsbJCi>_tJ*;c~oDKm_e$+EYVHjR)~ohBw|U#)OcyeHP!ph#$Id|a0esT zKYK7ulJ^?Z;=XRlKg{zV6&{0)Z9(!%@<#TyyXd5ZerK%lLS^zXPVz!HxQL6&Fx=R` zt12-c`#obqDzR2CzGHpC*21im9sYG%@qH9S1I=@hhw0oLZ0H@O3#|93!7$bSw4(lj zh?#<$3l>$^`kTfW$+`4Ud-L%I#_@7M@3mRgcro<m7^2)%hf{bCTY=H$&^Pl5Zl<sv ztGYlQM+b?<z8t)J_7U9x6tMl*#qUX_FCgX|l+Nmo8K0F(#rX8Xv-z~efYR~}gd0Vw zyu1oq=F#?JwjSx_PwS;sveRxaAp+^}S@&RPN>N4mSWvrLJ9Uev_GH)P5`ffUy7E5! zDIfDpPANn(p4G4fw5SE(%wVEU{-1%0&JcfINRq23z8J-PtXtE-+&e=wC@^4l4z(ss zC|DQ(G)$7GliGZ%k4@NmuP!g-{Rs=9+`u0-1fqfqKXD;ft*!gYS2*uyyi@d<quRQH z)9CPL(Ond0w?+ZE1WwVAP9^+Y95~u!=cdf4sI0mXkqY2}H)JadG~Bgv-_zi*xiU0J zcEM!-WAYdy2r}rJW*ud?ELElM&Z4i(vsuNixWt|yk6eNZ*|iKaUt9kt{P1G{U$!EP zBhgZi(F{{nqhF1VziguE&T7yljS$H)`aG?c8PD+Ytec4%7^b<_(bER9*H6C<7-M4& zWZRXu-A*m?o7&|4@E(ba_6np(4X_|?{f=0mjr(bv=mLJFazS!D4#YT%!z;K|8-o@M z@g&;kI?`QpuG(z=k*1ma`)MEZ2d_0|cmm;jF?0oKYJ}Assk*L9C(D>04nY?W!_hj! z1J8l*<5ym!oWiCmI}67Dv@h7{TjA|Ie{Pk0#P0wyyTjWgkUAAG{e4zjWyQn}gPk{E zy{+G*$5Rjv*uu>EF3W=PCdmnHz@T?L_a40<IC%B~B;x(js<Wxev@nC4HoblhVdA0C z%s!%1=%`(U^glW149>}G`ZPmq*<e@6m1DSQZXme~O`tp&eFrx7Uo3yLlmt%A&l`m; znM}nTF&)zEMQ%aom&*YK_m!Qab{iv-3X+J{6XU$`A+-wC%DS@db?YNb?sXv5(<30S zNSlKJ@5wC388J17saMX4+DuKL`F3pEHKG)!<m$)8IRA6A0Xvo@l|_-fpPrju3sQHA z*}5-pMTlrEh{el5?r5YiF%v>$x`5^Y*ukAChKtU7-%A-=wqTefC2Jx*F{`^>Z>)%2 z(%2IYPBa6p5#vQ^lVL2tQkuqkzOL|o)EIxDzITu{KL25;(J~H<Nw3?*CK<L)OXSZ> zq$(kG41Ly*HZdIgY=^WhBpVRCjF8o{yE4KShO6v-X6AV)rQBoOOh|Rj$Kdz;>$hJ8 znBteT7(|CIZb*1rXk8KH&K*w35+L61>mkS~<$qs0$?cm8<~mM-Zt?5Bm@zv2u|%=P zL1$sEBjXx_a;x2!ZguzRa&#$V5~;cT2NHZ!p*dh3m&=dHLRZ|Fmk$~z1oZ8a`Sd|G z1Orj*xvb-XR?5rV2#900C^pgsw$kLo6M#db@=d#n)v}^Xp01IpL)L8OfJVTnxBXr$ z!v`B$7wa{B)?yO-Qou%-8D_g@XYvKm{T_gDI--Zmw)Fl9sA$t&!?e|FxX~?C0igo8 zH0*c>W?e!vDW0p>lzdZefUZ2zv_?rsD1XOP-07ZTA0_H!n)zRC$Sf|ZWE|i1ijviF zydZeWrA>HzWVF>h1`Ow7z!|%DnVJ_Z$h791@j<6*BAK7tqA7)VPo^ZFp%_20u8<;` z8E&coNMXvpjhoOYHhl)5xhE64l?9t@RxU}&+_^rJPwE5&lTX$kfaN-4!FbF5e5D0s zUEkKb8AIqiVmjbJLyh_xlcc?k7@(`!2_h64g?<lUf@_k~Qr178E36=EaWT=RtWA&2 z@Ve`pQ~FeXf+o-vs0sL>QE--w`J4zQ8e7*yf}uAVq`)iu)-OxE0F5@<Q3)%(^&dih zMp5k*Vb>KF;QXiK+M1pMO;be5&E2$pG-nvOb}UEAJ}DN=w{xyQ<N8)L@}%<ZLl>8g zk97+rozAx!wIdr?lM5zbBfDrO>7ll7_{&@G>&y1SbrzJx6ElzqTKrL9qkzaMYwIjB z&ndM)pAa)e)b&J)ojOf)=1tdn(1yym5i&+YxMn~Mr6b$i9yIHhv7}k(D?}(~N+hV; zqtVK&{s#UhkZbl>%J6)kO6JXE?!7R<JQdTRr>>NjfR$3+<jbFR8E*tRL|5N7c*ZWx z+xkh#wfG-tA9^*ss{dLg3m$3q1PGX2Yr*|0Mk+Oi5<;itcCuf~8)#qQ)xPol7%%J& z=~cgb$d4yKcffpQxQ9;Y;T>T&#iby0xqn9KMd#s~*j|PvcbI~^@M%<lJ*69=nJf1# z+N?CFyoX@W;n}}~3IGvl0rHi+>|-E9!C_sEt}-XKMz8)XG2%?CJCZq^pMx%zPQya^ zr3b5%!8oot!eo2{B(JIixv+6D)EkV10F&VqB|P&VG|I^<rcFEK?w~WqmqTv-y|~Xc zb`ssx8m@;iF<T0%VTR<@f4&BbK<I+MZ<On2Ym-<wXB*vga96ZlZ4tt*WDx^Q*tH)D zDcnSbKypHgpREj=)w2<@I(DY`y1RqU`H0CsZ86W$2$A-=ebv{-hjde*uXHN!*K>C! zbPLqM&Oxl5Z-?U5@^0}gc71I?95i05d&A3MCm`*~bFc8XB_Id)w0zBEm_FBBGa@zd zFk)<ql)aLNjy1*hXCbuU9Q&!>0p!?6qE6vC1uxUZU#1<`*VK{4)2!zai<g4t6?kg1 zLj#}HN}I=iSQl%1?v0%Bs=at2M29x7#Kki3<k{L!ZINPcxtp49otSG^R`2vt>s8G* zwfI>tKz4cTg9Ww#*O^%`Z|oh#37Q?5-qHCMYbuXqN)LUz1v|fkIX-s|8C8r@mi673 zzB}<<{SkQL<#$X0K*f!g&=fsQD|AL^PlBVV$GMx(V0AQETE8GFARn#P6R|F5Is_W& zRkumobSB<MT%Cg*KC_wL=!otWZ0?mG)EdD+-+sUyX*3@wkc;G?f*+jC{A*1+{J0bo zjCgvCpV5ZjclXNupIO1#V~g^PTF9kFPyEYEM_<^_`c2P$4PUSg&0>n9*i(DKvKqY! zmWaT-A&EeC)fKz5&#Gsn%f7bs`JQSNwd?T;!_uQm1JlSt!Tx=abFiL`P*`k;0*V-I zetB_`rMk$fk^g+a^^MTr^V8sr{VJV%^YL|t&T7|exF5DJ(-eG(jRi+M`A2-B5%zzg zHjdVby4)x!{V?i=av8e<UerQ*`&^3Qy;mXYy_}%Ek<#paPy$Oc(We#TK7ODTI0Cga zsriJ|8}y(V*YWcWs?`zL{D`AnF1Dut8HI%wAX5Gm#EhpS+n9qwUzfU~uL2+bw!e(4 zIG~?5+7!XRDrAeZ9-e%E04P%g?l$|x-6r)Sj23J-Z3Bk~OA|Q$Zmkq+1AD0xj(EDB zlDE#!r_zI|)o;Xf_%ja3QQp#e8M0=QG3C~Q$*e5}9Qs@A^_F^#ua5>;&D3&0l9yy} zms#4V26*ZdMlK)+S~6X5%8S4_0!Im0`P#OjNDTB8*4~x6vqn&%W%kt3dqP=6LJLQf z6x5n}bd(^hbPAY&(A+fk%<k3TzGuK@idztE$(v~2iF|AMsyq%1+r>azb>~6t4V8+q zXIx6hHBUwZC#|-a+-k~w=DP)1%XXA_#WScz!;f2V`*Yk{!|uscKXt6^D|l#aG<Ful z4&PN#`ufA{rAq_mPpT54CT~z8<Ucs{&VTQIY22nY_%<}BAgmpr(#ye{5eb7i7F4rw z-fp{|vIm1fk3yFjET-1bxZb;Jr2@OiedOh(w88GQ!GUPOXWB|R+Ss@%vMz^$dy4Px zhkd5ZAeflJ7DwIChu6s82D>9-F!6zd&bHLe!bw}qpqoK~CREjIOjBbVu{~%YsO|yh z8~1ER$<?+X#T2%cJ)exCoGr>Z!n<r|dvKWz+j^6iZQpPJFdXz9Q@2M$2X6(GJ;TUV z293LxtHg1M@hZPz*L?!^$gR&jqojlJ9B@zuYs`)Fxx}}49Tna{=gA3Z<Ek^Z6ja5% zvFxh5LjP7x`_wi=#MCX!Bs)Q4A57N*lqy=(RmyZMYDV4_&3_=mqIVgPSkQ|-w*eq4 z6m&mh=QPn=tPLaPR@(L+oWJ{oY5%dnEhb*Nb!tAD7@6OqlVwYD+gk3vT6sVbyK`}t z7$3Q4gc$Xgf^#PZ@k>X*h|yM|x}|A>(UNJhk@b8t!xHb3sp&l0tFtM^XXV@i9*n^p zPZA9(zxTj0GX0OW!ub`~xne-3Vtx+E(;AF^S@&14=cy-z7%}2)7mBeT+V=hS$1+7F z4`v^*pd6JF(6uH)%m!%Ue2g0B{T%g7<);5}$W7`?lU_RcOR?*F&WpB;KhECLxyMww zWDNSWgx*^3<NAe@lYc#1(&H8G87gNdd4$$_gxWr=y<gF2$yvJhy>{WY*w|+3{NjP@ zU&&0X$&Ym>;=nm(sx?sgGocAvq09oHkhh6p_Ne5wqhH0VeCD<+pyaq1I>3r)+A(KE zNa@iB9h14aFIjUP8D(iGySui#XR6CY?u|G3wumlI>*^}`LVozjr$GF^Z3omWM!^FE zN?S|&%O>kkiHOd+Jdz-8fGNvNRKfaAZM3J=XdKp2LN+yHhgnmAI~tuO2UWk%w3i6+ zK<u^C-EFrnVNnHeXSzZfRn*c1$;CDYB_AYl;u_lk5&v;tEvL>@u=CBjH&Bg>b9+4g zGHDmLQ(C>UO3sf=`UkrweL=i3j6ozhw!|i|dMrF=#or1SBj_jD5;l*^02PBQy>Yf{ zAEfaB{`k%LJ=I%9Le-{MU{NaCofMII4I@9K)`%3pPl74G*i^V_4c0uOu|EDiDkyWs z_s>7sN;6m_MAP4Y$Ggv0i4Se}0CYsjtezQ0uxSNVdz+_>wwg!gN9TPXM2;CdEWuzi zTZPOvQAnfI(REL%_v&HH59rH+@x!Nx3S*xd=IG@}?vm^=yL^EDcXRsCi{nP8&Wc?g z+}booJd}mB#6m{5ohQ{&llZpQM2|<^-KDnz?dB1?pDla@=_!yG`6!>g1aaW;fpyrE z+|_V3oshXLTusai5b8<gBB?4)MycFSp_sLwR(lE`muHeL;$j!Zez}R=yKf4AY|9EH zwnm71_lZSoJ?y>~6*ziMisBiwg=1e+RQ*gRTgCWU0%}3|L|J5%U&k%a-fj<1s^S=+ zx&h#_x9SNczu~edqF&$yv)AZPH675`o^_j?p!<V#PS63|^A7uqnl%Cu*z`SXuDCoW zj9ThL=JBR(n_nw(D#zZ%6oa;+w5>6ZSy>sAY4$Vq-s;=qo~6|Ffh3HYY}pIR6k)-v zeFa<TnhZdrt1mJ>%vEK$+^t&a@U~w(XHp-f5jlJoltw>Bz$oVJ(fAt~HPd$u6W;WF z$>5F5&<cQYS$dp7+F$8ZIO$mXz8P?#OV44^hn&`vMjtWtaOTx^596x!-uAL~lk1=6 zhlpUkvHRW)(aFY}3xj5EiMnk?I16FQG<cx$KIquiQqO+*MF0iV?>=<QnYldz?Qcxm za)|pJdE!B<>2Aft8qzaWPw6V;H9<k*1w(PWmpxZRW?m>y#oc6qO1y);B3XjolXL+` zDT6d&FY1U-1|juavxC<}=(dSFybx51<@IK1CydH)^~fK=DPXJ@GY)`E!;%!o7f&i| ziKFGwUfxS!Rn2Z{r@5zpgE5>}8%_!sMi%Cl86?|}E2NIzY0?NPeC&?~1UWT{m6pFY z;xBv`aE}wkPl7ZpqB`U;+CqS6w!pT96XY4ZEEc@?{??^mQPZSY0|}uFY2|LAJ;@#q zKBGi;g*nd-8HY#!o9)01F}8!}>5nI=^*4PL%Sl-*YUv0nSJ5Q7e;^TlxpU5<G92*z zcYWUW)E?pLLX_EsBpRRv&MYG|xXy;4j&aiEV}~h91%@?sb=YKXH+2`zhQkwE<chm6 z%R|Dft_x0I*}Gfn&e8crR=bl3rBVzOo2WW`sTLzGd?$KE);&|18j!m9(EkN8bSMX3 zqLSmW<t&05D}nT4#}B8)W@s;7#)bOL$vnuxy(b-X3S%3=ZQI;M7Fl<YM5&&Vgcb1T z_;XVSd1*$22}9$n0P-`YK{FSi>G59l3h+zi6TnJE`K#Ap-+qon_jFE4y7}M~8Fnq? zvw3h@APzeh6|5I(SwCk4=&Kf3{-0mq2!#;J*=+xFH#gWWn2ql01|Y>2wYZflt;*>^ z6S~T@?bZ4Ls@bAA#jmW}KC@RtEDZY#&^tT*Ycu^z!aYkSa>Hv?^)SH+Bur=heI^Vy z+=+O=tZjB|Q@xp5cV&L=7+|!ey(DsYJj<jXf2;%3BLA_jj~X2RcI^IhJ68Zl_h||) z03>L>GY-j}DyaoWSMEwI>EXOm7h`B=4CEmE1OoRoP8)zuOy(*|dV3uUuXcL@y$m~c zl~G-`8k3C5=&d!(+whR@;MJ`*H+GIq6YrW-t?UZlbTAQI*^iTwJB}~_8tV7`apgWq zS7*CjrAmtRT}9O3Ii!b-Q>0sR+}X{~&$RhgEsV)WL>H$WPKj>BiiL$Tr6#YV{Nj1y z@uHeZ{m|~QfXz@DCQ=??xmB#)4~++}3<jBq<cE?hVa3E(PGm|-;2@d2+5M$utuDI% z6+Wj1!0Fa`D2D?6n-Oq;mBsOmi$!##6W@Cv=wdD5eOm`{AC25HK?|)Vm1rDVuU+aQ zdRmzJh3L1HNYas76E0G7qM`d@V9aiftxtKI(Lb3~zeUkjJdTuZm#Oe6&*ExQtZ<<n z_L&KGm1T|N=aiD%K88H=ox%%uV8H3qi~5%aL~}wI-ZMYImJcg(509>BjL_S57+KhB zUzwk=uA=B#T9gKc9Uk>S8AY0q77lN|BwyBjZJ8f3*bWy`VMj6PdPu@?9;2$0D&1B< z?9NjE-ioO(+Zb^MEbb8D5#Zb}97*%)*^+#zc1*sNuQS+&m%jILfExSR*9k_)7*^XM z%YeMd`m;Zfcqg3V!k@f^BUw+V+co0iP*RhCIpDltbhH8qz^9lMNbEBT(DClBwiQWP zq+xMIs<ru0v|6t*BI6m8$y4ix)myw-zsU(^z|22rUAw!Iw>epBKcg_SG|1hJL^BU? zO7Vnpg2t8mtn9sw!^3GGJiM~Sex6t)2O<eEL(95O0vqK1u^#r?;#=RSvO1DcJP4EE zTPPg|azK?5KIj(zGI%`u<JWfom$`G(Dj8oO%6RzFF`_`(-v%ceH@<{j?K^UG|5zb_ zBv>r?E{Bb<=x1hN<op|JD*BJLDQCWL%BmTV<=Ex}ewCWsOp!|v!Nna5VV|7Z#Fgk; zHdof2g>MB9SS)Y6Z_BB(5OvP2X0+^80kDMQl<pGzhxRbxtHmE|eH_c~Zd5^3qlIBU z#irmepKxc4+2XovJVq+7AhaaE3tX_dtfzll+f8md<ceT^MPsj796KE`QMVcefC-uL zScv(#1(Izmz3>@}F6f%#6SnCRNUq;P5_EVBP$QC3lrM#_zK{5MyRDICUXFhdqkX+F zW0@sj?VR;d5S~2h!F)%`iH}vvSD@?3w31m+oexO=?7ZMAZE~cB5>2GI-_IUw78V&F z8wD%G6H1aPTYL7))&DXnRs|+8<5H|^$FX(d*jodgyNM>(-snxd4VGxa56Yu#&AT7t zzcxm41$8mt$``9WUU_xPZ1h3VY{ky=sY@R_W$0vvusaWoQ|Yx4KU>_v(#IvjqLvT? zD(vJFZ^hG@BF?!oO;wN^5&<Y*#_-xcng-rRcvL0+sge_O69Ts<P&2E4s?9~HL*Rio z7PAM94L2WggN0!I8)*4fOPEf5`RW3V!Vo^HNwj!Fo7HOxMwk0#FGcDR*2lK`{N@R8 zjDGsMi8|iCuyS2=hEt(X$Sfu@HO58E@6}c!LtiNZj=+<fnxz6>;3NHKXLiBPt}t<l zNPCe2@(pi$peL-&h1KW7RQtKd9e$B(j`{w|cmHyRV6kw6nv*j4b*i-MBdWzNXEHG? zzv^37n@hA=UQrG({QU-L-fRZoT%wN`W^;l{ga0z@mUBNeW&~U+@?5R7(+j5U$Yk?d zoct4y+~YEze-o8hvXO7&<{qoHfN#9F_6{*{==H3gRm-ytDOgSe1W*wRhwVPDGNR{d zn0|?1r2>w>8tg~l9ZR01L@-K)d_-@MT;as;ae*w?nD4jYaR5pDW%x3ajzVY~Dc(7q zdu2^|bJE{jw=}?hF)|dAIMjaud2j$Uc$d7L{P~v{>n#UR<bK(s0&IX9Nyz$bnU2__ z?vjTO!f<qQqj?)VOFu}+_%m591@N(hd3N3O_tmhp5?UquxCSi02o5epD?7^pJ#*~Y z0P-@T`a1^f$-Ei5u$!+T;7GGl3BPWTzjNJ}`|)RiJ^@^iMkKq9WO_<c7JBRojs^^R zt5JayMXaAUc{r3N<%<yQw&S_GI(>d$KOSoi4v9X;E7_FPZlP>y71@u+P;l7sKN??M zK=NMK_vZ9tH9upxs9903F4b~NIkqJ%2-D}>qG<r@z&wYY-lU8a*^jj375pj=znK0~ zL~q&hnN+k~#3k%)-FEQ?;I=10!EB)_J7v7Emg}!7<orTG0leBI9k%&Qfs{ov<!+n1 z+oLqojxh@P%kS>C&>7K@D?#pEe>A#jU(o+!YPW0Ac~iZgn*_vI*0Ucro&Ltnsj^5N zlZJW4g<-85L7DJEt!G@0oh<Jznw_yw>+}5mqLKW^(aVwP$O78QTLFn?1WxG*TWbEZ z>8%#G#Y?7MK7mob>0}o!0(8*EauNpQlqNAvHo{l<x1$|KIx#^>hv((;XAYij!4gl% z^Xn}a3wuA0XjxchtqA#5euEvf2;v+K^;zM5BeuK!85%>f<#tSl5=;sfAnc3;YnhO^ zLDp!RG{rU-c%#TeTPMP{<zF(CfAf&Y+3H&R{`?$p3x9IXMR>&Rvh!H9)@*-Wq*K9J zBy$st`QSWpyZiZc?J3qpnLz$`pu?QUXbnC!K4_*uA?aV4lj@TN-SPzRKZCr1HS0@~ zRd+kX)Ydfb1zw=ZBbqk^wVz|_FzXwbQ4>v8-2;0sFfc;L&RmcE{%Vt5+_svQw#H$i zbBDc3YNq`$g@Oy;tM(@R>OQk_CszzQ{MW!WFXgk4IZyhAp=ms#Y`$P~(Xa0FsjN99 z5m*go$R0$u;>Xo-SO9b9a~T-wjHAt!yiwDLt&6U)E3`B>nuYhxZ{B7x-#r#)OxCM~ zq9qu&x%!=k{+4tP(^V=gkcqg^9i;FbL!N8?(R|nS5iGvSQid}1^`_6@-Lbpmt3}X^ zwAEkNq2B>CJItv*IS)1Yq7~GP`tf!;t~zP2=lj{X%R-M;NYWnGlO~}PBJ2lB*%B9! zmo*e0?O2g!I;WWpy>QXncjLz7phz+)(GkM&?(JDeRo=TfO$2=e`T`%{(T_lslYwUv zT#k}|T5ps$N@|l;GA>(GsG>U)vt74Mdd!|TAGR-4TC>((QUqiZ_Sf@%UU3@CQ)R$i zgF@>MZn{XUp$P~`H-f-ihsNMBp&Sqp?=o2Bu-_ZcZbtIQOG?X9o<B<XugId>+iAP9 zI_*s(OyduOvyL50yIo3V9!F<xpP!0*2r;c&LGVyi4oSs$W)5s-wBM^Baqi}R+^=>o z=MbYZt<codA<Jv7xza$y8-|><u0Ck$7n*%WQK*<GfZ~a@=PkoimVN+2WmAp3l{aBV zY8Gl$6$D*9%G=%|SOinW9PG1)34J#<dYyZ%*rbvCv)0peU(~v$-D5+r+eT>=;|a1* z<)U*fMpbI65E_Le@Fsrsi|+mXTa*bnAEf9g990!+>L$2do2PTW01AT&K$VnYx*c$2 zh(dh@u(#}1MZ4y2Dti+E@ne*``UPZ^m-<TWZr_eKJLji~Fwr(lG+hci8->Zc)bKa2 zFZxWjrhT;CzQPRWgAgWM8e2$cw4|)O9BYxKJYUZ{bp3Ay1#FF(b{6f<ouDEOuS(e0 zDYHa)UT;k1K83t|mi!_}ef_3zaWyPQA>X%un7BAZgyr8q$b^=rfKa*2qsJ4>E5ax! z03q~SFAX6|tx*fnwhJFuXoCm%Mcz92+U@26#KD4M^;{X=yWr>$LzZ)ju=z_wl~b?{ zw-&;*7rsiK5I&E|jpp=$R#IVJ*Z1OE&P?#jRXkpiqT>d36Qyjga!u+dJA$sl`e+dK zzyz7KLjh>Mh>f#L*7{&G;Cy^sbwJ%d{s-9Sv?0*HleIoqymwhivp22JD`1&|i3V_% zowBH3*-?~52L`_y+gEFWkxYct!PHoL%GFEjde#R#>SnWcPOZ3u(zXGRXibF44(@z% zehnb7PSWuBdYM`<A5nK$>B~Xo1(y;KcOJ8Po$z6`GAUsSw10-EaAqXpZRAn0b7UjC zD~x7^S1LWa{gwAF;kp;d=k@WTIr$LURKfgniU<-iaz-ZB&9w|B+*Oq2-LtrZb3^zZ zz7^<f?g}6_R7G1ZRg|iD972NKvZ>CjkCY?pyE|<a{Lz;F)kXmqhsIl#c?#{WmQ!Di z#MbuK;?}k5d(%X^VOG5?h~=Qbpiz*M1L}7>QyOSz4%8iT3E}P@^<AOh!d2((wi=pl z>QL3Up$<XQcUy*ul^?gdnIFzkUlCrw)+Td5Iu=Q44m`&5>3iiU(`VmoMeWJU-$FpZ zZde-2Ar-xj!Yh~LZ>t70Tp*dQVh*4$Dgs1~7qPEx`vLel&>FBn>%`xQ8NUIMKdesP zpU{e-oR9mh$Jln!;n&S0?~9slE*`o@dS=f99JZ(IG`8fpJzvbuBY_?eNDF}IFPoHW zDTV0O03s<DC@20_q~DDP;#Fxy5O%A5k=udV-V?9>r3~D1hzES>j>eGpop$bo{1Dgr z{0XpR+W}~sfoTN8)A^g=fI}6`CLK|*g*BY~{RMA%@0<9sm_wL%qRY%2+lsfQ5DMS+ zbcrl->Bay2w^5u^8sb+3g6NzV!8c4Sqdw%<+N2!Y50L&zZ|2UEiN}VUFBbytLmZIu zNk;1%7F27U04!T~=y;ekvUtaTvhLev+Cir({QdPm3S1+fW+0gti*{-tdE%C5kmtsc zjhq6qOhNDa&m$<V+Q=dBdSEROg+r@@;F=K>XzWS#Do>1b8+;6ycKRy=Zs{hs1|JA- z%)a0F(r|9p&tm03Z|+c^7FTW4<mB805i=^lkvYwJxd}Ehc$0o)YGy-#zJ`p7a4=jY zYy6jT<d-5h3u;l0a@0R3Jbpe>{^_|sKInbS=~s0-N_Hs#MaqE|_!Vb&ImfFHO4E|S zH|<f0ekQ%|EeteYe$UD8#B>Y(=hN!nsK2mfEaN!6(YQO)^u5jXfUHe;HfSaf1eg~J ztHnnS3duHC_0JMLcSLTa=mM(W@PQ+M-dwH$=DpO=|GMLiyD~!kf0qgfVrMS;rzzQz zP#3fO7U}5=v}B&R`R7JyB+tEM|3J7__IV#a5q$xvXahL!-lxU4DT{x3Lqd4>tcxX& zd%B`aqTmg^Y2Y8QGozSNn-~8j7<%?YtpgiK&`)TD%D1KoFs930ZVCDU_M=I(>_YB* zYkrN{OThB)u%?F!@F4eYE75LuL>|ffSudUwd*}}Qe?>CkAI5LY0jgcp;m7wT{$UQi z?ccPrj0FPl7cPEU{y)K=^na+G)^aWuZtDWf9sm8U|H~KTzgGYMP449K*H%ejF$@f8 zF&(D^b{I_)zZwSrCd%FV^vtL0<(|C&fF>hMf4Khsya)hh{9j#EXNW225cHz8WUxXY zsKBuL^)HL=|C3h#<9VyTsl}h11*v2!+&w7Je$541IrB<HFVVg6w{Oya1_0Rh*~Tea zqNj}@-!ZY7vl(Bi&35_yV(<P}L=4AL4U_42-lN`uWp#TR+GqBrQ?{(r|LZ{>t&W{) zi+L^z`rDn^h5<};eRp;J8i?~>y0ODPUe6kik~-f3>eIOYl0yOi*3lKa%XGi6E<k{} zY!4tj*^VC1E{MK;;24UNS>OqXZoR}~s=qsvt7EygEES^E&Ub_Nc$}YB@Mh8dH%eBd zagmh&`Ax#%2z2cBx#>IA>Azwp)`3BS2dtftYBl53RHxXB^$!4*hOk(Of+#kn&YgJ; zM*}7YFb9`w#sWLtqe#+DiOJ}ktaImUNYtv2t^1o_i$*7hj!}(qBtitPW6YcauG?DM zr$2xBR|Dboj~j7s+?PtmYniFpeclAFT~<GVjE7W(f2ZP{YS?wVQ~?(xDqk)U(dquB za2%i*vjJ<p;Z~|EPUOLbQMd3ysf(I}?jpDfx4h0y$a(gam`ZFNfiE`>ACprHwSTi- zz(ZNW3Pn(Y_--8s=l}~^=)};)fs?tKP=bnnJ3m+ZsJ@&-|K_3xzmba9hFl+R32voU zH2R)xwgh~r*q?ca_Sm2LC24;$@w=1)MyH%w%zJiCu(ZH$(~!6StT&)(HRvc;X2+2{ z5Zl<dahV;2JH~6`I2R}9WC;(Z46d%9#r*t{6BOl3mFSGRSkp??Q)EDAe&E8tg)YL< zlr>3IZAi^%K*7?c8V{A&>1lje((thtEy}x-`KTnVj-4EOo8)_*oT^t8TG5@%E4-&q z8XK-3@@Ib|Gu01qi%9HFNKe@!qeS%g9`5?{|2os|E-d=DTe!LRk!r7gSvdhSAvoNU z=ZeY)&A)S!hTKA0sXO#P)`{?4RIlMH$Ebfa)p{w{T$Dos=I&P?eI+ZrWw^%IMTzq} zMAm|0y;Rt*SNk2gh`(}@L#_J<aU9jZEK?*3eLid{bSC)BgO6}yuH=+RU{X{vu3|4P zM;%Il&Kj<^h;%H$W*<f)lej;qzD1utPg10h&KmW^15QFpgz2EY(_YI$YmabZ=B?tk z8012wsh`Yq(0D(J-y7HkI8R2W6irG|{P<SUnk^|gu<Y!@Sa2{p$4%0Ktm}-v*-@XH zDX=Jqz>3gR*;%+gd<P<fxO*_@GXxALu+X!m>vRd61BmTHV+A->Xux?Uo2UpBNbLoA zXJ%-_xGNL(TQiqy^Q(l|axM60w317nUl=`lDSIQPEudlx2vTjT>V0r`<l`ELrHT_u zk-&=6bYH@VZ0(cw5w{`Y_5)mFTv>nFln$Q(YC|~;DDkrG%GLp;lb6CAuVOn9%4iGg zT=H2Z_j`P*uBnUUCvmToET51ULv*!bEKN%{LM-D;6k)rnI;h)ljE-X}Vved15$|WD z>vrME1X5k@18eN75NW#wp<D~jAh2PMRv^B++u%jvn&`gFg>$Rnd&`CTN{(6jN{YK_ za-ZCD+SC|!Mc*ui@NjUwVNLm3LWz@*CMBf7U1nDmaTBYRb$!#Z8v6{&FPo*#Q(5TE zD~)!L(<5n6pB#|NC1(e_7tBi|U)_;S?Mj<aL{Y-jO-jm6xQ?|$@Eu98DKtuu2$I*5 z6<t(d*>hh%{axcM{2rI^Pvd{!JXsgj6cy&#=8eiYg(<v5T+f?o-9;z6b&loePsJV; z@_bPKJU<F^#}g&H$iaPR5>ohvFd5CM8+0%w(F-=4Xh-kRGJ~gd>Ndc-U3{batHW#G z8Ue$S&MLzgT8z_p0e}ogmvi3($c~tNZtaa6DkH`pZo$7QT$Os}Sp6V1CtpFQmwLXb zZw%Gm7s96Nch}jUG0HF95Jtnj3u}bymI`l-02^#G5l@(LN?kCyKEQHY!tAP~gq*7- zI8MNT>6!S8?EHkGn{b4o0r%?oQ2PWZ^$}s7P8MHsXdE^ZLsoi%y$I&j-($_sOHo<I z!eIh%UcxL21Nw*WSW5PPiiQE|i`PZ}^Do(GYi;CRqra(^<sra)7uMBXpQP^8yd|ch zi~iaaHCG-_R$4^mU7h3#JMsR0L@;n&DZ!j<BM~Uv{Ks~d!)cjEyE`%bqW$!<+QKW_ zXA;b3hz)^PBBavK$si3<yb~81*Uz(G`EN+YQ|&V?WUn~!V0Mj;M+*)<CTQ_RmQ0l7 zbwcq`mt^Oy#+L`HE<w>zQzk`FzgZ37P7LQj`5)?Mf`V7@)pz(Jsq~j?p!J0o0r;7h z%<>gCVT2c;f=#90#vL&0(7F^#Ok_i|rz>^T@~^euhU_0Z`TP9Tn2vhrg}8U4D`}&N zhd)~}c-N(ONSgRe00rfO`3#yYCbhq*Mk4yhm_0mp%yXDhY6;};Pxk<sL`#&!+c^FM zfAq<3Zo(X%mCKkQuyL3+2FV^pe=^p?Ly*OP1s^bH@oaRzlU&F+CokjL5D#@5{}!lg zGy4yZRT_bUJ%bwgLRG&svylk7FC*MC=E6Lpja`0>TkIcj`~rM<eaxjb%00|_jiF^4 z*dgoNs=A#k%_@4K3DyZ=V2#+%q(1KCZP)HtanbEW_S68<W*Q6F7(k??t(<)~w*uwH zFl)iV+FV*zXARp>bPw}SNUK<Yl%Isq1~}ZjOSQe@bk;)7#3Cztg0=?Og^d6X`u(Vy z^;5qq+x_^F3HmtCYivWhUi5m+${vl^A;2ZWNJp(e8>D!jfKX$<UJNY{5DO{idUgX~ z`~S_<OLzx%m;sM0?kr;|0`O+~z;W<e>=&fG!N@J+X&UqeCLX{F*HHD04pobNFLA;@ zs_Uc)baEkO{SQQid@i#0IfoSiIQS+$R^(ev_0MfY4ngr>iGLK)b6vaF&A!)SgWq%N z0X0sG16hHm!G4V9J(CqKgl3TJ7n*CMmyQIWwOI6*)gJYQ-_#eaL|h1o%H&d``>h|{ zDw7bEU07OZl%(`V(y=vWZAEco;c^fR^^ZdJcC1pgHmipQOoy{XY0VG8rF}|TZa?q+ z>gx5f^aY6L8G<gAzR|P#6BneP2b4q?#{q>4<440`l5;<wDW)GyG$n@b>-0D4V8a;V zgjldcF0&nDQ7BUTBj*-tC*$0lm6?_)YY`Y;gHGC6zLz;JT0{`Mndj1&8lMaP^I#Z} zPDbULrha_8cI;6f5GSC86eX!2_z_unFNEmA`w2q@8alMNw7~-g^0?)|_^)50qFYDa zXi0x2)K~MCG=R_bZ(Of%KA@3#RDD1v=jvMNj!;wR>3|emx#WqBh98$|rTq_Jx*~(C znH)*3*^F8V-4_tSkVSc?{kxp|(%F^}u|NNjfplYvkH&1D`isHXKF0KV?(h)kct!+h zt+s!&QePSUt|1XEdRO)RtynO5#@zUz85H{m{lErEdbLu|k{WOg4;-^bVwyirPSv#a z4)NiinuT3WR_yx|molamjd&rMhr5k(O)lml5hGLyCrpPWpQ?@YMryY#AM&^~H#DJr z`BM#9NGGq~f8evjoj|cu6T(a+!no*ffGG1k&T!*&{7IxCQj&L#l>@gQQ{v6nGQ1uU zFlJS>oUeI2gM|~JPxR{rzTVWcAs@xf2$$+4(ELVV_Rs-PzdLAGcY}tAMp-AnzY1vy z*X(J<<jmc0Mfy}|?%PdHLlVr81P?vvB%BxRNoDriSXlmy=>WBFKv!+0eg{VsVK+lu z*(Bfk6V3HeIxx2S0xLU9B+>k}9-I<ezX30JY3;ps@y|3ZN5Z{s=GMjHw4qcXHSJQ} zhsOB2YqflPxb?2}6X$b@t<Sz=psN5-mfK2KiUW^p`+vH(Vb``FGtfJNC_2N~g>#TM z=EMh|m~O>jECydj_Cr8({E!%ZBYXmuPX~88<?e>VxHJ!lE7yw~9OY_}BX<gktNw%E zjHKAst=`veKKCBHK3^zhrn@xU@AA+IfCv&h51QF69gyq1CTZc}508~HKBY4#1m^z~ zS>j!>JR1nKRV^*5+3nsNtUqwlYjbtru;^7xhEl-!cL9SSUGp}Fz1Y|bBQTyM0XVKi zB>Y;v;hIEqw;5@_nRVzY`DWSEiiMch4bK{?YM^7;kP|LYN$9NBL<cJqc>t(&YrKL; ztE;ZMynT-d4JbU|SWN!Mkd!A*3xE}hf-La)2#{b8GJKgez;X7?z4i)=erHo0@SRuF zifqN)<`Z=8G$_X>Cmue#Gj;81bWn-V4Q1lf4&Bv@w%km9#J3QH{icn}qyXR>_`}Gd z$90ABj{G_lD99(DR;xEq?f&joX<M@|7aUJJ&m@&Rzmz3qTD;+ck8fbKJ>};qP#=9A zWP9DdD3*EbxU76_UB`UFvgIZFjr24s)2GP)y}mg<fn?kuft9;oe_L>o-Fc8cnEWw+ zR!;wogLw};%OOAXLkcY9D}PY}f(ic%i5PQWY4S?jIg;HgJh9ld$t>3gC}(0rk_Xcq z&9iU2C7U;}Y3~f?B2;TCc<X+hAe$WjXdN9>@`fCaxS&X@J=k4o1irK<ieYKjFO;9Y z8Jhyofmdz7GHEHL5cW4@+?bW7vho1vmSX*L7@|-qSZa|ht~(=T+BhwZ;;`18#?{#G z2;Al6s&NNzg0>uViHV)?DAAV6ujJX^UhbLwj*7iVzKn!;AF7p<0Gp8C)if3X{Jt%I z$-NC>A&jgY+-vCCZcU(zkuPqPgd4X5sMGWGREw}xa>nxA44hhy9t+y5ztxS3(H3BN z`18cCX991}W&XGqas{QjQu{0(=yZ`m?6(o%4+QN84|rNc!Q7hjics+P`A4bV^cN*~ zDNRv8BfQ5`fS>G{BNxi39wl_cbOw;^5@Wq9+3F6P;$_ObPvH9kG9~y<pZ2n^5n5R$ z6YJ_NLlzCQy+94xpA{tQ{Iz>8#=&Qx%24QtpXMgdqGt4N@?z}5m*vin^x&|bzSMo5 zY>X55l4j#wXSaSaen&Dr05>n+7$r{eMR&L7&y5*HH|{$fa_hd!M=6Gu1jW#K$Rb~l zm*;Rk1ihWJp@D1-)mYL<)u4#G_`3y4C=o`@Y4rwrfo#)p6DK%UWl<`8+{im2xaPsM zm@?TNrA+?z17*N<3w&-}Sqay<dZk+AESy0cLv=oYo@|;Pn~vx#zw?dzaHH_I)ziHs z;r*Dp9A1`8hXhbyv^@VhANUo;UE2N*tZ+9?#j*P9Y#&dovmK)-7f!YQGd#ieZ|O$y zWpd@B#B5XWL7{KT!*8El)B%0QY-qeJwsO#qLR-j=NNF~_z9;lX)2EUAo#MiRip-20 zTG{vVob3#mh?VPQ7cIQNbSGskv+#(WYUz8{lYh*a=0sV34H^}9UZq>-PdN%mPhFA- zO~7H8fe^iW%iAg~VI%*#)#5BR3UE(<nl=dXK;uC($NBv!c!P1Mcc}gUW9`4An%bT} zU>GY(y()rq=}Hj<=_M*69i(@V8hQ)8MMXjBNUx!a5Q=m{RZ%*GUIR!==tyrNc@L=f z-tT>X?^^GA)^q;AB%ZU+?3vlK_spLCnFxBjs=d7e0FHCVjL-DLwr)e1x#S9C=ZaG* zBrPl&nx?bcL5vf^WvF%oZVKfTWF7_0hv4mGAh=bN<|g*F!<$g#l(!}Fo#AWHA?Ew9 zlOGwzh!}85iK|CQN*YM^@ejFE7QKoB5jv!CM1IC1zFuFPX+O<Sz2cO2*ber<rS6%v zte`Cr(e#w>hc}p&f%K@))6%m;DxJ9ldoeCYqRNU_N7YcT;jthp1wCq#r=h=nh-a*R z0i}4}&NX-K%m<^sxst=;JKJk`huni%Wpayp+KRvkr`v09qe<#dCL&Tc9B_qQ-gjIX zfZ{7l(<s6MUGOM?StYQsA33@Vpeh!Eeqd{@HECauih@Rgec!#9n(YXaM<#hULzZhy z=Y?h@w!oLO;lDxOnt4qaRy<lxGuFXPV>f%EJ-30W*l{w+J3VA{4y*SL5_KoC7mE-z z%D8dNN-lEa@`L&()zkR5!kKYNAo2tF_wO9C71*mqj&MIhbrlXZkJJgws!(IDMCI_8 z)R$cs7KD2fkHPaPd@r#{UlwhD#Y;c`>@>oray0S8?of8Xi0S(#oPUl1*7)l-P+c_8 zyF5h*c<0y-@5TkK;*necP*60kp9d7?u;7JzZuV5{2lxArypT5)dDJbC$+p+4AuAQS zqZ1Am-OqInw=oeDZ6$uki<cFADbN+KAVkbiE52H~UoitdtSbh&S#@jkSv3=YwT65n z=A;P&`Px8|Unc^1nh<Hg!t71+<?U22G!1oh!3g<B?A=353BRt?ZDEk;)%v)A-Y~2v zZl}4eg=h#wD1P^_AqE8Qx_d_lhvh9dVUx^>{GyxK8rdau?-(h08Vbq)Kps}V3UG!5 zSU&22@yI%gk^oIn635RSLV7x;faw3B`pm;77%Z<r>&{AqM0jc3&e)3-HJ$5^$hqGh zLX=$>ki5xjed!&~`BF<8$F95MFPs(AAx=5N2?XMz6fD*FAi?a5wa;*L?XP9EarVFp z!sb%-`qbrqoxLZvIi0e-63|a#z(KJ3X?yh!>!w}BT!&NQ2ncq66<WJ<q<lYX8_bo) ze0j;b{U&gr<XU()>_*_p%bi!-6(ZHV3%j_V>I13I!~&ivF8B56tcRuy-`%`dq0%ab z)sARhNE(p4QLK)Wxa;4d_dCXz@e5ZT=(z^#JTggHOg(1V5CHr-g3Cp6=`l&w-*KNu zBj2%@2S|V!<nVG9l{QJTN~_n5_+O>#$oPvKZfgn6SpC8Id3?529UGA-5Wa&Q>xg?8 z1Il|x_?4Op059peVnz5~>N>JP(gt~lgn99v3Pk_FZkg<GyYo-HbN*MDpZ>nEoT_8W zd$wL(>)puF!Ro8&_m2a&FiyV<<Gr}{tAOdL)6q~1>4<%3ZaSP$@|m_cMRVhX3cxP- zboIs`Xud1IP?S!+f8$BfcgW5Qt_t>-Up+9!Ve2xd{}Vv{+l~28B=rBrdHny4pmi3r z&Yv((PTo0N7=OI@zZ(WVG*<wmwY(uA0AefFGl*4b@#&cOYYa&QxBpQiv$^qP-Q(Op z9rz6cC9|Hw+?JTVxwWHLR71qS2<%;7D!b@&`)*!%>*~7!=68;>sXs#4E`N>g!(gx{ zGuit$n+~XhQ{qKAFqtg8Dl2Z>|Aj^ZN^j+-Mu{>(JxsPB%X$Nf3}vrUEM9U0=*01a zTgoc{3N6I89mZm!&1%{+s@^J%>4G)HJa+oeeu~9>%G0IoRO*47Jf7SR>8Vco901^= zj7Be-_N`^kiG1AWO&jlcBK0vZYgnQ{Uc;0OF7+etT_8O@8k39MWDVf!pEiH~sNOXB zKbuku*QY5IV1%7XkjtG@73_nciC4Pk({6F^=MD-{b;AUtbQN)Qhe!Nn3(xhFu%eqX zn!iIE1OSZYX~Z6Yo4!aC6U>b91M-6kvfTg-nKA>*b8u_r&S1=&?D0#tq3e-rtPXmf z<nu_<|H!;7$tm_a=C%T`64i;5(n$pIK4<H-IsExh9Y;s~ZjJrOtfYeb5iq5QbO4ya z@2jHYdG>*We}qL6vzWIb|KX9}@(N8?%3LI+5)u~7AgL>JAW`}iJ4RV}eQ^~){>4s6 z976n9t#$z%NRA-n@Lebauo?p(V^fl{V=}Ra0kmNmH(F2rGiI*_1e4^p-!)@`$QZ#e z@GVEZD1{8-ArNM%DO$jvz6wX{f0wXBw`%1GBk@JNK*03tYvp5MBmDFVI2=4;0v*{s z%N-_I*7EJ2=u*==5HHom8F~YxjRT}*^bc1&7ws1Ywwh8UIr!{>ji5D1tL5a4y90P? zNg?1-ZY7Tihw9pDpsG}gQ{!Q+!X({rK<>K6#TWIqs;AIfUC_DyBPY#~?J+Hvt;)}_ z4><t5nch=_LJbJ*wy!El{G8y>S+6AbB0TG}*Leu;tiIz&KTyj}zhc*<zJK@pL&q~w z4zYh$Yd?fI^<z4=!3NJ5c&Nz31BGY?`12O@IHd))F^xIFmwQ4R`a{z0o{qJLkqz5v z8->2a1Vp|^OL>gNg9D~(I?GZr1Z_oUaj#_(5$^lYy;)4nPAdgk^F(q0wxwAY%{Emb z%1~^j1OW>PK+_X&V~w!_G;Q~J_|H@;qg80azWl7m7#I|nuOP|zyT_<MY2#^OfaRln z3!r3vO1+hJ50I;wYFyjgrMZbSe89z0o@!LtSw9yNOaeZr^9EO%<R4R<yIuVUbhjLU zsnz3C$N)I}qQ!TlZc1yPl7M0_4|KAm6L+McdmLA*dX2#KAJF`g_0&rl7f;ItTh{{! z0<~wY$LSa!D(4zs{U0u#X3Q-Qr47KQDo#cJP^N0kD&?#@Q0yFIQ^_Fc>v+kae+WU; zukiC9d|KdMHzz>WMW_5c9%;hu<|&+T6`m+e=3OB`{7;3b(`NUpCLHU2HH$x<E{~z} z7&U!Y;_0_P{l7B!V{U<GYGrXGVNdXfNGR_8yz|{7?Fs1rHz^8}3<HDn-WkchrxgSr zs?8%m%k7NYm7EB+&ori%5E>KzPj4kjUvnT62W(RSJnRnfmwE$SB8F#X)+}@31j}|y zm#>TexCC?{E>7^A_2Z9{9fF`qC_u2zd%E?ufcvve|4S{fTdEv&A1HKfeUvHz|3u_? zT_J-?#eZgJh~6KUYO@4EFGxL`WxfCe4(tF;Ol+9JURQ0B1-(s5n4=+kJ$(cd2uM19 zSYnOaFe{NY#u|C~dw!E)XT|Xx#N|{6Bn8B_<y&^uv+N`4#9dlJ#Kk~1=qEV(l&ldv zZolazg{;VIlk#@cr#&ur7&F1V_F3i}|CTZUgy>TS>|p|yafg4&49KRr^U_#kC<P?D zHTC`wqFC+16s@{TC6WIaNCT`>90`<RW*!0bN%tMx9i=+kD&Y93O`TeR_yjRXbv#&K zybiE8NJkKwOUPG$8Sfx9c}<=lT`glbgzoxZRprb@LadZ@%21-Z49Uj8p0xb#N8OLC zLGken#8mHV<XB6&lR<U0ZzGOl)(>BzOgA3t+#LDha$~L+D~tS#wIy0Zu?tqNF?KsU zLMasH3xj@J6%-&F*Xd(?wEe!=bi9F-;GwzZo{kSe^Bn-eP_}n025^tUe!<zDP7fh5 zga%@&fQiN=$I1%sUuEkhMgZ9WJgJmGLdJk`SJbV&y_@ouv?(B@;<#xaR`iY@avS_= zpWeM*D+s9WT~B)XpqZ4Q*DdZOj^Q)kaw4einp<lUV3M9zosCCe7D%0)&wL=tqVI78 z(ToO;Rjg`fUi2{qupL%EL^P)Y4R^5SS>iN)?7dwSV`E4M%(=(?P+-lpJM->?s3M#3 zkOW~7D^#WK%@Mrj69K`FdfX{v4S^88@x?SS4FEI|{mUeUphj}Pd4JmR#%+jUkUSU` zHcb!sv-1snojtI*>}Q&Zlq9v@PDxlqC=VOuzSTy##nviN)4NqR6Us`6J&`?P0Af&^ z*T$66W8CqmHkBg4RcAv=rq_B(+#?|9ezst;bdDq;^$-$p+P_a{{oBefvEy^{7(g2q z31V4m-7Xp}Og_H4^BCTO^)^PQrXm@+^)u51pv8RNdq5g1olORi2)fEJ?*G~hda(N= zL^-r*?li1^Tju*|uegC#%k##wmfuG^y-g6xYY$0ixKe9R@Vi|uap<}lKAe9SxxUCu z-7^5q9-ki*0P;9c=H7Y0j0b*Fw%N@JbR%Nyohreq*RvxhU>Di(CLR#aCjcY$#o-@A zYdVQR4oSTFG)o(FeesP34**pt7r%-()HEBVRn-V?!XbbOHZ=`cC=7_%Jc(C;kEvh< zUSr756GUYlHT7Rulmu3-iN8SFHGfQ~O&N~Cp^myZrK>w%^Wy;k$Jca#XL#Wp0Q`L8 z0<z+wm&h?NAA<-1hZ_xmIrj*^Kb@*=iUiK|C@2oacPiUmfD6680Dt-Z<N#G?$6~#Y zNPy*-eJy}9TY8Gop7`~=P2x7@_LLh->&sED%^wfU;W9G%@;jbl8r47o<K0al;Re0a zeFrFz3DK8->Cq&>)Hw4p_IofBl&mrP_K8aU8^GEpreot69!3I-*w21vvm`JiRQk6t zdYgN6rzpBu%SxE*mp9Vm($lDCz<NVe3cZj>33Af{V6&Gz3$YuKMp+W*g_`pK-f|#3 z8FLsIZF3<BGFzmEVxjaQd)`u{`ye)A12I2IOz?1HcOEcBKBu_^=wHQeQx2^Z+hN(^ zSzK*r$s?I&&Zf_taH*6P9$gFo#_$|%r_=NKd1O2V7TpDt+!RHd)K-AluEQRS0Mp|9 zYVCmta5k)1=aglq7`MM!*3o?a*SbXPqmZ9U7tBtSmtgVn+G#QPO1$vq4Z!qgytT!P z5fR*4Vm4J-SOI-{_z_!1@bSs7d#DiWP=BC>&sQ|oOk~dyu+Rh58{$kT3F1CVp2Fwu zF^`;-@B*#eGA%e+xkK<ghXvY`z14X><9hQAOhk<%(~$9eEq?bBa0`o4C6xXWL73Y- z(pxh?j{s1vEld#i<5S3#7ijoiNjAZYXaGMivV)iSg+dhQ%tOhr`ER@PNT7Rwz><HH z-3Hq}qZp{{nuI;PBHL2&_xmnE`v?g%nJ`TU`}!k*_jxjsMyHcKFLSw9%@fM{9^{z@ z!ZiJG$FH2iEIv)dLScjiJNh@67uUBiSn(2Z(c-7=p(M9~1Z_E1==weAJ-7T7+z1tL za~Pi}o}ZlH7DJ_MuhBg6&7PsBt6}(iD(Z(SGWgS*nW6W5qW`|x8~6SyaKLf*X)ln0 zpH)}%r{$){(6%TLFs$khps9b8-O~g<PY|RLeho+;LWKGc|0epG91djL1_SctCr_Zt zllY_a0N<{$<4pw50jC0suK+n=s7bOFl?b@n7W0KWoESzCfHI&bRKr^PO^pE6&tJEn zR0j}z{+WqG%qSRJ5WIPYN7Z2wy$id8f5f<TQp8BW=Vwa-!}Q`sVW(XRc!P^#`fry+ zal=6WrFMgm5a7rfglHYHK3_w_#>@XAH3SzeheH|R3>Ve^){ZT#I|Tusge^G?;}!=( z-Ywg%jhVBJt#2dPTAYo1vV|$$1_-VHqir$Ur`lj__xL~}ZvyMBvi@JuCA7mJ1;-{P zK(F||Y95cM5qy>#amS@<Ot!lSayD_FqWlAS8~}$t<p2MxS<UevS^P(AYkhbmf={aa z#O%1}z>oaQ+oZfaggfm(e>4cAc4&F-**jB3H<r0%-}DgKUgHB)0KC}f%>T`}`d@t& zw5pH3QY$(maMsYW)_=#5Fq)Kk@#z~Rut^1U2Dpq?+yTNHG<^G4WO~DiV84Qxz<*@q zfMNbsdpRSa8MHU0emn5M+D)Fc9Y!m%jI%m>91ybw3-k|wHo(N&|1W<5KzpWLUypr= zf$GmCoK<Q8-plgWAtV}mm=`0wCKc)ktzo+Ffk|6@5?S*dzxIPoPGZwbs6<tapPWKe zsUH(~sa|s4SZrexb%VqXIVVg0i|~ik07B+_5P5C^X&e9c8tZ+i%3H_gb44HCXg4mr zExbV5<C(BSc0;TUdnrrrlP9yhsq6ZHf_P*bM+p7dDGxx}kyr$vd!*GBRa02RXO-() z7?ubT=JfsA5q3dTw@6TVxWV;!RdLN(b_he6E{<-J?bo|sVB286sUX5b%e6;V(P;o+ zK{e}>Z|jvy6t_9(%y6qcdaeq%R4?W=ME+10uuZ-5s|GNzmVbyd1QIc$WdMi1`6M!} z@Bu2TMoIN8pwC{jw6zSId$b7Q=<Hb0fTe+^FokW*IMn&KoWeBck!)L-oV?-O56#{h z)6Z7LcUG*+Xcc{Y%VN9$AngnmL{U>Xor}XA=AHo^ao3Msd&oF6a_7abYJmi`PjH5S zp~-<Pr&M|MuYC7qq#Bd=0Z!L)nc8g=*OW)7)nG*_OTo$;oKUjRCzBKpf3xX(G)R~o z>LER~xUxwee<h=H0h##}nLpC3nhBhbq5zPI2A5g3UOHpmf4hUII|7USd2o^m>ZpJ- zd_b!l3h&%tZA@A$eZ}M6<uEW6u~X6JVicqApOXfyJQ4mKaUpoI9tBEhgK@3Z8uHPS zsxkuD{p-hTf@1S6OYYr$l5S)f<^ufJ7nhHJnfp`D0K@@L5HBT~Q4-0ntl(FBM%@Nh zF_$Udz7>~x#TRh1AN2KC$QqD0`)#PB5^h!JeqCwFzFkSV%M|*C)@lv}N9VMON~cJV z=?h?SxiPgAY*G)XkRr^3p0gWv_jfsyQwE}d!c3sY>ic0o2X++}GH)&*`#y_IUC0S- z<!NDLUPQ{*@040d8GL0SYCu}~mrM$e|7Jd=>pYTv8@$ufW^MOq_w3LffV(WX1>VBc zhP}4-WL^Dr<b=Sw02sD=i6u&=-()AJyS`?0X;1`9zw_Ywtp;uX8sQv^O^@)W4%z9o zcnN3>{Oj}ovoFzj^7B#KiA0u;77#aAOH+r_PfljGL`3|;xA|_Le!4FrA}T8U&+nqY zf0vNpRkCyhyIJ2B-~)bA=Y48p?`G-B`_$gl&GLz*xs!#ZloZkLR=rZ=v^xtX`2L#2 za8=y<Hnix#7sRTPF==$gO|5pBn5cSTN*UU;{oag2W&FAvoehJm064;4oUcikw}oax zPe*Ch9OL?c?V--~#F3H|a;GlU($C11{cZp;D4&ZRJiVJMjNwJET_q8L;Pzack6l(S zi;wZmB3)j8`QT!3+2Hn=Nc<NWe&;Ds{<p)KS2N@p3~6jGyyBs3;qlq3?p(a|h9MKP zAvs2G*}lFy&u+k4$jUuzf?FhNZa;8J38I9#!g)42Z7cGV?O1=(wOl%4j!nG5B&!$A zH_znT=k0nS^xclq(QQ*U)0euEsZOmJ8Q;&0VG+i3u=6Tq^sDFkM5VqnvkX1Qx&<_e zrVFdW*A%J(Q#?#RnM<B$CBK-X&82`GrVV<!^TTiV3r*(z^Gar42=9i_`Y%b0hrZ(( zddS&*-$I;#{sCkXV+6A&mmM{Y>Hk4q?@z;Wefi<l5Q>}TvX_bS-}Bz?kVmpbQTso= z(yzTE`iUGmwC(k|+^jU(uhP7dd($zK$-}0yKTtdz!?+@~kgn>y@Aom2Y3`$O-R-Lk z2-d}~q=bH-%PDPmhc2LUX~(;Itsp8<hO|EKgT>^Pj0y+71;&3;%_8a_T%Kg_u$uSO z^m$~>nkuL`aCc5chxFR<#MP8*(Ht$i?g28EJJDr<2DF@4=Re^8BH7d;ASdL1jmkAR zvFChv;d_TDyy%DNjlAzpMA?Q6Ogsznf4Njj@>aZ4{<eWwz9*y3Nrl10u|9|2KC*i< zn;0u=mJ@Cn9h0~WSNihY+gOh+?q~3b&NrF)`&Fwtq`Fs%;tSd*=Bm7=<5H?LDZ6h* z-p+LGy2bhZ;`Eh|fnRb$I>qImz_K4)qFev~pJ}h{e%kh3t;w0$bvC{%yFu>w*3i!< za@0F)a_-frTeiS%dLFj~1IPQn*hp9#SR_$#q?hMzs7#jj*gTHS|EfUDZ!HQ=Sg5>+ zpl=?FbP3>+d(|2GDjmk2oj*AQZ(ev>^3GX&D=d4xkWU3{^ChzBS=YX!au9W4Cm!c` z-ByKyDAlLP)!cCHo<C3*vn%uwMf>abw`A^+nVdHYB0CD$`$|RRCMlgKN!!j<uJfb> ziA<^9NS91pO32KB5@^uyM*bfo_G}oQj#!ZgqJIxpf&2dqS50qcOI}@7Gh0h@H(m{Q zGq=<4@(!k8OI{rt3t%AM7v<;Um9w+~Tf5!9&nLpi``E?}^32jz+R4G$$<fl$?Y79@ zW1jzX%oF_|gPvE~$==CT!`al_lJ|+FhmE<Vy6j`3f185Uw5x`63nzG(*Yr{OxNW7D zLCMF;D%%OD0n)apsA}A22%f&#2>E#bDtk2QDnh#L(e10k@-@<Ox91yQzW!_dFGot< z=VJ@H&++Bcra?(*Nt1e%qojxR$MviH+g$=kiS1QKwB+;&nXem(v>F91!SmaTOttTd zi|@gQ#>d9SrlzKbhpkF=yR6FFEo^OUY;0|9?d|QYtv_;*T$ZL+QylzlQh|S74BRM5 zF`nk0iuWKOx$y+g-GPaSAj|i2w6*1@2`42bt%sncVhiAKctHW@JEAPQe;!Ru_nO=} zvf8YwxbQsj$6r`fU*8u(P)av?cz76%w#x3ib#`Fx*8@R!jfEQ;_3C-n2yT&mybPS; zuT~6%t*opd$eEq?DgJ4dgy`3e{`$a;cTUO^50l6P9PRB3;qbsevlejot>UwnyNEhw zUrgtyp^|nkBM@nD{)z0Lr#1TtQC23!{+^M5n?E~$U->X19J;K#Sv592jbF-xp>drj zqK+t$^~#SKFsfU#F;`wVW$hq=M->%A`>Y?_A{iPQ`uTf7dP-gM%`-lAy!62xVqgJB zHXu;bj~|thQb&s))v{|qt>Lt-JlA9@K4wsxOG7!&{S?f>C8^>Hl^WIb^seI1Ht<f{ zA>cFItX<me&Z4_B#dCakXlY^L%=<Kgu3a3w-UKjPTmC|3Fi!LQ4?F8aa7_ERW6b#Y zct{A*!Jl~$kl9Sgh;oS&<<ei0c<grMbyd)bo3Sy&epY>bD)Q@>6Y5*H+Bg<|82_Zs zJi%hW<<L!u6%ibq&w^4iN?Dicegn2ANJ#|+1yOZZanxrto&I@VGwVJ8*J8k#jS1X% zbuye&tRfnfu4VB+FQ}|~_TcBs?)@oWUZ>2?&Q1j0RWUgw<&+ESyI%qc5mbhkq^Jn@ zUm3JDpmCv3=$?CNyr-1QiL=)1-9qy4@MJ-y+?Of-Ba!sOmV^@oo>Qyb)0b;KIueZD z-O7%Xq5-HsNjMe|@#2Aj19f`+L>}nGkO!kVf0p*r;Pifa5M_}G?+w{X(B<at9bC4k z)Ee%r&P8kP=PpKAHT%()c`VSv-E?YA))?$6^2Q6yZ!W0Bg<tU<rt@jMd2Cy$5`y`< zAg{KT91-X$=D1Y~324;ZTd3h`{a{IIy`f_+mwMa(AR`beL=(QdyE`<*@jhM!GiBJ* z3V54;uG9}Cxwehq!TR7PU34{j9M_Vbj4Tn?cc}w?r|*(ez8eiLE-ol&N=k}sIE|p| zyqqJ`M%Ky631S2VJ$!}%^v17;RO(^!J`#{!MI#GKQXZebN8Cr-gH*zFqRXXDJVTzJ zVqIZ(_41jM7V6>(XP5U*axL@Tuq_kjmyxfDH3YLy5;n;-zB6aB4bE9sH97)QamZw2 zddL+T0-(r*Q2%^X@}k|uVSwdgA95LosI06U0WpT83EB<!=g@uoeYWhhKO{OqPciY@ z;u=nk8!%uW;xH_XWc_<vG)rLM$kx4NWcil{^s;j&0))^C2neW;K;Q8E**MOY+@jOT z*1vU!^qjSma#epEr{=1R5k=_B(s5<cRrykL`u_eTskkwFFjs8&oqd!EeifTT@*29g z>bGl0;J&7#HnzYdx{J)6(C$v6MwAp5lKhV@@_!T4fs;!O8I*$jg1{gUNNVCK1hQS@ zGUr9r-M}E~%DRz6&LGiN)BtED;s}Ss87@R$Y~tBBp_0v|cPg|w^lJ6e9eS`=bR*f# zk$!h<d@4P*Ci|(NzDu!4<!=6f!$OJ;UG&NhyAQT}JBFVCH&(tqggiG`Y9eEveuya? z75$&lPj>+3phrt5%SO;qQ&H{TiB3pp1&{tH;%B7k26;#MO4<(IF@Cm<$N;45eQgb! zK{2fQL19SHq{LiPBfMdW$wH4g*5>A*K4gr;@g?z_yBkH?`>D2y-9-01cqUX%-WrN| zq~XR6<y}@XDk5{IG4Q4fi#|<TK0f?<;>aeKJ03k<Nsr|Jmng~uFy_?AbmfizxM4>p z;T7e(xig@;{Z53RpZ|d4`WBIXSJM|ooApX!d|?)r?y>vO7AbLrn)sJD&DyW-YsQ5x zAJWb1rTgMNST2uAep#t~70P4jI}p=1e&JMJHIQfeUe1lF46o8xCwdsf?l|?7AArsM zPcqw*1oD(qgnFD_hBo|)ubrwAFqxcEbO;zo45N5rLW1zAg_ZI47Two(>p{T)DWN!V zNI?A!XDS6+8(#07TOtzCa!JcF*Oag663#1&PHY-;i6m?3zki@tOMcU4f{J9N*B*aT zPS;oqUo?6X=zcR3J|?N06DOz=qK`}~>Hh!}cSG<7q^+;^Bp+)HZjFLQbaZqutUL=- zQpI(-FYKxi2t*%!O~ZD>>|!g!zlg2-3=&`BbBa9Vxax}M;pN5LaB(i#-r72Nll?S& zYkxnIrH0K9cREa)y>X;Q*Ybq~NABK_Qm4L~|B*6dqI%$A?&m?*Y}dLaO|va!aYa1$ znj;Jy+dhd4+OTaUu*(tLyMr71F7NVf?EoAsS?AJ-61nKP57#a6muoQKWr@G1%rm%$ zJn6xsP^i@R@2@YB0i>dWCMPHVt$NZIu;npi+cbxOS)muSrGO0`{`eAzg<M8x`E8LJ z^GDJO-{a$p!p9)bcYkq$Q{z`xO9MHzZmR1>GwGW?PvcPZi09FBmo>{Xl406+<hybx ze3XRObJrk00Te%LKf^8S*iY18B2q=<9g^|W0Vd!W)6(+Pu{oR;ySK`)P-bC&Y~P)H zh&mp*{LeJ@f=TwIb&tlYuH0v))|T&<p>`nDW6D%2?66Ok@sv!b^uxj)zfp*>vGLQV zL5Vc_7C9G-%v~}y7DPIvk`z|mvpc|eL`>1+<9F^f)(?tpTPn%Fd0*%d6oaU8(Ws3L zYn*D}qU4>lMRAjR!+Y6O<NLIJ-$5H=k{!DER`W4rY@C$i{mIsw>)$g^c;$$za|&iR z-~L?siEMnAQhIo*kEhq?rQiU#AI%{+@XKEnW^W*ux{K)fvweMTy1Zpz^MZE;KM0Ma znm2*qwT623i9V7y80?LG_~g&I*`THtLZdRCur^J~yQEENwM)2w7>z0Kv5rWdBeG=a z*r8`QJ~g@<kCwiMZ!cIBO}*x&Io7IJV8I>g?g^-#nEQT4E!9KO#$j}N+&rl3o+stA z!=ZDfwJP^}Mw|n(G#Rfi?_7@5X4Lvn_Y~>xT(ofjUc317!gNC>D#3$LbAPC=MV>r3 zC-7HC2>1%G&_&?J&<c;X?SgeN1+!(ZD$u>hV5v(FN|Fzsfu(Rsb2jI2f-vvE>H(BC zi)@5NSU!F5b}Lzd!Q-T79&TYoacuCO25oPPj2LTE2f8O}^2z)iy5j4)36`!?)WH-3 zG@+WbE_=E%3BDtXwF5C(#~GTozRrz?C0Y^j2VDvr$L@*o>BpzWvGiDCA6fU5e*E}r z+eBz9lwMaG>-9Nx2^G3&zP9iZL|=bY(4yufo6B0S<F3#I)ox6gztNzRt-xii{MaGs zPK~aOt@~l%6L*eUwY8>I<-CK!pQV+JbFkxE9a7#a2bC8qToJtKOuzds(tWEKH};_@ z<NLx-<h>Jtl8o<dV5w^l@X1JGo_p80wl|R|J1zVwD_q8e0i3Jv%GaTA6@KU?VM&qF z$T6J%<0BJYvbLR!x(rgq&8=luMT^#DWAiQNgzZ}zdee5tV=#G7f__()0{U9qZqL5> zEu1%CZ_jKTV8YU*S;R@EKpVH*t*H(%r7vfRAt(OvN5?f(C>ZMTy1Q2U+%?k%93t3R z$gk%~itnQXHJb5=AXU5EXPG8kH&-l(RbncoJ}3Qv39^?@*~|Ry6ak9K`QQkglKd+E z-b<**m}$!`r?~Gwt)vc;RBM=ak$yQ3no@m>u3=G5hB<=-Qv@8}simW#Earn>!l<53 zX-fpS{b0g<*LfLVaLhfl@1j@(LcBq(6kuCfhWC%aV29d%dljyaY)qg+pYjZ+G<1(4 zs>fMcS&{M(tq-e60l$W7-|V&R^xGu)Z5BV<wEWyd3L%_5di#DN#l*3|Y!d2|MAc*V zQ-E=qo6{QCw4Tb?ut+3&Nt#$C<VMg}kQ2R@$HAs|OkO0O*%_Pgat=hSbk!HB?!l;2 z!^YyoBUQ6-3E<HB+_e=$0ONM2JWyc$M4F3=WF&+uay2UB@xg!%wr+U+8wHnCjW(Tj z!qqIx%wyYeO>-mAvvk|=Dfymq?28@GmO%fjDGCwBSy&^_hj&vdp%Ul+wnpiEt0(2k zS!wiUnKLkVk3?kA7qBmS;87?!<2=OW?UtVSngD_NAZ%SQ)nf120cKDQopsDDvmcIs z;5^UsJ@~ybAJr6xkt^R=V-Dxa=G)3*Z21aCpjIx2x!mos(c0jRaom^-s6RdbmMm3L z?Dt_mhy#qvU4%@})jsbgU5}ys_={uk7y|`n?8{6?|C<%L#<?$zblY#YClmzgY7&Qv zVUq>@(!a%i>-u2fJNBvdLc5-ec>962OQiV1rsl98Y~@!Nsd&(S=#@nYI)Wf!=^2>D z)1=7h*0@c^OA+;mgXbt>ER0OCfJ}mcp`a7w`xmZo9X7OTW}^AY&|n#Hm1#aMUh<${ zO@*uar$4^%I+8o)lL{xvV;VZl)dKpxHGcCN$hoyIjj<kjCwD*HOJCwlQQ~x;IZMh0 zX!~pq&=YomIk(D3$eSv2`R>eRf;>ThiW{;?ko7r*j*fk_zrcw_%N!O~#x}OEwdOA& zVeuSWUbl(dN>JA-a8RaCkGm_qM8$TztK3}J2@)^%Ou9XOzo}vcMkXTRJ&>>J-sszY z9o(XgDWQ=VO&C~CR(!C(zJ5XX&$PT~H45a8LK&O^**drXb%5C+g=wt?pe);`_h7qr zR)`M#D!=-WOd(t!2W~8R+*SVdnVrywrP?9Qj1l^>gp=~#bh45{s_*M@)}p3*oYtOm zuu0Si!2!74r@Q#;pJnfhRuU(CVVHOPJ!+aX1O2ttSy~+R3)9mV3c}IB!AhQb!zD?T z%+~L?@T-|G;+=So;Um-SFwR8@yVq7GnnEjZ_?CoHJM*-mI3G^0){UU-V;!pDg>A88 zIF|ZCL&?icWLfO&vgDh;UDinI7Mz|Srrhl?irT0cC15+%Y{I>55YrL2Q<%l_Ce9E1 z19t9KJV`nfO;cD@6doB#PEH;<D66YGnkgMzL*{JMZ?7}Waz#ryHIxu>)h30WQZy1e z93YnYm``Ebw~g!}I=~-NH2#qb!YmHYxWyQGsbV{|OJxtOJF*+QjBmW$2HGE%8(<Lr z+mrm6II|3^oG*7<dv*jKa-HkMp`g==*Ji5O-J5&N0hdN4;tIf)fwy0_k?b+~IXM;+ zRSx<2`AbVn6K+xO-@E?&@dbzq6m#?>d$gtZ)+udOE4(h!?=8yanxAkd30v#@KC{Z? zN=BxE%S%4+z&#K*G2og{b(Z^(+4NXGx$0np!*)#4LcEUxS60xV_Xzb9>9}V10$VQf zS^wnqzc?3<8$<X}u6Rv?;PG5I(ajm&_`A6e0CzI)S|A3dnkH6hH&UD??zuiz4sIgb zTbpPdLY0~m?kBIjfTQE&y@txD#G#F;wrwSa)OvK~1DE6OSM)P*dfu~9$_7hSYQIl= z;{Vx5D~dcFvo-d?%5XtEI!&aq*S?f@ePP-eVsc>~W|YhG@*j$>x)C~gYV#WEq;-NB zO5j%0+|tgk2yX3>yoaKzB;6LDxw*MLe*9QnUA@dv$bR&*gX{9(-D286x3=eeFK~ah zj0jXr>K%Rj%e{^(2>9r3vEmJljT_BdBivVpU1*;oq`kbn?Cn=K=UNdB<UQ8{AD#Qh zLlW^n3nI*}4V?e%{5%RPP;KhsvY8nW9TTIWr)MLSLbw$5<vGFM7Lp*f@mH{B&*t27 z5k5H_qNu0{ff(!MrJ<n#l<R~#NBVN$xqm!#=OZ8*u#)n9BJa|Rna@8Yp@03Ev<L`N zDgV{hzurOM95naOLj?acM(~+B;w)m}1fwJfy72GSEm-6%+#^9ZwE9C;Dya%#^{}UR zsRsY(`7MV2s2`Iq{|@?yH2(^nh#GsOVdR{Js<W)NE2R2_fA*_dHdPp`jeo^i(r@3g zRsI^4-+hi+oknKJ<;DofsxxBfzE*0g<s=XJ*BKEH-RzYAgM<gIiW(Twm(bzqtQ&ZH zlOfeS`5v|5cdI`JIze_si;W9Yn@Im&oMc?j^~(XAdsDBX_M%O4%4qX&-k2=U>9nSs z|A>d+xyTtOWFYlBOA;nqNY|qhVM6_|+I9lc{Mr}85upsOev=?Ovbbd;Fb;9s>ioZ% z<=lD}twMXHA#h`z5gr*qnrnQ1a-icHsK>Z?oY9v*W(*KX>dcue`sjFpQwm0Nx{Aqy z2q=H=o2PE0FAJ*<f_qXMdTM{v?<WV}Mbhw$IXO)qr0+UpsW(-Ba8t%}7pV(%wrV30 z8bvI6KVCl3p3n@Kt>_Q_sN=j?Q21d&(#^#%q=NU0p5)M793#Z<NukK-3e1z&*J<#h z+D7B?`h-){Neiu0y=XvYisT<74v>{ccqY~dt#C%19y`ae9edgV*f?shatwYe4mTEa zqG&K2O<>SStCwv3hE}JWja!ng4<yc@g*R->exZH8;vO>1FU43!^0s^xy=v5)3unZH z%q4l%n@OK1*R#^=Za0JzjZcAc3xsh9W|!q)#(-NDjGO-o*Ma}~O+e@UAl*q(aRpHR z;)==Riwgm7gtW$ELR(&LBh4<*T<bX^8*s@;ZCL?|vYST`-j1o9Bil_Amknj8Pl9tv zvYpVIW70GRo%3FCOsX%XZ0}+v^wQWmn_Qf~2Qw-~@cv^I2na;Xf1XA5M2**5KwNP~ z`1*WwfR@fj%=99D>gE+neeuExmv<7mLE6m34zdLjJvgvX{GM_pp;%8^PByA@ijEn3 z-nS?q&(OmrA?=%Korn~U!Yhho{C@Y_@<!rAVGG=$=GRzqsVn2e|BP$`=awI*qYluu zqXk%8>N-x(UKeR9X5s0PbjP>%q})QdC)qt<{mFFK3Z@aiF9%xLL|)%tD|_XE!{C(8 zQ<2+hcH&9?-Qd$d$}15GU1w}ugt3K-+6>!Rk?|gaT|k@;i;|x2*^jmicBGj425!xL zc?b0<?3;eTr!Sqw-v>-%f18RP=Q9Im9g#4BWTd-214o!tre4`HYzNFXn~-{)(a;mR z<U`>H6V$pu9tP}r9J?D#-1vbL<!-s_BfPlKokQ5d4&>kgX+<*;?m?cW;t50sU;yaK zc;spB)t@U>^v@uuJ}K`XwItlvIJU8G$<zGH^G9OxnCU=(fx)r#UKu^5h)|(VV%g1x zL&gVyH|AW^WW?UFNFHLU?l8QBV43b>y0_#oaN}fkvHs@EjtEIttw(#<M`O`mv62Q0 z#V^ORRHgL%pZr7yYX|Ji1as{fa5vz_Y9M`e8v(TO7yiXUzOX-*>f|R<$Y$6ml7GXN zJv!csvuZ;}93ND1cmF7J^<_b=dtbv8;jZW=G9;*iU)c){6V!NC<FZasit$Tfc#{DC zW(Wt>s(~*hK|Or-P+v`jtQQE{3sg4oqdl@7+6?wi)jNk^^OHRpU?A=R19205@P=XM zG~4L+b#U+Rc)Cb~S~niG{sRcR!{KR|X}-!N6||+}MD(Dnf_}>$YP>9&2D0`}dSaih zok!fV%H7S*{hMw1&<F(svPVSo*~EBnrtWl~b-uVuq8&z8FR9$)a_T+b){rtXb~cA- zIwSN9RwA(5OsmLGLj2_UBW1h5{5~@g7ZJ!tbT$V<s#<&pQ8!?97vwHsr+W0Vo~BZI zk1Q?CA!v&w>A0FGIJwGm;$@kw#xa50CwTL4l*#)BfxDK9>Mf<I*sP!<thD$ZL(g5& zd^%WWPOELXre<o}RD(OzSWB@1nM!OYD=o9vbHN{DraImj6W8sqCOr{e9MKZ8YBUyH zz89CAGEr;I<XJ^S%AsnJx7Jx=&rf0&+%+5#^0gtUj&-APzT1G`l{4h>^OC*nkG$eO ztb%KDrvBdB1a1j=d7b0h-W7bj9J_KdGtu;HhpiFAV@mYz)6zST3X?G=j)gbKzp78` z#Wierjp0~Y3(C~V7ZRw3NwJ^y+}wpI*FYW?`1n+P=}?O-Pa%U8qR90z=%TZ!JiHsV zP(#0q_&kNt2oLP#{Ux;*CBKHWdtvOgHs(N|i26#CH2+&2j$UuKvwzOMJkSJJIE(u9 zr;|rPi|=bY0S4wI)n%?JWfinb2#ugVrx^c%l1|L!t8NXCk4;-ktaNa=LJ?EHWBCG@ zt+ntZz}rm4C{w<4%C$qcg2#$_q~}rI8i~kWgryUi5$<qtgF_|#!4M4Wt@Kp?T~T{q zvon;+!YM*e+(z%Qhw>vMZ-|SJ{qx13oD0EWl10N2LK+Ya2Xn=gp><^4xV^HTY?Zx! z`5m*BcSro&QS{N5B`2%yh34jFWjUL)jDLq?b{O*UsJQJBD~4igN4MCub+a``feN}1 zg{w*XyZaD!UKRPaQTKueEMnFU_Fo$V!-Zn<)>iUbtyZj^9Bc{z14K2sR`p>u)xqV< z_DJ5saC{Y+o@#}!HHa!Mj*YM?n1_@S`91aK_OJ!r9RVRPF>RyCNlFcW^YXsIam$ru z7wyWr@^*WXDqbt^Z{u%o8W4ppbGzleSb3y2wWrK9&HZ*7%31Qg87Gq2SY&C^fu%lY z-b4=?gA(~yDWwQ{%A55Ro2eo-R3j^!V-u<c#QcT}-S4*U$5$C3EKw-F>RWcp2Ha^U z^&I_^W0v`#N&$Ws^R69I(WK~e6W3XE7;Q_e(JAHQwM1L|!i97KT%6^1;F+F`lR@?9 zlP`)wt7IW>K~*mLi!Ez+Wo`9~?)5~}(U&KaBIG-Vi*zNJESx-&N;e25Y{d%rV}@VL zw62d%JQwf~vv2qR5l^wIqATFzh+2Pdet~28w=r%E`g;MU;&izOw1HY={3Ip9wB)7b z;(b%r-NDERQU@#w;SIT^#Z#m9LY`x_f<_@+c+_NON!q#KeWV)Gbax~wz~0H_X5^RA zepIohv@0HEzfm5&0?~jY;MsK;3tTbJW+-#@cGcLrZ#UY?yumuBf%x#}YQ-)Wx`$Z4 zeaxkBUk<Kf1rv)#@HQd7{g@%6>1qk2ekm|g^j5dL4t<c1{y?cAE325D`LYFk2bn)) z#l?lH6Lfr}`?SOX?a%9Zk0yDda4PH@dTITW-~yd8xxsy354ry6HQDbFmkR8Y7Tk@N zEPZm%=k@~h-6Zc&^)~ysrv~NO_OX51TDlD!jw5|ohom|WnW8Z*T`e=l(###?u?Ct~ zubSIO!*S@H#?F|!hQ^4+eQ&??TCs7}HB@}LxH~dGbuhMpkc?7zv{uYvAvd^x4juFX ztg|=ZT&-2Dwf>e^bv)5+(aRq)*QYGrKg<4|l5)6L`9r#j!S+mHHyrH0yN3E0XmhFI z*c#qeAeYi4cK8hS#Y|%@n*N$;%8lv`yHA3mKuIi*!Ve9ckb$GhP%w|46x3T`FQ0ic zrmC(yZ(vY!y4U(azP!^P2d;<WZ}-93N5C29J@OR)rY~CDV|br8YA6o6M^g_4#_U}_ zrn+IR)_L66d<`cUQs}Q0-^^)}Q9fX3)adJP>t_AzNlOIw17~S)T1!uS*;ehIkLs}@ z*mg9H&u;JN$NW6MLAEgT>$FYzO@@iu`)=6T*V1tum;2K8B30}R9KKJztw@YoFrDDv zrs4X=;31@EprU<ioFsj3?77Vp?17V>W?Ouim_fEivyG6Z7UP78t@S<l9eBr>2bN+Q z2C$z{9ZmT3vXe?lIjMDWa!+v&x+DA0Qig3Ptvh#*>ZZGpU2xICw}^u%mvfuGstg+m z)@wkyW04A>2UcKg`quDzL~%iv|B}4Mt37(IYW(x8Ja|Kq*LG%X#+%TDZo?+tLudL+ z^VLH@0t|&1uN8P|-BrU=R@%}^$wz&5tHC`l?1D#E8tEm{;K#$?bBf6#dPve}5pxH{ zu4x<6{|B@A=oYD;;O*DSk_|{myZv1{QR(B|;qIiBX56Lux!DcyU~Ktx**6vr2q*1w zK|uk$z?L?dw%bVi*lO4@*kkotA8>c&ppvqdR$ysvQCfi1w3V&U@U1Y?%Ym7h#l>T` zyQ~JmTzI8PK6T*&yN;D)$lf>Et2n(yh(>w-<fx|Sa~-9{tqpWAm~PTwSa$?9JT}DM z+15vUZPIsjFT0?~&U($hJTgzx@^yo2cxEo5H1o@6aw7-n7(S`=zDawbd5eqPA@3BF z?vx5v*bHZjn6@(Lzh)SZ(QotB)tDZ9UZr0*F=3#{xg{ifgfu8OGk<LCATMoTCoAij zkei!M%gBU7)Rn`tzgzzxEdNl9KxBToW6}OeflI@Wy(uR;e#dQhbl<UXU2;RPvbzX% zP*t5w3tzS^IQTeL5HxJ1XyB<+o{#%66}}P=6%h8b+gpzbuXMZjEsTyrr&IQcaEPqF zk;aO14vNms21s3qWw1#Y+IG7-+3gUH5ZCSwzZyBAX)mB#v7Eo#J2+Dj+!Ca12d478 zr=orH!&77;Bi$`p&wBQz77IqojyBUm0q0#iJ6hTl9#q{sT2n{DLj+<WPen^BPE&g! zPBWQQSx69%8eyc_s7)Sc*9ab(E9C4sDfiEF=uaCS^&D?k{%hTth9+f&R==jwy^>RH zV3NmZ%`z{9OOXg(zzHu<iPhH9*6~PLrX^#PBO#^}5U}6QOv@z|RCb^r7V>>cmaM<K zOWIJkh{lcdYpN<wARkIg-w-z2^ORFu`tqs<u~KE_#A98VN9oklGZtOzW!(RAw)XNm zq^eo7+-`DeK8|Ukis#B$T75%B+Ob>(bqARxYmZ?K+sgbq?T*+0euw?4Z<|bd-f=t^ zC?cmV#k@cAIrh|66uw^bE#Rko!@jQCRZ!jUHZ#1pQ!ys16b7x5eX`H++}+*MXrQ!t z$>ln}D_mlK(-LNYZPS4?_dC*me*XKo@CzNlsafcF+u9^`+<uiM{UH9tvT#HkSnPg& zcs~(`X#DPMF|oCq?|%s6p){X~Ud&xN|JtylbfP-GO1L@(nl1uzk+rp0J+j2%1h6L; zhI60L3ki)1!-a<!$0)y5vdlxPVrfIGzHz63rl(r$q4=MpYu>q45grrmH^i&$Q|T-2 zOWe6*Jy~XHQ(2k*dIhnCjNke&%TxMt&#@~}*mDVe5ceqa71Yt%p-sW$T6}Wsdp$os zCg-UvrzVEu!$l`{mGla3tEG5s@&~_;wrhPU(b>W*Znr#F1pxe#ZWEfu684ewgRB87 zalKFCJOS$kYj^uhO}P#-iLWS!hzwd=@9J*psR-V5&;tpGxXw)#dKkdte=eha64TPy zmrOs;ernKaT|Qulzqwwz&&R?hCQ)A<y#4q_Gx_jvQV8+B{o6$B<UFrzB&~SBY}cjG z_uG4M@hK@~)g@%p+-PW(W}-s1BZ+<+DSAf~63@<2LL6BRZWl4uv2~>2+*shO9*s<l zzqqX^W>B~nOG693>_9@Sk8qu=mr2>z6hc$2OI}}Sa$|6}L`&d5N!rM6^K=JS6Y}cv z<5o&x;W(?W`!VrPcu=V(rX|2ciaVMLql>+Ev{?1_;fx%($KX~~-R#E`xwR$nkUfX+ zlm>nlQBGzv%Z=#bcP7w`(yH%skUlHM*KZMaU$Z^w9jk3RWIOs?xF@HY_58>&_jH@! z5_$0(Gx@V86RVO+vpzKni>9dB6L-Px@81b$ne&tqw{CjgYoy-*d3Mwq<%=FVe8?7m z%q)D5I3&WD`meukMki|wPTJUrC71K~wa>Q;Ko7o5LzlxuA&&(*BQz&8u@KL^qNT;s zFu6=nC;B4mhM3ld&4<5$o$m>o?LO4ntV%*pdO}5c*E2f-kHp9|L)uDFFNdd3ciyv| zGaFt^GgAq#>Zl5-sEG@`@ZsPX&({o9Xgm7mAR3?Ay+X-Li|-yqHXfnHo8&{AF>DL4 z2lELG3ezGi)^oKPL+}yTx>1+@X9L=k#?jHY>MhP$*6jmH2Jxv{7AyBBlHsl%7TjcV z63>(nX>|@pg1LkPbLe}M$^HcymEGgoN%ZCH4(8T=I9$}B%hmgYL=Hw)$9292qX)fR z^&Mr7V)vRGrK#@<P&p#S#`yj^Z1c4@Y>im&(tRN80-c$OVJmv$V!F~VWZ&+TQC-|U zJUEtKC(bP<(}hPF52#g2+I087LG^YgmWoJuSju_9pzBLzf|&GC>V{M)zmt=MuGF+B zJwpQl0;At9q1O#wv8ip?$;{KHnv_=&SP_x^<WFDWBWR;Kc1%2*I4{(*bVSCD7}yN} zGJH~!lf#~x1DCY4w7<W<k&%%*U^6T&y}b|HV>pP3i6IckNU;%o^H9^gaH_Nq+Ojp) zc|JQvh@I6X$FWo5*|@sH?9dLg`oJVR98tO|*E8JKwi~UcMjP{%UY2NUd19jQP_KPO zCp@LrOL?_c`EI*QseI;k{H5ZQhP`Kw4PzE?n}V@Q8=4UnbdL|bUEc)aH!{`M`?F2N zSHNXcKGROvVX_)gSennmE6x^X2X0SZtW5E+pH3g?&!T=@aA67*Ttp*oxw-tYa_?Rq zI~%=7s)^+%cRdF~;r{(6+y)I+&Es;8T7Iq_<3D6V(JJ~?ed{p0logLwWfMC3^h9lK zzuS`RRx_zf=6PM1ae49j6EDkhwvqH`b7oj{cIBjIY!lmqfXQ)7CVAS~_wR*@CMZh% z4wDCSBy%m%5qs;eQU{%jX%$}~<`h&yrlTlmK1n#Qg+&F*t|+CWTdaBRqd7{*Mn5qv zSX0xN+vY|L&tfYoudX~^lSF;nb@n%W^1L^>`(52310{oUsIH*Z*88Ep%smE2CH>A_ zJ~yAAQ>)`;v$K<R=JC9Tj$5nLp%;W5CQ>zw)J;rnM^pHGZ3b%{l7fmq^aPFHnAm^H zO=?`uRN=`tQlwYr)#IsXMy|6^J$N;)+EMtYyi2a4Sh5&#q(iu&<k2x3oJCsL@<T3$ zlD1pWoh^@y&0+d$C1r!lT=L;Ii`n~qis1zG>gXraP1I6$6S*$+wc3RrRVan*!x~nW zV8no-`X_h)+1lP*Ci&6^*;?*9tZb$_?eY+?fsX0A(D+Ef9kG68c{@yrF2ih-4^-Pd zG!Jp7i^Cv9{V|o}Ta`8`n{u1iSt;T?xtAusULOhOHUhx@!d7NNqGAuyz7IBM%~7kt zo3;$fIQd_%n4TYLzQh$@a%eg<)vU!4s=7W=$7DVB?QVG<kN)*KHV;)bN11oI-X^Y} z>ob-@<6ClC*jGVO2G52(_=P38<;y}3-sYn2&3aHIBp0FXvEq`Bk2Ot?KJY|eW9pMn znMG_y$Q#m9`hMJb`=wcl%MXWnkzqre@PzIAw+YaFb@hS0n?kV=aR-oA;<bd9wFjIw z*%o=hE1VNb#~PH*1^^8)*JGkmDd@{=hE}N+uYVN?SzcXl?0Z&$e{Lb?HsA7=R9^n- zRr!_S)?E9kD5#ldOHhsFxq-%1ioYnT*moa}_Z9ePOueJO4{u7XaFg+BYgx-TC?j4` zjiX?EW}i;2Gp=rTmv<_GL7eT*iLQ6)N$(m$uprWE{YvWfrjkWxBZ%z8yRKc@>Tgbx z>QGL}2d)N&M^YN#n3>PfYj+`N2T4PH)i2+*4JJy>#jCheu2+|Qtm-MhRxvPOX~%VM zv|7+@{fNGmt5cbjo-|l}<ombQHL-D9yV7Y&`^8Um3PyAk2u>S22UUMrbN}}A!06DC zpeH3)F+mddMJ-RpGuQ;4BE!p$!HPOy85gUs!)<Q`v2Cs2Sc3{DoHG`mrwQLUD_H}? zKO|ZWUhQ*aH#@4@HoBzjde#*=VcelQ<GZE-BPI}EM=_NDTw_&=4!s1X{i^W}Qkj4t zGCCQ^?|23z{%Dxv)!e<kz4i3;<mKf90&u0~t&gRp1*KrNVM7zbM^F$Lb+EyHta|d2 z`90O;r>iBM@Pq@fbY6bL))ODiomA>hA=s#A2e-{jB%ZF!Z-=$%MNZ9$WlIFQxPP9< zPWppN_>@OMX@S8kjMU-7-kj`vW^HBNze*)NO<c5w+Fun&uEbQ?8@*T4o^a(BXR}zS z264X?Z>$?E>@z+2i4%1@#AG+YM7;Y4r*u~m!{*o|*Vc?$Bkhf=myZ$G>Ix#L?Ts9s znrnOc^`^?l#LIMIAuVLmzM(@*`0}W0K*nJAP&d#KrG4_NDk^s}ciMo(&{v+Ba?G2j zj>;uV*6ZAD@<y}|hBuCX7^Otg*r%~iw0BPo2P^G`%5fEy?EK_7Dq?H-8at#IGuyvq z>odo6(`}?;(8@7Yl*hu|OahkOtlnpsN_k)S_5)@I17%qa*_ply_ebXJ%Ek>WqIo^T zW42t1-B*Y=Qz#m9bBeQ4+%^l@EK&}^Q$xFlnA(UBRX0R!OyTT3VWVn24wI8p{ju~( z6|U>wHsYTw?IHnNzim*%#8Iv*vSGAlgl_TiJs*LZy^+H5ftSdjQ)@k^qaTah3hV8z zEDEAeu|n#W^Gg+vYCD1cKeWAPSd-hjHN4hRKt(_SK|nyH_uflXq&MjuRC)<W??gpF zdXruvy@S*cs?vKPp;xJ)1*DS@k}qrRea_kEI`7|)>k2=gXFm6A_Z;^aW5U(-hi1w? zpjqCQn^(#*$lmjUR9g!Nc5fPHM$P+3RQ4IArO`c<ae8Uu{1ym}M0N+)7iVO@S7VSw z8ZEl+4T0KR#>iwhkmD8&@ATc{<C`mHQWoEB3*Is9k{(<6dpTL-?W70T*(tv?svcXg zmu>P<vEAuC-q*Y5tnI^l3h>gn;2_bY$mt42=k?!n3vP4ak84{;j#*GOI@u&u$NRn& z&`2=-{?yh|-K?o8-*O$Cy~h{VMzzgPP8PcxqW<gHvTwKYlb&aC0-ZcVJf=A<g!|Ot zcI=HW))vowHZNkM{i8M4ZhqPa*e@S-N*fuSz%jaLncV5Dr0xr^E092RekBsURZ@M$ z(plCr?kY;tY#+{_-5D5gRpVNj8YIdD`(i0=Z-2F|C`$^}X-zS_E^IDlhpp&YnSm_w z@bk_M4xi&KZl)nI1>_6*&hIq{_*1j{&SHB(l{2U@<aFwU((N?Yd^VJ^S+uL-r4+Hv zWS)&~$}<s92(3}GBr1+#WG*MLpr)`|2zYbYSX2a`*~{t8HQyLe$sMfS4$EzG?RYrJ zLijNea4*A#>(|OBIqYrq+7el=z?qARoVkgyy5ns11((rf0(NBR&MjBR8@SanwB{5} z;^HcA$v6hhZVn&4_B~rVZ_|jUgC?AW48^2H@Wn5^uiEoBHJpy>u%qKODt;0LlL%Zg z{x@1GN$1%lOK{(Cz&ZQ;?4WC|jrTcn-f=!^G;3>ZfzMA*zimouHbWYE%V#WlUFKhC z0PfQtU(H$_!+sLh4pXhFXGS#^(06^&-@bkO@#BZx2!SwHZ#!8)(5k|~q7LI%#~c4z zKx8E`BvlmJsxnrF7Ax6wEp^ii_NiA$vxcGf?~fvO>~L?*qxZFaRIBeDfmszf1mc$r z1E(e?r)_q32c;h~Lr<;^)dtA=?4v-<kOp_ZgZf=?LZ*;M{i*>7U#^ek47pjxHX+vI z4e7k<^$T8d^2f`+&U84lSRyPOJezIkq{Rdjf7)i&p~&UqOVoT$i}&QVqFq06Wp!y= z^+=A-Qw7()BD>>546-$)|I=4-Kvn$QcfrbK`;yzUKr%a1T~R73N{L6lVvUbBi<BcZ zO&&w9Hzxz#98k^ig^?)*#@hGQWz6(9^Bvv!h4WO+<XPo-aPL2kl`sjqNzWU6rIZ2s z_{Sy|7Pd819~&5*9Ta`OiX&n?PwOsp5@y+;eeWPt3W*$uFM3s*@m)^1v~}WO3NYI! zPDg&AqhTQjKtFe4WiJLE)!Q;_-=n~|spVMVpHQ8kuo?1p1N7miD<*TnY&>&$A8byh zxKldOCy`2lSg+;swDqxl``eL9C<VBi=wwo}q~Uh&xK{M)WAh28@6_9FF_x!e?SqVc z^B1hB?>?LMrTsOJyZD4F>wolk-`!5(4<E|+diG4>$tV)1SB>x;HfRmF8U1zsP&UZR z+uP4q%y`T7j%xhkgOpWM2LYM9y0>GqUaTT9_4h3(WT8yku2Ezdd#CQTXsnSTzFkoI zjmKO?(N|BGkf4O>>h|-^?eC^P_j|5=C+GFF+P=gML1wbpanPEjU=eQDi>dMg_B=VK zy-TVAVqlE)Yt;Pv-^VbGnW$vbQEwoRWIB5!%wul%bKMK`!b@hLD5I+BcW=wr!NE>J zxy6e!hKojBq5@C3_-r-oLkN|gHP)d@`_PN&-Xko>{HeR<`Q^25_fqPr(iY9sW*Hi( z<<dVMKh8Jow$n^uPrx3j`?kG|<|J#!buq}Ag{A&w-ZbC>LrU{VFrRb4S$tWp9ial_ z6Ey2k;$~6bakA6wlUdGSUu=|m77^ps!w<WIqLZJw*v`qwEoa!~$m6MU*>Cpo^J|_t zB-faKAQ7Pd_HCT$HrS==Jc3nPHu*1m*M(eT{aGgp@S*dFd>Rv#RN!I%GW)<Dk1UU* z3elAg<LMYA1qw;)!hcoMzv)jf&!g`wg(EuuUCwJCeh{>*kp~W#ZC&UpHHXalHu)|z zc}Y$x6*r936!Pch4w%by$<O<oT8(U3S2G@`dng`(JN}W2+_%R$M1g9Y#HSAy9zJS# zzZa2fs2ou8dIj)5H4o^kb#QrZ?&Qyg&O8R{hYXo)i2?pWR!TAKlCtdf)y$AovsQb^ zB!QG`*F1f+(iCvI{)2JA#Z0p!m9$I*jGt%3Tj;|x(p&Z-eUgqNPj25@n$$CXAjv8& zEx=J*xT2Ss!o#uuUH45@h}uqXaW^H!P8E=Qm8$EFhk<76)5u4SX=1smW~eTKcZi>z zOj&!R>kh>n?y=+hLK&n9CBQqm-`Unw4MW{2oQC|clt|n>+@QhFePKIXLnOgad~$M5 z6438nGYfG4PP*BXist|N^M{_UhksC@s^eUV)<Z(BDp5s|CE*VIN{+Yis)s&x8awk@ ztGiAhC2nbGsuS`!Oe>lz+sO6V?p^{iD0W#=gUVhm$w^wa_NI8f6*4~3FstX|feS>& zRUo@9?0MAh<<=?i1v1YnTIu*^Wk)A(7qcs?FdbC^`3W<Hdow%ym}Gc&?ZbulSTcJB zE&$~D{LLz*m#K^H$wKCZ<>tM%?`Bys$+zH?h0i>z#j7a^@tZNr`R+T@jcy2=VPik% zm{C*HS}^`<zP9$>5ebq2i=?yFWRIb|p~0o$1H&4F0Ks%uLqUOgBgFh`uV1g%7wD|V z?%$8QPYZZ1((B5gj(@@|Vq^kec5;z>FXe=a6=alH?FwJDSOWvc`qJ9xQs3_G_ei9o z?%&rQQ5y#y?mD~kuCz;vzV$u(Se^gEoNB!%zR4)_Dzeyj(bbUs8g9c$0+bD`7)0dI z(6|K6*Ts!=(~M`fNI8cz%15cadueenoJqPZ@I>Bk|1cS2PeKT^5U<y14%D0?^|iu- zAUR*PpNF4UurTpQC_A;aQyP-d`}b*76au{9E1z=o^Vk;uxm@XwKm5Tg7p<4KX|Swg zX7HtXw<h0vC(zP?8JB$S+pX1w2>7H^W8-zI&vJ7Ys-3oktOIo6yF&0rxOFQDq!<bE zWyDv(0GIs$75=OzX=Vn-C5{d|*wb$V0Pt{hR(8(UoY(NlIfV?|yuFi)z;JX%gRq>4 zx4WfBNU4%s)N<~!QA2S@TcMIT4l2hRXr-?AE?7-PF`E-NZ-?~?aoPB|84y!23!FCs zih2UgE6pk(1LI~-O7_5Qe9f(vK@xqVdF^jiGV@E?=Hc(<ytYn0$K~|`1Xa~y6L=4+ zAooi^%}qXyY1^-0tJH*K#SfUDuNWv0SXG^NQFB34eT59?zMC!a$d8_nz@;9$LMml% zNV@UW&zL@02kZCP*P6B|c!4ULpp^qXEQ#Mx;KkuFyYe-!na?$gowd^oY>Q4Eq<B}U zU^Z!vH%og(2l{;|IK_jX60*mzj$>He=|Oh-qalgXcDlCa@DN&_k?cvMX`@W01`Yx5 zp<y7yw$c#*TC48p0D>>EC*>n(`v!{aCFba5!hH#uk*^yW6Ejq{t97`C<)C6;=rGn= z&V5Caiu3wf2NiO-Pl3bfcY>w7)+Kp264KJWTN&`}>^x7|Y{!~As*N_D=ehkmJxQli zFArMgd<gooKUCIeCL>e$&Zg_?WQ0!Cp@xFOTI_OB_o!V$^68uHD$}EcK$|VN6R}MS zw7O$z3I}UHY?CyOBPi(!g$Qlgh(SQx_&<HV4I(#H2*s@Tws+XYqwXhx4xJ!mfjA^^ zts%^2{nEb4uhEyH0(5xj=F(`Z1hkTM?;d4$@iX3{|16#s-MkPs-&c~-RDlK~Shs7U zRvIG%cL*HhT>QMPlT4@A)@a7>7BZr*$1TUNHhwmdmX2E%?SW;@f$ZG7427IytAXFT z=WMy%xz)(P9b9Zxt7x!j!Cx;6Bn}kdD^7b%286mHV$yXeO3R%2_i`f<i|k0k%srQd z3Yk6fO=`&3sj_X*_?Jv(%13Rd?}HpPAOkp4dHm@`1`$h=@RC5)lE5Y!?8iQu-Q@b> zYWOBDb??u!8^uL{-)s||ALlsIm%jNONKr|@)RmVL2c21X!!4Ef@S#{BJbA8%t`B}j zBZKvF$2qv2MiCH>Vp=sx!WbYCrF0NjNH&~Fmn>{6?)lo~vb_E%g;NU`x`OH8OrQ_< z^;IH@N4pKDlZHL>wKoOww-2N07P1m-?MlYMsexs^Z_eJ|$&Th%=?P0yAyPUVtR{f} z>*ZAy!+>Na2KkV8y%*RU@xyJ<N_M-W+pqSfk3kH>Q#NP+F2R<vE82StUd>Kf*E%yb zR8|hbbxkZhhuG6&=|uZo>!@jHIxt`oCd>`&@$n|BWEb`ToPb1TFD_^Sfs^8l5awn} zKtPHy_H?RTf6TtYk8EYP`&;}Y?a!gX&Q%6Cr@c{BP&|1NsOCt*bS%#9x}mx1E_t*G zr1{csQ8u1>a~c9M^|?m=8%0|j|6UxER%6ZHD4Kzm>^6$at@ro&+EUrrF+iTy)Yv>b zZR@_$6nI!LEzFAwc)p&ZKSL~NCgumPkBi4aEBnl>+htioFTQTM6wZ_|u7tMN&nGV; z!CKX*k^(G${_*~d0IAx-gY>VB+%gIxuE5R1(Hx$z>K<nX1H5a4kIx+aNeo4=d$b8n zqkWH=aJ8D}$u=;PL_MogvzoEG5AEbaH50xN)Dm^H7FZLx*uV>A@?DVo4f_|ARcP*8 zo7Z9Ma~8ew(*j~Yv@X5MAJue?)UJe91TPNvp7YvAvMG55>BO(JyxqdyZ7{AF06-S$ z>nTe61Tq`EExix=H(Ofb)?VVst~=E)**Qls3S45(yhnZlp{dHJ9#KgWepwp#nrn0{ zXj{eDxYOdrSUi_o2QBGLmy&!vRb(=7nIdvx)L)s@V`EI{sVN!gS)^&5=&obpQY|R{ z2eM*Ct&N|tKJvL>lDUL!`|2NePAIKu(C|ksQ?`|IK?-^&0gIzE%_-r#Z`DHDzNme% za9Qnp>qa|6p4|(8{7&tWB&yA6Vw2&K2<19)e=qMU$UAyxwJ~DR$-p+YMc)`Lx!1}d zLr<pEcA>&Ye%}HTJVvaBi^~esA1m)MPqx=IgL1fPRj{$D5U}CqdHVerRJI_61@C+? zKCQ6nyrcv}6+~X0OWPpot^>`GDr~4+e%&4raD}BSEd9*RSXm%`;X9nbHgF9>ci<Nc zhoC;|8ywKPuT!Cd@=l%;orR@Ya++OlxdD1<axSKGGlP~})zk%AXLGJVG9p=unq$)F zMX-03!8$l-PnLfFRFtABuP)f<)i?Pb)pwr5n5GvR_OW>kO>LVd4aJoW?NXvVp<~gR zF@?{#@<~qI|Fwb&$vq}Wc20L%WEHCxc^Ae|j9aOOv2`&5tvi_x;N=d#qqVB4<Bcw8 z!UpcT>)I_?+s*Bzo@dj~H_k3DV&+Wp@SB(~e_bK-KRW&LBvf>nf0p(S+u$u$-$~W` zpj)T@rpHKlrEgRKM`ksQrXf?zbIrlJua96qZqf(bR?QYBm#hNcsW@Yk%TPpQ)RRkZ z8`RRLviA~PN!J&o=N99OmrNSj?dP#*TnHIa$=0j{5<Ca(>og2i%#768YB*k&%ItE{ zFY3ZS!7KbV!=b_?G6OLKlA*~+SdICbYjcF%SKwpWv(>BAU0j|)p&^;j{3aIO5G505 z_(w%$hUsM=E;#7eqNY+<1F|_QwuL-epzPv$cO4ZNWc+W!&1e48OR$=3W*gVL(<n^J zMd3~(z6Rt+Zz$o&M|X$s5kI>VLz>_Y!}N!V@HLXt`yAIytxzU=hteqd97(^o{_1&i z;QDTPr(@C{(UUz}4VvE?^rKqybd^1loCmUVgR4c3n`y4;0#1CcGEbTUxh0?D5Xe!h ztOpF#jS^RFKZ*|aUN*@8tgCjtUb#x`U?jbt^XL(kgrL7y_exk?F8@q@cZc}~&1btO zwY<fh1d>py^kOqHMsO1&BlzC_wX4bN-`n0b_0@gDDCeUjF1+1oi*Esq+jy<xD8yX> z6r$_~bmE2h$odtjK$LFZQ;~7NVQfQFm$%X$p;8PEE$ic~_12FO>w!*{&isos5YNfK zjx9#bslFfnsLP@ue5|aimh=D|C7+|TZ%<OCA!DQuUj*y-T|@easzxSE-T_5(hwrOd z^f9hj;LqFiyiOK1Rs24`a$9K(0u?6y(cXrb@jf$AE^3J}J)L1^tUh%4{XB4~-G>fK zIWW9*{g!<8Wc$F3GqUWKO&fY=yh%4(@^D>dX7hp52&xh7c<8&U?QmVYn3<fr`c^^N z9JRFi!`+TL{a_=#k-#9aWg`~cWmqX*J57$(CU9cliqgWk7k^@tu_+N)xZ-a1_UFIp zCVlDzx{0hCQ$Ntk%)za4xO~v0o#Xhqo>5q;Tx}fauU~b&jCUu!US8N4OGJ%{r7|hB zddx(}$tKtL#$GMU8#Qd1yxUIu%<U1b)Rfl=$<}5XS{9R)k#|u^+5lEGXHgl-8rP~V zWc#yqHOTw<nRu%o#CMQ=^=aR=y{^mn{^&yIlar`DUwi^Zoc5AfkQOG%Ge}h4vUz)n zO13cl`Wm)P0m5kFn=<dJI2&C5Yxe#jW%>8?y`Jg;MSYjZTpUF)rp1q|g|1qMqPJq} zyvF4(53TW-Y6#)>gtyQ9ghlKR<_Py@;8Xw@U5j@G<<-^mu6dTuH}m}qr})z_3JfxI z(JZ}X`m2#7W>UB&ewb~tt~wMopKu7>GAKsv0BCQ8Qp!82!y?RFBGW<5zNTaR5fS!> zVc$k(mN$YQbrsD_T#NqZ37edPPa>ufllIPT6)s{;rrd?1#)hrE3#bWgKNaI3FB?lB z(9l}ZhaWgoBN1Aew&E-I`6!~UuA-u(B4Ht-MA<7nbw9Fc%-KzBYTnprc4|soQc~=3 zwllheG{nt$>)I74n#oXk;6oPYGX~5JHg*ZGx$s_W9o^oJkg4HbP}2h1H1s%rNi|Hn ze|tIC62-3^W^3TG@4_$&oN-&YHLDm?taR{JOA8p*7>TOp*J>i;-_xjCwoFUIbWZ-V z|Fl8r5|j?D%VQp`sBf)j+|`{V<%}q$oi+TuftZ9ZuxUPVOOv2yaNcwBy2d6Q<rY>V z;BY--!;$l*lA47#u0m6ikh#n0X`6j#ca%J>&p#ZDu|@RwVnU;CV3F23kBmTJWBo?* zM`_w+#uG2yp4=EC4F_7(i|WWUZBvjly_pz+>*42@v4^rTwbY+}<J{cn<7cjU9yg|} zUpdXec7|G1BI}BwM+=OeSPt^U@S8Wq>o8l&TMW=Yk>Pl^>XbdKy-01&y|5MmX(%r5 zta10>r+3a;kZm!YcWV|iqH{*G|IMM0fd{UshBp+}1^8){mp^q|Zmnj3(1=X{AMZKo zq!$lOO_}Hm=Dm<<CvWI8=?Nj0$W(%ikL3^BFc3~JU!NGmtz3@16^`2+UF$Na^&1HA z6~e%Jb!zw~rM9$GOG3etQJ&_I-v-dRx3||y*cAIYuAgSeenyOi1dG#SlsmH+0)}+| zJ)E^Q2!i?etC3kr%vNXy+>Wrv02?BoOFqt)=<n+|-p&Setr3$P`OTO*EWh7~3ukBN zr_pGbuWu?rZS$A#u2}43<4o;T<(t#h!}j!)Flgz;@;v3<tO}K0{OnMKOjD`z^}3au ztHo0Io(n`~J702pE$g9~CrnAU_NYB~Z4*p-?_RRlFC*xs8q%h*x%qIePVs!A*?o0o zDV8~#f`%}V$V`*eSSoKEI8glVa<BCY#0R9{2n1C603|@dSX^AJt!%SDQ@yk}zZfDH zw(EN6Dpdz?va!I<l=VD1HlGGOZ=3_y?N0qH8=TmQE00t+1EvYg%6gBN>z7&_p6yH) z-tyS|_vr?amp=)000^&b4~3_|WzG3$^v$!O)$(4mhm$q~G^x2fwPmrf(KzfWEH7X? zlh!KuI7LSx<kv?MfzGS-rFN<@dky_cv`GiLdFq0>gVvv*)y?KL-=_(D`Ica7kb8oN z(q(>t;wFz@LXgKU(fH+K%yb6iq@%E=cgV@NVd4H?v818Wm(~=I8b?m0a<E?Z_9b1! zOFRhxZ2MhF4ql_G*Yb@7OxI&$14T~G$+k9ZXjmG3dKm$`d)GpN_u!3NuG9WXhnZKb z4FU2^O-)@n#81?L@S&WAb#H!tIyv!lzdVkOfHfy&ru|~}ngWF;rlb_Jxt4c5V~tdK zBJJ6`rA<XeMPmE67a!s810whDh{)qmf}ERi+RYN#{OzB#VWaKq(YyjJzdorj1)OzU zuHsKBYn9^ykA6lnweA$eJhtgVkGT(5y0i={>+ch=Gk!IG{N>C#f^g#73d)_GLVRVy zAGCjJENPfuC$PccS3fWg9KAtp``}`Q90t+I_4@EPFMUc2KKaf%X(YUaJv{FL>;shj zB+n)Q*_tIhWG#k=A#n6#qsml<2h)lh%H<7I010NUgWW9NdWf5)@^0464Jbn<1TGn4 z^a{9&cq3ufW^QKQw4EWZq6$RO`3RU<#wn|)MD82?_%(?D!kQ=H2Gfq^6^8gfCJXXw z)RU5WSX%_?(`C0hiHQFr8Z08MAiAIt$$7lh?DUlL_9O3($rj%m%m6b8o2()5kbMz~ z%nSNSMEhQFCE#*-Aws#vv#?yevFv7hr(eS=%cu1U*;(gPe9zQ9nmAiTBdqQ4OzZ?k zKH!LWd$8<NQ2_FFq3ZjIk;d*?z(iPZrZ*NcO^ESq9~bqVjK)y-EICQB^$T7}Z%3%p zA18oYzgXlYvinSu(joFri}niae_VpDDYgvhd+)dYs|N}HA8SU8?ySiB4s`svOw?4} z{%Kp?#%pAJIp`!NCPiPr=h-tFeoM?~11!&PB><V@rTymhYnzy%L$JA~`%%+M%igAG z0!UPoAWJovAjhA-z>gNT=5yMxPxn>i9uR;VjbD=GZ5}H4QT(hL>APeyPP`A{!r~yQ zK&&W;+H9ae<%R63(NcIQe(Ar=&<Kr+U?rR&YlEGRI~o>gj&>ZyGPBK4TLy;b9hb{~ z`vkXcKl}}3$#Z1>w#`AUj-0MRAl%UzDAvSOCV`hIci23zROALn&H!9^9Ib!DDttbL zg{6|_CZs;2nG-HammbTQtj(e1K}prtN`-_<m@1P4kWh{cHhjaktedImMMkg3yvUt1 zn6^^uHjlhd5o-SuR{h@*BWRvPy!9>xZH{o5UtLDt%+*2+T7<xjkIOT)yxZClwgFtP z$CTr6em8r@Fx>U(fOd|fSd&C^22WfG?9v3(RgU`PP)cr%clFBqq?i!2ImYRpVfb)X z<|yIhOV$(<5?KS95hW+bPp`Hphha^wpbb$mR}SUrGtNI*7EI?qwMnNjYIiUZRj&dl z^az*xVZHvx0_cy&@%M|T<dIQ#6NnqNw06scv*^t<<4TNJ1GZb0ZGeh}__N&x<T!6- z)w+>KaVM0$ZZP;LA`cu&Bi?%w;CSN&4&LUkbM{#IdJ6QBC<uJD-pvt3cNhtp3G=qb zFwD*sTBpQ6w~o}7i2~7h9D-AiVf4T~RI;8_o56$|+QCi-lZ!WPvb(`S|HDJ+zDmU0 zz7<+;BBX&2p(lIKS+m_?dw6KL;`7%r(*e%_)M#pSMB3-SP8D?-A==Ac7gVd{F8Bk2 zKNI{RepGI}i)GpO`8qg^sK}==uxu5eu~o{YdQNm!5u4fXWau8})C-Vpamh8ZFjR=C z%yFGduwXywxAY#Z&cfVy{f{Tn-_fa?mEW(c1z|A@0GN0e(?ZkQm*W1pZc>NN$5~m> z`r4}V82;QY(p~7ZJ1js4P1X_2WcE)>JomuGk1!~3=D;y*IGp+lDEN+%e|fLn109bo z5?nfgRaBGtV;eN0_$9W2pXcPLQ{0^XC|CvP{D(@VCn?{!jTI+y*j-vGFV(iK^QS!i z-d+xPva{)%cw2#wUz8JSt(js&7T?l}{AdWA4Wab8u<m$(mg~jMd!d)aCUB;EX4%AC z_y(q|#-@r9Dwcym9n8Du*wa7y0U9JmrJzF<h)?|V#J5#I7xrXC@PE`pAKpenZXXe* z>*)xEBrfnB&N8&AE7PgfFCGo?G7l9mJf11%Jj(mN-(4E|+h}0v943&v_X{WhbohpC zpmxHMaTDro9LC(NIU^3~aT*K9`UJ&PFb%|ze<53H0(OPuSf&6PcxGXcf9rG9|7XGo z9sI7@-Wm?qxp}`uN(#cN|1uQh?>t*=fCXY1YW>u@Ko^V_6|Rua&8pvthqJ==_Rhg~ zbUvSc*yw#jVZ|BZ4BxwiUBI6G#}l!?n+e`h-HW1Ny#R&r|3-)YmnO@*9Y_$J{=OJ3 zHONaK_`I-QO_}^JN#U;l;y=D#kXvu0zU_et&R@eLBmXTEC%kR^&OeXvUtIiC=*frw zmc<ejaERl--@guYC;9RIkN?m^{?Z&+{M&&G(!uyg&!7LrsU|$?gD9i>-~MCm@*^aF z`2UEa;yn4XF_3`V-e!^y6yxON<mKJ}z1BlQ{$#Gr?`S+%7J)#d3s~O!Ppy^QKQDcT zaX1Q(|Ae3%rQ`ncf7?WeNz1EW0vV!u|Ic9D7kJo0x*bdX|7=>A#_hvT(yT=P_k&2? zVZSIpw!Ilw{a-@Be}&=yw^tI+uq$``Ot@muy*2mi1{X<ECNA{!2SDTh-G*F&<L~$z z0dXN?hd;(d6G-u+*KVkL*uVgASvDo6ndSgG%tLY|VT&4;G@>Kk4c#K+y;z+6;F(G> z=b!GSEYYhi>sni`_riszJXdFzzUiYLgXPd;Uf<%<(|E5h%YgH5JK#&LPUGgoJa@hS z93~N>D-s0HH~*B99>C?Wgz>u9^Ros^8ui7AEpU@BuSs`jlY#Y&)f9s#p6~w{T{T+O zvvQK`wy3x1D1JGWW(AYP4^-%xc7e8)2_R3?SYzc!J)mK6+qmq}&W|`{n@#*}{1coE z;R>XoAj~@0_=fgBdh1Qb29O|;42L+3TNa4<8YF-&#H5Vh-toC|;Ab83Q*DK(vKSv| zTINOnto_HoO1|I7;#UNSDTm8T(qj!=SYR8u-q>?^g<NUfD=c>Sc6Q}Jo14C@@+)a` zRZ3_}q2G!EG1}#UPd(6%Sg*on)OkH_ORLN7Sf;A|D*L!Cwa(>n+lRV_9Yy=w9i20a zjEXN_yg0rQN$!*tus^uxetDb7PG}gmV@+f%d_n4d`N{$M?u)=bz%g_8-xG&0&T?8` zO_J|<j98t*aJY(8%*<V~ib2Ixev3gXoKWGC?mT_<AZ9BMbm2xxE_n)&m5p?}a;U3t z4hkezCnOvz0n@FNc+E+eHr8u9_299hhmit1k$hg=ZTHJwUiO$evHnhuhanF`0&-Q9 zF|zJ{_lbyz`YuNl`Xz)fg8K6=e05&GCNAXr7Ifw=Ofxj6>+YwlgGNqR9sO;o+xY?V zw<Fz3-mX_v%~HK$yyd_L-KIwc3sjy`*CUI+_Ah3VwigX25zfl>k|~jV`H><w5$~u{ zM@OAMjtEp02e&u2a*n;OS_HJ!L+Qi#0T1IJt|g~pd8+^9Tsno_qQ>);mp3QnecX!# zrBxf&@`T`?-rc$8I3n1T7#fQ(5Wc2F<U+rnMmP;{bxoj~3)!5~ol*_!^*4*mOx2eB z#g2M!M{JW#$LrO==r)@l8`3j(9UG#7(tPWB*XFt-#44hyaq=6#4PQ<jB}U)E&XzBG zJ3?x3Y0x$Qr=R0nP8(h}A3Zvk$2lumkImTuN4QvaVIv-cIbQ1#TDRm{PM@bt#^mSv zRo^o>bUK2qQL(6ZuEnn%B(xqK0^eO+a5Eg}^_Xy&(s~59qy&AlKGK&j&aS(+U?bFV z<UGB1CN$GM$I}1lakjE$*65r}7TAipMzp;#@g(qT-E8|Zl{MFr!ypsJifUDMWJgi$ z{PcU+o)?&>l8(2CLbCP}<f#62oi*@QNaKa--h20p2XBFY*m%SmI>)}f71CZ?L}QjS zW14R{ptgqb6|k`>(~x&_+fO}_`Mc}JrT)DixDu>90vT17_kTkO)CYnsnm21I#{tNR zv*o=i7ylQd=`dYb7Ypp9>U>Iu6IC{Y0)u?>aHd%!X3fQlT<@nCL<)zW+^-aIh*Crn zcKw>08Ug$P54kDqIrIpeiZPuxEeA>bzWYu3@O&|U54=CMt{5+BR5amuOK+ik%QM+v z+4)gK3xKf(vjGJ)!(SLCOYMEF-FxO>$Xmt3K7{77fsjTC;(F&IV;MbGcOQ8<<b+c4 z;<mrKICG$ZkcIL$2ao!319N6%$KqneDe+%qiAo*sMUCt`xxFXNW><91ccWF^))C0v zl5sALZ1&7}gJ#RrYJ~RGj0_RKzjbxrW^pqmanW7OMn}ju`+X;FaITH*Zr|y&vOKtV zZuK+O@f{nmknd|fm3ihm*!hA_wCZQy!65U#xm&T8+|ox~tVH}Pf+m$0gcs(uYtp}v zvpqadN#4MKs8^cP>x_mxa%~TSD*7Q_%u4<>=`DvJdB~z|055{v^CgXG8GSx3JXYs5 z-yvI3K6>S3=Z1T{nKEp*)|@pmXU(>8YFz(ZW!ZHgU^m~?Qfr$(uI{ck4UMWB)tBPz zZAw4i?FsG{u=YSLT~K75iQmOsnJ`5q8`9EYw?r7AcEr8^92SYFBp7I1PH-BQyXVBb zY|ZQgH7}{*Lp~q6GbOGrY-sR@Y$^=SDaNuRf?nX`TNK9&Wh3C_i<-#wqD`9|Ydzli zAjy!jyds)*adklvU%HUyFJSo610d~zKy3_C_et&57EUHaool-8qXd>TM6wSNWD1py zl&N4^RGSz2hJ$_@Hye2~Zurj@>+tkndqa?fKhAWlf(NeM68JLb**jBKuX^=vyHMT% z5_*YqHDjgACxHiZfL#T#`(@4zt=NVqQ1|p-%Igk8Oa{a+;Np=;VHu_mCvvT8V9QrI z`xh{Q)Xuz*p0fa1Z>z$RB>)2f(7Dj;gg|J!a$ClJ0tAgl5(W(M6wszW@#!GpfOg@{ zRfF7qy(Szstqznz{Ny(-r-+qNYqqQ6=6DGp`T9#bGn6%w*YWTfZ&DhplvMFnA8(0n ziz`jX)rUIsLFU%|xBxu1xtDcoa%K5^u6R?_`dgyq#?#oY@outl4O<=s_9Gqv3Xa8# zyGqDt#Vp0UicIOF;GoArX(dKPblu|7cQ1qjaE#8EQk0K_qU)H;(a6AsS)&D^Y^(Rn zZAmY6DDL>2>>PBxB1KdE94iLBZv1Y-X#gBwRSdd6S#x?{T(9JD8OcuC$EjK)jqPUm z*0|jPEOzW!(9@Zr{IEv}`(FK_+BBADbDWRO$LBy!EUV<RJ(6_S(a(;FFAgHP<8N5{ zm4(x^Ew{$6D7<N(^DZJ4sXM?LxHwrxs;yLzif~W3TPL>!ymyeA*!juUmF2p<?6?L= z$X{28WoBHLv8aUQ7$AFR$Ex6R*R0<cu`8ucRW+9@uUr|o;=Uu$<0dH!8-rZ#SdG^F zgu46FKdL3v=`f#zQ#y_INI-t$8qnV>^V&VhFIHm##W1j(lAYU$+`!!V;Wd&8Gl-$G zsnx?#c?8_k+V$ho|Lm>y!S=`=^Loqvh<1gcn0EJCBWtAK<$Bu44iG1CE)+Ra!y1H@ zk1GxPb43MwAK<qKX590i1tb(^=PweUhD!eJwDCdo!N0Rk1~GgU(-g0dKaaTgCMb>H z<9(H0KJR=~bD*928s7_U`|CV?q=@s3(#$VhFQ9GMnqQu8{-KojV19Fq!x?uv;W+&A z-6IEtaw*7{F0;nv+tM+NCwCSFMq^>J95-p>KixakQm-5U{Q{gl7g5;Ds}VMZ;g@+5 z$p(+CKL$N~!PH++8y{5@`xo8y7dSUQS|GCPVFhEN1+7lWAQ;4jX)u5@XHUF&VtIWV zaiq+MX~-@3^Ab@TQpk1vnc32QTR+#R;(N}8Cz*|(#|GD#1G!~<)Xl>iuTMp}PK~l# z=k?CQ_l#p;iA^ar6~*2(OLjK*GsQ@6ATPd5yOva*SnICG<hohCJ;nuCfCMMZxEyxn z`V|U$y2ARAE-YY0DO0Vw`pj1rPol!by#=}lDPwAaXc-5Y?oGy)2)TylB<x?T*?oO} zu2(-s*O;2RjtKp>gP>)*<RE`d0mygp^1x{p2*;Lqy)Cx1enol0n%^BcHF&%A;E~_L zi}VX#)hEZIGd}^4yT}o~oLZu@mbyBzwksJ1F1B;3)*58`0h`)2b70J|MvGGbOW#B& z+wQ6DNoLU0o~G@AhKOiFasXGVchn^eyvHyt0DrNz>D;Uv+%n_AU!dAISrm+xG4*Cz z{U-Ua%a)=eOrfA*wac{BkVe#3!6spnaGx{Mrj<oJTH*Zy*H6_C-}lI}(3g5dp+kJ0 z8=N~FeJZwQD>OzSS|m+FV;Lw8maBF{)!>J!rxOYGSI-%JXggjcbD^Kp$D#Vf)>3iM z598epMIWNWFR53BA?s;jgRJuEkdEE}sc;3%tAvmY1xg5l0a*Ck36QC<UcWQelrDoM zyNkAl2RX$4rt8cl9#fMAOq>`wJ1{SwF4VT5rnO2%!j$`q^XuViI^RyWgs8DsPx5OM z^t(SC6~gMIvV?edo_n%0*iSkZA;$D^8%fN}kwN9lQ>Zs@|Dc8ciCfXaFTH@UQn5Q( z+3SJghY+vNCM3<OipF{J<LBb;o`q#GsP)H}IIkkEJIp$3+0dOv+!x|ci^C5m4M_R3 zcc>1C133?0KbZ~m?7N%{nzzJbpM(tJb2`h>A%>Ip@pR#2B=^Kwcjg0D;hNv?TJjX# zK_Llvw-}v$nVo={1~`SWRkoy|UDf(Q1z@m#QgU#0D6#g@-jhN_|0w%H@5+}Le^A0< z{Y}cs9d&{k&8gV*E(D}qR0|~%GveL3=}y4D4P-dXcPd%B_FaeuAv{D+-C8$(TVvuk zNTgF+`NbEN4Ddl_vX*nkF|SKgI!pA~%j>RWR6fi6WAHQn{J&D0FE<T^^h{ECK9ETP z-{1lou{C9`UtY!-QT>YEMD7DxGKb!g#IB;5JO3fP8Wa^TT{s|LDOuBOLicpMP=48f zM7<U?v)7IZfS<s=;-xdL{p8z_*=*&Y&W{IfA1}_8ZgKY}aBCXSC+2WL+4zbo`y|ys zQNqQ{N%4*a`|<2WS8nzPe~GL}CYQIRc&kW3T{?4zywB_AoItUg1zntzm;83bSCW?B zKdTmeg_72RCu~lzYNgnZb^DG9QJZP|yNT8Y`!Lp%Cx7XOBPpU$OWK_n?$*ZH;RP0c znpPa<3*Vt{ln3hDN~bohOKP->2~P5S#PP91&;xu9uZNvL8&8@{JxzlC*?G9P$}eS^ z-?Br0fYfRIg2y;o&$88#@8nR&0Pg~04J=l3_>ORV`;7{<t&cpkoXnZFs3QClMvLfk zdQ23S$&ILI&c#Tw<D_F>ZQa&eU*ASesZHjO<-dkYCo{Q~?%q5g6YnaD;TXC{nXRFA z7?Mx$<c2G920rSeggvdCQKao|;BM=CH?*RYbk>qmBnGBn`_S*uytF4v-8s%zfl%W7 z3eIFs%Au}|I)-5bkgVWTHKpFn%$G-5T)@-;W@8~DD(#d3KyA??Rm{$qo`zLC?O#!D z<A&*W!X1jGDfVmW2c>9VSt1F^VZ?%MVmgzOm4=05u}AiEN&OX$fo?&`$tj*wDMmlB zG1!sg(XF6^ccwKcu;^eb=($g{lM(n^3VeOreJ)IOUdwPX+{9>tWSjG>1Q)v^0zq^{ zaSqCgPZ*$?L(;5XZV|H}x;swXGgG~F)@+=SUYM`f(jEFn2n**@#<+ZQe)7u$nX+*c zy(NL8Kbr4ezFObqw<*zCNI65#Xdy!$W%kR9QJtu9CzRyIKl_NL4gp3<H_j$HTqk0% zMCX~Zt@y&4XshLyW7>s4^wH1K-Kscm1i)Ai3@AQQ>C6Sd{Vb9<R~%&-2k%AGc7*$S z0G3<HC>7YdcSerMTfO}1HZ7L4jIf_=t?znE6ki9bUDZ4(Li43j6Y>mJwDxX^B57&D z&I9=N(ZvYBi|X7=2Ciq;5~ID;wIe&rk8e*<(8aT%b$`U2X+v{5ceTl1_6G^$po!!0 zVjj_{%G<83<$)GLH9lv&sVX~6lAzNp*fUBcYhD)bL3eI!gJLdzQqrmG=JfjP#SMQ5 zH8xGAAyJ_&Xs6Ks{_;Dif;owtm65_-W{Sccg`=%Aop>;UQ9iWM0WnL5uccMEytBHv z=s3Qr0<ES&yg&AFcG8P00o`3v;>Uj6R^%i5$58x(C{?ZVN&^#P$XJ&``}LM2?y7%; zqVt9T^PyLRtU)&=_}JFpQG(;o@pAshu=W1GZD&t<^^B_nzn*-1Cruw$ndK1>b9211 zKx{TJan2acCwxY5b2L_y%#o-$XbWUi(sr4>RZMU*+;87YlsSjlEp~1QTv%D`)evs_ z8iCw&*S;v#zdi1%rg`#GT}LLn<{4V%dbfK_mA2amL&!0es+V5Q4iY5!!mWGh$`5vr zVGKL(_JUd;*M6%U(W2H51oTZF`;<(GPd0h0HGO<J75Yt~bW*%&4*cqbQzuzM7X>p2 zY`$)?^}q7<O=)V06i6rE`SM^x>qPJ5krx{Wnp*ryj;>w1kHUDdY<s{vJaz2_4!N2r zo2yi+2olOp6?l2d?Yb*)ugy{mLK)9}!p}KzN9UP&H#p{YYXSC_lS${eCVh{~POD%V zF_6R3nzL;e3{r`9uM?`JnUJ&4E?t3w4)gz{_B!Rc@lweBX07(D-(1xcq*|_f;?ya9 z31c+CYxIY{2(zc*J7)9DGiM8Oe`<Km;G6;@q5M?>+8*=0LpF%t4Djs5!Y&hIGL#*v zO$*1A>%B;+?-`rP40XkEuq1N9@D`f(N8B=rXt8a<iF|RWw6P^kG03gh!#{T=HHq@t z0r4AV5BFx)y}7SO5pWB!=20{GNUX2~{^aqT4Q&h+KIi$-gs@nUbpd20tY{vwbhamR zb870nu^}CZKov{c@P)K=JWt9DKV$ix;MR*xT3BKUcAHYGKd50ly0mGv?1MCX4rEfp z45}Zk3hoLRX0_k4PyUE6aH`GHd~UX|%kWl=;71C#Za245c8BquBp$(IG*5aq%0=4? zwF`$S5T$gh3-o)Z(`QliYBPa!9V9*MqCzpvf$`%+c=?u(3d(Mt2!MNmV9D_rbQt3G zMaGmrvy%O+4okbIBN9@>F*&=wcouq)-(an-a>I2l`g$-hi5KSI9%ZlsISB!#AG!Qi zr(Q0-GD=Pu)Lh1;#rHigtp(u%*rZ|TGw8Bnsr$W~OLNH^FJ3aAJT?YmJjDmj-CNM* zT!uE8m<&9c`3%}>d9p!$Ypk_lcPhr=d*=9VitRfM$3Mo-ilslQGscC%0p>fE!GDER z&P@7!<iw$^Wc1s1_`iS53XJO9sXo(2$Kxz%3+FCaG3h^K=<zAu)H=F{m~iiztI3)q zY)y3z4?Z_uEMCE(c|v8T?d*sQXYR^-Qy7kaOA7AU6pDKrE(HDuB+U8ful76dW^PAi zHN>N@z#5g%SrT~K2b3M(T@f!3J>|2(paVRN-7Er5%WCm~yD4BYeSDQ5{`5HpN$}z| zc6`r?GqvZ=^?%b8HjQeUMyN=6l%C**jGg3&bZ$(eYM2_N9^*`P(jGWeOYXv9@g!vq z-@O0E?Ti@=khp+U`9Bs24tQgvKLziWY7|XUN(&|6#_$T3)M9rNKDy}jS}}2sT#8td zH<qDB2os<{qEvTc#8a)&i^x)SMbj9=xtsj{p5@P*+!`@7yGq$2dvf7-UDC^mI@j3= zZ+&k6gCp<B0f<e02@`8Vep6~a+ax=@Et&HZinEw-5TJW&&muhN-})vvywRcjn)Z8~ z_pi{Gdr=9hcJ8yNpgz5qMtEuQ+Cc~V42@eYuhu;)cTP^pF}vQ}maH%~pMDbVV+~KP z!S=y1ECarz0ZYt{cnR0XdDo$HdjSr~@!Meqpr?!>s;X@)1o<cotLs|wbX0}?QjlB^ z;&3mDOU3C5DdFkHTSnoIKx0fYS{c2?Z-|Iij=s7lYeb$>TGB#Vj=<I4bPBn|0rhe} z%cGXQ_^$v;n2k!+&caP9hI+>fV!XEw7lzoXiZ%ix<M$PnTAXh2V_B7m6|^fhL6k~z zACz{%K<}B(!plL56TSgDXWYChvlfhpM}w4^m9hMSH>k6UO=<hLfMY4-!avLNZdhi+ zR20ZcC-Br1^E^+DImBkCaGO=qE1z)8Lh8NWa9z7u)TY^2%7T@5Yr5oLUR$$kJQ-GR z<zxqzesKGXi8i!cSB-p+2IKlr$CNR56$GE;)_3O8AXzS<(<wc=9b$xy`FcVvv%I*o zvdR|NK$5bbClKYkeR<AFZxU+lGI%Yo88#}&ZLqnc`i)`~!cG?v<Migp0|6L-U!GJ> z;fX0-7^4j+f_6L5e2nB>70I0-w5u8Xg?~hZj8bT+G9Sa|km`pEx`!@8>J%YjS_QSU zTv1lzR0=^GP8`9D)_CmGWs&O)UtJxlYZv-PCr|w7PTq1*_ac^oz9X9*H=qC8nhaEg zXL^#86h$c`nzs(O&iCrA+<3W%H$8z!fI9PvhoITy%^y}wMY%6EB$uglF%EU(#1*1L zqIj%WM>*M4rigmUF?Hq&Jw`M`q0oM^tL4fZ6?ZmvE)wGXBpvJW+pv|QNv)8<^h_}U zKT%bdPr<CPfR>hdj^j9@kqHrmU&rHxiNHyU?L_~$0{*(+tMSQieG?$=+WAe^>obs3 zKP^vlCe33!{(KgH0`-e51{v8i`X&ZBFHC!62H~KRUY`noq+Qviz9Mav`@ZmVm|ST< z5!;IqXkc)8QeDqqPGMN)&0$(x2YErTe7#>#R2dJWnM!q9G$f~Tphz^ZE-O5Z-h855 zD0~9C)RCWiZOx3636j^`1BVeNVna};S}_(z8hCTs<Q<UAcK3+;X%f5Pz`Gwp)^F<) zmBqEo9%!Uf3QlZ|lD9?+mVmIby@q?ou-QaY^{<zu;TXgVS{(R}Zi!Yhna%_(+M3cV z@0tHWa8t(@r3At~-0SGDt)hkgmJM)1vNoF6^0*0J{F=IaD*R-LzFjgjYHGdOdyQ@{ zzSJ;HqJ9gUGL*?($16kFewNf+R1i`FLx{#Sy_RLr=W2VsZ#EweW9NsvuaSO3OxTYC zx*Lv|F}98a&STgk?_CVF5(O?g2liK1VnDLVg!EY@x^7BU!nAy-Xr!}<*K|d-w%EF@ z6hY^)4mRH@xVBph?og#&Kz~Y?eI7wLHv3J+#o|@^JxStp{y<L)PceIpgA-Rf*Y;ye zWK_5k4_N6_Ud1IIkjpgI*`}2YBOfy>bY#1lw_^k1-#M|@T~xfc2!5GLMG2cxSH#ej zSJUp0%u-DJETQOjzc9S<BF!Dp^`0r>rWcvQHhgpwz(%cDl!{%zwd>C`P{_xf>dh5q zE0Kj~+n85%&OZnNXwSjIZW^0&R!+jbi~N#Ob{~X((tRO%no+a~mmT41q+;8gnR}Y~ znR83>z$mdW?<FL$H{3qZFL<W})S0;AC%q7vqpXgy8EU(}V=98vs&<&DIwMBs$)T9C zP@uvOYuw&bYiG@7TJAcaJs1!AplO10$mYyaUnB5B4%0Y^p>EP6MNY~J7>lUIL-E+3 zxo2zmXLN(8GaUcZfH{ux6xE|P$d1J+(uFxh0sFD@g$x@vX`aU(*iY>uHNUR*Pr>T5 zq0^?sffh{>i@UZ(lJLbDDm<2YY{h|#^_5JAPFFFc|4BHgGx|{BxBF?*nPos!7N|Lq z`sQQ*Uh1D(7d3__TveAUXQ=Nn@%vmIL{G4yc-eT`9Tk#tvG3es5tH4F4#gk|-CU6B zp61CYAR$Q(ln8+0i!RBJ(k>^vNEE(Zb7RvN?gnQ6hC~(nMdn^3?_)~)_Rn<cpJbhq zIJ(KHm$qd_tP9<Y>?!TRjrI%`nm9t^|Eb?f-J&zAm0cIKaSJ%iz4~UoAYux;c*tLl zq*cOO_YY^kL#{kjxH&A#>{@6)NUJ)ZeM~7>Ujpu%9!fxWajt|M9(2Vrx#3J3gPv(? z)`zXybZAd#;We*Q=#)wD2OsjtotUbgxr7<DMe~qXE}y|D>jV=9QtwMZM%U(JD{>jw z@Kq6rFOF#C_)Cf$hxTpb*2i3NtR5C+4X4AweE1m0UpEc6x^CRe?@C&T;DZIYcg)#J zw$!3ofyvm0E^XCcqsCX#0oAmGWl$AAxT?e=fG^r#NAA-9WO@2J0c3Q6yt`(6YTvpO z6qYmh0?Kmffp^U(U)7<t2-@NCr$ou<AEqh6z)F}cQS~XIo*OI-&Z{qKX@^fA)%%p4 zO%MeEsk`N)?YjlgP%g$Nc&v1Xf4If)$fm%vM>uF$$vYOZ6At*bHM~6}laIvOfxJ)H zN>Nv@-8$q8u>(b}mZ&96pdb-PDI-A8oWuyMXxvVa&njA_@YZ!L-m>P!dXdI0hHMu4 z>oY#xO^`w|e=~o%et0DV$d~a;nZJ&|FsV#h$%HMoe_VOUj39Lay9}muy^?n_UTn{P zmE&(=<MgdW^#pK4#bitKqM0Ww9wQt$OLBS1=aQO#43qc17}<(2GE=9HQg2Qkeyjqy zm9r^Cm$<$JuzoH-&t@{<8%Uw>@+fdcmHAoQRoPP6s^Z(VcYg#YCYo=gC#zk>TRfyF zCft=NAg}2j9ID1+TC#igvCv_nbw>-OBX7!m8v=R`-rH>qRtRadhu`n|vcjSFXgiIN z`LpI~5PBsAMa$_7z&1p65?xFVg~Z1$rHCEC%bAozI-?anD)|M9j-@y_=ACvEFlwXa zSz8K)n)9#nw)6w9&pIEwEGt@<YlPpmKOY4Eblg7+I?)4kx?=7cox)hlZXDHCzO%ih zinRCIJ;28srM95o!*Hn*nCC$sIZ*WUah@0f!p&ax82jL?ZD;b35y3)H|5q6>b$q*` zt^@oH2C47Od83Aj)GrnKGmnNToLlP+AuL|YZJ$14VY|F)?bh$PZ-`4j_yS9Gx^8v* zEis3GwJ?3j`frdZVrCzQoxk*ru$awNC}2e$<i41#&G5WDo9x1`jQ~_*@Wvn$u{DTr zgL}1BOK;kEY!tHVyl++css=<%NE7I|$4}kAe*J<o9qjUe{*JK(<d2q)hzVP43hlPQ zcJ9U3{uUX^nPtPxbFdA}DH*TYaC@VeZS9BIea^0sBaVuZxJ`Y~)fCy$q@iz#oDgi_ zrXfz?rxndhzjs5L3WXtYFqJi81Vw+>(?8dT>|CRtZhgJ`IG2_%3Ug~_0QtN>#h^-p ze-G$K(5*f(j;?&w3chd<jRpgEAs;0v)h<`(BTA1^7WdQJ;SWx!T<_jErl)tro!vsF z@0?_Uf7@_Dx0oH*fr)aw`T?CYlj7$N)LDaq=#NDnExp}_2&J>-BHR`3c4EwRWf36M zn;BVVYtSd-jtFRvwEty<3Z4p{=gGNzKlGAxC?{YFqG!wsV^+#|Z*kmxaz{@Lp*s89 z$2U>)>K0kL$8*tv3Ic(9bM=a$Bejtu-yAJ@)yRO`ys+5?io7PNG|WM+wq%lPW${3x z>_<q&q}uZqR7I@=U#0ApXr_Hvdk|2hqUIZwBJ`?252&~g&UQk1on=DP4_0|j$|mWV z41F&0zGa@0X7T5HOU3NmFlp+)<5+f(R%d=l3zth*SMs~@dK5Q@E|TnHx_|*<7VRek z(D4dMp*o0fuT2;<z#X7xc1R)PV!hd7&~{8ze2fnJnKg^Gcm8#VuPLFaqMu>xy8^9h z3SBP?PV`w4CT@AlUK?gr61DmrKMAS6ywhcimJa#MH1iv_Dl>*3P5&!P;u4;IRq^66 zO||EjPCw-&fy0tRB1Fev0A=PVvfe+Z#D#I}xA897Rh<wsQ-S+vdboqw<wTKZ+3EM! z4smQ65qb45*1!zAL2GxTf7X=H&8Zh+B7RqbZNyF};GGql*Pe%9{oTVk=A9hvuQ0T@ z_rW@9$_UeIqNTrMh#~nAj1k+3_?r>)URk8k%5S{!x)q^(=4w~2;f`4wS=GW}FU{<R zX}hc?cHI=0!keoP{5SE-7udz$upgH{bCTAZL7hJhaY#FA#S;lraooW5q&N5R|Hs#R zhc(qLZ=hHZ1qD%hRq0*2)F_}d=^ZITfGAbzJt_hMp*N|aN)wO{QUwW}P^I@0dJ8QO zlDqXgp6~pgd!M`i<_UYvT5I;qyzjijkAe7y1oD174VV)u*Yjl$zliywJ`mW#<4Ra) z>&PJmNDV6+@R;kk2Xb~DB?ew?XLPlG8^tf<dWMo)Ft!OpxC~z#0MT<w?f{*~=N}H9 z_a~TJxhXR#bVl0JC1H`v%HC2R6*vi<uL$sAS4~^PK0o;cz{0sJtj<!KY($osc9^*# zrjuAX+Q;~5erbg*!E&}|fl$ZnF!L~0?%H&btx~R-iVw!0vpsPcl_Ht}(D;ubv(GS+ z{t7kf{!!8#s$NY(oOH*+At-b86pe%ik_a8$V`k0=Vdi({)p004k;}-K`$;M(N>@HJ z_WPth`0ewD@}lq)MS?yU1@WP!?wqAF6QTZ|wV8{?<r_I}BK;>rFS6xki)@n1yd;@u z@{Ad<E*zqs(-$bRCKUvWk*15~Kw3ONg{HST6Y-3+iR-DP=W8vir`KE4Og%;Qi7?A% zR<MLaar9|n&NCqt9}ZWbzn0)?uCZ&%XDwQ8=>RAn?k$_7epn-Ni#=9r4DOm3shlqF z55vo-v$ww}$s;R)4!+-WTOIcCjb7f-mQq`49(uTwBazL4^Saay>8Bi;G%SeLJ-a;m zJGYx>UtlM7s)pzwwoceQXscu9&fifKDLZ#`a5tZ~L2Nuzn-t=l9*_F<v9)2C{P-kC z#BY!-@r?OB8nVp1)tuqNtycdd(eW(fJQ(ZeL7A2eoKcX@i5Cj+U$UI5gGg;L5=Q_v zn0{jZplChp{Mu0SwQbWH;-%~(DU!6iE!+*`T#?Y~L7xrDvz+eRvbjA<yr3s1OW$A7 zf!LVaie4MzQgMT=PVHlLs>S`U3Wtm9Yv|W5j&8Wc&xJ<1`@?X#WA_Urf)ikO(;2b6 z+nt$JHER*_aR`C~t>N84qEA{5{ZhRUdOzINA=6C!pjsRMKj1T~Jf|BJzro`W0&)A2 z+GyQ{ypX*}OTQz16!E1N?V~-utPFj$TPCmoe;*kj!D2msfhN;M@qBNZzqNPy`?y!Y zRqAHe;L3MKwPs5f=p$ECfhu1%SECcLr^%v!ss*bK<JzIC$@j_0C0He(&#Du~=7Ca_ z@^=-#SlGvnrz-?!kh`Xro0T8zb5Lw~D=;~ZJ&!4ruZ0zU$*xU%CM&PKO%cA3=1S~b zCGfH+kfhSqnZ4$wD-MD)`O2Dy64)=Q%MtK@ayKKM{{*;1Cj*#bip7O+VtjA#H>P;2 zD!%M4v6!>AO-n#NKxLa+>5hQa(7R^-t3e@xU3_;2yE&>pKZ(wVN7F5CZsj;OD=bEs z-%*TSfU8)BTmb+~#n;XCT_6}MAD7yEuSd3)r=V#xzV7KM;SYv|EzXl%>5>UoIZ*s* z{+rM!-xmjmy(S0JHPPJbQNfkDL-kuHBeDLeeg)8-FG?eQhw9B~uBq~iVK+tby&Ymu zRdMp!oc=KV1gCF5(y;VIoQdr^hZZYB+X#Khb7+RqWOEnt_m}P6)t&%X<8~~PhjYU% zX1Y>J;K~~O#X6F@z(2`YO7fy2-gT3Mb($%QwpN`fa=YBHfQ+Tn!e7ay{^M*XG@Cr- z!AMAM+@rZcMagChLAL{@@`#3hz)@n{#Rm93d#v3J5g#g}Kx1@fa7l9;kNjLmNK`$6 zpme4x&VN%a>-hn)hi9y-!q8)A!YiF!IRw$<-g(k~jw&71#q-lefriG+L0<&nO{cUm zQMYU(AAQZ8;AvWq7-F14tpyo~rCm=0bDp8Z&aO&5+uZ?1hQ?ayz%%Y0=em;3bVW)X z4~7?l24^HM?*AlhzlXK^`MB&CAbW(R@s}Td{eAD(tUUjT{05}P@@C{9<e-A0*-zng zCaJtXST3!Nu32rEoBovzE{#G4A6TB)w1ks4zZfc;e1f`=q=TOn_?Kl>?Tg4zy~g(N z!DX*7=S0pq#2h*viNyM>wcnVGu2nfi!UrGU|4oo<N$S$1ok265J9mWIIdE-th8A%^ z-FH7m?hYGS=HX+e3ME%t>EVoo_?x~AK%{eJ7Y<g=#0KyeHFI<w%SgNrR{G%ZB`i_t zJNqJ(T;e^yr}=&5dQ*Qs6IJ%@Ti=Ihd9Xiy!dO3d*Fjf%$T#**T#GB;FGjP+zCAO% zGgmYWqVJ4qR!)=#=Yxd1vOblG1G_Ax-0rK9j)l0=&ayU3@?>SEbJ4azhpnA*q^a^h zQ4q1P<<k+5KXdyscpbgnpppkJ8gAhmUHl0`vneXE)P3@wZw`8v4x*+Hlmvc_F@c^E z=f%<2h76ooQB)6!oS{@JaKV4&t)j!gRo7`C!)EM5J_{1w-zU74DXc}+b|bs8_AW4= z)D<gp)Za<rFtt&;4-)#<d0d6_6*|>*o^8X(&(L)3{kclc_u__1<~Szut4d=jxFr;w zO_0N-6=Ny~Zp%aUyAEg1=OgVz!iN-X>ohH2QJFroJAZpj9V_DryLn>{PPTr#Nh=J6 z)I=j?taQb6h|IF~@i2v8=EfgwX><nGAzzpa@iCSv7atF<Tu3V<eFC$Dob@P^*1L_E zx|U>rJchGlFq{QByRV<SUl&bL?(<V`4F{D7ipaXKx*f*ddy2aSnjCwe3|tl$DX$8x z!{U93D&auK+E3q=0Xp=TlqV!yyy%+4XZ+5fT}KALm$Rxf^AI@-+HcLn!65UzccgeC z@9g&IjuiFXiO4lk^Nw7=R~szc3|;VzwN=l)A(rf@x_*MxqsYaJ`gxxZinkja=3*!s z<9~WOUy<lSaz>r&O@_h04I75cY-i1npRg+PHRXwWW_~NBsPelASgjMP2F1fp;;k}g zBuRXgGw;3?zF7L9p)F>+e71Ic504HDUAaIblU!>S>5@N|DwRh8(*?5vp3VUsGKwSb z{ZCP(whyC@g+lt*Qz}p1C~tXRxdBj4nD58t)5C{B`TDO>eV_9?fxV8E?!jZZ`+WTk zn=){{cguxCM2ptV?ZgKi(jwQ-4Y<Cutf5iL%9c@v_nm^&Iz@yM%E67#=Li>5BQwb0 zI)}Td`>npK&7Wtpu8j?59<}_Q!19QNmOJ}A*ucyYCV@=ooLuUcEk7s>1n-_52l%8V za=~#nn;$k)z}qk0t_%w>e}G<-B?TD9Cs?%Q9Vv1;En8o%Y~o0r-t9(;UqXpFYfG-- zVv)|eC0|xfRQ&rTLiwG;55DxW-fT|L^@%d>xx>xNcInQSXln!BBi-T15{9{~qE_Tu zYmRdMH`t`nZXqMd({o=Q=+2aV*XXNz?Z%~vknZ9yYBoBoIsKn_%YNRNd?;78!CCiH zku42FMtdjN?pfkKvQLBpA5)1IGiCi%KcPn-NY|v47<*m?&Vo^-t}9aeISps}J-1Yl zJ}P>pD=)1S`{L>3n=h7LBog1-W3c1(>x+k%y2?P$ZS3<D7)vd-kcZ~hd-1jl!p^-J zTJf`vkJL%^lM9w;W9aiJ(oB@wvh+CO7H=3xZAX@?v)yQf4!uGri5S0{ZMwIP+{~G@ zW!qlXVi{gf>@+@?eBuOeR-VLA7dQpiXx~+C=lCc|7QNK1sj8f&lnC_AFtMWaZ|LN- zo^q%KX;*a<UER*m9cGurhQ!FuDQlJLye2q0;gI8#>Sz?9>vq@fbTQM&>nhIP$rzX` z9XWOr4{ssf?k0;VcPVj?XESy%Z_e`Lqu%&A5X~Pu$84YN(Lv!ohK4kU$@YCwoy6Qq zi<@a>FI$dHn>(TCVK2lQoOy0_U?m<r54qJE^St~Acp15}#VWs|C~QU1Xfc;Tmf)={ zzVp^iqauDbQ|DFd9Gh3`r0QXDUS5sw^8@z#y@m`e)cHQ7aK0H=h~}A}H}&fcqZky~ z@xa(mdyGWd;}eR?<0I*$Q61ZvDRuP1GrCm&)G&oA33uulw%!q%a02aYsp&eeNqJ_` z?(=xx2Zt}u#z>l310`?YtE283^NMUbI%P|#aye*FgooO6@w*RlVAVu&fQcm7Sy0s0 z;@sh=QDHvq(-Yk3RXS+yeP`#p4$-%#%=1hkWf78vff`PtDLZ#()GoYIXB7(JpmkS) z1HtcOV7;O@AH2`)x~}`Gy-<c0R>V#=ztBeQ9txU0&#p=8#llzS%!}B})BdK{-E02G zfI2iiawmj&kP+0H&>|_G7GH%ejGvp4+(y?o`{8Tm8la_yP59;XT=Ti~y1mKO&*<7@ zlQKk_br__;1q#gi`}6tP!Js6+Cp+q%vwby`%$JiT^kB@pUP))6EZA5*@YI{Um=fCW z6>~GEjSO4APFy6Xy?wRnp4pH63#|+5l1jq@8#Ylr6-#uSH2ht^``H*=eKO}+%z-gf zP}@m$L?kUx*P<y$_-W<O1tJ_{$pOgYM&vp96xa4H%fhK&+ED*!%WnTY5ViI4+0V0U zbfey0>Mv_lINaoE@xPw#6sczgs!^o*%Q<ghLUAMY6U;n}rd5`=Pfe*ikp|(G-TO;A zS*CgETft}?=ca4SCH|c3C8=Le@0J_-&(g1;8pG)detohTlPr-7Un-2zm3rcYp{jcA z{^9wO4n^*-$cniPr9dsE;0#HVV%Ku+QPOWIq<#16y5C9?*T~t@kCwZ<s*2S(IEKp= z5?!<_%SM^dT?%lw#+kfg3-;KoWjG#HQZ(j3a?PmaWvd+UZ)P?c^h_1RO&1FnR%PqS zar#_?f5>1)ckn*Hk^SwXhNTIAv&^KtaCoU#40qg6ekgiENpYb8>3iU?@290yTs2T% zF6R+k+&ZR^Zbc9#+SG5nJZC=SQFJ=Px|*SxPEvDhot<37ReO@+pBBa*zAP3$>EUb_ zSmo#kP1EktoZ(}2p=$O`dA(Z|<I+7Q!8N$sH!0zz&V4YInzMd(IdJB<4dg+x-jg%O zb!3amiavIGewz3=clgAo_#s&u%z{yk73HR@O4654H>p}ug!?%h`9wA=MW_((ZW~+K zM%`pE^g~4Jd`Ob;@QYpEd)qG_C5Lkafd{4P|6!oYTf0&}Khr}Y$XD)Dx2v5SttYGc zh=qT1u>2Jc(feo?C%c=B0Y8iII}slS)${lxj-D3rSN%-wD_&9YJH<?)E?6DU+)U{e zM@m3sINH-kKywK|R==qIr~uIW2hEQ)Z%&QH#PLGZCpZ{<w&r*3PUHCxl!k$RfCtWc z%+{ZT;@DI_BQ0ikLY$~%CD3CcrsrvRui6B;(CDTRe{tQF#{EAn9dE7)=|1x~B4hE% zGCCf@)1&)kmgewB-TTd7uh->6u2eX@G%aJ9%<AVia|;pNlD6x;PS01VkQOVwnHLNC zZZ}<ja@E(3-r)U|Z>M((8NuG?yBzAv<Q<XB$i6-q@55K>>gxLXzZTkp$rv7e^VppQ zX6b#&%M&pDPJyE(B(xq-<-X9Bmc!-$6wa~Fz52w0ZrwpkmxMXgM5S6dO6YzAyH^l< zD0L6NB=vn)^OnuD{U5C$=)>{XLU`fgz0Aov3JFm1hc-Qz;+sbQv!I2K^^z>(A=Zih zN54v&J<&`hZv+w|&Q}(m;>T)t8g|ymt7(4SZF_Ekq98QAvv5-Jc6YYVV5z&c)UoVY znjW=xf7H>hskhk#H;HcJVIMv$%I79w<+F)y7^=?=$uU(ez@(4;6G@4g{Q`!jWS`T{ zcnr{ZH-b5RH)6c~LUj6DhC=tX;%HRzaXj6s_!~1Z=p8cJKixs8?{CHrUL3TY^JYTy zu9-f>rAf(pZ9A6v;+oAdP}j{#r&5qK{-CyNtoLFo5j^)@$M`)D`J5>v?BzNxk<7@6 zndzCQPtc|L4^q1gcYoUu=%uI$jbBtU7;ZbK608n%G;<}z`D+0!6%7nuP$+*5B$--{ z)j>bJTX6hOpHT~KXB6!W1V34M#xT6$V&iuhc7pdwl*i1k)XVy9M?{*{>C}bt)S(5c ziotUYK0x^yMAJDTB=$L1k<2Q908orXs~qKR>}jxm)soh}{reUEJS(oe_`_pR6QD}; zE)$Xu+X)0_9*g0#(nalO#_gUpdUi+&Oczx2p6><i%#$DW^yAvW_+u^n7JSCaC5LNj zE>mBw4t>OZE1u(UO7cYT@m*_PRdvX^rE)d?_Na2;^2>1d%c)|Q`xUlu7#z<;+VfoL zXI;i9!DD8`j$YBb4}TwLx_F+3i^$&^FE7`Ahf*yh0(4YxCu8qwyc7t!G*^SyFvl!x z({E6vj#Ye6V|H7@MEW~Vo<XYUhzW~}Vmz=Fx^!V|lX`@KX4SzOJcWd{Q%TRSR7{Mh za+zmWo@mH_v2WA9%eVV7>A<$zlDi6&kRuN+Hk7=%bIh1;ae_23D=1$SLil%#6C-4; zw&)Q3j0fqL2Amvo*1nX|0PQ0_adOARUZRdM&3pxI@lG^85oJ@Rqh4la|B-JaAlNes zQb47n6HE0Y>nnUFKDDk>H=%b^=6rS%!RAd1qtKbNZctjhhWY8!{X-J(gfg9BWIf7B zqfGJHc{$XbJrpy5YNBiWGGTESzvaAs`AB6)m>`z*(FA{J_7y9P_=f;C(aX!#MxO## z#VjUCu4GX%y&yZgs0d&do0y0D-BH8)(#y2?-3KFyRr}efJy?>&1%o~o9fJ}46dNWj z<D;+{?t(oMM2Y1VgL01nPxay>c$xW-Tp4Li;wEjqLUF$r?80RBR&Z<a_xBs-#bpV0 z811g6I7&y$EobrK`i;}+C)sbqC%ISDopNN&a}C`{z@Xf0Dy?4&-AWtBlrfT|irx9- zJ20$5`7-aultuyEqx0PNQn3u9SJaoCO9*0`p4_WKQe4~1PBisO+S?G=_Ln?`kmjx# z<hcD#k&!mayGqi9=DbIf`7Ur0{yYQBfKg{Ly(#U(0u_9gw<?eYDPHQx2fwJ^=%3~p z_~WohbN`J*0qlj%Yp;FgW`?7!@Zs6hbuK)*RxKF<Kk5qefO+mM-H$~EEW@oSUxgGM z(slQpwGljzd3FD@5flfJ9WhD{45;ZN^^)+cVBFHDBb^0FxiqsTNJ+958jW{b#qd!G zDj!w3r-;Q$F%n7+9wL!LEO4{fpI&Bd<L2wHHS1aV`2)%#m5dLje~c5s9Ab5^gSSkb z8y@WPR9mvDix21wwoBI2ru2_rIgl*VMR_Brdg>Q6YaJ4GE>1*#_1}BiC9F~`cO9%D z<X$W#kGb1zSRSLBH?B(setmonayMQ7rc$R<(%J`W%r=Z~9jDOVdEiu3^(LyU3MRu+ zP?1=cL~+97EVH7E(Jo)M+&H#EXs_RRVhL~lQo&VKl}Fy3dE*#_V1jHhCHL~s@Z{Xx zw^J6K1(ili`4WMljnC40f=;9Un*5!=AgkmUzHROW>fwubUk`i1qoCA!yJ@y3PWZKR z>QY+tv_`Yf!lYNJY1%1fCD0$`(NFthlq=bDHVj&SkqT;*iaYQE0KNxtM#288HT%*R zh_)*al@(OCN}ve{P*I_cwdfc?<G2>UOBkHl<`}8E0Qb912~=DPR>_otac0-AGzGP0 zjtNz#;WibmOJvTP#<a{Ie?L$~EaqPo5{oahK9o#n67>%oz$qXK*96y2l-;|lqU5RK zAeX^Zh;mwbzAoHbDZYgbEHhXjR&}|aT+O0{&?*nZwv=xG^wlwnH|HaJ*f4i%tMCbj z5NUAnfn?_KZQpA3JLkp0inJ+6!<z-_Z_RZICTjB0rK)EPY=>R}IR<zZE&MI8O(sZ( z=7oxlr}%5^i$K2%qjBz-vbz*(_35O`d_%?3CIQ<pMz&br;@h$pB!$wZ`7T83C!!;y zV-8STv`^t4KifqD0uFzM{YY^rz)6R-KSRGjs1NbQcd(9n;-x!Y>oh>qr9L<Qw<-Es z<o&@qb6JnzIW#Cbp%`vro6=r8Bpl|}Ph*kfp5QfUG!2~s*qiBHr+OV7Y0x?5U75}I zWI=|qWDU@SW%t!W2@<;m*_<~7(-mp&KeNegz?Q8VaT3PSQ$}?^)!z*VQx;|ogA%nb zhtJv`PU;flw_@{8QL4(h{(a*jh>}>|8#Z4*EGEJ4*qX^#qnW(-S%ealVJpJN5`iIR zkB8i@wWk3xMK`^Gf<6;MQn?8C^phwhfba?o`o}8mN$xR%MJu~5CgmTdZ#<74@rpTq zp=NVnJ7e@{Hm`F*4|XA6zITWCN2971hA<Q9#HsJsX2=+_Ij1EVF{R{Br$i3Q&c{lF zQ##S0TtiWHnl`1F5`zJ`K~QAI-JjcjWMDRm-3yO9=dkBT#jeI0bEgot-G>Q^5vG!w zmRMo9^RoB%Ddz~^woSK@{|N9A5cnnlHf8ZYL3}zlPfQ4dq7R8QX3DpRRYRL(O5b)* zY!5#h|56cA@D+1j(cL5?fR0sd@;;_coI@KNw+zU*49MeovnYS@>h&aNB8OBYg<RJx z-mwF+(MQsPQ5sd5$=HdvQv@eEkL^|fo=Qh<Bb4qV1p}5n_a<(FLu(%i%6&9m+9hGm zZFEQR0Hd)y=h@E&@*;1njlLY@5nb09>?{R;8iW=MCGO9=_S>-Pg$c^#hY-0m00B-M zws2%~kX4C^pOh%XB_T_EGqcLo@x3n=k(}Dz!h~*8^V6UgU0J)pI8*UKz)<KIFRB?G zLzNVB^~~1i<LgiJTyPM!X_{X{kFZANn!Wf`wLBlH@V3Zhdb84O(!Z`?zQVI@XR?PS zdjdY&ymulHj$LAjlzwv}Og4MaDlaa3KF}8ldNVcy_1%jBH9T63+$~dVI?z9v7H)9H zf2I1~YiC`rwsW_af4W?A5KJf&RgrrV@?M=Kp*@(gdoL8a(}yvcOz{o)0Xk=oz+r@j z(s?-XL7z_-ZG>{ym-$M^Uaje?I5vb=qC{g>Y6Oo3b7imJrW;v@({qlwGO&gDCor5w zVIa@C666c|j1D>FWu%|($OK4ZYvPEPE-5dP5FK`aB6Aq}+hG7A?Ys(zF{E&Q^I}O$ zMsX#Z9wHO9Mci(J<Kv80B>g%bd75;N<H1{M${Tlrg+fX3&VAQJ>OMa6xdHB?_$ZLp zlBktn50X58A4i)a<$-rL=1AR;&c1l|*H{F;#7-DUnKYKoXU*k!03wH(Zd#5WoZZ&L zJCx36<zAZ<TnJh#a^rfXL3sGMKjGc0daqUC*ZJ%Yt1A_gz$t2eBCu^)mo1LD763g~ zW4J&&Sg}xd>oCtfiOikivAUyg&6-OW!7;`Wo`<7dvE|QdnV-|tEmp^ysB{CI?%nw_ zv=a2fMW+3viBnp7$NiuSrMi)ShT7ybcyp)V)I93AAv$7T9pkd*c;~=)FL;khrcMB^ zEt3-^kK+J)6b1GG!i3>DlI9NxFYbE{&cs!m<%M?lU$_v0@oZBja+i+<L!hhQ4=KIY z?<^>!s*yO|iP#CsR1<kCk=As38zuZ~NRv~sMFQV3&ism?EzQxN{OLJSbU2wN8VkEw z*CYAYQtwI^+yEET&a$w%xBPgN=*BVkTBhgKg~$C=vmjwJb`D`o#nrSfh}a>LdD*($ z^wHEZv=wwt2OJTjgObwdPgMJ%(0-2dGlupx=hBYDG0+RH)LO%V&-KdpXITrfJ3t`i z_0p5B@U=^!(YVBKU4(JGXZq!FPCE0htc2lt0|A7LZ+77AvM%6qcv(Ben{%D2=Oe&E zZ?N6*N?`Kv{15?f51UfYxaj5|cVG9*&6;@9`oo{6M_{_Eo$tUYIrct9#EuoZg7Y5s zmZW)^t(W>wN&MXnP7eCNOPmk*M>#?16rh`Zw@krE%C5uX3ys)N6%1ygQXeIYR9;ip zuD}@^1hEwYLnt^h7fZwZusWt}jwBMhw19TnVnY_h!z^3SPRm-$djeeyOqnB8U>ZPC z2f7N-s1XSyuNe^0rVT3EiW<1^dL?y#7UcCG922#QWy3xBQ)D{N)~w^cdwqF89_)g* z{~{Z#)4FXbv?tJg&ik7YF*U2Ied0FMPY&~Y(rT0pU7}$7+9cQcZl5ZxKxJqZ&jyha zx#@|!CA*C<k=zh}^`UOrXd$Pe$P`7J+0Qxi?}X=uPk;KoYp#|;-Q7PNma+#=({U%I z`tWp(I?GibYE&sOU9>K7-5H?XnBIhAtonyeAu_L111ScwvUmE}xAhMot0ho(LqL8a z;1GjS<$7~shxo!(ehH0ao>pJ6xRbdUyM7vc^ZOC@i7dYdd*JGU$>SaIurlS=JA)u$ z?H@d^$B1a{7?%OeB>SXfV+>6skeQsQ^1<FI!-_qSLP16wM<FMJfx~UKoZ<#pVq-va z#m5ZtGPtDZ3(_3HX$?8EGwhE$cg~yRQ-@QO^vTMgOygMk#KD>HN0I^R)pYlJ&2a5S zw);p@H?t@IozDGknD|fQpyLg*l_es^D=Ftpl51!81N%2UyFhtG6tD9uPEF*37jJL( z20xaHBUoiOMlx^34gn?j0vjpz6~rDg08rv=ieN>LS!D{u8!V2xa)PTU;?7B*#+p4Y z;?Ecx(>(a-p`5=8d}rC7&l~jJyF{-V>A&O^(3%78{P8>3RHQJ!i2tUr0k3Ps$M@zW zmF+w^Mxu0Dj$c>}7SX0GsrLs1w~+%T!>O!wz@uHyp<Es2o~Q_L8(Fq5m=75ccVT|Y zw<I%$LFUiJFY8CQ?6Tu~r$)q;93cbm=AKMweNM!pTUO^hVb`|rrRj6LNK?IolU!&Q zshaL5b;CyE0o>@%)ABm-&oMZ;SsL(8U#)OKQ?ZXn%6se58>IU+n{<Vq+%kE@%`{w6 zp$a#rkkaO5oLBAOCR`vpl^$^U2vK75j=WXR__8Vrd3udj7jEmPG#dN4Co#PZ0SvDh z;vW}&gPC>2(l$MPwQW$@1q9Gh-!48jm}kf+&EfJNF%>{pPjC{1N+~k^%?pa*&?nzN zL!^z2n)-FU4K1$TKqpzv9HBL0mWw#`lja7cyXhKZ%5O^n;@J2ICj80WZuY*&jYr*A zoyoyaDtB^a+cSc2l&6>MZQysOFrS5zDr2Clbpbo<ycv0S)miZP8*EAvDuY|lT+~Tg zM8ne#Gu6Q*e>qIhP)JzFBYw8xZABq3;_#Mdh?s(YpgmknGY!S&_SZKMm?M4*IrKdC zG&i@n2LaglwC~<$kAdc%Nf1$K6Pxgr+`nI!9Ap2<h}=E87h9o;A{82+Vx?^5<Ug~0 zs&n_1UW{gf&NZ^=lP=>qZlePZVwoA`4<qk6l<5T6u57jV*d{TQE2)MeuQKH3M?GIJ zn4yG0b)>W3h!ck6O}8_{p?A-)Fw0RX*!IgU9py^&_DC1sG8)dxfvui=%a}ud)iS_I z=O&slCISE0*hgxH{q}-<Hiv3Ip?On+f&$zftKr~#EG+iIS>t_5Ec8B#SN~JiBj48t zNks)s=zqPuz#pZJ_Nji)d;7;Xue1<00{%M&S*mq>gReig^1FBpDP_fjX?6acJDL52 zIa`kLd1|$xi%yKm-xKs_9>mcvN22PJnY=yUTXnHjW>1Zj3j*|vxyNLKF7vik&q+Nr z$)Gu=D5`E6-}Ed|lu3!$Bk@6JYg}+o<+*SCo6nZjkhi){8Nd3!NOmvLDc9G_4fXRK z#0^rDfKTsswN~T{gW^+3noP1gX`SizS;F`0%wk@wGI(F8DhHYmeN)v)NdNy?j62@9 zBmOvJg);8Ll8}?f_5bcJ!A*)k4ebrvFrqt7$cF?bFHexrhM{z{MV4{$|NPyXv&G+1 zB>!U|cRY5OXS<HB<f;CD166`|3;$d#C#j|PKc|Fm5>Owm{*R~)K^xg0KQ!x(xDrwW zp&{UZvkJ%LT{Ux)1O@*$k|UUZ{^!tz`2+#tVqL3BI@Qhc#UGtfn|gMM9JOPVlnpX% zEiHF-@1>~{KAGK#R8L^CtBK2Nw1;Bmavp#$n!K>i5FEx>h4_LLTod~N;1K<N@~Ho; z7YO=FE-H*~L5PiAN1Nv1E9E**eGe#aCYAEk#Pa*f3}*~RSn8bAKiIr$-uI;Epq|<z z_g7qK=je2{3fzZGv+mhZ=lSb!M$+t>;2klWa>11F_-^WiWL+xKd!>%W_B9NqmcYxz zJ;>G?Ku!YD;=k3JoS<uYlpp|dg83mn!!>KiklGKMV^r5kNyL%n;4K4~sdSFazv&e9 zAA{}Cnw9tTUrzQ)n>NTcP_(mu5I>q14b@i~7)FAMT-$Hqd70pr@vG6BvTuw$7_2Ln z9&fhr;JhZvj*ky24YmZRnFQ&=7R|RzGuPox;4QrpAtR~uqSp(NwDp>X&ivp+VRsU~ z<+^u;Gu>4@apqBnQi?<6<&10ws>bs@+prmh`hXim{B;3k8Z<ptU*DCPAVO(+EbOm< z$)X(G-=&o73MU}PsSsxOJ^m~Fc9Z^38*44Z^9TbmA~eq8PV_oANpF#|1617n^1V$9 zvg3<~er1Ky%;GX9VE%wsN;XsD*SDR<ja-}qWt&azZen~h`K6R~qwWHiC+UIJ>>nSi zn1S%(xg)QnIX{Bz&QTEB7YgK=H6*ICFL~3-B0I04P1?pmG^&|_(jJ;s4lu^MDm38T z7!4{fc-c)aDV5p8%9g|#Sg{50eWkogfWpGcI%s^-%Q|T5gW1ux2<~<N?(EQRlPVdQ zXxneN^v^>R@h3uhi`@Huhz#|Fs9j8tjl5ok1CwvFugUabU3Rl@XOR0sMh;hwB970% z7mJ3H84cT{+6})#sIlmxslutLNUh`WL>-kEFd|e~kuDZp$C?0oY0n03&Wi%4E5r1( zxC49w*+5H^;IE&l%pM<L{!aygo`X1cHA!jP7dh@XDU;q3e)sjpiX85vCNadcXIwZv zobb`z+BkL&gOZn9_S)TZLhdSp&|2klB1Dq~Z+MvyLhN6yEE@O!SxrnTor$QmNaZ_S zRk$Nie0A#(8OTe4>N}{HLU&YQndO1{ibq5SBvpZ8Tcz#WzB3@A^tE#1;<U81?d@%< zu-vMus@&Z6S0ca0#(+U)kY0cnkf;q?8-uBVw<NoqQ8<hu1u9j+>!xhp_$mpfyZ1G4 zAgo>JnAw6S4OeGuhT5f2>Ela%Iyi!Q<wWu>uHuynR3+rms`4Vdj_Xhd(FC>^1MARC zJ-vJLztTu858M9ea`^-q;9Q^ZS@X*3Xck2@evtok_!@{)g$+HYKt)+A@IWi7vjb3( ztew{RTbME9O5&zShj!1`5oFUAe7hmRY-YmCo~zL;ZgfaH`A~aKg%Xd|L14Q;Aa0F> z&1ukF=eT5y=O)+EkHF;%{tS`pXk`^BpZzEZ?<>K!JM)a&CysSVgrL9flg$CQ4b(@5 zD{07J_<%Fn-b1*W{D0oo>f#2yc|(b>Um<WCR&Wzv?#xVc#Gdn31{hbDM)6DDx~PyR zT^arXlFEpyJ;PRD%ia-R+MWh&G7teb`;!av3G%&HTH5Ff^QvZ(xY0@N<OhRDV!SUc zxEX9uxB>_Z;=VO2!>TmZVUO=~AWRThw01dTHA2;~*u6)Sn#*DcS(`0Z@FlqbfS14^ zu8I4|im-_}yVe#$LVFH{HF7=Yv!-nyZ;P>i$Y1xVjDxf9l#DfDN$JTPd%@m4HP#Yo zHDw?Jg8y~&H|6KyM1XP^xk=^7V=4CO+kS3v(}Zh^Ja5t`+bFL*0%r6<jI_Z{=MWj7 zNBujb?~CsFLKMarlhbl30{Ufji{us|VN)73;3x>hoVSNE(C#sQ5y2Y=wB#az)R|l6 z%eK)|`B<6?A$`S5NUZQBG%XM0Yrx^W5+Xvo5JgQBi_k#}4n4KP`^)Qpo5Nv%AS)JX z)<3RxK}$SeZ=$Z;Do=q-qfli9Gi$$TQpZIC0uA?FUZ1f&6iY5M*TJGE;`mpusGMV& zRfK?<!2h}CFF#+#OSj;RMtT6Xty7)v-!vYR(c^hTXFg;Ad()$BlP_Vyh%@^1SpVLR zYIe3GX@He<ZaweygLN#j)S+~HV+bft)Gv6I^rvMbda&pU7~f)boMPy~^9PuQk2le2 zy13SH8tnmpfT1ev$>AIOuqtkaI!<uOWQ^}f)bkctTu1CPgzFUu{$Y<f_a1boQ94Zs zH21`z^<Pi)r3K{E0jgIoeQUfr7o{&ub2Bd->fXt)SjZLcJ{rB!`Nn=~TT3%UI8WyA z=&=Vlh_v2T%&MDeGS`);XJq{66|<iFYU4<Oie_K7;)W_wyG&m{I8-*#cZLX7Y_)Z= zyvFb*9Z!o9f5-7VrHZal=5o2~LuBpapCo;3l3cVd!gryhfEv0L_Yg6gfwK9pAYt3( zQwZ{+;!k2FAX^tCR1@@*?L^<1YTTFZ9FizELUbWKeEoy_I=tY6zHRvIt$0RC#m?ey z)|1^!78S9tznw!0999G14(##WzTaH&qlb31qWX4B>yYZ@{M;(uqviu*k6DafDYPk0 zPQKa3p3a(8bFmmjcCc*%XbX_qT@%A2BwBAS(>y_=;I8NgK@{S<a1Rwa&<{gluv!ew z>;LRB!Arw=Mm)Cj6|Vggk?i-4L62RZ1$4*USu)Qw$&Q9&ro1Tp1Q`*@?0SgUm=I0P z8{Gru)m(^xI_!V?UH8`;t>a$H(`I~$|4MfipnU{Y7Gt{t=+Xux5BwQw%BM;pREKt_ z-o@n&`RsFh1EA&vtzqjvlAJNsNMl~>0s*O!wH~}LBN%5D!pufp{Id><BM0wlzj2lY z!*yCel5j@20v?hz9M59EQUZkZUMZG3b%7O~%<03W`vkH*K!$TF=-@2aD4X~Jou{4k z`Fe6NYG9;MZRk`UmOHRT>7wxWvqjK$*{K}_$D;s&)v~#2QzE+XXGNpkn~!z~Pf*pS z=XiA2i3y=o7sLb5nRut~h9Gq_$#a!$yr>xdYz{v{K2INO#rz0E8jgfo?D!C8PDa-! zmKx<QTzVCXY_)L7O_VuA_Gq}e>E$)sK<f@aw`-RSAU{BxV9t(TGeii-UKz>)?*Fn% z?l~Lyt?uQnQ@-r6eTqr%uy3OZJKtz}G9-aKB;m3Sly4;I-iVR<HZPkCjl9@-w14>3 zN7<*8;N9Vz1F$_Y8=r=SJ%~@YulPL{`F9tCxXkvDWYB$-fue!_=(v4#f4_RgguT6O zq0_5n;*$^Ou`hs0C;5d7g>U0EfP{U@(<gNOrxBesnT+V(Tc8Wi;js5d;9-s!pKOM2 z9kW&gCsGu45zsrU*cv01KPjec6YwxJtjTz&|J-(hl2mgiFt2KpHC9zu?dIioR{*~& zG}C+=g|s2w9rLzlgGYm@z#3XKVt-%np$Uy8UV8C|MibT|y3fW=G->1JQ6C>4JK?mP zBc;LnB81+m*n8;lRVNL>v=$J&?(hr+0qFV9ly6klCjY{H7TP>WRekN_6m11=0>UzG zjg&X>(x!+};ANi0&^O4{_w&V_8$iwo-vqe`_9aX$qfwHG{;_-{WVtqdRam?J@0-v( zyO{>{w-WJLLzhCXP1=i9j81k_K6#YFHja0Ey`W#^=2qqE`X;_kt@c*%BkIbUwEf46 z+g#V)kpM_&1kd)99v)7@4(r*S+kbx%&>6lL)Cr1}@t+?Z6iewd)T!Ubphyz=x63A; z^YKwtOqgA-f9L4nAevOGN7RgUp38$9bBZ1Yltxg|1LJzAfi?dp(}-!5f1Ol%<o=(L z8NdHSON*e@J`#n;%oHYn7YnmKH^<%S8^4B7N#NhEp6CUBpZowRBlhBWZLkdXR4_r* zzoDwA==*o~Pt1yI4iM=mV52Y1U#^GZ*5i*UXvZGZ|2LW@X!&N@iAB4>{hcZ%k|!s_ zApJmLqR9oRX7kna#|JY)HLZch155={n`R0*-p`D$l@u)NvR@GM#SM4uAurmdbpGEd zO$1QnX2D?>A}$mqrKEuA)Ajb%XDdA}G*Zq#2)SUC{Yk?P6;;)hdj}GmZDchM6J#uZ zmNDbUUFQi5>Iw=%rXIS?S(K2UqWtIoSUnYka^d1U<Mu9`H<F*?``766g7Qo7QtxF4 zoJ7EJ9*LN!+oXM8W+tHH9P73a_=1KfRkm@;X0v>veAWxX16D-JO5rE%_!J{t$L;x^ zfq8y7cphc%p5{Z3k&fjOLvh=?nmn1)81JW)=?5SEQy@&hwhSn0zCRqHx_VTfx#pU{ zA2(l??#A6RtK|A_^=y8*$?vru$)}y7Scb1=5cR97YSt;@70Xss70<sTlAuiqF>=jq z<J&nIf8zvTGheq4oTARt@x8WHVsznZeSO8nz(@eKZLt?FR#pJPn7Q$Eu^1NrJSE|L zP;ni`2s)Y0+AI}kma+lP(lc<;M6W}uL#IQ(=syTLKV?<vDWpy${s+Bo6*0Ht(b4mO zVH@2dS|RgYr%1;7fvLXP_CmK)zmsj9`ksy8wW}RpFr<g_Pa>_m?qIe|NTlr84Gl;J zL;bjp%5^nQ5?*yk7Tp<7;Pb;t2u8P;k{j5bp?YY}8Noa>=TT*LQFL^vjwV0Hf!fp0 z&&=^}T{%|9V5XV*UR*O43#%AA*hOerSn&6}zq`~jFDQb;?C$#8RZIXEUQJDnk6o%S zJe(?}*n0R&R+xaS|9<;<zvSjT1_gg~GCf4^RJpuT<y=HZzx`u~k8hfNI%s-Tqv^a@ z;2bjg&L+uVr)aP!n=(aHCNi+%3KKHg9|NIu``QL7GI%@nq^Q=q$+{~m^9Wg3KG8I= z4c?4z%$mQorq^_7M`VZxUO+DEYBUNuc_zwHF?-$aiJvM<$<s(avD?MBC&Bt<l_K@f zbUxl2YF7LE_D5t`^JE-G3}I$%{|A^aS+(u?o%<<$F@Bv_$L^GQz|zh=>h3u7is+sH z8^OLJYuL8M)@Mz3;bTFt2N(BTHy}>AB3vC<W<YZuLVZT^*C;pd00$Q@Xxq?dQ&cQG zeo^sQ$FFh1M%ZE2#QkVA&;KB{oTr4d`AFZzzo{TEudXS*XyExM>={eV{Tj?&C#awC zIgmiQ4R7_}CPEzabk|0!NgegbFKvB#=|h<?KJ&<;gS24VC=u%ZOHKScD|Mf9!S-x4 zVQ1jOAM`JazfzZ^j2s|8I3yI`cyrS!LVuNDK|Ib?$hl|+RLa0tfR+f0fY7sSWoD}X z3E8qf4NL{HF)QgZnY#;C2W34k)w0J4ft7X5biR6<XQwr5A;<`%Q64Zg8{UAj^;VgP zNZP4hLmDt%PuD+P#7+3$va3a>=E~e@C2-{XU%q-}Z_l2*){OZ6T|cGR>&J&ebbpcb z=GWDh7AnAnzTnZHpBGyYvv+br(MgyBi1e(Hya*XJe!9L>4c{xCZCF}n2#rj$UU~!M zHbrh@Gvs0!+de1Ue#K;NqrK;5PrFIdUY$V#ZC69|pDFbCJ-Yj$(kF$X?M_X3<yA3b zGl;UtRP7-D8ZdIJZaMa!)DyDhY=L1#7<aA{5=-3rC6v%VZi&EgPhc-2c3$?v%kCgH zXi~l?%?U;e#x|sBB7_R6AR^a@32Hn)rYys91&<59Eh{5_2~u^8*T>jSn_OH0&uRAk z-(=JAW;nFzEV_oCj*gC=9)lOVL31l;wWI_gYFEhL@a>=hO=nPIzq2FuYb=cNr&=xE zIXtxlXB0z_T=WGNL`5TpGa6m`9#x-Q|F#Yac~LuN3!<#soV}hhZr)Q74!{ysCT}Z~ zuO5F>EB<Di^y1f>5#N-?CxhtmU&XvYmr{SFs5@SIj)|an5iVf8r3J{vy7{JA0jn-l zqMqa7^@{jt#soH3DtsH>_+;noA@~|XF2AaWm6BasYEIZ4{%x6=;<ItvIPV`WN(b)p zJX3Ra2%Y@!X`)CtUcRgM%Il$nH^W<bFu#tig4bU(Z~N2ydjJ*?fcGPZdP6rO8rfsJ zG|hpkzM;X`^f1`4s&H{gwTHj9<(sp0Y~Qa}50y6Gq`aYboT`ho`<ZxA@hJh6AZwzT z9kGQ8=nt&+mriHlAC{8JH@V;Zu^;FWe)-a^s)*`&adrpclYZB-*ss6n>H$XlvpJiX zU?xde?2Eqr9fKKAebQxPg&q*PrwS{)n~>|3Q#Hv@F_{E4vmkq?{~Ov}TPf|L2cX@O zLnJ=3j24z=Y5yT-(v9^HDCJ*Snft^N>DQR^VF+XnFhVF)7*!Vv45W^!2~KK1m(|yu zu(SOdf2{MC5?lb2=^w}6a043sn4VT77B&2z{Pz`B*dQH$c%Gh~9@@=)W$^LH*oer{ z;Rq2?qPf4<1Y07FezEN`?rX6_PL;2k<6TF2M>If#VLF3|dh~`_*SqcL^m3CLufo&1 z?Zx*zBLGImhOtqr<~d|L{gDJWAQ)FV0Fk1@8L>@N+4bKBGUN7$k_;?8sh4mLfH@ET zNQ+WJl(QL;@@Id%rlpH{qVk=--%v<qQB7eTF5#GQcwHIRXSD?}ULp(<pdQ+Wi3i5< zb_<1;1+z`OG;!wZYm@W-Hva^1JXCypy^V-Drwb9ESK!S0?@n8EMqyBB{Nb-IofWrh z@@{Hsetv$Yri>@RBp$cyK7D2ell^SwwC`BwwvEwSrl!|2Km2%^4@?OvF5=-St(`~8 zC;GNI;CY|E8PvYA{rQdj;b{L>`Fxg)*Z>ofJPjjmLT8TZ;=9IzGg?cUtae<PTXX1` z0a#dKY`7%j8UYasihKAVTU_`QjZb`8;34)25xbTwiVfEInD`6?<Fno(upakR$#)S} zUbh+=qaLUrsr%yG#bEYeMC%ASrqiPg<AZEHYcKin4dt9HaX%EI6Ur7-M#lBXoGelB z_{H~=ve<O)&b}6woNT<x4YPimEk%*1!>{PfiT=%>$AuJdnCQW2D6{ub(az3Jxy}ku z9%>A#`~E#MFVDX(xey4c7Q1;iKLpT!)t6Vh<&;-vYqFA_&g3XxMs9wBBqQ-QI_x6_ zB;LM9_4sKGr_b**ycNJ#R2Lqp;2>(hXC#~m?*`dxG^(k{w~&0;!#)W|k;(RqKR}qV zkZ-rJBEIHigwaa%8<K;A*9PB1;}mjbpVvtx48~qXJ|OJdmJG{!&U||V=!9TvxZ4zx z5>59v0iW=KvEM(z`A1e?P_upPva#o3^Q?oJoVcn`xDZv{_;-<?g@EwX-3L3L2hQVL zq^y)7o&+}X>(>h7O?i1c|Ko~oyHe4QA4jTdTu5$Rlh<<-H3%=l9>LhAgMQDkXa#LL z_vGb5so08IPmj?H{yUqH4mDlMN;CZQZUg-R`^RfJuf@;oD|c2$eM|K-%GE_KDr}9( z0^<_CEDdZd7b+wqAoNuT4^h05=?<`$$9ur=;8h)4-^Y=p*hXx~d+AsjI}6?bro~mo zmAj$7O>){OYlJrEnrpEpM|2r+_cpdrlL*M~W8U{Q?^DejUB5@}C&sk`9l8}EZR{yN zV>R(?Sm+%cTupFDQTa*pled2dVgb?f%QdWUJUN-K$XRe8Pyuv{)5|VzXs9kK;^)i< zJb5=#rp6s}FnR3mxX^VFIyq?!q?<sVL#u+GCIhILX=(Q^in@Sa6&3dISrt-k$@?$P zJa%oEKtTgb5{o5J8@eY0CD;mM6)TP#BGVgX<??`ZZXUo{v60pu_uFf#K@y<lYMZ;@ zNjmu6QfHWZ!qn<4#Xt<{-Y?_H`OkXp_y+5+nQ!|a*~?EotIvpVrLuTmE}4jJJ8zSD zH`_)%S*T|BM9$Y{)<{&8#KI$RE-XBc7}9eg%*^6PnGW(q2!F$f%jP}4z~p@Oa?Huc zNr#R@Kka00#fkWTD6>H%a~io4G?M=fY~ES?xP1=s@!A_EGQTLVJ+uPG%#@XtCGc>l zk9;-OtFXCsl2wwKSymSPqFrykaDoLMY$98~3uj~ot<h9|^)1OLG}13vE%Q5$fa>4+ z@C#`9{hHjbNPC>uK}u{K33We!$)%*o8P(N~36q>z=MdiD<tscMH=_R$!KW0aE1<~p z%hvj10_D?R5qdY=@u|t(Voo+)UA+H9vd0*JPT__aW1ZvI+pKc|oFdy;nz}`AWS209 z^iyrg)G`hwVU-JEILnzss8q3qJyqSB%QU^#LqM1eOTRl5OLVtO0*#IS=}ZVFdF4I# znAYYef;p@9f>nhYZ5NIq`)h{OAkQBlow_{@Cz+G|9KI<J0|PzL7rYK)^ai!m)9^nD z?+>2UI%eF2*5e}f-Z%N#JMk-*y#b0BV<bwc87r(4B)qwg^y@o%AuF|BHc;-@2iUc0 zRr-2S#IJ#N$-!NCl8Jy_$j+?N>swFyggLU1pbp;HlJz5GqE>%6WgK*g?p6<K8ifB@ zf|@WvAhbxd{kse=ceT8Yd*$%}%zi(zL)ZJ0#Z|B%tncL(`O(f5;4_{n#TDW@))q-D zzPZHJboR9Btn+_v`645pm(@jfQ)BnyG`eQTXJ@IoQ84JgB_hCCHHFvYedhRtNHC~U zzv+%Iez+$IpoU_h6sAf@=8?rKD$)Do?P1(?L1i~`GT@r5>njF)Yyp0Z;9VYV9@gml zx@u>a9^-41cY;1CiycRq;qnk7OFYOd!wcqHZW@1csCPfwUhE@f&HjPtGz2xG6>ibr z+(WiSo8hs%U8pfmuJ=?1!;{Rz*^6<hs!wvpt}Ca<7dd7uH=?wqNDC+($@MQi)J&Bp zD{nCU46f0+7Re*>h1MM7{oU=up}^lg3?kn{?jiH8xZk){A#GB2j*=>=><}x>pkPS! zs+a%!R{-bv-8(4ImETf7et~8#wc6D*UbSnS`7f7*fZ*Yq77&1(%$ow$gFJ)sA|+Xt zEB^v;Ee|i_Xo1T3?oi5q@p$0JZ-V|{MV?c%WURC476i5bJB8!r_&?aAOxx!FC36>! zcHcc)NzL^X18tGvbl!1XD%|(}^23Jbde+zmQuXG`^>sfs3D3^@HS7Nmgz!&0#Xk#s zXA$<75nzY^s^6BI<-SwUxDIDza4iU#u#aeu;<DoyerY~#5ml4kCAmz3v5m+L=%ODE zRLlPCI#O2GES2P<KZpbeSRd3i6DL1=ZvDx=S9kJ7yOj?8hIR+qa_CjZvny6>1BRPF zl)c;ls@clgo%0_27Yf?&5B`8X+v3nP^=V~!v_6q#!L;>e#r+eoi;rcBH0P;h`!EbZ z0|h$?A5Y!i=K8x84?q1uan^w$3GAU>rGIe2A}QO6p^x^=dq`6DDg)&cKD{GkR@d@= zCrF3OdPi^sXLJY08~%~%6Z-;#boB|+j4`bjAz8h|FoT=;K^BJU4Ez6r3>Vhmb%`~a zT9WHUb(06qQebf*_oU??ffq$>+dFv&dCc6Kdupc0aW=U$mx2lU*L8*{QiP*5KuqU< zxy9?}cGz-+5<~d+jt9mB0(^Q^<4%|Ofi~5&Us_CKN(g|lO}w#<Trt&S>_s0P8Py4_ ztn#0ug&8jvg7z6CH|RwW7`d6HEeVM5F$*2ST=19<Y)2#2J$?ea06pz<$zP3y^;z08 zgC}5&;H~Sx4ZrZn_x?Bc6#EPK0=UXFPofn2*c;c8D~Nl~>4XL%a1*TLKeL`u&6K|Y zM9h-AR>zxOeD35Za-5mdgixAT&wbJ#w>gh_<>AqG4$0d|q%Vme^|~(UU@cVeGgr83 zIB(Jh<anvm$i1PlF=h;jSK|_;BO_h_u$kUb<*b9ytY|W&0p%Y410Rhju&Wu$31-SO z;$^PI5hABi8oQ-x6wLDv*IJIzF)vcMI@JCCuP#dfuoGm}63AK8FO~!cN_x{+gQB<Y zB6ebU8{VfV!Ti{<7=Ex1P0EjP`4~x1;+U7>b}gw8Rrk2Chyn@iRDr%C!~1yH%-2$+ zQ;|bcsC{#+q%ZWB(6JL;BZ0w%ky;F<gW_p}iCGdosu<=c|KRL_pWkt6Pc8BaFo~i% z<eCc!SQLgS!k~(1ePCr)g&0CGlpTVzOGbJWi2Mah2vQUN2Sx-yQN9alg7tLDo7mL* zqlKN#3!D#Ct+mS2Pa#JRZo(qC39sW@h!3$VH^e!qU0vVR*AD_?m#<B<99%Ip-q6Ei zH>x*|kHK+%ODl0hR7*cFi-o|q`@UD}Ygqh4{f==mR?l3)u75(Cvd2U1{#INy!%#e1 z0XSythTcdLXMu2hSuX1h5251(g>d!T8@$w$3*C=mvMkd&XqF;a5~S7vTMfXSVtQ62 z@zhn4It4~$5ljeS{ho0O#7-h_Ltv{l^!9H(eKCY{r@gsqG!kaAZ=sw9BJulVxpfsx zMDs$C-nqk{3;@fI?>O-P;>sx361t3!RnU<NF0yBL;Aiq-r9IH1=;=dqba6L<HrHR) z;jlp_J7F<6h3gj+tm{bnoC4+tI*jt((-x_7(J;jAH<!TB3<7{kzV5>KD#xh!5P33u zW9F$0o)SzwEGNs-K`B4_;_sDz`R$)MMd=G}>u|Ok8FjYZuU=Wm@WrvdXS&TO({eXx zxk9?`V?v9FQr4T`Qs^p?LYOR>OafaTiG=v&vkUAK0CA1GW}a^Yb=YWRnJ2_EcxLt3 zR=K;oSJ%|M;7$1T>sLYoRra8vxw*NiX_}z?A{?r~|CSA-eT9$@07cmZL&~@hLQjZQ zaX$=c+7tUTo|B@KHm39Pg>~|Uqc?mt-1swKw@A7?gLSIS(r>`@NZcw<KRvLoBgLDR zM{Vwzv+Wl#Yp3b`Ka9O~Sd?GeHB1Ny2#A!ll1ev{qaq+mh)5$KNJ%q<<bZ+*f`~}R zfJjKg&^eNlLw8CHT|*5_yw@-Ex$ozD-{biHfj{Rucbt2zz1BX@Ncors=H-GB(5cwC z2HD~D?w7gy2rki29nX6v^`;d9@4Z)rjHH)DMrEV!#FsBf%Dj1ZuGi_Ip$_^ExT}xt zn62@nF8gv>AlKUlO)9^XjGECMEBL)#LnK*bX(bi~_FU%vST4Hp?BloZXOuS&{y160 z6#s5D^($j39`yXlW0uF9BKi3vthlt|*V<V%P|z)v4yBo)Ye_k|g!>390h*jUV-b(> z+fU@r%V{)z!b}d4=0rR+oSq6O(ik<I-Nqscm&_@9k$KQ9`=|-|e-o8^fMu*?4ZCeJ z31zcpGgffWzLEp@HOt9vKazV_p<`AIIAG*~wfPhu!00<P1YDpcv`+T68emTlc6y^F zN%|^dAcfJPx7v889GAV!FRikJ_c?+4aovQdI;lg+>lfKy4=vA-uvtzdVOInM$C;i| zMgJzFXYwWmHBFvMt#%IY@Ab1-+5WF=KCzG^z1v$dWS6Bs?D{i-qS%k+lF}1NRTX7P zLtL`O?h=aZA{~=V6#?-+*uJMgICQ_2Dk6;9&0nV;3wG6t`xNljcLGGV=H+eR8aRgY z&^2&;>=5|?L<v}3JU$Qcgmb>!wtiIoNeIDEbcBfF0M%rqtz40qe1z|tFy<dcCv)M@ z)SYYM20tg+G+cnDlW1t=))ftk4`lSWrH}rOcJ`tBa_Yl-_;9IQK%Pp1SX1l>MwMTs zkT5*g2U@YkNwscNemMAIaDG#E#Kr7k<e8SnIW^#gE)NgO_rTscKyVJT^?nmyvR!*A zk9mELQjJgeJr2Pm*Zy|ZU~8J*NGGt^cZITkE#1}YZNeGvruc99-pVAi|9VFe{G=zi z3)CAqVn*k8{S5|D@);zl+DfI&UU@-b;)A2&i-M3rfq@tU>7Ak6DIh_-RYg^+Kksi$ zE2u};Tp&|#vq^=OpN6Jg|FA*pK_lTE@kAf+4n(!vUgHHf-)jSby%H{ax$xkfGI>Rx z*zb0IS$|E&`<@Z1dnaU5C`aDsX<hm>$YOZ=p`YfGL1g+s_J9s=;JIKA@2|#zxzF;6 zdZlU<3cn~%ky@V>;ec0@nb$3&+eloAXixO*8sJw{Uf8WfEMMRH+RoSU#XI}G)pU#1 zcFikvG@#qn=(_m}M5D+%W%TH=E$i+<h7Pi~Ry|TeZcZcQqj;<_dV$3ez$jV_V@m@3 z@>kQp2(JVcbf>qIth6CK!2dQ41s>zk`~%Lomjt_4iw^TVUqDR^iboqp`7to>BUm;3 z%cI9Shamr-ndf%HhbfnrJ7(4v%PX|dVJ^yV2HEkm7ndKRp(;C2iy8Bov7BVQoKG7{ z^9T|1No?hq8%k$=#ik_bUQFLIP%p`eq0ye&`a<IrtB0#?BmXSl7&NPe_}ri|yiM|@ zf7zf%4@=EU6Jh1Vs<Ad9z1jCwe&ZPuazCB_wtKsB-Hzg29c_AOa{dU2DHe&LQT>dR zJUPxpBl+_Y{;Pq?52tuCXg8y{k69i*!pKG`Jq{TRqyLI2`g#voZX_$ob?!l-Z=iNh zF^Zr8S4Uv5oa(vV;%4(7_lmARt7om<odwlAg`))DI5#JeZr(^gR|w<3_D3Gill~ir zC|+v@sv+@khab6yo4nEy@J#&yRoNtpON8=8gUIJ)9?L53U|{TtLx@dWohWxW>)*cX z@`+zii~p}~?~02yyk+afpDYU!031Z0?gyym%L82jG{4YsrwQ5I4y#s1OvZoK;=AmX zK#67Unk;1bQJEOK7MOHDomit>+mL5!aTD{@-0s~Iq=?`CFWEyUnt+Or7L=)5M+g!g zF~|XaN`Xe~c4RRXgyJ$+xBlm^mm{zB$x$XT&=d3Z5pvtAs?rlDUDYkUVJn_>otCh) zgv+Y4(9xtrXyQ1<oq^%l4xdq)>tEQ`ceLF%&?mBRF}j?-qx@WdP7h|jAm<<HaiNtm zFBu}b`2%#il!ibdd@mszvskSsATAW1D^tdvIAo}N-w?>Za&2c1?!io#OsOPde)Hqk z(S@@}LGUN9GRl^X*TIyvUhCIxhF-mY8Tj+{hpy9zX^ODm4~5*XR`poDGAEen%v6uH zHtEzWInP^Mx!R+6779vDFps4IgzA}q_haT6ajGFu*QEbozO6-7G*}#kzI;19LI?|s zu|gx;Z1H=0ErQ>n;!AT2kc-0wvJ2vCIN#`s&|H7evx7zAW-q2E^D+k)NSnDY6H*s6 z)8ergG}HtqE8m%tnr6GE3q`cCNQ1j%xDiyJqZm-UhwuEv%JsXIGNB9D`j;EE^r5tY z%xg;Ja9Ly7$wjnX8T_!gu~hc#=B;zw+jm-L;{h5V&Kv6ZMj|NKaZ9e0nyoK|-v`$2 z)2j&+4!}mgH9ocx=&C|NEnc|P9YVwY8Hf8))RE49k6|{vuiIv5NF8lQUF4Ho;#%{A zJgO1ChlpH^S|kx$hO>5ygXPNn8^W<Pbv#>LjU|<q*$qBft99fh8jwZ9PUggR<lw=> za(w3VTMD@loU}fuMa?Yb14P;B1dl^EcwDp42{=7nXu+J`40#_4QO*~Ny%He0#W2G_ zL;Ccd&WoyWnIOE=s|TEInnQT;#Md@_Q`0!PtKcfuWi+z*mN1#b#(ChP6!ok3%g`Fa zcXb!!EaQ2e*vOzNlIUOKy5dNQH33;ZpkFCNeT`2x*pYu&-_OEo5?9AiCMmt<3dhGs zL3Vp*_gsNR<oct=m8_TMH0uKUCG~OV_Z+jcbJkSUSwjGyITqP#ban087=-cfWpe-W z(8F4M8_P&!Nx<U*8@t!UzwT6+gKzM~8=fR@vQdKgyL;uk$3c0I2C-}om!w&~LaNii z^4K)^40s=1|5BNiB@@!T+6KX)*U)X(MERRfFZL+!pC{wcJrxgPL&3%&Q?|lAoq6^W z3PZw%k~6;7ir4y!G7c`Qx>%fk{xDb1yp$B=5`~1y=4fxXYtiJDr|;O_3*T~$`t?IH zSa>doRQ&k~wZUsK!U<jUyvvyEyn>o0+qlir$BSUr+m+$vW+yz#%sNifxT(>GJMkp) zK`;!edRHp9LZ*Xt8$|?}yAm^tMSX2A(0XZ=dXN9$rcSPgjMH+4-_LXe)`dML`aXN^ z0m8o)fvz6}bC~6IPb4#%-85&9$qQLXMh2ud1XY8%(`D`X=l497nf34(-4etO&?@)e zeRf~!)(RB02z{JtB`SVX;?q82x%b-P6p!4DXYPm8hlR7r8_gk~FH64e5sCODV5={< zb}4c-uGk4V-?%U5qF2lMSUl~je#nyWqH!)4>xrc^ng0Sj(czvCtRme<hZferKo>_% z4?At3_9l(D^$}dWQ-5wg9$RdmffSRSbaNUFOs3i+4O5$qrh!<Ee!s&;$Fgo?Tes)X zWV3YLm9s5Sg?;ze0Dr(MyG3n$(0ft6Vw%2YE47c6F9PEmvUdxKZXsu0l5yISw6s<Y z3EC|DyDDxzc&mal23%ghJ_9z@o@*LEbAQ6LBp*$eJbT}7guU_PT2{D!54UZf{Aiu| z&MKo~t;`3~REN-u4Hc~>nL?@S(-lczQNc`p$~%=+?>^Ac#pMRD%=xP4%IV|+OICuW zy6j`+*VnSLTOFZ$g-m&)B2reY)I-vn&)8b6!}gRcP!4U#SxHWWoci$Sf!LPa>XUsI zoLtSrv8sRf_2r@cPmlx%<JVdq4A|JX-0pYg10pz#0o;SIs~xI1<G*s@KMAp%3onEh zdf*=WXX)PzwJ-V!>IG5inyviF7ng6c2p%F15syW)1$Fh_ro4(;i&@pjlo$Mj30%$A zeI8f4(6iEyns-dY3o9NXeven^)#!Mx3uKU;=*;O+?o9fmQ|fYxvzKRFe~gj$NLyNU zt4w(Ou|n;#NVq4n*vqPr@Tvvyx&(GW;5l9~*Xo7Vr!WR<BHa<Dmtf_<A`IC4;kljR z9ag;AbK_AthAR^w{xEQzP6rbs`hNm_-}%TL18#w(o`RZCCn^Rro=6wgy}_ze#`JpU zLFXNg@GCA5beQvAOYv&dcVY9_uj&l#r11!t@VuXQn1ZWmgDPHc=(LY?3!2UK#-#2N z7R8pyr+2||mL?h$UGMGQIInz4cIixc)6)FbDcUYO8+MG)m)13`+i2%&sI8dpkvh4b z-%uDC>*kbSfrSkX{pWaaLFwl~vOAEqcf>JDn53*3mzFj)R_9sk9ja4~L2Ngf3I0qg zZlT$Dt+c=<At0L9;zf6&(IIm}z#Cr9rB#0U_?_1ni9p0H8+@AfHP$LK*4WXZ<R%GG zGcl!xjY~gYc+vNQAbWcSIE-YDW3fEY$nL5PqpYP%T#n+S84$m%jaEZ}eU<uWTwN1N zVAPM;kyx-UOS@10E}12Ibgs&Ba@v4@E+jrA*SIqjIYMkiVxJ(>>7W!Ma<_0)T>GwU zW^s$)(3yRwY`x&ZR&H|J?-S*{nnnl~+%=~I+SsPeg9e=gZA>dx6H+<EYLO_|^r+DN zeo>=C_5=(KIT|CqiefT4yqypb#mo7tm|3u-yen4gLe>etP5GWT0rdikGKO#uOXkUE z^ngUw9y#4p>XJ7<#MQ}XCQdo)>wDv-^v0JAbUxOPVo(}z|Ev?n{VQ(ytbSbkif$6Z zE&_g%+j50*WWmepA+Sifn^MWi@LQH+mEzj|%(d4h=cDD61uP}X6b9u^!}%X2X%Dnm zg_wpY74JRyoxk4aMBN8!-6>=QjK6;z1Hzr915MGx*{ff_eiaUanA>){8XeLlV3Gzv zh6y!0lIx#V&!O{Au;5z@avzP?ROM!n?~qWY@YYQP2>G^v<(dAuV)gfBU2}5)y1jgO zj?}#?eSFCC%6vqP$d16YHj7DtCap_0Vl$tl<1iU6C6fp34M|0xYb?6)iK%yLu54|% zM7`i)I(AxQlwD)C6mj#6yzV;C77|#TM9GYL!vLmXx(I|TqXVM8J~JYmj9>U1Ma)P5 zC5j=KsCBgF&+THZ_K4ZO!uDfAyHCz+erGmGSjDiIaGQ{A9Zz3rxe~j}q7bu?=VW=z z{d)-LBU;hG&gBf)F4NOd@=AQ}J!PLAG{UjBkKpX(k$^(9&XFmcPf+ZyaN#WD3;FKT z$b6u23rZXxCX>qMW{G;Y1uZ5T)Hb@qDnCZzTZW)QfFQd9>xjAKoIPl7U|oB}gnqZv zrrD+|PmQ{ew$|GHr(4h#?VSXw4J_)Br;B88Oz=oD_uQKfkrE<hQVx<6>%MZhUX&cS zDliuNRBq&D-&w)L`|M&Q*X=tnG2*E?8K|(Ry3xp~bcb?n<b=esNjx(Pvkkls)6-^b z-GVY)CR$XHJ;q*n^`b2qE(&)xGl?N6MRD(2h%8IbUgyX0+m5=fa%@myJ{+jbaSN7- z^xH%%$dk`u3HPZXS@IJuMwzL<A;Qh4x?=dor!CeximR1Mr?cP-_Va}x(}{(G)E0?` z-ZZ=V#{HuL*T&gjr>?0j`_B^Pbi93+B1Bx3CJHup3`7BYX<B$gUy$1|6Nf!+Rj{~P z?sW?zR!7hVza9ICW#)p?_FAual(*AijnVK0@+V^+4u!-8BZ{f1sD6N04b#N>a?jL! zLm>kKHFCG1O;|!!NnaGgQSAE}@AMp%F}I&_!E$==)@@>hbzhT%^?;8*3=4~p`#=Z_ zRw+u7KSNf-WuAq_JiY1t9-a1pIP12cYZ1xz<!6I(P)a9c0&e$mr6)Jy5^l-0mOojv ziOR6ov@guOEjnTuDr+5yQ-HU@3E^w-7x3q1g?aSrxqmXjGx|P|&z{eIaESj-?Q%(? z*)S3TO2F>7>3>u{U$KsvI`|q(wp-t;9miiRzcLsX4z1c^&SP&zC=+)^%^poIYb&1Q zE9K5sv=L9#VE49!fhURfXk4DmWjtFIEYlr9zGdc^HF9SiLm#C5xuxT&82-w~U(sV% zF|eTlX?>Ris+BcpZz2aeO7R?7Wz4xOH!isTlHDSlahK9ku~(vHv(xjWE3GeS%hwt9 z1P69a&^t@g=$)xE9P0-u6lqf_zqMgD&<QNQ#nU@-z+n^rl)N&_v&Grkr<P@(V&66B z1ua^*Em`xEH{%Wo+)vYb{?;>D?vD_T_FpTa9_7VEQe@++6TJ9)+4wE;-zRO3PRL)U zlK*zuLP^6;^~J6NB7G*P+amw9UCx~M%tdXsNz>W(D^u4dR9#;2ETl`RlyhWhfOTTZ z<sx01ecFE!9um$miry>W!v|FMO^DWP`%Gr8UeE~Y;+=r{vNLzdC|zDR%bSQJ$CPD% zp0kp=a<`H$LFfEf#>RF<g1kyv%00X7CUIzmMLtV0NmZ?_dvg<gR9bsbf5JV9_#=Yx zyZc7bMEi7$)TbRs`AKhmH?`&A37)+Rux%8f(A_`@vG_<=*T-fG;vliLyFRT-Atm&| z9I-fG{rQb6F4_~qHC_CNs-}D#Iv=O?hAYEAP4a@{C)qm>5QH^sd><joq)9Z2glU^4 zZOxbg8)a^-&n>@Ei!Kkv8nnSVaUTKX*g2mC8H+=vwSng@Iq~u*W)0mO4b?`D{qZg> zS;kv3>?MtEb-e?QQ@J}m{(IvEU?jCty)>sU1*8727SYl{d|6ZC-o#Z5*uqfMzgccS zJ5a1gB2^MSf(S&_7*T9PTYQ#T-$PCs%dytuxT&3Q9=9Kv79ArXdiNl&m|OBf2n{5_ zAy}9!)W<0Gl+;pGR$*F9LJFB!hsZ4cvI=FT&@$p^Og%nU&-Aiu+O<vge*`SR0D*n} zeaZd!25Qiy=1VwB)fDBvqCcr3^1%-b7`a0|?{!L;2dzfqvC+JcB{Y&Q+qImT!|&=| zV}u>_A?9_*<us7cfmN6D;8!`B^|$=H?NH8Ng^31}K|htLxbbzaig+jem33C-jJzJi zJB)Aw(S=<tE3Jsj4P0`mBPwBQ5t^umzA^(cBpz^mr(w|Xb|m<?IFgK{q-9BHb86OY z|DH(S_rCt>;wmQa2Zg02p{9lkhU{}zsxW{y=f8!_M;rL2tU`4zHIvM*nNaolLTb3e z|6`U6@W6{J^}X6&^9l1AyKYbw&bOsW7bW{Ds6#S_KdABKnpuFsudoAz!cH)+g;jU> z*-P(2VVc=e)$ePdnD6;XF8E5ZC#G$}Xs7PAmrs65syA%T{#>xS-3X}`d^|zU9qL%H zRet%E{xr*g@fq^&xu@Uk;>+TgcUs@~Kz9fx<E$_wmO?O%#2TxL0(|3@E)(Mmngkx- z(w3pHmNA@G-rQ}08^BVFCqJ<^_L_ZZ&)Jr9R=Eld7X#sG7wzX&^*E$H2nSVH|A`3% zBrDkspEbUj-JsJsr6@>-Bw4WmJc}%Atu&N9z=g%YKB8*k0rKOd6L*>?PtWv=y}7cL z51|m;esVSIHrVn5E-$_SLhS;&uIW@V=P5SF7j~Qty;yTCU+DnlP34MhLzi40)Y6|J zrTpm)4Ap!@@NAa6yK^#cS<s%5zZivn1~8mb1<+5%h<6d`hy(RB#Yqt$S5=_dknLe$ zjh!f;AbvJ2VqASB2+~%3Wu~F}34MCw#KQU&MQz=Hph%(9J2>=pWFoPff}y3O?F6W& zU>OW_x|3}2O-4Mx5;ju0WhfbKsQ$+Mw**K~h~6Uw$JJu$W<2g2;DuID#7YS)bbMYY zTd~8O$z=px!v|f{0fp!+v@^N>N><<B1sfe|w1Qfs3+GJy*{aR(BacTwWF($1ch>G| zezPuN!p_P<KIGiOF&`o}FyQv@@6^3<bt%Up+brx%VlAG5DJ%1yej}4<NxxyuX6?_U zhybOzXz|xLU%i4x?a{!s0@$3;x*IlHSMfDzS<Vb1EXp@T+_s49`_)pS^NB9tX}=0H zQ=1eY!lJ9nU76DA$dmZj8S?o?0@Thq`f<`_r7)XLyfYdpZNzLVK-sI<`c)+RdH}Cp zwmwAV-{>Fc-cEw3wZIa$e5S{i4J2{C-JC{;3JI7<-m$+C-Fw~z>+Tw(r(wJn*4>6h zjRyeoPTNP6YHkf?;l=yUp}Jpjb(ObIuF)O0+dq>P!3SL9ozXaI`+i5fK%jN2Pm^P@ z^T>7*Yyc<j`{3ewOvnEhwbd(fLYg-guqDA+8l9QxG7vLx*t4m3%PNGD8>9^@%Tp0g zb9q~=t|Ki9t&8{Asq-|Hi6?J(@hc?}DfQN46fG}(NT#W7)qHg{H*UmWR><@UfA9Cf zqMGZ5tHaCno`4)rU--|WjSw1oeiq=F^TfHz1N4Mb&_KLthWC_Ao5+;yWWICU&R1sy zOV!wZZ*}8#N_1zm1%5oDNra=xxB<s6vjNG)fZ1>T6<*tVj~Yzx#W1MG&N=eLz-v`( zC%b^_$g2O6t6?qU71J3DnHM&Y<PUemZI#)J(60@P2bNO4CF!_!7Jcy>P)hn-Zx)o1 zaqD?P4x@R0i$TMF<_q4n`##^kYlq#wKHpZ~NGIrjXRgFPEcw?>$I$T?b~Qii{_IK~ ziVf({-gYil+jR`T;*HgDn%N7L0sf8Pzl}$Ddu-wILQ}x|Jp8%NcskQlg>ql~$k3h; zP)qa4HZR}i+rvo(1{s3S|G{+cOUYAgLceDwZupD?{OMt3kX`*w5q-2Bv++apUljP} ze^X%kX^`wE11GyQoyey4(4WBobN<b0A6Nqv`mb96fII(2%a@0YVgcf9?k8?~HukK| z>6f8-2WMf$*0%yacm1})c14yk>2d0JLbslOWBu<R`Uyh*08*oo5#7rd9Z7dbk4QEU z>PMB9e$R7Ys^y7B<Z(xc5;qxKUA;tuHcLH3d!TVP?-%8V|Mfw2H*j(ST;DRWZ{%Gm z>L(xfi6JjS7tAn$i?<lVX&66wKp`^n_3OC0is?s>OLPJxW#vtP7!=D%%b464#d@5( zhyz2sab+@aaf7Il0kRV^Kif#=?HJnMQ9oipBLmRL^-$Zl;=NV08tgj_JibNavix42 z13(4&$9+#yaLL0}26yz-4Q;-EW-WneUwKK6EZBC8S&0aR%ohpW9H}SjHRhitZVGm} zJ2NP4bC;$%zUZx%{iXrg_!@72kzRj@v~K}b+poc>AC7~E$L=$K(NbT>cOl&UcRXo0 zq9pA~p~|?m(BfYZmai|$mE5@ZNyRu{bDmvFqMRjgx>Q-&YCvpG8bmM;p4oyMWwtPk z@CvM%Sa#iCi2FT#x@0R*$~9;pq2e#S-cHa=xP&)r3~)`=_H+>%H>UWCYumk`hhwdl zd9Yb=^1eg2{`k~7dBdu7BO^!CHw-FGqVdwKCdrQbHKm!CmUq`vRDzkE!cE9#2pS0R zM7aLP@}_z9#4&_)!Oyduym``t(?b+KB_$!Tw#0dZG_2YL=8LgjbKLA9b0Nv_vM1qW zbzo&h&sX`<p$^(KiBA+GNqf}b-EdknRaT-4f*L|jVk8l((Th&df^*>U;D<ebN5S03 zkx4Qn&Ah)ez*mu<Af{GO_+fh6xm?;_8b5Zn=AZeH<Gjvb#$3^*ES&bWUR6K;T-_FL z#zA}4vsYJ~*X*18611>qU%?q{VN%6-*VR&S-(u0X<)utsCjpdj;XsvNc5Et*MT0*; zw5-Ozdkr227h2@1Z&-~DvE2q=cB5&iM+p0gQP*ai)F!fSL>+@7fA!CDKVMG<5sFau zqdj~E42Pp<Hm10P7w(J;UrBu!hPzfMa`f}WJ#sjco59nEan`<-Q<R{2@swM^7>Lm# zwOVi)+BJrB`a>qpvnO+Fq)ffv$-cXNLUC8&#gfxHk2&Ew$w=GOpjYmsVBa9{YCt$G zj&I5}RZE}B^igV=TY9wTvFvQo+B7W0`BH>NA@!PSjL0Kr<ekxTB*mhUrLaN%oolt} zyp$Oy7j}E2kl?*!`soGe<$9`KCZWs`)AZa^w#^2?key#z`3!?JwQ(o@6k>x)^AQn6 ztR~50;((r3eC)iNw)bN7lK%krB*JDpPYy5=>gZu_I9~qH83L;oth=%u5G0DPlilj{ zd=V6+hYx#h)&BbszRLT!T+7v=dizQ##OKGe;mLV(G5x4HJ&vbPjdH`JEWl(HEJDo` zrv1pF5U!eu3EO*3fp?N8e{W-*y7L<R?O})1=G|eC;h=!Uz0;X6YP268F=+b~G5=k> z$VNOmaneh`gwRyNu|93pTb(G*sNGsJBT@w!THHl9+A?Fp+9_?lI-g*$>7j{lq;Qkw zU!EP%OGD{<E^|~v%-^Ah?aEyCM>N|QqX7WvTIW|&MeTPC6|A)?%}S?!c6sj_x7zPW zZW;fhB-p*i;^cbRSx?i-2C5k4*E6+5BLp2Udc)ri_(sgixA1*N*VqneSOd?M&6XdA zZ-3By?kFD(k;&sSeNY!eUzPnh<{KoVbGTMAL^7l}KfQ}cy&MyUgwE`bJ~J4e%m_>5 zT;X-R@D~CX+BMQBKAuv55C3G|pw`U$(VXHZM#UXsVN8F{Sf~~**~BS~-|q9J901eP zmFd`OAGg#MXNB)TP0O0Qj2>;fH)`o#Pe5+U_XG;IIp5l9YcJw-8KJlnyxNssRS(5) zeU>SzkciyF@sz|}7|HW#_0e};dFt!-d%IDETBXhpJ9*VKl_*sAyO%A#LnaE7unW{K zMQ)}scn&;%fRhtGz`~j+v&i2I{Y)dnvoWOYG)I!~0QD6}Pi#WokOk8@*o)d7M>GI9 zjgiv0Z>19=obQHL?QVPvs_`|>Xre#s^?e(>gmE_(%oHAsPN|83=+wB3j%wHJ5tI@l zCB5W;fLn}jE$jI#z+;Tgt;<)T6PKv13r;i)oTF)y*LHTqW#3E{576EDRB`@t@#Z+k zR9DM~ula`49u4sBtfm`HCs!BRj~;XNMQZ+pe44-0zbb63(TOfTmllMcMn@Vet400E zn6Kz(juLEpHO|KQB-F9?oJGg|Rpi5rYnCNI;uq|@fxqI&bRWf~8W<IYldG5Ve5FYH zynsS}11d^3Zs!|Pa~rys^^WQc*(}uHE=l(w`lWLCfg#W>^18GVq0xO3r4X08ForVz zhQNMTriDy@wxk>gE@Xy;WBt)K4n74pOn}V)NJlBVI7dqwKU`uFtnm$9Eniqtj*>m( zAfBO*^vfatVB(2_2)?M<y?e2}5E~f6Usw52+aFzlQU3LiZywaMC-k&~ZK;zjV^#C_ zk^TPblfT74{w3Bf5Lp=b8{}iNglS|`>*oM%vh%{dq}bt>AoFjxSHmykw|&>1l%>a| zJ>t%b?eiw}GDvD2@~SPn!GlHJveYk_He9!iv3UpB8##&ktgQB%Tr@(NXL<L1A?Ygv znn6LqcF2nPLmQkG$yRw^D;l>+!L+|f>Vl0nG~UWIo&MhS9Ut&X0eLYSl3|70bn4~& zNDxG9ZW&oLqHK+hC4RPCQ?}BCdw07*{9`vl{amo*n-!;sNgjKmyzM7eNvV_niHYm! ze+ir;t#_TNYCfywPru7a&`a2P*kt&^3<yy%sQ6&UmJg($-VCLSk}{X)d{tk7bG%_# zr#z)MsCGlWXMRN_)FJPSwnRf%`dd5o>>l~243E6DC3CK2j)Q6ly-8et%|jf^Pb!em z)cx(`qH5aw$o+f2wxUCoT-wU2zl4^GFCSesmxvQr=n^4xKH*HGYWx|n7GHeG&bJ}I zhI?x}ke8Q%dN@!Wp^x_^C?ku5TM(3xjOWlZgxzd8mQAY((hE90u%9kWa5wzo>u&!H z2fktZ{y!wlTmLCx=D6?VzLmkXujQK`T0$TH1o<0Gxx{wJvgATesz$jDYy`q|xAKb( zGESV}!s<G=RqHnX3WW7VgZwHO+yaq#b^gd!d2gjOQY={Bhk|&zqPmmETsoAM*8AIB zAe4zZN;b<tvniwR&2<_Hx~jyj5G@;;Qa-RBel}(Jf?_eqk_n&YLpGm-n2k07N@kl9 zv%gmNLFEo)zG3_)9(_N4u^3m!6refxX`lWali`CgZ|e3aUF;v}f-2$yR3uInKAW{x zwSC3)F1xzG@?A|&-RR)FfjK390F|Q->JZ_%!@X3%z4MqY-^4eOZ6~pf{tbOMBMGu! z#P8&m*WPaAJ#%`61ryAGd@c>x+<v=smme~jQe=NXueyMPcRcG?3FdHtuPL5UxDoe0 zsG<Hy_l-IHdMnGQXxZz%{=WAds=5K!P$s}7ESPNkjrUrB`7Nv$m2KyM+ha|C+|)+i zZFSH`!V#lIzvnL6{49*>u$0ppILv?~237Z<={{TW_bPQ=K8w!#t1*(#A&^2d%{y!2 zomWm0zx)@JR6Iit=T1J>oP45}_=-KsDs~?M?zv_zdzXLhX3Ps^H@ihHf%WGqB(D{Q zh;_c1b97%B{-Dxaqfk6Yd{n=)tW`({OWY$cuMiMx>|@&oF0|=x<?EDJd{L07@#PbX zDi!@EwjliMJeycY>s!Na>-}cY{cELA^KFcA=Qc-!$NO9CAKw=&9>|L&s6M|k@N_nI zV2U!S$63~}>f8Zwb|n5A_C6rz{!1aFP)}(hNwfmAeOSe1;n}EeXyMa4ve|ETR~UV% zL*?@7E8NuWI!mt!_zb2w49^+&)j2deNG}^XikXfT!UyB(YvWm$`+V7ZR#uA(rzMW- z-%2B^zazIbz3TFVO!gP28^7<bemye2UGPR-w1iWXxaGD*sRK#TMhV+Xx<7aFU&Q_r z;lAQ-yWYwXi@e_oN{nal|8vU}dX)?RmvZ;vJkRV<j_N;Ur)UPW9iWj#{%_Xs|DZ80 znQY3)ixdKstMJLU2hTtKFLCf6!g5_IOPW%!^U~K`(T5OadKkc1;sH~HX!$wUJIG1c zL+wPN|MdyTH)qKF_nB`#+LeD;gu144W+<S829_LJF?J(fN%9ixUwR!xqLaMmNUt47 zV_^27o|mdgw29T~`hA;d$|@LOe{q!r2C(8Flf7MslSBIPbQoM5&Szjmmq|PrlO6Rw zGGZ#`_puf03TV))(2?&}apQnY_N@PeH%o<9+>0A2eXR|YcbPnoEpM}sy1N@#=^i)s z0wfqrNbBh}fUaddgLLZ@LU!r)G)F}Bgw84xUkH^Z4JxQ*2&V}Oi5*d&ZO6Z_!BZ5+ z-o0>lQ}f9kC9!AN%u`|X;ZJz#N8A=H2M<^bT%=oMUlg}g$OOy`jm@;L+ai;Dxmk&Y z=dL3S$Nh097M3^nujnwR9MY95xKZu1Jo!;p6RaM5)1~i)E*8@o^zqiD%I_UhF2#j6 z69d$-McP96yYhZrjS)G@^|Xoix^)g$+=q8axze&jxHAH%jVzI`GqB*5D9q^(Xc}jL zl}SSVEuQ~mE&K9f%-65huU)kyoyi*iAp;kIw**5_p9jXj?>>Y4%UbveM2QWbUi0%L z=EyOm=Ta&pR3LmCk{&{pj1J)6mp=A@$l7u*zT8}ReqHi%Z8W3bow5*C*k=^^K@IJf zG3(^p&h|9hm-{Z|656?SoV=hJcx55$4B{l1kZ?5l4IJ}j0UovlRjKQ{hfVAIMExva zASQUgH@f`@k^IfMdCo;1&!%L<;Z-Vz^9^!VKEar}RzZFucvRW0;pz&mw2a7{=BT;+ zI2t<89155hP453L4!48*1Ppa+dCBCd5s4C<68SeIIt|DZ!-7BL&n3jj3g<x=k{|h1 zOFz)zsFTw15n&N8{+?-QEgsD$)a6dN&tSNALpJv>Vgl()#8BJh<tryHQ?QXL-p!ip zP-<qLSTS4lvka8AUU;@*&omYTOPV0mCd@5^jvc<9`I9g{5nUji2O4*hdR>$@hii8x zdtK(vDrZ=ME6zxTzxj(>81<HA$;H*RMm33Z<dgCbw|;4C3O!tg>P6X5^Sidk_eb1v zg|@cWX?o?T&VN5fFu=><CVgXy0B3o$<In;*(Z-UUanz<xeRD1fc1~ic4~|GL1fBt< z<!i1*MO{iDfXKD*CY!x_2kcxgOXJOTz2usJ^msg5r!hX>Y<?*XQWnP@j7pYnD)0&b zB@88zrgeXnYN~w_J?@h571}n1xSi1cC$DUV0}(Av%$_fP5#)pfJnQp5otuFAbqG_n zg8aV?cW9)hadj%0`geX1rNXnd+u19Hq&`(aJ_qHY+HE^;W59=H&SQbA^1ys+1Dxea z!}A}n2%fKhDkT#k<M^9^T_0aa>U``JJ|1aWtVHvLSoR6GjumZ8KPEm+QsVPrT_kTn zsVDfsDpZx-UIQ6Gwl7yGRin-B%K|&^^4Mz?V^3Q!>x<o8Wa<q^Z6#eKnPH{&`SvNm zsi!B7uVPLxPogYAy{aU?m)=!$_CBue5KA0{_ZmrZ9`9QM4pem>3DZ^SSHhl81ZRTe zr!-Wb>3@8BglOl_%BJ%Ajz+!|sT37A!PPASm``faY`jc~ZZdM(SICXNIOTt6%2X=N z;pZx>QiA(Tm4A}UxsV$JOk>7It~eGRQ#7@u=_J!jU&Mu<%{R^{>^1htep;DTL_-G) zx|5&oV^eZyZ_t;dM$)7mxo9B7s1&m0i_foIkq!<_9)mnwAB}*^V!p0$lz7_(YG2A& znGhihd(+?{9uvK({yVgMvdAsygfS9zB8aEACnoE2vBXVvdJR>FP&3Z%2Y3w%nQ|$( z7i5h>s4achO`=Vo;Mp2*?=WDEPe%w@y;A+*(e$56mqf`<tik}nwzT6JB6*grjKq1r z<yNxKK2k=s7nWF0-q(g+t}wW3y2~@!+rn-t%Hf3UjCxtUX_-<VQ|D|3LL=3*Obu$1 zt~4foRccofH;kBDio`rx)esrd3En8;ZN3M<IR(BQ(9dtHaVi?Uy>5hi<g=I9?3}gM z-ANPA)xRJH9+`(s;jDv2&j^j@pJTK^{UJ)TK{9>6rhdnI)hqWh4n0TAC_H=QQyt<z zFz*5s)ps1<-m7*ltXZ(l7|~Wf2ts~|NS4mdLL-}RI<q;%#^uTdz5=i0h8oAASO5># zjNzDh0vCVX?urfm9vb=d2Eba7;|{CvnJ<XbC+#GFj$~4mYHS35xCXusscJC~(H)_i zB^sbxPcSti^sktiz<3`})pv!s^gX0#>Q9b3zia{J1}4~{b@SI8X5rCfv4WuC1A}MU zV=wrF94c<=edKp%h>ii&i<s1s0MGnt(zE61XH$4vUsOU?FM@!vJY41ZOe2wxOu$=+ zvSn1|Mjlz>L5ne^((Iq3O_zrL2dE_wzPI4|YMM(1sd^C)nGQ<z4O!Msm2QeXM_zZ4 zOZfWn-hksb7u=Mnmu@O!x|jOKxz1`t_S!ax4{s*_7jwxC{P<#H+NYM*wB-{-`BGAc z7WtkRKnV$Oy{`}|MH~uxv>-SPY<#*X0lD|~*vNJ%0OA!!`FilN2z&R-?c)$>2a<(f zYN1F1i*AtY(?fGeTQ>P%tT9%!!Y}IiS?ia%>s>2IZZwH{(m4DD=JTrj^tKqkM_d0z z@V)VS$dRLK4RfRYwJ!ZJ!(*O{N);`Xzd80-ZNMf2*<U04&^+&{tN#_di$QI*gJw#P zMovuo!RD9&&VEXM%kelW_<zVs+>KS4tS=vLteblXHxJcZ#Z4L1iD=AhqiU<dzN!2` z!A_etl-xap_5$pc4-q*k#SoV^zdBh$ok3W!EgH$E=+F0<`BDK_0Q^2PlUOGCv8BbD zj85*lLfo-@T2eYph;RpO7d}=e`->8;xF`!O@<%~iu2RQL&GtV!0z|<ZF&@^_PpB0N zvEnCeb%vIDL056AXvJXW=@--<{U@{rIMh3MFXk)>z&nU&7m%Rch36kOD*yBn@X`ec zcoJC5s!jtR;tkIoE`*W79yGY!YGWNKK>eN#5=*LLn>G<^6}H>Wsl~}%%XZQu4Hb4N z7?eMo*UY$MbxQ$AQJ(q72sMdPZS?Hy9yB_o`7^02KSV#2aI{zN`d~tpG~YqN&Dr;5 z++uIW&&>;~)!3Zyvn-QgwjQ+mkV8cD7tHv=`l4t+xy)9wsO9~`AeX+6vx^=aIyswl zN?Trv14^<pPr1XV(ja&CsSTSA@o0%4N^r8{H!V;MAyeM&e<q_vD3YVh9+%sKSnwQD zPn8#CJm~1L0Xf&86_Fi#C*Naa(vOXZ_YwEJ*c_sX#dUrAgC3_dou=IYN~I5h)Jbi6 z5(l)DxfA%Sz3*SqdiYOlguwU49=mqAOa9Qtl}U%>O^R3-uYLHQ5^lsmDueuC7|d$K zC*OEs%2N$->Aa_7SG=Kmh~OgKa!>4|G^$;eV7v(>X&iWK9vht<tP|oIVplA{i3BsB zR-VhHOTX0CQ8G|3*uFsDPI|zkMEm+nkDtG+?ej&c6R;X?PycuNd8k6W32JeJe?67K zVw<$+@Btt+*Ai4VwPqcwMeIDz4cIgiWjf5Qj>8n)vu`dzkzaT>X)dj|UmLVeTAEFk z*fEpsmb)tRxpjxMx%N%9+!LNG1xWxUeYEDXXVYGM=i+FpUcK~kji{}n;a<5^g<MNs zl5_mt>y)j$R0i<tXYnx;A?4#7VX5LF5XIgHc|S(qH_z;>FzhZ)^-@eqnS=g7lIGj@ zaVQj-P{HKUX{1&YMBdr5Ws0AsZsB6c5yp`K8HoQ2wznqErimj>zKD_I8;y-a8C}#0 zs|CWqk^<}6F0shFN#FuON*_;Kj6l{?(*9(=xpW&>YXc5@gv1TuBJSczw7gL9jR$@P zi}Ge&0t-WLxAN*3U{8UsG@liORgLM`;e_Fl4&jm=D&uYn8yZ8-rSnPH--CG-4dn7V zOt7k}GYhOgMF5{B`1i<Rz<-TgZ%?GspWJZ&ax8>m54u;o)7h|Bt8Ck_GfsYpkb4RU zKMzR%+p<V<f=Go1&HP}R^Lw%_^K!J9^-9BYoE+2tMbgRngsU5)^-1$s-9g4c*;<~v zVU_YMy!;!oSD;(k<%vmGng5#x(GP?6+~<p9l+Py%OPkLhIhp(KRCNLP=yWMe1n`;v z-<6{rOTZnz?8*sRN~i-Pn{nq`r5&B*LFm=QuG!b>7uFOeVcZIB3V`>~jlVGka6b-T z3L8*U6HYRhUEa<E`11QJKSBR96jBBh%g|JIzpmKCS&!3|Zb`d=v{+u4ZGSy#w;MZ9 z=R9?jY67HVah2kISud^bZB?%Tz)sX`5tYJHh)q$%p-XYgPEe$)+0aiwm5PqzyQ`kb z=_c=XQ;gy|AsexiQ%B`etge9qC(w#J`L=Bt!*Wywm0JOW8%r6@;5-OA4j;k=iR_>L zVW^|TfcU?a?lF_^=;B$MrG1Bqy5-gVy*O84z_8d!&)?)x>_*LAM(u~?DfS*9mFMhz zIdDq*Zpz_9i%wef5kmVSNL#s+F*@TP#puWXU&UxKs+oF_&`5byCtPS(TPR0r_17%> zb;?H4X9RnMctQ?R>gs=_p+(~nb0jaeI7viTe1b@!p0FuIFPJG94Znc%!xiAmaB8!C zjzS_Z7TdVA_aB)I80S+qY<rS_M)T&pe2sCUPLSVeFQ;n~ZtDH&ttlt=$J1+9biHmO zrJo8yAygbSSX8M&C#?I6j9u8zyR9I^?Y778{%3<6{6jD;Qqs^8xl2huyz{-vsLCk! zMHd$uzrnl;6!x!+5l%|?*s6OFiKUv9#(0&n?%xs<!u3bw#8bny0sV!1@rtFX$TzB5 zqKT^3C`favoz|A>((H8P#%HeF=&^3?zL(zP_;>Idi`1EsP?8y8R=lE|*Z-sfr6)hJ zWUNnm2ljJM5uHM0I%H!Wm9N%@*d#N-=G-mgmySJx%OIUdAYaOm<IVKnEjXlJ48N<g ze1v?x*aAldbvtQC6DkuoFMrT>DS*jIe~!rfmuPL00YqzkHbGq|EvT7Lgixl6`s5|o zR*u{P%>L+3;jRQvvwj`55sgs@nU?BDZ-b-*!~|gCIYYXCCpLjW$0osa1$(Fv5_n)y z>(UDh%FC;X`+oodpmF^Kk&Swk)v5tqY&iym3FW&O4t*c2fyH=MpjthZ7}$H&Vn_+W zN0M=?r8nFmGv9mvTi$`!{g!u(2a!(}o|8Kz_E)YzRYk6lW)S9zqwC08m^Zo=G2XZy zF>}BcHXgmvioxXKO6uF+9~dP7k8Sq}TYg0JK|YTBL1MA|e_t}_?Fp`DlvMT3lg!_Y z!=<%?kO>6oGei+Ubu#+pv8^XqJK7K5ASIdl&2KKMys}i9Icn36J)H5|=`3yMtRt^A zm;^H!%6MV9y&<gmvHU}I&YgM(z>chQ<7wflOVs#@U)wSaCJSy_4^e77M=+R`Pn3D~ zJ^J_4G8TT`;mi>YQPLZQ$Y7&vK!V8A>OTtFjYEX*DT0<uj;$=S)inXAvPWHclz3V9 z@i0h-c!0!~$d1TVS0RSv<JV>s2F#j~(gU~;VRuk(8(%s@Vr<}77ddu2P5>gKWZEE< z$BS>QELSv4gsrIM*sB<G^4Vhd<7$J}_8VdfYi(UfGge~AOkNCpR(_Xm(JA_fW97}l z3_kwR4O<FpQna;6#Tlv_Zg1j(9PwmIEYxybw1<FBfw}*seDlv#Q~xcAhex}IO3J*O zQeenGHLEz5-CTpNW~ed(xV0bNe3y4;DngUF381Y$rZ`{WMK=m0ozYGmzmJhW=j0FQ zOrsFOoC4GFeDWQt%ceNEdRC(>v5Gcz>O*mA&i7SlqD-2;`z7qY|Ltj&%AUgZtsNmt z@qJnp>Y@yXvJJrUjvOYQiavaD<CM&Wq}g^Zs#!Ns1S+4)4mdoPyO!uI<sq|T9rJH` zQKeU0mhzVUn*WC_Q=yTH7s%#=&j~8xIrVtUiX=76IRg6l-UlHKpnzP+u`%PKa}Ux# zsgD_WMPTf`Y|Hnar8|Inxs<fJ%1`Q*A5mE-g&)zJ2c@8;j`u~%f=Khd(>sIFu@LiV z`_`|F|B{Nqd5b1FDm%g!-ODuY&L|3aCp^_`CUBOWTuF0ojoVm$O?R;@Us<b<)}?O= z*X{F*Ns3h>X9^wFmuEUJ?hJxWA!rYFAO1do^XU!|ss{+#Rhh4sJS)Epd`_GASt`ve zLl;$oZ@eym7qW^yLS!33y|47HG`B@xz6ishZo-Ae%bF&HBgBZ$M7?IO7IqChYp2=Y zHj@WXZU@D<b#fRAJH{Zg_=9TpIvSZ14cL~>A}PIGw-#TyFsy6Y2e)mvscuy+KRs3a z8O_Y%RZTt^0=XfU82^eoIx^zFcNzE;VJ#q#I|CBF;;eF~iOVTP#azyJGH$s0qeoxR z0MKjZgzk#qszovrd&y92(a%^JN0awFRk%8;GC?=G{Y#Q^hA<46E<-79m4ry2R{7z# zIsR>T)^}AoJOR<&ec}6`lcT2Odan((P3?@qWp-m3g|hY;-P|*v!MDf{O(AW@{-VPK zoVy4}P<(uH69#EhTar>IN*&z;p>DrIz6z49qVP*f3VF5=Q|4AVrvt8muB9zGt^PT! z^L>C+u>^hFK&gfl&zs2-ODz-X?vnVfKNynG3Q`DYxuY^(c~#>T78cuAsHZG@dSREH zTl!6ZrrUzy1;OzlJ!z$lbF@a|tIM)n+n1v<tC}YYifO~SgOT?8)NV0HRvMoSjZN-J zDFYvCO=;jCl$aw1<cdV%QpxZ0BOU#<{%Zxh9|XU?QXsSH47Hjzy+0GN@go#ZLcjJF zi#>9?*!Yo7p^yLlIOGAA8>m<ep{7`W@5hXLFZFbaDam>%ng?wvq;{KZMe^yMZc>yX zW937gV&E>}0{IbM2fvfc>vI@hOs?4B&0GeGi`&Zy*j*xZ8hBgkwov1&H>z|QCQ@^+ zk+YWedZ)}g+nHo|LfveMk^K5kAX6+F1jo(Ruf~*>^m@B!I{Gc^e(6pue}Z1toLE>8 zV50lz8zug>IO*8Pt!*?;TpVVEz&tRBIym3xr+G7n5ITXG5OVzXD!$KQ0(RlQ62to| zf8BsqJg|97ke-w*_l|iWJ>)}vrVkav;?9FS*;qec9?6HI)C?Ny+A}8vy_?lBN|Jd< z%I}$WwL6S!T@<w8GD5NLHKxtW42-Ai4kVR;4Lin^S2<UrD@Y%riPscQE$2g{4Ejbe zH#}*MQTYrgF}KJTk^0{^(YiGMKB)O4A84fhKjeeYf6E6U@y0^3e7VS7%^aCx!G>#G z)FE#;l+g8I41-?;1GEa;yHaMA%8V1l1>O2ftvizBS^KSzU}jil;@?U1{-1YBHZ~m@ zzs~|-v*(kYL$euOI=nm4-zEkBH=H#2TT^40VMfMTm5SYzxbdG3C;Qvg8^ZnndZJqY zmnSMa=Wm}zdAhsu?ZNv6MQU191%h!PgE5|<A_0UBa#cTK{t&3eApKtmUARN0DQBue zve8<Aar~08kvN~$ll7vQ4a&4nBqK1H{vmq%o6Puaa=T@ypgJ;pYbYP+C(4);{-5Tj ze}5Tph`=DZy3|+c`$EiFQXn$7dop-s<mE+iazkKgE<XXCD=%u`Zu%!v1&d>APViS` z*NU@+{d{-sfm1h96i{DcciXv$H-+Z<qeJtS#OftR(tLe>a6Ikf*K%E>eU4Mcp~)bk zm(9=4i7@*azPIs0EH@nq{0Z#{vuC~kQY4Txrqt`?S3D8k8gnlk)iN%zQ5TU_R%kmr zME|Oy46zQ@`g(3mb|)5Fw71vw!q<{%@nuaMDtI}Vs@TDYpqf;>id3F`lF5E=FOQr% zT|u7e`qBW>$Z}*bAdS3;Dvf}RHU+VEd$)JP4mL{j=-<5k;QK!>S{2$JgVXqO<Q$-m z(H`r;f>7V~G-rF<)a!>jV{64$YLP3*0{Q_-=Ic*KUIel%fXL>&2(hr|!#v7EG+pes znDA`X2kuzZ!t2wg3t@zR@xRt$ubhvl-xA2F5$TboX}A33C41r`?etZ%;Xe5>Hlw(_ zX)z({f%QO4ah^i5ZE`8&V}%)FSt3^gRLE(FPH-KZ3a)ndu}Eut?TrayYT{kec@h!A z>PK@~v6Y;J2m+PhkK^ClLQXL|E%5tl9JHHxWY15-;V^jCUH+|SkAr^k5tJG|Z@NFz zn87;o!P~Fe%VLjUBtK=QR$L2BK1Wr{@|r5&668u4<JL~#sOt_PQ0#)G7wd&Tm@|~N z3wpNZbNA0c{iF6Pw59$4siRjsKN{nvxFpbZ0%4TJ9_mFD$ur;Ps_J`ML1dR+`?e1{ zoLBOH;=8HHw#d9#^eToY%nhC#qvmysc$R}#@xj^a%yu99#dcYeCD~pS0)o8^`0xKi zX8BA<stJI6H3b0V+in%fXwG4n_Fc`bJ{0Z3t?3;b)TXu{YG1A^P23>&L7fUc;9(sa z;UL`Z!z={`&jiPWfJ3Ni4QP-ifp1dInHM2&1_vz4vS88TD+cu_YwwZT6Y3a}^RV+N zC{`%y5Rp0@0-`ZnK3NVRg_7pFJy2n?<kz-knxD9_=)K6g$j2dDiLBKj)FHBa+Hv~A z1tpTubuyU<Eeg}c)d_i8Amv)#2fM>RCTILM<iG#CgrjlP6s$iK{+^J&1iTT@dIjG1 zWa*w2!-AWx#$(cs3S$}Mwu3*pL>E0t9|9RRICNLVh8-dtc6q7RKA#zn00x-4gL<Hn zZBVNPWGOsydRZB-SXA_{aFgOlctqMMId|~icC(v+-Hg1EV3u-w$Gk!gZwp~`qh%OB zJjjR|L6r8P8auFUc>iFzZQm!29PPuJ>H_P#MP@^xAajC%d&ow*iOmG~kD|BYmy<4G zE}12_f>IYz_E9b0DyYxwQf-Aw#iNE_b6QG6K&E9-yE}0XH}Q>1E!n>Bh9?1tz{wrs z6H{pmEv!2oBfLI<*uYA4ztf66tJqL2@GAZGj@*2Rr9=)XIh&3+`UIg~nCOP9z=LoX z*Z#d_(VhN>p#*pwTCM=sO(L-xqh54%mm{WXadi^DW#bKugP^=UNtT+Ehkd_h4zOTS zSo$~!e<6W6W5QwRB<Gf^AsjL{H=u$>Q(nSrV2<v_o;uBzN-WH069hlie7Nh1U218Q z(Y!DtFzY=hO%DMlS^DypJug!K{E`PIFIp}zzDuYGe>)-826K>UB6k-8`?!ASL4qW! zAl?a60vMtW<FUk>2X;g>-;NQ*$;N@o`a1=<AbCmAbCaH>I{MKi4Dv%rICC|l=t3eL zkif1=k5{nmzMP+UEr|E!6j<dCff?^+GdWINXV_zybm++vT?`P(Dhd)ShM0%gA@WQT z1OCOq?@7Zj;ARYXGn#mAq^e@7;Vw>&>L~f%O!9q?>2LJaYtsduFJf_WzFBsj;C;mR zR}$P+5ScDm!Aq-{cyU^Jz_ziem^V7TftB1pG9<@iF6_F2@oC=t82S&5g48X9RqyyA zJ*LHGK>m51Ww=f$bF01S@yPD42>$u}2X%9?m3DD;FN`e<tByjkU{jWDWUzWjmgX8g zmvSEAg2%B7t9*PXs0Jx3q?g>(!m<CF4?mm1e8J=vD1+kM>snd*Fonnlwg@l&?&7^g zeQK$9oZTMdX~wj)m6p(&gRP8^@rk=CMmuO_TseFMo?3Kva8<IYDW*UY%6?~@7Xu4Z zmp~&WEV)4O>=^xDzYpOrzysO;!`fShMY*<Zpwdc;fHbHmEg>B;E+rHR5h+ROuAytd z03`*aW0aKc7#cyE8M;$ohOVK8nAs1m<@&z&{q}L}Kl?un%=6rFUFUViWkY6k*^u2S z=Ou}Ta1PRC0rl;6)urZPFv|4AYR4<zf%F}H9bDET5ErkBK|Ok|^GP}u;&Jjz{TvHq zck}K^Z$fj+M7LGyYA@+>t_fvl{J5Fm-0-kzHpvfgTh1EG3Z6{7`jC6hP@-bf4x9QB zaMayRXzTvS@sO`^(cM19&V2(zCD@AgkAGQkp_n$BTJ2*r#LyHNN7gKv)+fKMp}FtK zglixMM|GAz^2rZ4`c*}xh_M>jmg|xpWyeEvXXI9xRQ2x{F8e)bX7dT0$D36R*%bb= zQfRzvwac5MuWl}VU>?sRY`+1wx^8$tU~>W12{xpu^8fZvf%Gv(2`fc~o#ag2Ol{Y- z*!i*!%H?{1VN~dWa8|8klIcS@KI2%%LB0}(Nw+zhAn?!cSld8m+CM<JBh?>lAwWxb zZiZ7%{!Rl6Sy*wi@YEl&xj%L@vAZ8ne>dv%zj$?;x+c{`R6dnNb!Gg4ja7QThgb5a zD1jL(2VzZ?`fSLpjBkVS(?n{NTQX}^A+_v4I+;iP9h&`!9aVSlEQsR|TM@1Y1l}O+ zHsB#8EZ&)q-9Sq=3yT8=03#Qzn_O`a$Nu|7J67(I5OnO}O_5m7%sbWWBa<U=wHB@! zt6c-5)fEu5Cu+`beZ^f*+KeV36_oqlIH-}r!sU?QBuN?g)Hg}1vtElY;z#~8mV*PI zA@B;wc8YCV>xu9_A}<E|Oe^PChj$5XGaW2ufBOPVKF=1Cr4l*SDWrW7vClv%9SI?x z!%{Y11ec%`MgV6a{Wz&74XVfPR5bhqfQN`3{!CvZ(SOnLsKo!9j<?#;1rl^%P@nF{ z6}_LW8~!5RI};n_KRYs?scFo%2Gu7B*;}aU6L5?l14)==uYfU=lkst)ch2+@qVvwd zkbqjp?1Sxo^+~S<)&Sn9njd{0p>~5(RHlyTPX13zqYybd-S+miwnY9$epH2AMcxi7 z{aq(mZoKS9m#YnMkCaqMg|MC<-}`4)k`Z(ZXF!Xyrv-;z$Dm$yBar46#PrGJS7BpQ zgq9nffjdR}%p<%w(HLgx9Pw^ouQ67ihed&or#b6S5jHAbvbgZ)yZug|tZG~K5&psV z&e7bKmXUArCOm8PeviWLMn6e=3UBzQvn_Z?RYttkw~Qk3@(`dA6GYQL)Qz&Z2|w1+ zsSPA)Y}Xi_*PZI}y`a$aFk|Uok3LtsO9#l}ESQ#Dk=LS7gvD=q_Ua9$gD4}+o06mL zFfzuU=%ny38ae}Vb^{s%A{W@cj#o4&(v1CLXc07!yW(h$^Z-K;oJg+#fQU{={sfcP z0NtL=q!9|i`q963w2~8aF4Raps!ttyS9#D_SfIV2bjCa8YRq*=K>O!5`T>9_+tAKe zuT*LvuNkI-oqawyB+n|d<dFkeH&zk^;#2~nOE2<bp%hv?J=9UfDyP%=1FvE&`1oa* zZssrET?~X&hw;(_kuurh<x_q_`)f(XcjoI8v5Ypc-)R7nMvEpCXsZw)eJo5J5Q*S< zWbgRArF0PM1xYMUimc6F_Sg&ahsG^|oFni2lcr^pnod>5Hk?g8;N^ssTTs>F!=5Qf zsYdMlDYHYZYmQ5mc>`}8gsqdeXO2*gFaYmnxg`3qCDPGcGe8&nGyE4GEnJ*$(2V3% zuS<M>9>LRcEZTSh(9QE8^Ja`ka+R&BvtKN0e+m=tK2K6QNsC^*!nBt6W!eaf_Hk5L z-8$jAwum|ZA-m3eqH(xwM+bM7#R;_*<K6kQsuo`e;m+ax{mr#B(GDFGlnx#;RjY6* zfWA9pC}bUFX9wz>|0d*a&vA^fiG@CtC1N!shRL4Vdxxv_T;K&Ic}<RECLsgsywgA6 zc^_vagjCmE{cz#jQ4Zq?k*VGjAelb(MQDV%QQAHXHV<MJ^S`G$u7=IOO7J})SLo|~ zJ3EzMT2E@J-zb?779BPMJYLBO>?G}hWUzPcypVt8!<9s9mE{_2aE0>D^38yRpS8S0 zAm)OGNU<Q+L>%bdA-8zt`u!TKweU`upw;w1kA2TFq#nA3$?hYMFDW~dN+$Lqe%SEl zx%6(yNzrHF?ycDvxO149L61EuZv-B!O4Hm$lQ&YMcL=zlUqlS5kQvW{pbk>2{9{y; zT@Yh`n`*(u1f|pVe>AP~ZCNH*sW?9YRid=CMT)Mak9`&p`S<GakfV<7FXt@jFL|{# zhI@I+J^aTc%&psil_Qdb-h^seFj?I_F#q8L6Bh@p9Awlz9o^9guLn~glF|#XQeB?Q zj7n)N$X<0j@aSL8qICy(3VMN0rD!HTj`Ww%jgz>0WR8ntHZ*!H3)J!Ws|kCiWg}qG zU7p?hyM<b<OMU`_>F0`O&kM#n`4>Eq<nxLlew?xI+p>VUJDW2TxJW%pqUO~hRAK>T zCyhw{r0N!?!@k*3*jq%dx|RGqsarNS`QmPYqaw-at}n3vJ}9`S2Cyx4I-h;V0G}}v zlAXm)0uS{x{xf4!j(LkgsXP9ae6*30JLV@`heT`SO(EFTxeaj!Q?$OHEEF1+tp;nK zo}i>Gu0iO&(x~n*SW0^4B*=`bx>CN6$Xcii5-k3TB>f_@s&;XB#o1u9`4{N+tAID0 zF$(z~y1J+}=wywoc#v3?y@#puMeogcb(t}>0K%sbY4=z`T-+=M=VjvD080uTFq=g5 zXyi8hVkmh*MpYhvk<+IbFqgdB3@n9YY`|-cn0cE+GhQ$G@;grJQ!k<;RA<hlh35SK zh?TjY0dibWEnD<fg>Rjp-{JdYbwmkfb=hre=|{H}29*)5uwP*<3v7Q&3+mUkjNmw( zY-dMBqS@~I`z%*C`W{ympnv9nK?J#y^sjZ+4Ojm>=ffU-+b4UN;dAp&Ok4)9*MTWd z_?Tl+lvsu-;6V{mS=#z)dG!Wwc^SSA)|M9LB19+k<Kot<!b~oZ*jC`mOkn&uZJ~pz zmxIxbiDYLz?Pk5U^;~8?FZrSNG<6xA-|M<#t(!Ydf2QeQ?gAo5F{n{uxxbfbD!_M; z07iblG>tx=4rMF@ui(Ko&VP}TkBUzh&%rALEGg&U*-Po$9fJShEym%WqRd?F_Yv-y z|8Mg*6ci-M+xgF*_%BezEZZ52xo89b{^dt}dF4|&jj(*qJu|KJ>Kh|X?<1K0)3{{u z9PRtW)joRzIJo%>ua%dYsw96MnEW33lF;ILkao--BK=Yc=ISO_#}=`Eo@cM&^Iy|I z6m<S!mz@sip;NPOQ{P0Y&{=*kP$vprB^u#R+}^pz%gIhz_lU1Mi`zGTVs*9Q1SO9c zeR?EMZ+Mm&HaNSYK@wZUn}O;oczI;<+S)o=1fZJ=4>PS^OC@9>E+i>5NqbE&K_*GY zuu{Dg)bvOOLUljLFer95aX8RF@QA15HHjp(B#SOPK!~)WFMtjQ`9HZ3#glfXgmZH+ zc-(g82Rs`}KZxm<5SiBD69kDA1=0itw1i^I;z>Lx`*YucI$$3%&&{MNn8*(z>-_(` zq<hcsF3@;J(<?`an)F?p4&?huow!<vnptS9B}`i~gz_%clz;6@neTZOIgj{k+_Kdr zQ2^?33nP^S5uoy38hI-%gG(K+yYu$<qP?axPNxf(9%Nf3awC`uF6JTdDJ?Q*wa2f- z`#(~&blwtz`+8rYl-ernkc~C9T0Qv$QyX)Ksc}q;NXzYj<~r6(85*LA$`8M9B|2g) zl!9+pbAiQ=+AC_y-Gp}llm+hB?Id7#Exi3mY2(WpiWmZ-B9M7~A-ck4C$V6=Aolg` z8vwy5m1z66y<&7GxJ#xaI}|ZVT$_F|ee6y{ROM-WAA@1qfg(6WhmI07(tvp-d(k2i zZ;65P&*c^LLK3*V0*t~qpsE!mwx!s~3FK#c_-cGa5L}7?c;k8LKtMN!(dD87Gsve% z0i@_Szfr;2liWS)*0G_EzI91YSiHAj$!i@I`#p=3fZ*{s3x1!8%!u?v@LJk`DBBX1 zn5rkEQ?K+9t9{ctS|yexC9g2W7udE?^OC@=n%W?*EYOV)5TBzJ`>+q+Zg@N~x$eyD zu;pw*AYm!8U}{3@+;qm;32T7_o+T2qn3RfXw}6~T4VHIMEOjeqMFCTqb~5Y*Hho5O zk#9D@J{vG$z7I`c*p-tjwejOj;#X(K@3&a7_&kxYq=BRGkRmAoa90%gtC+(Qbf+SC zgQ&2Bs{T)BLHrol+dprWSS&(|3YhXCkz-xLgq5(;Z_A)@vc(<*5L+(1xcHVih;;OO zEF`#K%mH@a6^JwZM;Dizee?Y6bWf$|ABO3O-fvml<OCp#d*lAMEUu7BD6FX<3Ivs+ zPy@|hNzm0IYB@lXF1+MJ>e#O9&-}V_d<86dD(CLck}<fz-*unI5K7cUn0^(5ihMON ztLL0~4bl)8jl=hFH6z~p@oCIwE^g{bm6)VMItqy)GrF;h@U6cf2mD(ePo8m7l)lj{ z-h!#b9`$%8hO%sBIF>Sk6V>t9%-6z4XO>uJ&R!2To*OLi1>jYNF;~#vKbAMLp7?}L z>WqpD*+WQV1$6y;Wu*fSFEz*eQ)3eTzr@bGPAe#;K_s#Oeo?oKl;jz50S?37ppSRg z8L(1XYc@;S4o(IVxKvxpjN(fjop!Wgm{hzHevRgbhg+A@Gu)MV0#A{RA+_KcVg@pP zlgG&Qz9(`aHr+Z8pdxa@7ib(qMUt<%r*x&0WXKV}^{sd{K;=Ofu(w$FzW4Lf9muU^ zXq)6lb4>4aF9sCseF$fo?s+(rk{tuG)QDUOvXIiYvRy7SNVO~sgvcdd7}y>Thbg3^ zG(A%Sj<TBqV)D8kG7JolE_u9RiPGk`^_Qb_OQ<|{r`@G?CaJ3MTqcl9a+u+O>*khw zb;*0mmF`1*E9#!ot0}Vc{d3S*zo3PKnyYfhtLwfE*&Xd2SUsNs<<95~$QbgaG?JC` zO=(=-B<tj2PD1??wez(7AAfz(o;0vqQ5YWtr7QuRJqG~be4i~|kh3tf9x5ggu=@1+ zH$YMQ0l#>+zC>Gv&|gl2NH$tr>PBLFGDFITYP09+v*%!a6a59L_%(*)XX2rXDkK3S z`$F{Hr!7l+=V+V0b@pB@b4j|B_^=stM?qOmr>{!IPTLRo7A7yLha7jPYs<L_4Jm{2 zU0je8&$$=q7q(C(=WV(OHXnNfqE<HZo`Zai3d2wA#ncUXPygC-d9X{cA@1bFieanm z*+;;0y+8p?sof<T0k0c@@$$L6ac>$0$Fb4B?F0ZGgAmiLcKQZ7i+?YbpCBc#73Y?> zp`t(2I7D(bQ~<5A;iuwTY4wom1{XD~lwdtyDB&}lYy>0=6#K!dCZm?Q_ipz;AcfWR z9DwB|sf1VZWct;I_(C5(?-aYGfEOe>(hqufuW%=uxjFgTM8>yLS)FkWN1ixm=AKg_ z;f)X{1d(%<eyE=<0M>+xd*P3xv12;CN-xDgKkO({G?XB%g2o;zw)1dSyIX1KcN*Bq z1N8S%z|rtV=RpPYnN+%603}F9$0hAIDzUII@V>sht54U??#EN@uUg_-lT@X)ZY=O9 zROVQ&Z*05Zn!I7!S}H<$+e~<;E8A^W)634Ii0a>aNxc>5fe=mx=pN!6hk$<B5^s`W zsJnomA&zA+vdwbxuBdPBOQZxUZykIeAT+si0I){cx)V1J_6?Y)N@((F4GE?_)pwV| zy~a8Az9>>~5Q}BTRehzv(%&DW#LgfsypLWk2%`FbIXd2-0ih%+SJd7%o=<;2{M8Cf z$<i*s^b4G)DE*0V*4&jV@!qjde3gB+Zf}2rDdz+v52U5H@5mjQA)OU*Gm+2EsD?_? zH`T@GqAmE0z8Q&=9a=Lj?dT1iKPv8~Npful3976>&y)_)glFE#>-7W`B{)-s$b#8$ z>!t4?RLqgBDL;XzRbJ9Hw|(ZE0NSmS!CI&$6EdOW;^df8aM&aT!_tlM>twn`a>7Lw z@czs-Y{==vlS0PQhyLHfj2tM;Jf;sq6B^^UCSM*S{52gU8TdGN_F+y0hls&$1b4(K zVrB4*IkYb30Fh9k5`?at&+%&txg)Ru1&AoKef=ZhzXgQ)holSnYu8$CoK{|Q>%CtX z_;7N|E};H|cy{TLgd*14rp;@~5$kksb1W^6J=tPCm!kO|EXJ}*VoBr_<v%03l*wp9 zHJJR?^TueI-gl~U`+d|VSSLWG*!)eXT!T;?#N%`_5SpgLpBBJ#=AEb@G&KYg{G~z( zb^t$*#3pNH60l^GfP4^un8#vWsf<20Y3GgM#-oVHF@CxS(WFy-R=gl(=mQ>~lmT{r z{@&-5OCHcDVV*w%2*7cP8w)$oSNkCm3=yA1w0=Gx^{WP)B?<@tXotEN#Ef7$YU_Be z6Q^WM_sl%dWl76MfM)V?3ZK|06&$e1N?H(b8|QZwEQcy@`N>_)*aFepniRkvNHX2R zOHb=HAM8CB%NWmWmYz2@T*POaX^GIdh{%rc8=bdCJnlre=oxjAbv}5GGql8KZ`E3U z)8iPPDJnMv>B-FANa`1bTPowYT8hqlkct6zBFqekit&M!rrtyL)qyoDdI$(r4xLUM znN2;Ez&;;sC~=PiuPgMdtIkHq>F;rPi}jY0D9?K(mNT2##6=<LAH7K>X{r!|f+e#t zEos|+KpHET9kFK9A5>KI`ZDytM*Kg-`yKB^23i-hpQTFR4AKkBSc*QNm3x-0+V>H2 zQAe*L{3s1{NpSX&-%k{c0GWit>ZIc@=wivw=CR|yNBwMqFX$Etkj_T`pb%wJf1?m5 zfjI?+;=@dE$CBzJCA+^6=Qo|peA|x@y+S4yTc8P(Zk-E?B`E4OeZbXoe11Z?jC<QV ziq+pn{NG+{<jS5{D#>f!RUp%jZwh86iu~nMA0HqoJLY$~$f|iTJX6GU!7gCZhL?Ku zD%4I8=S{$tx`_lytjIcjea+r=?Y#|!eS1{P68{jJUV)S>)IrbfRQ2ZEo=|Q)*q9~j z{Er~e+6%yN+CU_p^yIe7Q&WgM5AN{rPn7nXSSi(gkzc1)PSw%Ow8X`s)>@4CU(Ql> z{);+bZoBt?;f3ti{{t_u{1tJ2H9PeiJy^_`2<{pM7^g~sRii8;HzfMb?bW+EnMg7D z&4XW_*W|h{QWloUzQZ&!zd$f~m>2KJGL64_SaVF@q?<D3Eyt&`*;7_`Wkc7@0ntpI z*y{F+Vm5rm8T9Z(tfzC+N&+bSwy&H}iWC61OM+{^@%H+!qw@fihFYdWDBWCCRnGi^ z+^3*&<|F^24JhI%r`dd8&k!5(6+Pw1I|$$p{l`)AHwX&kj1#%_s1gnHT3}Gik~Y9@ znFi^T5GYGoJd(v31Rm^UN4>_ev>YK=_4rI!hGS$fZDWM#ruE_arG_e_vhS;VN~Nfp z9y?SOS>T2$1aKX=fH8^Rj09iFnoyB&!T^iM$osTzG<ph)8aXaU>cdsKJx{f8818r( zZ2X5WO0X?I0kaavj%5A;7fN-*4pZcDg?z^?$TP+$08`*NgF!F6Fx{-Rjyp@aYc~Z> zJ{chBHSCzjERt5aP7;XnBvUyt`T_4mdh(q_CV1Ni(`vlM)eYByYBnCbiyRK!qZhV0 ze~GndH{+*-n1rU<{(IkiItR0zgKac7@5R%t#X=R9?*0$2SiVQN&v{#g!o4_UndK_; zGYt;{V}rk@S-4{c(va(T3zD2h9qntF$F^mRj%4;cUXQ=ax2fDE(<57a!|Q6$wtOB} zxD=wKh4D)3M$aA7KMXWW1l+S{I@H^hsh95R0-$B_wVwwjuGqd8pdfsvoNBb8V;|qS zcy1J3DG%<eNyDKh-kV_g*>PF9_h~bURo~~Wbn!fQ1!*^<a=WVnCPKa6&l5hA`-i<M z|L&5b0DIr{`JA7L>ks9)!(c^=CpAUmFHhGnS&|>p;PK{BjHy-+>JiU7WFKx*ZTe<2 zXYd+KW;V^n@M1cniYm@}m0GM$w?~*xs_s3hb|J0SN+vx=Bfr1qtA-G|0WtSQvRVL4 zFcYIXtWbOf>UGt&s}+8T`Ov$s{pfiBcj~mB@Zm*#c5TUMq0g;ov<(WXt|=EHR+K2F zNq_J!gCqZv!I40|!s}e-7PE`^KctHPUw9Kor2maQ#Q(M$_)XS$ME3syA1MB@l-NlO z{UG+&P3`b!G_=ypvx9Hf+~eRkiC#bL0QvryJVEsgVpe@b^U=BG3TwCjFTn#C`1bz| z8N6R{eI=2n;=YElip|*6GtJCI|ANvy)XA*oT3=0m5ysX_K?yA)^)!vTLkdtbtotg7 zeek*PLhv^5_)ZYjgdRj{#ENAUB#{K-SElIR<oszo<Qsp_;)^J;QW4y0Q>fRAEYhDh zErVv2UMivZzmipcR@6Bab(-U~d>;$dJVAB2vRi6<yty8A73krUZ{HDrhMOS=cnE*# zjdwaU22}+`YUJYgON|0O{dx`gYHRgN>#nY{F+Axjz4gLdPn4!yKNjoNwI-S=%xTb1 z^}a%1t8fiZ6h**j2Jm&oQ|f6LUD!6S0isRDh3ic+Y<#<m^W+Wq4XEmbpf@db3MnOj zmO-@DAF~UQ6DzZni*l)T-GdL$VGv4AP}?B_5VhAP=P#^$65Y(tvZYkv^cz^VM-|zB z{0ML@Jx%Yd8n!%-5AzKh+qO4J7|44BR#VMjIg-320_$3Lscr76K|(5$f~Ptoq=J;x z$|5)MRLq$Z`?uT)J&3n=qYm+Xk64xlzRUP9){;)lg(k&ztFX~?bR;1nTeeyZ><Vjw ztdjhuWs2%=x-VQ=U%6xpShi#vSn9xx2_*}D*(~5KESRe5{Gt4HN&I2otX))en^C62 zxxZ!#77+Y2dIP(zhmq<5DY5gbBSlDT-!a_DuKYyK^*rnpFtP9?cD%wy<mh5Y9j@F^ zR!b-O*685rg2C|#hYEKZf<ANR2T@2}9{fH7i1>v3gtGSS4;Z7m*peOBzLE06*-URI z-uUpVW7k}<8z;oIgcD!9^QTLpNi8<~QP)FqSnL2}8CEls!ZxXAZC4j0;GIpLsK_G= zY&AXlzB6OC1+TzI>fxwN8N`;jU16`(!Qdk+2qmnG$cokRTB>>t?%u9^7wDLXb9d8b zJ9-wTma|tt_~-b{aQQ<5xwL$E1<wD)<ne7)wiZPQd}pcaY4WVopm8H3wrEz?HE5;` z{UPw)s0gra4KuTaV24E7SuVGTglRwPS5X#UMr$hCc7nR$g3=yD@fE9`eJI?6-jQDO zZ9@C5vB`(O0Kpmm^alSY5+0lSpG{@j4M&s<b|$2y3BC<x)`iq9xCh=#fS(dg;?`!L zZ6G9HW=~w9$(pnf-{5Naip>6vaeYagH*GVSB)cw+F5N`bJedmqk>FUvpMvS5pXP6? z2bs2wc}by_rngmcll8ZXAaH}P95;cl;~vZ_d52D_@Z)UgK+pnjuawRQQakxGE3g3; z_B9KQP+g5^qq_|_i)!&)6z7Vjx7rW!={{$C^)@r<lk^9k{;iqk$u3;A@s7!&{5U@* zLGN^dGQI)XqX>6Pqdgkh@#$>Vf>j_BiWZ?al0<nvw)93I>oBM@^BheoD+XAOvzc{Z zS^0;{$VyGikoW)8|H~=APqax!qh?6tZqH&M5nWP`T`i}y6_Md4owm+P?ayjeIFqj@ zU|0!Kv9?rE8kd@oMx$U5gY~{nG)q>f?Skh_TUw+g!SRR*7<VgB<>1p-c<uAN>KB1g zuq0YYr#-;%np9N|GhI9Hnpq3cjXA#KkwQ27y~&C|hoB%gf<Ftwc4cN~i~trWCQ+?3 zNl`9aN=HBUoz{VyW@@@)!@;*{M+Y6`iF`|bX0`jJqD78a4j+kEg0Id?ZTN>ww3P9i z?KbP+BsnSd%)wGb{pVz$&=}_jM!=+~fcdh3--5Qu5GVH&+KH9(w7$6~&WHQ${5#k3 zOtg(1k9~l_xaX8%1E!VcFm!^d(tSM%JD0z?uyt+bYJ)m>B6KBf{@aSoJTHX0`{{zt zf|MH43|U@H`m>T~%mnIRI2MM40Wu1a2;)qo;k_+gjzIRnlpumxHJ@PDB0%+?mL6r* z{{|(c^Rg()(&6)AW;*(%g1$BrG}R}nH>6g6xH-;b2&)|K7k?<Kt-1xBzQT+?G01t? zi~yiP%l@RejXlMGSK8aZO+^5s6f0DVZao>&itLAJNvU)+(9G^Bi{|!3SF5;JLL&2N z@2@9iL5$d})vf9|B#fD#TO6|p@hLyZ1p@r^Iu|VO-pEhLek+&4c4B+8wW|k&>l<P$ zaiMA3YmjYWYndf4y}!cjmgsA-2E`${p>=5ueG&BaXJ-4qp!&N~C90VL<jxdT>u5i? zQcjwAX6Ntzjt1!Oq68k?p3k9Z#)HM!)k-V@bO~123#Szcd^MbJg|&*puj9{0?0>L~ zLF@nV_FuW{XJ%~{JDJ+e-x<~;4?q~KPh-!+b+O)V7L|V0v#wbX@ws~CQ3+DzAs}hu z4J8=FDKt;&_ZZ5;-5%WmVt*VbO<y~HKV_HJli4r5H3!>Ka1daZl{WU2bdlM{dgo1R zXc*76tvlTt<pymSEH6dQ_n()>FXN`0uO;zMBC3=eU1S(3Srn&jIsv~(-^#_|)#sQs z*$7O-a5n6^Qq#JV<j$02fcr0g*oN1lE>gU?w}(qfh-lWCw)q<aqMtp**{r8AFeNcT zE`45)ziQ{-x2E|19K4P7R#Eurc9#3$TV4M!pM6Mbet89m*Wz}RefO|3kNWBKm)DYz ztmgrW{5TfFCvB>s0>`H3nTZ^{O&ZRCM>w746MemO7_*2gD3^7syWKGADb8M;Pd2t# z@P*VO!I8+@3xj9FG9jV979REdf)d?Bix(s$SA2)=$x)_~9(-(6hfYGA#dq(-Mr@VE z??q{Kog(;lrE01bcX~P{p(&svqfpP=egDyHnfJ%;8IT7LpRjfwj!XrMof!GGl*pd$ z_Wxm8-DZ;9M__glt+Pb$9AVW*;Cxn6P5Bi^D04bQ4SF8VfQ89gP*$YP8N}WB>op8P z#I**kSuqN-MEuo8ta2YKNJi_69J{^-Ec*Hvg7cm4U)H<+xT3tq(}FGRb)kB=^{&u$ zpjT`<N4HYvOB>+jqA?-;aHe~|A-AkevNA)bAtiE<xp!g~SqNW@(0Yn%pu2y1G`6~d z2k2mha8kRe3B3DSkW8MM>P;KNT7nIGgb7a~1vieOv%K;|v(H_^zW>V_Q456u@AEC+ zf3GI$+kfcR6a*L4JXx*-W~kPOTwTCx`T{Us&cpk#QifDx0`K1dEzXD|wF00&Ya1Ds zNtBTeb&z$Yk99q!G^AOB%HX5+_ZQ>a#evpa9giNLc`x5LiRj{PY=IKEmb%YzcBHW# zjYxSZCCy5?=*O0+ut~$AUYq9|$20#X%KaOp@X~=ZwS{ryr;VvfQ53~&BAIDBxf>Mi z?%3kK4W1JmX8lwbosX@kphYb8r2cB6mjI`!Al1J7Tis;>TraA>T{3$^!@Cg~)Buu0 z@O{>(CjVxGykMQ(Q_gop!kpz4rIa2S6%P{<2tyB&HEHzPytS~kWauR0@?hU2*zg?Z zJFXW@P*V#T&tJjsM1rohI0~;{VV1_189pZNs0)4875q(Olx>bU-9q7`sIb!uN8bQ! z?e|1)Y~t+6D`T`el5OtwDFvfK8qgXPFV-3ItbfrdT%xO6ZLC%PpI!3T;05|cLTkIX zh8y4mX(0N53lygK6ks%1ti3bR9(|k6A2Q9E|LZS(?fcv72`&BBFJ$&&II&)U8Zzuy z+{~^G?t2=dAEzKfzNL33^IaTjCcN$NiZ&{&<$B&zF>U$+$|q;vZK;4V^}Zn^<8T;N zQ5y4Q`PtR&w!~@yxFW6x=XDK!pn}<q<hd6fXUNR+H`4!kmP}-TCZj_<ic!Q8@PCGb z(%3_&*tZ*wXb(&Pg8K}B7KN$9LQVM7?q2+lKjnLCH$Xj2#U|?o{7$A~MBPTQ@7eJV z$Zhons&la|L`F%LdW&bZopuEZ&g=p>;41$$L<B^``fOshBb$>IY4nXghY#SBm|Pb) zoJWTGHC9UL|6M)ly}QtQ(cKb6z{kgzMo)H=Ur0+bm7Pm9**w%$Qcy)<RU=c;TR{p? zQvyiw|5a1=fl}I$s^XLFx~oKFHzjdyk>~rpf&?U#Zbpa{3553|Vd85RI2r0IdJ1E; zNajL&$x+8I%IdK-K1Ajxw?}DBDZemR{9lfr8D)Skv;BTjgwghVGcM~{Y$`+=H0M6v zm;(>i7~o```XstGpcdHuL9MUK`~v+SO_S*<KCwVz`s}Ma+ylxFu#+_K4v<cyz`$z8 zZNLubPcZ|Segbx~bLO$CIjSkhb991n0Hd^<b%{}<t*vc%7@LS?IPl-*K67sZ-hgU9 zMeHqyb2RXTn9Ct*Q|9bzBjxn-&gWq7I0T59)zA}wxN2u?S_#(&zZXAC&v(#jEhzXQ zJj#$J%sHa&rW+wREc1ZhdCVmJ+3DgC4d#`S&M9TG#2winUff?aHz#{$<%Vk#owiqY zmY|T`<N1>f!E+2(0FL!H|7-I0e@${1K+`uS=p-2#eu}e5Qchg4)_I>q`sXw{{43}J zz0ms33X#6musT{WZs<8{XHc0}vDn~Ynz{s!g69FRlabYd)KjwaazygXhH~XWuDWBj zyGPp|BKl?}d__W5hN*CYdJXzSS~O0y+BYonQ)V7PFiaM$o0r3ymp6QU9u&eJ@C<`m zw>>}qMh_ekTWLDjvCGT}%fp+IYfoS`yaS}Vl)7o4V6%p<VsbFRpI^Pg@8muQFwaRe zBj}{qa}fe854Aup&ZqVSg^N%>CliOSnj?8#XSR;+x*e0!4%uF2MClzp-#8p3<;VFO ztwpBBi<3G+8!`nN#=_PZeVXyxKiM#ev7=LE&_66HVD*WTY0xWuB<XmRdxGI~l0hj! zI)TSCM-PO^b!*rx|FDG~)4uz0Vx_t0J@Q>6XR1T6`TT+3iStrM+W6&uN%x*>@P<!b zF6U3|z$&1b2}`s~gNOqISNn?jyGpDT(qMR2WLFHZfX`1+@A-=|Dk!cl4pNg8*uL$k z;=OCqIAi7%+{&OsO;TxFTW}@l2S+!Y*Iy|E9Mii2r0eY$6uey9-tX(42wFZW6awOO zj|-ou4}t_+J}x7k;rwE<7gSR43{-?yT}-(<Yy|Oi@Tc($@Mth*k{w~G@`pZvy!2VF ze<8dcFG}NrQSGXsTr6XL!Rv(7NBXPbO^xmYYdDPpsH7XA2fpL6I@V!9Z(-)UW)QM( zQC!(6iU4zv>LEX(D^uPE)20FkY9^)GN#67tgqZ8d>E}}PAe*GGTu4dy^5>$43)7=M z)n)1g*#!bV0)v~aFx!g}GgdmFZB;j3xCt1i-(bf#ctkz>Af-O68?Y#7mdBv_1E0fa zOI$5ZcmQ54K}+kQ5Y3;JnZZEY0ZRFTG-~uwO%X2w0qN?ZbmA<)hEuVvob(>>eh3_M z9N$&%uL_%WFi_9lx~QP;X&vS{aCOk3=m(*w)xRsQj&b9{X-9Jj>O^k^wFz^6b;L^f zKX4YniZAI>11TeGLj;()>|f9zj0V=5_63Ekx`Lln>|^LR`iG>ty^Xu39etL4+y&;X zP2oHQ!7nC~m#9S6+~gce>Akr%-wL|2UA@ev5GzP;kvRwoj&3Po*|-U}x`Pr)5U32H zLz568r4E)k#e7)VVEie$l^o6wcdu#{c^W5xtx-q5cp>`7Vxx^EorP!8sofJMH{Apy zv5dQ{fK6vLi@I30pBzJN$gz8~FQ%%6LUgoo7L$swOS@*TcCTK{7{@HhIw3U2np8%K z&j~IhIX7dqNrG7Ihn*<S+s>YOw*>gb5ToXrNjk3RXR!@>lLd6qRuBlKlP!4w-SkOn zR0Z3sCTl$V?hp+B?tiw@L1%$Bss9RJ2f4WuA>u!ws(BQex@MQlJuHZTB>6E*g%v_v z<^~hd*66&@%PH?!fYa4-my3#6AOoyMEbtR6^+wMoF+%T9Z<rP<bxR{Ny9_t=N@{5G z6lLDz;-!4l<tP=#LgD6zldY4LEEw8D;4qxgxP}Gyokv9wY_gm)O=x|3i)u^Fs|13X zfv~j*RTV`_7jPgIMOx?@wAsb1&(HB|TpB)kr77Tp<PsxO{*-8a8LDnxjb?30A8Q?J zfor%k3@wYx6n06s)!;k1Rv!!d*WFhydbH@xymRpvUo4EHXg^pxABKXSX($_aoJ<!9 z;y)OQDL>YhYYPeVznrp{X}d&`=jyYijWMHoLF~OXCjusdxL2MkDPo2a$@^@AgdO{M zP3;Od;1IT-JFIZ4)6@LQZGbc$cY%J${_kRb3b@Y$7xjd_jIN%Z6mWu|e!e9lOC3)K zdjzlm2M4(4+-uzMSi0ZZDn#`u&lzguUdrEm`W6(FrUQ1=0%WGxe2UE(Df&cR7(*T3 zi1hLS1|qq;h;Dq=y>*Zh_nwMY^j5%n>eaLl5RZ3Temi$gQI9TA-t?2Vsj=RAyz^in zXGKpXQw#_WO2MSAz){!vkb)j!A@^vtms$aYf|GV?(Y6CHN#g=~=Aa`lX%U-}H$Tk= zM2vg*XY%+NhTx4^jI8$03o5Gs>~saxi&-AuO-NKz_m!*T;@0teDx(dQSmiwF;K;-& z4k~bTA(brK3RGtyFOPp<kAVw9GQ8=zczpFw%_E=rRS2N3m{r7nMI(S(An`E^e50pF z8SK0|@Xf3vJV`N?BL^G&?6U{=#VNBKzIXp6iqM+Ra&6vz8ks!`BC)qEt#kFkrApT@ zep`w*l^VUrcuYa=I6<F8$vTxMB$TR?B|WMJ(F0iZ3L8EEmD+>%pd)k+;@mW=<aU_{ zqMV307<8B&xPt`ApczU0`bcj8Ffj<<^JQgI3;(<pu%1ZDnL6xq_>5a_uutm|J;cx2 zLpbOPn~~-=vXU8qTJ|Y(N)>hBU~zVv@k+E5yYAJQ-b$3!$wUnt>G6mT#{liFq8+#4 z2Kvj<`{^h%#@3->8C?sBc#>+<)>sXmsTZ7|YgBz@*rqE^x<~uwc2v4qjt~oZA+^N- z8d0`;7_04K|L-zd)GR$m0o%{9yqoh$2&I@-8md3V>WI-zE$J7t;sYvnIlrN-XGkSY zqN!E`{W=Une9;_rw}Z<!7vBeVWKWn^BOd+)Xnx~gVOAVoI{A2r&SMZ&_df*o>q0ml z6+KZijL!53YoSfKi|hoQL5%<wks)L$c0S{no#kihbV^`rVX`kNSjqTn%GR=xudo@X zv${luvA%l#NLP6y><qP|cZ9jZ+aH^E-I(yGdi|B8Fckb_T=JM`rt8aiAjI)G-gIwT zsZC?;>>C-09Qv9Ee(^WTV|d0AM3g-JwF@XecYsQ|Q~X2KOQftGr2B7o*|OOIwhnV9 z8XpBT)ccnF79@P8j=kT>p!cshco{#`oYC=|8j(2psQp}K%z42|+eEI*M}2%3^%~f% zC2h2;xfm6><uJaJV8<(keV*%AZx*UmA(oyz-Hd@LuVX1xPm0spCENh{;!^-iv8ol0 zLS&;n(~tBGj_O_I{&S_;a7Mr&IPB$fM^3(S7q>yg#l-=q;F0nZ--B}QL_c^p=vcLC z(d3i?WA%jliR7vcfN4L<UbVJKty6S+c~wbj!v3PdU+eTOUC=3mOBY~DCBl<-il9`7 zcOpPbjh%h!RalJE`ilBmknvKypKqD%`vhXYGCH#_3(xuEnUnfc0L}#pEgklHQ-N`= zFEk19W$8lC`WHv?P#|QEwKk>3ETvDP_S(XnqYBy0Lfw?pQ{Ab}kna#Hg=a`nthX=c z4fW;V@ZQqtVJS?R%0WMX%sjR@<)vwGGMRG<G}P<*rG@kFHyb<n%71|djr7j>o<7j* z@zoW^>?7{4y8D(E9}cRh1q}GZJL~3ZQ|7-<7s<@$bY;1vh|f^&E6W|tg{!YXJ(uND zYVbQNaE&k|pYE>w8P%V9)0!VR2amZrcvHSuI{E%}S>k7T%(Z6=1MzApX7Bke4kb3* z7gqhIF0Twrj%=4l8H!^NO6I9LjMdV6k*m}Dg%{u~5^)j18naE*lB2w?p)wYe;SK19 ze)1u6U*in6#uU9i+SE`DZA^V|7PRcMmquyWx8)_YJ^RrW0>Q?asV=I><vwO1|Du-= zZqBrIsv;{F+Ffu=U`1f8hxIm02Zrd~t+bO9w?xatH}eIDzj2lEw`qNQ%wltn#(R|q z*0cCQE}EvLYAG@?GVc{3GgHKP*e(mt^=SIU>Gxp%%X4pz`$dUzEzvFB*fXZqv#Eii z=DpY9hGc1;&eUYq^R|t-N+%B;n$9bf?0S}2bzhp{&$n;PaKOfaY5mLlh&`C$<+Q#A zV<-^CQ9DGgRJMKWwM{+w-neS>XQxs3yMnBzoBz`{(tbEV<PcVB^mC3*E`wyq-Gob2 zS18PK(+X~MBPg@i|3ev|;0$f;bA*kYgJJUo<0M!nrq*v;$sN_kht;?W0rKZd`7cz% zUkT&&CId>p52#JS2J+00nw$2CX(R6QAEtaJ;#$v0Ppt|HmDWyBn9)HDA_t33FNE#k z7p;l)-8wu9?$x<KEw)&xKxR804&hIPKiD-r{-^`^{^lOY=8DG8xqI_<oLCLi&cPGC z`HiBrfK1epq9T68Oq^6D`!L<{{!S$Q8nmC&CwB-;oUiEj$UA@<9niU}Xq2;SkEl0_ zPe?Ie+r_?vGnX-MJXIlpo7j5x`JeV--yy(OjcLP?{{uW3r@4c8lQNs=B;NJ`p2~X& za1j~ETn_WtvMb6ezJ5_u4z*EqurF3?05b9MV^`DtGcK`Spq0c;7GUi6Qya%~1S&n- z$;2@T_(r?I^Kp<Md0gMF@6yM0CPq73et)dg3#A`9;*FCP{Xs~H;^-7&#VJeZOA7BL zQNz)!*-oL|uP^C5)SUb|K5h1-J5PXok1f=BRP()cMF7>tyECes?>PH&bi4{7YnL+R z&QRWwi*IiNL@s76FG}dm#6SvN`tON75T3%P+>0j~yHk;&z|Pl!Mid1Zeix?4!zE-x z=9m~d))|c~)(*K1o6WHmR*n?W0Hh}d@Xn)l)=QYmn4e3lSUkYoimyIN=RNf5wNEh} zoLfzY%q5GvtK05+e*bFb7%?6LYxf+uroN)vID4?RqHEJ$Q41_C{TG;RlZb6usEFRF znXHA=ncv8~b&nv&X3vC7>DU1|vct)QZdfkfSXh>b1<5v<%ri`;i#GShoeBJDpG8#w znmG-HkoM$rC-H7X&O$Jt3dyOIO8?#v^tK0Oe*u2+NJ-KRB46kOe-4F2s@xDC0n~>p z&^9B{&G$<;$DGfozN|gnv1t>Ku(xeHJ5WdlhH1fJ+#)e~avsa6Wb07W^zFZJ4cF+5 zxyHUGc6h|6xU&>D3y0n~3FqEO1n!hh`LQz_OmLZDs~jTxLi{p|##8PIP*HEeJC6{m zj9}^5@ALp1eVj4V)OLSdC{%FU^zotGw}q#GR8ZZ9Wppne>jlVuh&8{aS@{Zq?W`(9 zJNs#yGj*v??^*^j%i<cOb_zI3T#;yQcbBi%mF^<*-+38Z7Cyt4iF<Oi9ZD#|cJdO^ z0vuoUU0q->;gCS4G6?&=Pe)50OZm>rkC5c8gPhv&IfwO@e)e^GE2S^rr7A>Vu10^- z`WwRPqWOu%RcGAg{tmHZmURA_n-JlA6a!VwugLw{4<fTq-}v=!4C?`ctIVM7naUTj z1I7IX)xI@{w*9M%`B$Cr5c1EE4`DR(@;NU<*5tb}fg7%A9%KdVUa5~<d_v>4X2NK= zt$r@d>XMug_Ow+M6;xZ2ZW~B%oouR++3skZJh->Kt*utx>A3B`<-oexl01aki}Apo z9Lb7Bi>2yh-kgi>7!|m_M_LfQxnShVzk5dn(P)o~^dk!|pPM!QB16HdYxheWr(059 zsBA2OO#FU);BfOoaw<Yfnir{R*|oFL!9vGjX_W(M{?)v927CNKd$fy4GkS@sxH~RG zt-lH>@?l<S6_@!b<JY;><7C6=zaP)XPv;dv02-Du#gsEu!9%j;AZKms;<XRkwScZb zKXA(eqvZ5^x2E*zf)kYX7uLTZR8P!mc^^A5E$rTW?~rslEw*e%(f{3}zJj;>l5x<O z^i4(=ZPWVB4lL&|iz)oM#8zZYIlh+*v&_0b>M6L9<5PZJei}ghqK`+v)C_m0F+9$# zt2>(%TWT|CGrsl1d-i8OS()qVT)&oG8Fcr0o^^*@y(JUhsBfL?RHBie{FZ6ESGDYZ zM}4jr+`Ao+Mf?a#R!n={34(eY%Cg^n@MmPd|Mu^%#>FHYGugJR;421=Me_ywUB<tD z{*4EI9D4K*9=1$`v3kQD38_w|hO_<Ttpz?qzU<P^>|+eT!uWl{{rw|#5P?4q4}Vf` zzR><7hqxmM;Dqn~SBR`K=|A#?XnMfa;V*#BAq9G+otZ;C8rRKUV0#0k9Y=5NHu#z6 z8g3@sx9zaYb^Z|$FB|?3-1xBpu$LeQD6_kOv&+q3Ia9z*I_nx~nwX05b!?$PqLI#C zY8IeXII&W{%zTxqdz2X#tO6J`s{z9z6%*ZPE&z>DQ2O8h|7VE6M@S@3Jb<tXl<fZw zXFUQmys9p&gZaW!k$V9us&W3_T85_iKZZZ9bKNQINT6^`SNzH&F_R4_18iGb0T-}r zh4hctAJek_uP>(%^Ji>%ilXJ|kJm01>;6V?w3qq;9Eg8EYcNi3(caB%EL6-Gm_5|R z?(>^v{B*Tm1<Df{lQmAj6p;TNS}<Gu5e*Jz5p)wUS>r1;XxN^Td3dT%WkRPt@$|_A zNMgxv?26B8!$aaR%W^j|_<iH7WN@E8JhbcVb;t*$ctkmL%+Hu~*H4@BA$#s2;7q+$ zzLsmVF6D{b>P$r|vow<VqOChHZatQAeA!JUbWa|7T6{{(DLY$ZUC)K1^&;#P`Bne- zvyb^Z*8#q3xeI{IXH~8v!Wfj7qm-hGR@XMbG<VlJPn@cEKJ>a(BExX=PAc%IqLj^J z-$MdQ$;|={pClI$X)Wrt^dC66NK$(t<}I(#6RhE~>5mY<V{ZZz3XA9P(~02UzV!Bt z<ycu;!$pFgTT7zVluVQsJWPtkW>^+pnKW*m!TRSB(|&SoJRp6f6I>}IJ!*K4aGU6; zKL<+r=n^GL<-1|5xcJr{=|{NBBs7Mh2aMB1oI&G?ew0ylCAcfccxU==SiRf5M+m-u ztXQ{l7Dr2o=0ha{?Sj(E*OWy4{&5|VHv$&@vp*z`;WI1EG!8H6myaaOajES4fI9CQ z6@5=B->c3~e|^yvpOf^&rCL%xXTOG%Eg+B0doz88sLEMpAydJtLqF9wQ8&4oHvNo$ z+>f?Gbh<9Vfc%`akC+oLLDK+4(C{>5vTc3xV97u(bW6qL?yhk!Xot{%N|tnHy(3(? zu&F&t>7{s%`u8KiMa!Sixp=zUS<TYW4i1Fn1k!(3Op{V4#H#N2heP1^gNnQz@&ks3 zzi^^W7TDyVXR`stM2-vOzWU(pZZ4KYw9lCCMc`fw$3ey%8kSn)Ob$i3@*w@l&ur+O z;K2?vz3hZ?S=5bCs{S=w4hc&;xQ9}Jo%3C1wj}~#8D}_^X0tE2DI6>ZPe$*zXdCFv zrA85r)gb+D0-=TiXU9V$IwVGmuf-}YUmt$MTCE;b1dSrJxAS-!O1uGh?n5fN!_TcA zp9@X#`ifsqu7AYzsM^>#jehWH(yyb6YxL{VEsvVW(k`gRV8e!iv)-OXfy03yZq(NC z0lxC4(PV>h#^N7X{qj_M`uDt9rtOlYQ3>b~7VZGqQzxib*|`xrV%HEZrq}Pqa|jlu zKqA45Lx24M&Fcr(uae6QIv3*=5`8J7!0W)1c%U$eana{p@y+W>H~F<)abUSoKWn%t ztLsytI(uM)nsTyPCax8B$lKf|HmY*XV!skld5-Sx^Jq#tyWvxrQ?d~YFmLdVOi?BE zW?FTQ-VPF$gu9^7f&M^b<%e;Cd5xOwm5#~`+a^-4bnhwl+E4Yl?Qng-w79uu4<q@I z$~DT9P~057yqxc+eSC&GC%soBfm)IZk}1ly4W8&uMv(ex>s&!-K$E3Fodz3+8uUk~ zlz@suU0FC@K+dzKpn0YSJU_xdl)hiEKJ1t70_$DvWPk7HukD=V_y(#XkriU#fRH+@ zXuesSUdxRILDEIT8783gn+c0rbwS$rerk_GmxbVP<8m#cfEUQdLa5vLuop+z3B^zR zb&K4B1WZIX@i!n#J|LzUx{{RZPrx;RfG#yYaHdhGSlAdoAuq}3qkk>|C^rO0M=OlI zgcFVc!SDDyWb^lp@i7B<Y5$%fr^oE%7_(!yBKsqOkAVG!4XLt~LYa=PHXxTYpbLGr z1=UnG1i#UmNp#k&eH6kPpHmIy1)!>4(D9n4hoRn&8-P<`i+k@AU7<x4WTBC~jL+4m z`3_CH0S)$NRc8Xub<=4;eTZ4Du-UZ~J{&LQT0w6Vy1WUUNq-!5@f?r?yoa^wY0a(T z+pDurAXx2a?Koy0ZP}DwpdX~78QpT#(P|X>n&jI10mrCW)(`SSC&MH8E~{PjV77%< zYI$kC4UB2#&-pTaM+Z`s_HAamHcg)ZWQH-EUv-vW0JP3mXlMJW946P>oAv1q6o=Pj z)$+{G;DWnue&u4jRZ#HG1=s|h!l6OhVPJvulSIjeWgC)P;Xw%Ig|xg_N;#<jMO4|Q zxvX>G8F`J>4OerXeV~eb&mK}`9W`%>LY2qLooi>Cy{h{B7XUl!1vouOwX-K|w%%Rs zYo=t_IrRqSUN?q8h=9ePo}kk^0V#(+8XozYP8~F3Px;hwE`NJ)DpO*tqO<<V%o^W; z(h$zLNSgcwxS3M|32-hjt|#=qA1oB`&P4>nY2MMAO8IF;Vx|22cmUB8g0IcJB~BFD z7Kli^@D+f#Q5vBvF-B^5zPAfV8OBUsZquvyZ9NHN=z?tb_o6C3wt8%9<qo8&Rppa7 zwFNry<LqPNtwhF8@y7%vBISfECn=)D`(}*#^9@{RH-co%N0C(*V6q%|q(ux`@>H=c z=+##+Mpxx9iXsTjBPAFv5nJq5Q8DR#YC5$j#l8*4JUZ@5SNWX275_srS#xW1Uc?3B z2}i+l#lK!HT9|%C0??Nf`a(ca&n<|Q$M5ToE(-@74g`JR+&06<5IEXIvOWgSji;fB zw(|}rG1FsHl3~VLGrjVFm*TsV`%hXx&~{e=b!Y!%Ce|X&9UjIt=)*dpMGRvA<Dl>s znh_X~QjqLx%-E)__t2euKAZ(YDV#s;KtZR=z&<#ubnJ(DtaC(N04_J~=TVHm;W&-` zE>PIr-^99gN8h$?_%qwt2kHt=j~J+-6+r?=q`jd)r_|+(1y>SBiDZQBLx%xAsZ#vC zgPk-t|Ag|97HDBmDH~O!84@kvcfoVdoNMFM$gNcU!C+;$DcaWrA2Rbc-<!8;d2Zwr zC&v`yFFS~UwHL0{sLvBHg?77_wrnwyzL7maAV6^$nkPYZWN$mI#}Bi2w%jK;Tnb7> zcUQgz=iO^eX2>l)`jJVSk^{xkelxzJgU*TX7mcV&^t>SUckf7}NO4`Qnkj>4HKr<f zJFa&7%p!I%eqCRXgMM8b6*2D?<<tGcJ<U(oI!Cq<)@Mt7QjdIa=LDJwHKmlrJvSJS z>#^RfIrl&g{TNcXH-R1eiT9C<oU;==*VQ2$MbFZ^Uj`vy>Cnf%J*@M*hC%tmJ}rYA zY_B&{thHi9fomQA1XXmR1&=)s=qwd!u7bt9o^xh;(VvRDz1=9Y<66_;SjEG1bq~;$ zHQ{W!V{p%><Ij!XLR2c$rN(>yw%wzpN8!%;QzQh<5^0v?$G$=S-5h}I!l$iu)9iuF zx-RYIj<_}s5tpG-<Xx3MMM+B3zxuq3sE@lRuI-!d>dyagj;n7}_7h3x&<^Y4v)9k! zthjCiwj=W@Q0$kVH;t^a!y0EsEHtTo@OSSG8`s0q0K*wF$KYCVv7NHiwpZ)zdbCk` zgV8<5JT;WN_-Z>u%@E2yjG|7Wucr^&aqwA^h{T0od-2VRThB@uVuXOi*Ys;G!?R^g zzYdVP*hycxi<7%0-$WpDJKqtJ$!MK(*G09QoDjaJSzJoEnYZaM5|kg{hVX7XwULR_ zDk~j5`>OmtFby$nIyP$9P#z1pc7mewe&;)&fp~LzFq~>6A^+kE;OPST%Sotl()lX= z;@;TY+gzBKiX3?7f-c9~N^93Zl(c*w!44@m8R=Iyez3Oo+$qU@&7ne|-VC|o+0XD0 zlP7$v){NdmVb9S~3Sj|fiy=FzU?V}jeMqMPW?5KAHTLh|7;b4avfpm3LBWTJm5Y-O zu$F!HJN+*8y%TwjeV=O%DUfR89x6;J#UC0$Sj-#6{Eqezy7hx8`pp~QRBdq={CW2r zyi?xJEDg<rk83b6u}VaebPh0X_mp2l!`ck>H%?0d5bs)trZqjtlh5#ru$MPdcD`pR zL_>!82X-=(qTj)Ife;xM(3dp{FC%lY@8D&m8oCi>>YI2ky7vN$k?3jRv4;vHuRt;m zlL`m-Zt^`1->>n1tZ?^^@S%j!lFFD0GmNLeT%`<oe%<pIU(HOp67x|tfhw}UvTD2* zEj5~kzW64!!|Vjdb3H(?6$NdlqF)3s?%mc&OG0#~qNfe)gQRv)HwPpE8#6NH+1q|u zn%))c`dCK(g_-E$GyZ^U55ng8Q(K%K;nTK&WNI3y!GlhVHB$Qf(?LmnZyiw`sfx#P z<396<%<snk4`pv17v<h=4+|)muodYNP>=@6p+*Hnkq~JS5Gj#n=o%0ZkP?v|7?qNa zp*y5uMnJlA=o)HZ;&<cT`#JkL=Q-#7y#FireCx_}t#xPf%QulvaZtkkpaXeSl|xa? z(bXFBJ^A$Q@$Fn0^5}XX9IRyBFM2W}D^_1~l5mmeGgL<H;HCIyvh?ld<Dvve3`%?t z)$*slqV7BQ-#{^LE&tZxb^s|h2rDgpWUh~#_+#1n>u2T9;z%$6xpEA4tRe+U)i`=X z{uE9fzmb;|L>TkaHpv^n0T~!@@EpmEw=wCj&Z~TA=Js&RNU6jL@y;*gq+cu0kFWkj z>Zs>sT|~f~s~Fp_8L1ljss@%E*ri;s(TXu6({08N?4b(Y@B@f5&ufee8rD1Wi%d-K z4P-6>+Dp+HPhqP^XNARcmc8*1<Ou2di*#nPy6y?th{~}b3bhaswW=}bj%RmoYGVC{ zPSeGG$R`<e>!emlHRKQgrTWMh6y(+Hv4Tmr93d&uE>j!VT~i_c%y@_gG7sSexdTb* zgHfSjY|E+1M%WhM|A>yxoo_HHD)DI3m#ivx^@PORRR@q99lP6#WgMaM?ggGOsOM;D z`*(c#MPR^PUVg4VYw4F&c&@NgUIk$M)qGk(@a&|aV)g3#+}be({c-Jx#dT1wL$&5~ z#c*3{897l1wYAKE%I{_=tJiz0ydcV&-4%9uG)3U!mOB{vjptERxD#iN)RZ3q(zfW| zDX77v>7A{24=S0b^@N}EbzJTFBrEXwIR>>_iQ|i=-07O87rFj=jAbgmE9R7Hyxy|{ z^fUe>mEsxz3V3grI8Qs?wqQ-!xX>*6@~IDHWnpaqD3cuFFiX7KH~!Pn3n(Wtjs)Da z-|jCsa5@F0bnlv4&M|Vz!K!l_figH#?!spN<=%BsmVLetwa4Y*D72C4oSL}RrFl)& zB43Gau!9;L<S)HXHho-U-<!6vs5PuGI@M<&&f-QH#n5-TcfKL^0xhfa6(N4MAyl<} z@AOtqjL#nG1;O*FC2s50osPmDic=6vzNdVxX!tQT<E)(iC(>Rv<Jv-=a?lA{pz7)d zC}m(6{-PYvOTl&cjC<EuV*)@E081BN*<^bghHBdvRLS3!W=~#=hC}C_rzFI%`-Eyy zOgypg!`-}WU-`g+6SOX{cIO<K=-nIBwn;QV8RF&qDO#iPWO-1d5wvR(ohG(Bx4<Rq zID0%n9$9PM<hpQFV><aIrQLY<XL<|)`>Qq^hTkzqkAEg$7j_LtV(%0-{>ie*c+YeQ zR_jv;kT<jb4X-C5VbK(BWs7;vdwRizbrSLpII{Ok@Gy-l*;CTOI;t+O5i$YylcF|o zkPle?IDq1~gx?n@12CwYJ>0uZSYeh$UYmlw-KSMqZcWPamQx#_63YZc!c*?`r`~;$ zU6Q(K`C$8p_8MBhXa2_J%9QWNex*3ftylN7JUgn(FSe7pJGoap7@M3XX}UTrCTwQZ zRl=I_t|8USN2v$w&>k_SUS}bShOD?6mbSOCPtp~^7~1rlRI*yh=7&n(sIWtYgK@UQ zZVgF8Vag>O`%jpsiotn0jVo}>P2GX2*yx&wPm{9n^+_}&_0;DOa=O|+$GVj6mv|6g z4`TbQhL5zHWM?%mh>-jqsw~Xy!zsxX1)b&;LpyE3sEU_;Zdoy<VVb|5Fgb?X!hVd8 zHv+Ua6F#K1_3si)+L>27lI}Oab$q<}+!?hzOfcWqg%*A7Y^RhM@I<i&n*|1_{L^j^ zSJ{fI2cm78R@8ZLK%rpn;qv#!E_uD(?GXC2f^TL4%Dlv;L@cHNDvyckprUs_-O`(^ zLW_@3)os<(JJh+sFO6)-tmg8u`AH3c;rN|J47|?hFKd}m91JmDgaFas&fPN#)Of0G zLtY?gxD*or^l#-cuDP<UPjF79jm8hGybxj9<{Hm7r~Aaziv*j)ez|ZPreqx~H=|e1 zsYOPq^9Oiy@7zdT6Wx#JvP|?IV%@-syK`0?=~uLXN)0!B%oK!jJDm@AB(y?{9HV<P zMmJh`e+W6QxZ?HXdSnhtQ}xVGcI$^ftA?O0wWu;Ui#dl@Ugp8|?!It$H1l#+LFp^J zTw+a9N~w{CFB<V*dJTqqC+*vyB`VEmqP!nM<b_i36wwueN8>5X_CTfe?sUJks#c|g zo2-K!)r-kgY}W4rD^|c?4qbtBGb^RhZ9ZBjbtg7+9^c&vkU*Oysa><*gKL<!??Lm` zvz(tykg>43nh?Jp&dgjkOye0Ic_C7S>0mM27nRx<rr6aI4Rm<puaJHsa^&Yz=dL0~ zTY7*BEKDow(2=}a<%Vlo@7Tlx^hBz4UX6x@%s!`yd91#7fioa3Zqk7vTD(MA&SEJ! z165a;`T8!~#4a*=xpdJ<rmP}l(%Wsbd?<GH#}<3!R1{+;GeYn+I%)YgDTXGS$2dr6 zuNpuEdi*YP@l}W-xq-QehvtC9&&0ihGP?B}Oyigid%_fXiYC#`LVUSgzuxVd?(`c= zqjJhvBRRH-cN8O8;^N}c$-8ZgHw)@L-|9%VPh=Jfka=l>l7|OVRdvh5>-$fG+Slfm z2eaS^J<u2y-3<$ryfbK;ZMzmQdSpNIf-at4T^ud=6{PHT!%tpKKaisXRAg(kC6167 zHxQA-qkc|qyoJ^Av@wIwTP5hpv4Z}R8_+U}7Xi^0EYk@&#K{0uZskx{vd{a&`@ai& z1;rNFVVB(wm$}W1)ol0gYzi{!`5^}no`TsR+jFn_zXQ5P+fE19$lCAN*l&1ahE8X^ z+DP0Z<X5(y7J1^D9}|6cMI|GXWF%^FR;;@`6aG3C=~h>-87|iCZ*;#p`dIC@UJ$6v zA?I`wFiG98n$@6qmhgW|>rDS`*aVND`erZs;~bupzm{3>`BQo0x7fO(^~VBe1@KYm z1P#TsC$>3Oh{1WL%`98)nGwE+h@SzgpQ7Q7sfR~1Q2fEj{GNvKUE(6v76*A;{~~@E zF39{~bY-|2U2J5jy7D;4UtRLqW?^X9_s<Zuq4KjSEX9Ur1jKiMbpNb)FL+j%)_iWh z4&O{>qL_9aV?TQ7yn?4=A<Tw44Q`(<B?JSx@jCD=B8x%Q4tmD#w4kPD9F!IeRgWpN zjmp5(v*y6;<K?oiX?Wh&g^7+1D}>mmf^-ZSexCLCzjJF74SunmX)ZpzNq1HbzRLq# zUbntTg)J7>Q8LbGkCk`ntn%A63`hJgk0GuHLNmTcQ<awpM+?zl0)SsdHpBf+cnpcm zTyb{}<KC&mi7*Qk;K#JdlzK&{@B9W5U^)0<m~UTz1)WvU|CW`%qf|i{E39@J{d^@F z=0)g_z6w6vMHIn7K(Yya0W8L$5f5*bobkcnk7kHC$U}MJ@j^6c32dnNcH*<KWI`Gy zg~%*EI&9dHn(}++Sf6AjL-c+EAs^uHfO02qo~BmdTK8hKj(8YbUiTHT8enP;NShR& z#Kb`haXXki)>N;91*$0D*WKkB^1}8fz9Vw3+s6z?FTs$#DGj;ZL12;lgV8g$zdIjq z)jB|NyB%zg)eqnT_pnybzU7x*$TqN5ahE;b>IiD~@;7uchHc>KGBXVz)*yUy2J9et z)sQ(jl1g0+9gG1qj3L9oyh2;cPi0%vwnVW9UlHZ1Ca>JjlqEkSqDc#GFTmyIfV;A^ zLK-Q^c<-;%2iW}iv5jkMCZv(#5`Ki$4z^U{?qz%2V?W0yXn5<IWEI_P#MiCW{jXWH zAv7PKqQ*|F8c)>0&-Q{E8-FGI+58BW@&eIa5CHlSN*I(c%C;OEAXmZSF=@cbt>HV5 ztu6xfc{)uR(19pYwbbu(?xFm0Y(t;*TsO5=bydAw_NhD1hcLFXvVp_A(N?xl1Niiq zU0w($)yTH)Iv$p<c0U~`Y@Mv572XW^Ixy*%+v^AkE7CDr-8uSm5kHPl4h=_7zMWT2 zO@`RLC2oW*e2F;NVWHGF$a5}*aM6EMKmjLzlWaGU=4RF1w#nZ;)V+5YsPKHK1$TQ` zz5)?A*k?D1ldpSPCC061=!}z&)*ZrWLmVjqD*5tAxA7uue2C;NA`F!In=#3w{?~cw zWaIv4ID}?xnv=M+bnPBf+5(`@d-%ili=?QcOI-A0aU)}8EVJqRf{m>W973j~NiK`Q zg6FO&#~BFvj*==7H{sAIx4WpN#paoh+>F(bKf9i5J8buUU+r%X&N@87hbTPKzILpE z&d9aZA>8jM2oovFMaeAFX^p%x@i4m18TY|(WBcVm6CP30=QqYIZyB|iw#EGIJ|7Rz zPpKJ)vIpDgXglbrJJQ6tYNt64sOw?p*FS1*SkL({xkZgMgSjnrB6GhZ=AOnUGmihY zrTZvKC=q`I2i?N{Mr`+20WsNo(o-}|<tQ;NN8{|a&IsVPQiY~PbFp6&*v1y$MW#v| z3@P_rNB^n>L(xH?=1Ui*z5v6KHk4@q5&qpLscdIFVhY5U2CK1!k4EG5$XSZAYt3|P zzULQe2|DH8VEd~18f(Ql%9q~bA0)(J1ki*7hI0ov-`^YZFavnw^p^q7Ok2;<J7&a# zGr=I-jK*Qz+vrmh*t~^I<I&RTwl6l|C>;VYLy^hn0DOB5J0EuYDrLVlpQ2Y@GfgYS zXH<N+k5*Eq^A2n4I7au2)!0uv$KA2DyPi^9u4<{SH!xP-5$8%%9q?^92KaP2&wM)P zKt*f94~BY8;6#9<3;v5iz4OZ1wUHuD9`yoO<fu}qQ3&TcM<Tg_7`l`462GW3H;;PH zmsT}!NouFvH+9woYFO5<eoEsZ({iR=Pi+1uMoH&(D7Zs;XAsW!P=-Mw5l?~fUx(Y+ zxPRu3v;7IK4f`>@uFcbJ9Jx}n0ZMEUP;SrQ`D1eq1gWYRbL$}?ZuHgduAiyX2Hh3- zXPf3dK&Ypi!gk!khoKcRmR;-DoG@-k8a%9X1I)VM)gClF4>}FmKyob)bO<^{eQrF? zg?K9LqArmROEG^G>mwn)G@GzF`t~yROE_?73jkk2`h6{*)~C*gs<vN-T}GG2wKES< zIlr8$!MDJKF}LL{fzhQL&Lg&ne7=E||I{5#gc{qd%R%vW{UczXDPp(4sc}iQHCh$4 zFrw5rzBh*5-JnoEB6X{Ko0rR$2fN~JD^u)(hkSlZxg;<WKUAD+3v|~!B}yMFM*+&| zPx<B3pl$$rk}1;;Dj@ZItKdj$e2r;BiZT&aLU`Y0RVa5uWrFeqy-}%RTl}YK{`cl@ zCtyK0st}I^jq8qw(OjDz2g`0UYZZaSm$>X06cmRI!I<5ejiR%6RcG-%xo8W{CjnI0 zb0nBm*{FRZ0jc&AbjI^TVxo5WQvZMye?UF{^i#csgUg_mF4JqkOBGJ6Pc~#AsqGX0 zm#;hhlB3cvtn=7irGnLAsszY3V;$u28&J5kRinwV@9{=36?_v`v)<g1s?Hb*l~_f( zJw6Wg79P3$6JW#HEx|!vg~$W+NWn3!eR}5UlL<HNHtdIWzSOf^)e4{0CxFUDskDPA zhoMm_YxXYx=|{AKg%DlM2oo>g-TAhTY0sZqBMvlg5WJRBeW24;AuzL;b#&9%0yo<l z%*$`frpMO#vGoaBgob8t6W(HxlC3vNIacuFx`8cc*%MPF6Hx8Q{HzR`#=Sm8H!%Qn z8A2=-rAy60bN3@Di>8$-XyWQi>6@8^G_nLcc2Ub6j*PBx;+c-!E-a~@tqN!P!oN4g zzdj>iKcdkM6&}0u)LRVqcCre{HfOeb9g}&QcjrdpD5gsDd=Gzk-ymSC=}ZJnf0K=_ z!~<lb-imLQzWX^>pdx$06mG0#C3w5hC6179v@tSdUYVlzPOXT@z&V~Itr$q*-pI<E zjQ_Md`Goex91VWpdbD(?vxzxP-1lCdN>UdkU~?+rqwWKThhs6(@Hys2NVi!gK(l-+ zigQi;lyl&*1yE=!*@1kLE%-dJgR(Sfc^t5@`S1;|o}%<b#*;z?BMV7i>6ewDbg245 z@21g3PCQ}+nvQ%2fDir$rr;xV+HX|E>SYzM2dBpMzC^>yD`i$Q@KrJN2H*~44!&}d zTCsU-7Lr#GUxjII{H^2mE#vGBp803b-&S)GehMEnn+RwmRIDHzz%q-4eiYLs^;6y8 z#8t6aqR&we^`@5k4&98e?in*g1%tjYFww=Y$PU>3|M8;|q4t1}N0pr4Z%kwI?VOSs z-K_35P=~1do?;{ev?S%A!4TXSs3^Y}8}M(`kBU$J{SEel)3=kDHp^y;8U;?~61GuZ zxSy@t>*#U^Kf=ibywL!79YT!)Wzlf_u_+J~212^X@kdUA3D80&;0-)9|Bcc3Z@0#g zP)!5@Cf{c<ZiEQ<DHFoZ7-*1E<|M!`YwBb`94bf{1f1vgZ1o@|qy;v6<x#YueGlhl zp5Jlt?LR%B6fvpzP5(EOzkos{XyS9AEUv(gM-1vtz9xES$pe2GiaYM1iZ!m;3kq?U zcY6!Xo+7N3tBV$;23FSjENKjZrA*zy#~!r;<aGM-J>V;vkI!uMw+u&uXft*@IQUPu zw&;(6@&FO+*Cql3;Oh}%ew>B$#IyKA$QU;i4F?|{E;<QaZ9HBzgDuy2<j<#F0Q;@N zoJj@g<?P#DcLJoMHO~wplNq)3xS;vDPjLD=#$WoC6waU%d<tye#Up^RpoY=#M;A5W zXZIWke?lkEN-RKZVcTQpbo^ds%aAai*Zz>=JHf6W0Wlu?LX-~{s?}5`$^v3~-+%PA zd=RmI_t1(3P%GCF<mRnW#3Q(2k<dbBqrW}`@E^(nACjP6G1^e#4EnC|w=>!Tz8L)t zV9H$gw#@6J+9=s<GDBAF6jHE30gIvzF=hsAD|+^F3Y-4yHH!5yFu<vPVUQ{AUl0@w z06}4i6PK&G=k(LM*?ev9YDeqXNEV;a6B*8a+WMDo<r;zVsSd;2FT=v)+)Z3<#$pdc zPyVXaK3t4Ct2-n^562H%i`z6uk7pGp=2w11w+$kzkI`bEq^#p@f*~vS$N5A<GBW|Z z%y%PHHzP}`5f+gC8_~v6GR3iM^<BMgw8Z&bEy0Q#K6ip{0ss*hwE-}c!UvE_;CGX= z65kOwEcafl{q8bJ6+k3u%#Om|Jf=PFx%Yi0xX^hVE|xdbPHz)Kv(SrGwn4hu5Q|Y4 zHu{*>$&hGoq|cLIKCsy${~3?!RrD!6B#L=mfoP=IUbl_xz+Sa``5*QZsJDHx9b=fj z3PAlW8<nD@X?;zj4y&8broo88pX+rr>vcfQI@-fS7kg$iQVaLmlpkdQ;s|6P3<)3< zP$E+U<nRKU5(+Q)veLI5)_I#h)CSFO1~@fM<d~6@5lerR4syK*ez_GOg-6cE<(zL* zkOxa70C)wuYAo8sUorrJJzrNML4J6_J~P1Ns_JF6c7_w}S)Ey{O1R;-<vIajT8|#a zb#N1iP;x?gL;^PyaR`1bG4BIoUp}`^<4}E(eU0sJjF1cvMkx@gr}2m!<aOCpgZr2o z*e0YIVC(q;EzIA?P6s_IeB^2I6YO0hqxO}`o9ajR+J<kH=H%Rl4WLvM3$S|m7mC$j zlHy-Ju<^ProHSP59xg3n7a$j4TA1uMF5V=nI()4o;ym));aqgIzDUBk0)M-^u5>ln z*0^7}oKuNU10<5#onP17GDU*B`@oH#^a)ZIqy`z+Ic9xko!s9ikQD^T(OZ(LpQoG; z2ib$u6-3l)8IL7JGl`~p8apjy{$K5z9A`;&T?yTr=%HU2&xl-~z!v^%?21l*+u>@U z;V%owcrU`qxImu5t^+O&8xUYZI(;>As&0u_x0jw}4|NINYrYKhA*XnmNwQhkL~EX8 z7P3494(&W1a$!frku%mCRc>D7)RR{mB^}q}`dSxaMsS{1JkdetBK+wDh;{rwNu|=d zdc&U|TP?&7M#Kpbedvn$tO%c6cig#ny+K_GWO>3d6HMy{v$tQ#$nya@)h%qCXbi;; zWw4Lrthw=)g$%T7c}Y`)+>Jz#eECF35~GQ?VrK+S>9@V&a0lLY$Zvs)Zr=;_zXd98 z#X*tUn$k>X0sg`XdVHLvaP``Wl~zuA>7i@xq-D_~7hMauTm<y+{bOmsUddALqo@W; zSrwyenoM4JYR3~iFVXCue+5X|&GPhsE6;h6o+2)H5CP%<B3oOP`>81rN0Jx3pK&*8 z0S=wbp-v>?q{|T?0+q6X?NChAKFU%a3fSlV<1=@4=Jo#CZOj&&v(EXfhi|SEbsNir zgJqnBj)l-eiOXVbl6AMOP{I^%)c}NJ&Hx}Qb!t^q2l*0bNV5D;^mVCE84i*LP@|<L z?)coxQ;0CDup1SyT7uJw7P#NG;W4ooy5DeqrD^_#@;NeU2kVwT+I}z?J$wm7UiD6? zc&7AnU=VPnGj?xk{W#rw#Z1J}I9|*%jW&DXk&KnyMxx)mx{AiISt=9z5WwDwx&6at zhW{xhH8gejJ~lNr@g2YrDs}+JyoEDmK;3$5v`-I;3W7IN&&N7f@lKjOR~z}I$h2@w zV5nFE1ZhP9;kK*vq_!mat*Wy#>66Y@yz>lA-nMK?OOM@O_i6$9%j~oIuasX&q!ysz zBcy4TY74H|g>``MaTWdWF!pUeFu7Eecu>z5n<QyIw4Rdajbq=5U4qM;;{*iA8TR-w zu}8Co!NzwY`y;CTMdm=zUb*w`uWJt6lK`x4F%ud=B7kq4#NzG(5yZm3K!$)V{{E-Z z)t?RIDv@PX!aigMpu;!@!quG5craJFqi2~IWx_1|X1wpAg^-nk&i4(->zlxp(OQSg z+~fA-ex;K|q6f@5T5A84gY}HMokw083O#%+LF$%$$1h<1*Hi9>Aj<<a-j!JYg8-X! zAWF_BFt793oGq$tzZVmbP~ALp(6p*b3JxMn0$eU2c)9;{(|E6sd~8%bkN_J;NLq0( zhXd0ZuPtR#u(C*AHmfR35|Fn4Z)^F@L8!?t8=KvYdjHpI44lWr+bf`lD$*e-MV*hT zg?Przg{%xO)O16iICHkV#iDV*_*p7c$f(OrwwO+QgYN6(az#^GlW+rT+w&V#hEH1D zdP|x#U5dGXg7pjmn^j-MFar%x_P3LoSET(?frq4gFY(K#Aa0b;1UTsXEU;&ZIP~TS zW`G)*-}D8cwI;EXy)7(_`U%mLZ7+KY{Tva=RC6qmJBIuF7%UrFG%jbBNz@Fd#-((H zol)o?uUqLaWw9H8ve<u#2DZ?41B`;9%xI~c!Ld)-!OvNjJTT##a55`dqHUc^)vrgM z!mXfZ>6}#|uVhIHW9y0pP|^7#HW)>(Y4X-w6Q1yiF1<8|h$G+OC>GT@6mQDb1*bs^ zzrK?X*NJgYuM$+jqi1q{5{vJZHCjypZKN&}$TC2Q(JFu>1X4VI*4TL!-B_h$7Fnyg z0488@TW}QrvJt$~-Kw6Wh=E<P{&!&oc>T`6jr;W{434jvY1&BmcTSK!{`Kb;Pvc3o zLmI7$^)b2$87L8_`@-2m`-3w}t|MSzzYB+UQam8Oe1gT2@|oFQke!W>1_p{!{Fa4@ zp479(d2AD4p>H|zVPi<O4~y^_3(JF3mzL#DbpEFjF2^*RFo1&*x)ZNq(HoY(gDYQO zBw9`%poV?2PS6XoHC_Bl&XfR6zS2vfhoN5o;ZXo0Y`4B>EsJNnqI}n%fRFkHAM#uy z+8*AC&~BU-49Ze@q~ocm>MYYTdKr+fiFs%r&V2C%ja98R>g=ZH7P)dlTlq)F_h$eD z#Z81H;;tefKY^d@u)7wbj|a36eoT_vcFfaQuQ?=^aJ?{7YJW*0+gWe|gc4&-*nF%H zfT0Zb@nzh}V4@xbQ>;07K>S+k2f6RUsb&M^Qpu7)8s*ElhrfK@V>-o#0F?CZ-=M>P z>~;}pRp;NWorW-RN!IfXE&?kL<HJT%X<b;U<G8CP*2e6pUxAmYQu4SQwOV*|D=-Q9 z0d=Af_f$W>^k|k94O>47dK3%Z-Z5G=g3-q8l}YZnn26!PU_2mWhb|`Xl+fkI^T18Y z?|tMZ!Rvoq#Qeffe)2+6)rd5nBhICdc6}I&zoSA}XqSq{+Y)_F`b!#Hus{&nKl)GC z@b<sS@!bc)xsKjxcs_3*@m%A;4WTbS1n}+G(^tx=-YC`!TvP*tU*P$d$L@pK5Ujyg z_E3rj3(}oRU9eO8<qmCU_r|qf@lun1OOw0>>hiC-8x3d@TaRe$XF3uwV4sUuMpNi8 z>_-eQ7vZQ7o@HR?6wUs_1^BK1_nXJ=36XhbIG3if>;LO_`{N*FHvfzB_@@%#WK%Lw zw2J%}EE{m<-~Pdm_m`NVWHHzO_0#@`G@;NLr$g)x3ewFXfwW=XG@NzVVm-DlvHDc> zA2Wf!yqblT$G=hZucXnc7NtWf0PVwnr;7mobV}S;Dn_eXl4Fv@i_H2PNsD<0=i-G9 zzg>U$i~B#AEYZ3oJZAsGSO4OdQJ1>|-wFPF$om(T{r^fNbTsiPGCG#-1VG-P^qvd( z3F(<Kp~O}Cb7kcZM@SDzkmawVE>v82VF6mC)TJ`6JtuW}wCS=9xeKWqsXB$Ai&@lR zM;XcCqP7}$>(~=En{i|?kxcM{M33_)pvwYiEdS0U6@hH%Z_nNg&Q`H5r0FT=1-X1F z;w~Aa7z!p8xSj4MH}{h6$@&R8nRmuCy;RF{c7>NM=539v4E8D(O$t!hGM%#`D<T1C zu!=i(CYtcSD$<On!@_<z7>Ed+8!2X1)McpV4tlGiE%MZp%h8`{@aoEa68SWQSBNRb zADF<NqPKd@MB+|b^unl*Jc`1rTEqzl@qWcZiJnptW!zwuO%#gH6fn7_&-A8)T{fPq zhRi4+F2Mdi>Q@&EnIrDMJY3G_oF?aC=O3p4$O^r=_|KfO{2!?JN4HPqoR0ya>aU#E zWo|&B|Kr{gJTDJV_nc8r=|Fesyq>0k9w*EywQNwQ;kdI?4A6iJ%7AW>Z?tgG$T$PM z?SN=ADxjp-QNorIkWjF1n^aixW*mCsGagd5_GWF1&);q`QC-#6kJTe+wa-w*R^gST zw0<D9EP3M7dfO8aS)!6%1DuJv15B0q*!_{gh}^*SQ5KKOQsOD6DjIyRtY%MsWM2;a z_*m*lpC$3~Wbek7w}*1h2XN!nNu;7nbaT_yiu8w^tYmeahWbKKcc7^S{hucZ+~&dX z*PQWz*{!6~iQ6!4{AA@QAHV!QFv{BSc{ymK0LWdQVZHt<cd2=7hDE>oxR2rzcNbq? zNp7J-)}Amp(y8Tt6}2&OF|#iYt7bl?uc91nC~U2Kb+T{JGzCm;@NVteeNQ(bEBvM} z!BA)Utf-=0u<7<Jh)b5~Fw4j9)2GQl4pHl*3Zr$>teo_aB$~lsUO#z<pT$W!<hOqw z&czxC4yH<2=^kQTrj88W`)Cc*B$2#qsg)nkb-Wh`aU5UJ4T#~K%(oq!%ba|%YsmGD zB5UqE6lFNdF$nZbG8F-~5i7XwVK=>Mve+sB;;a;M@pGZH^yVE}L5A-b6v4#?Lm_n4 zs+^^0sliUEHzzU$6JM-ZEt4mnh%5G%U#Aya_I}&meb{BiET-;Q@oPr9cga@+;;DP( zi+%JRTszIHa&wt3W+9>5ckT_{NP3j`DOI23?tHz~fzS#mZv1)<kV^gQg0=6W0&wWX z=9@a-=v1k!6h@NH0xx=^Z1V6(pJCzawupX!6l$mI&ys#Y%XP<bKonf?;uE6nU=Zzz z&+=^(izRRfh{YoztX5{k^*BynahzdYYFWvf`7(|vksQ|Yj;228a3jZ|RidmYTFa#9 ziMuZ##(+j7FqxgAEyc=^_o+l}9nJt5ZeD)x%au2h*`cJ3B-ASbX2VsZm#Y|$-!X9( zBC)XM6LviWzneeVbF@UDk}NFSg>Q#zho$XQU3TScny57+1BY2kFqsw+=PRmn9?Vip z1s!dSVTSZf%KzTuCQo##RazK^!*Q*Vh~M5{9UOUKQ=nV$BB@JC2*#Egh|JN(do;6J z7pj0G+5C>@fPNBa>9ZD$dsa4NpN0J0!c|7>4^p!++uF?v08)r3x{Uf+XM((ru7XJP zrM7!Mn=7CDkx?^wNgX5H>i%~4QSz*qmYV1r*lhmy5m)`nBe|g;1491N`SD^wGgYMd z@%fgCr%S;Zidio>1}|!rQuCctsyj*~zC*5!s0%hmD)9pH@c+`NCEzI(21ez6D*?P4 z7~kTd%0U4dx@W0aAx+&<*W~gSs6?DJuZ>CejTWHYk>4%veP$0X5+}(=;|?UJ&0a&2 zH!ldCrxn(!LB2=uISR3CbR(fA1|1sbrq6L{<uUG_-h*VgBY5@7z5%HGY}T*$-R83) z$jy8PFG4jL6xMmk!LsegF3O^i{OIlb#2*WK2C*3zdSp6GFL23%Tgx_?0>a<)Y?D=- ze-ZL-5D;Znz1|oj3P+-a<A=V=0T2I8;^)s$zoRL4tE}ba6o;+xA*`J7d7{stnxtLT z+<O7T3g&y}p-B;#7HmIg1*S3-O}7!VoV!2x{rh*Rl`nz1hIZoUOHwFy-;jV=slZ3_ zB~AJgz_5E^Zf@!SeHwu1Y)FU7|F5&iT!nAWfDQ2DT}zcEkAareU#XYddjQzZ`6sUZ zJFl``YSj3SkJQT9<EbKyP2Bx?b7togOm2zkySUw3n+z3)LX}N;UydW+5k)6><Sexm zI67q_f7xY6$Rd#xQI`C4FTS`cc(sG9poYPqgo|eVU^xCAs}&j10*|gu3iQ3yk=)Kk zVPHD--55+RpHbu&CtBIV=}o}io>iS5=V@~D8<Tlw-7Dl6s%bk?de{~n53R87d(JKi zsY2+-N%O(bKEe)*zQgYt-j9u2XvSFMAWU8xr=B(wds|yp4(l%fJ->%ysw&;!?5}lo zxO@b1ZM0;8E5-Jn^I~VT{7I)gFbN|wA}uF{50W7QiUSVy2g9lE>IBzFJiKx`heq$E z6F|SEm8~w`kxB=!Gd)0mrhY}d<D5)XRfp)DSSQwAobmR^-w9L!ze$v)f8Xiefz8H@ zgFdZwjbI;G)X7?^vfv=eC2O?Iv84H}HA$J;)P{*(B){y+GuY%h;{M<U2=!NCf0?uH z-{vgeZ!`1+C|>`WrW9;dNS?_z@)eq@Uswl+T(+;;1@Zkp6A!|eK+)VC5CxFOazB6! zPrv=y`hC@$ChA$_8!UR@%P`p8QhMv^EZHpetcX4Ts0=T0?9w)cY;)fpsVh*!;D@|F z0$6W&-=4O_G_fIXeDef2Gb+B)0vsTXTr*VyJqEJvMu%w@JJ7_ZlL;1bSLp_tr_ae= ztec-P|7mu9NAjt@&)V?taj551IFL&lZnb&{S!~<gKib&#Wk3=+C{L~_YsAT?wu9ZX ziE!lRg#@x;lJ@@AZQC4IpuWe*mAMUv9?ylK<WFr!i%kLAAy>jR=P`?fqy-ZI#o{wx z7rFqyw%Yexic1aUP`BGYZ0IocRe=HxN7`(AqzdRJTPK#(d25L3F0L3n2?VykCTW7% zb>{gJ{7Nz9x@G*@jznfsBBDj+<IZypuvZixySl0_sslHiy#0ybu6=8?8QU+&@`_ma z6kHhT8z&jGIwnKI%7;(2guV6H7mjg{8KTac&^M3^s#E1hQa{BkKT7*Rq+N7!DS`vc zar-O%t<~<puUQvk$?~j47@=H`>0ERh-3F+w#)9ac<Qhg{+S@$eyIv6lrZNADsX>=! zR<2PDb_7*&?o%%F0xi^*dBElW*)D82YZq<=Dc4%SW9tpNrMdP{7rp{n=3Xa~7(5nK zyD-%@j?_~IlpTMlDY4$jO}QRRn~(One&?`Vvn^Jc^h$toKyzW5U0ae*6TgL7hT4ri zyC#t)uSp6=QX5_H`V4f3YL?~8yLJ!E_mW5Fz{PoFQ{#;Iq*0vGXXtd~hf}^}OyT5t zVZ&rCx|wtQB!p6XZdE{|lqD}zby3D5=+N4yu`tt5@+@Z(=J6%skTToMK0D2Mv0>EQ z(%|F;YA)5$_fkS1=HYp{xoJ><KP%0v8=GzP`HMUb!O&BCBxcqH9`Ot%UxQ=HDW5ij zW%zJBH;mU-l~GQ2euQ<cVH0OwOjKnMS!gc0Ir^2s{qePe_$rA*o#{WathTj1^7q}7 zopR^;TNS63bT#tr%`6W7*t=IErNQ5q!sN+IF#OojU+*U|{w6(Mz)<>V3pePQn$;@i z;9jv_T}1#POD_q1(ynAiM}}jruG7Ax|Cb+fzR@6pgLLvM15*kdGNJ&W?W~Jhnv1ZB zup@57xll@)#6&uqJTH3^gsiw+R?YiS%1DPhPT)DUCb62~XV?($vasE#U=*PC@Dg=? zmYtwNXHaq@b61~B)IIF76w`6U2XCtNR~l~@Wdb5$#FPuLtG#C2GCu>{=e4;-t{tn? z>|5@m8h^%XSPd<O>sy2F!%k4Mp@yP;$1JZ@wEI3Lx||cV^xVu&tj6CKe$OidoQo`d z;)Py|u}Do@4d<sn==?dS049__-_-(+Vp*BZ*JUo4&K`I<EHZAgryB^k_g3}J(t9Jf zv8BTahsvItQq9Oa$YA3L{7kmBm%7pvzwU|k54OA}!kFhLB*rCe?E_z76#(y&+yAK$ za1I>`nFKNU?PV^**JX#KRrw7s1Mh4WUaz#S+M8s&2rrY-IMAOjh!jJC_)1SYZw`Pb zqT42G2fs=VX|wqVN#O*ulM<;#<AV}{fam5ph=AN4(zo6cLu%8#_v2=^iCObSt%Z%5 zi|guAv3G<mE%jZ4f56f%`nq6FJG^s|54Hom*>F4FF$pHwtKj7eJ1B;PNX#meoY#IA zH=NnCCnx?*FG@YxB+lRh-3=@N75_aCk$)bbZvU`)sBuMM;t%zrVwO@v1G5J|bSiAs z+k+29d(WWWdv`lhOl*nFQVRg}NoH%NM0X$q^1;&$doB7gXg5RfjqKP%ncU%!?|i^y zdv7kO=?63BCdC<L|G>$g6{@wq@5SSz)r{QIL04pszNSX0QrWlH<Ls?W(Nm*#iRmv- zeLuz#>#pH3ijt<sq_Z}|8i)7FMizg_li9nP)t#W|`YjvPb(lI0fg-kHiDQQjY>4SI zDixqrcdQWF9b;{Yq=V1juQfbn_W~q!EylWp<D>mhGxD?b(es>kXZ1&g%pZ7&j?PeT zlBhRenMy5s3M$6C1%(_}GZP9`VRXxny$;r5*1+0wEkxh7tNn#WwOne+Ft4>7c$Lp? z8y%Q%Z03QqCdf$cxxv(7g|M_#LaL^!o5A9eaj_)Dc5WgSJ0EeQcQ9#_n|<T<gp^!| z-uYEFZU6j;Z}@i4MD{;go3pmLi*J-(Mt<-z3NfhPW(au<jADrvih8}u@9ewQYJLzC z1|G82d)gl630K*UL<phiH(>W1?2jLxoL)ZKsIO+|ctL-_6AB&*-bz`=SyDos*MCAz zDAI<`j4(5I{6Y#-gKS>qEi*@EzLcRx6%J_TdHLn(Y#H44mJ~{O&&(K*6(zW26U$@Y zj(M;=BGC37Z-3rV=v-sSqC&1Y=<oekp;`BxWL@p6XN)7me(L24rY=IB#s9(tK;k$t z@$0(5oTZP-J~%AK0jcMYjd@zxU+;=KG%cq))Gl4~E}g{~-fXn)ws%2i1#OG0OWk`= zLtUHPb{j1rmT6jH`Wh3`TYk6(HtD*ILRUXJ(I%IDqGvlA;LSydj^P3*MPy2k+f$nc z%Lb?NOXh)@EFL(YC)T=&v24Zlm89jHnYPR97Wb83%&TOHP+h(N7$)5&b^ZpC;QE7- zaY26Yo^Wit-e;iP_VxKZ!Ludk5|cw+31&tsgxR?hf|9c$y3fmO*NLWjK$~Ac31hgS zf*g|4f^gByPH>tU#$-RHa=~RD_eR>C6gHA0c=WCw<e}H*bI|~6WtE1st-NMR^mLHJ zqQ$noVLh!PhfHYG_xB|Tpi+2~N++)r-<m6n<w1iLGlv{96j_B_2`G6@Sn|+iOFGu- zb1OH8B_1_+IKX^8+h0*&mfuHbG!{9crc+X!@`E+u?~b*MRvN024$C{-m6USX&{>1X zxFLm3r`Mo{>bV|-*OhzZ=qa!=LFJN9Z@q^5@ywJ{n(1Ok9iVK0TU968a1WL4N=M)X zl6Pl#=0ZLWiK?;zhy<13zt{w({iUOxwG%==(}<I%NxL7xZfRV}6vH9L5`>@M@~-_O z`Q}pYU1iv0l<?CFb`Gz<cQYLTRX&HSu*cLgAKLdUmqDnn*nQ?b9<hNL649w-s`R^{ zqXX|{V}8Y#tuB*0me5ztXvk>S&tHRUs$nM=5BB<g6;ujupOEJHw_Cz?_*I-mlME+Y zew|i{0JJX=h2B(aGm;+Wd}j%v{HM3>*TcP4Gs6$ln&e@d&Pl9gJTp%0d=AX*R~=ik z_}%a~`ml$v3}s+SHY`)K-Dx~v;7*>CWP8$9&Kzuq`NYkk0-2L;(4=@#Gxu{o6sbST zu6jZ=mcUC9yM}YLfW!vWfkl-y{ejHcSz<j)_(HF9Mmd$7J`ul`jkdunPOHy0Y7B;# zMhteQLnXB2xD=DSvbTlfI6|>sp39-79`yq$AJZ-&UbX=mwE@thz>YHQo5!B}yV9e5 zqlvT`&8xyY#y@a9yZQ3>cC(W=-*!or>}NY)J@oVS+;*<|so2ooy|#A_*}YGjhIp2` zlw6dy?wSug;Gv~ug-zf1`YsveIukl<avej@DL=p+W;LO~Jnz#BIFn5ccbJKc!IX3I z5yz0wniLgpo-+qBC1s(}!Wn4Y|5dzao37Np`&T`*PT;9Xqd5&EvH4z`TU;2m!UeYJ zg*$pDM|XP@0h=4SeyypgOw=$eYhT{|OF~XUE!M2&*+heRo2sR5vE=50!42%qo*=eG zl_}0iP6Y<h-Vdvt@8~r|+Q!2#&D2_(J$JbE2Eie|N25KHht()h&&J=fn&_8qU<!{^ z-OqkhNrAMwalExLXlap_{5YXO8lVHWl8G*_Jqq~an>mjf5!WX<)0-@wryR}N0}z_V z8`?7%__3?Ph^%F1Yp+UV1*;ct0Jb7K)$K)YW2ie<<MYs_&7f_uJnJ7g)Id|Jbf6z2 zN1w?|HoFjT{lCCCk)lp%5u!uKM`?DdJ`S-9DbJycHY|d@M-8!K^Q!Gh&tXUP_H0Qf z`T_=Rzu?q|oeB4m;SmRZT~d65Hw7JajjEiLjBya(vktKBFan=4oIky@G;PITpF@Fu zJS81LT-n=#r&iwDaiB#%X7PLa1D6PZL9I^vY@-Ncr+u`3@;QEH9iH!lah0kS|EgR5 zS5X<LUlsW47`V0aEzjbJSvoi!uJO}6xy0dEx{A`4d&5wBC2-vf?KZQNted%0`2jWW zrC&yUE6=7Gj2w!tx0ZnzhZqt({i-4=hXeg&bW}y%1_CJtCu^<qUSuK$e+E?|c;Rnv z8F+zIPPdrb{ATSudW`T?-5X`2fKqP6&zwSL3lJq;nw^mRH@80?e&z=fUT$?*RTo!E zneEu#Y#^1OkWjP%O~pq-^|x>HCd8AGwY;L~a+?taDmk$|q50G<jVsryQg>2mfr-ID zd$yL^@Rn2bPM~v?6zYfPJ*4)+jCX}dWD^(-Y&(Ai)QxLFl?QohTp1mKg9P9aM^D=g zl8`4Zx;coo-WPo(XyF49U4Vkj0Cni_0^!w~;0?DZ{uKx$iq9)4!&m;>Rwpz-5B(6q zaE;uVQKz)8fB+2r@6zch^bkqb`<55q3V$58cJ6Yh_NrT3sf1fWZG1UkzK^DrFKpEN zk3K7LSG?)UKU$l9_rnF6RGpIIF9bT*1nAcGWUTk6*hQ|R=_GSYzimjGr=@cv40hY< z`84eGj-A!ZCj(oiK{wgA;ecSVd7$kHdSI(ys~VlQSus)gG(j-Mp#dvUIl0$HXVP1_ zMbVcCl#!}|OPvP<8adf%C;iH7cZ}Xx7-bHo_4s4LW!j9wzahA5dfX&h8ff2gD(36m zLh>UckP<Ex83;L`T4-S6FWOd_x?uag$;iNEDz<&phOt6A=>Ub{`$fgM7Iq71?_BY9 zZPab1_(_=tHNHp8jc9wMO0%G<No+(4@k;H03jx#>0-stxyKyDkOlperWb}E~azUeo zPB*yrTDa6A?<5O%=g_PSj4M}IiMZkRm<jE8z5i2jrZO?bY6i^L3n`Sg9QOwGOJqQ~ zA_L3R93-BOBdb1TOtoI*A;pUV8}T6@iw59ayLm+o(#wfv@h_db)KjH(^z^us<zk*{ zD$c-j4}qYo18eQ4BT>8@>eb??>u4=xH&LO3kZH^>AAZ66<lWo$${D})l=^q>W0@D| zjFtxEKMY2kh<*^Md~1D0Ao64@<ody9P{P#JY$g<m(+NVY7n*eAEwU7PSpF0AP#(J& z8%TcbUhQ{GwrD^0ZvXW!^8^r0-$W>*<$}yQ$Y>n9irZ3kBF^x+UOh@x;oXAsx&92t zI!x>15MhJP+4!wBZ5;o?#>-Q&{*OPwv82{1)3)(tsZMvE)P`Jte*VPj;l-|-1{l;f zaE*+;H;0N$8s&XYUiuykZ8x0Se;ec5g6nw0p7Nu!u{vW-$((DKS`C^*>Nfxm^tW#4 z1R%{@1FnZtiil~;`I(J<RR2VE*D?B^%gURGm%@*6EjOxO5|`v4ZZNYeM=_5z_<AG4 zrJ>T)snIuBNLJuXRi+XRh_u1XR5)@QdGm-^|GdL-Cg(PS09tPJG}}k1_oN=y=4tIB zA`p<xK}Cg!MAgd~c3udBf&I2Pu1(fQkFT!)_xHAzc{dn*GzmfWX-Bil=^DA}pc7W; zs$`n=&Y|htUo%I3d2S~azA}*6Q!!!h4HWM3JjonZCSPUiAceL{Ig(#2r+WM_+N3qK z6|o+;En4r-vXLK!c#h1iZVsz>J4?&=q5dcK_-!4g_UsC$kBIq+CdWbT{r&Wlp_DeG zxE;!m-z(1(QcmwSa{mYmL->B!%4#Ch#QCn-OFv+J-&F7xdUNVnv7=W?O|2|n(U8Ai zokxo&VXXKYkxo4!N=kkL(NQF<zQBp3!$d;ci$!DVw*n5Tt{mX6041i1Fwb|CGM_S* z;G6Z-65ikJ=<645u(a|~;zfBrR;>0}KAB+9`$WF>7(v@P-&Xocmw>8is|K&XWqh-m zA)-K3y~v)#p+y+0=ad1ibi-BjdQl?*KrNb0<CP|5+X2}^BcroY%R%s)A@TzwYpZXm z>>2Vn4Diq7fzp|T-S|~j*<;|*J4-6P67^}mu68X$jLN$5=b!g5O9tNla<KUF)1IN9 z<~YPR<I}IT;y%8;gpu&U;uXq28Y{&j45O&2iNuy^M)lygALP8h`7%yLsQBKbWk%$f zQt*XX0oLhYNUxHZLv1G#tJuS9dir^?xOi-{khOn(Bl-qDJ+7{CQjHF+y2wgB56@7M zdDt%dpks#7N&Pvd=Mc37tBob^Fi0i$CnVi`Jh5+yxGh?@@D?p}DB9@uQt{(~by^N2 zl6P5MpkK<{`b$&>4#5YDgQkgB1jMT|iteL={`kaGx(Wvf{)v^2hhtW7VBD#Z9ghKG zYRFQYo?s(x&%PCA0t2UpA(c&SG#~u-^Qv%p-vlE!>zM}pxJ}Wf{f8#Y<9D3NjE}7e zWA<M$gV?F0c~v3yJMW5G&i1l@!|63+DztFKZ^iza2^)fVFfYbmL-u1^AhI7kVc44U zOs&L9qf8?`MRSG#veas&)TNZ!s#=JYoPI;p;vRp^6&A14a>!F{YKoXJl8b?=??>zI z5u7EBV4^YJs-e(Nxm8e!5i!DWDCASJNd;68J((&dg<KOmw~xxWKb|F-awlm{U<)p1 z3{n*8C><R;K#9Au67yYL?h$2mY0pO{v&!&E_VW;$e~Bw)O{5p;=xp8E{B}2di|0y^ zdi}ud9TZ=vEw}Th$K`?)q4`1sU*#v1FS7SVsAAEzTQxS@^e~r!CkV?v=fG5xNk-Tz zGTUBt_NKeR;mz8IwU#EL9K#&NX~#^>X>yLIH|-uNs@^g+<kws<;*fX<yGCPW^SLfG zv|%oVuU}pOL8hn$#s4e>`B{Z0$|0x2E($`0^mw`YiNOvwQZ$cxS)uSplIhRcbTV=P z#`hHkcbI_gcxm^f{2eiV$8hYh+$y_ZKlp|9Dc@_!;0qmNbp7i(pB1@R5)C=kMd#sM z^XIvz=<b{!>G0&f{`dA|o+mPY{eU^Fz6C3|ROl=C>$Te5IN)KaY}T|Gtge`^N|r&5 zU!s%pwJVHLUMM=oN8cAWidB_=`UPrf9Mc_pgqlj7$-k$X(fHVkr6#P?BgS1(o)-IT zQ7Z<mBuL93IH2B9c4PJSfQI>ZP1GMT77>Y3=Z6>g-xNQlimBibxIMCbEUp)J_2KH8 zk%~r414q5$3-1NP4}gfGI`n3hFRbE#c9q^c^29^0qp;6lMnd1d-(pN8@aKziS|p0( zQSj^D%tPyh9j`~{+eU51FNf<7zv#<6aNDx<%~&&#Fx9w~fsNrIsy-H-tKDu$VG0DC z{BkzjPo=g500TefUx7af`0W+%wHp2a^G$59Y;C}^Y!Q`FU##!^yw8&JoZ#6^x*hSc z-St8F5UAPp+3*9iPZ+lvBsJV+-#PV8i4g<x7e^fDHk^t&$vSRC$)0*lC8Y39b#c9t z1g(LBIYrFGbvLn$%x@u`mK>F#b>_b?u+F(hs?0Di37YCLLzE1MMmX%^gK_o6KQ8WY zD(XgP&J}VDK0B1)66ACy&o}|?<Z<b6oPK}_ISa~5-+gmh$Km|7^U?0`_k_+N4k7ZP z^zI%GNz;#5k_YexUgwz3yG9cP-6m=d^aH0Wj6OoVbqq8gL`G6LVnw3l^3#%}ExlO~ zZ1H|2ohFgFu)M@tr6`0hgrYw6s8W8M&KpA?6SrU|@-UeXFcM<2)ZFTmQsn8%(UiUJ z4*+<f`5z}%&u`fcru2R4-FbA1eigYv{qsRo%|lY@O;%dAW3&N6mMj9o=o#><chCEk zp1bnx6XBTvDVqn*Y^*>zGG$Y7;ro-@o<v!d>|Y*DV<sF9O#*OotCjJVG>*KL>-_~^ zLOVizIGn3H-+OhZJxf4^Pk!aAQ(e3qQ-3RR0TI?2$3gXB@>RwueK=S-{SI;-c@s;! z=3#EGV<+M`ZoP))m<fOR#fmQCt^9*U%^2>2WdRB!*$0cS-mDEO`89i~iH$?<-QJw_ zuvxS%n~K=Da}?J5$g}gi9h=yyc8p1ZMJj3ey5RcFAH7ZFAgaswC&xQv*G11!Vu^}x zccs2udGvrPP@qVm?{v*;c<^9`Z}0lyX{!DhUQu^YL_LMbxhKy!tVLC_71BXX$H+Iz z*qV}>D^HE3Jgv`m*T#l%fI}mw4P>TiIWwvO=l-}Af=+ecVhE(xkQK4Md?q$^Ti_p; z5@_I@PL_ge-|wLsq)7){KHndg<CpISM+YAaEyS<C^6CJjRnV~_i6Gug1hQogGQN9h zABB}=S3Peeg2Td({_xaal#UU2-RpC;Z1H@A&Q|DdNvvW6ZS_-g8<s%@bDhs=Pm*1w z9?8ty-lH;mtvssj&g`m6d>Jf)lKfC7aF5E^*X;JuGaCELri2)Xn8e=GvS4fIRX?4` za(Nc@gSyu}A5cgy*v^~vbgj9rj#o{d^x5<x1u-Fu_eQ6@l`4h+k`!4Lshe=O_Vj=- z`T$(U9Nft5hUfWOXQuV^SVaQ&o(v3|B`u^3C}p}2gnL}Et7U3_%0vR(z8`^vq_Y{+ zpwCqQa{QJa^$wI}E+vG~?oC_u0f)O~pA;p5$-2%d%~-aHjUyDVR!4rzwy9al6mx&( zH9g8h)Sb+|TXUb6;HW>6!cDtuI2(g7JvT!;4k9+13l!rYTE}G=1Q0x*JXV+Vc2p%! zUP<CBd{^LmRiN$}I_DWpTBuV?!mFE=uj$J+uYT8yvyturAiH9FZz8hNqP{M7gHeiv z$Sbn}2?59TjH`-UYFlvPA6U9iAur#N?A%y{*RCtULfDtot8WT8eT8z}W<B%0z@jpI z{&CFf2PhJ<q)q?oa$WmtBa(EyIoG<o`}gsP({K0Vd|Fu+H@se%6k5j_a@u-8jH;lN z-u15{C2x&_xlzjx9^M7`mD!y+-c`O|V7XX($`3Q&?(|$JzDBMI4r%VnW@q_9POoC8 zvLQvNrnW`PbzUhUDLb5^KPUSubnJovwD<9~`mj#%PQsjeS1DAtT3qnqe0Wa`=L;;l zBL?ot`))+>btGT$qe`wL6h_1z$9@$)&CvDa#1juujv0z^X|o<UDL!)lBAS?!whF%# zMsb!`088Xy``c7Juh}f8kTLXPU{kv7<3=GTiNc|ZyLs#1%XE&R;l8cWL)puD<VKSt z7s!`G1$)2{9Hi}T8?dOMc237n6t8FV?gunP(+#C23lBZI_4a%z;t2fc#-#)2dOJnk z8>_iyKz%WQo=WzbgSu^?>P<b4iFT7nTPA3;H~GxNU?atG1$Qu|)>>4kywRfa%9zo| zbLQu-x|#ekVC*MgxntIMk&5mH__`kHworz!@>&Wk+`S2LZVB#iee8xpEnAa)GPx0s zDuP#I4c_>uLy8SlR@Cah=4VWtWE(4BQ&Nc^?tI{T$>*51-7V`sAF)A;WRyfyW;_{- z>uVql-36L4#ysA{UhmoDSJt-S^Ci-okcNuIcBxVDNYI-7^BbAR=&6{tdEN8w)Yf5P zaezwo*K!I@0Sw8<q@yrdvg`E;QDF;k$#*-jTcxQ;EhpyB8*T3mx6WO_Q{K?RQM>Km zi#e)`I&oS2a?Gmk%GKS|$s>2mqoghD5Or8;f5V_T6x0^#NyU5o!rX5wn0>w*Z1Uln z)HM<f)7#ko%o8+-Uamplu!VooXcc{cT4z7)_V|@vfw}$$YcU!Duy#M3e{dFN1Lxcw z@^=XO`HqiS)l$>QHF9083P093H>&XHIk@lku_zvqGB75XcALrgX+HTw?mkkM6}S$W zibo3jCH5q!uJ!*T?W@D0>Y{#MP(nH+q!~)2K{`en1w;i2Nl9txW>k=_K?x-W1d)<d zkd_ceL56Nna_AbGVdkFU?fAa?+~@u$k1(^(K6|gdezDe;E(`COYIjz<kBK*$6+Ja9 z3(2Z@c^4GPG2O+-_<WK!RT60ZLHF%MJwL2a!-MIVTs&yqHGDtpE-b?3t7coD(xtpj z&w98B2$4r#oc-di>fyanfeA3yNywRftLnCL4_Q8K9Vz_@Ua5<8a4{N1kiN)LiV=*1 zVw{UG$6hWAm?W(GjUo2<=k=HX;3(W0aP_TmU>&iBumWg8O96+uaQVXVAK+5$nV*^K zh5@Slc*OL=yOGxg<DtV={z8kqKN#<eVa;e4`~_lHU?H$i7?S|UpmmRUNO(0^Jt9>1 zq1D;LF^nv%D(tKDwVU|ZsViYtuxFtPpYN5go`oS)V-lVb-*?}nMZ08dpM|k*e`}=Z zG&}og1rAGLji{y4ICa=}Yqe2R>dT9o-sL3R%Z`?OK+~$2dyl=HYAs03O=9M5A>0Ln ze6KFmb^F!R1%!Z2_a{u9qNj-^o~#0XKt}ft;u*OlUeK`*lwj<ZP(>Cc<#;b_K0Y!_ zOe-7nD#^bOOp6P;NxML}A{YR=kqbs&EI;#AZZWN~5Mty=jUBxQqFcQ>zKv*>rhHvU z-TQp6-_ZDyiA)S{6mJU0Q^*X>CD@NvQoQL8%)+c<jR(H|6AjSE{)`{0e<J(BZ_19e z%Pf$`)fq;3pOMVNQpOX2E4QHqM?jkocZn=5lav;&`|u{?E@5H|rm$D+Pxa3(6{$-_ zNcwy&g;-Eh;@7CvAQRORG-F&w!2+_4jc^YCmEAM1AeUDeVoYegBL_)4vKr)%rpW+( z+u=|u()VwGJt_R3VOPHkZ)A*_TD)-Fxkz9x+smLZ&$b<0a!5l+VtXhQPJJx4Th0~t zKF1YnmRRy5`0FY1uAFPz1^Dnbq0X)&Rf@n`AJ<RLmac~5;`kw|NiKB_0Vo?N2qf8s z@~4}=_~@$>e6n3_L~EebRgC!9o}0>$v|h!QW@@EIZb=9F9G)-M{|MpeAN2DYqf!XI zJ($3zTK8ndh56lT;zV1j<+C(04DtJkL3yjm-j=)Zge(G8Zpr(eH(x^9%||S~d-x;r z-1w^m2h4PoWv@^is~$P9*FY@vMj;}5`^<g&?`)XM3T$++rKyX1;kA{@!r{hB^pnSA zQEorxHoN-PBt+BEYS15Q7F2bu#^r<kyTjTO5#iVG{(H5P6#dXi@}=a;Cl0^{r>7`9 z<n<Js;;l-dP`rM1iO0Wp-$#d%Osbh+Fhq=*+i?UeN_;Gtmz*YMM{1+C$Emy#aKUwk z@bw-U+}JOvx?B9{kwWL~L#cwT;;d~Y!ypQh2O|w2JtBgxhosl78gmEDDTpmo*WwQ& z;ff@AS#+xX@OL?9!y;WKk|JTX!r8I4V)grD-GQ`})HS1Gr_nkLCjEsDu4Dudw%BEo zE1|_~3oZk6lMn@k0Pyu0ixE@f5sJ4iDk`t9{d*Do!G@{Kfc*~bZ{M+Fw2(y><PyhS ziFsJY>a8Qd9lRX5@=(lUIqp_OfWX~&k4PTP4|Sw%fo+iuH?z%$G(*IW>OP7!kpx^L zRL(phHXC^iZB=gdSPm!L`#AN9qxR-lRs9t))t@gWSNL7~;jM-GXH}*5y#(@kR_p|? zKQ`Hv^0pzoLQ1nRWlTYCOwaWuXnA8@`|BH})!3gS(C!EIFLkxF^q>Db7s8PsAA%S; z)whulpnFa7|Mqyll6|<qjSJfM0FUNx`1lWE^eOHO#0ma&cqi9LlyN&AimJriI44$~ z{r5orcQ)of{>Uw$Yq;0a%qnz4M&5RH3WSGoTDq+}Ly-Y|5<qXZnH(ccY?%KfbpGQb zfMjq}wvV-oc!y*alr4uxJ_L1IRlwkYD<+^+keEqQ(bv%JjXpZ8$T>!*R@1VicuILf zy@<5f^1Wlcbf-Q&aZ?b@uY}saquxz)SxslbZ8jrQ=Wlkdu<0bU0^5Zw*b);Gtz*Z$ z{2NLh=X0FD4?RT0t|`1o`9^{I+-jnPKkTh5ek{my>afIiQv+C7excRhfK>r9_jzR1 zBMQZUveZ*A1E`p&S_V=hp4zWr%b~OyF4~ZtTbTbs%*ZsHT*{g-%A3~F(SW%>TUaAb zKfoPI(HZx?KijV2lM->ong{a;!$zWNE#t;Y!Q^27B%8xVDtWm>;SBtJTso)mb6@3s znTOpBrsbiPqp?&275{#`oej4c8qI=lckIUnl81wzJ3ienywa`H-v8gIcRv0%)NAV* zjCJY!)RwuTIR`v<WOUDmZvcjkUN2ImB##L&Uyy>nw@Q?zt<zYzi5?#`?)(KBsa8fi z&O)<KRg#>h=0-Q(mhQ|*Z)DRk#pB5lR}yQUs6TTfsHR_xD7H}$z_t;caUtq#RI;}^ zWa%tp-%joq&h-RwO|VB^2y^n+U+{%OR?{!2SttidiQBJpdBWgg8gbKcUqM)^mA5tr z3;}p070Gw?+@V4033Mx*o+<EH=$cO~JjZ`co!HU%-_dQ%bF>^f-&I)DOx+(k99LwQ z@Z@$w<QF1Lz=$B?=WOP>IfrC5I$?BpnmSsk$B(1;LDE!Y+A3^1UCriwhFAdBOsML{ zf(dku=dj_LgNl9GdsXRyLH5T7{5o5<&_T5WI+H70sgX9RNU>?jGUw<_&fRdh31h${ zMT_9&fL`N~4dcC!R71sV4t4r>cw^$IuZZkM!404xWX|=u*=M29#J+6#zH9(u_KWqt z!Rjq2LTNc`hmU4kL0fMogh36_nfYsVdbU#ER0F?#1qInq`LIZduI_wvxX<cU?1uRI zNY7cvOnE^F>Y>q7J{Cvo^St(<SA66%!%WbwqTxfKJiH4z4T#8vAH&AwLHmJ<E~TSN z7O(V(zmoksV7k<q_H}ARIKV_Hu6$Yd=;mab<SWt!;lTeQtgCH#)uY>|;**UK7U&qu z*u#=CVB#>lExU2_avg@MQ%fh7qbI<k$$J)<#FoZcdA%CpKi(&f(AKHhmcidLj!e?d z9oj)ja~$X#WaV!!us|jEU$W)^H(huu41}<7>@o(gRNfhJg^J9nK=rI5{3__{OWY9P z(!^e>V;FpkQK?Cc&@mQBI@dws<aRJdX3l5k6>_(OYCb5*-LFNmL3KG|c;Eo0-UU}a zV^@(Ecym^rn6($UVLB5?t-^G!6#P9tmQ4;%d>RS#vTD5&X}7%nXeH+|Yu+4rxv&Nf ziBEtTF1qW60@pKwOLSPPNm?S~U46aO(xfied1KA))h909dVc0b1oaV3uOsB==<VP@ zPO51zT}gMvHVR+dPXjq{$#&W<bbQjbm5fVs!y{;_1PBgxRm4fu0iq=qt!+z4=F6_5 zGYZB&J!s_c6f-om2JZddUSY}m4!oP|=Ko&JpWH@S_gt>dB^?qEfEm<J9S+r>UOUD? zEuY3_v%zb%8e`i_^^dVE2dkfD>Ljg?kqcMAuX*SW5ES=8K^$*8i9mYoCvJ9)PxKmr zdtZ|2w&Gc+w?IU@9G}J=a*czoc#%`fnk|qTFK5pjG6NJ4yE?BjF@kEG&8J`u2GOWm zi>!Pt4<hmjhqy%_UXq(cx#iC*DR%)8XuumtDbLaGB9K=9Ds0TvPdA!U=zN;JZHtLd z2h!ztqmPMXPtn!xk19`wf`@ZrPp^Ic%+kNV36sUh;uephxad~+ONL@Hm1j|gBMSW( z6LKRZh6{;nNlu@Hc<VEH#3{?Urc7*o76uv1e=vWNyyw~&X@HPdwQJbZC|lConQI(Y zOBGj&IY4;b8UB)f$b>A+sDWTe$eZshNVsgrhoMn=jMB{lBi=#RO`EzNo1TM!!GE8? z(L#RnjZ#Tl>~YbvFx0K_Q-_(Ik&D_krud1&j(`P_r?&O&Df0Clp4);Xm}APT-w|r| ztKzJxX+g#)wNr<bvSYcd<*{QsMqt!-f@`XeW^0qY=0zBJ%{{OR%;k5csLOTHjP8rT zO+k=|V6MrvQQmB(1=#ck3eWJ^)s}1gGo!|B0H2%>?Ou8C@nYHwKE37$+g}_sWg56P z*p!JKtNws2W1iBYbrFyu&!i_c1q7Ftlc0lNwSYL+1tju^hp#Z>x+^XWddcMFc!n2p zU)Vo2^g1TIeM%^$DYHs5<3A?Ie}p7}2YM)0JudY80RMKv8o=9+spBIA{~(w>egnS@ zMOh`9_tKbL-Oa2l%@f_NBUO6ukBLuIGo-$9Rh)@maI?ddqD2P*hTub#e$fsfjh0Mk z2dG3a_S$YET+QYbJ?K0S5D1R-xWj5S1#mDg$4T_cpn4?Ax%fQ*=Paww&|M-n|D0;B z%xS1^B1iajlRrol{H6@OL$jogk#LpQkA6IIC^w<_%51*0jEp%(zUJsMHPOMYpLXmc zzG+X+$2g<8GS5~-_MAyBtWml`B_GSVx5N|TVA%)&%jWLQq7hl@8qtjrwoDD}rAi6P zy%|h4ejA6BuMN;=VL-Vx%aQJOy?YcoxduXS8=74>SuMJI7ADoDoNF1Q+)v^_`#z?4 zeIEcG`G9hwLtF$nnE;<kBv$+098MTHobsZSTjl_=F|DRQBtDu;GmSC_KiR9-n+ruj zyoGP7HoRz2=O8QHCgnnxP+ID9E>TVIC$7S&WZ~iZ53!9r8j?R^jF#@tP6xc>itezD zdu*t7iYx;WMJYryUg-jnf4sHq!P&E+3TN2hDu8SflZOguFkq!GVCur)y#CU2B9HVy z*hZp=C~#Cr?qjL`*6o9L#;v%>at#+*_G5Mti3+=L7zDF|KIU>Xw*UTme>pEP+w&Vg z@JmT25x--9Zl6ZBCYGf*-6j_L`J%#}4#2KDbhm02HXL;60zuU&eOuHN!|^CJuR-6E zHrYl14pC(kIwpSxyXOxoEBst%Ap4jl=*d*N^sS<3EjBYgI*21a!dgftSbgEzMQ_0+ z*klY@WI*;aacW*)g}6<F^oO-e<UT<LAiH;pemRP#j<bRQA45}Dny9>sv|MWiyXQ=L z!G^Q%`@{i#v)T~s&r3O4xc3lTRvCQr!{M55;=a_#5jcJb!NsM*93U<Y36w!FKwG?) zGr&Cx$OM-8cmaTOuq%-rGUd_Lk6V+>e=u5?wle5`_Y+XI`%kq03~iSg@|Vmtwa_e% ze=q750O4j=n#`y*NlH87To{zOlivX6)WQVIa62)!SA1f!QFb~2)DYEY6DY!o>i7g% z#*x4%u~AE_K+7jb`#XM7n>$)HX81&eACbDy$#@dVCq!)aJs*XKcF3YUq%|bn-@?E6 zL>4vcH`u+KiZi-0;ZiW_+>ku-d$PAm2fVb+hOGg&yQn#!oaQa?gx7)d{GVw*;D=~X z9q`p`UKFiwXFUA|WT#rEQ}^<jJ(&)7n_2pD$t|$bzu*b+w3OO`(uV0DhQ$-qRd+e+ zF>u)v3@r`d#k0)aACKvUD@~84D^gEee|X2->7KFSSUy=@O0DmG8pYN-%}!T5K$$U7 zpdau@3bs#j=5@Z&naF;h)IX6%(jkr{t-=GqNWMib<Te9tr-T7J={GUlw=;$NFJkz4 zyr4Tlo*ysQ8UOu|e`1^e-;ZM|<of=ABbK52naMGDjUI_9Epg0w`=XQV+)RPPSGXOW ziK82m2m${3H*vQ1T$~jaZSl=y758z2{-XDDs^}{-wblh6?nRjSY$+O5T1o!FdmtTm zLMG|_8Z?+<A<gp%^1i4!9eyU4F16s7B>(taiAIaV((RS`1<v^I;L)J~boD?#Kpj?A z{jxbBw8XJ0x21{qR`^p*VQRR@U7=p-DAV^v5ar69_s`_5&Gs~6EsA8AM`}ghw3FC9 z&ENY3sL8)!z<i6Z%@CjqW;uJ%dS#aHL=kXN<=Xq&8T$;^CA4>_UxCbEmfnWRZP~@k zKEytumr9Tk%x;f9rx4>#$pNcB4jt}LBT8qf=R2P!9_X_>e_W4PK=St_Cw{)T|Ih}7 zuyF`zEcDE{Ip|(^YkkfzV+h<p_xklHx6W}f&jiNgzVQPK>XxmK-hQel$e%(c#RejY zjgZYv^pcRO`bo4mjpJL@$y>rM71R<p@-wuw^W^xfqTu47jksu6HA3q*%r+t=<yvdj z`$rXPckcsAVv;TG#SsadTFJnrF+A0uUis0lsh&Wxvnap1lDvW7y^*uaS3BwvBCqic zF~3_G+|HWBjzBj$+;OyiiX62Fa{V}L=sa9JoW!Y`9da;UUoVGzhcijM+6;C=08lby zzb8Yw9M1@J`R_}1Zqi(zB{Da>N_sKkwFpR0vw9El)I>hB_?b@$Q!R_EleB~L+OtTp z*x8_v;*nQu%dla&h@$mJX2<Ip)3350_4%s<lyUc@%@_TB9Ol|fO;h8Ib`c%`-b<R< zn1n`87Ko_rdp*mwT|iz;dMkWEjg3ZD1skB%SH;^_8bgg@u@_t0c{n=%GEH5WYFzXy zugulLY-u$&hU0hCs2KQj5c3s@1G+lPg-2(|r^@jj*N!8#^jN)~z{#Lo>W1R0E9Xdy zxZ%OVmz;x7bTiylD#;(Y!mmr69~8Gb&rqy>Q<cMpraqff0o_8inF;~Bz}5CEI^Lmj zE%N#}ZQPfad=gAF@`3>OC**{`i#k9W#dX~i$|xxb7ni<`HKT4*^AJ@(^U}3wCp;Z{ z-AI*SocT^s(k_lF;RRuS>zS7$sEG}Jigbb!fDkceB6UBq#7!0g&}cplB}xX_+qNVz zv=SP&_@NL3Tle;;?2UDqp5}texQC#v=*&E<g0?N^UR6UW5r_F9?Uj5RKtN=`&5cJv znZuj1E`GjP7xy9BNb<eL!|33PsNhJr<0Hg1xg~EXw*5ioMeWi~33=@RO%g1AuV9N+ zUfo6=`S*s~wxj^og8PAx(WQ3RKaU5xN5{2mt(aF5*D6-uWs@3lW4Gy$<jm&>j(Z>- z5Z{Dd&=lu8Sq5xH0YFPhznK8!!Nz1cU@8C<SC_(?E*#zQmwhzmS^G04e($@|Fw5Kv zF<H2ov<=XVHHl?#haQD^E;gpTDifL<Q^7PxJ9sFS4)L81lCq#O*+%^M{J1O^Ja%hA z7(PG>J(#@%bp)~7q;C>4Iy%g$gJ4k##ET_SE3mZ>rfyG*Z&L-Zs{~1~0*w$LvFT8{ zaT-v==e-1m@qv?N;PIo;!k)G8PO2|}u9afyJ6Zi6&IMvu;r|syResN^a_1RIpc>Hn z^*Gg?0pl9!0?x9)wUPHklx*l82}Cf^T$6nGz!<lw{tW#zqZ_Na-#>b_TM9F#=5iTG z0FSpG*#Cy>h1X>i!Y4wkMk1)=igQ+C5&z+Suo%!(Did2L%u#?wBbKTL*oawIVe(wD zU%VJI*GqR^z>_^9;l*(C(#9QLkdgJ1&98xF`2Z2WUZTFF^0_R}Mtm8Dz45~0iO*J8 zwE7up!njBlgj_vOX{>+U?L8-el5L;mKNpRwOGRWW>VePpfU2k?{7n8{Z=^oZJk@({ zI?)Wf9-KemhMs4~!VM<K|8Y*u)tmeERf{FaV%?Pefb;GidTWK0*@tBV=Bz+rIP4fR za)hZ{Za8k6iCH$xR>o$kIuPtM`Bb)E+DAO|LrxQ5kCWhOaCC4Ll;S~7LgHu5G@HPZ zg=6W?&xdl_b?OUSpeAn}!ZVbfR@50Wjf}fUm0A8d>e}S@q_j>L6vG`Ce?F0sWr)x6 z9pv1-Ou&8?Z4C^*uQ}w@XT*fh*-_f;ADeQ`7v&}^IvXJmJ(j-pR(Rq}<HTXnk(6YF zsXfyQU5(*!$$V^g=B2s-R82xyA3Bl9eFGmpjmsjOucs=?_M<5h$4_M#H(!uwyzDLs zeG7C(1gkZ7#j(c(ldJ^^Y8d+Ui;10~C?CxVYh4n@S86QR%D7jn{sDra!DGlBALSs8 z+<-yU=&AW!d}LOg)o1payOMxCaSuorfHQVr;SBW?xK7c@sjAvS=^sNE@(VMsG!jCc zg)LI;EHx8jUE<e2o)y#7d7!`y`hERldF2;w0{51CrDV?6lL42-qqYs3vt}LrKL11} zLZ@t;aT}n4EeMd!{0}X$zYgp2igM=2OyWp3u=qnP&Rn7LJE85uazF<Bmoa&z37gl9 z+h+j#xFnY;`+Tf_<}KFU)1McZLO-%_=Y+kzo&z~})A$I4b)i@$*L9$tXAN!^8+a@5 zXrq08!S;4H7|Hw!P?8|W(o<-}d(rt;(BKY9n~k>)K<MxK>vYhR^fxxC)u+@8y*Wd< z#PzXph%;G_kBfK32G8yzTA~!(KOnC{UDZ;hR&hDSWt^CPul%|zcB%z}{WxmT5OR9Z zuwK;-)Kj+{FJ(kHh5lm&+|2Pqtz?tdkG;O5MZ0mEG-_uwT@qXB>Z;gWLV+2yY_V{A zqC<X&@Oe7;@#4YTFT}=0uNxabdU+3h>4QJLoc!SQ;+ApIptidxwiG`YR`Pn#pW)#X zh~XCfy5YbnQI<0np)P#cL{HC=bo4~{Lv`C8BIaWf@d@+1V#t*qY$>{0)g8(_`|8J& z#|i$}obNk*`)O8pKD-ekeA*Iy<vec}#68)NfbJyF!n{XJPjP<;SQC>U93=o3->4;| zDfcz|Kei+eWa%9ItnJ#2B~i70rsQ{tg=gB}%<E^)qE!mh63kh}q4JB%wg8qs^2DJi z>e)dmfd!U@&sFP&SdHq~vniiT<itU*Y|dzY!X~Y)P<V`Ur>wSBC}b{GF1t<CE-|YY z6wU{t1dUc&Uyry6{>87DQP}enyrfh9$OYS22`7h}^<PB;jF9e*aGRw%CZi9$#lI_9 zgK!IsnWzzAruYFQP)YWe&NE*?@WRZ+iU5U7AHL9=dan%FO}f@Loo+US;Pqa1s7Dn6 zw-d?jY-*N4d_(yk=>0RD9@+`q^GFw#QuKK&wQRo$d-|hXgR!3qr~><B1fe&0x7cJ} z%W{y=Rv%RhqHjN}Qt=7`jt*g$m^aBSoL2#~e<yF$=IZW6Xi&~gk;_*ICKXul14v?+ zB?xZj9%>L?`f>{t$+@y~AEfyvGZFqGNx{S;wKv0~saIc&`u_B_s`m+%Ud{%p+nan< zw`_Y}`KRPIl*+i|Ae;0SxZ<3e+aII?$PDBFzsopu=B$EMP+6cFg2c}#%~!DAraz9Q z(*dZB>hSYrYdZoK(0O6js|l1~GRk_|o*r!YP5X=j#@uW2(K3JE{`{(k_6g^@2#_PR z?+Ku%#L2&A1~KKf&!)n}tT!*q0$8lJlP&49pQE1~dFV$N_2a0IrD+_nT2Xq3uAcBK z&ENesA6oSQnv`mE7cwWwZd!O(k84RR?!K=H!_qMUG;jaqg`GE@KwcDQX6Bc^Dj&b$ z^@4L-x8}3e`c6bDU-<P4xH0YDlGs7?7AyYhZ+4oj*#H_B>~}J|UsqeR!Ko>ZqJQug ze-om*`pl}yXjYydUa0@@T%OgXgY3rZ<<uD_Q)Mp78|1}%bdIhU$GVwf{8)X(fg#6z z4kF8{5Qd7i_qUbZlv3`oBX6UByuvY;`86_1Fz=oBAfzVN%uL()bdT1N_VW0pjI#26 zG8HWeT)uy=+;$2K2FfS-V8Na^GqI`bM}0lT`zt1YWVWjvM@u9IgO)%c9pI3!0-}W< zuoi)C3Ju8YASQ2J72J9MU%2Zxv;Bqhke%#-UEiJw+S&j-_dx8~7<`A295s`$`*!({ zF9K3%vFm~8qaEkc%FcV*LLVpH8it34hK7eF;kUwZsndVW*q_>#R#P%iwhMI84+Vfb zP$0UOtSvnLRyz%-29yJ5{m42$x`R@QvFLKh*;+JTHske2cN%;*Mob*ChG;$ho|F6u zNB<PQfXM=E_1OVSue6(F^kWE#IstDyvLM6FQ^^NNb4MLYVsZB4|Jx`BjL}}_ir!x` zJe*w}aOz%neky1oNNT@`Ej7(Ntu8D0i(&VCP5lRMp4v?)$!huZ89m|Q3m>Xe$DcDu z&ir3ww0q@!;CH0B5Yr00xnDK@uVm#$%mRP{$7H>_a!U>;Z~fIO`}sk}7uGwhtTkhd zZtv+?@6*fpERff^KdE^@>Svv$=$_Rg+gi|6pmw$il<CO~*DT+oH8A}w6<4YDgF<q& z+v1K+_K`~Hscz`8I=x^L43f&;Ox5`AoKij49RCZKCm)$_#Or1$l+}#9?4D3+;5-gc zAe?w*KVk2jeGfNPzNuZGPSo5Quc>r+nm1Mex3UNN?tD37GI<7}FcBGL<2yjOJ)a?D zP=e8!ML)0x&K|l4gi7>!-?m!1A(;7n1Q^~jLpKSQZ=q1B%<>k1-UgkiMaWgJh@06~ zz^g#6>JK_%SKNXZ==o-3#eAt8xx}d;2Vb^?d(GO_PGY^q3dT~#06N@6Bj5aJ>5?;` zIVH@B_42Or49KlCbA%^>&XdXiU?!TUzdO%qX_vZG`(3SmE#m3#6_+G){f=gFIz-CO z@#iB`dBNlx2o@>DJ}`szhknT~RcnQc#Zq+;!`Oqw`(>9{o6Nk!>n6B-p0=m!9-ARy zZ0j&uH(yG<uk4V|U@QkReUP2x01*_WqdMMRT=bjwlv`Xs&CgRiiIyXBvNKk;;|MM! z5^Kg$g-3=`J@NvD`gtq`s^av!cz$1=<~j=c0E-1;C|!GPpEBo0-5uNZ?es47-sgD$ zLlN^Uj#-ACbI*TS#sJHlz(tX8S3j@OXD7-Ss5F_QwUtS+`yK-s!BfIET0LF-s=bfc z`7vfZ1RmwDHKR?D;<ol^J_vX1lnLJU>IGwuLdTE<*eQw&DF}vRvxU>Cvfi%?h8oKS zAfsr7tDa$i8QW$DsU$ZRT_?_M{~<wE+cp>O1sY`*1E5=?@)uS08QNpr1zjXD|G<@R z6OLncAWNIFChwr$p?#g9lqt%sCid04fC?w1wgcbR^#+VXeM7Wi6E<Cd^af)#$Tl6p zFiz+abEf>7GyQwBR4$e=O=Nm?;B+u2;f}Ftjr6soahex^<4G^cn4&Mc=)__2WaMFA z6=cuT6T42Km9XL;dxU)bOp(HPkcxlfQc-Lvr;^PA61<oQ^Td}5e+JnkQ4f9rp9G=Q z+@51L9)+_-Lwjz2{t+LYCHgZ!Ejhh9GbMS-YF#pnY2gHUD7I>Bhd-{lpm8*_Vu3{q ztzO};x_EuxgYi{x6MRXIw*ca6-77$k%1Uqy%VaaM5|{>VpV$VP&vMJ+FhSsRjO@8~ z^cNJq=DXjw^k8lJDS<l+fWan2jJ_#JJ7HNeAINg+d5+zgAvr+?+dFnAAwN`$NNV2P zVlR!YloRg9jGIx*S8HZgj=1S;lhWHrEL}K8=^Z=Tt7)}@59#YJ=B0IUVmmL#J(tom zeCif(b9vGCrZr&MJG}Gt`0>vsHQ~0tHI&*W=?=nGbUuZVYvTiil~tb|V^X(iqh{Y8 zxphT}fis*N@R<RJ)xTec$8?$e@;GBxCZsk;o~I6y@Iqfs$?>q_=wggrP^MSdDYDQH zU56QG{aniAa*V8~1)Vgx=|aC8Un3iA^C_q;-*Nv6;IKy$Z!E2^-b8!xL0dQ=Ure+D zgD+|vD7kUxJRUP#5MIbh7xa7$Zw9TI%F4}k0Nr%-p(24yp=Dg2BD?N!8Xun?OB>vd zYe)(_VZSpH6A1J#AS=V@e{jnC%dCIdM_`W;5M03%a0$wh*T546;NZo*kO+XH{FN*0 z@M#FpXGwqDo|P_$)p%Z|#BeUs&~&$!&p2<RnV-|Vta#J==$&VqY`G~=K~=-ucBXNJ zL}w7ij|T%6R>nhmYq@R1jQYUkPgofAem)Oz<$PMME*wj)F1Oq_3yO?Z;M%Q(M-nSh zx?eE6R3|@`t{VF#^LY>5X!LqqJ_}dHr)JRmouXX?ZEh9#2_g7mdt6s;_Dx`w5#75F ziLeW~wp#(O1eL^i|BB#1v}(RPHSgl3mo!<cQ{l6Z#<W3`(R*=Y^?)aZ@%-qYJ8?iB zIt~_0>oTQ&eZe<~!~TT7)4nvOn}iK^<qvLeV_IXnk$2+}U}r=T+Ud!&+x%EBfCFlR zBhn6JrL}J!OS`B@tK>r{yr$h00~}f8v0fjZ3AYW(0vS3MWy$H!7v;h=fKPIw2K7@H z?)b(2xkRPBMQv>*{3+uv!R!VoS`CVrD8^A{n4SOptE(c)GKcN&zJXzsl<0gdq0pHG z&T&8o#B0y?qc&kJCvChkb4pSA98>_5sUhteMLlk4#SJ!&s+TD*A+u+4rvV?0)cIyo zKSq)Yf3n(L_}Yu`(hBohdgZ_tumCiy`>R6Ik=pRINE}Tst964&x5TX1;l+m_<6xCt z@M+|VAskF}GFhKPcm(|D^4R>2(;`8?2vMA#t|yiy8P*~FvR>Faysi?o*(su_4B4(m z??j?8_s5U{fOyl%*g`yL8ZS;>_Y#&erKu!$)2(sOQfw#yM97v{o$N9uhFnXp_MVAb z+poGE(Q0@hKLw)1;N(YUP!UKyYZ->F&cN33Tmw@%?<i>~3jjAbSSCr>zUj|y;uzRS zZ@8<ZS(cm?uZ(+K&hrce5QT_Xz56)1@1Orj{yUHN8(<vy127ixotgm<cAj0;G{B{D zJ*ddi*qHkvX8c9jl`*bNKm_91L;-g*>Mp>%l*S(vSzXxbBob12|6H*tiCIl@@O#EX zkq>2e66=;LsDFM503=jDVDoq$XX@HF3h=do4@;8gq3hNKwZT`#i5xTKXIY=Is-?E- zjY=G<-d;k8Jq~0f1Z#GfmD|iMK$MK~^MDErqgaI)yx}I`;sI;!fso)ZSWFBOGDA{s z=zY*b#tpIP_b&%=h8y6YFWWb06dn=FV~(424h+AY<i8g`Xl*aqRS~sl_*xn;GSM1n z-*8)5T7<<fjvTe&YbU*=Kp|-6_n+aR9^9JRf{}mB7y}cP8ANT717z02>Y*cNQtjzR znGUeFEXm2&MhIp@8qjX1j<#`$QD_n*B>520V7R#JqN6boN3Ai=L~`N={hpgMs!9__ zE;?Xb83X4Bd3go#@}-(GiYdNN_rOJb3mVdmFpnYE`D0`Yr+eq&{t68H%%k5lmxtXt zXFukP6c~u2I4J~>ic#OCaf}uh_XQdGwsBU+Lt+)J7eG4pn_h9Q=Gn*Twz~kjeI$iT z+0N?Jw_}GLlOIX5U6=r$3okQ1o>i;yIwX9iZ=;sHDDsBayYYjuJLmPaN*}*5d6H>> zU~g^`P3LRgK0%6jJ}_SV@hRt;^vgqTRY3v68}tcXNr`WWW<L5cdkR_>pbX6L$b)Fb zIR)lA#*U?nIbS5wnE<-968>3rao6{ZS+uzNg5h;l4?^pnDW+k@{wDU0Pi?&|vo#Lp zTubsBh4;%6FI1HBkGToN2&PyW0ao3M!0!8p&px12+Vs5gRizhfc{k-np;J=zO}$TZ zJ0OSoL!n$>OKBSK#&G@&<~cb*`*Y`_;Ty_#jW4<{Cwq0D0Ue2C2b>D4qwX?3YVz?{ z6lo95=$4atWa7^8{o`6YB}q(x^x>|?cvsY`r-pTTS&?sc-&KZSga_X4ncpDh<o)+} z{)BwJ;Kagj<K`&~<N0)IZkAAsqb7-kZBZ`et~>dDo3^$=3ABUL8H=hZvs$}T_w(c7 zH@KnnC1R}VsS-Nn=7>9jO<t9D<f_JMiuOTM>70*JGB)ajcquv$R$N@=04F{ju$=!V z-ybJ%BTn&v8v)?>Rrp`V_$SEvpFZeMkqtNTf4cww3rFEb^OvfQ|GAu#F0ZqiK3^FJ zFn?9Wa6armE$7_-64oqvVi^!wuNyh(0XN`Fi0^Zt!+3S4RNsIA;h7f+ZWn76;64qv zHvV*>Bww*;k)pWMC8mOJqoU>m{HktN7g&Hb3l2uw7YXd>vwsT>y44c^1k3W8z^Xx~ z*nn^Nj=w;*EZx@Q*TsEPTNW=xHsQ{-|NQhLbH&o}p|A5!&boD_->aCDVO`ESfc;U@ z&MUN_iohFC0eLt970}xoMEQy~ceeARaP$%RHbTs&3;`a!IIIs2P{&7m@e51i)kq5~ zR}e|dzmi3qA`L-VYA4ZTKD;a9YWWRX@~ji|5DF>$->ie9tdcVCK2dabNP#Y>r;1r? z_{U0UL$2rC_m9($;4F>Ra)v6+6im<^eDTa%i#9Ib)UcV_UlkhYPam6Tu$Z>)_#`MK zPW-lH|E{#lv0a>yCDZ%9<mM42^UemnhUeu$&S+V{3-!MCc{9)*-WKL7C6&iIzZv`1 zN5`n=lS`wIU+qI_n>T~ZX(A)iCpJFyosSYHl)~bE`6&Ipxu4E!UxP?Wx>;W@k<nQ> z>fgRonjf1>LLRmSWOf-%Ad~M5LTO@_s2#-J>bMjFi?ubccS@XQNQv5XMSlg~_|b;I zvucr|sD|YMboGN)(eKWQjEV4EbE6tE5tq+$SnukGp_&`atmd>X8EenbsJ-$9Fc$hF z^o3<8l%V>%-Y%vt621g_p=Lqzs;Ijf6xmwGA2E+`h<hThP7z+_EqhrKz)4TVJf6T+ zL7K~8N-?K9UtTR5LWR@<Bf4Z3$)S^KH4$qKBa;S}0VcMfi$7aA_oo2XsHya!@zkKk z=V=g8z}rd`QUJsd<6^6`F5uY$?>|9Y2(v!%w=wgje-$A<akBgiltC?l#^meCRqETP zSYFROcx-2J)056ml9bBTu<Q7nUq<fCdCR(xIM~eKYi?A*;HID#>NTVK2jmk3epU|q zB#Ezz*2a~);yT?FHEb6d1wJ*+L=Z93X3hA&@=FO>q}zLw3ko6%IgxtZlvn1O1jm5% z81W9HSrUZi=Y~-A@V6l5AnE363%)L6QWc;)@}G4NIC!UlgLmysKAEp=pa9~D@3L~X z$@D9cWRqrASQ@#L7m6*NE=PbFSbs57p@)j%Pr4M_1ep{Egf_8U=WYmp$>Cu^wL-gu z*IgW)QDw8qzI(bA0kPl!BT@!Y>`Q3W_O)@+`t<;GsYV@8_xDwoJ?3ssyLtlct7o1~ za7O5*qqDn5wRC$`z4XVr`GyM@WppHUywl-9Amnm-wHkelLS*1jl^esWr|Rw{Hc~_E z(;~anah0eQM^RXbmH+A{i0_IRpvevC-`41EAQ<+Fyqox-+-5IOw<9o~AwX?G>{Fj| zy<+du3Apsj&7=jVrcAvb&}SRq@63Ztv_?+`t_OKAyCiw3D={43Ua;me_9%uQKKlCL z%b}~NkXX3CQIw&B{ExTNZErzF51TZW?OEQAo)JP(6`Pc?3JDt$7xA$^P4`T#K6o+j zMUrMI#m!W~Easv?E!KQ9IcYuu_?fq>-X<K!VwTy~W2O5m208tWM#XN|9xE>dLw!I- z6_T%Kz4H+j<mFEm4JRwOrkW?EH%CHjV)~^I)RAVRQ67_C5pIbOI%We;r=m8zShMpL zE;)h?q?e4L>URbma;~_FddNoYb!$(D<p-Qs%l|E=0*R{ABd=Z%^LR$cz$Ypj#Oh)9 zmmhc2({cH#6B$>rkn>E}$mQTFfq3)#Yqxir&icGdp7Pf9@)<azV<bha1fY@Qj!!n) zb-kQx`_k^oM=B;w@~zs?AeiOJD?&awI4{4|3|glQO$B3;*nf!V1fZCYj~!keC!Gi& zVSd0t*jBggZn{#z1}b^8_XMs;bwL*#@tzgWOWt4s1lT@9radYgV$pgFevf8aR^l$! zK+4)-&a3>U*8M+JI!|Z<*9p1gEEd>j*FKf75jFVP#+mEU+0Gl3e(?YasIXBy#iB13 z^s^EL)mxM|i1mDw;GMvX$B(OZjbZ9Yr;f-OPfiu3UNV<n{Q(vMq}5&!=J`&~<jP9- za>xYf_b~?heXp_k6e}|#n>yG-(~aUYlzT6jIHH+SS^hA*5ORrWWDjv(=4q-o&Xf}T z<olcr5hLbOCzW?vI&jg1QP9uhFB#j2!zdSf?(d==U0Upn7L&eX6tr<&?D&aIlqa9l zK<|D!stdTloLnmTA3d2fZu-IAkw$DF?gM}(!hfIAX0;_m{G&`0V=!_#K~>G1)NDEF z{L}%U`^6U`as4_=BYp<V(1b)EH*)^toqgZ}hB2FRjf3yWU1?a8)BCWUvR_j14&JB9 zAB^R}!Zg%~C^m$v9#6V-DZ7$y+3&?cDK1a^%2m|OL?;3}l%c#3?1>3bx!?P4`Z;xR z8L=xteBH}l+aSK+3D%0V4Ydb1l-)s|JcMcW0ffB~Q6=qn#!%3!s(^R37e2ZpNR};< ztJ!pdRALM~qlw#DH7@6=uz<8DO(b@(@?@VbQZ7$1SWTZ=z1aXv*0Inm)n{lg$_2hU zk^;YLgh>spF+jbKpUaG<8rzeo%{T8dPCqbIIW>ld({RQ6us_e;Vz)K|E&$eFu>TMs z!MN@LGRngQfzD7`@2e2CuZ@}^n-Sm2J4HPuiLv6g_BH(DV37+?u{4+W>c<{Aow{80 zyj1g*ku{(c4)YJ(rKyi+lF-BId^<PC{4H;ZUh|z+Msyl4Hmdl(1Fp})Bnsr@3~oNW z`PfoC{Y9luAN<a1*{@gTQc?c2)I`mYK3Es1uk{2ivHfnPu;cNvD0W>ysRSp%<crrm z!<gJ<m`N972i$f`o#0cHJ6aIjW56kkMc=yLduH+TyOXo{Me&U*{`RO8CspY1v9`Zd zitD_~QM)O}UUpdD8eKb>^x`_}b~wZAnTPQHDvSuE*-?F`d8wYV^YIVF!|3}p@jwl< zO6a;~&Pc6hBcQLU%tUME<oMl)LxBCBr8hCpd0)u)`$SswPLokv1X%u*&L;{qZhNHB zD;cL?_?OJt>7QXq*H39(N?M{CW7oU7T6g5gO)oU8+#;K8mh1qRtg|;fl>9;Q?Wq}H zH@sTKv|A}->Z6#?VpL>fNKPU=4nAy)X?e0afk;=PvRQIyy<OtM+y#R5umUs9WY{PT zU`f({C#z+X-y0S`hcj<>a34#rM*$fVV7|U|OP(~?-kkh8zsoxb#jWu6%Y}aRKfpxs z-SJy6#qR>D%0&4Y3EK$eSb&F`Tq)ohY2wXM6g%@WzrXp`<(>a@)z`;lN5KZRd|4JZ zDiwA`A-tZnFMr<KM!>jSzr1~%ZWN7{%!X{nFVqhvP3FSHnk>#xR!75KYQEGftFAr5 zjH8N|=HE=VgCWt;3=c!fmFX!afqxUc5>vt|{1U*N$-`FU6=If9%A0Yc<l47G#D%2v zIdZ5(liPSc7(e?ny%bTV2oYF8yM=yR)g>HarOW>0O9+|3kzc-=)ENpf=GTzR=K_@Q zHv3(!e+e|}u;J2sN@paint9Np{6g+QE6*u%#{c=8{+MMq(_j$iy5iWrWMzj9^nxur zcNB(Z-vuxSfBSdc4B)p3qXYEuv;$0Q-<221zLeT3z2(A5l_#!Yo6MKiKwk1lVkT@R zg4@;Z0liHiAW=(kjQ@Nnuk8hRw4dm78|uhjM6y*DlJ-cN_cWa{l>>%p39h9=0LT(s zxbZE28yAhy1*V0Bzy5-S-I177+6D})UPdU<iG)di-kPV*+m&Sri}$)jV|TS`2`1A1 z`nI|}tZgq3a9+besJ<&opMCv_F3D*SytNYs{K4w(?OFR$3S^{BEYbSG*W(}<LWD_; zM$HB#l<PI-)k~aD@b8!d$0_lSZkH@_B(ih~op#<$)55KoV}nk&8V6!Ty-6LcjNm?n zlqiv>H^u>W->~}Vz84vmB|ThrBrsr?x2qewe!rvDRrnINfk6o0P$C=BYqS}m7{7x6 zFIFjrCm~vPu7z8`l5*6JrIk8j(S$0uM?fO2(I87n44SzbI{WYm{L$6L2DJo+<F+-J zLwh^r=SO3;R9>0V_6}EnFjQ6zUrlVYP>OV-OZnEa!<0>0N<~8p#&$lZ8gj@RXMfm@ z7J`GZF+JSU%lmRn*)=5>?-W30EZo~0_Nv(W`MW5IN!*^GnJsNh_f`Eu==3ZSZa4tA zh6m>y{0BzrYdBW;PB7`Bdo@4W_Z>lp46U>7U@4N{2%K1aN3*|(?ivW(ey7)~6+iK& zMa5^X7t@0DWyL=4)PTUx_`z(xyelLnyCK2nfa9TJvTQ$xt?83dlRClm%I|m+W+Kxq z44q4YAs~{kHw0m3$fYTYuT*oB49&U^5l5{Ec*{<nrE-h7gtXjf2=*uHP7d?zcQ@Ca zK;?dsD>^3_<wY1l1d5)qS6V&v(hj0H+bw?fEUelmVs_?EIl>0LEdpHPXjSdrCq_y= zi2oIq*rql8YG#*nKr=J`P*m8Y?vN6wFrWkE^mh$<X?>^HF{eZ#9mL!5mAVBsNMQ!R zs{z>ab8N9w`1A3U<l_-An>-&4e5bUC0Bp`K;#qbu`N63(2n*D0^WY?ne@q=s<B9H5 zUQ8nsU>D%BezwX#sU$6obrIp&QfNxJE<;|$sc^y5`(l7iL$*n^AeO}-*)9A@55jPD z>GKp*jTB``arha{#I=t+8$F1TInYRV^$y|%3?BuC+}%dV8!RSY3nn5D`b9&s_DiYj zP7tN>#|xYQ3)dV)eUcX|dgnlytE+qkCLirW*m_z5hp3{fiya_wc4vkQ)`H!8kwA<u zsaP&Dj-BswNqKP`tP?;ST}lT;-d~F3Z<ZV7KzwaN`^B8T$+#?huOy$YA|Q<UK~&V> z&4WhW^MCnR!fZ2y5uw0BtInsh$uppCYw16Vc$jE3z#gwm5g%Fk#SB}zaJ<XNIxVb- zZM=N_D8RS~;$J)4>EAQEUM18NR;CS<?utd7aguHMVe}23eqfKA9f5I$QnCWKrTY5& zdt5j;g#mV4wSNPN{DjfGwD!!(m9#KxbV5D;rmW_3xm)c=4&5}7cGnJG=~+s}{bcE{ z_mmi8MP(+|?z*Sr;n_=KUVq>1HuZa<apZ96=F3^y`LD@$gLbt2z4S+o2RHD>0&m@= zRXP(WhhX4m+(=lY(N_!j+G!)bht1FN+g-+kl2*}??R~eE>)7yUw@>pbn%$C#2Enz@ z8kFc|Swi<ukk0{qbM;E1S}WyeFU<WemqLAksYDOBdrrVRW&bkk_vYacpxJVJq2~Kh zvA`zY)dPiR`F(l0rogPbMeobq!p*u{bbhNQCwUbU*EIRDoUm&87EO*w@YZ#~x6)`- z`4|JO&-`%nn4WabRi~9+`#SQ;fNN6w#zS6&G>=LN29?N!4Aw#~G;aETSnv>ZjsmKg zUM|6~Z$=k!cwnb*)>{GJ*t{!~W0$$gV(O>4A6@nJfk3l}#*vVwl*4B)L)%WSwt>q_ z)><YXA+7|Pyx*~1c-$1?)^Sirp>c9^NXlT;<^;(j_V|R#*3tyfwr_RR=^pKmS~Af5 zN)i$F^6;EVe0_oIv{e*-_?_gu`ZEcIxPM<Zw_dh$t=V?ry8k7vyQ8DI?YY7*G5pOB z19mJVCJsw17L+NCQE{JQR7)2w4ekj{ax2*LuI~UH3^Nj2R5Ru5fTkZ|s;hO=jKT6` zu|X5WpG+4xqSVsDtnwq7^hciehu~=#cyL%pn21SG4YDpBU;a=NTMJ#y+Y!wS5xqF= zhRS$^su>~Cs37Z{n~93w8bMtne3dvLrrNj87yl%vQqmxGYq5eqfwVZ_!dE+QkFKVz z*taqzb)Nn~2jmaRYxiO)=<>L1ij!6ruakL}?HX>P188byWgdB@>3aVdyNh0D{ZLxF z6W&J7c9Hcgocb|){+{PdVD^p@6JvBdsuY?Qfn$zvr_IgSzxUGvDu`=Uo;?q}Q|fj* zEO*<5)%%fY`arA3=U)WOHT>X6sm_-ag|>ycUJXGKd~r_}*PibT(6CA1JJq)ExD)V0 zPT!2Ne<|X7+*EJ6aV38+IeksC!?@fHDkijZt({HoYjyNVp@@`<^AIg$n(NVXZkmwy zArs7l(>`1D&71FckX44?g({tz;tsqA8$Ox)2Z2VM9a#q@#Wms;wj6l^=+Ew2x;(Bv z^%)4UaonM867)JH6UQgCmNX4myHYxsadpCGo@}SN^u-^~_xxYacitG_{Qr{*G|$^> z{k?qn*NNfG|C;<qm$q{w&hLa9ZrU8Her;&?HxEDVKX8-!TJS$w_npr+Ku_{&pMPcD zBCC-+#N+Al$NBZ7BCpts7cb%nKYpe2dW>@x@*m^C)d>f9B*`RDThA4*0=>HeVr_S< z^8|bJVAXx{tai5-Q?*~q{06JehoYN${_Hd@CFYeyF<rwWujh;>9i+KEy{lJ>fo56` zJ*1*Nw@t2#96AC)_FLnX6k{pJT^zgk+gAgnN$0H-fGS%Hdd)y<fW+dL9ty^Dlo=xO zdRP3a>L-kJHy{^MzXD@m;>sS@a@^<VRR5280z89v;?1sW1T8%=4!7?Di<qsCb}PAH z1-$_4kjrmz^{;aWIEAgE<4dmqPGRe0v2o^@o5!C^kC3u>T(C3FREVK!!3yl=@666$ z|L~KW5v6O{@D?eV))XKBx6}00T_Rx5qQ<g_*3=otWt4{<|4)C2t2m6a>1{FX%c2<s zBQe))fVOW3Da$6r{O8`8-(K&4?M+;(I-J5;d#-RY@?kp-oPYVK>>aowc;Zm+ko?PU z$v<u$e}CaMQ{=wgGef-|GvIU+Y^GiTH5iLxx%Ma-=tcF%eE;Q_b;@S%cemop8Q)^I z<;F&|w|!B!-~|lB0Z`F1iRj;%M%=2>dckwv%Ie0}lBO_&TBT%e67R%|^|~nYUf^n* zAAFAl7N0XRxFVO~4hvB%lDb-K|M88`pXA@NW)C}mO%a^FKZDTgE1%wqg7~J_7Qzc1 zRsL&T++;1+6p7>+7FG1wdD;7F7eVs&Wyr2c8^E(9BCkH80YtUmmi-^2yjQdLo$Aj* z{J+m>{zja@%?ZW0Uo9v9ScH!9^S6L3A86n3A8Y&%72=%X|7{=sJ~4l<{r`Xe$`X-- zY%%xB#Bu5T=|W;B+nqVHqE<^Ahgk%HxYVM(-P246n+XqBzHBO;+C)Lqh2IBGrLvlM zz5_kG<;#4VIaQFO3Dv3vy+SlUqx*V*-7dxk?Dl=YF5LXEriq^pWxt+vE67=)O?C^m zcF*zF2>cj%<-WN7YnuQaTdfKCC%-)x(02**d%Hx7LzcpLoA9`A#Sn`7brvtyC`k_+ zcewJNKq#^#gK!N5M2QqeUjmz52>xBNTi$+x?UuQI8oTp`h#aqIPG^H4UA0we3%Sos z^zmCFy4p6BQqno2MQQpz6H-=^{AGZpy9-ppy+-ic!~u&nKKl2-^0t!yJg`ih2NrPR z4<Q@R@wRczadYkn2*ssJ)Wh)M`zlLukFYHDApWK0LW$=R-XC23@-A&7B=J%|UB|AM zjK}W;tel__v1*~u5`DS|A)LF_a9G6qvl%AvdIyAOm$WUE;dsI{j8(zNleB8h<C~zt z#~UKrA02!v4}!UO-^0s0JFro~*LJfoD7|30(a8!*Y6;4g^2}0(KV~faI`1E$Oi1&V z&2OQs`8tcq0fKr)3U;ZTVOD2f*JH67!6ZM({26B^#7O+`zYj$w#^?uNS;V6r6wTK& zVfUhbxnDh={VeZbgnb#7XT)6q!Q5K_in8OT;6$-HPj`KWH+>8-3-LhVet@}cGh7<P zXLHNA$_|-F%lWE{D5RdEI8Z~R+Yu20%D93@6r+I8zfsdw<ZuD1tv(~h+e<xud*RyI zyTOWDwcFce6RV&}`KCJyve1WjnG^qbo_vq<%mzTg7bHDP86}4WGMGO?gn3;BHhf<k zJE&!><)BgPZT{=y(o<HLyRS41851D~JbR*70UBYx&`XT8g4o>_=pAoV>?!U``I1Y$ zH=M*b^am+PV3}{-FwonfMomZZ8z-n?HjUw7F*{YA4&*}voat)A3V*NWp(+R1p`(;Q zqOk>j3_7${K!M;$=CFxszRMpbv%S<OVoUkN@v=?G<1xgluMvG><qHQXES#R17KQq~ zG_v;>9;Tz{@}$`Qj1Kd>xEKZ?-s0TvvUV=E{uE5ZF3xs32N6>Du%$#&n%{o<C(Gg8 zL|5CvNW&_<BtMml_dMrDto1*>jQ08zoSKZTeh*E7u&sr-z8T7ZWZy}t?kI_x!aF=| zsOIpWNKvDp3;4E;2oYWNugTu!#vkcYvvgW40ukjZ&}4@OT-)1yUeOU7Pu;C=m67%K zN5lu_Vnw9&H%{ZiHCP&zW9-|;lIq7tXcRZ}d;e})ygE8Ux!)@t`)hAE+-uRzI^Prk ziy0|3`apz2(0HMOj1}*}1Par-tUSEK-w=Bd>2kpM!02a$({juj@?y4(=)i~7?290v zOZDhNBv0g}rJsAfBcvqe*!88y2S`Y#VDk`*7z&)>8at2Ulo#`49#DcY>@T-UdK(|t zF+`psUxCtM$y99LqETkhyd?JdtK3e$lc?8l#^pIua_p3bZ6Q2?(d?{z40GI)Gz|2y zKG#BU5o%!Q_j7DB$3c}I$x|i&)&Scm^SEr`<+Qr>k;6}DUu%RM9hL<>q3l)clzFUK za8|wXBBWyv(LBd2vT=e$8#}wcTl)&8EKkk?T4EfxCVjAsoe~nivA~@*{bpht0kNLT zqk=PYUeEvr_zskz!mrmRfdBnqimM7gS+?XLQ(%BKT2dp{MQHc>#1;yH;PC76mHX1A zs70@6$+z~GOhRk$*99`Vu{7;z)kf}TjYc#3^3aL)+4(`|j-?wJ+3IsV^ihb`gSxw? zK+~0vQ8hCPg;B2{TsjPZ`>?84+g`9Nd)M9I{^G8A50%NIqZxK}wyv=yF6c`eYP6T0 ztxYyz?CIs}TdDpfKdVzvi0UK<8)={eD82urgt=`Ld{*mQB{3%87hXfIc$6$0xsF0u z&MHP^*re|jiw=*1O!qb6YP!F{Z`{dWpnIO`ouB*`A6c+xVU^ePZULdO2qJ~N)>D9S zTSg<;s$FW!`%fGW4{s1;31Yo;E1pT6Ro{>=F}Zh$c%PG#72U2*7>lOMgZ?;(nTr6r zD>KiiX)L!}C5zOcQ6T@Nae$pj0{Sg<MXkpfvCnA#bpW@29{`X|7<DV-vWXzaA<X!_ zmOx|gxtKSrB6HFGdq2}PwqQJF%6uVMt5E-H>D)*JI5w1e_Swk}Vh82!-T4H`wbP(q z)&+MkRgyNw#B+i^9xW?367Jl{Ct7hha;QZ|T<mvOm51?Gy=D_>vL5Q>`s1*0oI1~x zX_lvhv*Vue)bL&&P-_^(xAxR`)@9v5aG75NUf>&y?A0&oGg3hcZk*5$bPDoyTSA-B zTwb9DGvHA=?QSzAC9L2`Hy+*1vugP-2IHYv7h6~vCDv^Bl!)tAdn4q|G2qQ||M}LB zW*k2mO{OZ3<=%zJ&7!PjHo8RTsX>Tnve*g#KL*7apK-ofL9Na$l6`C+{!*;o)CB3< zhUendd?6<lYCWXi@95`$mk|X?<se{1W0dE4!k+#g+TJ=U%C_wnR#6Zs0fC_fR8YE` z5lN+`rMtUxq`Oo?i2*@Cx}>|MhVC9<=<b;LF5`Zld+m3BYwh*L|1fc0#~kMozwn<{ zj{#=-B>0`c_=Pn4`sg<jm#*pNS<^Kw7I8NW+=~b9j#LI*t}#_>yh(sG<flU3BsfD@ z>G3p9EDlivXcT+LJ^#>)vCMSClQpfl!%w1&D_RK<3jrAc^tVpV#G1qVu)VNZycl6U zh0g(TV`vg7KcJW`^8cwVhE;z5eE&sRr+^a;64}G}dv<97-l4u?>A~>oPqXK{VG;EQ zB^&2vZneJ`%kG4pch3>&Lj&=Luws>;IEsy4FYiO2J2C;u|Ao8lx0@p;0iUj2TB|T? z+A<)$cSmNR>qDM98Yz06irYB-nr^c7@rGGH9v<3<!NOC*Q(*KPL1}&qF~lC9F8)V; zQE9z04FZ;KK5?r;{ZH`uQQGS9%8fv<#|*COcO#%UcHWeCb~}?+z9KL9cf6pbB4l<< z9n4!VIqF*Ey><zw`tI{RJiMT{6V_^_sZ*XOta)Ypsaw^v=ZLl|;<_UjVHXQ4HXQqR zVypOlGJlK7g2ur;&Pd+1FUCpr5Z${!uGrtc%{{z_y#o!NyP>)bHVk!CLe<~m|J;P> zDF_t6Z)Z7VRv76t{!|zKvje-I7Q`FH=$b~9i4E(InKIL2O4IceiT+jEe&P9dzc)s5 z43i74hp=pZOg8>UDg=nUzZvX*0h0U;$-hm-{|5yy01JZUK5(becVdVM!+!0B@t=|* zaFqJ@=Uho})86rhOSm6dbxqMIBZx6ez7n&h337WVd;fzhiYfSj4-|e6Xl+L3Z~yma zbMmKO{=9Tji+JfkL1+AFL6`)8%;CGX-sdW5Vpg7>*6U+_tcDS#H5J>Mtgw&2#w`|A z{{Q+6Xum%Lz^IlnQl^i|FXUb=19(HyzG*e0qEv99A3TIekIwpAZQGwDjvS!?zA~pT zSt-oq<1;`$^}pr9pO)trx}wm*IPDj@g6{K}cV|U<dbpx1$@6YR5OM>+l9@-ktI>TM z%L#n+zv-xf+KD-eLQqofBr3G%Wvy96SzUK)hi}7n+bN6#!0ERCV#WQ_n*E&y0RMwE zJ=wj#t=vyzN&3+xcPTgO$sp0tkcn&T|50;l1%J2I;djsFS8tm6?FcgZuK2m^)lI-{ zqvVK=>I(s&qG<nT+41Ym|CvIpK?4Z*NwNVgZ_)YMZPCHilbCbll=@dQnyg#@n}Y$a zNlJ&`*JR2yxd&<+C;Z5^ZTZs#_{|Z_8TRCtFztW7+TSsObq)D;g0Ln3_!WjxLuLtA z&ldHCG1<Wp7?$Dx4D(-s{Lk>?7ZH%A$Jd79N#f0jw^4Rf*sAG!mbwTgZS55k|CS3V z3FZj+<8O}aKUwSVJOT5#D4w70aeQ!m55G{hesX}5*OQ!WmgPo;LA4$%c9!XZp*UDK zKELIc|Dd^kf84*Hl(uE7QE;#s%Gu_lWYC%fD2&{@E>C(et^Vq|yschBLQ;<K!!Mlm z|MKi!Z@LR_^7WA>rwPc*)`UTiREmljzHNVm5g?;my@jMiKbrq5i~KXidE>rN@JBW9 ze{*L4zqXzKZ#rFI&PkVV99W{#h)uLXKP;K0HO*Yw`#8?k!cF9#V+kDP{ck?F?zp%1 zr#p?pW&@uRXlPjjz3G#>ZDFIdA=p~~q+qJ)%Jos?i_g!Q;#pZEW}k2<t~6I@876L& z4E`sUET(^7_5cvA*h>xQaJil&BQJudYKZ$9Y0UH3`N1ucf^x+h*r%x%AXF>cR1!#K z%uvtk)wGVlMbLCOk9ohC8dF87LEKZ@bocYBhnBCUL=o3cI`K@z2|bBW@iah;-SOS8 zuY#bp${t+!C$1h2r~i55|4Fv-Mi<E1{i-ws#Qq(jqOx?|1<enT(}@BjZvrkX<djbK zQ**HiA^8a5ANQm_)3Ea@&Yob7&crL99soj_djY}Sz6^)YpX6~QMC@O6Nj8(vf+Mai zH00{iVB(F07nD!|aMS7dBIAIRQ)&9%!Bxz;&e%4SNk%t)F0+frj0RAmS)+=@eeo|? z|NAo?zW&|5w^!A9{Giwfjkh_CHdH&3h_NmT^eL)<s6F6nZ<VZ;@e;AZ{z0Q}!)g^o zMEYGz6IJkqO)yv9OSCc{*Ss{p@Fc~Pr8k58qoHkjQa+)OyKof#ARujNqZq!(E$;fT zMvuIgRbm%^YV<yz^a?(M`GlpenQGa`Ztizv5IV>3?#`vxVE{gh)_cSK+Lz=}Rh~y< zw+yXTn09=ns;xNEgQXHxN?Y7E{|gcL_oVxye%DPvu8^X`0L13-T}f}7%piI$5sLX* z{*cNprF_wvqw6r1;WJon-*?8`;oQ4V=UW!yrnu@k#mAJr(TLgzp<4b$z1IyizyVvv z4V2VLz1ekB?F^ND=z-N{-sJp+p$sFO(CJx0_R&=ut@0v&{Fus#wMDyi2$=e19}G}V z*UsKrpbVdR4)mglqHd@sjz!XTKQ#}gYS*aa%G~egMP=$DB7~kCKEghQ)KlMtDd-W` z;El0#?k^%rX$P39!e<#Ad9iowJQGN16T|DD9X?pAeOTC_y+TLVS!niEH+4&CtT_-6 z{RW+1DK+IG-sYae#C^G2kqRq5ae@Jcz7hecH!c;@3itPi*iiD5Pic$8`!fIHF@Yb$ z7mVLOtVu_89Gd}6L%Ozd1#S|<ZB4O$mv7rn_img%4KsIuwT@OAa>2b0n@G(qMDsf_ z;uQ;HjR>rxPQoi74DtK+XZM0!0sqx2!_kB7$8-YJ@Dw)^O-*Bt$lX0!7g|JU!4t>( zT*W|pI&qSl^ikq6l!EopUv)<%GF>eo*M~ZO586b)e@g~Jwxbt1O6~NxN>weqH$~_D zT{>`Esi2Gy=2v%c+)hTjofz&z)frHniMTuoDZOKEw*YN#7<R{t>vW?OiF%Cwy3bSt z4UC)H@q=Ip`c*?ycW`Z5R7sp3Pw*F1aDpCg0~i$Sp~EC^aRg0oOa)_vRS*KQka&fv zs&mo5s1tu<CyW2L?FoQ4`G=zO>lUOFmmyhuzV{=5W%UGa2Q1c!@NBz2?^?f9$<eE+ zH5^U;LT8FZ@U?xAS-5-gWxM}j<zrdaW#}CKBL17Xyqt6N@KO=Uphlk$nyBmeZv2um zDWmp1+BlRbYtu7Fs;uJ<VD;LeO@BxtJ=aAx4o1nWV23UUW`sf~Y%g@N@qCF6PoES_ zw<YOD5x<ZUmRPwP_hT_v2M}R03X?L5JWhT%1PO6>yE(#M-z}6FnAj+=3t8Sx8w4vf ze`RgI%=4Uo835sUYa>Wl{QjluJ7iY(49LJ2o!AYdwK1g2_l~6}XPlN|o9uQYHT&a~ z|6WQKxW5zDA901H@S{Cq=bTTAP{xnv{0bg7ZHx(GPt9ZjpTrt+qwGvYNY*w~?uO!V zI^B(vuV)3sHJjuJW-8pls~Ac2U>|lt#tCfa=`4=qyX6i7*l(<`t0`~A2~tm&13mZ) ztFF(q`EA*a9|r+#dJmyIC3(rB7~9gDBcZr_cEbzD>UA%JVBYrTMTpUm`eV`#Df5{x zNyySt-7~}e{S2TN0L4YqqTW-eDbN3Kbe?4@^XpzJX|(L|q9rkC1MF`nLb2OSJ?^8W zp<d?UoJ5cxRRaX0nU_QPF(PgAns}!(I9J#kaw(K&6t1x~zZ7NuM?C!1XkfQMMukr! z!dDkU$3L<k*#*{_@pdL#3XsHGB5@dB|ImAx!vT0)#~xlg(UjlUElDbZ01^=i-CV+J zuFohAUumr3#nu|QVISz|^Yu|Ly~AiDfM70dkB*>)pR;2VG?Kh#<H0?I0?iR4mqqM= zDElMYDmiP^HD`jafUfy@T=%cp&WD3;aUZ&QBX<nlKDP>K2xtx(H3cTtR5d2SPC@cs zJFzA$#RMdLlk|i}WKj^tl8VW(?%V_@mwb04uDSJEW?mv_!2sX3uOFo93kufAPd(vy zR`mYlhEfg?Qv2tkl>VnLckR{vk+OXgAh95m^y%<2<hwfEBj>Vfm<K84`704SHMsU5 z&htw|Z0UICvKX;3!lqKoT2}rOYHEhZ3#~(wUO@!EL2?5DIlY+2?`CC3o9BpwxNd3U zaHn7eU1i1z0<@o9zd(W*QePKZaR*scz2XXK=tAm#XY-8Gj2{SB7$<)Az8I3?tp>J# zD34YWfY$J%8K-ZFUBFY<j)ovf*H9+)Z}*`Oy9GnF!;GhG`<~KL#!h86Eg`O2VAL-T zaZdleiugTZEnT(Mcf@IWg-bBl^0szT3sWYe9=SxAY4AYc;0mLGG%^Y#IMiA1@%;j! zcvC-VW`BcqD34=XYGx_zYqPhKM9wh&&Lc!AnYf;ISp*;8P-+@8(k)1Ery%INS>qT` zl4dLYe77)ZB>_4O%&YL1(F2enP=p@T0e<QLw`7L>?&XU}1uE9EnDP#ZMhUftIYDSc z-3yUZgcpc~IH^l_(4thNoXQtq=LIPpRF4(DGB%!{r)aBb8ooX8wV!;WZ_LzVRC@d$ z6bcZpTu#5g8s@RB$edFPj~3wri?4GQx7j82B~FfVfd^Np9?<6i@SM2rPY=-HGl-K9 zfJ5qISr;6g6y2NAIZUy2JiNHdQ#aeFfjh86yENFPPib`G3S;5rZm3*b=DA_$pac$} zJlU1BLMWd1*upOGb&+3?2&urCr?Bk>mx@<0d-FMO!E`vSmw|+D7%%dID>Ac@GFiq3 z3X5AdQnW@DtX<;BTo)TuDl{u1lnt^}SA;=iK96`($qP(*r5qs9k%M)MltJKs-{ybT z6SOVKi9e~XO{aizT3q&K9iaqt7cXP17}poi@W_<>h9}h(6se4QTO@JcRCcO|RMMZ; zVg!?GJ+&5H^EO~UwT)h6=zT}B@Y3P_BsFiJe6MuZA?#?0-z~&4Es|va23N}~y88_X zd=2<lm>C@JVSCpGr{x2#a34zLz1}Ss1|hx*m$T=3an>{Jds4!$IUf8>SQtHOjG-Cv zVe`IJpPb{nfEI^r3*XsMk-RiDe!M|21J19R4>;CcKY<CyM#Ir4FKC0c@}p3-xN7Ce zX%|*;bK;UlR}cX4_&3=Ea)Ez8!9Odj3!@QbjLy*rUn*5yU~|x*yYvx&+`Er}?>0%n zEJejG5V@kQLG_^9SPxzwQ{<4&cdy@_${=T8L7IMxyCiKtghj;8PigiFD@F(26(Mfg z3p-ow|8ad}joqFabGzBHC`@s1jbYvM1eP~@|Ed9<Kr{DL8{?v$=u<(s2gz&xffgyi zJh{8Zd<?(aB*XCQP5FyreMvJpJV_gpMFqr}iP4prN%CHoBBH#6eav;9aFvv<yo<Nn zu%Woyb+9+*u?DkqZ5*U+%3R&({0vM}nwo@#zYpLY{^^j1g??9<Dk`^fWC6@rg!ua5 zO4^rCGV@?P#xl$@0dG=UsV4E}>`tr)@d7*;v$`R&LvG}msZHXR5pwJa=W<UX>;s@9 z&m*9v3EcDiLgBL}qnvsxPu=19AI=eo6I#pTPazpL3f$RD!4s+POGfmq&R%B6sYj{S z>8=#hx`p>)>Ww!^%y(J}XgRuMG1iE$+y-a{MWGY#xZhv!#8J|O%<a^J+s|X>7w@_A z!wn=SEeD4Pqt5V<)L)!~@yn@#U7P+jOXb4*{q+9s0DEbVVV`M%@}{eM9_nAlRcC^K zC#B?bt@mv)t7jByC)ehq<<j(xN%>BiN$4l!kFItCU4<dEz3ue03r`PVScMYT*df<H z+%h2gVGH_~6xCD3={+cHyBHm0`-1_Al@MC!@=dVioKdCb>cRQ#jWRG-<q?IEba_qn z#o(3gB!<Sikjf#r{hCDXvNQDay^b5k|8eyH9p$XtIC*FG4s$*D*WXb5emwvEn?W$| z$Un%fU+D(p-(UB4BiLW@uf=@-AHS!6wVzI$%>V6ArJeqm8~t5;4v&7<Vu~P<(ZNB2 z7_s&d1*Hd!zgLSvXCtLtA35fx&Q3<3|7S7qf%NyA|76~)p1z2{>MN!+3z1FLdeW@d zyIiCEk+&VtNgkI?TB4kqN&)tH<)<)i%oo7x#i{ZW{Twdn0lLhS5&HkW9Oa*v!!CxA zVSI;!XsEzCqW4l=@$#8C*H%}ui<wg3I9~!bux^f6j^$Da72}oH&Jm0QDd{VBI6q7f zhDgxVU=x$FW3?$$eJXM7Ncz#txmZ*51f{L2dJ&BOPc;!3`)8l=<e=^yd2+V9woTzi z)DIt5vBM*Gv(I~}j~*%$0DS5mK;F*DByP#8_XsBcIdPDZ@rR%SiXTSMO7z4FS(80L zm*OPg>GwpsDFY}I{%9$Xi5Z84I`c~Ytn7dWM7_UFJ172*Y|N!gyH`BAaK|>P!-aU7 z8pk|7ef0?;U!Ao_+&pb+gK&!h=J98f!QyGMk;KmREzxx$ky`Yq5ncJLDBbZ}$HaO; zfB?f_P(so1blj!sYiFt)EEmj8u#J5+=so<k>L43(>3r1Zy=fO;gUMq7$*uh){B>|I z{Gm7*olXIz07!6D2#3ERU-%jBfh2AV{<D2LJv`FTlB696Pg4atUFHUG0@1kX81!mU zBX6CeLf5B$%cQIN#QC|66%Sb8-p;NlUwN*wf`YZe5!>=GnSs20NV;bV)tI{R_mv%o zQ+?La?-~U0#}ceMt)ZoEK6*w?GwgZ7JB23q#@mi8WCgyqiQ6Hb9@y1s4<49#h)+{b zQF5%2zG2Q+KQHt2C|-$Rv3gE%GuoknWpv4rOJ9OYI&t2g*R1|VE#JkQRWmX_t!z2s z(sf{l=|i+b6)pP?j&i;wf7exb)3U~>^|az8YQth@mWB`8_5NkItv5+#t1I6bPHRWn zUNF17uuPD%`VYA;9w<#>a{H1q`#D@?wTBx9I_gy&uH=DYetXe%l-V;kIUk8KixS2X z?4sIU=^1Id3g;bnA>VPFmPy~l{X+MI*|{;>P`u~(Isb{=QpD)X7k$!=SaC{BfUT}d zyb2}h=X_Q}=8@s{1`yuGNv`V7YXTiDy7<UwfwWFpn8q++M{o9q6Lc|OtU^->yMA-8 zINsg`Gdh9>u)>$lk4Whj<>SyCFqeR?%853F+-Zu!aFy1T*fYPIxH^v}3JbA}cn}vM zjx;cTDPg63hw`~2maoH<s4-d3Z8e+BfJ2p-HkXKWui2-E4?KGx8Ws77&lA+3aewTT zAc@10U?H69^m>A?-Ba|wEvS4%op_3yA?iZ#+?iK6g7PS@`-XM~-YHcoqbO{bL2fs% zXeIZew{jfUWgtvFyuiGjPbw!4*dGen1vbQt%uc4qc&~EDg-DEtPf+D>HZeNZ;uk0Q z)^%Ta_Kb_lcqpup#T7dDsj0npLN>fJCIXH#QVTZz)ONtMYi%6eo6;<|!Cq?H{!6zD zt>9AQj1)MKzlA*1I+)629I%VK8^=vhX{J1?%v@Gf*{>t6MpT2}P!SaE!D>Ds7%?Lc z`w>QTBy>lTtan-?izh2>C%IuJ>}N2oooCfNc3jw`4@;^&F?j&mz}394BR}q=Qz=u2 zO~@TVVO&d1geK8Ivy#J3dd#+ojj2jCx_suyp!AVJ&kzuJ)U_vkfCO1f*d%T>evZ-1 zcOKr92Gmy<Q4UHHFyrE@?wW74q+Or=#_JmnAfD9ncj-za`aM&;@{`4R-b|+9^0}l1 zjpTaRyWb8GMZ9#&K8c$<w~2fpwRkzZ0VeUXBg73;f`KK}q<G8Go`r2&2xVEN0l3D> z?vL{`(0I00rMQoUS7j~LbjiVt^Ck_{g`qWl%-1jcd5=0}yXuqI5mr798X#83JSt_b zJE-$hWG!WtyUs(-*>Ddc!A~ShIAVXhg&$mw+n`?Ft1dxxX>iONAVd>xp;D4xMD&f4 znw%p_Jm~I!YH(^@E$OX4?0jO@2~Lz70CuxII+L=U@%zTJCn|0Cb^Nf>GTikyQ<#2J z(S+rB3HR%q{Ab7~q{GW4HrcMeEJX-mk#F#iW+u1@7JYdpMi<*Dp`Z=rn@Et-h`~!} zb=kY1#mhk5k33e~J^+SbZ8qu(d!ZbNx0}4$tMl)*vbOBM0}JRD&-EauutNwf^-DLm zAtHf@bCTM@+c-bQv)(dAHF#HbvsXuRJJ`xhknocve$R)`=aF@6SX0C2PjzQ8DD~Gr zwe6dHN^~gC_P1+IofDtUe2)9WFfZeQTeP>OWLcki9M~b<K3W3tvO&Isvj3nOUzsl_ zOGbRRWhCEHXQ0JrguNtG5PqJSEeO!$vbUb+e04jCnV>?XoC|(AP#6AI*UjMEF?0L~ zF?*@!KJZ%7YoN95Q@l%G+I*6ged~?lO8b6Nv!^tdAUtnJF4InSuxj3mMxSE9Fvmzb z4G*#C^uV7tI2}p7S%VX=&3t&@bLe|X*TK~7D`#5oOpc#AGzV$^=-O|)t}!K?l1mp- z%R;&>J&Sf4*wvRvd#npW$;(r_sYOq=E!tzvD<54D;fc}1V;zY+d!?$Wbj9|H4crG@ zFoJDTtgI1M`_4v>g=P+tzLC}W5}%GbRZkX4_9=<ZvBuI=dq2<~C#}}zO>_~)eO~Tx zW5;4uUDVIdx`**oI|L3>G}1ontY+ntnK<$*GAj_tr-~}yG^IVtAl=)qGy^nJv=XWg zl5ase=2pBW^^A_2HnG;_F^sGPF|NA?e{9oh=IfgY)0NT5voDaIX#2HwU`$e4-Scsy zi@ZIVQw49ejx22|dPN?b(N=eLBf#XqqkVR-)7Opq14~T6FgfkQ;{D1m29dm6n>9T3 zX(#M^ve-Nzs|qtNs%)+!1PKZJ7Lt=^qU_vmletU~`F%l@TBGy+Zq&!Q-pMqW(bi`p zxYR2h@6a0&Twe3D#ph#B-9L@XcX_iM-jb)FbjY2;OI%M3yVlv8;&zBYj4K!R`tn75 z$I!5HHySNV!L|R6FZLILWnGh><uE`>PMY?Y4v6VO_!5?C857L%8Q4ymV4lJTZd+x< z-LEycIr^Gz4de7jmmtUb{_<61_UbR}#hhz@$Im%Rk1;ei+5F{1TM$ABXBq+0R;cVy zUH`2?YF?e1gsj0$WVh{0&^WH*`{)W^HP198-Tt9fs&%EmD5p0o>(aI-2p<VM&yLsc zp*kO_nYp1Np-T2_;&%1##@qk7wZ1emunpd%DF9TwLA72CfHyX;2<uXd@QqVuCa0~v zZ5xcpUNrwQrsuj`SW;?Xld`+^>8?Nha&T{#0pBgXaB|{~>}nNXy$1^q_(#KOqEd%w zQ7v-^43U!*xB3tBeTDKSsU+9sDcH3W#Cbs$s?}l0=uU^HKj;Az6D98)1gGH6c9@n7 zQTg5Rtw%x`UfB88U9rQHr1R&V+io4T)s(*Et`duo-R6etJORAUmpAn;Sk;Xo;^QO8 z3r}JBAJmsIBb?M-L@M5i<O|>h{q{*~yY`Bg<uMYd&n%9yR5O4`G)`<FGl4bd+m{yz ztwGXv%db}L;~+*5%It;(hROJ=(p5P^K7x?P3le+M+Ug2zE{>RcVe=0cn%r-l4p%r? z8SdxVX<9vYB&&5uKb@jTG++(&4#FzbDWvZRA7g)@9u;T1cO!j)m|?Si+<4DMgaPG^ zvD>6#T7!R{=uJuTQ*|=N4el|1d4E01Nz{(w0Z;3XvxX8#<|1^jomX#~Mjt$@Ashm^ zKG)=vT(%0vgU>{)Y3Cc@+cdN=k{KnVah_h|Bmy#z-hO6ISLp{lbc-`P?8AV5<s3*^ zj&q~!1g35!Q;*N$X0@-f{Gb@(3jPux){g94WCv7+TzVVqOSv#6nCamZ07Pz{^vZz? zSxntg1CzKgQ&rFq!C8gI3$F*7?1X>OYn6~ci>;CV_Geq*Qs-&zRCu!4>@R@ZJBXk4 zt$*T?n*KWHuUaJmkf+Q}+=9Biz(Zl-&}mZaLU$ewa=u6mugQf}_C}^J9{>D}Mu_Wk zTSD*Z7n*uNfB9`+2BJM&AJ`kI>fmqX7ZEGBZ__x%$NL;u5~ez+UNgx{VjPZ+<gSM| zKz^LUl9$Ua474YiaAdssccm_As>xY=i#kC`Qc5gGx)EQHn%`nXC}4bP?Jm)WFzRK= zy;rluE@G?dnSyg-sM-4)p@NxK6_EM+<Eu2Yl~r9f6RYk6CTn)DSD@;mu#_PAuK?%3 zGm_`J{AEq<Rkj%$k1Svlp4c2p31yCxy)^rwTerx9)V!X!+Zjtxa&z<$`=JjOrKG)S z4Pf6f#%_xA#U>;YQfheg#S^C&T-B*w+xQ;E{~T}$;6`usjgGUU-|}3C_I4qlT4LzF zk@-l@irZ8~%g`D4!<CtUlNBghqUtD^I#Qg}Y!PB05Zr;j=9CU$A)NuU#zcH3tv=pC z=XPV>tsI}o<k)TDwl||NU}?!A*92bwS!2M_00_QT#9)B*cz(Sh_~y|GEc1Yyi#z@D zwe(su7soN|n*+P;7b@{HzWaJubA(-A%N@{b08Z7I)EH>=;F0SrI8wm}a4HGzZwfpZ zCfPEkEP{w&)Bg~3kkx|KZOQDz3Kfqc*4+~gC&|C7|L&*&$*8Re9L*H!j&1p{Ehv_S zzyso10$jktR!#HkuQ{>D9<}VJYfV73_Q4l3iIHD$kJVi>RyN(J6{GtDqOirZ4k1?T zApL8C=v<6}$KNi@THZf!!EsVj443$zDPR=Z@ogOq%^q6hXq6JsyXIuC<a{^H)~%hg z$5<P)7z4*00~m9%hFx`n^JmGN6n`#MKzs>yO~R1`2Rr-nUdvmEV^~!5>7?5xx+TbX zAO}?HgfGx%F<H~)iJ{$b3}d!mYCx-<N?s2KM7grN%=gX_M6m~pTFxJsUHUE`K30Ic zZZOS$xADg}v<Y~@v;e+xG}I1UXkxOvK6*KO;Dbk5;i8EB90v->jzRb^&sx<DdQPif z)>7(eAO+KEP*|AWcg?D{oGo#o5UTfk5jXF(kUJkLq%IJ=Q7Ir2!yJejz>JL9D~I4+ zln8f$)q%g;4JntUEOK=nX1#cKFC=rL+L<5kHbg4xW?!b~6vjyB*XNwV5W&LO3a;vq zYvC)H_T)3xiSou3yf+3IxN-p6a9nARwL|JUXK0M7n!BT3OS_lxaLD-tM2`}+g%x*^ z+5o{RNYZz;obG^^R@=#2C1yYCMd9T{f$nD=RIZ?(y?P%ti>{6|qgyOCZ(EgaD|1s6 z{u4fN@-6J%97r66u7}Y+_GivPr?A3<pwy8;Ql2)#D4BzM)JNGr5zxdomaAJ`Uww{` zuz-2nqWLKWRmZO3>otPwBge}fW;{~<udn}hKY%=PHs3FKWOg-VREhK8D&zXE%kca4 zxtZPb7VNH{O-h<a1?KNAcsKJL&opxa!A=y>NB)=LQ62^*Lh=gGrHxa|YBmOd5!<;s z&XqEH8Q-9m)w2FRxfqMxSJ$NV`X0-=qjtOedx81eEVbabALLt@Ym&9#PTKG4#F*rp zeR^<0wF%GU+(hBqky{#oTWK4U9sHFE<cVj)-70lnU@r1%+K}RkPdl^-Pq^&ibG2v9 z{Cb$Bl@Vuyj{xd#ht0HZ^#Y2%sC40^F>_zBeKtG^|FU5Q?M-bzJ*feg_O9`D83!&_ z)nWv}6+As-J*0e040P}2d85B4DXyHAhTT%!n{xz;#$k}+#x^x(|El<xM3{C<V=Xmq z06*_of7*V?3)81U8+D}c7kC_L-MLA1v|BVox!16>uWgad_@>x^KSdWwnK<O<jfHnb zj)>$O-hv}l5#&@9Lm7FYn-V6ezl_7zMVYprCwYN@vbnxHfokR=NP58wAtr^nXIGE+ z+$C0_WA6$=ZTaz2QPL^V{ns#CS$*LrWUEl>R>h_GA+b(4O-CtTIYa&eVX`NO>#7;Z z-<NsdjTL;l(+t^r3==LXn29pc3CYx3ETg@4;-$c}d#OAF*YLbwyUM<P(U?O8D1<-i zYs?$!T8`<qnPxx<5s|Rv!^79Pp2+&%)yYM3oqa7`SHVbuB<cQo#1wt>f_t!~I+7Hy zDgxp1<!8F-1i>f2UkV4aZ{P;_l<$IB7pqH2h6RtuyQmZI15w`@r5!<MtllR`_UuAs zR{HYNKnZotM|E0ga13QBoyf&>Vn6J?p}g7>(_V<~Dm7=Ur&@im0~Lfbxjx0kYEV3V zDJ4K&C%L1%3Wc^;bxJNfyOO4nsK9*-e?(tsH@!Pkr{Jo6r}OFpk)sHEH>uaA6fh+` zKFBUbC&|2}<IU?TT@KrryY+jk1|U=Pt0=M(G8e!gjTo5GFWziHS>P|qjN=I6IhM9O z60vf(XP!TS!uI?Cb_`pJ02IgHRCM@KMBpDv!Tqj!yOSIkcg>*f_h7Z|%?(tootY#x zHQc7ld2qYhN<#Z4Av|@yy*44ekmU7MwostjU}PtND|siMSZJ3~0oR?mMU+_A)Z_&H zvgPShP^F-O9aTW6?t)h){tgrsaXSPGuiPTk9u$cr7dUHn$;IbXZgRV#g1hi%4Y5ye zc`dvLtYQzlC~YUmeDohX3hx9N4W(9xe2JFD5&<~aB31PwWEYha;46v~tB1H-AfS&Z zoOq%U<k#uBL#hIMWcNFGbQZ2K2SgOM=yUFLIa1(0AB&~u)Hlsu)OKYZ5QVhaG#<ii zh3%Fzg)`m|%qcRWyrHL)bg|w>c#&PF7iJ?$O}8bC)+8tA$&a4N4(Tf1w)Of1@CHd$ z2heRy8GyZ6<r2o^fE)apdvtQ3(4KfJrZ;2m*sBWK!aZCwUd7gP{L7|yq*nlz#|Ciu z^u6!BUUiy$#OTgQ_28=38Hf+g##@JeyWtA@k8cC#f-t)B4y7lde#sisSw8gi0MF|o z?l#GiqnkkG66gKud+K~Mi?kk(uFJJxT9f6Q7b?k5E+Fr|qK*U3=I@a?5k!Y5e7!C5 zlVS;awfuGWjki-J=OqmNlA$7m`%7&u#C5{znVO9NIw&^6p`FS<e|<{Y;NVtcVfp6? zFlz{EnK4#6ha4B*3U0b%yEnPUFRhJ=-v!4k`g;&jq$dorL$^4G?razP6kxmttQ}AK z+T&p#=lA3amZChc5F>5--g(RmURtPsA`lQsN0#=9-kIiQ9t2}VY-Iu1x)(AfkTjYI z;@)Km&xd7u3LO+yoewS${G!EV*qqHcpHVeRzY+Q9ruFP9eHce}v25>_A6#HNU*xmT z9^-0D&%PHO0?y~GJsyEu4R^;EJIPa`5>;@g${ct^udm&OweRO<m^Cg|?e|t)5wJt{ z$JjNavF7nyTv&&aGry4O#B@h(xNpx24zk;}+HBV)Ri~V(@lJzTTP05VYhx%Q*qq*P zWvKN%cUK#(6H)&-%9yz{r5k{q64*BI(Z0#gtm2e!t{~(V_loI<_|QxPK<UrXIVD`m z@g~aibd>$9g|jd4?j$TZ+7uS+iT-Kya4qZ*X7{Q<HIo8QZ21&gG`S6?eff0R{eIn{ z^K95cRQETaXdt}WdL~5UgS*VI(HIIvT`<#0by<MycqVhryeKoLl_Sb`THJk?zFs>y z|Bma0miZdYrux8-N{c)ydofxVl-qZ-hlTv5N2UNZZnQ)fk;~0T+EvND;rlQv{iw9A z!P%ohUR%kv&%FNr5toQ}DYGyM;T)st)=&<$!si*+M_$$IlmR<V1oE`DC`~d{4s`i$ z4uOMEE^C&RzM;C`040zIsa)6lC*|yx3C!KU<0xZtjkmVVmR7I$J_sIE>B2{9K3_#R zQ^i<Pj5M|mt<lPGket9cOM8r>kZtT}{{1IpESRnxaVu7{p*G=Brk9A8>Ogm5Hv<xV z^5`y|8NpBoCqbAWj_<>k;$_IG@t&(1@&fakPN6wY6ku)izyDQI_vM~mk-FQK0sE2Q zXr*4ydpD<#c1MB%kY;lK2Y~){Wc+CK5B)3Ev}66gG7pA|3c!0U=`p-A<L)>ce#uQS zjjd(gq*3w;sac`mn#jYtvKr9&fl)t$ya#aJS>@d?D2@L<NQ*+YAROXK@Tnpz$MhmC z{T8&w5LXzg!gJ@y7Rdnz(909hr{0?Cks9KOW>o7QGaK^4Uii3!iF(;^O-Sgaoy7`d z9$j5=#G%70e%GZ4qWi#OpQWv1zo+^Yz%U-A@XvUpkUo=(bi%Ryv9@`g|I35T+}3RE zR|7D90j&zLuEE0yCohfAAsoi7l1`0`YZJDgRg^b1vHRKzC?o@@#J%@djb8RS9#~}o zl~smGs2XF}%6YJPIa(1Tv`y};rn*pV!36n8U8;wm4zNOR=eOcW!<vnz&+_}OOqZZK zb%wVaSp0bw{V6wT{zhfU1+>>pCKcsjW<Hs$Ke^j{K9B3USK+s^VJ#%H6E3q$Zy#4) zG*J`(E4+Ttyzs`1neQ_Rx<H(oqqfGmXJn5r>ev+9y;-zJ!3&+&Fq-QzPeAQI*uI1n zUc!dn1?@fH+eV`x9+ewm0N#byIm60;M0I*4`gP~0%HWD^!^khY{vS62)+dwQ_l8;l zX1h5oG8TChdr}zt75VuBiso>0)MH=I3Jj9bki`H#1ve)qC*ZV$9w0Cb9!PFp!@TsJ zk4@}b&z7CXUqdM+H_z~D+3gmyt(ECa`=4AuRfQ7`HP4n*#=^|LUef=L80q~@+5Ts~ z7TWIL^fhD^#qVu9jU2-|^vFQxwk<)T?D6}sYz5ceNJFQ7#@C{(4?L>Uzt@pxK;|=E zxXq(*5oc&@0<U!L{OH&dUJSu&f4ymxvM9M8!_xXwra|;&+$cET^R#Ph``08y=0kR* zabN&@o@m3Qxz%w(-M#`3Nx=7MF_M^;v5tikl5o|jyCfBOOSnY<NoOmQ{u-^y5xOYj z%}9={xyO=|*u{C{3Um|D1{YKfx$x4h+5CYvjc9f?fDC!S{_YA9<zPGsYRWI~lcp>u zz@<wj3wVdIEPcXa>ow!y1TyUh+l34EG_~-1M?k`V6o4)f9{}h1s&@5;MzP|_I{}C; zxb+Fn2l0#RBjR^W+L1|Ek3n!{2UPvNfmZURFFRh>*AcuZ&KoEGYNUq@1%&54)iudV z-=!x6r#=0WIVy6nVM$l_z5l7s8IXZ67Mp*>mlmwXGTNaxg32P@G=aWQPUWy#KHN5; zjwbc=)K@bASz`>y2fIA}*d!4$MM{o(tIa*ORAa2(9yyG>fL5pIlDHY`Ey{Aec>N%K zHICMooWXERHKF4bwDoyGQxyuRW>l4aW>zmBo<Lv6Mq$vlL|_4?Le<C`O4kuZXLKk; zmlO`6YNa~Zi6D=a*;MrIpE`jFE{2;hdna1*81jsxMvEZxx4Dahmdy6xrQ6R0p2b1t z@lPV#0sjy-YyFRbF;=fJf8S;w1axDBaAlGVJU16X(4Q;|!ie8PhnFY{rgy5u(QKm3 z@yD=bxq?!@pOIJ_P$#5^yXvm4J4d4#?>$5u`z51%$THUuvEHHpE>yl{XABf52R!!q zPSy6Q$y+d*?CEm>L?a*CivbS9&c$cDR4I8ZE0oTeCJNf*D1Y4{ysOIxpp4Jei{D#~ zB6{ulSFR+zS!Wf&8DPhoBLRW(uEyGl)Nrq=vn6OpULdkYsho~V?3x_Ldijb-_ZH(J zO-hDgmPp#HABKUQp?>G*$&Df-z);Tz5b1PK6o~GEO7@!XK&4vpTtYBax}uKQ4$C>S z26rYm)HhOnF>M3wBrWeze_vV1?ZiBGUndLNNJxC2H7!~^p>ZF|A_{n$c=E7*Kj@F; zLwXnq-CW}@@aa;GuNrG_`P`XWKLQ3Pu%d_0EFn6fGT*<oZSg*5Mg_m1Z$A89Q^`x= zf~8W%UDhG*=T8-;T%HPPD>RcK+i(ZM3`@I8Wyyc#wlzY=fqjHXU{|tT8!cZuip2pd z8Z4z{TLQp&I9xp!%c4uM&5|JV_a>|p4V=Hml!8n>;?FX_BB%PAGQyo47ZUc!A`npZ zE|<fqYG+L%H)D(?tq`aEYZ*!nNefgxcWwW$yRirT<<b~Pv_ZE16k8NlBLSf<B%4^_ z%}lX=dIbo+&TJsd{Zvt(`4V)uZWxr1QI>NMSL;)|X_uSwFc{db@GQtD%!?!Ksa!MQ z<S~y68>-dsUHJN=xf2w%c4@|IYNP#TE{YHuUV3DwvQ@xQw~2&bB6gN?1>s(#yjE=` zug|w~r6vBL7XDC108emWtDKiNo8jv;+uUgE&5n2~OrXk6;feUQR%6uZ%n;Sv_n@re z(b`H9D|m0g$ICqNJ|9?dWeey`9(eXNR)0$coSBQNyZKe|9C^OCO2Hjer|_sYp3c(N zC@`XnvB`J!S6{A*ACzNzZtzz>rH_h>VjH}9Ds=RAJD8r#ZHc6#NVJPsP!jM@J=r(e zAy9#N@s&|3>1|1ECfW=U%5$cPAGf(Th1lPp#(lm%(ZSw+El}dQuuvpw@pYm_)Iw;! z5I%e-j*hmMZT6E*fWcS}dFH45!O9tjH>%c@qj(EaRC$EJN-dVh40LiV8bICr(+xw& zbLK@o)s^DwJ5v<oJKNofJVnvSeTv;>qGW@jD+i*Az_ddV7Sq|Gfd-mydo68cscgcv zsL1Bj^K41s-LnPtpyqmQ!6i9|(J}zHxX$*%l(0R;DAH9Iw{y)lw^e5_l}C~qs{kSE zOUg_|zU;9MGOBP=(7urEq%n7+h*lGCO&~MEYVsTExFXH`q@%L$p7KFfxK29~IdTtN zyw4)ju(x*$yX}-&=3Y#f;%#N$-Jtxkx%z+<BCpLhxMyek(t1iB6_gW&#e%yd!b2ym z#w#}7n)x%rp5~D$9HWg(B#6=Gn}?Jk(=na9^t6(~XFpHL4bNJ*u`|{OcvSEn^E4!n zZTo_jsdr9!(+3i=oT)Y+jMF+2bx?iIi&3{5sdU%N9fQA)`a9BSbI`9gjgYCMK|tQj z73Cq?gqzLpbf?JA%Y&XJ2-PKK@1+W~PC@4}REGVH4f7<)%OyuoqS1HF5if-L>#0WY z+P4|M(rX(;x~lcoHiwe>WkxkL>9&h8K1~RrTYHn4_U&NO_Kv{3D5zWR?<(OxsEc1( z8LjbRV2Y!;t=Np}Sr<UUnwW(17eruu0=+I|_QP41s)I(~;}l^Zb?z+uC0D953A?#t zUp+G6EQ~j1TfS;Oqa?zG+(l1RpYGm7yulN>&%Q}=Rq8HtJgi$Pl^9nrq;v*N^L#_Z zqKE;)W6JZ7W_ImkJB|%ywFn;L<U3t|{DHexAMcb)Mbc_}-S2XA<V};Sedt+x#hupe z;=ugH#(A$99#EOdf@=Tqd``>*O9h$h`33jB>8C5FkWhz5I~0w&X!g}sK}jW^eEtm2 zQcF5KCGtwXIiob^1t(snBzd1ytIHLZCZn(4xTuyQISGx-1r3^#Pnf=wm(=t8eDTb_ z>5OX{o}UwM3wt?t1W2$#IV<@`@G(BFMq0xP_wnWzCI@z$JK2uTIq#=-sYSo2W|e=v z#sVVDL|LnMmdSF@5m~7aamlFrxN|i<Tj0r}5}h236{)1?nuM2d-i77SmT~2)zsBv1 ze=B2DL}cHn!I71gupV+#a#m-^<}`#X7d&;}OGl2(b>H9l>VHMnugF9>4@nrm$uWxb zyc^QkLUWVjRt}M@WQs;K&LD`-n|7nE-X}~hHVoa~1{|3i*8?@tmzpN~n`a3~Kt826 zbq212+4r(p%{nHptQbsH<bG^v4r{2L?X%vA4gU>ce*H`8_pdq6Z#Zk<5W(5nSlp`f ztS~-7cXY?40{89+Cguv1{Ss#R{6~~A6w<y9whHQ#xo^So`$`@Df2<txe<oJKaBg-& z;HNt-So7tgH;A!!crt5k%QvCT)b5U*zUCdq;gL=7TsUm{c*Eb#2Ah*d-md<ACg%3p zo6@_wFGn(w3z(Br(<Hq{dQ6($Y9B17)2jj-dReWUD=rQ6PTN#0j2bAWyc6}t*Wath ze7?z{)*bCYiUG)_ShoKg@DO>K`|jvU|NV4=2IEd4&H8G^wf_4NA0_0QTi-C1l`dI- z=#aGF=+iRZzLX%SM3~64=nvI@NB|V3Yz|!C9o=;Ag$g|_GYc!EzrD?L2*9j6B}J&K zVt0mZH7+WGnT6&wez-|kik~Xf8EEQj#cj~qk&+__Kmn%~yi9@>f%5!Alj3`TYk;Hs zH<F5{rya?i{zZ>8F-1bSbl)v9?@N)^o%qC=Nkq%k85ms4tvJN-MxyJnmOV&|iB(yr zcPuFtOaV+OEi9^DM4pIehu7OyxPIu~bngTlHUb|K`~md-;l+7q8%l>}%ZpFx7!SOP z@m71<$Hl^=`Kq(ctW{N$uWQ0kwu<Zg)j~V}ZB>4gXh`F7-$9R=>MK<n52gq2#tmiN zG(iOA8XpShTGMw3ua9rXP+besKD&pi|J0pF%Ny>^>c~7F;GGS)7g!~#uwoj^#TkhY zG_N(h&5~c?ndRiUjW;D}Y!YWB?o0gH{1|!yoDi{w>WX>yg(aXc&`3~&k(yyNjnj); z_;`gC|3Y<z*gCiTF`ksFrzj)o72rt^lb~uBT-dlF<7VD}Y!}(RN9(4KNMm-a?|udx zW@JXmYEH&?1Yj#k*${od+~8Zs!;~+nj6b|emGg!m$TZjdRt-_Waz)uic_D;Z530v! z+2>3$rLw}-ppfs7H%+kc;TJvl#jD@2hOmV(qlAC_ao#ci^2dqPJfyj|1Sq}51B|?s zAgXWMWQ+b*DawN%iXa1;TcJy3-vAWXjhGXF;Zj1Y7gMyHn3FzYqR|#5n*=8((}Ibo zCxb2BRyMh=omiNLK<Bqm*SE!E<=ke|nc<WLGm^&X2b34P)rGnPf=PqXq)W^LOg9n& zEuujkxh3<G{eJ9?DKviUfWa}#JkQx_PxE-kv{37pe64Oz7oPE6<9pblHl9ciT<bKs z#Z%J7IT0PP)5MxoG$ZdCk=D%(J8Zly%P}VN*AQbrhUql<C3ee(+Q4l$L=#-%(hLi* zL8o3$$$xcvbxUk2s3UOoU_G4X65x#9ngFBj7#WQ`&9XaYcl9BW-5~XNX&a`H*flkn zm~X(J`jT#-Om;e42(aem0cxzDm$^AV>U_)sMXNbB0>NIS>d$4Cd-A9SBEKq2KlO>S z`XIl~y!J@KZnRun5x(~oA|DgIj<#8=zLWaYfnhyh7{GO%)zuEDIN@|;=9-C%w78sG zYtzotlm#g{VOVMM6b?FFlFN`rip<_^G@Gcf2-*59I@#1HF2KBR!O9r0@bI`4myaVC zEzTp{BIZ3&Y)JTLk1sFs?2aogI}iEdbKwdy&XJAdL=hg}M{sZG_m^u5MW!d&0SMMA z*Oi75&2PmAfWpb`U|jTz!ud?IA0dBqLn=^scQa#z0dM2W&(>QOCV)><^apWUrBD0E z*rjQ3o!TeIuz9v0mSMs6u(mmWI}0qM-uWQR)DpWIKjx^WW8++5t6X1RK`Gw|(l_9i zVZw8S*n!JhTLV;pL<Wz1A<oTEm!RgQF`8YU7$`rJul<T>;&alfnzqpyc8o($@B9}u zqj@5acgA*<PWFm@<g`^0*UDWKfnQi3O%0ltJAG-ShL6mG>eAHNCL{&cn$yt*u`Z>g zaeuC@LC<ie-@AodM@3k6tf%i>lU1xNIQNN&vj2D(h9TaWt5rkk(l>v8Sf*LN_+l=M z|7U3FmItL#5-)Cy!}yl1bIGcICEAVCV_;ZcBzm<>8JajpYeakK4y-{)!!HpwV$tO4 z<OeA67y%t)<8%MK{S6aZm{yHQ=jL6qnLwsqej!^T75W<|;?R9qPRs7})u=F?Y+L+K z({;=-+O18}y2Y~1XK}qJH+A8qjHEFvd4@a^k(?%i#YXj@le>-F?~(ixJmRl%*e8)a z&Cac>vE>-WZIG&P4?6QEaHtiWCv+pEclyR&se+($KBl8;g+;8N8NdAYB|vl==ExEj z9(1zhO*nkg7*px!V|V{86(gM5gKXE?o8$?lxLSLnXIjhCs5&#f<}=mQU59%t4mn;5 z>{iP&%`uDl#`V+Ic}(||yvd48t)dzo_;-~PUda;KO3;%*MPhPv)<{y++x=RF1RA2A zOSQbJ8fPB~h&HN%S4OB0Mg39v0%&Pn_`hgr(^`xYlu2=!+P8J^QYAIJdbavOchAk9 zgZ8{X0`mofBguyhUWmY6gG7&~QLj(?)BGVt?!J3>kr&q5nCcM)2C@{{cGa^<3-;(j zw<nqlog<wZoTH=pe*vSi>HtY^$_eR@4ybQ@%3ZQtjp6QP-KXxSWcZnmA_bX%Soa99 z5K38iuOoz`exARcG$Mh-V+Pn(8b3VP#M?o1z&9!0ImI4l&(UPBGHBR+nIz|Q1f&0I z$EV)QyT0SZh^!~HC?%rTU>`dVKZuS+3x~V(MUDIF>2($4=PX3sAfFX&DoAl`j=A(X zoG-V^@`dPLF6Z&4k!j}{MN2HW57iYY(=Y@FcgeOw-Cl)E1M}y%qu`j)<cW)rOVHJ^ z?)DiPww62S^m{pm9nWcE5By*vU0?&6j12@HfUG)T+alg`FjCK@>JV86t4o>sXreV7 zQ&H5;c@Fql2}m}nJKM#fUJ=S2p0>@sdi3y5z(Kk^a>!Oqv1L=E=;thZEULw*14&UK zSjloHkpuW^tbE<GIdX^5p&lbMkd!hEmS&Yc+;wpI(x*#vzsGzLbJQH2kwE-aj#^|^ z4$8Y*T(g3MDdsHCaE5=nrfjuoR@bN8K{+uD$XT)=C@RQk>oVz8mO|M{CJ5@*Wj-~* zYuyNZF|Ykq_3kdjT++kiS=5)^PY76a#<8o$pXgjJwjU7hmZvp;ZoMYkcsZ*p*U7yD zf>%3m`{H)29`8v*-0q+kRK5(l3il2cV6AAB75##)W1m~|NGf^5-BF2|12-oF&Msp4 zTsy%!fPClqIvAdwz1M!TQB$q+b|DfJHdBS?BFo*H*3t2k^s<kGfPbqGq<YG^Ni+3( z+y-dd5Z9N+HBOmDqRlz_mf_-%0aTiAnU7w~o3vsxudICaNLVXmXhCYmv<x7qZ8cE! z3=A_zk?EpCov+@=h8hg-Bd5yagsJr}>%B3gWmj*GP|oNBO&b*V{-Yhfyt|==y|)qE z3+I$Tu11ye6PBkC@~icms7H=a#Yi=a$WPcbV&O%^2bbL(xm9b1YK&W`^$}0vTAsgg z+cM1{y+lykcPxw8FFaBg*Mk$hvw;#mbZR`f+tOK+eOamz*?U^O{6$}A+MZv2?+k<O znVbbRpji>fSnE<a)e(9@ns{d0*Ew0}G_;UVdMfxkla)s}Rl7fOI}m(FO&N@~|E=?5 zD8RE$#&)=NQmUfp0^3DMy>oj7s$~ijKihS%v!l=`!t~fQ5JRQhqrEQwc?nAAV_qK% zJh(X$Zx38mP()tfY4_P$dB+4J`I7+$D;7G3&KlB%JS&}owWe1mvsiJU5wKlY?>Tiw z>KJH4#Qn|H^R%Rt+%BV!1*MoQbWp+z0@&*_ad}{n%dX_}arAgNf600bJtuj=p~3UH zzZU$}@f{TnV29^S>gN^954v(LYxGs5`>H+$Pe29de<?nYONnx5n!;-Hoo~@bfNVW* zZ9^+Z&Yt-=$elc+%8qG|>;WgUXR-g*5Bx=UyuUhKv&2e*-8;B6Htb4lA^g+|>0zMn zdXJM+%rS@@`VV;LGE{tTNb4W$jzJoc#7()5>D_x>PpzxSM%qs0@n7sgAySjrpw@YT zXVYM}PM5>-Y9{c*7iE4oN7Nd#*xFeqE$!ieKza3<HyKG323=JE=8Y4*xXA4@M+S5# zZwUlRsI&f5XjShvA>%Ssa2c|~Za&;r$V34+xdVRpj?%y`>^A)(Rp$njoKEuyc67{U zaTfU+l_IwZOnLnBQ)k$`m8RAJu?}bLw)*$;xsKvhoi!(1vh@>Itgl@ssXh0ZupNB~ zz`Q&nz}QG;iNg^y#kR4-Va*X+(k2F)*P0AGe3m*xhC|Nkkj;!3Ff-dDkLRgX7x#T+ zCl$;BZG-Sn2KsxI88#~?0DOZ(o1;jhpb&9tEV9PpPxG|~ZJ<j$nx9OZt^te&y`2m| zE;jq!8>83dto=b}nI2eJ)2{Qhn$;z`1kU1DW(vg1fMETL*C!SLQA`v-Gf1OSAUj5b zoI#|Vj&(C~#|;nBGCnfr9wIL=v_lkH<_0U>``(R$v8c-D{k&=;_J;$}PhsFCPbB{K zx1AHgU;EcPP!IC<)~6a$gqLP5C&T@UgNbws?r2wtd)3`;w&;2icpEx2C?@w{N3`*+ z7j#CE{z!g6=kF~p&Kh*0P4voQ)<5-LSVfq8-O?-6Ea>|u2#=GMcBoYzOy&^w0@7+7 zN9W-9=n_!?m^TSd>LK)-^xk8=pIW^@$SK0G+`}9E2d;ER!FoYkJNXTX2EDY*`y-$= z_KMfq_B>Cg7t8i3ys7Q!gr@2V1RdPyOc_o$;O@EX#EAl0%O#7o>sI^v$9&F($#FSn z6cnzmT_iF<?teiK?{=~qY$)vI@7ClU@)9lMYCOMqIRB-B#a0ram+{?c%i5Dn%!JsI z{qA51E)mW3q`U2W7ra7a9?G7^Pf<?7t4O)&@NhtBEP<fU9*~}h=Z1x&_ckp}Ri20f z2@6r(R{N-UzwrU0jt^PGt2@eplhf^M-+PoE;WlnJLHPhO)0wm?TitUY?aJHg-tU%} z-g{_{y1w_K2BfD{kFKW%<gJ*&q`JT=`awX2T>{Q!J?S^UIt<1dR@V00;l!M|z8iN@ z?J(0nIdD_I020>i+TQhvKN=Rj5}pP_u#~ybDVxKlgaDo+`IW6(rtnR}4(2gTN9iZm ztRnUiOCpj#_RR%CZz%DU<FZqcuc2Ac=MwQui~?0aAQm-FX#|S?xmL;>4cU#z90{nN zLOr@caNKX>j<l=Zj@lcY4YTX7>wQOa&G&z?^%hW3c5U0Rfgmj)-6ax&BTB<ar=)<i z(%oI7g3=&J*U%s--6bhCbTfb;0}MTM%>0+$_w&5(_kBNWu@=LEYpyx>zV_bdah&II zr~%6t&=dgqfh*gZU_((J8d!Oa3Q!1JIgOHpyL~u<ade5nqzjj*t0%x#WWXQx24Xs9 z_wfN&$z2!gCW5L%0#?b^?gN<MYU=glwFK&qCAqa@$-3FKNt|XDiap<cs3Q&=iuGu8 zv#-{+k7fMxGDY3{sLl;WYbCn0!jQ4KW=7q7VRrk1&L~$L<IZX@ui<`=#cm^zXe339 zX*-7d&jyg}4XVB{_G9yQt;F^n3=vx6q1=O>O%%4!*Ftpo*bVU!6{`(i22E|#F_ZZJ zwzLb*KJlA!O+O=kR3yepzV&GC3ygFRI>k+b%5@(6iAhg?IVai|*F^|MH?k;y^Sa<U zS%rc>zFEMvsssep^DhwKw>c6MXD)neto)3r^!#MYZ1dPDbpA3|2sP)m_Pg`fpuH=5 zjD0;qPMk|o5@Se$x#mDuO3W-=khkdew0sqTho^)UqD1vmc=M7WnfPNhgyrL4nSH>@ zYbkS~MJWY%<JSXV4CT_$4sFHCq2zv6@jv?w3Uff^61_*YjU3uo6^Vv85^_9!Ae?*p zL%l{c8(pwAnl~$Itrz1>902%S>1AmG)jM5JDniC0EA-KG?voX{b%asA@enwEwP;~` z{b5Tj(8;f(0n|O}8BkvZ7>VVlY7|3sKwiJ{X9HT6%l?!z9{0WKOK4Eo3pEDe2{P5^ zQhq~EkltxzJYC~$h-xC&<x{h*_b0qGF!2{WFuT8f<t%kgd*k-?5jp1CDYoM2no4?R zCXeShn;z@mWa+<x@VAZp?cLtMqw`+pBw-=^RfFDQ>@A^nnAby<mZe`HnPkVsoloyB zez|~he{bLBPw@IMaD^Z~9Ip5vWHt3`$CE`>TM^~N(|t23b0a?e^{{lgrM}86-IZYE zd!17FDU8u<3Fn7KOO!$5nv0(`V5Y|;Jbbzn1;XVWYS)OprfpvxxWG0O-H&*h^yh5a z8wkF=R25M>3OuXidt_HOvd-Y%wBgfB1SW{rGsy!_r0(K<(1jqE6rcmgA|}}|w@F)= zC5=r41A_Dn*u)_}?k?wu_I^`HnT3S{%$(8u+Lty4+ctux6`hPwGpF;ene4Dd3;K<K zKwBXFy+`v5Q=O8#_Iy?f^&Ft@d8stog=<#%0oDZY1pR8SH+Bt6dr76*ncqV*y=RGz zD(D-y#OVH>F6y0Hn-Nk<cQQ&TGN-qbd==Bvv+lllvKXGxOps|H9-daJ?82lUgKkuG z1FAfs-NUL><bX^*Gny`>%@=#GdFH`*@?VmI4G^TS8P;L2nxI7j%IY;8$@A}p2VS*- zitnI(Mt)o}-lnBp03)=>{0xddOQ*fV-=)OYQ7z{^Ene|q=3{)GXm}fc=@z>2L#8Mo z>QlJV;>NsJ_|U<H{53v#sq;<s3jCTPy$&8s2FRU0QCF<5Sq2wfS9dThh6=QQ5J&=q zU~yZG{V`b)ThOV~t<=*ioc8hY*+%PjimRI!Vsm`LnCfO@yMvn`+;`|d8&4vpk)9#M z<JqDHv3Ft8*psOVHGpo9GzWUun>WF*AB{HH(NV`R>O4(=L6kEw4C*6ntD)uf$Gjyo z<78X*{(0V;Xduypxw>U&RNrf1OL<)$O>1<3L4Q|mc8NKKm8?o#zPP`wy6FV0Fv&(P zLEqZy7w|DlPfp~^2K+E@xv|bRu5i*={w^ajA7^}B-gXpOuvWV%s2qlp0^*1~1ip$U z%yY6`zvees_y`I7>sNkcB`cj<O>i{lZ*HXM#(gw?c;qOl<)zyT^j1U1z~5W^NzV~u z4P1d84WhI}t*102rg#%zuOAar3oaJu<p-EWiXhNw-_k_=`6CU%ba9{rmfl6zyTsA$ zC%Tc)(ekV(YfmIH8tJ&i^V|xvNHZsJDtUHJ^F!VNS_4q<4e#4;A8o^)UAu7;m@UvY zd+=T^Jev+Igb)FK?(xz=7YK5f#|x9^5`!<-4ZLyWuRKSC0FF9#=n~=KOr-yw?d?DD z^pRzI=glx9d(&zoXb7b7Ph6-mti|)UcDI7=P8L$(yX2hhlCycFBQd#SYD5CY`q=~K z={l!foCU;f?3IL$bgvnaAEdh{M0R_zcA-f>-Xy&f0<<^;edJa$H|-X6(jy=~g3YRY zi&nM0OT$y4jkv_3^J}>oW6ha;uWCf>&H>Sa#UCcY%;ptq6Q{uN{F5zf_90{Y-T~m7 z8vVnylUZ_?ztVAYXRyv3ZHv|WWRse!>!kcG0zwi1r3-*430Yoy-Dg+PGQx~AVjR@e zfVKT19;HIxuLbdTz_@H6%|+b3)4QPo$N9rLybNb!T8ON+%&Z$Ig{Iy1*_Sun7R<V@ z+C`p`b{{BMd@{C?>ygHK<kYb1GQ4gh7ujq~{Oh>YMSUSP8{+9^mmcE2?6uZ;)6>we z@yAT@#M3j%ln&EUo_XfDb0+BG7bueHURrJjaG-4Ev&6Ee37=wtKO6fH(`AuKzg9le zrT)zTt2PSQ&vVc|d2qDX3ghW3g5M%!UekLd@6nBOno<CXnf^Um(0)}y#4_#-bHlVI z)Go0zIxIw7{9gG1grA5HPZaaHndj_{)t@zIe4t&UOiSTLx(^7b?$F6IhLLfw)gRLL zfr!eBa$>8_Yn9G>UD*wL+HMZP6=c(^1J03voz*i^7ob><Xnnm=F492F<TxGBlnHMn zouTDp#ve`XJy3|d=h<;9Verf2F8LRldxk+VpI7IPDEzh5cF*vg#~bymqT1xHtjK_K zh#DoGEpN}*hF-c3?^Iu~8R($kZtqj4AY>w^h*R(Hh9u~Rw#xFrNnn)?ksERVT!X~h zk{4zB&X1gmTuF&UGsb7{<YE0q=*czPQ<!!c<P=Cq&#fds2lKlW^1n(#w%SAy_ux9- zGaK+#|HSu;_9Y;K@09YY>tawv>uujqH~ZN{!$U8#O!->w&lT`a$&;23WQSmnAxR+@ z;ujm2_^PFRZ(Baln$4hi=c{9)g-7wc={U}QOV3X)UZdKkPg9~R+)wyT<!~Gj`it$1 zS!So58IvHmuFd%@M^R>d7VnZ|wV&BpN<tC-3BsB4cW-blBI_V|YZG->YF-XQrvQlc z+4X}~dHrFNQ2_UAR)RD27Rc4iA8$kJ3Ae%fYl*ww^e9+X^4Y=iHUnbjgJkMEtRgS` zJ<D{wdY~yCSJELDGI9rWgWC3P5M!|NXH46gdDo!E-Sh_=TO8zj*FC$mCVZ|)Ud?Gb z)R!cEaI*cas8CkDWD}}oE-j``6|`Hy<HBJGcuVlxmzcrt&+ileVyPoE6}TVPcsrn~ zHrhx0@dk5lCIeN5ck|)a*9LbJ;ZF|I;ooU_DZT2A)ypL`LsFxjemODCQ+mp0UAQJ; zeNRkFh~9JF>vHq`RW9pO^N+e|uM+YPEY>HSUl`aOe_3!|$|<)mIq-MOIov{dqb=H^ ztz_vQ59JP&Y`#wOF)P5KhZuLe@tVXb#{DDN{y%EjKY``z@#bx+!E7ayeck)bYx+e| zp!~bR3+ii){$5A}%b<f-P#w6h+#3s_^3En2khHqPO8rCDZR*ea0)Qv-+_h?sE$U0Z zz{2hpMV0Zp3Lz&)w6OCP4*~$byXxHpf&8M}jpfwut+;JFpF=mnX`rA^0JlTvVN+M= zsXK9u2GRmenfwn1rTb|o;&!jNF8Qe|F_Ihh?q6V&SMtUR3%#5a6{!(0BtBB#r{@%U z)=_om(iq7$_$>RM@zUJ96%eH2#If_+ST1~ton#s2O|Zn-;&lAn^s`@#f`iK&gWD%q zmb+OH)!1mE`#goHC-|p+qU$P~xlqa?D!+E(ZjXZ05@`h$6T^C$zT}gdAIwGVhg)xt z%R`kP#ZhQ)3TsR1MrvQGPmsvJhtI}r_*gyQmC=^l%oG}_Ii4Q9BN{-R?scbKP%`zF zE#H~U8I|Ml7j%Q8##Jl3>f?Y`tMuP3XPLXBxxl!nyBDj*f*jY6n5jP~VE=DHN<iHl z(BIrYB&@K_ID5OhiKjq1-QBUo|J|peoAOCoCIqc##i?;))mlTFcuz-GGijnyk5?8> zd}+l9G=*tfDX9CX%Ke9{@lOKsV%(KW#PZ>b5ZjD>)2}tO6us*H?Q#L^7_mHD0Q9Gv z0WX)dYx#?f)0=-Ke_DF@dTH`(>#t6yX5?Qrum2&mJHaKow=<D9j#pYNeg#Y21>Ga( zffIkJw)s5VNM((Rhhj@<(7fLMu=(^kie){&!C9fCm-PZ45JU+%?2!Xu@D?1{3SnV_ zg)(6C5p~Z9mvbrmyp*lErsMJN+){tazWk-{Ptn+`*Pq8$kg-IeFv;;8Xu@}7V-_2X z`ki>*+EXo%%8%-u{D=|7KXl@T(qES7zocjO3e@1G<QX1}PjbM@21%<q_^ukq(%s&W z=L7i`b*5mh@Wj1kJ^prq1zKYI)Q-T4hstm72N0KFc(nYd&E4xxdyZx)uRU$e3JHCc z)BP#+vT~=0uc{aelxVrf5>v=n?c6)=idJKeyXt3WA%D3&x&P-5{;O>ur9k%gVE+G# zdMcRCubn_P-W;QoXRFRjgV$}M)-lp$g58I-glr#myuojs_6_dfhW%AFj$1s6F3D(b z=(wJDA$gY#y(~@v)Hp@|D)3bg8L&lABC8ZEgM){YlkndN6~gELqfDb<Di;puoTbJ_ z_&tL!4s+X)Lg6gU5iO?2Ig~QIE3~&2*ji--$Qs|6Pt+Jl(UAN-e3^fqL1qRm9!@rH zSOGrPwB%2!*1mcY+Y#{)aiSuVWs^xayaV1j>b>D%VtJPODT45#bg-r4bQl-&7<>8V z5d_T)x#n%h$fHqd*QXKJRZM641$S8GRQ{uH#72Dsh;0jN=h6H&icLEBI2PXC^8Wcd z>`*%9BYrryew1rY|LLn=yX$%AO%^~*YM13|)q(PQ<X+f6jm`igI6eD(1n`+Hyu9-^ zF5w$d;=qOPA~8y*+5Rq|8(~NEx*H4&)d+h%2~JZI2H3tLixDaD$AH$=h+%|3A(vbh z#Q31v|Ew~)|H|rwJTq`QslADo65OVXitIps^<71R|5%oI@P^F%J};6Y3~H$mvVSt( zw?NQb*Cttk=L+7Xui*iNC0@nxN+Le4HstPy*ZZG#*016GQa;=;3^UD1n(Ct}vg{-1 zTKHA${4rv}l9B$Tu_^@Qg4;sxq;TG-`J_gihGKey*TV7gkz`@ktHN@X`OV~M?|_3_ z`zLC|Egmx#iY>Rl*Vk%&erviSe<~%KBi_Y5#-OccV#jyZtE`*!)O4r!SoS6l>(Lna z>v{wF;`^T=q*R3gexg{hgf5B9d5`~&=eeh#Q<z!7!2L7Whm*(bMwT?uKogJKOX?MC z;IR2gvd%{}6vFHA)K!SzJXR1tMD(S;1zcTED2Lwz3&5A!GdWc*vUm|t2wJkupB{p^ zsdihaYHYLjY`;F?;SHAC)FXZ&p=puYKc_wl#Es0u_`Q6Mgr_{A>fB)R<|4Hb!r^m8 z3(qr>trH^Li{m@#pMdA%IZhp+2xSY0YfQg{cd##g8$ISh8|VI!8f!rrNwtnbq-k1~ z#Z<T<Yt<hkU)00crL2>O1~^lww*FR@+%od(5((W*YZZHTK;H|siWr!w9QBZ?Bbbwz z$)Pq!{f+1478PQ^oZ}cva03*pb<n?%9{~{Ll;L8Cvf&F9OYGD~i7Lt_<~GHfz)^X> zwE-*KrA&I+JpogOz6Xo%<opCWjWe05=rg}J2t_qYArh9TT4x-Gup(QZBUnHwG8mOO zz*bbr%qIQWNXLzLeGRQN&Aq<?2kc{QU%KTSyq${tW)b~fwK?Pk4%a3$!cwo?1e5Om z(1XApvvbg02$&vr6`r&HF>w05SN&*B)w2q{F=NpnJvZ3U>Z<C15A<*WUa*UqVxO=q zu1voq&{nJWy+*n|b2P`Meq|lOEVw2E*s~h1`$sNltQ94FPLfcB`L*}k$KyoJpZ-uh zRcS2^iydSkl%|ZmTZtdt>Fgz?^wuIaS5}qsLVo@Ub5yAI$stA{od^CSY>g*2NM^d{ z*2*^)49NvHM-tbYT5=|0#A@ts7pfQQy*nhNxw8iAYUk^Uy*>z@hTjQM$(SG1O(3$^ zS(I_?UH74Z%UlDGG{z3xNgI?&q_)8w>8cD!xSC8`58mmtiIP5P?-iC2j4hztUsDZ` z_;<FB5-&ZSb#NTniR5k;tmG@!NFPkom315=?!#G0;(T1sykZ-B^<6DS{!FWspw=(R zg+70v*4ud$hmxbuj8BxzY5b~0E+pfT>%($m&knS&7T+M}+E}LIrv8(+*=G-Zx)(D2 z#xlv6ni6v13;|PH!n#s<&C+XoGFDp4lW^5_V)yoi76<r5Q3#tU=?%Xk5#Y-hHGTeQ zveNr=8&{j8w8Ha$$Fn{w3Xt(#{UJ074)M==lq7fy=%SpaD++~V>Sp^Yu_igNZn6j2 z&Z1hL8B0=aLh0Mkl7Z*Cd!7%`J|V@64l{;}f{m;VzAG|y#fP6v5Cz|e1RvSGWFqbf zt=MmIYXsTJ)s^6N{Y<~AsIT00>S9Xos6X4IcrK^!@@TIQc1UEyYBNS0C@tQrS7QB~ zS#l@LO0#`+R!Tur;DcP-?aaBJ6PU-rPwrJc#HqSx#R_Nf78IG~per}z38(6Tv$UIC znslXQo0fx2r$2v0KP()yh~mM!qjr+qAGLWcpls@Xru`JIx{%os`kO&A_Jdg-xnBp! zIK+Y^EkhO^60(uD$%!;ALM_Z%f6R2I&Ga$}j=@4SvmVr#HucBOPoU`~E*Qk(1&4P< ze0jf~R4x}vie5dhID(OZieClP2>6aHJXkAM7Miig^x73p%c_8_OB%f|oog8Cfqrks z2J58}Z(jQ=1nmJSceH2u{jY%Sk1Oykyb}&G13K$E@8kXhaLw%6IvCou3O}8t4!N{q zm3J>a#{&9hQtuw31myk9+)kg)&;qsoi|+>Au75(wl_W}nVedXR0e!a@6Cx8}wW5Kj zoJRbv@<oEgGH2zs_*nQHkZS@e`d5JenS4tLIT?^ZcLhu&u$Z~v3*1xW_r;MN2MbbM z0&8p)pmF^B0f1J1s%obCQAXIt$<JV-mtlX7fU%f81dz*9su^F(*QdB}(Qa!X^+n9# zTKC=vk;B=leAU@*+<wlYeePp(wcpd`Zcz83PWobiJYFdSi8au4#X0eAKo@XYzp}(a z7=lk*J_OS$ho=`VR7aIJzL3LD|J27`zr9E^0ESI;rOk|;On_&&{~M#ommB4WLWCrw z|JVtXFL>aH(}vGt7&_lb0AQzv7AJ=1fmNHY|La9Cf=m=g8)PQOi|=kM%ql70bA!S; z<NRa3$~%R+*E9a;ycbMN*+}PQkhG#YKuNX=6<w9sG{$lY<t}e#uEfE)HvvSW=_v-A zlXhd7=}$OJejsu8x>6kP_0Q7AN_u?+ej_*3$_xqz6w^8$7~jG8^H1h02LnAGn!jjx zMudlVW3;bsnNR}Z<fR50YQqiA6`dP_*4$zBh9v550$7EO4zk8Fu&tns7o=|DoJUVp zKjE-eA0ILA2Z!%NGfwS4m@`#m@$-bij|6x-hN36&w+2jJvTO#vDLR71{JK5RM^z~P zfPDOa$H=|YAkmR>j(EA!HpSCVA@T2l`;SEvW{0es`I+zl2R}wGw?N{^l7~QJG-0?M zlpEPi0|IpP8q2x7Ox%?E>wS$z<jOaY&ee59<?(wHtj<Gp^eFd8--t`~7ME|e8Zf*D zaR{B)C09&{o7+uxe^C}lY7F3v#CDf@no9+A*nrdOBeh^iAXZ_S)!X-8eLn|<z3j0% zH!l&Kq2EY+Xh3HymeT&(eaA2eU<d#z-)`Y2(64B%?0$;z7Z|Z1X3h8rgmLfFqK?<E zPx#6&)zd!?er=6%;%Wr2aWLr87o0oH?Y*#=u5kg~|Fp{ZVdh2j2Shs~vGzU2*09ON zyOE7ezqrj_Y`#XWs-4k)sy+~pwi;{p{Ft<7^Q5K-(ndV@L)&kpOY}D5OIrQ6x^16y zpAsL}SsA(SBh-BaccE$@e9%N0o|Hq5S5~zJ+}mxSP(_)+xBpo>zuxv%@V&#Ue}~bR zH0K{lg2ZNA6WabWVu4rNd`>79yT={?B!0Kw3Ks>NSZ`)r58?aGthf!uy#I(M;M0cC zpXn@6RS+Hb6xA2C2fvfOiS(6Q9S$OU>Z$PiQ0TVP+xGivP5}UCw_Ii1`z0HFSWgTD zwLmHu(nh~e-#}=5s7KYJ#e)%}2G#qT0m_}=SjNKuP7k=xu;u_@XHXKF9^pG_fWOee z7#LlRnAUNwft=P}co0O?ekB!Di-({U*YWMs)nwp({Gs%3UD)d&j!~44i94WvZ<k+v zCd_1DONqF&Y8Dp_bC-X~f@vY1=f{;Ua0>RUyQyw2P3b>66e^!ku=#V;{RylV763)| z%niHzc~kxpRh-3NTm?|S47^n{LmLvKAKhO_!j=`3?=A&MX%Bw@ERNg&5;bJqzg*}8 z`XWs2H-a&5@9s6ow7c679i<BzEm1SK7@>B!?dY)AyE{vFy@*>V#&5}NT0Y~X0j92> zGKxxG`r@!AyGDOFVl+F`uw2jX2FOJZrdspZ@nw4AGUw@$u0owYFo;q7I52rINNa%h zi4)v--3_?Es0kqyFI(KWB0pR#R%>1e#%p?(3o%R%HsL3+Rjgz?ymd~7p!w3P=YT>f zfm-3*YgC%|v3iuNm_VwZ>_dLc=Rr+{=0nQk;0Se;xQ+_Yy!nVBspvHQ{ps=4?XV-K zozE3!PSKtcL3VjbPcYYsl{|&w@}JhFSzVI<JxUGay=b#`<7o?O;cD-a`tkP>{ez;r z!|o~Czj_)vfY^c2(x)%53Ii=`8!u%6rXao}72(~*^$SYLJ92^WWw=TQwE0cYO!$Go z%lfHhR=LRjR>*-*=wcL;)57-i_qNVeH|WkMp!0z+2t$P}4e$6!IPMUD5ypWTBgQQF zTYpR2Z}C6)o(IB50Sle}>ZK1>Thl_hw-EDfcR36-#j%HnR5&THNdzC$;#b!*?|j*X zY7bF$+XquEfH{VN)_gUauWgX;cjZI@*=yp11SnG7ikmg_0;&u!cv&&Y`;7Jx6+s>X zaqm6)0(~g10$${8x+@-|B^kru;D)qJq>5qna7TSFu#2Jp6B(`_<t(}@-`l0e)W;3~ zi3@3qkIPPH4NMZ+N651v0j$bcANCoK6}LLhuz3a2-QK)+3U+<-<{4)hHh958qvx4& zGXOI7?H^r1*1_#Ro!a~P@LhpTQQkvl1iY`FKpTEdk1fFXo@c<}Fhyy^e#2A8(TAR( zaE@l#Iy3C-Q`C3UJ3yhp;+o-mvEZ~#nRr(B&t1e%<*f0YER`=2y+2$x!Tg7(`3d8W z1U7m0pZ1H}Kj}Uojf=O&v|yPpxq5eufx5v9Ad5=`#RGg%X^ud=d#$Bs?DswZ{adb& z(m(Ix?fw$iEf2@UTD|4;qpltWCjpbFh5j?(bo<sap(c;fd`xhbQr=cs?4ikz`5y{G z)07#jFMe8x+U*C_8An6l6mb{JRJXqKnqEp84EJ1|Sv$l9pnV(+1BT@R)8KOO-#iJZ zVF+I_WQ*(-Oue9RBK;?K|F$+9qfO-5TX|F6p7V^%X&vyC2afE&p!ZB{pA^TZ0o7k9 zIY8b1pg4UgBeD{t^~J!IfbM9^TXuy;WYS~M?(M8LaSJ>EZ{SeqcP&1E0~2cam)1>l z{8BFEFj%9-Svkdk{GZHU1C23+ZhCniwnFy3N}LEv6FkinSS{4@>Td}5qQ4}U7RO-f z!-jfM5mz9JW2RYQpn)5pcRW?bu4$))4(W*vHhYsVc*`Ywm%dRY)MP~K>B0O;98q_R z5KQY1)?r?&M%b%c5^(LB-m>4-=hm`jzB$*lj%k81i{FQX0i63*`OC?v=m9O47jWWp zyt>t55&I|pzW5Sla*g*Ft}P9f*oQHH+N0OhFGB0Z&$hdHO12vP(Tyej(dxNinT_S5 zX=-p?UMz2z;xUX(7%;tMaqldNckE;DuDTRb3sw9Bh2)dM1-buY6r!vB+x%$bvdX96 zaJvKLl9VU(@T?_-w!W(ibVwa*2lBJJ7M|eRUl}a)lhlLaUbHlNeW~7z>0Rr!5;nU8 zKXvgRMJ5vA>Q6U&zk<QZ;YxWzt%t^C`>UElEE)0Gec-R8vjUrj2MlfM)x->u#vu>! zB#IBjGqgx11mylEk*zUb*A7=fu#N}i_LD6h3gUolwWe~qN=cdINDi1L22U4MP>~Ny zxYD<)v>2_j{Iyl~q$G_w&CD*H{$jmJ5bo&`Q+YDEc9bnQv^|T4QG+Uwg@~I{JYD%D z+87QZiJvW;zEZUe3v|<&^e0}?uYKs~J(5YPanblg8qPtos^c+IlW%vT4o|I`oy204 zpEX60{`bM|xh2*jaa#?R#KoYRO8+<8sL60)2j(A%W^fC{@zXlhjWhr6K$zF#*UmWf z^G4?P%ZrwF+8jVGPmN1+j|9BV0=3>GtcGrdYfOk|rv@ly%0eb7&*m*v2S<`;XVQem z9Mrn26z)ziEQ@Bo7p>3^4<RGHg#yC1N$Sc=_1;YqKRr9Kdc!s>S0~04q`Z|JY7y1( z(`D{}$|LbP*_wR44{rL3uioG5&J=%dmC*I9p3ZUePV;-yIs8R+mZsI+5%E&r%!J@+ z9h}L&wN7qGbCy#&GWp$o<o0lbDfU?pyk>!)Zg=Z#KzxySF#}4keL%hSj&V#wFbUbL zpzr4eC(=%~ORG3Kpa6z5u~&MC|3H1Jje&{nZxiZ&%^AO(!Ghz%+&bMJ%Kb3;h;Q>p z*b}hO0{gSCzRqY`H~Mph8L-+E{gzDL=qj>BQB!|yYZY`JK3wem^&a!1|1-E)z?)Gg z_UQWZ{iqL^%l-r8jjvOOohi3jn)9VZ){7rWg?1MT8mC=_k3|@F;7f~ALKD8+ssq&M z8nZ5#BG3OGaQ?SI>(_x%Jd>^6s1l1uQEWi{y297O*8Z34`YzQ;$9*!!_hZj%dhbSL z!|8+u^&0VT!+ws7gpm=;bpK<S^Irh-|Hp{tf7(e7t`J-;J(dsJg%wDvu;31p6TXyr zH%Afq9*p?c*5A)O6k21^<+9SHx0!LRgJ#0Z-Y11V`BcU8x#MI7zwcjIlKLM=^8dmV zH&R4qzL^3o7*Y4x0NQ8VG`8Q=Xd`ba`SCT{hd9>ev0vWIqj4%5LJ$9@*p@w`Sen?I zvVMAZMp35CTn@mSi>vWIMXFScdDLwdzX&ldS918lulO|?_yb`@^Qf8yxj!KW#_XSQ z_=_=;8wU{N0^%=Mwtq6K@3UN}Z7WIC$He>r0(w+gKO;+f#I^joV62G@#R~Z#IMko1 z4kGb#UHjnzAt|XOZES*Uxg;VrG|3Barz-9D)mhI36bdW?YDA3Z{IM<D4cF~rMc<)B zCjC&jigMuNb^R7wTc3C>8H(`qdz63sGJyM;`&(un*S&9BZ;!X;Qd_GPaQn;100`$C z(c&*h&y@*KxkFN$%d(d+>cj`-OeZT)FLEC$iy2>QKARsvK|yrCer)W*wuFGlvr;~~ z7dLLzIn^V><4c!C1N{Rz1L_1)j#k|b!l1?E58h{9$bMgJ)?sA>|0Xv0Ie&Nf;S+bx z^|@I(r;>J^8UOEqSKDigw*d|en!&0~7#_QT$)5RyuJ48Ow4iN5^}A8Y<m%dKz$MnU zg0@4HSE9fqH&#^J&ncBO3two037>jSFkJ`Lzc3Yf=gViee9{XSG~0Qm&N%A(5J@}Y zDk{)T^Hphl?CMBzdCm%#wSdoep0u}RkU2;TpUx`$G)lFB0?#l}ubQ48>-L66JUzdP zm8_lFB>!_cacSv!txvv*m2t&$_`8PfR~*Qij;&l>_0z^^Uz3{dZ-vmamWjcurH<2C z$qmEs%;d^^k_lozfEZIbqq-_l7I!3wOZL2E$<y*K|KU07a!O=$+bTctyf0>UpDXRx z`0B}VU+q~O^B_$)e2TN^ox{NxQ%$?JdRp#GMEpP7blcL49+$;UmJ7i@&_F}ooH<be zPbBE7MN?i0cA(@0lu2R81qzqJPMogv1BvV}f}b1wx<b72U|f)R7Kv`8u1Xjgc1=DR zE0@!u&`#fTq4dp&aBFXm>3_|-A$fmQLT-pxM_et;@MGGu&QE(6LRljOoFh{Eo%gK} zIRX5!eKNgUsasGjE3zd>bhX6%^n5}^m>Ao$@lcm&;pSXe14v6owL?60P(Vi<#)K2G z9RfH)Q20o+V1)1kWXyMcm+;t_N9gxdS<Yyhw?O_G?}|vOsSAL5a%9GtX6#_iu8S$0 zcz)|Ff-ab<a0Kz=su#K0L@O|<|5XXFq8AMEEOKKLHU!@+KA1~+lv9|JYEjznolJrF za$>K5NeR1zcGON_Z*q8c5VD9OEgasjMP6*--#?G2Ts$eGstvvC3`pCu$xT&fYQTJj zIOca7NecB5RR`8|%*zpm6;HOkFy{1#OHbK!A%EI!me{D{3D};{$)c&hevqDy;5K!b zGNo0y2HdKkFhXT~|5%R<RKKD!0}tQga(!%DPB>@c6s97ttl;?u*9V`Ea!yE0H#@x2 zYcp4f+e5aXyD;_z$ho~eYR*eWK7-+*vuJtiR8SttdEu#%!16~_Zj_sg2fwPn?kaQW zPv_V^+461=`u*G7|M+3oEk?1&lYIsZqg?N64Zm}p6*T*qBEki<EqCOvP{2hUfm8W1 z_-rP?UcsE|&ojv0tDDYs#7U$-^X_f353vVTv@_sJgoVEzFDe5k5hhLgW_v2lL{PZ$ z@zgL<CGf$SdkB-9OHp}WRLbX)y<F$HMICd|Sh5qAM-fAEDFub;cM@vEF4teaIc(of zoq2gR)BBiYyrZT=7%8*_aRl|&aLYwp<7T)<z!U0!iN5Sxn^qZagYJR9%8Yc5?F2qf z%6$Ofr!#B4V&T539k)lfLJZctyhw^MDl=NDvTA$F&a|H&O0v7^Uft;I<d(?pb?MSZ z^Sf^C1OwB<h0orVxV!cU*7Yv9*d;PG%I`Gf5Yegr@nbdo5S~2uU3}_sVRj*5F-H4Q zg2jVlqZh|VJn0DqE9<V0Ro*Ih+lM(Z28L@b;C;Sqz6TV4<eD@FNKf(8s&V&H1(+rG zFS~>s5{<k<Y-g^;w>sa^grD!9r>-@NY$&DU0QxYmmNK8TfTo1vTiIM`AG#aRqxQ3W zM?l+ihURVc4BDsDAlfy|CXY(`d+Fcyi&c?5@e|BN@{<eYKP8mcR-9`CU5f<<FE;P? zt&qH=6??fXx$byeB09!i-qCeN8N1>5<Yw_*e81QI+4-y1?{=fHiJkkj%$7vu5S{0| zWfgKmRrj6GW;_m7t1GkcBX4Szg6yeD$qMiKe{h?wTRl@6%of!)lWz}#%yIx|aYwt4 zpO}IO#nLw#u5)^zt%_pDR7Lo1bw#ul9W=r}6fQJ!4p}Bvv(&C|Lmz_qO?fex(~-Nz zuEp2OIC;76@$b*R^d;%JBcOggM}Cjn^h0e#s8V%K>HU&7hZXO0G~-#cJMP&i>xDCg z8)E60uilBEJor(yGs^3Lc56pGa*InJV&hLywA@4akKpWCs;bVXs2r^i`yF%pwEhq? zrhTyv`#Ry6?ujmuI8C*VJmz-)A!d}V1fR9pOs;z6^g`LPalySu^>V|#JreRclRxv< z7Y<U%F=kYH9(Be~E3G^T_GaV`TA1}5Vbi08mn0%3X?nJqirV#Mf4Yv}WP%Rc>rd2# zT*a4viJ8_uQ=)lx^4hG|9rwm{>B6ySA%B6KM4aE+%4?~8!P7ot|J!f=$T{{(oqd8m zy!Kh-Zphvn9YN0aFVqZQ$9;64<M*lDNTH<!x8!aRtW94pgMMKrO+jeAj?a*Lfp*ke zCl<jJ#drM$tgUqOt1mxgiq48GKi_zFQn^HGcT$jr*;!Z{4vF@uNH<s`a1I4kOvj%b zzecwE+J3iEe-Z&9n$r<K@apwvIn*c}5#9#dc)a~St6%Y&E`OrObu6Y75-0_GA+g>P z2UNGb5iKln@)zVHeYFCO8Dp%RnOYK2K7QIW?UNmN!l3TIMoC}4GYyIhmq(tRopq8Y zoxu9Gy_|(>Q9foATVX#lB}D;$ABm!g)TF_<j9j;!fn6>&GUJ?(d9(Qvzk7agIT@#X z<X4NDuMl=8fA0qi*Zw!8OL@r`PS~D~S3`i@4sNee21hnff8<lCFDeh3Dmk&md0B6M z2xF#2+69(oKFeFWTo6HQg5*n;-(dVx0|h5EW%V%j$kH4hP_uRU;MCMo$>pv)SA#m# z*lEZrC&uIu)|zWSVK5vwwTms`!}hH0ZIeVVSQ_@N_85jDors{x`d$W6-GH=B2LiLf zv;!<HSeo-Ct?QwZ%V&EyU+#W;Gg|n#_l*0oo!=52eSuK8u<wLVeuqZ84v2v@{MYve z^xX7CUU?$l<gf?9H7e_Si=#vI=tRhbdw+D~XPaU7>*|x<Wlc39L#Nt`EMAvSag{AE zoLL8vuRXsQlM+|^Hv<=#ljUfQct}NY7h~v>sM)ca(DZq}Q+SVWB5V^tAMw%D^W)Rt z<wE8CHTUBu0SB-_#kcT0UEwye=gG$~<WDY>Y)TOw+-=~rB%HzJ^jZ`L%O&z0!8@nT z@kQC4zDnmoXIl-?gpwrh-i>>7lL}15!4dKM7`>wV8ww*xho7e0pjeC^W^ASpAHaf? z0noZC73nJOd!<;@8H2T-OP|YqKz7Vc_Yty3Z;=MKO)Pa3B=Gf&KbrIoHvakNDf+qu zrnJa>a&GmQ_L|>4GU`-Vsb08Z47uIM^=0bSSLDX>cOQP$(W`)cUBl_^Cj4ei&G}*a zW0s}m8)d<MfoypmK)Pc|X_=k)qOLo96^ipQ!DBRLba!097jo^@)DDM#<DdB1{tjhH zS7DGwtlUys)OIW=UN*a!g8YQ1(;_G61=Fp4bM0o<Xfi>6<CIgcN^$Mhqo-7u0oe>* zktp-d-21(YDy3AwT7_mmakxPVU$Uq2T~ueQG6C^KZjWsniL8AR&M`wbx{w_}w&6)7 z%f4&SnJG1t)XmWzoq696u-8u>@nta$Fon&v!aU}{dSmy6`_9Oi1x!c8e8K7zMp>MM zR_1_4P2K)Cim2mAG<L>>B{sc{u!SGGN$1L;iQuX-Fcgfe3HqN{dJTa4f~&~;B?kY7 zk{#14lf5w~g(mzP%pv@Qdwb7~qUUEfg51aFe>U!1e*~#<2JQ$fMJ(lHE4J~<i%XxG zQf^_}>bCAtR@Lo|p|c}q%U*~L><uJ3my%kxsW@HVNR}V1k-h>Q!0vXUp0kWI=G)oZ zqtLzsm$7eO(&f@Z3(22?X^x@zuXjCsy({BX))Mff+~iCAqs36<+jlE;%14Y&B79pW ze<{CicVWdiDeilaaes!C3n~9(z!=rHB1I>3XG+K@zqROKy1~*0^OuNyg;jX|*D3k+ z8xa)Dswg9g%k9Y0*CrsrI)hy`BSy&xUTQBzyGdXJa2N%X$3W@56F1LqHC0DKB(zI} zams8Ng0!cI*08>*F00laxC~x_ex-YqkFn!mgB$cQNSw`Wa&2=IZWXmECyD$SfMwmf zB7-~Z4bRX%U$)vI5++-l^<!rNZc|=3;+5!&k69x)FJ$&ZM=aB@IC`}w$%&`(CsFQW z=y$dLS%D6_jeysY=zu`$6i>?U@?~;6E;O|g^VNA!Kr{qcGGaQx(tWc$I3Y-)nT_uA znmsoRl;8Z6ay=?0_Oat4{yvp^oz_Fc*g<dz!<7l1!%bBAmzk4KPJbqI66fB{)48`~ z>z-}eBxCz{+e5Dxj}9-*l$Wvv_rmsG_su>5s#?WQfdaa|&1ste6HF&qm+qSXp@ISC zT2K7xO<B|8zQ_F55E#s~=ANr637Jthb&8tS`!#vd?0&{!{<(`eV40x|#rR@sbC+>K zk<WdSxOjwKQk3Ic#&A%}gGWHqWrlM=93L6=b#;v9HOjatR78aj>xKRsGK^UN@iG`( zWLKDW9MG;Kav7vb|7QR&qo{97C;qmdR$2}X39Y@082rk%);EQIhQ;=R&!Yd`OGU|V z(I@nH=BP2PL9-br$)pJj6m2H@u3_g^n;_sjnf~FBe+sXJ)wlEltr?5)5eh*JYP>1s zvZ(w^h1QMXg`hn{%-83K%S|^iddLTWvh0B+eXbA9d)LGP#Y>G=O~LuZ6hJRB-+d5u zTNnYcU1|LHe>`G5bAS0ukkn2ypCiJhfyd=b9ona0M9fK})@Pd`$#Wfw`NlSmvu$|x zs)yQ<p{!b_J+jc&qI@dlAOcT<z{gLW!`=!kzOclkkLa`(g}kaUyQy9nsgK8n;4h;) z!5k_1qoZya^7)E*KnZ#e)7n7T<&&$Hhrig*5uJG$^u;41zG0pHC6h-N<bOiuG_JT~ zz0?==_*KdkesgvpBi}Srdq`16*W{50&A0{qROf%fM${^ru-Eu4f{cvr05(c&t3fWt z_jKrICyp6;Q|0Ktt7wO&63f{)Cij6Sg4?dg@=b?&kG7#t3}{e<_Z;b`$IgR9ZH^u6 z${_jQYZ6FHLjF98Tk8j7@o2Y_V3cimc?#e;Jy;O_xLNY{5Pc;0Tq3~N^{LX5r$jD* zw+hYmG5S}G(8~YZeUqpqcFlPi`vV;Ga|8OsB*`bUkoy?^8v@r$QfnV0OC)=KlOk!Q z91Tup8^X}pAu?1&*CBgxMjj+pFUJGvcM~l>#v~33qgOne%taLY291Y!a-r=eoU5qR zRMJbU!K9$TbCYXShvwWhjB(1tV{KsDw+xPxAG<r7S}|QaO&I1Hk=fHClVpC5fNRuk zm0A8|_bv=}!<u2Zl8DhIz<G8&)~mY)WmXi|m=FIw7X9$J!ATFa6b1R*_8#(?=#8<2 zb7GwKUQyP!@Alk`-gTN+<y$CNMJ#rUw4*b-5i-+uDA{<^&*zK$r9sm(=-T3W2-?SQ zNwZa3k7iH(Vc#Ix-|!6<fp;p*jytU}Hj7xpQ{p3j9wuOZfN#xyNQcknmZ+VM3R5a| z`Qlh*&#)D6?0PIb@?9t!5?H<04$t$eX(qo)65C&emcaZhV2O|MkW;BunVKtT-E2KS z>?wFrNily$=p~|LFeAS~=9)iQ4DDmrTI>c@ebkDAiS{qpmxS;{p|ANll}ZHNE)ewb zO|}MQC}3N1pd9)H#5-w|z!`eHU+<w^Eq5@6@*u2^^gOCqk0PGgpE<g;*8P-hTsl{l z;g_N+51IZl;5m@m<S!x#Q`DV_Plg1h1d3xy0=;q3K2N^^$G-NQy?ULj{$bzuCzb(+ z^^+dwTb&W4ju#1V#YO4W+y5O1q&MrOP<g~5OdXFb8joREY(@x8jZF@0@*Vu_i4d-U zddcHlYTx{`k1M%+SU&uLl<RMV4D0nF>H`B7?!(tUOOOoqyUtlH$6Et77e0uS^-*w$ zkC+7MkjH!Y19!gSLm0W0a1_&pmTaRF#SH+dM^BE`bH1>|_Ti5vx`gpr1V(F(Ao4v5 zF+a07=vYxGW%02Fm5O>N>gTkV2tg&<@@z2%&+;I5(e~nMqI1M{bzAh7-esAv3jG>o zQxc|RZ?qn-xK&-PA$qjYLM>sx2ujBkWHo1qNzZqigv3{@5CD$rM;^e=DBUIJJ1VTq zk$#~R?UESy-ZSY*O`G5b)N0cQ$=-WifxM=z+u@#QuvhQ%800sPQybI2;dz?gcwG&= zJZ?B$&&rr7&M-$u=}8L2WRS|yVA9v;M1-%Unk~vzIl)AytGbg8I-@@kHv`^p)wFOF z2{McP8<(d~>Xu-3-{!MLD6Y2YPF}IoVloRBq93AQuxS!8U9a$@6)4VEhmSma?^Fp4 z+KMW^-{gp^E!iac&Vx@riR&iGIc9wMvnE~?=j@fS6WyTvURb>N9VM*aI`ioJWli~9 zU@?9k)fLy$T*Yzh2~3bP4_s%ozf%7FpUuu_6F#8fNqpD(E}A<0Him%yfJZU&CWy%@ z$!a^7HD1KbjPQ`cPivoRX{b%D@?|37^Tb8E!jY}G5JyLNM#9EfiE0fBn^YY#UA7!8 znJP1gti2=OuOWR;&sdOk8TVtl8RKrY*_qpt{C+&p&CZ>E(xrO#Mi=MOy>LXYiP@Du zyj}jxaoKgm6={n#H1VQg^(rT<+l2lYnj${u`}i~E<G2fFYN{)|gXQD5$PAh(J9e{7 zlF92xDRG!fICtW5@oUsiuW&W(m-Z^p+6|S(ew>jIP*muKXRf<|jS91Ve-xS7<at>2 z!MH+5Ie_U=ib-kpG>J&#6UG~BQIC=JstrX<In`vNe(xhdq|3mnAH4aYU!Hum-62Pn zw0@*YQdD${+qr<@s!hRit2q8dQE6kCtvqHl<|zE<?^n8+-&h0RXC@l&?{wuJ51R7Z z%qnc;W~d=-6W5gu7<FoeM}%#05EHuFqYX3sd|$pvyqW=*$fwOKY+T&;czs8mdoWRH zIpdlLt*4h{Ra1gG>2@*EHG#7pkI{_97?;j`jN3IV*Gf#7GEi`2q>&M&72ohKTu0rz zY`to_oGQn2jjq&k{&_4Q4!enP(sMh0Ycbs2@+IT%_B=PzpfIra?v?|P*ML@_*>^Lu zm8U&EvcZ1FOeYu{OX`kQ3Z4i|J-M#VU@H0T!Q7gyWp($$ToBLh^WMi9&noc{x3Z)+ zQC7D1re8rcNCqr8>6a1MikV*-%Sx`0<l4;B5P=Cv=&Cz0?OOc@Eh}jcDc##;1q(SI zbhV@-CoCs&UN3ZrF4cC>L|mVS*RQ4WUoT04Lcr6shi(sh8xzQ`>OV&x$*H<P(sUG$ zD-U?$Tl9<-l?{`wHaih|A}QW6S8g9e@aslwM+^s%i&fc8o#SKJx|4c#Mpma^tO|JS z$TF~#Jh#PQKgU~2DQ<FBBI{c!RO76+<ps(zrh+^LUg<#*>~(hcteO*5d7YX}`F~01 z!sZ0MPFH<J-gwGC$rW$UL~Zq^vI|@H5NI!q3d=WEte2KbuNlL53cD&lY=j#H&B-t# zi*qHqUdrleWH4XQFRD{E4Pto+*y?ha3kUejoCL&Aj}%<m@*yXEB){y=6`@Ltu?461 zm*%&1OOU}2%xYKSY!VWYEvlDV{QXjM1@)=<_Ev^$7H3c23jm`+C55?u50}cwr@VU> zPBgoen1rOSym@g2i??}zA-Hubz|5mH?%JTI0xbuEA(L8_ZUJ9QT7Nc5&IM{p#W`_; zEJEPW@cH+#^_9VhvgXVdVW-+}oAn!C`5pbjSjKH1uV=k?Z{5nGEG_tsxQTy^Mz+la z-v+LN{m(J(|ClE{`Ci|qU5w-A4dr~JPOAlcJbw{(BarMo##30g-lGo)#E)w#a4UBG zUQq#8c)Rj=;aI0Sem62AZ-)VU6#JV0&+P$U9iy86_bmdyegArg>J!o~zC7Xe^dzka z%tI~*OM#WHaUU>0;^rLoULd&z+*o-2-=ux{XoNw}(5cGX+%v+q4D7J1Ao1^X20qQL zyd!@z3F{%nUb_6r(WoQgDD|g<$usdSwoh-Bnhp6y39J6r-UjnWU4(#eXsgRWgYm7t zw{AUs_4kI?`CBv`>;XNfGLY4~*0MLz)0`ucNlRT>&`4S>C*2KdtqI25HlMx>&f0j2 zM>*A#q$Qx$v}8OqHSo?%2?*-yub?Da{=Q_&B7ftgx8P@%$f_B_Vwiq!ivjC1!GTBH z;AU#ncMwJm#+Rvax_$dr$MfvJAF6L38$SDDq*`8XqnoRr%|I(-8@fb%=Nmow9KE_H zaZsRUIHb;@378mhrP=kbpiV>8>0yK0Q5&_uxy^B?;1UtuCUP3{>IAz+lqo(S=0w&P zERtR&TVr30SJ_yn5I;-v2x-qoQtAKU>Rx2Zswjo$^#G!#q`FN44{2XuaHXBz3(Y2~ zR`nH)YODMp0&~5Y(|;VDpKxpSo-aVwbr%jIYpOpOdz+|+1l~n7I2BcgUl|!c850!H zS>vuNtxiczmBdin(zM^Jc(Ea7rh31?Uwy{pN}1z_`v$d$teBd3r#Sx`SWDH9G}?B) z3V{t3vyuCxbuEL*A(6rg91rB)V80)E18Pv$WA}Zer<~OH6Up-a?|S9gESew2um4L2 z-Pk;^6%UMtOiQM)gKsKCb%Y_U=fyb1HUH~4H7d8-oF4e5ihntXgQnW)0G85g_-;ry z(kD#IDkCfUX04)^j<)sp@~izy2B)E`3{F8AK)Y^v@cHMR)S`*U5dMw6DCowq2!a|F zU^FTDVds}9#SE=mEXWVbLt>`{rREW4lr9pLdBAT5-*}F;Z+(W@U4e>n&@>JtYfbqW zj}{Jp`thbS`7XKixiNwy$igN-4Qw;C6|QasOOByJaUdF?7DE!x#+gMQUG~b_`YRWX z_>p>)C+gU`|M0l_-l<MH4ThQzt#&@V=6|CzMn2ftYiK{zp3dKue+in`CoU|7I2s1i zm94|DfdxQzv_V4Hq%alGa-|rQXc7x_v_amR`sWGJ+uLyOra!m(1<iK5T!V6u@&iA` zlor*?FFOv=M(WjC4BtfhsCZc|$8%Oyenetx&R11{&J+*Y=2H$oJqrfop}i-QX`_4! z?~o*Y)pVR}H`u@JFOr<^vUCy(N}@&?{6^Tvg9n~K;2NWTB_qF8GvqElgBYE+ck+AY zM3%q$2<h(bFlf(>vilV|8QKi(r<)zp)93C6i5TEa#0YL!nxP$sepU@YJ>d`x09;VH zeN8u~Dro!6V`?4cIU{_eq-e9SvVT08J0>jwPm20<M^B^PsE`V!eUG_WOuDeZ2|4sV z4FrvImQY3`ntQJ`iRozyL&fP^7mH5wMilz6JT^A%t7EjRbPGp#5?D{Xk>*eCd`?I> z_TLWZZDCEWYK%rB^9$aIRHv+?aJg_q!0*~8r$#REyp1I*basn)=mc0?SOYF0H2rah zIJdL->p&ZxM)!8}I#r|ti}1-ABBbN~&2{bE>{LWdIdI*ZOh(qAX|KHGfu&a|4~+IP zesGWeBjmG0RdL?%+3UKQvguS#KL1^-p^09x^1-}%tj1>m1|mp{lBHhJemHS%chQB) zMf+%sj%YTWTzv$g@?*X3Z|{_efUSjnCyiAzEKZ^qm{VO-pTBt6!_dp4v3`Mk_Bt>L z1W7zrX86drX?Whi)grwy2ed-2VO@|#U7Gu}rmycl8;3DR{CHXUkpSh=G&OISX=U{3 z`GULnzJO(2TUp5C2b+Nz1$9JHxwKYcpL)~HhOC07Jty`NeC}M;9&Pz_Wp2l@7P=na zO@#Jco~u4<2U&jDnb2oL+)lQ%uc-G>ol5DxxtP^&f41(4{T}`S^0_76!M8-Os%fc% zBZjS)=-6*<2i^GiDiV@8U2_V9j|*U`(`?PeMn`HlUj_qk04q%WcqTfoLzfHS9J(V8 z5^o-+`PTmkgV5xC-|PS{vl)1Yy7H7}&*(z3-}Zdf{DYoGaaa0T2uUN8XTSzAt<5qM z_k1fD!*gC@uH%W0O`?QV-q}0~f&?b!7+~1QFD!UxaKe92`UFy+BW5;b+*8|@200OG zYp+q<`NNG;CJXggKXsF4j20x7W?kQmrXryZ88MrJEn|?jhm(qzhy?Nh?;M5?yJ`2k zu-~s*UOmLLRJlK>9KJOwdI0;9^mi)g)YD>%iz@lpib++Nk8D6uzvCVMnF~(nIV|YB z1pqScw<zHGnwSwK(4pHLyG^NuPx&__&CpC^Uil!#abywwIRcgc38rcNYjAP}!@ptX zOAk+jbZra^NlM0v+GZ!VpyxI&h2H4;wyPJscpQG`2E{s%=MvuXt9+Z^;ig(cUR)*d z=)R2#)x$(>seQ)nG_+>Ed_zyNpLt%=jL%AvF9~{I1a{5j>ugfwgDHm}`HLHc_kf+O zhh|QM)&#db67wJe`qMGL>mh|-NpGnz8W%6;qTKadvjR=w*>-6OgT|m+RKEY~LyKC3 zn@P>lSVJvFR-pI;my3UPeD-nZHEp6spDKX=h{0Kiuhq<WHP%<t*gSROhvs0(ps-(a z+u!A>P}9-ZsQm=TOMRamwXLahMx^JyAW+7b*Tz!M8GyW_ZCBdC9n``ohrW=sDT%?# zopR!eZTncg*_tj=p?<kZ7TGAbwkTea)a=q!86syYBDZ9Qk8mD3u;>EBqZyxW@DKcS z*3BZUK1XOzB1dAI18w-~9{6@W6ZuJJJv4W@RxQ#Hv&~akx7Qw67B;h$GQ;6PgzFO> zS7DsJhPKV1_WWufVSG2cP39y<U}IUNGML{NaD7W+$nqR{x}hB~?|!QY3%U7o=5XN9 zBkeQ2n9AL_Hl-j439v%9-o+63aQ-<5nI|@*pHrvKhe3D^C7fb_$KZGZOl!p?b<H2& z$ED<X$Z$^zqm@g@kdxe%kO$d+YAI^Onvo+~>*Tc#g_K{HL#AmfD7lI+xFs-jzH4QX zJ{8X=@67e6>+kIf*^27lnB<oUxKXqwX(3E#d=7M*Cj0}HqU|;##p4CnBoJ?AyDB5d zDj3G+0lJ`%%xR{wO)>x%Bi1b@opVkrvf!^}ren-&=Kue3_TFJlwB5U?9R-9}#Fq{# zA|N0jJ(P%ofJjG>jz)@9ArwQ4qJT=19)u8jFG}x73sOVxMQMT12`!Ma2j24g_P5VD z*S^mDNhZu>%`@v+>t6S|S8n|gTvv0$GgsJZ2cspRv6BtLNB|=a42qLCWiA3Sj%n<W z?N8x;Z{3=ufMD>F3f9N!0{0EMQ#*7-vH5?t9xpwsbd&jEa#dv_<}MJ;@<k{dVPTqK zz&X(^i=WlV@p99sTcI;qOUVoKDCd!w{$R$%Ln$+1Un67bI5_$HJx#dEvIIHp-9-up zi)tofFulo^K)@Cpy({Gp@)j^`Ug#ez(XYS#u&f+d2#o5msz`ONB10fF9x=}I^nPs& z^n8W4|3SVh{bz}rbh*py&_h6s-sMx{BSS*6*U$LR#tnd4#={O>)=fA1g~@{gr^>LX za|*XrYg|f`J|ZJzDCnqMSg~=X4!^`Pk~lwe>Xfj+(v$v5+(CAaq~UT`$(2vir;=@c zp>7DDls?$KJnu|F2UvM;OP6kA>b_%uGNA^FRN|uh$n!S<6*&1qrv}fyd}+0iHmX$U z92TwVdcCO^%tn~t-ua4~i9V3p!C2h0PTARI^XCs`t7a1L*`f-Ao2zY%Q}mm#JYKD3 z0r2wLCmmk;vwe{Q6uft7OT$lPN)sZ^o+Fu$x{D&m`LXfoP{iG*Sfj*QR9vJ?V&efY zmbEPu_RRSqd!Z@&%t+kMIpk}<JR%s}4#09pjA)-?O=*>!ybl-n7g2E|+ze<g_A};x zyacpURwdpwzJQta=i@$riVE!!&}+=wcBGb5rPjz_#D~uBOlu!tI<y8L!bfvuPhOw) zf$c04j1{>|(h?;Ca<%^htTW_3QqVGZk~ie^4Or~ydLIE1A|0DpX0sz~IPNwHbx-CL z3oIs(P@^wp8pL-U<}2UyI!YfXpHa`x+*#R(3WJlsi88T4tIwnhu?ZkItXLgIb};H} zc)?}=P@cHr1MJ#-CV3(UKCS5)?ZHpO_*FeN@XT@m+}!-aug&Ce7zux`IDqSE^y=EZ zP|TK9V&Lb2rAwZ6$v?pS6KLLRK|Uzgw-hCt6#91hnWBNgVbHt$qLP*e@@@wXy_!p? znS8OXgy=P_lgwJddr%>~e9ebXS|~C3NY=c9ODVShtVRL>TVPd0OZz9=(#!3;$jh<A z(byH6g?sWP=4N2=Qw3vSX^Kzfi9yBAgE4)ZO9q0N-sPodp&xN{PfN6V+Z1$qzCL*R zSN`E%tM^Kph-RkHTIqa-bFK}8H*#*(UG;*oBnt_2%&ZqC>~FNs*D7jFM*(#`mQP=W zZJ8Ut&Y`6AXc`QaW|Qtvb*}lCl>;^sttAt#OpyYrB>Z?@5xnbMoYfX*5E;zNbyf*N z-ZEk1i(8`_hHf_eW2>=!aZ||<z?KE?A#SyzQdFXQGsBAXQ^_l+xY#G;XgdYwUCh;v zU6<(E+2{A7Y;w+S^p;!(1kdj-*!kTzn+-U8(WCol3l2b)1zEHx>iQ}b0sa-?81BP+ z$d~1`<CjSIJ%&j8pAHjM^;w>L1~Kq*8Bo}zaT&!5zo0u9Ia)sT9Q>$2K7DN6J&|V) z8C2#fD-N4xNFTaBaCkqBgk0|jLH0ir;TOs8O!Eu7*uZ@mtA_4scz0!6_IzNRs;eDY zWC?N<Q&y;b`J_@a#WG`e0$x3w1jCIRG4wbix%(ytF{K2rn-h;BwU$UbLP-9Jb2<Y@ zpsO}~)dz1{dB$Dy?|Czq!BaPymSu_uLXYbAsq{Rcf!}GUN@R6ji8ookHM{E0YSn_M z`dmr3V#*JUIh1w26|u`?w8G)`n`){g_`|fH5ESb->RC(9X|4{|!*2g#30kmXWp*l* zOSi%*aWkp<I`>Bjz4zN>opLnGWV_p``FPJSQuBQ5uK$%w&2xUSocfNxN=wqb1}hSI zSyysBk%eNB8dj7fB}&y#1SL!9zDOmI{d3@7AWz?Q?YT6vbn|zVrjq!5`;YKIr#B6p zZ;%U<pgOQl(1FdjlOU|a1FfukjN<{OaL%$ET$!IdHNH(NGg@|aOfoY6N_yu-Bcqhg z1f?Ln$)kcg)y$FD-RSe<*`(dHxwC;Ka(Ws8kf8$3mohY+nO{96Y<QyF%e5Erp~y+w zJbQFmq60=?X(04grolqpxIZGLcfZWUdMGKvwRYHZo2N(H)0N8GSd9Y$!Twe)Muxus zjkUaQWHi&Jk(i~PcixxV=Rs*A9qB@k%Zy0G-R7RMuz`T4D)aP#&f?stRj}~Kq%q4s zZcxPB(4Q40zilRdi@(b-e4UN{WgrpLdl@ra*B{tZpy#^jv<-fLvj6Coi`|VZ_GZ4% zHcN)_)*1MOkb%tn<aqlo^ElJ~pEKm<=#!F(XA|NoH2*nA`{Ic^FGjjV0D0!A@jv!4 zVmm$CthE{d;&O6`9Q+?<Jw_dlj~~4!p6@@=m%lzZ^)}_N&GEmG3-@Qzyp+$k_-cYq zmjV#$-zSTdo?Ky@Wx7&QGj~pgW(orYyhZVDhRFD0@6p#{&!5y;#lOz&4(>4-Xz8OZ z7)rhNC~d6^ufYyz7M;?*CMmhtjCRP{(vlLlW`dLpd&gM5eP-dicsZ0y5;82d_z+!N zwffZm^b51gjkR^6!jg;U(X}%O&*-|xA}{4I2qaqt1?}*vizale53$c&;xJ}^{?w^~ z4<|t`X9HWM)rd5PlO_IY-t`EFYtUS{`I4VVMq16Ey;l3*erGaL<gPf{09E%noaeQv zZ_c^0o+grUbjF>CYavGC2nl3(Q*peg@IC9NS*<qNIoMaz-Fo9=`qz?{yUJ=s*_iQ( z3eNJ3Ev%qSj7wmF>7yyjha8@r)Vbvm1F&I3o7Wq)28OcsW$a|vT_xU0eT@RN#^kSo zN){BPD=rjP(ZP@QNjv^|vySLQ`z{4tP-p{?an>}dgo^cdM1D?C!f+-mwb?3@TpPu) zm(iv`<U0tTw(Sx{6Tbo9yD|6lFm%EK>_M^Via-<nx9YQ`)bq~Dja0oVULc_5IuRNA zHVZAnBbn7!-Ud~9bXFygQYR`~r+pi=eP4+^4cl@sV=PFcD}S+bK`4<VQ|((q5;1Cv zWm+B%3C>ph3+<U&*EE_9iN9xjh&{(Ja)4EA!p+{QB0}?xi;<65Ja5wl!_7@RSK64N z0isgp7EowY%dYzBo>#=f)pZ}n*ajB7H^k$$v1u!!f))C0kz`Yf>>ljFmPK>%b%>^K z&F%6+_Ez!34;6iy5S<y9Ef}7>GW}lLiYS@)7Yq%?YOz6+24I>7S;lRzY%&i4(w;}; zYV6VnxWu9o%X{pu<v=oOHI=TnQUG4%)u|Oics7=I?re)DnmC2<#GTu|)ZVOhfva1@ z+8*L(-IdXkGiQM|&9}${=04M8%7o@61JD7=Dcf`4X~()%5d$qt(TEH#t-6q$t*KyP zaO%PnlcXG`yL2LpHz9?deo21Wyf4a~#r<mU2Al6o7DoH!QHvm7net*JtXn+2r};)$ zq4lB-;)^P1(}Lhs=1{I0)QZb!-ryz7em9xNXlX&8(%P3$`HiU9fXKT&9%Od{F}4eO z;x8@84MEEjHOJ%~jQgl4?01&Fjek49Rxsl!Au?u-%q9N)l_KO&KfPgtm&<Ja%ULX9 zGYI<-nI42Qj!CFAzy#;FMz0&(phHu__|D^_DC*v#6*~WAmuCn}2^@EHL5R)lvs7UX zo#1o&`=?iJx_r@H!xAA2FfSP4k=X;`tht&jw;dxK^NiTyYe<jwx7n=pOrfJ(<OUla zw_~-IMux^0*4gB+r@@nwN7kO-H!{Wu)@KLLKN9vrih_q5eQORel81AYmsd_l3TDLd zD-_H`thrZ^uab6ZWwSRQ?`B7Z$P5!g?e(P}(AOpv*`$dejiwOcY|vm=CkLx8ts(ho z!#(51U&R@I<<skOEY3tfU+wU^>8#NvuBB8@8}q5JXgQM<=?0NS_G{h)JHAuFzO4wy zvlPHFPzH(s+135)5ITuPeKSk0{JgY<$CIb{Vjj^08UxOG6T}C<%_%xhdcwu6;Jc}2 zA!E%5I2$xtQ$@fY9pml~Qk5ce8PJXnN3uw<;8mu&yZiBn!Plno8NbGBbg<>N93~2{ zy6oSCLtdW*KR}iwS%H4JQxa7tW5!w$)8Ul5bY>C{AmZO%DRU8_8jTny-LU6d7;l^+ zc4KFPvG{Y-yK>bo{FV4-?$n$sal@n|n~<u<M{|7L_FRF5*GZL6|DX^#AW4#oE_Ljr z%<DK>id-*%K;+%|MtA~ol3L93GX9>JlqE&CU+}eFUBvJa#Rp#6ld$`9?ymfTMU+X^ z>2w#XBi*`iA`Oy?m8sc6Te~f#+QdSOguOpi(7>ZQ*nFAkLw=@gj%TOLO#bxtt0^hc z18i)W8x2JPC~_vx6n(K-+H+iqG+?{abf>xp7S|)<$&8nQcnq~p{l3?4k9Rn;{Vmu0 z&5UWoiy*#$!Pt(dZ}Elk^n+qy!s@aXwp~RTPUdf`;|s+LgBqN=5O?3~QTH>9e_Sev zZgOJL7&9jm-qbl(`*R{BtGngVrm0mwn@&ISeA>3ek52jI5S!4!Y>_)b)EEp%;+2@H zbU%#on|tyLr6smlrx-qdpGgP)^j9y9Kd3@^<;V5E-W#09S(F?Di-m~%4VAl;MEL?0 zbpT%<_&iJ=GZ|lm7b*)3CY~RI1&xCzp7gZmy(og0M-s5EAq~AMdFR@b^S_$&{{+n5 zjul<2<yr!D0ENoLVKR)vy+FXNuQ=3eP!~t*{6)CBuf1<P9&WD8qzvzq=x2(4M1LXJ zZ16Ix=feJ-N|J$5GS4Bls#<mWvD!5{!{no7YV@1uV=J^n&$E&#;_Gc(L-gBgij*pC zn~=)@cSW~)z@jRBDDd;9WS!#V64-O)!G_1wi;-JCcVjrlOIIa6oSrqSzQEaM|JM70 z6JgiOW)ob!<J*Oh-4)wUJ{*mqwwNql9SYPPeM*{VAk3E~CS+c7A1L+t;^}#m4L8@+ zBj>buQbp{aQlg>AJ&fzkTB<FrVcaqB8r!@W@NP^!IUVrXidIa(<E~4l1G>)tTGZ|} z&wESKqO%x_4ew!9bAPi9f8#zeXFUO{V`J1ji}LIjkc`7U&(_HKUJ%939XJ9mvhJc{ z?DR_Lzh3(K?Mwtj&bWM&A?H1I7O*4$+&-HLoH^$VAt@DAQ?$s0fa<sLSqXxMY);ws z2^79_wj5?Uo{Ol^!U;I9AuRiAK;sMh)=y?dvO8&RF5dCxx(cRo9g=HknrpwR<EDeb zk9IwIxv4%DxY3j8r@|?k!nZAQZ|SJu$_6Ty%04<u=r;x&mTs}_7}ZHBj$am`_Djl0 z*jkAhUS>3lC#qmm<#)CH)`~~|$i>8ZL9r8uV~1r)x$sGZ;kidH+-AlWg}hd6sxs#3 zaT0z-&z3yzd9}J(#csbt@m(JE2V5X<{~9$KabsK&ITvhyqv8fMhNawJ`IbBNS}(iW z(oe~cF&`n|<{DB)LAa64((C%bOU(Wcz{pQwzuIBIaU=+(nxpp+O71*fsO0&X*EU>S zoD>I(Yqiftnx*)ockYiR3B@pq9ve49XO5CPW|7a|Y5Q%8>3s8Cy~xLp<S@Smg=~u- zCX9UBkBIoUB`8rX9F2>;2y1Ki=S|oXGE9DI9F>(cXU-^ZsQ5|h4&T-_YNgdta1p-{ z02kFT<VoHKfa$Qyp|Ao`_;B}NAt;Jyz|<~#t1vaRX%U`fQr_vd_s07V%W}6%dGtIb z(Oy3<fZiqMDms7*2l|S3yH-dzv)ElXG9fB8nQ6%i3#c*+B!WaP8$BdpTU}+L;<qO2 zbwA>F%+a7VwzsdkU8_}{Odo6%(9D@I8huw0f2g0<beM~m4aM$WdP)wsTV;cL@R6(N zRp)cG;2`~Qxlo>?Fhx$q(@uCKXPK#b;xI5O?QEtDQ083-WnF%iGTl_EtF>ma;A2NB z;duSpUcPe1FaiVJVd!O5L{9jFCYFZ%phEj&bu%EoFMng-D~2s!$LrvCtuHnKp=oI< ziVRD-swfW#a456XYV2Gji?L=cGX~fIfmj;@{^brP&)&9b?(7ZNn=e-mW$&FbQCCD| z@}>E1Vb1pWq2-coo6Y>&E<5Xwe>i_&W7}Th#_N}v`jm;SMAc^CxDQ4(uHO5=dQ98y zQ022HDei8$1^X?{53gFcSxdIvNb7?AMoW^r0KrSvEMwZrNHb-d&GuVXxczA6RmM?h zk|w{1ywPJOxhx#Rg5PfZH;VY(eRAeo(YJrrYSR&n>qh;)lBbPFWYlHcJqFT-R(5Ol zEH~Lai(Jo<9*)%228cSgFQAwNB*rvwl38|$_e`=fAj_`<!(g!bRKCmCYR&L=^FK8d ztV#IypE;`46qWG1cgC<g7qpqVeG~Ms7m$ZNBWrTBf1KnPU9O&YPJ!+uuPIqfy7F!T zh|y`ld}HU%UeToe1gA4ncEW~wRgk2%gG#P`k~YT9R4Q*s6y4z{EnwUccF&Mkfyr3^ z1ka@Z#9fZwS_R4ANITF#IH$HT7Ji#@A^p3*CR2%<9|EB7aV;s3ULg7Qh8+z<LfykD zkh)^8O!Kr+Ba$P*uShl;bMLTh+@cX5hl`!OJqrw2IO|sU2KpiveR-rBU8||{5j;fS zD|%}d0VEZ_?oPnTjJIYhAH!F#*8M!Kdhem|#%htxOx6nMB^Sw|>PAix;LK4wKUM@G z^;uU3!EVKNruf<*#i%UNlAZZk(~Qf`jeFae5p_<^j3-tjd}s*XFQ1$C0svkYKua~1 zRCuP>0b1tmP<?3=dHhQC=(L<M5Gx=_L-ZCp2k864Cy45NZ;c-8YeKn<Xk$tSJV|U; zlU`TdGY?fEToa@raJY(U=AjFK`(^qSBrTg>Xi#mCO=D&A99XJ@t!z;_)1hfhZoJ8P zEoLUcLn?^~m3zGJ3zu5FaZE=WK6qb_9AbgL{xSC0Z0WjuvsY5f_UTU`f#si0`9TK2 ztIc%wioX>N5>%hHFKjU4+;Ic=5T}T{)8oBmzrx!Uwnk>~JvR`gF$kyA-$upk6b@rL z&3Txmo1Rl)am13CB&fXXM-4NJ27{TWUAWxpZ9=HCn=`^`HMebvCi;R8hdk$Hl&K(= z4gQ+RY@IVRu0eCKIoJk(lyBC+%iUkZw?)p;-@ZY?zy1eldmnMe%=BpWXwtCHu*e>$ zv#bjQ0K?+rne;yruzkO`FcUbTMMtEIhk0(x3(sZwg=?wH%e7?KtEWdHd&4|mJxhKV zS8QTJXNoH9dYgknVbm14Z^v;G&gjt`>yZbf{?1TIVxd2se*Kb|yRu_DP#%%3$)TCb zP(6~k#KU@jRm~Dkz>ci!MDAdOM_Q^rXHasi$L^1ecJd^=e}!g?eljO}_z6~)x)cRW z>O^Kv&&qupy$^mi!U9cH>J>YzLTmGwr`Z;6;NolrE?)`)N=W&+(9Xr}F8HAGMueBp zl=+w1C#U;o^!&FBRTbt?jZ0n!3DxU$O3oMSZ>yHt?-*zzCSXTDz#G{?tVMkby=&D= zQ%P|R_W_8O`{aGA4U@WPum_sUC(HD!imt-|lmKv86!O?a&s)(2)J&dtVcIPZ>m2r6 zuHu<xySDAXUugr;*Kn*;<#0V`(S}>u1C?!*e9msJyKGezf#G27-EbY(<)=V{w-L)m z-L2D{fQXA=0SWK=Idn$PCD3NMe8n4g!)B?VS&N_81=Lr=ZB46Y&LInQ>N7yX^tjcl zg9OLk9<HIm@cCQM{~)|A?v`?z@VvL!3@WyGtzf4493OhM6T`?|=RG&Brd51OaHIdy zbFN(!{Sp#c$KYN*AQqM;P6o=GTq}mle9D8(Zi^a^E4SQtQOI<+dY!#HCt-hUeL*nF zd3kk5j)z#Kbk$Rr5U;5?Pkd*yQnAdW>kr+H+L`;sgcHEYl}9;n9bh@c7sjfoL5hZh z4ZV6t5}gz0vM>7LF;3*mCiS^;Z)%k!`A#<9&ztp6Q;xYEf&7%(_eA`R|MxS_+T|Z0 z;x8<juhiAxUp*sdvUmbXsxs@QCFw_%)y(yqhxqE3<3HmU+z)Tmn0{us5TUiS={p8v z*kTW0O<D+9EBiDpCy!Z{<IU5n;{R!VcsL5)NuMJrBBvOx_2^MxI&jHrUO(tqH+Oui z+Yi5iB9Hi<^VC7N+>0IWQ#%h|%|^Pjk#Foqy}a8!!pH8C1f8xl7Pjy~XiBV&X~yw! zjc{=d)>z8M07%EVT6M6AMO?(R@uf6{oX)9zd($cU?ZQ7l+SoBSp50+2dtsSye034u zBXJG|Hu+$;ROE>Mc4*qJ)AEzLp0fjqyKXDKA4DzG!+W1;>9Cjg;Est|5$EWK&W^?S z;>ST)g44j=5%q`m8C~a}p0u0%5A>8t#OL;VCh$jO3MJq??XF>|VH((hZw{F(hVI5b zfs0;Av?V6P)Z1_Jb38jHe}voQk~5dJ98zZUudvr|`u1D-e-~_~iM*!o$eo4HN2$hr z_wwTM_V7Z6GW$9GFnWsoJw{!PNC}%q>j)NnvX62+tNShMD+>;cF#sD$=(N$vR;ul^ zyuhaFX+V>5xFUvjgVw-#CuYgdMHQ5}o0S&R{$|zW@|Jw%tteQ)`68%dbdnHYtOeGR zB>e6;-14fAT7$75GlvI?MscR6-WR@1%34V*OPfPk=a;1VQCTF@<YthdT0?5nnU1+E zu;jm&&A)hLb2R+IKk(S^|1u8%WBq+RRR3>c)G<Nn_y~+Wi9!B@r1TFCM=SK7AfDwY zOJ0K4R7m#_m`+lC2ScE;aX$5bfNdtzW8A?j8h?g&Iq3-P>IKQr4D~k25Da-9U8#FH zeUPq8+j&r1>Sdj(lVZ?vlPVN_H%HbAB)UkA{Q<^w_nkT+03F|!rR`t)6F?-|H{Jg@ z$Dc6SqshBs*a!|EzPUXX`^g2qV0@?&@Q2v%^1(+C`~2lgm(7DU*muQ;_|mor<6^8a znDTVB!@KdDLV1PDH_D<x?gQ<^We{?t>JL2gzt=f+<^<`65uJX0HhU`P{qm(|zJGd& z#E>JgB(DURB4U=o&iX5}o!#+*GQex@H`Zd@u&g7)iYq&DJ>UxJP0hyKsn@)rydPe_ z)5m}@9Kjc{Y8-Vf^QsM34zLoTV}l5Q2=fFB1czh22<$nEY2y=viAqr|?O`eF%aB+X zYoh^zxZwBLI0@@(kl}%yZ#}n-dp~Q+e&-LZGLW!N^H?ddcJoaJ=l_;nPhi3OK$5Nv z8a;v+vB|H8HjKE2ZR0-icV<^OWPggiR$3X#(B?ZvcD&2j6%tLxpWz@``46-nYPNlY zIu-)lpYp52us}_vgah1%I??ir%ohy?bj;fjG4J^WR`g2%9_@1u=b1MtenzqP7RPcM z;-MYIf*Avycz0^!dJB_t8JkZ?#o`^~pTb#f!ea(6zu^6X1=STQBR3CiVxprk)wtB> z$nLAW&7p(wj`XHA3$QMOFn0*>IR9lJ@dS%`&C-&`3;=SN@yeY8?5(-0SJWnGzm$87 zSpQy9oiA@a#HxPWwRKy*odpjwC`pJF_%JcPINEO)Z{=K|$1BGfGmR9gyZCt<V<ECg z4XJnTD(|sjV}@n|1S5*W<R22bW-q%gE6Ow?FiX>NFFgT&AZ|>4CpvN7owY*KSz^&v zgMP&{^}OSiK|*b&PhWgLVg-pNwj$);^C#qtn`T8^4JG7rXQw#(G<i+}1S=JEt!Vau z^xX+IXu4>e$`KmiLaAxnSig7-DU{0LT4#GQHi|fb0)O)3;xTKO%m?(Nts`*q^DYb! z0hVhr87|Y18Egva+3;E#ldbWQ4!rp#pEX_ZKJE^$1ZQtS%#EAq-WHCksSpy-4jfNl zp`t3;tBZqboLg5Qe$TsVc6M;@L9(PNgp?ASg+W#v*9v3l^M>+^k5gP?T*Eq~7`O_o zyA06msRCCkXu5T6I?c0O9vsCL32>&|t&Yak^5|fljq}VxVG%eV`R^AiOw$B1o=F|M zjeh{6_%mOj`p%0%h4t|Dxap8zTbRsOwOIx^G{7`IXPVk#PjNH4pb$@{C{q^7q=X(B z7AqRQWbNY|Z_f6(8uogn)Sv9+;}+Xd6e{x*VX?dcUP<Ds6#(Ct{lzd8e=WL*1+Q>^ zUN8?0w(fF4o7#14DF&ce@lc4u-3$jpxu_=_-V9>S@&r~-+kXZ^M>}j&Wa%3=c*uT3 zT}Gwpd0PFd>_vd>5M;IIH^;t@79vtHW|oCKpz@Sl+((-Vve*g`m9}j%MTP0c$3_rG zw=P)#RxA|VkXU?_v%0{Ta@hK-k}{0gV1ZVO+Ni3)jZsb4kBi$Z&<xQA=pm*egz%+) z**<qdF0+Vol%5vX2l@C2>AfS(?enPIUBr2A(zV2NwjC5Neu$Q&cJM1Yw0njH-?5?6 zt1qOo!)#FY9(s1^?;pUuns#X+<|z+hRn@)ri6AXp%4nY^*HL+rkpoMY`!_#NYguSP zA+*nVH+V00so8+}-tb8L{GYq;uI_HPJ_fLLr%g%s_xN3?nEJvW8iWU%gUtm{>(m}e zMZM6OmMnL>!@2=_wuLm;kzsJd3?eJl9cYLA4sok0D;0H?vgR^#>h71pTO->RagncL zIa_?xY*dfk>0itmpgFg+MRPdBtzi-k&MV_zFg2qjTHErx<3(TnTA@uO%Y1B1dVFrm zf+F|3b59P##JDDy{`LcN^Ad_}Un#tkmSVBFXuX6Q`4TImQXylZ^JJUa)fYV2J-!_I z0LXLt5Z15^=jRw*afi7*%H64%I$1=0`Fd@6Kh0n)0A0CX$|xz@se36LH*!e4uSZTd zkz3+DYG=bpE<UZ-V)NW88iDwGGv=}H#bVF3$<vxSt)UDflt9ghiCyivjC=iTdFqq7 zCgkuPhqEbJtIxX_0uc2*`#HOqa9nA1MUT3`V-2pmR=)LfsE5-TDiD=B*%G0i=f8)w zk3Ii}04PhId?>Wxu2avlrgUk6SPGT-L{<e}QeF<3g-ROQ`LUA$s!Lp?`515`%|+2Q zTNFOD+a7>kT_TD&7T8>sK;Bij`ovV|fMl#i@yWmm>L4)}Zp#?70h9Gq<$IppvC_zg zd#uzxj(akKtD=ad##m&vt%nAz3rk!E9>JGK$6GK@-o#~}ZPk}PjczWJ{a`It?4nA{ zE=FSGy07G!vD?pkie8sQEuz+ToJi0w9o!1Z&(&+wF88Rbot7`E)bDa6L1zM$R%0{a zex|qs-LVGjG9Wh9pjv@9<a_a2pdFQwkvx-Mxj<39U<`0Iu(%6rPax#%gv=rT<<7@C zh4bl~j%z3jJ}tk1^`GXMyGD;!@VBSH)A<KnOT0kP&5C2T`FXKUXDct(ilMEp3~sLe z-P}->s;)z3-T6y(t&Z>63lV~3f^`6e)QjNQxiu?`X3z9<ze$FTi-~PwygQnZ1zkdH z(w|@&l9bw{CT(G<MN|3PCMqPX2PxGNslY^gT7B7QugHDtb@8?#`^q^XcppN~{mT9g zQle4P6{6o*VwbnH`|y(-2nZOi!2gTDY9{*|1%xZfVkcX*(UcSO&MMzR&ep}c$f^K% zQet;m_tPEBcX6h^aJ0RKqpZSnyRxK~nesi1-ari-T*PqOCTa}KWSb;(ypT<x(fzEZ z`9D$az{G`5=`+gPUF(%{k}ORe)ngS#vVhetyQR5(H-GG_*g16Q@uh7}l~+Y&ZgJgD z27S3qR(M!_*lBo1!;St;jZzDUR&_+>*wD+PX1RXFew`kBPdO2tiE^CaK8}6LJPK80 zIRf;{t$?78*@)5vEBd6oWLsuIfFuxX#iTU?$q@o<c#%izK<L<ldKfKAIyN$HMHwM= zge%>}2&}wxMfiF3^g4HA+-AqyS>_l5!((=|kF@J_x2P}MY}(5|gR5x&rtp(mxpe)0 z34$@&ZEo`@L&K)fv}*|@^%KIl+vC5N9&#Han&L3@9dj@15G(WPlwDBQaz-8FkY2ve zy3vc!e0!ZYL};m-Wnjtt4BxPvNuVeNeP(KxsLwCxaI?D?JOL&P#?MU$Hr!{ScZ#9$ zig%i&>ou1#y>Z`zZ%-qGx`1J_3$fxJzIT~-C@{{M4gVp3uAuP?ND2`Dr6S&kEnb;| z`tnsPVB*4!lcn3^l;6)JX94w|v(*;UtupH?{L*7f;dwFL+oz@$D=aM*Y#rTFCKBiT zvi#ZL>9C?mf3m7uv>F??@B0VOEv~!_e|P!?J%qD=WDlZAF|xR^4s>Gj^1mTJR<2mT zEq?%gh34MG3?#*aoQY2%1`7G+rMX2tb6x>9*1c_#>Mg2l@@2%gxk7#MSoT1U#0&XC zLqu<R7OBI=aYH6H6!mmJ$Ov?(T}O#QtFhn^KftI|_7~5=lYECIRwU>%tQqU_uM2et z_^}T!(O@8IzW?ZCfdc)l;KxRKK^<VjhYAU96o()s_KH6%6Nnf>yENI7GKZq-1-O`= z`!|%C$tuF$9*Zc*^Z|7MLqXPI6%k+ArMvW<q7{kPBtm({gg4Q@T^e+^j6E)<?`|Jp zTdDnkR#rBN=>9WAymm>DPp5AWG$_wa+#*%008TDDv#ce#Xu<kw<=ien=Vs<#;N7vD zz4@v+&HZ(hd(tqQc$y+tjq#0v?=7tA{EEFjUNmzTTGfjdZfU(unQyHwJjf75jez3} z_hMvs)Jvl>8P`!v%gRC%^pwn!-W4Qh7#!s8)Tg%b0NEYMZ8>}VUS9tT82Aq$4i_Rh zM_;XfhY|?JLRk(-B?-PDf>x*P3$#BGpY5F8D1LSlL&Q9lHjlSG#ImIyN$PiDKAOKI z=ROFtS?D_ML??oNqBbRz(+Ua?B`N5qtPgGKV)KST6fs~93fhlaHW54Deem@I#`th> zapoW)i3X7FKn@d7?G2*&t0{l%3+&#qkL?(7f8u!4YXwC=5EW3gvh#xKCJ{^&`xxKf z({=}s)<K(IzkE<^%eeDIp1a1_!z;E!Dr8K4A#SO=<CIT)e@Jt039{!ben;*_Y=?`N zzROdQ^?Ay`DBLE`niXt_gc=WvzJrr%nhMs6>vL@K*<{?0H-Oc=uKATi)|UTR5;8mM z`tz=Oi~z5VHXY7cu)rBv<avu!f@Cmx$VRtjkjF#yr=U|}i<kcS@GM$|CBdpwG*bY| z?CD@fg#lM0E?jLPmGsH?h(7irc&fD;DTjmK<T&k2XS?_qTwF&uybl3OC%<HYZ{BQ2 zRjBh8GPCbzq_!cqsIqvCw!vJPl`T@X7n?f8#Ye{vZ2k~?zeP2ZrPs!<+dFe_aiPaV zL`-ZRP6vbbO6{!=-Ff)*nNj^d`a0{FP{o}(Vu^(KZ-6$fpqGV=Nxaq7DKkf3UH}1c zz`p_5GO(}xR6TJnaldvKdQ`)1As*yf7KXtK2^W^_Z`Ujdr#L!^*(Q5BG=448yh0w^ zZ6BjLV%tzv)JhK#TEeY2?ql+p@sgLOgWRu*tCKgysvE1u5JlPJ)YN|DlxbRdGfxr_ zIuMNdd*C9A=5_gpELQX1`28K<Ki3UA4k;Ft<xJFP)P*s3i^kx|{P2Du&YdXW1D-ll zqO5W>GS@RvYD6iG4WQaw-vj=B4JbbV>jQ{L`z`m*@=*8ao6|8X-8%$&py^=s({9gL zD72@=&H@UcyI-W1V-j^poQ`XQKzn-R$Wp;)nroJ|%B6_~_U-gIsih+v7>jFj%DXOH zszW4t9nQt%;t@EXr&{PJciNK_v*Ry)jFBzPjNhAC_GmEEM?e-)Ij_4Z;&!%11bIy9 zs{J6o>sd3{n}{!Fko6XzY2%J;7f@xE%uLMKwujK^(uJ1Xf_b<H+B^n$XFTz>aUrRW z1W4pWoZYkq|4pyh7en>GMi+siVj;%7@sK@dSLVS5*D&;LsD)L4!k4ZFQ32`o(3&|b z#_HOV>D%?s+LlHlhf3T!Yl9#KCP&x>|7hX8N{T_+J&wEFzDb;F4&(cmgC3|JliUWW zygUB{CXqhs2Rn0gdDn8rlFUAtG!)c-*LdMU#P^B-JN`uHhy<vsW++Z`h`;IfEF%7A zgQz<A+0oDK)*oQ4tFis(o3%m-pEzyN2k>fbLQaxxtww`1Hjik)eXU2A5UC*HCAdCJ zFayfP?<J!MQr72LB&S(Mtxq<t9sd(>Vx+&~!3mE@WC7K19afWqZ!GVBYbfn%4dtH= zPOQ+=(xxquz2384ANP!sQ;`DZ95k9hR6IUo`g^cSx3Ba0Yzs#H1zc2n)}zq#4lg#T zF}hpdv2ft$CsvMWj(EDmW?r8*5{Lt-b>2ORTXwKAt9~*ETGp~nIqz<rYv{wn{HCX8 z_qKbF?|XhWb>1Ybxa()H%!EtqK%v!#g!Mu??)4sRsB{*#JbU;(cxHGtmOd*HuIYyR zP;0(^cyUHW<k@O^8c~CH92S^l$C0&dUT0JiRpd-m50~6i6F<NuJFgD66}%;vL>E4< z&%2Jr@+y#?^j<bEv|KDmj~4#qk;3gSO07{2a(-H*?$N3~_^!awFBsR=Pbeq=x{o=V zB>&u!Ik8x2`u|SO0uZvVk(f?dE;+sTa7WzI<hAs#QXbQqW){@8EH;G_SDn8(-EgUM z5jmHl!?<(Di^E+nt0&WVQVi)K*_UeQwrKqHU3bBVP508_efTqOQf1K<0DdS!AL9=R z%Y_spMdZ-#vT=`##iKf_W=p<@X>;{~UJq6)#U|%}-Q%tUDrLTw^1L!yKks!keGjvC zp6WT&ME)_s1~m4ad*5mY>R6E;OLClf6VYJ@lF46OVKZ3@vMx}1FF@rB*=<n~d6}PL z6NlNmY+CcE_p-x1Y>fXr*ogv5iL&8VM?UR8`VG=Vc9$7o#Mg|}){59d&jBv!l<I#q z$LakK-V+%9e}{LS8h`sQu*PhBvawsq&fVnye<YdxjmEuyZj<kXa~G2|q)3kn_JOfn ziFKz>9?S7f{oS(H?hLaD7c7)AlDk)<TsEkM70l;7Ca`rV0R*<jZ({%7SlH?STIYKR zoKq6VZ#9`Cmcox8myo#Pm@-`WAowfk#s4e1bv@Kf=ReS`0upqjN#+s2=K*O0a{%H} zuIMQP+l}DOL|*qDhA3{*g?}w(`Q|U~eMODlcMMC0C>bXG{X(S#kco8LB&g^Sp%c<L z1^<6-^;Z1vAjpX=C9woVhTZ4y1&4b~_56DG?>T?l69|;L3q*55khgl5L97(HM8;WE z8;zaK=8xm8^W^v&g9IdTHru&By*o?#QzjVh<oq2E&{7lVUScLD$JuI1vd%y7#)ISH zh*cN=8}dBPx85gl7|HQO)E!EP!<|yTLr=cTxPS^Rh2|rfPd2fWi!rnRonWj-!^19F z<wf`cX>Rq>4`olslY;m=^ZD-V3_ja!=fCgn)Q?|(m5u~G69}lQdNn(koKS4WDyJmJ zlG*g)CnY|Kf6aL6LeSsE-eXY@_ZE*-4BH$kC~6v@FZ{biPSJ{-V6MkJc&$eR497h9 zJq+~GB)#!MM9;&29+&o3xg2Z3Fp#Eub`1iePvk~<<1_zW=^yBnp|)M;Y}($~K5Y22 z*@O)d3f>F@Ge`ALyPRDKgKFme!Db>-V2nu@|M#1xKqu7B$iKEL*|{#Vj6un%eL0{B z_GFz%c9irP@Xs9weJ6+IUxXvZ-@bVd{_d0g`;)(!n*W2;|MzqG&mP@>{@wpA6#f6_ z)jVt4oDQG%3LI<F<|7x!igq%Wl#8;(*4-Ww43)>z?qPNWR+vjl>p336CZ!}7tI&W3 z(v&4XBz6S72j!3yTa4$SD4aR|b+ngG9uYCtbMNP@S5zx^iHW{C$t_Zb2I+yL!OmO6 zFrV}uKRLw0#JVmAKG=$@3pHv+6tUs4#Utro7wpmb)?I$+#HV{-wGWNzAzdA4pH_re zhj~;}XG2KUDB^4=?2{;_f1?EuH@nX^ff+hT5S@rQn7DX+c@d?5Xsy}ad!OdA^)+`f zeRc&a)|tSvn|#8o=WKL4(GH)A9~O5Je`sH38_;Jfi}$%o^+}B)Ckb)oj{PY^97h=4 z0ZS~3L;mF1TjDt8Zhk_W+H{fXIrh>;gF~yD5Ed-ZFJBMeiSn}HH#~wmO~{Zg*!B%i z7HEwq&^{Qx)L7Mm;C}D!B)D}G!ntaz7+vc6ah8*QZRcX(f)3=*Ts@MYv^iLG@f_q& zX8h~1iBXMLK6(Zt<&*k*U-ir7avs8SL>r_QSs`R>9v&fT$cnE?c4p5MCj0h*v{uA- zJ$)A%itMOzXw10upXEbauPAbdZmUCjx_f)}Lu963@v6%_aPlaReRjxsxBSV{lbQxm z)X@7ZG?`GiH*ZBU3q>!JkiH~|lkMPde*=L0fE%3q+YKreOAPsCu|He=nFW2ciHZ4_ zaEqtR{|P)5y2cvJ1T$V#Iaw$|!RrTt((w(M$5#muMN8*jJ2=bpTghuFU^&pWPc-T} z5W=ibMHTAVCy@H|i_P}wZD9TYE3j7!g3!<He0iAAjb0Vti0-r@W0<@=qiUB@i2{kO zYl2_GyniCHe6FE=SD<N&+tifx5v&1Z{fPw%m|cYY{0BKvw1_@zWF>@9DGDE?{xHNj z0-kbgFlqzM>9Us0WE!nU_tR$0WI?=a7Td0BWj9lJ<)!g6c56CBs2A+9xA&8p?_0Z+ zOwozQf-{J0LUz(!j_jzwHMR*h{CP;BK}D&1(qQ{R5t^u)m1CGY-Z`&|p~VRfR?V8B z9bR-TKEAod3Q@RGLi$o-K%ax;QkfuxEOytspFhO%mJurKTayHjvWLo8Ly?r{5WhT4 z^I^MRe|d+`sVD8&#{}KE5ZFEA1DiHoCUwA%7(aJ5ikjcXe79@&z-_<30T8$7qiBhN zqHyY+@uE;dX>?!f=Q{vB_-wkZpF@{7kB8p^9uvIqedeZ)Ph|Sm<<EDB34_{H)U*4# z(Ui#bqmo!Zm(9Li>UQsj*}OFnr3HZuAykP{x=KD;9O;JFPa^jD9co_ZxCRZwoYxY+ z7BxBhtl;kzV7R=$DR{ErZ$S3?MYjvJbjSdg(POAjMoQWoIuxuhC#RR)dFUryz2+=w zeG9LP4jF4jNa4P>3ia$jtXTI4`%6lp4NVF&IN3i_u21P%oF+nzVfvz7R4ih87X9J; zHrwI8WWo%!GWnzCy>e&v8%(5!{I(`pnMFjZA^EVl`{nUB3;V88nb<_&Ow+HHkRV(T z^JHH8s_}MR>KzO{E1qBeYn86n;bZV?^$=LNIGG)?F61onw<}ftOUy^m)8xE3HrHtv zdU`qODi9@SUfYY6P<uy~(eHg;ma>V#_8>|ha>czQ=k?nYpD}E>H@2wUI>iQO&+=hH zi7p283#(Clki`PELx}g+dTcxq-9IDbKa{O^xmOOqd?#wCX2w~dJW9>WT#_bg5j$6` zcQ;bSx9BBg?>xuLt~(4I-k_p2uJp@9Z*A-q*qmNk6*rmh`L1d?h@PMFBVs$%Ufr^X zcG{8hef}BZre*n~DX$=Zbn`ADX&B3DQ^sYmA*-&K&~`_6OG%k7==)4u-a?+fW=ux{ zj}geieRZ{=kItviUm5s9gf$EOaSsf87IJL7Gz7itqO8MNWW})o{Nn<2L;BRcJ7z{B zij+_VQhC^7InKe*O5tnh!%e$SjRm{ev(J_9&E!})-Wo{Sif?*2UJ-O5uR2e(NSk0O zvd}jEdmji@!is~5swmEUE$7#)KKd#xoJBJ$Z#asadz)c6Q=SO#08rO*W3eCNBLQw2 zwtvg!X}JAZPdL)_Pl~I-VuNwi!?d-@L;~qd4XX_sG$cu4HBV_Q=zxevUHeQ_<~>6w z%B7r^hZO6P3$m`s=EhC4`fNDd4izaUh{{V>TIj8+H1szY`?|UQoYss5CeWAcj;`~9 z*c%Lw=wD4xa<ez=2Q#KvP`ymp7aU8EWFGUkjEqPJhT_)@-xr~4vyXgrp-2XHnwoq< zpJRiH_cm4&2}yGw=PZIs97#p50STg?9qvBI;pU`wfmdh7c(vHhwQs)U@ulLV!G5jK zLX3vc3Q@bRb-3}b_={2bB(pD>bhLvU_hp9xTTKs@Cd1MLH@A~FdBZx2aS3JrE`}z` zl{NrQ-V0H)^2&8<Gp+hM!d#LgDlD;>cJG#`hN!?4n4;!fvvI?@{66dN#p@Lh3->!H zS<H(xR^aJZT^6@eJ);^c^>xC+@91v_-0QEPf`)dO<qN~ND-(5Nt$>AwPp@*)EGhv6 zSJbKVFP}~Kj9z1*!3lnGB}PYC%w9&Xa<+(13$N@xH|o9ivUX%Zvpk}-&3?gAw&dFF zLyB=B=IpyOhq<CNx}}7pkTIhKu1EZo`*Rok9<n$!Sa#W$#j|xXO=bNV29%y!mkz~; zDfF6xOE-Ytzvr^$<2C6$#q482yQ8zxyYbwm!IH6C(>jp^?f6nW!<c50b{BC(b{iwW zR+2&2W@dbN{;}nexqDB~i*aG?q#(?pHRY8E`4|05ZHp{YN!8(6L?aodEm|>SSVr2l zZam^Kgkz<NrJx3PocP{QE<=fj(F7~rXAKpFOz#M{<0b0iCF$0!$8T`;ie5h31TW;S z4<8@XTXV?$x}h!X%lGr5%U4m9A*GZAlie*1mhD!@tE1q4#uh{9Lpc*)KShzLOlo*e zsy}bEIHZs>VzrRNH7|Xkp)68;@M&bQx3Lp}9+c4SF^g*U@QW%ymb!kZ9vdm$KEid9 zA9L)aomHmTb98Jxn%i74&YQs{)Br<n3dacoD>(zzjdAw&-JD65TmvO<xpz1!+IF6L zjm$A)1zoc0$GxSod`G9Y{JUV@oPB+;n&IE^jfW1YndZ4ke=N!n3N&AMKW2g(O^_cT zdBR*02@sGJ86@5AkeR3{i%Z{f&gz-^1lqWS``@<|Kx=gT%`MT_$rc;{h|M1^AIaSQ zWs8c6+WTQby7JehK93>0K57XYMUQE~`)$OFF1r`Sxyn8H>RI@LTPrf9V*wQ|u{ag^ z*}F5Tt_dN<|9Kau^oONM1!SP2Q0RAgL~LcX!-SLWg4C-iN!>3g2`pA&i{pB@G)Mo} zCIC)E80Ur4Y@a2nrY;6)KH0t!`5;I&V;nT1ns_&|+xtP_rU9fU!Wvd%+Wl1V_U|KP zS@$do6ZsgKu~w(fv5AQ^E9(C|1_Fy%v#kA?Vx02|&8!t-4qH=OD>Nx9H#v8yZff^Z z6fYM;X^DMrPs}}Z(HFIHmL`*p-#nm~4RHqJn%28M1ibyVb?@@Q9WDmvL(e%>MZ}ow z6F_fzt&8jDg^d9=3XygV75+G$tl_);h9h{Y^b9@jbjK5`chY({w>%toM|kk`)Z;Qz zI#~807&3Ln5&5tzzbrbp>Fx^eb|@Ucc6=NU?4vhk<w8ebne~xkWfVswifV0jHXr}# z>&o2tM6f$h)k~!?>|h&K1VoYs1_E1GP^du{XF)3sN9WO%b;H{L|3!gDf<(JJUDQ6g zo<DVTfg>VVkBFNCW%+8%tb=7mD{OL+MY%rGwpg*{we%SDzOM{N<Jr=-M{d2IPZJu3 zM+gk^-^axdVlH;RQ0{Bc@+Ln*x)<qZO&L5UZeOPmDT#GkT)WdF_RW}~cZjqFKyR1E z0U5Q^wQ$P4VDpVx=2XJg8+jf!BA5I4NDlFl&?ph_DP5)LXW!M2mQ%q<X!b2m-1Yp7 z7cx(_bM8ftyDOOF?W@T@aa(cN$b<gP5=oZ+J1sn}JK4_W99R`eJI$fEr$M$g6W5oH z`EO0ry|?)%!Qr4zR%%KuA*9_fYa{X<;S()_1GW}UAmK5$3_T<EWR$+cy*sb?>b$s7 zGf}0V#$K;q1>gTN1WV9IPcy_wX0>1$6R_47{FD}7(!7d~=rTG36pB>*_Ya#L*s|`# zH!JAocytKQcY%3z%AdVhi}*!fkz*3wMR?e+H~oFn_{c^!b0VDat?!4cY6lj}`5I*v zDprMlf6Q-5%OUPX{_N9<BYR~KF|GWVi*!1&&h+Cj{RNA!+sivulf|leUX@`}9`~B* ze}0m`W8#i%nF?oMX{y=60PVvGIa6<ftGgZKpN=(10pRK-qJ^!^I7!Un5|8zrKnh&} zI`+_+x!tECeMw#4=H1>y$R1N(PiP-VIHs-K$dvBsw?mVs-I`T5B1|BKJ5ynY_r^(b zxpU-4zGc9|%0pHx(NFZG;hbf0HIjyABwP6oLb{}koH@PQ9n=axnc%V(MY<&>?2!r1 z4fR5DLP!sN$<KHK-Zb2yXtUhd8@MvY?WKJ?9U30#N-5=}_ED&AnaM-$^An|qd(>c( z*o&>FHd1|SRM}ihZr3YnO|B0(QF3~MR6x#GC-d%ZX`Z(XnrTr6_0>I`a+s{hhj|T` zL>au%`O>?nzx$!+g1cs~$66-X0ompc-sa4qa<BJI&~%#KB>=idxhkY*b^Fg9y#*`K z3*!`7{`8qb^aJ@HUNw6@6QHAioYy}>$(k~=2yIQS$KR0fu<Au02wUbc9APlZHh!yh z@q};BK#_x>({<~$yf(F8eW<Z|+raCb*a^l&=1m$Dz7o8sD5v!Bt*?NIW{8O9!I`>` zbrrMM;JhiM^8prjBiAb*&jRE4P|-|Ny8X)?(S19S3)icPoMl|zOW6*@Dh;_*zW9A$ zE2~aT;?I7anW_uEwdEaOn!Ed1loHhnF3O4E!b-0|q2Cm)8VA+w*bx(#Y^^FTT>2~= zah3ee-<4uf<8l^IftWvd4;kO{Ehb=(7IOUVh?T!5m&^ZF<LEg5)$eVT3eV(kjw38) zN$o@EX$AGX!-oMT7+fe^GYotHmj86{`R13RA%pw^s&h_@pD7(h>x_ehz&&VjPkDb6 zRHDv>(fa35#m`z_{}*0h-ggeN;h}BQ4?YjA!xA=TRdhtX8|q(J&=K*lL(a8){13T> z<|<{DK(Ts*FM{S2xf^xF3}8~7?gZHjd2aF51ifDEmLzVJ=InDn#5rd~T3R8edq`^L z8Vw`YmtYU*buP|Qyl)oAQB$i;qQ`hF@XP4$`0q<lzpK}<cP&)fPjbyI?*Z>H{(@-I zzLtLvSI_|FH21~#at`D%IuP&4U;nn^qw~6!u6JyLv#17n9k<E@v>mE(%pLAL>goNo zFhHGJzT#6RIUf@_?}2ngYALTI7JjP9y;@&a)DU=_)1Uf_p2t%%xl7NModakdQqIa= zqsU2*CQRR|+r<2)8A|))ae+1*PDTP_s3S3`&JEN^^kTJ$h*`MmdFQ)D60tX!olUJ5 zAG)gKwf}U?9&E8!f6<^aZ1teu6$6Yf6bvZKF*u5~l&dLUxZb*5kOt77qAPN9s8T)F z4f|!wo2rdb^fF|^>9sEc88<znsr?#uHm3Sot+p_ow}!FZ#s2iRaI%JhjW0}j<cr}j zSeP!-nLY30jPPS2O<TP4Q`-40oF=5Ns(K4!q4RdBjWLyQMZ#5AjZ6^!x=+J8zZJQ( zMSUza97N|;tZ5Fk@<(1O%5e@|lM8ij31-|RUaDK%d?raDCLiJ~h61JqC{=0JRds0` z&$PBMl5*Y@;78nie`r@V3Gd|O%3M4A@S>@pt`zrX;<`!@sUDo6H|D6D#<bk)oXI3w z=&^@+?B%sk4h_DE2jfZy$^n^ksg?Ba$Ork3NT?gbQHqDds6HV7E9-c~+6SqwmwXv# ziHtipSISu^hLQ9d#{2SSc<kwZgew@h5BKKu7vily_nNEOGz5TR%Chl_?%Ps(D?xu8 zKRe6Hf3!)a|5$KyOvIr`q60acvh>IOb^&$E8vQgB2mgufPfD_9(EtYJflkjv6b;q~ zb-w4gHGvnaOKAvh>7%fJ7s<0ChsJf>uJTy8-FgeI<MhpO^Q8v$I+d&RM&vy4^SDpN zFz({{KNR>g2$zk@!0J*%XN^3IOV<?YTbN!gTn}yC)4a51q$s05EYMZ%g7o-l$QbS@ z;G>^o0bV@7dVPBVA95n*KH!?U``j-}k2e@z4il?i%ExGxDbTBPlGWR6<(DO-q8<Uo zZH@6Y`o~I}0lyIIMWG-AyF+?vuUcV{p%i({<85=slZyVEg#zthlt5#B+~l@Q-`urB z8xtF6j-r=HKreyMSJ+&*6(nE`v^ezsoJFlD7RTA&(rHN1EUxSK4e=<YuOpA$oedff zYLmgndzYG+7ao`=#Q%OKA2qHrH9duK9*o<P#7@|C4(Jy1sx|wyv&e4j+u3Z`0-|dB zaL@?Pgqi@5wHAFS2;C@KseOjc<0!jkXx|(@sJ0toTaGUWy7_!(DxT`UUPUC$-WvOs zK%^I1NC34v<cS=ZKsj?B0E1htV%7%Uje<~&`Op=Rr=7(K40(V51YUDpno?S%b-okI z-%o<xiwOc(sQ4Xsn^AiYB&4g5$D}>S)5tOx-l<WDWh_y;OG?Z2S9zccxlF0TkqT1} zPJ35KC&(UWJvxzg!U1l9TNuN3?zIFV@>nce%%fkbRg)&^u<$2?gq+g78=s>}^$HE0 zg5uQbtmA}$f-S}1c_=D+-Ot!$i<eM`S)!L+xDx;HXuDpcw_59qTJum=#f2-8OiFWk z&HW$>{wj6$v;{;si4XiL3w(29N0+0fAt%pz2a~o9mhF^)jbwRKh}mI%TgDlBFBcv2 z=jcAu$lw1gC=>Sk!`=_S;sAKC-_Dya7Z(;k2myMn5Z9iWzKaO%|3%$<hBdiuZKGIO zf{2QM6j4!nlirCHq>G41S6b*T^cEFS5drB)3(}D$gdU0@gih!!2^~TWLg*zq59nID z_TJywd%xd%UFSOan~*%rImeiz-1j|(i&6oUQFT{IkCdK!BXRqv?9g^%wNNAXo&<(N zob&#=Ukf+k^7<V;@Ux<h?1;M)+&Z;)gtu_Q>tD>(r={FE-6>2E7F&1Ii=ovIT-VNl zH#mxCM!Ujet0E24mj<|X01c+7l=Z<`GF;rMy{w#jF3Zh9F5K~QUNy)>6e(qLH|xsD zt!9g(L5*x1HR;FB&A1W+^Ak=8eT6kKkoHu3X!1{`W0+6hu87vmP2Vqx6WU{Dk*TQQ zAMQQo*<a%KkZd1Snge-MYo3`W*|-vL<<cgNl;OC7`dpjCmzN`(y~ncj6+WLOc_;R7 zQ%b4!#TSjMOF&EW?hp^!+GNj@55bXB=PSntU!2MF+3>+<Up!+z+ga=bD0I_$O~zi2 z22@x)Zu!SRS*W<*$G$M@29eB=srg>H*T1?5Ih86l?J1<so@96`9x$8Z3=~;X`yYq# zJtN}oOuPDq@{!<t^cGuRCZ|(~+<I|qC`ekJT<RA^>1orU%KZD*rod6yBV0ww80pS+ ze<i!j4uZ!4Qld^(DiKRMpP+^czTLETZdMSvPq~DO1fc)>u71=a2EHtfUpUFtxn88s z685}h7PkEG^}CN<vps_)ZgVhL7*^Jhe8Gb2R@}n+c{aMOvP#UI0QdD+ry6e!>RUwG zeG8S{&U7}00N)EcxQyaX(#hbRBQR*S9=h6}dB$Z)$`nlW$Ro-<4kKM@%<mZZG<1J8 zH+^|vnf8p&2Lk?iF1!Hw8NQ3_JWbrTVi<_d3NfIq9|UE+owxyawkCO3)7gff7C2*G zO7sxbX%AgXE9K<dBSd=26$c*8U5bF41=OTIcqZMzI5(j9?X^c7ly8Vw_4WEda)1QB zkBLFxp#TNylz4W6ZORgJR)!7v3^4xkrJ6*>NzD$eOu}yQ<7dT<MWC7_nx>6;pnLML zT_$s+FtGXzrBCb5n~qGq1w~9`Erb>EVv`(-$qb=8aao5{8Md<r`r#8mY`D@cSA+4K zLDI`vPdywuKuSHk!{<kf==sEt1L0D6&V|_xsk0ABwu=scWdLnERh~sE+pv*su>GNr zPXw6=UHINgp@Idu?{7=!urulJyd}!<Z&`SmJl4VtCw80Fgt45W?KeAbborDM?;>Bo z8fAuBlvCl_49x6nN4UE5H4PlU;%C%->>%xK<?RU6yBUOq9*_(OUzc%vusa$#Ec*am z?DN57+^GA(=!cXzwyeTv)2>EZdAxa4nfk*O8l}oFFd#TaU(AD8lWbbwy6(Q{9s}RE zXW^8d52pXv1rq4)+D`2qs@8?wDUx$LPFt~wD%n%bE~-(9l{MVuk=WZ+n;1PY90WQo zhrQ#os(s4H?M<>uP@><S=n5coT#yDDBcR;4>9CxUn~{9l)g~nG(2eg@PGO@xd2)9? zZzqkpC(yNprFDE_*dt(Thw-VnYeqef(Q00<C3{S`W}d{kHQe%SU}d)Rg3-f7&Fig` zR;1K1hZ@bg4L;p>OBLgCH44c@WhEOs9;gQHL-;yxTfa`uHJ~{kVDwmESY37h(Y%n% z4tV~_tA)L*vRT_cMF~(V9cgJmGST*+KXAs?ZE4UU!L9$+d#ZPy(Tqmg`7gYcKkXJg z-BmDk2BiqM8CuO>3F2qWBUE`lA)L6>6SAQEEPCsh?Xr(ji>yMy#HeeDk2o7%jwg2E znle{Ch@`H*P@PHB+UN(t^7@RT{#do&Q?JRhbZM$NygeRVIP49vR@!SFs*ybF28Fc8 zI13Hj*Qw-c3i>V@l(z2h)TSd$9nGq-$mx|KHT<lgas}r{VIQW|#P(`|f}8k`RWd(1 zX2(Ryecq?==6KBW%O4O34qTyc?u9~*qBbk9jFJ^w-Ii9`kK2<^TXxx^^CFKEpBL7= zmd5oIa&9WbdESkznSO+R%>I2ism?yNIK)2M%q_IvJ1TZ3)o^~aCm^UOc$Ui3%0aKy zm4%9x_S?Eg?rDdu$}u-3_PsY2(vw04pw;Pii>t-*z4;^Od1r%!+O#DWy!|~}U3b>Z z3c)oLCwZLXtj>{S(x0?kW{;}A+p%#&miG@1b09#qev0f+^>)sA=@b%RK4frVwl>@E zk14j{aClKRD0i|LF@;W^RVv9NkY7qjL7T1l+&#11+9BwZ)jRzRD7Q5#R$ivP6mM7X zeqz(l`wFyId_ha?8iLzL$@SxQCLoboO+YHAF^4#EgMizKH}fg^9FwYud-dtuT*Aqv z%i5pNZ)e>kC|65NOu{x@hqvPexDhUribtAjG-3*DaahkMllv73p9x6x1<!=NwNnYR z<_f56a(P&;3a3DeoLWM(#lo3Lmzq0)TVGhJU(w1X`$<GW5c8fnR<II%h9%fDNmc7D zo>86~b{_iR<^6cA;fG#x8NidfqI>3V5U(6u9XB-&g9xR^NdH64Ab_Le`;drJJH;Hw z^z2i3`<5a@9ojDh;}m`&YJqd{qW81uxV}f|XXGZ+M{?WlI9*Uqb*P&2fIT>l&8;n@ zyB}<(B6ul^WXZN{Umiv?j3i0Kd8^-OAnt!L-8$;Sh>u76IcS!0#l4^4&ls-pqqFgM zRJE*<8!sVgs|K}rV$Zc3pDQ6eX?0DcSbg+rLD<MxtVC|}9@^tJ95dM(7y3A{x2v*s z&P3cg0qb2N2Cb`Ep9>m>kqBwFmZ7AfbmwYx>6${{uwOt65S@Thm-h4Ro0@iu8jW{x zidxmuv9~>BET%Tb-20Nf@@+3I7gjc|-SY9PGhsx3+{{i`sh0||Ot2o--n8aGxiOZv zGtBcVE9SjM$d%q5rF2&!Rq|yz1ooRIoB5IYiH<#@=sSCt!M92h2JxO!T^&mw-&{J~ z%IY)JSlpw_+Zr{>2!B1%Oq$>AooTL-_B6bti3`Xj)YZ#XYI`*&CWSRF5chC*5HNe~ ztTb=LQVA*FAkRjc#n>rf*>N?#C=*iSw0y8jWItoQ->Fm`Je-^tDEzxiWUgxM%9@C2 zi#Uxuy4X|xfpnluOqRs?k3bNWPY*axMBj+t)t&xh=iTcqn^3-wVZ1*tj2{ui@9NF| zw?AFbXX#3MgW!%^VT$yaT#e9gi75IBpWuA=kJuDV&I?Ml(~fDLa!TL+U`fBa;gr^q z-n;UH*VS;?0s2!X>2*RuMb<$3p#J{kQ}|s{Jk(+1q|i35QRK=ar?Y|-z%M`W)F7I- zxytU0A9h7!%zt!}f9Gtqljh?6*DpNOYrXrg30oc-dQu61oDO6RhMTdt5)L(d+UCWm z#RV+d?K$P4wixinj2q3tT0O1!(Vzmmr{ISQ9n>oHSZ<JHbOW2fdhE#kNb9-Fw71({ zp&v2@<rbuKh`95KIrjEEN_mgOS)(%5W6}?}TlZJsG-?UD709Kh3&Vm?#p`1pyfx4f z!gnC}FA#)3RGLg-GW!!NLiY5_j|+MQ@j~1+h_DzMDp^1g*3|z9yxANp`neF&<3i7n zdoRMt;&~i9q=@0dr5&82wX8;^-}(-&d4fM%nuOv0Dt#i`^;?2S;@P?r4`u&`iIE?J zfzt*geq+7G9Ijv?8k;qUdmk(TgYwtOZC)o4w(j2T7CV-ji!IiXkUC#(TR@aNZ!F7b zP|-XGOX*uopQadRp?=Nvj+Y0%nCmkCsxhS-0Z*ep@(YR4{U<X=@>ne4kv2AO2|~RO zsaZ2W9s(6pos=zBGT6cudFYKrR;A22Ntjk5Vy0TQaCtvlH^BP;gwC`%4b1e%0JM+u zv(7c~2a}{=USqJH)4A8b*Sp^)(7hW4kqZuL1|;n+z&N~z5^>uvlN0<ed^iiJZXRso z!7DQ3u$lW~%9o%kP<aQhqdpH{zxZ9fw;2=b_Cb#6g-!SkoOaoeA_3*<SxS_=KYi|U z=NGn-u9LX5)aQxX`rI=m#B%#PtggVot-~+<i{oc{DD5%%E(3XOZFmwGbs1BS(!4OJ zV{FNvd^u<!cG%UsuGdO7pax(rWTd-^6QAZyq1fS2{!SUaU$Bw~9)APxSSJDCop30B zuN*xNmiw>K?LRN=-~K}#ychw*k?uMRvyGfsBW(CPhg&s)!||}C4{s;?kGh4EBtZ;~ zmlvUX!hii2WGz2HGdg&+6E_uH94l_yEyFbXTpBNQDep<bTE8yCu!}v-P+fT%VY(@p zf)6mnhhfYY5P+#$X*vGa*Zhgv0SNhXi9ZPW3D6EHxo0dDc-E9+%$?Qs;8bXdrm?lf zw@+BB;;FAM8-l{0gnS-biKrz{V55KfX?Gfi3szkk+a{;)d3y9OP|=^bv!7#M<aXsY zA1?;@j#Mx3KO|6f52(0y8Qn%>%sX!`555#NN?_fCFNDLXH^fImUnbsX(Ch5O{=!IQ zo;-|jDudm)sot>RLxgv6iL<yR1fI2T6Xn}w1$Rh2Wd)4+6YHvHT$d5<{|<~Q`nlbI zVuCWs_yGYnKw7S3(3tYqQ#$+uX78W=?k`EYUz`4KXszOAD|bRVWTvj~L9Bu7{a{kV zpUwiX4(TbombN=;p9dDI9(4YN?R(Y&GO}T(Eh^Q2{|m3C(&F0G_vp_L0U*7{;_DR* zaoJF2o2XeBfx2VlYbrER{2S(}ZlrL~&=&=!pZ_x%nQV&93w_lS34hb9%Yq?wvjpP9 zq4&-Mr(`Bbox9=7dz5lEn4OW<>K?CCr^RAeg=RX9NuC2x=EN{l0brtBu*z%kQcfmD zxVL@(<v+jQQ(<VMES5qFHXfv75+aod@7(8Y04ea$rY8Y=l2ZKEyTr^GV^khR)VNx& zQpQ)@HOOe~dE0Nmm_|WXRkX#zyL#ij{4|`;GOSve-MjU(wdZ}lG&QVqq03TC&Gqx& zW%@&*iGnFxw12ML^KLG^OWK;ZaDbZ?b5&jW>1I3nA9?K)BI@l*g!=3Tj#e!23+V=O zPIr=ttIk*mb4snD!uvgw-N_f$QQ-{+kKKsnTF>1m9xuI?wv@U0iZa!c=z)K7S3-S$ zmW^Fuhw9h4`2Mg&JTLuahn*YEu*97uI-(?Zf!@q~lM=O5`+wkPOG+e5ige9~^cH$g zg(#%Cft3Y*nFd*^Mv2J5mjft@Kc*}DCRaL6%;A>2IxTZjm;OBu@^44f<Y1R|@Vb^V za|ejVB_zGdu8ay<m4liPV}%LDvXJHL$LHORWj=XOHY~&ZE-q%>?c4|SK&x#~1n*m2 z9k(g&zx@S~eBPp2!p~wuV&0kxt?zu{>w@9eAHLN5<#{Jq!#O0&gM1Etu1V|^#MeJA zL4;(J;kE$td&IJGgi3GXlC6WG62+`XLz=PO0&G|8x^d~xCIoP30F0fB<B4gA9f>)z zK~tlRFHB~)-H8BC_vf#>MgKo>x=7jx)b>6^g+}k#5~OjCC>iQ-?LM-r_$B}6j3?U| zcs--eK=Su3oW<PN(_kPB&+#bv0R8hYk#VaJb(g(dm3#wrT?IVv%qnWcwOiJeg<_7q z?*j^;rlGH%Ys@`?XD2~?g@QqYq%H7YM}sUvb!g<^j{zlUis!-aCf90@5w>xzL&<QB zy8<gXZ~kL7P*=D*2g#B_we86VD9bvPXpH&u-H)Vlibfuqzipq3{;lo!MqqrBQ0%;f z;MG8lGY{numy4}9$qn2>yL9naw>=fQL1?Z5(W3EAyJB6Zr?nGE#T*5#@9r&QejQ<y zUpn_!QIN)T*YA6NftELF>AYBie|ZqKmXgMUh1!D%Yr+G0f_z{cJYwXRRBSV^ll1>X zFYGr1qXwP%>sr1MAHny5hZ9EF!IjAbzYzx$P>Hcv1WpmSF#feOPOpNF*auFk9kP`U zJ;-T}LpM0_hGog$8~+ug{lhai{rZujh@}tNI)BB;z!;;SuIJ~4^?P*t^PPV^o8;il zKd*rQ-j$0g|5PZrvG~4EwaN}TGk=*p4p27R^Mi~36H<GdZ+S7aVVylt!MrpxYG-Z( zLMIi(3;0`6ng7h+{>@+x=Gw}AV{$>sc`&cEa1n<Flq#}1)CLSpi|9g8B`WWCc?P;c z+^=Fzm8OX?>Y1pjTYT5GnaIq@l4l4)4J3ADdY7=NcDpsdve$7@rOrz0&5Bbi$-6{| zzI!yWadj6bOWpYEV&XWwU}b#89a{4o6J>>jI3C~P9+EPLX(bk-+C$FMNTvO6`qqPi zaCUAPA^<I$A&WS)d8;C)<KF+0Yd!dGUN?x;MDM(qyp(xC;JHrOS&_%x8_M?b-?zX$ zA|smFz5Y<OxY84bL(;MQZ|)!wfr@#6?hfN$M*e5?0zj-s1{Fu+?cSreaD(KUA7v|; z-+cMbAO0Wkm;W+!vP_x7)%}4d4_!IYlji7o7a|nsEMfkvVGq(SeIFKdvqUk5z=K&# z-3Cin>5-UISKm@w44z-M@FP5YcoW6LPYcl_VM?!_L!9{COn#1PxG_7V(V{sr$aEab zoq~)n`*x<t)nyOD+kS5?WkpvL9jqRso6E6M3XpAk*YL>8ZIOFJrW>devEW~U@qt(T z!4(Dwn<JGBa;+Hl6nOZzl#ksh+}r<6IP2L+Rip`wR`|$>Qof2!Wn3Lf1waCT?o{zt z>=d*^9l1ijdzthr(s^D8G_&X)itQ{u^GfvI&*5R&!)sAPm*Ts`SsYrr?RRv6S%Z)2 zoqErq1LW)hf9Vy6f6nR|@Nap3e~Y}bC-JS>H9o`9`R?<Vz@YtL$ilKrDX|~EAS~dy z1Lr^)&Df4ERzc77h;bmP);uTah#nhFP4Vsx_;7n0qv!u42Ho!_ooxI4XXFQO&)@F9 zTmy(Xfrz-t(ekklzM3_J7HAdj*6y*Efa@D|Q}n^L&R?#sB)(8ykk)?yZIo2EC#3}L zjKgG)ks}x3%LLPV9Gmdc$W`C~iQhL89=ZoTWebVBb*##Svfta~-FH-;dWYQLsJjA% zC##vwEo}g?^C#v#iE-_w+-3&|v`pF9R{1?(iTDWm?c;iBn};W?Ms6i)Qr@lX3-N`= zdWgQ(=z47PYFGBc<;oml2j%>-#6lOX+m<UJ>8a1sXc7hA#<^GB282F=3u}HCTw?(w zpWVlcxw=7d7REuIi44}i-JO706?x+g_6Xhf#Q9dJ+kh*$Z`8?fKY_k~)J4PRP2jw= z!Rp$sKt6Qq^NvD(*78nB^J+oOfLrzF>PfbB@%^;w+7XWR#y@Y2e~jgeyzTa|*GQGa zyJvj+EY<f%jpmmt%ZQ1s^U{WfqjRe}Uiq0dr2KViLxa(6`*ms~VI4-O_t@v1;OM?l z&s#pbAlXWSBgv592M4Mhk-uBo1wNPw(W5HF9kXn;ysbvAth2rkFO^IoA_)u2WkuEB zrq|t!1hqyWKqF-(e?8$5BUA){g}2VzS7j1+YI;kzHTQdPys<0Qen2MCcl<XacK(!r zwQ2a|?Yd9!y!`RfZd1#A1GVh%i<iDwH#O``TZSRjcV9KScT_5$*xwpEZQIqowZ<3S zPg<VXam5W7t>bo-)v{`Ko6hYC-xU2l7sqbnN_tE_brnF(1@d=h6zvlUYpoqQH9MG{ z68ip91n^`Lh1h!`_7I|r0IAg@f2(ymU&?-^A3R{><hdW2AyYo=MGbIDAD#WpHFlej z7Nu~((}Y6%-5s6~gQAt@bv{&1&0_ox4=UT<r#ho@b&o?#azT3`zNlRnijm-q%XORA z7L(q`Q>kTwHX)6GS#TfBr1<fAYB2|x9j!BXwOk_+j(#SvwcoP<(;uCBzXK$!_KvRm z4FQD>Lm|~;5m;sdhS!?3q9q{VON4{m00K&qJ90jKCGzs`iP7(pJ`Bf!1Cc@cvQe;3 zAOFZ`xoBqx+$%28qnQY8DXm)d_#9uh&kd8wi9RrQV~$H36QM&Z6cD<K?LzvF=1vve zH1GfZ`X1TE;R*IKgz&}=i3(yo&HO^VJ`|s|j!TT<%or)@zbw8Ii?iRKOd5a@I*^xn zma9zi_aMEpUYLUXmkI(3v@Wqtcm&{b?oGk@XeNm*#cLrHSIz5evx1QQPkLw=E9v4S z<}E*K$WIcA!6Mu+TgC7-1EF!f#|Axjthij})5CME8~4~kpW_7o+B&l1Yl9$qA>tT? zbh~fAeWKy|;0`<_AGKxTvo0^m1*qpuo-^F`?sNh9RuI=}=t<xNke$$EbpB!x^h{1c zb~rfXJwOTGUFqf3C})OAu;n7eIu8TYyIgNhmRSlZ#NF!p1WhdJr)iLWk`GPf#TQl( zP`O7dHNRMiV-zP(UDdzRM*!kg);f=e3Ic+X-S)pZ$Y}f?<ZX7u9a80pf;opRWD*v5 z+0(gr)0?BQuw>M$K}S4y3%#S%*sD$S@tFqoYRmCIG>`w1Pun4FwAvh`=H<@=TlQKc ziW8@SL9%kVGF7i}SO%}-$RmcwV$u)~v|{i4D;DS2m4LUYwkPlFA*|sJ&exsL#`}=# z^`0UX&fz^Eh3p~KR@ypSTZoNiaa&<&e-;f(h|+RLl;QCcTev&FiU8jf>4}njO+!IY z!{ux6@O45nPTpg(TDiuDWCnF#7OKe;*p1sMtjQJFMcmg}DpMp?PGUl2h`lt|Hb=kA z&7te3AgDcfA9C9y!Ym3qwD(z3Blno+{~!nagT$=aY3U(Z!EKKLXNh}z%wdD|tn!tk zhjE2z8y|5|k<>$8xgfi}y>Ky**SJSe+9;u^N^l#)S=C(A)r(XM#+B4bSmtWVlq6sb z$ehOw*xNgmj;g=s5V8NXwGTP#CmZ=kMGeuTE_%r$QGjz;=l+pXg0GuF%K^V-8t*jg zKfS~UK%-uY*>4pNxl+TI=#8ftmWP)lIn<P9aEV1jbEPQDoSQ0g;w?&E%a1CdXNp$t z8&7?u>lnnv<~FLWps*)y(qm1mMsDrc94}O@i#HlK=V%9^=de4tE0GG`H@`)>D=@`J zhaL4abj*rD@8GJb0tWe}em#XQg;xDzxy=?(DKAQDjIUofpU|iZU0+TyS@j4SwJGjJ zS9kM}n6>IhYEP7g_{MHI-1zT<q%M}SH!G;zR=o|wrN(?n0^~`*%uYkA_ZXyHw{_k% zV-KQoHlu0k@mxIl71HZSl&o@2s0$xO2sAkAOq)a09#casxb?>L=x@OZ*FJqi6_5Qe zIIYT6pD@dJhp-nvDXue}B+g&;Ezu*c1&C))GYxw3*1ih?J)zpR=>}9@&pTpt$AH-h zIF89Jzx@zkp!uKq?aiSG{vb*L`w{TR1W?r;2dD(oXwJVLEa29E-@N>Q3Am0-%$(i` z5b-`bERY6y_}}KO&IbC;VRx3*(!A`HChA|kw~U|kNZBu!T|KOI|MxlrHU+rxzry9` z<A-eGFy-%R0h50uj)AEQn#|Sj7@%=S|3{(DkA8#H$lGUX4EMfNL4&oIgjSFj{$Jvi zUsTJV<?O#&tN%3U;s3uWY9mjZ&aAhgkwnHlz0bpi@+|LW*$7CENaH6+Tw0$nO%O#f zE1jf;h^r!&t0zEETY{YEVHbSzmk0a_9|UTE72uGk8(Q}-&OAw*-@<k2-jzcO3F7nh zl}VXrjoC3#!xlC{qOzZAtqTHD64M#YMC6RT<Wm4WJrTuGHkxX)K2h1!sD~MLQbQH4 zZARx$xwCxxb(U`)CM6-GR7c|so&hYn>v$M8B*WY>IW=Pn&OM~gGyQ*|miMdlb<yy! zl0USR#}f?cY!TFM2XQdK-rgTJe_m9K5TjI3U@hhA2PxdnQAkl1m)wUG#bS%}uVVVe z8lxV!@_Jb(NR6*#uHkLw?mc)8mHREei$6SoLahebFxk08^p(bVA#~Cf&Udc;4?yHP z7U^XbS@9iZNhtZs<E79u?a<`zCfFRgf->;?&9NOm+_p@ienEJ3d2X<sZEiOHKk28K z#Ox6g|H-s~o(ijn>9e@n6F$Oeiu3PwasO>QW&5vO;wOLh$NW4oNy)OL!2Ke#SI#c` z{}<_}U_$(SjGmcKFv?JpWHSvxowqhM2&|igrKBAbj%Opu7t9O^sceh?b{c=E4FO<Q zgmFH&gB_-cUW~b2p(r{9SKLIo-miDGet~Ev#lzlDQg48WfZoQ>;FHYkaO^HnGRQcZ zlu|gT_Flz0nlP01k~jn-l%L)s4z<fA>}8mV2%6j?di09-K8-zs2NQAJ%=v&6|DPGv z&s8{6B^`+`&kCfWSslX71M<E93ne_Usy^QG<I52a!DFX<H#&17b<>tC{Hr!mqN7)Q z+D+;A*^1h2Pg1P~^F1K|Y8W7doaF9P=;S4?*?@?G69zyi^p{kp)eqwM;RN_kzy$b) z@%4Y*J~<eg_T%-F#rpe1@t^Pfe^iS5hki=jh*i|ji9i3XSZJ_z47_u@vf4pSA;|gm zzwSK$CsLudi|5*^DNd1JqU~*voXtZtS@5yKY(HMy)XqzTKKetD#!lH*qy!n8*f~}_ zSg)b386?CA%a={j*tSuQO<fK<HCi|y%koe;OH(|-#z1;TAmF%6$f5Yy;YwdgI_!fU z&KT}%24)OT5Qp~Nt)epZ?NppOj&}@S=1TB8{MF=$JI630A5+?sW;;RZx(fjlmvRO` z>U3^8KqC0~$OzYyVkUg*%B!>dAAqx2ZgOs1CMzX6hI#HcJNkC0*~*5%CUn<(@D+%5 z=Hd!f-7X!$`l$)aoeM2$C$qG6v!x3TzH6tK0}X!lBt$;i&S?i{A&Rgpzg?DV8_bs* zrL)m5<x)4PF^3)M4*b=*CbRtM3bAUJ3icpzLpJE?Mi56qSc#FR@XJO}T>46)ZW{j{ zWVn*=d&@|dvm~?7h=Gce*&bxzpG-|IgjZp4%H1wIMObHn_iDEeXJu<DgRbIOz{;x` zz6&+bGsa&s&fnSu7GSGT7DYI5PnweJ%GF;I6Tj+RRCibJ8!vvP8!5}*D0c@c<7c|T z*FM;upV^}jm$oDhsV(<|$g^Z7jxm<hOAn7#MqKD5yi;z#^n*5S@7LS?o^k(K=sWG{ zYE$UuP#dFd#|M*c<4U;wB7rSxhIOaQJvYm?kwYc7KYR-fC<9q}x=m8gC=qRhc5z4B z;lD}_zxv;5A17ke)Lhzp+JNz#nTf{#+8y2|9_alYzJAslfhIhR{oBGv<xmuwehQX- z6{cDNExE%QtVfAaCF1r>nW0}ufOh?#tx_`1xSwJX3#yUh1x-F3+l&8oXn1&5e}sm* zll8A2E<uhEJ&K~d?pKe5uAy9&Y^ZD{iu7`$n4f$pb3DJGK`WCew3P&(I?C%@12i2A zvM$Mx#*7(N{;9hD%LR`0uNHUvX4d&`;bQGSRGSwD63-9Mi20rLY^2NCp1&{-Gl0eW ze5qLpzOZ(;W$<Ml{<qLr^e;H&xA+^#E!+g4BKvQPRtGZ?=Q_3?2Of5if4g-4M*_#& z*v01P_aaJQSYCC{5lW&LEN)~gw2@_W`|D&SEsOV7mnxW;33p|Lil-OZl9Nt9kos$n zo_}HsiKNQSAGlFU?2Q6GH(UGWa)Qg^HlJM8%qZm&2#~DHn(SW^Nk?RNC0_yxLUX@c zPMgw3EL7mMUr_jK$t6vmG^Vr_1wDIAOc!lKNue#Dmvo6aXMqVY8T-iRUxxD3qM2sf zdzJ0l_+<uAkjG>KwTxX?m;&Z5gCL2y|NY0Q#ihYECP7iGMZGO>uRgeF;-Z-!S5Usw zSZf|Ylq8KUQrQ$V(COJ%tt0<DqBopPsZRxG&76_5U4VfvdHL$@K{i|~iIQ|W*kdFh z%qs{F@?2?JboU1oE>H`UxFY-OxsTP}-FW{W#Hc0DUrc@AQ<L)u3=csYtM6N*zOAED zlnl9mUeL2CgJn<cp=>g;a>?zfaMA-#4h2gUE-#uRPh%|O!M=uPg9uu{@Xz)(=JSDy z!D$^9p{3>bqzkTh+s1K!1vM5s-oCWUeSN90G^){b6aBv;4E@B8WK-=}UQSShwDQfQ z$F;2w#6gKYd;7~X0&l#m@V;T?JM-p}mYcJUZ!C9)R?0hEIauf{pMAb=u4v6&AvQB% zs>uz$9Oc-9E`qEmcCe?~<V&wCy7HLt)c51Rz~g9^Msr)A;jN5pTv64Hx{mVRg1CLp zc^cG6xr7@5#{h9btS%%Cd#q^1#k)I}^kXQR`zkTw=K$;(l>l_Rwbk$hSyOwTwvlY< zgS_DGn1>teN59_akw7u)oejrj6L-L+Pc)c&>c+3UrV?VDG?fmbwP<5`eG?7cXakYI zXwOpvT1w|PQTRqpcs*uyG1MRbit7@#_&L6!F{qzaNmAsiYPjU^>33)L38}@2oFlcK z`vg<R=)MG~9qm}cOD)8>8l(Cj<43a+p^4IT=Q_frJOi3TeZR%n8(JcfZA+zbCn(!$ zNVayBU3&{g;jBA5HL<b@R?vz%eK&(j{S}T3WN57Wv&wx+Y=D9%<40cY7=hRg)q7jX z<#p&@mzlb21RJQQ^mxC4dxE`BQ5e*zf49zN30S=*${(v2il3;{>VACpjDl;PicYsA zU~fp~NbtGnix2~Z)1wDVVY8Jui;2h~-9W9kxl^KDuE0?jT4~X)E?m?idydg}!@5M% zx4399YPO8rCA(<Oi2F!GX}s#Kl?W9JIL##XS#k{t)M@P-?;cBK>hX$(nzWq9wMRUo za*iv1l;ur|H}z&^wTwH`-H#vUWxf=EDS1L-K2^XH#E+d?1H@Qddz}0o^w7+Dx_p0w zciq|~dXTc)w#v3qX&tGfail$PA;x>C_f-|q*sj{6keR7p($%WPtWiEg-`rS#Mop!E zs8yfITCytZ4_Bl$6G`BGjlOg_rsleC<>E{|@+8mP<7(c5tD3ufPnu2ro6Y$NDmGPe z?G65j`@pP&nxdhb)B`8cu6-*jbC3jz_SxXccB<-~Z91#Ab|g(YG&0?YHbFw0Cf`<@ zZ%8c#b2h>EPSGX6GF5Eg?P6y6N6DsUX5#FLUY{_`X@Y5ss>h!{OLt6^th&OE(oWj} zi;uq+x0jc<XI939^2#znJLhqG!DUst_@e3Kva^2wNuMuqS>J??Pbj6JtTR704lm+{ zd8XD|lUHuCx*S-|m<yShs+YDCGIAk#s8;S<V*;wB=&`-}4+5<m8LemetNvJwtrypf za|oAvmxBvfX&JzT4t|)uYwu5!zjCk?{*Em!!=F#gM65{>io3NXH1lFWlG7D*gd&q_ zLARLuaZw8*`xUeGJR*+12tbg8?)qoGw<SRF=0m_h<&5Z$B?y+rmwkGGf7>0??N?lF z_X5XS{uQ~zr#iJtyZ|3NBV4ookjcdp%786ved1t%iteT&AP}dxpPtYiDN_Z%hM+_` zgu(RnQ`?^#fdEDkQj;fMGI<iIn+V($K><M_g{3`Jv?yTYy<?l&#!N}K1eOnxa)E9v zk%Oy}JpJFtQOL8~xMO*u%26=@kw+c0<Ox}>n%U6|l5|-O@yg$9^V+Wpznox23Vpcb z>1LeVku|V8qhw?pZXct^<YH&LS962E#>J^TnnTydrY<*HJ$F8L+{-ls$)m9G+CI7T zrLCA)!TQbxq$(u`y+hB(+<8oTq$})%>Bnr*QU*xAU^9+V+;T^?D`3E4!glF18(LD6 zR5kFi`o{1X0AtH;xH~)$RYgJeA<k>LYBTC~xww*vlEC9#M);QoGdnlFQADS+_bF(* zEpdT_T=QDCjp{#l*OvaAo!5(Yx+Yr>yO)@D%NJFpR#8!nvu$y0wgdGUWu@jpqBi_% zD)3IrA+?&^hQddq*sthH(fnpled9Q>V&e{7(b8!~)Oc{tXM#q`kOQ*0y{5eeT$eyI zIx=f#>1Dz+L{WU!+SRIjU@I!}2}X3T-P0l-%+L9@nV<#q!Cg8mS5P{8@BstFd1>v{ zAZDWE+2(7(VjI-_vmcwm(Kz0=VI^~2-^<cTGnZ0P@>kH;+qP-#T)P2^&PXow%tMcQ zauJ&Vx1w4PF0LdTZS=eHTqqv>;jIAyyU_NHIu1eOajM#<*kkO7FzGa$)E9oF+s$z4 z<L3MA@XH2OHT#WIqk-qCkvIg6ZGwd*FKbs`P1YZ~andxZ+j^~SeQr{5G}u?o?bK1T zcKLc9)pD}m>N8$3h2=bb=`(AvP_)kV7Tzu!L|f5V#8T|=>G4j*7_1bNqG~0sZB54r zZ=(O|9hmObT6en7n6~bOKVgK%mK>0Br9s;vY!9zwog#~_CI3QBV6*HWS2|Yt7*NN` z?$W_C<CMpdRd<Xx?9lI>u(u&7z6No<D?!pJdP1Wo{NutCke}?OTkB?no|qV6X*ygI z2yQLI6*NpxflB_uwR>DlgZhHl+rv`fZ?dKho|*8M?r+`h>+KyK5RJ21EN$x21`buJ zPH8r;O3wS5Yix`*FE+1Kw2Qgbxl~t;+nFHDWdU=d|7lK=kAvklV}U5BgJ|my&yFye zJUPtVG19MFI_VoL8{mv1N?L{Q`%%h++RqLz9*m4DT%T8|@7BKyV$2sUUfOz<)#rI0 ziXH~3t1jE^)#^9HRLx2HNggGqL!oltJqd#*GthyCjLQzW9<x^=sN!}|SbWvf)szz( zB3>I)qttwF2Xw~Nid>ARSs*tn4WOD`z!bdeaTMC=*MNbPh5pu)*23kdTnS5gF}maM z$w>OG{zj~n-c@3D*;nBMtE%5N*D&#?6D5wm^YYPiF>zC_9*BAKJ|k3G1gnQ{f57*+ zcJ%{1=iZM?tN`nZjy$xbH!PkOIS*Lg0ZyrXJ^?hhvo|m<9(&Ktoqe<*(?is^ar@S_ z+6adzrsae^#LDQ5%WhD>!nRii-39y3>#+u=_^N`T)k|HXa-`s-tmB)=$11iX7mF6{ zo<1Rrcx9w#h%(tdBKX#e#ck~x+ICgpktcV>s%etZUiPiK@y+J;r@7y}LD}}GsVsi) zZx<`&FX-DyLO{e_gVDoNpyil(<#6)Z;F;>G%}-k^?^JC>SQf;BxSDk^<?Pg|W#hy4 zBRkJ_3#dZc@GP@TaXpg?qq6k@=Gc}3*-1<8v|2ihdp@r9qUDA>PA_Up9^qAH3ughY z>Ezey2{K0O10cO`i@~R3-fOw?q<R1`b{T9Y$Q$1TYIJt`Y|<f_^fdhz1v)HOyR@+d zm&n%NR6*z82vSfcH<wT*1{t@*&EBrsdoQ0PY)#G(?-m9w2dj9_bwM(S7cZ~0dEsZL z6t0aHlVbLE3+i8oRM614$RkCk3y>Uk2x5Bj0vO5Uf^2s~+Zdf$Y<YiOm)S*ZwBK@( z4iRQI-PM?0!p56|L!txhEx%Bk(CFo>-_o~;5_xQ)I7!Ma6DZNzr2R4_&lF<m{q>@o z<&HsDfVlO9&w<-?1REvSMBhaNg{-Ff1tZc<q4p6nC*TN%VD&gd?pdnLIZ-Y3ZJAVO zPq3{70IRw19qGSgKrcqBRwrP*M@{24mXZ3(F9T;NmzAo*+|U7SX`+<^`jJSG&%%dF zg}1qbQ=|CY#`gByM1AybtmwC5Rk4LU($r`Pm#7z{%(HfM(_gyZ0L-_UH`uPOL}`eJ z;1gr5y`B+#=jFg|qGGm+fznYI#dnum*+aaHBk>R`G1q%00YO$lOR@33khQlUy3whb zPhCj0eIG(^b@9^Oe(vFyUX{k^xYRD)#h$^%_S|a8LX&F{wlnXr93#6uyUDwqqd4@X zY18ROmOy5u(xDl;?ck^L#1+wnPmYP(*0)p=^PS!eSv~}+wl%C9o-^^Q9=pk}ue1$j z>uLTU+Al23B=63knE;Nq<ofRnqzY)aGHKzaNk`n?<chQ`VPt!2N&z<nO?`yuNtn%s zjMZHKN}5(tGD;SXE3eVO5s@Uyl=5Z`yt6hcPtPP96{sD&NOgIH0*C!5r9BMXgsi!p zSo-386C>&hvrsW#jqII|QPypf$m>Ru6?#3(!D^NFXy}Wxqii^)J|z+F{0u-}i&uU+ z3_xXwTa%OitL_oVh?o7nRU?TLbc7FH1zw>ZoE}}ifgXETY1HB>9~g<OD@f$;Zr*dt zFhmMCF%1;fMV9Ygg*WNI<^70WZ}iy3pIPaYs$d2D%?eMH>fr3%y70s7aX~qXWp{)` z7V^BEs8#S$v%@82lJ9bD2X#%btV{s1+|oV7K5*VmJldFKx929*xr4upa(pa+5pL!) zxZs>Buexl-OA&nA<}yD;$pH4)cwrdL<eMvt-%8zG0Tahq+Nr-?w{k<p)Ym5L+@})D z03$#}szY?F?XTeqh$?JQU|3xENX{Fi$ISf87#X9;17MUB_e9L|5}Ip0QV*LyLR^Zj zYZ}@4{X5Xmki@J!VJdv)#UK;ssBmE74Rv0tJ!qJ}x{B01Q#E}qgg90IMa_n;R87+k ztwXmntTX7ObbfiFV)FI9>h|6lgfDT=e>n5586sNO6#l)W=7tYXcYnqW{%Sqxol`xm zea*+ZDBM6Y+o(6fhDvG0mTfdhcqc+swtwTOs&|q>v8nV``UP0fs>6?{7|6v>hH@mj zPgLLbU<K~QTh><jr6vPYLD~2jkboF9=o!9RLJED9Q2&iRzGUnOq5haA^wq#Tel%R0 z$Q4~jT^3}mgKr=m!&`~UsUi{$&)U=-9o_dw=MYK}7H+oT?ehKCF;^L4ZA;dkgMq!H z1B;g+5hZqTywZ+1N7@j%E+)hSe5${^fEZ4AEp7S&`YDJO-V^S{UdeV^xzPU$;jU|R zsh&JNBRX$z#BQTGN!Tk`qv#GYR&`^ZymG13=Ek-0mfbjmvAO%<n;lDdkly-NV4v(y z2zpd=qt_n8r=seEZPiqotYEnJWwbAQyRq}QCBo+X#s2{VA<WNCL|xX5ZuBCoo0C!? zCU#X;a$dgtN{(}FZ-jrl;tY~}g4^p^PH+MbcT_mUBfDWc(IZI%_kwjFZV=8CPLwS1 zbnQ|{@(8?NN}l3IV`p;+Cn)u7Eddj3o_MNErvUX6C~w3-6ybF*>v;pEx7yF>-I!4X z=*kK`%K>WoNdbXqE#;DMedC<Ntmeo5!Ms<Aw>^Y_{foAC5Ae9|n1(fd;Za{cQiVH5 zn7S4u$tuF%x?G;RU0Nk)^rcKPW!G(TmDt=sq;*6)##!auSuL#TGJoPxE8DIWYXf@n zO`bBOp1;4ifbu+4yu|u*I{R=<ReQz4sD9Lp(nv{t3Fi}oQG@ro-!a3PPBuKT=;^jT z%yG8?ONF$h?@dm092=3}rW`ldKOkAYP*RZo(3aN!<`q9T{%(8oJzQcrqkyW^MRzUp zOYu~&EuPg4C1Byo;s$-)hcU;PhcArb&ypC~8EuMBb;Q0R?;Tw{iW2Wd2X@CM?4V_D z1`*msf9>u0%G&!c_z&8+U0*DXr2nfnE_EzaZi}6;)|0q8rW$G`&Yu|8ZKuN=7+c+` ziOWI^Ydt9cVk^zv?)`}TV*{5<qAq6Z1|aJ6O3zK(SozL9XbL<P5yliYmREwtKi%98 zk`zn7#-cJr^b)Z3^~{$3mNui2ahpR~WQL2zRuhvwSD@lqYBk{(U^U{DuXz=z8E}}y zYt*yJlC8yMBzjtDe3GFBlG3<7Ykdunm9CNM=&r@o%kmY}_uKomdVcaRxk643be77^ zl6Jej+BFZ%56Qo1Per#jHg)^*dxK(eI>w?NiyDvJvsmU$I+MZ^K;H9=va4okar2~g zTz`)Aet&(vUV{0gUIa#@)C?>xw(MvZwAeQjTp?cl4J)>k!56F+Kbstm=wex$^68ms z$uyt*B7de6pll}dy>WTCsq&?4Cc}=>4prV)^LeCyB7tMrhR~xo`6dN8wIg8`{pjq= zr(;()x9|GpijQa2t9=*uvR;#5_bTf_RJO+^35!$T0#qm?pou@d=;~qXTms-oNgC!J z=<=2rVqgBBpnj0=-XY!_j9q@o={xNC^s-GdG5iHgOP>0hey0o;bJJHxDfcO@dY)2t zqfcoQYnrJ9XVS?hrN?XL5d4xRQCh0}$zTlK=oaZjjVCbg4Q;$GAR1!16ShVE@riL; z4|`WSFxh;K)SzwaG!b@J)P5VLd9@&5<!}20^WAxI+d~SlwS4h$F~T5ecwnAOIez!$ z2XvG>`)yeH8uZdgAeHQ;#gA-qmmU!Dw((%1;Xxtmu>5^)q?9`X`|Pl@mjo$GCBJx= z-K2$rjaaxg(NHz|b|v8aQIriur)g|EJE5)q?yh+7r-9zjf+|l=FoekhMX|k<gHpv| zC*VhC>Tlomx(;;g>)Htb{@QVG=n~ywK~(CEvgh+#2R-9sR6uJoKCn=l_wWtpGtp~g zeoaLys7V@ss_cl+u2}o$9AuoplntUJy_wsS!%xjJ^Und7MC}@ifQ$oDYGnoE@&Vtn z!3~c6axuCLs<TJ_#jlw<0BYQ|ZO5iy9F0<^OG=}}Fjv2>9sl!_uM-4id02j7>i9i! zpFWL|rnS4#=QpzeQ$8&V2m@bve(>C>6Tsl$k1-Z|9D+kQnC*kLt;(m!v1MJ^bCNQQ zRIrYx&em$vT@KhVK50>FQPTNF>=Hx!h3-Wu@W8!eWW@4V0C@Ly*ZPaQscU6jygy#O zp-$3vIPUXEiJ{lKS?2;b2V{87L(TOyVL?9BV35H>w-#sPHrkFC&_umerP{F@;;iu* zdxR&=JSWJ=9<WhVq>?|ce&`7F)?)`m>$6r+DVm~<922*%Fa*WR%9YP(){8buzVelz z%ajq-Hp#smh$q?>Zi5@sm=H^H9Mm^dYeCu_AO$R3;l?g^k#p;(oV=HSHJ}D2*_K4` z``er!+{L(;Y5Fvv$)9y?j3=6HWLGBRLJt7<X$l~{e+g)4U4ZHFER?G`xNvg#b+fie zJ?=sKT4gTj8x6c=&_E0acyMgKmKIElg_UPzOZD6N==xLPbjjWB=-T)e-Y%NK6hx?p zD_k$}gaC5iYG3Xy?mbY>yGwjyHX`7)swb8QLi!N;3yZ~2SvQ_d^m@}AIhbWQ5ynEc zqq@Eix!GQRE*R^G*bM1EeSLXTdJ~nha!*Co`MN`9f&tg15?BQ7ww*fwdF2Dh7(m4~ zZ&0h@uSO%CdW7=>X-K@YR|Vd&U^MvqW~PVn<sXv?SKlO&XV@Je{Q}4n0PU@VCSz|( zo~6t^2HM-}z!Z<5PeMVIgQuT_mz(-3P2RFL9H0Bhb9Q)T!ll75WN96>u3}uyL}Hdg z7rc7Dv4y(}w?uTQEsq7<Tre<*ftKir)9F-{3KwxOOV#fN0Uz+h_dMbvN^Z9|00<Ek zfp>s;KKB*2AP$X8mNt=O*t}?9QHwBy7b$j+i7aaj2B1SSOdSo?ZK#Uu`O#x_l5?U? z-F|WwY$0B&A;)Q?R^E8rJ8Wd`MFst>k=aP2)_nY=MBpJ)w(2F%a(7^o7YW1a>c;yZ z^qCB#C*@?6gt7G{H%7s{pt*t#Er?A{mP&%El8VYn%S~Vih23IIjjzmSOdJ?ZuV}Za z_t2vBD@$kDk;H{f6a$S<X&ylJJ2MSg^nd%E>Xvw(N!XZ5U%Msul66cgsI;uf<wWrT zH2<k*SDdmZ*(@Kxt?^j3f7KK2x8|`Akq>36QKV*PC)kVR&1Xa<_u0*i-bW-}Zg;l6 zth}I6R!esA>35XYDyp9@<G4`iP1hmexZ$3)`Q1NZC+BP8{w0<7_C@94-meM60V5Oz zy|wJ85$zwUuJ+C(zPeg{;p__MMDjkQtiVt!PG1p09Fe7ilzTvQ2BXm23rF`M=Z>R3 z={oP0LC+*6XpMr@uYW#hVyDwrl>?hJ0vII5c(1k|{nB;9Lc(M%3PZCLFZ4W#ev|K> z+uLtji{tgDgcF5`Pi0qPU86b+izMit&z&KbD-p{r0}^r=Y+amViyvESwv<;8CEGhs zg6@oP#M~R-M7>am-Km-d&fs@5uf&0eJmrExmq_(gfJ_b&qo$<1pw<I9+E{P1vDovh zEmxtGoetMEd~X-$Aiwaz1i@NvU@1SKRvH&BO?YiEZJOyZOrZ^A?Hy!X*Y_cdTES;# zL!f8gh*J$*0KD^!s@aBvSRnS@E|~0jKXAOJV8=pb3U6#^b}BKK0!*1KV62+r8{q&S zI!hRA<~M4xyHo5!Ian48;yBS&$=U`_%Y~}7a_Xs`4{gIY`5CfFYqe4x>yUF!kj{D5 zl5E1pLah&s^$Azo>b9r{$PaikdwA_ko9d{gErWHzc!A5?$cThd2x$={P@E%7i|aIq z-2v2i^a`h-iS)TQ1VXh~emrmO!SgZ$5a81yTey~OT&Aj>Y+2HNFJXL&yjhSUdm835 z_o?n5N0`~2$qa7%jV03hVH@|=<8?`oDi0O_L8&+;PBGz=<6L{CiAe%J&KdwnM#MN- zuno_MRMPc!f-Kg=2b87c7U^J;c5qMTx=fPl_Ti@ti@&r2x8H%?RslzX2=sWLzc@+K zmnAXxH1l188>yfak3T@v@Rau`BQEr<<aqOYi40Cm!Vpm!I;-{<tbti-k<f4TPV@@o zpLiqy(jTp4;{LTRwOL)S2$Bb{E=M9#at?;JO#vCWDu~#+mK?ug$UO%Ol!#mBBfWM^ ze8vDQ#8>B(uLmZ@1T<AIT6{;*uA;a!S`1O~{IJseYG~eTZ!v&R7}i)kxyN)V)N!wt z*a!jwQCEUm{lp9S40OXR?>jHp_t72pYw<pTfzscP?!(0~QWaP6=H?70f?h0(@1ML_ zlslRk1uX$TU)+Y-R?p&Vi2G|O_ARS{gXVEhP%>~~C&5mqL+$jnH}Ud9%yR<grC8CO z?BwPtYRfLKz*idHX)M@%k3IT039;yZr_BNX(OBI$?Evla*T}2-rlO*F)EqGJN<M0^ zjySf7vfG%O0`a8;Fi@_d4E-YhA{}x(8wn_Q1z#s$V}B^FUOp66JphxaYbTEPVFLnK z8spyPbWFgoWRp)$`Q(d}Ac2?;|6MR*yKfyezHpi^ud#9)hN!GtghRz@hfIzh9IRZ< z*@Mfa<>?L%dBP%}dC@}KB>#Q?Ui6OU3$}Zy1CV_PP)NVePm0&bKv18UR}4LGHsZdg z_(Dr$T(=J+opZ%6o6ptrXAM2JbjG58@;tgIix$%VxtuR0@moSvjib=0&5g;anSnho zc8ui8QV>3>fAh;q?gPpK^J^YtVP3oyWnF9LvSYC9DcHBB>2yvtmDzeZ?Pd^~#y;-{ zb@GjotQ%Fhc~(@W=9omldZzWepbJr^MSmO&x?&#gGHm(Ag=v}^{NgsQ(B2I35%oJe zJ4GQbW}3I+-g|%7M6FeW6#uBYS;91g4xqJ$w+v$|o+4A#SqMvMgBb|`_vH__mI>|| zSi<GbEv^39UV6|rb2~)03DH@-i*r=CbqqLepWYrEH}PZhFfY2Jmtrf_aGS4gx}nV@ z9t_f<ZC<PakS&ojK4=}|7u7*NqJmw_@2u-AYY`>InK^1!%*!XmwA&nefy#9npWD3x z#8FKe>{l<`cvI>TNJ#bP@^<%q_=^9{UFnC(wRG;($!Hr0hdXRJwNn2>F@UZI41B*_ zSf&=mqB}G_zXe{t11mvUc;4OH){yO!@c7&ZP=&U1R?e{YyKcUBOHJZ<c#;=l*86n_ zJb7J8twPftQ^;|0P@}UzNL+CBsZ-ad6gBHl?Jq08UD$bNKyXhFt=||9d1#WWIkVIc z@){W8n5tqcSK9xMV&7hr+qpYPU{UzaTQ&*Txe9nED>eVYVbudbLORnu{qAEoYqH7! z274C8zIH9w)lPiFhWm}%iWha~<j;r`&rH5i2wL8dDH~j0018cw>uh(D^xjVB+BD>> zQR=E8KdX+276G%(AFO4<KR4Ipn&q<HtG6)bxLaCkD_^_PmE`2Ug%P_$JBPSxrHVmN zcy(gSO<q)olbB%#g<=aCfc@)Ix&%~+NA%#a1CksQY2iG}0sXEOK7^ant75)u!n<Io zgL}w6T(&<2xeV)J;RHPXqaXQDy(B<S__hGsAJrd4u$+5GK(WU@Nl64F8Hq!sWf4=z zg5Gw%$6Oz$hFS&-){t>2XFc~JN~a;Fre954m-gV|gA#?OOxn}xeVjVog(xao_n4Zi zqSGUQ{o+upY`<W5Y>V*6iFN6~m;4PN)Bzq=Mf^v!qj?b7YS%SWj+_3mmilImsvzRM znTt`9>$<kJ_Ts$%lP}hU+gSReOOBNRv~hcAU^eS8#!9=QqWoG|`;MPl55NIr#kjDn z2Sh~BRrWG3=|g&VWHMf6FF@)+yNhWn+h7{1wc_qR&&lSwl&))u4hqGy-vVbY8Wv|Y z+}l7|RQktU&o8bFQ3fc$CYRTbQ#Yd5w!x@x5%r0J_qM>3Ud9t*XbkJ<IY5c5`oKJS zW?|VXNW&laB-&SpIl~T7@+(coIm#CsCu8M(v}bFLbs`|UxXgq=uKFV0&d`;_%B~u| zW0B$3aW-Ow?Bi#eJ97}L&9Wa(7g)<C2MyF$$QRL&F#I1R$~)}H9442|>CPB^ujDDP zuI8gEwhi0@qitfL!II+|ld!=SP)5T$a4<A@i6J~HQ<6?FlJ9!An3>*N5hkCCb7+7T z>7AoP4G`5J{6gzyhdEW|b>MuSW(C;K3#Xd<_rPYrmL0Dsms6{tUbYS?--q|;0@5fm z&lsw#nP|E$ZQ)9yx`hM7b6I<L!xy3wE7_Q#o#A)ctj6?A<7ZunR4BogNti0DL?wC) zJPK69)*C=xMtb+H`vGn<knrtQF&_Tx=c5M+-+drv_ap`>CbK#|G~FJ-Z_bR)wtx^) z&b>78bFXiP1S=RA35nlxHVIFbh*~gdnca!C4TWBNFPdArh8k&CWV*_KzH4dmqp5k= z%IpVd9<<}U9$Ht^i(r3|qf<O_&Aq7n^<>9dtT3m#wFyRwC@DvL+Df%(vsdfhF%=Jh zaF|EZpe%0v*JYB10G1nlnyB^5DarOb&jFGFj#V%J5K#J@yN*rv>y@8z-Sa1O7V2Sd z)>g>Fq2NtayUI~f*lp+AN!TMtOjg_537xDYc?b=ATN#taqIJJ8F-h35$Y2j*+B3f* zG2;IC-35}29Lwl<=riU<G;@MPKo`UqA=nOzyV6+-Oj~_>>1Dqc`xAZM^CRJ@#=QrH z4H@H6>ETI>JqMA^Cu$^{<l1p801ohfySoKgWy%|&k#7kj)3!j21|X?{rpzHX;wJ5Q z7|YYMikjlW;0~Kl7P{WU@I9ui)TxKF9F_sRg&aJuS<Z>0&UV%&X7x>OlxgYCRBJ3M z<~aX9ti5Ga9oy123c;P=?oM!bch}&-VFmZ#1b3I<?(XjH?(PuW9q!8B=j?Od_xtXT zJI3ulYmM%n-8E-Vsj6AeQ?uIRe`gi?A9lGUoKxI^nU;rYsJHxN(3Hv=qfw{tC~_Nu zXV!ue!R~Qa^yxpV_P;y<220qpPTl`Smo#hvL9QS5t})SkAg`+>f0y<2e25}~1Wft^ zz4b>{K)H2nD20_<G0+$&VCc{2ljZ=%1OI`Ve|}ih|5t?6dS+;VgGYquNnJ^@9|^av zrQpmQR2F-+Y#`c0uY^(3Tsm|5zvz<^+msa{*B=iBITfA`+aiFS4xR-<7dRDv1C(0p z$n2&E1C=rq>U%QvmOnu1zj%~#BRtVPOo4VfSFC%d?z7t@XKerq%l7+MdvR2l-+oRv zX5|kQfXQBSRsPkP+{T~(#prRngCG4QLjpQ!1mq)+w+~OO7De6o4$NtAP_O`?8NcOL z(cUga{+8KQ*J?8Sy4T=ZB8GFTj-~jrlI-2!5CA&q(7FZ|@|krln|_Cf`=ginB8l&b z4tJ4ox5L$9Su6EW^%tYv_l^)?ilRC+J1HcPHww9RGBG)fCm_7ohhODiA1@XdJv+06 z{vV?@Q8d1;z=bZ&$Z>sljo2c>=)cLC*8Rd|ft1dgYbH*Inc5IP3KgST3a-#hRH6R{ zuR;D$mN=Bnh^9%*J&Qld+;!uU`!d)EFneFtO$N<j`LN8?^mi!!95p;CY>c(p$Fagw zAhPj)v0G<_*ZUm*4^e^HYXaC069yIp2M<dMyyXqa6{!Bi{iv65UIhgpsp<cpa5cUR zTWJc$E=}V<x#~~RbzGD5z{Q>pgYDrFE;UBKXVecP^Q|_>1CudO+kN@I*mr|fs2;Xm z%9wcj`>aao2yjOk6=S2ur?(EUQudL!`_bn4Fk6lGkrw?lJaljP>Ohrg#31T#RG{&( z_R7eq;^dGb{elBz&7jMv(iJ-U!z1=f@Ad$w5W2}&IK|a*l+yyS##xhS?kKeDK>xmR zVyn7<`wU;BP=Tx9PG+3Oq{@hS#vkwl0pR}y{II@@IU1rmL;h@Lgb%RzI8Erne>$ux z&MT4A-LIA$a{NL)vL`S|!nWJrNPL3|dKfb=1xKpj_L4YC6THQx8fH!SFxg#O3p98` zMA`l*{kJ(Bz?pSQd!;0`AA0}~h-nqn{4e>&IZY`C9klV&P0OKr1q%O1{0r}l>Y9=F z+l@cN>P=gs)^G&ibO{9sh**^c9O;kVPD;t75j5%qdrzc7E}y4q$Vb^OMg+XjMGwf; z;>+5(l-*69!!F&g%cYi}MrcQtJIMM4v4uTM#;^#&N`2tDC**=X?`HOH%k{GT?bLAl z(~sLJ!dj~DDP-#Vfo96lKLa0_hngr>0tF1Jp=#)uX*T8x>IO>fg}Mcd0)K)Gn9JK# zdHla}c_RxiuNd|h6}}wi5v6?fcWnSBcLrdaluD#%L~_pGzD{cT+P@9+<>VJj8J%-5 zmS((8Msg6yEPZv^n8QN@ymQ&m?>A52Or%@dehGI~S8)zu$|qdbGs7?Au+D!*t^Kjs z?8zgx{g(}zP?_7xdRGoyE{umicp0<|^hip1|Mp<`{n3B9u;=BRf!5EILMUHIf;Dh^ zuBK%j$XgK85AcI)$!vIK%pI7J{^`l^e~*#|S`t*vu>z@M@6CcYmdWhzTxlCNA88rt z!WO%zqX3*{qmML7HL+h}uFA|&0GH+EL-q${EkXM)^C6unJQ88?)aQ{YsU2Wp<gMP3 z2?TtQG;0E>TWWBvU;geLOMhepssMkPgur3`7Xsx?GxH6czQqDeS9P%Vy4fs*t)@b3 z8@Qm17JYf*2xXg01VnrH;(n}kzT)cXuIV&4Y1~(83_fvO4+!v(3b4Qb(%EiSL2RbZ zX~!1!n1#EUl;0(o{6>`ict|o~>N(nJkY=U<`Ny7Gr@H)OPyGqHg~WMv2zadpvVJkK zohRQ69jXJf`$g-0{cGRZfh@{`{$uS<+~n`zZNH05BaFJT*GVHi2q3DjID`V2zdV_p zy<uUboarlq{COSGSs+3X`-Iy)!#mfA#syj(ADHpvhvki!%g5bCA<&}x+8X$009&Iu z{h2=h<%9;hU0i8ExPJ$q0j<p2v`M<6$UjQN65;>E!z^1w&%oOX+z5Q#{$Y}vFy`22 z3D`w~bYnM^Q@IvsT$m$Jrm17=%1Es9KA4QsxEeUG`AA=>VVdMmleUZ<`T&N|zc|F! ztv$Vi&p{x!O-vaw3fa6Lwmmr;-Yx^b&nYm~F;F&jG)JIpo_~Vlfevz@Y+Pe;({+6z zFv({(X`dU#Pk3jRk6Q+p1-o_r!&vr<Ri<7v{nH?jE=O0zGOvm(S4`u`>&c83-aUa` zh^*iK*Y9QYg#0J7*|DK%o%B48iGt$Yyv8^l1N&d>WWVgLm*@b9{6`B?@^&tk?l1Ud zd1j77MU7ExJB_yijBFYD%G6Qvo>y^`)4YWNZE$Bmw6+TxD+q`z=HGfc5We-7cZ2TZ z6qjuZ_w|$*W91Z3WbvZY)nDQ=Rk2_f*iKqEULDISpYi=~1~eDs>V{UcHc|+_7-s!s z+FZz40m?7|*+!@FQ=s)Upo|*=1>@dtpHgs-!DFKpz)OlWkeJ}ub6yRHWFFRU64D{x zz``zo^P#g<U_z!kRULbf*~_HH!=H-2li8kspc-7h{)hWbzXjN;Sfaqe$T$VG5DzkU z1G%=tYo8B)`OtUqDa<%Um3DaFhb?q{d4l+#Ob(qI_u-FUOT3-G>f5i+d`dkOclj#u z-n@IcRlOARy)jmA(uUdW!!}CtmmPP*rlB9w!HD_#=V=D7br_rb!_Tn4T`(YYL%lPC z{_b&qE!cnh|DUgl)L$9)Z#dP8QdVO%*(!rcD~NuI;wkpu8rZ2k|6ex{A@%D;egf&r znpI(&+luYZzO;hELVQ=D>aWl~22z;hFQx0;pTYf6sNu2xb*rB@BDKdVXdu|@O;>`U zi~VvV!=LMn`e^Q4upl6Qi0@o^e?8`MQf!~#Z%9X%W7g8B5(o&E<K-lAfDKQVt&cao zDE{9(8h_;4rvko#`|&Wkrx9PDvrFJ#3>!5n{~xX(m3n6!PvvO+M<Cm5BoGj>=&OOw zMaR=jmJ07>WiBY)b15GK@^La;C}0Ji4o^FUOg20I)S$~psVjgV1O!bK9nI0~o$Dnf zi7vrmYCi)UOI>Sd4-w6=`Xtc%d`#f*`HuSK9=JsU0s<NSiT)N8B#Tq}>lDy*(K*p+ zP@ND;a!1kE0G!3$&>R^qB7Cg<^qzQWRr#kOA#{$wKm@bnOS6F7Pi+?3|0z-$??C-m zk+ektm&>sKU1U1GD9hpL5OJZ_vN+9;{(-EkDwe#2tJRm@dHr&-`PIR!lkI<1=GLbM z&C&T|Z5b!=pUMDvs83;AmYjM84zDM}{>GmBY^eNQd4#J;wX9J-7{)T>4_?`KSEj!K zidlnbf3;?Sa*l_d?7LaeUvF2=@)!{K+AY8^;Yz{qznf$vVKVII<*=V?vH2fy|1Qu6 zEa32e6d;mLnhXOb;tIPdbN%N-<qHD!PhdiFy|gD;z5msMpH+qU8P4Z`4{Lijk=e&{ zY^DSaO!&0V^4_fc&PDp4miSjE0&c5>#{*kI@v#969%^}=`QPBh|1bS-5%r7L(R4Zg zORe$vK;MAG@H21=@lRKfg$ixQg8=ang8INy{_72ohsIn7ZJm_pbqSLZQ6pNkf8VJ3 z(~v;|xUDqREf9p(aR$;0`py;RTM-Ft%0IT1VDtYukgU)h^Y<LKfiuqEN0yP>8PNCR zCUIP_NOL4T{9mMMAc9F_nF5`Tvlf5K{1?w9NR|xEPA09!2tV_`o&x;w`?E{>4}cS7 z3huuMAAynNdVlQHe}mycKyHE5d;iD)gfw9Ou?he4uy&CDq9OtTIRYk_|GUP2-6F`) zCD3>`SvbaOda}Hj_#^s11tF1N9SA-=&Q8mD9Hvv4h*o@Fl**2W$vKi;rGo~W6md#d zze6pR1FB0(re4>qa|-+O?xIdbK4go-uEq)3k=MtqQYTt?UBGf#e_tv7BX0rN<6#DH zD~)AX9&&|Qz4~ghV9N5u>7_fq+o~F@z|unR<20F+#$1iAW=+Mkfg3UIZk^)HkOU6E zj_lH%etMGlzT8?6=b*Y9^H=KFKLQI@b_pC_P2xw>P<UqUm#lqVW89ca|16Gmcryt! zg=Hsp&+pn&`878+hgEpT3+YB$W3e%lCj|x<QT|<D{l_kWhXsK_Fgx8Dd(pf(1{M>M zBWZ0(m6vI1tGV(?fy^DHzVn3!)S(QqK9WK0i8SDvle%1#iZh-zD^SSsZxAX7BiU9a za5`v1Y%=lO4AKo46=%WYVXtcvohi2X487#svUrghH^5Ot8hgyaTxl4nc(BK>AOIWi zY(|px@AW}{s9V5gJJZu>R1DrmpFBO(YRo*P!jiUQS1L>)nd{DFZJk2LdbK>5VW5^^ z-0FBrfD+!(($6npEX#s4lv8Hld?`n(07%p-5C`_R;{{mFK)hE6%=c!xl8*XaEZwKn zZUK&Y+tz@CtA%yr*n1$xr8^S1B}6(I%F)}ZeHO8{JqZK4S>h(~&Lu7DgbMNx{H_=7 zy?ODS%gMY|=W24Hy+L+AhVQun4)lzvVES}S_wi6trP!UjYN|X|Yj61dROaq;DsjqU zUui5)m^TF&P=omUfaiET)O$9|On^@v+RwynlqHW@^lHFCuV#b!!22fr^?eyoQQl}( z&tO<wd9%N1&IM$3|8GPz<Jwkc>*eGb3#GfLO)ZSV7rRk^`0_!DQ_lD1)Yr-4nC@cO zMj){Zoja~gT1E42YgN0C{G7Q#R@mf!4G5oYh>x`Z?+Ks9%7TW48Ht9_FBAC!aFZWt zg;&n+T#QrNjRYKwK_u2Z;0E@D`I9}5e*dlj$a42zJx0}3Csq6%A4x`jV6OqS=5w{h zhdf!Nb+R7G>;aIFhEj!>gGTJ6ZVekiU1Efq`m*SvID4<0{hoaJ4>A$U{&JG<eljdq ziYAtY=a^x~mo;{Rq}Pztfs>gvg*=ybcNy~o4|8A`o|x`y_ogYcnxx{OyW%SR<5I_6 zv8(pouZdaPe?}NQIM7}9jtv>nEomWi``0x1M`n0F;K;wZWP<+gg1i94KK*@U@f=KM zek^BZNJ}NwM8P|Xa2S2L_lrbn{`U<)9pit^7(^eCPaOYT25|#2EdT#DTk-9DfK70S zaKM^a8#_4Kn;2OA`DbJJ9Tt{_nTV0-&p&2HW=1x)|D0$2*LhxE23ZqpGe>hG7B=81 zWd?D8rK5>GgSe%Eqlu`Ak&Us*ziwb6VrJpu<mBgv{ntBwq|JM{d#KLWU+NvExti!5 z${r*SkEI!-=n*3^!yvovA;%&^M}dAaRUG!`l|+jrhEe=RPV)%TE-L1s?$92uEOSC+ zKCKl&cW+YuBTVarw%yR({e-lBPK%s!llx^%mIAcB)4lT|(<YY1?4o|rtGxbx#iG1D zt|Q~js!#M8MkX(@e7t%^-xQsAZ_(eU+(aU?Nk74epdbjw;Jux%!Sw`8pzRfpcnwC_ zk&@k}x#g|1q@hDPxY!SQcw>5D?K#gq?^pExq5*C#53+5lM?K<Au);NW!@cJ&+u`_^ z1MeWKlm^E}R>BD{tT6So{z~mec5hPke%*288hf~d{)&TgD?{?HK~JkNOy|K)5BK%4 zZA`-Kw$iR;g>((CKjjz<`J<4XK@5BZMh5+*%45wm<a6hb5wOMMmJRnIv<ud^9h><y zH!L#+hz|B3Z>|ev)7d@6yT^KRc49U2vum!G9S+oWm~GyD0}^I(Xs$mVBpjgZqPfRE z8Im(S^KJJMkQ3Mo5E~KFG+)`cJ}qH>Fi2#7{q_*ky9eIv*CtgVi8dF@cucnXIriQ4 zXIrS^J}L$7kdg7lS627<v_5-u2I+fRmgXZ$*>m#2;YrF{6bkL(dd@`3;Z(-3R}``Q zR1a7;dob6}+HYtEwDb#TM%|UpDV7R;9byE=_c12nB!dsM<g!e?aVmSnOTlyx+q@T& z<3HXZA~u981~2OK{7$=A-^?-6KKPiz-w@24_%y|>$-;&b>u@G}NG&0+D}VC(vU>jP z35^SA;l7tXpbo@t$7OMe9e-p6n@Df=)4fGUdnWW=a_WPhUG^|+(x6rmFT2K+JznBs zk1~#SG9r~)(s*0iTrzDAv)HL&gKJ9as6aYPUsErW8{m(wOweYdWebYYmQbAi(rhV` zXQ$h{!dBW_s$QX?*J%k@k6lUm-LDpwHxdAMFxi@Cc%HVrUn?CN25Tmt%1ti7@GBM7 zb`@gdI}<Joyj!|@Z#8^$vLRj$n;rW%wC|~YY~2SfJ;{a<t+_3>rgBy6IGCyZoE=Tn z-7Va(u<V2VMOc}>l?SZ0tn|dDFJ!V({qf4by25UTJ@Uh{u)LeOsWSW#N^zMyC7c*Z z1_W}B(OJjkvawlA?d_`|@e`P}swwnZbB%1|&<3Fg!?DBs!d97K&0>wP#bt4r&@(Z@ z@%;dBKPi3z*pl#!f;Y+>!&u4z))7HpIe-+%4)!DgEJ*`&-QTrDF=i=tSNiSnt&~qy z1Lf~S22Byq+TX|&*u~&v%exm2Msas7Sr*nu7f#pRWpt>56_C^i3%@xmM6lR|O~R`$ z_QA!gpDgA*7ZYBf?4)?`Q=Px@bRUBYJlm4wae+=B+;~$;Gf#Yp>`fWK+uto0)4EvK z#znJu5Px9L#5>tULwnlVFrt{<&_IYy^~bFai8Go!y&15uiRybYhtffjl5KaE^W=57 zGl{UH=u|&77l(dVhjch_bMQx#e=H4!iG>L9Lz@^@8mhX;6J<A`*ywCg8V@s$dw?N9 z#}wU>Ri(z3PUKvmCVv}_RlPGucGd1|umh$l{I-HqCKP&M5&2*veB7dJAR8T}&3|(M z{;&dGox>??Cx$mavmnn@k?bqlqjij~XdO@E?wV5VQP9DEZ3v|To~rS=&otioyD!^x z-$f)M2Rji-_6e-2khyud%>1wD6jZ!YE_LN_wv^nVs)_F-V?XQ|F&d#tmDkh))n=O; zV$`Kn!&Wf|rRvC)X!UeN785jTIkd_Vg#ffoEmr^(99({N3b&{rN$e0++M$VlDif9O z_v{S~gJ4QFv=yz+)zhh{NhCwtl2z4oIl=hK=Fe40uoC_w(jrE0EBbH05h5H=!Ia?Q z51L+6q{hK<+rP6=`Pg}O=vf-KS%QCd1rM(O1+6|lc+o`vEea_Lyiifhw)7w@VvAhL z5>MQtMPpVyy-Vd96=$Amr>=>9IYoWgkSFY<jVlK4PK7hB+mLCRX<>?1v|I)wJEi9n z-^k$(H>|SxvAVyWC42(}X*VJheE@DkGxc7!sywpa3~zU7AWSo>A#t)KA_gT3EYog1 z#D?R}K+=>4jW$Q|4?vB^S}D>(<$5VAfh?<}?Vil8=w|~!#a4ccpyrg&TsujWObY!` z`yiQ=<`{kwRRnla!#P5QRhmMzQl`#DyZG^_`0wnF>=Ijwl7<o^p(dw0CKzko*6b?) z!C8+sE>5Ptk0xGuDBfsq%|M~p8Y@-2QWmV@aImyE0Dxe6i?;bvCn_mGw@>ABpe_F? zo6!>mGH;(Ox93NFE_EGg2%|<%F}X5Is>m<BfIAheH#}0<;XL?=yd?P85GIxlqb#2c z!66p&K^z}Ej-S|VgH;PSu>3G@gYdCm`;R2xrSP}QPX=1`8ndsOU|h@?-UcE|;*mnb zTEUVdR;44BN}xxaVj|n8gKL(8Q8oQKk%P8`ja6)k5k)OR&A?Ynb_VnlK2@r2CD7=U zb~#byY=M_;M71Fe3dQ)0;yBn!g=%)*p6?4NbD|67*Cc&pAyWr>fpg$nDPnR_;ybTc zI)e(9*5hhMX%kIL#!b;N27Ia#-GUg%`V3y)-6cT^sjJf0<(oLmF2=bEgM@e81&Va* zo;3+pPO!zx2#jJO;1t=04tLAy2Ae0~Jo~9aAgQ*TUgn!03nk4<<klsxUBoGos(8gH zum?(U{?kfs)h&K<fR+NtD9q3IJ4h7+nryG)3l*|uUXSit-BoA-ZABM+6ODiLGfOEr zcoJ!$M<ioCuLQJwx-y9HL>h9z){uKH1FwDjTa$Enx+~m01jZL=MqF`$o5Upd=Ahb< z{lm?=@D6UOM*dLv3f!0I^??q-HnL311R4lWFMi4tS%OG07D^6M7pJ~6WdBp!J{oZF zfj-zz(`KAbI-EHU$P%2wkMG4(tmt{gJ|VOX)7_{Xp27{VCP$7aBmOf3mGGT&$BL$m zYPe(QBN)Qu@kw$p2U^4${J4%7wo4-UwTE4$NNdfyi9qPWo73@@r^^@3g%);~^ISpe zmS%vrlMMAs4~Grj`Y!d_64-gfBE4aAYbpc7#=E`Zy+cZb?v;=B)fUbGzp>Y7hh#xa zuxes%tyywNx@@Mwgn=%-H|LJiRoUmmUhWq&K}$$cGr=E_!7N)>*i)=v>f=6SL6RoH z6JZlYp9=lHW%pU0az;?AjEc~k71gzsVTJy>u364jP6E?J9h>Jql~2kv@p3<Xso$id zPE-4c$Xp`?w6@*0f~69E$xzy;bz2WjaIq<Z_kF(y%{)`!P$TRp7)w%FS9V{2?;6z( z>zzlZt(6YLsH7b6IOWU~K8M^PlgTT_#t5U2Gtsr4FlG%<YKl<jA@2DNZO6Y8*n~^7 zu6U|m5RFo*NYxzyt1Sj7CXr5Aquv*;YC{o@j3%X8vO{#h!|+L%F0iPyDfQTma3xPF zLpX1EurxiVPkUamK*(*yP`e6S1MO#}q*V&c5PUY>3eJeJMrIYyA*OHKK#4qZ9UzEg zl%GcEL+G`JZq4pPXu}mZzpuj$JfebHXWR<(;^<pLcJkYUtRHEUprVo$B1apU^}T)e zt1Hk#=%i#Qlq!{@lL`j-hB)$FaY;f30OWNwea)zRPf_jHlQ-Ya&lbJCcTzbv>pTw; zT3@#5G^0PBub#YL&s+ptO&{L~GfCnZW@E4(i1AO2>s6_a9QB#G(zJe-5Qd5CWAjX= z_I}<dVKE^pWyX_}hvpQr?`f!GtAy5|@;?!mtO-U$+^70liu>)lA^_R&oVF?NwqeFQ zq15>tJk{WR^kx}zpT5$eZbU`n$UsbC`+jD0zB*gBiZJWqTm(^9?$kMI*^uc6{JReW zE#B2<9#fqR+rB+}W9D#i(y|cq$8HdKD19mr4-iQZ8b%gm9}SQkP-rMYSV1X}J`iwo zCX72und&3fa%`k7eH>oh^}AbH{Ymx&5aHko246DCLwR2jXZ#87Y>sGnlkPRvP{Hzw z^Pq%9okh}bPH)>09A~lGE*psXr)KzKvxgs}bh%LIDU7&L&*Cfz@qu=<?n4yu>rJLy z$wJl%>I${{hpjpdAf@#h!HH;NX^DW*x;ybu7Gf5bAryfNGx)MiLU_|VabNC*CESqX zXQyyAC~o|d7}Fdm=w22BTMALLPp0$3IV)7+cXIs*nq^0#plZ1#SaB+KO7rHWl0~t_ zmP7l4%@gAJ8u0rL7$qx8VZW6Gae{qyOK-q%KVIJs30Tz8<<~newV@t1n!P_7=vH4w zUrZrOwICC_kj^{bigT;(hQDD7F4W4~Z4I5TIzF>OT75(`>YO+bexi_x&Rlu0YTe~g z6}QHAC#;~T{7h;mBc3y#GFG<TJ-Q^D!z{cl$gk$`o8)Jy#mLC_?;_bNqh|B-<FNA! zG*($@?ZNIf1dD>z;-wJyaAm|Iy9ZMX(-*;~Uv~hHqvrYWMA(dJpnllM;~-=5Ss3e2 zG^lgc(-SOy!jWLU(Kn+s&f7;u9E^9lgIu5B)IEkBf~u4luCMX$slI2s=TR84IHYx( z+BUN#PsplX$kPTD%%=n=yQIKV9Y+e42nEK%<{NU#4I-DsE4NT(%rVi3I*PQ=NMRbp zB5(H5%K4xV<Y?uu*4LbA68$;>6|<&=tX#cjKwhEtF8g*ZyFbLyg;bCWdZ3WebA$8) z7KpqD;h8<B&f_f+o#88RjsIcLaLbcAJM7k8F$O=8baw03wjDeubeddbw=7$VIA5s* zrAKJX&w1!a_@v*6^z1S9+war2PhRtyglSjZ)P!l5-JqdA`|kiw9TM9~)7;Lm-qbLI z4LBZ(>HgoYF;}LD3E}gc)DHZ3LxnuL!XNdQpb9-1kNms{`#gxA1aCnv{5Z$2(HPdr zRu<-1q*QeJfSz{d4jC0sZtEZZs>C#zECy!xKWp}t=&pk#2;c7cXiH4d4-!=qJ+Jy@ zm>Z+4(%9;M-`XCGE^-?p@y^-4*QWLK;H};CP+8O$o#2zDt`S>Zf@sv<B9`_ZJ|MFu z@`57a$Ph#gn>qxNvTx*R;xlmty&^yKW)VWZPF)23BFyoEe);)mK-@tl5dSE23w9Co zIW$NTl`Py#ndfT{>lZ8z(Yf><dGw%~pSxP<wiP*BAZru$BLyIh`ilq4P}0&J?eFDD zUN^jsBM;7wy}C)gsSWK9K~@9JKXZ_TZk7w}UvPdL4Q1~>(7x~}-Mg&ugg3e0%9L7h zr$;q;(0dcXEh;6dge5kn>*816sISeJiRQq5TV{kjT3||BgPFq@UMC2Q1u#WVSaVO# zZIoF<L7-xOR`cT)T24urCtY$1Wwu|!?teGjdrv*QGhwsbbYDN}Sk2N{b=#a8_5NY? zMoVk3w+9mhnCt(Dq_xK!xmpIJ{dnCjdYz;OZK<#<YJB%^>6Mv~w9?8Qx12FHS>a1t zJh7`v#t|}OH#L6oP<F7uKdgNL0xy#*foPl6GoC%3eV$#O6BepVUT~T$RA}B4p2N|i zE#!hMe8D32C_`EZoXz3t?A?wu?tQxPs+Qlj<cxh^cY5&$j2e^6&8f|0HIvi20rhV6 zY12OJG)A`3S7%KA?tv+gzlqV%EJd!ZPN*d<DYCE9S-yR?AyuU2pfYwiYWqD3a+<k! zx7bO&N%Wyl8$U|Aez|m~kkJ9UU>PG2bluY<j9C^P#RUuJ+Jto8S3XPY4a?hse{EzR zBg|uZiqx{Ic(`hiK&Ewujng`CtbdDrz&&8hoO-qZA0a=B_Svzl-<+50zS$8rEc^>H zeeFEVN&1$f?*fdsbC0(CV=^it&vq8-3P7nG)s)8oR_y3?4945B=S2R;3JeD~sG)op z<OKJ2IBLhCKU8|vWHJc5Vr$75jH`T=ioc3H=eEBH8l|jEG72R!rD{0mHaaEmg+D0e zC7R<3jEH>j>;N)z8l>jFzv1@=UGvebBX+qNh3^Kl5bEYVsnFB~Kd6S4SP_K#vmN79 zQCYXVlD1T+x;e)O?4P1v^_z9t(}@{!Hs>^<lSGC~FHi45UZ$SZBe+W2cu!tw?x$~X zmyM*gmTd?5_u^-<;T&a*xCitNzNl{)PBG#6t%94)A9t5gZk_ICCj>zfl(<su5=TMt zAmJe${@@(##U_xyvh@uT;l<lB;6VE3C-5rJUHRB~s()$tNX{F~dx`deW>uRBMG<(U zM4)PFm3n)ee4D&i<n06`aKNpUtg-)u6bGNjP+*(v;fa>f0%e)i4n@DIZ&s;<F@Gd) znpsn%xOp%%y3Bb_M;|M4FIoDgK4I$6%%X$cER-~E4JUD`SBn+-E1kb`qLsVn_y@)V z-U1Cowg5C4G&;Eu7Ge+bxP%{3e*W|z9_Ff@2`<h9KgBX#s7q?HEhmbbbIELB2}((L zF@47c%@hmExrW<LKZoARLIoe03{UdHiHp@Y?B;9Uuz}IEw&ZWGi<H-x6D`LztxZeg z6?o4|6GcQ>E94RObT1T#<SJ6wF<S-zOH;e*(TZ`cqg0uK<Z)wZ#oarTWrVPjrEA+h zHO1)cD|r}uOUP7W*qt_8(Y=5fThSqYB?vz?+br1U(yU5Yt<tP)*pkw$GT7^qE<Fex zboj5`$uw9cpG5gZV_XzO)tRKw(@K47(Vpf+_ZHw*$|NQD;zgw|Qd>cY=krDF`e^ij ztei<E#FvI&v*Mei$pd`ksnsE-X{fS?P{nGFX~`aGdt@<53YO8#RnbaU2m5?fdc2g| zQE&N#xk6bLaly`txx|k0$nd}x@scKnbIkXsl<-=VR0PDGikI&*dFu-rV#`wzCSJ}r z-U&arZ%13q`$vKZ-;Y_IJb$|QzF;U+>XH!tQu5OMaLI^|vT3(8k~l1&0)l6P$~j=( z*FDpb%2%uFJsji?_V*ROxZnIFT?jw-{rP;OO_SGl9(#AU$h2CyS#PF2dA`1>cwg{I zxQ;+argjSkAj=4-t#ufx1DN+FFDV|E<=7f0I%&x_=+k_mf|vNT@F_^5lnv|Df&|iw zW`rWOlcMLEN4Sa~yjCO{^OG5L9r5EAa5E8G3UC3q?rdZ{`0fH^K~C^_Vyf&P_sF)y zM_5uM8PG!Cp!1O9rwzaGVEQ%+Gotx&S{b=OYl(zVsN(U5ICFy+3SYJ(!z<R63Ntc* z8`eZMe~0oT4i3yBUJgoM;FYl;fEE&PW<bwNa0jf{I)ccik@T5AES0i>Kl>lC%0;Jy z4bS(Rd~b8ZL6NFGMyc?!Kap8-J>Chd5m!T0<0X)6e#H>yAOQWvObxE+En2dCu6-qa zH#C3UvI<rE{W}eQ55E0;htmm;O^b+Lrvs&N&9tw~2n}q>UMHFFrwEB@jcro~Y12h< zkK7Dn=l}wNI1_WQ4;ZU0+3#SLH4frCSC@DfNXFOOk_94co=(e0=GO#eT}|o|Sd=*3 zGBc#)WPnG#wNLVj^bxXseAKe}S`I5&RPoDGLCG~BDDPxbS?P@ARLq_0&XsK^4`vNO z^ikk%{wD{nsZRIRK*=bN4rj2}Z9<TWG`_>NfN#8K)c#4CFVm_A3ZLqK9&T$rfvwnC z+xr>UHtDbvnWB#VzB9#5-DjdrT($ITp0J#2f$*E2LaSzU8)Fe)FfqE*@>KB$;jC-e z{=%6KA)<*q>D&FKXv{Zn7bQoF+@Kw!NUB>sX5tC_#K9M^Z3VV9kUUg_>sPbu&wF^J z#0gEgWpyOr=IHnc?$Vo7Nd~rd$aU}Gx{#D=?v;r1(Sq>gB43+^M#H3^<W-UhtrD<9 z(z(HJ1i4bcNIH9N720&RCdmYk*?Vk=MHBe>Syvg}uzG~VDf6QQ%hr^}SS3$QSC$z2 z^=?-LtnUQ_;wICw?M)j_tE2fal@3l^&;7Pptoz=NW3x5OWHCdR4vwE-<NC#E>dDw{ z{oQ84N=H?L)#a^%7BZ72`oqI~dEqGM4$c%~vh}p!NI@?(R%Bn93v4+13WEbX_Bli( zF2=w~qm~!aiq(+u7mzI}^xaIQZ@^Sze4!wCxj_KV*+j?%1I;XZ7WTrV`$qE;I-o3P zP52Qjpi}s#9GX={=mT$g*@8!!`l{FoI2Bnjn{ve(_~JPUB`)TpGXxP41lw-gR}x(z z=Uy-ctKX03og=j0a6OM>axWn~9w!BAuWUX>k20VphSiGWBF;Kp@m<^T5Sf(<u;{{| z^60)y+X`kxcGZ&O49)uJf~7%D0Jh2?C(O6}ArS%kjgZf*ise7SaE=zULW+JCLH6K8 zv--@7A|N9?!{A`ebX7sh&x-1R`JwTNUpWJ2z$T>-mRXt9W1#cZvZ}I}n$oI!yI(F8 z%J|OR_HvUPrRphK@p-jqZI}5~Oj&1)f3q_MQ0Rw*a4<ne4EtLb^Wj_xtMpmyhEGEe zvWjs!{~Ay;<cFSZl4jNrL?8N^MmA1U><@<+ZSRj)jUsG0(Ux1Rl1B>`ix!RKOYqB9 zOzj}4vLKy2U1cIxd~;hMiLk%|L9O6Gi91PT1|x!WH3`6U9IwJrxnO;uvC(D96&%=a za%gHL#}ECug-XbK?x)MIvF|5MsNu<Y;P()#L>wX>a3IB6Gp9f*{v8WI#kFfrV;w)0 zhia^#TaWo;97cYx(7nGn>HB7nZ|`*t*d^T4ihJ^L)KAm{yg)*NXq%r&7r36gOs<S& z!34E2F=!kz8{kN@E(7MI0VnhAMmRVqy(!;gg}xX^s9GM}X4Qj)RU{=WT6`%paR;YE zVEkRTmH2~bt`<8_KD4heC+C)vu9!JNY*#uR3^E|izKazhvW6uxl7HY7n3LK|gEZ_C zR5oGLzu0~0W#Zw~Oh%%TXxEHAh3$4sJhmV_bNN>MmV00W*ML{~dd!p&8&VE&-;k0r zylXem*vR!3DfYN;csRLHLC@hPg3t4<wbBSNVnK+OwF}lf@k7oFuY^dOpYlVHpXLL? zw}gMTOl;W>S)jr{05RhsrQK(vbD4e#yfzUom=_iUwsWxyn|F9tM~H8t-ho}uf0m?A zG`g=ZJ4w3MF`Z?bDpq`*GQE%{v0S}y$cH#TZfi&;x0263Uem*CuL5_gglGRy37+}< zY5E}&zcWdb-a(4|cBz)*!*S%u+if&?-}dc|BmCVls)m9+3;uNQjWSg<pGz-ec!3Km zXtJ`_H6);s5puz>dYRdcl$~xD;vy1S`cniP;w-0rJS3FLo&p4WoEZ#iL-z5A9Vm;J zPFCRHm#o>}_DgSv-`ox!WAb^d>7&rWOEXsP?s<|jIPn1{8BH&(o6o~G_iI0B`7o&- zw_OYcyswt7M~~b#q$VXXh$P(daDb>bWQ_$2eXyKSA-s0;dvItYLv)eVxOP%sNLE;- zFS!DK)uw{tfeU_VL?rNGj8wv`!@r~sNp`!(V8)c9LMZWr(XuDARVF^!`!8R1dv|;+ zLrtz5mC>ZRo~;F4#8_|IE$1s83>~3rYrHpSzW<inKk7Z}JX~^WJ!nmSxk$oYE3V}x zIO76yRSgA%V?$bT8WM%73oESH4L}!$+x9>Qh1+&Pw?<5v`Ky!eVRu`DPXrSX_G2;b z=o$DIeeMyD4res>Z~6=gNaXm$)B`<EqQ||0j+zjMLnPf;Jm?x8F87`4`<C-Z=_xjz z|H?`oOPOJOxj<G_Tm(kf9U0546>GAib^2uH8H_|tdGas2mfjfnLXi;rnzo%8yz5>~ zfwXJCb)+;x8b*gMBu_8%I}ty^k~hVJAYOqV0J}9LS+_BqfU7z}<?T~6UQa{0k5bf* zkVE&lvX|fJ0!^ZPo7(Nxy>hL4w2f9^sJQ8xG29y#I;-)Vo4Ex%ihPYIfZaYP4#N60 zm0eLfGXx1)w+(>VSt)55YW-Tz?d<+%w~8`?N1|6d4p!<GhW_#h>UUY_h5cNHFR;7L znME17wX|mV>qL`JH>r*A6Vw{3l$kG$7wh%;BsScycMQ3pPhq|N_Jhfk4s)EpgHjHc za{J`pDV|tZ)msP7ZA<LtjM3QeK07XmqTLl3qs=dG`G3bb-b?S|+Qy4;MC9J~L3QTI zj!H~a1ey><0}=^Shg>-PR+0fC{l?&Rn=sSHX{rI41;jH#T4)Z!s1SOpv8Xw`)6{L| zbq<DQv%kWf+=%0Y<sCK>KAyUnpCr~VUqvq3H!le*`9RL_olQrNeu~anBF(b9F*txl zq*1@%Jimk^+?9QHiMEkC>ocB#^&K6?S=b?f;~nKD3!=jl@|LTDJ*we4rQgz#gvNw# zvSn%|`t4f<M}`UCOmyxml!C6?)#}rv?=OtZhVPI=nMTw*P-h}rv-WBeE5UaBGhVdM zA3y2JBEKg&mbF%KL{a@22*BD<xtU2y3Lm{&3V!7pjIt8NT_ncFsssGwMHNz0Bm%KY z7yEscM&-S+k#T#*`cfo!-!zx7?Fb7Q74#YFTSGT~ga$%Fpc>@D5DvU(FYaAgpqPYE zuUpzDk*T^mRPEnb3S37#VhZ=lP~L|gwuz={WUS-AW&s67-yx%9dc@Uw6C!zhVJs|n z?9`RX{Z)Iiz<$O3DD6{j(_>Y{o>VeDR2qoT+wvyBZ$B$)fk`rpcu%ONv6)9O9+CKV zok)s*K;^P#7hw`hsvORg0&**kdsu~=3=iq~08jf1y5*XEXXyfD7&Heg7)+jr=-lT4 zk8#WA7g&$f<Llckn`{`AxtqUfka>eZNP8&8@u1o(8I+VRQ9deCWE_TD5#C%n9wic2 zel7Z}2V!qKOJgqqm1zbJA5t><<`^uxJM8j~?0X`EX}b5gg}0Jd;&nTS(}>7iVW)Pe zY08>b+(MkmEOPDq8k#{_S@%y0Rf-^f9SaOrV<9JucoQK#jHTKwQ4G8hUog!o9=PXN zTYfm?7afeOq{%e-=f~<V(3ESh1;e!8=9Bt7W0sm)h9Gz_(QZai*Y@o~_t)qsw~{3G zz0;CD=s!fZ>FeOz$2?_`*f(BIhQ4hYjG8~wJ)IXu(w=NYUVAF5NR;(K%FPt|_J7~E zG$r5=#-FTCcCHnx$|C&&-DSa+CN-!Dn!XKRm0sJc$pcgesCm+=dWm`Ps(P(?ZkMy? z5fPk=8bp%uuTOpCvCV=$sJ;3ZRV4=xs3xNEe>LGlo-yhNdGYj}A~*OM2chr;J8zva z%EnL-m(}zFCne-{AIfyo*G4n!W4+klR?#`}WGhs&MZKcBxzWE#s=2;Yab4E5?eRbE zJ6tXp<#zH`n>p@bEImj(S~VM@dcWuEY5Lm6dGIYVwdh6+?&WsAeBxtCV`w)r3J=e4 z;*=9bf>f`R0GsW~(WzlC@d_@Vfl+sZ58|2fqCCx6RUlvgiR_i&=EEU5YIqw=F9@gl zV+|&1D#uz&Zhh*LW0HGR;=M|f8y2Tc_<gSWssfz)bj@ejD9RUeY3ne5jCP4AC_*Xg z$b?}L;T`|5Xm=Em4*D+c=?zTPFoEGXP4ZBZJQoUx{s0EwPyHc3T`L2`D=+B}2ukjs zz3(D4D~VCh>pNj@_AtNAV|TW}q7(0TOFxM%iFwKVU{<lWh#?lw)i-Lk5&Lo)Gg=4S zWC~ufeFWbp^4uMfSS->BIaH9-17Eot(zWyUa&l^}`@UeMFsZ@BVT#G(H**>~Dz)=Y z{s4MDtXHErBDCP9q0pdUAv9o0)H*G)#Y-T3`fF0P2O|UqGuMUDfJYEji0qSsy|ixf zh>l;*Z!_h9B9r=SmTS-@=!nWl^U~LP1&RG?q>n3u$;yL$hM5klAdF~zusZ*}MlVIh zFCVS1Do<8Viw>b)#GM*a0|T+%#C;aWnTbq$)71~#*7p!~q&j5ux>h881@kR@h$ntY zTtDu#=9241yNXl0ezR@0-CA@N&YWX>`w^jW3)1WEGbJ<VM}T!H7{0-YI6I(hI2BJ% zh^lU%BEUb99S<PR+gxgCrN~=bqA4$@LzrKP5BQG4(fIvWT=vQevMHLE>z>xV!y0Mr zw&(sB*{qfQ3tu?GSlalJgBdIZ+<7!&Si;ei8^!VwYu$?hUkkL?V|)v`+3O{X0PlX# zYLQH~o_+DP2(=US)b7-C_AZM++j&st<2H;y7KeQjp|i@V^KYLy<x?Gjr6Mr<2_)~l z$D``B%ie7=uP8$HCj+?|gXA43GZX=~NL19-O#jMA({nR49<~&);e~ve*}*u8!Q97v z(m6JPbiApb#wX>D72i(|sXpblNKrok5(vxQ?X>lGKt~%g3O=$Y&Y!eA)Jl^IE;??l z0p=b`CI=MObPWDnsMdi#0Z&gO`~6%$xlAHt4u_CLxBEb!YFiC<DV`?8rumx}?v>}* zyazok!?kwS$JRs9z20kVkiL*or{3_-T_x`+7n7+J)?>qCl=mAfBA5E4R%Qt4>N8~% z49z7^ZTU*iZwTK2rm`Qk=WL<LD`)eAI+R_8)Z&QW%0QY@(Pp!sUc*8}J{`c!TR+YW z@ZIf$6|?w)Nd2Z5rz=Voy-jynuGgf<A?Iq&Sv<4~ee^I#hLigYHrSFvVtEj$V?G(M zqVp>jE_1)9^Y9b=eou%FXFME~y@3n8ze6@R=7>Ep17?#>QP-gkecE_{3fhIB7E>nN zm@R#uJ#h-0GJS9}%ncx|7SLuXUBgVL73(Z7aPCckmd7Y0L;-J(u=vmqG9No$b-wlz z*3QPD!zRwp{UFsl9GiPNELX2GLIfLj)oj?o>+wUq`8D*F<w@=-0kCZAxp2Cyd1N() z`{Mf&pTV&-gmxY2*hrjYZ1Dvnh%`EVR4z4TQiAlU!Dk?kDf?SCC~4_*6U+KUL2zoA z_?l$_*s>LF8YI|kmN!mcfsiAP<gES=9A07KUkEC}oCq7KkRoWx!nMXYI@hpt2Zi0x zR=!gyg@xTjRx;(uC~t5LOE5v}sMb@|NpcL2U}45b3~?0kewK1OioOF-Z(CIkTu-MC zNFE;vjRftTXUkv3@A+@r2PbkFdg@}TkuKVfhck!02}$k2UY_ciG-nxjE}8(hiz_?= ziYAvEB0Pv@W?ml)m|hiXllB7>77e6U2u+7yl0w;>4I5I|2{2>F0{R@PdCz0o=yA5K znsimA9dED-TE)Z9(SC<YLA=iH)RIvag>OQZ`0PO)^EQcGmtJSed+e@ezPa8y90fQ( z@m#y?ujO*SlWzT7W2l@Lp?}GF&GQhB91Y@fT5??9LNR0C)`-xL_bOvb4cBVNNMbD= zxYJzq!G0b`W)UgH#u-zzf}DnL!{%fO|7EZQZ#HH-0#6y6Z(=&c(!0$1NX&vK$&MnI zlc31TV`ZiX>)wd{Y_9NK1n+FC4qL4fd&d+j55XT`<%FhDfMIZREM0%xgL+!ou;E6b zVH)?zsfa&QnOC{r1%@&~-c?<h!5)8PbD~%0_#qszoSwi|!AiJwR9}=9nvJ1!7P|<> zl83m97!(n@O52AYbOl0#L9iS|1>6=k3w<jM#2alZ97F(hiy9OWuF5Zmjci&Eb1NR? z_$&{(1cC}3L=^P&6Ef&HI_SjA0CKgOPmM7s3rSZMNFf9k3K4}5nP5oP-0tj_9VjFK z@QXx8u&KathFv$j4z+=WnP5l0Gm%V{3Z)#?Ui#2Da0$FQIla>7y?!Ae%<`L;4{K)S zw3+9!0aQ{Ot(<AX+YwA&Ymf)M=VCI@XTgLMIIqp7sh8xpouH!Zr!r}88Wl0Vbp$A$ zu;keb0A)D67cRxbX=9v(OT!dzvt59rY`e_Dd^T6A#~f+1U4biX^HD=2yHaa9g5W9F z_z4k<8H_3QJHUVe-j(<~z>A^JTnMHgzkm+Gjrg?vlKHlu{#%}8BJb%h+mQqeIR!i` zAuSDb4#hPIHW|WrGZwh>c!kLKv*GON&61b|+y`@vc(dUd^NPkaE{{T98=ZIw8<UP~ z<V4~#TYtDJ30s$`&r&0^%sAk`5x(4bk{?i1mC4TlItgKp1fN7;hWi$eCGEP=S1AJf zV_RT@@_BW(UQzCkZ)C7!+<ADXHY(DxheneT$MHppmSaP(zNG!EHAx8>kfEWaGzV_G z?Nfa!Xd4r^5n|aY=W9AMyKr)DdkM3E#ONKoc74ic3B%$3fGHJt!czD2G7&k`zFt)o zFR6;Mtw92t)(GxTOcol-<7Xbl^p)F628Iw!lQ}M7Tg^B4)rUb<JoUHY<6n%7;$pNz z?sxfOTyK<EHT@>Mu8tB&Bm}asxT{!3>fz)%#xBQZ{;KnpvTZ)IRO!nAD4na>_C-9W z59Bslt^VlmmtTtqWB*CeQ0);}GB5V&sq<wQs?+->%G+&M%~U|O*Isp1<QmRC4LjcZ zOD9}&Q!B%#%GaN-ybh}G4X;hFzh0@_bl{h1zLmbI&I)40=I<dKH*j(9e4(yZH9J(O z)ZtEdGUai?NH@`Jw>rT6oI0oiOrcnD>(=)haP8=>k;}#rJ$hM2xfnN!6Op}0B5qAQ zI^j;&qjh3XMi6+i?Z^i|FVaQ;d162YvwiY&&d;Byn85H3S<VoCP9%$<s)iq1Is;4f zoVdRj4CQVBNBZ+f%qQ9C;Y4m?Is8jNoem>M6!qYlO7^exZcEqYv_ABPfKy&7r|Mx^ zi-v1vR&Xxys#VVCpkNh;`tWCtkQB=E=nvaRq-z)NTk==vFUWyb0x_A~9g^P1G5t=Z z7>?d%mji9o<a}-xUS6AuvhM+}SDE{sHoVX(UUplV?t34<oOXB9x0_uUIG5*djm%&9 zjC(78#$?8Addl<Pmns6@@?*-A&O8LXtg@YNclDzvH*ajBU%FgvI~ghyI$w)Dp519v zmU4AO-(NG_F%qen-F?dgkytIJqP%rlw8BQG%<Euwy?7~Cwoq}icm$07-sXxa*^h#k zvt|PA!7rAHto?M^p$iSrfX<ZEmrw*qN)iZ5Mnk_tD@MVqPiPEpzX$tT2?6TAaxy9U zyC?%t_$32TFv_-fPz_;{X70GqALRGFr+y4k0|LYfXSHA^c?2yMPU;caM`>Mi^-L9& zsz?fYH;6B)zP9>2479^v&<P37xv%i-%%jK-w1Ghr3j4@Ux+T0k#?byga_{H9)72B& zRJQIe<Bnp%yF%V5b1~+QZ`H%VAH-q7*V5S^*<YQDQIx*QaTEsiN@3T_-WXNrOw4?Y zE09`5m_cgA*$$Me@@Vxy#97_fJu!J&QFmRO@MMJ3^OtA~2%vx3osQBC2q0)W#CV#W zvm>hc7_WYCQaRqVYnF^2i}4V(sA+!lN=+OeowUP>zYJI$F_nHII_O2GrnJ~mk0B79 z@({z(lYWQ6y77Zk85V$plXFA8<L6e%F7BW9qVG@ePVYfR7&JzaZ&!05a-}T%sW(cU zo8&x)%TpMe<gA*e?xrBoKRgRk32F%=e#DnPN1iVA;QDy`!utj=A)#x%bW>n;MWB+m z@N%MJAU-^Pu%pBZKXwmB_T8fRk*lWi(r?hh(8hMp-&VFXXO8_lj}WC+(}MZRH@RM` zt4~WqDuSn7UXHKs%#;#=e;&hw5AdnPc_YGnDVq)>|3HJSe*e0ty<o|eREo!jYMl8L z69pY77M&ARIq=&^pk+R^`4$s3Dx=BA9h{VV{&CN-0-5S8ID$|*Gb@x=L}~stt+1wL zFhb9$)baD~1*WyEG}eRPjZ=w$!iV1RkLV|}IH&i`WS?j694{r$XO3a$&81+S(pI?} zDycVA>iP_Ni3;MR0uc%i3=3Mto7-5|Q~bQhyBNp<-z6?#b>^s;<HrW0#-ijQ3Xjd6 z;wa2fn$H4b#U||Q`2JFP4wryFcDT!S*+bHss<YMj`|1h%b5CZ48wcfJli7HF){|<T zH%b$p>Tmg-hL$emJB;vFMwZ~SBTENctssOv4Kb5NPPp;a#2dL9let^lvsrb;dDWdJ zA@2uv95K#gHeH3%-P2ZN+Dx9GPUOT4+e567$2!HRuc?-{xjFmin4p$*Ub%YSLuVZp z%`v{qn-`iZ93%d2Jeo9J3a^cjkd>c}FpX<of3=YD+cy~X)?Cz9xb*UB)JNsE#BQ)z zK{Pcr*)UmL*>r;Ep5QFx3`>*HEnIItH{-?6IIN+6XlXBO%QTxD>fn8;vT3}4`#5`d z0mC<h+@CSL71PYoQs<?nNHW?fJe@=?h=0ze?H|3P?)YR_p^%4Nr?rX-z&L9w4`B`B zY^0dMF(iH<pV2ZT4?+dtHwW@2OP++_hoS<&s=IbXxxrfWok*<6md9?2Kd8R;wIxWV zN^x08=FyRb=@x}&sJx>tC^ay}K$6(&kc=b4B_&DL8nb^*k#q>2jghpFWOuP3DJS<j zS0pJXJ#5M(n{i{7yHO>vB3e#yK|O{)uo}k<sf!t#@63<{!dD<=NUSKn;#A1y(dCWV z7PL4xn0-5Bvnn^VaQIfcG=tyTQt03yk;z$Z(xRcoTq>$Fv)=A1liJkOO1ZE;ySBKz zt`=YYgITM%2{N_F;yjg_{_H!o)<$!&TtE6^!<}P8C1AD9Q^sL3XCtwpVxfVcS}`r0 ziL0}tyzuLAJVru1TEKt|C8^7O=(yoG1qX}Og@cUJzVrJKu+Q!*>@N5B^>;*7wK6(i z>l!5CIUeer?n1_O%MC?Jc1rH=Clc9VEdeLT7UFy79f)|p6IR{1-L-kN<2T&GlvyN6 z2Uj{8@U3=24>~#;HqI+b4)jjpBo?NY=ht~u)|RK2XNb=&&(XD4-FP@$47LkO`$L>W zzW{?j9G#plx+q-g#{29VAL{O$9i6Q(+!LrNzlV9^k9&^fH8$J<YsPA`Y|nOWX#sCx zB}{R4dV10o3A_+WyXqWj(bCB7!l#~x2mzRl6h-H09B^xKnPS4YZ@8_icQP;=FCS0k zZgjjiu)rVZ8>f?GBGWdLVaSI@5e{c_L0_=EIF78}mSoVa@xc2GRis?o=st>gs@Z-1 z-NHi6t<T`XeAPFhYL{+({VVki;NradXT!Y{T0ulxduu6DsdLzPc{!(Dp1RBEeK~Aq z^qA*xH(TSaqmibij00gqO?_igZY6`Wl-<=tI!{;%Y8gOi0?lBw|J&CE7pMQHnJW)# z;@aX>T%%TH^%appSww|oW-{4|AV~lL0SSvsUbG<$5Wobp2rh-XpcSf!0#>os1rgCc z<rT1k7PTlMS``s$P~$><fP#XkfC%s2Aeunm_x|mCGr4!p{hf2}a?ZIof1EktbRlip zk<6cjSu@_1n%1s3+7n`5u&PP1GGu&HQ0hh#lQH<EoT%St?agc)UirsAo;`DFZn-C@ zx&QN-gpd}6z>iZIv99~&nazdiq0=AV{;n%xLD3GG@r*^grls6jzc76PuTiyb_fBJM zoOSvf_Y<-?+6}KgYWCd!*7~sadf|OpwMWYQQBGamwLWN(J(|K<y4F57E9|{_te9O} zzv)O*OG>y?vg*+OkZ75G{mQA=$1LHmDG0TETqqcyZu<C@wx~^;dGhG72f^Ns+mDY( zN}1nyNZnVO^<{xmdUZ)!)=bHLpNb^2izNjQ>H_)vvy7`{%jQTAp9$6ESHIzuFZM0C zSeVOAb=3$hE=B(`KkfLbid84H+|_%^V-K#FjU6n$x2<XWh>(-~l(#o07gn#SJo7s2 zhDH0s$JGT{+hwC$lp~X8cP(2Qn%woE{A}=E;%1;~M)1K){!_PB%SZb$gVq#RYf>`Q zcF{8K8I!VNYc%jQ`@(K#O~v-|nVB5iq(gR8d#+IH{G6BbB<PGwfjqtX*dBrC&yLVJ zEr)+`8l&Cdw#cFOZfH)5rY^VKN8?>bdWBsUN=v6N+4|y#;8`V(+7gArF|Fd*p{sst zxdM-+%*{<QPO7cdI7fNLp2Az{vyMfSykUyBITgy)u~xyHy^ivF<Fl=Y@%h!q2{eeT zK`D;5M6h#)nKtV{(~&&KtmTCsnH!q^ee7lUI4ik)X}w5Q_|q|Veog49V%s%>$g|1O zImZP((xdIUg2K$=&`vYD{Agj5Z->Uut0u*5Rz=9&=F27Zj&3!tb9|KAkr^?$9WDMf zse$Kec2B7aEpg@KjktWpE=p+rq%q^i>9e*p9nZBZh)6M(IQK5E3%YD}*mS{i>$%4Y zVlSc20VjI@Rg+)8zc_K%zQw7WDE1wTf=xX&_A?#)qurMfyNaI9c`mQbS&~=%$JQ=a z&i-XSRns|Jt}p(TvUah5OVpjZs~1pFgYw#>WrbrkW9E&Hwclg=S>V5o_g>*F=9_=B zNj|nJ|K+(UudbGkG2f9`F8t<Y^7lWcy<DB=V$><xdSlkQH&1?hbT}*n@kD=3HR<AB zyHWnd$%o9FUh6}r2d}37w$AF;-L?;k#+<wm?>D{7^i`*Q;7!NAP05LF6Zfg6ZuWYV z892#HT(^5tuW`4VRcA)mvnw6vpUk+CMmz2*?QUob_+w|l`R=iem0mqwkJ1iVUvmAT zXMVQ${iFpAROGCi3-jfJ4e_<-N*}hU8?5%-{nGBmCT&xaL+|#dR$tYfyUsD{*})3N zOf8$OIdkbQbS&pZlI$V-X~hlm(I;+<+D{IzSY)MD@7p$Q*t7KWlkI!H>Tr*EXmiTd zG$F6k=FR$dsl(q=+eWv}Wf8P>aSh1f5yhYHP1Zz;&E`0a+p&3e+Ru{p6&CETM*3H! zXosy!X<L#Uz;u1r=3X}XmQknaZwje%y=vl=7wr#1;_8axTS|RRO3(B?U7vlocdpUe z?<?Y6$~HDl2$-mfHycrsb!|)nw^dy-snkF9{>(>(N3z?G-to-NnP)OxRD96(l(@2E zUc{AR|BWV3C*8U_>JOh)X7$%wBY%ukcN5~IuL#%Q9;MS}Bu~g)`Yiu^{^OA6l?CEs zKe>(;3eAPJW#5UGemQsH>2TTk65CTb36-;b9|+qkjaS?@P8g9CV}0`LU$Zi!k6P6E z6!q@YJm<XNL|!TI|LhsZHC$Bj8OGt)nh7gTe0N6^exD4vxMovR{Dx8f7ta@LE*d%V zwS!s`)BL3SCAsn!Vt-j^S5~O}+Zg$_U203`7?)8msp)g$@44r%d)-!Dw5=_VDzKJc z+LUA4jb3=So$VcxbNckjZxRn2`0RFlTefK|b>73v%glTPf94#pSQF^=y4q*q0VHqr z`4_{Fj34GR_q@h(?bh}qrsjE>8JcrjpGJ|dQ|<3r_D#&5vU%lSr5eKgL6~ZY(s3O7 zlxfKLlxY~eI*z1z%4I4(sgx+BaVj}TGz72y;uR#7>khBk3#4JBLadU?WkIAu8bN`X zh>=Q!0V)8=<;oL;P6QoCoNyYBpcs>duvwUh>a7yTN+s^H$XF7gQK;@p2`N({EH+A^ zLS^v92}6Mto;YqkDUFO$0Y1<eq#{>@A}qiH#e?KW5<_s994VlHOvjIDl*~_q_>eA1 zpu}I~O6q4viZZHX^|VPIZ@VeZw>^+H8^>Yehi$hqT9z}Rxx*-Y>#C78JLgr6>-#$4 zKbX_a<ZV@tTz=m%_0R10tK2^K?VXm}`p`lR(g!-9smA@V$SY~u<pq{^Cf?r}+O8F8 z*j19}j}k>aq}%@7JF}{iE}wg5+}bR@AK=yJRF$;p!4|R0@h!`<dH=MQz3Qo0-t$Y| z^q4R1ybHSas`htned-On=9Sut7V#Ok%R7=jw|;wf_KX<63|aGgwd_l4P22OILjvj1 zMfJoU>vw%`@>6Uog5H)+xE116cPK8zq-e588a2D5_~v$v`|ggr?u!a78~46(Xmq%h z`%R+x3cDM7-z;jh(8M%Oc$INe_;m9AMbQN>@&bJ=I=r0xdW~1pyJE_l%O{TV>-AY@ z+-JVG$E>@$AwJ9@X>5dFub|yFvCXE;DBC{C(WT+^&RspBVU^1_Xm@B+?8`i+?fN~* z$gh_YNgBH)jPHu+2s7@(>0Q3}QUObvP13o|fUU^btyN>2NV9CW6eDH3N*b0Qw#e>G zzrC|;)JD59qo2WZ)UJ$Imeuol(VVUy%5z_NiLyJFAGrPQ!k&6nZ)4R??ff}iR%=c- z#9thn7!=j!{bDp*WV32x{Nw6(?jo<=1iLBw=r&Vqu65Q$<+qx1r}}nHy5bUMyyaHk z`_OB*znj_h^>C}Gk*$B_B&<({^wArrLFzCSbd6wzn$%IbVkHUf@qasoRH0PyqQnYl z><h#n>I`7ti=^SID5a3eWFiE?K<L0#a26ZE;5&_m;5e=;F@k1L4zxi$s8irOyT7i( z!FQcZP_lqLC>uUd9s>n!81@mz0R4b?_zdWUav^5m9o7eEunuLwJ^@}>QuJ}Uc0h-v zfj$Np8_*9Q*v7^_j*o)UJ}8HcqJHoG6m<|BMkN7-8Y~ZyNnw&Rf<qTKbb9uuwem#4 zEDi?HX?g&#S_lp~fYikSVbP>S1#+vsSD+{YZa{{03`DGfIuk*4Dj}VPfV&@q(GhTe zs1sl=KGbp0g8?~oq(4FdRszuhK-{4&RLCVkq)JF#$oHfMlL;!&ERH03{e^db!4>Jp zH7F2<Y|vAk-7N%o>O!#shD$JSuonVSDOW2bq!Q5$S3vb6!=+*vhT-T5HsK5cF&k&n zXiOH9j<D#cGq4XP17|YX1jZ6ky%chF98eGh%v&r|#zE<l)l^;(2+XUb5>nvBrFtVO zVEV4ER34Z{pj?UQrb#aX5B8hCPfvAguGdpkFSY(}HmT@<tqkmI*x%Ry23r93_cZ}* zunp*ZXRu=_DMOrz^2wWkGwIw3dJqg)zS3}|5Yc%&qKgfP&aecCZp}c^PXtJwTn*fn z&@(|G!O*XHVsJc?M*`Q51diPA*%WF(94T{`z@wJ1Uk`QhlBI}D9UI&KLj%GWh-Hy8 zBNR@a0!RJ8L5HjJVSqgF#R+hdbMf@>^rX=U7zr>Mjll*b9h6`fU}F8@DO@cf2XJ&= zKZXIYIy}J90Y8KB;Q{;%96W#yAT%7%F%MAEfh?U$&~HBYNX1M(2Y%cFrC}@-#aK8x zn}#~jXbz5g6Oy1HBPcY4j#Gf74;R892=L8|2n5nlCV|mWu#E6RWICFz{uea3MH%3L zRyGYR2fXxn8LXi=77MtbJ`P7&V3-Cp*cSq9u|sf!<pEv>V<-;Hydf_EzWf0fOkXdg z!97Qh2K6$DLGnN#r$LL;!_k-wI+!p+8k-3=T0?m{++Z5SK||J)hoTG`&NS>F><b(2 zcY|?k!#M@KC@>O398RaB48#8EaD&EyLL4}j80a9tFrYi@>tzx+3jS;u&>)T&LZgET z9E_u5gZs?H83a0L96-kqUWkL6u3=wj>_KY;=86XX0}aNZD09d-P_T4^aTv-T!i!<> z++nB}r_+YuaCpS~h*K#*ehaC9r->lx8WOl0RUntE5M4L|$0Bc8gdEXD4*0@Hgoq1D z$M|$EN&wI2Gd#inI-JSiVr(wUolkJt48oQ2{~<71^5qg<6e)>Os#hRXIuD#IF&>UH s7(5;y#V|gL$EUjkDih`LdG0WfDOF;HN*5Nu^x+I9L9w&*2=Ju*7ss#jRsaA1 diff --git a/MSP430-FORTH/BOOT.f b/MSP430-FORTH/BOOT.f index c981bd8..f1a04ca 100644 --- a/MSP430-FORTH/BOOT.f +++ b/MSP430-FORTH/BOOT.f @@ -3,96 +3,107 @@ ; BOOT.f ; -------- \ -\ to see kernel options, download FastForthSpecs.f -\ FastForth kernel options: MSP430ASSEMBLER, CONDCOMP, SD_CARD_LOADER, BOOTLOADER -\ -\ TARGET SELECTION +\ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) \ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 -\ MSP_EXP430FR4133 MSP_EXP430FR2433 MSP_EXP430FR2355 CHIPSTICK_FR2433 +\ MSP_EXP430FR4133 CHIPSTICK_FR2433 MSP_EXP430FR2433 MSP_EXP430FR2355 +\ LP_MSP430FR2476 +\ +\ from scite editor : copy your target selection in (shift+F8) parameter 1: +\ +\ or, from windows explorer: +\ drag and drop this file onto SendSourceFileToTarget.bat +\ then select your TARGET when asked. \ \ SYSRSTIV decimal/hex values for MSP430FR5994 (device specific) -\ ---------------------------------------------------------- -\ #00 $00 No interrupt pending -\ #02 $02 Brownout (BOR) -\ #04 $04 RSTIFG RST/NMI (BOR) -\ #06 $06 PMMSWBOR software BOR (BOR) -\ #08 $08 LPMx.5 wake up (BOR) -\ #10 $0A violation memory protected areas (BOR) -\ #12 $0C Reserved -\ #14 $0E SVSHIFG SVSH event (BOR) -\ #16 $10 Reserved -\ #18 $12 Reserved -\ #20 $14 PMMSWPOR software POR (POR) -\ #22 $16 WDTIFG watchdog timeout (PUC) -\ #24 $18 WDTPW password violation (PUC) -\ #26 $1A FRCTLPW password violation (PUC) -\ #28 $1C Uncorrectable FRAM bit error detection (PUC) -\ #30 $1E Peripheral area fetch (PUC) -\ #32 $20 PMMPW PMM password violation (PUC) -\ #34 $22 MPUPW MPU password violation (PUC) -\ #36 $24 CSPW CS password violation (PUC) +\ ---------------------------------------------------------- +\ #00 $00 No interrupt pending +\ #02 $02 Brownout (BOR) +\ #04 $04 RSTIFG RST/NMI (BOR) +\ #06 $06 PMMSWBOR software BOR (BOR) +\ #08 $08 LPMx.5 wake up (BOR) +\ #10 $0A violation memory protected areas (BOR) +\ #12 $0C Reserved +\ #14 $0E SVSHIFG SVSH event (BOR) +\ #16 $10 Reserved +\ #18 $12 Reserved +\ #20 $14 PMMSWPOR software POR (POR) +\ #22 $16 WDTIFG watchdog timeout (PUC) +\ #24 $18 WDTPW password violation (PUC) +\ #26 $1A FRCTLPW password violation (PUC) +\ #28 $1C Uncorrectable FRAM bit error detection (PUC) +\ #30 $1E Peripheral area fetch (PUC) +\ #32 $20 PMMPW PMM password violation (PUC) +\ #34 $22 MPUPW MPU password violation (PUC) +\ #36 $24 CSPW CS password violation (PUC) \ #38 $26 MPUSEGIPIFG encapsulated IP memory segment violation (PUC) -\ #40 $28 MPUSEGIIFG information memory segment violation (PUC) -\ #42 $2A MPUSEG1IFG segment 1 memory violation (PUC) -\ #44 $2C MPUSEG2IFG segment 2 memory violation (PUC) -\ #46 $2E MPUSEG3IFG segment 3 memory violation (PUC) +\ #40 $28 MPUSEGIIFG information memory segment violation (PUC) +\ #42 $2A MPUSEG1IFG segment 1 memory violation (PUC) +\ #44 $2C MPUSEG2IFG segment 2 memory violation (PUC) +\ #46 $2E MPUSEG3IFG segment 3 memory violation (PUC) \ -\ SYSRSTIV values added by FastForth -\ ---------------------------------- -\ -3 reset after FastForth "flashing". -\ -1 Deep Reset: restores FastForth as it was "flashed". +\ emulated SYSRSTIV values added by FastForth SYS +\ ----------------------------------------------- +\ n SYS ( n<0) : user WIPE = Deep Reset: restores FastForth as it was "flashed" +\ -3 : reset after FastForth "flashing". +\ SYS : WARM +\ n SYS (n even ) : user COLD (don't reuse hardware SYSRSTIV!) +\ n SYS (n odd ) : user WARM. \ \ note -\ -------------------------------------------------------------------------------- -\ any reset event is kept in SYSRSTIV register. Their values are device specific. -\ WARM displays the content of SYSRSTIV register. -\ -------------------------------------------------------------------------------- -\ When BOOT.4TH is called by the FastForth bootstrap, the SYSRSTIV value is on -\ the Top Of paramater Stack -TOS- ready to test. -\ -------------------------------------------------------------------------------- -\ to enable bootstrap: ' BOOT IS WARM -\ to disable bootstrap: ' BOOT [PFA] IS WARM -\ -------------------------------------------------------------------------------- +\ ------------------------------------------------------------------------------ +\ When BOOT.4TH is called by the FastForth bootstrap, the SYSRSTIV (hardware or +\ emulated value) is on the Top Of paramater Stack -TOS- ready to test. +\ ------------------------------------------------------------------------------ +\ to enable bootstrap: BOOT +\ to disable bootstrap: UNBOOT +\ ------------------------------------------------------------------------------ \ -\ first, we test for downloading driver only if good FastForth version - -CODE ABORT_BOOTSTRAP -SUB #2,PSP -MOV TOS,0(PSP) \ -MOV &VERSION,TOS \ -- sys_event version -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_BOOTSTRAP definition before resuming -; - -ABORT_BOOTSTRAP +\ it's an example: -[UNDEFINED] = [IF] + [UNDEFINED] = + [IF] \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + CODE = + SUB @PSP+,TOS \ 2 + SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ 1 TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] -\ -------------------------------------------------------------------------------- -\ WARNING ! -\ -------------------------------------------------------------------------------- -\ it is not recommended here to compile then execute a word -\ because the risk of crushing thereafter. -\ Interpreting mode as below is required: -\ -------------------------------------------------------------------------------- + [UNDEFINED] + + [IF] +\ https://forth-standard.org/standard/core/Plus +\ + n1/u1 n2/u2 -- n3/u3 add n1+n2 + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -\ it's an example: + [UNDEFINED] EXECUTE + [IF] +\ https://forth-standard.org/standard/core/EXECUTE +\ EXECUTE i*x xt -- j*x execute Forth word at 'xt' + CODE EXECUTE + PUSH TOS \ 3 push xt + MOV @PSP+,TOS \ 2 + MOV @RSP+,PC \ 4 xt --> PC + ENDCODE + [THEN] -$04 = [IF] \ if PUC event is <reset> - LOAD" SD_TEST.4TH" -[THEN] +\ ------------------------------------------------------------------------------ +\ WARNING ! +\ ------------------------------------------------------------------------------ +\ it is not recommended here to compile then execute a definition +\ because the risk of crushing thereafter. +\ Interpreting mode as below is required: +\ ------------------------------------------------------------------------------ + 4 = \ from SYS + [IF] \ if PUC event is <SW1+RESET> or -1 SYS + RST_RET \ remove definitions above + LOAD" SD_TEST.4TH" \ load a file to test the SD_Card driver + [ELSE] \ else + ' SYS $0A + EXECUTE \ resumes WARM to remove definitions above + [THEN] \ then diff --git a/MSP430-FORTH/CHNGBAUD.f b/MSP430-FORTH/CHNGBAUD.f index a27a2f3..0317a8e 100644 --- a/MSP430-FORTH/CHNGBAUD.f +++ b/MSP430-FORTH/CHNGBAUD.f @@ -14,21 +14,21 @@ \ \ COLD \ uncomment for this TEST which must not disrupt the downloading process -CODE I2CTERM_ABORT -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #$7800,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" <-- Ouch! unexpected I2C_FastForth target!" -PWR_STATE \ remove ABORT_UARTI2CS definition before resuming -; + CODE I2CTERM_ABORT + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #$3C00,TOS \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" <-- Ouch! unexpected I2C_FastForth target!" + RST_RET \ remove ABORT_UARTI2CS definition before resuming + ; I2CTERM_ABORT @@ -36,446 +36,484 @@ I2CTERM_ABORT ; CHNGBAUD.f ; ------------ -[UNDEFINED] DUP [IF] \ define DUP and DUP? \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP [IF] \ define DUP and DUP? + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DROP \ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] DROP [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] OVER [IF] \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] + [UNDEFINED] OVER [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR [IF] + DEFER CR \ DEFERed definition, by default executes that of :NONAME + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1+ [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] U/ [IF] \ U/ u1 u2 -- q unsigned 16/16->q16 -CODE U/ -SUB #2,PSP -MOV #0,0(PSP) \ -- u1lo u1hi u2 -CALL #MUSMOD \ -- r qlo qhi -MOV @PSP,TOS \ -- r qlo qlo -ADD #4,PSP \ -- qlo -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] + [UNDEFINED] U/ [IF] + CODE U/ + SUB #2,PSP + MOV #0,0(PSP) \ -- u1lo u1hi u2 + CALL #MUSMOD \ -- r qlo qhi + MOV @PSP,TOS \ -- r qlo qlo + ADD #4,PSP \ -- qlo + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] + [UNDEFINED] R> [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 flag Z = 1 -ELSE \ 2 - XOR #-1,TOS \ 1 -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] < [IF] \ define < and > + [UNDEFINED] = [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 flag Z = 1 + ELSE \ 2 + XOR #-1,TOS \ 1 + THEN + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/less \ < n1 n2 -- flag test n1<n2, signed -CODE < + [UNDEFINED] < [IF] \ define < and > + CODE < SUB @PSP+,TOS \ 1 TOS=n2-n1 S< ?GOTO FW1 \ 2 signed 0<> IF \ 2 -BW1 MOV #-1,TOS \ 1 flag Z = 0 +BW1 MOV #-1,TOS \ 1 flag Z = 0 THEN MOV @IP+,PC -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/more \ > n1 n2 -- flag test n1>n2, signed -CODE > + CODE > SUB @PSP+,TOS \ 2 TOS=n2-n1 S< ?GOTO BW1 \ 2 --> +5 FW1 AND #0,TOS \ 1 flag Z = 1 MOV @IP+,PC -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] IF [IF] \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF [IF] + CODE IF + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP + [UNDEFINED] ELSE [IF] + CODE ELSE + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W - MOV X,-4(W) \ xloop --> HERE - MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 \ goto BW1 LOOP + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] CASE [IF] \ https://forth-standard.org/standard/core/CASE -: CASE 0 ; IMMEDIATE \ -- #of-1 - -\ https://forth-standard.org/standard/core/OF -: OF \ #of-1 -- orgOF #of -1+ \ count OFs ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE OVER POSTPONE = \ copy and test case value -POSTPONE IF \ add orig to control flow stack -POSTPONE DROP \ discards case value if = -R> \ we can bring count back now -; IMMEDIATE + [UNDEFINED] CASE [IF] + : CASE 0 ; IMMEDIATE \ -- #of-1 + + \ https://forth-standard.org/standard/core/OF + : OF \ #of-1 -- orgOF #of + 1+ \ count OFs + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE OVER POSTPONE = \ copy and test case value + POSTPONE IF \ add orig to control flow stack + POSTPONE DROP \ discards case value if = + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDOF -: ENDOF \ orgOF #of -- orgENDOF #of ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE ELSE -R> \ we can bring count back now -; IMMEDIATE + : ENDOF \ orgOF #of -- orgENDOF #of + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE ELSE + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDCASE -: ENDCASE \ orgENDOF1..orgENDOFn #of -- -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] S_ [IF] -CODE S_ \ Squote alias with blank separator instead quote -MOV #0,&CAPS \ turn CAPS OFF -COLON -XSQUOTE , \ compile run-time code -$20 WORD \ -- c-addr (= HERE) -HI2LO -MOV.B @TOS,TOS \ -- len compile string -ADD #1,TOS \ -- len+1 -BIT #1,TOS \ C = ~Z -ADDC TOS,&DP \ store aligned DP -MOV @PSP+,TOS \ -- -MOV @RSP+,IP \ pop paired with push COLON -MOV #$20,&CAPS \ turn CAPS ON (default state) -MOV @IP+,PC \ NEXT -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&STATEADR -0= IF MOV @IP+,PC \ interpret time use is disallowed -THEN -COLON -$1B \ -- char escape -POSTPONE LITERAL \ compile-time code : lit $1B -POSTPONE EMIT \ compile-time code : EMIT -POSTPONE S_ \ compile-time code : S_ <escape_sequence> -POSTPONE TYPE \ compile-time code : TYPE -; IMMEDIATE -[THEN] - -: BAD_MHz -$20 DUP EMIT - ABORT" only for 1,4,8,16,24 MHz MCLK!" -; - -: OVR_BAUDS -$20 DUP EMIT ESC [7m \ set reverse video - ." with MCLK = " FREQ_KHZ @ 1000 U/ . - ABORT" MHz? don't dream!" -; - -: CHNGBAUD \ only for 1, 4, 8, 16, 24 MHz -PWR_STATE \ removes this created word (garbage collector) -ECHO -ESC [8;42;128t \ set 42L * 128C terminal display -41 0 DO CR LOOP \ to avoid erasing any line of source, create 42-1 empty lines -ESC [H \ cursor home - -FREQ_KHZ @ DUP >R \ r-- target MCLCK frequency in MHz -." target MCLK = " 1000 U/ . ." MHz" CR -." choose your baudrate:" CR -." 0 --> 6 MBds" CR \ >= 24 MHz -." 1 --> 5 MBds" CR \ >= 20 MHz -." 2 --> 4 MBds" CR \ >= 16 MHz -." 3 --> 3 MBds" CR \ >= 12 MHz -." 4 --> 1843200 Bds" CR \ >= 8 MHz -." 5 --> 921600 Bds" CR \ >= 4 MHz -." 6 --> 460800 Bds" CR \ >= 2 MHz -." 7 --> 230400 Bds" CR \ >= 1 MHz -." 8 --> 115200 Bds" CR \ >= 500 kHz -." 9 --> 38400 Bds" CR -." A --> 19200 Bds" CR -." B --> 9600 Bds" CR -." other --> abort" CR -." your choice: " -KEY - -CASE -#48 OF ." 6 MBds" \ add this to the current line - R> CASE - #24000 OF $4 $0 \ -- TERM_BRW TERM_MCTLW - ENDOF - 24000 < - IF OVR_BAUDS \ < 24 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#49 OF ." 5 MBds" - R> CASE - #24000 OF $4 $EE00 ENDOF - #20000 OF $4 $0 ENDOF - 20000 < - IF OVR_BAUDS \ < 20 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#50 OF ." 4 MBds" - R> CASE - #24000 OF $6 $0 ENDOF - #20000 OF $5 $0 ENDOF - #16000 OF $4 $0 ENDOF - 16000 < - IF OVR_BAUDS \ < 16 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#51 OF ." 3 MBds" - R> CASE - #24000 OF $8 $0 ENDOF - #20000 OF $6 $D600 ENDOF - #16000 OF $5 $4900 ENDOF - #12000 OF $4 $0 ENDOF - 12000 < - IF OVR_BAUDS \ < 12 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#52 OF ." 1843200 Bds" - R> CASE - #24000 OF $0D $0200 ENDOF - #20000 OF $0A $DF00 ENDOF - #16000 OF $8 $D600 ENDOF - #12000 OF $6 $AA00 ENDOF - #8000 OF $5 $9200 ENDOF - 8000 < - IF OVR_BAUDS \ < 8 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#53 OF ." 921600 Bds" - R> CASE - #24000 OF $1 $00A1 ENDOF - #20000 OF $1 $B751 ENDOF - #16000 OF $11 $4A00 ENDOF - #12000 OF $0D $0200 ENDOF - #8000 OF $8 $D600 ENDOF - #4000 OF $4 $4900 ENDOF - 4000 < - IF OVR_BAUDS \ < 4 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#54 OF ." 460800 Bds" - R> CASE - #24000 OF $3 $0241 ENDOF - #20000 OF $2 $92B1 ENDOF - #16000 OF $2 $BB21 ENDOF - #12000 OF $1 $00A1 ENDOF - #8000 OF $11 $4A00 ENDOF - #4000 OF $8 $D600 ENDOF - #2000 OF $4 $4900 ENDOF - 2000 < - IF OVR_BAUDS \ < 2 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#55 OF ." 230400 Bds" - R> CASE - #24000 OF $6 $2081 ENDOF - #20000 OF $5 $EE61 ENDOF - #16000 OF $4 $5551 ENDOF - #12000 OF $3 $0241 ENDOF - #8000 OF $2 $BB21 ENDOF - #4000 OF $11 $4A00 ENDOF - #2000 OF $8 $D600 ENDOF - #1000 OF $4 $4900 ENDOF - 1000 < - IF OVR_BAUDS \ < 1 MHz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#56 OF ." 115200 Bds" - R> CASE - #24000 OF $0D $4901 ENDOF - #20000 OF $0A $AD01 ENDOF - #16000 OF $8 $F7A1 ENDOF - #12000 OF $6 $2081 ENDOF - #8000 OF $4 $5551 ENDOF - #4000 OF $2 $BB21 ENDOF - #2000 OF $11 $4A00 ENDOF - #1000 OF $8 $D600 ENDOF - #500 OF $4 $4900 ENDOF - 500 < - IF OVR_BAUDS \ < 500 Khz --> abort - THEN BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#57 OF ." 38400 Bds" - R> CASE - #24000 OF $27 $0011 ENDOF - #16000 OF $1A $D601 ENDOF - #8000 OF $0D $4901 ENDOF - #4000 OF $6 $2081 ENDOF - #1000 OF $1 $00A1 ENDOF - BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#65 OF ." 19200 Bds" - R> CASE - #24000 OF $4E $0021 ENDOF - #16000 OF $34 $4911 ENDOF - #8000 OF $1A $D601 ENDOF - #4000 OF $0D $4901 ENDOF - #1000 OF $3 $0241 ENDOF - BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF -#66 OF ." 9600 Bds" - R> CASE - #24000 OF $9C $0041 ENDOF - #16000 OF $68 $D621 ENDOF - #8000 OF $34 $4911 ENDOF - #4000 OF $1A $D601 ENDOF - #1000 OF $6 $2081 ENDOF - BAD_MHz \ other MHz --> abort - ENDCASE - ENDOF - ." abort" ABORT" " \ ABORT" displays nothing -ENDCASE -TERMMCTLW_RST ! \ set UCAxMCTLW value in FRAM -TERMBRW_RST ! \ set UCAxBRW value in FRAM -CR ESC [7m \ escape sequence to set reverse video -." Change baudrate in Teraterm, save its setup, then reset target." -; - -CHNGBAUD + : ENDCASE \ orgENDOF1..orgENDOFn #of -- + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + [UNDEFINED] S_ [IF] + CODE S_ \ Squote alias with blank separator instead quote + MOV #0,&CAPS \ turn CAPS OFF + COLON + XSQUOTE , \ compile run-time code + $20 WORD \ -- c-addr (= HERE) + HI2LO + MOV.B @TOS,TOS \ -- len compile string + ADD #1,TOS \ -- len+1 + BIT #1,TOS \ C = ~Z + ADDC TOS,&DP \ store aligned DP + MOV @PSP+,TOS \ -- + MOV @RSP+,IP \ pop paired with push COLON + MOV #$20,&CAPS \ turn CAPS ON (default state) + MOV @IP+,PC \ NEXT + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC [IF] + CODE ESC + CMP #0,&STATEADR + 0= IF MOV @IP+,PC \ interpret time use is disallowed + THEN + COLON + $1B \ -- char escape + POSTPONE LITERAL \ compile-time code : lit $1B + POSTPONE EMIT \ compile-time code : EMIT + POSTPONE S_ \ compile-time code : S_ <escape_sequence> + POSTPONE TYPE \ compile-time code : TYPE + ; IMMEDIATE + [THEN] + + : BAD_MHz + $20 DUP EMIT + ABORT" only for 1,4,8,16,24 MHz MCLK!" + ; + + : OVR_BAUDS + $20 DUP EMIT ESC [7m \ set reverse video + ." with MCLK = " FREQ_KHZ @ 1000 U/ . + ABORT" MHz? don't dream!" + ; + + : CHNGBAUD \ only for 1, 4, 8, 16, 24 MHz + RST_RET \ removes this created word (garbage collector) + ECHO + ESC [8;42;80t \ set 42L * 80C terminal display + 41 0 DO CR LOOP \ to avoid erasing any line of source, create 42-1 empty lines + ESC [H \ cursor home + + FREQ_KHZ @ DUP >R \ r-- target MCLCK frequency in MHz + ." target MCLK = " 1000 U/ . ." MHz" CR + ." choose your baudrate:" CR + ." 0 --> 6 MBds" CR \ >= 24 MHz + ." 1 --> 5 MBds" CR \ >= 20 MHz + ." 2 --> 4 MBds" CR \ >= 16 MHz + ." 3 --> 3 MBds" CR \ >= 12 MHz + ." 4 --> 1843200 Bds" CR \ >= 8 MHz + ." 5 --> 921600 Bds" CR \ >= 4 MHz + ." 6 --> 460800 Bds" CR \ >= 2 MHz + ." 7 --> 230400 Bds" CR \ >= 1 MHz + ." 8 --> 115200 Bds" CR \ >= 500 kHz + ." 9 --> 38400 Bds" CR + ." A --> 19200 Bds" CR + ." B --> 9600 Bds" CR + ." other --> abort" CR + ." your choice: " + KEY + CASE + #48 OF ." 6 MBds" \ add this to the current line + R> CASE + #24000 OF $4 $0 \ -- TERM_BRW TERM_MCTLW + ENDOF + 24000 < + IF OVR_BAUDS \ < 24 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #49 OF ." 5 MBds" + R> CASE + #24000 OF $4 $EE00 ENDOF + #20000 OF $4 $0 ENDOF + 20000 < + IF OVR_BAUDS \ < 20 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #50 OF ." 4 MBds" + R> CASE + #24000 OF $6 $0 ENDOF + #20000 OF $5 $0 ENDOF + #16000 OF $4 $0 ENDOF + 16000 < + IF OVR_BAUDS \ < 16 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #51 OF ." 3 MBds" + R> CASE + #24000 OF $8 $0 ENDOF + #20000 OF $6 $D600 ENDOF + #16000 OF $5 $4900 ENDOF + #12000 OF $4 $0 ENDOF + 12000 < + IF OVR_BAUDS \ < 12 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #52 OF ." 1843200 Bds" + R> CASE + #24000 OF $0D $0200 ENDOF + #20000 OF $0A $DF00 ENDOF + #16000 OF $8 $D600 ENDOF + #12000 OF $6 $AA00 ENDOF + #8000 OF $5 $9200 ENDOF + 8000 < + IF OVR_BAUDS \ < 8 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #53 OF ." 921600 Bds" + R> CASE + #24000 OF $1 $00A1 ENDOF + #20000 OF $1 $B751 ENDOF + #16000 OF $11 $4A00 ENDOF + #12000 OF $0D $0200 ENDOF + #8000 OF $8 $D600 ENDOF + #4000 OF $4 $4900 ENDOF + 4000 < + IF OVR_BAUDS \ < 4 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #54 OF ." 460800 Bds" + R> CASE + #24000 OF $3 $0241 ENDOF + #20000 OF $2 $92B1 ENDOF + #16000 OF $2 $BB21 ENDOF + #12000 OF $1 $00A1 ENDOF + #8000 OF $11 $4A00 ENDOF + #4000 OF $8 $D600 ENDOF + #2000 OF $4 $4900 ENDOF + 2000 < + IF OVR_BAUDS \ < 2 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #55 OF ." 230400 Bds" + R> CASE + #24000 OF $6 $2081 ENDOF + #20000 OF $5 $EE61 ENDOF + #16000 OF $4 $5551 ENDOF + #12000 OF $3 $0241 ENDOF + #8000 OF $2 $BB21 ENDOF + #4000 OF $11 $4A00 ENDOF + #2000 OF $8 $D600 ENDOF + #1000 OF $4 $4900 ENDOF + 1000 < + IF OVR_BAUDS \ < 1 MHz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #56 OF ." 115200 Bds" + R> CASE + #24000 OF $0D $4901 ENDOF + #20000 OF $0A $AD01 ENDOF + #16000 OF $8 $F7A1 ENDOF + #12000 OF $6 $2081 ENDOF + #8000 OF $4 $5551 ENDOF + #4000 OF $2 $BB21 ENDOF + #2000 OF $11 $4A00 ENDOF + #1000 OF $8 $D600 ENDOF + #500 OF $4 $4900 ENDOF + 500 < + IF OVR_BAUDS \ < 500 Khz --> abort + THEN BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #57 OF ." 38400 Bds" + R> CASE + #24000 OF $27 $0011 ENDOF + #16000 OF $1A $D601 ENDOF + #8000 OF $0D $4901 ENDOF + #4000 OF $6 $2081 ENDOF + #1000 OF $1 $00A1 ENDOF + BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #65 OF ." 19200 Bds" + R> CASE + #24000 OF $4E $0021 ENDOF + #16000 OF $34 $4911 ENDOF + #8000 OF $1A $D601 ENDOF + #4000 OF $0D $4901 ENDOF + #1000 OF $3 $0241 ENDOF + BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + #66 OF ." 9600 Bds" + R> CASE + #24000 OF $9C $0041 ENDOF + #16000 OF $68 $D621 ENDOF + #8000 OF $34 $4911 ENDOF + #4000 OF $1A $D601 ENDOF + #1000 OF $6 $2081 ENDOF + BAD_MHz \ other MHz --> abort + ENDCASE + ENDOF + ." abort" ABORT" " \ ABORT" " displays nothing + ENDCASE + TERMMCTLW_RST ! \ set UCAxMCTLW value in FRAM + TERMBRW_RST ! \ set UCAxBRW value in FRAM + CR ESC [7m \ escape sequence to set reverse video + ." Change baudrate in Teraterm, save its setup, then reset target." + ; + + CHNGBAUD diff --git a/MSP430-FORTH/CORDIC.f b/MSP430-FORTH/CORDIC.f index a764d61..2b44c8b 100644 --- a/MSP430-FORTH/CORDIC.f +++ b/MSP430-FORTH/CORDIC.f @@ -34,33 +34,30 @@ \ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>= \ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0< -CODE ABORT_CORDIC -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #BIT10,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" build FastForth with FIXPOINT_INPUT addon !" -PWR_STATE \ if no abort remove this word -; - -ABORT_CORDIC + CODE ABORT_CORDIC + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #BIT8,TOS + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT_INPUT), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with FIXPOINT_INPUT addon" + RST_RET \ if no abort remove this word + ; + + ABORT_CORDIC ; ---------- ; CORDIC.f ; ---------- -[DEFINED] {CORDIC} [IF] {CORDIC} [THEN] - MARKER {CORDIC} - \ CORDIC USES \ OPERATION | MODE | INITIALIZE x y z | DIRECTION | RESULT | post operation \ --------------|-----------|-----------------------|---------------|-------------------| @@ -74,267 +71,314 @@ MARKER {CORDIC} \ --------------|-----------|-----------------------|---------------|-------------------| \ Gi = CORDIC gain for i iterations; Gi < 1 \ + CREATE T_ARCTAN \ ArcTan table + 12870 , \ 286 * 45 = + 7598 , \ 286 * 26.565 = 7597,605 + 4014 , \ 286 * 14.036 = 4014,366 + 2038 , \ 286 * 7.125 = 2037,755 + 1023 , \ 286 * 3.576 = 1022,832 + 512 , \ 286 * 1.790 = 511,914 + 256 , \ 286 * 0.895 = 256,020 + 128 , \ 286 * 0.448 = 128,017 + 64 , \ 286 * 0.224 = 64,010 + 32 , \ 286 * 0.112 = 32,005 + 16 , \ 286 * 0.056 = 16,0025 + 8 , \ 286 * 0.028 = 8,00126 + 4 , \ 286 * 0.014 = 4 + 2 , \ 286 * 0.007 = 2 + 1 , \ 286 * 0.003 = 1 + + CREATE T_SCALE \ 1/Gi table + 46340 , \ = 65536 * cos(45) + 41448 , \ = 65536 * cos(45) * cos(26.565) + 40211 , \ = 65536 * cos(45) * cos(26.565) * cos(14.036) + 39900 , \ = 65536 * cos(45) * cos(26.565) * cos(14.036) * ... + 39822 , + 39803 , + 39798 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , -CREATE T_ARCTAN \ ArcTan table -12870 , \ 286 * 45 = -7598 , \ 286 * 26.565 = 7597,605 -4014 , \ 286 * 14.036 = 4014,366 -2038 , \ 286 * 7.125 = 2037,755 -1023 , \ 286 * 3.576 = 1022,832 -512 , \ 286 * 1.790 = 511,914 -256 , \ 286 * 0.895 = 256,020 -128 , \ 286 * 0.448 = 128,017 -64 , \ 286 * 0.224 = 64,010 -32 , \ 286 * 0.112 = 32,005 -16 , \ 286 * 0.056 = 16,0025 -8 , \ 286 * 0.028 = 8,00126 -4 , \ 286 * 0.014 = 4 -2 , \ 286 * 0.007 = 2 -1 , \ 286 * 0.003 = 1 - -CREATE T_SCALE \ 1/Gi table -46340 , \ = 65536 * cos(45) -41448 , \ = 65536 * cos(45) * cos(26.565) -40211 , \ = 65536 * cos(45) * cos(26.565) * cos(14.036) -39900 , \ = 65536 * cos(45) * cos(26.565) * cos(14.036) * ... -39822 , -39803 , -39798 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -\ https://forth-standard.org/standard/core/Uless -\ U< u1 u2 -- flag test u1<u2, unsigned -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 - THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] \ https://forth-standard.org/standard/double/DABS \ DABS d1 -- |d1| absolute value -CODE DABS -AND #-1,TOS \ clear V, set N -S< IF \ - XOR #-1,0(PSP) \ 4 - XOR #-1,TOS \ 1 - ADD #1,0(PSP) \ 4 - ADDC #0,TOS \ 1 -THEN -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] DABS + [IF] + CODE DABS + AND #-1,TOS \ clear V, set N + S< IF \ + XOR #-1,0(PSP) \ 4 + XOR #-1,TOS \ 1 + ADD #1,0(PSP) \ 4 + ADDC #0,TOS \ 1 + THEN + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] HOLDS [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + RST_SET +\ \ https://forth-standard.org/standard/core/Equal +\ \ = x1 x2 -- flag test x1=x2 +\ [UNDEFINED] = +\ [IF] +\ CODE = +\ SUB @PSP+,TOS \ 2 +\ 0<> IF \ 2 +\ AND #0,TOS \ 1 +\ MOV @IP+,PC \ 4 +\ THEN +\ XOR #-1,TOS \ 1 flag Z = 1 +\ MOV @IP+,PC \ 4 +\ ENDCODE +\ [THEN] +\ +\ \ https://forth-standard.org/standard/core/Uless +\ \ U< u1 u2 -- flag test u1<u2, unsigned +\ [UNDEFINED] U< +\ [IF] +\ CODE U< +\ SUB @PSP+,TOS \ 2 u2-u1 +\ 0<> IF +\ MOV #-1,TOS \ 1 +\ U< IF \ 2 flag +\ AND #0,TOS \ 1 flag Z = 1 +\ THEN +\ THEN +\ MOV @IP+,PC \ 4 +\ ENDCODE +\ [THEN] +\ +\ $81EF DEVICEID @ U< +\ DEVICEID @ $81F3 U< +\ = + + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + + KERNEL_ADDON HMPY TSTBIT \ hardware MPY ? + + RST_RET + + [IF] ; MSP430FRxxxx with hardware_MPY + \ https://forth-standard.org/standard/core/HOLDS \ Adds the string represented by addr u to the pictured numeric output string \ compilation use: <# S" string" HOLDS #> \ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number. \ (2 supplementary bytes are room for sign - and decimal point) \ C HOLDS addr u -- -CODE HOLDS - MOV @PSP+,X \ 2 X=src -BW3 ADD TOS,X \ 1 X=src_end - MOV &HP,Y \ 3 Y=dst -BEGIN SUB #1,X \ 1 src-1 - SUB #1,TOS \ 1 cnt-1 -U>= WHILE SUB #1,Y \ 1 dst-1 - MOV.B @X,0(Y) \ 4 -REPEAT MOV Y,&HP \ 3 - MOV @PSP+,TOS \ 2 - MOV @IP+,PC \ 4 15 words -ENDCODE -[THEN] - -$81EF DEVICEID @ U< -DEVICEID @ $81F3 U< -= [IF] ; MSP430FR413x subfamily without hardware_MPY - -[UNDEFINED] F#S [IF] + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @PSP+,X \ 2 X=src +BW3 ADD TOS,X \ 1 X=src_end + MOV &HP,Y \ 3 Y=dst + BEGIN + SUB #1,X \ 1 src-1 + SUB #1,TOS \ 1 cnt-1 + U>= WHILE + SUB #1,Y \ 1 dst-1 + MOV.B @X,0(Y) \ 4 + REPEAT + MOV Y,&HP \ 3 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 15 words + ENDCODE + [THEN] + +\ F#S Qlo Qhi u -- Qhi 0 convert fractionnal part of Q15.16 fixed point number +\ with u digits + [UNDEFINED] F#S + [IF] + CODE F#S + MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo + MOV @PSP,2(PSP) \ -- Qhi Qhi u + MOV X,0(PSP) \ -- Qhi Qlo u + MOV TOS,T \ T = len + MOV #0,S \ S = count + BEGIN MOV @PSP,&MPY \ Load 1st operand + MOV &BASEADR,&OP2 \ Load 2nd operand + MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack + MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS + CMP #10,TOS \ digit to char + U>= IF ADD #7,TOS + THEN ADD #$30,TOS + MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string + ADD #1,S \ count+1 + CMP T,S \ count=len ? + 0= UNTIL MOV T,TOS \ -- len RESlo len + MOV #0,0(PSP) \ -- Qhi 0 len + MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG + GOTO BW3 \ 35~ JMP HOLDS+2 + ENDCODE + [THEN] + + HDNCODE XSCALE \ X = X*Cordic_Gain + MOV T_SCALE(W),&MPYS32L \ 3 CORDIC Gain * 65536 + MOV #0,&MPYS32H + MOV X,&OP2 \ 3 Load 1st operand + MOV &RES1,X \ 3 hi result + MOV @RSP+,PC \ RET + ENDCODE + + [ELSE] ; no hardware multiplier + +\ https://forth-standard.org/standard/core/HOLDS +\ Adds the string represented by addr u to the pictured numeric output string +\ compilation use: <# S" string" HOLDS #> +\ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number. +\ (2 supplementary bytes are room for sign - and decimal point) +\ C HOLDS addr u -- + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @PSP+,X \ 2 X=src +BW3 ADD TOS,X \ 1 X=src_end + MOV &HP,Y \ 3 Y=dst + BEGIN + SUB #1,X \ 1 src-1 + SUB #1,TOS \ 1 cnt-1 + U>= WHILE + SUB #1,Y \ 1 dst-1 + MOV.B @X,0(Y) \ 4 + REPEAT + MOV Y,&HP \ 3 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 15 words + ENDCODE + [THEN] + \ F#S Qlo Qhi len -- Qhi 0 convert fractional part Qlo of Q15.16 fixed point number \ with len digits -CODE F#S - MOV @PSP,S \ -- Qlo Qhi len S = Qhi - MOV #0,T \ T = count - PUSHM #3,IP \ R-- IP Qhi count - MOV 2(PSP),0(PSP) \ -- Qlo Qlo len - MOV TOS,2(PSP) \ -- len Qlo len -BEGIN MOV &BASEADR,TOS \ -- len Qlo base - LO2HI - UM* \ u1 u2 -- RESlo REShi - HI2LO \ -- len RESlo digit - CMP #10,TOS \ digit to char - U>= IF ADD #7,TOS - THEN ADD #$30,TOS \ -- len RESlo char - MOV @RSP,T \ T=count - MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T) - ADD #1,T \ count+1 - MOV T,0(RSP) \ - CMP 2(PSP),T \ -- len RESlo char count=len ? -U>= UNTIL POPM #3,IP \ S=Qhi, T=len - MOV T,TOS \ -- len RESlo len - MOV S,2(PSP) \ -- Qhi RESlo len - MOV #0,0(PSP) \ -- Qhi 0 len - MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG - GOTO BW3 \ 36~ JMP HOLDS -ENDCODE -[THEN] - -HDNCODE XSCALE \ X --> X*Cordic_Gain + [UNDEFINED] F#S + [IF] + CODE F#S + MOV @PSP,S \ -- Qlo Qhi len S = Qhi + MOV #0,T \ T = count + PUSHM #3,IP \ R-- IP Qhi count + MOV 2(PSP),0(PSP) \ -- Qlo Qlo len + MOV TOS,2(PSP) \ -- len Qlo len + BEGIN MOV &BASEADR,TOS \ -- len Qlo base + LO2HI + UM* \ u1 u2 -- RESlo REShi + HI2LO \ -- len RESlo digit + CMP #10,TOS \ digit to char + U>= IF ADD #7,TOS + THEN ADD #$30,TOS \ -- len RESlo char + MOV @RSP,T \ T=count + MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T) + ADD #1,T \ count+1 + MOV T,0(RSP) \ + CMP 2(PSP),T \ -- len RESlo char count=len ? + U>= UNTIL POPM #3,IP \ S=Qhi, T=len + MOV T,TOS \ -- len RESlo len + MOV S,2(PSP) \ -- Qhi RESlo len + MOV #0,0(PSP) \ -- Qhi 0 len + MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG + GOTO BW3 \ 36~ JMP HOLDS + ENDCODE + [THEN] + \ T.I. UNSIGNED MULTIPLY SUBROUTINE: U1 x U2 -> Ud \ https://forth-standard.org/standard/core/UMTimes \ UM* u1 u2 -- ud unsigned 16x16->32 mult. - MOV T_SCALE(W),rDOCON \ rDOCON=MR, X=MDlo -UMSTAR1 MOV #0,Y \ 1 MDhi=0 - MOV #0,S \ 1 RES0=0 - MOV #0,T \ 1 RES1=0 - MOV #1,W \ 1 BIT TEST REGISTER -BEGIN BIT W,rDOCON \ 1 TEST ACTUAL BIT MRlo - 0<> IF ADD X,S \ 1 IF 1: ADD MDlo TO RES0 - ADDC Y,T \ 1 ADDC MDhi TO RES1 - THEN ADD X,X \ 1 (RLA LSBs) MDlo x 2 - ADDC Y,Y \ 1 (RLC MSBs) MDhi x 2 - ADD W,W \ 1 (RLA) NEXT BIT TO TEST -U>= UNTIL \ S = RESlo, T=REShi - MOV T,X \ 2 IF BIT IN CARRY: FINISHED 10~ loop - MOV #XDOCON,rDOCON \ restore rDOCON - MOV @RSP+,PC \ RET -ENDCODE - -[ELSE] ; hardware multiplier - -[UNDEFINED] F#S [IF] -\ F#S Qlo Qhi u -- Qhi 0 convert fractionnal part of Q15.16 fixed point number -\ with u digits -CODE F#S - MOV 2(PSP),X \ -- Qlo Qhi u X = Qlo - MOV @PSP,2(PSP) \ -- Qhi Qhi u - MOV X,0(PSP) \ -- Qhi Qlo u - MOV TOS,T \ T = len - MOV #0,S \ S = count -BEGIN MOV @PSP,&MPY \ Load 1st operand - MOV &BASEADR,&OP2 \ Load 2nd operand - MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack - MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS - CMP #10,TOS \ digit to char - U>= IF ADD #7,TOS - THEN ADD #$30,TOS - MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string - ADD #1,S \ count+1 - CMP T,S \ count=len ? -0= UNTIL MOV T,TOS \ -- len RESlo len - MOV #0,0(PSP) \ -- Qhi 0 len - MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG - GOTO BW3 \ 35~ JMP HOLDS+2 -ENDCODE -[THEN] - -HDNCODE XSCALE \ X = X*Cordic_Gain -MOV T_SCALE(W),&MPYS32L \ 3 CORDIC Gain * 65536 -MOV #0,&MPYS32H -MOV X,&OP2 \ 3 Load 1st operand -MOV &RES1,X \ 3 hi result -MOV @RSP+,PC \ RET -ENDCODE - -[THEN] ; end of hardware multiplier - -CODE POL2REC \ u F -- X Y + HDNCODE XSCALE \ X --> X*Cordic_Gain + MOV T_SCALE(W),rDOCON \ rDOCON=MR, X=MDlo + UMSTAR1 MOV #0,Y \ 1 MDhi=0 + MOV #0,S \ 1 RES0=0 + MOV #0,T \ 1 RES1=0 + MOV #1,W \ 1 BIT TEST REGISTER + BEGIN BIT W,rDOCON \ 1 TEST ACTUAL BIT MRlo + 0<> IF ADD X,S \ 1 IF 1: ADD MDlo TO RES0 + ADDC Y,T \ 1 ADDC MDhi TO RES1 + THEN ADD X,X \ 1 (RLA LSBs) MDlo x 2 + ADDC Y,Y \ 1 (RLC MSBs) MDhi x 2 + ADD W,W \ 1 (RLA) NEXT BIT TO TEST + U>= UNTIL \ S = RESlo, T=REShi + MOV T,X \ 2 IF BIT IN CARRY: FINISHED 10~ loop + MOV #XDOCON,rDOCON \ restore rDOCON + MOV @RSP+,PC \ RET + ENDCODE + + [THEN] ; endcase of hardware multiplier + \ input ; u = module {1000...16384}, F = angle (15Q16 number) in degrees {-89,9...89,9} -\ output ; X Y +\ output ; X Y \ TOS = Fhi, 0(PSP) = Flo, 2(PSP) = u -PUSH IP \ save IP before use -MOV @PSP+,&MPY32L \ multiply angle by 286 -MOV TOS,&MPY32H -MOV #286,&OP2 -MOV &RES0,Y -MOV &RES1,TOS \ -- module angle*286 + CODE POL2REC \ u F -- X Y + PUSH IP \ save IP before use + MOV @PSP+,&MPY32L \ multiply angle by 286 + MOV TOS,&MPY32H + MOV #286,&OP2 + MOV &RES0,Y + MOV &RES1,TOS \ -- module angle*286 \ ===================== \ CORDIC 16 bits engine \ ===================== -MOV #-1,IP \ IP = i-1 -MOV @PSP,X \ X = Xi -MOV #0,Y \ Y = Yi -BEGIN \ i loops with init i = -1 - ADD #1,IP \ i = i+1 - MOV X,S \ S = Xi to be right shifted - MOV Y,T \ T = Yi to be right shifted - MOV #0,W \ - GOTO FW1 - BEGIN - RRA S \ (Xi >> 1) - RRA T \ (Yi >> 1) - ADD #1,W -FW1 CMP IP,W \ W = i ? - 0= UNTIL \ loop back if W < i - ADD W,W \ W = 2i = T_SCALE displacement - CMP #0,TOS \ TOS = z - 0>= IF \ TOS >= 0 : Rotate clockwise - SUB T,X \ Xi+1 = Xi - ( Yi >> i) - ADD S,Y \ Yi+1 = Yi + ( Xi >> i) - SUB T_ARCTAN(W),TOS - ELSE \ TOS < 0 : Rotate counter-clockwise - ADD T,X \ Xi+1 = Xi + ( Yi >> i) - SUB S,Y \ Yi+1 = Yi - ( Xi >> i) - ADD T_ARCTAN(W),TOS - THEN - CMP #0,TOS \ if angle*256 = 0 quit loop - 0<> WHILE \ search "Extended control-flow patterns" in https://forth-standard.org/standard/rationale - CMP #14,IP \ IP = size of ARC_TAN table ? -0= UNTIL - THEN \ search "Extended control-flow patterns" in https://forth-standard.org/standard/rationale + MOV #-1,IP \ IP = i-1 + MOV @PSP,X \ X = Xi + MOV #0,Y \ Y = Yi + BEGIN \ i loops with init i = -1 + ADD #1,IP \ i = i+1 + MOV X,S \ S = Xi to be right shifted + MOV Y,T \ T = Yi to be right shifted + MOV #0,W \ + GOTO FW1 + BEGIN + RRA S \ (Xi >> 1) + RRA T \ (Yi >> 1) + ADD #1,W +FW1 CMP IP,W \ W = i ? + 0= UNTIL \ loop back if W < i + ADD W,W \ W = 2i = T_SCALE displacement + CMP #0,TOS \ TOS = z + 0>= IF \ TOS >= 0 : Rotate clockwise + SUB T,X \ Xi+1 = Xi - ( Yi >> i) + ADD S,Y \ Yi+1 = Yi + ( Xi >> i) + SUB T_ARCTAN(W),TOS + ELSE \ TOS < 0 : Rotate counter-clockwise + ADD T,X \ Xi+1 = Xi + ( Yi >> i) + SUB S,Y \ Yi+1 = Yi - ( Xi >> i) + ADD T_ARCTAN(W),TOS + THEN + CMP #0,TOS \ if angle*256 = 0 quit loop + 0<> WHILE \ search "Extended control-flow patterns" in https://forth-standard.org/standard/rationale + CMP #14,IP \ IP = size of ARC_TAN table ? + 0= UNTIL + THEN \ search "Extended control-flow patterns" in https://forth-standard.org/standard/rationale \ multiply cos by factor scale -CALL #XSCALE -MOV X,0(PSP) \ 3 hi result = cos + CALL #XSCALE + MOV X,0(PSP) \ 3 hi result = cos \ multiply sin by factor scale -MOV Y,X \ 3 -CALL #XSCALE -MOV X,TOS \ 3 hi result = sin + MOV Y,X \ 3 + CALL #XSCALE + MOV X,TOS \ 3 hi result = sin \ ================== \ endof CORDIC engine \ X = cos, Y = sin \ ================== -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE \ -- cos sin + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE \ -- cos sin \ REC2POL version with inputs scaling, to increase the accuracy of the angle: @@ -342,282 +386,279 @@ ENDCODE \ -- cos sin \ input : X < 16384, Y < 16384 \ output ; u = hypothenuse, f = angle (15Q16 number) in degrees \ rounded hypothenuse, 1 mn accuracy angle -CODE REC2POL \ X Y -- u f -MOV @PSP,X \ X = Xi -MOV TOS,Y \ Y = Yi + CODE REC2POL \ X Y -- u f + MOV @PSP,X \ X = Xi + MOV TOS,Y \ Y = Yi \ normalize X Y to 16384 maxi \ 1- calculate T = |Y| -MOV Y,T -CMP #0,T -S< IF - XOR #-1,T - ADD #1,T -THEN + MOV Y,T + CMP #0,T + S< IF + XOR #-1,T + ADD #1,T + THEN \ 2- calculate S = |X| -MOV X,S -CMP #0,S -S< IF - XOR #-1,S - ADD #1,S -THEN + MOV X,S + CMP #0,S + S< IF + XOR #-1,S + ADD #1,S + THEN \ 3- abort if null inputs -MOV #-1,TOS \ set TOS TRUE for the two ABORT" below -CMP #0,X -0= IF - CMP #0,Y + MOV #-1,TOS \ set TOS TRUE for the two ABORT" below + CMP #0,X 0= IF - LO2HI - ABORT" null inputs!" - HI2LO + CMP #0,Y + 0= IF + LO2HI + ABORT" null inputs!" + HI2LO + THEN THEN -THEN \ 4- select max of |X|,|Y| -CMP S,T -U< IF \ |X| > |Y| - MOV S,T -THEN -\ 5- abort if |X| or |Y| >= 16384 -CMP #16384,T - U>= IF - LO2HI - ABORT" |x| or |y| >= 16384" - HI2LO + CMP S,T + U< IF \ |X| > |Y| + MOV S,T THEN +\ 5- abort if |X| or |Y| >= 16384 + CMP #16384,T + U>= IF + LO2HI + ABORT" |x| or |y| >= 16384" + HI2LO + THEN \ 6- multiply inputs by 2^n scale factor -MOV #1,S \ init scale factor -RLAM #3,T \ test bit 2^13 of max(X,Y) -GOTO FW1 -BEGIN - ADD X,X \ X=X*2 - ADD Y,Y \ Y=Y*2 - ADD S,S \ scale factor *2 - ADD T,T \ to test next bit 2^(n-1) + MOV #1,S \ init scale factor + RLAM #3,T \ test bit 2^13 of max(X,Y) + GOTO FW1 + BEGIN + ADD X,X \ X=X*2 + ADD Y,Y \ Y=Y*2 + ADD S,S \ scale factor *2 + ADD T,T \ to test next bit 2^(n-1) FW1 -U>= UNTIL \ until carry set + U>= UNTIL \ until carry set \ 7- save IP and scale factor n -PUSHM #2,IP \ push IP,S + PUSHM #2,IP \ push IP,S \ ================== -\ CORDIC engine +\ CORDIC 16 bits engine \ ================== -MOV #-1,IP \ IP = i-1, X = Xi, Y = Yi -MOV #0,TOS \ init z=0 - BEGIN \ i loops with init: i = -1 - ADD #1,IP \ i = i+1 - MOV X,S \ S = Xi to be right shifted - MOV Y,T \ T = Yi to be right shifted - MOV #0,W \ W = right shift loop count - GOTO FW1 - BEGIN - RRA S \ (X >> i) - RRA T \ (Y >> i) - ADD #1,W \ -FW1 CMP IP,W \ W = i ? - 0= UNTIL \ 6~ loop - ADD W,W \ W = 2i = T_SCALE displacement - CMP #0,Y \ Y sign ? - S>= IF \ Y >= 0 : Rotate counter-clockwise - ADD T,X \ Xi+1 = Xi + ( Yi >> i) - SUB S,Y \ Yi+1 = Yi - ( Xi >> i) - ADD T_ARCTAN(W),TOS - ELSE \ Y < 0 : Rotate clockwise - SUB T,X \ Xi+1 = Xi - ( Yi >> i) - ADD S,Y \ Yi+1 = Yi + ( Xi >> i) - SUB T_ARCTAN(W),TOS - THEN - CMP #0,Y \ - 0<> WHILE \ if Y = 0 quit loop ---+ - CMP #14,IP \ | - 0= UNTIL \ | - THEN \ <---------------------+ + MOV #-1,IP \ IP = i-1, X = Xi, Y = Yi + MOV #0,TOS \ init z=0 + BEGIN \ i loops with init: i = -1 + ADD #1,IP \ i = i+1 + MOV X,S \ S = Xi to be right shifted + MOV Y,T \ T = Yi to be right shifted + MOV #0,W \ W = right shift loop count + GOTO FW1 + BEGIN + RRA S \ (X >> i) + RRA T \ (Y >> i) + ADD #1,W \ +FW1 CMP IP,W \ W = i ? + 0= UNTIL \ 6~ loop + ADD W,W \ W = 2i = T_SCALE displacement + CMP #0,Y \ Y sign ? + S>= IF \ Y >= 0 : Rotate counter-clockwise + ADD T,X \ Xi+1 = Xi + ( Yi >> i) + SUB S,Y \ Yi+1 = Yi - ( Xi >> i) + ADD T_ARCTAN(W),TOS + ELSE \ Y < 0 : Rotate clockwise + SUB T,X \ Xi+1 = Xi - ( Yi >> i) + ADD S,Y \ Yi+1 = Yi + ( Xi >> i) + SUB T_ARCTAN(W),TOS + THEN + CMP #0,Y \ + 0<> WHILE \ if Y = 0 quit loop ---+ + CMP #14,IP \ | + 0= UNTIL \ | + THEN \ <---------------------+ \ multiply x by CORDIC gain -CALL #XSCALE \ 3 hi result = hypothenuse + CALL #XSCALE \ 3 hi result = hypothenuse \ ================== \ endof CORDIC engine \ X = hypothenuse, TOS = 256*angle \ ================== \ divide x by scale factor -POPM #2,IP \ S = scale factor, restore IP -GOTO FW1 -BEGIN \ 4~ loop - RRA X \ divide x by 2 -FW1 RRA S \ shift right scale factor -U>= UNTIL \ until carry set -MOV X,0(PSP) - + POPM #2,IP \ S = scale factor, restore IP + GOTO FW1 + BEGIN \ 4~ loop + RRA X \ divide x by 2 +FW1 RRA S \ shift right scale factor + U>= UNTIL \ until carry set + MOV X,0(PSP) \ divide z by 286 to display it as a Q15.16 number -SUB #4,PSP \ -- X * * Zhi -MOV TOS,rDOCON \ -- rDOCON as sign of QUOT -CMP #0,rDOCON -S< IF - XOR #-1,TOS - ADD #1,TOS -THEN -MOV #0,2(PSP) \ -- X Zlo * Zhi -MOV TOS,0(PSP) \ -- X Zlo Zhi Zhi -MOV #286,TOS \ -- X Zlo Zhi DIV -CALL #MUSMOD \ -- X rem QUOTlo QUOThi -MOV @PSP+,0(PSP) \ remove remainder -CMP #0,rDOCON -S< IF - XOR #-1,0(PSP) - XOR #-1,TOS - ADD #1,0(PSP) - ADDC #0,TOS -THEN -MOV #XDOCON,rDOCON -MOV @IP+,PC -ENDCODE - - -[UNDEFINED] F. [IF] -CODE F. \ display a Q15.16 number with 4/5/16 digits after comma -MOV TOS,S \ S = sign -MOV #4,T \ T = 4 preset 4 digits for base 16 and by default -MOV &BASEADR,W -CMP ##10,W -0= IF \ if base 10 - ADD #1,T \ T = 5 set 5 digits -ELSE - CMP #%10,W - 0= IF \ if base 2 - MOV #16,T \ T = 16 set 16 digits + SUB #4,PSP \ -- X * * Zhi + MOV TOS,rDOCON \ -- rDOCON as sign of QUOT + CMP #0,rDOCON + S< IF + XOR #-1,TOS + ADD #1,TOS THEN -THEN -PUSHM #3,IP \ R-- IP sign #digit -LO2HI - <# DABS \ -- uQlo uQhi R-- IP sign #digit - R> F#S \ -- uQhi 0 R-- IP sign - $2C HOLD \ $2C = char ',' - #S \ -- 0 0 - R> SIGN #> \ -- addr len R-- IP - TYPE $20 EMIT \ -- -; - -[THEN] - -PWR_HERE - -[UNDEFINED] SWAP [IF] + MOV #0,2(PSP) \ -- X Zlo * Zhi + MOV TOS,0(PSP) \ -- X Zlo Zhi Zhi + MOV #286,TOS \ -- X Zlo Zhi DIV + CALL #MUSMOD \ -- X rem QUOTlo QUOThi + MOV @PSP+,0(PSP) \ remove remainder + CMP #0,rDOCON + S< IF + XOR #-1,0(PSP) + XOR #-1,TOS + ADD #1,0(PSP) + ADDC #0,TOS + THEN + MOV #XDOCON,rDOCON + MOV @IP+,PC + ENDCODE + + + [UNDEFINED] F. + [IF] + CODE F. \ display a Q15.16 number with 4/5/16 digits after comma + MOV TOS,S \ S = sign + MOV #4,T \ T = 4 preset 4 digits for base 16 and by default + MOV &BASEADR,W + CMP ##10,W + 0= IF \ if base 10 + ADD #1,T \ T = 5 set 5 digits + ELSE + CMP #%10,W + 0= IF \ if base 2 + MOV #16,T \ T = 16 set 16 digits + THEN + THEN + PUSHM #3,IP \ R-- IP sign #digit + LO2HI + <# DABS \ -- uQlo uQhi R-- IP sign #digit + R> F#S \ -- uQhi 0 R-- IP sign + $2C HOLD \ $2C = char ',' + #S \ -- 0 0 + R> SIGN #> \ -- addr len R-- IP + TYPE $20 EMIT \ -- + ; + + [THEN] + +RST_SET + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -ECHO + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] ROT [IF] \ \ https://forth-standard.org/standard/core/ROT \ ROT x1 x2 x3 -- x2 x3 x1 -CODE ROT -MOV @PSP,W \ 2 fetch x2 -MOV TOS,0(PSP) \ 3 store x3 -MOV 2(PSP),TOS \ 3 fetch x1 -MOV W,2(PSP) \ 3 store x2 -MOV @IP+,PC -ENDCODE -[THEN] - -; ----------------------------------------------------------- -; requires FIXPOINT_INPUT kernel addon, see forthMSP430FR.asm -; ----------------------------------------------------------- - - -10000 89,0 POL2REC . . ; sin, cos --> -10000 75,0 POL2REC . . ; sin, cos --> -10000 60,0 POL2REC . . ; sin, cos --> -10000 45,0 POL2REC . . ; sin, cos --> -10000 30,0 POL2REC . . ; sin, cos --> -10000 15,0 POL2REC . . ; sin, cos --> -10000 1,0 POL2REC . . ; sin, cos --> + [UNDEFINED] ROT + [IF] \ + CODE ROT + MOV @PSP,W \ 2 fetch x2 + MOV TOS,0(PSP) \ 3 store x3 + MOV 2(PSP),TOS \ 3 fetch x1 + MOV W,2(PSP) \ 3 store x2 + MOV @IP+,PC + ENDCODE + [THEN] + +ECHO + +10000 89,0 POL2REC . . ; sin, cos --> +10000 75,0 POL2REC . . ; sin, cos --> +10000 60,0 POL2REC . . ; sin, cos --> +10000 45,0 POL2REC . . ; sin, cos --> +10000 30,0 POL2REC . . ; sin, cos --> +10000 15,0 POL2REC . . ; sin, cos --> +10000 1,0 POL2REC . . ; sin, cos --> \ module phase -- X Y -16384 30,0 POL2REC SWAP . . ; x, y --> -16384 45,0 POL2REC SWAP . . ; x, y --> -16384 60,0 POL2REC SWAP . . ; x, y --> +16384 30,0 POL2REC SWAP . . ; x, y --> +16384 45,0 POL2REC SWAP . . ; x, y --> +16384 60,0 POL2REC SWAP . . ; x, y --> \ -10000 -89,0 POL2REC . . ; sin, cos --> -10000 -75,0 POL2REC . . ; sin, cos --> -10000 -60,0 POL2REC . . ; sin, cos --> -10000 -45,0 POL2REC . . ; sin, cos --> -10000 -30,0 POL2REC . . ; sin, cos --> -10000 -15,0 POL2REC . . ; sin, cos --> -10000 -1,0 POL2REC . . ; sin, cos --> +10000 -89,0 POL2REC . . ; sin, cos --> +10000 -75,0 POL2REC . . ; sin, cos --> +10000 -60,0 POL2REC . . ; sin, cos --> +10000 -45,0 POL2REC . . ; sin, cos --> +10000 -30,0 POL2REC . . ; sin, cos --> +10000 -15,0 POL2REC . . ; sin, cos --> +10000 -1,0 POL2REC . . ; sin, cos --> \ module phase -- X Y -16384 -30,0 POL2REC SWAP . . ; x, y --> -16384 -45,0 POL2REC SWAP . . ; x, y --> -16384 -60,0 POL2REC SWAP . . ; x, y --> +16384 -30,0 POL2REC SWAP . . ; x, y --> +16384 -45,0 POL2REC SWAP . . ; x, y --> +16384 -60,0 POL2REC SWAP . . ; x, y --> \ --10000 89,0 POL2REC . . ; sin, cos --> --10000 75,0 POL2REC . . ; sin, cos --> --10000 60,0 POL2REC . . ; sin, cos --> --10000 45,0 POL2REC . . ; sin, cos --> --10000 30,0 POL2REC . . ; sin, cos --> --10000 15,0 POL2REC . . ; sin, cos --> --10000 1,0 POL2REC . . ; sin, cos --> +-10000 89,0 POL2REC . . ; sin, cos --> +-10000 75,0 POL2REC . . ; sin, cos --> +-10000 60,0 POL2REC . . ; sin, cos --> +-10000 45,0 POL2REC . . ; sin, cos --> +-10000 30,0 POL2REC . . ; sin, cos --> +-10000 15,0 POL2REC . . ; sin, cos --> +-10000 1,0 POL2REC . . ; sin, cos --> \ module phase -- X Y --16384 30,0 POL2REC SWAP . . ; x, y --> --16384 45,0 POL2REC SWAP . . ; x, y --> --16384 60,0 POL2REC SWAP . . ; x, y --> +-16384 30,0 POL2REC SWAP . . ; x, y --> +-16384 45,0 POL2REC SWAP . . ; x, y --> +-16384 60,0 POL2REC SWAP . . ; x, y --> \ --10000 -89,0 POL2REC . . ; sin, cos --> --10000 -75,0 POL2REC . . ; sin, cos --> --10000 -60,0 POL2REC . . ; sin, cos --> --10000 -45,0 POL2REC . . ; sin, cos --> --10000 -30,0 POL2REC . . ; sin, cos --> --10000 -15,0 POL2REC . . ; sin, cos --> --10000 -1,0 POL2REC . . ; sin, cos --> +-10000 -89,0 POL2REC . . ; sin, cos --> +-10000 -75,0 POL2REC . . ; sin, cos --> +-10000 -60,0 POL2REC . . ; sin, cos --> +-10000 -45,0 POL2REC . . ; sin, cos --> +-10000 -30,0 POL2REC . . ; sin, cos --> +-10000 -15,0 POL2REC . . ; sin, cos --> +-10000 -1,0 POL2REC . . ; sin, cos --> \ module phase -- X Y --16384 -30,0 POL2REC SWAP . . ; x, y --> --16384 -45,0 POL2REC SWAP . . ; x, y --> --16384 -60,0 POL2REC SWAP . . ; x, y --> +-16384 -30,0 POL2REC SWAP . . ; x, y --> +-16384 -45,0 POL2REC SWAP . . ; x, y --> +-16384 -60,0 POL2REC SWAP . . ; x, y --> \ -2 1 REC2POL F. . ; phase module --> -2 -1 REC2POL F. . ; phase module --> -20 10 REC2POL F. . ; phase module --> -20 -10 REC2POL F. . ; phase module --> -200 100 REC2POL F. . ; phase module --> -100 -100 REC2POL F. . ; phase module --> -2000 1000 REC2POL F. . ; phase module --> -1000 -1000 REC2POL F. . ; phase module --> -16000 8000 REC2POL F. . ; phase module --> -16000 -8000 REC2POL F. . ; phase module --> -16000 0 REC2POL F. . ; phase module --> -0 16000 REC2POL F. . ; phase module --> +2 1 REC2POL F. . ; phase module --> +2 -1 REC2POL F. . ; phase module --> +20 10 REC2POL F. . ; phase module --> +20 -10 REC2POL F. . ; phase module --> +200 100 REC2POL F. . ; phase module --> +100 -100 REC2POL F. . ; phase module --> +2000 1000 REC2POL F. . ; phase module --> +1000 -1000 REC2POL F. . ; phase module --> +16000 8000 REC2POL F. . ; phase module --> +16000 -8000 REC2POL F. . ; phase module --> +16000 0 REC2POL F. . ; phase module --> +0 16000 REC2POL F. . ; phase module --> \ 16384 -8192 REC2POL F. . ; --> abort \ 0 0 REC2POL F. . ; --> abort --2 1 REC2POL F. . ; phase module --> --2 -1 REC2POL F. . ; phase module --> --20 10 REC2POL F. . ; phase module --> --20 -10 REC2POL F. . ; phase module --> --200 100 REC2POL F. . ; phase module --> --100 -100 REC2POL F. . ; phase module --> --2000 1000 REC2POL F. . ; phase module --> --1000 -1000 REC2POL F. . ; phase module --> --16000 8000 REC2POL F. . ; phase module --> --16000 -8000 REC2POL F. . ; phase module --> -16000 0 REC2POL F. . ; phase module --> -0 16000 REC2POL F. . ; phase module --> +-2 1 REC2POL F. . ; phase module --> +-2 -1 REC2POL F. . ; phase module --> +-20 10 REC2POL F. . ; phase module --> +-20 -10 REC2POL F. . ; phase module --> +-200 100 REC2POL F. . ; phase module --> +-100 -100 REC2POL F. . ; phase module --> +-2000 1000 REC2POL F. . ; phase module --> +-1000 -1000 REC2POL F. . ; phase module --> +-16000 8000 REC2POL F. . ; phase module --> +-16000 -8000 REC2POL F. . ; phase module --> +16000 0 REC2POL F. . ; phase module --> +0 16000 REC2POL F. . ; phase module --> \ 16384 -8192 REC2POL F. . ; --> abort \ 0 0 REC2POL F. . ; --> abort -10000 89,0 POL2REC REC2POL ROT . F. -10000 75,0 POL2REC REC2POL ROT . F. -10000 60,0 POL2REC REC2POL ROT . F. -10000 45,0 POL2REC REC2POL ROT . F. -10000 30,0 POL2REC REC2POL ROT . F. -10000 26,565 POL2REC REC2POL ROT . F. -10000 15,0 POL2REC REC2POL ROT . F. -10000 14,036 POL2REC REC2POL ROT . F. -10000 7,125 POL2REC REC2POL ROT . F. -10000 1,0 POL2REC REC2POL ROT . F. +10000 89,0 POL2REC REC2POL ROT . F. +10000 75,0 POL2REC REC2POL ROT . F. +10000 60,0 POL2REC REC2POL ROT . F. +10000 45,0 POL2REC REC2POL ROT . F. +10000 30,0 POL2REC REC2POL ROT . F. +10000 26,565 POL2REC REC2POL ROT . F. +10000 15,0 POL2REC REC2POL ROT . F. +10000 14,036 POL2REC REC2POL ROT . F. +10000 7,125 POL2REC REC2POL ROT . F. +10000 1,0 POL2REC REC2POL ROT . F. diff --git a/MSP430-FORTH/CORETEST.4TH b/MSP430-FORTH/CORETEST.4TH index b358899..dd67eec 100644 --- a/MSP430-FORTH/CORETEST.4TH +++ b/MSP430-FORTH/CORETEST.4TH @@ -3,25 +3,78 @@ \ ; CORETEST.4TH for any FastForth target \ ; ------------------------------------- -[DEFINED] {CORETEST} [IF] {CORETEST} [THEN] - MARKER {CORETEST} -: ABORT_TEST -$0D EMIT \ return to column 1 -POSTPONE {CORETEST} \ that remove all test words +: ABORT_TEST \ flag -- +$0D EMIT \ return to column 1 +POSTPONE {CORETEST} \ remove all test words ABORT" {CORE_ANS} word set not found !" ; [UNDEFINED] {CORE_ANS} ABORT_TEST : CORETESTSUCCESS -$0A BASE ! -$0D EMIT \ return to column 1 -{CORETEST} \ that remove all test words -1 ABORT" CORE tests success!" +$0D EMIT \ -- $0D return to column 1 +$0A BASE ! \ set decimal +{CORETEST} \ remove all test words +." CORETEST + COREPLUSTEST success!" \ true -- ; +[UNDEFINED] SM/REM [IF] +CODE SM/REM +MOV R14,R12 +MOV @R15,R11 +CMP #0,R14 +S< IF + XOR #-1,R14 + ADD #1,R14 +THEN +CMP #0,0(R15) +S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) +THEN +PUSHM #3,R13 +LO2HI + UM/MOD +HI2LO +POPM #3,R13 +CMP #0,R11 +S< IF + XOR #-1,0(R15) + ADD #1,0(R15) +THEN +XOR R12,R11 +CMP #0,R11 +S< IF + XOR #-1,R14 + ADD #1,R14 +THEN +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] FM/MOD [IF] +\ https://forth-standard.org/standard/core/FMDivMOD +\ FM/MOD d1 n1 -- r q floored signed div'n +: FM/MOD +SM/REM +HI2LO \ -- remainder quotient S=divisor +CMP #0,0(R15) \ remainder <> 0 ? +0<> IF + CMP #1,R14 \ quotient < 1 ? + S< IF + ADD R12,0(R15) \ add divisor to remainder + SUB #1,R14 \ decrement quotient + THEN +THEN +MOV @R1+,R13 +MOV @R13+,R0 +ENDCODE +[THEN] + \ From: John Hayes S1I \ Subject: tester.fr \ Date: Mon, 27 Nov 95 13:10:09 PST @@ -52,7 +105,7 @@ VARIABLE VERBOSE \ DO 0 LOOP \ ELSE 0 DO DROP LOOP THEN \ THEN ; -\ +\ \ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY \ \ THE LINE THAT HAD THE ERROR. \ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR @@ -1084,7 +1137,7 @@ CREATE ABUF 80 CHARS ALLOT : ACCEPT-TEST CR ." PLEASE TYPE UP TO 80 CHARACTERS: " -ABUF 80 \ ACCEPT \ JMT +ABUF 80 \ ACCEPT \ JMT ['] ACCEPT >BODY \ JMT: find default part of deferred ACCEPT EXECUTE \ JMT: execute ACCEPT CR ." RECEIVED: " [CHAR] " EMIT @@ -1100,100 +1153,13 @@ T{ : GDX 123 ; : GDX GDX 234 ; -> }T T{ GDX -> 123 234 }T -\ ------------------------------------------------------------------------ -TESTING TO VALUE :NONAME IS DEFER - -[DEFINED] VALUE [IF] -T{ 111 VALUE v1 -> }T -T{ -999 VALUE v2 -> }T -T{ v1 -> 111 }T -T{ v2 -> -999 }T -T{ 222 TO v1 -> }T -T{ v1 -> 222 }T -T{ : vd1 v1 ; -> }T -T{ vd1 -> 222 }T -T{ : vd2 TO v2 ; -> }T -T{ v2 -> -999 }T -T{ -333 vd2 -> }T -T{ v2 -> -333 }T -T{ v1 -> 222 }T -[THEN] - -[DEFINED] :NONAME [IF] - -[UNDEFINED] CASE [IF] -\ https://forth-standard.org/standard/core/CASE -: CASE 0 ; IMMEDIATE \ -- #of-1 - -\ https://forth-standard.org/standard/core/OF -: OF \ #of-1 -- orgOF #of -1+ \ count OFs ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE OVER POSTPONE = \ copy and test case value -POSTPONE IF \ add orig to control flow stack -POSTPONE DROP \ discards case value if = -R> \ we can bring count back now -; IMMEDIATE - -\ https://forth-standard.org/standard/core/ENDOF -: ENDOF \ orgOF #of -- orgENDOF #of ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE ELSE -R> \ we can bring count back now -; IMMEDIATE - -\ https://forth-standard.org/standard/core/ENDCASE -: ENDCASE \ orgENDOF1..orgENDOFn #of -- -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -VARIABLE nn1 -VARIABLE nn2 -T{ :NONAME 1234 ; nn1 ! -> }T -T{ :NONAME 9876 ; nn2 ! -> }T -T{ nn1 @ EXECUTE -> 1234 }T -T{ nn2 @ EXECUTE -> 9876 }T - -T{ :NONAME ( n -- 0,1,..n ) DUP IF DUP >R 1- RECURSE R> THEN ; - CONSTANT RN1 -> }T -T{ 0 RN1 EXECUTE -> 0 }T -T{ 4 RN1 EXECUTE -> 0 1 2 3 4 }T - -:NONAME ( n -- n1 ) \ Multiple RECURSEs in one definition - 1- DUP - CASE 0 OF EXIT ENDOF - 1 OF 11 SWAP RECURSE ENDOF - 2 OF 22 SWAP RECURSE ENDOF - 3 OF 33 SWAP RECURSE ENDOF - DROP ABS RECURSE EXIT - ENDCASE -; CONSTANT RN2 +CR .( End of Core word set tests) \ " -T{ 1 RN2 EXECUTE -> 0 }T -T{ 2 RN2 EXECUTE -> 11 0 }T -T{ 4 RN2 EXECUTE -> 33 22 11 0 }T -T{ 25 RN2 EXECUTE -> 33 22 11 0 }T - -[THEN] - -[DEFINED] IS [IF] -T{ DEFER defer5 -> }T -T{ : is-defer5 IS defer5 ; -> }T -T{ ' * IS defer5 -> }T -T{ 2 3 defer5 -> 6 }T -T{ ' + is-defer5 -> }T -T{ 1 2 defer5 -> 3 }T -[THEN] - -\ ============================================================================== +\ ============================================================================= \ COREPLUSTEST -\ ============================================================================== +\ ============================================================================= \ Additional tests on the the ANS Forth Core word set -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- \ https://raw.githubusercontent.com/gerryjackson/forth2012-test-suite/master/src/coreplustest.fth \ This program was written by Gerry Jackson in 2007, with contributions from @@ -1204,9 +1170,9 @@ T{ 1 2 defer5 -> 3 }T \ but WITHOUT ANY WARRANTY; without even the implied warranty of \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -\ The tests are not claimed to be comprehensive or correct +\ The tests are not claimed to be comprehensive or correct -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- \ The tests are based on John Hayes test program for the core word set \ \ This file provides some more tests on Core words where the original Hayes @@ -1218,12 +1184,12 @@ T{ 1 2 defer5 -> 3 }T \ Parsing behaviour \ Number prefixes # $ % and 'A' character input \ Definition names -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- \ Assumptions and dependencies: \ - tester.fr or ttester.fs has been loaded prior to this file \ - core.fr has been loaded so that constants <TRUE> MAX-INT, MIN-INT and \ MAX-UINT are defined -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- DECIMAL @@ -1262,7 +1228,7 @@ T{ -20 30 -10 GD7 -> 30 20 10 0 -10 -20 6 }T T{ -20 31 -10 GD7 -> 31 21 11 1 -9 -19 6 }T T{ -20 29 -10 GD7 -> 29 19 9 -1 -11 5 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING DO +LOOP with large and small increments \ Contributed by Andrew Haley @@ -1300,7 +1266,7 @@ T{ 0 0 0 -USTEP -UWRAP? 1 GD9 T{ 0 MIN-INT MAX-INT STEP +WRAP? 1 GD9 T{ 0 MAX-INT MIN-INT -STEP -WRAP? 1 GD9 -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING DO +LOOP with maximum and minimum increments : (-MI) MAX-INT DUP NEGATE + 0= IF MAX-INT NEGATE ELSE -32767 THEN ; @@ -1319,7 +1285,7 @@ T{ 0 MIN-INT 1+ -1 MIN-INT GD8 -> 1 }T T{ 0 MIN-INT 1+ 1 MIN-INT GD8 -> 2 }T T{ 0 MIN-INT 1+ DUP MIN-INT GD8 -> 1 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- \ TESTING +LOOP setting I to an arbitrary value \ The specification for +LOOP permits the loop index I to be set to any value @@ -1329,7 +1295,7 @@ T{ 0 MIN-INT 1+ DUP MIN-INT GD8 -> 1 }T \ n2 is the value of I in a DO ... +LOOP \ n3 is a test value \ If n2=n3 then return n1-n2 else return 1 -: SET-I ( n1 n2 n3 -- n1-n2 | 1 ) +: SET-I ( n1 n2 n3 -- n1-n2 | 1 ) OVER = IF - ELSE 2DROP 1 THEN ; @@ -1354,7 +1320,7 @@ T{ PL7 -> -1 -2 -3 -4 -5 }T : PL8 -20 -5 DO I -20 I -2 -SET-I DUP -1 = IF DROP 0 I -6 -SET-I THEN +LOOP ; T{ PL8 -> -5 -6 0 -1 -2 -20 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING multiple RECURSEs in one colon definition : ACK ( m n -- u ) \ Ackermann function, from Rosetta Code @@ -1368,7 +1334,7 @@ T{ 0 0 ACK -> 1 }T T{ 3 0 ACK -> 5 }T T{ 2 4 ACK -> 11 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING multiple ELSE's in an IF statement \ Discussed on comp.lang.forth and accepted as valid ANS Forth @@ -1376,22 +1342,22 @@ TESTING multiple ELSE's in an IF statement T{ 0 MELSE -> 2 4 }T T{ -1 MELSE -> 1 3 5 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING manipulation of >IN in interpreter mode T{ 12345 DEPTH OVER 9 < 34 AND + 3 + >IN ! -> 12345 2345 345 45 5 }T T{ 14145 8115 ?DUP 0= 34 AND >IN +! TUCK MOD 14 >IN ! GCD CALCULATION -> 15 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING IMMEDIATE with CONSTANT VARIABLE and CREATE [ ... DOES> ] T{ 123 CONSTANT IW1 IMMEDIATE IW1 -> 123 }T T{ : IW2 IW1 LITERAL ; IW2 -> 123 }T T{ VARIABLE IW3 IMMEDIATE 234 IW3 ! IW3 @ -> 234 }T T{ : IW4 IW3 [ @ ] LITERAL ; IW4 -> 234 }T -\ T{ :NONAME [ 345 ] IW3 [ ! ] ; DROP IW3 @ -> 345 }T +T{ :NONAME [ 345 ] IW3 [ ! ] ; DROP IW3 @ -> 345 }T T{ CREATE IW5 456 , IMMEDIATE -> }T -\ T{ :NONAME IW5 [ @ IW3 ! ] ; DROP IW3 @ -> 456 }T +T{ :NONAME IW5 [ @ IW3 ! ] ; DROP IW3 @ -> 456 }T T{ : IW6 CREATE , IMMEDIATE DOES> @ 1+ ; -> }T T{ 111 IW6 IW7 IW7 -> 112 }T T{ : IW8 IW7 LITERAL 1+ ; IW8 -> 113 }T @@ -1400,27 +1366,22 @@ T{ : IW9 CREATE , DOES> @ 2 + IMMEDIATE ; -> }T T{ 222 IW9 IW10 FIND-IW IW10 -> -1 }T \ IW10 is not immediate T{ IW10 FIND-IW IW10 -> 224 1 }T \ IW10 becomes immediate -[DEFINED] :NONAME [IF] -T{ :NONAME [ 345 ] IW3 [ ! ] ; DROP IW3 @ -> 345 }T -T{ :NONAME IW5 [ @ IW3 ! ] ; DROP IW3 @ -> 456 }T -[THEN] - -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING that IMMEDIATE doesn't toggle a flag VARIABLE IT1 0 IT1 ! : IT2 1234 IT1 ! ; IMMEDIATE IMMEDIATE T{ : IT3 IT2 ; IT1 @ -> 1234 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING parsing behaviour of S" ." and ( \ which should parse to just beyond the terminating character no space needed T{ : GC5 S" A string"2DROP ; GC5 -> }T T{ ( A comment)1234 -> 1234 }T T{ : PB1 CR ." You should see 2345: "." 2345"( A comment) CR ; PB1 -> }T - -\ ------------------------------------------------------------------------------ + +\ ----------------------------------------------------------------------------- TESTING number prefixes # $ % and 'c' character input \ Adapted from the Forth 200X Draft 14.5 document @@ -1454,7 +1415,7 @@ DECIMAL \ Check number prefixes in compile mode T{ : nmp #8327 $-2cbe %011010111 ''' ; nmp -> 8327 -11454 215 39 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING definition names \ should support {1..31} graphical characters : !"#$%&'()*+,-./0123456789:;<=>? 1 ; @@ -1467,7 +1428,7 @@ T{ _`abcdefghijklmnopqrstuvwxyz{|} -> 3 }T T{ _`abcdefghijklmnopqrstuvwxyz{|~ -> 4 }T T{ _`abcdefghijklmnopqrstuvwxyz{|} -> 3 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING FIND with a zero length string and a non-existent word CREATE EMPTYSTRING 0 C, @@ -1482,37 +1443,83 @@ CREATE NON-EXISTENT-WORD \ Same as in exceptiontest.fth CHAR $ C, CHAR $ C, T{ NON-EXISTENT-WORD FIND -> NON-EXISTENT-WORD 0 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING IF ... BEGIN ... REPEAT (unstructured) T{ : UNS1 DUP 0 > IF 9 SWAP BEGIN 1+ DUP 3 > IF EXIT THEN REPEAT ; -> }T T{ -6 UNS1 -> -6 }T T{ 1 UNS1 -> 9 4 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING DOES> doesn't cause a problem with a CREATEd address : MAKE-2CONST DOES> 2@ ; T{ CREATE 2K 3 , 2K , MAKE-2CONST 2K -> ' 2K >BODY 3 }T -\ ------------------------------------------------------------------------------ +\ ----------------------------------------------------------------------------- TESTING ALLOT ( n -- ) where n <= 0 T{ HERE 5 ALLOT -5 ALLOT HERE = -> <TRUE> }T T{ HERE 0 ALLOT HERE = -> <TRUE> }T - + \ ----------------------------------------------------------------------------- -TESTING MARKER (contributed by James Bowman) -[DEFINED] MARKER [IF] +CR .( End of additional Core tests) \ " + +\ ----------------------------------------------------------------------------- +TESTING TO VALUE :NONAME IS DEFER + +T{ 111 VALUE v1 -> }T +T{ -999 VALUE v2 -> }T +T{ v1 -> 111 }T +T{ v2 -> -999 }T +T{ 222 TO v1 -> }T +T{ v1 -> 222 }T +T{ : vd1 v1 ; -> }T +T{ vd1 -> 222 }T +T{ : vd2 TO v2 ; -> }T +T{ v2 -> -999 }T +T{ -333 vd2 -> }T +T{ v2 -> -333 }T +T{ v1 -> 222 }T + +VARIABLE nn1 +VARIABLE nn2 +T{ :NONAME 1234 ; nn1 ! -> }T +T{ :NONAME 9876 ; nn2 ! -> }T +T{ nn1 @ EXECUTE -> 1234 }T +T{ nn2 @ EXECUTE -> 9876 }T + +T{ :NONAME ( n -- 0,1,..n ) DUP IF DUP >R 1- RECURSE R> THEN ; + CONSTANT RN1 -> }T +T{ 0 RN1 EXECUTE -> 0 }T +T{ 4 RN1 EXECUTE -> 0 1 2 3 4 }T - [UNDEFINED] 0<> [IF] - CODE 0<> - CMP #0,R14 - 0<> IF MOV #-1,R14 THEN - MOV @R13+,R0 - ENDCODE - [THEN] +:NONAME ( n -- n1 ) \ Multiple RECURSEs in one definition + 1- DUP + CASE 0 OF EXIT ENDOF + 1 OF 11 SWAP RECURSE ENDOF + 2 OF 22 SWAP RECURSE ENDOF + 3 OF 33 SWAP RECURSE ENDOF + DROP ABS RECURSE EXIT + ENDCASE +; CONSTANT RN2 + +T{ 1 RN2 EXECUTE -> 0 }T +T{ 2 RN2 EXECUTE -> 11 0 }T +T{ 4 RN2 EXECUTE -> 33 22 11 0 }T +T{ 25 RN2 EXECUTE -> 33 22 11 0 }T + + +T{ DEFER defer5 -> }T +T{ : is-defer5 IS defer5 ; -> }T +T{ ' * IS defer5 -> }T +T{ 2 3 defer5 -> 6 }T +T{ ' + is-defer5 -> }T +T{ 1 2 defer5 -> 3 }T + +\ ----------------------------------------------------------------------------- +TESTING MARKER (contributed by James Bowman) T{ : MA? BL WORD FIND NIP 0<> ; -> }T T{ MARKER MA0 -> }T @@ -1525,9 +1532,4 @@ T{ MA? MA0 MA? MA1 MA? MA2 -> TRUE TRUE FALSE }T T{ MA0 -> }T T{ MA? MA0 MA? MA1 MA? MA2 -> FALSE FALSE FALSE }T -[THEN] - - -CR .( End of Core word set tests) - CORETESTSUCCESS diff --git a/MSP430-FORTH/CORE_ANS.f b/MSP430-FORTH/CORE_ANS.f index 57013a6..67f5e5e 100644 --- a/MSP430-FORTH/CORE_ANS.f +++ b/MSP430-FORTH/CORE_ANS.f @@ -1,8 +1,5 @@ \ -*- coding: utf-8 -*- \ -\ FastForth kernel options: MSP430ASSEMBLER, CONDCOMP -\ to see FastForth kernel options, download FF_SPECS.f -\ \ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) \ (used by preprocessor GEMA to load the pattern: \inc\TARGET.pat) \ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 @@ -32,264 +29,353 @@ \ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>= \ ASSEMBLER conditionnal usage with ?GOTO S< S>= U< U>= 0= 0<> 0< -CODE ABORT_CORE_ANS -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_UARTI2CS before CORE_ANS downloading -; + CODE ABORT_CORE_ANS + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ; + + ABORT_CORE_ANS + +\ BC! pattern @ -- Bits Clear in @ + [UNDEFINED] BC! + [IF] + CODE BC! + BIC @PSP+,0(TOS) + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ BS! pattern @ -- Bits Set in @ + [UNDEFINED] BS! + [IF] + CODE BS! + BIS @PSP+,0(TOS) + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ ============================================================================= +\ $8000 KERNEL_ADDON BS! \ uncomment to select FLOORED division + $8000 KERNEL_ADDON BC! \ uncomment to select SYMMETRIC division +\ ============================================================================= -ABORT_CORE_ANS + RST_RET \ remove all above before CORE_ANS downloading -; --------------------------------- +; ---------------------------------- ; CORE_ANS.f -; --------------------------------- +; ---------------------------------- \ -; words complement to pass CORETEST.4TH - -[DEFINED] {CORE_ANS} [IF] {CORE_ANS} [THEN] \ remove it if defined out of kernel +\ words complement to pass CORETEST.4TH -[UNDEFINED] {CORE_ANS} [IF] \ + MARKER {CORE_ANS} \ if already defined removes it before. -MARKER {CORE_ANS} + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #HEREXEC,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP + [IF] + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] EXIT [IF] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/EXIT \ EXIT -- exit a colon definition -CODE EXIT -MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack -MOV @IP+,PC \ 4 = NEXT -\ \ 6 (ITC-2) -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack + MOV @IP+,PC \ 4 = NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DEPTH \ DEPTH -- +n number of items on stack, must leave 0 if stack empty -CODE DEPTH -MOV TOS,-2(PSP) -MOV #PSTACK,TOS -SUB PSP,TOS \ PSP-S0--> TOS -RRA TOS \ TOS/2 --> TOS -SUB #2,PSP \ post decrement stack... -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV TOS,-2(PSP) + MOV #PSTACK,TOS + SUB PSP,TOS \ PSP-S0--> TOS + RRA TOS \ TOS/2 --> TOS + SUB #2,PSP \ post decrement stack... + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH TOS \ 3 + MOV @PSP,TOS \ 2 + MOV @RSP+,0(PSP) \ 4 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DROP \ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/OVER +\ OVER x1 x2 -- x1 x2 x1 + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] NIP [IF] \ https://forth-standard.org/standard/core/NIP \ NIP x1 x2 -- x2 Drop the first item below the top of stack -CODE NIP -ADD #2,PSP -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] NIP + [IF] + CODE NIP + ADD #2,PSP + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] >R [IF] \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom -\ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] @ [IF] +\ R> -- x R: x -- pop from return stack + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Fetch -\ @ c-addr -- char fetch char from memory -CODE @ -MOV @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ! [IF] +\ @ c-addr -- word fetch word from memory + [UNDEFINED] @ + [IF] + CODE @ + MOV @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Store -\ ! x a-addr -- store cell in memory -CODE ! -MOV @PSP+,0(TOS) \ 4 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -\ https://forth-standard.org/standard/core/CFetch +\ ! word c-addr -- store word in memory + [UNDEFINED] ! + [IF] + CODE ! + MOV @PSP+,0(TOS) \ 4 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Fetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] C! [IF] \ https://forth-standard.org/standard/core/CStore \ C! char c-addr -- store char in memory -CODE C! -MOV.B @PSP+,0(TOS) \ 4 -ADD #1,PSP \ 1 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] C, [IF] + [UNDEFINED] C! + [IF] + CODE C! + MOV.B @PSP+,0(TOS) \ 4 + ADD #1,PSP \ 1 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CComma \ C, char -- append char -CODE C, -MOV &DP,W -MOV.B TOS,0(W) -ADD #1,&DP -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] + [UNDEFINED] C, + [IF] + CODE C, + MOV &DP,W + MOV.B TOS,0(W) + ADD #1,&DP + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ZeroEqual \ 0= n/u -- flag return true if TOS=0 -CODE 0= -SUB #1,TOS \ borrow (clear cy) if TOS was 0 -SUBC TOS,TOS \ TOS=-1 if borrow was set -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ 1 TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Zerone +\ 0<> n/u -- flag return true if TOS<>0 + [UNDEFINED] 0<> + [IF] + CODE 0<> + SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ 1 TOS=-1 if borrow was set + XOR #-1,TOS \ 1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Zeroless \ 0< n -- flag true if TOS negative -CODE 0< -ADD TOS,TOS \ 1 set carry if TOS negative -SUBC TOS,TOS \ 1 TOS=-1 if carry was clear -XOR #-1,TOS \ 1 TOS=-1 if carry was set -MOV @IP+,PC \ -ENDCODE -[THEN] - -[UNDEFINED] = [IF] + [UNDEFINED] 0< + [IF] + CODE 0< +BW1 ADD TOS,TOS \ 1 set carry if TOS negative + SUBC TOS,TOS \ 1 TOS=-1 if carry was clear + XOR #-1,TOS \ 1 TOS=-1 if carry was set + MOV @IP+,PC \ + ENDCODE + [THEN] + +\ HERE + +\ https://forth-standard.org/standard/core/StoD +\ S>D n -- d single -> double prec. + [UNDEFINED] S>D + [IF] + : S>D + DUP 0< + ; + [THEN] + \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ 1 TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] \ https://forth-standard.org/standard/core/Uless \ U< u1 u2 -- flag test u1<u2, unsigned -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 + [UNDEFINED] U< + [IF] + + CODE U< + SUB @PSP+,TOS \ 2 u2-u1 + U< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,TOS \ 1 THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE + +\ https://forth-standard.org/standard/core/Umore +\ U> n1 n2 -- flag + CODE U> + SUB @PSP+,TOS \ 2 + U< ?GOTO BW1 \ 2 flag = true, Z = 0 +FW1 AND #0,TOS \ 1 Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] < [IF] \ define < and > \ https://forth-standard.org/standard/core/less \ < n1 n2 -- flag test n1<n2, signed -CODE < - SUB @PSP+,TOS \ 1 TOS=n2-n1 - S< ?GOTO FW1 \ 2 signed - 0<> IF \ 2 -BW1 MOV #-1,TOS \ 1 flag Z = 0 - THEN - MOV @IP+,PC -ENDCODE + [UNDEFINED] < + [IF] \ define < and > + + CODE < + SUB @PSP+,TOS \ 1 TOS=n2-n1 + S< ?GOTO FW1 \ 2 signed + 0<> IF \ 2 +BW1 MOV #-1,TOS \ 1 flag Z = 0 + THEN + MOV @IP+,PC + ENDCODE \ https://forth-standard.org/standard/core/more \ > n1 n2 -- flag test n1>n2, signed -CODE > - SUB @PSP+,TOS \ 2 TOS=n2-n1 - S< ?GOTO BW1 \ 2 --> +5 -FW1 AND #0,TOS \ 1 flag Z = 1 - MOV @IP+,PC -ENDCODE -[THEN] + CODE > + SUB @PSP+,TOS \ 2 TOS=n2-n1 + S< ?GOTO BW1 \ 2 --> +5 +FW1 AND #0,TOS \ 1 flag Z = 1 + MOV @IP+,PC + ENDCODE + [THEN] \ ------------------------------------------------------------------------------ \ CONTROL STRUCTURES @@ -299,52 +385,57 @@ ENDCODE \ IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words \ LEAVE compile three words \ -[UNDEFINED] IF [IF] \ define IF THEN \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF THEN + + CODE IF + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/BEGIN \ BEGIN -- BEGINadr initialize backward branch -CODE BEGIN + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + + CODE BEGIN MOV #HEREXEC,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/UNTIL \ UNTIL BEGINadr -- resolve conditional backward branch -CODE UNTIL \ immediate + CODE UNTIL MOV #QFBRAN,X BW1 ADD #4,&DP \ compile two words MOV &DP,W \ W = HERE @@ -352,977 +443,1138 @@ BW1 ADD #4,&DP \ compile two words MOV TOS,-2(W) \ compile bakcward adr at HERE+2 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/AGAIN \ AGAIN BEGINadr -- resolve uncondionnal backward branch -CODE AGAIN \ immediate -MOV #BRAN,X -GOTO BW1 -ENDCODE IMMEDIATE + CODE AGAIN + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/WHILE \ WHILE BEGINadr -- WHILEadr BEGINadr -: WHILE \ immediate -POSTPONE IF SWAP -; IMMEDIATE + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE \ https://forth-standard.org/standard/core/REPEAT \ REPEAT WHILEadr BEGINadr -- resolve WHILE loop -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0, init + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W MOV X,-4(W) \ xloop --> HERE MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP \ immediate -MOV #XPLOOP,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] J [IF] + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/J \ J -- n R: 4*sys -- 4*sys \ C get the second loop index -CODE J -SUB #2,PSP -MOV TOS,0(PSP) -MOV 4(RSP),TOS -SUB 6(RSP),TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] UNLOOP [IF] + [UNDEFINED] J + [IF] + CODE J + SUB #2,PSP + MOV TOS,0(PSP) + MOV 4(RSP),TOS + SUB 6(RSP),TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/UNLOOP \ UNLOOP -- R: sys1 sys2 -- drop loop parms -CODE UNLOOP -ADD #4,RSP -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] UNLOOP + [IF] + CODE UNLOOP + ADD #4,RSP + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] LEAVE [IF] \ https://forth-standard.org/standard/core/LEAVE \ LEAVE -- L: -- adrs -CODE LEAVE -MOV &DP,W \ compile three words -MOV #UNLOOP,0(W) \ [HERE] = UNLOOP -MOV #BRAN,2(W) \ [HERE+2] = BRAN -ADD #6,&DP \ [HERE+4] = After LOOP adr -ADD #2,&LEAVEPTR -ADD #4,W -MOV &LEAVEPTR,X -MOV W,0(X) \ leave HERE+4 on LEAVEPTR stack -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] AND [IF] + [UNDEFINED] LEAVE + [IF] + CODE LEAVE + MOV &DP,W \ compile three words + MOV #UNLOOP,0(W) \ [HERE] = UNLOOP + MOV #BRAN,2(W) \ [HERE+2] = BRAN + ADD #6,&DP \ [HERE+4] = at adr After LOOP + ADD #2,&LEAVEPTR + ADD #4,W + MOV &LEAVEPTR,X + MOV W,0(X) \ leave HERE+4 on LEAVEPTR stack + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/AND \ C AND x1 x2 -- x3 logical AND -CODE AND -AND @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] AND + [IF] + CODE AND + AND @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] OR [IF] \ https://forth-standard.org/standard/core/OR -\ C OR x1 x2 -- x3 logical OR -CODE OR -BIS @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] XOR [IF] +\ C OR x1 x2 -- x3 logical OR (BIS, BIts Set) + [UNDEFINED] OR + [IF] + CODE OR + BIS @PSP+,TOS + AND #-1,TOS \ to set flags + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/XOR \ C XOR x1 x2 -- x3 logical XOR -CODE XOR -XOR @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] S>D [IF] -\ https://forth-standard.org/standard/core/StoD -\ S>D n -- d single -> double prec. -: S>D - DUP 0< -; -[THEN] + [UNDEFINED] XOR + [IF] + CODE XOR + XOR @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] -\ https://forth-standard.org/standard/core/Plus -\ + n1/u1 n2/u2 -- n3/u3 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -\ https://forth-standard.org/standard/core/Minus -\ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] 1- [IF] \ https://forth-standard.org/standard/core/OneMinus \ 1- n1/u1 -- n2/u2 subtract 1 from TOS -CODE 1- -SUB #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] INVERT [IF] \ https://forth-standard.org/standard/core/INVERT \ INVERT x1 -- x2 bitwise inversion -CODE INVERT -XOR #-1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] INVERT + [IF] + CODE INVERT + XOR #-1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] NEGATE [IF] \ https://forth-standard.org/standard/core/NEGATE \ C NEGATE x1 -- x2 two's complement -CODE NEGATE -XOR #-1,TOS -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ABS [IF] + [UNDEFINED] NEGATE + [IF] + CODE NEGATE + XOR #-1,TOS + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ABS \ C ABS n1 -- +n2 absolute value -CODE ABS -CMP #0,TOS \ 1 -0>= IF - MOV @IP+,PC -THEN -MOV #NEGATE,PC -ENDCODE -[THEN] + [UNDEFINED] ABS + [IF] + CODE ABS + CMP #0,TOS \ 1 + 0>= IF + MOV @IP+,PC + THEN + MOV #NEGATE,PC + ENDCODE + [THEN] -[UNDEFINED] LSHIFT [IF] \ https://forth-standard.org/standard/core/LSHIFT \ LSHIFT x1 u -- x2 logical L shift u places -CODE LSHIFT - MOV @PSP+,W - AND #$1F,TOS \ no need to shift more than 16 -0<> IF - BEGIN ADD W,W + [UNDEFINED] LSHIFT + [IF] + CODE LSHIFT + MOV @PSP+,W + AND #$1F,TOS \ no need to shift more than 16 + 0<> IF + BEGIN + ADD W,W SUB #1,TOS - 0= UNTIL -THEN MOV W,TOS - MOV @IP+,PC -ENDCODE -[THEN] + 0= UNTIL + THEN + MOV W,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] RSHIFT [IF] \ https://forth-standard.org/standard/core/RSHIFT \ RSHIFT x1 u -- x2 logical R7 shift u places -CODE RSHIFT - MOV @PSP+,W - AND #$1F,TOS \ no need to shift more than 16 -0<> IF - BEGIN BIC #C,SR \ Clr Carry + [UNDEFINED] RSHIFT + [IF] + CODE RSHIFT + MOV @PSP+,W + AND #$1F,TOS \ no need to shift more than 16 + 0<> IF + BEGIN + BIC #C,SR \ Clr Carry RRC W SUB #1,TOS - 0= UNTIL -THEN MOV W,TOS - MOV @IP+,PC -ENDCODE -[THEN] + 0= UNTIL + THEN + MOV W,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] MAX [IF] \ https://forth-standard.org/standard/core/MAX \ MAX n1 n2 -- n3 signed maximum -CODE MAX + [UNDEFINED] MAX + [IF] + + CODE MAX CMP @PSP,TOS \ n2-n1 S< ?GOTO FW1 \ n2<n1 BW1 ADD #2,PSP MOV @IP+,PC -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/MIN \ MIN n1 n2 -- n3 signed minimum -CODE MIN + CODE MIN CMP @PSP,TOS \ n2-n1 S< ?GOTO BW1 \ n2<n1 FW1 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE -[THEN] - -[THEN] + ENDCODE + [THEN] -[UNDEFINED] 2* [IF] \ https://forth-standard.org/standard/core/TwoTimes \ 2* x1 -- x2 arithmetic left shift -CODE 2* -ADD TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2* + [IF] + CODE 2* + ADD TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] 2/ [IF] \ https://forth-standard.org/standard/core/TwoDiv \ 2/ x1 -- x2 arithmetic right shift -CODE 2/ -RRA TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA TOS + MOV @IP+,PC + ENDCODE + [THEN] \ -------------------- \ ARITHMETIC OPERATORS \ -------------------- -[UNDEFINED] UM* [IF] ; case of hardware_MPY + RST_SET -\ https://forth-standard.org/standard/core/UMTimes -\ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult. -CODE UM* + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + +\ $81EF DEVICEID @ U< +\ DEVICEID @ $81F3 U< +\ = [IF] ; MSP430FR413x subfamily without hardware_MPY + KERNEL_ADDON HMPY TSTBIT \ KERNEL_ADDON(BIT0) = hardware MPY flag + RST_RET + + [IF] +\ https://forth-standard.org/standard/core/MTimes +\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply + CODE UM* MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication BW1 MOV TOS,&OP2 \ Load 2nd operand MOV &RES0,0(PSP) \ low result on stack MOV &RES1,TOS \ high result in TOS MOV @IP+,PC -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/MTimes \ M* n1 n2 -- dlo dhi signed 16*16->32 multiply -CODE M* + CODE M* MOV @PSP,&MPYS \ Load 1st operand for signed multiplication GOTO BW1 -ENDCODE - -[ELSE] ; MSP430FRxxxx without hardware_MPY + ENDCODE -[UNDEFINED] M* [IF] - -\ https://forth-standard.org/standard/core/MTimes -\ M* n1 n2 -- dlo dhi signed 16*16->32 multiply -CODE M* -MOV @PSP,S \ S= n1 -CMP #0,S \ n1 > -1 ? -S< IF - XOR #-1,0(PSP) \ n1 --> u1 - ADD #1,0(PSP) \ -THEN -XOR TOS,S \ S contains sign of result -CMP #0,TOS \ n2 > -1 ? -S< IF - XOR #-1,TOS \ n2 --> u2 - ADD #1,TOS \ -THEN -PUSHM #2,IP \ UMSTAR use S,T,W,X,Y -LO2HI \ -- ud1 u2 -UM* -HI2LO -POPM #2,IP \ pop S,IP -CMP #0,S \ sign of result > -1 ? -S< IF - XOR #-1,0(PSP) \ ud --> d - XOR #-1,TOS - ADD #1,0(PSP) - ADDC #0,TOS -THEN -MOV @IP+,PC -ENDCODE -[THEN] + [ELSE] ; MSP430FRxxxx with hardware_MPY +\ https://forth-standard.org/standard/core/UMTimes +\ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult. + [UNDEFINED] M* [IF] + CODE M* + MOV @PSP,S \ S= n1 + CMP #0,S \ n1 > -1 ? + S< IF + XOR #-1,0(PSP) \ n1 --> u1 + ADD #1,0(PSP) \ + THEN + XOR TOS,S \ S contains sign of result + CMP #0,TOS \ n2 > -1 ? + S< IF + XOR #-1,TOS \ n2 --> u2 + ADD #1,TOS \ + THEN + PUSHM #2,IP \ UMSTAR use S,T,W,X,Y + LO2HI \ -- ud1 u2 + UM* + HI2LO + POPM #2,IP \ pop S,IP + CMP #0,S \ sign of result > -1 ? + S< IF + XOR #-1,0(PSP) \ ud --> d + XOR #-1,TOS + ADD #1,0(PSP) + ADDC #0,TOS + THEN + MOV @IP+,PC + ENDCODE + [THEN] + [THEN] ; endof hardware_MPY -[THEN] \ endof hardware MPY +\ HERE -[UNDEFINED] UM/MOD [IF] \ https://forth-standard.org/standard/core/UMDivMOD \ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16 -CODE UM/MOD + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD PUSH #DROP \ MOV #MUSMOD,PC \ execute MUSMOD then return to DROP -ENDCODE -[THEN] + ENDCODE + [THEN] + +\ HERE OVER - DUMP -[UNDEFINED] SM/REM [IF] -\ https://forth-standard.org/standard/core/SMDivREM -\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div -CODE SM/REM -MOV TOS,S \ S=DIV -MOV @PSP,T \ T=DVDhi -CMP #0,TOS \ n2 >= 0 ? -S< IF \ - XOR #-1,TOS - ADD #1,TOS \ -- d1 u2 -THEN -CMP #0,0(PSP) \ d1hi >= 0 ? -S< IF \ - XOR #-1,2(PSP) \ d1lo - XOR #-1,0(PSP) \ d1hi - ADD #1,2(PSP) \ d1lo+1 - ADDC #0,0(PSP) \ d1hi+C -THEN \ -- uDVDlo uDVDhi uDIVlo -PUSHM #3,IP \ save IP,S,T -LO2HI - UM/MOD \ -- uREMlo uQUOTlo -HI2LO -POPM #3,IP \ restore T,S,IP -CMP #0,T \ T=DVDhi --> REM_sign -S< IF - XOR #-1,0(PSP) - ADD #1,0(PSP) -THEN -XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign -CMP #0,T \ -- n3 u4 T=quot_sign -S< IF - XOR #-1,TOS - ADD #1,TOS -THEN \ -- n3 n4 S=divisor -MOV @IP+,PC -ENDCODE -[THEN] -[UNDEFINED] FM/MOD [IF] + KERNEL_ADDON @ 0< ; test the switch: FLOORED / SYMETRIC DIVISION + [IF] \ https://forth-standard.org/standard/core/FMDivMOD \ FM/MOD d1 n1 -- r q floored signed div'n -: FM/MOD -SM/REM -HI2LO \ -- remainder quotient S=divisor -CMP #0,0(PSP) \ remainder <> 0 ? -0<> IF - CMP #1,TOS \ quotient < 1 ? - S< IF - ADD S,0(PSP) \ add divisor to remainder - SUB #1,TOS \ decrement quotient - THEN -THEN -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] FM/MOD + [IF] + CODE FM/MOD + MOV TOS,S \ S=DIV + MOV @PSP,T \ T=DVDhi + CMP #0,TOS \ n2 >= 0 ? + S< IF \ + XOR #-1,TOS + ADD #1,TOS \ -- d1 u2 + THEN + CMP #0,0(PSP) \ d1hi >= 0 ? + S< IF \ + XOR #-1,2(PSP) \ d1lo + XOR #-1,0(PSP) \ d1hi + ADD #1,2(PSP) \ d1lo+1 + ADDC #0,0(PSP) \ d1hi+C + THEN \ -- uDVDlo uDVDhi uDIVlo + PUSHM #2,S \ 4 PUSHM S,T + CALL #MUSMOD + MOV @PSP+,TOS + POPM #2,S \ 4 POPM T,S + CMP #0,T \ T=DVDhi --> REM_sign + S< IF + XOR #-1,0(PSP) + ADD #1,0(PSP) + THEN + XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign + CMP #0,T \ -- n3 u4 T=quot_sign + S< IF + XOR #-1,TOS + ADD #1,TOS + THEN \ -- n3 n4 S=divisor + + CMP #0,0(PSP) \ remainder <> 0 ? + 0<> IF + CMP #1,TOS \ quotient < 1 ? + S< IF + ADD S,0(PSP) \ add divisor to remainder + SUB #1,TOS \ decrement quotient + THEN + THEN + MOV @IP+,PC + ENDCODE + [THEN] + [ELSE] +\ https://forth-standard.org/standard/core/SMDivREM +\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div + [UNDEFINED] SM/REM + [IF] + CODE SM/REM + MOV TOS,S \ S=DIV + MOV @PSP,T \ T=DVDhi + CMP #0,TOS \ n2 >= 0 ? + S< IF \ + XOR #-1,TOS + ADD #1,TOS \ -- d1 u2 + THEN + CMP #0,0(PSP) \ d1hi >= 0 ? + S< IF \ + XOR #-1,2(PSP) \ d1lo + XOR #-1,0(PSP) \ d1hi + ADD #1,2(PSP) \ d1lo+1 + ADDC #0,0(PSP) \ d1hi+C + THEN \ -- uDVDlo uDVDhi uDIVlo + PUSHM #2,S \ 4 PUSHM S,T + CALL #MUSMOD + MOV @PSP+,TOS + POPM #2,S \ 4 POPM T,S + CMP #0,T \ T=DVDhi --> REM_sign + S< IF + XOR #-1,0(PSP) + ADD #1,0(PSP) + THEN + XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign + CMP #0,T \ -- n3 u4 T=quot_sign + S< IF + XOR #-1,TOS + ADD #1,TOS + THEN \ -- n3 n4 S=divisor + MOV @IP+,PC + ENDCODE + [THEN] + [THEN] -[UNDEFINED] * [IF] \ https://forth-standard.org/standard/core/Times \ * n1 n2 -- n3 signed multiply -: * -M* DROP -; -[THEN] + [UNDEFINED] * + [IF] + : * + M* DROP + ; + [THEN] -[UNDEFINED] /MOD [IF] \ https://forth-standard.org/standard/core/DivMOD \ /MOD n1 n2 -- r3 q4 signed division -: /MOD ->R DUP 0< R> FM/MOD -; -[THEN] + [UNDEFINED] /MOD + [IF] + : /MOD + >R DUP 0< R> + [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + ; + [THEN] -[UNDEFINED] / [IF] \ https://forth-standard.org/standard/core/Div \ / n1 n2 -- n3 signed quotient -: / ->R DUP 0< R> FM/MOD NIP -; -[THEN] + [UNDEFINED] / + [IF] + : / + >R DUP 0< R> + [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + NIP + ; + [THEN] -[UNDEFINED] MOD [IF] \ https://forth-standard.org/standard/core/MOD \ MOD n1 n2 -- n3 signed remainder -: MOD ->R DUP 0< R> FM/MOD DROP -; -[THEN] + [UNDEFINED] MOD + [IF] + : MOD + >R DUP 0< R> + [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + DROP + ; + [THEN] -[UNDEFINED] */MOD [IF] \ https://forth-standard.org/standard/core/TimesDivMOD \ */MOD n1 n2 n3 -- r4 q5 signed mult/div -: */MOD ->R M* R> FM/MOD -; -[THEN] + [UNDEFINED] */MOD + [IF] + : */MOD + >R M* R> + [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + ; + [THEN] -[UNDEFINED] */ [IF] \ https://forth-standard.org/standard/core/TimesDiv \ */ n1 n2 n3 -- n4 n1*n2/q3 -: */ ->R M* R> FM/MOD NIP -; -[THEN] + [UNDEFINED] */ + [IF] + : */ + >R M* R> + [ KERNEL_ADDON @ 0< ] \ test the switch: FLOORED / SYMETRIC DIVISION + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + NIP + ; + [THEN] \ ------------------------------------------------------------------------------- \ STACK OPERATIONS \ ------------------------------------------------------------------------------- -[UNDEFINED] OVER [IF] -\ https://forth-standard.org/standard/core/OVER -\ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] \ https://forth-standard.org/standard/core/ROT \ ROT x1 x2 x3 -- x2 x3 x1 -CODE ROT -MOV @PSP,W \ 2 fetch x2 -MOV TOS,0(PSP) \ 3 store x3 -MOV 2(PSP),TOS \ 3 fetch x1 -MOV W,2(PSP) \ 3 store x2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R@ [IF] + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @PSP,W \ 2 fetch x2 + MOV TOS,0(PSP) \ 3 store x3 + MOV 2(PSP),TOS \ 3 fetch x1 + MOV W,2(PSP) \ 3 store x2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/RFetch \ R@ -- x R: x -- x fetch from return stack -CODE R@ -SUB #2,PSP -MOV TOS,0(PSP) -MOV @RSP,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] TUCK [IF] + [UNDEFINED] R@ + [IF] + CODE R@ + SUB #2,PSP + MOV TOS,0(PSP) + MOV @RSP,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TUCK \ TUCK ( x1 x2 -- x2 x1 x2 ) -: TUCK SWAP OVER ; -[THEN] + [UNDEFINED] TUCK + [IF] + : TUCK SWAP OVER ; + [THEN] \ ---------------------------------------------------------------------- \ DOUBLE OPERATORS \ ---------------------------------------------------------------------- -[UNDEFINED] 2@ [IF] \ https://forth-standard.org/standard/core/TwoFetch \ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack -CODE 2@ -BW1 SUB #2,PSP + [UNDEFINED] 2@ + [IF] + CODE 2@ + SUB #2,PSP MOV 2(TOS),0(PSP) MOV @TOS,TOS MOV @IP+,PC -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] 2! [IF] \ https://forth-standard.org/standard/core/TwoStore \ 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr -CODE 2! -BW2 MOV @PSP+,0(TOS) + [UNDEFINED] 2! + [IF] + CODE 2! + MOV @PSP+,0(TOS) MOV @PSP+,2(TOS) MOV @PSP+,TOS MOV @IP+,PC -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] 2DUP [IF] \ https://forth-standard.org/standard/core/TwoDUP \ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells -CODE 2DUP -MOV TOS,-2(PSP) \ 3 -MOV @PSP,-4(PSP) \ 4 -SUB #4,PSP \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 2DROP [IF] + [UNDEFINED] 2DUP + [IF] + CODE 2DUP + MOV TOS,-2(PSP) \ 3 + MOV @PSP,-4(PSP) \ 4 + SUB #4,PSP \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoDROP \ 2DROP x1 x2 -- drop 2 cells -CODE 2DROP -ADD #2,PSP -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2SWAP [IF] + [UNDEFINED] 2DROP + [IF] + CODE 2DROP + ADD #2,PSP + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoSWAP \ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2 -CODE 2SWAP -MOV @PSP,W \ -- x1 x2 x3 x4 W=x3 -MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4 -MOV W,4(PSP) \ -- x3 x2 x1 x4 -MOV TOS,W \ -- x3 x2 x1 x4 W=x4 -MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4 -MOV W,2(PSP) \ -- x3 x4 x1 x2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2OVER [IF] + [UNDEFINED] 2SWAP + [IF] + CODE 2SWAP + MOV @PSP,W \ -- x1 x2 x3 x4 W=x3 + MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4 + MOV W,4(PSP) \ -- x3 x2 x1 x4 + MOV TOS,W \ -- x3 x2 x1 x4 W=x4 + MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4 + MOV W,2(PSP) \ -- x3 x4 x1 x2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoOVER \ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2 -CODE 2OVER -SUB #4,PSP \ -- x1 x2 x3 x x x4 -MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4 -MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4 -MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2 -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2OVER + [IF] + CODE 2OVER + SUB #4,PSP \ -- x1 x2 x3 x x x4 + MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4 + MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4 + MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2 + MOV @IP+,PC + ENDCODE + [THEN] \ ---------------------------------------------------------------------- \ ALIGNMENT OPERATORS \ ---------------------------------------------------------------------- - -[UNDEFINED] ALIGNED [IF] \ https://forth-standard.org/standard/core/ALIGNED \ ALIGNED addr -- a-addr align given addr -CODE ALIGNED -BIT #1,TOS -ADDC #0,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ALIGN [IF] + [UNDEFINED] ALIGNED + [IF] + CODE ALIGNED + BIT #1,TOS + ADDC #0,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ALIGN \ ALIGN -- align HERE -CODE ALIGN -BIT #1,&DP \ 3 -ADDC #0,&DP \ 4 -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] ALIGN + [IF] + CODE ALIGN + BIT #1,&DP \ 3 + ADDC #0,&DP \ 4 + MOV @IP+,PC + ENDCODE + [THEN] \ --------------------- \ PORTABILITY OPERATORS \ --------------------- - -[UNDEFINED] CHARS [IF] \ https://forth-standard.org/standard/core/CHARS \ CHARS n1 -- n2 chars->adrs units -CODE CHARS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] CHARS + [IF] + CODE CHARS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CHAR+ [IF] \ https://forth-standard.org/standard/core/CHARPlus \ CHAR+ c-addr1 -- c-addr2 add char size -CODE CHAR+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] CHAR+ + [IF] + CODE CHAR+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CELLS [IF] \ https://forth-standard.org/standard/core/CELLS \ CELLS n1 -- n2 cells->adrs units -CODE CELLS -ADD TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] CELLS + [IF] + CODE CELLS + ADD TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CELL+ [IF] \ https://forth-standard.org/standard/core/CELLPlus \ CELL+ a-addr1 -- a-addr2 add cell size -CODE CELL+ -ADD #2,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] CELL+ + [IF] + CODE CELL+ + ADD #2,TOS + MOV @IP+,PC + ENDCODE + [THEN] \ --------------------------- \ BLOCK AND STRING COMPLEMENT \ --------------------------- - -[UNDEFINED] CHAR [IF] \ https://forth-standard.org/standard/core/CHAR \ CHAR -- char parse ASCII character -: CHAR + [UNDEFINED] CHAR + [IF] + : CHAR $20 WORD 1+ C@ -; -[THEN] + ; + [THEN] -[UNDEFINED] [CHAR] [IF] \ https://forth-standard.org/standard/core/BracketCHAR \ [CHAR] -- compile character literal -: [CHAR] + [UNDEFINED] [CHAR] + [IF] + : [CHAR] CHAR POSTPONE LITERAL -; IMMEDIATE -[THEN] + ; IMMEDIATE + [THEN] -[UNDEFINED] +! [IF] \ https://forth-standard.org/standard/core/PlusStore \ +! n/u a-addr -- add n/u to memory -CODE +! -ADD @PSP+,0(TOS) -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] + [UNDEFINED] +! + [IF] + CODE +! + ADD @PSP+,0(TOS) + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/MOVE \ MOVE addr1 addr2 u -- smart move \ VERSION FOR 1 ADDRESS UNIT = 1 CHAR -CODE MOVE -MOV TOS,W \ W = cnt -MOV @PSP+,Y \ Y = addr2 = dst -MOV @PSP+,X \ X = addr1 = src -MOV @PSP+,TOS \ pop new TOS -CMP #0,W \ count = 0 ? -0<> IF \ if 0, already done ! - CMP X,Y \ dst = src ? - 0<> IF \ else already done ! - U< IF \ U< if src > dst - BEGIN \ copy W bytes - MOV.B @X+,0(Y) - ADD #1,Y + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV TOS,W \ W = cnt + MOV @PSP+,Y \ Y = addr2 = dst + MOV @PSP+,X \ X = addr1 = src + MOV @PSP+,TOS \ pop new TOS + CMP #0,W \ count = 0 ? + 0<> IF \ if 0, already done ! + CMP X,Y \ dst = src ? + 0<> IF \ if 0, already done ! + U< IF \ U< if src > dst + BEGIN \ copy W bytes + MOV.B @X+,0(Y) + ADD #1,Y + SUB #1,W + 0= UNTIL + MOV @IP+,PC \ out 1 of MOVE ====> + THEN \ U>= if dst > src + ADD W,Y \ copy W bytes beginning with the end + ADD W,X + BEGIN + SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) SUB #1,W 0= UNTIL - MOV @IP+,PC \ out 1 of MOVE ====> - THEN \ U>= if dst > src - ADD W,Y \ copy W bytes beginning with the end - ADD W,X - BEGIN - SUB #1,X - SUB #1,Y - MOV.B @X,0(Y) - SUB #1,W - 0= UNTIL + THEN THEN -THEN -MOV @IP+,PC \ out 2 of MOVE ====> -ENDCODE -[THEN] + MOV @IP+,PC \ out 2 of MOVE ====> + ENDCODE + [THEN] - -[UNDEFINED] FILL [IF] \ https://forth-standard.org/standard/core/FILL \ FILL c-addr u char -- fill memory with char -CODE FILL -MOV @PSP+,X \ count -MOV @PSP+,W \ address -CMP #0,X -0<> IF - BEGIN - MOV.B TOS,0(W) \ store char in memory - ADD #1,W - SUB #1,X - 0= UNTIL -THEN -MOV @PSP+,TOS \ empties stack -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #HEREXEC,PC -ENDCODE -[THEN] + [UNDEFINED] FILL + [IF] + CODE FILL + MOV @PSP+,X \ count + MOV @PSP+,W \ address + CMP #0,X + 0<> IF + BEGIN + MOV.B TOS,0(W) \ store char in memory + ADD #1,W + SUB #1,X + 0= UNTIL + THEN + MOV @PSP+,TOS \ empties stack + MOV @IP+,PC + ENDCODE + [THEN] \ -------------------- \ INTERPRET COMPLEMENT \ -------------------- - -[UNDEFINED] HEX [IF] \ https://forth-standard.org/standard/core/HEX -CODE HEX -MOV #$10,&BASEADR -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DECIMAL [IF] -\ https://forth-standard.org/standard/core/DECIMAL -CODE DECIMAL -MOV #$0A,&BASEADR -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ( [IF] + [UNDEFINED] HEX + [IF] + CODE HEX + MOV #$10,&BASEADR + MOV @IP+,PC + ENDCODE + [THEN] + + \ https://forth-standard.org/standard/core/DECIMAL + [UNDEFINED] DECIMAL + [IF] + CODE DECIMAL + MOV #$0A,&BASEADR + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/p \ ( -- skip input until char ) or EOL -: ( -')' WORD DROP -; IMMEDIATE -[THEN] + [UNDEFINED] ( ; ) + [IF] + : ( + ')' WORD DROP + ; IMMEDIATE + [THEN] -[UNDEFINED] .( [IF] \ " \ https://forth-standard.org/standard/core/Dotp \ .( -- type comment immediatly. -CODE .( \ " -MOV #0,&CAPS \ CAPS OFF -COLON -')' WORD -COUNT TYPE -$20 CAPS ! \ CAPS ON -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] + [UNDEFINED] .( ; " + [IF] + CODE .( ; " + MOV #0,&CAPS \ CAPS OFF + COLON + ')' WORD + COUNT TYPE + HI2LO + MOV #$20,&CAPS \ CAPS ON + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/toBODY \ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] EXECUTE [IF] \ " \ https://forth-standard.org/standard/core/EXECUTE \ EXECUTE i*x xt -- j*x execute Forth word at 'xt' -CODE EXECUTE -PUSH TOS \ 3 push xt -MOV @PSP+,TOS \ 2 -MOV @RSP+,PC \ 4 xt --> PC -ENDCODE -[THEN] - -[UNDEFINED] EVALUATE [IF] + [UNDEFINED] EXECUTE + [IF] + CODE EXECUTE + PUSH TOS \ 3 push xt + MOV @PSP+,TOS \ 2 + MOV @RSP+,PC \ 4 xt --> PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/EVALUATE \ EVALUATE \ i*x c-addr u -- j*x interpret string -CODE EVALUATE -MOV #SOURCE_LEN,X \ 2 -MOV @X+,S \ 2 S = SOURCE_LEN -MOV @X+,T \ 2 T = SOURCE_ORG -MOV @X+,W \ 2 W = TOIN -PUSHM #4,IP \ 6 PUSHM IP,S,T,W -LO2HI -INTERPRET -HI2LO -MOV @RSP+,&TOIN \ 4 -MOV @RSP+,&SOURCE_ORG \ 4 -MOV @RSP+,&SOURCE_LEN \ 4 -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] RECURSE [IF] + [UNDEFINED] EVALUATE + [IF] + CODE EVALUATE + MOV #SOURCE_LEN,X \ 2 + MOV @X+,S \ 2 S = SOURCE_LEN + MOV @X+,T \ 2 T = SOURCE_ORG + MOV @X+,W \ 2 W = TOIN + PUSHM #4,IP \ 6 PUSHM IP,S,T,W + LO2HI + [ ' \ 8 + , ] \ compile INTERPRET + HI2LO + MOV @RSP+,&TOIN \ 4 + MOV @RSP+,&SOURCE_ORG \ 4 + MOV @RSP+,&SOURCE_LEN \ 4 + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/RECURSE \ C RECURSE -- recurse to current definition -CODE RECURSE -MOV &DP,X -MOV &LAST_CFA,0(X) -ADD #2,&DP -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] SOURCE [IF] + [UNDEFINED] RECURSE + [IF] + CODE RECURSE + MOV &DP,X + MOV &LAST_CFA,0(X) + ADD #2,&DP + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/SOURCE \ SOURCE -- adr u of current input buffer -CODE SOURCE -SUB #4,PSP -MOV TOS,2(PSP) -MOV &SOURCE_LEN,TOS -MOV &SOURCE_ORG,0(PSP) -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] -\ https://forth-standard.org/standard/core/DOES -\ DOES> -- set action for the latest CREATEd definition -CODE DOES> -MOV &LAST_CFA,W \ W = CFA of CREATEd word -MOV #$1285,0(W) \ replace CFA (CALL rDOCON) by new CFA (CALL rDODOES) -MOV IP,2(W) \ replace PFA by the address after DOES> as execution address -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] VARIABLE [IF] + [UNDEFINED] SOURCE + [IF] + CODE SOURCE + SUB #4,PSP + MOV TOS,2(PSP) + MOV &SOURCE_LEN,TOS + MOV &SOURCE_ORG,0(PSP) + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/VARIABLE \ VARIABLE <name> -- define a Forth VARIABLE -: VARIABLE -CREATE -HI2LO -MOV #$1287,-4(W) \ CFA = CALL rDOVAR -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] + [UNDEFINED] VARIABLE + [IF] + : VARIABLE + CREATE + HI2LO + MOV #DOVAR,-4(W) \ CFA = CALL rDOVAR + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/STATE \ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] + [UNDEFINED] STATE + [IF] + STATEADR CONSTANT STATE + [THEN] -[UNDEFINED] BASE [IF] \ https://forth-standard.org/standard/core/BASE \ BASE -- a-addr holds conversion radix -BASEADR CONSTANT BASE -[THEN] + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] -[UNDEFINED] >IN [IF] \ https://forth-standard.org/standard/core/toIN \ C >IN -- a-addr holds offset in input stream -TOIN CONSTANT >IN -[THEN] + [UNDEFINED] >IN + [IF] + TOIN CONSTANT >IN + [THEN] -[UNDEFINED] PAD [IF] \ https://forth-standard.org/standard/core/PAD \ PAD -- addr -PAD_ORG CONSTANT PAD -[THEN] + [UNDEFINED] PAD + [IF] + PAD_ORG CONSTANT PAD + [THEN] -[UNDEFINED] BL [IF] \ https://forth-standard.org/standard/core/BL \ BL -- char an ASCII space -'SP' CONSTANT BL -[THEN] + [UNDEFINED] BL + [IF] + 'SP' CONSTANT BL + [THEN] -[UNDEFINED] SPACE [IF] \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -'SP' EMIT ; -[THEN] + [UNDEFINED] SPACE + [IF] + : SPACE + 'SP' EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP + [UNDEFINED] SPACES + [IF] + : SPACES BEGIN - LO2HI + ?DUP + WHILE 'SP' EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL + 1- + REPEAT + ; + [THEN] + + [UNDEFINED] DEFER + [IF] +\ https://forth-standard.org/standard/core/DEFER +\ Skip leading space delimiters. Parse name delimited by a space. +\ Create a definition for name with the execution semantics defined below. +\ +\ name Execution: -- +\ Execute the xt that name is set to execute, i.e. NEXT (nothing), +\ until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name. + : DEFER + CREATE + HI2LO + MOV #$4030,-4(W) \4 first CELL = MOV @PC+,PC = BR #addr + MOV #NEXT_ADR,-2(W) \3 second CELL = ...mNEXT : do nothing by default MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ DEFER CR \ DEFERed definition, by default executes :NONAME part + CODE CR \ replaced by this CODE definition + MOV #NEXT_ADR,PC + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] -[UNDEFINED] TO [IF] \ https://forth-standard.org/standard/core/TO \ TO name Run-time: ( x -- ) \ Assign the value x to named VALUE. -CODE TO -BIS #UF9,SR -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] TO + [IF] + CODE TO + BIS #UF9,SR + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] VALUE [IF] \ https://forth-standard.org/standard/core/VALUE \ ( x "<spaces>name" -- ) define a Forth VALUE \ Skip leading space delimiters. Parse name delimited by a space. \ Create a definition for name with the execution semantics defined below, \ with an initial value equal to x. -\ +\ \ name Execution: ( -- x ) \ Place x on the stack. The value of x is that given when name was created, \ until the phrase x TO name is executed, causing a new value of x to be assigned to name. -\ -: VALUE \ x "<spaces>name" -- -CREATE , -DOES> -HI2LO -MOV @RSP+,IP -BIT #UF9,SR \ 2 see TO -0= IF \ 2 execute FETCH - MOV @TOS,TOS \ 2 - MOV @IP+,PC \ 4 -THEN -BIC #UF9,SR \ 2 clear 'TO' flag -MOV @PSP+,0(TOS) \ 4 execute STORE -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -RST_HERE - -[THEN] \ end of [UNDEFINED] {CORE_ANS} - -ECHO + [UNDEFINED] VALUE + [IF] + : VALUE \ x "<spaces>name" -- + CREATE , + DOES> + HI2LO + MOV @RSP+,IP + BIT #UF9,SR \ 2 see TO + 0= IF \ 2 if UF9 is not set + MOV @TOS,TOS \ 2 execute FETCH + MOV @IP+,PC \ 4 + THEN \ else + BIC #UF9,SR \ 2 clear UF9 flag + MOV #!,PC \ 4 execute STORE + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CASE + [UNDEFINED] CASE + [IF] + + : CASE 0 + ; IMMEDIATE \ -- #of-1 + +\ https://forth-standard.org/standard/core/OF + : OF \ #of-1 -- orgOF #of + 1+ \ count OFs + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE OVER POSTPONE = \ copy and test case value + POSTPONE IF \ add orig to control flow stack + POSTPONE DROP \ discards case value if = + R> \ we can bring count back now + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/ENDOF + : ENDOF \ orgOF #of -- orgENDOF #of + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE ELSE + R> \ we can bring count back now + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/ENDCASE + : ENDCASE \ orgENDOF1..orgENDOFn #of -- + POSTPONE DROP + 0 DO POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + RST_SET + + ECHO ; CORE_ANS.f is loaded + diff --git a/MSP430-FORTH/CopySourceFileToTarget_SD_Card.bat.lnk b/MSP430-FORTH/CopySourceFileToTarget_SD_Card.bat.lnk index 636c0bf689f544a36d92031802467a016153e00f..9e9e5326aa40034aae161e924f5dcd00d343e0ab 100644 GIT binary patch delta 409 zcmZqVT+2B@L~%9)2ZI6w1B1b9Hr2u%R~TV*!-J>sZEG(xZl7psP#<L#15|<zLKqCe zLUw-a_5uva`FUxX=?n~Z44e!s4Da{Z`Q5Yw$>;&qREdBTW`k8D2*yx;hGd3(hCGHe zhD-*aRt7PKNeo5|+Zh=cB77#-Dlj<v2Sf(@*O?gVIXQ+fFqFZKeg!o8l^w|Fez4Je z2vfnVhG{b<uV-?Pl>zcvffz(Hfn^{Bh#w8a_CU-G#2`a#fEc7ICMLjH*UQz>&(|}? zIVZm~CAcK9Br`uRrl2T4E48FJCbzi2#Mpo#YVs1sHepVNC<ZHr7-Wx3mSHh8xRYu7 tJzeFcU|07NrkzVyEIV|2mE_9IhaPheG(Er5QFb0(ezO+SXGRu~3jhHQVa5Oe delta 366 zcmZ3>*~mFTM6sKJgF%6Tfx*b_)#1pQR~TXRE}qKQH9M{_uAgXXQ14_F15|<zLKqCe zLUn#tz5)!%`FUxX=?n~Z44e!s4Da_%^{tu&lF<XI2^0V+6a}kB5EGvAGbS_SGvqO( zF=R3TwK9k?Okyx%SkDMF#jn^)fx+27ATrp$&csm9$uWe1p$y4rkntd+<Ap#5a)1aV z;HGkB@?S<*cLoL-plB`-gJ>os6(GJd5UT?*GZ2dau?i4_RK>&uIO}@3I{Nu~#-wMK zFgQ)#!`QZY8`EdT$ze<eCa)i)O}QWTQm|`HLHAkJ1uGBTUM0CQ^P$Jw15MBGbd;S( Imj@XN0IfAydH?_b diff --git a/MSP430-FORTH/DOUBLE.f b/MSP430-FORTH/DOUBLE.f index d565105..a7bf3d9 100644 --- a/MSP430-FORTH/DOUBLE.f +++ b/MSP430-FORTH/DOUBLE.f @@ -28,1240 +28,1393 @@ \ ASSEMBLER conditionnal usage with ?GOTO S< S>= U< U>= 0= 0<> 0< \ -CODE ABORT_DOUBLE -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #BIT9,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (DOUBLE input), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" build FastForth with DOUBLE_INPUT addon !" -PWR_STATE \ if no abort remove this word -; + CODE ABORT_DOUBLE + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #BIT7,TOS + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (DOUBLE input), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with DOUBLE_INPUT addon !" + RST_RET \ if no abort remove this word + ; -ABORT_DOUBLE + ABORT_DOUBLE ; ----------------------------------------------------- ; DOUBLE.f ; ----------------------------------------------------- -[DEFINED] {DOUBLE} [IF] {DOUBLE} [THEN] - -MARKER {DOUBLE} + MARKER {DOUBLE} -[UNDEFINED] >R [IF] \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] @ [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Zeroless +\ 0< n -- flag true if TOS negative + [UNDEFINED] 0< + [IF] + CODE 0< + ADD TOS,TOS \ 1 set carry if TOS negative + SUBC TOS,TOS \ 1 TOS=-1 if carry was clear + XOR #-1,TOS \ 1 TOS=-1 if carry was set + MOV @IP+,PC \ + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/DROP +\ DROP x -- drop top of stack + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/DUP +\ DUP x -- x x duplicate top of stack + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,PSP \ 2 push old TOS.. + MOV TOS,0(PSP) \ 3 ..onto stack + MOV @IP+,PC \ 4 + ENDCODE + +\ https://forth-standard.org/standard/core/qDUP +\ ?DUP x -- 0 | x x DUP if nonzero + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/NIP +\ NIP x1 x2 -- x2 Drop the first item below the top of stack + [UNDEFINED] NIP + [IF] + CODE NIP + ADD #2,PSP + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/UMDivMOD +\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16 + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD + PUSH #DROP \ + MOV #MUSMOD,PC \ execute MUSMOD then return to DROP + ENDCODE + [THEN] + + KERNEL_ADDON @ 0< ; test the switch: FLOORED / SYMETRIC DIVISION + [IF] ; FLOORED DIVISION +\ https://forth-standard.org/standard/core/FMDivMOD +\ FM/MOD d1 n1 -- r q floored signed div'n + [UNDEFINED] FM/MOD + [IF] + CODE FM/MOD + MOV TOS,S \ S=DIV + MOV @PSP,T \ T=DVDhi + CMP #0,TOS \ n2 >= 0 ? + S< IF \ + XOR #-1,TOS + ADD #1,TOS \ -- d1 u2 + THEN + CMP #0,0(PSP) \ d1hi >= 0 ? + S< IF \ + XOR #-1,2(PSP) \ d1lo + XOR #-1,0(PSP) \ d1hi + ADD #1,2(PSP) \ d1lo+1 + ADDC #0,0(PSP) \ d1hi+C + THEN \ -- uDVDlo uDVDhi uDIVlo + PUSHM #3,IP \ save IP,S,T + LO2HI + UM/MOD \ -- uREMlo uQUOTlo + HI2LO + POPM #3,IP \ restore T,S,IP + CMP #0,T \ T=DVDhi --> REM_sign + S< IF + XOR #-1,0(PSP) + ADD #1,0(PSP) + THEN + XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign + CMP #0,T \ -- n3 u4 T=quot_sign + S< IF + XOR #-1,TOS + ADD #1,TOS + THEN \ -- n3 n4 S=divisor + + CMP #0,0(PSP) \ remainder <> 0 ? + 0<> IF + CMP #1,TOS \ quotient < 1 ? + S< IF + ADD S,0(PSP) \ add divisor to remainder + SUB #1,TOS \ decrement quotient + THEN + THEN + MOV @IP+,PC + ENDCODE + [THEN] + + [ELSE] ; SYMETRIC DIVISION +\ https://forth-standard.org/standard/core/SMDivREM +\ SM/REM DVDlo DVDhi DIV -- r3 q4 symmetric signed div + [UNDEFINED] SM/REM + [IF] + CODE SM/REM + MOV TOS,S \ S=DIV + MOV @PSP,T \ T=DVDhi + CMP #0,TOS \ n2 >= 0 ? + S< IF \ + XOR #-1,TOS + ADD #1,TOS \ -- d1 u2 + THEN + CMP #0,0(PSP) \ d1hi >= 0 ? + S< IF \ + XOR #-1,2(PSP) \ d1lo + XOR #-1,0(PSP) \ d1hi + ADD #1,2(PSP) \ d1lo+1 + ADDC #0,0(PSP) \ d1hi+C + THEN \ -- uDVDlo uDVDhi uDIVlo + PUSHM #3,IP \ save IP,S,T + LO2HI + UM/MOD \ -- uREMlo uQUOTlo + HI2LO + POPM #3,IP \ restore T,S,IP + CMP #0,T \ T=DVDhi --> REM_sign + S< IF + XOR #-1,0(PSP) + ADD #1,0(PSP) + THEN + XOR S,T \ S=DIV XOR T=DVDhi = Quot_sign + CMP #0,T \ -- n3 u4 T=quot_sign + S< IF + XOR #-1,TOS + ADD #1,TOS + THEN \ -- n3 n4 S=divisor + MOV @IP+,PC + ENDCODE + [THEN] + [THEN] + +\ https://forth-standard.org/standard/core/Div +\ / n1 n2 -- n3 signed quotient + [UNDEFINED] / + [IF] + : / + >R DUP 0< R> + [ KERNEL_ADDON @ 0< ] [IF] + FM/MOD + [ELSE] + SM/REM + [THEN] + NIP + ; + [THEN] + \ https://forth-standard.org/standard/core/Fetch \ @ c-addr -- char fetch char from memory -CODE @ -MOV @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] @ + [IF] + CODE @ + MOV @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] ! [IF] \ https://forth-standard.org/standard/core/Store \ ! x a-addr -- store cell in memory -CODE ! -MOV @PSP+,0(TOS) \ 4 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] + [UNDEFINED] ! + [IF] + CODE ! + MOV @PSP+,0(TOS) \ 4 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SWAP [IF] \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ROT \ ROT x1 x2 x3 -- x2 x3 x1 -CODE ROT -MOV @PSP,W \ 2 fetch x2 -MOV TOS,0(PSP) \ 3 store x3 -MOV 2(PSP),TOS \ 3 fetch x1 -MOV W,2(PSP) \ 3 store x2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] - [IF] + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @PSP,W \ 2 fetch x2 + MOV TOS,0(PSP) \ 3 store x3 + MOV 2(PSP),TOS \ 3 fetch x1 + MOV W,2(PSP) \ 3 store x2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] < [IF] \ define < and > + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/less \ < n1 n2 -- flag test n1<n2, signed -CODE < - SUB @PSP+,TOS \ 1 TOS=n2-n1 - S< ?GOTO FW1 \ 2 signed - 0<> IF \ 2 -BW1 MOV #-1,TOS \ 1 flag Z = 0 - THEN - MOV @IP+,PC -ENDCODE + [UNDEFINED] < + [IF] \ define < and > + CODE < + SUB @PSP+,TOS \ 1 TOS=n2-n1 + S< ?GOTO FW1 \ 2 signed + 0<> IF \ 2 +BW1 MOV #-1,TOS \ 1 flag Z = 0 + THEN + MOV @IP+,PC + ENDCODE \ https://forth-standard.org/standard/core/more \ > n1 n2 -- flag test n1>n2, signed -CODE > - SUB @PSP+,TOS \ 2 TOS=n2-n1 - S< ?GOTO BW1 \ 2 --> +5 -FW1 AND #0,TOS \ 1 flag Z = 1 - MOV @IP+,PC -ENDCODE -[THEN] + CODE > + SUB @PSP+,TOS \ 2 TOS=n2-n1 + S< ?GOTO BW1 \ 2 --> +5 +FW1 AND #0,TOS \ 1 flag Z = 1 + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] IF [IF] \ define IF THEN \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF THEN + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] TO [IF] + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/TO -CODE TO -BIS #UF9,SR -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] TO + [IF] + CODE TO + BIS #UF9,SR + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] DOES> [IF] \ https://forth-standard.org/standard/core/DOES \ DOES> -- set action for the latest CREATEd definition -CODE DOES> -MOV &LAST_CFA,W \ W = CFA of CREATEd word -MOV #DODOES,0(W) \ replace CFA (DOCON) by new CFA (DODOES) -MOV IP,2(W) \ replace PFA by the address after DOES> as execution address -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] SPACES [IF] + [UNDEFINED] DOES> + [IF] + CODE DOES> + MOV &LAST_CFA,W \ W = CFA of CREATEd word + MOV #DODOES,0(W) \ replace CFA (CALL rDOCON) by new CFA (CALL rDODOES) + MOV IP,2(W) \ replace PFA by the address after DOES> as execution address + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] 2@ [IF] \ https://forth-standard.org/standard/core/TwoFetch \ 2@ a-addr -- x1 x2 fetch 2 cells ; the lower address will appear on top of stack -CODE 2@ -SUB #2,PSP -MOV 2(TOS),0(PSP) -MOV @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2! [IF] + [UNDEFINED] 2@ + [IF] + CODE 2@ + SUB #2,PSP + MOV 2(TOS),0(PSP) + MOV @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoStore \ 2! x1 x2 a-addr -- store 2 cells ; the top of stack is stored at the lower adr -CODE 2! -MOV @PSP+,0(TOS) -MOV @PSP+,2(TOS) -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2DUP [IF] + [UNDEFINED] 2! + [IF] + CODE 2! + MOV @PSP+,0(TOS) + MOV @PSP+,2(TOS) + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoDUP \ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells -CODE 2DUP -SUB #4,PSP \ -- x1 x x x2 -MOV TOS,2(PSP) \ -- x1 x2 x x2 -MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x2 -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2DROP [IF] + [UNDEFINED] 2DUP + [IF] + CODE 2DUP + SUB #4,PSP \ -- x1 x x x2 + MOV TOS,2(PSP) \ -- x1 x2 x x2 + MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x2 + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoDROP \ 2DROP x1 x2 -- drop 2 cells -CODE 2DROP -ADD #2,PSP -MOV @PSP+,TOS -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2SWAP [IF] + [UNDEFINED] 2DROP + [IF] + CODE 2DROP + ADD #2,PSP + MOV @PSP+,TOS + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoSWAP \ 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2 -CODE 2SWAP -MOV @PSP,W \ -- x1 x2 x3 x4 W=x3 -MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4 -MOV W,4(PSP) \ -- x3 x2 x1 x4 -MOV TOS,W \ -- x3 x2 x1 x4 W=x4 -MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4 -MOV W,2(PSP) \ -- x3 x4 x1 x2 -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2OVER [IF] + [UNDEFINED] 2SWAP + [IF] + CODE 2SWAP + MOV @PSP,W \ -- x1 x2 x3 x4 W=x3 + MOV 4(PSP),0(PSP) \ -- x1 x2 x1 x4 + MOV W,4(PSP) \ -- x3 x2 x1 x4 + MOV TOS,W \ -- x3 x2 x1 x4 W=x4 + MOV 2(PSP),TOS \ -- x3 x2 x1 x2 W=x4 + MOV W,2(PSP) \ -- x3 x4 x1 x2 + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoOVER \ 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1 x2 -CODE 2OVER -SUB #4,PSP \ -- x1 x2 x3 x x x4 -MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4 -MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4 -MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2 -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2>R [IF] + [UNDEFINED] 2OVER + [IF] + CODE 2OVER + SUB #4,PSP \ -- x1 x2 x3 x x x4 + MOV TOS,2(PSP) \ -- x1 x2 x3 x4 x x4 + MOV 8(PSP),0(PSP) \ -- x1 x2 x3 x4 x1 x4 + MOV 6(PSP),TOS \ -- x1 x2 x3 x4 x1 x2 + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwotoR \ ( x1 x2 -- ) ( R: -- x1 x2 ) Transfer cell pair x1 x2 to the return stack. -CODE 2>R -PUSH @PSP+ -PUSH TOS -MOV @PSP+,TOS -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2R@ [IF] + [UNDEFINED] 2>R + [IF] + CODE 2>R + PUSH @PSP+ + PUSH TOS + MOV @PSP+,TOS + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoRFetch \ ( -- x1 x2 ) ( R: x1 x2 -- x1 x2 ) Copy cell pair x1 x2 from the return stack. -CODE 2R@ -SUB #4,PSP -MOV TOS,2(PSP) -MOV @RSP,TOS -MOV 2(RSP),0(PSP) -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2R> [IF] + [UNDEFINED] 2R@ + [IF] + CODE 2R@ + SUB #4,PSP + MOV TOS,2(PSP) + MOV @RSP,TOS + MOV 2(RSP),0(PSP) + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoRfrom \ ( -- x1 x2 ) ( R: x1 x2 -- ) Transfer cell pair x1 x2 from the return stack -CODE 2R> -SUB #4,PSP -MOV TOS,2(PSP) -MOV @RSP+,TOS -MOV @RSP+,0(PSP) -NEXT -ENDCODE -[THEN] + [UNDEFINED] 2R> + [IF] + CODE 2R> + SUB #4,PSP + MOV TOS,2(PSP) + MOV @RSP+,TOS + MOV @RSP+,0(PSP) + NEXT + ENDCODE + [THEN] \ =============================================== \ DOUBLE word set \ =============================================== -[UNDEFINED] D. [IF] \ https://forth-standard.org/standard/double/Dd \ D. dlo dhi -- display d (signed) -CODE D. -MOV #U.,W \ U. + 10 = D. -ADD #10,W -MOV W,PC -ENDCODE -[THEN] - -[UNDEFINED] 2ROT [IF] + [UNDEFINED] D. + [IF] + CODE D. + MOV TOS,S \ S will be pushed as sign + MOV #U.+10,PC \ U. + 10 = D. + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/TwoROT \ Rotate the top three cell pairs on the stack bringing cell pair x1 x2 to the top of the stack. -CODE 2ROT -MOV 8(PSP),X \ 3 -MOV 6(PSP),Y \ 3 -MOV 4(PSP),8(PSP) \ 5 -MOV 2(PSP),6(PSP) \ 5 -MOV @PSP,4(PSP) \ 4 -MOV TOS,2(PSP) \ 3 -MOV X,0(PSP) \ 3 -MOV Y,TOS \ 1 -NEXT -ENDCODE -[THEN] - -[UNDEFINED] D>S [IF] + [UNDEFINED] 2ROT + [IF] + CODE 2ROT + MOV 8(PSP),X \ 3 + MOV 6(PSP),Y \ 3 + MOV 4(PSP),8(PSP) \ 5 + MOV 2(PSP),6(PSP) \ 5 + MOV @PSP,4(PSP) \ 4 + MOV TOS,2(PSP) \ 3 + MOV X,0(PSP) \ 3 + MOV Y,TOS \ 1 + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/DtoS \ D>S d -- n double prec -> single. -CODE D>S -MOV @PSP+,TOS -NEXT -ENDCODE -[THEN] + [UNDEFINED] D>S + [IF] + CODE D>S + MOV @PSP+,TOS + NEXT + ENDCODE + [THEN] -[UNDEFINED] D0= [IF] \ https://forth-standard.org/standard/double/DZeroEqual -CODE D0= -CMP #0,TOS -MOV #0,TOS -0= IF - CMP #0,0(PSP) + [UNDEFINED] D0= + [IF] + CODE D0= + CMP #0,TOS + MOV #0,TOS 0= IF - MOV #-1,TOS + CMP #0,0(PSP) + 0= IF + MOV #-1,TOS + THEN THEN -THEN -ADD #2,PSP -NEXT -ENDCODE -[THEN] + ADD #2,PSP + NEXT + ENDCODE + [THEN] -[UNDEFINED] D0< [IF] \ https://forth-standard.org/standard/double/DZeroless -CODE D0< -CMP #0,TOS -MOV #0,TOS -S< IF - MOV #-1,TOS -THEN -ADD #2,PSP -NEXT -ENDCODE -[THEN] + [UNDEFINED] D0< + [IF] + CODE D0< + CMP #0,TOS + MOV #0,TOS + S< IF + MOV #-1,TOS + THEN + ADD #2,PSP + AND #-1,TOS \ to set N, Z flags + NEXT + ENDCODE + [THEN] -[UNDEFINED] D= [IF] \ https://forth-standard.org/standard/double/DEqual -CODE D= -CMP TOS,2(PSP) \ 3 ud1H - ud2H -MOV #0,TOS \ 1 -0= IF \ 2 - CMP @PSP,4(PSP) \ 4 ud1L - ud2L - 0= IF \ 2 - MOV #-1,TOS \ 1 + [UNDEFINED] D= + [IF] + CODE D= + CMP TOS,2(PSP) \ 3 ud1H - ud2H + MOV #0,TOS \ 1 + 0= IF \ 2 + CMP @PSP,4(PSP) \ 4 ud1L - ud2L + 0= IF \ 2 + MOV #-1,TOS \ 1 + THEN THEN -THEN -ADD #6,PSP \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + ADD #6,PSP \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] D< [IF] \ https://forth-standard.org/standard/double/Dless \ flag is true if and only if d1 is less than d2 -CODE D< -CMP TOS,2(PSP) \ 3 d1H - d2H -MOV #0,TOS \ 1 -S< IF \ 2 - MOV #-1,TOS \ 1 -THEN -0= IF \ 2 - CMP @PSP,4(PSP) \ 4 d1L - d2L - U< IF \ 2 - MOV #-1,TOS \ 1 + [UNDEFINED] D< + [IF] + CODE D< + CMP TOS,2(PSP) \ 3 d1H - d2H + MOV #0,TOS \ 1 + S< IF \ 2 + MOV #-1,TOS \ 1 + THEN + 0= IF \ 2 + CMP @PSP,4(PSP) \ 4 d1L - d2L + U< IF \ 2 + MOV #-1,TOS \ 1 + THEN THEN -THEN -ADD #6,PSP \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + ADD #6,PSP \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] DU< [IF] \ https://forth-standard.org/standard/double/DUless \ flag is true if and only if ud1 is less than ud2 -CODE DU< -CMP TOS,2(PSP) \ 3 ud1H - ud2H -MOV #0,TOS \ 1 -U< IF \ 2 - MOV #-1,TOS \ 1 -THEN -0= IF \ 2 - CMP @PSP,4(PSP) \ 4 ud1L - ud2L - U< IF \ 2 - MOV #-1,TOS \ 1 + [UNDEFINED] DU< + [IF] + CODE DU< + CMP TOS,2(PSP) \ 3 ud1H - ud2H + MOV #0,TOS \ 1 + U< IF \ 2 + MOV #-1,TOS \ 1 + THEN + 0= IF \ 2 + CMP @PSP,4(PSP) \ 4 ud1L - ud2L + U< IF \ 2 + MOV #-1,TOS \ 1 + THEN THEN -THEN -ADD #6,PSP \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + ADD #6,PSP \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] D+ [IF] \ https://forth-standard.org/standard/double/DPlus -CODE D+ + [UNDEFINED] D+ + [IF] + CODE D+ BW1 ADD @PSP+,2(PSP) ADDC @PSP+,TOS -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE -[UNDEFINED] M+ [IF] \ https://forth-standard.org/standard/double/MPlus -CODE M+ -SUB #2,PSP -CMP #0,TOS -MOV TOS,0(PSP) -MOV #-1,TOS -0>= IF - MOV #0,TOS -THEN -GOTO BW1 -ENDCODE -[THEN] + CODE M+ + SUB #2,PSP + CMP #0,TOS + MOV TOS,0(PSP) + MOV #-1,TOS + 0>= IF + MOV #0,TOS + THEN + GOTO BW1 + ENDCODE + [THEN] -[UNDEFINED] D- [IF] \ https://forth-standard.org/standard/double/DMinus -CODE D- -SUB @PSP+,2(PSP) -SUBC TOS,0(PSP) -MOV @PSP+,TOS -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DNEGATE [IF] + [UNDEFINED] D- + [IF] + CODE D- + SUB @PSP+,2(PSP) + SUBC TOS,0(PSP) + MOV @PSP+,TOS + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/DNEGATE -CODE DNEGATE -XOR #-1,0(PSP) -XOR #-1,TOS -ADD #1,0(PSP) -ADDC #0,TOS -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] + [UNDEFINED] DNEGATE + [IF] + CODE DNEGATE + XOR #-1,0(PSP) + XOR #-1,TOS + ADD #1,0(PSP) + ADDC #0,TOS + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/DABS \ DABS d1 -- |d1| absolute value -CODE DABS -CMP #0,TOS \ 1 -0>= IF - MOV @IP+,PC -THEN -MOV #DNEGATE,PC -ENDCODE -[THEN] + [UNDEFINED] DABS + [IF] + CODE DABS + CMP #0,TOS \ 1 + 0>= IF + MOV @IP+,PC + THEN + MOV #DNEGATE,PC + ENDCODE + [THEN] -[UNDEFINED] D2/ [IF] \ https://forth-standard.org/standard/double/DTwoDiv -CODE D2/ -RRA TOS -RRC 0(PSP) -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] D2* [IF] + [UNDEFINED] D2/ + [IF] + CODE D2/ + RRA TOS + RRC 0(PSP) + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/DTwoTimes -CODE D2* -ADD @PSP,0(PSP) -ADDC TOS,TOS -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DMAX [IF] + [UNDEFINED] D2* + [IF] + CODE D2* + ADD @PSP,0(PSP) + ADDC TOS,TOS + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/DMAX -: DMAX \ -- d1 d2 -2OVER 2OVER \ -- d1 d2 d1 d2 -D< IF \ -- d1 d2 - 2>R 2DROP 2R> \ -- d2 -ELSE \ -- d1 d2 - 2DROP \ -- d1 -THEN -; -[THEN] + [UNDEFINED] DMAX + [IF] + : DMAX \ -- d1 d2 + 2OVER 2OVER \ -- d1 d2 d1 d2 + D< IF \ -- d1 d2 + 2>R 2DROP 2R> \ -- d2 + ELSE \ -- d1 d2 + 2DROP \ -- d1 + THEN + ; + [THEN] -[UNDEFINED] DMIN [IF] \ https://forth-standard.org/standard/double/DMIN -: DMIN \ -- d1 d2 -2OVER 2OVER \ -- d1 d2 d1 d2 -D< IF \ -- d1 d2 - 2DROP \ -- d1 -ELSE 2>R 2DROP 2R> \ -- d1 d2 -THEN \ -- d2 -; - -DEVICEID C@ $EF > [IF] ; test for MSP430FR413x devices without hardware_MPY + [UNDEFINED] DMIN + [IF] + : DMIN \ -- d1 d2 + 2OVER 2OVER \ -- d1 d2 d1 d2 + D< IF \ -- d1 d2 + 2DROP \ -- d1 + ELSE + 2>R 2DROP 2R> \ -- d1 d2 + THEN \ -- d2 + ; + [THEN] + + RST_SET +\ \ https://forth-standard.org/standard/core/Equal +\ \ = x1 x2 -- flag test x1=x2 +\ [UNDEFINED] = +\ [IF] +\ CODE = +\ SUB @PSP+,TOS \ 2 +\ 0<> IF \ 2 +\ AND #0,TOS \ 1 +\ MOV @IP+,PC \ 4 +\ THEN +\ XOR #-1,TOS \ 1 flag Z = 1 +\ MOV @IP+,PC \ 4 +\ ENDCODE +\ [THEN] +\ +\ \ https://forth-standard.org/standard/core/Uless +\ \ U< u1 u2 -- flag test u1<u2, unsigned +\ [UNDEFINED] U< +\ [IF] +\ CODE U< +\ SUB @PSP+,TOS \ 2 u2-u1 +\ 0<> IF +\ MOV #-1,TOS \ 1 +\ U< IF \ 2 flag +\ AND #0,TOS \ 1 flag Z = 1 +\ THEN +\ THEN +\ MOV @IP+,PC \ 4 +\ ENDCODE +\ [THEN] +\ +\ $81EF DEVICEID @ U< +\ DEVICEID @ $81F3 U< +\ = -[UNDEFINED] M*/ [IF] -\ https://forth-standard.org/standard/double/MTimesDiv -CODE M*/ \ d1lo d1hi n1 +n2 -- d2lo d2hi -BIC #UF9,SR \ clear RES sign flag -CMP #0,2(PSP) \ d1 < 0 ? -S< IF - XOR #-1,4(PSP) - XOR #-1,2(PSP) - ADD #1,4(PSP) - ADDC #0,2(PSP) - BIS #UF9,SR \ set RES sign flag -THEN \ ud1 -CMP #0,0(PSP) \ n1 < 0 ? -S< IF - XOR #-1,0(PSP) - ADD #1,0(PSP) \ u1 - XOR #UF9,SR -THEN \ let's process UM* -- ud1lo ud1hi u1 +n2 - MOV 4(PSP),Y \ 3 uMDlo - MOV 2(PSP),T \ 3 uMDhi - MOV @PSP+,S \ 2 uMRlo -- ud1lo ud1hi +n2 - MOV #0,rDODOES \ 1 uMDlo=0 - MOV #0,2(PSP) \ 3 uRESlo=0 - MOV #0,0(PSP) \ 3 uRESmi=0 -- uRESlo uRESmi +n2 - MOV #0,W \ 1 uREShi=0 - MOV #1,X \ 1 BIT TEST REGlo -BEGIN BIT X,S \ 1 test actual bit in uMRlo - 0<> IF ADD Y,2(PSP) \ 3 IF 1: ADD uMDlo TO uRESlo - ADDC T,0(PSP) \ 3 ADDC uMDmi TO uRESmi - ADDC rDODOES,W \ 1 ADDC uMRlo TO uREShi - THEN ADD Y,Y \ 1 (RLA LSBs) uMDlo *2 - ADDC T,T \ 1 (RLC MSBs) uMDhi *2 - ADDC rDODOES,rDODOES \ 1 (RLA LSBs) uMDlo *2 - ADD X,X \ 1 (RLA) NEXT BIT TO TEST -U>= UNTIL \ 1 IF BIT IN CARRY: FINISHED W=uREShi -\ TOS +n2 -\ W REShi -\ 0(PSP) RESmi -\ 2(PSP) RESlo -MOV TOS,T -MOV @PSP,TOS -MOV 2(PSP),S -\ process division -\ reg input output -\ ---------------------------- -\ S = DVD(15-0) -\ TOS = DVD(31-16) -\ W = DVD(47-32) REM -\ T = DIV(15-0) -\ X = Don't care QUOTlo -\ Y = Don't care QUOThi -\ rDODOES = count -\ 2(PSP) REM -\ 0(PSP) QUOTlo -\ TOS QUOThi -MOV #32,rDODOES \ 2 init loop count -CMP #0,W \ DVDhi = 0 ? -0= IF \ if yes - MOV TOS,W \ DVDmi --> DVDhi - CALL #MDIV1DIV2 \ with loop count / 2 -ELSE - CALL #MDIV1 \ -- urem ud2lo ud2hi -THEN -MOV @PSP+,0(PSP) \ -- ud2lo ud2hi -BIT #UF9,SR \ sign is set ? -0<> IF \ DNEGATE Quot - XOR #-1,0(PSP) - XOR #-1,TOS - ADD #1,0(PSP) - ADDC #0,TOS - BIC #UF9,SR \ clear sign flag -\ now, make floored division, only used if rem<>0 and quot<0 : - CMP #0,W \ remainder <> 0 ? - 0<> IF - SUB #1,0(PSP) \ decrement quotient - SUBC #0,TOS + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + + KERNEL_ADDON HMPY TSTBIT \ hardware MPY ? + + RST_RET + + [IF] ; MSP430FRxxxx with hardware_MPY + +\ https://forth-standard.org/standard/double/MTimesDiv + [UNDEFINED] M*/ + [IF] + CODE M*/ \ d1 * n1 / +n2 -- d2 + MOV 4(PSP),&MPYS32L \ 5 Load 1st operand d1lo + MOV 2(PSP),&MPYS32H \ 5 d1hi + MOV @PSP+,&OP2 \ 4 -- d1 n2 load 2nd operand n1 + MOV TOS,T \ T = DIV + NOP3 + MOV &RES0,S \ 3 S = RESlo + MOV &RES1,TOS \ 3 TOS = RESmi + MOV &RES2,W \ 3 W = REShi + MOV #0,rDOCON \ clear sign flag + CMP #0,W \ negative product ? + S< IF \ compute ABS value if yes + XOR #-1,S + XOR #-1,TOS + XOR #-1,W + ADD #1,S + ADDC #0,TOS + ADDC #0,W + MOV #-1,rDOCON \ set sign flag THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[ELSE] \ hardware multiplier -[UNDEFINED] M*/ [IF] + [ELSE] ; no hardware multiplier \ https://forth-standard.org/standard/double/MTimesDiv -CODE M*/ \ d1 * n1 / +n2 -- d2 -MOV 4(PSP),&MPYS32L \ 5 Load 1st operand d1lo -MOV 2(PSP),&MPYS32H \ 5 d1hi -MOV @PSP+,&OP2 \ 4 -- d1 n2 load 2nd operand n1 -MOV TOS,T \ T = DIV -NOP3 -MOV &RES0,S \ 3 S = RESlo -MOV &RES1,TOS \ 3 TOS = RESmi -MOV &RES2,W \ 3 W = REShi -BIC #UF9,SR \ clear sign flag -CMP #0,W \ negative product ? -S< IF \ compute ABS value if yes - XOR #-1,S - XOR #-1,TOS - XOR #-1,W - ADD #1,S - ADDC #0,TOS - ADDC #0,W - BIS #UF9,SR \ set sign flag -THEN -\ process division -\ reg input output -\ ---------------------------- -\ S = DVD(15-0) -\ TOS = DVD(31-16) -\ W = DVD(47-32) REM -\ T = DIV(15-0) -\ X = Don't care QUOTlo -\ Y = Don't care QUOThi -\ rDODOES = count -\ 2(PSP) REM -\ 0(PSP) QUOTlo -\ TOS QUOThi -MOV #32,rDODOES \ 2 init loop count -CMP #0,W \ DVDhi = 0 ? -0= IF \ if yes - MOV TOS,W \ DVDmi --> DVDhi - CALL #MDIV1DIV2 \ with loop count / 2 -ELSE - CALL #MDIV1 \ -- urem ud2lo ud2hi -THEN -MOV @PSP+,0(PSP) \ -- d2lo d2hi -BIT #UF9,SR \ RES sign is set ? -0<> IF \ DNEGATE - XOR #-1,0(PSP) - XOR #-1,TOS - ADD #1,0(PSP) - ADDC #0,TOS - BIC #UF9,SR \ clear sign flag -\ now, make floored division, only used if rem<>0 and quot<0 : - CMP #0,W \ remainder <> 0 ? - 0<> IF - SUB #1,0(PSP) \ decrement quotient - SUBC #0,TOS + [UNDEFINED] M*/ + [IF] + CODE M*/ \ d1lo d1hi n1 +n2 -- d2lo d2hi + MOV #0,rDOCON \ rDOCON = sign + CMP #0,2(PSP) \ d1 < 0 ? + S< IF + XOR #-1,4(PSP) + XOR #-1,2(PSP) + ADD #1,4(PSP) + ADDC #0,2(PSP) + MOV #-1,rDOCON + THEN \ ud1 + CMP #0,0(PSP) \ n1 < 0 ? + S< IF + XOR #-1,0(PSP) + ADD #1,0(PSP) \ u1 + XOR #-1,rDOCON + THEN \ let's process UM* -- ud1lo ud1hi u1 +n2 + MOV 4(PSP),Y \ 3 uMDlo + MOV 2(PSP),T \ 3 uMDhi + MOV @PSP+,S \ 2 uMRlo -- ud1lo ud1hi +n2 + MOV #0,rDODOES \ 1 uMDlo=0 + MOV #0,2(PSP) \ 3 uRESlo=0 + MOV #0,0(PSP) \ 3 uRESmi=0 -- uRESlo uRESmi +n2 + MOV #0,W \ 1 uREShi=0 + MOV #1,X \ 1 BIT TEST REGlo + BEGIN BIT X,S \ 1 test actual bit in uMRlo + 0<> IF ADD Y,2(PSP) \ 3 IF 1: ADD uMDlo TO uRESlo + ADDC T,0(PSP) \ 3 ADDC uMDmi TO uRESmi + ADDC rDODOES,W \ 1 ADDC uMRlo TO uREShi + THEN ADD Y,Y \ 1 (RLA LSBs) uMDlo *2 + ADDC T,T \ 1 (RLC MSBs) uMDhi *2 + ADDC rDODOES,rDODOES \ 1 (RLA LSBs) uMDlo *2 + ADD X,X \ 1 (RLA) NEXT BIT TO TEST + U>= UNTIL \ 1 IF BIT IN CARRY: FINISHED W=uREShi +\ TOS +n2 +\ W REShi +\ 0(PSP) RESmi +\ 2(PSP) RESlo + MOV TOS,T + MOV @PSP,TOS + MOV 2(PSP),S + [THEN] + + [THEN] ; endcase of software/hardware_MPY + +\ process division +\ reg input output +\ ------------------------------ +\ S = DVD(15-0) +\ TOS = DVD(31-16) +\ W = DVD(47-32) REM +\ T = DIV(15-0) +\ X = Don't care QUOTlo +\ Y = Don't care QUOThi +\ rDODOES = count +\ rDOCON = sign +\ 2(PSP) REM +\ 0(PSP) QUOTlo +\ TOS QUOThi + MOV #32,rDODOES \ 2 init loop count + CMP #0,W \ DVDhi = 0 ? + 0= IF \ if yes + MOV TOS,W \ DVDmi --> DVDhi + CALL #MDIV1DIV2 \ with loop count / 2 + ELSE + CALL #MDIV1 \ -- urem ud2lo ud2hi THEN -THEN -MOV @IP+,PC \ 52 words -ENDCODE -[THEN] - -[THEN] ; end of software/hardware_MPY + MOV @PSP+,0(PSP) \ -- d2lo d2hi + CMP #0,rDOCON \ RES sign is set ? + 0<> IF \ DNEGATE quot + XOR #-1,0(PSP) + XOR #-1,TOS + ADD #1,0(PSP) + ADDC #0,TOS + CMP #0,&KERNEL_ADDON \ floored/symetric division flag test + S< IF \ if floored division and quot<0 + CMP #0,W \ remainder <> 0 ? + 0<> IF \ if floored division, quot<0 and remainder <>0 + SUB #1,0(PSP) \ decrement quotient + SUBC #0,TOS + THEN + THEN + THEN + MOV #XDODOES,rDODOES + MOV #XDOCON,rDOCON + MOV @IP+,PC \ 52 words + ENDCODE + [THEN] -[UNDEFINED] 2VARIABLE [IF] \ https://forth-standard.org/standard/double/TwoVARIABLE -: 2VARIABLE \ -- -CREATE -HI2LO -ADD #4,&DP -MOV @RSP+,IP -NEXT -ENDCODE -[THEN] - -[UNDEFINED] 2CONSTANT [IF] + [UNDEFINED] 2VARIABLE + [IF] + : 2VARIABLE \ -- + CREATE + HI2LO + ADD #4,&DP + MOV @RSP+,IP + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/TwoCONSTANT -: 2CONSTANT \ udlo/dlo/Flo udhi/dhi/Shi -- to create double or s15q16 CONSTANT -CREATE -, , \ compile Shi then Flo -DOES> -2@ \ execution part -; -[THEN] + [UNDEFINED] 2CONSTANT + [IF] + : 2CONSTANT \ udlo/dlo/Flo udhi/dhi/Shi -- to create double or s15q16 CONSTANT + CREATE + , , \ compile Shi then Flo + DOES> + 2@ \ execution part + ; + [THEN] -[UNDEFINED] 2VALUE [IF] \ https://forth-standard.org/standard/double/TwoVALUE -: 2VALUE \ x1 x2 "<spaces>name" -- -CREATE , , \ compile Shi then Flo -DOES> -HI2LO -MOV @RSP+,IP -BIT #UF9,SR \ flag set by TO -0= IF - MOV #2@,PC \ execute TwoFetch -THEN -BIC #UF9,SR \ clear flag -MOV #2!,PC \ execute TwoStore -ENDCODE -[THEN] - -[UNDEFINED] 2LITERAL [IF] + [UNDEFINED] 2VALUE + [IF] + : 2VALUE \ x1 x2 "<spaces>name" -- + CREATE , , \ compile Shi then Flo + DOES> + HI2LO + MOV @RSP+,IP + BIT #UF9,SR \ flag set by TO + 0= IF + MOV #2@,PC \ execute TwoFetch + THEN + BIC #UF9,SR \ clear flag + MOV #2!,PC \ execute TwoStore + ENDCODE + [THEN] + + \ https://forth-standard.org/standard/double/TwoLITERAL -CODE 2LITERAL -BIS #UF9,SR \ see LITERAL -MOV #LITERAL,PC -ENDCODE IMMEDIATE -[THEN] + [UNDEFINED] 2LITERAL + [IF] + CODE 2LITERAL + BIS #UF9,SR \ see LITERAL + MOV #LITERAL,PC + ENDCODE IMMEDIATE + [THEN] + -[UNDEFINED] D.R [IF] \ https://forth-standard.org/standard/double/DDotR \ D.R d n -- -: D.R ->R SWAP OVER DABS <# #S ROT SIGN #> -R> OVER - SPACES TYPE -; -[THEN] + [UNDEFINED] D.R + [IF] + : D.R + >R SWAP OVER DABS <# #S ROT SIGN #> + R> OVER - SPACES TYPE + ; + [THEN] -RST_HERE + RST_SET \ ============================================================================== -\ Complement to pass DOUBLETEST.4TH +; Complement to pass DOUBLE TESTS \ ============================================================================== -\ -[UNDEFINED] VARIABLE [IF] + \ https://forth-standard.org/standard/core/VARIABLE -: VARIABLE \ -- -CREATE -HI2LO -MOV @RSP+,IP -ADD #2,&DP -NEXT -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] +\ VARIABLE <name> -- define a Forth VARIABLE + [UNDEFINED] VARIABLE + [IF] + : VARIABLE + CREATE + HI2LO + MOV #DOVAR,-4(W) \ CFA = CALL rDOVAR + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] CELLS [IF] +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CELLS \ CELLS n1 -- n2 cells->adrs units -CODE CELLS -ADD TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] ALLOT [IF] -\ https://forth-standard.org/standard/core/ALLOT -\ ALLOT n -- allocate n bytes -CODE ALLOT -ADD TOS,&DP -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] + [UNDEFINED] CELLS + [IF] + CODE CELLS + ADD TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DEPTH \ DEPTH -- +n number of items on stack, must leave 0 if stack empty -CODE DEPTH -MOV TOS,-2(PSP) -MOV #PSTACK,TOS -SUB PSP,TOS \ PSP-S0--> TOS -RRA TOS \ TOS/2 --> TOS -SUB #2,PSP \ post decrement stack... -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -\ https://forth-standard.org/standard/core/DUP -\ DUP x -- x x duplicate top of stack -CODE DUP -BW1 SUB #2,PSP \ 2 push old TOS.. - MOV TOS,0(PSP) \ 3 ..onto stack - MOV @IP+,PC \ 4 -ENDCODE + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV TOS,-2(PSP) + MOV #PSTACK,TOS + SUB PSP,TOS \ PSP-S0--> TOS + RRA TOS \ TOS/2 --> TOS + SUB #2,PSP \ post decrement stack... + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP -\ https://forth-standard.org/standard/core/qDUP -\ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0, init + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W MOV X,-4(W) \ xloop --> HERE MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP \ immediate -MOV #XPLOOP,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] + [IF] + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] = [IF] \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ZeroEqual \ 0= n/u -- flag return true if TOS=0 -CODE 0= -SUB #1,TOS \ borrow (clear cy) if TOS was 0 -SUBC TOS,TOS \ TOS=-1 if borrow was set -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] SOURCE [IF] + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,TOS \ borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SOURCE \ SOURCE -- adr u of current input buffer -CODE SOURCE -SUB #4,PSP -MOV TOS,2(PSP) -MOV &SOURCE_LEN,TOS -MOV &SOURCE_ORG,0(PSP) -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >IN [IF] + [UNDEFINED] SOURCE + [IF] + CODE SOURCE + SUB #4,PSP + MOV TOS,2(PSP) + MOV &SOURCE_LEN,TOS + MOV &SOURCE_ORG,0(PSP) + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toIN \ C >IN -- a-addr holds offset in input stream -TOIN CONSTANT >IN -[THEN] + [UNDEFINED] >IN + [IF] + TOIN CONSTANT >IN + [THEN] -[UNDEFINED] SWAP [IF] -\ https://forth-standard.org/standard/core/SWAP -\ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -\ https://forth-standard.org/standard/core/DROP -\ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CHAR [IF] \ https://forth-standard.org/standard/core/CHAR \ CHAR -- char parse ASCII character -: CHAR - $20 WORD 1+ C@ -; -[THEN] + [UNDEFINED] CHAR + [IF] + : CHAR + $20 WORD 1+ C@ + ; + [THEN] -[UNDEFINED] [CHAR] [IF] \ https://forth-standard.org/standard/core/BracketCHAR \ [CHAR] -- compile character literal -: [CHAR] - CHAR POSTPONE LITERAL -; IMMEDIATE -[THEN] + [UNDEFINED] [CHAR] + [IF] + : [CHAR] + CHAR POSTPONE LITERAL + ; IMMEDIATE + [THEN] -[UNDEFINED] 2/ [IF] \ https://forth-standard.org/standard/core/TwoDiv \ 2/ x1 -- x2 arithmetic right shift -CODE 2/ -RRA TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] INVERT [IF] \ https://forth-standard.org/standard/core/INVERT \ INVERT x1 -- x2 bitwise inversion -CODE INVERT -XOR #-1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] INVERT + [IF] + CODE INVERT + XOR #-1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] RSHIFT [IF] \ https://forth-standard.org/standard/core/RSHIFT \ RSHIFT x1 u -- x2 logical R7 shift u places -CODE RSHIFT - MOV @PSP+,W - AND #$1F,TOS \ no need to shift more than 16 -0<> IF - BEGIN BIC #C,SR \ Clr Carry + [UNDEFINED] RSHIFT + [IF] + CODE RSHIFT + MOV @PSP+,W + AND #$1F,TOS \ no need to shift more than 16 + 0<> IF + BEGIN + BIC #C,SR \ Clr Carry RRC W SUB #1,TOS - 0= UNTIL -THEN MOV W,TOS - MOV @IP+,PC -ENDCODE -[THEN] + 0= UNTIL + THEN + MOV W,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] 0< [IF] -\ https://forth-standard.org/standard/core/Zeroless -\ 0< n -- flag true if TOS negative -CODE 0< -ADD TOS,TOS \ 1 set carry if TOS negative -SUBC TOS,TOS \ 1 TOS=-1 if carry was clear -XOR #-1,TOS \ 1 TOS=-1 if carry was set -MOV @IP+,PC \ -ENDCODE -[THEN] - -[UNDEFINED] S>D [IF] \ https://forth-standard.org/standard/core/StoD \ S>D n -- d single -> double prec. -: S>D - DUP 0< -; -[THEN] + [UNDEFINED] S>D + [IF] + : S>D + DUP 0< + ; + [THEN] -[UNDEFINED] 1- [IF] \ https://forth-standard.org/standard/core/OneMinus \ 1- n1/u1 -- n2/u2 subtract 1 from TOS -CODE 1- -SUB #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -\ https://forth-standard.org/standard/core/UMDivMOD -\ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16 -CODE UM/MOD - PUSH #DROP \ - MOV #MUSMOD,PC \ execute MUSMOD then return to DROP -ENDCODE -[THEN] + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SM/REM [IF] -\ https://forth-standard.org/standard/core/SMDivREM -\ SM/REM DVDlo DVDhi DIVlo -- r3 q4 symmetric signed div -CODE SM/REM -MOV TOS,S \ S=DIVlo -MOV @PSP,T \ T=DVD_sign==>rem_sign -CMP #0,TOS \ n2 >= 0 ? -S< IF \ - XOR #-1,TOS - ADD #1,TOS \ -- d1 u2 -THEN -CMP #0,0(PSP) \ d1hi >= 0 ? -S< IF \ - XOR #-1,2(PSP) \ d1lo - XOR #-1,0(PSP) \ d1hi - ADD #1,2(PSP) \ d1lo+1 - ADDC #0,0(PSP) \ d1hi+C -THEN \ -- uDVDlo uDVDhi uDIVlo -PUSHM #3,IP \ save IP,S,T -LO2HI - UM/MOD \ -- uREMlo uQUOTlo -HI2LO -POPM #3,IP \ restore T,S,IP -CMP #0,T \ T=rem_sign -S< IF - XOR #-1,0(PSP) - ADD #1,0(PSP) -THEN -XOR S,T \ S=divisor T=quot_sign -CMP #0,T \ -- n3 u4 T=quot_sign -S< IF +\ https://forth-standard.org/standard/core/NEGATE +\ C NEGATE x1 -- x2 two's complement + [UNDEFINED] NEGATE + [IF] + CODE NEGATE XOR #-1,TOS ADD #1,TOS -THEN \ -- n3 n4 S=divisor -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] FM/MOD [IF] -\ https://forth-standard.org/standard/core/FMDivMOD -\ FM/MOD d1 n1 -- r q floored signed div'n -: FM/MOD -SM/REM -HI2LO \ -- remainder quotient S=divisor -CMP #0,0(PSP) \ remainder <> 0 ? -0<> IF - CMP #1,TOS \ quotient < 1 ? - S< IF - ADD S,0(PSP) \ add divisor to remainder - SUB #1,TOS \ decrement quotient - THEN -THEN -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] NIP [IF] -\ https://forth-standard.org/standard/core/NIP -\ NIP x1 x2 -- x2 Drop the first item below the top of stack -CODE NIP -ADD #2,PSP -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #HEREXEC,PC + ENDCODE + [THEN] -[UNDEFINED] / [IF] -\ https://forth-standard.org/standard/core/Div -\ / n1 n2 -- n3 signed quotient -: / ->R DUP 0< R> FM/MOD NIP -; -[THEN] - -[UNDEFINED] NEGATE [IF] -\ https://forth-standard.org/standard/core/NEGATE -\ C NEGATE x1 -- x2 two's complement -CODE NEGATE -XOR #-1,TOS -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #HEREXEC,PC -ENDCODE -[THEN] - -[UNDEFINED] CHARS [IF] \ https://forth-standard.org/standard/core/CHARS \ CHARS n1 -- n2 chars->adrs units -CODE CHARS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] CHARS + [IF] + CODE CHARS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] MOVE [IF] \ https://forth-standard.org/standard/core/MOVE \ MOVE addr1 addr2 u -- smart move \ VERSION FOR 1 ADDRESS UNIT = 1 CHAR -CODE MOVE -MOV TOS,W \ W = cnt -MOV @PSP+,Y \ Y = addr2 = dst -MOV @PSP+,X \ X = addr1 = src -MOV @PSP+,TOS \ pop new TOS -CMP #0,W \ count = 0 ? -0<> IF \ if 0, already done ! - CMP X,Y \ Y-X \ dst - src - 0<> IF \ else already done ! - U< IF \ U< if src > dst - BEGIN \ copy W bytes - MOV.B @X+,0(Y) - ADD #1,Y + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV TOS,W \ W = cnt + MOV @PSP+,Y \ Y = addr2 = dst + MOV @PSP+,X \ X = addr1 = src + MOV @PSP+,TOS \ pop new TOS + CMP #0,W \ count = 0 ? + 0<> IF \ if 0, already done ! + CMP X,Y \ Y-X \ dst - src + 0<> IF \ else already done ! + U< IF \ U< if src > dst + BEGIN \ copy W bytes + MOV.B @X+,0(Y) + ADD #1,Y + SUB #1,W + 0= UNTIL + MOV @IP+,PC \ out 1 of MOVE ====> + THEN \ U>= if dst > src + ADD W,Y \ copy W bytes beginning with the end + ADD W,X + BEGIN + SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) SUB #1,W 0= UNTIL - MOV @IP+,PC \ out 1 of MOVE ====> - THEN \ U>= if dst > src - ADD W,Y \ copy W bytes beginning with the end - ADD W,X - BEGIN - SUB #1,X - SUB #1,Y - MOV.B @X,0(Y) - SUB #1,W - 0= UNTIL + THEN THEN -THEN -MOV @IP+,PC \ out 2 of MOVE ====> -ENDCODE -[THEN] + MOV @IP+,PC \ out 2 of MOVE ====> + ENDCODE + [THEN] -[UNDEFINED] DECIMAL [IF] \ https://forth-standard.org/standard/core/DECIMAL -CODE DECIMAL -MOV #$0A,&BASEADR -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] DECIMAL + [IF] + CODE DECIMAL + MOV #$0A,&BASEADR + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] BASE [IF] \ https://forth-standard.org/standard/core/BASE \ BASE -- a-addr holds conversion radix -BASEADR CONSTANT BASE -[THEN] + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] -[UNDEFINED] ( [IF] \ https://forth-standard.org/standard/core/p \ ( -- skip input until char ) or EOL -: ( -')' WORD DROP -; IMMEDIATE -[THEN] + [UNDEFINED] ( ; ) + [IF] + : ( + ')' WORD DROP + ; IMMEDIATE + [THEN] -[UNDEFINED] .( [IF] \ " \ https://forth-standard.org/standard/core/Dotp \ .( -- type comment immediatly. -CODE .( \ " -MOV #0,&CAPS \ CAPS OFF -COLON -')' WORD -COUNT TYPE -$20 CAPS ! \ CAPS ON -; IMMEDIATE -[THEN] - + [UNDEFINED] .( ; " + [IF] + CODE .( ; " + MOV #0,&CAPS \ CAPS OFF + COLON + ')' WORD + COUNT TYPE + $20 CAPS ! \ CAPS ON + ; IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + DEFER CR \ DEFERed definition, by default executes that of :NONAME + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] \ ============================================================================== \ TESTER \ ============================================================================== - +\ \ From: John Hayes S1I \ Subject: tester.fr \ Date: Mon, 27 Nov 95 13:10:09 PST - +\ \ (C) 1995 JOHNS HOPKINS UNIVERSITY / APPLIED PHYSICS LABORATORY \ MAY BE DISTRIBUTED FREELY AS LONG AS THIS COPYRIGHT NOTICE REMAINS. \ VERSION 1.1 - +\ \ 22/1/09 The words { and } have been changed to T{ and }T respectively to \ agree with the Forth 200X file ttester.fs. This avoids clashes with \ locals using { ... } and the FSL use of } - +\ \ 13/05/14 jmt. added colorised error messages. 0 CONSTANT FALSE @@ -1272,14 +1425,14 @@ $20 CAPS ! \ CAPS ON VARIABLE VERBOSE FALSE VERBOSE ! \ TRUE VERBOSE ! - +\ \ : EMPTY-STACK ( ... -- ) \ EMPTY STACK: HANDLES UNDERFLOWED STACK TOO. \ DEPTH ?DUP \ IF DUP 0< IF NEGATE 0 \ DO 0 LOOP \ ELSE 0 DO DROP LOOP THEN \ THEN ; -\ +\ \ : ERROR \ ( C-ADDR U -- ) DISPLAY AN ERROR MESSAGE FOLLOWED BY \ \ THE LINE THAT HAD THE ERROR. \ TYPE SOURCE TYPE CR \ DISPLAY LINE CORRESPONDING TO ERROR @@ -1320,6 +1473,22 @@ CREATE ACTUAL-RESULTS 20 CELLS ALLOT ELSE >IN ! DROP [CHAR] * EMIT THEN ; +\ Constant definitions + +DECIMAL + +0 INVERT CONSTANT 1SD +1SD 1 RSHIFT CONSTANT MAX-INTD \ 01...1 +MAX-INTD INVERT CONSTANT MIN-INTD \ 10...0 +MAX-INTD 2/ CONSTANT HI-INT \ 001...1 +MIN-INTD 2/ CONSTANT LO-INT \ 110...1 + +\ 1SD . +\ MAX-INTD . +\ MIN-INTD . +\ HI-INT . +\ LO-INT . + ECHO \ ============================================================================== @@ -1337,7 +1506,7 @@ ECHO \ but WITHOUT ANY WARRANTY; without even the implied warranty of \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. \ -\ The tests are not claimed to be comprehensive or correct +\ The tests are not claimed to be comprehensive or correct \ ------------------------------------------------------------------------------ \ Version 0.13 Assumptions and dependencies changed \ 0.12 1 August 2015 test D< acts on MS cells of double word @@ -1367,23 +1536,6 @@ ECHO \ included prior to this file \ - the Core word set is available and tested \ ------------------------------------------------------------------------------ -\ Constant definitions - -DECIMAL - -0 INVERT CONSTANT 1SD -1SD 1 RSHIFT CONSTANT MAX-INTD \ 01...1 -MAX-INTD INVERT CONSTANT MIN-INTD \ 10...0 -MAX-INTD 2/ CONSTANT HI-INT \ 001...1 -MIN-INTD 2/ CONSTANT LO-INT \ 110...1 - -\ 1SD . -\ MAX-INTD . -\ MIN-INTD . -\ HI-INT . -\ LO-INT . - -\ ------------------------------------------------------------------------------ TESTING interpreter and compiler reading double numbers, with/without prefixes T{ 1. -> 1 0 }T @@ -1571,7 +1723,7 @@ T{ MAX-2INT -1. D< -> FALSE }T T{ MAX-2INT MIN-2INT D< -> FALSE }T T{ MAX-2INT 2DUP -1. D+ D< -> FALSE }T T{ MIN-2INT 2DUP 1. D+ D< -> TRUE }T -T{ MAX-INTD S>D 2DUP 1. D+ D< -> TRUE }T \ Ensure D< acts on MS cells +T{ MAX-INTD S>D 2DUP 1. D+ D< -> TRUE }T \ Ensure D< acts on MS cells T{ -1. -1. D= -> TRUE }T T{ -1. 0. D= -> FALSE }T diff --git a/MSP430-FORTH/FF_SPECS.f b/MSP430-FORTH/FF_SPECS.f index 01ed51d..aef700e 100644 --- a/MSP430-FORTH/FF_SPECS.f +++ b/MSP430-FORTH/FF_SPECS.f @@ -25,209 +25,208 @@ ; FF_SPECS.f ; --------------------------------- -\ first, we test for downloading driver only if good FastForth version -CODE ABORT_FF_SPECS -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_FF_SPECS definition before resuming -; - -ABORT_FF_SPECS - -[UNDEFINED] AND [IF] -\ https://forth-standard.org/standard/core/AND -\ C AND x1 x2 -- x3 logical AND -CODE AND -AND @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] \ define DUP and DUP? +\ first, we do some tests allowing the download + CODE ABORT_FF_SPECS + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS \ ARG + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_FF_SPECS definition before resuming + ; + + ABORT_FF_SPECS + \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP + [IF] \ define DUP and DUP? + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DROP \ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] SWAP [IF] \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/ROT \ ROT x1 x2 x3 -- x2 x3 x1 -CODE ROT -MOV @PSP,W \ 2 fetch x2 -MOV TOS,0(PSP) \ 3 store x3 -MOV 2(PSP),TOS \ 3 fetch x1 -MOV W,2(PSP) \ 3 store x2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @PSP,W \ 2 fetch x2 + MOV TOS,0(PSP) \ 3 store x3 + MOV 2(PSP),TOS \ 3 fetch x1 + MOV W,2(PSP) \ 3 store x2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -\ https://forth-standard.org/standard/core/ZeroEqual -\ 0= n/u -- flag return true if TOS=0 -CODE 0= -SUB #1,TOS \ borrow (clear cy) if TOS was 0 -SUBC TOS,TOS \ TOS=-1 if borrow was set -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Zeroless \ 0< n -- flag true if TOS negative -CODE 0< -ADD TOS,TOS \ 1 set carry if TOS negative -SUBC TOS,TOS \ 1 TOS=-1 if carry was clear -XOR #-1,TOS \ 1 TOS=-1 if carry was set -MOV @IP+,PC \ -ENDCODE -[THEN] - -[UNDEFINED] = [IF] + [UNDEFINED] 0< + [IF] + CODE 0< + ADD TOS,TOS \ 1 set carry if TOS negative + SUBC TOS,TOS \ 1 TOS=-1 if carry was clear + XOR #-1,TOS \ 1 TOS=-1 if carry was set + MOV @IP+,PC \ + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 flag Z = 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] \ https://forth-standard.org/standard/core/Uless \ U< u1 u2 -- flag test u1<u2, unsigned -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 + [UNDEFINED] U< + [IF] + CODE U< + SUB @PSP+,TOS \ 2 u2-u1 + U< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,TOS \ 1 THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE + +\ https://forth-standard.org/standard/core/Umore +\ U> n1 n2 -- flag + CODE U> + SUB @PSP+,TOS \ 2 + U< ?GOTO BW1 \ 2 flag = true, Z = 0 +FW1 AND #0,TOS \ 1 Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] IF [IF] \ define IF and THEN \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF and THEN + CODE IF + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/BEGIN \ BEGIN -- BEGINadr initialize backward branch -CODE BEGIN + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + CODE BEGIN MOV #HEREXEC,PC -ENDCODE IMMEDIATE -[THEN] + ENDCODE IMMEDIATE -[UNDEFINED] UNTIL [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT \ https://forth-standard.org/standard/core/UNTIL \ UNTIL BEGINadr -- resolve conditional backward branch -CODE UNTIL + CODE UNTIL \ immediate MOV #QFBRAN,X BW1 ADD #4,&DP \ compile two words MOV &DP,W \ W = HERE @@ -235,329 +234,423 @@ BW1 ADD #4,&DP \ compile two words MOV TOS,-2(W) \ compile bakcward adr at HERE+2 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/AGAIN \ AGAIN BEGINadr -- resolve uncondionnal backward branch -CODE AGAIN -MOV #BRAN,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] + CODE AGAIN + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] WHILE [IF] \ define DO LOOP +LOOP + [UNDEFINED] WHILE + [IF] \ \ https://forth-standard.org/standard/core/WHILE \ WHILE BEGINadr -- WHILEadr BEGINadr -: WHILE -POSTPONE IF SWAP -; IMMEDIATE -[THEN] + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + [THEN] -[UNDEFINED] REPEAT [IF] \ define DO LOOP +LOOP + [UNDEFINED] REPEAT + [IF] \ https://forth-standard.org/standard/core/REPEAT \ REPEAT WHILEadr BEGINadr -- resolve WHILE loop -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W - MOV X,-4(W) \ xloop --> HERE - MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 \ goto BW1 LOOP -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #HEREXEC,PC -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #HEREXEC,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - 'SP' EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + 'SP' EMIT + HI2LO + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2* [IF] + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/TwoTimes \ 2* x1 -- x2 arithmetic left shift -CODE 2* -ADD TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2* + [IF] + CODE 2* + ADD TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/TwoDiv +\ 2/ x1 -- x2 arithmetic right shift + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] UM/MOD [IF] \ https://forth-standard.org/standard/core/UMDivMOD \ UM/MOD udlo|udhi u1 -- r q unsigned 32/16->r16 q16 -CODE UM/MOD + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD PUSH #DROP \ MOV #MUSMOD,PC \ execute MUSMOD then return to DROP -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] MOVE [IF] \ https://forth-standard.org/standard/core/MOVE \ MOVE addr1 addr2 u -- smart move \ VERSION FOR 1 ADDRESS UNIT = 1 CHAR -CODE MOVE -MOV TOS,W \ W = cnt -MOV @PSP+,Y \ Y = addr2 = dst -MOV @PSP+,X \ X = addr1 = src -MOV @PSP+,TOS \ pop new TOS -CMP #0,W \ count = 0 ? -0<> IF \ if 0, already done ! - CMP X,Y \ Y-X \ dst - src - 0<> IF \ if dst = src, already done ! - U< IF \ U< if src > dst - BEGIN \ copy W bytes - MOV.B @X+,0(Y) - ADD #1,Y + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV TOS,W \ W = cnt + MOV @PSP+,Y \ Y = addr2 = dst + MOV @PSP+,X \ X = addr1 = src + MOV @PSP+,TOS \ pop new TOS + CMP #0,W \ count = 0 ? + 0<> IF \ if 0, already done ! + CMP X,Y \ Y-X \ dst - src + 0<> IF \ if dst = src, already done ! + U< IF \ U< if src > dst + BEGIN \ copy W bytes + MOV.B @X+,0(Y) + ADD #1,Y + SUB #1,W + 0= UNTIL + MOV @IP+,PC + THEN \ U>= if dst > src + ADD W,Y \ copy W bytes beginning with the end + ADD W,X + BEGIN + SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) SUB #1,W 0= UNTIL - MOV @IP+,PC - THEN \ U>= if dst > src - ADD W,Y \ copy W bytes beginning with the end - ADD W,X - BEGIN - SUB #1,X - SUB #1,Y - MOV.B @X,0(Y) - SUB #1,W - 0= UNTIL + THEN THEN -THEN -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] WORDS [IF] -\ https://forth-standard.org/standard/tools/WORDS -\ list all words of vocabulary first in CONTEXT. -: WORDS \ -- -CR -CONTEXT @ PAD_ORG \ -- VOC_BODY PAD MOVE all threads of VOC_BODY in PAD_ORG -THREADS @ 2* \ -- VOC_BODY PAD THREADS*2 -MOVE \ -- vocabulary entries are copied in PAD_ORG -BEGIN \ -- - 0 DUP \ -- ptr=0 MAX=0 - THREADS @ 2* 0 \ -- ptr=0 MAX=0 THREADS*2 0 - DO \ -- ptr MAX I = PAD_ptr = thread*2 - DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx - U< IF \ -- ptr MAX if MAX U< NFAx - DROP DROP \ -- drop ptr and MAX - I DUP PAD_ORG + @ \ -- new_ptr new_MAX - THEN \ - 2 +LOOP \ -- ptr MAX - ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD = 0) -WHILE \ -- ptr MAX replace it by its LFA - DUP \ -- ptr MAX MAX - 2 - @ \ -- ptr MAX [LFA] - ROT \ -- MAX [LFA] ptr - PAD_ORG + \ -- MAX [LFA] thread - ! \ -- MAX [LFA]=new_NFA updates PAD+ptr - DUP \ -- MAX MAX - COUNT $7F AND \ -- MAX addr count (with suppr. of immediate bit) - TYPE \ -- MAX - C@ $0F AND \ -- count_of_chars - $10 SWAP - SPACES \ -- complete with spaces modulo 16 chars -REPEAT \ -- -DROP \ ptr -- -; \ all threads in PAD are filled with 0 -[THEN] - -[UNDEFINED] CASE [IF] + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME \ part II : :NONAME part as default runtime of CR + 'CR' EMIT 'LF' EMIT + ; IS CR \ set [PFA] of CR = >BODY addr of CR = CFA of :NONAME part + + [THEN] + +\ customised WORD + : WORDS \ VOC_BODY -- + PAD_ORG \ -- VOC_BODY PAD MOVE all threads of VOC_BODY in PAD_ORG + THREADS @ 2* \ -- VOC_BODY PAD THREADS*2 + MOVE \ -- vocabulary entries are copied in PAD_ORG + BEGIN \ -- + 0 DUP \ -- ptr=0 MAX=0 + THREADS @ 2* 0 \ -- ptr=0 MAX=0 THREADS*2 0 + DO \ -- ptr MAX I = PAD_ptr = thread*2 + DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx + U< IF \ -- ptr MAX if MAX U< NFAx + DROP DROP \ -- drop ptr and MAX + I DUP PAD_ORG + @ \ -- new_ptr new_MAX + THEN \ + 2 +LOOP \ -- ptr MAX + ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD = 0) + WHILE \ -- ptr MAX replace it by its LFA + DUP \ -- ptr MAX MAX + 2 - @ \ -- ptr MAX [LFA] + ROT \ -- MAX [LFA] ptr + PAD_ORG + \ -- MAX [LFA] thread + ! \ -- MAX MAX=highest_NFA [LFA]=new_NFA updates PAD_ORG+ptr + COUNT 2/ \ -- addr name_count 2/ to hide Immediate flag + DUP >R TYPE \ -- R-- count + $10 R> - SPACES \ -- R-- complete with spaces modulo 16 chars + REPEAT \ -- + DROP \ ptr -- + ; \ all threads in PAD are filled with 0 + \ https://forth-standard.org/standard/core/CASE -: CASE 0 ; IMMEDIATE \ -- #of-1 + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE \ -- #of-1 \ https://forth-standard.org/standard/core/OF -: OF \ #of-1 -- orgOF #of -1+ \ count OFs ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE OVER POSTPONE = \ copy and test case value -POSTPONE IF \ add orig to control flow stack -POSTPONE DROP \ discards case value if = -R> \ we can bring count back now -; IMMEDIATE + : OF \ #of-1 -- orgOF #of + 1+ \ count OFs + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE OVER + POSTPONE = \ copy and test case value + POSTPONE IF \ add orig to control flow stack + POSTPONE DROP \ discards case value if = + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDOF -: ENDOF \ orgOF #of -- orgENDOF #of ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE ELSE -R> \ we can bring count back now -; IMMEDIATE + : ENDOF \ orgOF #of -- orgENDOF #of + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE ELSE + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDCASE -: ENDCASE \ orgENDOF1..orgENDOFn #of -- -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] S_ [IF] -CODE S_ \ Squote alias with blank instead quote separator -MOV #0,&CAPS \ turn CAPS OFF -COLON -XSQUOTE , \ compile run-time code -'SP' WORD \ -- c-addr (= HERE) -HI2LO -MOV.B @TOS,TOS \ -- len compile string -ADD #1,TOS \ -- len+1 -BIT #1,TOS \ C = ~Z -ADDC TOS,&DP \ store aligned DP -MOV @PSP+,TOS \ -- -MOV @RSP+,IP \ pop paired with push COLON -MOV #$20,&CAPS \ turn CAPS ON (default state) -MOV @IP+,PC \ NEXT -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&STATEADR -0= IF MOV @IP+,PC \ interpret time usage disallowed -THEN -COLON -'ESC' \ -- char escape -POSTPONE LITERAL \ compile-time code : lit 'ESC' -POSTPONE EMIT \ compile-time code : EMIT -POSTPONE S_ \ compile-time code : S_ <escape_sequence> -POSTPONE TYPE \ compile-time code : TYPE -; IMMEDIATE -[THEN] + : ENDCASE \ orgENDOF1..orgENDOFn #of -- + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + [UNDEFINED] S_ + [IF] + CODE S_ \ Squote alias with blank instead quote separator + MOV #0,&CAPS \ turn CAPS OFF + COLON + XSQUOTE , \ compile run-time code + 'SP' WORD \ -- c-addr (= HERE) + HI2LO + MOV.B @TOS,TOS \ -- len compile string + ADD #1,TOS \ -- len+1 + BIT #1,TOS \ C = ~Z + ADDC TOS,&DP \ store aligned DP + MOV @PSP+,TOS \ -- + MOV @RSP+,IP \ pop paired with push COLON + MOV #$20,&CAPS \ turn CAPS ON (default state) + MOV @IP+,PC \ NEXT + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC + [IF] + CODE ESC + CMP #0,&STATEADR + 0= IF MOV @IP+,PC \ interpret time usage disallowed + THEN + COLON + 'ESC' \ -- char escape + POSTPONE LITERAL \ compile-time code : lit 'ESC' + POSTPONE EMIT \ compile-time code : EMIT + POSTPONE S_ \ compile-time code : S_ <escape_sequence> + POSTPONE TYPE \ compile-time code : TYPE + ; IMMEDIATE + [THEN] + + [DEFINED] FORTH \ word-set addon ? + [IF] + CODE BODY>SQNFA \ BODY -- ADR cnt BODY > SQuoteNFA + SUB #2,PSP + SUB #4,TOS + MOV TOS,Y \ Y = CFA + MOV Y,X \ X = CFA + BEGIN + SUB #2,X + MOV X,0(PSP) \ -- string_test_address CFA + MOV.B @X+,TOS \ -- string_test_address cnt_test + RRA TOS \ -- string_test_address cnt_test/2 + MOV TOS,W + BIT #1,W \ cnt_test even ? + 0= IF + ADD #1,W \ if yes add #1,TOS + THEN + ADD X,W \ string_test_address + cnt_test + CMP W,Y \ string_test_address + cnt_test = CFA ? + 0<> WHILE \ out of loop if yes + MOV @PSP,X \ loop back to test with X - one_word + REPEAT + MOV X,0(PSP) \ -- string_addr string_cnt + MOV @IP+,PC + ENDCODE + [THEN] \ ------------------------------------------------------- -: SPECS \ to see all FastForth specifications + : SPECS \ to see all FastForth specifications \ ------------------------------------------------------- -PWR_STATE \ before computing free bytes, remove all created words -ECHO -ESC [8;40;80t \ set 40L * 80C terminal display -39 0 DO CR LOOP \ to avoid erasing any line of source, create 42-1 empty lines -ESC [H \ then cursor home -ESC [7m \ Turn reverse video on -$0D EMIT ." FastForth V" \ title line in reverse video -VERSION @ -0 <# # 'BS' HOLD # '.' HOLD #S #> TYPE -." for MSP430FR" -HERE \ HERE - MAIN_ORG = bytes code -DEVICEID @ \ value kept in TLV area -CASE + RST_RET \ before computing free bytes, remove all FF_SPECS definitions + ECHO + ESC [8;42;80t \ set 42L * 80C terminal display + +\ title in reverse video + ESC [7m \ Turn reverse video on + CR ." FastForth V" + VERSION @ + 0 <# # 'BS' HOLD # '.' HOLD #S #> TYPE + ." for MSP430FR" + HERE \ HERE - MAIN_ORG = bytes code + DEVICEID @ \ value kept in TLV area + CASE + \ device_ID OF ." xxxx," $MAIN_ORG ENDOF \ <-- add here your device - $8102 OF ." 5738," $C200 ENDOF + $8102 OF ." 5738," $C200 ENDOF $8103 OF ." 5739," $C200 ENDOF + $810D OF ." 5986," $4400 ENDOF $8160 OF ." 5948," $4400 ENDOF $8169 OF ." 5969," $4400 ENDOF - $825D OF ." 5972," $4400 ENDOF $81A8 OF ." 6989," $4400 ENDOF - $810D OF ." 5986," $4400 ENDOF $81F0 OF ." 4133," $C400 ENDOF $8240 OF ." 2433," $C400 ENDOF + $825D OF ." 5972," $4400 ENDOF $82A1 OF ." 5994," $4000 ENDOF $82A6 OF ." 5962," $4000 ENDOF $830C OF ." 2355," $8000 ENDOF @@ -569,94 +662,120 @@ CASE $833C OF ." 2633," $C400 ENDOF $833D OF ." 2533," $C400 ENDOF ABORT" xxxx <-- unrecognized device!" -ENDCASE \ -- HERE MAIN_ORG -['] ['] DUP @ $1284 = \ DOCOL = CALL rDOCOL opcode -IF ." DTC=1," DROP \ [CFA] = CALL rDOCOL -ELSE 2 + @ $1284 = \ - IF ." DTC=2," \ [CFA] = PUSH IP, [CFA+2] = CALL rDOCOL - ELSE ." DTC=3," \ [CFA] = PUSH IP, [CFA+2] = MOV PC,IP + ENDCASE \ -- HERE MAIN_ORG + ['] ['] DUP @ $1284 = \ DOCOL = CALL rDOCOL opcode + IF ." DTC=1," DROP \ [CFA] = CALL rDOCOL + ELSE 2 + @ $1284 = \ + IF ." DTC=2," \ [CFA] = PUSH IP, [CFA+2] = CALL rDOCOL + ELSE ." DTC=3," \ [CFA] = PUSH IP, [CFA+2] = MOV PC,IP + THEN THEN -THEN -$20 EMIT -THREADS @ U. 'BS' EMIT ." -Entry word set, " \ number of Entry word set, -FREQ_KHZ @ 0 1000 UM/MOD U. \ frequency, -?DUP IF 'BS' EMIT ',' EMIT U. \ if remainder -THEN ." MHz, " \ MCLK -- U. ." bytes" \ HERE - MAIN_ORG = number of bytes code, -ESC [0m \ Turn off character attributes -CR -." /COUNTED-STRING = 255" CR -." /HOLD = 34" CR -." /PAD = 84" CR -." ADDRESS-UNIT-BITS = 16" CR -." FLOORED = true" CR -." MAX-CHAR = 255" CR -." MAX-N = 32767" CR -." MAX-U = 65535" CR -." MAX-D = 2147483647" CR -." MAX-UD = 4294967295" CR -." STACK-CELLS = 48" CR -." RETURN-STACK-CELLS= 48" CR -." DeFiNiTiOnS aRe CaSe-InSeNsItIvE" CR -CR -ESC [7m ." KERNEL SPECS" ESC [0m \ subtitle in reverse video -CR -KERNEL_ADDON @ - DUP 0< IF ." 32.768kHz XTAL" CR THEN \ BIT15 -2* DUP 0< IF ." (RTS/CTS) UART TERMINAL" CR 2* \ BIT14 BIT13 - ELSE 2* DUP \ BIT13 - 0< IF ." (RTS) UART TERMINAL" CR + 'SP' EMIT + THREADS @ U. 'BS' EMIT + ." -Entry word set, " \ number of Entry word set, + FREQ_KHZ @ 0 1000 UM/MOD U. \ frequency + ?DUP IF 'BS' EMIT ',' EMIT U. \ if remainder + THEN ." MHz, " \ MCLK + - U. ." bytes" \ HERE - MAIN_ORG = number of bytes code, + ESC [0m \ Turn off character attributes + +\ general + CR + ." /COUNTED-STRING = 255" CR + ." /HOLD = 34" CR + ." /PAD = 84" CR + ." ADDRESS-UNIT-BITS = 16" CR + ." FLOORED DIVISION = " + KERNEL_ADDON @ \ negative value if FLOORED DIVISION + 0< IF ." true" + ELSE ." false" + THEN CR + ." MAX-CHAR = 255" CR + ." MAX-N = 32767" CR + ." MAX-U = 65535" CR + ." MAX-D = 2147483647" CR + ." MAX-UD = 4294967295" CR + ." STACK-CELLS = 48" CR + ." RETURN-STACK-CELLS= 48" CR + ." Definitions are forced to UPPERCASE." CR + +\ kernel specs + CR ESC [7m ." Kernel add-ons" ESC [0m CR \ subtitle in reverse video + KERNEL_ADDON @ + 2* DUP 0< IF ." 32.768kHz LF XTAL" CR THEN \ BIT14 + 2* DUP 0< IF ." /RTS /CTS " 2* \ BIT13 + ELSE 2* DUP \ /BIT13 + 0< IF ." /RTS " THEN \ /BIT13 & BIT12 THEN - THEN -2* DUP 0< IF ." (XON/XOFF) UART TERMINAL" CR \ BIT12 - THEN -2* DUP 0< IF ." Half-Duplex TERMINAL" CR THEN \ BIT11 -2* DUP 0< IF ." I2C_Master TERMINAL" CR THEN \ BIT10 -2* DUP 0< IF ." Q15.16 input" CR THEN \ BIT9 -2* DUP 0< IF ." DOUBLE input" CR THEN \ BIT8 -2* DUP 0< IF ." MSP430_X assembler" CR 2* 2* \ BIT7 BIT6 BIT5 - ELSE 2* DUP \ BIT6 - 0< IF ." MSP430 Assembler" - 2* DUP 0< IF ." with 20bits address" \ BIT5 - THEN CR - ELSE 2* \ BIT5 + 2* DUP 0< IF ." XON/XOFF " THEN \ BIT11 + 2* DUP 0< IF ." Half-Duplex " THEN \ BIT10 + 2* DUP 0< IF ." I2C_Master TERMINAL" \ BIT9 + ELSE ." UART TERMINAL" THEN CR \ /BIT9 + 2* DUP 0< IF 2* DUP 0< IF ." DOUBLE and " \ BIT8 + BIT7 + THEN ." Q15.16 numbers handling" CR + ELSE 2* DUP 0< IF ." DOUBLE numbers handling" CR \ /BIT8 + BIT7 + THEN THEN - THEN -2* \ BIT4 free flags -2* \ BIT3 free flags -2* \ BIT2 free flags -2* \ BIT1 free flags -2* 0< IF \ BIT0 true if COND. COMPILATION - [DEFINED] DEFER [IF] ." DEFER word set" CR [THEN] - [DEFINED] ALSO [IF] ." VOCABULARY word set" CR [THEN] - [DEFINED] LOAD" [IF] ." SD_CARD Loader" CR [THEN] - [DEFINED] BOOT [IF] ." bootloader" CR [THEN] - [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR [THEN] - CR - ESC [7m ." OPTIONS" ESC [0m \ subtitle in reverse video + 2* DUP 0< IF ." MSP430_X assembler with TI's syntax" + CR 2* 2* \ BIT6 BIT5 BIT4 + ELSE \ /BIT6 + 2* DUP + 0< IF ." MSP430 Assembler" \ BIT5 + 2* DUP + 0< IF ." , 20bits extended addresses," \ BIT4 + THEN + ELSE 2* \ BIT4 + THEN + ." with TI's syntax" CR + THEN DROP \ BIT2 to BIT0 are free + [DEFINED] FORTH [IF] ." word-set management" CR + [THEN] + [DEFINED] LOAD" [IF] ." SD_CARD Load" CR + [THEN] + [DEFINED] BOOT [IF] ." SD_CARD Bootloader" CR + [THEN] + [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR + [THEN] + +\ word-set + LASTVOC \ -- VOCLINK addr. + BEGIN + @ ?DUP \ -- VOCLINK word-set here ? + WHILE \ -- VLK + DUP THREADS @ 2* - \ -- VLK WORDSET_BODY + CR ESC [7m + [DEFINED] FORTH \ word-set addon ? + [IF] DUP BODY>SQNFA \ -- VLK WRDST_BODY addr cnt + [ELSE] OVER @ \ -- VLK WRDST_BODY NEXT_VLINK + IF S" hidden" \ if next_vlink <>0 + ELSE S" FORTH" \ if next_vlink = 0 + THEN \ -- VLK WRDST_BODY addr cnt + [THEN] + TYPE ." word-set" \ -- VLK WRDST_BODY subtitle in reverse video + ESC [0m CR + WORDS CR \ -- VLINK definitions display + REPEAT + +\ extensions + CR ESC [7m ." EXTENSIONS" ESC [0m \ subtitle in reverse video + [DEFINED] {CORE_ANS} [IF] CR ." core ANS94" + [THEN] + [DEFINED] {DOUBLE} [IF] CR ." DOUBLE word set" + [THEN] + [DEFINED] {UTILITY} [IF] CR ." UTILITY" + [THEN] + [DEFINED] {FIXPOINT} [IF] CR ." Q15.16 ADD SUB MUL DIV" + [THEN] + [DEFINED] {CORDIC} [IF] CR ." CORDIC engine" + [THEN] + [DEFINED] {SD_TOOLS} [IF] CR ." SD_TOOLS" + [THEN] + [DEFINED] {RTC} [IF] CR ." RTC utility" + [THEN] + [DEFINED] {UARTI2CS} [IF] CR ." UART to I2C_FastForth bridge" + [THEN] CR - [DEFINED] {CORE_ANS} [IF] ." ANS94 core" CR [THEN] - [DEFINED] {DOUBLE} [IF] ." DOUBLE word set" CR [THEN] - [DEFINED] {TOOLS} [IF] ." UTILITY" CR [THEN] - [DEFINED] {FIXPOINT} [IF] ." Q15.16 ADD SUB MUL DIV" CR [THEN] - [DEFINED] {CORDIC} [IF] ." CORDIC engine" CR [THEN] - [DEFINED] {SD_TOOLS} [IF] ." SD_TOOLS" CR [THEN] - [DEFINED] {RTC} [IF] ." RTC utility" CR [THEN] - [DEFINED] {UARTI2CS} [IF] ." UART to I2C_FastForth bridge" CR [THEN] - [DEFINED] ALSO - [IF] - CR - ESC [7m ." ASSEMBLER word set" ESC [0m \ subtitle in reverse video - ALSO ASSEMBLER WORDS PREVIOUS \ type ASSEMBLER word set - CR - [THEN] -THEN -CR -ESC [7m ." FORTH word set" ESC [0m \ subtitle in reverse video -WORDS \ type FORTH word set -CR -HI2LO -MOV #WARM+4,PC \ type count of bytes free without re-executing INI_APP, no return -ENDCODE - -SPECS \ here FastForth displays a message with some informations + 0 SYS \ WARM + ; + +SPECS \ performs RST_RET and displays FastForth specs diff --git a/MSP430-FORTH/FixPoint.f b/MSP430-FORTH/FixPoint.f index a8a3956..69cdf6d 100644 --- a/MSP430-FORTH/FixPoint.f +++ b/MSP430-FORTH/FixPoint.f @@ -20,7 +20,7 @@ \ rDODOES to rEXIT must be saved before use and restored after \ scratch registers Y to S are free for use \ under interrupt, IP is free for use -\ +\ \ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC \ PUSHM order : PSP,TOS,IP,S,T,W, X, Y, rDOCOL , rDOVAR , rDOCON , rDODOES , R3, SR, RSP, PC \ @@ -37,286 +37,310 @@ \ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0< \ -CODE ABORT_FIXPOINT -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #BIT10,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" buil FastForth with FIXPOINT_INPUT addon !" -PWR_STATE \ if no abort remove this word -$1B EMIT $63 EMIT \ send 'ESC c' (clear screen) -; - -ABORT_FIXPOINT + CODE ABORT_FIXPOINT + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #BIT8,TOS + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with Q15.16_INPUT addon !" + RST_RET \ if no abort remove this word + $1B EMIT $63 EMIT \ send 'ESC c' (clear screen) + ; + + ABORT_FIXPOINT ; ----------------------------------------------------- -; FIXPOINT.f +; FIXPOINT.f ; ----------------------------------------------------- -[DEFINED] {FIXPOINT} [IF] {FIXPOINT} [THEN] - -MARKER {FIXPOINT} + MARKER {FIXPOINT} -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] R> [IF] \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] \ https://forth-standard.org/standard/core/Uless \ U< u1 u2 -- flag test u1<u2, unsigned -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 + [UNDEFINED] U< + [IF] + CODE U< + SUB @PSP+,TOS \ 2 u2-u1 + 0<> IF + MOV #-1,TOS \ 1 + U< IF \ 2 flag + AND #0,TOS \ 1 flag Z = 1 + THEN THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] DABS [IF] \ https://forth-standard.org/standard/double/DABS \ DABS d1 -- |d1| absolute value -CODE DABS -AND #-1,TOS \ clear V, set N -S< IF \ - XOR #-1,0(PSP) \ 4 - XOR #-1,TOS \ 1 - ADD #1,0(PSP) \ 4 - ADDC #0,TOS \ 1 -THEN -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] HOLDS [IF] + [UNDEFINED] DABS + [IF] + CODE DABS + AND #-1,TOS \ clear V, set N + S< IF \ + XOR #-1,0(PSP) \ 4 + XOR #-1,TOS \ 1 + ADD #1,0(PSP) \ 4 + ADDC #0,TOS \ 1 + THEN + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/HOLDS \ Adds the string represented by addr u to the pictured numeric output string \ compilation use: <# S" string" HOLDS #> \ free chars area in the 32+2 bytes HOLD buffer = {26,23,2} chars with a 32 bits sized {hexa,decimal,binary} number. \ (2 supplementary bytes are room for sign - and decimal point) \ C HOLDS addr u -- -CODE HOLDS - MOV @PSP+,X \ 2 X=src -BW3 ADD TOS,X \ 1 X=src_end - MOV &HP,Y \ 3 Y=dst -BEGIN SUB #1,X \ 1 src-1 - SUB #1,TOS \ 1 cnt-1 -U>= WHILE SUB #1,Y \ 1 dst-1 - MOV.B @X,0(Y) \ 4 -REPEAT MOV Y,&HP \ 3 - MOV @PSP+,TOS \ 2 - MOV @IP+,PC \ 4 15 words -ENDCODE -[THEN] - -CODE F+ \ add Q15.16|double numbers - ADD @PSP+,2(PSP) \ -- sumlo d1hi d2hi - ADDC @PSP+,TOS \ -- sumlo sumhi - MOV @IP+,PC -ENDCODE - -CODE F- \ substract Q15.16|double numbers - SUB @PSP+,2(PSP) \ -- diflo d1hi d2hi - SUBC TOS,0(PSP) \ -- diflo difhi d2hi - MOV @PSP+,TOS - MOV @IP+,PC -ENDCODE - -TLV_ORG 4 + @ $81F3 U< -$81EF TLV_ORG 4 + @ U< -= [IF] ; MSP430FR413x subfamily without hardware_MPY + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @PSP+,X \ 2 X=src +BW3 ADD TOS,X \ 1 X=src_end + MOV &HP,Y \ 3 Y=dst + BEGIN + SUB #1,X \ 1 src-1 + SUB #1,TOS \ 1 cnt-1 + U>= WHILE + SUB #1,Y \ 1 dst-1 + MOV.B @X,0(Y) \ 4 + REPEAT + MOV Y,&HP \ 3 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 15 words + ENDCODE + [THEN] + + CODE F+ \ add Q15.16|double numbers + ADD @PSP+,2(PSP) \ -- sumlo d1hi d2hi + ADDC @PSP+,TOS \ -- sumlo sumhi + MOV @IP+,PC + ENDCODE + + CODE F- \ substract Q15.16|double numbers + SUB @PSP+,2(PSP) \ -- diflo d1hi d2hi + SUBC TOS,0(PSP) \ -- diflo difhi d2hi + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + + TLV_ORG 4 + @ $81F3 U< + $81EF TLV_ORG 4 + @ U< + = [IF] ; MSP430FR413x subfamily without hardware_MPY \ unsigned multiply 32*32 = 64 \ don't use S reg (keep sign) -CODE UDM* - PUSH IP \ 3 - PUSHM #4,rDOVAR \ 6 save rDOVAR to rDOCOL regs to use M to R alias - MOV 4(PSP),IP \ 3 MDlo - MOV 2(PSP),T \ 3 MDhi - MOV @PSP,W \ 2 MRlo - MOV #0,M \ 1 MDLO=0 - MOV #0,P \ 1 MDHI=0 - MOV #0,4(PSP) \ 3 RESlo=0 - MOV #0,2(PSP) \ 3 REShi=0 - MOV #0,Q \ 1 RESLO=0 - MOV #0,R \ 1 RESHI=0 - MOV #1,X \ 1 BIT TEST REGlo - MOV #0,Y \ 1 BIT TEST2 REGhi -BEGIN CMP #0,X - 0<> IF BIT X,W \ 2+1 TEST ACTUAL BIT MRlo - ELSE BIT Y,TOS \ 2+1 TEST ACTUAL BIT MRhi + CODE UDM* + PUSH IP \ 3 + PUSHM #4,rDOVAR \ 6 save rDOVAR to rDOCOL regs to use M to R alias + MOV 4(PSP),IP \ 3 MDlo + MOV 2(PSP),T \ 3 MDhi + MOV @PSP,W \ 2 MRlo + MOV #0,M \ 1 MDLO=0 + MOV #0,P \ 1 MDHI=0 + MOV #0,4(PSP) \ 3 RESlo=0 + MOV #0,2(PSP) \ 3 REShi=0 + MOV #0,Q \ 1 RESLO=0 + MOV #0,R \ 1 RESHI=0 + MOV #1,X \ 1 BIT TEST REGlo + MOV #0,Y \ 1 BIT TEST2 REGhi + BEGIN + CMP #0,X + 0<> IF + BIT X,W \ 2+1 TEST ACTUAL BIT MRlo + ELSE + BIT Y,TOS \ 2+1 TEST ACTUAL BIT MRhi + THEN + 0<> IF + ADD IP,4(PSP) \ 2+3 IF 1: ADD MDlo TO RESlo + ADDC T,2(PSP) \ 3 ADDC MDhi TO REShi + ADDC M,Q \ 1 ADDC MDLO TO RESLO + ADDC P,R \ 1 ADDC MDHI TO RESHI + THEN + ADD IP,IP \ 1 (RLA LSBs) MDlo *2 + ADDC T,T \ 1 (RLC MSBs) MDhi *2 + ADDC M,M \ 1 (RLC LSBs) MDLO *2 + ADDC P,P \ 1 (RLC MSBs) MDHI *2 + ADD X,X \ 1 (RLA) NEXT BIT TO TEST + ADDC Y,Y \ 1 (RLC) NEXT BIT TO TEST + U>= UNTIL + MOV Q,0(PSP) \ 2+2 IF BIT IN CARRY: FINISHED 32 * 16~ (average loop) + MOV R,TOS \ 1 high result in TOS + POPM #4,rDOVAR \ 6 restore rDOCOL to rDOVAR + MOV @RSP+,IP \ 2 + MOV @IP+,PC + ENDCODE + + CODE F* \ s15.16 * s15.16 --> s15.16 result + MOV 2(PSP),S \ + XOR TOS,S \ 1s15 XOR 2s15 --> S keep sign of result + BIT #$8000,2(PSP) \ MD < 0 ? + 0<> IF + XOR #-1,2(PSP) + XOR #-1,4(PSP) + ADD #1,4(PSP) + ADDC #0,2(PSP) + THEN + COLON + DABS UDM* \ -- RES0 RES1 RES2 RES3 + HI2LO + MOV @RSP+,IP + MOV @PSP+,TOS \ -- RES0 RES1 RES2 + MOV @PSP+,0(PSP) \ -- RES1 RES2 + AND #-1,S \ clear V, set N; process S sign + S< IF + XOR #-1,0(PSP) \ INV(QUOTlo) + XOR #-1,TOS \ INV(QUOThi) + ADD #1,0(PSP) \ INV(QUOTlo)+1 + ADDC #0,TOS \ INV(QUOThi)+C THEN - 0<> IF ADD IP,4(PSP) \ 2+3 IF 1: ADD MDlo TO RESlo - ADDC T,2(PSP) \ 3 ADDC MDhi TO REShi - ADDC M,Q \ 1 ADDC MDLO TO RESLO - ADDC P,R \ 1 ADDC MDHI TO RESHI - THEN ADD IP,IP \ 1 (RLA LSBs) MDlo *2 - ADDC T,T \ 1 (RLC MSBs) MDhi *2 - ADDC M,M \ 1 (RLC LSBs) MDLO *2 - ADDC P,P \ 1 (RLC MSBs) MDHI *2 - ADD X,X \ 1 (RLA) NEXT BIT TO TEST - ADDC Y,Y \ 1 (RLC) NEXT BIT TO TEST -U>= UNTIL MOV Q,0(PSP) \ 2+2 IF BIT IN CARRY: FINISHED 32 * 16~ (average loop) - MOV R,TOS \ 1 high result in TOS - POPM #4,rDOVAR \ 6 restore rDOCOL to rDOVAR - MOV @RSP+,IP \ 2 - MOV @IP+,PC -ENDCODE - -CODE F* \ s15.16 * s15.16 --> s15.16 result - MOV 2(PSP),S \ - XOR TOS,S \ 1s15 XOR 2s15 --> S keep sign of result - BIT #$8000,2(PSP) \ MD < 0 ? -0<> IF XOR #-1,2(PSP) - XOR #-1,4(PSP) - ADD #1,4(PSP) - ADDC #0,2(PSP) -THEN COLON - DABS UDM* \ -- RES0 RES1 RES2 RES3 - HI2LO - MOV @RSP+,IP - MOV @PSP+,TOS \ -- RES0 RES1 RES2 - MOV @PSP+,0(PSP) \ -- RES1 RES2 - AND #-1,S \ clear V, set N; process S sign -S< IF XOR #-1,0(PSP) \ INV(QUOTlo) - XOR #-1,TOS \ INV(QUOThi) - ADD #1,0(PSP) \ INV(QUOTlo)+1 - ADDC #0,TOS \ INV(QUOThi)+C -THEN MOV @IP+,PC -ENDCODE - -[UNDEFINED] F#S [IF] + MOV @IP+,PC + ENDCODE + \ F#S Qlo Qhi len -- Qhi 0 convert fractional part Qlo of Q15.16 fixed point number \ with len digits -CODE F#S - MOV @PSP,S \ -- Qlo Qhi len S = Qhi - MOV #0,T \ T = count - PUSHM #3,IP \ R-- IP Qhi count - MOV 2(PSP),0(PSP) \ -- Qlo Qlo len - MOV TOS,2(PSP) \ -- len Qlo len -BEGIN MOV &BASEADR,TOS \ -- len Qlo base - LO2HI - UM* \ u1 u2 -- RESlo REShi - HI2LO \ -- len RESlo digit - CMP #10,TOS \ digit to char - U>= IF ADD #7,TOS - THEN ADD #$30,TOS \ -- len RESlo char - MOV @RSP,T \ T=count - MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T) - ADD #1,T \ count+1 - MOV T,0(RSP) \ - CMP 2(PSP),T \ -- len RESlo char count=len ? -U>= UNTIL POPM #3,IP \ S=Qhi, T=len - MOV T,TOS \ -- len RESlo len - MOV S,2(PSP) \ -- Qhi RESlo len - MOV #0,0(PSP) \ -- Qhi 0 len - MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG - GOTO BW3 \ 36~ JMP HOLDS -ENDCODE -[THEN] - -[ELSE] ; hardware multiplier - -CODE F* \ signed s15.16 multiplication --> s15.16 result - MOV 4(PSP),&MPYS32L \ 5 Load 1st operand - MOV 2(PSP),&MPYS32H \ 5 - MOV @PSP,&OP2L \ 4 load 2nd operand - MOV TOS,&OP2H \ 3 - ADD #4,PSP \ 1 remove 2 cells - MOV &RES1,0(PSP) \ 5 - MOV &RES2,TOS \ 5 - MOV @IP+,PC -ENDCODE - -[UNDEFINED] F#S [IF] + CODE F#S + MOV @PSP,S \ -- Qlo Qhi len S = Qhi + MOV #0,T \ T = count + PUSHM #3,IP \ R-- IP Qhi count + MOV 2(PSP),0(PSP) \ -- Qlo Qlo len + MOV TOS,2(PSP) \ -- len Qlo len + BEGIN + MOV &BASEADR,TOS \ -- len Qlo base + LO2HI + UM* \ u1 u2 -- RESlo REShi + HI2LO \ -- len RESlo digit + CMP #10,TOS \ digit to char + U>= IF + ADD #7,TOS + THEN + ADD #$30,TOS \ -- len RESlo char + MOV @RSP,T \ T=count + MOV.B TOS,HOLDS_ORG(T) \ char to string_org(T) + ADD #1,T \ count+1 + MOV T,0(RSP) \ + CMP 2(PSP),T \ -- len RESlo char count=len ? + U>= UNTIL + POPM #3,IP \ S=Qhi, T=len + MOV T,TOS \ -- len RESlo len + MOV S,2(PSP) \ -- Qhi RESlo len + MOV #0,0(PSP) \ -- Qhi 0 len + MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG + GOTO BW3 \ 36~ JMP HOLDS + ENDCODE + + [ELSE] ; hardware multiplier + + CODE F* \ signed s15.16 multiplication --> s15.16 result + MOV 4(PSP),&MPYS32L \ 5 Load 1st operand + MOV 2(PSP),&MPYS32H \ 5 + MOV @PSP,&OP2L \ 4 load 2nd operand + MOV TOS,&OP2H \ 3 + ADD #4,PSP \ 1 remove 2 cells + MOV &RES1,0(PSP) \ 5 + MOV &RES2,TOS \ 5 + MOV @IP+,PC + ENDCODE + + \ F#S Qlo Qhi len -- Qhi 0 convert fractionnal part of Q15.16 fixed point number \ with len digits -CODE F#S - MOV 2(PSP),X \ -- Qlo Qhi len X = Qlo - MOV @PSP,2(PSP) \ -- Qhi Qhi len - MOV X,0(PSP) \ -- Qhi Qlo len - MOV TOS,T \ T = len - MOV #0,S \ S = count -BEGIN MOV @PSP,&MPY \ Load 1st operand - MOV &BASEADR,&OP2 \ Load 2nd operand - MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack - MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS - CMP #10,TOS \ digit to char - U>= IF ADD #7,TOS - THEN ADD #$30,TOS - MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string - ADD #1,S \ count+1 - CMP T,S \ count=len ? -0= UNTIL MOV T,TOS \ -- len RESlo len - MOV #0,0(PSP) \ -- Qhi 0 len - MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG - GOTO BW3 \ 35~ JMP HOLDS+2 -ENDCODE -[THEN] - -[THEN] \ end of hardware/software multiplier - -CODE F/ \ Q15.16 / Q15.16 --> Q15.16 result - MOV TOS,Y \ 1 Y=DVRhi - MOV @PSP+,W \ 2 W=DVRlo - MOV @PSP+,X \ 2 X=DVDhi - MOV @PSP,T \ 2 T=DVDlo - PUSHM #5,X \ 7 PUSHM DVDhi,DVRhi, M, P, Q - AND #-1,Y \ 1 Y=DVRhi < 0 ? -S< IF XOR #-1,W \ 1 W=INV(DVRlo) - XOR #-1,Y \ 1 Y=INV(DVRhi) - ADD #1,W \ 1 W=INV(DVRlo)+1 - ADDC #0,Y \ 1 Y=INV(DVRhi)+C -THEN - AND #-1,X \ 1 X=DVDhi < 0 ? -S< IF XOR #-1,T \ 1 T=INV(DVDlo) - XOR #-1,X \ 1 X=INV(DVDhi) - ADD #1,T \ 1 T=INV(DVDlo)+1 - ADDC #0,X \ 1 X=INV(DVDhi)+C -THEN - MOV X,M \ 1 DVDhi --> REMlo to adjust Q15.16 division - MOV T,X \ 1 DVDlo --> DVDhi - MOV #0,T \ 1 0 --> DVDlo + CODE F#S + MOV 2(PSP),X \ -- Qlo Qhi len X = Qlo + MOV @PSP,2(PSP) \ -- Qhi Qhi len + MOV X,0(PSP) \ -- Qhi Qlo len + MOV TOS,T \ T = len + MOV #0,S \ S = count + BEGIN + MOV @PSP,&MPY \ Load 1st operand + MOV &BASEADR,&OP2 \ Load 2nd operand + MOV &RES0,0(PSP) \ -- Qhi RESlo x low result on stack + MOV &RES1,TOS \ -- Qhi RESlo REShi high result in TOS + CMP #10,TOS \ digit to char + U>= IF + ADD #7,TOS + THEN + ADD #$30,TOS + MOV.B TOS,HOLDS_ORG(S) \ -- Qhi RESlo char char to string + ADD #1,S \ count+1 + CMP T,S \ count=len ? + 0= UNTIL + MOV T,TOS \ -- len RESlo len + MOV #0,0(PSP) \ -- Qhi 0 len + MOV #HOLDS_ORG,X \ -- Qhi 0 len X=HOLDS_ORG + GOTO BW3 \ 35~ JMP HOLDS+2 + ENDCODE + + [THEN] ; end of hardware/software multiplier + + CODE F/ \ Q15.16 / Q15.16 --> Q15.16 result + MOV TOS,Y \ 1 Y=DVRhi + MOV @PSP+,W \ 2 W=DVRlo + MOV @PSP+,X \ 2 X=DVDhi + MOV @PSP,T \ 2 T=DVDlo + PUSHM #5,X \ 7 PUSHM DVDhi,DVRhi, M, P, Q + AND #-1,Y \ 1 Y=DVRhi < 0 ? + S< IF + XOR #-1,W \ 1 W=INV(DVRlo) + XOR #-1,Y \ 1 Y=INV(DVRhi) + ADD #1,W \ 1 W=INV(DVRlo)+1 + ADDC #0,Y \ 1 Y=INV(DVRhi)+C + THEN + AND #-1,X \ 1 X=DVDhi < 0 ? + S< IF + XOR #-1,T \ 1 T=INV(DVDlo) + XOR #-1,X \ 1 X=INV(DVDhi) + ADD #1,T \ 1 T=INV(DVDlo)+1 + ADDC #0,X \ 1 X=INV(DVDhi)+C + THEN + MOV X,M \ 1 DVDhi --> REMlo to adjust Q15.16 division + MOV T,X \ 1 DVDlo --> DVDhi + MOV #0,T \ 1 0 --> DVDlo \ ------------------------------------------------------------------------ \ don't uncomment lines below, don't rub out, please ! \ ------------------------------------------------------------------------ @@ -328,153 +352,161 @@ THEN \ MOV @PSP,T \ 2 T=DVDlo \ PUSHM #5,X \ 7 PUSHM DVDhi,DVRhi, M, P, Q \ MOV #0,M \ 1 M=REMlo = 0 - MOV #0,P \ 1 P=REMhi = 0 - MOV #32,Q \ 2 Q=count -BW1 CMP Y,P \ 1 REMhi = DVRhi ? - 0= IF CMP W,M \ 1 REMlo U< DVRlo ? + MOV #0,P \ 1 P=REMhi = 0 + MOV #32,Q \ 2 Q=count +BW1 CMP Y,P \ 1 REMhi = DVRhi ? + 0= IF + CMP W,M \ 1 REMlo U< DVRlo ? THEN - U>= IF SUB W,M \ 1 no: REMlo - DVRlo (carry is set) - SUBC Y,P \ 1 REMhi - DVRhi + U>= IF + SUB W,M \ 1 no: REMlo - DVRlo (carry is set) + SUBC Y,P \ 1 REMhi - DVRhi THEN - BEGIN ADDC S,S \ 1 RLC quotLO - ADDC TOS,TOS \ 1 RLC quotHI - SUB #1,Q \ 1 Decrement loop counter - U>= WHILE \ 2 out of loop if count<0 - ADD T,T \ 1 RLA DVDlo - ADDC X,X \ 1 RLC DVDhi - ADDC M,M \ 1 RLC REMlo - ADDC P,P \ 1 RLC REMhi - U< ?GOTO BW1 \ 2 19~ loop - SUB W,M \ 1 REMlo - DVRlo - SUBC Y,P \ 1 REMhi - DVRhi - BIS #1,SR \ 1 - REPEAT \ 2 16~ loop -\ MOV M,T \ 1 T=REMlo -\ MOV P,W \ 1 W=REMhi - POPM #5,X \ 7 X=DVDhi, Y=DVRhi, system regs M,P,Q restored -\ CMP #0,X \ 1 sign of Rem ? -\ S< IF XOR #-1,T \ 1 INV(REMlo) -\ XOR #-1,W \ 1 INV(REMhi) -\ ADD #1,T \ 1 INV(REMlo)+1 -\ ADDC #0,W \ 1 INV(REMhi)+C + BEGIN + ADDC S,S \ 1 RLC quotLO + ADDC TOS,TOS \ 1 RLC quotHI + SUB #1,Q \ 1 Decrement loop counter + U>= WHILE \ 2 out of loop if count<0 + ADD T,T \ 1 RLA DVDlo + ADDC X,X \ 1 RLC DVDhi + ADDC M,M \ 1 RLC REMlo + ADDC P,P \ 1 RLC REMhi + U< ?GOTO BW1 \ 2 19~ loop + SUB W,M \ 1 REMlo - DVRlo + SUBC Y,P \ 1 REMhi - DVRhi + BIS #1,SR \ 1 + REPEAT \ 2 16~ loop +\ MOV M,T \ 1 T=REMlo +\ MOV P,W \ 1 W=REMhi + POPM #5,X \ 7 X=DVDhi, Y=DVRhi, system regs M,P,Q restored +\ CMP #0,X \ 1 sign of Rem ? +\ S< IF XOR #-1,T \ 1 INV(REMlo) +\ XOR #-1,W \ 1 INV(REMhi) +\ ADD #1,T \ 1 INV(REMlo)+1 +\ ADDC #0,W \ 1 INV(REMhi)+C \ THEN -\ SUB #4,PSP \ -\ MOV T,4(PSP) \ REMlo -\ MOV W,2(PSP) \ REMhi - XOR X,Y \ Y = sign of Quot - CMP #0,Y \ sign of Quot ? -S< IF XOR #-1,S \ 1 INV(QUOTlo) - XOR #-1,TOS \ 1 INV(QUOThi) - ADD #1,S \ 1 INV(QUOTlo)+1 - ADDC #0,TOS \ 1 INV(QUOThi)+C -THEN - MOV S,0(PSP) \ 3 QUOTlo - MOV @IP+,PC \ 4 -ENDCODE - -[UNDEFINED] F. [IF] -CODE F. \ display a Q15.16 number with 4/5/16 digits after comma -MOV TOS,S \ S = sign -MOV #4,T \ T = 4 preset 4 digits for base 16 and by default -MOV &BASEADR,W -CMP #$0A,W -0= IF \ if base 10 - ADD #1,T \ T = 5 set 5 digits -ELSE - CMP #2,W - 0= IF \ if base 2 - MOV #$10,T \ T = 16 set 16 digits +\ SUB #4,PSP \ +\ MOV T,4(PSP) \ REMlo +\ MOV W,2(PSP) \ REMhi + XOR X,Y \ Y = sign of Quot + CMP #0,Y \ sign of Quot ? + S< IF + XOR #-1,S \ 1 INV(QUOTlo) + XOR #-1,TOS \ 1 INV(QUOThi) + ADD #1,S \ 1 INV(QUOTlo)+1 + ADDC #0,TOS \ 1 INV(QUOThi)+C + THEN + MOV S,0(PSP) \ 3 QUOTlo + MOV @IP+,PC \ 4 + ENDCODE + + CODE F. \ display a Q15.16 number with 4/5/16 digits after comma + MOV TOS,S \ S = sign + MOV #4,T \ T = 4 preset 4 digits for base 16 and by default + MOV &BASEADR,W + CMP #$0A,W + 0= IF \ if base 10 + ADD #1,T \ T = 5 set 5 digits + ELSE + CMP #2,W + 0= IF \ if base 2 + MOV #$10,T \ T = 16 set 16 digits + THEN THEN -THEN -PUSHM #3,IP \ R-- IP sign #digit -LO2HI + PUSHM #3,IP \ R-- IP sign #digit + LO2HI <# DABS \ -- uQlo uQhi R-- IP sign #digit R> F#S \ -- uQhi 0 R-- IP sign $2C HOLD \ $2C = char ',' #S \ -- 0 0 R> SIGN #> \ -- addr len R-- IP - TYPE $20 EMIT \ -- -; + TYPE $20 EMIT \ -- + ; -CODE S>F \ convert a signed number to a Q15.16 (signed) number + CODE S>F \ convert a signed number to a Q15.16 (signed) number SUB #2,PSP MOV #0,0(PSP) MOV @IP+,PC -ENDCODE -[THEN] + ENDCODE -RST_HERE + RST_SET ; ----------------------- ; complement (volatile) for tests below ; ----------------------- -[UNDEFINED] ! [IF] \ https://forth-standard.org/standard/core/Store \ ! x a-addr -- store cell in memory -CODE ! -MOV @PSP+,0(TOS) \ 4 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] + [UNDEFINED] ! + [IF] + CODE ! + MOV @PSP+,0(TOS) \ 4 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DOES \ DOES> -- set action for the latest CREATEd definition -CODE DOES> -MOV &LAST_CFA,W \ W = CFA of CREATEd word -MOV #DODOES,0(W) \ replace CFA (DOCON) by new CFA (DODOES) -MOV IP,2(W) \ replace PFA by the address after DOES> as execution address -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] + [UNDEFINED] DOES> + [IF] + CODE DOES> + MOV &LAST_CFA,W \ W = CFA of CREATEd word + MOV #DODOES,0(W) \ replace CFA (DOCON) by new CFA (DODOES) + MOV IP,2(W) \ replace PFA by the address after DOES> as execution address + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] 2CONSTANT [IF] +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/TwoCONSTANT -: 2CONSTANT \ udlo/dlo/Qlo udhi/dhi/Qhi -- to create double or Q15.16 CONSTANT -CREATE , , \ compile Qhi then Qlo -DOES> \ execution part addr -- Qhi Qlo -HI2LO -SUB #2,PSP -MOV 2(TOS),0(PSP) -MOV @TOS,TOS -MOV @RSP+,IP -NEXT -ENDCODE -[THEN] - -[UNDEFINED] D. [IF] + [UNDEFINED] 2CONSTANT + [IF] + : 2CONSTANT \ udlo/dlo/Qlo udhi/dhi/Qhi -- to create double or Q15.16 CONSTANT + CREATE , , \ compile Qhi then Qlo + DOES> \ execution part addr -- Qhi Qlo + HI2LO + SUB #2,PSP + MOV 2(TOS),0(PSP) + MOV @TOS,TOS + MOV @RSP+,IP + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/double/Dd \ D. dlo dhi -- display d (signed) -CODE D. -MOV #U.,W \ U. + 10 = D. -ADD #10,W -MOV W,PC -ENDCODE -[THEN] - -[UNDEFINED] BASE [IF] + [UNDEFINED] D. + [IF] + CODE D. + MOV #U.,W \ U. + 10 = D. + ADD #10,W + MOV W,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/BASE \ BASE -- a-addr holds conversion radix -BASEADR CONSTANT BASE -[THEN] + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] -ECHO + ECHO ; ----------------------- ; (volatile) tests for FIXPOINT.asm|FIXPOINT.f @@ -483,58 +515,58 @@ ECHO 3,14159 2CONSTANT PI PI -1,0 F* 2CONSTANT -PI -PI D. ; D. is not appropriate --> +PI D. ; D. is not appropriate --> -PI D. ; D. is not appropriate --> -PI F. ; F. is a good choice! ---> +PI F. ; F. is a good choice! ---> -PI F. ; F. is a good choice! ---> -$10 BASE ! PI F. +$10 BASE ! PI F. -PI F. -%10 BASE ! PI F. +%10 BASE ! PI F. -PI F. -#10 BASE ! PI F. +#10 BASE ! PI F. -PI F. - PI 2,0 F* F. - PI -2,0 F* F. --PI 2,0 F* F. --PI -2,0 F* F. + PI 2,0 F* F. + PI -2,0 F* F. +-PI 2,0 F* F. +-PI -2,0 F* F. - PI 2,0 F/ F. - PI -2,0 F/ F. --PI 2,0 F/ F. --PI -2,0 F/ F. + PI 2,0 F/ F. + PI -2,0 F/ F. +-PI 2,0 F/ F. +-PI -2,0 F/ F. 32768,0 1,0 F* F. ; overflow! --> 32768,0 1,0 F/ F. ; overflow! --> -32768,0 -1,0 F* F. ; overflow! --> -32768,0 -1,0 F/ F. ; overflow! --> -32767,99999 1,0 F* F. -32767,99999 1,0 F/ F. -32767,99999 2,0 F/ F. -32767,99999 4,0 F/ F. -32767,99999 8,0 F/ F. -32767,99999 16,0 F/ F. - --32768,0 -2,0 F/ F. --32768,0 -4,0 F/ F. --32768,0 -8,0 F/ F. --32768,0 -16,0 F/ F. --32768,0 -32,0 F/ F. --32768,0 -64,0 F/ F. - --3276,80 -1,0 F/ F. --327,680 -1,0 F/ F. --32,7680 -1,0 F/ F. --3,27680 -1,0 F/ F. --0,32768 -1,0 F/ F. +32767,99999 1,0 F* F. +32767,99999 1,0 F/ F. +32767,99999 2,0 F/ F. +32767,99999 4,0 F/ F. +32767,99999 8,0 F/ F. +32767,99999 16,0 F/ F. + +-32768,0 -2,0 F/ F. +-32768,0 -4,0 F/ F. +-32768,0 -8,0 F/ F. +-32768,0 -16,0 F/ F. +-32768,0 -32,0 F/ F. +-32768,0 -64,0 F/ F. + +-3276,80 -1,0 F/ F. +-327,680 -1,0 F/ F. +-32,7680 -1,0 F/ F. +-3,27680 -1,0 F/ F. +-0,32768 -1,0 F/ F. ; SQRT(32768)^2 = 32768 - 181,01933598375 181,01933598375 F* F. + 181,01933598375 181,01933598375 F* F. 181,01933598375 -181,01933598375 F* F. -181,01933598375 181,01933598375 F* F. -181,01933598375 -181,01933598375 F* F. - -RST_STATE + +RST_RET diff --git a/MSP430-FORTH/LAST.4TH b/MSP430-FORTH/LAST.4TH deleted file mode 100644 index 358d913..0000000 --- a/MSP430-FORTH/LAST.4TH +++ /dev/null @@ -1,562 +0,0 @@ - -; --------------------------------- -; FF_SPECS.4th for MSP_EXP430FR5994 -; --------------------------------- - -CODE ABORT_FF_SPECS -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_FF_SPECS - -[UNDEFINED] AND [IF] -CODE AND -AND @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] -CODE 0< -ADD R14,R14 -SUBC R14,R14 -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] -CODE BEGIN - MOV #$4028,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] UNTIL [IF] -CODE UNTIL - MOV #$4034,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE AGAIN -MOV #$403A,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] WHILE [IF] -: WHILE -POSTPONE IF SWAP -; IMMEDIATE -[THEN] - -[UNDEFINED] REPEAT [IF] -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2* [IF] -CODE 2* -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0<> IF - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - THEN - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] WORDS [IF] -: WORDS -CR -$1DCA @ $1CE4 -$1810 @ 2* -MOVE -BEGIN - 0 DUP - $1810 @ 2* 0 - DO - DUP I $1CE4 + @ - U< IF - DROP DROP - I DUP $1CE4 + @ - THEN - 2 +LOOP - ?DUP -WHILE - DUP - 2 - @ - ROT - $1CE4 + - ! - DUP - COUNT $7F AND - TYPE - C@ $0F AND - $10 SWAP - SPACES -REPEAT -DROP -; -[THEN] - -[UNDEFINED] CASE [IF] -: CASE 0 ; IMMEDIATE - -: OF -1+ ->R -POSTPONE OVER POSTPONE = -POSTPONE IF -POSTPONE DROP -R> -; IMMEDIATE - -: ENDOF ->R -POSTPONE ELSE -R> -; IMMEDIATE - -: ENDCASE -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] S_ [IF] -CODE S_ -MOV #0,&$1DB4 -COLON -$4014 , -$20 WORD -HI2LO -MOV.B @R14,R14 -ADD #1,R14 -BIT #1,R14 -ADDC R14,&$1DC6 -MOV @R15+,R14 -MOV @R1+,R13 -MOV #$20,&$1DB4 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&$1DBE -0= IF MOV @R13+,R0 -THEN -COLON -$1B -POSTPONE LITERAL -POSTPONE EMIT -POSTPONE S_ -POSTPONE TYPE -; IMMEDIATE -[THEN] - -: SPECS -PWR_STATE -ECHO -ESC [8;40;80t -39 0 DO CR LOOP -ESC [H -ESC [7m -$0D EMIT ." FastForth V" -$180E @ -0 <# # $08 HOLD # '.' HOLD #S #> TYPE -." for MSP430FR" -HERE -$1A04 @ -CASE - $8102 OF ." 5738," $C200 ENDOF - $8103 OF ." 5739," $C200 ENDOF - $8160 OF ." 5948," $4400 ENDOF - $8169 OF ." 5969," $4400 ENDOF - $825D OF ." 5972," $4400 ENDOF - $81A8 OF ." 6989," $4400 ENDOF - $810D OF ." 5986," $4400 ENDOF - $81F0 OF ." 4133," $C400 ENDOF - $8240 OF ." 2433," $C400 ENDOF - $82A1 OF ." 5994," $4000 ENDOF - $82A6 OF ." 5962," $4000 ENDOF - $830C OF ." 2355," $8000 ENDOF - $830D OF ." 2353," $C000 ENDOF - $831E OF ." 2155," $8000 ENDOF - $831D OF ." 2153," $C000 ENDOF - $832A OF ." 2476," $8000 ENDOF - $832B OF ." 2475," $8000 ENDOF - $833C OF ." 2633," $C400 ENDOF - $833D OF ." 2533," $C400 ENDOF - ABORT" xxxx <-- unrecognized device!" -ENDCASE -['] ['] DUP @ $1284 = -IF ." DTC=1," DROP -ELSE 2 + @ $1284 = - IF ." DTC=2," - ELSE ." DTC=3," - THEN -THEN -$20 EMIT -$1810 @ U. $08 EMIT ." -Entry word set, " -$1800 @ 0 1000 UM/MOD U. -?DUP IF $08 EMIT ',' EMIT U. -THEN ." MHz, " -- U. ." bytes" -ESC [0m -CR -." /COUNTED-STRING = 255" CR -." /HOLD = 34" CR -." /PAD = 84" CR -." ADDRESS-UNIT-BITS = 16" CR -." FLOORED = true" CR -." MAX-CHAR = 255" CR -." MAX-N = 32767" CR -." MAX-U = 65535" CR -." MAX-D = 2147483647" CR -." MAX-UD = 4294967295" CR -." STACK-CELLS = 48" CR -." RETURN-STACK-CELLS= 48" CR -." DeFiNiTiOnS aRe CaSe-InSeNsItIvE" CR -CR -ESC [7m ." KERNEL SPECS" ESC [0m -CR -$1812 @ - DUP 0< IF ." 32.768kHz XTAL" CR THEN -2* DUP 0< IF ." (4/2) UART TERMINAL" CR 2* - ELSE 2* DUP - 0< IF ." (RTS) UART TERMINAL" CR - THEN - THEN -2* DUP 0< IF ." (XON/XOFF) UART TERMINAL" CR - THEN -2* DUP 0< IF ." Half-Duplex TERMINAL" CR THEN -2* DUP 0< IF ." I2C_Master TERMINAL" CR THEN -2* DUP 0< IF ." Q15.16 input" CR THEN -2* DUP 0< IF ." DOUBLE input" CR THEN -2* DUP 0< IF ." MSP430_X assembler" CR 2* 2* - ELSE 2* DUP - 0< IF ." MSP430 Assembler" - 2* DUP 0< IF ." with 20bits address" - THEN CR - ELSE 2* - THEN - THEN -2* -2* -2* -2* -2* 0< IF - [DEFINED] DEFER [IF] ." DEFER word set" CR [THEN] - [DEFINED] ALSO [IF] ." VOCABULARY word set" CR [THEN] - [DEFINED] LOAD" [IF] ." SD_CARD Loader" CR [THEN] - [DEFINED] BOOT [IF] ." bootloader" CR [THEN] - [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR [THEN] - CR - ESC [7m ." OPTIONS" ESC [0m - CR - [DEFINED] {CORE_ANS} [IF] ." ANS94 core" CR [THEN] - [DEFINED] {DOUBLE} [IF] ." DOUBLE word set" CR [THEN] - [DEFINED] {TOOLS} [IF] ." UTILITY" CR [THEN] - [DEFINED] {FIXPOINT} [IF] ." Q15.16 ADD SUB MUL DIV" CR [THEN] - [DEFINED] {CORDIC} [IF] ." CORDIC engine" CR [THEN] - [DEFINED] {SD_TOOLS} [IF] ." SD_TOOLS" CR [THEN] - [DEFINED] {RTC} [IF] ." RTC utility" CR [THEN] - [DEFINED] {UARTI2CS} [IF] ." UART to I2C_FastForth bridge" CR [THEN] - [DEFINED] ALSO - [IF] - CR - ESC [7m ." ASSEMBLER word set" ESC [0m - ALSO ASSEMBLER WORDS PREVIOUS - CR - [THEN] -THEN -CR -ESC [7m ." FORTH word set" ESC [0m -WORDS -CR -HI2LO -MOV #WARM+4,R0 -ENDCODE - -SPECS diff --git a/MSP430-FORTH/MSP_EXP430FR5994/BOOT.4th b/MSP430-FORTH/MSP_EXP430FR5994/BOOT.4th deleted file mode 100644 index 62208c3..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/BOOT.4th +++ /dev/null @@ -1,41 +0,0 @@ - -; -------- -; BOOT.4th for MSP_EXP430FR5994 -; -------- - -CODE ABORT_BOOTSTRAP -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_BOOTSTRAP - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -$04 = [IF] - LOAD" SD_TEST.4TH" -[THEN] diff --git a/MSP430-FORTH/MSP_EXP430FR5994/CHNGBAUD.4TH b/MSP430-FORTH/MSP_EXP430FR5994/CHNGBAUD.4TH deleted file mode 100644 index e519753..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/CHNGBAUD.4TH +++ /dev/null @@ -1,429 +0,0 @@ - -CODE I2CTERM_ABORT -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$7800,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" <-- Ouch! unexpected I2C_FastForth target!" -PWR_STATE -; - -I2CTERM_ABORT - -; ------------ -; CHNGBAUD.4th for MSP_EXP430FR5994 -; ------------ - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U/ [IF] -CODE U/ -SUB #2,R15 -MOV #0,0(R15) -CALL #$4066 -MOV @R15,R14 -ADD #4,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 -ELSE - XOR #-1,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] < [IF] -CODE < - SUB @R15+,R14 - S< ?GOTO FW1 - 0<> IF -BW1 MOV #-1,R14 - THEN - MOV @R13+,R0 -ENDCODE - -CODE > - SUB @R15+,R14 - S< ?GOTO BW1 -FW1 AND #0,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] CASE [IF] -: CASE 0 ; IMMEDIATE - -: OF -1+ ->R -POSTPONE OVER POSTPONE = -POSTPONE IF -POSTPONE DROP -R> -; IMMEDIATE - -: ENDOF ->R -POSTPONE ELSE -R> -; IMMEDIATE - -: ENDCASE -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] S_ [IF] -CODE S_ -MOV #0,&$1DB4 -COLON -$4014 , -$20 WORD -HI2LO -MOV.B @R14,R14 -ADD #1,R14 -BIT #1,R14 -ADDC R14,&$1DC6 -MOV @R15+,R14 -MOV @R1+,R13 -MOV #$20,&$1DB4 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&$1DBE -0= IF MOV @R13+,R0 -THEN -COLON -$1B -POSTPONE LITERAL -POSTPONE EMIT -POSTPONE S_ -POSTPONE TYPE -; IMMEDIATE -[THEN] - -: BAD_MHz -$20 DUP EMIT - ABORT" only for 1,4,8,16,24 MHz MCLK!" -; - -: OVR_BAUDS -$20 DUP EMIT ESC [7m - ." with MCLK = " $1800 @ 1000 U/ . - ABORT" MHz? don't dream!" -; - -: CHNGBAUD -PWR_STATE -ECHO -ESC [8;42;128t -41 0 DO CR LOOP -ESC [H - -$1800 @ DUP >R -." target MCLK = " 1000 U/ . ." MHz" CR -." choose your baudrate:" CR -." 0 --> 6 MBds" CR -." 1 --> 5 MBds" CR -." 2 --> 4 MBds" CR -." 3 --> 3 MBds" CR -." 4 --> 1843200 Bds" CR -." 5 --> 921600 Bds" CR -." 6 --> 460800 Bds" CR -." 7 --> 230400 Bds" CR -." 8 --> 115200 Bds" CR -." 9 --> 38400 Bds" CR -." A --> 19200 Bds" CR -." B --> 9600 Bds" CR -." other --> abort" CR -." your choice: " -KEY - -CASE -#48 OF ." 6 MBds" - R> CASE - #24000 OF $4 $0 - ENDOF - 24000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#49 OF ." 5 MBds" - R> CASE - #24000 OF $4 $EE00 ENDOF - #20000 OF $4 $0 ENDOF - 20000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#50 OF ." 4 MBds" - R> CASE - #24000 OF $6 $0 ENDOF - #20000 OF $5 $0 ENDOF - #16000 OF $4 $0 ENDOF - 16000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#51 OF ." 3 MBds" - R> CASE - #24000 OF $8 $0 ENDOF - #20000 OF $6 $D600 ENDOF - #16000 OF $5 $4900 ENDOF - #12000 OF $4 $0 ENDOF - 12000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#52 OF ." 1843200 Bds" - R> CASE - #24000 OF $0D $0200 ENDOF - #20000 OF $0A $DF00 ENDOF - #16000 OF $8 $D600 ENDOF - #12000 OF $6 $AA00 ENDOF - #8000 OF $5 $9200 ENDOF - 8000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#53 OF ." 921600 Bds" - R> CASE - #24000 OF $1 $00A1 ENDOF - #20000 OF $1 $B751 ENDOF - #16000 OF $11 $4A00 ENDOF - #12000 OF $0D $0200 ENDOF - #8000 OF $8 $D600 ENDOF - #4000 OF $4 $4900 ENDOF - 4000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#54 OF ." 460800 Bds" - R> CASE - #24000 OF $3 $0241 ENDOF - #20000 OF $2 $92B1 ENDOF - #16000 OF $2 $BB21 ENDOF - #12000 OF $1 $00A1 ENDOF - #8000 OF $11 $4A00 ENDOF - #4000 OF $8 $D600 ENDOF - #2000 OF $4 $4900 ENDOF - 2000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#55 OF ." 230400 Bds" - R> CASE - #24000 OF $6 $2081 ENDOF - #20000 OF $5 $EE61 ENDOF - #16000 OF $4 $5551 ENDOF - #12000 OF $3 $0241 ENDOF - #8000 OF $2 $BB21 ENDOF - #4000 OF $11 $4A00 ENDOF - #2000 OF $8 $D600 ENDOF - #1000 OF $4 $4900 ENDOF - 1000 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#56 OF ." 115200 Bds" - R> CASE - #24000 OF $0D $4901 ENDOF - #20000 OF $0A $AD01 ENDOF - #16000 OF $8 $F7A1 ENDOF - #12000 OF $6 $2081 ENDOF - #8000 OF $4 $5551 ENDOF - #4000 OF $2 $BB21 ENDOF - #2000 OF $11 $4A00 ENDOF - #1000 OF $8 $D600 ENDOF - #500 OF $4 $4900 ENDOF - 500 < - IF OVR_BAUDS - THEN BAD_MHz - ENDCASE - ENDOF -#57 OF ." 38400 Bds" - R> CASE - #24000 OF $27 $0011 ENDOF - #16000 OF $1A $D601 ENDOF - #8000 OF $0D $4901 ENDOF - #4000 OF $6 $2081 ENDOF - #1000 OF $1 $00A1 ENDOF - BAD_MHz - ENDCASE - ENDOF -#65 OF ." 19200 Bds" - R> CASE - #24000 OF $4E $0021 ENDOF - #16000 OF $34 $4911 ENDOF - #8000 OF $1A $D601 ENDOF - #4000 OF $0D $4901 ENDOF - #1000 OF $3 $0241 ENDOF - BAD_MHz - ENDCASE - ENDOF -#66 OF ." 9600 Bds" - R> CASE - #24000 OF $9C $0041 ENDOF - #16000 OF $68 $D621 ENDOF - #8000 OF $34 $4911 ENDOF - #4000 OF $1A $D601 ENDOF - #1000 OF $6 $2081 ENDOF - BAD_MHz - ENDCASE - ENDOF - ." abort" ABORT" " -ENDCASE -$1804 ! -$1802 ! -CR ESC [7m -." Change baudrate in Teraterm, save its setup, then reset target." -; - -CHNGBAUD diff --git a/MSP430-FORTH/MSP_EXP430FR5994/CORDIC.4TH b/MSP430-FORTH/MSP_EXP430FR5994/CORDIC.4TH deleted file mode 100644 index 8c042b2..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/CORDIC.4TH +++ /dev/null @@ -1,505 +0,0 @@ - -CODE ABORT_CORDIC -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$400,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" build FastForth with FIXPOINT_INPUT addon !" -PWR_STATE -; - -ABORT_CORDIC - -; ---------- -; CORDIC.4th for MSP_EXP430FR5994 -; ---------- - -[DEFINED] {CORDIC} [IF] {CORDIC} [THEN] - -MARKER {CORDIC} - - - -CREATE T_ARCTAN -12870 , -7598 , -4014 , -2038 , -1023 , -512 , -256 , -128 , -64 , -32 , -16 , -8 , -4 , -2 , -1 , - -CREATE T_SCALE -46340 , -41448 , -40211 , -39900 , -39822 , -39803 , -39798 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , -39797 , - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] -CODE DABS -AND #-1,R14 -S< IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HOLDS [IF] -CODE HOLDS - MOV @R15+,R9 -BW3 ADD R14,R9 - MOV &$1DB2,R8 -BEGIN SUB #1,R9 - SUB #1,R14 -U>= WHILE SUB #1,R8 - MOV.B @R9,0(R8) -REPEAT MOV R8,&$1DB2 - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -$81EF $1A04 @ U< -$1A04 @ $81F3 U< -= [IF] ; MSP430FR413x subfamily without hardware_MPY - -[UNDEFINED] F#S [IF] -CODE F#S - MOV @R15,R12 - MOV #0,R11 - PUSHM #3,R13 - MOV 2(R15),0(R15) - MOV R14,2(R15) -BEGIN MOV &$1DDC,R14 - LO2HI - UM* - HI2LO - CMP #10,R14 - U>= IF ADD #7,R14 - THEN ADD #$30,R14 - MOV @R1,R11 - MOV.B R14,$1D90(R11) - ADD #1,R11 - MOV R11,0(R1) - CMP 2(R15),R11 -U>= UNTIL POPM #3,R13 - MOV R11,R14 - MOV R12,2(R15) - MOV #0,0(R15) - MOV #$1D90,R9 - GOTO BW3 -ENDCODE -[THEN] - -HDNCODE XSCALE - MOV T_SCALE(R10),R6 -UMSTAR1 MOV #0,R8 - MOV #0,R12 - MOV #0,R11 - MOV #1,R10 -BEGIN BIT R10,R6 - 0<> IF ADD R9,R12 - ADDC R8,R11 - THEN ADD R9,R9 - ADDC R8,R8 - ADD R10,R10 -U>= UNTIL - MOV R11,R9 - MOV #$40E2,R6 - MOV @R1+,R0 -ENDCODE - -[ELSE] ; hardware multiplier - -[UNDEFINED] F#S [IF] -CODE F#S - MOV 2(R15),R9 - MOV @R15,2(R15) - MOV R9,0(R15) - MOV R14,R11 - MOV #0,R12 -BEGIN MOV @R15,&$4C0 - MOV &$1DDC,&$4C8 - MOV &$4E4,0(R15) - MOV &$4E6,R14 - CMP #10,R14 - U>= IF ADD #7,R14 - THEN ADD #$30,R14 - MOV.B R14,$1D90(R12) - ADD #1,R12 - CMP R11,R12 -0= UNTIL MOV R11,R14 - MOV #0,0(R15) - MOV #$1D90,R9 - GOTO BW3 -ENDCODE -[THEN] - -HDNCODE XSCALE -MOV T_SCALE(R10),&$4D4 -MOV #0,&$4D6 -MOV R9,&$4C8 -MOV &$4E6,R9 -MOV @R1+,R0 -ENDCODE - -[THEN] ; end of hardware multiplier - -CODE POL2REC -PUSH R13 -MOV @R15+,&$4D0 -MOV R14,&$4D2 -MOV #286,&$4C8 -MOV &$4E4,R8 -MOV &$4E6,R14 -MOV #-1,R13 -MOV @R15,R9 -MOV #0,R8 -BEGIN - ADD #1,R13 - MOV R9,R12 - MOV R8,R11 - MOV #0,R10 - GOTO FW1 - BEGIN - RRA R12 - RRA R11 - ADD #1,R10 -FW1 CMP R13,R10 - 0= UNTIL - ADD R10,R10 - CMP #0,R14 - 0>= IF - SUB R11,R9 - ADD R12,R8 - SUB T_ARCTAN(R10),R14 - ELSE - ADD R11,R9 - SUB R12,R8 - ADD T_ARCTAN(R10),R14 - THEN - CMP #0,R14 - 0<> WHILE - CMP #14,R13 -0= UNTIL - THEN -CALL #XSCALE -MOV R9,0(R15) -MOV R8,R9 -CALL #XSCALE -MOV R9,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE - - -CODE REC2POL -MOV @R15,R9 -MOV R14,R8 -MOV R8,R11 -CMP #0,R11 -S< IF - XOR #-1,R11 - ADD #1,R11 -THEN -MOV R9,R12 -CMP #0,R12 -S< IF - XOR #-1,R12 - ADD #1,R12 -THEN -MOV #-1,R14 -CMP #0,R9 -0= IF - CMP #0,R8 - 0= IF - LO2HI - ABORT" null inputs!" - HI2LO - THEN -THEN -CMP R12,R11 -U< IF - MOV R12,R11 -THEN -CMP #16384,R11 - U>= IF - LO2HI - ABORT" |x| or |y| >= 16384" - HI2LO - THEN -MOV #1,R12 -RLAM #3,R11 -GOTO FW1 -BEGIN - ADD R9,R9 - ADD R8,R8 - ADD R12,R12 - ADD R11,R11 -FW1 -U>= UNTIL -PUSHM #2,R13 -MOV #-1,R13 -MOV #0,R14 - BEGIN - ADD #1,R13 - MOV R9,R12 - MOV R8,R11 - MOV #0,R10 - GOTO FW1 - BEGIN - RRA R12 - RRA R11 - ADD #1,R10 -FW1 CMP R13,R10 - 0= UNTIL - ADD R10,R10 - CMP #0,R8 - S>= IF - ADD R11,R9 - SUB R12,R8 - ADD T_ARCTAN(R10),R14 - ELSE - SUB R11,R9 - ADD R12,R8 - SUB T_ARCTAN(R10),R14 - THEN - CMP #0,R8 - 0<> WHILE - CMP #14,R13 - 0= UNTIL - THEN -CALL #XSCALE -POPM #2,R13 -GOTO FW1 -BEGIN - RRA R9 -FW1 RRA R12 -U>= UNTIL -MOV R9,0(R15) - -SUB #4,R15 -MOV R14,R6 -CMP #0,R6 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -MOV #0,2(R15) -MOV R14,0(R15) -MOV #286,R14 -CALL #$4066 -MOV @R15+,0(R15) -CMP #0,R6 -S< IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 -THEN -MOV #$40E2,R6 -MOV @R13+,R0 -ENDCODE - - -[UNDEFINED] F. [IF] -CODE F. -MOV R14,R12 -MOV #4,R11 -MOV &$1DDC,R10 -CMP ##10,R10 -0= IF - ADD #1,R11 -ELSE - CMP #%10,R10 - 0= IF - MOV #16,R11 - THEN -THEN -PUSHM #3,R13 -LO2HI - <# DABS - R> F#S - $2C HOLD - #S - R> SIGN #> - TYPE $20 EMIT -; - -[THEN] - -PWR_HERE - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -ECHO - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -; ----------------------------------------------------------- -; requires FIXPOINT_INPUT kernel addon, see forthMSP430FR.asm -; ----------------------------------------------------------- - - -10000 89,0 POL2REC . . ; sin, cos --> -10000 75,0 POL2REC . . ; sin, cos --> -10000 60,0 POL2REC . . ; sin, cos --> -10000 45,0 POL2REC . . ; sin, cos --> -10000 30,0 POL2REC . . ; sin, cos --> -10000 15,0 POL2REC . . ; sin, cos --> -10000 1,0 POL2REC . . ; sin, cos --> -16384 30,0 POL2REC SWAP . . ; x, y --> -16384 45,0 POL2REC SWAP . . ; x, y --> -16384 60,0 POL2REC SWAP . . ; x, y --> - -10000 -89,0 POL2REC . . ; sin, cos --> -10000 -75,0 POL2REC . . ; sin, cos --> -10000 -60,0 POL2REC . . ; sin, cos --> -10000 -45,0 POL2REC . . ; sin, cos --> -10000 -30,0 POL2REC . . ; sin, cos --> -10000 -15,0 POL2REC . . ; sin, cos --> -10000 -1,0 POL2REC . . ; sin, cos --> -16384 -30,0 POL2REC SWAP . . ; x, y --> -16384 -45,0 POL2REC SWAP . . ; x, y --> -16384 -60,0 POL2REC SWAP . . ; x, y --> - --10000 89,0 POL2REC . . ; sin, cos --> --10000 75,0 POL2REC . . ; sin, cos --> --10000 60,0 POL2REC . . ; sin, cos --> --10000 45,0 POL2REC . . ; sin, cos --> --10000 30,0 POL2REC . . ; sin, cos --> --10000 15,0 POL2REC . . ; sin, cos --> --10000 1,0 POL2REC . . ; sin, cos --> --16384 30,0 POL2REC SWAP . . ; x, y --> --16384 45,0 POL2REC SWAP . . ; x, y --> --16384 60,0 POL2REC SWAP . . ; x, y --> - --10000 -89,0 POL2REC . . ; sin, cos --> --10000 -75,0 POL2REC . . ; sin, cos --> --10000 -60,0 POL2REC . . ; sin, cos --> --10000 -45,0 POL2REC . . ; sin, cos --> --10000 -30,0 POL2REC . . ; sin, cos --> --10000 -15,0 POL2REC . . ; sin, cos --> --10000 -1,0 POL2REC . . ; sin, cos --> --16384 -30,0 POL2REC SWAP . . ; x, y --> --16384 -45,0 POL2REC SWAP . . ; x, y --> --16384 -60,0 POL2REC SWAP . . ; x, y --> - - -2 1 REC2POL F. . ; phase module --> -2 -1 REC2POL F. . ; phase module --> -20 10 REC2POL F. . ; phase module --> -20 -10 REC2POL F. . ; phase module --> -200 100 REC2POL F. . ; phase module --> -100 -100 REC2POL F. . ; phase module --> -2000 1000 REC2POL F. . ; phase module --> -1000 -1000 REC2POL F. . ; phase module --> -16000 8000 REC2POL F. . ; phase module --> -16000 -8000 REC2POL F. . ; phase module --> -16000 0 REC2POL F. . ; phase module --> -0 16000 REC2POL F. . ; phase module --> - --2 1 REC2POL F. . ; phase module --> --2 -1 REC2POL F. . ; phase module --> --20 10 REC2POL F. . ; phase module --> --20 -10 REC2POL F. . ; phase module --> --200 100 REC2POL F. . ; phase module --> --100 -100 REC2POL F. . ; phase module --> --2000 1000 REC2POL F. . ; phase module --> --1000 -1000 REC2POL F. . ; phase module --> --16000 8000 REC2POL F. . ; phase module --> --16000 -8000 REC2POL F. . ; phase module --> -16000 0 REC2POL F. . ; phase module --> -0 16000 REC2POL F. . ; phase module --> - -10000 89,0 POL2REC REC2POL ROT . F. -10000 75,0 POL2REC REC2POL ROT . F. -10000 60,0 POL2REC REC2POL ROT . F. -10000 45,0 POL2REC REC2POL ROT . F. -10000 30,0 POL2REC REC2POL ROT . F. -10000 26,565 POL2REC REC2POL ROT . F. -10000 15,0 POL2REC REC2POL ROT . F. -10000 14,036 POL2REC REC2POL ROT . F. -10000 7,125 POL2REC REC2POL ROT . F. -10000 1,0 POL2REC REC2POL ROT . F. - - diff --git a/MSP430-FORTH/MSP_EXP430FR5994/CORE_ANS.4TH b/MSP430-FORTH/MSP_EXP430FR5994/CORE_ANS.4TH deleted file mode 100644 index b8f35fd..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/CORE_ANS.4TH +++ /dev/null @@ -1,1046 +0,0 @@ - -CODE ABORT_CORE_ANS -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_CORE_ANS - -; --------------------------------- -; CORE_ANS.4th for MSP_EXP430FR5994 -; --------------------------------- -; words complement to pass CORETEST.4TH - -[DEFINED] {CORE_ANS} [IF] {CORE_ANS} [THEN] - -[UNDEFINED] {CORE_ANS} [IF] - -MARKER {CORE_ANS} - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] EXIT [IF] -CODE EXIT -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] -CODE DEPTH -MOV R14,-2(R15) -MOV #$1C80,R14 -SUB R15,R14 -RRA R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] NIP [IF] -CODE NIP -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] @ [IF] -CODE @ -MOV @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ! [IF] -CODE ! -MOV @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C! [IF] -CODE C! -MOV.B @R15+,0(R14) -ADD #1,R15 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C, [IF] -CODE C, -MOV &$1DC6,R10 -MOV.B R14,0(R10) -ADD #1,&$1DC6 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] -CODE 0< -ADD R14,R14 -SUBC R14,R14 -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] < [IF] -CODE < - SUB @R15+,R14 - S< ?GOTO FW1 - 0<> IF -BW1 MOV #-1,R14 - THEN - MOV @R13+,R0 -ENDCODE - -CODE > - SUB @R15+,R14 - S< ?GOTO BW1 -FW1 AND #0,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] -CODE BEGIN - MOV #$4028,R0 -ENDCODE IMMEDIATE - -CODE UNTIL - MOV #$4034,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE AGAIN -MOV #$403A,R9 -GOTO BW1 -ENDCODE IMMEDIATE - -: WHILE -POSTPONE IF SWAP -; IMMEDIATE - -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] J [IF] -CODE J -SUB #2,R15 -MOV R14,0(R15) -MOV 4(R1),R14 -SUB 6(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UNLOOP [IF] -CODE UNLOOP -ADD #4,R1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] LEAVE [IF] -CODE LEAVE -MOV &$1DC6,R10 -MOV #UNLOOP,0(R10) -MOV #$403A,2(R10) -ADD #6,&$1DC6 -ADD #2,&$1C00 -ADD #4,R10 -MOV &$1C00,R9 -MOV R10,0(R9) -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] AND [IF] -CODE AND -AND @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OR [IF] -CODE OR -BIS @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] XOR [IF] -CODE XOR -XOR @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] S>D [IF] -: S>D - DUP 0< -; -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1- [IF] -CODE 1- -SUB #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] INVERT [IF] -CODE INVERT -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] NEGATE [IF] -CODE NEGATE -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ABS [IF] -CODE ABS -CMP #0,R14 -0>= IF - MOV @R13+,R0 -THEN -MOV #NEGATE,R0 -ENDCODE -[THEN] - -[UNDEFINED] LSHIFT [IF] -CODE LSHIFT - MOV @R15+,R10 - AND #$1F,R14 -0<> IF - BEGIN ADD R10,R10 - SUB #1,R14 - 0= UNTIL -THEN MOV R10,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] RSHIFT [IF] -CODE RSHIFT - MOV @R15+,R10 - AND #$1F,R14 -0<> IF - BEGIN BIC #1,R2 - RRC R10 - SUB #1,R14 - 0= UNTIL -THEN MOV R10,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] -CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 -ENDCODE - -CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[THEN] - -[UNDEFINED] 2* [IF] -CODE 2* -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2/ [IF] -CODE 2/ -RRA R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -$1A00 4 + @ $81F3 U< -$81EF $1A00 4 + @ U< -= [IF] ; MSP430FR2xxx|MSP430FR4xxx subfamilies without hardware_MPY - - [UNDEFINED] M* [IF] - - - - CODE M* - MOV @R15,R12 - CMP #0,R12 - S< IF - XOR #-1,0(R15) - ADD #1,0(R15) - THEN - XOR R14,R12 - CMP #0,R14 - S< IF - XOR #-1,R14 - ADD #1,R14 - THEN - PUSHM #2,R13 - LO2HI - UM* - HI2LO - POPM #2,R13 - CMP #0,R12 - S< IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 - THEN - MOV @R13+,R0 - ENDCODE - [THEN] - -[ELSE] ; MSP430FRxxxx with hardware_MPY - -[UNDEFINED] UM* [IF] -CODE UM* - MOV @R15,&$4C0 -BW1 MOV R14,&$4C8 - MOV &$4E4,0(R15) - MOV &$4E6,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] M* [IF] -CODE M* - MOV @R15,&$4C2 - GOTO BW1 -ENDCODE -[THEN] - -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] SM/REM [IF] -CODE SM/REM -MOV R14,R12 -MOV @R15,R11 -CMP #0,R14 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -CMP #0,0(R15) -S< IF - XOR #-1,2(R15) - XOR #-1,0(R15) - ADD #1,2(R15) - ADDC #0,0(R15) -THEN -PUSHM #3,R13 -LO2HI - UM/MOD -HI2LO -POPM #3,R13 -CMP #0,R11 -S< IF - XOR #-1,0(R15) - ADD #1,0(R15) -THEN -XOR R12,R11 -CMP #0,R11 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] FM/MOD [IF] -: FM/MOD -SM/REM -HI2LO -CMP #0,0(R15) -0<> IF - CMP #1,R14 - S< IF - ADD R12,0(R15) - SUB #1,R14 - THEN -THEN -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] * [IF] -: * -M* DROP -; -[THEN] - -[UNDEFINED] /MOD [IF] -: /MOD ->R DUP 0< R> FM/MOD -; -[THEN] - -[UNDEFINED] / [IF] -: / ->R DUP 0< R> FM/MOD NIP -; -[THEN] - -[UNDEFINED] MOD [IF] -: MOD ->R DUP 0< R> FM/MOD DROP -; -[THEN] - -[UNDEFINED] */MOD [IF] -: */MOD ->R M* R> FM/MOD -; -[THEN] - -[UNDEFINED] */ [IF] -: */ ->R M* R> FM/MOD NIP -; -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R@ [IF] -CODE R@ -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] TUCK [IF] -: TUCK SWAP OVER ; -[THEN] - -[UNDEFINED] 2@ [IF] -CODE 2@ -BW1 SUB #2,R15 - MOV 2(R14),0(R15) - MOV @R14,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2! [IF] -CODE 2! -BW2 MOV @R15+,0(R14) - MOV @R15+,2(R14) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DUP [IF] -CODE 2DUP -MOV R14,-2(R15) -MOV @R15,-4(R15) -SUB #4,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DROP [IF] -CODE 2DROP -ADD #2,R15 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2SWAP [IF] -CODE 2SWAP -MOV @R15,R10 -MOV 4(R15),0(R15) -MOV R10,4(R15) -MOV R14,R10 -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2OVER [IF] -CODE 2OVER -SUB #4,R15 -MOV R14,2(R15) -MOV 8(R15),0(R15) -MOV 6(R15),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] ALIGNED [IF] -CODE ALIGNED -BIT #1,R14 -ADDC #0,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ALIGN [IF] -CODE ALIGN -BIT #1,&$1DC6 -ADDC #0,&$1DC6 -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] CHARS [IF] -CODE CHARS -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CHAR+ [IF] -CODE CHAR+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CELLS [IF] -CODE CELLS -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CELL+ [IF] -CODE CELL+ -ADD #2,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] CHAR [IF] -: CHAR - $20 WORD 1+ C@ -; -[THEN] - -[UNDEFINED] [CHAR] [IF] -: [CHAR] - CHAR POSTPONE LITERAL -; IMMEDIATE -[THEN] - -[UNDEFINED] +! [IF] -CODE +! -ADD @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0<> IF - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - THEN - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] FILL [IF] -CODE FILL -MOV @R15+,R9 -MOV @R15+,R10 -CMP #0,R9 -0<> IF - BEGIN - MOV.B R14,0(R10) - ADD #1,R10 - SUB #1,R9 - 0= UNTIL -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - - -[UNDEFINED] HEX [IF] -CODE HEX -MOV #$10,&$1DDC -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DECIMAL [IF] -CODE DECIMAL -MOV #$0A,&$1DDC -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ( [IF] -: ( -')' WORD DROP -; IMMEDIATE -[THEN] - -[UNDEFINED] .( [IF] -CODE .( -MOV #0,&$1DB4 -COLON -')' WORD -COUNT TYPE -$20 $1DB4 ! -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] EXECUTE [IF] -CODE EXECUTE -PUSH R14 -MOV @R15+,R14 -MOV @R1+,R0 -ENDCODE -[THEN] - -[UNDEFINED] EVALUATE [IF] -CODE EVALUATE -MOV #$1DC0,R9 -MOV @R9+,R12 -MOV @R9+,R11 -MOV @R9+,R10 -PUSHM #4,R13 -LO2HI -INTERPRET -HI2LO -MOV @R1+,&$1DC4 -MOV @R1+,&$1DC2 -MOV @R1+,&$1DC0 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] RECURSE [IF] -CODE RECURSE -MOV &$1DC6,R9 -MOV &$1DBA,0(R9) -ADD #2,&$1DC6 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] SOURCE [IF] -CODE SOURCE -SUB #4,R15 -MOV R14,2(R15) -MOV &$1DC0,R14 -MOV &$1DC2,0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] -CODE DOES> -MOV &$1DBA,R10 -MOV #$1285,0(R10) -MOV R13,2(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] VARIABLE [IF] -: VARIABLE -CREATE -HI2LO -MOV #$1287,-4(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] BASE [IF] -$1DDC CONSTANT BASE -[THEN] - -[UNDEFINED] >IN [IF] -$1DC4 CONSTANT >IN -[THEN] - -[UNDEFINED] PAD [IF] -$1CE4 CONSTANT PAD -[THEN] - -[UNDEFINED] BL [IF] -$20 CONSTANT BL -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -$20 EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] TO [IF] -CODE TO -BIS #$200,R2 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] VALUE [IF] -: VALUE -CREATE , -DOES> -HI2LO -MOV @R1+,R13 -BIT #$200,R2 -0= IF - MOV @R14,R14 - MOV @R13+,R0 -THEN -BIC #$200,R2 -MOV @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -RST_HERE - -[THEN] - -ECHO -; CORE_ANS.4th for MSP_EXP430FR5994 is loaded diff --git a/MSP430-FORTH/MSP_EXP430FR5994/DOUBLE.4TH b/MSP430-FORTH/MSP_EXP430FR5994/DOUBLE.4TH deleted file mode 100644 index b7f7c4b..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/DOUBLE.4TH +++ /dev/null @@ -1,1435 +0,0 @@ - -CODE ABORT_DOUBLE -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$200,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" build FastForth with DOUBLE_INPUT addon !" -PWR_STATE -; - -ABORT_DOUBLE - -; ----------------------------------------------------- -; DOUBLE.4th for MSP_EXP430FR5994 -; ----------------------------------------------------- - -[DEFINED] {DOUBLE} [IF] {DOUBLE} [THEN] - -MARKER {DOUBLE} - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] @ [IF] -CODE @ -MOV @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ! [IF] -CODE ! -MOV @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] < [IF] -CODE < - SUB @R15+,R14 - S< ?GOTO FW1 - 0<> IF -BW1 MOV #-1,R14 - THEN - MOV @R13+,R0 -ENDCODE - -CODE > - SUB @R15+,R14 - S< ?GOTO BW1 -FW1 AND #0,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] TO [IF] -CODE TO -BIS #$200,R2 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] -CODE DOES> -MOV &$1DBA,R10 -MOV #DODOES,0(R10) -MOV R13,2(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2@ [IF] -CODE 2@ -SUB #2,R15 -MOV 2(R14),0(R15) -MOV @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2! [IF] -CODE 2! -MOV @R15+,0(R14) -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DUP [IF] -CODE 2DUP -SUB #4,R15 -MOV R14,2(R15) -MOV 4(R15),0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DROP [IF] -CODE 2DROP -ADD #2,R15 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2SWAP [IF] -CODE 2SWAP -MOV @R15,R10 -MOV 4(R15),0(R15) -MOV R10,4(R15) -MOV R14,R10 -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2OVER [IF] -CODE 2OVER -SUB #4,R15 -MOV R14,2(R15) -MOV 8(R15),0(R15) -MOV 6(R15),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2>R [IF] -CODE 2>R -PUSH @R15+ -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2R@ [IF] -CODE 2R@ -SUB #4,R15 -MOV R14,2(R15) -MOV @R1,R14 -MOV 2(R1),0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2R> [IF] -CODE 2R> -SUB #4,R15 -MOV R14,2(R15) -MOV @R1+,R14 -MOV @R1+,0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] D. [IF] -CODE D. -MOV #U.,R10 -ADD #10,R10 -MOV R10,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2ROT [IF] -CODE 2ROT -MOV 8(R15),R9 -MOV 6(R15),R8 -MOV 4(R15),8(R15) -MOV 2(R15),6(R15) -MOV @R15,4(R15) -MOV R14,2(R15) -MOV R9,0(R15) -MOV R8,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D>S [IF] -CODE D>S -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D0= [IF] -CODE D0= -CMP #0,R14 -MOV #0,R14 -0= IF - CMP #0,0(R15) - 0= IF - MOV #-1,R14 - THEN -THEN -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D0< [IF] -CODE D0< -CMP #0,R14 -MOV #0,R14 -S< IF - MOV #-1,R14 -THEN -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D= [IF] -CODE D= -CMP R14,2(R15) -MOV #0,R14 -0= IF - CMP @R15,4(R15) - 0= IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D< [IF] -CODE D< -CMP R14,2(R15) -MOV #0,R14 -S< IF - MOV #-1,R14 -THEN -0= IF - CMP @R15,4(R15) - U< IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DU< [IF] -CODE DU< -CMP R14,2(R15) -MOV #0,R14 -U< IF - MOV #-1,R14 -THEN -0= IF - CMP @R15,4(R15) - U< IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D+ [IF] -CODE D+ -BW1 ADD @R15+,2(R15) - ADDC @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] M+ [IF] -CODE M+ -SUB #2,R15 -CMP #0,R14 -MOV R14,0(R15) -MOV #-1,R14 -0>= IF - MOV #0,R14 -THEN -GOTO BW1 -ENDCODE -[THEN] - -[UNDEFINED] D- [IF] -CODE D- -SUB @R15+,2(R15) -SUBC R14,0(R15) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DNEGATE [IF] -CODE DNEGATE -XOR #-1,0(R15) -XOR #-1,R14 -ADD #1,0(R15) -ADDC #0,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] -CODE DABS -CMP #0,R14 -0>= IF - MOV @R13+,R0 -THEN -MOV #DNEGATE,R0 -ENDCODE -[THEN] - -[UNDEFINED] D2/ [IF] -CODE D2/ -RRA R14 -RRC 0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D2* [IF] -CODE D2* -ADD @R15,0(R15) -ADDC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DMAX [IF] -: DMAX -2OVER 2OVER -D< IF - 2>R 2DROP 2R> -ELSE - 2DROP -THEN -; -[THEN] - -[UNDEFINED] DMIN [IF] -: DMIN -2OVER 2OVER -D< IF - 2DROP -ELSE 2>R 2DROP 2R> -THEN -; - -$1A04 C@ $EF > [IF] ; test for MSP430FR413x devices without hardware_MPY - -[UNDEFINED] M*/ [IF] -CODE M*/ -BIC #$200,R2 -CMP #0,2(R15) -S< IF - XOR #-1,4(R15) - XOR #-1,2(R15) - ADD #1,4(R15) - ADDC #0,2(R15) - BIS #$200,R2 -THEN -CMP #0,0(R15) -S< IF - XOR #-1,0(R15) - ADD #1,0(R15) - XOR #$200,R2 -THEN - MOV 4(R15),R8 - MOV 2(R15),R11 - MOV @R15+,R12 - MOV #0,R5 - MOV #0,2(R15) - MOV #0,0(R15) - MOV #0,R10 - MOV #1,R9 -BEGIN BIT R9,R12 - 0<> IF ADD R8,2(R15) - ADDC R11,0(R15) - ADDC R5,R10 - THEN ADD R8,R8 - ADDC R11,R11 - ADDC R5,R5 - ADD R9,R9 -U>= UNTIL -MOV R14,R11 -MOV @R15,R14 -MOV 2(R15),R12 -MOV #32,R5 -CMP #0,R10 -0= IF - MOV R14,R10 - CALL #$4078 -ELSE - CALL #$4080 -THEN -MOV @R15+,0(R15) -BIT #$200,R2 -0<> IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 - BIC #$200,R2 - CMP #0,R10 - 0<> IF - SUB #1,0(R15) - SUBC #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[ELSE] - -[UNDEFINED] M*/ [IF] -CODE M*/ -MOV 4(R15),&$4D4 -MOV 2(R15),&$4D6 -MOV @R15+,&$4C8 -MOV R14,R11 -MOV R0,R0 -MOV &$4E4,R12 -MOV &$4E6,R14 -MOV &$4E8,R10 -BIC #$200,R2 -CMP #0,R10 -S< IF - XOR #-1,R12 - XOR #-1,R14 - XOR #-1,R10 - ADD #1,R12 - ADDC #0,R14 - ADDC #0,R10 - BIS #$200,R2 -THEN -MOV #32,R5 -CMP #0,R10 -0= IF - MOV R14,R10 - CALL #$4078 -ELSE - CALL #$4080 -THEN -MOV @R15+,0(R15) -BIT #$200,R2 -0<> IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 - BIC #$200,R2 - CMP #0,R10 - 0<> IF - SUB #1,0(R15) - SUBC #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[THEN] ; end of software/hardware_MPY - -[UNDEFINED] 2VARIABLE [IF] -: 2VARIABLE -CREATE -HI2LO -ADD #4,&$1DC6 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2CONSTANT [IF] -: 2CONSTANT -CREATE -, , -DOES> -2@ -; -[THEN] - -[UNDEFINED] 2VALUE [IF] -: 2VALUE -CREATE , , -DOES> -HI2LO -MOV @R1+,R13 -BIT #$200,R2 -0= IF - MOV #2@,R0 -THEN -BIC #$200,R2 -MOV #2!,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2LITERAL [IF] -CODE 2LITERAL -BIS #$200,R2 -MOV #LITERAL,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] D.R [IF] -: D.R ->R SWAP OVER DABS <# #S ROT SIGN #> -R> OVER - SPACES TYPE -; -[THEN] - -RST_HERE - -[UNDEFINED] VARIABLE [IF] -: VARIABLE -CREATE -HI2LO -MOV @R1+,R13 -ADD #2,&$1DC6 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CELLS [IF] -CODE CELLS -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ALLOT [IF] -CODE ALLOT -ADD R14,&$1DC6 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] -CODE DEPTH -MOV R14,-2(R15) -MOV #$1C80,R14 -SUB R15,R14 -RRA R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SOURCE [IF] -CODE SOURCE -SUB #4,R15 -MOV R14,2(R15) -MOV &$1DC0,R14 -MOV &$1DC2,0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >IN [IF] -$1DC4 CONSTANT >IN -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CHAR [IF] -: CHAR - $20 WORD 1+ C@ -; -[THEN] - -[UNDEFINED] [CHAR] [IF] -: [CHAR] - CHAR POSTPONE LITERAL -; IMMEDIATE -[THEN] - -[UNDEFINED] 2/ [IF] -CODE 2/ -RRA R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] INVERT [IF] -CODE INVERT -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] RSHIFT [IF] -CODE RSHIFT - MOV @R15+,R10 - AND #$1F,R14 -0<> IF - BEGIN BIC #1,R2 - RRC R10 - SUB #1,R14 - 0= UNTIL -THEN MOV R10,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] -CODE 0< -ADD R14,R14 -SUBC R14,R14 -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] S>D [IF] -: S>D - DUP 0< -; -[THEN] - -[UNDEFINED] 1- [IF] -CODE 1- -SUB #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] SM/REM [IF] -CODE SM/REM -MOV R14,R12 -MOV @R15,R11 -CMP #0,R14 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -CMP #0,0(R15) -S< IF - XOR #-1,2(R15) - XOR #-1,0(R15) - ADD #1,2(R15) - ADDC #0,0(R15) -THEN -PUSHM #3,R13 -LO2HI - UM/MOD -HI2LO -POPM #3,R13 -CMP #0,R11 -S< IF - XOR #-1,0(R15) - ADD #1,0(R15) -THEN -XOR R12,R11 -CMP #0,R11 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] FM/MOD [IF] -: FM/MOD -SM/REM -HI2LO -CMP #0,0(R15) -0<> IF - CMP #1,R14 - S< IF - ADD R12,0(R15) - SUB #1,R14 - THEN -THEN -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] NIP [IF] -CODE NIP -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] / [IF] -: / ->R DUP 0< R> FM/MOD NIP -; -[THEN] - -[UNDEFINED] NEGATE [IF] -CODE NEGATE -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - -[UNDEFINED] CHARS [IF] -CODE CHARS -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0<> IF - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - THEN - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DECIMAL [IF] -CODE DECIMAL -MOV #$0A,&$1DDC -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] BASE [IF] -$1DDC CONSTANT BASE -[THEN] - -[UNDEFINED] ( [IF] -: ( -')' WORD DROP -; IMMEDIATE -[THEN] - -[UNDEFINED] .( [IF] -CODE .( -MOV #0,&$1DB4 -COLON -')' WORD -COUNT TYPE -$20 $1DB4 ! -; IMMEDIATE -[THEN] - - - - - - - - 0 CONSTANT FALSE --1 CONSTANT TRUE - -VARIABLE VERBOSE - FALSE VERBOSE ! - - -VARIABLE ACTUAL-DEPTH -CREATE ACTUAL-RESULTS 20 CELLS ALLOT - -: T{ - ; - -: -> - DEPTH DUP ACTUAL-DEPTH ! - ?DUP IF - 0 DO ACTUAL-RESULTS I CELLS + ! LOOP - THEN ; - -: }T - - DEPTH ACTUAL-DEPTH @ = IF - DEPTH ?DUP IF - 0 DO - ACTUAL-RESULTS I CELLS + @ - = 0= IF TRUE ABORT" INCORRECT RESULT" THEN - LOOP - THEN - ELSE - TRUE ABORT" WRONG NUMBER OF RESULTS" - THEN ; - -: TESTING - SOURCE VERBOSE @ - IF DUP >R TYPE CR R> >IN ! - ELSE >IN ! DROP [CHAR] * EMIT - THEN ; - -ECHO - - -DECIMAL - -0 INVERT CONSTANT 1SD -1SD 1 RSHIFT CONSTANT MAX-INTD -MAX-INTD INVERT CONSTANT MIN-INTD -MAX-INTD 2/ CONSTANT HI-INT -MIN-INTD 2/ CONSTANT LO-INT - - -TESTING interpreter and compiler reading double numbers, with/without prefixes - -T{ 1. -> 1 0 }T -T{ -2. -> -2 -1 }T -T{ : RDL1 3. ; RDL1 -> 3 0 }T -T{ : RDL2 -4. ; RDL2 -> -4 -1 }T - -VARIABLE OLD-DBASE -DECIMAL BASE @ OLD-DBASE ! -T{ #12346789. -> 12346789. }T -T{ #-12346789. -> -12346789. }T -T{ $12aBcDeF. -> 313249263. }T -T{ $-12AbCdEf. -> -313249263. }T -T{ %10010110. -> 150. }T -T{ %-10010110. -> -150. }T -T{ BASE @ OLD-DBASE @ = -> TRUE }T - -16 OLD-DBASE ! 16 BASE ! -T{ #12346789. -> BC65A5. }T -T{ #-12346789. -> -BC65A5. }T -T{ $12aBcDeF. -> 12AbCdeF. }T -T{ $-12AbCdEf. -> -12ABCDef. }T -T{ %10010110. -> 96. }T -T{ %-10010110. -> -96. }T -T{ BASE @ OLD-DBASE @ = -> TRUE }T - -DECIMAL -T{ : dnmp #8327. $-2cbe. %011010111. ; dnmp -> 8327. -11454. 215. }T - -TESTING 2CONSTANT - -T{ 1 2 2CONSTANT 2C1 -> }T -T{ 2C1 -> 1 2 }T -T{ : CD1 2C1 ; -> }T -T{ CD1 -> 1 2 }T -T{ : CD2 2CONSTANT ; -> }T -T{ -1 -2 CD2 2C2 -> }T -T{ 2C2 -> -1 -2 }T -T{ 4 5 2CONSTANT 2C3 IMMEDIATE 2C3 -> 4 5 }T -T{ : CD6 2C3 2LITERAL ; CD6 -> 4 5 }T - - -1SD MAX-INTD 2CONSTANT MAX-2INT -0 MIN-INTD 2CONSTANT MIN-2INT -MAX-2INT 2/ 2CONSTANT HI-2INT -MIN-2INT 2/ 2CONSTANT LO-2INT - -TESTING DNEGATE - -T{ 0. DNEGATE -> 0. }T -T{ 1. DNEGATE -> -1. }T -T{ -1. DNEGATE -> 1. }T -T{ MAX-2INT DNEGATE -> MIN-2INT SWAP 1+ SWAP }T -T{ MIN-2INT SWAP 1+ SWAP DNEGATE -> MAX-2INT }T - -TESTING D+ with small integers - -T{ 0. 5. D+ -> 5. }T -T{ -5. 0. D+ -> -5. }T -T{ 1. 2. D+ -> 3. }T -T{ 1. -2. D+ -> -1. }T -T{ -1. 2. D+ -> 1. }T -T{ -1. -2. D+ -> -3. }T -T{ -1. 1. D+ -> 0. }T - -TESTING D+ with mid range integers - -T{ 0 0 0 5 D+ -> 0 5 }T -T{ -1 5 0 0 D+ -> -1 5 }T -T{ 0 0 0 -5 D+ -> 0 -5 }T -T{ 0 -5 -1 0 D+ -> -1 -5 }T -T{ 0 1 0 2 D+ -> 0 3 }T -T{ -1 1 0 -2 D+ -> -1 -1 }T -T{ 0 -1 0 2 D+ -> 0 1 }T -T{ 0 -1 -1 -2 D+ -> -1 -3 }T -T{ -1 -1 0 1 D+ -> -1 0 }T -T{ MIN-INTD 0 2DUP D+ -> 0 1 }T -T{ MIN-INTD S>D MIN-INTD 0 D+ -> 0 0 }T - -TESTING D+ with large double integers - -T{ HI-2INT 1. D+ -> 0 HI-INT 1+ }T -T{ HI-2INT 2DUP D+ -> 1SD 1- MAX-INTD }T -T{ MAX-2INT MIN-2INT D+ -> -1. }T -T{ MAX-2INT LO-2INT D+ -> HI-2INT }T -T{ HI-2INT MIN-2INT D+ 1. D+ -> LO-2INT }T -T{ LO-2INT 2DUP D+ -> MIN-2INT }T - -TESTING D- with small integers - -T{ 0. 5. D- -> -5. }T -T{ 5. 0. D- -> 5. }T -T{ 0. -5. D- -> 5. }T -T{ 1. 2. D- -> -1. }T -T{ 1. -2. D- -> 3. }T -T{ -1. 2. D- -> -3. }T -T{ -1. -2. D- -> 1. }T -T{ -1. -1. D- -> 0. }T - -TESTING D- with mid-range integers - -T{ 0 0 0 5 D- -> 0 -5 }T -T{ -1 5 0 0 D- -> -1 5 }T -T{ 0 0 -1 -5 D- -> 1 4 }T -T{ 0 -5 0 0 D- -> 0 -5 }T -T{ -1 1 0 2 D- -> -1 -1 }T -T{ 0 1 -1 -2 D- -> 1 2 }T -T{ 0 -1 0 2 D- -> 0 -3 }T -T{ 0 -1 0 -2 D- -> 0 1 }T -T{ 0 0 0 1 D- -> 0 -1 }T -T{ MIN-INTD 0 2DUP D- -> 0. }T -T{ MIN-INTD S>D MAX-INTD 0 D- -> 1 1SD }T - -TESTING D- with large integers - -T{ MAX-2INT MAX-2INT D- -> 0. }T -T{ MIN-2INT MIN-2INT D- -> 0. }T -T{ MAX-2INT HI-2INT D- -> LO-2INT DNEGATE }T -T{ HI-2INT LO-2INT D- -> MAX-2INT }T -T{ LO-2INT HI-2INT D- -> MIN-2INT 1. D+ }T -T{ MIN-2INT MIN-2INT D- -> 0. }T -T{ MIN-2INT LO-2INT D- -> LO-2INT }T - -TESTING D0< D0= - -T{ 0. D0< -> FALSE }T -T{ 1. D0< -> FALSE }T -T{ MIN-INTD 0 D0< -> FALSE }T -T{ 0 MAX-INTD D0< -> FALSE }T -T{ MAX-2INT D0< -> FALSE }T -T{ -1. D0< -> TRUE }T -T{ MIN-2INT D0< -> TRUE }T - -T{ 1. D0= -> FALSE }T -T{ MIN-INTD 0 D0= -> FALSE }T -T{ MAX-2INT D0= -> FALSE }T -T{ -1 MAX-INTD D0= -> FALSE }T -T{ 0. D0= -> TRUE }T -T{ -1. D0= -> FALSE }T -T{ 0 MIN-INTD D0= -> FALSE }T - -TESTING D2* D2/ - -T{ 0. D2* -> 0. D2* }T -T{ MIN-INTD 0 D2* -> 0 1 }T -T{ HI-2INT D2* -> MAX-2INT 1. D- }T -T{ LO-2INT D2* -> MIN-2INT }T - -T{ 0. D2/ -> 0. }T -T{ 1. D2/ -> 0. }T -T{ 0 1 D2/ -> MIN-INTD 0 }T -T{ MAX-2INT D2/ -> HI-2INT }T -T{ -1. D2/ -> -1. }T -T{ MIN-2INT D2/ -> LO-2INT }T - -TESTING D< D= - -T{ 0. 1. D< -> TRUE }T -T{ 0. 0. D< -> FALSE }T -T{ 1. 0. D< -> FALSE }T -T{ -1. 1. D< -> TRUE }T -T{ -1. 0. D< -> TRUE }T -T{ -2. -1. D< -> TRUE }T -T{ -1. -2. D< -> FALSE }T -T{ 0 1 1. D< -> FALSE }T -T{ 1. 0 1 D< -> TRUE }T -T{ 0 -1 1 -2 D< -> FALSE }T -T{ 1 -2 0 -1 D< -> TRUE }T -T{ -1. MAX-2INT D< -> TRUE }T -T{ MIN-2INT MAX-2INT D< -> TRUE }T -T{ MAX-2INT -1. D< -> FALSE }T -T{ MAX-2INT MIN-2INT D< -> FALSE }T -T{ MAX-2INT 2DUP -1. D+ D< -> FALSE }T -T{ MIN-2INT 2DUP 1. D+ D< -> TRUE }T -T{ MAX-INTD S>D 2DUP 1. D+ D< -> TRUE }T - -T{ -1. -1. D= -> TRUE }T -T{ -1. 0. D= -> FALSE }T -T{ -1. 1. D= -> FALSE }T -T{ 0. -1. D= -> FALSE }T -T{ 0. 0. D= -> TRUE }T -T{ 0. 1. D= -> FALSE }T -T{ 1. -1. D= -> FALSE }T -T{ 1. 0. D= -> FALSE }T -T{ 1. 1. D= -> TRUE }T - -T{ 0 -1 0 -1 D= -> TRUE }T -T{ 0 -1 0 0 D= -> FALSE }T -T{ 0 -1 0 1 D= -> FALSE }T -T{ 0 0 0 -1 D= -> FALSE }T -T{ 0 0 0 0 D= -> TRUE }T -T{ 0 0 0 1 D= -> FALSE }T -T{ 0 1 0 -1 D= -> FALSE }T -T{ 0 1 0 0 D= -> FALSE }T -T{ 0 1 0 1 D= -> TRUE }T - -T{ MAX-2INT MIN-2INT D= -> FALSE }T -T{ MAX-2INT 0. D= -> FALSE }T -T{ MAX-2INT MAX-2INT D= -> TRUE }T -T{ MAX-2INT HI-2INT D= -> FALSE }T -T{ MAX-2INT MIN-2INT D= -> FALSE }T -T{ MIN-2INT MIN-2INT D= -> TRUE }T -T{ MIN-2INT LO-2INT D= -> FALSE }T -T{ MIN-2INT MAX-2INT D= -> FALSE }T - -TESTING 2LITERAL 2VARIABLE - -T{ : CD3 [ MAX-2INT ] 2LITERAL ; -> }T -T{ CD3 -> MAX-2INT }T -T{ 2VARIABLE 2V1 -> }T -T{ 0. 2V1 2! -> }T -T{ 2V1 2@ -> 0. }T -T{ -1 -2 2V1 2! -> }T -T{ 2V1 2@ -> -1 -2 }T -T{ : CD4 2VARIABLE ; -> }T -T{ CD4 2V2 -> }T -T{ : CD5 2V2 2! ; -> }T -T{ -2 -1 CD5 -> }T -T{ 2V2 2@ -> -2 -1 }T -T{ 2VARIABLE 2V3 IMMEDIATE 5 6 2V3 2! -> }T -T{ 2V3 2@ -> 5 6 }T -T{ : CD7 2V3 [ 2@ ] 2LITERAL ; CD7 -> 5 6 }T -T{ : CD8 [ 6 7 ] 2V3 [ 2! ] ; 2V3 2@ -> 6 7 }T - -TESTING DMAX DMIN - -T{ 1. 2. DMAX -> 2. }T -T{ 1. 0. DMAX -> 1. }T -T{ 1. -1. DMAX -> 1. }T -T{ 1. 1. DMAX -> 1. }T -T{ 0. 1. DMAX -> 1. }T -T{ 0. -1. DMAX -> 0. }T -T{ -1. 1. DMAX -> 1. }T -T{ -1. -2. DMAX -> -1. }T - -T{ MAX-2INT HI-2INT DMAX -> MAX-2INT }T -T{ MAX-2INT MIN-2INT DMAX -> MAX-2INT }T -T{ MIN-2INT MAX-2INT DMAX -> MAX-2INT }T -T{ MIN-2INT LO-2INT DMAX -> LO-2INT }T - -T{ MAX-2INT 1. DMAX -> MAX-2INT }T -T{ MAX-2INT -1. DMAX -> MAX-2INT }T -T{ MIN-2INT 1. DMAX -> 1. }T -T{ MIN-2INT -1. DMAX -> -1. }T - - -T{ 1. 2. DMIN -> 1. }T -T{ 1. 0. DMIN -> 0. }T -T{ 1. -1. DMIN -> -1. }T -T{ 1. 1. DMIN -> 1. }T -T{ 0. 1. DMIN -> 0. }T -T{ 0. -1. DMIN -> -1. }T -T{ -1. 1. DMIN -> -1. }T -T{ -1. -2. DMIN -> -2. }T - -T{ MAX-2INT HI-2INT DMIN -> HI-2INT }T -T{ MAX-2INT MIN-2INT DMIN -> MIN-2INT }T -T{ MIN-2INT MAX-2INT DMIN -> MIN-2INT }T -T{ MIN-2INT LO-2INT DMIN -> MIN-2INT }T - -T{ MAX-2INT 1. DMIN -> 1. }T -T{ MAX-2INT -1. DMIN -> -1. }T -T{ MIN-2INT 1. DMIN -> MIN-2INT }T -T{ MIN-2INT -1. DMIN -> MIN-2INT }T - -TESTING D>S DABS - -T{ 1234 0 D>S -> 1234 }T -T{ -1234 -1 D>S -> -1234 }T -T{ MAX-INTD 0 D>S -> MAX-INTD }T -T{ MIN-INTD -1 D>S -> MIN-INTD }T - -T{ 1. DABS -> 1. }T -T{ -1. DABS -> 1. }T -T{ MAX-2INT DABS -> MAX-2INT }T -T{ MIN-2INT 1. D+ DABS -> MAX-2INT }T - -TESTING M+ M*/ - -T{ HI-2INT 1 M+ -> HI-2INT 1. D+ }T -T{ MAX-2INT -1 M+ -> MAX-2INT -1. D+ }T -T{ MIN-2INT 1 M+ -> MIN-2INT 1. D+ }T -T{ LO-2INT -1 M+ -> LO-2INT -1. D+ }T - - -: ?FLOORED [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ; - -T{ 5. 7 11 M*/ -> 3. }T -T{ 5. -7 11 M*/ -> -3. ?FLOORED }T -T{ -5. 7 11 M*/ -> -3. ?FLOORED }T -T{ -5. -7 11 M*/ -> 3. }T -T{ MAX-2INT 8 16 M*/ -> HI-2INT }T -T{ MAX-2INT -8 16 M*/ -> HI-2INT DNEGATE ?FLOORED }T -T{ MIN-2INT 8 16 M*/ -> LO-2INT }T -T{ MIN-2INT -8 16 M*/ -> LO-2INT DNEGATE }T -T{ MAX-2INT MAX-INTD MAX-INTD M*/ -> MAX-2INT }T -T{ MAX-2INT MAX-INTD 2/ MAX-INTD M*/ -> MAX-INTD 1- HI-2INT NIP }T -T{ MIN-2INT LO-2INT NIP 1+ DUP 1- NEGATE M*/ -> 0 MAX-INTD 1- }T -T{ MIN-2INT LO-2INT NIP 1- MAX-INTD M*/ -> MIN-INTD 3 + HI-2INT NIP 2 + }T -T{ MAX-2INT LO-2INT NIP DUP NEGATE M*/ -> MAX-2INT DNEGATE }T -T{ MIN-2INT MAX-INTD DUP M*/ -> MIN-2INT }T - -TESTING D. D.R - -MAX-2INT 71 73 M*/ 2CONSTANT DBL1 -MIN-2INT 73 79 M*/ 2CONSTANT DBL2 - -: D>ASCII ( D -- CADDR U ) - DUP >R <# DABS #S R> SIGN #> ( -- CADDR1 U ) - HERE SWAP 2DUP 2>R CHARS DUP ALLOT MOVE 2R> -; - -DBL1 D>ASCII 2CONSTANT "DBL1" -DBL2 D>ASCII 2CONSTANT "DBL2" - -: DOUBLEOUTPUT - CR ." You should see lines duplicated:" CR - 5 SPACES "DBL1" TYPE CR - 5 SPACES DBL1 D. CR - 8 SPACES "DBL1" DUP >R TYPE CR - 5 SPACES DBL1 R> 3 + D.R CR - 5 SPACES "DBL2" TYPE CR - 5 SPACES DBL2 D. CR - 10 SPACES "DBL2" DUP >R TYPE CR - 5 SPACES DBL2 R> 5 + D.R CR -; - -T{ DOUBLEOUTPUT -> }T - -TESTING 2ROT DU< (Double Number extension words) - -T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T -T{ MAX-2INT MIN-2INT 1. 2ROT -> MIN-2INT 1. MAX-2INT }T - -T{ 1. 1. DU< -> FALSE }T -T{ 1. -1. DU< -> TRUE }T -T{ -1. 1. DU< -> FALSE }T -T{ -1. -2. DU< -> FALSE }T -T{ 0 1 1. DU< -> FALSE }T -T{ 1. 0 1 DU< -> TRUE }T -T{ 0 -1 1 -2 DU< -> FALSE }T -T{ 1 -2 0 -1 DU< -> TRUE }T - -T{ MAX-2INT HI-2INT DU< -> FALSE }T -T{ HI-2INT MAX-2INT DU< -> TRUE }T -T{ MAX-2INT MIN-2INT DU< -> TRUE }T -T{ MIN-2INT MAX-2INT DU< -> FALSE }T -T{ MIN-2INT LO-2INT DU< -> TRUE }T - -TESTING 2VALUE - -T{ 1111 2222 2VALUE 2VAL -> }T -T{ 2VAL -> 1111 2222 }T -T{ 3333 4444 TO 2VAL -> }T -T{ 2VAL -> 3333 4444 }T -T{ : TO-2VAL TO 2VAL ; 5555 6666 TO-2VAL -> }T -T{ 2VAL -> 5555 6666 }T - - -CR .( End of Double-Number word tests) CR diff --git a/MSP430-FORTH/MSP_EXP430FR5994/FF_SPECS.4TH b/MSP430-FORTH/MSP_EXP430FR5994/FF_SPECS.4TH deleted file mode 100644 index 37a909d..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/FF_SPECS.4TH +++ /dev/null @@ -1,563 +0,0 @@ - -; --------------------------------- -; FF_SPECS.4th for MSP_EXP430FR5994 -; --------------------------------- - -CODE ABORT_FF_SPECS -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_FF_SPECS - -[UNDEFINED] AND [IF] -CODE AND -AND @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] -CODE 0< -ADD R14,R14 -SUBC R14,R14 -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] -CODE BEGIN - MOV #$4028,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] UNTIL [IF] -CODE UNTIL - MOV #$4034,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE AGAIN -MOV #$403A,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] WHILE [IF] -: WHILE -POSTPONE IF SWAP -; IMMEDIATE -[THEN] - -[UNDEFINED] REPEAT [IF] -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2* [IF] -CODE 2* -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0<> IF - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - THEN - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] WORDS [IF] -: WORDS -CR -$1DCA @ $1CE4 -$1810 @ 2* -MOVE -BEGIN - 0 DUP - $1810 @ 2* 0 - DO - DUP I $1CE4 + @ - U< IF - DROP DROP - I DUP $1CE4 + @ - THEN - 2 +LOOP - ?DUP -WHILE - DUP - 2 - @ - ROT - $1CE4 + - ! - DUP - COUNT $7F AND - TYPE - C@ $0F AND - $10 SWAP - SPACES -REPEAT -DROP -; -[THEN] - -[UNDEFINED] CASE [IF] -: CASE 0 ; IMMEDIATE - -: OF -1+ ->R -POSTPONE OVER POSTPONE = -POSTPONE IF -POSTPONE DROP -R> -; IMMEDIATE - -: ENDOF ->R -POSTPONE ELSE -R> -; IMMEDIATE - -: ENDCASE -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] S_ [IF] -CODE S_ -MOV #0,&$1DB4 -COLON -$4014 , -$20 WORD -HI2LO -MOV.B @R14,R14 -ADD #1,R14 -BIT #1,R14 -ADDC R14,&$1DC6 -MOV @R15+,R14 -MOV @R1+,R13 -MOV #$20,&$1DB4 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&$1DBE -0= IF MOV @R13+,R0 -THEN -COLON -$1B -POSTPONE LITERAL -POSTPONE EMIT -POSTPONE S_ -POSTPONE TYPE -; IMMEDIATE -[THEN] - -: SPECS -PWR_STATE -ECHO -ESC [8;40;80t -39 0 DO CR LOOP -ESC [H -ESC [7m -$0D EMIT ." FastForth V" -$180E @ -0 <# # $08 HOLD # '.' HOLD #S #> TYPE -." for MSP430FR" -HERE -$1A04 @ -CASE - $8102 OF ." 5738," $C200 ENDOF - $8103 OF ." 5739," $C200 ENDOF - $8160 OF ." 5948," $4400 ENDOF - $8169 OF ." 5969," $4400 ENDOF - $825D OF ." 5972," $4400 ENDOF - $81A8 OF ." 6989," $4400 ENDOF - $810D OF ." 5986," $4400 ENDOF - $81F0 OF ." 4133," $C400 ENDOF - $8240 OF ." 2433," $C400 ENDOF - $82A1 OF ." 5994," $4000 ENDOF - $82A6 OF ." 5962," $4000 ENDOF - $830C OF ." 2355," $8000 ENDOF - $830D OF ." 2353," $C000 ENDOF - $831E OF ." 2155," $8000 ENDOF - $831D OF ." 2153," $C000 ENDOF - $832A OF ." 2476," $8000 ENDOF - $832B OF ." 2475," $8000 ENDOF - $833C OF ." 2633," $C400 ENDOF - $833D OF ." 2533," $C400 ENDOF - ABORT" xxxx <-- unrecognized device!" -ENDCASE -['] ['] DUP @ $1284 = -IF ." DTC=1," DROP -ELSE 2 + @ $1284 = - IF ." DTC=2," - ELSE ." DTC=3," - THEN -THEN -$20 EMIT -$1810 @ U. $08 EMIT ." -Entry word set, " -$1800 @ 0 1000 UM/MOD U. -?DUP IF $08 EMIT ',' EMIT U. -THEN ." MHz, " -- U. ." bytes" -ESC [0m -CR -." /COUNTED-STRING = 255" CR -." /HOLD = 34" CR -." /PAD = 84" CR -." ADDRESS-UNIT-BITS = 16" CR -." FLOORED = true" CR -." MAX-CHAR = 255" CR -." MAX-N = 32767" CR -." MAX-U = 65535" CR -." MAX-D = 2147483647" CR -." MAX-UD = 4294967295" CR -." STACK-CELLS = 48" CR -." RETURN-STACK-CELLS= 48" CR -." DeFiNiTiOnS aRe CaSe-InSeNsItIvE" CR -." Strings are case-sensitive" CR -CR -ESC [7m ." KERNEL SPECS" ESC [0m -CR -$1812 @ - DUP 0< IF ." 32.768kHz XTAL" CR THEN -2* DUP 0< IF ." (4/2) UART TERMINAL" CR 2* - ELSE 2* DUP - 0< IF ." (RTS) UART TERMINAL" CR - THEN - THEN -2* DUP 0< IF ." (XON/XOFF) UART TERMINAL" CR - THEN -2* DUP 0< IF ." Half-Duplex TERMINAL" CR THEN -2* DUP 0< IF ." I2C_Master TERMINAL" CR THEN -2* DUP 0< IF ." Q15.16 input" CR THEN -2* DUP 0< IF ." DOUBLE input" CR THEN -2* DUP 0< IF ." MSP430_X assembler" CR 2* 2* - ELSE 2* DUP - 0< IF ." MSP430 Assembler" - 2* DUP 0< IF ." with 20bits address" - THEN CR - ELSE 2* - THEN - THEN -2* -2* -2* -2* -2* 0< IF - [DEFINED] DEFER [IF] ." DEFER word set" CR [THEN] - [DEFINED] ALSO [IF] ." VOCABULARY word set" CR [THEN] - [DEFINED] LOAD" [IF] ." SD_CARD Loader" CR [THEN] - [DEFINED] BOOT [IF] ." bootloader" CR [THEN] - [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR [THEN] - CR - ESC [7m ." OPTIONS" ESC [0m - CR - [DEFINED] {CORE_ANS} [IF] ." ANS94 core" CR [THEN] - [DEFINED] {DOUBLE} [IF] ." DOUBLE word set" CR [THEN] - [DEFINED] {TOOLS} [IF] ." UTILITY" CR [THEN] - [DEFINED] {FIXPOINT} [IF] ." Q15.16 ADD SUB MUL DIV" CR [THEN] - [DEFINED] {CORDIC} [IF] ." CORDIC engine" CR [THEN] - [DEFINED] {SD_TOOLS} [IF] ." SD_TOOLS" CR [THEN] - [DEFINED] {RTC} [IF] ." RTC utility" CR [THEN] - [DEFINED] {UARTI2CS} [IF] ." UART to I2C_FastForth bridge" CR [THEN] - [DEFINED] ALSO - [IF] - CR - ESC [7m ." ASSEMBLER word set" ESC [0m - ALSO ASSEMBLER WORDS PREVIOUS - CR - [THEN] -THEN -CR -ESC [7m ." FORTH word set" ESC [0m -WORDS -CR -HI2LO -MOV #WARM+4,R0 -ENDCODE - -SPECS diff --git a/MSP430-FORTH/MSP_EXP430FR5994/FIXPOINT.4TH b/MSP430-FORTH/MSP_EXP430FR5994/FIXPOINT.4TH deleted file mode 100644 index 529288d..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/FIXPOINT.4TH +++ /dev/null @@ -1,447 +0,0 @@ - -CODE ABORT_FIXPOINT -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$400,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" buil FastForth with FIXPOINT_INPUT addon !" -PWR_STATE -$1B EMIT $63 EMIT -; - -ABORT_FIXPOINT - -; ----------------------------------------------------- -; FIXPOINT.4th for MSP_EXP430FR5994 -; ----------------------------------------------------- - -[DEFINED] {FIXPOINT} [IF] {FIXPOINT} [THEN] - -MARKER {FIXPOINT} - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] -CODE DABS -AND #-1,R14 -S< IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HOLDS [IF] -CODE HOLDS - MOV @R15+,R9 -BW3 ADD R14,R9 - MOV &$1DB2,R8 -BEGIN SUB #1,R9 - SUB #1,R14 -U>= WHILE SUB #1,R8 - MOV.B @R9,0(R8) -REPEAT MOV R8,&$1DB2 - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -CODE F+ - ADD @R15+,2(R15) - ADDC @R15+,R14 - MOV @R13+,R0 -ENDCODE - -CODE F- - SUB @R15+,2(R15) - SUBC R14,0(R15) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE - -$1A00 4 + @ $81F3 U< -$81EF $1A00 4 + @ U< -= [IF] ; MSP430FR413x subfamily without hardware_MPY - -CODE UDM* - PUSH R13 - PUSHM #4,R7 - MOV 4(R15),R13 - MOV 2(R15),R11 - MOV @R15,R10 - MOV #0,R7 - MOV #0,R6 - MOV #0,4(R15) - MOV #0,2(R15) - MOV #0,R5 - MOV #0,R4 - MOV #1,R9 - MOV #0,R8 -BEGIN CMP #0,R9 - 0<> IF BIT R9,R10 - ELSE BIT R8,R14 - THEN - 0<> IF ADD R13,4(R15) - ADDC R11,2(R15) - ADDC R7,R5 - ADDC R6,R4 - THEN ADD R13,R13 - ADDC R11,R11 - ADDC R7,R7 - ADDC R6,R6 - ADD R9,R9 - ADDC R8,R8 -U>= UNTIL MOV R5,0(R15) - MOV R4,R14 - POPM #4,R7 - MOV @R1+,R13 - MOV @R13+,R0 -ENDCODE - -CODE F* - MOV 2(R15),R12 - XOR R14,R12 - BIT #$8000,2(R15) -0<> IF XOR #-1,2(R15) - XOR #-1,4(R15) - ADD #1,4(R15) - ADDC #0,2(R15) -THEN COLON - DABS UDM* - HI2LO - MOV @R1+,R13 - MOV @R15+,R14 - MOV @R15+,0(R15) - AND #-1,R12 -S< IF XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 -THEN MOV @R13+,R0 -ENDCODE - -[UNDEFINED] F#S [IF] -CODE F#S - MOV @R15,R12 - MOV #0,R11 - PUSHM #3,R13 - MOV 2(R15),0(R15) - MOV R14,2(R15) -BEGIN MOV &$1DDC,R14 - LO2HI - UM* - HI2LO - CMP #10,R14 - U>= IF ADD #7,R14 - THEN ADD #$30,R14 - MOV @R1,R11 - MOV.B R14,$1D90(R11) - ADD #1,R11 - MOV R11,0(R1) - CMP 2(R15),R11 -U>= UNTIL POPM #3,R13 - MOV R11,R14 - MOV R12,2(R15) - MOV #0,0(R15) - MOV #$1D90,R9 - GOTO BW3 -ENDCODE -[THEN] - -[ELSE] ; hardware multiplier - -CODE F* - MOV 4(R15),&$4D4 - MOV 2(R15),&$4D6 - MOV @R15,&$4E0 - MOV R14,&$4E2 - ADD #4,R15 - MOV &$4E6,0(R15) - MOV &$4E8,R14 - MOV @R13+,R0 -ENDCODE - -[UNDEFINED] F#S [IF] -CODE F#S - MOV 2(R15),R9 - MOV @R15,2(R15) - MOV R9,0(R15) - MOV R14,R11 - MOV #0,R12 -BEGIN MOV @R15,&$4C0 - MOV &$1DDC,&$4C8 - MOV &$4E4,0(R15) - MOV &$4E6,R14 - CMP #10,R14 - U>= IF ADD #7,R14 - THEN ADD #$30,R14 - MOV.B R14,$1D90(R12) - ADD #1,R12 - CMP R11,R12 -0= UNTIL MOV R11,R14 - MOV #0,0(R15) - MOV #$1D90,R9 - GOTO BW3 -ENDCODE -[THEN] - -[THEN] - -CODE F/ - MOV R14,R8 - MOV @R15+,R10 - MOV @R15+,R9 - MOV @R15,R11 - PUSHM #5,R9 - AND #-1,R8 -S< IF XOR #-1,R10 - XOR #-1,R8 - ADD #1,R10 - ADDC #0,R8 -THEN - AND #-1,R9 -S< IF XOR #-1,R11 - XOR #-1,R9 - ADD #1,R11 - ADDC #0,R9 -THEN - MOV R9,R7 - MOV R11,R9 - MOV #0,R11 - MOV #0,R6 - MOV #32,R5 -BW1 CMP R8,R6 - 0= IF CMP R10,R7 - THEN - U>= IF SUB R10,R7 - SUBC R8,R6 - THEN - BEGIN ADDC R12,R12 - ADDC R14,R14 - SUB #1,R5 - U>= WHILE - ADD R11,R11 - ADDC R9,R9 - ADDC R7,R7 - ADDC R6,R6 - U< ?GOTO BW1 - SUB R10,R7 - SUBC R8,R6 - BIS #1,R2 - REPEAT - POPM #5,R9 - XOR R9,R8 - CMP #0,R8 -S< IF XOR #-1,R12 - XOR #-1,R14 - ADD #1,R12 - ADDC #0,R14 -THEN - MOV R12,0(R15) - MOV @R13+,R0 -ENDCODE - -[UNDEFINED] F. [IF] -CODE F. -MOV R14,R12 -MOV #4,R11 -MOV &$1DDC,R10 -CMP #$0A,R10 -0= IF - ADD #1,R11 -ELSE - CMP #2,R10 - 0= IF - MOV #$10,R11 - THEN -THEN -PUSHM #3,R13 -LO2HI - <# DABS - R> F#S - $2C HOLD - #S - R> SIGN #> - TYPE $20 EMIT -; - -CODE S>F - SUB #2,R15 - MOV #0,0(R15) - MOV @R13+,R0 -ENDCODE -[THEN] - -RST_HERE - -; ----------------------- -; complement (volatile) for tests below -; ----------------------- - -[UNDEFINED] ! [IF] -CODE ! -MOV @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] -CODE DOES> -MOV &$1DBA,R10 -MOV #DODOES,0(R10) -MOV R13,2(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2CONSTANT [IF] -: 2CONSTANT -CREATE , , -DOES> -HI2LO -SUB #2,R15 -MOV 2(R14),0(R15) -MOV @R14,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D. [IF] -CODE D. -MOV #U.,R10 -ADD #10,R10 -MOV R10,R0 -ENDCODE -[THEN] - -[UNDEFINED] BASE [IF] -$1DDC CONSTANT BASE -[THEN] - -ECHO - -; ----------------------- -; (volatile) tests for FIXPOINT.asm|FIXPOINT.4th for MSP_EXP430FR5994 -; ----------------------- - -3,14159 2CONSTANT PI -PI -1,0 F* 2CONSTANT -PI - -PI D. ; D. is not appropriate --> --PI D. ; D. is not appropriate --> - -PI F. ; F. is a good choice! ---> --PI F. ; F. is a good choice! ---> - -$10 BASE ! PI F. - -PI F. -%10 BASE ! PI F. - -PI F. -#10 BASE ! PI F. - -PI F. - - PI 2,0 F* F. - PI -2,0 F* F. --PI 2,0 F* F. --PI -2,0 F* F. - - PI 2,0 F/ F. - PI -2,0 F/ F. --PI 2,0 F/ F. --PI -2,0 F/ F. - - 32768,0 1,0 F* F. ; overflow! --> - 32768,0 1,0 F/ F. ; overflow! --> --32768,0 -1,0 F* F. ; overflow! --> --32768,0 -1,0 F/ F. ; overflow! --> - -32767,99999 1,0 F* F. -32767,99999 1,0 F/ F. -32767,99999 2,0 F/ F. -32767,99999 4,0 F/ F. -32767,99999 8,0 F/ F. -32767,99999 16,0 F/ F. - --32768,0 -2,0 F/ F. --32768,0 -4,0 F/ F. --32768,0 -8,0 F/ F. --32768,0 -16,0 F/ F. --32768,0 -32,0 F/ F. --32768,0 -64,0 F/ F. - --3276,80 -1,0 F/ F. --327,680 -1,0 F/ F. --32,7680 -1,0 F/ F. --3,27680 -1,0 F/ F. --0,32768 -1,0 F/ F. - -; SQRT(32768)^2 = 32768 - 181,01933598375 181,01933598375 F* F. - 181,01933598375 -181,01933598375 F* F. --181,01933598375 181,01933598375 F* F. --181,01933598375 -181,01933598375 F* F. - -RST_STATE diff --git a/MSP430-FORTH/MSP_EXP430FR5994/LAST.4TH b/MSP430-FORTH/MSP_EXP430FR5994/LAST.4TH deleted file mode 100644 index b7f7c4b..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/LAST.4TH +++ /dev/null @@ -1,1435 +0,0 @@ - -CODE ABORT_DOUBLE -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$200,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" build FastForth with DOUBLE_INPUT addon !" -PWR_STATE -; - -ABORT_DOUBLE - -; ----------------------------------------------------- -; DOUBLE.4th for MSP_EXP430FR5994 -; ----------------------------------------------------- - -[DEFINED] {DOUBLE} [IF] {DOUBLE} [THEN] - -MARKER {DOUBLE} - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] @ [IF] -CODE @ -MOV @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ! [IF] -CODE ! -MOV @R15+,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] < [IF] -CODE < - SUB @R15+,R14 - S< ?GOTO FW1 - 0<> IF -BW1 MOV #-1,R14 - THEN - MOV @R13+,R0 -ENDCODE - -CODE > - SUB @R15+,R14 - S< ?GOTO BW1 -FW1 AND #0,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] TO [IF] -CODE TO -BIS #$200,R2 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DOES> [IF] -CODE DOES> -MOV &$1DBA,R10 -MOV #DODOES,0(R10) -MOV R13,2(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2@ [IF] -CODE 2@ -SUB #2,R15 -MOV 2(R14),0(R15) -MOV @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2! [IF] -CODE 2! -MOV @R15+,0(R14) -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DUP [IF] -CODE 2DUP -SUB #4,R15 -MOV R14,2(R15) -MOV 4(R15),0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DROP [IF] -CODE 2DROP -ADD #2,R15 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2SWAP [IF] -CODE 2SWAP -MOV @R15,R10 -MOV 4(R15),0(R15) -MOV R10,4(R15) -MOV R14,R10 -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2OVER [IF] -CODE 2OVER -SUB #4,R15 -MOV R14,2(R15) -MOV 8(R15),0(R15) -MOV 6(R15),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2>R [IF] -CODE 2>R -PUSH @R15+ -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2R@ [IF] -CODE 2R@ -SUB #4,R15 -MOV R14,2(R15) -MOV @R1,R14 -MOV 2(R1),0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2R> [IF] -CODE 2R> -SUB #4,R15 -MOV R14,2(R15) -MOV @R1+,R14 -MOV @R1+,0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] D. [IF] -CODE D. -MOV #U.,R10 -ADD #10,R10 -MOV R10,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2ROT [IF] -CODE 2ROT -MOV 8(R15),R9 -MOV 6(R15),R8 -MOV 4(R15),8(R15) -MOV 2(R15),6(R15) -MOV @R15,4(R15) -MOV R14,2(R15) -MOV R9,0(R15) -MOV R8,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D>S [IF] -CODE D>S -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D0= [IF] -CODE D0= -CMP #0,R14 -MOV #0,R14 -0= IF - CMP #0,0(R15) - 0= IF - MOV #-1,R14 - THEN -THEN -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D0< [IF] -CODE D0< -CMP #0,R14 -MOV #0,R14 -S< IF - MOV #-1,R14 -THEN -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D= [IF] -CODE D= -CMP R14,2(R15) -MOV #0,R14 -0= IF - CMP @R15,4(R15) - 0= IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D< [IF] -CODE D< -CMP R14,2(R15) -MOV #0,R14 -S< IF - MOV #-1,R14 -THEN -0= IF - CMP @R15,4(R15) - U< IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DU< [IF] -CODE DU< -CMP R14,2(R15) -MOV #0,R14 -U< IF - MOV #-1,R14 -THEN -0= IF - CMP @R15,4(R15) - U< IF - MOV #-1,R14 - THEN -THEN -ADD #6,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D+ [IF] -CODE D+ -BW1 ADD @R15+,2(R15) - ADDC @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] M+ [IF] -CODE M+ -SUB #2,R15 -CMP #0,R14 -MOV R14,0(R15) -MOV #-1,R14 -0>= IF - MOV #0,R14 -THEN -GOTO BW1 -ENDCODE -[THEN] - -[UNDEFINED] D- [IF] -CODE D- -SUB @R15+,2(R15) -SUBC R14,0(R15) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DNEGATE [IF] -CODE DNEGATE -XOR #-1,0(R15) -XOR #-1,R14 -ADD #1,0(R15) -ADDC #0,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DABS [IF] -CODE DABS -CMP #0,R14 -0>= IF - MOV @R13+,R0 -THEN -MOV #DNEGATE,R0 -ENDCODE -[THEN] - -[UNDEFINED] D2/ [IF] -CODE D2/ -RRA R14 -RRC 0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] D2* [IF] -CODE D2* -ADD @R15,0(R15) -ADDC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DMAX [IF] -: DMAX -2OVER 2OVER -D< IF - 2>R 2DROP 2R> -ELSE - 2DROP -THEN -; -[THEN] - -[UNDEFINED] DMIN [IF] -: DMIN -2OVER 2OVER -D< IF - 2DROP -ELSE 2>R 2DROP 2R> -THEN -; - -$1A04 C@ $EF > [IF] ; test for MSP430FR413x devices without hardware_MPY - -[UNDEFINED] M*/ [IF] -CODE M*/ -BIC #$200,R2 -CMP #0,2(R15) -S< IF - XOR #-1,4(R15) - XOR #-1,2(R15) - ADD #1,4(R15) - ADDC #0,2(R15) - BIS #$200,R2 -THEN -CMP #0,0(R15) -S< IF - XOR #-1,0(R15) - ADD #1,0(R15) - XOR #$200,R2 -THEN - MOV 4(R15),R8 - MOV 2(R15),R11 - MOV @R15+,R12 - MOV #0,R5 - MOV #0,2(R15) - MOV #0,0(R15) - MOV #0,R10 - MOV #1,R9 -BEGIN BIT R9,R12 - 0<> IF ADD R8,2(R15) - ADDC R11,0(R15) - ADDC R5,R10 - THEN ADD R8,R8 - ADDC R11,R11 - ADDC R5,R5 - ADD R9,R9 -U>= UNTIL -MOV R14,R11 -MOV @R15,R14 -MOV 2(R15),R12 -MOV #32,R5 -CMP #0,R10 -0= IF - MOV R14,R10 - CALL #$4078 -ELSE - CALL #$4080 -THEN -MOV @R15+,0(R15) -BIT #$200,R2 -0<> IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 - BIC #$200,R2 - CMP #0,R10 - 0<> IF - SUB #1,0(R15) - SUBC #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[ELSE] - -[UNDEFINED] M*/ [IF] -CODE M*/ -MOV 4(R15),&$4D4 -MOV 2(R15),&$4D6 -MOV @R15+,&$4C8 -MOV R14,R11 -MOV R0,R0 -MOV &$4E4,R12 -MOV &$4E6,R14 -MOV &$4E8,R10 -BIC #$200,R2 -CMP #0,R10 -S< IF - XOR #-1,R12 - XOR #-1,R14 - XOR #-1,R10 - ADD #1,R12 - ADDC #0,R14 - ADDC #0,R10 - BIS #$200,R2 -THEN -MOV #32,R5 -CMP #0,R10 -0= IF - MOV R14,R10 - CALL #$4078 -ELSE - CALL #$4080 -THEN -MOV @R15+,0(R15) -BIT #$200,R2 -0<> IF - XOR #-1,0(R15) - XOR #-1,R14 - ADD #1,0(R15) - ADDC #0,R14 - BIC #$200,R2 - CMP #0,R10 - 0<> IF - SUB #1,0(R15) - SUBC #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[THEN] ; end of software/hardware_MPY - -[UNDEFINED] 2VARIABLE [IF] -: 2VARIABLE -CREATE -HI2LO -ADD #4,&$1DC6 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2CONSTANT [IF] -: 2CONSTANT -CREATE -, , -DOES> -2@ -; -[THEN] - -[UNDEFINED] 2VALUE [IF] -: 2VALUE -CREATE , , -DOES> -HI2LO -MOV @R1+,R13 -BIT #$200,R2 -0= IF - MOV #2@,R0 -THEN -BIC #$200,R2 -MOV #2!,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2LITERAL [IF] -CODE 2LITERAL -BIS #$200,R2 -MOV #LITERAL,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] D.R [IF] -: D.R ->R SWAP OVER DABS <# #S ROT SIGN #> -R> OVER - SPACES TYPE -; -[THEN] - -RST_HERE - -[UNDEFINED] VARIABLE [IF] -: VARIABLE -CREATE -HI2LO -MOV @R1+,R13 -ADD #2,&$1DC6 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CELLS [IF] -CODE CELLS -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ALLOT [IF] -CODE ALLOT -ADD R14,&$1DC6 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] -CODE DEPTH -MOV R14,-2(R15) -MOV #$1C80,R14 -SUB R15,R14 -RRA R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SOURCE [IF] -CODE SOURCE -SUB #4,R15 -MOV R14,2(R15) -MOV &$1DC0,R14 -MOV &$1DC2,0(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >IN [IF] -$1DC4 CONSTANT >IN -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CHAR [IF] -: CHAR - $20 WORD 1+ C@ -; -[THEN] - -[UNDEFINED] [CHAR] [IF] -: [CHAR] - CHAR POSTPONE LITERAL -; IMMEDIATE -[THEN] - -[UNDEFINED] 2/ [IF] -CODE 2/ -RRA R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] INVERT [IF] -CODE INVERT -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] RSHIFT [IF] -CODE RSHIFT - MOV @R15+,R10 - AND #$1F,R14 -0<> IF - BEGIN BIC #1,R2 - RRC R10 - SUB #1,R14 - 0= UNTIL -THEN MOV R10,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0< [IF] -CODE 0< -ADD R14,R14 -SUBC R14,R14 -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] S>D [IF] -: S>D - DUP 0< -; -[THEN] - -[UNDEFINED] 1- [IF] -CODE 1- -SUB #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] SM/REM [IF] -CODE SM/REM -MOV R14,R12 -MOV @R15,R11 -CMP #0,R14 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -CMP #0,0(R15) -S< IF - XOR #-1,2(R15) - XOR #-1,0(R15) - ADD #1,2(R15) - ADDC #0,0(R15) -THEN -PUSHM #3,R13 -LO2HI - UM/MOD -HI2LO -POPM #3,R13 -CMP #0,R11 -S< IF - XOR #-1,0(R15) - ADD #1,0(R15) -THEN -XOR R12,R11 -CMP #0,R11 -S< IF - XOR #-1,R14 - ADD #1,R14 -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] FM/MOD [IF] -: FM/MOD -SM/REM -HI2LO -CMP #0,0(R15) -0<> IF - CMP #1,R14 - S< IF - ADD R12,0(R15) - SUB #1,R14 - THEN -THEN -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] NIP [IF] -CODE NIP -ADD #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] / [IF] -: / ->R DUP 0< R> FM/MOD NIP -; -[THEN] - -[UNDEFINED] NEGATE [IF] -CODE NEGATE -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - -[UNDEFINED] CHARS [IF] -CODE CHARS -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0<> IF - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - THEN - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DECIMAL [IF] -CODE DECIMAL -MOV #$0A,&$1DDC -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] BASE [IF] -$1DDC CONSTANT BASE -[THEN] - -[UNDEFINED] ( [IF] -: ( -')' WORD DROP -; IMMEDIATE -[THEN] - -[UNDEFINED] .( [IF] -CODE .( -MOV #0,&$1DB4 -COLON -')' WORD -COUNT TYPE -$20 $1DB4 ! -; IMMEDIATE -[THEN] - - - - - - - - 0 CONSTANT FALSE --1 CONSTANT TRUE - -VARIABLE VERBOSE - FALSE VERBOSE ! - - -VARIABLE ACTUAL-DEPTH -CREATE ACTUAL-RESULTS 20 CELLS ALLOT - -: T{ - ; - -: -> - DEPTH DUP ACTUAL-DEPTH ! - ?DUP IF - 0 DO ACTUAL-RESULTS I CELLS + ! LOOP - THEN ; - -: }T - - DEPTH ACTUAL-DEPTH @ = IF - DEPTH ?DUP IF - 0 DO - ACTUAL-RESULTS I CELLS + @ - = 0= IF TRUE ABORT" INCORRECT RESULT" THEN - LOOP - THEN - ELSE - TRUE ABORT" WRONG NUMBER OF RESULTS" - THEN ; - -: TESTING - SOURCE VERBOSE @ - IF DUP >R TYPE CR R> >IN ! - ELSE >IN ! DROP [CHAR] * EMIT - THEN ; - -ECHO - - -DECIMAL - -0 INVERT CONSTANT 1SD -1SD 1 RSHIFT CONSTANT MAX-INTD -MAX-INTD INVERT CONSTANT MIN-INTD -MAX-INTD 2/ CONSTANT HI-INT -MIN-INTD 2/ CONSTANT LO-INT - - -TESTING interpreter and compiler reading double numbers, with/without prefixes - -T{ 1. -> 1 0 }T -T{ -2. -> -2 -1 }T -T{ : RDL1 3. ; RDL1 -> 3 0 }T -T{ : RDL2 -4. ; RDL2 -> -4 -1 }T - -VARIABLE OLD-DBASE -DECIMAL BASE @ OLD-DBASE ! -T{ #12346789. -> 12346789. }T -T{ #-12346789. -> -12346789. }T -T{ $12aBcDeF. -> 313249263. }T -T{ $-12AbCdEf. -> -313249263. }T -T{ %10010110. -> 150. }T -T{ %-10010110. -> -150. }T -T{ BASE @ OLD-DBASE @ = -> TRUE }T - -16 OLD-DBASE ! 16 BASE ! -T{ #12346789. -> BC65A5. }T -T{ #-12346789. -> -BC65A5. }T -T{ $12aBcDeF. -> 12AbCdeF. }T -T{ $-12AbCdEf. -> -12ABCDef. }T -T{ %10010110. -> 96. }T -T{ %-10010110. -> -96. }T -T{ BASE @ OLD-DBASE @ = -> TRUE }T - -DECIMAL -T{ : dnmp #8327. $-2cbe. %011010111. ; dnmp -> 8327. -11454. 215. }T - -TESTING 2CONSTANT - -T{ 1 2 2CONSTANT 2C1 -> }T -T{ 2C1 -> 1 2 }T -T{ : CD1 2C1 ; -> }T -T{ CD1 -> 1 2 }T -T{ : CD2 2CONSTANT ; -> }T -T{ -1 -2 CD2 2C2 -> }T -T{ 2C2 -> -1 -2 }T -T{ 4 5 2CONSTANT 2C3 IMMEDIATE 2C3 -> 4 5 }T -T{ : CD6 2C3 2LITERAL ; CD6 -> 4 5 }T - - -1SD MAX-INTD 2CONSTANT MAX-2INT -0 MIN-INTD 2CONSTANT MIN-2INT -MAX-2INT 2/ 2CONSTANT HI-2INT -MIN-2INT 2/ 2CONSTANT LO-2INT - -TESTING DNEGATE - -T{ 0. DNEGATE -> 0. }T -T{ 1. DNEGATE -> -1. }T -T{ -1. DNEGATE -> 1. }T -T{ MAX-2INT DNEGATE -> MIN-2INT SWAP 1+ SWAP }T -T{ MIN-2INT SWAP 1+ SWAP DNEGATE -> MAX-2INT }T - -TESTING D+ with small integers - -T{ 0. 5. D+ -> 5. }T -T{ -5. 0. D+ -> -5. }T -T{ 1. 2. D+ -> 3. }T -T{ 1. -2. D+ -> -1. }T -T{ -1. 2. D+ -> 1. }T -T{ -1. -2. D+ -> -3. }T -T{ -1. 1. D+ -> 0. }T - -TESTING D+ with mid range integers - -T{ 0 0 0 5 D+ -> 0 5 }T -T{ -1 5 0 0 D+ -> -1 5 }T -T{ 0 0 0 -5 D+ -> 0 -5 }T -T{ 0 -5 -1 0 D+ -> -1 -5 }T -T{ 0 1 0 2 D+ -> 0 3 }T -T{ -1 1 0 -2 D+ -> -1 -1 }T -T{ 0 -1 0 2 D+ -> 0 1 }T -T{ 0 -1 -1 -2 D+ -> -1 -3 }T -T{ -1 -1 0 1 D+ -> -1 0 }T -T{ MIN-INTD 0 2DUP D+ -> 0 1 }T -T{ MIN-INTD S>D MIN-INTD 0 D+ -> 0 0 }T - -TESTING D+ with large double integers - -T{ HI-2INT 1. D+ -> 0 HI-INT 1+ }T -T{ HI-2INT 2DUP D+ -> 1SD 1- MAX-INTD }T -T{ MAX-2INT MIN-2INT D+ -> -1. }T -T{ MAX-2INT LO-2INT D+ -> HI-2INT }T -T{ HI-2INT MIN-2INT D+ 1. D+ -> LO-2INT }T -T{ LO-2INT 2DUP D+ -> MIN-2INT }T - -TESTING D- with small integers - -T{ 0. 5. D- -> -5. }T -T{ 5. 0. D- -> 5. }T -T{ 0. -5. D- -> 5. }T -T{ 1. 2. D- -> -1. }T -T{ 1. -2. D- -> 3. }T -T{ -1. 2. D- -> -3. }T -T{ -1. -2. D- -> 1. }T -T{ -1. -1. D- -> 0. }T - -TESTING D- with mid-range integers - -T{ 0 0 0 5 D- -> 0 -5 }T -T{ -1 5 0 0 D- -> -1 5 }T -T{ 0 0 -1 -5 D- -> 1 4 }T -T{ 0 -5 0 0 D- -> 0 -5 }T -T{ -1 1 0 2 D- -> -1 -1 }T -T{ 0 1 -1 -2 D- -> 1 2 }T -T{ 0 -1 0 2 D- -> 0 -3 }T -T{ 0 -1 0 -2 D- -> 0 1 }T -T{ 0 0 0 1 D- -> 0 -1 }T -T{ MIN-INTD 0 2DUP D- -> 0. }T -T{ MIN-INTD S>D MAX-INTD 0 D- -> 1 1SD }T - -TESTING D- with large integers - -T{ MAX-2INT MAX-2INT D- -> 0. }T -T{ MIN-2INT MIN-2INT D- -> 0. }T -T{ MAX-2INT HI-2INT D- -> LO-2INT DNEGATE }T -T{ HI-2INT LO-2INT D- -> MAX-2INT }T -T{ LO-2INT HI-2INT D- -> MIN-2INT 1. D+ }T -T{ MIN-2INT MIN-2INT D- -> 0. }T -T{ MIN-2INT LO-2INT D- -> LO-2INT }T - -TESTING D0< D0= - -T{ 0. D0< -> FALSE }T -T{ 1. D0< -> FALSE }T -T{ MIN-INTD 0 D0< -> FALSE }T -T{ 0 MAX-INTD D0< -> FALSE }T -T{ MAX-2INT D0< -> FALSE }T -T{ -1. D0< -> TRUE }T -T{ MIN-2INT D0< -> TRUE }T - -T{ 1. D0= -> FALSE }T -T{ MIN-INTD 0 D0= -> FALSE }T -T{ MAX-2INT D0= -> FALSE }T -T{ -1 MAX-INTD D0= -> FALSE }T -T{ 0. D0= -> TRUE }T -T{ -1. D0= -> FALSE }T -T{ 0 MIN-INTD D0= -> FALSE }T - -TESTING D2* D2/ - -T{ 0. D2* -> 0. D2* }T -T{ MIN-INTD 0 D2* -> 0 1 }T -T{ HI-2INT D2* -> MAX-2INT 1. D- }T -T{ LO-2INT D2* -> MIN-2INT }T - -T{ 0. D2/ -> 0. }T -T{ 1. D2/ -> 0. }T -T{ 0 1 D2/ -> MIN-INTD 0 }T -T{ MAX-2INT D2/ -> HI-2INT }T -T{ -1. D2/ -> -1. }T -T{ MIN-2INT D2/ -> LO-2INT }T - -TESTING D< D= - -T{ 0. 1. D< -> TRUE }T -T{ 0. 0. D< -> FALSE }T -T{ 1. 0. D< -> FALSE }T -T{ -1. 1. D< -> TRUE }T -T{ -1. 0. D< -> TRUE }T -T{ -2. -1. D< -> TRUE }T -T{ -1. -2. D< -> FALSE }T -T{ 0 1 1. D< -> FALSE }T -T{ 1. 0 1 D< -> TRUE }T -T{ 0 -1 1 -2 D< -> FALSE }T -T{ 1 -2 0 -1 D< -> TRUE }T -T{ -1. MAX-2INT D< -> TRUE }T -T{ MIN-2INT MAX-2INT D< -> TRUE }T -T{ MAX-2INT -1. D< -> FALSE }T -T{ MAX-2INT MIN-2INT D< -> FALSE }T -T{ MAX-2INT 2DUP -1. D+ D< -> FALSE }T -T{ MIN-2INT 2DUP 1. D+ D< -> TRUE }T -T{ MAX-INTD S>D 2DUP 1. D+ D< -> TRUE }T - -T{ -1. -1. D= -> TRUE }T -T{ -1. 0. D= -> FALSE }T -T{ -1. 1. D= -> FALSE }T -T{ 0. -1. D= -> FALSE }T -T{ 0. 0. D= -> TRUE }T -T{ 0. 1. D= -> FALSE }T -T{ 1. -1. D= -> FALSE }T -T{ 1. 0. D= -> FALSE }T -T{ 1. 1. D= -> TRUE }T - -T{ 0 -1 0 -1 D= -> TRUE }T -T{ 0 -1 0 0 D= -> FALSE }T -T{ 0 -1 0 1 D= -> FALSE }T -T{ 0 0 0 -1 D= -> FALSE }T -T{ 0 0 0 0 D= -> TRUE }T -T{ 0 0 0 1 D= -> FALSE }T -T{ 0 1 0 -1 D= -> FALSE }T -T{ 0 1 0 0 D= -> FALSE }T -T{ 0 1 0 1 D= -> TRUE }T - -T{ MAX-2INT MIN-2INT D= -> FALSE }T -T{ MAX-2INT 0. D= -> FALSE }T -T{ MAX-2INT MAX-2INT D= -> TRUE }T -T{ MAX-2INT HI-2INT D= -> FALSE }T -T{ MAX-2INT MIN-2INT D= -> FALSE }T -T{ MIN-2INT MIN-2INT D= -> TRUE }T -T{ MIN-2INT LO-2INT D= -> FALSE }T -T{ MIN-2INT MAX-2INT D= -> FALSE }T - -TESTING 2LITERAL 2VARIABLE - -T{ : CD3 [ MAX-2INT ] 2LITERAL ; -> }T -T{ CD3 -> MAX-2INT }T -T{ 2VARIABLE 2V1 -> }T -T{ 0. 2V1 2! -> }T -T{ 2V1 2@ -> 0. }T -T{ -1 -2 2V1 2! -> }T -T{ 2V1 2@ -> -1 -2 }T -T{ : CD4 2VARIABLE ; -> }T -T{ CD4 2V2 -> }T -T{ : CD5 2V2 2! ; -> }T -T{ -2 -1 CD5 -> }T -T{ 2V2 2@ -> -2 -1 }T -T{ 2VARIABLE 2V3 IMMEDIATE 5 6 2V3 2! -> }T -T{ 2V3 2@ -> 5 6 }T -T{ : CD7 2V3 [ 2@ ] 2LITERAL ; CD7 -> 5 6 }T -T{ : CD8 [ 6 7 ] 2V3 [ 2! ] ; 2V3 2@ -> 6 7 }T - -TESTING DMAX DMIN - -T{ 1. 2. DMAX -> 2. }T -T{ 1. 0. DMAX -> 1. }T -T{ 1. -1. DMAX -> 1. }T -T{ 1. 1. DMAX -> 1. }T -T{ 0. 1. DMAX -> 1. }T -T{ 0. -1. DMAX -> 0. }T -T{ -1. 1. DMAX -> 1. }T -T{ -1. -2. DMAX -> -1. }T - -T{ MAX-2INT HI-2INT DMAX -> MAX-2INT }T -T{ MAX-2INT MIN-2INT DMAX -> MAX-2INT }T -T{ MIN-2INT MAX-2INT DMAX -> MAX-2INT }T -T{ MIN-2INT LO-2INT DMAX -> LO-2INT }T - -T{ MAX-2INT 1. DMAX -> MAX-2INT }T -T{ MAX-2INT -1. DMAX -> MAX-2INT }T -T{ MIN-2INT 1. DMAX -> 1. }T -T{ MIN-2INT -1. DMAX -> -1. }T - - -T{ 1. 2. DMIN -> 1. }T -T{ 1. 0. DMIN -> 0. }T -T{ 1. -1. DMIN -> -1. }T -T{ 1. 1. DMIN -> 1. }T -T{ 0. 1. DMIN -> 0. }T -T{ 0. -1. DMIN -> -1. }T -T{ -1. 1. DMIN -> -1. }T -T{ -1. -2. DMIN -> -2. }T - -T{ MAX-2INT HI-2INT DMIN -> HI-2INT }T -T{ MAX-2INT MIN-2INT DMIN -> MIN-2INT }T -T{ MIN-2INT MAX-2INT DMIN -> MIN-2INT }T -T{ MIN-2INT LO-2INT DMIN -> MIN-2INT }T - -T{ MAX-2INT 1. DMIN -> 1. }T -T{ MAX-2INT -1. DMIN -> -1. }T -T{ MIN-2INT 1. DMIN -> MIN-2INT }T -T{ MIN-2INT -1. DMIN -> MIN-2INT }T - -TESTING D>S DABS - -T{ 1234 0 D>S -> 1234 }T -T{ -1234 -1 D>S -> -1234 }T -T{ MAX-INTD 0 D>S -> MAX-INTD }T -T{ MIN-INTD -1 D>S -> MIN-INTD }T - -T{ 1. DABS -> 1. }T -T{ -1. DABS -> 1. }T -T{ MAX-2INT DABS -> MAX-2INT }T -T{ MIN-2INT 1. D+ DABS -> MAX-2INT }T - -TESTING M+ M*/ - -T{ HI-2INT 1 M+ -> HI-2INT 1. D+ }T -T{ MAX-2INT -1 M+ -> MAX-2INT -1. D+ }T -T{ MIN-2INT 1 M+ -> MIN-2INT 1. D+ }T -T{ LO-2INT -1 M+ -> LO-2INT -1. D+ }T - - -: ?FLOORED [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ; - -T{ 5. 7 11 M*/ -> 3. }T -T{ 5. -7 11 M*/ -> -3. ?FLOORED }T -T{ -5. 7 11 M*/ -> -3. ?FLOORED }T -T{ -5. -7 11 M*/ -> 3. }T -T{ MAX-2INT 8 16 M*/ -> HI-2INT }T -T{ MAX-2INT -8 16 M*/ -> HI-2INT DNEGATE ?FLOORED }T -T{ MIN-2INT 8 16 M*/ -> LO-2INT }T -T{ MIN-2INT -8 16 M*/ -> LO-2INT DNEGATE }T -T{ MAX-2INT MAX-INTD MAX-INTD M*/ -> MAX-2INT }T -T{ MAX-2INT MAX-INTD 2/ MAX-INTD M*/ -> MAX-INTD 1- HI-2INT NIP }T -T{ MIN-2INT LO-2INT NIP 1+ DUP 1- NEGATE M*/ -> 0 MAX-INTD 1- }T -T{ MIN-2INT LO-2INT NIP 1- MAX-INTD M*/ -> MIN-INTD 3 + HI-2INT NIP 2 + }T -T{ MAX-2INT LO-2INT NIP DUP NEGATE M*/ -> MAX-2INT DNEGATE }T -T{ MIN-2INT MAX-INTD DUP M*/ -> MIN-2INT }T - -TESTING D. D.R - -MAX-2INT 71 73 M*/ 2CONSTANT DBL1 -MIN-2INT 73 79 M*/ 2CONSTANT DBL2 - -: D>ASCII ( D -- CADDR U ) - DUP >R <# DABS #S R> SIGN #> ( -- CADDR1 U ) - HERE SWAP 2DUP 2>R CHARS DUP ALLOT MOVE 2R> -; - -DBL1 D>ASCII 2CONSTANT "DBL1" -DBL2 D>ASCII 2CONSTANT "DBL2" - -: DOUBLEOUTPUT - CR ." You should see lines duplicated:" CR - 5 SPACES "DBL1" TYPE CR - 5 SPACES DBL1 D. CR - 8 SPACES "DBL1" DUP >R TYPE CR - 5 SPACES DBL1 R> 3 + D.R CR - 5 SPACES "DBL2" TYPE CR - 5 SPACES DBL2 D. CR - 10 SPACES "DBL2" DUP >R TYPE CR - 5 SPACES DBL2 R> 5 + D.R CR -; - -T{ DOUBLEOUTPUT -> }T - -TESTING 2ROT DU< (Double Number extension words) - -T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T -T{ MAX-2INT MIN-2INT 1. 2ROT -> MIN-2INT 1. MAX-2INT }T - -T{ 1. 1. DU< -> FALSE }T -T{ 1. -1. DU< -> TRUE }T -T{ -1. 1. DU< -> FALSE }T -T{ -1. -2. DU< -> FALSE }T -T{ 0 1 1. DU< -> FALSE }T -T{ 1. 0 1 DU< -> TRUE }T -T{ 0 -1 1 -2 DU< -> FALSE }T -T{ 1 -2 0 -1 DU< -> TRUE }T - -T{ MAX-2INT HI-2INT DU< -> FALSE }T -T{ HI-2INT MAX-2INT DU< -> TRUE }T -T{ MAX-2INT MIN-2INT DU< -> TRUE }T -T{ MIN-2INT MAX-2INT DU< -> FALSE }T -T{ MIN-2INT LO-2INT DU< -> TRUE }T - -TESTING 2VALUE - -T{ 1111 2222 2VALUE 2VAL -> }T -T{ 2VAL -> 1111 2222 }T -T{ 3333 4444 TO 2VAL -> }T -T{ 2VAL -> 3333 4444 }T -T{ : TO-2VAL TO 2VAL ; 5555 6666 TO-2VAL -> }T -T{ 2VAL -> 5555 6666 }T - - -CR .( End of Double-Number word tests) CR diff --git a/MSP430-FORTH/MSP_EXP430FR5994/PROG100k.4TH b/MSP430-FORTH/MSP_EXP430FR5994/PROG100k.4TH deleted file mode 100644 index f629d96..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/PROG100k.4TH +++ /dev/null @@ -1,24955 +0,0 @@ - -; ----------------------------------- -; PROG100k.4th for MSP_EXP430FR5994 = 76 x RC5toLCD.4th for MSP_EXP430FR5994 -; ----------------------------------- -; download source file sized to compile 100 kbytes -; ----------------------------------- - - -CODE ABORT_RC5TOLCD -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_RC5TOLCD - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - - - -ECHO - ; downloading PROG100k.4th is done -RST_HERE ; this app is protected against <reset> - diff --git a/MSP430-FORTH/MSP_EXP430FR5994/RC5toLCD.4TH b/MSP430-FORTH/MSP_EXP430FR5994/RC5toLCD.4TH deleted file mode 100644 index 3fef6d5..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/RC5toLCD.4TH +++ /dev/null @@ -1,352 +0,0 @@ - -; ----------------------------------- -; RC5TOLCD.4th for MSP_EXP430FR5994 -; ----------------------------------- - - -CODE ABORT_RC5TOLCD -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_RC5TOLCD - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] - -MARKER {RC5TOLCD} -6 ALLOT - - - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] - -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -CODE 20_US -BEGIN - BEGIN - BIT #1,&$3C0 - 0<> UNTIL - BIC #1,&$3C0 - SUB #1,R14 -U< UNTIL -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -CODE TOP_LCD - BIS.B #4,&$243 - BIT.B #1,&$241 -0= IF - AND.B #$0F,R14 - MOV.B R14,&$222 - BIC.B #4,&$243 - MOV @R15+,R14 - MOV @R13+,R0 -THEN - SUB #2,R15 - MOV R14,0(R15) - BIC.B #4,&$243 - MOV.B &$220,R14 - AND.B #$0F,R14 - MOV @R13+,R0 -ENDCODE - -CODE LCD_WRC - BIS.B #2,&$243 -BW1 SUB #2,R15 - MOV R14,0(R15) - RRUM #4,R14 - BIC.B #1,&$243 - BIS.B #$0F,&$224 -COLON - TOP_LCD 2 20_US - TOP_LCD 2 20_US -; - -CODE LCD_WRF - BIC.B #2,&$243 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; -: LCD_HOME $02 LCD_WRF 100 20_us ; - - - -HDNCODE WDT_INT -BIT.B #$20,&$240 -0= IF - CMP #19,&$3D6 - U< IF - ADD #1,&$3D6 - THEN -ELSE - BIT.B #$40,&$240 - 0= IF - CMP #3,&$3D6 - U>= IF - SUB #1,&$3D6 - THEN - THEN -THEN -RETI -ENDCODE - -HDNCODE RC5_INT -$1800 @ 16000 = [IF] - MOV #1,&$3A0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3A0 -[THEN] -MOV #1778,R9 -MOV #14,R10 -BEGIN -MOV #%1011100100,&$380 - RRUM #1,R9 - MOV R9,R8 - RRUM #1,R8 - ADD R9,R8 - BEGIN CMP R8,&$390 - U>= UNTIL - BIT.B #4,&$200 - ADDC R11,R11 - MOV.B &$200,&$208 - BIC.B #4,&$20C - SUB #1,R10 -0<> WHILE - ADD R9,R8 - BEGIN - MOV &$390,R9 - CMP R8,R9 - U>= IF - BIC #$30,&$380 - GOTO FW1 - THEN - BIT.B #4,&$20C - 0<> UNTIL -REPEAT -BIC #$30,&$380 -RLAM #1,R11 -MOV.B R11,R9 -RRUM #2,R9 -BIT #$4000,R11 -0= IF BIS #$40,R9 -THEN -RRUM #3,R11 -XOR @R1,R11 -BIT #$400,R11 -0= ?GOTO FW2 -XOR #$400,0(R1) -SUB #8,R15 -MOV R14,6(R15) -MOV &$1DDC,4(R15) -MOV #$10,&$1DDC -MOV R9,0(R15) -MOV #0,R14 -LO2HI - LCD_CLEAR - <# # #S #36 HOLD #> - ['] LCD_WRC IS EMIT - TYPE - ['] EMIT >BODY IS EMIT -HI2LO -MOV @R15+,&$1DDC -MOV @R15+,R14 -FW1 FW2 - MOV @R1+,R2 - BIC #%1111_1000,R2 - MOV @R1+,R0 -ENDCODE - - -HDNCODE STOP_R2L -CMP #$40AA,&{RC5TOLCD}+8 -0<> IF - BIC.B #4,&$20A - BIC.B #4,&$20C - MOV #0,&$3C0 - MOV #0,&$340 - MOV #0,&$342 - MOV #$40AA,&{RC5TOLCD}+8 - MOV &{RC5TOLCD}+10,&WARM+2 - MOV &{RC5TOLCD}+12,&$FFEA - MOV &{RC5TOLCD}+14,&$FFDE - MOV &{RC5TOLCD}+10,R0 -THEN -MOV @R1+,R0 -ENDCODE - -CODE STOP -BW1 -CALL #STOP_R2L -COLON -ECHO -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; - -HDNCODE INI_R2L -BIC #1,&$130 -MOV &$1808,R14 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #%10_1101_0100,&$3C0 -$1800 @ 16000 = [IF] - MOV #1,&$3E0 -[THEN] -$1800 @ 24000 = [IF] - MOV #2,&$3E0 -[THEN] - MOV #19,&$3D2 -MOV #%0110_0000,&$3C6 - MOV #10,&$3D6 - BIS.B #$20,&$204 - BIS.B #$20,&$20A - BIS.B #7,&$245 - BIC.B #7,&$247 - BIS.B #$0F,&$224 - BIC.B #$0F,&$226 - BIS.B #4,&$20A - BIC.B #4,&$20C -MOV #%01_0001_0100,&$340 - MOV ##3276,&$352 - MOV #%10000,&$342 -COLON - #1000 20_US - %011 TOP_LCD - #205 20_US - %011 TOP_LCD - #5 20_US - %011 TOP_LCD - #2 20_US - %010 TOP_LCD - #2 20_US - %00101000 LCD_WRF - %1000 LCD_WRF - LCD_CLEAR - %0110 LCD_WRF - %1100 LCD_WRF - LCD_CLEAR - ['] LCD_HOME IS CR - ['] LCD_WRC IS EMIT - CR ." I love you" - ['] CR >BODY IS CR - ['] EMIT >BODY IS EMIT - ." RC5toLCD is running. Type STOP to quit" - ABORT" " -; - -CODE START -CMP #$40AA,&{RC5TOLCD}+8 -0= IF - MOV #STOP_R2L,&{RC5TOLCD}+8 - MOV &WARM+2,&{RC5TOLCD}+10 - MOV #INI_R2L,&WARM+2 - MOV &$FFEA,&{RC5TOLCD}+12 - MOV #WDT_INT,&$FFEA - MOV &$FFDE,&{RC5TOLCD}+14 - MOV #RC5_INT,&$FFDE - MOV #INI_R2L,R0 -THEN -MOV @R13+,R0 -ENDCODE - -ECHO - ; downloading RC5toLCD.4th is done -RST_HERE ; this app is protected against <reset> - -START diff --git a/MSP430-FORTH/MSP_EXP430FR5994/RTC.4TH b/MSP430-FORTH/MSP_EXP430FR5994/RTC.4TH deleted file mode 100644 index 2bb1286..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/RTC.4TH +++ /dev/null @@ -1,674 +0,0 @@ - -CODE ABORT_RTC -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$8000,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" target without LF_XTAL !" -PWR_STATE -; - -ABORT_RTC - -; -------------------- -; RTC.4th for MSP_EXP430FR5994 -; -------------------- - -[DEFINED] {RTC} [IF] {RTC} [THEN] - -MARKER {RTC} -8 ALLOT - - -[UNDEFINED] OR [IF] -CODE OR -BIS @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C! [IF] -CODE C! -MOV.B @R15+,0(R14) -ADD #1,R15 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DEPTH [IF] -CODE DEPTH -MOV R14,-2(R15) -MOV #$1C80,R14 -SUB R15,R14 -RRA R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] = [IF] -CODE = -SUB @R15+,R14 -0<> IF - AND #0,R14 - MOV @R13+,R0 -THEN -XOR #-1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] CASE [IF] -: CASE 0 ; IMMEDIATE - -: OF -1+ ->R -POSTPONE OVER POSTPONE = -POSTPONE IF -POSTPONE DROP -R> -; IMMEDIATE - -: ENDOF ->R -POSTPONE ELSE -R> -; IMMEDIATE - -: ENDCASE -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] - -CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 -ENDCODE - -CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE - -[THEN] - -[UNDEFINED] 2* [IF] -CODE 2* -ADD R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM* [IF] -CODE UM* - MOV @R15,&$4C0 - MOV R14,&$4C8 - MOV &$4E4,0(R15) - MOV &$4E6,R14 - MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] UM/MOD [IF] -CODE UM/MOD - PUSH #DROP - MOV #$4066,R0 -ENDCODE -[THEN] - -[UNDEFINED] U*/ [IF] -: U*/ ->R UM* R> UM/MOD SWAP DROP -; -[THEN] - -[UNDEFINED] U/MOD [IF] -: U/MOD -0 SWAP UM/MOD -; -[THEN] - -[UNDEFINED] UMOD [IF] -: UMOD -U/MOD DROP -; -[THEN] - -[UNDEFINED] U/ [IF] -: U/ -U/MOD SWAP DROP -; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] -: U.R - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -$81EF $1A04 @ U< ; search device ID: MSP430FR4133 or... -$1A04 @ $8241 U< ; ...MSP430FR2433 -= -$830B $1A04 @ U< ; MSP430FR21xx/23xx/24xx/25xx/26xx -OR ; -- flag - -[IF] - - - CREATE $4B0 2 ALLOT - CREATE $4B1 2 ALLOT - CREATE $4B2 2 ALLOT - CREATE $4B3 2 ALLOT - CREATE $4B4 2 ALLOT - CREATE $4B5 2 ALLOT - CREATE $4B6 2 ALLOT - - HDNCODE RTC_INT - ADD #2,R1 - BIT #1,&$4AE - ADD.B #1,&$4B0 - CMP.B #60,&$4B0 - U>= IF - MOV.B #0,&$4B0 - ADD.B #1,&$4B1 - CMP.B #60,&$4B1 - U>= IF - MOV.B #0,&$4B1 - ADD.B #1,&$4B2 - CMP.B #24,&$4B2 - U>= IF - MOV.B #0,&$4B2 - ADD.B #1,&$4B3 - CMP.B #7,&$4B3 - U>= IF - MOV.B #0,&$4B3 - THEN - ADD.B #1,&$4B4 - CMP.B #2,&$4B5 - 0= IF - COLON - $4B6 @ 4 UMOD - IF 29 - ELSE - $4B6 @ 100 UMOD - IF 30 - ELSE - $4B6 @ 400 UMOD - IF 29 - ELSE 30 - THEN - THEN - THEN - HI2LO - MOV @R1+,R13 - MOV R14,R9 - MOV @R15+,R14 - ELSE - MOV #31,R9 - MOV.B &$4B5,R10 - CMP.B #8,R10 - 0>= IF - ADD.B #1,R10 - THEN - BIT.B #1,R10 - 0<> IF - ADD #1,R9 - THEN - THEN - CMP.B R9,&$4B4 - U>= IF - MOV.B #1,&$4B4 - ADD.B #1,&$4B5 - CMP.B #13,&$4B5 - U>= IF - MOV.B #1,&$4B5 - ADD #1,&$4B6 - THEN - THEN - THEN - THEN - THEN - MOV @R1+,R0 - ENDCODE - - HDNCODE STOP_RTC - CMP #$40AA,&{RTC}+8 - 0<> IF - MOV #{RTC}+10,R9 - MOV #$40AA,-2(R9) - MOV @R9+,&RTC_VEC - MOV @R9+,&COLD+2 - MOV @R9+,&WARM+2 - THEN - MOV #0,&RTCCTL - MOV.B #XIN,R9 - BIC.B R9,&XT1_SEL - BIS.B R9,&XT1_DIR - BIC.B R9,&XT1_OUT - BIS.B R9,&XT1_OUT - BIC.B R9,&XT1_OUT - BIS.B R9,&XT1_OUT - BIC.B R9,&XT1_DIR - BIS.B R9,&XT1_SEL - MOV &COLD+2,R0 - ENDCODE - - HDNCODE INI_RTC - CALL &{RTC}+14 - CMP #0,&RTCCTL - 0= IF - MOV #$7F,&RTCMOD - BIT #-1,&$4AE - MOV #%0010_0110_0100_0010,&RTCCTL - THEN - MOV @R1+,R0 - ENDCODE - - - CODE START_RTC - CMP #STOP_RTC,&{RTC}+8 - 0<> IF - MOV #STOP_RTC,&{RTC}+8 - MOV &RTC_VEC,&{RTC}+10 - MOV #RTC_INT,&RTC_VEC - MOV &COLD+2,&{RTC}+12 - MOV #STOP_RTC,&COLD+2 - MOV &WARM+2,&{RTC}+14 - MOV #INI_RTC,&WARM+2 - THEN - CALL #INI_RTC - MOV @R13+,R0 - ENDCODE - - : TIME? - $4B2 C@ 2 U.R $3A EMIT - $4B1 C@ 2 U.R $3A EMIT - $4B0 C@ 2 U.R - ; - - : TIME! - START_RTC - 2 DEPTH - U< IF - $4B0 C! - $4B1 C! - $4B2 C! - THEN - ." it is " TIME? - ; - - : DATE? - -[ELSE] - - - CODE TIME? - BEGIN - BIT.B #$10,&$4A2 - 0<> UNTIL - COLON - $4B2 C@ 2 U.R $3A EMIT - $4B1 C@ 2 U.R $3A EMIT - $4B0 C@ 2 U.R - ; - - : TIME! - 2 DEPTH - U< IF - $4B0 C! - $4B1 C! - $4B2 C! - THEN - ." it is " TIME? - ; - - CODE DATE? - BEGIN - BIT.B #$10,&$4A2 - 0<> UNTIL - COLON - -[THEN] - - - $4B3 C@ - CASE - 0 OF ." Sat" ENDOF - 1 OF ." Sun" ENDOF - 2 OF ." Mon" ENDOF - 3 OF ." Tue" ENDOF - 4 OF ." Wed" ENDOF - 5 OF ." Thu" ENDOF - 6 OF ." Fri" ENDOF - ENDCASE - $4B6 @ - $4B5 C@ - $4B4 C@ - $20 EMIT - 2 U.R $2F EMIT - 2 U.R $2F EMIT - . -; - - - -: DATE! -2 DEPTH -U< IF - $4B6 ! - $4B5 C! - $4B4 C! -THEN -$4B4 C@ -$4B5 C@ -$4B6 @ -OVER 3 U< -IF 1 - SWAP 12 + SWAP -THEN -100 U/MOD -DUP 4 U/ SWAP 2* - -SWAP DUP 4 U/ + + -SWAP 1+ 13 5 U*/ + + -7 UMOD -$4B3 C! -." we are on " DATE? -; - -RST_HERE - -[UNDEFINED] S_ [IF] -CODE S_ -MOV #0,&$1DB4 -COLON -$4014 , -$20 WORD -HI2LO -MOV.B @R14,R14 -ADD #1,R14 -BIT #1,R14 -ADDC R14,&$1DC6 -MOV @R15+,R14 -MOV @R1+,R13 -MOV #$20,&$1DB4 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&$1DBE -0= IF MOV @R13+,R0 -THEN -COLON -$1B -POSTPONE LITERAL -POSTPONE EMIT -POSTPONE S_ -POSTPONE TYPE -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] EXECUTE [IF] -CODE EXECUTE -PUSH R14 -MOV @R15+,R14 -MOV @R1+,R0 -ENDCODE -[THEN] - -[UNDEFINED] EVALUATE [IF] -CODE EVALUATE -MOV #$1DC0,R9 -MOV @R9+,R12 -MOV @R9+,R11 -MOV @R9+,R10 -PUSHM #4,R13 -LO2HI -INTERPRET -HI2LO -MOV @R1+,&$1DC4 -MOV @R1+,&$1DC2 -MOV @R1+,&$1DC0 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -: SET_TIME -ESC [8;40;80t -39 0 DO CR LOOP -ESC [H -CR ." DATE (DMY): " -$1CE4 DUP #84 -['] ACCEPT >BODY -EXECUTE -EVALUATE -CR DATE! -CR ." TIME (HMS): " -$1CE4 DUP #84 -['] ACCEPT >BODY -EXECUTE -EVALUATE -CR TIME! -RST_STATE -; - -ECHO -SET_TIME diff --git a/MSP430-FORTH/MSP_EXP430FR5994/SD_TEST.4TH b/MSP430-FORTH/MSP_EXP430FR5994/SD_TEST.4TH deleted file mode 100644 index eaa3e9f..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/SD_TEST.4TH +++ /dev/null @@ -1,430 +0,0 @@ - -; ----------- -; SD_TEST.4th for MSP_EXP430FR5994 -; ----------- - -CODE ABORT_SD_TEST -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_SD_TEST - -PWR_STATE - -[DEFINED] {SD_TEST} [IF] {SD_TEST} [THEN] - -MARKER {SD_TEST} - -[UNDEFINED] EXIT [IF] -CODE EXIT -MOV @R1+,R13 -MOV @R13+,R0 - -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 0= [IF] -CODE 0= -SUB #1,R14 -SUBC R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -CODE ELSE -ADD #4,&$1DC6 -MOV &$1DC6,R10 -MOV #$403A,-4(R10) -MOV R10,0(R14) -SUB #2,R10 -MOV R10,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] -CODE BEGIN - MOV #$4028,R0 -ENDCODE IMMEDIATE - -CODE UNTIL - MOV #$4034,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE AGAIN -MOV #$403A,R9 -GOTO BW1 -ENDCODE IMMEDIATE - -: WHILE -POSTPONE IF SWAP -; IMMEDIATE - -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] - CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 - ENDCODE - - CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 - ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -$20 EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -$1DBE CONSTANT STATE -[THEN] - -[UNDEFINED] IS [IF] -CODE DEFER! -MOV @R15+,2(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] U.R [IF] -: U.R ->R <# 0 # #S #> -R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DUMP [IF] -CODE DUMP -PUSH R13 -PUSH &$1DDC -MOV #$10,&$1DDC -ADD @R15,R14 -LO2HI - SWAP - DO CR - I 4 U.R SPACE - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> $1DDC ! -; -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #BEGIN,R0 -ENDCODE -[THEN] - - -CODE SD_EMIT -CMP #512,&$201E -U>= IF - MOV #WRITE,R9 - CALL 2(R9) -THEN -MOV &$201E,R8 -MOV.B R14,$1E00(R8) -ADD #1,&$201E -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - -: SD_TEST -PWR_HERE -CR -." 0 Set date and time" CR -." 1 Load {TOOLS} words" CR -." 2 Load {SD_TOOLS} words" CR -." 3 Load {CORE_COMP} words" CR -." 4 Load ANS core tests" CR -." 5 Load a 100k program " CR -." 6 Read only this source file" CR -." 7 append a dump of FORTH to YOURFILE.TXT" CR -." 8 delete YOURFILE.TXT" CR -." 9 Load TST_WORDS" CR -." your choice : " -KEY -48 - ?DUP -0= IF - ." LOAD RTC.4TH" CR - LOAD" RTC.4TH" -ELSE 1 - ?DUP - 0= IF - ." LOAD UTILITY.4TH" CR - LOAD" UTILITY.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD SD_TOOLS.4TH" CR - LOAD" SD_TOOLS.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD CORE_ANS.4TH" CR - LOAD" CORE_ANS.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD CORETEST.4TH" CR - LOAD" CORETEST.4TH" - PWR_STATE - ELSE 1 - ?DUP - 0= IF - ." LOAD PROG100K.4TH" CR - NOECHO - LOAD" PROG100K.4TH" - ELSE 1 - ?DUP - 0= IF - ." READ PROG100K.4TH" CR - READ" PROG100K.4TH" - BEGIN - READ - UNTIL - ELSE 1 - ?DUP - 0= IF - ." WRITE YOURFILE.TXT" CR - WRITE" YOURFILE.TXT" - ['] SD_EMIT IS EMIT - $4000 HERE OVER - DUMP - ['] EMIT >BODY IS EMIT - CLOSE - ELSE 1 - ?DUP - 0= IF - ." DEL YOURFILE.TXT" CR - DEL" YOURFILE.TXT" - ELSE 1 - ?DUP - 0= IF - ." LOAD TSTWORDS.4TH" CR - LOAD" TSTWORDS.4TH" - ELSE - ." abort" ABORT" " - THEN - THEN - THEN - THEN - THEN - THEN - THEN - THEN - THEN -THEN -; - - - -RST_HERE - -[THEN] - -ECHO SD_TEST diff --git a/MSP430-FORTH/MSP_EXP430FR5994/SD_TOOLS.4TH b/MSP430-FORTH/MSP_EXP430FR5994/SD_TOOLS.4TH deleted file mode 100644 index b2b77fb..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/SD_TOOLS.4TH +++ /dev/null @@ -1,257 +0,0 @@ - - -; --------------------------------------------------------------- -; SD_TOOLS.4th for MSP_EXP430FR5994 : BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER -; --------------------------------------------------------------- - -CODE ABORT_SD_TOOLS -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_SD_TOOLS - - -[DEFINED] {SD_TOOLS} [IF] {SD_TOOLS} [THEN] - -[UNDEFINED] {SD_TOOLS} [IF] - -MARKER {SD_TOOLS} - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] - -CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 -ENDCODE - -CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE - -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -$20 EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] -: U.R - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUMP [IF] -CODE DUMP -PUSH R13 -PUSH &$1DDC -MOV #$10,&$1DDC -ADD @R15,R14 -LO2HI - SWAP - DO CR - I 4 U.R SPACE - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> $1DDC ! -; -[THEN] - -CODE SECTOR. -BW1 MOV R14,R9 - MOV @R15,R10 - CALL #READ_SWX -COLON - <# #S #> TYPE SPACE - $1E00 $200 DUMP CR ; - -CODE CLUSTR. -BW2 BIT.B #4,&$260 - 0<> IF - MOV #COLD,R0 - THEN - MOV.B &$2012,R10 - MOV @R15,R9 - GOTO FW1 - BEGIN - ADD R9,R9 - ADDC R14,R14 -FW1 RRA R10 - U>= UNTIL - ADD &$2010,R9 - MOV R9,0(R15) - ADDC #0,R14 - GOTO BW1 -ENDCODE - -CODE FAT - SUB #4,R15 - MOV R14,2(R15) - MOV &$2008,0(R15) - MOV #0,R14 - GOTO BW1 -ENDCODE - -CODE DIR - SUB #4,R15 - MOV R14,2(R15) - MOV &$202C,0(R15) - MOV &$202E,R14 - CMP #0,R14 - 0<> ?GOTO BW2 - CMP #1,0(R15) - 0<> ?GOTO BW2 - MOV &$200E,0(R15) - GOTO BW1 -ENDCODE - - -RST_HERE - -[THEN] -ECHO - diff --git a/MSP430-FORTH/MSP_EXP430FR5994/TESTASM.4TH b/MSP430-FORTH/MSP_EXP430FR5994/TESTASM.4TH deleted file mode 100644 index edebebf..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/TESTASM.4TH +++ /dev/null @@ -1,512 +0,0 @@ - -; ----------------------------------------------------------------------- -; TEST_ASM.4th for MSP_EXP430FR5994 -; ----------------------------------------------------------------------- - -CODE ABORT_TEST_ASM -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_TEST_ASM - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -MOV R7,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] - -CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 -ENDCODE - -CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE - -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] VARIABLE [IF] -: VARIABLE -CREATE -HI2LO -MOV #$1287,-4(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DEFER [IF] - -: DEFER -CREATE -HI2LO -MOV #$4030,-4(R10) -MOV #$403C,-2(R10) -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >BODY [IF] -CODE >BODY -ADD #4,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -$20 EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] -: U.R - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] LOOP [IF] -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] +LOOP [IF] -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUMP [IF] -CODE DUMP -PUSH R13 -PUSH &$1DDC -MOV #$10,&$1DDC -ADD @R15,R14 -LO2HI - SWAP - DO CR - I 4 U.R SPACE - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> $1DDC ! -; -[THEN] - -CODE TESTPUSHM -BW1 - MOV #22222,R8 - MOV #3,R9 - MOV #2,R10 - MOV #1,R11 - MOV #0,R12 - - PUSHM #4,R13 - POPM #4,R13 - SUB #10,R15 - MOV R14,8(R15) - MOV R12,6(R15) - MOV R11,4(R15) - MOV R10,2(R15) - MOV R9,0(R15) - MOV R8,R14 - RRAM #1,R14 - RLAM #2,R14 - RRCM #1,R14 - RRUM #1,R14 - COLON - space . . . . . - ; - -TESTPUSHM ; you should see 11111 3 2 1 0 --> - -CODE TESTPOPM - GOTO BW1 -ENDCODE - - -TESTPOPM ; you should see 11111 3 2 1 0 --> - - - -CODE TEST1 - - MOV &$1DDC,&$1DDC - CMP #%10,&$1DDC -0<> IF MOV #2,&$1DDC -ELSE MOV #$0A,&$1DDC -THEN - COLON - $1DDC @ U. - ; - - -: TEST2 - $1DDC @ U. - HI2LO - - - CMP #2, &$1DDC -0<> IF MOV #2, &$1DDC -ELSE MOV #10,&$1DDC -THEN - MOV @R1+,R13 - MOV @R13+,R0 -ENDCODE - - -CODE TEST3 - CMP #2, &$1DDC -0<> IF MOV #2, &$1DDC -ELSE MOV #10,&$1DDC -THEN COLON - $1DDC @ U. -; - - - -: TEST5 - SPACE - HI2LO - SUB #2,R15 - MOV R14,0(R15) - MOV #%1010,R14 -BEGIN SUB #$0001,R14 - LO2HI - - DUP U. - HI2LO - CMP #0,R14 -0= UNTIL MOV @R15+,R14 - MOV @R1+,R13 - MOV @R13+,R0 -ENDCODE - -TEST5 ; you should see : 9 8 7 6 5 4 3 2 1 0 --> - - - -[UNDEFINED] C, [IF] -CODE C, -MOV &$1DC6,R10 -MOV.B R14,0(R10) -ADD #1,&$1DC6 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -: BYTES_TABLE_IDX -CREATE -0 DO I C, -LOOP -DOES> -+ -; - -8 BYTES_TABLE_IDX BYTES_TABLE - -2 BYTES_TABLE C@ . ; you should see 2 --> - - -VARIABLE BYTES_TABLE1 - -$0201 BYTES_TABLE1 ! - -CODE IDX_TEST1 - MOV.B BYTES_TABLE1(R14),R14 -COLON - U. -; - -0 IDX_TEST1 ; you should see 1 --> - -CODE TEST6 - MOV 0(R15),0(R15) - MOV @R13+,R0 -ENDCODE - - -1 TEST6 . ; you should see 1 --> - - - - - -CREATE TABLE0 -0 C, -1 C, -2 C, -3 C, - - -CREATE TABLE10 -$10 C, -$11 C, -$12 C, -$13 C, - - - -CREATE TABLE20 -$20 C, -$21 C, -$22 C, -$23 C, - - -CREATE TABLE - - -TABLE 2 - CONSTANT PFA_TABLE - - -CODE REDIRECT ; <table> -- redirects TABLE to argument <table> -MOV R14,&PFA_TABLE -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE - - -CODE REDIRECT0 ; -- redirects TABLE to TABLE0 -MOV #TABLE0,&PFA_TABLE -MOV @R13+,R0 -ENDCODE - - -CODE REDIRECT10 ; -- redirects TABLE to TABLE10 -MOV #TABLE10,&PFA_TABLE -MOV @R13+,R0 -ENDCODE - - -CODE REDIRECT20 ; -- redirects TABLE to TABLE20 -MOV #TABLE20,&PFA_TABLE -MOV @R13+,R0 -ENDCODE - - -' TABLE0 10 DUMP - -' TABLE10 10 DUMP - -' TABLE20 10 DUMP - - -TABLE0 REDIRECT TABLE 10 DUMP - -TABLE10 REDIRECT TABLE 10 DUMP - -TABLE20 REDIRECT TABLE 10 DUMP - - -REDIRECT0 TABLE 10 DUMP - -REDIRECT10 TABLE 10 DUMP - -REDIRECT20 TABLE 10 DUMP - - -TABLE0 PFA_TABLE ! TABLE 10 DUMP - -TABLE10 PFA_TABLE ! TABLE 10 DUMP - -TABLE20 PFA_TABLE ! TABLE 10 DUMP - - - - -; ----------------------------------------------------------------------- -; create a primary DEFERred assembly word -; ----------------------------------------------------------------------- - - -DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY) - - - -CODENNM ; leaves its execution address (CFA) on stack - SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -DUP . - -IS TRUC ; TRUC becomes a primary DEFERred word - ; with its default action (DUP) located at its BODY addresse. - -TRUC . ; display R14 value --> - - -' TRUC >BODY IS TRUC ; TRUC is reinitialzed with its default action - - -TRUC . ; display R14 value --> - - - - - diff --git a/MSP430-FORTH/MSP_EXP430FR5994/TSTWORDS.4TH b/MSP430-FORTH/MSP_EXP430FR5994/TSTWORDS.4TH deleted file mode 100644 index fb92b9c..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/TSTWORDS.4TH +++ /dev/null @@ -1,90 +0,0 @@ -\ ----------------------------- -\ MSP-EXP430FR5969_TSTWORDS.4th -\ ----------------------------- - -PWR_STATE - -\ ----------------------------------------------------------------------- -\ test some assembler words and show how to mix FORTH/ASSEMBLER routines -\ ----------------------------------------------------------------------- -LOAD" \misc\TestASM.4th" - -\ ------------------------------------- -\ here we returned in the TestWords.4th -\ ------------------------------------- -ECHO -\ ---------- -\ LOOP tests -\ ---------- -: LOOP_TEST 8 0 DO I . LOOP -; - -LOOP_TEST \ you should see 0 1 2 3 4 5 6 7 --> - - -: LOOP_TEST1 \ n <LOOP_TEST1> --- - - BEGIN DUP U. 1 - - ?DUP - 0= UNTIL -; - -: LOOP_MAX \ FIND_NOTHING -- - 0 0 - DO - LOOP \ 14 cycles by loop - ABORT" 65536 LOOP " -; - - : FIND_TEST \ FIND_TEST <word> -- - $20 WORD \ -- c-addr - 50000 0 - DO \ -- c-addr - DUP - FIND DROP DROP - LOOP - FIND - 0= IF ABORT" <-- not found !" - ELSE ABORT" <-- found !" - THEN - ; - -\ seeking $ word, FIND jumps all words on their first character so time of word loop is 20 cycles -\ see FIND in the source file for more information -\ -\ FIND_TEST <lastword> result @ 8MHz, monothread : 1,2s -\ -\ FIND_TEST $ results @ 8MHz, monothread, 201 words in vocabulary FORTH : -\ 27 seconds with only FORTH vocabulary in CONTEXT -\ 540 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 2.6866 us / word, 21,49 cycles / word (for 20 cycles calculated (see FIND in source file) -\ -\ -\ FIND_TEST $ results @ 8MHz, 2 threads, 201 words in vocabulary FORTH : -\ 13 second with only FORTH vocabulary in CONTEXT -\ 260 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 1,293 us / word, 10,34 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 4 threads, 201 words in vocabulary FORTH : -\ 8 second with only FORTH vocabulary in CONTEXT -\ 160 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,796 us / word, 6,37 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 8 threads, 201 words in vocabulary FORTH : -\ 4.66 second with only FORTH vocabulary in CONTEXT -\ 93 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,4463 us / word, 3,7 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 16 threads, 201 words in vocabulary FORTH : -\ 2,8 second with only FORTH vocabulary in CONTEXT -\ 56 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,278 us / word, 2,22 cycles / word -\ -\ -------- -\ KEY test -\ -------- -: KEY_TEST - ." type a key : " - KEY EMIT \ wait for a KEY, then emit it -; -\ KEY_TEST diff --git a/MSP430-FORTH/MSP_EXP430FR5994/UARTI2CS.4TH b/MSP430-FORTH/MSP_EXP430FR5994/UARTI2CS.4TH deleted file mode 100644 index fb338a6..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/UARTI2CS.4TH +++ /dev/null @@ -1,297 +0,0 @@ -; ---------------------------------------------------------------------- -; UARTI2CS.4th for MSP_EXP430FR5994 -; ---------------------------------------------------------------------- - -CODE ABORT_UARTI2CS -SUB #4,R15 -MOV R14,2(R15) -MOV &$1812,R14 -BIT #$7800,R14 -0<> IF MOV #0,R14 THEN -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -ABORT" <-- Ouch! unexpected I2C_FastForth target!" -PWR_STATE -; - -ABORT_UARTI2CS - -[DEFINED] {UARTI2CS} -[IF] {UARTI2CS} -[THEN] - -MARKER {UARTI2CS} -8 ALLOT - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] - -$FFA2 CONSTANT I2CS_ADR - -HDNCODE I2CSTOP -BIS.B #2,&$265 -MOV R0,R0 -BIS.B #4,&$265 -MOV R0,R0 -BIC.B #2,&$265 -MOV R0,R0 -BIC.B #4,&$265 -MOV @R1+,R0 -ENDCODE - -HDNCODE STOP_U2I -BW1 -CMP #$40AA,&{UARTI2CS}+8 -0<> IF - CALL #I2CSTOP - MOV #6,R10 - BIC.B R10,&$265 - BIS.B R10,&$263 - BIS.B R10,&$267 - MOV #0,&$3C0 - MOV #{UARTI2CS}+10,R10 - MOV #$40AA,-2(R10) - MOV @R10+,&WARM+2 - MOV @R10+,&$FFF0 - MOV @R10+,&$FFF4 - MOV #1,R14 -THEN -MOV @R1+,R0 -ENDCODE - - - -HDNCODE U2I_TERM_INT -ADD #4,R1 -MOV &{UARTI2CS}+16,R10 -MOV #$1CE4,R11 -MOV #$0D,R12 -BEGIN - MOV.B &$5CC,R8 - ADD #1,R11 - MOV.B R8,-1(R11) - CMP.B R8,R12 -0<> WHILE - CMP #0,R10 - 0= IF - BEGIN - BIT #2,&$5DC - 0<> UNTIL - MOV.B R8,&$5CE - THEN - BEGIN - BIT #1,&$5DC - 0<> UNTIL -REPEAT -CALL #$41C8 -BEGIN - BIT #1,&$5DC -0<> UNTIL -BW2 -MOV.B &$5CC,R12 -MOV.B R12,0(R11) -BW3 -BIS.B #4,&$265 -MOV.B &I2CS_ADR,R9 -MOV #$1CE4,R8 -MOV R0,R0 -BIS.B #2,&$265 -BEGIN - MOV.B #8,R10 - BEGIN - ADD.B R9,R9 - U>= IF - BIC.B #4,&$265 - ELSE - BIS.B #4,&$265 - THEN - BIC.B #2,&$265 - BEGIN - BIT.B #2,&$261 - 0<> UNTIL - BIS.B #2,&$265 - SUB #1,R10 - 0= UNTIL - BIC.B #4,&$265 - BIC.B #2,&$265 - MOV R0,R0 - BIT.B #4,&$261 - BIS.B #2,&$265 -0= WHILE - CMP R12,R11 -0<> WHILE - MOV.B @R8+,R9 - MOV R9,R11 -REPEAT -THEN -GOTO FW1 -ENDCODE - - -HDNCODE HALF_S_INT -ADD #4,R1 -FW1 -BW3 -CMP #0,&$1812 -0>= IF - MOV #%0001_0101_0110,&$3C0 -ELSE - MOV #%0001_1101_0110,&$3C0 -THEN -BEGIN - BIC.B #2,&$265 - BIT #8,&$5CA - 0<> ?GOTO BW1 - BIS.B #4,&$265 - MOV.B &I2CS_ADR,R8 - BIS.B #1,R8 - $3C00 , - BIS.B #2,&$265 - MOV.B #8,R10 - BEGIN - ADD.B R8,R8 - U>= IF - BIC.B #4,&$265 - ELSE - BIS.B #4,&$265 - THEN - BIC.B #2,&$265 - MOV R0,R0 - BIS.B #2,&$265 - SUB #1,R10 - 0= UNTIL - BIC.B #4,&$265 - BIC.B #2,&$265 - BEGIN - BIT.B #2,&$261 - 0<> UNTIL - BIT.B #4,&$261 - BIS.B #2,&$265 - 0<> IF - CALL #I2CSTOP - MOV #$4000,R0 - THEN - BEGIN - BEGIN - BIC.B #4,&$265 - MOV.B #8,R10 - BEGIN - BIC.B #2,&$265 - MOV R0,R0 - BIT.B #4,&$261 - BIS.B #2,&$265 - ADDC.B R9,R9 - SUB #1,R10 - 0= UNTIL - CMP.B #-1,R9 - 0= IF - MOV #2,R9 - THEN - CMP.B #8,R9 - U>= WHILE - BEGIN - BIT #2,&$5DC - 0<> UNTIL - BIS.B #4,&$265 - BIC.B #2,&$265 - BEGIN - BIT.B #2,&$261 - 0<> UNTIL - MOV.B R9,&$5CE - BIS.B #2,&$265 - REPEAT - CMP.B #4,R9 - U>= IF - MOV #0,&{UARTI2CS}+16 - 0= IF - MOV #-1,&{UARTI2CS}+16 - THEN - BIS.B #4,&$265 - THEN - BIC.B #2,&$265 - BEGIN - BIT.B #2,&$261 - 0<> UNTIL - BIT.B #4,&$261 - BIS.B #2,&$265 - 0<> UNTIL - CMP.B #2,R9 -U>= WHILE - 0= IF - MOV #0,&{UARTI2CS}+16 - CALL #$41C6 - BEGIN - BIC #1,&$5DC - MOV &$1800,R8 - BEGIN MOV #32,R10 - BEGIN SUB #1,R10 - 0= UNTIL - SUB #1,R8 - 0= UNTIL - BIT #1,&$5DC - 0= UNTIL - THEN -REPEAT -CALL #I2CSTOP -CMP.B #1,R9 -0= IF - MOV #$1CE4,R11 - CALL #$41C6 - BEGIN - BIT #1,&$5DC - 0<> UNTIL - CALL #$41C8 - GOTO BW2 -THEN -MOV #$4000,R0 -ENDCODE - -HDNCODE INI_U2I -CALL &{UARTI2CS}+10 -CMP #$0E,R14 -0<> IF - CMP #$0A,R14 - U>= ?GOTO BW1 -THEN -BIT.B #$20,&$240 -0= ?GOTO BW1 -MOV #0,&$1808 -MOV #$800,&$3D2 -BIC.B #6,&$267 -BIC.B #6,&$263 -GOTO BW3 -ENDCODE - -: UARTI2CS -CR I2CS_ADR ! -HI2LO -CMP #$40AA,&{UARTI2CS}+8 -0= IF - MOV #STOP_U2I,&{UARTI2CS}+8 - MOV &WARM+2,&{UARTI2CS}+10 - MOV &$FFF0,&{UARTI2CS}+12 - MOV &$FFF4,&{UARTI2CS}+14 - - MOV #0,&{UARTI2CS}+16 - MOV #INI_U2I,&WARM+2 - MOV #U2I_TERM_INT,&$FFF0 - MOV #HALF_S_INT,&$FFF4 - -THEN -MOV #WARM,R0 -ENDCODE - -RST_HERE ECHO -18 UARTI2CS ; TERATERM(Alt-B) or I2C_Master($20+RST) to quit diff --git a/MSP430-FORTH/MSP_EXP430FR5994/UTILITY.4TH b/MSP430-FORTH/MSP_EXP430FR5994/UTILITY.4TH deleted file mode 100644 index 2649d8f..0000000 --- a/MSP430-FORTH/MSP_EXP430FR5994/UTILITY.4TH +++ /dev/null @@ -1,451 +0,0 @@ - - -; ------------------------------------------------------------------------------ -; UTILITY.4th for MSP_EXP430FR5994 -; ------------------------------------------------------------------------------ - -CODE ABORT_UTILITY -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_UTILITY - -PWR_STATE - -[DEFINED] {TOOLS} [IF] {TOOLS} [THEN] - -[UNDEFINED] {TOOLS} [IF] - -MARKER {TOOLS} - -[UNDEFINED] EXIT [IF] -CODE EXIT -MOV @R1+,R13 -MOV @R13+,R0 - -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @R15+,R14 -0<> IF - MOV #-1,R14 - U< IF - AND #0,R14 - THEN -THEN -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] -CODE IF -SUB #2,R15 -MOV R14,0(R15) -MOV &$1DC6,R14 -ADD #4,&$1DC6 -MOV #$4034,0(R14) -ADD #2,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE THEN -MOV &$1DC6,0(R14) -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] -CODE BEGIN - MOV #$4028,R0 -ENDCODE IMMEDIATE - -CODE UNTIL - MOV #$4034,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE AGAIN -MOV #$403A,R9 -GOTO BW1 -ENDCODE IMMEDIATE - -: WHILE -POSTPONE IF SWAP -; IMMEDIATE - -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 - MOV R9,-4(R10) - MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT - MOV @R15+,R14 - MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] -CODE DUP -BW1 SUB #2,R15 - MOV R14,0(R15) - MOV @R13+,R0 -ENDCODE - -CODE ?DUP -CMP #0,R14 -0<> ?GOTO BW1 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - - -[UNDEFINED] DROP [IF] -CODE DROP -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -$20 EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL - MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 2DUP [IF] -CODE 2DUP -MOV R14,-2(R15) -MOV @R15,-4(R15) -SUB #4,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] -CODE 1+ -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] AND [IF] -CODE AND -AND @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] ROT [IF] -CODE ROT -MOV @R15,R10 -MOV R14,0(R15) -MOV 2(R15),R14 -MOV R10,2(R15) -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] - CODE MAX - CMP @R15,R14 - S< ?GOTO FW1 -BW1 ADD #2,R15 - MOV @R13+,R0 - ENDCODE - - CODE MIN - CMP @R15,R14 - S< ?GOTO BW1 -FW1 MOV @R15+,R14 - MOV @R13+,R0 - ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] -CODE MOVE -MOV R14,R10 -MOV @R15+,R8 -MOV @R15+,R9 -MOV @R15+,R14 -CMP #0,R10 -0<> IF - CMP R9,R8 - 0= ?GOTO FW1 - U< IF - BEGIN - MOV.B @R9+,0(R8) - ADD #1,R8 - SUB #1,R10 - 0= UNTIL - MOV @R13+,R0 - ELSE - ADD R10,R8 - ADD R10,R9 - BEGIN - SUB #1,R9 - SUB #1,R8 - MOV.B @R9,0(R8) - SUB #1,R10 - 0= UNTIL - THEN -THEN -FW1 MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] .S [IF] -CODE .S - MOV R14,-2(R15) - MOV R15,R14 - SUB #2,R14 - MOV R14,-6(R15) - MOV #$1C80,R14 - SUB #2,R14 -BW1 MOV R14,-4(R15) - SUB #6,R15 - SUB @R15,R14 - RRA R14 -COLON - $3C EMIT - . - $08 EMIT - $3E EMIT SPACE - 2DUP 1+ - U< IF - DROP DROP EXIT - THEN - $1DDC @ >R - $10 $1DDC ! - DO - I @ U. - 2 +LOOP - R> $1DDC ! -; -[THEN] - -[UNDEFINED] .RS [IF] -CODE .RS - MOV R14,-2(R15) - MOV R1,-6(R15) - MOV #$1CE0,R14 - GOTO BW1 -ENDCODE -[THEN] - -[UNDEFINED] ? [IF] -CODE ? - MOV @R14,R14 - MOV #U.,R0 -ENDCODE -[THEN] - -[UNDEFINED] WORDS [IF] -: WORDS -CR -$1DCA @ $1CE4 -$1810 @ DUP + -MOVE -BEGIN - 0 DUP - $1810 @ DUP + 0 - DO - DUP I $1CE4 + @ - U< IF - DROP DROP - I DUP $1CE4 + @ - THEN - 2 +LOOP - ?DUP -WHILE - DUP - 2 - @ - ROT - $1CE4 + - ! - DUP - COUNT $7F AND - TYPE - C@ $0F AND - $10 SWAP - SPACES -REPEAT -DROP -; -[THEN] - -[UNDEFINED] U.R [IF] -: U.R ->R <# 0 # #S #> -R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DUMP [IF] -CODE DUMP -PUSH R13 -PUSH &$1DDC -MOV #$10,&$1DDC -ADD @R15,R14 -LO2HI - SWAP 2DUP - U. U. - $FFF0 AND - DO CR - I 4 U.R SPACE - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> $1DDC ! -; -[THEN] - -RST_HERE - -[THEN] -ECHO diff --git a/MSP430-FORTH/PROG100k.f b/MSP430-FORTH/PROG100k.f deleted file mode 100644 index 60f2128..0000000 --- a/MSP430-FORTH/PROG100k.f +++ /dev/null @@ -1,41675 +0,0 @@ -\ -*- coding: utf-8 -*- - -; ----------------------------------- -; PROG100k.f = 76 x RC5toLCD.f -; ----------------------------------- -; download source file sized to compile 100 kbytes -; ----------------------------------- - -\ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) -\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 -\ MSP_EXP430FR2355 -\ LP_MSP430FR2476 -\ -\ from scite editor : copy your target selection in (shift+F8) parameter 1: -\ -\ OR -\ -\ drag and drop this file onto SendSourceFileToTarget.bat -\ then select your TARGET when asked. -\ -\ -\ REGISTERS USAGE -\ R4 to R7 must be saved before use and restored after -\ scratch registers Y to S are free for use -\ under interrupt, IP is free for use -\ interrupts reset SR register ! -\ -\ PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC -\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0 -\ -\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack -\ -\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP -\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15 -\ -\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack -\ -\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= -\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0< -\ -\ FORTH conditionnal : 0= 0< = < > U< -\ -\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol -\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM) -\ LPM_MODE = LPM0 because use SMCLK for LCDVo -\ -\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol -\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface -\ without usage of an auxiliary 5V to feed the LCD_Vo -\ and without potentiometer to adjust the LCD contrast : -\ to adjust LCD contrast, just press S1 (-) or S2 (+) -\ LCDVo current consumption ~ 500 uA. -\ -\ =================================================================================== -\ notice : adjust WDT_TIM_EX0,LCD_TIM_CTL,LCD_TIM_EX0 and 20_us to the target frequency if <> 8MHz ! -\ =================================================================================== -\ -\ -\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433) -\ -\ GND <-------+---0V0----------> 1 LCD_Vss -\ VCC >------ | --3V6-----+----> 2 LCD_Vdd -\ | | -\ ___ 470n --- -\ ^ --- -\ / \ 1N4148 | -\ --- | -\ 100n | 2k2 | -\ LCD_TIM_.2 >---||--+--^/\/\/v--+----> 3 LCD_Vo (= 0V6 without modulation) -\ -------------------------> 4 LCD_RW -\ -------------------------> 5 LCD_RW -\ -------------------------> 6 LCD_EN -\ <------------------------> 11 LCD_DB4 -\ <------------------------> 12 LCD_DB5 -\ <------------------------> 13 LCD_DB5 -\ <------------------------> 14 LCD_DB7 -\ -\ <----- LCD contrast + <--- Sw1 <--- (finger) :-) -\ <----- LCD contrast - <--- Sw2 <--- (finger) :-) -\ -\ rc5 <--- OUT IR_Receiver (1 TSOP32236) - -\ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_RC5TOLCD -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_UARTI2CS definition before resuming -; - -ABORT_RC5TOLCD - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] = [IF] -\ https://forth-standard.org/standard/core/Equal -\ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN -\ https://forth-standard.org/standard/core/IF -\ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/THEN -\ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] -\ https://forth-standard.org/standard/core/ELSE -\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] -\ https://forth-standard.org/standard/core/toBODY -\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ - MOV @IP+,PC -THEN \ read LCD bits pattern - SUB #2,PSP - MOV TOS,0(PSP) - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV.B &LCD_DB_IN,TOS \ get LCD_Data - AND.B #LCD_DB,TOS \ - MOV @IP+,PC -ENDCODE - -CODE LCD_WRC \ char -- Write Char - BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL - RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH - BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 - BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here - TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; - -CODE LCD_WRF \ func -- Write Fonction - BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 - GOTO BW1 -ENDCODE - -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; - -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ -\ CODE LCD_RDS \ -- status Read Status -\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 -\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput -\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 -\ COLON \ starts a FORTH word -\ TOP_LCD 2 20_us \ -- %0000_HHHH -\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL -\ HI2LO \ switch from FORTH to assembler -\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL -\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL -\ MOV @RSP+,IP \ restore IP saved by COLON -\ MOV @IP+,PC \ -\ ENDCODE -\ -\ CODE LCD_RDC \ -- char Read Char -\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 -\ GOTO BW1 -\ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment - THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ -\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 -\ - - \CNTL Counter lentgh \ 00 = 16 bits -\ -- \TBSSEL TimerB clock select \ 10 = SMCLK -\ -- \ID input divider \ 10 = /4 -\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 -\ - \TBCLR TimerB Clear -\ - \TBIE -\ -\TBIFG -\ -------------------------------\ -\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} -\ -- \CM Capture Mode -\ -- \CCIS -\ - \SCS -\ -- \CLLD -\ - \CAP -\ --- \OUTMOD \ 011 = set/reset -\ - \CCIE -\ - \CCI -\ - \OUT -\ - \COV -\ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ -\ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - - - -ECHO - ; downloading PROG100k.4th is done -RST_HERE ; this app is protected against <reset> - -\ START diff --git a/MSP430-FORTH/PROG10K.f b/MSP430-FORTH/PROG10K.f new file mode 100644 index 0000000..7230f9a --- /dev/null +++ b/MSP430-FORTH/PROG10K.f @@ -0,0 +1,4625 @@ +\ -*- coding: utf-8 -*- + +; ----------------------------------- +; PROG10K.f +; ----------------------------------- + +; load and compile 10kb (9 x RC52LCD) + +\ to see kernel options, download FastForthSpecs.f +\ FastForth kernel options: MSP430ASSEMBLER, CONDCOMP, FREQUENCY = 8/16/24 MHz +\ +\ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) +\ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 +\ MSP_EXP430FR2355 +\ LP_MSP430FR2476 +\ +\ from scite editor : copy your target selection in (shift+F8) parameter 1: +\ +\ OR +\ +\ drag and drop this file onto SendSourceFileToTarget.bat +\ then select your TARGET when asked. +\ +\ +\ ================================================================================ +\ REGISTERS USAGE for embedded MSP430 ASSEMBLER +\ ================================================================================ +\ don't use R2, R3, R4 +\ R5, R6, R7 must be PUSHed/POPed before/after use, OR restored after: MOV #{XDOCOL|XDOCON|R>},{rDODOES|rDOCON|rDOVAR} +\ scratch registers Y to S are free, +\ under interrupt, IP is free, +\ use FORTH rules for reg. TOS, PSP, RSP. +\ +\ PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC +\ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0 +\ +\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack +\ +\ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP +\ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15 +\ +\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack +\ +\ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= +\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0< +\ +\ +\ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol +\ target : any TI MSP-EXP430FRxxxx launchpad (FRAM) +\ LPM_MODE = LPM0 because use SMCLK for LCDVo +\ +\ DEMO : driver for IR remote compatible with the PHILIPS RC5 protocol +\ plus : driver for 5V LCD 2x20 characters display with 4 bits data interface +\ without usage of an auxiliary 5V to feed the LCD_Vo +\ and without potentiometer to adjust the LCD contrast : +\ to adjust LCD contrast, just press S1 (-) or S2 (+) +\ LCDVo current consumption ~ 500 uA. +\ +\ =================================================================================== +\ notice : adjust WDT_TIM_EX0,LCD_TIM_CTL,LCD_TIM_EX0 and 20_us to the target frequency if <> 8MHz ! +\ =================================================================================== +\ +\ +\ layout : I/O are defined in the launchpad.pat file (don't work with ChipStick_FR2433) +\ +\ GND <-------o---0V0----------> 1 LCD_Vss +\ VCC >-------|---3V6-----o----> 2 LCD_Vdd +\ | | +\ ___ 470n --- +\ ^ --- +\ / \ 1N4148 | +\ --- | +\ 100n | 2k2 | +\ TB0.2 >---||--o--^/\/\/v--o----> 3 LCD_Vo (= 0V6 without modulation) +\ -------------------------> 4 LCD_RW +\ -------------------------> 5 LCD_RW +\ -------------------------> 6 LCD_EN +\ <------------------------> 11 LCD_DB4 +\ <------------------------> 12 LCD_DB5 +\ <------------------------> 13 LCD_DB5 +\ <------------------------> 14 LCD_DB7 +\ +\ <----- LCD contrast + <--- Sw1 <--- (finger) :-) +\ <----- LCD contrast - <--- Sw2 <--- (finger) :-) +\ +\ rc5 <--- OUT IR_Receiver (1 TSOP32236) + + +\ first, we test for downloading driver only if UART TERMINAL target + CODE ABORT_RC5TOLCD + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_UARTI2CS definition before resuming + ; + + ABORT_RC5TOLCD + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET +ECHO + + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] \ define IF and THEN +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/toBODY +\ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern + SUB #2,PSP + MOV TOS,0(PSP) + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV.B &LCD_DB_IN,TOS \ get LCD_Data + AND.B #LCD_DB,TOS \ + MOV @IP+,PC + ENDCODE + + CODE LCD_WRC \ char -- Write Char + BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +BW1 SUB #2,PSP \ + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL + RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH + BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 + BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output + COLON \ high level word starts here + TOP_LCD 2 20_US \ write high nibble first + TOP_LCD 2 20_US + ; + + CODE LCD_WRF \ func -- Write Fonction + BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; + +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_RDS \ -- status Read Status +\ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 +\ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput +\ BIS.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=1 +\ COLON \ starts a FORTH word +\ TOP_LCD 2 20_us \ -- %0000_HHHH +\ TOP_LCD 2 20_us \ -- %0000_HHHH %0000_LLLL +\ HI2LO \ switch from FORTH to assembler +\ RLAM #4,0(PSP) \ -- %HHHH_0000 %0000_LLLL +\ ADD.B @PSP+,TOS \ -- %HHHH_LLLL +\ MOV @RSP+,IP \ restore IP saved by COLON +\ MOV @IP+,PC \ +\ ENDCODE +\ +\ CODE LCD_RDC \ -- char Read Char +\ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 +\ GOTO BW1 +\ ENDCODE +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value + THEN + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ +\ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 +\ - - \CNTL Counter lentgh \ 00 = 16 bits +\ -- \TBSSEL TimerB clock select \ 10 = SMCLK +\ -- \ID input divider \ 10 = /4 +\ -- \MC Mode Control \ 01 = up to LCD_TIM_CCR0 +\ - \TBCLR TimerB Clear +\ - \TBIE +\ -\TBIFG +\ ----------------------------------\ +\ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} +\ -- \CM Capture Mode +\ -- \CCIS +\ - \SCS +\ -- \CLLD +\ - \CAP +\ --- \OUTMOD \ 011 = set/reset +\ - \CCIE +\ - \CCI +\ - \OUT +\ - \COV +\ -\CCIFG +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ +\ set LCD_TIM_.2 to generate PWM for LCD_Vo +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET + +\ START diff --git a/MSP430-FORTH/PreprocessSourceFile.bat.lnk b/MSP430-FORTH/PreprocessSourceFile.bat.lnk index 2c3a33f1f4f42b6ace3add803c4b26097c248225..fb57da00ba759b07895c841645b02f3ec8e36f35 100644 GIT binary patch delta 389 zcmZ3^ahYR+h~jJp4h97V28LN0qN;^Et}w!A2Kk=Nmid<%ttOfp)JIvx0F|JF5C%iA zkewg9y#PaUeqLH;Is=0p11AFu!~1=9emCtvGI~HYRU#mT*<jTOf-#hzA(<hcA&()A zA(H{9l|hW5j=_k*ijje#-Mi3TfgvEsH6X~p&d5m5$uWe1Aqj5uE1=P@>_A3O1RKqV zFcrd@T+L+4Dg$I!PYz%dcZ>$I?17jWh(Q``fS7@Si6JH?z**PJ)zQz_GsZb5zceMd zB(WqjKQE@BC_gK;q&OzGxWL5NfFWw~1jY<uPKGE3D~1?kM^8S)Y-q6R&bkBnDlY}Q ox|cBRT)JY}q1&q@S7tu+n0uh<`JIlk^XT%Me=weAWC6JV0A03UB>(^b delta 348 zcmcc2v7BRqh+;Pb2ZI6w1A~0V@57NZuQ0;sXVGf6YIa;<G@58?Q14_F15|<zLKqCe zLUn#tz5)!%`FUxX=?n~Z44e!s4Da_%^{tu&lF<XI2^0V+6a}kB5EGvAGbS_SGvqO( zF=R3TwK9k?)G-(_7%>7(@k{YiU<e3u4G8kDGcnS0atvW$NJ26iWIV{|bRm#|Tp$7o zNEz8qzRzgL&cGl86iuESz$mWi3}mSTF*6X00I>=XGcYhQ#KZ(R>w395`uTdsq-T~e zI89!`n6bHq=``bH6($3d?E7g`?uWe;>{?UMeO7hB%0stTNv_O%=rQ*|)AKtWW#`f5 HL52bVb1zo$ diff --git a/MSP430-FORTH/RC5toLCD.f b/MSP430-FORTH/RC5toLCD.f index 9740ee4..a38a99c 100644 --- a/MSP430-FORTH/RC5toLCD.f +++ b/MSP430-FORTH/RC5toLCD.f @@ -40,7 +40,7 @@ \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack \ \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= -\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0< +\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0< \ \ \ display on a LCD 2x20 CHAR the code sent by an IR remote under philips RC5 protocol @@ -85,219 +85,226 @@ \ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_RC5TOLCD -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_UARTI2CS definition before resuming -; - -ABORT_RC5TOLCD - - -[DEFINED] {RC5TOLCD} [IF] {RC5TOLCD} [THEN] \ remove application - -MARKER {RC5TOLCD} \ restore the state before MARKER definition -\ \ {UARTI2CS}+8 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR -6 ALLOT \ {UARTI2CS}+10: make room to save previous INI_APP address - \ {RC5TOLCD}+12: make room to save previous WDT_TIM_0_VEC - \ {RC5TOLCD}+14: make room to save previous IR_VEC - -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] -\ https://forth-standard.org/standard/core/STATE -\ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] + CODE ABORT_RC5TOLCD + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_UARTI2CS definition before resuming + ; + + ABORT_RC5TOLCD + + MARKER {RC5TOLCD} \ restore the state before MARKER definition +\ \ {UARTI2CS}-2 = RET_ADR: by default MARKER_DOES does CALL #RET_ADR + 8 ALLOT \ {UARTI2CS} make room to save previous INI_APP address + \ {RC5TOLCD}+2 make room to save previous WDT_TIM_0_VEC + \ {RC5TOLCD}+4 make room to save previous IR_VEC + \ {RC5TOLCD}+6 make room for 20 us count loop. + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] = [IF] \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] IF [IF] \ define IF and THEN + [UNDEFINED] IF + [IF] \ define IF and THEN \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] ELSE [IF] \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS - -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -\ -\ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... - -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ \ https://forth-standard.org/standard/core/DEFERStore +\ \ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. +\ [UNDEFINED] IS +\ [IF] \ define DEFER! and IS +\ CODE DEFER! \ xt2 xt1 -- +\ MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] +\ MOV @PSP+,TOS \ -- +\ MOV @IP+,PC +\ ENDCODE +\ +\ \ https://forth-standard.org/standard/core/IS +\ \ IS <name> xt -- +\ \ used as is : +\ \ DEFER DISPLAY create a "do nothing" definition (2 CELLS) +\ \ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY +\ \ or in a definition : ... ['] U. IS DISPLAY ... +\ \ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +\ \ +\ \ as IS replaces the PFA value of any word, it's a TO alias for VARIABLE and CONSTANT words... +\ +\ : IS +\ STATEADR @ +\ IF POSTPONE ['] POSTPONE DEFER! +\ ELSE ' DEFER! +\ THEN +\ ; IMMEDIATE +\ [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] -[UNDEFINED] >BODY [IF] \ https://forth-standard.org/standard/core/toBODY \ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -\ CODE 20uS \ n -- 8MHz version -\ BEGIN \ 4 + 16 ~ loop -\ MOV #39,rDOCON \ 39 -\ BEGIN \ 4 ~ loop -\ NOP -\ SUB #1,rDOCON -\ 0= UNTIL -\ SUB #1,TOS \ 1 -\ 0= UNTIL -\ MOV #XDOCON,rDOCON \ 2 -\ MOV @PSP+,TOS -\ MOV @RSP+,IP \ -\ ENDCODE - -CODE 20_US \ n -- n * 20 us -BEGIN \ here we presume that LCD_TIM_IFG = 1... - BEGIN - BIT #1,&LCD_TIM_CTL \ 3 - 0<> UNTIL \ 2 loop until LCD_TIM_IFG set - BIC #1,&LCD_TIM_CTL \ 3 clear LCD_TIM_IFG - SUB #1,TOS \ 1 -U< UNTIL \ 2 ...so add a dummy loop with U< instead of 0= -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE - -CODE TOP_LCD \ LCD Sample -\ \ if write : %xxxx_WWWW -- -\ \ if read : -- %0000_RRRR - BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 - BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test -0= IF \ write LCD bits pattern - AND.B #LCD_DB,TOS \ - MOV.B TOS,&LCD_DB_OUT \ send LCD_Data - BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data - MOV @PSP+,TOS \ + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS MOV @IP+,PC -THEN \ read LCD bits pattern + ENDCODE + [THEN] + + CODE 20_US \ n -- + BEGIN \ J_loop 8000 16000 24000 kHz + MOV &{RC5TOLCD}+6,X \ 3 X = {40 80 120} + SUB #2,X \ +1 X = {38 78 118} I_loops + 2 J_loops = {40 80 120} * 4 cycles + BEGIN \ I_loop + NOP \ 1 + SUB #1,X \ +1 + 0= UNTIL \ +2 + NOP \ +1 + SUB #1,TOS \ +1 + 0= UNTIL \ +2 + MOV @PSP+,TOS \ + MOV @RSP+,IP \ + ENDCODE + +\ \ if write : %xxxx_WWWW -- +\ \ if read : -- %0000_RRRR + CODE TOP_LCD \ LCD Sample + BIS.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 0-->1 + BIT.B #LCD_RW,&LCD_CMD_IN \ lcd_rw test + 0= IF \ write LCD bits pattern + AND.B #LCD_DB,TOS \ + MOV.B TOS,&LCD_DB_OUT \ send LCD_Data + BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data + MOV @PSP+,TOS \ + MOV @IP+,PC + THEN \ read LCD bits pattern SUB #2,PSP MOV TOS,0(PSP) BIC.B #LCD_EN,&LCD_CMD_OUT \ lcd_en 1-->0 ==> strobe data MOV.B &LCD_DB_IN,TOS \ get LCD_Data AND.B #LCD_DB,TOS \ MOV @IP+,PC -ENDCODE + ENDCODE -CODE LCD_WRC \ char -- Write Char + CODE LCD_WRC \ char -- Write Char BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 BW1 SUB #2,PSP \ - MOV TOS,0(PSP) \ -- %xxxx_LLLL %HHHH_LLLL + MOV TOS,0(PSP) \ -- %HHHH_LLLL %HHHH_LLLL RRUM #4,TOS \ -- %xxxx_LLLL %xxxx_HHHH BIC.B #LCD_RW,&LCD_CMD_OUT \ lcd_rw=0 BIS.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as output -COLON \ high level word starts here + COLON \ high level word starts here TOP_LCD 2 20_US \ write high nibble first - TOP_LCD 2 20_US -; + TOP_LCD 2 20_US + ; -CODE LCD_WRF \ func -- Write Fonction + CODE LCD_WRF \ func -- Write Fonction BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 GOTO BW1 -ENDCODE + ENDCODE -: LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! -: LCD_HOME $02 LCD_WRF 100 20_us ; + : LCD_CLEAR $01 LCD_WRF 100 20_us ; \ $01 LCD_WrF 80 20_us ==> bad init ! + : LCD_HOME $02 LCD_WRF 100 20_us ; -\ [UNDEFINED] OR [IF] -\ -\ \ https://forth-standard.org/standard/core/OR -\ \ C OR x1 x2 -- x3 logical OR -\ CODE OR -\ BIS @PSP+,TOS -\ MOV @IP+,PC -\ ENDCODE -\ -\ [THEN] -\ -\ : LCD_ENTRY_SET $04 OR LCD_WrF ; -\ : LCD_DSP_CTRL $08 OR LCD_WrF ; -\ : LCD_DSP_SHIFT $10 OR LCD_WrF ; -\ : LCD_FN_SET $20 OR LCD_WrF ; -\ : LCD_CGRAM_SET $40 OR LCD_WrF ; -\ : LCD_GOTO $80 OR LCD_WrF ; -\ -\ +\ CODE LCD_ENTRY_SET +\ BIS #$04,TOS +\ BW1 COLON +\ LCD_WrF +\ ; +\ +\ CODE LCD_DSP_CTRL +\ BIS#$08,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_DSP_SHIFT +\ BIS#$10,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_FN_SET +\ BIS#$20,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_CGRAM_SET +\ BIS #$40,TOS +\ GOTO BW1 +\ ENDCODE +\ +\ CODE LCD_GOTO +\ BIS #$80,TOS +\ GOTO BW1 +\ ENDCODE +\ \ CODE LCD_RDS \ -- status Read Status \ BIC.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=0 \ BW1 BIC.B #LCD_DB,&LCD_DB_DIR \ LCD_Data as intput @@ -311,205 +318,173 @@ ENDCODE \ MOV @RSP+,IP \ restore IP saved by COLON \ MOV @IP+,PC \ \ ENDCODE -\ +\ \ CODE LCD_RDC \ -- char Read Char \ BIS.B #LCD_RS,&LCD_CMD_OUT \ lcd_rs=1 \ GOTO BW1 \ ENDCODE - - -\ ******************************\ -HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! -\ ******************************\ -\ XOR.B #LED1,&LED1_OUT \ to visualise WDT -BIT.B #SW2,&SW2_IN \ test switch S2 -0= IF \ case of switch S2 pressed - CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 - U< IF - ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment +\ +\ +\ ********************************\ + HDNCODE WDT_INT \ Watchdog interrupt routine, warning : not FORTH executable ! +\ ********************************\ +\ XOR.B #LED1,&LED1_OUT \ to visualise WDT + BIT.B #SW2,&SW2_IN \ test switch S2 + 0= IF \ case of switch S2 pressed + CMP #19,&LCD_TIM_CCRn \ maxi Ton = 19/20 & VDD=3V6 ==> LCD_Vo = -1V4 + U< IF + ADD #1,&LCD_TIM_CCRn \ action for switch S2 (P2.5) : 150 mV / increment + THEN + ELSE + BIT.B #SW1,&SW1_IN \ test switch S1 input + 0= IF \ case of Switch S1 pressed + CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V + U>= IF \ + SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement + THEN \ + THEN \ + THEN \ + RETI \ 5 + ENDCODE \ +\ ********************************\ + +\ ********************************\ + HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt +\ ********************************\ +\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use +\ ********************************\ +\ \ in : SR(9)=old Toggle bit memory (ADD on) +\ \ SMclock = 8|16|24 MHz +\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register +\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 +\ \ SR(9)=new Toggle bit memory (ADD on) +\ ********************************\ +\ RC5_FirstStartBitHalfCycle: \ +\ ********************************\ + MOV #1778,X \ RC5_Period in us + MOV #14,W \ count of loop + BEGIN \ +\ ****************************\ +\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period +\ ****************************\ | + MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R +\ RC5_Compute_3/4_Period: \ | + RRUM #1,X \ X=1/2 cycle | + MOV X,Y \ ^ + RRUM #1,Y \ Y=1/4 + ADD X,Y \ Y=3/4 cycle + BEGIN \ + CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles + U>= UNTIL \ 2 +\ ****************************\ +\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first +\ ****************************\ + BIT.B #RC5,&IR_IN \ C_flag = IR bit + ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag + MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG + BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change + SUB #1,W \ decrement count loop +\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 +\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 + 0<> WHILE \ ----> out of loop ----+ + ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present + BEGIN \ | + MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles + CMP Y,X \ 1 ^ | cycle time out of bound ? + U>= ?GOTO FW1 \ | | quit on truncated RC5 message + BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present + 0<> UNTIL \ 2 | | + REPEAT \ ----> loop back --+ | with X = new RC5_period value +\ ********************************\ | +\ RC5_SampleEndOf: \ <---------------------+ +\ ********************************\ + BIC #$30,&RC5_TIM_CTL \ stop timer +\ ********************************\ +\ RC5_ComputeNewRC5word \ +\ ********************************\ + RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 + MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 + RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_ComputeC6bit \ +\ ********************************\ + BIT #BIT14,T \ test /C6 bit in T + 0= IF BIS #BIT6,X \ set C6 bit in X + THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 +\ ********************************\ +\ RC5_CommandByteIsDone \ +\ ********************************\ +\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit +\ ********************************\ + RRUM #3,T \ new toggle bit = T(13) ==> T(10) + XOR @RSP,T \ (new XOR old) Toggle bits + BIT #UF10,T \ repeated RC5_command ? + 0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! + XOR #UF10,0(RSP) \ 5 toggle bit memory +\ ********************************\ +\ Display IR_RC5 code \ +\ ********************************\ + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &BASEADR,2(PSP) \ -- TOS Base x TOS + MOV #$10,&BASEADR \ set hexadecimal base + MOV X,0(PSP) \ -- TOS Base RC5_code TOS convert number to ascii low word = RC5 byte + MOV #0,TOS \ -- TOS Base RC5_code 0 convert double number to ascii + LO2HI \ switch from assembler to FORTH + LCD_CLEAR \ set LCD cursor at home + <# # #S #36 HOLD #> \ -- TOS Base adr cnt 32 bits conversion as "$xx" + ['] LCD_WRC IS EMIT \ redirect EMIT to LCD + TYPE \ -- TOS Base display "$xx" on LCD + ['] EMIT >BODY IS EMIT \ restore EMIT + HI2LO \ switch from FORTH to assembler + MOV @PSP+,&BASEADR \ -- TOS restore current BASE + MOV @PSP+,TOS \ -- +FW1 BIC #$30,&RC5_TIM_CTL \ stop timer (case of truncated RC5 message) +FW2 BIC #%1111_1000,0(RSP) \ force CPU Active Mode and disable GIE in saved SR + RETI \ + ENDCODE \ +\ ********************************\ + +\ define our STOP_APP +\ ----------------------------------\ + HDNCODE STOP_R2L \ called by STOP|INIT_R2L|{RC5TOLCD} +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ only if START is done + BIC.B #RC5,&IR_IE \ clear I/O RC5_Int + BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag + MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER, clear LCD_TIMER IFG + MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER + MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 + MOV #{RC5TOLCD},W \ + MOV #RET_ADR,-2(W) \ clear MARKER_DOES call + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV @W+,&UART_WARM+2 \ restore previous ini_APP + [ELSE] + MOV @W+,&I2C_WARM+2 \ restore previous ini_APP + [THEN] + MOV @W+,&WDT_TIM_0_VEC \ restore Vector previous value + MOV @W+,&IR_VEC \ restore Vector previous value THEN -ELSE - BIT.B #SW1,&SW1_IN \ test switch S1 input - 0= IF \ case of Switch S1 pressed - CMP #3,&LCD_TIM_CCRn \ mini Ton = 3/20 & VDD=3V6 ==> LCD_Vo = 0V - U>= IF \ - SUB #1,&LCD_TIM_CCRn \ action for switch S1 (P2.6) : -150 mV / decrement - THEN \ - THEN \ -THEN \ -RETI \ 5 -ENDCODE - -\ ******************************\ -HDNCODE RC5_INT \ wake up on Px.RC5 change interrupt -\ ******************************\ -\ IR_RC5 driver \ IP,S,T,W,X,Y registers are free for use -\ ******************************\ -\ \ in : SR(9)=old Toggle bit memory (ADD on) -\ \ SMclock = 8|16|24 MHz -\ \ use : T,W,X,Y, RC5_TIM_ timer, RC5_TIM_R register -\ \ out : X = 0 C6 C5 C4 C3 C2 C1 C0 -\ \ SR(9)=new Toggle bit memory (ADD on) -\ ******************************\ -\ RC5_FirstStartBitHalfCycle: \ -\ ******************************\ division in RC5_TIM_CTL (SMCLK/1|SMCLK/1|SMCLK/2|SMCLK/4|SMCLK/8) -\ FREQ_KHZ @ 8000 = [IF] \ 8 MHz ? -\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value -\ [THEN] -FREQ_KHZ @ 16000 = [IF] \ 16 MHz ? - MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register -[THEN] -FREQ_KHZ @ 24000 = [IF] \ 24 MHz ? - MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register -[THEN] -MOV #1778,X \ RC5_Period * 1us -MOV #14,W \ count of loop -BEGIN \ -\ ******************************\ -\ RC5_HalfCycle \ <--- loop back ---+ with readjusted RC5_Period -\ ******************************\ | -MOV #%1011100100,&RC5_TIM_CTL \ (re)start timer_A | SMCLK/8 time interval,free running,clear RC5_TIM__IFG and RC5_TIM_R -\ RC5_Compute_3/4_Period: \ | - RRUM #1,X \ X=1/2 cycle | - MOV X,Y \ ^ - RRUM #1,Y \ Y=1/4 - ADD X,Y \ Y=3/4 cycle - BEGIN CMP Y,&RC5_TIM_R \ 3 wait 1/2 + 3/4 cycle = n+1/4 cycles - U>= UNTIL \ 2 -\ ******************************\ -\ RC5_SampleOnFirstQuarter \ at n+1/4 cycles, we sample RC5_input, ST2/C6 bit first -\ ******************************\ - BIT.B #RC5,&IR_IN \ C_flag = IR bit - ADDC T,T \ C_flag <-- T(15):T(0) <-- C_flag - MOV.B &IR_IN,&IR_IES \ preset Px_IES.y state for next IFG - BIC.B #RC5,&IR_IFG \ clear Px_IFG.y after 4/4 cycle pin change - SUB #1,W \ decrement count loop -\ \ count = 13 ==> T = x x x x x x x x |x x x x x x x /C6 -\ \ count = 0 ==> T = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1 -0<> WHILE \ ----> out of loop ----+ - ADD X,Y \ | Y = n+3/4 cycles = time out because n+1/2 cycles edge is always present - BEGIN \ | - MOV &RC5_TIM_R,X \ 3 | X grows from n+1/4 up to n+3/4 cycles - CMP Y,X \ 1 | cycle time out of bound ? - U>= IF \ 2 ^ | yes: - BIC #$30,&RC5_TIM_CTL \ | | stop timer - GOTO FW1 \ | | quit on truncated RC5 message - THEN \ | | - BIT.B #RC5,&IR_IFG \ 3 | | n+1/2 cycles edge is always present - 0<> UNTIL \ 2 | | -REPEAT \ ----> loop back --+ | with X = new RC5_period value -\ ******************************\ | -\ RC5_SampleEndOf: \ <---------------------+ -\ ******************************\ -BIC #$30,&RC5_TIM_CTL \ stop timer -\ ******************************\ -\ RC5_ComputeNewRC5word \ -\ ******************************\ -RLAM #1,T \ T = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0 -MOV.B T,X \ X = C5 C4 C3 C2 C1 C0 1 0 -RRUM #2,X \ X = 0 0 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_ComputeC6bit \ -\ ******************************\ -BIT #BIT14,T \ test /C6 bit in T -0= IF BIS #BIT6,X \ set C6 bit in X -THEN \ X = 0 C6 C5 C4 C3 C2 C1 C0 -\ ******************************\ -\ RC5_CommandByteIsDone \ -- BASE RC5_code -\ ******************************\ -\ Only New_RC5_Command ADD_ON \ use SR(10) bit as toggle bit -\ ******************************\ -RRUM #3,T \ new toggle bit = T(13) ==> T(10) -XOR @RSP,T \ (new XOR old) Toggle bits -BIT #UF10,T \ repeated RC5_command ? -0= ?GOTO FW2 \ yes, RETI without UF10 change and without action ! -XOR #UF10,0(RSP) \ 5 toggle bit memory -\ ******************************\ -\ Display IR_RC5 code \ -\ ******************************\ -SUB #8,PSP \ TOS -- x x x x TOS -MOV TOS,6(PSP) \ -- Save_TOS x x x TOS -MOV &BASEADR,4(PSP) \ -- Save_TOS Save_Base x x TOS -MOV #$10,&BASEADR \ set hexadecimal base -MOV X,0(PSP) \ -- Save_TOS Save_Base x RC5_code TOS convert number to ascii low word = RC5 byte -MOV #0,TOS \ -- Save_TOS Save_Base x RC5_code 0 convert number to ascii high word = 0 -LO2HI \ switch from assembler to FORTH - LCD_CLEAR \ set LCD cursor at home - <# # #S #36 HOLD #> \ 32 bits conversion as "$xx" - ['] LCD_WRC IS EMIT \ redirect EMIT to LCD - TYPE \ -- Save_TOS Save_Base x adr cnt display "$xx" on LCD - ['] EMIT >BODY IS EMIT \ -- Save_TOS Save_Base TOS restore EMIT -HI2LO \ -- switch from FORTH to assembler -MOV @PSP+,&BASEADR \ -- Save_TOS TOS restore current BASE -MOV @PSP+,TOS \ -- TOS -FW1 FW2 - MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode - RET \ (instead of RETI) -ENDCODE - - -\ ------------------------------\ -HDNCODE STOP_R2L \ define new STOP_APP -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ -0<> IF \ if previous START executing - BIC.B #RC5,&IR_IE \ clear I/O RC5_Int - BIC.B #RC5,&IR_IFG \ clear I/O RC5_Int flag - MOV #0,&LCD_TIM_CTL \ stop LCD_TIMER - MOV #0,&WDT_TIM_CTL \ stop WDT_TIMER - MOV #0,&WDT_TIM_CCTL0 \ clear CCIFG0 disable CCIE0 - MOV #RET_ADR,&{RC5TOLCD}+8 \ clear MARKER_DOES call - MOV &{RC5TOLCD}+10,&WARM+2 \ restore previous ini_APP - MOV &{RC5TOLCD}+12,&WDT_TIM_0_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+14,&IR_VEC \ restore Vector previous value - MOV &{RC5TOLCD}+10,PC \ run previous INI_APP, then RET -THEN -MOV @RSP+,PC \ RET -ENDCODE - -\ ------------------------------\ -CODE STOP \ -\ ------------------------------\ -BW1 \ <-- INI_R2L for some events -CALL #STOP_R2L -COLON \ restore default action of primary DEFERred word WARM (FORTH version) -ECHO \ -." RC5toLCD is removed," -." type START to restart" -ABORT" " -; -\ ------------------------------\ - -\ ------------------------------\ -HDNCODE INI_R2L \ this routine completes the init of system, i.e. FORTH + this app. -\ ------------------------------\ -\ activate I/O \ -\ ------------------------------\ -BIC #1,&PM5CTL0 \ activate I/O to enable SW2 test -\ ------------------------------\ -\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing -\ ------------------------------\ -MOV &RSTIV_MEM,TOS \ SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ RSTIV_MEM = SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_R2L then RET to BODY of WARM -THEN \ -BIT.B #SW2,&SW2_IN \ hardware SW2+RST ? -0= ?GOTO BW1 \ hardware SW2+RST execute STOP_U2I then RET to BODY of WARM -\ CMP #4,TOS \ hardware RST -\ 0= ?GOTO BW1 \ hardware RST performs STOP. -\ CMP #2,TOS \ Power_ON event -\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... -\ CMP #6,TOS \ -\ 0= ?GOTO BW1 \ COLD event performs STOP... uncomment if it's that you want. -\ CMP #$0A,TOS \ -\ 0= ?GOTO BW1 \ fault event (violation memory protected areas) performs STOP -\ CMP #$16,TOS \ -\ U>= ?GOTO BW1 \ all other fault events + Deep Reset perform STOP -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST event! -\ ------------------------------\ + MOV @RSP+,PC \ RET to STOP|WARM+4|{RC5TOLCD} + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE STOP \ also called by INIT_R2L for some events +\ ----------------------------------\ +BW1 CALL #STOP_R2L + COLON \ + ECHO \ + ." type START to start RC5toLCD" + ; +\ ----------------------------------\ + +\ this routine completes the INIT_HARD of FORTH, with INIT_HARD for this app. +\ ----------------------------------\ + HDNCODE INIT_R2L \ called by START|SYS +\ ----------------------------------\ \ LCD_TIM_CTL = %0000 0010 1001 0100\$3C0 \ - - \CNTL Counter lentgh \ 00 = 16 bits \ -- \TBSSEL TimerB clock select \ 10 = SMCLK @@ -518,7 +493,7 @@ MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST \ - \TBCLR TimerB Clear \ - \TBIE \ -\TBIFG -\ -------------------------------\ +\ ----------------------------------\ \ LCD_TIM_CCTLx = %0000 0000 0110 0000\$3C{2,4,6,8,A,C,E} \ -- \CM Capture Mode \ -- \CCIS @@ -531,122 +506,162 @@ MOV #0,&RSTIV_MEM \ clear RSTIV_MEM after use and before next RST \ - \OUT \ - \COV \ -\CCIFG -\ -------------------------------\ -\ LCD_TIM_CCRx \ -\ -------------------------------\ -\ LCD_TIM_EX0 \ -\ ------------------------------\ -\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt -\ ------------------------------\ -MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int -\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) -FREQ_KHZ @ 16000 = [IF] \ if 16 MHz - MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) -[THEN] -FREQ_KHZ @ 24000 = [IF] \ if 24 MHz - MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) -[THEN] - MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us -\ ------------------------------\ +\ ----------------------------------\ +\ LCD_TIM_CCRx \ +\ ----------------------------------\ +\ LCD_TIM_EX0 \ +\ ----------------------------------\ +\ set LCD_TIM_ to make 50kHz PWM \ for LCD_Vo; works without interrupt +\ ----------------------------------\ + MOV #%10_1101_0100,&LCD_TIM_CTL \ SMCLK/8, up mode, clear timer, no int, set IFG +\ MOV #0,&RC5_TIM_EX0 \ predivide by 1 in RC5_TIM_EX0 register, reset value +\ MOV #0,&LCD_TIM_EX0 \ predivide by 1 in LCD_TIM_EX0 register (8 MHZ) + FREQ_KHZ @ 16000 = + [IF] \ if 16 MHz + MOV #1,&RC5_TIM_EX0 \ predivide by 2 in RC5_TIM_EX0 register + MOV #1,&LCD_TIM_EX0 \ predivide by 2 in LCD_TIM_EX0 register (16 MHZ) + [THEN] + FREQ_KHZ @ 24000 = + [IF] \ if 24 MHz + MOV #2,&RC5_TIM_EX0 \ predivide by 3 in RC5_TIM_EX0 register + MOV #2,&LCD_TIM_EX0 \ predivide by 3 in LCD_TIM_EX0 register (24 MHZ) + [THEN] + MOV #19,&LCD_TIM_CCR0 \ 19+1=20*1us=20us +\ ----------------------------------\ \ set LCD_TIM_.2 to generate PWM for LCD_Vo -\ ------------------------------\ -MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG - MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) -\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) -\ ------------------------------\ - BIS.B #LCDVo,&LCDVo_DIR \ - BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 -\ ------------------------------\ - BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs - BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable -\ ------------------------------\ - BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data - BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable -\ ******************************\ -\ init RC5_Int \ -\ ******************************\ - BIS.B #RC5,&IR_IE \ enable RC5_Int - BIC.B #RC5,&IR_IFG \ reset RC5_Int flag -\ ******************************\ -\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ -\ ******************************\ -\ %01 0001 0100 \ TAxCTL -\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz -\ -- \ ID divided by 1 -\ -- \ MC MODE = up to TAxCCRn -\ - \ TACLR clear timer count -\ - \ TAIE -\ - \ TAIFG -\ ------------------------------\ -MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, -\ ------------------------------\ -\ 000 \ TAxEX0 -\ --- \ TAIDEX pre divisor -\ ------------------------------\ -\ %0000 0000 0000 0101 \ TAxCCR0 - MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms -\ ------------------------------\ -\ %0000 0000 0001 0000 \ TAxCCTL0 -\ - \ CAP capture/compare mode = compare -\ - \ CCIEn -\ - \ CCIFGn - MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 -\ ------------------------------\ -\ define LPM mode for ACCEPT \ -\ ------------------------------\ -\ MOV #LPM4+GIE,&LPM_MODE \ with MSP430FR59xx -\ MOV #LPM2+GIE,&LPM_MODE \ with MSP430FR57xx, terminal input don't work for LPMx > 2 -\ \ with MSP430FR2xxx, terminal input don't work for LPMx > 0 ; LPM0 is the default value -\ ------------------------------\ -COLON \ -\ ------------------------------\ -\ Init LCD 2x20 \ -\ ------------------------------\ - #1000 20_US \ 1- wait 20 ms - %011 TOP_LCD \ 2- send DB5=DB4=1 - #205 20_US \ 3- wait 4,1 ms - %011 TOP_LCD \ 4- send again DB5=DB4=1 - #5 20_US \ 5- wait 0,1 ms - %011 TOP_LCD \ 6- send again again DB5=DB4=1 - #2 20_US \ wait 40 us = LCD cycle - %010 TOP_LCD \ 7- send DB5=1 DB4=0 - #2 20_US \ wait 40 us = LCD cycle - %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal - %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM - %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. - LCD_CLEAR \ 10- "LCD_Clear" - ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME - ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC - CR ." I love you" \ display message on LCD - ['] CR >BODY IS CR \ CR executes its default value - ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value - ." RC5toLCD is running. Type STOP to quit" \ display message on FastForth Terminal - ABORT" " \ -; \ -\ ------------------------------\ - -\ ------------------------------\ -CODE START \ this routine replaces WARM and COLD default values by these of this application. -\ ------------------------------\ -CMP #RET_ADR,&{RC5TOLCD}+8 \ init R2L once, only if MARKER_DOES is not initialized -0= IF \ if not done, customizes MARKER_DOES - MOV #STOP_R2L,&{RC5TOLCD}+8 \ execution of {RC5TOLCD} will perform STOP_R2L. - MOV &WARM+2,&{RC5TOLCD}+10 \ save previous INI_APP subroutine - MOV #INI_R2L,&WARM+2 \ replace it by RC5toLCD INI_APP - MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+12 \ save Vector previous value - MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 - MOV &IR_VEC,&{RC5TOLCD}+14 \ save Vector previous value - MOV #RC5_INT,&IR_VEC \ init interrupt vector - MOV #INI_R2L,PC \ then execute new INI_APP, without return -THEN -MOV @IP+,PC -ENDCODE -\ ------------------------------\ - +\ ----------------------------------\ + MOV #%0110_0000,&LCD_TIM_CCTLn \ output mode = set/reset \ clear CCIFG + MOV #10,&LCD_TIM_CCRn \ contrast adjust : 10/20 ==> LCD_Vo = -0V6|+3V6 (Vcc=3V6) +\ MOV #12,&LCD_TIM_CCRn \ contrast adjust : 12/20 ==> LCD_Vo = -1V4|+3V3 (Vcc=3V3) +\ ----------------------------------\ + BIS.B #LCDVo,&LCDVo_DIR \ + BIS.B #LCDVo,&LCDVo_SEL \ SEL.2 +\ ----------------------------------\ + BIS.B #LCD_CMD,&LCD_CMD_DIR \ lcd_cmd as outputs + BIC.B #LCD_CMD,&LCD_CMD_REN \ lcd_cmd pullup/down disable +\ ----------------------------------\ + BIS.B #LCD_DB,&LCD_DB_DIR \ as output, wired to DB(4-7) LCD_Data + BIC.B #LCD_DB,&LCD_DB_REN \ LCD_Data pullup/down disable +\ ----------------------------------\ +\ init RC5_Int \ +\ ----------------------------------\ + BIS.B #RC5,&IR_IE \ enable RC5_Int + BIC.B #RC5,&IR_IFG \ reset RC5_Int flag +\ ----------------------------------\ +\ init WatchDog WDT_TIM_ \ eUSCI_A0 (FORTH terminal) has higher priority than WDT_TIM_ +\ ----------------------------------\ +\ %01 0001 0100 \ TAxCTL +\ -- \ TASSEL CLK = ACLK = LFXT = 32768 Hz +\ -- \ ID divided by 1 +\ -- \ MC MODE = up to TAxCCRn +\ - \ TACLR clear timer count +\ - \ TAIE +\ - \ TAIFG +\ ----------------------------------\ + MOV #%01_0001_0100,&WDT_TIM_CTL \ start WDT_TIM_, ACLK, up mode, disable int, +\ ----------------------------------\ +\ 000 \ TAxEX0 +\ --- \ TAIDEX pre divisor +\ ----------------------------------\ +\ %0000 0000 0000 0101 \ TAxCCR0 + MOV ##3276,&WDT_TIM_CCR0 \ else init WDT_TIM_ for LFXT: 32768/20=1638 ==> 100ms +\ ----------------------------------\ +\ %0000 0000 0001 0000 \ TAxCCTL0 +\ - \ CAP capture/compare mode = compare +\ - \ CCIEn +\ - \ CCIFGn + MOV #%10000,&WDT_TIM_CCTL0 \ enable compare interrupt, clear CCIFG0 +\ ----------------------------------\ +\ activate I/O \ +\ ----------------------------------\ + CALL &{RC5TOLCD} \ run previous INIT_HARD_APP +\ ----------------------------------\ +\ RESET events handling \ search "SYSRSTIV" in your MSP430FRxxxx datasheet to get listing +\ ----------------------------------\ + CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas | USERSYS <0 = DEEP_RESET request ? + U>= ?GOTO BW1 \ if yes execute STOP_R2L then RET to BODY of WARM + THEN \ +\ CMP #2,TOS \ Power_ON event +\ 0= ?GOTO BW1 \ uncomment if you want to loose application in this case... + CMP #4,TOS \ SYSRSTIV|USERSYS RST ? + 0= ?GOTO BW1 \ if yes run STOP. +\ CMP #$0E,TOS \ SYSRSTIV = SVSHIFG SVSH event ? +\ 0= ?GOTO BW1 \ SVSHIFG SVSH event performs STOP +\ ----------------------------------\ + LO2HI \ +\ ----------------------------------\ +\ Init LCD 2x20 \ +\ ----------------------------------\ + #1000 20_US \ 1- wait 20 ms + %011 TOP_LCD \ 2- send DB5=DB4=1 + #205 20_US \ 3- wait 4,1 ms + %011 TOP_LCD \ 4- send again DB5=DB4=1 + #5 20_US \ 5- wait 0,1 ms + %011 TOP_LCD \ 6- send again again DB5=DB4=1 + #2 20_US \ wait 40 us = LCD cycle + %010 TOP_LCD \ 7- send DB5=1 DB4=0 + #2 20_US \ wait 40 us = LCD cycle + %00101000 LCD_WRF \ 8- %001DNFxx "FonctionSet" D=8/4 DataBus width, Number of lines=2/1, Font bold/normal + %1000 LCD_WRF \ 9- %1DCB "DisplayControl" : Display off, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + %0110 LCD_WRF \ 11- %01xx "LCD_EntrySet" : address and cursor shift after writing in RAM + %1100 LCD_WRF \ 12- %1DCB "DisplayControl" : Display on, Cursor off, Blink off. + LCD_CLEAR \ 10- "LCD_Clear" + HI2LO \ + MOV @RSP+,PC \ RET to WARM|START + ENDCODE +\ ----------------------------------\ + +\ ----------------------------------\ + CODE START \ this routine replaces INT_HARD_APP default values by these of this application. +\ ----------------------------------\ + CMP #WDT_INT,&WDT_TIM_0_VEC \ value set by START + 0= IF \ + MOV @IP+,PC \ does nothing if already initialised + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 \ execution of {RC5TOLCD} will perform STOP_R2L. + KERNEL_ADDON $3C00 TSTBIT \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&UART_WARM+2 \ replace it by RC5toLCD INI_APP + [ELSE] + MOV &I2C_WARM+2,&{RC5TOLCD} \ save previous INI_APP subroutine + MOV #INIT_R2L,&I2C_WARM+2 \ replace it by RC5toLCD INI_APP + [THEN] + MOV &WDT_TIM_0_VEC,&{RC5TOLCD}+2 \ save Vector previous value + MOV #WDT_INT,&WDT_TIM_0_VEC \ for only CCIFG0 int, this interrupt clears automatically CCIFG0 + MOV &IR_VEC,&{RC5TOLCD}+4 \ save Vector previous value + MOV #RC5_INT,&IR_VEC \ init interrupt vector +\ ----------------------------------\ +\ init 20 us count loop \ see 20_US +\ ----------------------------------\ -- TOS + SUB #6,PSP \ -- x x x TOS + MOV TOS,4(PSP) \ -- TOS x x TOS + MOV &FREQ_KHZ,2(PSP) \ -- TOS DVDlo x TOS + MOV #0,0(PSP) \ -- TOS DVDlo DVDhi TOS + MOV #200,TOS \ -- TOS DVDlo DVDhi DIVlo + CALL #MUSMOD \ -- TOS REMlo QUOTlo QUOThi + MOV @PSP,&{RC5TOLCD}+6 \ set count+2 for 20_US + ADD #4,PSP \ -- TOS QUOThi + MOV @PSP+,TOS \ -- TOS +\ ----------------------------------\ + CALL #INIT_R2L \ run new INIT_HARD_APP + LO2HI +\ ['] LCD_HOME IS CR \ ' CR redirected to LCD_HOME +\ ['] LCD_WRC IS EMIT \ ' EMIT redirected to LCD_WrC +\ CR ." I love you" \ display message on LCD +\ ['] CR >BODY IS CR \ CR executes its default value +\ ['] EMIT >BODY IS EMIT \ EMIT executes its defaulte value + ." RC5toLCD is running," \ + ." Type STOP to quit." \ display message on FastForth Terminal + HI2LO + MOV #ABORT,PC \ goto FORTH interpreter without WARM message. + ENDCODE \ +\ ----------------------------------\ + +RST_SET ECHO - ; downloading RC5toLCD.4th is done -RST_HERE ; this app is protected against <reset> -START +\ START diff --git a/MSP430-FORTH/RTC.f b/MSP430-FORTH/RTC.f index 9ffe21e..8d931cd 100644 --- a/MSP430-FORTH/RTC.f +++ b/MSP430-FORTH/RTC.f @@ -1,7 +1,7 @@ \ -*- coding: utf-8 -*- \ \ ============================================================================== -\ routines RTC for MSP430FRxxxx +\ routines RTC for MSP430FR5xxx \ your target must have a LF_XTAL 32768Hz \ ============================================================================== \ @@ -10,8 +10,6 @@ \ \ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) \ MSP_EXP430FR5739 MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 -\ MSP_EXP430FR4133 CHIPSTICK_FR2433 MSP_EXP430FR2433 MSP_EXP430FR2355 -\ LP_MSP430FR2476 \ \ from scite editor : copy your target selection in (shift+F8) parameter 1: \ @@ -42,23 +40,23 @@ \ \ -CODE ABORT_RTC -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #BIT15,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" target without LF_XTAL !" -PWR_STATE \ if no abort remove this word -; - -ABORT_RTC + CODE ABORT_RTC + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #BIT14,TOS + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (FIXPOINT input), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" target without LF_XTAL !" + RST_RET \ if no abort remove this word + ; + + ABORT_RTC ; -------------------- ; RTC.f @@ -67,624 +65,500 @@ ABORT_RTC \ use : \ to set date, type : d m y DATE! \ to view date, type DATE? -\ to set time, type : h m s TIME!, or h m TIME! +\ to set time, type : h m [s] TIME! \ to view time, type TIME? \ -[DEFINED] {RTC} [IF] {RTC} [THEN] -MARKER {RTC} \ restore the state before MARKER definition -\ {RTC}+8 = BODY+4 = RET_ADR: MARKER_DOES does a call to RET_ADR by default -8 ALLOT \ make room for: -\ {RTC}+10 for content of previous RTC_VEC -\ {RTC}+12 for content of previous COLD_PFA -\ {RTC}+14 for content of previous WARM_PFA -\ {RTC}+16 for content of previous SLEEP_PFA + MARKER {RTC} - -[UNDEFINED] OR [IF] \ https://forth-standard.org/standard/core/OR \ C OR x1 x2 -- x3 logical OR -CODE OR -BIS @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] OR + [IF] + CODE OR + BIS @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] C@ [IF] \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] C! [IF] \ https://forth-standard.org/standard/core/CStore \ C! char c-addr -- store char in memory -CODE C! -MOV.B @PSP+,0(TOS) \ 4 -ADD #1,PSP \ 1 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] + [UNDEFINED] C! + [IF] + CODE C! + MOV.B @PSP+,0(TOS) \ 4 + ADD #1,PSP \ 1 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] \define DUP and DUP? + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP + [IF] \define DUP and DUP? + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] DROP [IF] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DROP \ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] DEPTH [IF] \ https://forth-standard.org/standard/core/DEPTH \ DEPTH -- +n number of items on stack, must leave 0 if stack empty -CODE DEPTH -MOV TOS,-2(PSP) -MOV #PSTACK,TOS -SUB PSP,TOS \ PSP-S0--> TOS -RRA TOS \ TOS/2 --> TOS -SUB #2,PSP \ post decrement stack... -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV TOS,-2(PSP) + MOV #PSTACK,TOS + SUB PSP,TOS \ PSP-S0--> TOS + RRA TOS \ TOS/2 --> TOS + SUB #2,PSP \ post decrement stack... + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS \ 3 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS \ 3 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/OneMinus +\ 1- n1/u1 -- n2/u2 subtract 1 from TOS + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + CODE U< + SUB @PSP+,TOS \ 2 u2-u1 + 0<> IF + MOV #-1,TOS \ 1 + U< IF \ 2 flag + AND #0,TOS \ 1 flag Z = 1 + THEN THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] = [IF] \ https://forth-standard.org/standard/core/Equal \ = x1 x2 -- flag test x1=x2 -CODE = -SUB @PSP+,TOS \ 2 -0<> IF \ 2 - AND #0,TOS \ 1 - MOV @IP+,PC \ 4 -THEN -XOR #-1,TOS \ 1 flag Z = 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF THEN + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF THEN + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W - MOV X,-4(W) \ xloop --> HERE - MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 \ goto BW1 LOOP -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 \ goto BW1 LOOP + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/BEGIN +\ BEGIN -- BEGINadr initialize backward branch + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + + CODE BEGIN + MOV #HEREXEC,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/UNTIL +\ UNTIL BEGINadr -- resolve conditional backward branch + CODE UNTIL + MOV #QFBRAN,X +BW1 ADD #4,&DP \ compile two words + MOV &DP,W \ W = HERE + MOV X,-4(W) \ compile Bran or QFBRAN at HERE + MOV TOS,-2(W) \ compile bakcward adr at HERE+2 + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/AGAIN +\ AGAIN BEGINadr -- resolve uncondionnal backward branch + CODE AGAIN + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/WHILE +\ WHILE BEGINadr -- WHILEadr BEGINadr + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/REPEAT +\ REPEAT WHILEadr BEGINadr -- resolve WHILE loop + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] -[UNDEFINED] CASE [IF] \ https://forth-standard.org/standard/core/CASE -: CASE 0 ; IMMEDIATE \ -- #of-1 + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE \ -- #of-1 \ https://forth-standard.org/standard/core/OF -: OF \ #of-1 -- orgOF #of -1+ \ count OFs ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE OVER POSTPONE = \ copy and test case value -POSTPONE IF \ add orig to control flow stack -POSTPONE DROP \ discards case value if = -R> \ we can bring count back now -; IMMEDIATE + : OF \ #of-1 -- orgOF #of + 1+ \ count OFs + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE OVER POSTPONE = \ copy and test case value + POSTPONE IF \ add orig to control flow stack + POSTPONE DROP \ discards case value if = + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDOF -: ENDOF \ orgOF #of -- orgENDOF #of ->R \ move off the stack in case the control-flow stack is the data stack. -POSTPONE ELSE -R> \ we can bring count back now -; IMMEDIATE + : ENDOF \ orgOF #of -- orgENDOF #of + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE ELSE + R> \ we can bring count back now + ; IMMEDIATE \ https://forth-standard.org/standard/core/ENDCASE -: ENDCASE \ orgENDOF1..orgENDOFn #of -- -POSTPONE DROP -0 DO - POSTPONE THEN -LOOP -; IMMEDIATE -[THEN] - -[UNDEFINED] + [IF] + : ENDCASE \ orgENDOF1..orgENDOFn #of -- + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] \define MAX and MIN + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] -CODE MAX \ n1 n2 -- n3 signed maximum + [UNDEFINED] MAX + [IF] \define MAX and MIN + CODE MAX \ n1 n2 -- n3 signed maximum CMP @PSP,TOS \ n2-n1 S< ?GOTO FW1 \ n2<n1 BW1 ADD #2,PSP MOV @IP+,PC -ENDCODE + ENDCODE -CODE MIN \ n1 n2 -- n3 signed minimum - CMP @PSP,TOS \ n2-n1 - S< ?GOTO BW1 \ n2<n1 + CODE MIN \ n1 n2 -- n3 signed minimum + CMP @PSP,TOS \ n2-n1 + S< ?GOTO BW1 \ n2<n1 FW1 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE + ENDCODE -[THEN] \ MAX + [THEN] \ MAX -[UNDEFINED] 2* [IF] \ https://forth-standard.org/standard/core/TwoTimes \ 2* x1 -- x2 arithmetic left shift -CODE 2* -ADD TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 2* + [IF] + CODE 2* + ADD TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] UM* [IF] \ case of hardware_MPY \ https://forth-standard.org/standard/core/UMTimes \ UM* u1 u2 -- udlo udhi unsigned 16x16->32 mult. -CODE UM* + [UNDEFINED] UM* + [IF] \ case of hardware_MPY + CODE UM* MOV @PSP,&MPY \ Load 1st operand for unsigned multiplication BW1 MOV TOS,&OP2 \ Load 2nd operand MOV &RES0,0(PSP) \ low result on stack MOV &RES1,TOS \ high result in TOS MOV @IP+,PC -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/MTimes \ M* n1 n2 -- dlo dhi signed 16*16->32 multiply -CODE M* + CODE M* MOV @PSP,&MPYS \ Load 1st operand for signed multiplication GOTO BW1 -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] UM/MOD [IF] \ https://forth-standard.org/standard/core/UMDivMOD \ UM/MOD udlo|udhi u1 -- ur uq unsigned 32/16->r16 q16 -CODE UM/MOD + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD PUSH #DROP \ MOV #MUSMOD,PC \ execute MUSMOD then return to DROP -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] U*/ [IF] \ U*/ u1 u2 u3 -- uq u1*u2/u3 -: U*/ ->R UM* R> UM/MOD SWAP DROP -; -[THEN] + : U*/ + >R UM* R> UM/MOD SWAP DROP + ; -[UNDEFINED] U/MOD [IF] \ U/MOD u1 u2 -- ur uq unsigned division -: U/MOD -0 SWAP UM/MOD -; -[THEN] + : U/MOD + 0 SWAP UM/MOD + ; -[UNDEFINED] UMOD [IF] \ UMOD u1 u2 -- ur unsigned division -: UMOD -U/MOD DROP -; -[THEN] + : UMOD + U/MOD DROP + ; -[UNDEFINED] U/ [IF] \ https://forth-standard.org/standard/core/Div \ U/ u1 u2 -- uq signed quotient -: U/ -U/MOD SWAP DROP -; -[THEN] + : U/ + U/MOD SWAP DROP + ; -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP + [UNDEFINED] SPACES + [IF] + : SPACES BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #HEREXEC,PC -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] -: U.R \ u n -- display u unsigned in n width (n >= 2) - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -$81EF DEVICEID @ U< ; search device ID: MSP430FR4133 or... -DEVICEID @ $8241 U< ; ...MSP430FR2433 -= -$830B DEVICEID @ U< ; MSP430FR21xx/23xx/24xx/25xx/26xx -OR ; -- flag - -[IF] - -\ ============================================================================== -\ driver for RTC without calendar -\ ============================================================================== - - CREATE RTCSEC 2 ALLOT - CREATE RTCMIN 2 ALLOT - CREATE RTCHOUR 2 ALLOT - CREATE RTCDOW 2 ALLOT - CREATE RTCDAY 2 ALLOT - CREATE RTCMON 2 ALLOT - CREATE RTCYEAR 2 ALLOT - -\ ************************************\ - HDNCODE RTC_INT \ computes sec min hour day month year -\ ************************************\ - ADD #2,RSP \ remove previous_SR - BIT #1,&RTCIV \ clear RTC_IFG - ADD.B #1,&RTCSEC \ sec+1 - CMP.B #60,&RTCSEC - U>= IF - MOV.B #0,&RTCSEC \ sec=0 - ADD.B #1,&RTCMIN \ min+1 - CMP.B #60,&RTCMIN - U>= IF - MOV.B #0,&RTCMIN \ min=0 - ADD.B #1,&RTCHOUR \ hour+1 - CMP.B #24,&RTCHOUR - U>= IF - MOV.B #0,&RTCHOUR \ hour=0 - ADD.B #1,&RTCDOW \ dow+1 - CMP.B #7,&RTCDOW - U>= IF - MOV.B #0,&RTCDOW \ dow=0 - THEN - ADD.B #1,&RTCDAY \ day+1 - CMP.B #2,&RTCMON \ February month ? -\ ------------------------\ here we compute leap year - 0= IF \ yes - COLON - RTCYEAR @ 4 UMOD - IF 29 - ELSE - RTCYEAR @ 100 UMOD - IF 30 - ELSE - RTCYEAR @ 400 UMOD - IF 29 - ELSE 30 - THEN - THEN - THEN - HI2LO - MOV @RSP+,IP - MOV TOS,X \ X = 29|30 - MOV @PSP+,TOS -\ ------------------------\ - ELSE \ month other than Feb - MOV #31,X - MOV.B &RTCMON,W - CMP.B #8,W - 0>= IF \ month >= August? - ADD.B #1,W - THEN - BIT.B #1,W \ - 0<> IF - ADD #1,X \ 31 days / month - THEN - THEN - CMP.B X,&RTCDAY - U>= IF \ max day of month is exceeded - MOV.B #1,&RTCDAY \ day=1 - ADD.B #1,&RTCMON \ mon+1 - CMP.B #13,&RTCMON - U>= IF - MOV.B #1,&RTCMON \ mon=1 - ADD #1,&RTCYEAR \ year+1 - THEN - THEN - THEN - THEN - THEN \ - MOV @RSP+,PC \ RET to BACKGrouND routine, with GIE disabled - ENDCODE - -\ ------------------------\ - HDNCODE STOP_RTC \ define STOP_RTC as new COLD_APP subroutine, called by {RTC}|WIPE|RST|COLD|SYS_failures. -\ ------------------------\ ------------------------------------------ - CMP #RET_ADR,&{RTC}+8 \ - 0<> IF \ and only if RTC_APP is started by START_RTC - MOV #{RTC}+10,X \ - MOV #RET_ADR,-2(X) \ restore {RTC}+8 default value - MOV @X+,&RTC_VEC \ restore previous RTC_VEC content from {RTC}+10 - MOV @X+,&COLD+2 \ restore previous STOP_APP from {RTC}+12 to COLD_PFA - MOV @X+,&WARM+2 \ restore previous INI_APP from {RTC}+14 to WARM_PFA -\ MOV @X+,&SLEEP+2 \ restore previous BACKGND_APP from {RTC}+16 to SLEEP_PFA - THEN -\ ------------------------\ - MOV #0,&RTCCTL \ stops RTC and RTC_INT, see RTC15 in MSP430FR2xxx errata sheet - MOV.B #XIN,X \ X = bit_position of XT1 Xtal - BIC.B X,&XT1_SEL \ XIN as GPIO - BIS.B X,&XT1_DIR \ XIN as output - BIC.B X,&XT1_OUT \ RTC15 :"toggle twice XIN ouput" - BIS.B X,&XT1_OUT \ "with at least 2 rising or falling edges". - BIC.B X,&XT1_OUT \ - BIS.B X,&XT1_OUT \ - BIC.B X,&XT1_DIR \ restore default state of XIN - BIS.B X,&XT1_SEL \ XIN as XT1 input -\ ------------------------\ - MOV &COLD+2,PC \ 5 link (branch) to the previous STOP_APP subroutine, -\ ------------------------\ then RET to MARKER_DOES or to COLD+4 - ENDCODE \ -\ ------------------------\ - -\ ----------------------------------------\ - HDNCODE INI_RTC \ define INI_HDWR_APP called first by START_RTC then by WARM -\ ----------------------------------------\ --------------------------------------------------------- - CALL &{RTC}+14 \ call previous INI_APP (which sets TOS = RSTIV_MEM) - CMP #0,&RTCCTL \ if RTCCTL = 0 = reset state, app is STOPPED and must to be started - 0= IF \ and if RTCCTL <> 0, we don't restart app and no time is lost. - MOV #$7F,&RTCMOD \ RTCMOD = 127 - BIT #-1,&RTCIV \ clear RTC_IFG - MOV #%0010_0110_0100_0010,&RTCCTL \ starts RTC with XT1CLK/256, enables RTC_INT - THEN - MOV @RSP+,PC \ RET to BODYWARM|START_RTC - ENDCODE \ -\ ----------------------------------------\ - -\\ ------------------------------------------------------------------------------- -\\ WARNING! because RTC_INT have higher priority than eUSCI used for TERMINAL, -\\ BACKGND_APP default subroutine execute pending RTC_INT, so you can download a file without RTC time lost. -\\ but if you manualy type a command, pending RTC_INT may not be executed during this time. -\\ ------------------------------------------------------------------------------- -\\ --------------------\ -\\ HDNCODE BACKGND_RTC \ define BACKGND_RTC to replace actual BACKGND_APP -\\ --------------------\ -\ BEGIN \ -\ MOV &LPM_MODE,SR \ enter to SLEEP mode, waiting RTC_INT -\ AGAIN \ loop back to BEGIN is executed before CPU shut down -\\ --------------------\ -\ ENDCODE \ -\\ ------------------------------------------------------------------------------- -\\ WARNING! because unlinked, this BACKGND_APP doesn't execute XON, TERMINAL is MUTEd -\\ but maybe that is what you want: RTC time keeps its accuracy. -\\ ------------------------------------------------------------------------------- - -\ --------------------------------\ - CODE START_RTC \ save current content of WARM_PFA, COLD_PFA, SLEEP_PFA, RTC_VEC -\ --------------------------------\ then replace them by INI_RTC, STOP_RTC, BACKGND_RTC, RTC_INT then execute INI_RTC. - CMP #STOP_RTC,&{RTC}+8 \ content of {RTC}+8 = STOP_RTC ? - 0<> IF \ if not - MOV #STOP_RTC,&{RTC}+8 \ STOP_RTC must be executed by MARKER_DOES of {RTC}, else RTC15 hangs out! - MOV &RTC_VEC,&{RTC}+10 \ save content of RTC_VEC to {RTC}+10... - MOV #RTC_INT,&RTC_VEC \ then set RTC_VEC with RTC_INT - MOV &COLD+2,&{RTC}+12 \ save content of COLD_PFA to {RTC}+12... - MOV #STOP_RTC,&COLD+2 \ ...and replace it by STOP_RTC, else RTC15 hangs out with Deep_RST! - MOV &WARM+2,&{RTC}+14 \ save content of WARM_PFA to {RTC}+14... - MOV #INI_RTC,&WARM+2 \ ...and replace it by INI_RTC -\ MOV &SLEEP+2,&{RTC}+16 \ save content of SLEEP_PFA to {RTC}+16... -\ MOV #BACKGND_RTC,&SLEEP+2 \ ...and replace it by BACKGND_RTC - THEN \ - CALL #INI_RTC \ - MOV @IP+,PC \ -\ --------------------------------\ - ENDCODE -\ --------------------------------\ - - : TIME? \ display time - RTCHOUR C@ 2 U.R $3A EMIT - RTCMIN C@ 2 U.R $3A EMIT - RTCSEC C@ 2 U.R + ?DUP + WHILE + 'SP' EMIT + 1- + REPEAT ; - - : TIME! \ hour min sec --- - START_RTC \ if not yet done, obviously! - 2 DEPTH - U< IF \ if 3 numbers on stack - RTCSEC C! - RTCMIN C! - RTCHOUR C! - THEN - ." it is " TIME? - ; - - : DATE? \ display date + [THEN] -[ELSE] - -\ ============================================================================== -\ driver RTC for RTC_B|RTC_C hardware with calendar -\ ============================================================================== + [UNDEFINED] U.R + [IF] + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] CODE TIME? BEGIN BIT.B #RTCRDY,&RTCCTL1 0<> UNTIL \ wait until RTCRDY high COLON - RTCHOUR C@ 2 U.R $3A EMIT - RTCMIN C@ 2 U.R $3A EMIT - RTCSEC C@ 2 U.R + RTCHOUR C@ 2 U.R ':' EMIT + RTCMIN C@ 2 U.R ':' EMIT + RTCSEC C@ 2 U.R ; - + : TIME! 2 DEPTH U< IF \ if 3 numbers on stack @@ -692,7 +566,7 @@ OR ; -- flag RTCMIN C! RTCHOUR C! THEN - ." it is " TIME? + ." it is " TIME? ; CODE DATE? \ display date @@ -701,7 +575,7 @@ OR ; -- flag 0<> UNTIL \ wait until windows time RTC_ReaDY is high COLON -[THEN] +\ [THEN] \ ============================================================================== \ end of RTC software|harware calendar @@ -717,145 +591,163 @@ OR ; -- flag 4 OF ." Wed" ENDOF 5 OF ." Thu" ENDOF 6 OF ." Fri" ENDOF - ENDCASE + ENDCASE RTCYEAR @ RTCMON C@ RTCDAY C@ \ -- year mon day $20 EMIT - 2 U.R $2F EMIT \ -- year mon - 2 U.R $2F EMIT \ -- year + 2 U.R '/' EMIT \ -- year mon + 2 U.R '/' EMIT \ -- year . \ -- -; - - + ; -: DATE! \ year mon day -- -2 DEPTH -U< IF \ if 3 numbers on stack - RTCYEAR ! - RTCMON C! - RTCDAY C! -THEN -RTCDAY C@ -RTCMON C@ -RTCYEAR @ \ -- day mon year + : DATE! \ year mon day -- + 2 DEPTH + U< IF \ if 3 numbers on stack + RTCYEAR ! + RTCMON C! + RTCDAY C! + THEN + RTCDAY C@ + RTCMON C@ + RTCYEAR @ \ -- day mon year \ ------------------------------------------ \ Zeller's congruence for gregorian calendar \ see https://www.rosettacode.org/wiki/Day_of_the_week#Forth \ : ZELLER \ day mon year -- weekday {0=Sat, ..., 6=Fri} -\ OVER 3 < \ -\ IF 1- SWAP 12 + SWAP +\ OVER 3 < \ +\ IF 1- SWAP 12 + SWAP \ THEN \ -- d m' y' with m' {3=March, ..., 14=february} \ 100 /MOD \ -- d m' K J with K = y' in century, J = century -\ DUP 4 / SWAP 2* - \ -- d m' K (J/4 - 2J) -\ SWAP DUP 4 / + + \ -- d m' ((J/4 - 2J) + (K + K/4)) +\ DUP 4 / SWAP 2* - \ -- d m' K (J/4 - 2J) +\ SWAP DUP 4 / + + \ -- d m' ((J/4 - 2J) + (K + K/4)) \ SWAP 1+ 13 5 */ + + \ -- (d + (((J/4 - 2J) + (K + K/4)) + (m+1)*13/5)) -\ 7 MOD \ -- weekday = {0=Sat, ..., 6=Fri} +\ 7 MOD \ -- weekday = {0=Sat, ..., 6=Fri} \ ------------------------------------------ -OVER 3 U< \ -IF 1 - SWAP 12 + SWAP -THEN \ -- d m' y' with m' {3=March, ..., 14=february} -100 U/MOD \ -- d m' K J with K = y' in century, J = century -DUP 4 U/ SWAP 2* - \ -- d m' K (J/4 - 2J) -SWAP DUP 4 U/ + + \ -- d m' ((J/4 - 2J) + (K + K/4)) -SWAP 1+ 13 5 U*/ + + \ -- (d + (((J/4 - 2J) + (K + K/4)) + (m+1)*13/5)) -7 UMOD \ -- weekday = {0=Sat, ..., 6=Fri} + OVER 3 U< \ + IF 1 - SWAP 12 + SWAP + THEN \ -- d m' y' with m' {3=March, ..., 14=february} + 100 U/MOD \ -- d m' K J with K = y' in century, J = century + DUP 4 U/ SWAP 2* - \ -- d m' K (J/4 - 2J) + SWAP DUP 4 U/ + + \ -- d m' ((J/4 - 2J) + (K + K/4)) + SWAP 1+ 13 5 U*/ + + \ -- (d + (((J/4 - 2J) + (K + K/4)) + (m+1)*13/5)) + 7 UMOD \ -- weekday = {0=Sat, ..., 6=Fri} \ ------------------------------------------ -RTCDOW C! \ -- -." we are on " DATE? -; - -RST_HERE - -[UNDEFINED] S_ [IF] -CODE S_ \ Squote alias with blank instead quote separator -MOV #0,&CAPS \ turn CAPS OFF -COLON -XSQUOTE , \ compile run-time code -$20 WORD \ -- c-addr (= HERE) -HI2LO -MOV.B @TOS,TOS \ -- len compile string -ADD #1,TOS \ -- len+1 -BIT #1,TOS \ C = ~Z -ADDC TOS,&DP \ store aligned DP -MOV @PSP+,TOS \ -- -MOV @RSP+,IP \ pop paired with push COLON -MOV #$20,&CAPS \ turn CAPS ON (default state) -MOV @IP+,PC \ NEXT -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ESC [IF] -CODE ESC -CMP #0,&STATEADR -0= IF MOV @IP+,PC \ interpret time usage disallowed -THEN -COLON -$1B \ -- char escape -POSTPONE LITERAL \ compile-time code : lit $1B -POSTPONE EMIT \ compile-time code : EMIT -POSTPONE S_ \ compile-time code : S_ <escape_sequence> -POSTPONE TYPE \ compile-time code : TYPE -; IMMEDIATE -[THEN] - -[UNDEFINED] >BODY [IF] + RTCDOW C! \ -- + ." we are on " DATE? + ; + + RST_SET + + [UNDEFINED] S_ + [IF] + CODE S_ \ Squote alias with blank instead quote separator + MOV #0,&CAPS \ turn CAPS OFF + COLON + XSQUOTE , \ compile run-time code + $20 WORD \ -- c-addr (= HERE) + HI2LO + MOV.B @TOS,TOS \ -- len compile string + ADD #1,TOS \ -- len+1 + BIT #1,TOS \ C = ~Z + ADDC TOS,&DP \ store aligned DP + MOV @PSP+,TOS \ -- + MOV @RSP+,IP \ pop paired with push COLON + MOV #$20,&CAPS \ turn CAPS ON (default state) + MOV @IP+,PC \ NEXT + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC + [IF] + CODE ESC + CMP #0,&STATEADR + 0= IF MOV @IP+,PC \ interpret time usage disallowed + THEN + COLON + $1B \ -- char escape + POSTPONE LITERAL \ compile-time code : lit $1B + POSTPONE EMIT \ compile-time code : EMIT + POSTPONE S_ \ compile-time code : S_ <escape_sequence> + POSTPONE TYPE \ compile-time code : TYPE + ; IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/toBODY \ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] EXECUTE [IF] \ " \ https://forth-standard.org/standard/core/EXECUTE \ EXECUTE i*x xt -- j*x execute Forth word at 'xt' -CODE EXECUTE -PUSH TOS \ 3 push xt -MOV @PSP+,TOS \ 2 -MOV @RSP+,PC \ 4 xt --> PC -ENDCODE -[THEN] - -[UNDEFINED] EVALUATE [IF] + [UNDEFINED] EXECUTE + [IF] \ " + CODE EXECUTE + PUSH TOS \ 3 push xt + MOV @PSP+,TOS \ 2 + MOV @RSP+,PC \ 4 xt --> PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/EVALUATE \ EVALUATE \ i*x c-addr u -- j*x interpret string -CODE EVALUATE -MOV #SOURCE_LEN,X \ 2 -MOV @X+,S \ 2 S = SOURCE_LEN -MOV @X+,T \ 2 T = SOURCE_ORG -MOV @X+,W \ 2 W = TOIN -PUSHM #4,IP \ 6 PUSHM IP,S,T,W -LO2HI -INTERPRET -HI2LO -MOV @RSP+,&TOIN \ 4 -MOV @RSP+,&SOURCE_ORG \ 4 -MOV @RSP+,&SOURCE_LEN \ 4 -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -: SET_TIME -ESC [8;40;80t \ set terminal display 42L * 80C -39 0 DO CR LOOP \ to avoid erasing any line of source, create 42 empty lines -ESC [H \ then set cursor home -CR ." DATE (DMY): " -PAD_ORG DUP PAD_LEN -['] ACCEPT >BODY \ find default part of deferred ACCEPT (terminal input) -EXECUTE \ wait human input for D M Y -EVALUATE \ interpret this input -CR DATE! \ set date -CR ." TIME (HMS): " -PAD_ORG DUP PAD_LEN -['] ACCEPT >BODY \ find default part of deferred ACCEPT (terminal input) -EXECUTE \ wait human input for H M S -EVALUATE \ interpret this input -CR TIME! \ set time -RST_STATE \ remove code beyond RST_HERE -; - + [UNDEFINED] EVALUATE + [IF] + CODE EVALUATE + MOV #SOURCE_LEN,X \ 2 + MOV @X+,S \ 2 S = SOURCE_LEN + MOV @X+,T \ 2 T = SOURCE_ORG + MOV @X+,W \ 2 W = TOIN + PUSHM #4,IP \ 6 PUSHM IP,S,T,W + LO2HI + [ ' \ 8 + , ] \ compile INTERPRET = BACKSLASH + 8 + HI2LO + MOV @RSP+,&TOIN \ 4 + MOV @RSP+,&SOURCE_ORG \ 4 + MOV @RSP+,&SOURCE_LEN \ 4 + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + +\ DEFER CR \ DEFERed definition, by default executes that of :NONAME + CODE CR \ create a DEFER definition of CR + MOV #NEXT_ADR,PC + ENDCODE + + :NONAME \ starts at BODY address of DEFERed CR + 'CR' EMIT 'LF' EMIT + ; IS CR \ CR executes :NONAME by default + [THEN] + + : SET_TIME + ESC [8;40;80t \ set terminal display 42L * 80C + 39 0 DO CR LOOP \ to avoid erasing any line of source, create 42 empty lines + ESC [H \ then set cursor home + CR ." DATE (DMY): " + PAD_ORG DUP PAD_LEN + ['] ACCEPT >BODY \ find default part of deferred ACCEPT (terminal input) + EXECUTE \ wait human input for D M Y + EVALUATE \ interpret this input + CR DATE! \ set date + CR ." TIME (HMS): " + PAD_ORG DUP PAD_LEN + ['] ACCEPT >BODY \ find default part of deferred ACCEPT (terminal input) + EXECUTE \ wait human input for H M S + EVALUATE \ interpret this input + CR TIME! \ set time + RST_RET \ remove code beyond RST_HERE + ; + ECHO SET_TIME diff --git a/MSP430-FORTH/SD_430FR5994/BOOT.4TH b/MSP430-FORTH/SD_430FR5994/BOOT.4TH new file mode 100644 index 0000000..1516317 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/BOOT.4TH @@ -0,0 +1,39 @@ + +; -------- +; BOOT.4th for MSP_EXP430FR5994 +; -------- + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EXECUTE + [IF] + CODE EXECUTE + PUSH R14 + MOV @R15+,R14 + MOV @R1+,R0 + ENDCODE + [THEN] + + $04 = + [IF] + RST_RET + NOECHO LOAD" SD_TEST.4TH" + [ELSE] + ' SYS $0A + EXECUTE + [THEN] diff --git a/MSP430-FORTH/SD_430FR5994/CHNGBAUD.4TH b/MSP430-FORTH/SD_430FR5994/CHNGBAUD.4TH new file mode 100644 index 0000000..70ad46f --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/CHNGBAUD.4TH @@ -0,0 +1,466 @@ + + CODE I2CTERM_ABORT + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$3C00,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" <-- Ouch! unexpected I2C_FastForth target!" + RST_RET + ; + +I2CTERM_ABORT + +; ------------ +; CHNGBAUD.4th for MSP_EXP430FR5994 +; ------------ + + [UNDEFINED] DUP [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR [IF] + DEFER CR + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] 1+ [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U/ [IF] + CODE U/ + SUB #2,R15 + MOV #0,0(R15) + CALL #$403E + MOV @R15,R14 + ADD #4,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + ELSE + XOR #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] < [IF] + CODE < + SUB @R15+,R14 + S< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE > + SUB @R15+,R14 + S< ?GOTO BW1 +FW1 AND #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] CASE [IF] + : CASE 0 ; IMMEDIATE + + + : OF + 1+ + >R + POSTPONE OVER POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + [UNDEFINED] S_ [IF] + CODE S_ + MOV #0,&$1DC0 + COLON + $401E , + $20 WORD + HI2LO + MOV.B @R14,R14 + ADD #1,R14 + BIT #1,R14 + ADDC R14,&$1DC8 + MOV @R15+,R14 + MOV @R1+,R13 + MOV #$20,&$1DC0 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC [IF] + CODE ESC + CMP #0,&$1DBC + 0= IF MOV @R13+,R0 + THEN + COLON + $1B + POSTPONE LITERAL + POSTPONE EMIT + POSTPONE S_ + POSTPONE TYPE + ; IMMEDIATE + [THEN] + + : BAD_MHz + $20 DUP EMIT + ABORT" only for 1,4,8,16,24 MHz MCLK!" + ; + + : OVR_BAUDS + $20 DUP EMIT ESC [7m + ." with MCLK = " $1800 @ 1000 U/ . + ABORT" MHz? don't dream!" + ; + + : CHNGBAUD + RST_RET + ECHO + ESC [8;42;80t + 41 0 DO CR LOOP + ESC [H + + $1800 @ DUP >R + ." target MCLK = " 1000 U/ . ." MHz" CR + ." choose your baudrate:" CR + ." 0 --> 6 MBds" CR + ." 1 --> 5 MBds" CR + ." 2 --> 4 MBds" CR + ." 3 --> 3 MBds" CR + ." 4 --> 1843200 Bds" CR + ." 5 --> 921600 Bds" CR + ." 6 --> 460800 Bds" CR + ." 7 --> 230400 Bds" CR + ." 8 --> 115200 Bds" CR + ." 9 --> 38400 Bds" CR + ." A --> 19200 Bds" CR + ." B --> 9600 Bds" CR + ." other --> abort" CR + ." your choice: " + KEY + CASE + #48 OF ." 6 MBds" + R> CASE + #24000 OF $4 $0 + ENDOF + 24000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #49 OF ." 5 MBds" + R> CASE + #24000 OF $4 $EE00 ENDOF + #20000 OF $4 $0 ENDOF + 20000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #50 OF ." 4 MBds" + R> CASE + #24000 OF $6 $0 ENDOF + #20000 OF $5 $0 ENDOF + #16000 OF $4 $0 ENDOF + 16000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #51 OF ." 3 MBds" + R> CASE + #24000 OF $8 $0 ENDOF + #20000 OF $6 $D600 ENDOF + #16000 OF $5 $4900 ENDOF + #12000 OF $4 $0 ENDOF + 12000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #52 OF ." 1843200 Bds" + R> CASE + #24000 OF $0D $0200 ENDOF + #20000 OF $0A $DF00 ENDOF + #16000 OF $8 $D600 ENDOF + #12000 OF $6 $AA00 ENDOF + #8000 OF $5 $9200 ENDOF + 8000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #53 OF ." 921600 Bds" + R> CASE + #24000 OF $1 $00A1 ENDOF + #20000 OF $1 $B751 ENDOF + #16000 OF $11 $4A00 ENDOF + #12000 OF $0D $0200 ENDOF + #8000 OF $8 $D600 ENDOF + #4000 OF $4 $4900 ENDOF + 4000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #54 OF ." 460800 Bds" + R> CASE + #24000 OF $3 $0241 ENDOF + #20000 OF $2 $92B1 ENDOF + #16000 OF $2 $BB21 ENDOF + #12000 OF $1 $00A1 ENDOF + #8000 OF $11 $4A00 ENDOF + #4000 OF $8 $D600 ENDOF + #2000 OF $4 $4900 ENDOF + 2000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #55 OF ." 230400 Bds" + R> CASE + #24000 OF $6 $2081 ENDOF + #20000 OF $5 $EE61 ENDOF + #16000 OF $4 $5551 ENDOF + #12000 OF $3 $0241 ENDOF + #8000 OF $2 $BB21 ENDOF + #4000 OF $11 $4A00 ENDOF + #2000 OF $8 $D600 ENDOF + #1000 OF $4 $4900 ENDOF + 1000 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #56 OF ." 115200 Bds" + R> CASE + #24000 OF $0D $4901 ENDOF + #20000 OF $0A $AD01 ENDOF + #16000 OF $8 $F7A1 ENDOF + #12000 OF $6 $2081 ENDOF + #8000 OF $4 $5551 ENDOF + #4000 OF $2 $BB21 ENDOF + #2000 OF $11 $4A00 ENDOF + #1000 OF $8 $D600 ENDOF + #500 OF $4 $4900 ENDOF + 500 < + IF OVR_BAUDS + THEN BAD_MHz + ENDCASE + ENDOF + #57 OF ." 38400 Bds" + R> CASE + #24000 OF $27 $0011 ENDOF + #16000 OF $1A $D601 ENDOF + #8000 OF $0D $4901 ENDOF + #4000 OF $6 $2081 ENDOF + #1000 OF $1 $00A1 ENDOF + BAD_MHz + ENDCASE + ENDOF + #65 OF ." 19200 Bds" + R> CASE + #24000 OF $4E $0021 ENDOF + #16000 OF $34 $4911 ENDOF + #8000 OF $1A $D601 ENDOF + #4000 OF $0D $4901 ENDOF + #1000 OF $3 $0241 ENDOF + BAD_MHz + ENDCASE + ENDOF + #66 OF ." 9600 Bds" + R> CASE + #24000 OF $9C $0041 ENDOF + #16000 OF $68 $D621 ENDOF + #8000 OF $34 $4911 ENDOF + #4000 OF $1A $D601 ENDOF + #1000 OF $6 $2081 ENDOF + BAD_MHz + ENDCASE + ENDOF + ." abort" ABORT" " + ENDCASE + $1804 ! + $1802 ! + CR ESC [7m + ." Change baudrate in Teraterm, save its setup, then reset target." + ; + + CHNGBAUD diff --git a/MSP430-FORTH/SD_430FR5994/CORDIC.4TH b/MSP430-FORTH/SD_430FR5994/CORDIC.4TH new file mode 100644 index 0000000..1eb0aa9 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/CORDIC.4TH @@ -0,0 +1,510 @@ + + CODE ABORT_CORDIC + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$100,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with FIXPOINT_INPUT addon" + RST_RET + ; + + ABORT_CORDIC + +; ---------- +; CORDIC.4th for MSP_EXP430FR5994 +; ---------- + +MARKER {CORDIC} + + CREATE T_ARCTAN + 12870 , + 7598 , + 4014 , + 2038 , + 1023 , + 512 , + 256 , + 128 , + 64 , + 32 , + 16 , + 8 , + 4 , + 2 , + 1 , + + CREATE T_SCALE + 46340 , + 41448 , + 40211 , + 39900 , + 39822 , + 39803 , + 39798 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + 39797 , + + [UNDEFINED] DABS + [IF] + CODE DABS + AND #-1,R14 + S< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + RST_SET + + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + + $180E 1 TSTBIT + + RST_RET + + [IF] ; MSP430FRxxxx with hardware_MPY + + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @R15+,R9 +BW3 ADD R14,R9 + MOV &$1DB2,R8 + BEGIN + SUB #1,R9 + SUB #1,R14 + U>= WHILE + SUB #1,R8 + MOV.B @R9,0(R8) + REPEAT + MOV R8,&$1DB2 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] F#S + [IF] + CODE F#S + MOV 2(R15),R9 + MOV @R15,2(R15) + MOV R9,0(R15) + MOV R14,R11 + MOV #0,R12 + BEGIN MOV @R15,&$4C0 + MOV &$1DBE,&$4C8 + MOV &$4E4,0(R15) + MOV &$4E6,R14 + CMP #10,R14 + U>= IF ADD #7,R14 + THEN ADD #$30,R14 + MOV.B R14,$1D90(R12) + ADD #1,R12 + CMP R11,R12 + 0= UNTIL MOV R11,R14 + MOV #0,0(R15) + MOV #$1D90,R9 + GOTO BW3 + ENDCODE + [THEN] + + HDNCODE XSCALE + MOV T_SCALE(R10),&$4D4 + MOV #0,&$4D6 + MOV R9,&$4C8 + MOV &$4E6,R9 + MOV @R1+,R0 + ENDCODE + + [ELSE] ; no hardware multiplier + + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @R15+,R9 +BW3 ADD R14,R9 + MOV &$1DB2,R8 + BEGIN + SUB #1,R9 + SUB #1,R14 + U>= WHILE + SUB #1,R8 + MOV.B @R9,0(R8) + REPEAT + MOV R8,&$1DB2 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] F#S + [IF] + CODE F#S + MOV @R15,R12 + MOV #0,R11 + PUSHM #3,R13 + MOV 2(R15),0(R15) + MOV R14,2(R15) + BEGIN MOV &$1DBE,R14 + LO2HI + UM* + HI2LO + CMP #10,R14 + U>= IF ADD #7,R14 + THEN ADD #$30,R14 + MOV @R1,R11 + MOV.B R14,$1D90(R11) + ADD #1,R11 + MOV R11,0(R1) + CMP 2(R15),R11 + U>= UNTIL POPM #3,R13 + MOV R11,R14 + MOV R12,2(R15) + MOV #0,0(R15) + MOV #$1D90,R9 + GOTO BW3 + ENDCODE + [THEN] + + HDNCODE XSCALE + MOV T_SCALE(R10),R6 + UMSTAR1 MOV #0,R8 + MOV #0,R12 + MOV #0,R11 + MOV #1,R10 + BEGIN BIT R10,R6 + 0<> IF ADD R9,R12 + ADDC R8,R11 + THEN ADD R9,R9 + ADDC R8,R8 + ADD R10,R10 + U>= UNTIL + MOV R11,R9 + MOV #$40C4,R6 + MOV @R1+,R0 + ENDCODE + + [THEN] ; endcase of hardware multiplier + + CODE POL2REC + PUSH R13 + MOV @R15+,&$4D0 + MOV R14,&$4D2 + MOV #286,&$4C8 + MOV &$4E4,R8 + MOV &$4E6,R14 + MOV #-1,R13 + MOV @R15,R9 + MOV #0,R8 + BEGIN + ADD #1,R13 + MOV R9,R12 + MOV R8,R11 + MOV #0,R10 + GOTO FW1 + BEGIN + RRA R12 + RRA R11 + ADD #1,R10 +FW1 CMP R13,R10 + 0= UNTIL + ADD R10,R10 + CMP #0,R14 + 0>= IF + SUB R11,R9 + ADD R12,R8 + SUB T_ARCTAN(R10),R14 + ELSE + ADD R11,R9 + SUB R12,R8 + ADD T_ARCTAN(R10),R14 + THEN + CMP #0,R14 + 0<> WHILE + CMP #14,R13 + 0= UNTIL + THEN + CALL #XSCALE + MOV R9,0(R15) + MOV R8,R9 + CALL #XSCALE + MOV R9,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + + + CODE REC2POL + MOV @R15,R9 + MOV R14,R8 + MOV R8,R11 + CMP #0,R11 + S< IF + XOR #-1,R11 + ADD #1,R11 + THEN + MOV R9,R12 + CMP #0,R12 + S< IF + XOR #-1,R12 + ADD #1,R12 + THEN + MOV #-1,R14 + CMP #0,R9 + 0= IF + CMP #0,R8 + 0= IF + LO2HI + ABORT" null inputs!" + HI2LO + THEN + THEN + CMP R12,R11 + U< IF + MOV R12,R11 + THEN + CMP #16384,R11 + U>= IF + LO2HI + ABORT" |x| or |y| >= 16384" + HI2LO + THEN + MOV #1,R12 + RLAM #3,R11 + GOTO FW1 + BEGIN + ADD R9,R9 + ADD R8,R8 + ADD R12,R12 + ADD R11,R11 +FW1 + U>= UNTIL + PUSHM #2,R13 + MOV #-1,R13 + MOV #0,R14 + BEGIN + ADD #1,R13 + MOV R9,R12 + MOV R8,R11 + MOV #0,R10 + GOTO FW1 + BEGIN + RRA R12 + RRA R11 + ADD #1,R10 +FW1 CMP R13,R10 + 0= UNTIL + ADD R10,R10 + CMP #0,R8 + S>= IF + ADD R11,R9 + SUB R12,R8 + ADD T_ARCTAN(R10),R14 + ELSE + SUB R11,R9 + ADD R12,R8 + SUB T_ARCTAN(R10),R14 + THEN + CMP #0,R8 + 0<> WHILE + CMP #14,R13 + 0= UNTIL + THEN + CALL #XSCALE + POPM #2,R13 + GOTO FW1 + BEGIN + RRA R9 +FW1 RRA R12 + U>= UNTIL + MOV R9,0(R15) + SUB #4,R15 + MOV R14,R6 + CMP #0,R6 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + MOV #0,2(R15) + MOV R14,0(R15) + MOV #286,R14 + CALL #$403E + MOV @R15+,0(R15) + CMP #0,R6 + S< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + THEN + MOV #$40C4,R6 + MOV @R13+,R0 + ENDCODE + + + [UNDEFINED] F. + [IF] + CODE F. + MOV R14,R12 + MOV #4,R11 + MOV &$1DBE,R10 + CMP ##10,R10 + 0= IF + ADD #1,R11 + ELSE + CMP #%10,R10 + 0= IF + MOV #16,R11 + THEN + THEN + PUSHM #3,R13 + LO2HI + <# DABS + R> F#S + $2C HOLD + #S + R> SIGN #> + TYPE $20 EMIT + ; + + [THEN] + +RST_SET + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @R15,R10 + MOV R14,0(R15) + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + +ECHO + +10000 89,0 POL2REC . . ; sin, cos --> +10000 75,0 POL2REC . . ; sin, cos --> +10000 60,0 POL2REC . . ; sin, cos --> +10000 45,0 POL2REC . . ; sin, cos --> +10000 30,0 POL2REC . . ; sin, cos --> +10000 15,0 POL2REC . . ; sin, cos --> +10000 1,0 POL2REC . . ; sin, cos --> +16384 30,0 POL2REC SWAP . . ; x, y --> +16384 45,0 POL2REC SWAP . . ; x, y --> +16384 60,0 POL2REC SWAP . . ; x, y --> + +10000 -89,0 POL2REC . . ; sin, cos --> +10000 -75,0 POL2REC . . ; sin, cos --> +10000 -60,0 POL2REC . . ; sin, cos --> +10000 -45,0 POL2REC . . ; sin, cos --> +10000 -30,0 POL2REC . . ; sin, cos --> +10000 -15,0 POL2REC . . ; sin, cos --> +10000 -1,0 POL2REC . . ; sin, cos --> +16384 -30,0 POL2REC SWAP . . ; x, y --> +16384 -45,0 POL2REC SWAP . . ; x, y --> +16384 -60,0 POL2REC SWAP . . ; x, y --> + +-10000 89,0 POL2REC . . ; sin, cos --> +-10000 75,0 POL2REC . . ; sin, cos --> +-10000 60,0 POL2REC . . ; sin, cos --> +-10000 45,0 POL2REC . . ; sin, cos --> +-10000 30,0 POL2REC . . ; sin, cos --> +-10000 15,0 POL2REC . . ; sin, cos --> +-10000 1,0 POL2REC . . ; sin, cos --> +-16384 30,0 POL2REC SWAP . . ; x, y --> +-16384 45,0 POL2REC SWAP . . ; x, y --> +-16384 60,0 POL2REC SWAP . . ; x, y --> + +-10000 -89,0 POL2REC . . ; sin, cos --> +-10000 -75,0 POL2REC . . ; sin, cos --> +-10000 -60,0 POL2REC . . ; sin, cos --> +-10000 -45,0 POL2REC . . ; sin, cos --> +-10000 -30,0 POL2REC . . ; sin, cos --> +-10000 -15,0 POL2REC . . ; sin, cos --> +-10000 -1,0 POL2REC . . ; sin, cos --> +-16384 -30,0 POL2REC SWAP . . ; x, y --> +-16384 -45,0 POL2REC SWAP . . ; x, y --> +-16384 -60,0 POL2REC SWAP . . ; x, y --> + + +2 1 REC2POL F. . ; phase module --> +2 -1 REC2POL F. . ; phase module --> +20 10 REC2POL F. . ; phase module --> +20 -10 REC2POL F. . ; phase module --> +200 100 REC2POL F. . ; phase module --> +100 -100 REC2POL F. . ; phase module --> +2000 1000 REC2POL F. . ; phase module --> +1000 -1000 REC2POL F. . ; phase module --> +16000 8000 REC2POL F. . ; phase module --> +16000 -8000 REC2POL F. . ; phase module --> +16000 0 REC2POL F. . ; phase module --> +0 16000 REC2POL F. . ; phase module --> + +-2 1 REC2POL F. . ; phase module --> +-2 -1 REC2POL F. . ; phase module --> +-20 10 REC2POL F. . ; phase module --> +-20 -10 REC2POL F. . ; phase module --> +-200 100 REC2POL F. . ; phase module --> +-100 -100 REC2POL F. . ; phase module --> +-2000 1000 REC2POL F. . ; phase module --> +-1000 -1000 REC2POL F. . ; phase module --> +-16000 8000 REC2POL F. . ; phase module --> +-16000 -8000 REC2POL F. . ; phase module --> +16000 0 REC2POL F. . ; phase module --> +0 16000 REC2POL F. . ; phase module --> + +10000 89,0 POL2REC REC2POL ROT . F. +10000 75,0 POL2REC REC2POL ROT . F. +10000 60,0 POL2REC REC2POL ROT . F. +10000 45,0 POL2REC REC2POL ROT . F. +10000 30,0 POL2REC REC2POL ROT . F. +10000 26,565 POL2REC REC2POL ROT . F. +10000 15,0 POL2REC REC2POL ROT . F. +10000 14,036 POL2REC REC2POL ROT . F. +10000 7,125 POL2REC REC2POL ROT . F. +10000 1,0 POL2REC REC2POL ROT . F. + + diff --git a/MSP430-FORTH/MSP_EXP430FR5994/CORETEST.4TH b/MSP430-FORTH/SD_430FR5994/CORETEST.4TH similarity index 67% rename from MSP430-FORTH/MSP_EXP430FR5994/CORETEST.4TH rename to MSP430-FORTH/SD_430FR5994/CORETEST.4TH index af330bc..69c1e1a 100644 --- a/MSP430-FORTH/MSP_EXP430FR5994/CORETEST.4TH +++ b/MSP430-FORTH/SD_430FR5994/CORETEST.4TH @@ -1,19 +1,80 @@ -PWR_STATE +\ ; ------------------------------------- +\ ; CORETEST.4TH for any FastForth target +\ ; ------------------------------------- -: COMPNOTFOUND -$0D EMIT \ return to column 1 -1 ABORT" {CORE_ANS} word set not found!" +MARKER {CORETEST} + +: ABORT_TEST \ flag -- +$0D EMIT \ return to column 1 +POSTPONE {CORETEST} \ remove all test words +ABORT" {CORE_ANS} word set not found !" ; -[DEFINED] {CORE_ANS} [IF] +[UNDEFINED] {CORE_ANS} ABORT_TEST : CORETESTSUCCESS -$0A BASE ! -$0D EMIT \ return to column 1 -1 ABORT" CORE tests success!" +$0D EMIT \ -- $0D return to column 1 +$0A BASE ! \ set decimal +{CORETEST} \ remove all test words +." CORETEST + COREPLUSTEST success!" \ true -- ; +[UNDEFINED] SM/REM [IF] +CODE SM/REM +MOV R14,R12 +MOV @R15,R11 +CMP #0,R14 +S< IF + XOR #-1,R14 + ADD #1,R14 +THEN +CMP #0,0(R15) +S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) +THEN +PUSHM #3,R13 +LO2HI + UM/MOD +HI2LO +POPM #3,R13 +CMP #0,R11 +S< IF + XOR #-1,0(R15) + ADD #1,0(R15) +THEN +XOR R12,R11 +CMP #0,R11 +S< IF + XOR #-1,R14 + ADD #1,R14 +THEN +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] FM/MOD [IF] +\ https://forth-standard.org/standard/core/FMDivMOD +\ FM/MOD d1 n1 -- r q floored signed div'n +: FM/MOD +SM/REM +HI2LO \ -- remainder quotient S=divisor +CMP #0,0(R15) \ remainder <> 0 ? +0<> IF + CMP #1,R14 \ quotient < 1 ? + S< IF + ADD R12,0(R15) \ add divisor to remainder + SUB #1,R14 \ decrement quotient + THEN +THEN +MOV @R1+,R13 +MOV @R13+,R0 +ENDCODE +[THEN] + \ From: John Hayes S1I \ Subject: tester.fr \ Date: Mon, 27 Nov 95 13:10:09 PST @@ -639,6 +700,12 @@ T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT ( MISSING TEST: NEGATIVE ALLOT ) +\ Added by GWJ so that ALIGN can be used before , (comma) is tested +1 ALIGNED CONSTANT ALMNT \ -- 1|2|4|8 for 8|16|32|64 bit alignment +ALIGN +T{ HERE 1 ALLOT ALIGN HERE SWAP - ALMNT = -> <TRUE> }T +\ End of extra test + HERE 1 , HERE 2 , CONSTANT 2ND @@ -973,7 +1040,8 @@ CREATE GN-BUF 0 C, T{ 0 0 GN' 0' >NUMBER -> 0 0 GN-CONSUMED }T T{ 0 0 GN' 1' >NUMBER -> 1 0 GN-CONSUMED }T T{ 1 0 GN' 1' >NUMBER -> BASE @ 1+ 0 GN-CONSUMED }T -T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T \ SHOULD FAIL TO CONVERT THESE +\ FOLLOWING SHOULD FAIL TO CONVERT +T{ 0 0 GN' -' >NUMBER -> 0 0 GN-STRING }T T{ 0 0 GN' +' >NUMBER -> 0 0 GN-STRING }T T{ 0 0 GN' .' >NUMBER -> 0 0 GN-STRING }T @@ -987,7 +1055,8 @@ T{ 0 0 GN' G' 10 >NUMBER-BASED -> 0 0 GN-STRING }T T{ 0 0 GN' G' MAX-BASE >NUMBER-BASED -> 10 0 GN-CONSUMED }T T{ 0 0 GN' Z' MAX-BASE >NUMBER-BASED -> 23 0 GN-CONSUMED }T -: GN1 \ ( UD BASE -- UD' LEN ) UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO. +: GN1 \ ( UD BASE -- UD' LEN ) +\ UD SHOULD EQUAL UD' AND LEN SHOULD BE ZERO. BASE @ >R BASE ! <# #S #> 0 0 2SWAP >NUMBER SWAP DROP \ RETURN LENGTH ONLY @@ -1069,9 +1138,8 @@ CREATE ABUF 80 CHARS ALLOT : ACCEPT-TEST CR ." PLEASE TYPE UP TO 80 CHARACTERS: " ABUF 80 \ ACCEPT \ JMT -['] ACCEPT DUP @ $4030 = \ JMT: if CFA content = $4030 (MOV @PC+,PC), ACCEPT is deferred -IF >BODY \ JMT: find default part of deferred ACCEPT -THEN EXECUTE \ JMT: execute ACCEPT + ['] ACCEPT >BODY \ JMT: find default part of deferred ACCEPT + EXECUTE \ JMT: execute ACCEPT CR ." RECEIVED: " [CHAR] " EMIT ABUF SWAP TYPE [CHAR] " EMIT CR ; @@ -1085,10 +1153,383 @@ T{ : GDX 123 ; : GDX GDX 234 ; -> }T T{ GDX -> 123 234 }T -CR .( End of Core word set tests) - -CORETESTSUCCESS +CR .( End of Core word set tests) \ " + +\ ============================================================================= +\ COREPLUSTEST +\ ============================================================================= +\ Additional tests on the the ANS Forth Core word set +\ ----------------------------------------------------------------------------- +\ https://raw.githubusercontent.com/gerryjackson/forth2012-test-suite/master/src/coreplustest.fth + +\ This program was written by Gerry Jackson in 2007, with contributions from +\ others where indicated, and is in the public domain - it can be distributed +\ and/or modified in any way but please retain this notice. + +\ This program is distributed in the hope that it will be useful, +\ but WITHOUT ANY WARRANTY; without even the implied warranty of +\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +\ The tests are not claimed to be comprehensive or correct + +\ ----------------------------------------------------------------------------- +\ The tests are based on John Hayes test program for the core word set +\ +\ This file provides some more tests on Core words where the original Hayes +\ tests are thought to be incomplete +\ +\ Words tested in this file are: +\ DO I +LOOP RECURSE ELSE >IN IMMEDIATE FIND IF...BEGIN...REPEAT ALLOT DOES> +\ and +\ Parsing behaviour +\ Number prefixes # $ % and 'A' character input +\ Definition names +\ ----------------------------------------------------------------------------- +\ Assumptions and dependencies: +\ - tester.fr or ttester.fs has been loaded prior to this file +\ - core.fr has been loaded so that constants <TRUE> MAX-INT, MIN-INT and +\ MAX-UINT are defined +\ ----------------------------------------------------------------------------- + +DECIMAL + +TESTING DO +LOOP with run-time increment, negative increment, infinite loop +\ Contributed by Reinhold Straub + +VARIABLE ITERATIONS +VARIABLE INCREMENT +: GD7 ( LIMIT START INCREMENT -- ) + INCREMENT ! + 0 ITERATIONS ! + DO + 1 ITERATIONS +! + I + ITERATIONS @ 6 = IF LEAVE THEN + INCREMENT @ + +LOOP ITERATIONS @ +; -[ELSE] COMPNOTFOUND ; download CORE_ANS.f before CORETEST.4TH +T{ 4 4 -1 GD7 -> 4 1 }T +T{ 1 4 -1 GD7 -> 4 3 2 1 4 }T +T{ 4 1 -1 GD7 -> 1 0 -1 -2 -3 -4 6 }T +T{ 4 1 0 GD7 -> 1 1 1 1 1 1 6 }T +T{ 0 0 0 GD7 -> 0 0 0 0 0 0 6 }T +T{ 1 4 0 GD7 -> 4 4 4 4 4 4 6 }T +T{ 1 4 1 GD7 -> 4 5 6 7 8 9 6 }T +T{ 4 1 1 GD7 -> 1 2 3 3 }T +T{ 4 4 1 GD7 -> 4 5 6 7 8 9 6 }T +T{ 2 -1 -1 GD7 -> -1 -2 -3 -4 -5 -6 6 }T +T{ -1 2 -1 GD7 -> 2 1 0 -1 4 }T +T{ 2 -1 0 GD7 -> -1 -1 -1 -1 -1 -1 6 }T +T{ -1 2 0 GD7 -> 2 2 2 2 2 2 6 }T +T{ -1 2 1 GD7 -> 2 3 4 5 6 7 6 }T +T{ 2 -1 1 GD7 -> -1 0 1 3 }T +T{ -20 30 -10 GD7 -> 30 20 10 0 -10 -20 6 }T +T{ -20 31 -10 GD7 -> 31 21 11 1 -9 -19 6 }T +T{ -20 29 -10 GD7 -> 29 19 9 -1 -11 5 }T + +\ ----------------------------------------------------------------------------- +TESTING DO +LOOP with large and small increments + +\ Contributed by Andrew Haley + +MAX-UINT 8 RSHIFT 1+ CONSTANT USTEP +USTEP NEGATE CONSTANT -USTEP +MAX-INT 7 RSHIFT 1+ CONSTANT STEP +STEP NEGATE CONSTANT -STEP + +VARIABLE BUMP + +T{ : GD8 BUMP ! DO 1+ BUMP @ +LOOP ; -> }T + +T{ 0 MAX-UINT 0 USTEP GD8 -> 256 }T +T{ 0 0 MAX-UINT -USTEP GD8 -> 256 }T + +T{ 0 MAX-INT MIN-INT STEP GD8 -> 256 }T +T{ 0 MIN-INT MAX-INT -STEP GD8 -> 256 }T + +\ Two's complement arithmetic, wraps around modulo wordsize +\ Only tested if the Forth system does wrap around, use of conditional +\ compilation deliberately avoided + +MAX-INT 1+ MIN-INT = CONSTANT +WRAP? +MIN-INT 1- MAX-INT = CONSTANT -WRAP? +MAX-UINT 1+ 0= CONSTANT +UWRAP? +0 1- MAX-UINT = CONSTANT -UWRAP? + +: GD9 ( n limit start step f result -- ) + >R IF GD8 ELSE 2DROP 2DROP R@ THEN -> R> }T +; -[THEN] +T{ 0 0 0 USTEP +UWRAP? 256 GD9 +T{ 0 0 0 -USTEP -UWRAP? 1 GD9 +T{ 0 MIN-INT MAX-INT STEP +WRAP? 1 GD9 +T{ 0 MAX-INT MIN-INT -STEP -WRAP? 1 GD9 + +\ ----------------------------------------------------------------------------- +TESTING DO +LOOP with maximum and minimum increments + +: (-MI) MAX-INT DUP NEGATE + 0= IF MAX-INT NEGATE ELSE -32767 THEN ; +(-MI) CONSTANT -MAX-INT + +T{ 0 1 0 MAX-INT GD8 -> 1 }T +T{ 0 -MAX-INT NEGATE -MAX-INT OVER GD8 -> 2 }T + +T{ 0 MAX-INT 0 MAX-INT GD8 -> 1 }T +T{ 0 MAX-INT 1 MAX-INT GD8 -> 1 }T +T{ 0 MAX-INT -1 MAX-INT GD8 -> 2 }T +T{ 0 MAX-INT DUP 1- MAX-INT GD8 -> 1 }T + +T{ 0 MIN-INT 1+ 0 MIN-INT GD8 -> 1 }T +T{ 0 MIN-INT 1+ -1 MIN-INT GD8 -> 1 }T +T{ 0 MIN-INT 1+ 1 MIN-INT GD8 -> 2 }T +T{ 0 MIN-INT 1+ DUP MIN-INT GD8 -> 1 }T + +\ ----------------------------------------------------------------------------- +\ TESTING +LOOP setting I to an arbitrary value + +\ The specification for +LOOP permits the loop index I to be set to any value +\ including a value outside the range given to the corresponding DO. + +\ SET-I is a helper to set I in a DO ... +LOOP to a given value +\ n2 is the value of I in a DO ... +LOOP +\ n3 is a test value +\ If n2=n3 then return n1-n2 else return 1 +: SET-I ( n1 n2 n3 -- n1-n2 | 1 ) + OVER = IF - ELSE 2DROP 1 THEN +; + +: -SET-I ( n1 n2 n3 -- n1-n2 | -1 ) + SET-I DUP 1 = IF NEGATE THEN +; + +: PL1 20 1 DO I 18 I 3 SET-I +LOOP ; +T{ PL1 -> 1 2 3 18 19 }T +: PL2 20 1 DO I 20 I 2 SET-I +LOOP ; +T{ PL2 -> 1 2 }T +: PL3 20 5 DO I 19 I 2 SET-I DUP 1 = IF DROP 0 I 6 SET-I THEN +LOOP ; +T{ PL3 -> 5 6 0 1 2 19 }T +: PL4 20 1 DO I MAX-INT I 4 SET-I +LOOP ; +T{ PL4 -> 1 2 3 4 }T +: PL5 -20 -1 DO I -19 I -3 -SET-I +LOOP ; +T{ PL5 -> -1 -2 -3 -19 -20 }T +: PL6 -20 -1 DO I -21 I -4 -SET-I +LOOP ; +T{ PL6 -> -1 -2 -3 -4 }T +: PL7 -20 -1 DO I MIN-INT I -5 -SET-I +LOOP ; +T{ PL7 -> -1 -2 -3 -4 -5 }T +: PL8 -20 -5 DO I -20 I -2 -SET-I DUP -1 = IF DROP 0 I -6 -SET-I THEN +LOOP ; +T{ PL8 -> -5 -6 0 -1 -2 -20 }T + +\ ----------------------------------------------------------------------------- +TESTING multiple RECURSEs in one colon definition + +: ACK ( m n -- u ) \ Ackermann function, from Rosetta Code + OVER 0= IF NIP 1+ EXIT THEN \ ack(0, n) = n+1 + SWAP 1- SWAP ( -- m-1 n ) + DUP 0= IF 1+ RECURSE EXIT THEN \ ack(m, 0) = ack(m-1, 1) + 1- OVER 1+ SWAP RECURSE RECURSE \ ack(m, n) = ack(m-1, ack(m,n-1)) +; + +T{ 0 0 ACK -> 1 }T +T{ 3 0 ACK -> 5 }T +T{ 2 4 ACK -> 11 }T + +\ ----------------------------------------------------------------------------- +TESTING multiple ELSE's in an IF statement +\ Discussed on comp.lang.forth and accepted as valid ANS Forth + +: MELSE IF 1 ELSE 2 ELSE 3 ELSE 4 ELSE 5 THEN ; +T{ 0 MELSE -> 2 4 }T +T{ -1 MELSE -> 1 3 5 }T + +\ ----------------------------------------------------------------------------- +TESTING manipulation of >IN in interpreter mode + +T{ 12345 DEPTH OVER 9 < 34 AND + 3 + >IN ! -> 12345 2345 345 45 5 }T +T{ 14145 8115 ?DUP 0= 34 AND >IN +! TUCK MOD 14 >IN ! GCD CALCULATION -> 15 }T + +\ ----------------------------------------------------------------------------- +TESTING IMMEDIATE with CONSTANT VARIABLE and CREATE [ ... DOES> ] + +T{ 123 CONSTANT IW1 IMMEDIATE IW1 -> 123 }T +T{ : IW2 IW1 LITERAL ; IW2 -> 123 }T +T{ VARIABLE IW3 IMMEDIATE 234 IW3 ! IW3 @ -> 234 }T +T{ : IW4 IW3 [ @ ] LITERAL ; IW4 -> 234 }T +T{ :NONAME [ 345 ] IW3 [ ! ] ; DROP IW3 @ -> 345 }T +T{ CREATE IW5 456 , IMMEDIATE -> }T +T{ :NONAME IW5 [ @ IW3 ! ] ; DROP IW3 @ -> 456 }T +T{ : IW6 CREATE , IMMEDIATE DOES> @ 1+ ; -> }T +T{ 111 IW6 IW7 IW7 -> 112 }T +T{ : IW8 IW7 LITERAL 1+ ; IW8 -> 113 }T +T{ : IW9 CREATE , DOES> @ 2 + IMMEDIATE ; -> }T +: FIND-IW BL WORD FIND NIP ; ( -- 0 | 1 | -1 ) +T{ 222 IW9 IW10 FIND-IW IW10 -> -1 }T \ IW10 is not immediate +T{ IW10 FIND-IW IW10 -> 224 1 }T \ IW10 becomes immediate + +\ ----------------------------------------------------------------------------- +TESTING that IMMEDIATE doesn't toggle a flag + +VARIABLE IT1 0 IT1 ! +: IT2 1234 IT1 ! ; IMMEDIATE IMMEDIATE +T{ : IT3 IT2 ; IT1 @ -> 1234 }T + +\ ----------------------------------------------------------------------------- +TESTING parsing behaviour of S" ." and ( +\ which should parse to just beyond the terminating character no space needed + +T{ : GC5 S" A string"2DROP ; GC5 -> }T +T{ ( A comment)1234 -> 1234 }T +T{ : PB1 CR ." You should see 2345: "." 2345"( A comment) CR ; PB1 -> }T + +\ ----------------------------------------------------------------------------- +TESTING number prefixes # $ % and 'c' character input +\ Adapted from the Forth 200X Draft 14.5 document + +VARIABLE OLD-BASE +DECIMAL BASE @ OLD-BASE ! +T{ #1289 -> 1289 }T +T{ #-1289 -> -1289 }T +T{ $12eF -> 4847 }T +T{ $-12eF -> -4847 }T +T{ %10010110 -> 150 }T +T{ %-10010110 -> -150 }T +T{ 'z' -> 122 }T +T{ 'Z' -> 90 }T +\ Check BASE is unchanged +T{ BASE @ OLD-BASE @ = -> <TRUE> }T + +\ Repeat in Hex mode +16 OLD-BASE ! 16 BASE ! +T{ #1289 -> 509 }T +T{ #-1289 -> -509 }T +T{ $12eF -> 12EF }T +T{ $-12eF -> -12EF }T +T{ %10010110 -> 96 }T +T{ %-10010110 -> -96 }T +T{ 'z' -> 7a }T +T{ 'Z' -> 5a }T +\ Check BASE is unchanged +T{ BASE @ OLD-BASE @ = -> <TRUE> }T \ 2 + +DECIMAL +\ Check number prefixes in compile mode +T{ : nmp #8327 $-2cbe %011010111 ''' ; nmp -> 8327 -11454 215 39 }T + +\ ----------------------------------------------------------------------------- +TESTING definition names +\ should support {1..31} graphical characters +: !"#$%&'()*+,-./0123456789:;<=>? 1 ; +T{ !"#$%&'()*+,-./0123456789:;<=>? -> 1 }T +: @ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^ 2 ; +T{ @ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^ -> 2 }T +: _`abcdefghijklmnopqrstuvwxyz{|} 3 ; +T{ _`abcdefghijklmnopqrstuvwxyz{|} -> 3 }T +: _`abcdefghijklmnopqrstuvwxyz{|~ 4 ; \ Last character different +T{ _`abcdefghijklmnopqrstuvwxyz{|~ -> 4 }T +T{ _`abcdefghijklmnopqrstuvwxyz{|} -> 3 }T + +\ ----------------------------------------------------------------------------- +TESTING FIND with a zero length string and a non-existent word + +CREATE EMPTYSTRING 0 C, +: EMPTYSTRING-FIND-CHECK ( c-addr 0 | xt 1 | xt -1 -- t|f ) + DUP IF ." FIND returns a TRUE value for an empty string!" CR THEN + 0= SWAP EMPTYSTRING = = ; +T{ EMPTYSTRING FIND EMPTYSTRING-FIND-CHECK -> <TRUE> }T + +CREATE NON-EXISTENT-WORD \ Same as in exceptiontest.fth + 15 C, CHAR $ C, CHAR $ C, CHAR Q C, CHAR W C, CHAR E C, CHAR Q C, + CHAR W C, CHAR E C, CHAR Q C, CHAR W C, CHAR E C, CHAR R C, CHAR T C, + CHAR $ C, CHAR $ C, +T{ NON-EXISTENT-WORD FIND -> NON-EXISTENT-WORD 0 }T + +\ ----------------------------------------------------------------------------- +TESTING IF ... BEGIN ... REPEAT (unstructured) + +T{ : UNS1 DUP 0 > IF 9 SWAP BEGIN 1+ DUP 3 > IF EXIT THEN REPEAT ; -> }T +T{ -6 UNS1 -> -6 }T +T{ 1 UNS1 -> 9 4 }T + +\ ----------------------------------------------------------------------------- +TESTING DOES> doesn't cause a problem with a CREATEd address + +: MAKE-2CONST DOES> 2@ ; +T{ CREATE 2K 3 , 2K , MAKE-2CONST 2K -> ' 2K >BODY 3 }T + +\ ----------------------------------------------------------------------------- +TESTING ALLOT ( n -- ) where n <= 0 + +T{ HERE 5 ALLOT -5 ALLOT HERE = -> <TRUE> }T +T{ HERE 0 ALLOT HERE = -> <TRUE> }T + +\ ----------------------------------------------------------------------------- + +CR .( End of additional Core tests) \ " + +\ ----------------------------------------------------------------------------- +TESTING TO VALUE :NONAME IS DEFER + +T{ 111 VALUE v1 -> }T +T{ -999 VALUE v2 -> }T +T{ v1 -> 111 }T +T{ v2 -> -999 }T +T{ 222 TO v1 -> }T +T{ v1 -> 222 }T +T{ : vd1 v1 ; -> }T +T{ vd1 -> 222 }T +T{ : vd2 TO v2 ; -> }T +T{ v2 -> -999 }T +T{ -333 vd2 -> }T +T{ v2 -> -333 }T +T{ v1 -> 222 }T + +VARIABLE nn1 +VARIABLE nn2 +T{ :NONAME 1234 ; nn1 ! -> }T +T{ :NONAME 9876 ; nn2 ! -> }T +T{ nn1 @ EXECUTE -> 1234 }T +T{ nn2 @ EXECUTE -> 9876 }T + +T{ :NONAME ( n -- 0,1,..n ) DUP IF DUP >R 1- RECURSE R> THEN ; + CONSTANT RN1 -> }T +T{ 0 RN1 EXECUTE -> 0 }T +T{ 4 RN1 EXECUTE -> 0 1 2 3 4 }T + +:NONAME ( n -- n1 ) \ Multiple RECURSEs in one definition + 1- DUP + CASE 0 OF EXIT ENDOF + 1 OF 11 SWAP RECURSE ENDOF + 2 OF 22 SWAP RECURSE ENDOF + 3 OF 33 SWAP RECURSE ENDOF + DROP ABS RECURSE EXIT + ENDCASE +; CONSTANT RN2 + +T{ 1 RN2 EXECUTE -> 0 }T +T{ 2 RN2 EXECUTE -> 11 0 }T +T{ 4 RN2 EXECUTE -> 33 22 11 0 }T +T{ 25 RN2 EXECUTE -> 33 22 11 0 }T + + +T{ DEFER defer5 -> }T +T{ : is-defer5 IS defer5 ; -> }T +T{ ' * IS defer5 -> }T +T{ 2 3 defer5 -> 6 }T +T{ ' + is-defer5 -> }T +T{ 1 2 defer5 -> 3 }T + +\ ----------------------------------------------------------------------------- +TESTING MARKER (contributed by James Bowman) + +T{ : MA? BL WORD FIND NIP 0<> ; -> }T +T{ MARKER MA0 -> }T +T{ : MA1 111 ; -> }T +T{ MARKER MA2 -> }T +T{ : MA1 222 ; -> }T +T{ MA? MA0 MA? MA1 MA? MA2 -> TRUE TRUE TRUE }T +T{ MA1 MA2 MA1 -> 222 111 }T +T{ MA? MA0 MA? MA1 MA? MA2 -> TRUE TRUE FALSE }T +T{ MA0 -> }T +T{ MA? MA0 MA? MA1 MA? MA2 -> FALSE FALSE FALSE }T + +CORETESTSUCCESS diff --git a/MSP430-FORTH/SD_430FR5994/CORE_ANS.4TH b/MSP430-FORTH/SD_430FR5994/CORE_ANS.4TH new file mode 100644 index 0000000..9504cb2 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/CORE_ANS.4TH @@ -0,0 +1,1273 @@ + + CODE ABORT_CORE_ANS + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ; + + ABORT_CORE_ANS + + [UNDEFINED] BC! + [IF] + CODE BC! + BIC @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BS! + [IF] + CODE BS! + BIS @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + $8000 $180E BC! + + RST_RET + +; ---------------------------------- +; CORE_ANS.4th for MSP_EXP430FR5994 +; ---------------------------------- + + MARKER {CORE_ANS} + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #$4032,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV R14,-2(R15) + MOV #$1C80,R14 + SUB R15,R14 + RRA R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH R14 + MOV @R15,R14 + MOV @R1+,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] NIP + [IF] + CODE NIP + ADD #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] @ + [IF] + CODE @ + MOV @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ! + [IF] + CODE ! + MOV @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C! + [IF] + CODE C! + MOV.B @R15+,0(R14) + ADD #1,R15 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C, + [IF] + CODE C, + MOV &$1DC8,R10 + MOV.B R14,0(R10) + ADD #1,&$1DC8 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0<> + [IF] + CODE 0<> + SUB #1,R14 + SUBC R14,R14 + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0< + [IF] + CODE 0< +BW1 ADD R14,R14 + SUBC R14,R14 + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + + [UNDEFINED] S>D + [IF] + : S>D + DUP 0< + ; + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + + CODE U< + SUB @R15+,R14 + U< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE U> + SUB @R15+,R14 + U< ?GOTO BW1 +FW1 AND #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] < + [IF] + + CODE < + SUB @R15+,R14 + S< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE > + SUB @R15+,R14 + S< ?GOTO BW1 +FW1 AND #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN + [IF] + + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] J + [IF] + CODE J + SUB #2,R15 + MOV R14,0(R15) + MOV 4(R1),R14 + SUB 6(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] UNLOOP + [IF] + CODE UNLOOP + ADD #4,R1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] LEAVE + [IF] + CODE LEAVE + MOV &$1DC8,R10 + MOV #UNLOOP,0(R10) + MOV #$40B2,2(R10) + ADD #6,&$1DC8 + ADD #2,&$1C00 + ADD #4,R10 + MOV &$1C00,R9 + MOV R10,0(R9) + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] AND + [IF] + CODE AND + AND @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OR + [IF] + CODE OR + BIS @R15+,R14 + AND #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] XOR + [IF] + CODE XOR + XOR @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] INVERT + [IF] + CODE INVERT + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] NEGATE + [IF] + CODE NEGATE + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ABS + [IF] + CODE ABS + CMP #0,R14 + 0>= IF + MOV @R13+,R0 + THEN + MOV #NEGATE,R0 + ENDCODE + [THEN] + + [UNDEFINED] LSHIFT + [IF] + CODE LSHIFT + MOV @R15+,R10 + AND #$1F,R14 + 0<> IF + BEGIN + ADD R10,R10 + SUB #1,R14 + 0= UNTIL + THEN + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] RSHIFT + [IF] + CODE RSHIFT + MOV @R15+,R10 + AND #$1F,R14 + 0<> IF + BEGIN + BIC #1,R2 + RRC R10 + SUB #1,R14 + 0= UNTIL + THEN + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2* + [IF] + CODE 2* + ADD R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + RST_SET + + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + + $180E 1 TSTBIT + RST_RET + + [IF] + CODE UM* + MOV @R15,&$4C0 +BW1 MOV R14,&$4C8 + MOV &$4E4,0(R15) + MOV &$4E6,R14 + MOV @R13+,R0 + ENDCODE + + CODE M* + MOV @R15,&$4C2 + GOTO BW1 + ENDCODE + + [ELSE] ; MSP430FRxxxx with hardware_MPY + [UNDEFINED] M* [IF] + CODE M* + MOV @R15,R12 + CMP #0,R12 + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + THEN + XOR R14,R12 + CMP #0,R14 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + PUSHM #2,R13 + LO2HI + UM* + HI2LO + POPM #2,R13 + CMP #0,R12 + S< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + [THEN] ; endof hardware_MPY + + + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD + PUSH #DROP + MOV #$403E,R0 + ENDCODE + [THEN] + + + + $180E @ 0< ; test the switch: $8000 / SYMETRIC DIVISION + [IF] + [UNDEFINED] FM/MOD + [IF] + CODE FM/MOD + MOV R14,R12 + MOV @R15,R11 + CMP #0,R14 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + CMP #0,0(R15) + S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) + THEN + PUSHM #2,R12 + CALL #$403E + MOV @R15+,R14 + POPM #2,R12 + CMP #0,R11 + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + THEN + XOR R12,R11 + CMP #0,R11 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + + CMP #0,0(R15) + 0<> IF + CMP #1,R14 + S< IF + ADD R12,0(R15) + SUB #1,R14 + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + [ELSE] + [UNDEFINED] SM/REM + [IF] + CODE SM/REM + MOV R14,R12 + MOV @R15,R11 + CMP #0,R14 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + CMP #0,0(R15) + S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) + THEN + PUSHM #2,R12 + CALL #$403E + MOV @R15+,R14 + POPM #2,R12 + CMP #0,R11 + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + THEN + XOR R12,R11 + CMP #0,R11 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + [THEN] + + [UNDEFINED] * + [IF] + : * + M* DROP + ; + [THEN] + + [UNDEFINED] /MOD + [IF] + : /MOD + >R DUP 0< R> + [ $180E @ 0< ] + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + ; + [THEN] + + [UNDEFINED] / + [IF] + : / + >R DUP 0< R> + [ $180E @ 0< ] + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + NIP + ; + [THEN] + + [UNDEFINED] MOD + [IF] + : MOD + >R DUP 0< R> + [ $180E @ 0< ] + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + DROP + ; + [THEN] + + [UNDEFINED] */MOD + [IF] + : */MOD + >R M* R> + [ $180E @ 0< ] + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + ; + [THEN] + + [UNDEFINED] */ + [IF] + : */ + >R M* R> + [ $180E @ 0< ] + [IF] FM/MOD + [ELSE] SM/REM + [THEN] + NIP + ; + [THEN] + + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @R15,R10 + MOV R14,0(R15) + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R@ + [IF] + CODE R@ + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] TUCK + [IF] + : TUCK SWAP OVER ; + [THEN] + + [UNDEFINED] 2@ + [IF] + CODE 2@ + SUB #2,R15 + MOV 2(R14),0(R15) + MOV @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2! + [IF] + CODE 2! + MOV @R15+,0(R14) + MOV @R15+,2(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2DUP + [IF] + CODE 2DUP + MOV R14,-2(R15) + MOV @R15,-4(R15) + SUB #4,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2DROP + [IF] + CODE 2DROP + ADD #2,R15 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2SWAP + [IF] + CODE 2SWAP + MOV @R15,R10 + MOV 4(R15),0(R15) + MOV R10,4(R15) + MOV R14,R10 + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2OVER + [IF] + CODE 2OVER + SUB #4,R15 + MOV R14,2(R15) + MOV 8(R15),0(R15) + MOV 6(R15),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ALIGNED + [IF] + CODE ALIGNED + BIT #1,R14 + ADDC #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ALIGN + [IF] + CODE ALIGN + BIT #1,&$1DC8 + ADDC #0,&$1DC8 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CHARS + [IF] + CODE CHARS + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CHAR+ + [IF] + CODE CHAR+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CELLS + [IF] + CODE CELLS + ADD R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CELL+ + [IF] + CODE CELL+ + ADD #2,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CHAR + [IF] + : CHAR + $20 WORD 1+ C@ + ; + [THEN] + + [UNDEFINED] [CHAR] + [IF] + : [CHAR] + CHAR POSTPONE LITERAL + ; IMMEDIATE + [THEN] + + [UNDEFINED] +! + [IF] + CODE +! + ADD @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV R14,R10 + MOV @R15+,R8 + MOV @R15+,R9 + MOV @R15+,R14 + CMP #0,R10 + 0<> IF + CMP R9,R8 + 0<> IF + U< IF + BEGIN + MOV.B @R9+,0(R8) + ADD #1,R8 + SUB #1,R10 + 0= UNTIL + MOV @R13+,R0 + THEN + ADD R10,R8 + ADD R10,R9 + BEGIN + SUB #1,R9 + SUB #1,R8 + MOV.B @R9,0(R8) + SUB #1,R10 + 0= UNTIL + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] FILL + [IF] + CODE FILL + MOV @R15+,R9 + MOV @R15+,R10 + CMP #0,R9 + 0<> IF + BEGIN + MOV.B R14,0(R10) + ADD #1,R10 + SUB #1,R9 + 0= UNTIL + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] HEX + [IF] + CODE HEX + MOV #$10,&$1DBE + MOV @R13+,R0 + ENDCODE + [THEN] + + + [UNDEFINED] DECIMAL + [IF] + CODE DECIMAL + MOV #$0A,&$1DBE + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ( ; ) + [IF] + : ( + ')' WORD DROP + ; IMMEDIATE + [THEN] + + [UNDEFINED] .( ; " + [IF] + CODE .( ; " + MOV #0,&$1DC0 + COLON + ')' WORD + COUNT TYPE + HI2LO + MOV #$20,&$1DC0 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EXECUTE + [IF] + CODE EXECUTE + PUSH R14 + MOV @R15+,R14 + MOV @R1+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EVALUATE + [IF] + CODE EVALUATE + MOV #$1DC2,R9 + MOV @R9+,R12 + MOV @R9+,R11 + MOV @R9+,R10 + PUSHM #4,R13 + LO2HI + [ ' \ 8 + , ] + HI2LO + MOV @R1+,&$1DC6 + MOV @R1+,&$1DC4 + MOV @R1+,&$1DC2 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] RECURSE + [IF] + CODE RECURSE + MOV &$1DC8,R9 + MOV &$1DB8,0(R9) + ADD #2,&$1DC8 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] SOURCE + [IF] + CODE SOURCE + SUB #4,R15 + MOV R14,2(R15) + MOV &$1DC2,R14 + MOV &$1DC4,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] VARIABLE + [IF] + : VARIABLE + CREATE + HI2LO + MOV #$1287,-4(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] STATE + [IF] + $1DBC CONSTANT STATE + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] >IN + [IF] + $1DC6 CONSTANT >IN + [THEN] + + [UNDEFINED] PAD + [IF] + $1CE4 CONSTANT PAD + [THEN] + + [UNDEFINED] BL + [IF] + $20 CONSTANT BL + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + : SPACES + BEGIN + ?DUP + WHILE + $20 EMIT + 1- + REPEAT + ; + [THEN] + + [UNDEFINED] DEFER + [IF] + : DEFER + CREATE + HI2LO + MOV #$4030,-4(R10) + MOV #$40B4,-2(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] TO + [IF] + CODE TO + BIS #$200,R2 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] VALUE + [IF] + : VALUE + CREATE , + DOES> + HI2LO + MOV @R1+,R13 + BIT #$200,R2 + 0= IF + MOV @R14,R14 + MOV @R13+,R0 + THEN + BIC #$200,R2 + MOV #!,R0 + ENDCODE + [THEN] + + [UNDEFINED] CASE + [IF] + + : CASE 0 + ; IMMEDIATE + + : OF + 1+ + >R + POSTPONE OVER POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + RST_SET + + ECHO +; CORE_ANS.4th for MSP_EXP430FR5994 is loaded + diff --git a/MSP430-FORTH/SD_430FR5994/DOUBLE.4TH b/MSP430-FORTH/SD_430FR5994/DOUBLE.4TH new file mode 100644 index 0000000..e292dbe --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/DOUBLE.4TH @@ -0,0 +1,1566 @@ + + CODE ABORT_DOUBLE + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$80,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with DOUBLE_INPUT addon !" + RST_RET + ; + + ABORT_DOUBLE + +; ----------------------------------------------------- +; DOUBLE.4th for MSP_EXP430FR5994 +; ----------------------------------------------------- + + MARKER {DOUBLE} + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0< + [IF] + CODE 0< + ADD R14,R14 + SUBC R14,R14 + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] NIP + [IF] + CODE NIP + ADD #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD + PUSH #DROP + MOV #$403E,R0 + ENDCODE + [THEN] + + $180E @ 0< ; test the switch: $8000 / SYMETRIC DIVISION + [IF] ; $8000 DIVISION + [UNDEFINED] FM/MOD + [IF] + CODE FM/MOD + MOV R14,R12 + MOV @R15,R11 + CMP #0,R14 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + CMP #0,0(R15) + S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) + THEN + PUSHM #3,R13 + LO2HI + UM/MOD + HI2LO + POPM #3,R13 + CMP #0,R11 + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + THEN + XOR R12,R11 + CMP #0,R11 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + + CMP #0,0(R15) + 0<> IF + CMP #1,R14 + S< IF + ADD R12,0(R15) + SUB #1,R14 + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [ELSE] ; SYMETRIC DIVISION + [UNDEFINED] SM/REM + [IF] + CODE SM/REM + MOV R14,R12 + MOV @R15,R11 + CMP #0,R14 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + CMP #0,0(R15) + S< IF + XOR #-1,2(R15) + XOR #-1,0(R15) + ADD #1,2(R15) + ADDC #0,0(R15) + THEN + PUSHM #3,R13 + LO2HI + UM/MOD + HI2LO + POPM #3,R13 + CMP #0,R11 + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + THEN + XOR R12,R11 + CMP #0,R11 + S< IF + XOR #-1,R14 + ADD #1,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + [THEN] + + [UNDEFINED] / + [IF] + : / + >R DUP 0< R> + [ $180E @ 0< ] [IF] + FM/MOD + [ELSE] + SM/REM + [THEN] + NIP + ; + [THEN] + + [UNDEFINED] @ + [IF] + CODE @ + MOV @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ! + [IF] + CODE ! + MOV @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @R15,R10 + MOV R14,0(R15) + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] < + [IF] + CODE < + SUB @R15+,R14 + S< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE > + SUB @R15+,R14 + S< ?GOTO BW1 +FW1 AND #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] TO + [IF] + CODE TO + BIS #$200,R2 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DOES> + [IF] + CODE DOES> + MOV &$1DB8,R10 + MOV #$1285,0(R10) + MOV R13,2(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2@ + [IF] + CODE 2@ + SUB #2,R15 + MOV 2(R14),0(R15) + MOV @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2! + [IF] + CODE 2! + MOV @R15+,0(R14) + MOV @R15+,2(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2DUP + [IF] + CODE 2DUP + SUB #4,R15 + MOV R14,2(R15) + MOV 4(R15),0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2DROP + [IF] + CODE 2DROP + ADD #2,R15 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2SWAP + [IF] + CODE 2SWAP + MOV @R15,R10 + MOV 4(R15),0(R15) + MOV R10,4(R15) + MOV R14,R10 + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2OVER + [IF] + CODE 2OVER + SUB #4,R15 + MOV R14,2(R15) + MOV 8(R15),0(R15) + MOV 6(R15),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2>R + [IF] + CODE 2>R + PUSH @R15+ + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2R@ + [IF] + CODE 2R@ + SUB #4,R15 + MOV R14,2(R15) + MOV @R1,R14 + MOV 2(R1),0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2R> + [IF] + CODE 2R> + SUB #4,R15 + MOV R14,2(R15) + MOV @R1+,R14 + MOV @R1+,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + + [UNDEFINED] D. + [IF] + CODE D. + MOV R14,R12 + MOV #U.+10,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2ROT + [IF] + CODE 2ROT + MOV 8(R15),R9 + MOV 6(R15),R8 + MOV 4(R15),8(R15) + MOV 2(R15),6(R15) + MOV @R15,4(R15) + MOV R14,2(R15) + MOV R9,0(R15) + MOV R8,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D>S + [IF] + CODE D>S + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D0= + [IF] + CODE D0= + CMP #0,R14 + MOV #0,R14 + 0= IF + CMP #0,0(R15) + 0= IF + MOV #-1,R14 + THEN + THEN + ADD #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D0< + [IF] + CODE D0< + CMP #0,R14 + MOV #0,R14 + S< IF + MOV #-1,R14 + THEN + ADD #2,R15 + AND #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D= + [IF] + CODE D= + CMP R14,2(R15) + MOV #0,R14 + 0= IF + CMP @R15,4(R15) + 0= IF + MOV #-1,R14 + THEN + THEN + ADD #6,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D< + [IF] + CODE D< + CMP R14,2(R15) + MOV #0,R14 + S< IF + MOV #-1,R14 + THEN + 0= IF + CMP @R15,4(R15) + U< IF + MOV #-1,R14 + THEN + THEN + ADD #6,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DU< + [IF] + CODE DU< + CMP R14,2(R15) + MOV #0,R14 + U< IF + MOV #-1,R14 + THEN + 0= IF + CMP @R15,4(R15) + U< IF + MOV #-1,R14 + THEN + THEN + ADD #6,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D+ + [IF] + CODE D+ +BW1 ADD @R15+,2(R15) + ADDC @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE M+ + SUB #2,R15 + CMP #0,R14 + MOV R14,0(R15) + MOV #-1,R14 + 0>= IF + MOV #0,R14 + THEN + GOTO BW1 + ENDCODE + [THEN] + + [UNDEFINED] D- + [IF] + CODE D- + SUB @R15+,2(R15) + SUBC R14,0(R15) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DNEGATE + [IF] + CODE DNEGATE + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DABS + [IF] + CODE DABS + CMP #0,R14 + 0>= IF + MOV @R13+,R0 + THEN + MOV #DNEGATE,R0 + ENDCODE + [THEN] + + [UNDEFINED] D2/ + [IF] + CODE D2/ + RRA R14 + RRC 0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D2* + [IF] + CODE D2* + ADD @R15,0(R15) + ADDC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DMAX + [IF] + : DMAX + 2OVER 2OVER + D< IF + 2>R 2DROP 2R> + ELSE + 2DROP + THEN + ; + [THEN] + + [UNDEFINED] DMIN + [IF] + : DMIN + 2OVER 2OVER + D< IF + 2DROP + ELSE + 2>R 2DROP 2R> + THEN + ; + [THEN] + + RST_SET + + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + + $180E 1 TSTBIT + + RST_RET + + [IF] ; MSP430FRxxxx with hardware_MPY + + [UNDEFINED] M*/ + [IF] + CODE M*/ + MOV 4(R15),&$4D4 + MOV 2(R15),&$4D6 + MOV @R15+,&$4C8 + MOV R14,R11 + MOV R0,R0 + MOV &$4E4,R12 + MOV &$4E6,R14 + MOV &$4E8,R10 + MOV #0,R6 + CMP #0,R10 + S< IF + XOR #-1,R12 + XOR #-1,R14 + XOR #-1,R10 + ADD #1,R12 + ADDC #0,R14 + ADDC #0,R10 + MOV #-1,R6 + THEN + + [ELSE] ; no hardware multiplier + [UNDEFINED] M*/ + [IF] + CODE M*/ + MOV #0,R6 + CMP #0,2(R15) + S< IF + XOR #-1,4(R15) + XOR #-1,2(R15) + ADD #1,4(R15) + ADDC #0,2(R15) + MOV #-1,R6 + THEN + CMP #0,0(R15) + S< IF + XOR #-1,0(R15) + ADD #1,0(R15) + XOR #-1,R6 + THEN + MOV 4(R15),R8 + MOV 2(R15),R11 + MOV @R15+,R12 + MOV #0,R5 + MOV #0,2(R15) + MOV #0,0(R15) + MOV #0,R10 + MOV #1,R9 + BEGIN BIT R9,R12 + 0<> IF ADD R8,2(R15) + ADDC R11,0(R15) + ADDC R5,R10 + THEN ADD R8,R8 + ADDC R11,R11 + ADDC R5,R5 + ADD R9,R9 + U>= UNTIL + MOV R14,R11 + MOV @R15,R14 + MOV 2(R15),R12 + [THEN] + + [THEN] ; endcase of software/hardware_MPY + + MOV #32,R5 + CMP #0,R10 + 0= IF + MOV R14,R10 + CALL #$4050 + ELSE + CALL #$4058 + THEN + MOV @R15+,0(R15) + CMP #0,R6 + 0<> IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + CMP #0,&$180E + S< IF + CMP #0,R10 + 0<> IF + SUB #1,0(R15) + SUBC #0,R14 + THEN + THEN + THEN + MOV #$40B6,R5 + MOV #$40C4,R6 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2VARIABLE + [IF] + : 2VARIABLE + CREATE + HI2LO + ADD #4,&$1DC8 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2CONSTANT + [IF] + : 2CONSTANT + CREATE + , , + DOES> + 2@ + ; + [THEN] + + [UNDEFINED] 2VALUE + [IF] + : 2VALUE + CREATE , , + DOES> + HI2LO + MOV @R1+,R13 + BIT #$200,R2 + 0= IF + MOV #2@,R0 + THEN + BIC #$200,R2 + MOV #2!,R0 + ENDCODE + [THEN] + + + [UNDEFINED] 2LITERAL + [IF] + CODE 2LITERAL + BIS #$200,R2 + MOV #LITERAL,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] D.R + [IF] + : D.R + >R SWAP OVER DABS <# #S ROT SIGN #> + R> OVER - SPACES TYPE + ; + [THEN] + + RST_SET + +; Complement to pass DOUBLE TESTS + + [UNDEFINED] VARIABLE + [IF] + : VARIABLE + CREATE + HI2LO + MOV #$1287,-4(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CELLS + [IF] + CODE CELLS + ADD R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV R14,-2(R15) + MOV #$1C80,R14 + SUB R15,R14 + RRA R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DO + [IF] + + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SOURCE + [IF] + CODE SOURCE + SUB #4,R15 + MOV R14,2(R15) + MOV &$1DC2,R14 + MOV &$1DC4,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >IN + [IF] + $1DC6 CONSTANT >IN + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CHAR + [IF] + : CHAR + $20 WORD 1+ C@ + ; + [THEN] + + [UNDEFINED] [CHAR] + [IF] + : [CHAR] + CHAR POSTPONE LITERAL + ; IMMEDIATE + [THEN] + + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] INVERT + [IF] + CODE INVERT + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] RSHIFT + [IF] + CODE RSHIFT + MOV @R15+,R10 + AND #$1F,R14 + 0<> IF + BEGIN + BIC #1,R2 + RRC R10 + SUB #1,R14 + 0= UNTIL + THEN + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] S>D + [IF] + : S>D + DUP 0< + ; + [THEN] + + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] NEGATE + [IF] + CODE NEGATE + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #$4032,R0 + ENDCODE + [THEN] + + [UNDEFINED] CHARS + [IF] + CODE CHARS + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV R14,R10 + MOV @R15+,R8 + MOV @R15+,R9 + MOV @R15+,R14 + CMP #0,R10 + 0<> IF + CMP R9,R8 + 0<> IF + U< IF + BEGIN + MOV.B @R9+,0(R8) + ADD #1,R8 + SUB #1,R10 + 0= UNTIL + MOV @R13+,R0 + THEN + ADD R10,R8 + ADD R10,R9 + BEGIN + SUB #1,R9 + SUB #1,R8 + MOV.B @R9,0(R8) + SUB #1,R10 + 0= UNTIL + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DECIMAL + [IF] + CODE DECIMAL + MOV #$0A,&$1DBE + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] ( ; ) + [IF] + : ( + ')' WORD DROP + ; IMMEDIATE + [THEN] + + [UNDEFINED] .( ; " + [IF] + CODE .( ; " + MOV #0,&$1DC0 + COLON + ')' WORD + COUNT TYPE + $20 $1DC0 ! + ; IMMEDIATE + [THEN] + + [UNDEFINED] CR + [IF] + DEFER CR + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + + 0 CONSTANT FALSE +-1 CONSTANT TRUE + +VARIABLE VERBOSE + FALSE VERBOSE ! + +VARIABLE ACTUAL-DEPTH +CREATE ACTUAL-RESULTS 20 CELLS ALLOT + +: T{ + ; + +: -> + DEPTH DUP ACTUAL-DEPTH ! + ?DUP IF + 0 DO ACTUAL-RESULTS I CELLS + ! LOOP + THEN ; + +: }T + + DEPTH ACTUAL-DEPTH @ = IF + DEPTH ?DUP IF + 0 DO + ACTUAL-RESULTS I CELLS + @ + = 0= IF TRUE ABORT" INCORRECT RESULT" THEN + LOOP + THEN + ELSE + TRUE ABORT" WRONG NUMBER OF RESULTS" + THEN ; + +: TESTING + SOURCE VERBOSE @ + IF DUP >R TYPE CR R> >IN ! + ELSE >IN ! DROP [CHAR] * EMIT + THEN ; + + +DECIMAL + +0 INVERT CONSTANT 1SD +1SD 1 RSHIFT CONSTANT MAX-INTD +MAX-INTD INVERT CONSTANT MIN-INTD +MAX-INTD 2/ CONSTANT HI-INT +MIN-INTD 2/ CONSTANT LO-INT + + +ECHO + +TESTING interpreter and compiler reading double numbers, with/without prefixes + +T{ 1. -> 1 0 }T +T{ -2. -> -2 -1 }T +T{ : RDL1 3. ; RDL1 -> 3 0 }T +T{ : RDL2 -4. ; RDL2 -> -4 -1 }T + +VARIABLE OLD-DBASE +DECIMAL BASE @ OLD-DBASE ! +T{ #12346789. -> 12346789. }T +T{ #-12346789. -> -12346789. }T +T{ $12aBcDeF. -> 313249263. }T +T{ $-12AbCdEf. -> -313249263. }T +T{ %10010110. -> 150. }T +T{ %-10010110. -> -150. }T +T{ BASE @ OLD-DBASE @ = -> TRUE }T + +16 OLD-DBASE ! 16 BASE ! +T{ #12346789. -> BC65A5. }T +T{ #-12346789. -> -BC65A5. }T +T{ $12aBcDeF. -> 12AbCdeF. }T +T{ $-12AbCdEf. -> -12ABCDef. }T +T{ %10010110. -> 96. }T +T{ %-10010110. -> -96. }T +T{ BASE @ OLD-DBASE @ = -> TRUE }T + +DECIMAL +T{ : dnmp #8327. $-2cbe. %011010111. ; dnmp -> 8327. -11454. 215. }T + +TESTING 2CONSTANT + +T{ 1 2 2CONSTANT 2C1 -> }T +T{ 2C1 -> 1 2 }T +T{ : CD1 2C1 ; -> }T +T{ CD1 -> 1 2 }T +T{ : CD2 2CONSTANT ; -> }T +T{ -1 -2 CD2 2C2 -> }T +T{ 2C2 -> -1 -2 }T +T{ 4 5 2CONSTANT 2C3 IMMEDIATE 2C3 -> 4 5 }T +T{ : CD6 2C3 2LITERAL ; CD6 -> 4 5 }T + + +1SD MAX-INTD 2CONSTANT MAX-2INT +0 MIN-INTD 2CONSTANT MIN-2INT +MAX-2INT 2/ 2CONSTANT HI-2INT +MIN-2INT 2/ 2CONSTANT LO-2INT + +TESTING DNEGATE + +T{ 0. DNEGATE -> 0. }T +T{ 1. DNEGATE -> -1. }T +T{ -1. DNEGATE -> 1. }T +T{ MAX-2INT DNEGATE -> MIN-2INT SWAP 1+ SWAP }T +T{ MIN-2INT SWAP 1+ SWAP DNEGATE -> MAX-2INT }T + +TESTING D+ with small integers + +T{ 0. 5. D+ -> 5. }T +T{ -5. 0. D+ -> -5. }T +T{ 1. 2. D+ -> 3. }T +T{ 1. -2. D+ -> -1. }T +T{ -1. 2. D+ -> 1. }T +T{ -1. -2. D+ -> -3. }T +T{ -1. 1. D+ -> 0. }T + +TESTING D+ with mid range integers + +T{ 0 0 0 5 D+ -> 0 5 }T +T{ -1 5 0 0 D+ -> -1 5 }T +T{ 0 0 0 -5 D+ -> 0 -5 }T +T{ 0 -5 -1 0 D+ -> -1 -5 }T +T{ 0 1 0 2 D+ -> 0 3 }T +T{ -1 1 0 -2 D+ -> -1 -1 }T +T{ 0 -1 0 2 D+ -> 0 1 }T +T{ 0 -1 -1 -2 D+ -> -1 -3 }T +T{ -1 -1 0 1 D+ -> -1 0 }T +T{ MIN-INTD 0 2DUP D+ -> 0 1 }T +T{ MIN-INTD S>D MIN-INTD 0 D+ -> 0 0 }T + +TESTING D+ with large double integers + +T{ HI-2INT 1. D+ -> 0 HI-INT 1+ }T +T{ HI-2INT 2DUP D+ -> 1SD 1- MAX-INTD }T +T{ MAX-2INT MIN-2INT D+ -> -1. }T +T{ MAX-2INT LO-2INT D+ -> HI-2INT }T +T{ HI-2INT MIN-2INT D+ 1. D+ -> LO-2INT }T +T{ LO-2INT 2DUP D+ -> MIN-2INT }T + +TESTING D- with small integers + +T{ 0. 5. D- -> -5. }T +T{ 5. 0. D- -> 5. }T +T{ 0. -5. D- -> 5. }T +T{ 1. 2. D- -> -1. }T +T{ 1. -2. D- -> 3. }T +T{ -1. 2. D- -> -3. }T +T{ -1. -2. D- -> 1. }T +T{ -1. -1. D- -> 0. }T + +TESTING D- with mid-range integers + +T{ 0 0 0 5 D- -> 0 -5 }T +T{ -1 5 0 0 D- -> -1 5 }T +T{ 0 0 -1 -5 D- -> 1 4 }T +T{ 0 -5 0 0 D- -> 0 -5 }T +T{ -1 1 0 2 D- -> -1 -1 }T +T{ 0 1 -1 -2 D- -> 1 2 }T +T{ 0 -1 0 2 D- -> 0 -3 }T +T{ 0 -1 0 -2 D- -> 0 1 }T +T{ 0 0 0 1 D- -> 0 -1 }T +T{ MIN-INTD 0 2DUP D- -> 0. }T +T{ MIN-INTD S>D MAX-INTD 0 D- -> 1 1SD }T + +TESTING D- with large integers + +T{ MAX-2INT MAX-2INT D- -> 0. }T +T{ MIN-2INT MIN-2INT D- -> 0. }T +T{ MAX-2INT HI-2INT D- -> LO-2INT DNEGATE }T +T{ HI-2INT LO-2INT D- -> MAX-2INT }T +T{ LO-2INT HI-2INT D- -> MIN-2INT 1. D+ }T +T{ MIN-2INT MIN-2INT D- -> 0. }T +T{ MIN-2INT LO-2INT D- -> LO-2INT }T + +TESTING D0< D0= + +T{ 0. D0< -> FALSE }T +T{ 1. D0< -> FALSE }T +T{ MIN-INTD 0 D0< -> FALSE }T +T{ 0 MAX-INTD D0< -> FALSE }T +T{ MAX-2INT D0< -> FALSE }T +T{ -1. D0< -> TRUE }T +T{ MIN-2INT D0< -> TRUE }T + +T{ 1. D0= -> FALSE }T +T{ MIN-INTD 0 D0= -> FALSE }T +T{ MAX-2INT D0= -> FALSE }T +T{ -1 MAX-INTD D0= -> FALSE }T +T{ 0. D0= -> TRUE }T +T{ -1. D0= -> FALSE }T +T{ 0 MIN-INTD D0= -> FALSE }T + +TESTING D2* D2/ + +T{ 0. D2* -> 0. D2* }T +T{ MIN-INTD 0 D2* -> 0 1 }T +T{ HI-2INT D2* -> MAX-2INT 1. D- }T +T{ LO-2INT D2* -> MIN-2INT }T + +T{ 0. D2/ -> 0. }T +T{ 1. D2/ -> 0. }T +T{ 0 1 D2/ -> MIN-INTD 0 }T +T{ MAX-2INT D2/ -> HI-2INT }T +T{ -1. D2/ -> -1. }T +T{ MIN-2INT D2/ -> LO-2INT }T + +TESTING D< D= + +T{ 0. 1. D< -> TRUE }T +T{ 0. 0. D< -> FALSE }T +T{ 1. 0. D< -> FALSE }T +T{ -1. 1. D< -> TRUE }T +T{ -1. 0. D< -> TRUE }T +T{ -2. -1. D< -> TRUE }T +T{ -1. -2. D< -> FALSE }T +T{ 0 1 1. D< -> FALSE }T +T{ 1. 0 1 D< -> TRUE }T +T{ 0 -1 1 -2 D< -> FALSE }T +T{ 1 -2 0 -1 D< -> TRUE }T +T{ -1. MAX-2INT D< -> TRUE }T +T{ MIN-2INT MAX-2INT D< -> TRUE }T +T{ MAX-2INT -1. D< -> FALSE }T +T{ MAX-2INT MIN-2INT D< -> FALSE }T +T{ MAX-2INT 2DUP -1. D+ D< -> FALSE }T +T{ MIN-2INT 2DUP 1. D+ D< -> TRUE }T +T{ MAX-INTD S>D 2DUP 1. D+ D< -> TRUE }T + +T{ -1. -1. D= -> TRUE }T +T{ -1. 0. D= -> FALSE }T +T{ -1. 1. D= -> FALSE }T +T{ 0. -1. D= -> FALSE }T +T{ 0. 0. D= -> TRUE }T +T{ 0. 1. D= -> FALSE }T +T{ 1. -1. D= -> FALSE }T +T{ 1. 0. D= -> FALSE }T +T{ 1. 1. D= -> TRUE }T + +T{ 0 -1 0 -1 D= -> TRUE }T +T{ 0 -1 0 0 D= -> FALSE }T +T{ 0 -1 0 1 D= -> FALSE }T +T{ 0 0 0 -1 D= -> FALSE }T +T{ 0 0 0 0 D= -> TRUE }T +T{ 0 0 0 1 D= -> FALSE }T +T{ 0 1 0 -1 D= -> FALSE }T +T{ 0 1 0 0 D= -> FALSE }T +T{ 0 1 0 1 D= -> TRUE }T + +T{ MAX-2INT MIN-2INT D= -> FALSE }T +T{ MAX-2INT 0. D= -> FALSE }T +T{ MAX-2INT MAX-2INT D= -> TRUE }T +T{ MAX-2INT HI-2INT D= -> FALSE }T +T{ MAX-2INT MIN-2INT D= -> FALSE }T +T{ MIN-2INT MIN-2INT D= -> TRUE }T +T{ MIN-2INT LO-2INT D= -> FALSE }T +T{ MIN-2INT MAX-2INT D= -> FALSE }T + +TESTING 2LITERAL 2VARIABLE + +T{ : CD3 [ MAX-2INT ] 2LITERAL ; -> }T +T{ CD3 -> MAX-2INT }T +T{ 2VARIABLE 2V1 -> }T +T{ 0. 2V1 2! -> }T +T{ 2V1 2@ -> 0. }T +T{ -1 -2 2V1 2! -> }T +T{ 2V1 2@ -> -1 -2 }T +T{ : CD4 2VARIABLE ; -> }T +T{ CD4 2V2 -> }T +T{ : CD5 2V2 2! ; -> }T +T{ -2 -1 CD5 -> }T +T{ 2V2 2@ -> -2 -1 }T +T{ 2VARIABLE 2V3 IMMEDIATE 5 6 2V3 2! -> }T +T{ 2V3 2@ -> 5 6 }T +T{ : CD7 2V3 [ 2@ ] 2LITERAL ; CD7 -> 5 6 }T +T{ : CD8 [ 6 7 ] 2V3 [ 2! ] ; 2V3 2@ -> 6 7 }T + +TESTING DMAX DMIN + +T{ 1. 2. DMAX -> 2. }T +T{ 1. 0. DMAX -> 1. }T +T{ 1. -1. DMAX -> 1. }T +T{ 1. 1. DMAX -> 1. }T +T{ 0. 1. DMAX -> 1. }T +T{ 0. -1. DMAX -> 0. }T +T{ -1. 1. DMAX -> 1. }T +T{ -1. -2. DMAX -> -1. }T + +T{ MAX-2INT HI-2INT DMAX -> MAX-2INT }T +T{ MAX-2INT MIN-2INT DMAX -> MAX-2INT }T +T{ MIN-2INT MAX-2INT DMAX -> MAX-2INT }T +T{ MIN-2INT LO-2INT DMAX -> LO-2INT }T + +T{ MAX-2INT 1. DMAX -> MAX-2INT }T +T{ MAX-2INT -1. DMAX -> MAX-2INT }T +T{ MIN-2INT 1. DMAX -> 1. }T +T{ MIN-2INT -1. DMAX -> -1. }T + + +T{ 1. 2. DMIN -> 1. }T +T{ 1. 0. DMIN -> 0. }T +T{ 1. -1. DMIN -> -1. }T +T{ 1. 1. DMIN -> 1. }T +T{ 0. 1. DMIN -> 0. }T +T{ 0. -1. DMIN -> -1. }T +T{ -1. 1. DMIN -> -1. }T +T{ -1. -2. DMIN -> -2. }T + +T{ MAX-2INT HI-2INT DMIN -> HI-2INT }T +T{ MAX-2INT MIN-2INT DMIN -> MIN-2INT }T +T{ MIN-2INT MAX-2INT DMIN -> MIN-2INT }T +T{ MIN-2INT LO-2INT DMIN -> MIN-2INT }T + +T{ MAX-2INT 1. DMIN -> 1. }T +T{ MAX-2INT -1. DMIN -> -1. }T +T{ MIN-2INT 1. DMIN -> MIN-2INT }T +T{ MIN-2INT -1. DMIN -> MIN-2INT }T + +TESTING D>S DABS + +T{ 1234 0 D>S -> 1234 }T +T{ -1234 -1 D>S -> -1234 }T +T{ MAX-INTD 0 D>S -> MAX-INTD }T +T{ MIN-INTD -1 D>S -> MIN-INTD }T + +T{ 1. DABS -> 1. }T +T{ -1. DABS -> 1. }T +T{ MAX-2INT DABS -> MAX-2INT }T +T{ MIN-2INT 1. D+ DABS -> MAX-2INT }T + +TESTING M+ M*/ + +T{ HI-2INT 1 M+ -> HI-2INT 1. D+ }T +T{ MAX-2INT -1 M+ -> MAX-2INT -1. D+ }T +T{ MIN-2INT 1 M+ -> MIN-2INT 1. D+ }T +T{ LO-2INT -1 M+ -> LO-2INT -1. D+ }T + + +: ?$8000 [ -3 2 / -2 = ] LITERAL IF 1. D- THEN ; + +T{ 5. 7 11 M*/ -> 3. }T +T{ 5. -7 11 M*/ -> -3. ?$8000 }T +T{ -5. 7 11 M*/ -> -3. ?$8000 }T +T{ -5. -7 11 M*/ -> 3. }T +T{ MAX-2INT 8 16 M*/ -> HI-2INT }T +T{ MAX-2INT -8 16 M*/ -> HI-2INT DNEGATE ?$8000 }T +T{ MIN-2INT 8 16 M*/ -> LO-2INT }T +T{ MIN-2INT -8 16 M*/ -> LO-2INT DNEGATE }T +T{ MAX-2INT MAX-INTD MAX-INTD M*/ -> MAX-2INT }T +T{ MAX-2INT MAX-INTD 2/ MAX-INTD M*/ -> MAX-INTD 1- HI-2INT NIP }T +T{ MIN-2INT LO-2INT NIP 1+ DUP 1- NEGATE M*/ -> 0 MAX-INTD 1- }T +T{ MIN-2INT LO-2INT NIP 1- MAX-INTD M*/ -> MIN-INTD 3 + HI-2INT NIP 2 + }T +T{ MAX-2INT LO-2INT NIP DUP NEGATE M*/ -> MAX-2INT DNEGATE }T +T{ MIN-2INT MAX-INTD DUP M*/ -> MIN-2INT }T + +TESTING D. D.R + +MAX-2INT 71 73 M*/ 2CONSTANT DBL1 +MIN-2INT 73 79 M*/ 2CONSTANT DBL2 + +: D>ASCII ( D -- CADDR U ) + DUP >R <# DABS #S R> SIGN #> ( -- CADDR1 U ) + HERE SWAP 2DUP 2>R CHARS DUP ALLOT MOVE 2R> +; + +DBL1 D>ASCII 2CONSTANT "DBL1" +DBL2 D>ASCII 2CONSTANT "DBL2" + +: DOUBLEOUTPUT + CR ." You should see lines duplicated:" CR + 5 SPACES "DBL1" TYPE CR + 5 SPACES DBL1 D. CR + 8 SPACES "DBL1" DUP >R TYPE CR + 5 SPACES DBL1 R> 3 + D.R CR + 5 SPACES "DBL2" TYPE CR + 5 SPACES DBL2 D. CR + 10 SPACES "DBL2" DUP >R TYPE CR + 5 SPACES DBL2 R> 5 + D.R CR +; + +T{ DOUBLEOUTPUT -> }T + +TESTING 2ROT DU< (Double Number extension words) + +T{ 1. 2. 3. 2ROT -> 2. 3. 1. }T +T{ MAX-2INT MIN-2INT 1. 2ROT -> MIN-2INT 1. MAX-2INT }T + +T{ 1. 1. DU< -> FALSE }T +T{ 1. -1. DU< -> TRUE }T +T{ -1. 1. DU< -> FALSE }T +T{ -1. -2. DU< -> FALSE }T +T{ 0 1 1. DU< -> FALSE }T +T{ 1. 0 1 DU< -> TRUE }T +T{ 0 -1 1 -2 DU< -> FALSE }T +T{ 1 -2 0 -1 DU< -> TRUE }T + +T{ MAX-2INT HI-2INT DU< -> FALSE }T +T{ HI-2INT MAX-2INT DU< -> TRUE }T +T{ MAX-2INT MIN-2INT DU< -> TRUE }T +T{ MIN-2INT MAX-2INT DU< -> FALSE }T +T{ MIN-2INT LO-2INT DU< -> TRUE }T + +TESTING 2VALUE + +T{ 1111 2222 2VALUE 2VAL -> }T +T{ 2VAL -> 1111 2222 }T +T{ 3333 4444 TO 2VAL -> }T +T{ 2VAL -> 3333 4444 }T +T{ : TO-2VAL TO 2VAL ; 5555 6666 TO-2VAL -> }T +T{ 2VAL -> 5555 6666 }T + + +CR .( End of Double-Number word tests) CR diff --git a/MSP430-FORTH/SD_430FR5994/FF_SPECS.4TH b/MSP430-FORTH/SD_430FR5994/FF_SPECS.4TH new file mode 100644 index 0000000..f08f9a4 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/FF_SPECS.4TH @@ -0,0 +1,674 @@ + +; --------------------------------- +; FF_SPECS.4th for MSP_EXP430FR5994 +; --------------------------------- + + CODE ABORT_FF_SPECS + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_FF_SPECS + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @R15,R10 + MOV R14,0(R15) + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0< + [IF] + CODE 0< + ADD R14,R14 + SUBC R14,R14 + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + CODE U< + SUB @R15+,R14 + U< ?GOTO FW1 + 0<> IF +BW1 MOV #-1,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE U> + SUB @R15+,R14 + U< ?GOTO BW1 +FW1 AND #0,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN + [IF] + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] WHILE + [IF] + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + [THEN] + + [UNDEFINED] REPEAT + [IF] + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #$4032,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2* + [IF] + CODE 2* + ADD R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD + PUSH #DROP + MOV #$403E,R0 + ENDCODE + [THEN] + + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV R14,R10 + MOV @R15+,R8 + MOV @R15+,R9 + MOV @R15+,R14 + CMP #0,R10 + 0<> IF + CMP R9,R8 + 0<> IF + U< IF + BEGIN + MOV.B @R9+,0(R8) + ADD #1,R8 + SUB #1,R10 + 0= UNTIL + MOV @R13+,R0 + THEN + ADD R10,R8 + ADD R10,R9 + BEGIN + SUB #1,R9 + SUB #1,R8 + MOV.B @R9,0(R8) + SUB #1,R10 + 0= UNTIL + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + + [THEN] + + : WORDS + $1CE4 + $180C @ 2* + MOVE + BEGIN + 0 DUP + $180C @ 2* 0 + DO + DUP I $1CE4 + @ + U< IF + DROP DROP + I DUP $1CE4 + @ + THEN + 2 +LOOP + ?DUP + WHILE + DUP + 2 - @ + ROT + $1CE4 + + ! + COUNT 2/ + DUP >R TYPE + $10 R> - SPACES + REPEAT + DROP + ; + + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE + + : OF + 1+ + >R + POSTPONE OVER + POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + [UNDEFINED] S_ + [IF] + CODE S_ + MOV #0,&$1DC0 + COLON + $401E , + $20 WORD + HI2LO + MOV.B @R14,R14 + ADD #1,R14 + BIT #1,R14 + ADDC R14,&$1DC8 + MOV @R15+,R14 + MOV @R1+,R13 + MOV #$20,&$1DC0 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC + [IF] + CODE ESC + CMP #0,&$1DBC + 0= IF MOV @R13+,R0 + THEN + COLON + $1B + POSTPONE LITERAL + POSTPONE EMIT + POSTPONE S_ + POSTPONE TYPE + ; IMMEDIATE + [THEN] + + [DEFINED] FORTH + [IF] + CODE BODY>SQNFA + SUB #2,R15 + SUB #4,R14 + MOV R14,R8 + MOV R8,R9 + BEGIN + SUB #2,R9 + MOV R9,0(R15) + MOV.B @R9+,R14 + RRA R14 + MOV R14,R10 + BIT #1,R10 + 0= IF + ADD #1,R10 + THEN + ADD R9,R10 + CMP R10,R8 + 0<> WHILE + MOV @R15,R9 + REPEAT + MOV R9,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + : SPECS + RST_RET + ECHO + ESC [8;42;80t + + ESC [7m + CR ." FastForth V" + $180A @ + 0 <# # $08 HOLD # '.' HOLD #S #> TYPE + ." for MSP430FR" + HERE + $1A04 @ + CASE + + $8102 OF ." 5738," $C200 ENDOF + $8103 OF ." 5739," $C200 ENDOF + $810D OF ." 5986," $4400 ENDOF + $8160 OF ." 5948," $4400 ENDOF + $8169 OF ." 5969," $4400 ENDOF + $81A8 OF ." 6989," $4400 ENDOF + $81F0 OF ." 4133," $C400 ENDOF + $8240 OF ." 2433," $C400 ENDOF + $825D OF ." 5972," $4400 ENDOF + $82A1 OF ." 5994," $4000 ENDOF + $82A6 OF ." 5962," $4000 ENDOF + $830C OF ." 2355," $8000 ENDOF + $830D OF ." 2353," $C000 ENDOF + $831E OF ." 2155," $8000 ENDOF + $831D OF ." 2153," $C000 ENDOF + $832A OF ." 2476," $8000 ENDOF + $832B OF ." 2475," $8000 ENDOF + $833C OF ." 2633," $C400 ENDOF + $833D OF ." 2533," $C400 ENDOF + ABORT" xxxx <-- unrecognized device!" + ENDCASE + ['] ['] DUP @ $1284 = + IF ." DTC=1," DROP + ELSE 2 + @ $1284 = + IF ." DTC=2," + ELSE ." DTC=3," + THEN + THEN + $20 EMIT + $180C @ U. $08 EMIT + ." -Entry word set, " + $1800 @ 0 1000 UM/MOD U. + ?DUP IF $08 EMIT ',' EMIT U. + THEN ." MHz, " + - U. ." bytes" + ESC [0m + + CR + ." /COUNTED-STRING = 255" CR + ." /HOLD = 34" CR + ." /PAD = 84" CR + ." ADDRESS-UNIT-BITS = 16" CR + ." FLOORED DIVISION = " + $180E @ + 0< IF ." true" + ELSE ." false" + THEN CR + ." MAX-CHAR = 255" CR + ." MAX-N = 32767" CR + ." MAX-U = 65535" CR + ." MAX-D = 2147483647" CR + ." MAX-UD = 4294967295" CR + ." STACK-CELLS = 48" CR + ." RETURN-STACK-CELLS= 48" CR + ." Definitions are forced to UPPERCASE." CR + + CR ESC [7m ." Kernel add-ons" ESC [0m CR + $180E @ + 2* DUP 0< IF ." 32.768kHz LF XTAL" CR THEN + 2* DUP 0< IF ." /RTS /CTS " 2* + ELSE 2* DUP + 0< IF ." /RTS " THEN + THEN + 2* DUP 0< IF ." XON/XOFF " THEN + 2* DUP 0< IF ." Half-Duplex " THEN + 2* DUP 0< IF ." I2C_Master TERMINAL" + ELSE ." UART TERMINAL" THEN CR + 2* DUP 0< IF 2* DUP 0< IF ." DOUBLE and " + THEN ." Q15.16 numbers handling" CR + ELSE 2* DUP 0< IF ." DOUBLE numbers handling" CR + THEN + THEN + 2* DUP 0< IF ." MSP430_X assembler with TI's syntax" + CR 2* 2* + ELSE + 2* DUP + 0< IF ." MSP430 Assembler" + 2* DUP + 0< IF ." , 20bits extended addresses," + THEN + ELSE 2* + THEN + ." with TI's syntax" CR + THEN DROP + [DEFINED] FORTH [IF] ." word-set management" CR + [THEN] + [DEFINED] LOAD" [IF] ." SD_CARD Load" CR + [THEN] + [DEFINED] BOOT [IF] ." SD_CARD Bootloader" CR + [THEN] + [DEFINED] READ" [IF] ." SD_CARD Read/Write" CR + [THEN] + + $1DCA + BEGIN + @ ?DUP + WHILE + DUP $180C @ 2* - + CR ESC [7m + [DEFINED] FORTH + [IF] DUP BODY>SQNFA + [ELSE] OVER @ + IF S" hidden" + ELSE S" FORTH" + THEN + [THEN] + TYPE ." word-set" + ESC [0m CR + WORDS CR + REPEAT + + CR ESC [7m ." EXTENSIONS" ESC [0m + [DEFINED] {CORE_ANS} [IF] CR ." core ANS94" + [THEN] + [DEFINED] {DOUBLE} [IF] CR ." DOUBLE word set" + [THEN] + [DEFINED] {UTILITY} [IF] CR ." UTILITY" + [THEN] + [DEFINED] {FIXPOINT} [IF] CR ." Q15.16 ADD SUB MUL DIV" + [THEN] + [DEFINED] {CORDIC} [IF] CR ." CORDIC engine" + [THEN] + [DEFINED] {SD_TOOLS} [IF] CR ." SD_TOOLS" + [THEN] + [DEFINED] {RTC} [IF] CR ." RTC utility" + [THEN] + [DEFINED] {UARTI2CS} [IF] CR ." UART to I2C_FastForth bridge" + [THEN] + CR + 0 SYS + ; + +SPECS diff --git a/MSP430-FORTH/SD_430FR5994/FIXPOINT.4TH b/MSP430-FORTH/SD_430FR5994/FIXPOINT.4TH new file mode 100644 index 0000000..ba083d7 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/FIXPOINT.4TH @@ -0,0 +1,479 @@ + + CODE ABORT_FIXPOINT + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$100,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" build FastForth with Q15.16_INPUT addon !" + RST_RET + $1B EMIT $63 EMIT + ; + + ABORT_FIXPOINT + +; ----------------------------------------------------- +; FIXPOINT.4th for MSP_EXP430FR5994 +; ----------------------------------------------------- + + MARKER {FIXPOINT} + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + CODE U< + SUB @R15+,R14 + 0<> IF + MOV #-1,R14 + U< IF + AND #0,R14 + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DABS + [IF] + CODE DABS + AND #-1,R14 + S< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] HOLDS + [IF] + CODE HOLDS + MOV @R15+,R9 +BW3 ADD R14,R9 + MOV &$1DB2,R8 + BEGIN + SUB #1,R9 + SUB #1,R14 + U>= WHILE + SUB #1,R8 + MOV.B @R9,0(R8) + REPEAT + MOV R8,&$1DB2 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE F+ + ADD @R15+,2(R15) + ADDC @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE F- + SUB @R15+,2(R15) + SUBC R14,0(R15) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + $1A00 4 + @ $81F3 U< + $81EF $1A00 4 + @ U< + = [IF] ; MSP430FR413x subfamily without hardware_MPY + + CODE UDM* + PUSH R13 + PUSHM #4,R7 + MOV 4(R15),R13 + MOV 2(R15),R11 + MOV @R15,R10 + MOV #0,R7 + MOV #0,R6 + MOV #0,4(R15) + MOV #0,2(R15) + MOV #0,R5 + MOV #0,R4 + MOV #1,R9 + MOV #0,R8 + BEGIN + CMP #0,R9 + 0<> IF + BIT R9,R10 + ELSE + BIT R8,R14 + THEN + 0<> IF + ADD R13,4(R15) + ADDC R11,2(R15) + ADDC R7,R5 + ADDC R6,R4 + THEN + ADD R13,R13 + ADDC R11,R11 + ADDC R7,R7 + ADDC R6,R6 + ADD R9,R9 + ADDC R8,R8 + U>= UNTIL + MOV R5,0(R15) + MOV R4,R14 + POPM #4,R7 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + + CODE F* + MOV 2(R15),R12 + XOR R14,R12 + BIT #$8000,2(R15) + 0<> IF + XOR #-1,2(R15) + XOR #-1,4(R15) + ADD #1,4(R15) + ADDC #0,2(R15) + THEN + COLON + DABS UDM* + HI2LO + MOV @R1+,R13 + MOV @R15+,R14 + MOV @R15+,0(R15) + AND #-1,R12 + S< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 + THEN + MOV @R13+,R0 + ENDCODE + + CODE F#S + MOV @R15,R12 + MOV #0,R11 + PUSHM #3,R13 + MOV 2(R15),0(R15) + MOV R14,2(R15) + BEGIN + MOV &$1DBE,R14 + LO2HI + UM* + HI2LO + CMP #10,R14 + U>= IF + ADD #7,R14 + THEN + ADD #$30,R14 + MOV @R1,R11 + MOV.B R14,$1D90(R11) + ADD #1,R11 + MOV R11,0(R1) + CMP 2(R15),R11 + U>= UNTIL + POPM #3,R13 + MOV R11,R14 + MOV R12,2(R15) + MOV #0,0(R15) + MOV #$1D90,R9 + GOTO BW3 + ENDCODE + + [ELSE] ; hardware multiplier + + CODE F* + MOV 4(R15),&$4D4 + MOV 2(R15),&$4D6 + MOV @R15,&$4E0 + MOV R14,&$4E2 + ADD #4,R15 + MOV &$4E6,0(R15) + MOV &$4E8,R14 + MOV @R13+,R0 + ENDCODE + + + CODE F#S + MOV 2(R15),R9 + MOV @R15,2(R15) + MOV R9,0(R15) + MOV R14,R11 + MOV #0,R12 + BEGIN + MOV @R15,&$4C0 + MOV &$1DBE,&$4C8 + MOV &$4E4,0(R15) + MOV &$4E6,R14 + CMP #10,R14 + U>= IF + ADD #7,R14 + THEN + ADD #$30,R14 + MOV.B R14,$1D90(R12) + ADD #1,R12 + CMP R11,R12 + 0= UNTIL + MOV R11,R14 + MOV #0,0(R15) + MOV #$1D90,R9 + GOTO BW3 + ENDCODE + + [THEN] ; end of hardware/software multiplier + + CODE F/ + MOV R14,R8 + MOV @R15+,R10 + MOV @R15+,R9 + MOV @R15,R11 + PUSHM #5,R9 + AND #-1,R8 + S< IF + XOR #-1,R10 + XOR #-1,R8 + ADD #1,R10 + ADDC #0,R8 + THEN + AND #-1,R9 + S< IF + XOR #-1,R11 + XOR #-1,R9 + ADD #1,R11 + ADDC #0,R9 + THEN + MOV R9,R7 + MOV R11,R9 + MOV #0,R11 + MOV #0,R6 + MOV #32,R5 +BW1 CMP R8,R6 + 0= IF + CMP R10,R7 + THEN + U>= IF + SUB R10,R7 + SUBC R8,R6 + THEN + BEGIN + ADDC R12,R12 + ADDC R14,R14 + SUB #1,R5 + U>= WHILE + ADD R11,R11 + ADDC R9,R9 + ADDC R7,R7 + ADDC R6,R6 + U< ?GOTO BW1 + SUB R10,R7 + SUBC R8,R6 + BIS #1,R2 + REPEAT + POPM #5,R9 + XOR R9,R8 + CMP #0,R8 + S< IF + XOR #-1,R12 + XOR #-1,R14 + ADD #1,R12 + ADDC #0,R14 + THEN + MOV R12,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE F. + MOV R14,R12 + MOV #4,R11 + MOV &$1DBE,R10 + CMP #$0A,R10 + 0= IF + ADD #1,R11 + ELSE + CMP #2,R10 + 0= IF + MOV #$10,R11 + THEN + THEN + PUSHM #3,R13 + LO2HI + <# DABS + R> F#S + $2C HOLD + #S + R> SIGN #> + TYPE $20 EMIT + ; + + CODE S>F + SUB #2,R15 + MOV #0,0(R15) + MOV @R13+,R0 + ENDCODE + + RST_SET + +; ----------------------- +; complement (volatile) for tests below +; ----------------------- + + [UNDEFINED] ! + [IF] + CODE ! + MOV @R15+,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DOES> + [IF] + CODE DOES> + MOV &$1DB8,R10 + MOV #$1285,0(R10) + MOV R13,2(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2CONSTANT + [IF] + : 2CONSTANT + CREATE , , + DOES> + HI2LO + SUB #2,R15 + MOV 2(R14),0(R15) + MOV @R14,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] D. + [IF] + CODE D. + MOV #U.,R10 + ADD #10,R10 + MOV R10,R0 + ENDCODE + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + ECHO + +; ----------------------- +; (volatile) tests for FIXPOINT.asm|FIXPOINT.4th for MSP_EXP430FR5994 +; ----------------------- + +3,14159 2CONSTANT PI +PI -1,0 F* 2CONSTANT -PI + +PI D. ; D. is not appropriate --> +-PI D. ; D. is not appropriate --> + +PI F. ; F. is a good choice! ---> +-PI F. ; F. is a good choice! ---> + +$10 BASE ! PI F. + -PI F. +%10 BASE ! PI F. + -PI F. +#10 BASE ! PI F. + -PI F. + + PI 2,0 F* F. + PI -2,0 F* F. +-PI 2,0 F* F. +-PI -2,0 F* F. + + PI 2,0 F/ F. + PI -2,0 F/ F. +-PI 2,0 F/ F. +-PI -2,0 F/ F. + + 32768,0 1,0 F* F. ; overflow! --> + 32768,0 1,0 F/ F. ; overflow! --> +-32768,0 -1,0 F* F. ; overflow! --> +-32768,0 -1,0 F/ F. ; overflow! --> + +32767,99999 1,0 F* F. +32767,99999 1,0 F/ F. +32767,99999 2,0 F/ F. +32767,99999 4,0 F/ F. +32767,99999 8,0 F/ F. +32767,99999 16,0 F/ F. + +-32768,0 -2,0 F/ F. +-32768,0 -4,0 F/ F. +-32768,0 -8,0 F/ F. +-32768,0 -16,0 F/ F. +-32768,0 -32,0 F/ F. +-32768,0 -64,0 F/ F. + +-3276,80 -1,0 F/ F. +-327,680 -1,0 F/ F. +-32,7680 -1,0 F/ F. +-3,27680 -1,0 F/ F. +-0,32768 -1,0 F/ F. + +; SQRT(32768)^2 = 32768 + 181,01933598375 181,01933598375 F* F. + 181,01933598375 -181,01933598375 F* F. +-181,01933598375 181,01933598375 F* F. +-181,01933598375 -181,01933598375 F* F. + +RST_RET diff --git a/MSP430-FORTH/SD_430FR5994/LAST.4TH b/MSP430-FORTH/SD_430FR5994/LAST.4TH new file mode 100644 index 0000000..b859119 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/LAST.4TH @@ -0,0 +1,505 @@ + +; ----------- +; SD_TEST.4th for MSP_EXP430FR5994 +; ----------- + + CODE ABORT_SD_TEST + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + [UNDEFINED] WRITE + [IF] + 1 ABORT" no SD_CARD_READ_WRITE addon!" + [THEN] + RST_RET + ; + + ABORT_SD_TEST + + MARKER {SD_TEST} + + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN + [IF] + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] STATE + [IF] + $1DBC CONSTANT STATE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &BASE + MOV #$10,&BASE + ADD @R15,R14 + LO2HI + SWAP + DO + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + CR + $10 +LOOP + R> BASE ! + ; + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #BEGIN,R0 + ENDCODE + [THEN] + + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE + + : OF + 1+ + >R + POSTPONE OVER + POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + CODE SD_EMIT + CMP #$200,&$201E + U>= IF + CALL &WRITE+2 + THEN + MOV &$201E,R8 + MOV.B R14,$1E00(R8) + ADD #1,&$201E + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + +: DOESWRITE + ['] SD_EMIT IS EMIT + $4000 HERE OVER - DUMP + ['] EMIT >BODY IS EMIT + CLOSE + ." , done" +; + + : SD_TEST + ECHO + $0D EMIT + ." ? Fast Forth Specifs" CR + ." 0 Set date and time" CR + ." 1 Load {UTILTY} words" CR + ." 2 Load {SD_TOOLS} words" CR + ." 3 Load {CORE_COMP} words" CR + ." 4 Load ANS core tests" CR + ." 5 Load a 10k program " CR + ." 6 Read only this source file" CR + ." 7 write FORTH dump in YOURFILE.TXT" CR + ." 8 append FORTH dump to YOURFILE.TXT" CR + ." 9 Load TST_WORDS" CR + ." your choice : " + KEY DUP EMIT CR + {SD_TEST} + CASE + '?' OF LOAD" FF_SPECS.4TH" ENDOF + '0' OF LOAD" RTC.4TH" ENDOF + '1' OF LOAD" UTILITY.4TH" ENDOF + '2' OF LOAD" SD_TOOLS.4TH" ENDOF + '3' OF LOAD" CORE_ANS.4TH" ENDOF + '4' OF LOAD" CORETEST.4TH" ENDOF + '5' OF LOAD" PROG10K.4TH" ENDOF + '6' OF READ" PROG10K.4TH" + BEGIN READ + UNTIL ." , done" ENDOF + '7' OF ECHO + WRITE" YOURFILE.TXT" + DOESWRITE ENDOF + '8' OF ECHO + APPEND" YOURFILE.TXT" + DOESWRITE ENDOF + '9' OF LOAD" TSTWORDS.4TH" ENDOF + ENDCASE + ; + + [THEN] + +SD_TEST diff --git a/MSP430-FORTH/SD_430FR5994/MISC/TESTASM.4TH b/MSP430-FORTH/SD_430FR5994/MISC/TESTASM.4TH new file mode 100644 index 0000000..2adc6a9 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/MISC/TESTASM.4TH @@ -0,0 +1,630 @@ + +; ----------------------------------------------------------------------- +; TEST_ASM.4th for MSP_EXP430FR5994 +; ----------------------------------------------------------------------- + + CODE ABORT_TEST_ASM + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_TEST_ASM + + MARKER {TEST_ASM} + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + MOV R7,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] VARIABLE + [IF] + : VARIABLE + CREATE + HI2LO + MOV #$1287,-4(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DEFER + [IF] + + : DEFER + CREATE + HI2LO + MOV #$4030,-4(R10) + MOV #$40B4,-2(R10) + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] IF + [IF] + + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH R14 + MOV @R15,R14 + MOV @R1+,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BEGIN + [IF] + + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] CR + [IF] + DEFER CR + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &BASE + MOV #$10,&$1DBE + ADD @R15,R14 + LO2HI + SWAP + DO CR + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! + ; + [THEN] + + CODE TESTPUSHM +BW1 + MOV #22222,R8 + MOV #3,R9 + MOV #2,R10 + MOV #1,R11 + MOV #0,R12 + + PUSHM #4,R13 + POPM #4,R13 + SUB #10,R15 + MOV R14,8(R15) + MOV R12,6(R15) + MOV R11,4(R15) + MOV R10,2(R15) + MOV R9,0(R15) + MOV R8,R14 + RRAM #1,R14 + RLAM #2,R14 + RRCM #1,R14 + RRUM #1,R14 + COLON + space . . . . . + ; + + TESTPUSHM ; you should see 11111 3 2 1 0 --> + + CODE TESTPOPM + GOTO BW1 + ENDCODE + + TESTPOPM ; you should see 11111 3 2 1 0 --> + + + + CODE TEST1 + + MOV &BASE,&BASE + CMP #%10,&BASE + 0<> IF MOV #2,&BASE + ELSE MOV #$0A,&BASE + THEN + COLON + BASE @ U. + ; + + + : TEST2 + BASE @ U. + HI2LO + + + CMP #2, &BASE + 0<> IF MOV #2, &BASE + ELSE MOV #10,&BASE + THEN + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + + CODE TEST3 + CMP #2, &BASE + 0<> IF MOV #2, &BASE + ELSE MOV #10,&BASE + THEN COLON + BASE @ U. + ; + + +: TEST5 + SPACE + HI2LO + SUB #2,R15 + MOV R14,0(R15) + MOV #%1010,R14 +BEGIN SUB #$0001,R14 + LO2HI + + DUP U. + HI2LO + CMP #0,R14 +0= UNTIL MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 +ENDCODE + +TEST5 ; you should see : 9 8 7 6 5 4 3 2 1 0 --> + + + +[UNDEFINED] C, [IF] +CODE C, +MOV &$1DC8,R10 +MOV.B R14,0(R10) +ADD #1,&$1DC8 +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] C@ [IF] +CODE C@ +MOV.B @R14,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +: BYTES_TABLE_IDX +CREATE +0 DO I C, +LOOP +DOES> ++ +; + +8 BYTES_TABLE_IDX BYTES_TABLE + +2 BYTES_TABLE C@ . ; you should see 2 --> + + +VARIABLE BYTES_TABLE1 + +$0201 BYTES_TABLE1 ! + +CODE IDX_TEST1 + MOV.B BYTES_TABLE1(R14),R14 +COLON + U. +; + +0 IDX_TEST1 ; you should see 1 --> + +CODE TEST6 + MOV 0(R15),0(R15) + MOV @R13+,R0 +ENDCODE + + +1 TEST6 . ; you should see 1 --> + + + + + +CREATE TABLE0 +0 C, +1 C, +2 C, +3 C, + + +CREATE TABLE10 +$10 C, +$11 C, +$12 C, +$13 C, + + + +CREATE TABLE20 +$20 C, +$21 C, +$22 C, +$23 C, + + +CREATE TABLE + + +TABLE 2 - CONSTANT PFA_TABLE + + +CODE REDIRECT ; <table> -- redirects TABLE to argument <table> +MOV R14,&PFA_TABLE +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE + + +CODE REDIRECT0 ; -- redirects TABLE to TABLE0 +MOV #TABLE0,&PFA_TABLE +MOV @R13+,R0 +ENDCODE + + +CODE REDIRECT10 ; -- redirects TABLE to TABLE10 +MOV #TABLE10,&PFA_TABLE +MOV @R13+,R0 +ENDCODE + + +CODE REDIRECT20 ; -- redirects TABLE to TABLE20 +MOV #TABLE20,&PFA_TABLE +MOV @R13+,R0 +ENDCODE + + +' TABLE0 10 DUMP + +' TABLE10 10 DUMP + +' TABLE20 10 DUMP + + +TABLE0 REDIRECT TABLE 10 DUMP + +TABLE10 REDIRECT TABLE 10 DUMP + +TABLE20 REDIRECT TABLE 10 DUMP + + +REDIRECT0 TABLE 10 DUMP + +REDIRECT10 TABLE 10 DUMP + +REDIRECT20 TABLE 10 DUMP + + +TABLE0 PFA_TABLE ! TABLE 10 DUMP + +TABLE10 PFA_TABLE ! TABLE 10 DUMP + +TABLE20 PFA_TABLE ! TABLE 10 DUMP + + + + +; ----------------------------------------------------------------------- +; create a primary DEFERred assembly word +; ----------------------------------------------------------------------- + + +DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY) + + +CODENNM ; does DUP + SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 +ENDCODE ; leaves its execution address (CFA) on stack + +DUP . + +IS TRUC ; TRUC becomes a primary DEFERred word + ; with its default action (DUP) located at its BODY addresse. + +TRUC . ; display R14 value --> + + + +' TRUC >BODY IS TRUC ; TRUC is reinitialized with its default action + + +TRUC . ; display R14 value --> + + + + + diff --git a/MSP430-FORTH/SD_430FR5994/PID.4TH b/MSP430-FORTH/SD_430FR5994/PID.4TH new file mode 100644 index 0000000..2de24fd --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/PID.4TH @@ -0,0 +1,815 @@ + + +MARKER {PID} + +[UNDEFINED] VARIABLE [IF] +: VARIABLE +CREATE +HI2LO +MOV @R1+,R13 +MOV #$1287,-4(R10) +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] CONSTANT [IF] +: CONSTANT +CREATE +HI2LO +MOV R14,-2(R10) +MOV @R15+,R14 +MOV @R1+,R13 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] STATE [IF] +$1DBC CONSTANT STATE +[THEN] + +[UNDEFINED] ROT [IF] +CODE ROT +MOV @R15,R10 +MOV R14,0(R15) +MOV 2(R15),R14 +MOV R10,2(R15) +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] SWAP [IF] +CODE SWAP +MOV @R15,R10 +MOV R14,0(R15) +MOV R10,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] DUP [IF] +CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 +ENDCODE + +CODE ?DUP +CMP #0,R14 +0<> ?GOTO BW1 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] AND [IF] +CODE AND +AND @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] SPACE [IF] +: SPACE +$20 EMIT ; +[THEN] + +[UNDEFINED] R> [IF] +CODE R> +MOV R7,R0 +ENDCODE +[THEN] + +[UNDEFINED] @ [IF] +CODE @ +MOV @R14,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] ! [IF] +CODE ! +MOV @R15+,0(R14) +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] C@ [IF] +CODE C@ +MOV.B @R14,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 1+ [IF] +CODE 1+ +ADD #1,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] + [IF] +CODE + +ADD @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] - [IF] +CODE - +SUB @R15+,R14 +XOR #-1,R14 +ADD #1,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] MAX [IF] +CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 +ENDCODE + +CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 +ENDCODE +[THEN] + + +[UNDEFINED] 2NIP [IF] +CODE 2NIP +MOV @R15,R9 +ADD #4,R15 +MOV R9,0(R15) +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2DUP [IF] +CODE 2DUP +SUB #4,R15 +MOV R14,2(R15) +MOV 4(R15),0(R15) +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2SWAP [IF] +CODE 2SWAP +MOV @R15,R10 +MOV 4(R15),0(R15) +MOV R10,4(R15) +MOV R14,R10 +MOV 2(R15),R14 +MOV R10,2(R15) +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2ROT [IF] +CODE 2ROT +MOV 8(R15),R9 +MOV 6(R15),R8 +MOV 4(R15),8(R15) +MOV 2(R15),6(R15) +MOV @R15,4(R15) +MOV R14,2(R15) +MOV R9,0(R15) +MOV R8,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2DROP [IF] +CODE 2DROP +ADD #2,R15 +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2OVER [IF] +CODE 2OVER +SUB #4,R15 +MOV R14,2(R15) +MOV 8(R15),0(R15) +MOV 6(R15),R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] DABS [IF] +CODE DABS +AND #-1,R14 +U< IF + XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 +THEN +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] 2@ [IF] + + + CODE 2@ + SUB #2,R15 + MOV 2(R14),0(R15) + MOV @R14,R14 + MOV @R13+,R0 + ENDCODE +[THEN] + +[UNDEFINED] 2! [IF] + + + CODE 2! + MOV @R15+,0(R14) + MOV @R15+,2(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE +[THEN] + +CODE 2>R +PUSH @R15+ +PUSH R14 +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE + +CODE 2R@ +SUB #4,R15 +MOV R14,2(R15) +MOV @R1,R14 +MOV 2(R1),0(R15) +MOV @R13+,R0 +ENDCODE + +CODE 2R> +SUB #4,R15 +MOV R14,2(R15) +MOV @R1+,R14 +MOV @R1+,0(R15) +MOV @R13+,R0 +ENDCODE + +[UNDEFINED] 2VARIABLE [IF] +: 2VARIABLE +CREATE 4 ALLOT +; +[THEN] + +[UNDEFINED] 2CONSTANT [IF] + + : 2CONSTANT + CREATE , , + DOES> 2@ + ; +[THEN] + +[UNDEFINED] <> [IF] +CODE <> +SUB @R15+,R14 +0<> IF + MOV #-1,R14 +THEN +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] = [IF] +CODE = +SUB @R15+,R14 +0<> IF + AND #0,R14 + MOV @R13+,R0 +THEN +XOR #-1,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] U< [IF] +CODE U< +SUB @R15+,R14 +0<> IF + MOV #-1,R14 + U< IF + AND #0,R14 + THEN +THEN +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] IF [IF] +CODE IF +SUB #2,R15 +MOV R14,0(R15) +MOV &$1DC8,R14 +ADD #4,&$1DC8 +MOV #$40AC,0(R14) +ADD #2,R14 +MOV @R13+,R0 +ENDCODE IMMEDIATE +[THEN] + +[UNDEFINED] THEN [IF] +CODE THEN +MOV &$1DC8,0(R14) +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE IMMEDIATE +[THEN] + +[UNDEFINED] ELSE [IF] +CODE ELSE +ADD #4,&$1DC8 +MOV &$1DC8,R10 +MOV #$40B2,-4(R10) +MOV R10,0(R14) +SUB #2,R10 +MOV R10,R14 +MOV @R13+,R0 +ENDCODE IMMEDIATE +[THEN] + +[UNDEFINED] DEFER! [IF] +CODE DEFER! +MOV @R15+,2(R14) +MOV @R15+,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +[UNDEFINED] IS [IF] +: IS +STATE @ +IF POSTPONE ['] POSTPONE DEFER! +ELSE ' DEFER! +THEN +; IMMEDIATE +[THEN] + +[UNDEFINED] >BODY [IF] +CODE >BODY +ADD #4,R14 +MOV @R13+,R0 +ENDCODE +[THEN] + +CODE F+ +BW1 ADD @R15+,2(R15) + ADDC @R15+,R14 + MOV @R13+,R0 +ENDCODE + +CODE F- +BW1 SUB @R15+,2(R15) + SUBC R14,0(R15) + MOV @R15+,R14 + MOV @R13+,R0 +ENDCODE + +CODE HOLDS +BW3 MOV @R15+,R9 + ADD R14,R9 + MOV &$1DB2,R8 +BEGIN SUB #1,R9 + SUB #1,R14 +U>= WHILE SUB #1,R8 + MOV.B @R9,0(R8) +REPEAT MOV R8,&$1DB2 + MOV @R15+,R14 + MOV @R13+,R0 +ENDCODE + +$1A00 4 + @ $81F3 U< +$81EF $1A00 4 + @ U< += [IF] ; MSP430FR2xxx|MSP430FR4xxx subfamilies without hardware_MPY + + +CODE F/ + PUSHM #4,R7 + MOV @R15+,R6 + MOV @R15+,R9 + MOV #0,R10 + MOV @R15,R8 + MOV #0,R11 + MOV R9,R12 + XOR R14,R12 + AND #-1,R9 +S< IF XOR #-1,R8 + XOR #-1,R9 + ADD #1,R8 + ADDC #0,R9 +THEN AND #-1,R14 +S< IF XOR #-1,R6 + XOR #-1,R14 + ADD #1,R6 + ADDC #0,R14 +THEN + MOV #32,R5 +BW1 CMP R14,R10 + 0= IF CMP R6,R9 + THEN + U>= IF SUB R6,R9 + SUBC R14,R10 + THEN +BW2 ADDC R7,R7 + ADDC R4,R4 + SUB #1,R5 + 0< ?GOTO FW1 + ADD R11,R11 + ADDC R8,R8 + ADDC R9,R9 + ADDC R10,R10 + U< ?GOTO BW1 + SUB R6,R9 + SUBC R14,R10 + BIS #1,R2 + GOTO BW2 +FW1 + MOV R7,0(R15) + MOV R4,R14 + POPM #4,R7 +BW1 AND #-1,R12 +S< IF XOR #-1,0(R15) + XOR #-1,R14 + ADD #1,0(R15) + ADDC #0,R14 +THEN MOV @R13+,R0 +ENDCODE + +CODE F#S + MOV 2(R15),R9 + MOV @R15,2(R15) + MOV R9,0(R15) + PUSHM #2,R14 + MOV #0,R12 +BEGIN PUSH R12 + MOV &$1DBE,R14 + LO2HI + UM* + HI2LO + SUB #2,R13 + CMP #10,R14 + U>= IF ADD #7,R14 + THEN ADD #$30,R14 + MOV @R1+,R12 + MOV.B R14,$1D90(R12) + ADD #1,R12 + CMP 2(R1),R12 +U>= UNTIL + POPM #2,R14 + MOV #0,0(R15) + SUB #2,R15 + MOV #$1D90,0(R15) + GOTO BW3 +ENDCODE + +CODE UDM* + PUSH R13 + PUSHM #4,R7 + MOV 4(R15),R13 + MOV 2(R15),R11 + MOV @R15,R10 + MOV #0,R4 + MOV #0,R5 + MOV #0,4(R15) + MOV #0,2(R15) + MOV #0,R6 + MOV #0,R7 + MOV #1,R9 + MOV #0,R8 +BEGIN CMP #0,R9 + 0<> IF BIT R9,R10 + ELSE BIT R8,R14 + THEN + 0<> IF ADD R13,4(R15) + ADDC R11,2(R15) + ADDC R4,R6 + ADDC R5,R7 + THEN ADD R13,R13 + ADDC R11,R11 + ADDC R4,R4 + ADDC R5,R5 + ADD R9,R9 + ADDC R8,R8 +U>= UNTIL MOV R6,0(R15) + MOV R7,R14 + POPM #4,R7 + MOV @R1+,R13 + MOV @R13+,R0 +ENDCODE + +CODE F* + MOV 2(R15),R12 + XOR R14,R12 + BIT #$8000,2(R15) +0<> IF XOR #-1,2(R15) + XOR #-1,4(R15) + ADD #1,4(R15) + ADDC #0,2(R15) +THEN + COLON + DABS UDM* + HI2LO + MOV @R1+,R13 + MOV @R15+,R14 + MOV @R15+,0(R15) + GOTO BW1 +ENDCODE + +[ELSE] + +CODE F/ + PUSHM #4,R7 + MOV @R15+,R6 + MOV @R15+,R9 + MOV #0,R10 + MOV @R15,R8 + MOV #0,R11 + MOV R9,R12 + XOR R14,R12 + AND #-1,R9 +S< IF XOR #-1,R8 + XOR #-1,R9 + ADD #1,R8 + ADDC #0,R9 +THEN AND #-1,R14 +S< IF XOR #-1,R6 + XOR #-1,R14 + ADD #1,R6 + ADDC #0,R14 +THEN MOV #32,R5 +BW1 CMP R14,R10 + 0= IF + CMP R6,R9 + THEN + U>= IF + SUB R6,R9 + SUBC R14,R10 + THEN +BW2 ADDC R7,R7 + ADDC R4,R4 + SUB #1,R5 + 0< ?GOTO FW1 + ADD R11,R11 + ADDC R8,R8 + ADDC R9,R9 + ADDC R10,R10 + U< ?GOTO BW1 + SUB R6,R9 + SUBC R14,R10 + BIS #1,R2 + GOTO BW2 +FW1 AND #-1,R12 +S< IF XOR #-1,R7 + XOR #-1,R4 + ADD #1,R7 + ADDC #0,R4 +THEN MOV R7,0(R15) + MOV R4,R14 + POPM #4,R7 + MOV @R13+,R0 +ENDCODE + +CODE F#S + MOV 2(R15),R9 + MOV @R15,2(R15) + MOV R9,0(R15) + MOV R14,R11 + MOV #0,R12 +BEGIN MOV @R15,&$4C0 + MOV &$1DBE,&$4C8 + MOV &$4E4,0(R15) + MOV &$4E6,R14 + CMP #10,R14 + U>= IF ADD #7,R14 + THEN ADD #$30,R14 + MOV.B R14,$1D90(R12) + ADD #1,R12 + CMP R11,R12 +0= UNTIL MOV #0,0(R15) + MOV R11,R14 + SUB #2,R15 + MOV #$1D90,0(R15) + GOTO BW3 +ENDCODE + +CODE F* + MOV 4(R15),&$4D4 + MOV 2(R15),&$4D6 + MOV @R15,&$4E0 + MOV R14,&$4E2 + ADD #4,R15 + MOV &$4E6,0(R15) + MOV &$4E8,R14 + MOV @R13+,R0 +ENDCODE + +[THEN] + +CODE F.N +MOV R14,R11 +MOV @R15+,R14 +MOV R14,R12 +PUSHM #3,R13 +LO2HI + <# DABS + R> F#S + $2C HOLD + #S + R> SIGN #> + TYPE SPACE +; + + +CODE D< + MOV @R15+,R12 + MOV @R15+,R11 + MOV @R15+,R10 +BW1 CMP R14,R11 + MOV #0,R14 +S< IF MOV #-1,R14 +THEN +0= IF CMP R12,R10 + S< IF MOV #-1,R14 + THEN +THEN +MOV @R13+,R0 +ENDCODE + +CODE D> +MOV R14,R11 +MOV @R15+,R10 +MOV @R15+,R14 +MOV @R15+,R12 +GOTO BW1 +ENDCODE + +CODE S2F + SUB #2,R15 + MOV #0,0(R15) + MOV @R13+,R0 +ENDCODE + +: F2S + SWAP $8000 AND IF 1 + THEN ; + +: DMIN + 2OVER 2OVER + D< IF 2DROP ELSE 2NIP THEN +; + +: DMAX + 2OVER 2OVER + D> IF 2DROP ELSE 2NIP THEN +; + +: DRANGE + 2ROT DMIN DMAX +; + +: RANGE + ROT MIN MAX +; + +: F.000 3 F.N ; + +2VARIABLE KP +2VARIABLE KI +2VARIABLE KD +VARIABLE SETPOINT + +VARIABLE SAMPLE_TIME +VARIABLE OUT_MAX +VARIABLE OUT_MIN +VARIABLE OUT-OVERRIDE + +VARIABLE SET-VAL +VARIABLE INPUT_PREV +2VARIABLE I_SUM + +VARIABLE DEBUG +0 DEBUG ! + +: ?DEBUG DEBUG @ ; + + + +: CALC-R6 +KP 2@ F* +?DEBUG IF ." Pval:" 2DUP F2S . +THEN +; + + +: CALC-I +KI 2@ F* +I_SUM 2@ F+ +OUT_MIN @ S2F +OUT_MAX @ S2F +DRANGE +2DUP I_SUM 2! +?DEBUG IF ." Ival:" 2DUP F2S . +THEN +; + +: CALC-D + + INPUT_PREV @ - + S2F KD 2@ F* +?DEBUG IF ." Dval:" 2DUP F2S . +THEN +; + +: PID_COMPUTE +DUP DUP SET-VAL @ SWAP - S2F +2DUP CALC-R6 +2SWAP CALC-I F+ +ROT CALC-D F- + +F2S +?DEBUG IF ." OUT:" DUP . +THEN +SWAP INPUT_PREV ! +OUT_MIN @ OUT_MAX @ RANGE +?DEBUG IF ." PWM:" DUP . +THEN +; + + +: SET + SET-VAL ! ; + +: TUNING + + + SAMPLE_TIME @ S2F 1000,0 F/ 2>R + + 2R@ F/ KD 2! + 2R> F* KI 2! + KP 2! ; + +: PID-INIT + OUT_MAX ! + OUT_MIN ! + SAMPLE_TIME ! + TUNING + 0 OUT-OVERRIDE ! + CR ." PID initialized - kp:" KP 2@ F.000 ." ki:" KI 2@ F.000 ." kd:" KD 2@ F.000 +; + +: PID + OUT-OVERRIDE @ -1 = IF + PID_COMPUTE + ELSE + CR ." SET:" SET-VAL @ . ." IS:" DUP . + INPUT_PREV ! + OUT-OVERRIDE @ + ." PWM:" DUP . + THEN ; + +: MANUAL + OUT-OVERRIDE ! ; + + +: AUTO + OUT-OVERRIDE @ -1 <> IF + + OUT-OVERRIDE @ + OUT_MIN @ OUT_MAX @ RANGE + S2F I_SUM 2! + -1 OUT-OVERRIDE ! + THEN ; + +: AUTOHOLD + INPUT_PREV @ SET-VAL ! + AUTO ; + + + + +CODE STOP + MOV @R13+,R0 +ENDCODE + +CODE APP_INIT + MOV @R13+,R0 +ENDCODE + +CODE START + MOV @R13+,R0 +ENDCODE + + +ECHO diff --git a/MSP430-FORTH/SD_430FR5994/PROG10k.4TH b/MSP430-FORTH/SD_430FR5994/PROG10k.4TH new file mode 100644 index 0000000..f50c044 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/PROG10k.4TH @@ -0,0 +1,2664 @@ + +; ----------------------------------- +; PROG10K.4th for MSP_EXP430FR5994 +; ----------------------------------- + +; load and compile 10kb (9 x RC52LCD) + + + + CODE ABORT_RC5TOLCD + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_RC5TOLCD + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET +ECHO + + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET + diff --git a/MSP430-FORTH/SD_430FR5994/RC5toLCD.4TH b/MSP430-FORTH/SD_430FR5994/RC5toLCD.4TH new file mode 100644 index 0000000..0bfbda6 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/RC5toLCD.4TH @@ -0,0 +1,350 @@ + +; ----------------------------------- +; RC5TOLCD.4th for MSP_EXP430FR5994 +; ----------------------------------- + + + CODE ABORT_RC5TOLCD + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_RC5TOLCD + + MARKER {RC5TOLCD} + 8 ALLOT + + + + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + CODE 20_US + BEGIN + MOV &{RC5TOLCD}+6,R9 + SUB #2,R9 + BEGIN + MOV #0,R3 + SUB #1,R9 + 0= UNTIL + MOV #0,R3 + SUB #1,R14 + 0= UNTIL + MOV @R15+,R14 + MOV @R1+,R13 + ENDCODE + + CODE TOP_LCD + BIS.B #4,&$243 + BIT.B #1,&$241 + 0= IF + AND.B #$0F,R14 + MOV.B R14,&$222 + BIC.B #4,&$243 + MOV @R15+,R14 + MOV @R13+,R0 + THEN + SUB #2,R15 + MOV R14,0(R15) + BIC.B #4,&$243 + MOV.B &$220,R14 + AND.B #$0F,R14 + MOV @R13+,R0 + ENDCODE + + CODE LCD_WRC + BIS.B #2,&$243 +BW1 SUB #2,R15 + MOV R14,0(R15) + RRUM #4,R14 + BIC.B #1,&$243 + BIS.B #$0F,&$224 + COLON + TOP_LCD 2 20_US + TOP_LCD 2 20_US + ; + + CODE LCD_WRF + BIC.B #2,&$243 + GOTO BW1 + ENDCODE + + : LCD_CLEAR $01 LCD_WRF 100 20_us ; + : LCD_HOME $02 LCD_WRF 100 20_us ; + + HDNCODE WDT_INT + BIT.B #$20,&$240 + 0= IF + CMP #19,&$3D6 + U< IF + ADD #1,&$3D6 + THEN + ELSE + BIT.B #$40,&$240 + 0= IF + CMP #3,&$3D6 + U>= IF + SUB #1,&$3D6 + THEN + THEN + THEN + RETI + ENDCODE + + HDNCODE RC5_INT + MOV #1778,R9 + MOV #14,R10 + BEGIN + MOV #%1011100100,&$380 + RRUM #1,R9 + MOV R9,R8 + RRUM #1,R8 + ADD R9,R8 + BEGIN + CMP R8,&$390 + U>= UNTIL + BIT.B #4,&$200 + ADDC R11,R11 + MOV.B &$200,&$208 + BIC.B #4,&$20C + SUB #1,R10 + 0<> WHILE + ADD R9,R8 + BEGIN + MOV &$390,R9 + CMP R8,R9 + U>= ?GOTO FW1 + BIT.B #4,&$20C + 0<> UNTIL + REPEAT + BIC #$30,&$380 + RLAM #1,R11 + MOV.B R11,R9 + RRUM #2,R9 + BIT #$4000,R11 + 0= IF BIS #$40,R9 + THEN + RRUM #3,R11 + XOR @R1,R11 + BIT #$400,R11 + 0= ?GOTO FW2 + XOR #$400,0(R1) + SUB #6,R15 + MOV R14,4(R15) + MOV &$1DBE,2(R15) + MOV #$10,&$1DBE + MOV R9,0(R15) + MOV #0,R14 + LO2HI + LCD_CLEAR + <# # #S #36 HOLD #> + ['] LCD_WRC IS EMIT + TYPE + ['] EMIT >BODY IS EMIT + HI2LO + MOV @R15+,&$1DBE + MOV @R15+,R14 +FW1 BIC #$30,&$380 +FW2 BIC #%1111_1000,0(R1) + RETI + ENDCODE + + HDNCODE STOP_R2L + CMP #WDT_INT,&$FFEA + 0= IF + BIC.B #4,&$20A + BIC.B #4,&$20C + MOV #0,&$3C0 + MOV #0,&$340 + MOV #0,&$342 + MOV #{RC5TOLCD},R10 + MOV #$4082,-2(R10) + $180E $3C00 TSTBIT + [IF] + MOV @R10+,&UART_WARM+2 + [ELSE] + MOV @R10+,&$4180+2 + [THEN] + MOV @R10+,&$FFEA + MOV @R10+,&$FFDE + THEN + MOV @R1+,R0 + ENDCODE + + CODE STOP +BW1 CALL #STOP_R2L + COLON + ECHO + ." type START to start RC5toLCD" + ; + + HDNCODE INIT_R2L + MOV #%10_1101_0100,&$3C0 + $1800 @ 16000 = + [IF] + MOV #1,&$3A0 + MOV #1,&$3E0 + [THEN] + $1800 @ 24000 = + [IF] + MOV #2,&$3A0 + MOV #2,&$3E0 + [THEN] + MOV #19,&$3D2 + MOV #%0110_0000,&$3C6 + MOV #10,&$3D6 + BIS.B #$20,&$204 + BIS.B #$20,&$20A + BIS.B #7,&$245 + BIC.B #7,&$247 + BIS.B #$0F,&$224 + BIC.B #$0F,&$226 + BIS.B #4,&$20A + BIC.B #4,&$20C + MOV #%01_0001_0100,&$340 + MOV ##3276,&$352 + MOV #%10000,&$342 + CALL &{RC5TOLCD} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + CMP #4,R14 + 0= ?GOTO BW1 + LO2HI + #1000 20_US + %011 TOP_LCD + #205 20_US + %011 TOP_LCD + #5 20_US + %011 TOP_LCD + #2 20_US + %010 TOP_LCD + #2 20_US + %00101000 LCD_WRF + %1000 LCD_WRF + LCD_CLEAR + %0110 LCD_WRF + %1100 LCD_WRF + LCD_CLEAR + HI2LO + MOV @R1+,R0 + ENDCODE + + CODE START + CMP #WDT_INT,&$FFEA + 0= IF + MOV @R13+,R0 + THEN + MOV #STOP_R2L,&{RC5TOLCD}-2 + $180E $3C00 TSTBIT + [IF] + MOV &UART_WARM+2,&{RC5TOLCD} + MOV #INIT_R2L,&UART_WARM+2 + [ELSE] + MOV &$4180+2,&{RC5TOLCD} + MOV #INIT_R2L,&$4180+2 + [THEN] + MOV &$FFEA,&{RC5TOLCD}+2 + MOV #WDT_INT,&$FFEA + MOV &$FFDE,&{RC5TOLCD}+4 + MOV #RC5_INT,&$FFDE + SUB #6,R15 + MOV R14,4(R15) + MOV &$1800,2(R15) + MOV #0,0(R15) + MOV #200,R14 + CALL #$403E + MOV @R15,&{RC5TOLCD}+6 + ADD #4,R15 + MOV @R15+,R14 + CALL #INIT_R2L + LO2HI + ." RC5toLCD is running," + ." Type STOP to quit." + HI2LO + MOV #ALLOT+$8,R0 + ENDCODE + +RST_SET +ECHO + diff --git a/MSP430-FORTH/SD_430FR5994/RTC.4TH b/MSP430-FORTH/SD_430FR5994/RTC.4TH new file mode 100644 index 0000000..9cbec52 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/RTC.4TH @@ -0,0 +1,605 @@ + + CODE ABORT_RTC + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$4000,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" target without LF_XTAL !" + RST_RET + ; + + ABORT_RTC + +; -------------------- +; RTC.4th for MSP_EXP430FR5994 +; -------------------- + + + MARKER {RTC} + + [UNDEFINED] OR + [IF] + CODE OR + BIS @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C! + [IF] + CODE C! + MOV.B @R15+,0(R14) + ADD #1,R15 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DEPTH + [IF] + CODE DEPTH + MOV R14,-2(R15) + MOV #$1C80,R14 + SUB R15,R14 + RRA R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1- + [IF] + CODE 1- + SUB #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + CODE U< + SUB @R15+,R14 + 0<> IF + MOV #-1,R14 + U< IF + AND #0,R14 + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN + [IF] + + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE + + : OF + 1+ + >R + POSTPONE OVER POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + [THEN] + + [UNDEFINED] 2* + [IF] + CODE 2* + ADD R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] UM* + [IF] + CODE UM* + MOV @R15,&$4C0 +BW1 MOV R14,&$4C8 + MOV &$4E4,0(R15) + MOV &$4E6,R14 + MOV @R13+,R0 + ENDCODE + + CODE M* + MOV @R15,&$4C2 + GOTO BW1 + ENDCODE + [THEN] + + [UNDEFINED] UM/MOD + [IF] + CODE UM/MOD + PUSH #DROP + MOV #$403E,R0 + ENDCODE + [THEN] + + : U*/ + >R UM* R> UM/MOD SWAP DROP + ; + + : U/MOD + 0 SWAP UM/MOD + ; + + : UMOD + U/MOD DROP + ; + + : U/ + U/MOD SWAP DROP + ; + + [UNDEFINED] SPACES + [IF] + : SPACES + BEGIN + ?DUP + WHILE + $20 EMIT + 1- + REPEAT + ; + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + CODE TIME? + BEGIN + BIT.B #$10,&$4A2 + 0<> UNTIL + COLON + $4B2 C@ 2 U.R ':' EMIT + $4B1 C@ 2 U.R ':' EMIT + $4B0 C@ 2 U.R + ; + + : TIME! + 2 DEPTH + U< IF + $4B0 C! + $4B1 C! + $4B2 C! + THEN + ." it is " TIME? + ; + + CODE DATE? + BEGIN + BIT.B #$10,&$4A2 + 0<> UNTIL + COLON + + + + $4B3 C@ + CASE + 0 OF ." Sat" ENDOF + 1 OF ." Sun" ENDOF + 2 OF ." Mon" ENDOF + 3 OF ." Tue" ENDOF + 4 OF ." Wed" ENDOF + 5 OF ." Thu" ENDOF + 6 OF ." Fri" ENDOF + ENDCASE + $4B6 @ + $4B5 C@ + $4B4 C@ + $20 EMIT + 2 U.R '/' EMIT + 2 U.R '/' EMIT + . + ; + + : DATE! + 2 DEPTH + U< IF + $4B6 ! + $4B5 C! + $4B4 C! + THEN + $4B4 C@ + $4B5 C@ + $4B6 @ + OVER 3 U< + IF 1 - SWAP 12 + SWAP + THEN + 100 U/MOD + DUP 4 U/ SWAP 2* - + SWAP DUP 4 U/ + + + SWAP 1+ 13 5 U*/ + + + 7 UMOD + $4B3 C! + ." we are on " DATE? + ; + + RST_SET + + [UNDEFINED] S_ + [IF] + CODE S_ + MOV #0,&$1DC0 + COLON + $401E , + $20 WORD + HI2LO + MOV.B @R14,R14 + ADD #1,R14 + BIT #1,R14 + ADDC R14,&$1DC8 + MOV @R15+,R14 + MOV @R1+,R13 + MOV #$20,&$1DC0 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ESC + [IF] + CODE ESC + CMP #0,&$1DBC + 0= IF MOV @R13+,R0 + THEN + COLON + $1B + POSTPONE LITERAL + POSTPONE EMIT + POSTPONE S_ + POSTPONE TYPE + ; IMMEDIATE + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EXECUTE + [IF] + CODE EXECUTE + PUSH R14 + MOV @R15+,R14 + MOV @R1+,R0 + ENDCODE + [THEN] + + [UNDEFINED] EVALUATE + [IF] + CODE EVALUATE + MOV #$1DC2,R9 + MOV @R9+,R12 + MOV @R9+,R11 + MOV @R9+,R10 + PUSHM #4,R13 + LO2HI + [ ' \ 8 + , ] + HI2LO + MOV @R1+,&$1DC6 + MOV @R1+,&$1DC4 + MOV @R1+,&$1DC2 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + : SET_TIME + ESC [8;40;80t + 39 0 DO CR LOOP + ESC [H + CR ." DATE (DMY): " + $1CE4 DUP #84 + ['] ACCEPT >BODY + EXECUTE + EVALUATE + CR DATE! + CR ." TIME (HMS): " + $1CE4 DUP #84 + ['] ACCEPT >BODY + EXECUTE + EVALUATE + CR TIME! + RST_RET + ; + +ECHO +SET_TIME diff --git a/MSP430-FORTH/SD_430FR5994/SD_TEST.4TH b/MSP430-FORTH/SD_430FR5994/SD_TEST.4TH new file mode 100644 index 0000000..c01bdc3 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/SD_TEST.4TH @@ -0,0 +1,507 @@ + +; ----------- +; SD_TEST.4th for MSP_EXP430FR5994 +; ----------- + + CODE ABORT_SD_TEST + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + [UNDEFINED] WRITE + [IF] + 1 ABORT" no SD_CARD_READ_WRITE addon!" + [THEN] + RST_RET + ; + + ABORT_SD_TEST + + MARKER {SD_TEST} + + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN + [IF] + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] STATE + [IF] + $1DBC CONSTANT STATE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &BASE + MOV #$10,&BASE + ADD @R15,R14 + LO2HI + SWAP + DO + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + CR + $10 +LOOP + R> BASE ! + ; + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #BEGIN,R0 + ENDCODE + [THEN] + + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] = + [IF] + CODE = + SUB @R15+,R14 + 0<> IF + AND #0,R14 + MOV @R13+,R0 + THEN + XOR #-1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE + + : OF + 1+ + >R + POSTPONE OVER + POSTPONE = + POSTPONE IF + POSTPONE DROP + R> + ; IMMEDIATE + + : ENDOF + >R + POSTPONE ELSE + R> + ; IMMEDIATE + + : ENDCASE + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] + + CODE SD_EMIT + CMP #$200,&$201E + U>= IF + CALL &WRITE+2 + THEN + MOV &$201E,R8 + MOV.B R14,$1E00(R8) + ADD #1,&$201E + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + : DOESWRITE + ['] SD_EMIT IS EMIT + $4000 HERE OVER - DUMP + ['] EMIT >BODY IS EMIT + CLOSE + ; + + : SD_TEST + ECHO + $0D EMIT + CR + ." ----------" CR + ." Bootloader" CR + ." ----------" CR + ." ? Fast Forth Specifs" CR + ." 0 Set date and time" CR + ." 1 Load {UTILITY} words" CR + ." 2 Load {SD_TOOLS} words" CR + ." 3 Load {CORE_COMP} words" CR + ." 4 Load ANS core tests" CR + ." 5 Load a source file to make 10k program" CR + ." 6 Read it only (47k)" CR + ." 7 write FORTH dump in YOURFILE.TXT" CR + ." 8 append FORTH dump to YOURFILE.TXT" CR + ." 9 delete YOURFILE.TXT" CR + ." your choice: " + KEY DUP EMIT + NOECHO + {SD_TEST} + CASE + '?' OF LOAD" FF_SPECS.4TH" ENDOF + '0' OF LOAD" RTC.4TH" ENDOF + '1' OF LOAD" UTILITY.4TH" ENDOF + '2' OF LOAD" SD_TOOLS.4TH" ENDOF + '3' OF LOAD" CORE_ANS.4TH" ENDOF + '4' OF LOAD" CORETEST.4TH" ENDOF + '5' OF LOAD" PROG10K.4TH" ENDOF + '6' OF READ" PROG10K.4TH" + BEGIN READ + UNTIL ENDOF + '7' OF WRITE" YOURFILE.TXT" + DOESWRITE ENDOF + '8' OF APPEND" YOURFILE.TXT" + DOESWRITE ENDOF + '9' OF DEL" YOURFILE.TXT" ENDOF + ENDCASE + CR + ; + +SD_TEST diff --git a/MSP430-FORTH/SD_430FR5994/SD_TOOLS.4TH b/MSP430-FORTH/SD_430FR5994/SD_TOOLS.4TH new file mode 100644 index 0000000..0ecbc08 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/SD_TOOLS.4TH @@ -0,0 +1,310 @@ + + +; --------------------------------------------------------------- +; SD_TOOLS.4th for MSP_EXP430FR5994 +; BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER +; --------------------------------------------------------------- + + CODE ABORT_SD_TOOLS + SUB #4,R15 + MOV R14,2(R15) + [UNDEFINED] LOAD" \ " + [IF] + MOV #-1,0(R15) + [ELSE] + MOV #0,0(R15) + [THEN] + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" Builds FastForth with SD_CARD_LOADER addon.." + RST_RET + ; + + ABORT_SD_TOOLS + + MARKER {SD_TOOLS} + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #$4032,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &$1DBE + MOV #$10,&$1DBE + ADD @R15,R14 + LO2HI + SWAP + $FFF0 AND + DO CR + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> $1DBE ! + ; + [THEN] + + CODE SECTOR. +BW1 MOV R14,R9 + MOV @R15,R10 + CALL #R_SECT_WX + COLON + SPACE <# #S #> TYPE + $1E00 $200 DUMP CR ; + + CODE CLUSTER. +BW2 BIT.B #4,&$260 + 0<> IF + MOV #SYS+$16,R0 + THEN + MOV.B &$2012,R10 + MOV @R15,R9 + BEGIN + RRA R10 + U< WHILE + ADD R9,R9 + ADDC R14,R14 + REPEAT + ADD &$2010,R9 + MOV R9,0(R15) + ADDC #0,R14 + GOTO BW1 + ENDCODE + + CODE FAT + SUB #4,R15 + MOV R14,2(R15) + MOV &$2008,0(R15) + MOV #0,R14 + GOTO BW1 + ENDCODE + + CODE DIR + SUB #4,R15 + MOV R14,2(R15) + MOV &$202C,0(R15) + MOV &$202E,R14 + GOTO BW2 + ENDCODE + + RST_SET ECHO diff --git a/MSP430-FORTH/MSP_EXP430FR5994/TESTXASM.4TH b/MSP430-FORTH/SD_430FR5994/TESTXASM.4TH similarity index 50% rename from MSP430-FORTH/MSP_EXP430FR5994/TESTXASM.4TH rename to MSP430-FORTH/SD_430FR5994/TESTXASM.4TH index 6a24972..5bc8b99 100644 --- a/MSP430-FORTH/MSP_EXP430FR5994/TESTXASM.4TH +++ b/MSP430-FORTH/SD_430FR5994/TESTXASM.4TH @@ -3,606 +3,690 @@ ; TESTXASM.4th for MSP_EXP430FR5994 ; ----------------------------------------------------------------------- -CODE ABORT_TEST_ASMX -SUB #2,R15 -MOV R14,0(R15) -MOV &$180E,R14 -SUB #308,R14 -COLON -$0D EMIT -ABORT" FastForth V3.8 please!" -PWR_STATE -; - -ABORT_TEST_ASMX - -[UNDEFINED] + [IF] -CODE + -ADD @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] -CODE - -SUB @R15+,R14 -XOR #-1,R14 -ADD #1,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] + CODE ABORT_TEST_ASMX + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_TEST_ASMX + + MARKER {TEST_ASMX} + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] -CODE MAX + [UNDEFINED] MAX + [IF] + CODE MAX CMP @R15,R14 S< ?GOTO FW1 BW1 ADD #2,R15 MOV @R13+,R0 -ENDCODE - -CODE MIN + ENDCODE + + CODE MIN CMP @R15,R14 S< ?GOTO BW1 FW1 MOV @R15+,R14 MOV @R13+,R0 -ENDCODE - -[THEN] - -[UNDEFINED] C@ [IF] -CODE C@ -MOV.B @R14,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] -: CONSTANT -CREATE -HI2LO -MOV R14,-2(R10) -MOV @R15+,R14 -MOV @R1+,R13 -MOV @R13+,R0 -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] BL [IF] -#32 CONSTANT BL -[THEN] - -[UNDEFINED] SPACE [IF] -: SPACE -BL EMIT ; -[THEN] - -[UNDEFINED] SPACES [IF] -CODE SPACES -CMP #0,R14 -0<> IF - PUSH R13 - BEGIN - LO2HI - BL EMIT - HI2LO - SUB #2,R13 - SUB #1,R14 - 0= UNTIL + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 MOV @R1+,R13 -THEN -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] -CODE OVER -MOV R14,-2(R15) -MOV @R15,R14 -SUB #2,R15 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -CODE SWAP -MOV @R15,R10 -MOV R14,0(R15) -MOV R10,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] -CODE >R -PUSH R14 -MOV @R15+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] -CODE R> -SUB #2,R15 -MOV R14,0(R15) -MOV @R1+,R14 -MOV @R13+,R0 -ENDCODE -[THEN] + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] -[UNDEFINED] U.R [IF] -: U.R - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] DO + [IF] + + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE -[UNDEFINED] DO [IF] -CODE DO -SUB #2,R15 -MOV R14,0(R15) -ADD #2,&$1DC6 -MOV &$1DC6,R14 -MOV #$403E,-2(R14) -ADD #2,&$1C00 -MOV &$1C00,R10 -MOV #0,0(R10) -MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE LOOP - MOV #$4060,R9 -BW1 ADD #4,&$1DC6 - MOV &$1DC6,R10 + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 MOV R9,-4(R10) MOV R14,-2(R10) -BEGIN - MOV &$1C00,R14 - SUB #2,&$1C00 - MOV @R14,R14 - CMP #0,R14 -0<> WHILE - MOV R10,0(R14) -REPEAT + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT MOV @R15+,R14 MOV @R13+,R0 -ENDCODE IMMEDIATE - -CODE +LOOP -MOV #$404E,R9 -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] -CODE I -SUB #2,R15 -MOV R14,0(R15) -MOV @R1,R14 -SUB 2(R1),R14 -MOV @R13+,R0 -ENDCODE -[THEN] - -[UNDEFINED] DUMP [IF] -CODE DUMP -PUSH R13 -PUSH &$1DDC -MOV #$10,&$1DDC -ADD @R15,R14 -LO2HI - SWAP - DO CR - I 4 U.R SPACE - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I - DO I C@ $7E MIN BL MAX EMIT LOOP - $10 +LOOP - R> $1DDC ! -; -[THEN] + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + DEFER CR + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &BASE + MOV #$10,&BASE + ADD @R15,R14 + LO2HI + SWAP + DO CR + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! + ; + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #$4032,R0 + ENDCODE + [THEN] + + RST_SET + + + ECHO + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word) +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) +; indexed instructions must be written as $xxxx(REG) (single numbers) +; ----------------------------------------------------------------------------- -[UNDEFINED] HERE [IF] -CODE HERE -MOV #$4028,R0 +HERE +CODE TT +CALLA R10 ENDCODE -[THEN] - -PWR_HERE - - -ECHO -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba (without extended word) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +HERE OVER - DUMP +; you should see: 4A 13 +RST_RET HERE -CODE TEST -MOVA @R10,R11 +CODE TT +CALLA $3456(R10) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 5A 13 56 34 +RST_RET HERE -CODE TEST -MOVA @R11+,R10 +CODE TT +CALLA 0(R15) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>1A 0B<04 44 55 4D 50 4F -PWR_STATE +; you should see: 5F 13 00 00 +RST_RET HERE -CODE TEST -MOVA &$1.2345,R11 +CODE TT +CALLA @R10 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>2B 01 45 23<04 44 55 4D -PWR_STATE +; you should see: 6A 13 +RST_RET HERE -CODE TEST -MOVA $.1234(R10),R12 +CODE TT +CALLA @R15 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>3C 0A 34 12<04 44 55 4D -PWR_STATE +; you should see: 6F 13 +RST_RET HERE -CODE TEST -MOVA R11,&$1.2345 +CODE TT +CALLA @R10+ ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>61 0B 45 23<04 44 55 4D -PWR_STATE +; you should see: 7A 13 +RST_RET HERE -CODE TEST -MOVA R12,$.1234(R10) +CODE TT +CALLA &$2.3456 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>7A 0C 34 12<04 44 55 4D -PWR_STATE +; you should see: 82 13 56 34 +RST_RET HERE -CODE TEST -MOVA #$0.1,R12 +CODE TT +CALLA #$5.6789 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>8C 00 01 00<04 44 55 4D -PWR_STATE +; you should see: B5 13 89 67 +RST_RET + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) +; indexed instructions must be written as $xxxx(REG) (single numbers) +; ----------------------------------------------------------------------------- HERE -CODE TEST -CMPA #$1.2345,R12 +CODE TT +MOVA @R10,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>9C 01 45 23<04 44 55 4D -PWR_STATE +; you should see: 0B 0A +RST_RET HERE -CODE TEST -ADDA #$2.3456,R12 +CODE TT +MOVA @R11+,R10 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>AC 02 56 34<04 44 55 4D -PWR_STATE +; you should see: 1A 0B +RST_RET HERE -CODE TEST -SUBA #$3.4567,R12 +CODE TT +MOVA &$1.2345,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>BC 03 67 45<04 44 55 4D -PWR_STATE +; you should see: 2B 01 45 23 +RST_RET +HERE +CODE TT +MOVA 2(R15),R14 +ENDCODE +HERE OVER - DUMP +; you should see: 3E 0F 02 00 +RST_RET +HERE +CODE TT +MOVA $1234(R10),R12 +ENDCODE +HERE OVER - DUMP +; you should see: 3C 0A 34 12 +RST_RET HERE -CODE TEST -MOVA R10,R11 +CODE TT +MOVA R11,&$1.2345 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>CB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 61 0B 45 23 +RST_RET HERE -CODE TEST -CMPA R10,R11 +CODE TT +MOVA R14,0(R15) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>DB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 7F 0E 00 00 +RST_RET HERE -CODE TEST -ADDA R10,R11 +CODE TT +MOVA R12,$1234(R10) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>EB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 7A 0C 34 12 +RST_RET HERE -CODE TEST -SUBA R10,R11 +CODE TT +MOVA #$0.1,R12 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>FB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 8C 00 01 00 +RST_RET -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +HERE +CODE TT +CMPA #$1.2345,R12 +ENDCODE +HERE OVER - DUMP +; you should see: 9C 01 45 23 +RST_RET HERE -CODE TEST -CALLA R10 +CODE TT +ADDA #$2.3456,R12 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>4A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: AC 02 56 34 +RST_RET HERE -CODE TEST -CALLA $.3456(R10) +CODE TT +SUBA #$3.4567,R12 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5A 13 56 34<04 44 55 4D -PWR_STATE +; you should see: BC 03 67 45 +RST_RET HERE -CODE TEST -CALLA @R10 +CODE TT +MOVA R10,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>6A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: CB 0A +RST_RET HERE -CODE TEST -CALLA @R10+ +CODE TT +CMPA R10,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>7A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: DB 0A +RST_RET HERE -CODE TEST -CALLA &$2.3456 +CODE TT +ADDA R10,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>82 13 56 34<04 44 55 4D -PWR_STATE +; you should see: EB 0A +RST_RET HERE -CODE TEST -CALLA #$5.6789 +CODE TT +SUBA R10,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>B5 13 89 67<04 44 55 4D -PWR_STATE +; you should see: FB 0A +RST_RET -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES V extended double operand -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- HERE -CODE TEST +CODE TT MOV R12,R11 MOVX R12,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 4C 40 18 0B 4C<04 44 -PWR_STATE +; you should see: 0B 4C 40 18 0B 4C +RST_RET HERE -CODE TEST +CODE TT ADD R11,R11 ADDX.A R11,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 00 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 00 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADD R11,R11 RPT R9 ADDX.A R11,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 89 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 89 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADD R11,R11 RPT #8 ADDX.A R11,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 07 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 07 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADDC #$9876,R11 ADDCX.A #$5.9876,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>3B 60 76 98 80 1A 7B 60 -; 76 98<04 44 55 4D -PWR_STATE +; you should see: 3B 60 76 98 80 1A 7B 60 76 98 +RST_RET HERE -CODE TEST +CODE TT ADDC &$9876,R11 ADDCX.A &$5.9876,R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>1B 62 76 98 80 1A 5B 62 -; 76 98<04 44 55 4D -PWR_STATE +; you should see: 1B 62 76 98 80 1A 5B 62 76 98 +RST_RET HERE -CODE TEST +CODE TT XOR.B $5432(R12),R11 XORX.B $6.5432(R12),R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5B EC 32 54 46 18 5B EC -; 32 54<04 44 55 4D -PWR_STATE +; you should see: 5B EC 32 54 46 18 5B EC 32 54 +RST_RET HERE -CODE TEST +CODE TT SUBC R11,$5432(R12) SUBCX.A R11,$6.5432(R12) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>8C 7B 32 54 06 18 CC 7B -; 32 54<04 44 55 4D -PWR_STATE +; you should see: 8C 7B 32 54 06 18 CC 7B 32 54 +RST_RET HERE -CODE TEST +CODE TT XOR.B R11,$5432(R12) XORX.B R11,$6.5432(R12) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>CC EB 32 54 46 18 CC EB -; 32 54<04 44 55 4D -PWR_STATE - -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand (take count of RPT) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) +; you should see: CC EB 32 54 46 18 CC EB 32 54 +RST_RET + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- HERE -CODE TEST +CODE TT RRA R9 RRAX R9 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>09 11 40 18 09 11<04 44 -PWR_STATE +; you should see: 09 11 40 18 09 11 +RST_RET HERE -CODE TEST +CODE TT RRC @R9 RRCX.A @R9 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>29 10 00 18 69 10<04 44 -PWR_STATE +; you should see: 29 10 00 18 69 10 +RST_RET HERE -CODE TEST +CODE TT RRC @R12 RRCX.A @R12 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>2C 10 00 18 6C 10<04 44 -PWR_STATE +; you should see: 2C 10 00 18 6C 10 +RST_RET HERE -CODE TEST +CODE TT RRC @R9+ RRUX.A @R9+ ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>39 10 00 19 79 10<04 44 -PWR_STATE +; you should see: 39 10 00 19 79 10 +RST_RET HERE -CODE TEST +CODE TT RRC R11 RPT #9 RRUX.A R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 10 08 19 4B 10<04 44 -PWR_STATE +; you should see: 0B 10 08 19 4B 10 +RST_RET HERE -CODE TEST +CODE TT RRC R11 RPT R9 RRUX.A R11 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 10 89 19 4B 10<04 44 -PWR_STATE +; you should see: 0B 10 89 19 4B 10 +RST_RET HERE -CODE TEST +CODE TT PUSH #$2345 PUSHX #$0.2345 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>30 12 45 23 40 18 30 12 -; 45 23<04 44 55 4D -PWR_STATE +; you should see: 30 12 45 23 40 18 30 12 45 23 +RST_RET HERE -CODE TEST +CODE TT PUSH &$5678 PUSHX.A &$4.5678 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>12 12 78 56 00 1A 52 12 -; 78 56<04 44 55 4D -PWR_STATE +; you should see: 12 12 78 56 00 1A 52 12 78 56 +RST_RET HERE -CODE TEST +CODE TT PUSH.B &$33 PUSHX.B &$.33 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>52 12 33 00 40 18 52 12 -; 33 00<04 44 55 4D -PWR_STATE +; you should see: 52 12 33 00 40 18 52 12 33 00 +RST_RET HERE -CODE TEST +CODE TT PUSH.B $3344(R11) PUSHX.B $.3344(R11) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5B 12 44 33 40 18 5B 12 -; 44 33<04 44 55 4D -PWR_STATE +; you should see: 5B 12 44 33 40 18 5B 12 44 33 +RST_RET + + [UNDEFINED] BASE + [IF] + ' # 2 + CONSTANT BASE + [THEN] : %. -$1DDC @ %10 $1DDC ! SWAP 8 EMIT . $1DDC ! +BASE @ %10 BASE ! SWAP 8 EMIT . BASE ! +RST_RET ; : %U. -$1DDC @ %10 $1DDC ! SWAP 8 EMIT U. $1DDC ! ; - -PWR_HERE +BASE @ %10 BASE ! SWAP 8 EMIT U. BASE ! +RST_RET +; +RST_SET ; ================ ; RRUX test @@ -618,9 +702,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRUX_T ; you should see %111100001111000 --> % - -PWR_STATE +RRUX_T ; % +; you should see: %111100001111000 ; ================ ; RRUX repeat test @@ -637,9 +720,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRUX_T ; you should see %111100001111000 --> % - -PWR_STATE +RRUX_T ; % +; you should see: %111100001111000 CODE RRUX_T MOV #$F0F0,R8 @@ -651,9 +733,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRUX_T ; you should see %111100001111 --> % - -PWR_STATE +RRUX_T ; --> % +; you should see: %111100001111 CODE RRUX_T MOV #$F0F0,R8 @@ -665,16 +746,13 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRUX_T ; you should see %11110000 --> % - -PWR_STATE - +RRUX_T ; % +; you should see: %11110000 ; ================ ; RRCX test ; ================ - CODE RRCX_T MOV #$8000,R8 BIC #1,R2 @@ -685,9 +763,8 @@ MOV R8,R14 MOV #%U.,R0 ENDCODE -RRCX_T ; you should see %100000000000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %100000000000000 ; ================ ; RRCX repeat test @@ -704,9 +781,8 @@ MOV R8,R14 MOV #%U.,R0 ENDCODE -RRCX_T ; you should see %100000000000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %100000000000000 CODE RRCX_T MOV #$8000,R8 @@ -719,15 +795,13 @@ MOV R8,R14 MOV #%U.,R0 ENDCODE -RRCX_T ; you should see %10000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %10000000 ; ================ ; RRAX test ; ================ - CODE RRAX_T MOV #$8000,R8 RRAX R8 @@ -737,9 +811,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRAX_T ; you should see %-100000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000000000 ; ================ ; RRAX repeat test @@ -756,9 +829,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRAX_T ; you should see %-100000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000000000 CODE RRAX_T MOV #$8000,R8 @@ -770,9 +842,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRAX_T ; you should see %-10000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-10000000000000 CODE RRAX_T MOV #$8000,R8 @@ -784,9 +855,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRAX_T ; you should see %-1000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-1000000000000 CODE RRAX_T MOV #$8000,R8 @@ -798,9 +868,8 @@ MOV R8,R14 MOV #%.,R0 ENDCODE -RRAX_T ; you should see %-100000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000 ; ================ ; RLAX test @@ -818,8 +887,6 @@ ENDCODE RLAX_T ; you should see -2 --> -PWR_STATE - ; ================ ; RLAX repeat test ; ================ @@ -837,8 +904,6 @@ ENDCODE RLAX_T ; you should see -2 --> -PWR_STATE - CODE RLAX_T MOV #-1,R8 RPT #2 @@ -851,8 +916,6 @@ ENDCODE RLAX_T ; you should see -4 --> -PWR_STATE - CODE RLAX_T MOV #-1,R8 RPT #3 @@ -865,8 +928,6 @@ ENDCODE RLAX_T ; you should see -8 --> -PWR_STATE - CODE RLAX_T MOV #-1,R8 RPT #8 @@ -879,8 +940,6 @@ ENDCODE RLAX_T ; you should see -256 --> -PWR_STATE - ; ================ ; ADDX test ; ================ @@ -898,8 +957,6 @@ ENDCODE ADDX_T ; you should see -1 --> -PWR_STATE - ; ================ ; ADDX repeat test ; ================ @@ -918,8 +975,6 @@ ENDCODE ADDX_T ; you should see -1 --> -PWR_STATE - CODE ADDX_T MOV #0,R8 MOV #-1,R9 @@ -933,8 +988,6 @@ ENDCODE ADDX_T ; you should see -2 --> -PWR_STATE - CODE ADDX_T MOV #0,R8 MOV #-1,R9 @@ -948,9 +1001,6 @@ ENDCODE ADDX_T ; you should see -8 --> -PWR_STATE - - ; ================ ; SUBX test ; ================ @@ -968,8 +1018,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - ; ================ ; SUBX repeat test ; ================ @@ -988,8 +1036,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - CODE SUBX_T MOV #0,R8 MOV #-1,R9 @@ -1003,8 +1049,6 @@ ENDCODE SUBX_T ; you should see 2 --> -PWR_STATE - CODE SUBX_T MOV #0,R8 MOV #-1,R9 @@ -1018,8 +1062,6 @@ ENDCODE SUBX_T ; you should see 8 --> -PWR_STATE - CODE SUBX_T MOV #15,R10 MOV #0,R8 @@ -1034,8 +1076,6 @@ ENDCODE SUBX_T ; you should see 16 --> -PWR_STATE - CODE SUBX_T MOV #32,R10 MOV #0,R8 @@ -1050,8 +1090,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - CODE SUBX_T MOV #33,R10 MOV #0,R8 @@ -1066,4 +1104,4 @@ ENDCODE SUBX_T ; you should see 2 --> -RST_STATE +{TEST_ASMX} diff --git a/MSP430-FORTH/SD_430FR5994/TSTWORDS.4TH b/MSP430-FORTH/SD_430FR5994/TSTWORDS.4TH new file mode 100644 index 0000000..3fe2fef --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/TSTWORDS.4TH @@ -0,0 +1,215 @@ + + CODE ABORT_TSTWORDS + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_TSTWORDS + + [DEFINED] {TSTWORDS} [IF] {TSTWORDS} [THEN] + + MARKER {TSTWORDS} + + + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,R14 + SUBC R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV #$40B2,-4(R10) + MOV R10,0(R14) + SUB #2,R10 + MOV R10,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH R14 + MOV @R15,R14 + MOV @R1+,0(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BEGIN + [IF] + + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + + RST_SET +LOAD" \misc\TestASM.4th" + +ECHO + + +: LOOP_TEST 8 0 DO I . LOOP +; + +LOOP_TEST + + +: LOOP_TEST1 + BEGIN DUP U. 1 - + ?DUP + 0= UNTIL +; +: FIND_TEST + $20 WORD + 50000 0 + DO + DUP + FIND DROP DROP + LOOP + FIND + 0= IF ABORT" <-- not found !" + ELSE ABORT" <-- found !" + THEN + ; +\ \ No newline at end of file diff --git a/MSP430-FORTH/SD_430FR5994/UARTI2CS.4TH b/MSP430-FORTH/SD_430FR5994/UARTI2CS.4TH new file mode 100644 index 0000000..4abc21f --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/UARTI2CS.4TH @@ -0,0 +1,338 @@ + +; --------------------------------------------------------- +; UARTI2CS.4th for MSP_EXP430FR5994 +; --------------------------------------------------------- + + CODE ABORT_UARTI2CS + SUB #4,R15 + MOV R14,2(R15) + MOV &$180E,R14 + BIT #$3C00,R14 + 0<> IF MOV #0,R14 THEN + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + ABORT" <-- Ouch! unexpected I2C_FastForth target!" + RST_RET + ; + + ABORT_UARTI2CS + + MARKER {UARTI2CS} + 10 ALLOT + + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT + MOV @R15+,R9 + AND @R9,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + HDNCODE I2CM_STOP + BIS.B #2,&$265 + MOV R0,R0 + BIS.B #4,&$265 + MOV R0,R0 + BIC.B #2,&$265 + MOV R0,R0 + BIC.B #4,&$265 + MOV @R1+,R0 + ENDCODE + + CODE REMOVE_U2I +BW1 + BIC.B #1,&$202 + BIC.B #1,&$204 + BIC.B #2,&$202 + BIC.B #2,&$204 + CALL #I2CM_STOP + MOV #6,R10 + BIC.B R10,&$265 + BIS.B R10,&$263 + BIS.B R10,&$267 + MOV #0,&$3C0 + MOV #0,&$3C6 + BIC.B #$80,&$20C + BIC.B #$80,&$204 + BIC.B #$40,&$21A + CMP #$4082,&{UARTI2CS}-2 + 0<> IF + MOV #{UARTI2CS},R10 + MOV #$4082,-2(R10) + MOV @R10+,&$183E + MOV @R10+,&$1840 + MOV @R10+,&$FFF0 + MOV @R10+,&$FFDE + THEN + MOV #1,R14 + MOV #UART_WARM+4,R0 + ENDCODE + + HDNCODE I2CM_START + BIS.B #4,&$265 + BIS.B &{UARTI2CS}+8,R9 + MOV R0,R0 + BIS.B #2,&$265 + MOV.B #8,R10 + BEGIN + ADD.B R9,R9 + U>= IF + BIC.B #4,&$265 + ELSE + BIS.B #4,&$265 + THEN + BIC.B #2,&$265 + BIT.B #4,&$261 + BIS.B #2,&$265 + 0= IF + BIT.B #4,&$265 + 0= IF + BIS.B #6,&$265 + BIC.B #6,&I2CSM_IES + BEGIN + BIT.B #6,&I2CSM_IFG + BIC.B #6,&I2CSM_IFG + 0<> IF + MOV #9,R10 + ELSE + $3C00 , + $3C00 , + THEN + SUB #1,R10 + 0= UNTIL + ADD #2,R1 + MOV @R1+,R0 + THEN + THEN + SUB #1,R10 + 0= UNTIL + BIC.B #4,&$265 + BIC.B #2,&$265 + BEGIN + BIT.B #2,&$261 + 0<> UNTIL + BIT.B #4,&$261 + BIS.B #2,&$265 + MOV @R1+,0(R1) + MOV @R1+,R0 + ENDCODE + + + HDNCODE U2I_TERM_INT + ADD #4,R1 + BEGIN + MOV.B &$5CC,R8 + MOV.B R8,$1CE4(R11) + ADD #1,R11 + CMP.B R8,R12 + 0<> WHILE + CMP #4,R10 + 0<> IF + BEGIN + BIT #2,&$5DC + 0<> UNTIL + MOV.B R8,&$5CE + THEN + BEGIN + BIT #1,&$5DC + 0<> UNTIL + REPEAT + CALL #ACCEPT+$2A + BEGIN + BIT #1,&$5DC + 0<> UNTIL +BW2 + MOV.B &$5CC,R12 + MOV.B R12,$1CE4(R11) + PUSH R0 + MOV #0,R9 + CALL #I2CM_START + 0<> ?GOTO FW2 + BIS.B #1,&$202 + MOV #$1CE4,R8 + BEGIN + MOV.B @R8,R9 + MOV.B #8,R10 + BEGIN + ADD.B R9,R9 + U>= IF + BIC.B #4,&$265 + ELSE + BIS.B #4,&$265 + THEN + BIC.B #2,&$265 + MOV R0,R0 + BIS.B #2,&$265 + SUB #1,R10 + 0= UNTIL + BIC.B #4,&$265 + BIC.B #2,&$265 + BEGIN + BIT.B #2,&$261 + 0<> UNTIL + BIT.B #4,&$261 + BIS.B #2,&$265 + 0= WHILE + CMP.B @R8+,R12 + 0= UNTIL + THEN + BIC.B #1,&$202 + GOTO FW1 + ENDCODE + + HDNCODE 500MS_INT + ADD #4,R1 +FW1 +FW2 + PUSH R0 + BEGIN + BIT #8,&$5CA + 0<> ?GOTO BW1 + BIT.B #$20,&$240 + 0= ?GOTO BW1 + BIC.B #2,&$265 + MOV #1,R9 + CALL #I2CM_START + 0<> IF + CALL #I2CM_STOP + MOV #'.',&$5CE + MOV #$4000,R0 + THEN + BIS.B #2,&$202 + BEGIN + BEGIN + BIC.B #4,&$265 + MOV.B #8,R10 + BEGIN + BIC.B #2,&$265 + BIT.B #4,&$261 + BIS.B #2,&$265 + ADDC.B R9,R9 + SUB #1,R10 + 0= UNTIL + CMP.B #-1,R9 + 0= IF + MOV #2,R9 + THEN + CMP.B #8,R9 + U>= WHILE + BIS.B #4,&$265 + BIC.B #2,&$265 + BEGIN + BIT.B #2,&$261 + 0<> UNTIL + BIS.B #2,&$265 + BEGIN + BIT #2,&$5DC + 0<> UNTIL + MOV.B R9,&$5CE + REPEAT + CMP.B #4,R9 + U>= IF + MOV.B R9,&{UARTI2CS}+9 + BIS.B #4,&$265 + THEN + BIC.B #2,&$265 + BEGIN + BIT.B #2,&$261 + 0<> UNTIL + BIT.B #4,&$261 + BIS.B #2,&$265 + 0<> UNTIL + CMP.B #2,R9 + U>= WHILE + 0= IF + MOV.B #0,&{UARTI2CS}+9 + CALL #KEY+$8 + BEGIN + BIC #1,&$5DC + MOV &$1800,R9 + BEGIN MOV #65,R10 + BEGIN SUB #1,R10 + 0= UNTIL + SUB #1,R9 + 0= UNTIL + BIT #1,&$5DC + 0= UNTIL + THEN + REPEAT + CALL #I2CM_STOP + BIC.B #2,&$202 + CMP.B #0,R9 + 0= IF + MOV #$4000,R0 + THEN + CALL #KEY+$8 + BEGIN + BIT #1,&$5DC + 0<> UNTIL + CALL #ACCEPT+$2A + MOV #0,R11 + GOTO BW2 + ENDCODE + + HDNCODE SLEEP_U2I + $180E $4000 TSTBIT + [IF] MOV #%1_1001_0100,&$3C0 ; if ACLK=LFXTAL + [ELSE] MOV #%1_0001_0100,&$3C0 ; if ACLK=VLO + [THEN] + MOV.B &{UARTI2CS}+9,R10 + MOV #$0D,R12 + MOV #0,R11 + BIC #$40,&$21C + MOV &{UARTI2CS}+2,R0 + ENDCODE + + HDNCODE INIT_U2I + MOV #4096,&$3D2 + MOV #$60,&$3C6 + MOV #4095,&$3D6 + BIS.B #$80,&$204 + BIS.B #$80,&$20C + BIS.B #$40,&$21A + BIC.B #6,&$267 + BIC.B #6,&$263 + BIS.B #1,&$204 + BIS.B #2,&$204 + CALL &{UARTI2CS} + CMP #$0E,R14 + 0<> IF + CMP #$0A,R14 + U>= ?GOTO BW1 + THEN + BIS.B #$40,&$21C + MOV #ALLOT+$8,R0 + ENDCODE + + : UARTI2CS + $0D EMIT $0A EMIT + HI2LO + MOV @R1+,R13 + BEGIN + BIT #1,&$5CA + 0= UNTIL + CMP #$4082,&{UARTI2CS}-2 + 0= IF + MOV #REMOVE_U2I,&{UARTI2CS}-2 + MOV &$183E,&{UARTI2CS} + MOV &$1840,&{UARTI2CS}+2 + MOV &$FFF0,&{UARTI2CS}+4 + MOV &$FFDE,&{UARTI2CS}+6 + MOV R14,&{UARTI2CS}+8 + THEN + MOV #0,R14 + MOV #INIT_U2I,&$183E + MOV #SLEEP_U2I,&$1840 + MOV #U2I_TERM_INT,&$FFF0 + MOV #500MS_INT,&$FFDE + MOV #INIT_U2I,R0 + ENDCODE + + RST_SET ECHO + + $12 UARTI2CS ; TERATERM(Alt-B) or USB_to_I2C_bridge(SW2) to quit diff --git a/MSP430-FORTH/SD_430FR5994/UTILITY.4TH b/MSP430-FORTH/SD_430FR5994/UTILITY.4TH new file mode 100644 index 0000000..fa56409 --- /dev/null +++ b/MSP430-FORTH/SD_430FR5994/UTILITY.4TH @@ -0,0 +1,527 @@ + + +; -------------------------------- +; UTILITY.4th for MSP_EXP430FR5994 +; -------------------------------- + + CODE ABORT_UTILITY + SUB #2,R15 + MOV R14,0(R15) + MOV &$180A,R14 + SUB #309,R14 + COLON + $0D EMIT + ABORT" FastForth V3.9 please!" + RST_RET + ; + + ABORT_UTILITY + + MARKER {UTILITY} + + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @R1+,R13 + MOV @R13+,R0 + + ENDCODE + [THEN] + + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @R15,R10 + MOV R14,0(R15) + MOV R10,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] U< + [IF] + CODE U< + SUB @R15+,R14 + 0<> IF + MOV #-1,R14 + U< IF + AND #0,R14 + THEN + THEN + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] IF + [IF] + CODE IF + SUB #2,R15 + MOV R14,0(R15) + MOV &$1DC8,R14 + ADD #4,&$1DC8 + MOV #$40AC,0(R14) + ADD #2,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE THEN + MOV &$1DC8,0(R14) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] BEGIN [IF] + CODE BEGIN + MOV #$4032,R0 + ENDCODE IMMEDIATE + + CODE UNTIL + MOV #$40AC,R9 +BW1 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + CODE AGAIN + MOV #$40B2,R9 + GOTO BW1 + ENDCODE IMMEDIATE + + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] + HDNCODE XDO + MOV #$8000,R9 + SUB @R15+,R9 + MOV R14,R8 + ADD R9,R8 + PUSHM #2,R9 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + + CODE DO + SUB #2,R15 + MOV R14,0(R15) + ADD #2,&$1DC8 + MOV &$1DC8,R14 + MOV #XDO,-2(R14) + ADD #2,&$1C00 + MOV &$1C00,R10 + MOV #0,0(R10) + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XLOOP + ADD #1,0(R1) +BW1 BIT #$100,R2 + 0= IF + MOV @R13,R13 + MOV @R13+,R0 + THEN + ADD #4,R1 + ADD #2,R13 + MOV @R13+,R0 + ENDCODE + + CODE LOOP + MOV #XLOOP,R9 +BW2 ADD #4,&$1DC8 + MOV &$1DC8,R10 + MOV R9,-4(R10) + MOV R14,-2(R10) + BEGIN + MOV &$1C00,R14 + SUB #2,&$1C00 + MOV @R14,R14 + CMP #0,R14 + 0<> WHILE + MOV R10,0(R14) + REPEAT + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE IMMEDIATE + + HDNCODE XPLOO + ADD R14,0(R1) + MOV @R15+,R14 + GOTO BW1 + ENDCODE + + CODE +LOOP + MOV #XPLOO,R9 + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] + CODE I + SUB #2,R15 + MOV R14,0(R15) + MOV @R1,R14 + SUB 2(R1),R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] + CODE DUP +BW1 SUB #2,R15 + MOV R14,0(R15) + MOV @R13+,R0 + ENDCODE + + CODE ?DUP + CMP #0,R14 + 0<> ?GOTO BW1 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] >R + [IF] + CODE >R + PUSH R14 + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,R15 + MOV R14,0(R15) + MOV @R1+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] + + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,R14 + 0<> IF + PUSH R13 + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,R13 + SUB #1,R14 + 0= UNTIL + MOV @R1+,R13 + THEN + MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 2DUP + [IF] + CODE 2DUP + MOV R14,-2(R15) + MOV @R15,-4(R15) + SUB #4,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] + + [IF] + CODE + + ADD @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] - + [IF] + CODE - + SUB @R15+,R14 + XOR #-1,R14 + ADD #1,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @R14,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] AND + [IF] + CODE AND + AND @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @R15,R10 + MOV R14,0(R15) + MOV 2(R15),R14 + MOV R10,2(R15) + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] + CODE MAX + CMP @R15,R14 + S< ?GOTO FW1 +BW1 ADD #2,R15 + MOV @R13+,R0 + ENDCODE + + CODE MIN + CMP @R15,R14 + S< ?GOTO BW1 +FW1 MOV @R15+,R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] OVER + [IF] + CODE OVER + MOV R14,-2(R15) + MOV @R15,R14 + SUB #2,R15 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV R14,R10 + MOV @R15+,R8 + MOV @R15+,R9 + MOV @R15+,R14 + CMP #0,R10 + 0<> IF + CMP R9,R8 + 0= ?GOTO FW1 + U< IF + BEGIN + MOV.B @R9+,0(R8) + ADD #1,R8 + SUB #1,R10 + 0= UNTIL + MOV @R13+,R0 + ELSE + ADD R10,R8 + ADD R10,R9 + BEGIN + SUB #1,R9 + SUB #1,R8 + MOV.B @R9,0(R8) + SUB #1,R10 + 0= UNTIL + THEN + THEN +FW1 MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV R14,-2(R10) + MOV @R15+,R14 + MOV @R1+,R13 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] BASE + [IF] + $1DBE CONSTANT BASE + [THEN] + + [UNDEFINED] .S + [IF] + CODE .S + MOV R14,-2(R15) + MOV R15,R14 + SUB #2,R14 + MOV R14,-6(R15) + MOV #$1C80,R14 + SUB #2,R14 +BW1 MOV R14,-4(R15) + SUB #6,R15 + SUB @R15,R14 + RRA R14 + COLON + $3C EMIT + . + $08 EMIT + $3E EMIT SPACE + 2DUP 1+ + U< IF + DROP DROP EXIT + THEN + BASE @ >R + $10 BASE ! + DO + '$' EMIT + I @ U. + 2 +LOOP + R> BASE ! + ; + [THEN] + + [UNDEFINED] .RS + [IF] + CODE .RS + MOV R14,-2(R15) + MOV R1,-6(R15) + MOV #$1CE0,R14 + GOTO BW1 + ENDCODE + [THEN] + + [UNDEFINED] ? + [IF] + CODE ? + MOV @R14,R14 + MOV #U.,R0 + ENDCODE + [THEN] + + [UNDEFINED] CR + [IF] + + CODE CR + MOV #$40B4,R0 + ENDCODE + + :NONAME + $0D EMIT $0A EMIT + ; IS CR + [THEN] + + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA R14 + MOV @R13+,R0 + ENDCODE + [THEN] + + [UNDEFINED] WORDS + [IF] + : WORDS + CR + $1DCE @ $1CE4 + $180C @ DUP + + MOVE + BEGIN + 0 DUP + $180C @ DUP + 0 + DO + DUP I $1CE4 + @ + U< IF + DROP DROP + I DUP + $1CE4 + @ + THEN + 2 +LOOP + ?DUP + WHILE + DUP + 2 - @ + ROT + $1CE4 + + ! + COUNT 2/ + DUP >R TYPE + R> $10 SWAP - SPACES + REPEAT + DROP + ; + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] DUMP + [IF] + CODE DUMP + PUSH R13 + PUSH &$1DBE + MOV #$10,&$1DBE + ADD @R15,R14 + LO2HI + SWAP + $FFF0 AND + DO CR + I 4 U.R SPACE + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! + ; + [THEN] + + RST_SET + + [THEN] ECHO ; endof [UNDEFINED] {TOOLS} + diff --git a/MSP430-FORTH/SD_TEST.f b/MSP430-FORTH/SD_TEST.f index 643aa3f..c9bce05 100644 --- a/MSP430-FORTH/SD_TEST.f +++ b/MSP430-FORTH/SD_TEST.f @@ -44,12 +44,12 @@ \ FREQUENCY .equ 16 \ THREADS .equ 16 \ TERMINALBAUDRATE .equ what_you_want -\ +\ \ uncomment: CONDCOMP \ MSP430ASSEMBLER \ SD_CARD_LOADER \ SD_CARD_READ_WRITE -\ +\ \ compile for your target (CTRL+0) \ \ program your target via TI interface (CTRL+1) @@ -79,112 +79,118 @@ \ copy RTC.f to \RTC.4TH ( doesn't work with if FR2xxx or FR4xxx) \ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_SD_TEST -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_SD_TEST definition before resuming -; - -ABORT_SD_TEST - -PWR_STATE - -[DEFINED] {SD_TEST} [IF] {SD_TEST} [THEN] \ remove it if defined out of kernel - -MARKER {SD_TEST} + CODE ABORT_SD_TEST + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + [UNDEFINED] WRITE + [IF] + 1 ABORT" no SD_CARD_READ_WRITE addon!" + [THEN] + RST_RET \ remove ABORT_SD_TEST definition before resuming + ; + + ABORT_SD_TEST + + MARKER {SD_TEST} -[UNDEFINED] EXIT [IF] \ https://forth-standard.org/standard/core/EXIT \ EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles) \ JMP #EXIT performs EXIT -CODE EXIT -MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack -MOV @IP+,PC \ 4 = NEXT - \ 6 (ITC-2) -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack + MOV @IP+,PC \ 4 = NEXT + ENDCODE \ 6 (ITC-2) + [THEN] + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] >BODY [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toBODY \ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] >BODY + [IF] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] 0= [IF] \ https://forth-standard.org/standard/core/ZeroEqual \ 0= n/u -- flag return true if TOS=0 -CODE 0= -SUB #1,TOS \ borrow (clear cy) if TOS was 0 -SUBC TOS,TOS \ TOS=-1 if borrow was set -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] IF [IF] \ define IF and THEN + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,TOS \ borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF and THEN + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] ELSE [IF] + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/ELSE \ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -CODE ELSE \ immediate -ADD #4,&DP \ make room to compile two words -MOV &DP,W \ W=HERE+4 -MOV #BRAN,-4(W) -MOV W,0(TOS) \ HERE+4 ==> [IFadr] -SUB #2,W \ HERE+2 -MOV W,TOS \ -- ELSEadr -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + [UNDEFINED] ELSE + [IF] + CODE ELSE \ immediate + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/BEGIN \ BEGIN -- BEGINadr initialize backward branch -CODE BEGIN + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + CODE BEGIN MOV #HEREXEC,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/UNTIL \ UNTIL BEGINadr -- resolve conditional backward branch -CODE UNTIL \ immediate + CODE UNTIL \ immediate MOV #QFBRAN,X BW1 ADD #4,&DP \ compile two words MOV &DP,W \ W = HERE @@ -192,385 +198,462 @@ BW1 ADD #4,&DP \ compile two words MOV TOS,-2(W) \ compile bakcward adr at HERE+2 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/AGAIN \ AGAIN BEGINadr -- resolve uncondionnal backward branch -CODE AGAIN \ immediate -MOV #BRAN,X -GOTO BW1 -ENDCODE IMMEDIATE + CODE AGAIN \ immediate + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/WHILE \ WHILE BEGINadr -- WHILEadr BEGINadr -: WHILE \ immediate -POSTPONE IF SWAP -; IMMEDIATE + : WHILE \ immediate + POSTPONE IF SWAP + ; IMMEDIATE \ https://forth-standard.org/standard/core/REPEAT \ REPEAT WHILEadr BEGINadr -- resolve WHILE loop -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W - MOV X,-4(W) \ xloop --> HERE - MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP \ immediate -MOV #XPLOOP,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 \ goto BW1 LOOP + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] + [IF] + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] \ define MAX and MIN + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] \ define MAX and MIN CODE MAX \ n1 n2 -- n3 signed maximum - CMP @PSP,TOS \ n2-n1 - S< ?GOTO FW1 \ n2<n1 -BW1 ADD #2,PSP - MOV @IP+,PC + CMP @PSP,TOS \ n2-n1 + S< ?GOTO FW1 \ n2<n1 +BW1 ADD #2,PSP + MOV @IP+,PC ENDCODE CODE MIN \ n1 n2 -- n3 signed minimum - CMP @PSP,TOS \ n2-n1 - S< ?GOTO BW1 \ n2<n1 -FW1 MOV @PSP+,TOS - MOV @IP+,PC + CMP @PSP,TOS \ n2-n1 + S< ?GOTO BW1 \ n2<n1 +FW1 MOV @PSP+,TOS + MOV @IP+,PC ENDCODE -[THEN] + [THEN] -[UNDEFINED] C@ [IF] \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SPACE [IF] \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -$20 EMIT ; -[THEN] + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + NEXT + ENDCODE + [THEN] -[UNDEFINED] DUP [IF] \ define DUP and DUP? \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP + [IF] \ define DUP and DUP? + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] CONSTANT [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] STATE [IF] +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/STATE \ STATE -- a-addr holds compiler state -STATEADR CONSTANT STATE -[THEN] - -[UNDEFINED] IS [IF] \ define DEFER! and IS -\ https://forth-standard.org/standard/core/DEFERStore -\ Set the word xt1 to execute xt2. An ambiguous condition exists if xt1 is not for a word defined by DEFER. -CODE DEFER! \ xt2 xt1 -- -MOV @PSP+,2(TOS) \ -- xt1=CFA_DEFER xt2 --> [CFA_DEFER+2] -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE - -\ https://forth-standard.org/standard/core/IS -\ IS <name> xt -- -\ used as is : -\ DEFER DISPLAY create a "do nothing" definition (2 CELLS) -\ inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -\ or in a definition : ... ['] U. IS DISPLAY ... -\ KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words -: IS -STATE @ -IF POSTPONE ['] POSTPONE DEFER! -ELSE ' DEFER! -THEN -; IMMEDIATE -[THEN] - -[UNDEFINED] U.R [IF] \ defined in {UTILITY} -: U.R \ u n -- display u unsigned in n width (n >= 2) ->R <# 0 # #S #> -R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DUMP [IF] \ defined in {UTILITY} -\ https://forth-standard.org/standard/tools/DUMP -CODE DUMP \ adr n -- dump memory -PUSH IP -PUSH &BASEADR \ save current base -MOV #$10,&BASEADR \ HEX base -ADD @PSP,TOS \ -- ORG END -LO2HI - SWAP \ -- END ORG - DO CR \ generate line - I 4 U.R SPACE \ generate address - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I \ display 16 chars - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> BASEADR ! \ restore current base -; -[THEN] - -[UNDEFINED] HERE [IF] -CODE HERE -MOV #BEGIN,PC -ENDCODE -[THEN] - + [UNDEFINED] STATE + [IF] + STATEADR CONSTANT STATE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + +\ DEFER CR \ DEFERed definition, by default executes that of :NONAME +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE -\ SD_EMIT c -- output char c to a SD_CARD file opened as write -CODE SD_EMIT -CMP #512,&BufferPtr \ 512 bytes by sector -U>= IF \ if file buffer is full - MOV #WRITE,X \ CALL #Write_File - CALL 2(X) \ BufferPtr = 0 -THEN -MOV &BufferPtr,Y \ 3 -MOV.B TOS,SD_BUF(Y) \ 3 -ADD #1,&BufferPtr \ 4 -MOV @PSP+,TOS \ 2 -MOV @IP+,PC -ENDCODE - -: SD_TEST -PWR_HERE \ remove all volatile programs from MAIN memory -CR -." 0 Set date and time" CR -." 1 Load {TOOLS} words" CR -." 2 Load {SD_TOOLS} words" CR -." 3 Load {CORE_COMP} words" CR -." 4 Load ANS core tests" CR -." 5 Load a 100k program " CR -." 6 Read only this source file" CR -." 7 append a dump of FORTH to YOURFILE.TXT" CR -." 8 delete YOURFILE.TXT" CR -." 9 Load TST_WORDS" CR -." your choice : " -KEY -48 - ?DUP -0= IF - ." LOAD RTC.4TH" CR - LOAD" RTC.4TH" -ELSE 1 - ?DUP - 0= IF - ." LOAD UTILITY.4TH" CR - LOAD" UTILITY.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD SD_TOOLS.4TH" CR - LOAD" SD_TOOLS.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD CORE_ANS.4TH" CR - LOAD" CORE_ANS.4TH" - ELSE 1 - ?DUP - 0= IF - ." LOAD CORETEST.4TH" CR - LOAD" CORETEST.4TH" - PWR_STATE - ELSE 1 - ?DUP - 0= IF - ." LOAD PROG100K.4TH" CR - NOECHO - LOAD" PROG100K.4TH" - ELSE 1 - ?DUP - 0= IF - ." READ PROG100K.4TH" CR - READ" PROG100K.4TH" - BEGIN - READ \ sequentially read 512 bytes - UNTIL \ prog100k.4TH is closed - ELSE 1 - ?DUP - 0= IF - ." WRITE YOURFILE.TXT" CR - WRITE" YOURFILE.TXT" - ['] SD_EMIT IS EMIT -\ ." va te faire voir" - MAIN_ORG HERE OVER - DUMP - ['] EMIT >BODY IS EMIT - CLOSE - ELSE 1 - ?DUP - 0= IF - ." DEL YOURFILE.TXT" CR - DEL" YOURFILE.TXT" - ELSE 1 - ?DUP - 0= IF - ." LOAD TSTWORDS.4TH" CR - LOAD" TSTWORDS.4TH" - ELSE - ." abort" ABORT" " - THEN - THEN - THEN - THEN - THEN - THEN - THEN - THEN - THEN -THEN -; + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + + [UNDEFINED] U.R + [IF] \ defined in {UTILITY} + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + +\ https://forth-standard.org/standard/core/BASE +\ BASE -- a-addr holds conversion radix + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] +\ https://forth-standard.org/standard/tools/DUMP + [UNDEFINED] DUMP + [IF] \ defined in {UTILITY} + CODE DUMP \ adr n -- dump memory + PUSH IP + PUSH &BASE \ save current base + MOV #$10,&BASE \ HEX base + ADD @PSP,TOS \ -- ORG END + LO2HI + SWAP \ -- END ORG + DO \ generate line + I 4 U.R SPACE \ generate address + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I \ display 16 chars + DO I C@ $7E MIN $20 MAX EMIT LOOP + CR + $10 +LOOP + R> BASE ! \ restore current base + ; + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #BEGIN,PC + ENDCODE + [THEN] -RST_HERE +\ https://forth-standard.org/standard/core/DROP +\ DROP x -- drop top of stack + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/OnePlus +\ 1+ n1/u1 -- n2/u2 add 1 to TOS + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/Equal +\ = x1 x2 -- flag test x1=x2 + [UNDEFINED] = + [IF] + CODE = + SUB @PSP+,TOS \ 2 + 0<> IF \ 2 + AND #0,TOS \ 1 + MOV @IP+,PC \ 4 + THEN + XOR #-1,TOS \ 1 flag Z = 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CASE + [UNDEFINED] CASE + [IF] + : CASE + 0 + ; IMMEDIATE \ -- #of-1 + +\ https://forth-standard.org/standard/core/OF + : OF \ #of-1 -- orgOF #of + 1+ \ count OFs + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE OVER + POSTPONE = \ copy and test case value + POSTPONE IF \ add orig to control flow stack + POSTPONE DROP \ discards case value if = + R> \ we can bring count back now + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/ENDOF + : ENDOF \ orgOF #of -- orgENDOF #of + >R \ move off the stack in case the control-flow stack is the data stack. + POSTPONE ELSE + R> \ we can bring count back now + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/ENDCASE + : ENDCASE \ orgENDOF1..orgENDOFn #of -- + POSTPONE DROP + 0 DO + POSTPONE THEN + LOOP + ; IMMEDIATE + [THEN] -[THEN] +\ SD_EMIT c -- output char c to a SD_CARD file opened as write + CODE SD_EMIT + CMP #$200,&BufferPtr \ 512 bytes by sector + U>= IF \ if file buffer is full + CALL &WRITE+2 \ CALL #Write_File ; BufferPtr = 0 + THEN + MOV &BufferPtr,Y \ 3 + MOV.B TOS,SD_BUF(Y) \ 3 + ADD #1,&BufferPtr \ 4 + MOV @PSP+,TOS \ 2 + MOV @IP+,PC + ENDCODE -ECHO SD_TEST + : DOESWRITE + ['] SD_EMIT IS EMIT + MAIN_ORG HERE OVER - DUMP + ['] EMIT >BODY IS EMIT + CLOSE + ; + + : SD_TEST + ECHO + 'CR' EMIT + CR + ." ----------" CR + ." Bootloader" CR + ." ----------" CR + ." ? Fast Forth Specifs" CR + ." 0 Set date and time" CR + ." 1 Load {UTILITY} words" CR + ." 2 Load {SD_TOOLS} words" CR + ." 3 Load {CORE_COMP} words" CR + ." 4 Load ANS core tests" CR + ." 5 Load a source file to make 10k program" CR + ." 6 Read it only (47k)" CR + ." 7 write FORTH dump in YOURFILE.TXT" CR + ." 8 append FORTH dump to YOURFILE.TXT" CR + ." 9 delete YOURFILE.TXT" CR + ." your choice: " + KEY DUP EMIT + NOECHO + {SD_TEST} \ remove {SD_TEST} application + CASE + '?' OF LOAD" FF_SPECS.4TH" ENDOF \ + '0' OF LOAD" RTC.4TH" ENDOF + '1' OF LOAD" UTILITY.4TH" ENDOF + '2' OF LOAD" SD_TOOLS.4TH" ENDOF + '3' OF LOAD" CORE_ANS.4TH" ENDOF + '4' OF LOAD" CORETEST.4TH" ENDOF + '5' OF LOAD" PROG10K.4TH" ENDOF \ download one ko, so no erasure here + '6' OF READ" PROG10K.4TH" + BEGIN READ \ sequentially read 512 bytes + UNTIL ENDOF \ prog10k.4TH is closed + '7' OF WRITE" YOURFILE.TXT" + DOESWRITE ENDOF + '8' OF APPEND" YOURFILE.TXT" + DOESWRITE ENDOF + '9' OF DEL" YOURFILE.TXT" ENDOF + ENDCASE + CR + ; + +SD_TEST diff --git a/MSP430-FORTH/SD_TOOLS.f b/MSP430-FORTH/SD_TOOLS.f index 32387e4..a57ed65 100644 --- a/MSP430-FORTH/SD_TOOLS.f +++ b/MSP430-FORTH/SD_TOOLS.f @@ -38,300 +38,366 @@ \ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0< ; --------------------------------------------------------------- -; SD_TOOLS.f : BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER +; SD_TOOLS.f +; BASIC TOOLS for SD Card : DIR FAT SECTOR CLUSTER ; --------------------------------------------------------------- \ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_SD_TOOLS -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_UARTI2CS definition before resuming -; - -ABORT_SD_TOOLS - - -[DEFINED] {SD_TOOLS} [IF] {SD_TOOLS} [THEN] - -[UNDEFINED] {SD_TOOLS} [IF] - -MARKER {SD_TOOLS} + CODE ABORT_SD_TOOLS + SUB #4,PSP + MOV TOS,2(PSP) + [UNDEFINED] LOAD" \ " + [IF] + MOV #-1,0(PSP) + [ELSE] + MOV #0,0(PSP) + [THEN] + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + ABORT" Builds FastForth with SD_CARD_LOADER addon.." + RST_RET \ remove ABORT_UARTI2CS definition before resuming + ; + + ABORT_SD_TOOLS + + MARKER {SD_TOOLS} + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #HEREXEC,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/AND +\ C AND x1 x2 -- x3 logical AND + [UNDEFINED] AND + [IF] + CODE AND + AND @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] \ define MAX and MIN + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -CODE MAX \ n1 n2 -- n3 signed maximum + [UNDEFINED] MAX + [IF] \ define MAX and MIN + CODE MAX \ n1 n2 -- n3 signed maximum CMP @PSP,TOS \ n2-n1 S< ?GOTO FW1 \ n2<n1 BW1 ADD #2,PSP MOV @IP+,PC -ENDCODE + ENDCODE -CODE MIN \ n1 n2 -- n3 signed minimum + CODE MIN \ n1 n2 -- n3 signed minimum CMP @PSP,TOS \ n2-n1 S< ?GOTO BW1 \ n2<n1 FW1 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE + ENDCODE + [THEN] -[THEN] - -[UNDEFINED] C@ [IF] \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SPACE [IF] \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -$20 EMIT ; -[THEN] + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + NEXT + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] OVER [IF] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] >R [IF] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] - [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] \ defined in {UTILITY} -: U.R \ u n -- display u unsigned in n width (n >= 2) - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] \ defined in {UTILITY} + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W - MOV X,-4(W) \ xloop --> HERE - MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 \ goto BW1 LOOP -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 \ goto BW1 LOOP + ENDCODE IMMEDIATE + [THEN] + -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] DUMP [IF] \ defined in {UTILITY} + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] +\ create a primary defered word, i.e. with its default runtime beginning at the >BODY of the definition + CODE CR \ part I : DEFERed definition of CR + MOV #NEXT_ADR,PC \ [PFA] = NEXT_ADR + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + \ https://forth-standard.org/standard/tools/DUMP -CODE DUMP \ adr n -- dump memory -PUSH IP -PUSH &BASEADR \ save current base -MOV #$10,&BASEADR \ HEX base -ADD @PSP,TOS \ -- ORG END -LO2HI - SWAP \ -- END ORG - DO CR \ generate line - I 4 U.R SPACE \ generate address - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I \ display 16 chars - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> BASEADR ! \ restore current base -; -[THEN] + [UNDEFINED] DUMP + [IF] \ defined in {UTILITY} + CODE DUMP \ adr n -- dump memory + PUSH IP + PUSH &BASEADR \ save current base + MOV #$10,&BASEADR \ HEX base + ADD @PSP,TOS \ -- ORG END + LO2HI + SWAP \ -- END ORG + $FFF0 AND \ -- END ORG_modulo_16 + DO CR \ generate line + I 4 U.R SPACE \ generate address + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I \ display 16 chars + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASEADR ! \ restore current base + ; + [THEN] \ display content of a sector -\ ----------------------------------\ -CODE SECTOR. \ sector. -- don't forget to add decimal point to your sector number -\ ----------------------------------\ +\ --------------------------------\ + CODE SECTOR. \ sector. -- don't forget to add decimal point to your sector number +\ --------------------------------\ BW1 MOV TOS,X \ X = SectorH MOV @PSP,W \ W = sectorL - CALL #READ_SWX \ W = SectorLO X = SectorHI -COLON \ - <# #S #> TYPE SPACE \ ud -- display the double number + CALL #R_SECT_WX \ W = SectorLO X = SectorHI + COLON \ + SPACE <# #S #> TYPE \ ud -- display the double number SD_BUF $200 DUMP CR ; \ then dump the sector -\ ----------------------------------\ +\ --------------------------------\ \ display first sector of a Cluster -\ ----------------------------------\ -CODE CLUSTR. \ cluster. -- don't forget to add decimal point to your cluster number -\ ----------------------------------\ +\ --------------------------------\ + CODE CLUSTER. \ cluster. -- don't forget to add decimal point to your cluster number +\ --------------------------------\ BW2 BIT.B #CD_SD,&SD_CDIN \ test Card Detect: memory card present ? - 0<> IF - MOV #COLD,PC \ no: force COLD + 0<> IF \ no: force COLD + MOV #COLD,PC \ no THEN MOV.B &SecPerClus,W \ SecPerClus(54321) = multiplicator MOV @PSP,X \ X = ClusterL - GOTO FW1 \ BEGIN + RRA W \ shift one right multiplicator + U< WHILE \ carry clear ADD X,X \ (RLA) shift one left MULTIPLICANDlo16 ADDC TOS,TOS \ (RLC) shift one left MULTIPLICANDhi8 -FW1 RRA W \ shift one right multiplicator - U>= UNTIL \ carry set + REPEAT ADD &OrgClusters,X \ add OrgClusters = sector of virtual cluster 0 (word size) - MOV X,0(PSP) + MOV X,0(PSP) ADDC #0,TOS \ don't forget carry GOTO BW1 \ jump to SECTOR -ENDCODE -\ ----------------------------------\ + ENDCODE +\ --------------------------------\ -\ ----------------------------------\ -CODE FAT \ Display CurFATsector -\ ----------------------------------\ +\ --------------------------------\ + CODE FAT \ Display FATsector +\ --------------------------------\ SUB #4,PSP \ MOV TOS,2(PSP) \ MOV &OrgFAT1,0(PSP) \ MOV #0,TOS \ FATsectorHI = 0 GOTO BW1 \ jump to SECTOR -ENDCODE -\ ----------------------------------\ + ENDCODE +\ --------------------------------\ -\ ----------------------------------\ -CODE DIR \ Display CurrentDir first sector -\ ----------------------------------\ +\ --------------------------------\ + CODE DIR \ Display CurrentDir first sector +\ --------------------------------\ SUB #4,PSP \ MOV TOS,2(PSP) \ save TOS MOV &DIRclusterL,0(PSP) \ MOV &DIRclusterH,TOS \ - CMP #0,TOS - 0<> ?GOTO BW2 \ jump to CLUSTER - CMP #1,0(PSP) \ cluster 1 ? - 0<> ?GOTO BW2 \ jump to CLUSTER - MOV &OrgRootDir,0(PSP) \ if yes, special case of FAT16 OrgRootDir - GOTO BW1 \ jump to SECTOR -ENDCODE -\ ----------------------------------\ - - -RST_HERE - -[THEN] -ECHO + GOTO BW2 \ jump to SECTOR + ENDCODE +\ --------------------------------\ + RST_SET ECHO diff --git a/MSP430-FORTH/SendSourceFileToTarget.bat.lnk b/MSP430-FORTH/SendSourceFileToTarget.bat.lnk index ba75eda9813714b1c2912a9069639038e5be382d..1fc31c35605a30e34185c1c8b85bb76207af42ec 100644 GIT binary patch delta 406 zcmdnV@swkNh~jJp4h97V1_q4>LaK#3t}w#rhRC3pwzZcT3n!Wy)JIvx0F|JF5C%iA zkewg9y#PaUeqLH;Is=0p11AFu!~1=9emCtvGI~HYRU#mT*<jTOf-#hzA(<hcA&()A zA(H{9l|hW5iNT1Wkdc8Q!e>IQ0z<H?pG&ZRor#g2lVb=2P#MhVS3sj**@29n05+Nr zVJeu_Fm1-<vy7(k3=A?rek~A#XeO{6gaGlQf!H31nSmH&j13TjRK>&uIO}@3I{Nu~ z#yIEXm!<@lB$j06=fxBh<!7aq6vyNi7nm3uFhotB!k8z_$q>b0#Snw+mC1}uh6W9H s*B!`Lc`4Y{y@YA!(iO`N-CiZRGV`Iw+yhO|?{t)%N0;B6#B`kz0H5Mu*8l(j delta 356 zcmaFLv6Ewhh+;Pb2ZI6w1A}0k*pbMYR~TWmsNnK5H9M{_W==FUsCTl80V+WUAq<9K zp*lY+Ujc^X{JgZxbOr`H22KVRhWGoX`c_Q>$>;&q1PXu@ih@-mhzU>m8Iu|E8S)s? z7%~}vS{cL`niz~2G8uuU_=S5ZFa*2$xdi*ynHcFgIfgI*mBEazo;20BdJ@R!3Bn)) zB|!udc-=dHvIL{GV=7Qg28fxE<Uo99AXW!rW*`;;Vih0;sfvjSaMty5b@cP~j7iTd zVQ`wfhB0rl9+QEA^u4qx_rqQacC9JsKC8N5<)PcFBv)oW^q6~~>G_?Gvh(QjoBNoq GGXenBN>rEt diff --git a/MSP430-FORTH/TESTASM.F b/MSP430-FORTH/TESTASM.F index 26c3abb..7a6cb47 100644 --- a/MSP430-FORTH/TESTASM.F +++ b/MSP430-FORTH/TESTASM.F @@ -29,126 +29,138 @@ \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack \ \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= -\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0< +\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0< \ \ FORTH conditionnal : 0= 0< = < > U< \ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_TEST_ASM -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_TEST_ASM definition before resuming -; + CODE ABORT_TEST_ASM + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_TEST_ASM definition before resuming + ; -ABORT_TEST_ASM \ abort test + ABORT_TEST_ASM \ abort test -[UNDEFINED] >R [IF] + MARKER {TEST_ASM} + + [UNDEFINED] >R + [IF] \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] R> [IF] + [UNDEFINED] R> + [IF] \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -MOV rDOVAR,PC -ENDCODE -[THEN] + CODE R> + MOV rDOVAR,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] + [UNDEFINED] + + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] + [UNDEFINED] - + [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SWAP [IF] + [UNDEFINED] SWAP + [IF] \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] MAX [IF] \ MAX and MIN are defined in {UTILITY} + [UNDEFINED] MAX + [IF] \ MAX and MIN are defined in {UTILITY} -CODE MAX \ n1 n2 -- n3 signed maximum + CODE MAX \ n1 n2 -- n3 signed maximum CMP @PSP,TOS \ n2-n1 S< ?GOTO FW1 \ n2<n1 BW1 ADD #2,PSP MOV @IP+,PC -ENDCODE + ENDCODE -CODE MIN \ n1 n2 -- n3 signed minimum + CODE MIN \ n1 n2 -- n3 signed minimum CMP @PSP,TOS \ n2-n1 S< ?GOTO BW1 \ n2<n1 FW1 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE + ENDCODE -[THEN] + [THEN] -[UNDEFINED] C@ [IF] + [UNDEFINED] C@ + [IF] \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] VARIABLE [IF] + [UNDEFINED] VARIABLE + [IF] \ https://forth-standard.org/standard/core/VARIABLE \ VARIABLE <name> -- define a Forth VARIABLE -: VARIABLE -CREATE -HI2LO -MOV #$1287,-4(W) \ CFA = CALL rDOVAR -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] + : VARIABLE + CREATE + HI2LO + MOV #$1287,-4(W) \ CFA = CALL rDOVAR + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CONSTANT [IF] + [UNDEFINED] CONSTANT + [IF] \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] +\ CONSTANT <name> n -- define a Forth CONSTANT + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] DEFER [IF] + [UNDEFINED] DEFER + [IF] \ https://forth-standard.org/standard/core/DEFER \ DEFER "<spaces>name" -- \Skip leading space delimiters. Parse name delimited by a space. @@ -157,217 +169,345 @@ ENDCODE \name Execution: -- \Execute the xt that name is set to execute, i.e. NEXT (nothing), \until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name. -: DEFER -CREATE -HI2LO -MOV #$4030,-4(W) \ CFA = MOV @PC+,PC = BR MOV @IP+,PC -MOV #NEXT_ADR,-2(W) \ PFA = address of MOV @IP+,PC to do nothing. -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] + : DEFER + CREATE + HI2LO + MOV #$4030,-4(W) \ CFA = MOV @PC+,PC = BR MOV @IP+,PC + MOV #NEXT_ADR,-2(W) \ PFA = address of MOV @IP+,PC to do nothing. + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] >BODY [IF] + [UNDEFINED] >BODY + [IF] \ https://forth-standard.org/standard/core/toBODY \ >BODY -- addr leave BODY of a CREATEd word\ also leave default ACTION-OF primary DEFERred word -CODE >BODY -ADD #4,TOS -MOV @IP+,PC -ENDCODE -[THEN] + CODE >BODY + ADD #4,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SPACE [IF] + [UNDEFINED] SPACE + [IF] \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -$20 EMIT ; -[THEN] + : SPACE + $20 EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] + [UNDEFINED] SPACES + [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] \ define DUP and ?DUP + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + NEXT + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] \ define DUP and ?DUP \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] OVER [IF] + [UNDEFINED] OVER + [IF] \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] \ defined in {UTILITY} + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + [UNDEFINED] IF + [IF] \ define IF THEN + + CODE IF + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE -[UNDEFINED] U.R [IF] \ defined in {UTILITY} -: U.R \ u n -- display u unsigned in n width (n >= 2) - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/SWAP +\ SWAP x1 x2 -- x2 x1 swap top two items + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH TOS \ 3 + MOV @PSP,TOS \ 2 + MOV @RSP+,0(PSP) \ 4 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/BEGIN +\ BEGIN -- BEGINadr initialize backward branch + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + + CODE BEGIN + MOV #HEREXEC,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/UNTIL +\ UNTIL BEGINadr -- resolve conditional backward branch + CODE UNTIL + MOV #QFBRAN,X +BW1 ADD #4,&DP \ compile two words + MOV &DP,W \ W = HERE + MOV X,-4(W) \ compile Bran or QFBRAN at HERE + MOV TOS,-2(W) \ compile bakcward adr at HERE+2 + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/AGAIN +\ AGAIN BEGINadr -- resolve uncondionnal backward branch + CODE AGAIN + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/WHILE +\ WHILE BEGINadr -- WHILEadr BEGINadr + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/REPEAT +\ REPEAT WHILEadr BEGINadr -- resolve WHILE loop + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP -[UNDEFINED] DO [IF] \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0, init + MOV @IP+,PC + ENDCODE IMMEDIATE -[UNDEFINED] LOOP [IF] \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W MOV X,-4(W) \ xloop --> HERE MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] + ENDCODE IMMEDIATE -[UNDEFINED] +LOOP [IF] \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP \ immediate -MOV #XPLOOP,X -GOTO BW1 -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] I [IF] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + [UNDEFINED] I + [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] DUMP [IF] \ defined in {UTILITY} + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/BASE +\ BASE -- a-addr holds conversion radix + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + DEFER CR \ DEFERed definition, by default executes that of :NONAME + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + + [UNDEFINED] DUMP + [IF] \ defined in {UTILITY} \ https://forth-standard.org/standard/tools/DUMP -CODE DUMP \ adr n -- dump memory -PUSH IP -PUSH &BASEADR \ save current base -MOV #$10,&BASEADR \ HEX base -ADD @PSP,TOS \ -- ORG END -LO2HI - SWAP \ -- END ORG - DO CR \ generate line - I 4 U.R SPACE \ generate address - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I \ display 16 chars - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> BASEADR ! \ restore current base -; -[THEN] + CODE DUMP \ adr n -- dump memory + PUSH IP + PUSH &BASE \ save current base + MOV #$10,&BASEADR \ HEX base + ADD @PSP,TOS \ -- ORG END + LO2HI + SWAP \ -- END ORG + DO CR \ generate line + I 4 U.R SPACE \ generate address + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I \ display 16 chars + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! \ restore current base + ; + [THEN] \ ----------------------------------------------------------------------- \ test CPUx instructions PUSHM, POPM, RLAM, RRAM, RRCM, RRUM \ ----------------------------------------------------------------------- -CODE TESTPUSHM + CODE TESTPUSHM BW1 -\ PUSHM #16,R14 \ uncomment to test error "out of bounds" -\ PUSHM #2,R0 \ uncomment to test error "out of bounds" -\ PUSHM #0,IP \ uncomment to test error "out of bounds" -\ POPM #17,R15 \ uncomment to test error "out of bounds" -\ POPM #2,R0 \ uncomment to test error "out of bounds" -\ POPM #0,IP \ uncomment to test error "out of bounds" - MOV #22222,Y - MOV #3,X - MOV #2,W - MOV #1,T - MOV #0,S - - PUSHM #4,IP \ PUSHM IP,S,T,W - POPM #4,IP \ POPM W,T,S,IP - SUB #10,PSP - MOV TOS,8(PSP) \ save old TOS - MOV S,6(PSP) - MOV T,4(PSP) - MOV W,2(PSP) - MOV X,0(PSP) - MOV Y,TOS -\ RLAM #0,TOS \ uncomment to test error "out of bounds" -\ RLAM #5,TOS \ uncomment to test error "out of bounds" - RRAM #1,TOS \ 0 < shift value < 5 - RLAM #2,TOS - RRCM #1,TOS - RRUM #1,TOS - COLON \ high level part of the word starts here... - space . . . . . - ; \ and finishes here. - \ -TESTPUSHM ; you should see 11111 3 2 1 0 --> - -CODE TESTPOPM +\ PUSHM #16,R14 \ uncomment to test error "out of bounds" +\ PUSHM #2,R0 \ uncomment to test error "out of bounds" +\ PUSHM #0,IP \ uncomment to test error "out of bounds" +\ POPM #17,R15 \ uncomment to test error "out of bounds" +\ POPM #2,R0 \ uncomment to test error "out of bounds" +\ POPM #0,IP \ uncomment to test error "out of bounds" + MOV #22222,Y + MOV #3,X + MOV #2,W + MOV #1,T + MOV #0,S + + PUSHM #4,IP \ PUSHM IP,S,T,W + POPM #4,IP \ POPM W,T,S,IP + SUB #10,PSP + MOV TOS,8(PSP) \ save old TOS + MOV S,6(PSP) + MOV T,4(PSP) + MOV W,2(PSP) + MOV X,0(PSP) + MOV Y,TOS +\ RLAM #0,TOS \ uncomment to test error "out of bounds" +\ RLAM #5,TOS \ uncomment to test error "out of bounds" + RRAM #1,TOS \ 0 < shift value < 5 + RLAM #2,TOS + RRCM #1,TOS + RRUM #1,TOS + COLON \ high level part of the word starts here... + space . . . . . + ; \ and finishes here. + + TESTPUSHM ; you should see 11111 3 2 1 0 --> + + CODE TESTPOPM GOTO BW1 \ JMP TESTPUSHM -ENDCODE + ENDCODE - \ -TESTPOPM ; you should see 11111 3 2 1 0 --> + TESTPOPM ; you should see 11111 3 2 1 0 --> @@ -375,48 +515,48 @@ TESTPOPM ; you should see 11111 3 2 1 0 --> \ test symbolic branch in assembler \ test a FORTH section encapsulated in an assembly word \ ----------------------------------------------------------------------- -CODE TEST1 \ the word "CODE" add ASSEMBLER as CONTEXT vocabulary... - - MOV &BASEADR,&BASEADR \ to test &xxxx src operand - CMP #%10,&BASEADR -0<> IF MOV #2,&BASEADR \ if base <> 2 -ELSE MOV #$0A,&BASEADR \ else base = 2 -THEN - COLON \ tips : no "ok" displayed in start of line <==> compilation mode - BASEADR @ U. \ always display 10 ! - ; + CODE TEST1 \ the word "CODE" add ASSEMBLER as CONTEXT vocabulary... + + MOV &BASE,&BASE \ to test &xxxx src operand + CMP #%10,&BASE + 0<> IF MOV #2,&BASE \ if base <> 2 + ELSE MOV #$0A,&BASE \ else base = 2 + THEN + COLON \ tips : no "ok" displayed in start of line <==> compilation mode + BASE @ U. \ always display 10 ! + ; \ \ ----------------------------------------------------------------------- \ test a word that starts as word FORTH and ends as assembly word \ ----------------------------------------------------------------------- -: TEST2 \ ":" starts compilation - BASEADR @ U. \ always display 10 ! - HI2LO \ switch FORTH to ASM : compile one word (next address) - \ add vocabulary ASSEMBLER as CONTEXT vocabulary - \ switch in interpret mode - CMP #2, &BASEADR -0<> IF MOV #2, &BASEADR \ if variable system BASE <> 2 -ELSE MOV #10,&BASEADR \ else (BASE = 2) -THEN -\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT. + : TEST2 \ ":" starts compilation + BASE @ U. \ always display 10 ! + HI2LO \ switch FORTH to ASM : compile one word (next address) + \ add vocabulary ASSEMBLER as CONTEXT vocabulary + \ switch in interpret mode + CMP #2, &BASE + 0<> IF MOV #2, &BASE \ if variable system BASE <> 2 + ELSE MOV #10,&BASE \ else (BASE = 2) + THEN +\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT. \ but even compile two words, it's better to compile an inline EXIT : - MOV @RSP+,IP \ restore IP - MOV @IP+,PC \ = NEXT -ENDCODE \ ends assembler : remove vocabulary ASSEMBLER from CONTEXT - \ + MOV @RSP+,IP \ restore IP + MOV @IP+,PC \ = NEXT + ENDCODE \ ends assembler : remove vocabulary ASSEMBLER from CONTEXT +\ \ ----------------------------------------------------------------------- \ test a word that starts as assembly word and ends as FORTH word \ ----------------------------------------------------------------------- -CODE TEST3 \ "CODE" starts assembler, i.e. add ASSEMBLER as CONTEXT vocabulary - CMP #2, &BASEADR -0<> IF MOV #2, &BASEADR \ if variable system BASE <> 2 -ELSE MOV #10,&BASEADR \ else (BASE = 2) -THEN COLON \ - BASEADR @ U. \ always display 10 ! -; \ - \ + CODE TEST3 \ "CODE" starts assembler, i.e. add ASSEMBLER as CONTEXT vocabulary + CMP #2, &BASE + 0<> IF MOV #2, &BASE \ if variable system BASE <> 2 + ELSE MOV #10,&BASE \ else (BASE = 2) + THEN COLON \ + BASE @ U. \ always display 10 ! + ; \ +\ \ ----------------------------------------------------------------------- @@ -435,7 +575,7 @@ BEGIN SUB #$0001,TOS HI2LO CMP #0,TOS 0= UNTIL MOV @PSP+,TOS -\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT. +\ MOV #EXIT,PC \ to pair with ":" i.e. to restore IP saved by : then execute NEXT. MOV @RSP+,IP \ restore IP MOV @IP+,PC \ = NEXT ENDCODE @@ -469,7 +609,7 @@ ENDCODE [THEN] : BYTES_TABLE_IDX -CREATE +CREATE 0 DO I C, LOOP DOES> @@ -489,8 +629,8 @@ $0201 BYTES_TABLE1 ! \ words written in memory are little endian ! CODE IDX_TEST1 \ index -- value MOV.B BYTES_TABLE1(TOS),TOS \ -- value COLON - U. -; + U. +; 0 IDX_TEST1 ; you should see 1 --> @@ -504,7 +644,7 @@ ENDCODE \ ----------------------------------------------------------------------- -\ tests access to a CREATED word with assembler +\ tests access to a CREATED word with assembler \ ----------------------------------------------------------------------- @@ -537,26 +677,26 @@ CREATE TABLE TABLE 2 - CONSTANT PFA_TABLE \ PFA_TABLE leave the PFA of TABLE -CODE REDIRECT ; <table> -- redirects TABLE to argument <table> +CODE REDIRECT ; <table> -- redirects TABLE to argument <table> MOV TOS,&PFA_TABLE MOV @PSP+,TOS MOV @IP+,PC ENDCODE \ -CODE REDIRECT0 ; -- redirects TABLE to TABLE0 +CODE REDIRECT0 ; -- redirects TABLE to TABLE0 MOV #TABLE0,&PFA_TABLE MOV @IP+,PC ENDCODE \ -CODE REDIRECT10 ; -- redirects TABLE to TABLE10 +CODE REDIRECT10 ; -- redirects TABLE to TABLE10 MOV #TABLE10,&PFA_TABLE MOV @IP+,PC ENDCODE \ -CODE REDIRECT20 ; -- redirects TABLE to TABLE20 +CODE REDIRECT20 ; -- redirects TABLE to TABLE20 MOV #TABLE20,&PFA_TABLE MOV @IP+,PC ENDCODE @@ -591,7 +731,7 @@ TABLE20 PFA_TABLE ! TABLE 10 DUMP \ \ ----------------------------------------------------------------------- -\ tests behaviour of assembly error +\ tests behaviour of assembly error \ ----------------------------------------------------------------------- \ R16 causes an error, assembler context is aborted and the word TEST7 is "hidden". @@ -604,14 +744,13 @@ TABLE20 PFA_TABLE ! TABLE 10 DUMP DEFER TRUC ; here, TRUC is a secondary DEFERred word (i.e. without BODY) - \ -CODENNM ; leaves its execution address (CFA) on stack +CODENNM ; does DUP SUB #2,PSP MOV TOS,0(PSP) MOV @IP+,PC -ENDCODE +ENDCODE ; leaves its execution address (CFA) on stack DUP . @@ -621,25 +760,26 @@ IS TRUC ; TRUC becomes a primary DEFERred word TRUC . ; display TOS value --> -' TRUC >BODY IS TRUC ; TRUC is reinitialzed with its default action +\ ' DROP IS TRUC ; TRUC is redirected to DROP +\ +\ TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? --> +\ + +' TRUC >BODY IS TRUC ; TRUC is reinitialized with its default action -TRUC . ; display TOS value --> +TRUC . ; display TOS value --> -\ ' DROP IS TRUC ; TRUC is redirected to DROP -\ -\ TRUC ; The generated error displays stack empty! in reverse video, removes the TRUC definition and restarts the interpretation after the end of the file. And as you see, FastForth is able to display long lines, interesting, doesn't it? --> -\ \ bla \ bla \ bla -\ -\ -\ -\ -\ -\ -\ +\ +\ +\ +\ +\ +\ +\ \ bla \ ... diff --git a/MSP430-FORTH/TESTXASM.F b/MSP430-FORTH/TESTXASM.F index 20dae53..66615ef 100644 --- a/MSP430-FORTH/TESTXASM.F +++ b/MSP430-FORTH/TESTXASM.F @@ -6,7 +6,7 @@ \ \ TARGET SELECTION ( = the name of \INC\target.pat file without the extension) \ MSP_EXP430FR5969 MSP_EXP430FR5994 MSP_EXP430FR6989 -\ +\ MSP_EXP430FR2355 \ from scite editor : copy your target selection in (shift+F8) parameter 1: \ \ OR @@ -26,642 +26,730 @@ \ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack \ \ ASSEMBLER conditionnal usage after IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= -\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0< +\ ASSEMBLER conditionnal usage before ?JMP ?GOTO : S< S>= U< U>= 0= 0<> 0< \ \ FORTH conditionnal : 0= 0< = < > U< -CODE ABORT_TEST_ASMX -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_TEST_ASM definition before resuming -; + CODE ABORT_TEST_ASMX + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_TEST_ASM definition before resuming + ; -ABORT_TEST_ASMX \ abort test + ABORT_TEST_ASMX \ abort test + + MARKER {TEST_ASMX} -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] \ define MAX and MIN + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 ( = -n3) + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] -CODE MAX \ n1 n2 -- n3 signed maximum + [UNDEFINED] MAX + [IF] \ define MAX and MIN + CODE MAX \ n1 n2 -- n3 signed maximum CMP @PSP,TOS \ n2-n1 S< ?GOTO FW1 \ n2<n1 BW1 ADD #2,PSP MOV @IP+,PC -ENDCODE + ENDCODE -CODE MIN \ n1 n2 -- n3 signed minimum + CODE MIN \ n1 n2 -- n3 signed minimum CMP @PSP,TOS \ n2-n1 S< ?GOTO BW1 \ n2<n1 FW1 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE + ENDCODE + [THEN] -[THEN] - -[UNDEFINED] C@ [IF] \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] CONSTANT [IF] \ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] BL [IF] -\ https://forth-standard.org/standard/core/BL -\ BL -- char an ASCII space -#32 CONSTANT BL -[THEN] - -[UNDEFINED] SPACE [IF] +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -BL EMIT ; -[THEN] + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - BL EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + NEXT + ENDCODE + [THEN] -[UNDEFINED] OVER [IF] \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] SWAP [IF] \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] >R [IF] \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] R> [IF] \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] U.R [IF] \ defined in {UTILITY} -: U.R \ u n -- display u unsigned in n width (n >= 2) - >R <# 0 # #S #> - R> OVER - 0 MAX SPACES TYPE -; -[THEN] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + + [UNDEFINED] U.R + [IF] \ defined in {UTILITY} + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0, init + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/LOOP \ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W MOV X,-4(W) \ xloop --> HERE MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 \ goto BW1 LOOP -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + DEFER CR \ DEFERed definition, by default executes that of :NONAME + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/BASE +\ BASE -- a-addr holds conversion radix + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] -[UNDEFINED] DUMP [IF] \ defined in {UTILITY} \ https://forth-standard.org/standard/tools/DUMP -CODE DUMP \ adr n -- dump memory -PUSH IP -PUSH &BASEADR \ save current base -MOV #$10,&BASEADR \ HEX base -ADD @PSP,TOS \ -- ORG END -LO2HI - SWAP \ -- END ORG - DO CR \ generate line - I 4 U.R SPACE \ generate address - I 8 + I - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I \ display 16 chars - DO I C@ $7E MIN BL MAX EMIT LOOP - $10 +LOOP - R> BASEADR ! \ restore current base -; -[THEN] + [UNDEFINED] DUMP + [IF] \ defined in {UTILITY} + CODE DUMP \ adr n -- dump memory + PUSH IP + PUSH &BASE \ save current base + MOV #$10,&BASE \ HEX base + ADD @PSP,TOS \ -- ORG END + LO2HI + SWAP \ -- END ORG + DO CR \ generate line + I 4 U.R SPACE \ generate address + I 8 + I + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I \ display 16 chars + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! \ restore current base + ; + [THEN] + + [UNDEFINED] HERE + [IF] + CODE HERE + MOV #HEREXEC,PC + ENDCODE + [THEN] + + RST_SET + + + ECHO + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word) +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) +; indexed instructions must be written as $xxxx(REG) (single numbers) +; ----------------------------------------------------------------------------- -[UNDEFINED] HERE [IF] -CODE HERE -MOV #HEREXEC,PC +HERE +CODE TT +CALLA W ENDCODE -[THEN] - -PWR_HERE - - -ECHO -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba (without extended word) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +HERE OVER - DUMP +; you should see: 4A 13 +RST_RET HERE -CODE TEST -MOVA @W,T +CODE TT +CALLA $3456(W) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 5A 13 56 34 +RST_RET HERE -CODE TEST -MOVA @T+,W +CODE TT +CALLA 0(PSP) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>1A 0B<04 44 55 4D 50 4F -PWR_STATE +; you should see: 5F 13 00 00 +RST_RET HERE -CODE TEST -MOVA &$1.2345,T +CODE TT +CALLA @W ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>2B 01 45 23<04 44 55 4D -PWR_STATE +; you should see: 6A 13 +RST_RET HERE -CODE TEST -MOVA $.1234(W),S +CODE TT +CALLA @PSP ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>3C 0A 34 12<04 44 55 4D -PWR_STATE +; you should see: 6F 13 +RST_RET HERE -CODE TEST -MOVA T,&$1.2345 +CODE TT +CALLA @W+ ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>61 0B 45 23<04 44 55 4D -PWR_STATE +; you should see: 7A 13 +RST_RET HERE -CODE TEST -MOVA S,$.1234(W) +CODE TT +CALLA &$2.3456 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>7A 0C 34 12<04 44 55 4D -PWR_STATE +; you should see: 82 13 56 34 +RST_RET HERE -CODE TEST -MOVA #$0.1,S +CODE TT +CALLA #$5.6789 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>8C 00 01 00<04 44 55 4D -PWR_STATE +; you should see: B5 13 89 67 +RST_RET + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV : Adda|Cmpa|Mova|Suba +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) +; indexed instructions must be written as $xxxx(REG) (single numbers) +; ----------------------------------------------------------------------------- HERE -CODE TEST -CMPA #$1.2345,S +CODE TT +MOVA @W,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>9C 01 45 23<04 44 55 4D -PWR_STATE +; you should see: 0B 0A +RST_RET HERE -CODE TEST -ADDA #$2.3456,S +CODE TT +MOVA @T+,W ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>AC 02 56 34<04 44 55 4D -PWR_STATE +; you should see: 1A 0B +RST_RET HERE -CODE TEST -SUBA #$3.4567,S +CODE TT +MOVA &$1.2345,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>BC 03 67 45<04 44 55 4D -PWR_STATE +; you should see: 2B 01 45 23 +RST_RET +HERE +CODE TT +MOVA 2(PSP),TOS +ENDCODE +HERE OVER - DUMP +; you should see: 3E 0F 02 00 +RST_RET +HERE +CODE TT +MOVA $1234(W),S +ENDCODE +HERE OVER - DUMP +; you should see: 3C 0A 34 12 +RST_RET HERE -CODE TEST -MOVA W,T +CODE TT +MOVA T,&$1.2345 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>CB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 61 0B 45 23 +RST_RET HERE -CODE TEST -CMPA W,T +CODE TT +MOVA TOS,0(PSP) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>DB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 7F 0E 00 00 +RST_RET HERE -CODE TEST -ADDA W,T +CODE TT +MOVA S,$1234(W) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>EB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 7A 0C 34 12 +RST_RET HERE -CODE TEST -SUBA W,T +CODE TT +MOVA #$0.1,S ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>FB 0A<04 44 55 4D 50 4F -PWR_STATE +; you should see: 8C 00 01 00 +RST_RET -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER: CALLA (without extended word) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +HERE +CODE TT +CMPA #$1.2345,S +ENDCODE +HERE OVER - DUMP +; you should see: 9C 01 45 23 +RST_RET HERE -CODE TEST -CALLA W +CODE TT +ADDA #$2.3456,S ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>4A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: AC 02 56 34 +RST_RET HERE -CODE TEST -CALLA $.3456(W) +CODE TT +SUBA #$3.4567,S ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5A 13 56 34<04 44 55 4D -PWR_STATE +; you should see: BC 03 67 45 +RST_RET HERE -CODE TEST -CALLA @W +CODE TT +MOVA W,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>6A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: CB 0A +RST_RET HERE -CODE TEST -CALLA @W+ +CODE TT +CMPA W,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>7A 13<04 44 55 4D 50 4F -PWR_STATE +; you should see: DB 0A +RST_RET HERE -CODE TEST -CALLA &$2.3456 +CODE TT +ADDA W,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>82 13 56 34<04 44 55 4D -PWR_STATE +; you should see: EB 0A +RST_RET HERE -CODE TEST -CALLA #$5.6789 +CODE TT +SUBA W,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>B5 13 89 67<04 44 55 4D -PWR_STATE +; you should see: FB 0A +RST_RET -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES V extended double operand -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- HERE -CODE TEST +CODE TT MOV S,T MOVX S,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 4C 40 18 0B 4C<04 44 -PWR_STATE +; you should see: 0B 4C 40 18 0B 4C +RST_RET HERE -CODE TEST +CODE TT ADD T,T ADDX.A T,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 00 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 00 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADD T,T RPT X ADDX.A T,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 89 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 89 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADD T,T RPT #8 ADDX.A T,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 5B 07 18 4B 5B<04 44 -PWR_STATE +; you should see: 0B 5B 07 18 4B 5B +RST_RET HERE -CODE TEST +CODE TT ADDC #$9876,T ADDCX.A #$5.9876,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>3B 60 76 98 80 1A 7B 60 -; 76 98<04 44 55 4D -PWR_STATE +; you should see: 3B 60 76 98 80 1A 7B 60 76 98 +RST_RET HERE -CODE TEST +CODE TT ADDC &$9876,T ADDCX.A &$5.9876,T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>1B 62 76 98 80 1A 5B 62 -; 76 98<04 44 55 4D -PWR_STATE +; you should see: 1B 62 76 98 80 1A 5B 62 76 98 +RST_RET HERE -CODE TEST +CODE TT XOR.B $5432(S),T XORX.B $6.5432(S),T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5B EC 32 54 46 18 5B EC -; 32 54<04 44 55 4D -PWR_STATE +; you should see: 5B EC 32 54 46 18 5B EC 32 54 +RST_RET HERE -CODE TEST +CODE TT SUBC T,$5432(S) SUBCX.A T,$6.5432(S) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>8C 7B 32 54 06 18 CC 7B -; 32 54<04 44 55 4D -PWR_STATE +; you should see: 8C 7B 32 54 06 18 CC 7B 32 54 +RST_RET HERE -CODE TEST +CODE TT XOR.B T,$5432(S) XORX.B T,$6.5432(S) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>CC EB 32 54 46 18 CC EB -; 32 54<04 44 55 4D -PWR_STATE - -; -------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand (take count of RPT) -; -------------------------------------------------------------------------------- -; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) +; you should see: CC EB 32 54 46 18 CC EB 32 54 +RST_RET + +; ----------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES VI extended single operand +; ----------------------------------------------------------------------------- +; absolute and immediate instructs. must be written as $x.xxxx (DOUBLE numbers) ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) -; -------------------------------------------------------------------------------- +; ----------------------------------------------------------------------------- HERE -CODE TEST +CODE TT RRA X RRAX X ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>09 11 40 18 09 11<04 44 -PWR_STATE +; you should see: 09 11 40 18 09 11 +RST_RET HERE -CODE TEST +CODE TT RRC @X RRCX.A @X ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>29 10 00 18 69 10<04 44 -PWR_STATE +; you should see: 29 10 00 18 69 10 +RST_RET HERE -CODE TEST +CODE TT RRC @S RRCX.A @S ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>2C 10 00 18 6C 10<04 44 -PWR_STATE +; you should see: 2C 10 00 18 6C 10 +RST_RET HERE -CODE TEST +CODE TT RRC @X+ RRUX.A @X+ ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>39 10 00 19 79 10<04 44 -PWR_STATE +; you should see: 39 10 00 19 79 10 +RST_RET HERE -CODE TEST +CODE TT RRC T RPT #9 RRUX.A T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 10 08 19 4B 10<04 44 -PWR_STATE +; you should see: 0B 10 08 19 4B 10 +RST_RET HERE -CODE TEST +CODE TT RRC T RPT X RRUX.A T ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>0B 10 89 19 4B 10<04 44 -PWR_STATE +; you should see: 0B 10 89 19 4B 10 +RST_RET HERE -CODE TEST +CODE TT PUSH #$2345 PUSHX #$0.2345 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>30 12 45 23 40 18 30 12 -; 45 23<04 44 55 4D -PWR_STATE +; you should see: 30 12 45 23 40 18 30 12 45 23 +RST_RET HERE -CODE TEST +CODE TT PUSH &$5678 PUSHX.A &$4.5678 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>12 12 78 56 00 1A 52 12 -; 78 56<04 44 55 4D -PWR_STATE +; you should see: 12 12 78 56 00 1A 52 12 78 56 +RST_RET HERE -CODE TEST +CODE TT PUSH.B &$33 PUSHX.B &$.33 ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>52 12 33 00 40 18 52 12 -; 33 00<04 44 55 4D -PWR_STATE +; you should see: 52 12 33 00 40 18 52 12 33 00 +RST_RET HERE -CODE TEST +CODE TT PUSH.B $3344(T) PUSHX.B $.3344(T) ENDCODE HERE OVER - DUMP -; you should see: 45 53 54 52>5B 12 44 33 40 18 5B 12 -; 44 33<04 44 55 4D -PWR_STATE +; you should see: 5B 12 44 33 40 18 5B 12 44 33 +RST_RET + +\ https://forth-standard.org/standard/core/BASE +\ BASE -- a-addr holds conversion radix + [UNDEFINED] BASE + [IF] + ' # 2 + CONSTANT BASE + [THEN] : %. -BASEADR @ %10 BASEADR ! SWAP 8 EMIT . BASEADR ! +BASE @ %10 BASE ! SWAP 8 EMIT . BASE ! +RST_RET ; : %U. -BASEADR @ %10 BASEADR ! SWAP 8 EMIT U. BASEADR ! ; - -PWR_HERE +BASE @ %10 BASE ! SWAP 8 EMIT U. BASE ! +RST_RET +; +RST_SET ; ================ ; RRUX test @@ -678,9 +766,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRUX_T ; you should see %111100001111000 --> % - -PWR_STATE +RRUX_T ; % +; you should see: %111100001111000 ; ================ ; RRUX repeat test @@ -697,9 +784,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRUX_T ; you should see %111100001111000 --> % - -PWR_STATE +RRUX_T ; % +; you should see: %111100001111000 CODE RRUX_T MOV #$F0F0,Y @@ -711,9 +797,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRUX_T ; you should see %111100001111 --> % - -PWR_STATE +RRUX_T ; --> % +; you should see: %111100001111 CODE RRUX_T MOV #$F0F0,Y @@ -725,16 +810,13 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRUX_T ; you should see %11110000 --> % - -PWR_STATE - +RRUX_T ; % +; you should see: %11110000 ; ================ ; RRCX test ; ================ - CODE RRCX_T MOV #$8000,Y BIC #C,SR @@ -745,9 +827,8 @@ MOV Y,TOS MOV #%U.,PC ENDCODE -RRCX_T ; you should see %100000000000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %100000000000000 ; ================ ; RRCX repeat test @@ -764,9 +845,8 @@ MOV Y,TOS MOV #%U.,PC ENDCODE -RRCX_T ; you should see %100000000000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %100000000000000 CODE RRCX_T MOV #$8000,Y @@ -779,15 +859,13 @@ MOV Y,TOS MOV #%U.,PC ENDCODE -RRCX_T ; you should see %10000000 --> % - -PWR_STATE +RRCX_T ; % +; you should see: %10000000 ; ================ ; RRAX test ; ================ - CODE RRAX_T MOV #$8000,Y RRAX Y @@ -797,9 +875,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRAX_T ; you should see %-100000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000000000 ; ================ ; RRAX repeat test @@ -816,9 +893,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRAX_T ; you should see %-100000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000000000 CODE RRAX_T MOV #$8000,Y @@ -830,9 +906,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRAX_T ; you should see %-10000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-10000000000000 CODE RRAX_T MOV #$8000,Y @@ -844,9 +919,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRAX_T ; you should see %-1000000000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-1000000000000 CODE RRAX_T MOV #$8000,Y @@ -858,9 +932,8 @@ MOV Y,TOS MOV #%.,PC ENDCODE -RRAX_T ; you should see %-100000000 --> % - -PWR_STATE +RRAX_T ; % +; you should see: %-100000000 ; ================ ; RLAX test @@ -878,8 +951,6 @@ ENDCODE RLAX_T ; you should see -2 --> -PWR_STATE - ; ================ ; RLAX repeat test ; ================ @@ -897,8 +968,6 @@ ENDCODE RLAX_T ; you should see -2 --> -PWR_STATE - CODE RLAX_T MOV #-1,Y RPT #2 @@ -911,8 +980,6 @@ ENDCODE RLAX_T ; you should see -4 --> -PWR_STATE - CODE RLAX_T MOV #-1,Y RPT #3 @@ -925,8 +992,6 @@ ENDCODE RLAX_T ; you should see -8 --> -PWR_STATE - CODE RLAX_T MOV #-1,Y RPT #8 @@ -939,8 +1004,6 @@ ENDCODE RLAX_T ; you should see -256 --> -PWR_STATE - ; ================ ; ADDX test ; ================ @@ -958,8 +1021,6 @@ ENDCODE ADDX_T ; you should see -1 --> -PWR_STATE - ; ================ ; ADDX repeat test ; ================ @@ -978,8 +1039,6 @@ ENDCODE ADDX_T ; you should see -1 --> -PWR_STATE - CODE ADDX_T MOV #0,Y MOV #-1,X @@ -993,8 +1052,6 @@ ENDCODE ADDX_T ; you should see -2 --> -PWR_STATE - CODE ADDX_T MOV #0,Y MOV #-1,X @@ -1008,9 +1065,6 @@ ENDCODE ADDX_T ; you should see -8 --> -PWR_STATE - - ; ================ ; SUBX test ; ================ @@ -1028,8 +1082,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - ; ================ ; SUBX repeat test ; ================ @@ -1048,8 +1100,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - CODE SUBX_T MOV #0,Y MOV #-1,X @@ -1063,8 +1113,6 @@ ENDCODE SUBX_T ; you should see 2 --> -PWR_STATE - CODE SUBX_T MOV #0,Y MOV #-1,X @@ -1078,8 +1126,6 @@ ENDCODE SUBX_T ; you should see 8 --> -PWR_STATE - CODE SUBX_T \ W register = R10 MOV #15,W \ RPT [W] times, modulo 16 <--> RPT #16 MOV #0,Y @@ -1094,8 +1140,6 @@ ENDCODE SUBX_T ; you should see 16 --> -PWR_STATE - CODE SUBX_T MOV #32,W \ RPT [W] times, modulo 16 <--> RPT #1 MOV #0,Y @@ -1110,8 +1154,6 @@ ENDCODE SUBX_T ; you should see 1 --> -PWR_STATE - CODE SUBX_T MOV #33,W \ RPT [W] times, modulo 16 <--> RPT #2 MOV #0,Y @@ -1126,4 +1168,4 @@ ENDCODE SUBX_T ; you should see 2 --> -RST_STATE +{TEST_ASMX} diff --git a/MSP430-FORTH/TSTWORDS.4TH b/MSP430-FORTH/TSTWORDS.4TH deleted file mode 100644 index fb92b9c..0000000 --- a/MSP430-FORTH/TSTWORDS.4TH +++ /dev/null @@ -1,90 +0,0 @@ -\ ----------------------------- -\ MSP-EXP430FR5969_TSTWORDS.4th -\ ----------------------------- - -PWR_STATE - -\ ----------------------------------------------------------------------- -\ test some assembler words and show how to mix FORTH/ASSEMBLER routines -\ ----------------------------------------------------------------------- -LOAD" \misc\TestASM.4th" - -\ ------------------------------------- -\ here we returned in the TestWords.4th -\ ------------------------------------- -ECHO -\ ---------- -\ LOOP tests -\ ---------- -: LOOP_TEST 8 0 DO I . LOOP -; - -LOOP_TEST \ you should see 0 1 2 3 4 5 6 7 --> - - -: LOOP_TEST1 \ n <LOOP_TEST1> --- - - BEGIN DUP U. 1 - - ?DUP - 0= UNTIL -; - -: LOOP_MAX \ FIND_NOTHING -- - 0 0 - DO - LOOP \ 14 cycles by loop - ABORT" 65536 LOOP " -; - - : FIND_TEST \ FIND_TEST <word> -- - $20 WORD \ -- c-addr - 50000 0 - DO \ -- c-addr - DUP - FIND DROP DROP - LOOP - FIND - 0= IF ABORT" <-- not found !" - ELSE ABORT" <-- found !" - THEN - ; - -\ seeking $ word, FIND jumps all words on their first character so time of word loop is 20 cycles -\ see FIND in the source file for more information -\ -\ FIND_TEST <lastword> result @ 8MHz, monothread : 1,2s -\ -\ FIND_TEST $ results @ 8MHz, monothread, 201 words in vocabulary FORTH : -\ 27 seconds with only FORTH vocabulary in CONTEXT -\ 540 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 2.6866 us / word, 21,49 cycles / word (for 20 cycles calculated (see FIND in source file) -\ -\ -\ FIND_TEST $ results @ 8MHz, 2 threads, 201 words in vocabulary FORTH : -\ 13 second with only FORTH vocabulary in CONTEXT -\ 260 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 1,293 us / word, 10,34 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 4 threads, 201 words in vocabulary FORTH : -\ 8 second with only FORTH vocabulary in CONTEXT -\ 160 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,796 us / word, 6,37 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 8 threads, 201 words in vocabulary FORTH : -\ 4.66 second with only FORTH vocabulary in CONTEXT -\ 93 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,4463 us / word, 3,7 cycles / word -\ -\ FIND_TEST $ results @ 8MHz, 16 threads, 201 words in vocabulary FORTH : -\ 2,8 second with only FORTH vocabulary in CONTEXT -\ 56 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) -\ 0,278 us / word, 2,22 cycles / word -\ -\ -------- -\ KEY test -\ -------- -: KEY_TEST - ." type a key : " - KEY EMIT \ wait for a KEY, then emit it -; -\ KEY_TEST diff --git a/MSP430-FORTH/TSTWORDS.f b/MSP430-FORTH/TSTWORDS.f new file mode 100644 index 0000000..4712eb4 --- /dev/null +++ b/MSP430-FORTH/TSTWORDS.f @@ -0,0 +1,306 @@ +\ ----------------------------- +\ MSP-EXP430FR5969_TSTWORDS.f +\ ----------------------------- + +\ first, we test for downloading driver only if UART TERMINAL target + CODE ABORT_TSTWORDS + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_TEST_ASM definition before resuming + ; + + ABORT_TSTWORDS \ abort test + + [DEFINED] {TSTWORDS} [IF] {TSTWORDS} [THEN] \ remove it + + MARKER {TSTWORDS} + + +\ https://forth-standard.org/standard/core/ZeroEqual +\ 0= n/u -- flag return true if TOS=0 + [UNDEFINED] 0= + [IF] + CODE 0= + SUB #1,TOS \ 1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS \ 1 TOS=-1 if borrow was set + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] DUP + [IF] \ define DUP and ?DUP +\ https://forth-standard.org/standard/core/DUP +\ DUP x -- x x duplicate top of stack + CODE DUP +BW1 SUB #2,PSP \ 2 push old TOS.. + MOV TOS,0(PSP) \ 3 ..onto stack + MOV @IP+,PC \ 4 + ENDCODE + +\ https://forth-standard.org/standard/core/qDUP +\ ?DUP x -- 0 | x x DUP if nonzero + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/IF +\ IF -- IFadr initialize conditional forward branch + [UNDEFINED] IF + [IF] \ define IF THEN + + CODE IF + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/THEN +\ THEN IFadr -- resolve forward branch + CODE THEN + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/ELSE +\ ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack + [UNDEFINED] ELSE + [IF] + CODE ELSE + ADD #4,&DP \ make room to compile two words + MOV &DP,W \ W=HERE+4 + MOV #BRAN,-4(W) + MOV W,0(TOS) \ HERE+4 ==> [IFadr] + SUB #2,W \ HERE+2 + MOV W,TOS \ -- ELSEadr + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + +\ https://forth-standard.org/standard/core/SWAP +\ SWAP x1 x2 -- x2 x1 swap top two items + [UNDEFINED] SWAP + [IF] + CODE SWAP + PUSH TOS \ 3 + MOV @PSP,TOS \ 2 + MOV @RSP+,0(PSP) \ 4 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/BEGIN +\ BEGIN -- BEGINadr initialize backward branch + [UNDEFINED] BEGIN + [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + + CODE BEGIN + MOV #HEREXEC,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/UNTIL +\ UNTIL BEGINadr -- resolve conditional backward branch + CODE UNTIL + MOV #QFBRAN,X +BW1 ADD #4,&DP \ compile two words + MOV &DP,W \ W = HERE + MOV X,-4(W) \ compile Bran or QFBRAN at HERE + MOV TOS,-2(W) \ compile bakcward adr at HERE+2 + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/AGAIN +\ AGAIN BEGINadr -- resolve uncondionnal backward branch + CODE AGAIN + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/WHILE +\ WHILE BEGINadr -- WHILEadr BEGINadr + : WHILE + POSTPONE IF SWAP + ; IMMEDIATE + +\ https://forth-standard.org/standard/core/REPEAT +\ REPEAT WHILEadr BEGINadr -- resolve WHILE loop + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] + + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + +\ https://forth-standard.org/standard/core/DO +\ DO -- DOadr L: -- 0 + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0, init + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/LOOP +\ LOOP DOadr -- L-- an an-1 .. a1 0 + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP + MOV #XLOOP,X +BW2 ADD #4,&DP \ make room to compile two words + MOV &DP,W + MOV X,-4(W) \ xloop --> HERE + MOV TOS,-2(W) \ DOadr --> HERE+2 + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE IMMEDIATE + +\ https://forth-standard.org/standard/core/PlusLOOP +\ +LOOP adrs -- L-- an an-1 .. a1 0 + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] + + + RST_SET +\ ----------------------------------------------------------------------- +\ test some assembler words and show how to mix FORTH/ASSEMBLER routines +\ ----------------------------------------------------------------------- +LOAD" \misc\TestASM.4th" + +ECHO + +\ ------------------------------------- +\ here we returned in the TestWords.4th +\ ------------------------------------- + +\ ---------- +\ LOOP tests +\ ---------- +: LOOP_TEST 8 0 DO I . LOOP +; + +LOOP_TEST \ you should see 0 1 2 3 4 5 6 7 --> + + +: LOOP_TEST1 \ n <LOOP_TEST1> --- + BEGIN DUP U. 1 - + ?DUP + 0= UNTIL +; +\ +\ : LOOP_MAX \ FIND_NOTHING -- +\ 0 0 +\ DO +\ LOOP \ 14 cycles by loop +\ ABORT" 65536 LOOP " +\ ; +\ +: FIND_TEST \ FIND_TEST <word> -- + $20 WORD \ -- c-addr + 50000 0 + DO \ -- c-addr + DUP + FIND DROP DROP + LOOP + FIND + 0= IF ABORT" <-- not found !" + ELSE ABORT" <-- found !" + THEN + ; +\ +\ \ seeking $ word, FIND jumps all words on their first character so time of word loop is 20 cycles +\ \ see FIND in the source file for more information +\ \ +\ \ FIND_TEST <lastword> result @ 8MHz, monothread : 1,2s +\ \ +\ \ FIND_TEST $ results @ 8MHz, monothread, 201 words in vocabulary FORTH : +\ \ 27 seconds with only FORTH vocabulary in CONTEXT +\ \ 540 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) +\ \ 2.6866 us / word, 21,49 cycles / word (for 20 cycles calculated (see FIND in source file) +\ \ +\ \ +\ \ FIND_TEST $ results @ 8MHz, 2 threads, 201 words in vocabulary FORTH : +\ \ 13 second with only FORTH vocabulary in CONTEXT +\ \ 260 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) +\ \ 1,293 us / word, 10,34 cycles / word +\ \ +\ \ FIND_TEST $ results @ 8MHz, 4 threads, 201 words in vocabulary FORTH : +\ \ 8 second with only FORTH vocabulary in CONTEXT +\ \ 160 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) +\ \ 0,796 us / word, 6,37 cycles / word +\ \ +\ \ FIND_TEST $ results @ 8MHz, 8 threads, 201 words in vocabulary FORTH : +\ \ 4.66 second with only FORTH vocabulary in CONTEXT +\ \ 93 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) +\ \ 0,4463 us / word, 3,7 cycles / word +\ \ +\ \ FIND_TEST $ results @ 8MHz, 16 threads, 201 words in vocabulary FORTH : +\ \ 2,8 second with only FORTH vocabulary in CONTEXT +\ \ 56 us for one search ( which gives the delay for QNUMBER in INTERPRET routine) +\ \ 0,278 us / word, 2,22 cycles / word +\ \ +\ \ -------- +\ \ KEY test +\ \ -------- +\ : KEY_TEST +\ ." type a key : " +\ KEY EMIT \ wait for a KEY, then emit it +\ ; +\ \ KEY_TEST +\ \ No newline at end of file diff --git a/MSP430-FORTH/UARTI2CS.f b/MSP430-FORTH/UARTI2CS.f index 15eb7c6..cbf9af8 100644 --- a/MSP430-FORTH/UARTI2CS.f +++ b/MSP430-FORTH/UARTI2CS.f @@ -16,29 +16,28 @@ \ \ FastForth kernel compilation minimal options: \ TERMINAL3WIRES, TERMINAL4WIRES -\ MSP430ASSEMBLER, CONDCOMP \ \ ================================================================================ \ REGISTERS USAGE for embedded MSP430 ASSEMBLER \ ================================================================================ \ don't use R2, R3, \ R4, R5, R6, R7 must be PUSHed/POPed before/after use -\ scratch registers S to Y are free, -\ under interrupt, IP is free, -\ Apply FORTH rules for TOS, PSP, RSP registers use. +\ scratch registers S,T,W,X and Y are free, +\ in interrupt routines, IP is free, +\ Apply FORTH rules for TOS, PSP, RSP registers. \ \ PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC \ PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0 \ -\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack +\ example : PUSHM #6,IP pushes IP,S,T,W,X,Y registers to return stack, with IP first pushed \ \ POPM order : PC,RSP, SR, R3, rDODOES,rDOCON,rDOVAR,rEXIT, Y, X, W, T, S, IP,TOS,PSP \ POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15 \ -\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack +\ example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack, with IP last poped \ \ ASSEMBLER conditionnal usage before IF UNTIL WHILE : S< S>= U< U>= 0= 0<> 0>= -\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0< +\ ASSEMBLER conditionnal usage before ?GOTO : S< S>= U< U>= 0= 0<> 0< \ \ ================================================================================ \ coupled to a PL2303HXD/TA cable, this driver enables a FastForth target to act as USB to I2C_Slave bridge, @@ -46,20 +45,20 @@ \ In addition, it simulates a full duplex communication while the I2C bus is only half duplex. \ Don't forget to wire 3k3 pull up resistors on wires SDA SCL! \ ================================================================================ -\ +\ \ driver test : MCLK=24MHz, PL2303HXD with shortened cable (20cm), WIFI off, all windows apps closed else Scite and TERATERM. -\ ----------- -\ / ┌────────────────────────────────┐ -\ notebook USB to I2C_Slave bridge +-- I2C -->| up to 112 I2C_Slave targets | +\ ----------- . +\ . ┌────────────────────────────────┐ +\ notebook USB to I2C bridge +-- I2C -->| up to 112 I2C_Slave targets | \ ┌───────────────┐ ╔════════════════════════════════════════════════════════════╗ / ┌───────────────────────────────┐ | -\ | | ║ PL2303HXD target running UARTI2CS @ 24MHz ║ +-- I2C -->| MSP430FR4133 @ 1 MHz | | +\ | | ║ PL2303HXD device running UARTI2CS @ 24MHz ║ +-- I2C -->| MSP430FR4133 @ 1 MHz | | \ | | ║───────────────┐ ┌────────────────────────────────║ / ┌───────────────────────────────┐ |──┘ \ | | ║ | 3 wires | MSP430FR2355 @ 24MHz ║/ | MSP430FR5738 @ 24 MHz | | -\ | TERATERM -o--> USB --o--> USB2UART --o--> UART --o--> FAST FORTH ---> UARTI2CS --o--> I2C --o--> FAST FORTH with option |──┘ -\ | terminal | ║ | 6 MBds | (I2C MASTER) ║ | TERMINAL_I2C (I2C SLAVE) | +\ | TERATERM -o--> USB --o--> USB2UART --o--> UART --o--> FAST FORTH ---> UARTI2CS --o--> I2C --o--> FAST FORTH with |──┘ +\ | terminal | ║ | 6 MBds | (I2C MASTER) ║ | I2C TERMINAL | \ | | ║───────────────┘ └────────────────────────────────║ └───────────────────────────────┘ -\ | | ║ |<- l=20cm->| ║ -\ └───────────────┘ ╚════════════════════════════════════════════════════════════╝ +\ | | ║ |<- l=20cm->| ║ +\ └───────────────┘ ╚════════════════════════════════════════════════════════════╝ \ \ test results : \ ------------ @@ -67,14 +66,13 @@ \ downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Master target = 1016ms. \ downloading (+ interpret + compile + execute) CORETEST.4TH to I2C Slave target = 1422ms. \ the difference (406 ms) is the time of the I2C Half duplex exchange. -\ [(45906 chars * 9 bits) + (1533 * 31)] / 0,406 = 1,135 MHz (9 bits / char + (2*START + 2*STOP + 2*addr + CTRL_Char) / line) +\ [(45906 chars * 9 bits) + (1533 * 31)] / 0,406 = 1,135 MHz (9 bits / char + (2*START + 2*STOP + 2*addr + CTRL_Char) / line) \ ==> 113 % of I2C Fast-mode Plus (Fm+)! -\ +\ \ also connected to and tested with another I2C_FastForth target with MCLK = 1MHz (I2C CLK = MCLK ! ). \ \ The I2C_Slave address is defined as 'MYSLAVEADR' in forthMSP430FR.asm source file of I2C_Slave target. -\ You can use any pin for SDA and SCL, preferably in the interval Px0...Px3. -\ you will find SCA and SCL pin by searching 'SM_BUS' in your \inc\target.pat files (I2C_Master and I2C_Slave) +\ You can use any pin for SDA and SCL, preferably in the interval Px0...Px3. \ don't forget to add 3.3k pullup resitors on wires SDA and SCL. \ \ @@ -87,31 +85,32 @@ \ \ 1- the I2C bus is Master to Slave oriented, the Slave does not decide anything. \ This order of things allows in any case to establish the connection. -\ The I2C Master device is therefore placed on the control TERMINAL side and the FastForth target on the I2C Slave side. -\ But once the link is established, we have to find a trick to reverse the roles, +\ The I2C Master device is therefore placed on the TERMINAL side and the FastForth target on the I2C Slave side. +\ But once the link is established, we have to find a trick to reverse the roles, \ so that the slave can take control of the data exchange. \ -\ 2- The I2C bus operates on half duplex. +\ 2- The I2C bus operates on half duplex. \ Another trick will be to simulate an I2C_Master TERMINAL in Full Duplex mode. \ +\ 3- Without forgetting a visual effect to show the lack of I2C connection... +\ \ Solution: The slave "slavishly" sends control characters to the master, \ and since this one obeys a bigger man than himself: the programmer.., \ he makes it his "masterly" duty to obey the slave. \ -\ To take control of the master, the slave emits 1 of 6+1 CTRL-Char: +\ To take control of the master, the slave emits one of 5+1 CTRL-Char: \ CTRL-Char $00 sent by ACCEPT (before falling asleep with SLEEP), \ CTRL-Char $01 sent by KEY: request to send a single character entered on TERMINAL, \ CTRL-Char $02 sent by ABORT": request to abort the file being downloaded if any, \ followed by a START RX for ABORT" message, -\ CTRL-Char $03 sent by WARM, to do a reSTART RX for WARM message, \ CTRL-Char $04 sent by NOECHO, to switch the UART to half-duplex mode, \ CTRL-Char $05 sent by ECHO, to switch the UART to full duplex mode. \ \ Finally, if the master receives a $FF as data, he considers the link broken, -\ it performs ABORT which forces a START RX on a loop. +\ it performs ABORT which forces a START RX into a 500 ms loop with an appropriate visual effect... \ -\ Once the slave sends the CTRL_Char $00, he falls asleep, -\ On receipt of this CTRL_Char, the master also falls asleep, awaiting a UART RX interruption. +\ Once the slave sends the CTRL_Char $00, he falls asleep, +\ On its receipt, the master also falls asleep, awaiting a UART RX interruption. \ As long as the TERMINAL is silent, the master and the slave remain in SLEEP mode, \ (a part the Tx0_INT interrupt every 1/2 s). \ SLEEP mode is LPM0 for the master (UART does not work if LPMx > LPM0), LPM4 for the slave. @@ -120,545 +119,567 @@ \ ------------- \ Since the slave can't wake up the master with a dedicated interrupt, the master must generate one \ cyclically to listen to the slave. -\ HALF_S_INT is used to generate a 1/2 second interrupt, obviously taken into account only when the master goes to sleep. -\ It performs a (re)START RX that enables the I2C link to be re-established following a RESET performed on I2C_Slave. -\ -\ This interruption also allows the UARTI2CS program to exit when Teraterm sends a BREAK (Alt-B). -\ -\ the other interruption U2I_TERM_INT is used to communicate with TERMINAL, by replacing of the TERM_INT one. -\ -\ Software +----------------------------------+ Hardware -\ I2C Master | +-------------------+ | I2C Slave -\ | | | | -\ UART to I2C bridge SCL SDA connected to: SDA SCL I2CFastForth target -\ ------------------- ---- ---- ---- ---- ------------------ -\ MSP_EXP430FR5739 P4.1 P4.0 P1.6 P1.7 MSP_EXP430FR5739 -\ MSP_EXP430FR5969 P1.3 P1.2 P1.6 P1.7 MSP_EXP430FR5969 -\ MSP_EXP430FR5994 P8.1 P8.2 P7.0 P7.1 MSP_EXP430FR5994 -\ MSP_EXP430FR6989 P1.5 P1.3 P1.6 P1.7 MSP_EXP430FR6989 -\ MSP_EXP430FR4133 P8.3 P8.2 P5.2 P5.3 MSP_EXP430FR4133 -\ CHIPSTICK_FR2433 P2.2 P2.0 P1.2 P1.3 CHIPSTICK_FR2433 -\ MSP_EXP430FR2433 P3.1 P3.2 P1.2 P1.3 MSP_EXP430FR2433 -\ MSP_EXP430FR2355 P3.3 P3.2 P1.2 P1.3 MSP_EXP430FR2355 -\ LP_MSP430FR2476 P3.3 P3.2 P4.4 P4.3 LP_MSP430FR2476 +\ 500MS_INT is used to generate a 1/2 second interrupt, obviously taken into account only when the master goes to sleep. +\ It performs a (re)START RX that enables the I2C link to be re-established following a RESET performed on I2C_Slave side. +\ +\ This interruption also allows to exit the UARTI2CS program when user sends a software BREAK (Teraterm(Alt-B)), or presses SW2. +\ +\ the other interruption U2I_TERM_INT is used to link the TERMINAL with UARTI2CS instead of FORTH interpreter. \ \ don't forget to link 3V3 and GND on each side and to add 3k3 pullup resistors on SDA and SCL. +\ +\ because Txi_int > UCxi_int > Pi.j_int and to ensure U2I_TERM_INT priority greater than 500MS_INT +\ we choose P1.7 = TB0.2 output linked to P1.6 to use P1.6_int instead of Txi_int for 500MS_INT. -; ---------------------------------------------------------------------- -; UARTI2CS.f (Software I2C Master) -; ---------------------------------------------------------------------- - -\ first, we do some tests before downloading application -CODE ABORT_UARTI2CS -SUB #4,PSP -MOV TOS,2(PSP) -MOV &KERNEL_ADDON,TOS -BIT #$7800,TOS -0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0 -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -$0D EMIT \ return to column 1 without CR -ABORT" FastForth V3.8 please!" -ABORT" <-- Ouch! unexpected I2C_FastForth target!" -PWR_STATE \ remove the ABORT_UARTI2CS definition before continuing the download. -; - -ABORT_UARTI2CS \ abort test +; --------------------------------------------------------- \ +; UARTI2CS.f \ UART to I2C bridge for I2C_FastForth TERMINAL----------+ +; --------------------------------------------------------- \ | +\ | +\ | +\ GND------------------------------GND | +\ Vcc-------------o---o------------Vcc | +\ | | | +\ 3 3 | +\ k k | +\ 3 3 v +\ I2C_FastForth | | UARTI2CS +---------------------------------------+ +\ hardware +--------------|---o-------------+ Software | +-----------------------------+ | +\ I2C Slave | +-------o----------+ | I2C Master | | +------(option)-----+ | | +\ | | | | | | | | | | +\ I2C_FastForth(s) SCL SDA connected to: SDA SCL of I2C to UART bridge TXD RXD RTS connected to : CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL +\ ------------------ ---- ---- ---- ---- ------------------ --- --- --- --- --- --- --------- ---- ------------ +\ MSP_EXP430FR5739 P1.7 P1.6 P4.0 P4.1 MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE +\ MSP_EXP430FR5969 P1.7 P1.6 P1.2 P1.3 MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD +\ MSP_EXP430FR5994 P7.1 P7.0 P8.2 P8.1 MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 +\ MSP_EXP430FR6989 P1.7 P1.6 P1.3 P1.5 MSP_EXP430FR6989 P3.4 P3.5 P3.0 +\ MSP_EXP430FR4133 P5.3 P5.2 P8.2 P8.3 MSP_EXP430FR4133 P1.0 P1.1 P2.3 +\ CHIPSTICK_FR2433 P1.3 P1.2 P2.0 P2.2 CHIPSTICK_FR2433 P1.4 P1.5 P3.2 +\ MSP_EXP430FR2433 P1.3 P1.2 P3.2 P3.1 MSP_EXP430FR2433 P1.4 P1.5 P1.0 +\ MSP_EXP430FR2355 P1.3 P1.2 P3.2 P3.3 MSP_EXP430FR2355 P4.3 P4.2 P2.0 +\ LP_MSP430FR2476 P4.3 P4.4 P3.2 P3.3 LP_MSP430FR2476 P1.4 P1.5 P6.1 -[DEFINED] {UARTI2CS} [IF] {UARTI2CS} [THEN] \ remove {UARTI2CS} if already defined +\ first, we do some tests allowing the download +\ ------------------------\ + CODE ABORT_UARTI2CS \ +\ ------------------------\ + SUB #4,PSP + MOV TOS,2(PSP) + MOV &KERNEL_ADDON,TOS + BIT #$3C00,TOS \ BIT13|BIT12|BIT11|BIT10 test (UART TERMINAL test) + 0<> IF MOV #0,TOS THEN \ if TOS <> 0 (UART TERMINAL), set TOS = 0 + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + $0D EMIT \ return to column 1 without CR + ABORT" FastForth V3.9 please!" + ABORT" <-- Ouch! unexpected I2C_FastForth target!" + RST_RET \ remove the ABORT_UARTI2CS definition before continuing the download. + ; -MARKER {UARTI2CS} \ {UARTI2CS}+8 = RET_ADR by default -8 ALLOT \ {UARTI2CS}+10 <-- previous INI_APP -\ {UARTI2CS}+12 <-- previous TERM_VEC -\ {UARTI2CS}+14 <-- previous Tx0_x_VEC -\ {UARTI2CS}+16 <-- Half_Duplex flag : 0=ECHO, <>0=NOECHO + ABORT_UARTI2CS \ run tests -[UNDEFINED] CONSTANT [IF] -\ https://forth-standard.org/standard/core/CONSTANT -\ CONSTANT <name> n -- define a Forth CONSTANT -: CONSTANT -CREATE -HI2LO -MOV TOS,-2(W) \ PFA = n -MOV @PSP+,TOS -MOV @RSP+,IP -MOV @IP+,PC -ENDCODE -[THEN] + MARKER {UARTI2CS} \ USER_PARAM-2 addr = {UARTI2CS}-2 <-- REMOVE_APP (RET_ADR by default) + 10 ALLOT \ USER_PARAM addr = {UARTI2CS} <-- previous HARD_APP +\ USER_PARAM+2 addr = {UARTI2CS}+2 <-- previous SLEEP_APP +\ USER_PARAM+4 addr = {UARTI2CS}+4 <-- previous TERM_VEC +\ USER_PARAM+6 addr = {UARTI2CS}+6 <-- previous P1_VEC +\ USER_PARAM+8 addr = {UARTI2CS}+8 <-- I2C_Slave_Addr << 1 +\ USER_PARAM+9 addr = {UARTI2CS}+9 <-- Half_Duplex flag : 4 --> NOECHO, <> 4 --> ECHO -I2CSLA0 CONSTANT I2CS_ADR \ I2CSLA0=$FFA2 + [UNDEFINED] TSTBIT + [IF] + CODE TSTBIT \ addr bit_mask -- true/flase flag + MOV @PSP+,X + AND @X,TOS + MOV @IP+,PC + ENDCODE + [THEN] \ note: HDNCODE definitions are HiDdeN and cannot be executed from TERMINAL -\---------------------------\ -HDNCODE I2CSTOP \ sends a STOP on I2C_BUS -\---------------------------\ _ -BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low) -NOP3 \ 3 l _ -BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ SDA as output ==> SDA low -NOP3 \ 3 l _ -BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) -NOP3 \ 3 h _ -BIC.B #SM_SDA,&I2CSM_DIR \ 3 h _^ relase SDA (high) when SCL is high = STOP -MOV @RSP+,PC \ -ENDCODE \ -\---------------------------\ - -\---------------------------\ -HDNCODE STOP_U2I \ STOP_APP subroutine, the next of TERATERM(ALT+B)|SW2+RST|SYS_failures -\ --------------------------\ UARTI2CS can't be stopped by any other means. -BW1 \ <-- I2C_MASTER_RX <-- TERATERM break (Alt+B) -CMP #RET_ADR,&{UARTI2CS}+8 \ -0<> IF \ run STOP_U2I once, only if MARKER_DOES is already initialized -\ \ ----------------------\ -\ BIC.B #LED2,&LED2_DIR \ set RX green led OFF -\ BIC.B #LED2,&LED2_OUT \ set RX green led OFF -\ BIC.B #LED1,&LED1_DIR \ set TX red led OFF -\ BIC.B #LED1,&LED1_OUT \ set TX red led OFF -\ \ ----------------------\ - CALL #I2CSTOP \ stop properly I2C_BUS - MOV #SM_BUS,W \ - BIC.B W,&I2CSM_DIR \ restore I2C_BUS I/O as input - BIS.B W,&I2CSM_OUT \ with pull up resistors - BIS.B W,&I2CSM_REN \ -\ MOV #0,&TA0CTL \ stop timer and clear its interrupt flags IE, IFG - MOV #0,&TB0CTL \ stop timer and clear its interrupt flags IE, IFG -\ --------------------------\ - MOV #{UARTI2CS}+10,W \ W = addr of first saved param after MARKER_DOES - MOV #RET_ADR,-2(W) \ don't forget: restore default MARKER_DOES call address ! - MOV @W+,&WARM+2 \ restore previous (default) INI_APP address - MOV @W+,&TERM_VEC \ restore previous (default) TERM_VEC value -\ MOV @W+,&TA0_X_VEC \ restore previous (default) TB0_x_VEC value - MOV @W+,&TB0_X_VEC \ restore previous (default) TB0_x_VEC value - MOV #1,TOS \ to identify Alt+B|SW2+RST request in WARM message -THEN \ -\ --------------------------\ when STOP_U2I is the next of: TERATERM(ALT+B)|SW2+RESET|SYS_failures -MOV @RSP+,PC \ RET to: WARM_BODY|WARM_BODY|WARM_BODY -ENDCODE \ -\ --------------------------\ +\ ----------------------------\ + HDNCODE I2CM_STOP \ sends a STOP on I2C_BUS +\ ----------------------------\ _ + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low) + NOP3 \ 3 l _ + BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ SDA as output ==> SDA low + NOP3 \ 3 l _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) + NOP3 \ 3 h _ + BIC.B #SM_SDA,&I2CSM_DIR \ 3 h _^ relase SDA (high) when SCL is high = STOP + MOV @RSP+,PC \ + ENDCODE \ +\ ----------------------------\ +\ ----------------------------\ + CODE REMOVE_U2I \ +\ ----------------------------\ +BW1 \ <-- TERATERM(ALT+B)|USBtoI2C_bridge(SW2)|SYS_failures +\ vvvvvvvvvvvv OPTION vvvvvvvv\ + BIC.B #LED1,&LED1_OUT \ set TX red led OFF + BIC.B #LED1,&LED1_DIR \ set TX red led pin as input + BIC.B #LED2,&LED2_OUT \ set RX green led OFF + BIC.B #LED2,&LED2_DIR \ set RX green led pin as input +\ ^^^^^^^^^^^^ OPTION ^^^^^^^^\ + CALL #I2CM_STOP \ stop properly I2C_BUS + MOV #SM_BUS,W \ + BIC.B W,&I2CSM_DIR \ restore I2C_BUS I/O as input + BIS.B W,&I2CSM_OUT \ with pull up resistors + BIS.B W,&I2CSM_REN \ +\ ----------------------------\ + MOV #0,&TB0CTL \ stop TBO + BIC.B #BIT7,&P1SEL1 \ clear P1.7 SEL1 + BIC.B #BIT7,&P1DIR \ P1.7 as input + BIC.B #BIT6,&P1IE \ stop P1.6 int +\ ----------------------------\ + CMP #RET_ADR,&{UARTI2CS}-2 \ + 0<> IF + MOV #{UARTI2CS},W \ W = addr of first user parameter following MARKER + MOV #RET_ADR,-2(W) \ don't forget: restore default MARKER_DOES call address ! + MOV @W+,&HARD_APP \ restore previous (default) HARD_APP value + MOV @W+,&SLEEP_APP \ restore previous (default) SLEEP_APP value + MOV @W+,&TERM_VEC \ restore previous (default) TERM_VEC value + MOV @W+,&P1_VEC \ restore previous (default) P1_VEC value + THEN +\ ----------------------------\ + MOV #1,TOS \ TOS = USERSYS value we want for TERATERM(ALT+B)|USBtoI2C_bridge(SW2)|SYS_failures events + MOV #UART_WARM+4,PC \ display WARM message then RET to FORTH interpreter + ENDCODE \ REMOVE_U2I is redirected to this CODENNM definition +\ ----------------------------\ -\ \ vvvvvvvMulti-Master-Modevvvvvv\ -\ HDNCODE DO_IDLE \ -\ MOV #4,W \ 1 wait bus idle time = 5 µs @ 16 MHz -\ BEGIN -\ BIT.B #SM_SCL,&I2CSM_IN \ 3 -\ 0= IF \ 2 -\ MOV #4,W \ 1 if SCL is LOW -\ THEN -\ BIT.B #SM_SDA,&I2CSM_IN \ 3 -\ 0= IF \ 2 -\ MOV #4,W \ 1 if SDA is LOW -\ THEN -\ SUB #1,W \ 1 -\ 0= UNTIL \ 2 -\ MOV @RSP+,PC -\ ENDCODE -\ \ ^^^^^^^Multi-Master-Mode^^^^^^\ +\ ----------------------------------------\ + HDNCODE I2CM_START \ WX use I2C_Master TX ADdRess with collision detection and resolution +\ ----------------------------------------\ _ + BIS.B #SM_SDA,&I2CSM_DIR \ 3 v_ force SDA as output (low) + BIS.B &{UARTI2CS}+8,X \ 3 X = Slave_Address&flag + NOP3 \ 3 + BIS.B #SM_SCL,&I2CSM_DIR \ 3 v_ force SCL as output (low) +\ ----------------------------------------\ +\ I2C_Master_Send_I2C_Addr \ +\ ----------------------------------------\ + MOV.B #8,W \ 1 l count for 7 bits address + R/w bit + BEGIN \ + ADD.B X,X \ 1 l shift one left + U>= IF \ 2 l carry set ? + BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor + ELSE \ 2 l + BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low + THEN \ l _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) +\ BEGIN \ +\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h The I2C_Slave hardware takes the I2C address without delay even if the CPU is in the LPM4 state (wired logic). +\ 0<> UNTIL \ 2 h + BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low +\ vvvvvvvvv Multi-Master-Mode vvvvvvvv\ + 0= IF \ 2 l if SDA input low + BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high + 0= IF \ 2 l = collision detected + BIS.B #SM_BUS,&I2CSM_DIR \ 4 l release SDA,SCL + BIC.B #SM_BUS,&I2CSM_IES \ 4 l set IES for SDA_IFG and SCL_IFG on low_to_high transition + BEGIN \ SDA_IFG=1, SCL_IFG=1 + BIT.B #SM_BUS,&I2CSM_IFG \ 4 SM_BUS IFG ? + BIC.B #SM_BUS,&I2CSM_IFG \ 4 clear SM_BUS IFG + 0<> IF \ 2 if yes +\ MOV #3,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 8 MHz +\ MOV #6,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 16 MHz + MOV #9,W \ 2 SCL is still active: load for 8*15/MHz = 5.6 µs delay @ 24 MHz + ELSE \ 2 if no + NOP2 \ 2 does the same + NOP2 \ 2 time as if yes + THEN + SUB #1,W \ 1 + 0= UNTIL \ 2 end of collision process + ADD #2,RSP \ remove RET to Nack/Ack processing and select.. + MOV @RSP+,PC \ 2 l RET to ReStart after a collision detection + THEN \ + THEN \ +\ ^^^^^^^^^ Multi-Master-Mode ^^^^^^^^\ + SUB #1,W \ 1 l bits count-1 + 0= UNTIL \ 2 l +\ ----------------------------------------\ +\ I2C_Master_TX get Slave Ack/Nack \ +\ ----------------------------------------\ _ + BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _^_ after TX address we must release SDA to read Ack/Nack from Slave + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) + BEGIN \ we must wait I2C_Slave software + BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released + 0<> UNTIL \ 2 h because Slave can strech SCL low (wake up from interrupt) + BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low +\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^\ + MOV @RSP+,0(RSP) \ remove RET to ReStart after a collision detection +\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvv\ + MOV @RSP+,PC \ RET to Nack/Ack select + ENDCODE +\ ----------------------------------------\ -\ **************************************\ -HDNCODE U2I_TERM_INT \ UART RX interrupt starts on first char of each line sent by TERMINAL -\ **************************************\ -ADD #4,RSP \ 1 remove unused PC_RET and SR_RET -\ --------------------------------------\ -MOV &{UARTI2CS}+16,W \ 3 W = HALF_DUPLEX = 0 if ECHO, -1 if NOECHO -MOV #PAD_ORG,T \ 2 T = buffer pointer for UART_TERMINAL input -MOV #$0D,S \ 2 S = 'CR' = penultimate char of line to be RXed by UART -BEGIN \ - MOV.B &TERM_RXBUF,Y \ 3 move char from TERM_RXBUF... - ADD #1,T \ 1 - MOV.B Y,-1(T) \ 3 ... to input buffer - CMP.B Y,S \ 1 char = CR ? (if yes goto next REPEAT) -0<> WHILE \ 2 if <> - CMP #0,W \ 1 HALF_DUPLEX = 0 ? - 0= IF \ 2 yes, echo is ON - BEGIN \ ) - BIT #2,&TERM_IFG \ 3 > Test TX_Buf empty, mandatory for low baudrates - 0<> UNTIL \ 2 ) - MOV.B Y,&TERM_TXBUF \ 3 echo char to UART_TERMINAL - THEN \ - BEGIN \ - BIT #1,&TERM_IFG \ 3 wait for next char received - 0<> UNTIL \ 2 -REPEAT \ 2 31 cycles loop ==> up to UART 2.58 Mbds @ 8MHz -CALL #UART_RXOFF \ stops UART RX still char CR is received, the LF char is being transmitted. -BEGIN \ - BIT #1,&TERM_IFG \ 3 char LF received ? -0<> UNTIL \ 2 -\ --------------------------------------\ -BW2 \ <=== Ctrl_char $01 (KEY input) -\ --------------------------------------\ -MOV.B &TERM_RXBUF,S \ 3 S = last char RXed by UART (LF|KEY) -MOV.B S,0(T) \ 4 store it into buffer -\ ======================================\ -\ ======================================\ -\ I2C MASTER TX \ now we transmit UART RX buffer (PAD) to I2C_Slave, S = LF|KEY = last char to transmit -\ ======================================\ -\ ======================================\ -BW3 \ <=== multi master TX -\ --------------------------------------\ -\ BIS.B #LED1,&LED1_DIR \ red led ON = I2C TX -\ BIS.B #LED1,&LED1_OUT \ red led ON = I2C TX -\ --------------------------------------\ -\ I2C_Master_TX_Start \ here, SDA and SCL must be in idle state -\ --------------------------------------\ _ -BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ force SDA low when SCL is high = START -MOV.B &I2CS_ADR,X \ 3 h X = Slave_Address -MOV #PAD_ORG,Y \ 2 h Y = buffer pointer for I2C_Master TX -NOP3 \ 3 h _ -BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low) -\ --------------------------------------\ -BEGIN -\ ------------------------------------\ -\ I2C_Master_TX address/Data \ -\ ------------------------------------\ - MOV.B #8,W \ 1 l prepare 8 bits address - BEGIN \ - ADD.B X,X \ 1 l shift one left - U>= IF \ 2 l carry set ? - BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor - ELSE \ 2 l - BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low - THEN \ l _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) - BEGIN \ we must wait I2C_Slave software - BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released - 0<> UNTIL \ 2 h (because Slave can strech SCL low) -\ \ vvvvvvvvMulti-Master-Modevvvvvvv\ -\ BIT.B #SM_SDA,&I2CSM_IN \ 3 h test SDA -\ \ ^^^^^^^^Multi-Master-Mode^^^^^^^\ _ - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low -\ \ vvvvvvvvvvvvMulti-Master-Modevvvvvvvvvvv\ -\ 0= IF \ 2 l SDA input low -\ BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high -\ 0= IF \ 2 l = collision detected -\ BIS.B #SM_SCL,&I2CSM_DIR \ 4 l release SCL first -\ CALL #DO_IDLE \ wait stable idle state -\ GOTO BW3 \ 2 l goto START TX -\ THEN \ -\ THEN \ -\ \ ^^^^^^^^^^^^Multi-Master-Mode^^^^^^^^^^^\ - SUB #1,W \ 1 l bits count-1 - 0= UNTIL \ 2 l -\ ------------------------------------\ - BIC.B #SM_SDA,&I2CSM_DIR \ 3 l after TX byte we must release SDA to read Ack/Nack from Slave -\ ------------------------------------\ -\ I2C_Master_TX get Slave Ack/Nack \ -\ ------------------------------------\ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) -\ BEGIN \ -\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless -\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low - NOP3 \ 3 h replaced by NOP3. - BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low, to keep I2C_BUS until next I2C_MASTER START (RX|TX) -\ ------------------------------------\ -0= WHILE \ 1- Slave Ack received \ 2 l out of loop if Nack (goto THEN next REPEAT) -\ ------------------------------------\ -\ I2C_Master_TX_data_loop \ -\ ------------------------------------\ - CMP S,T \ 1 last char TXed = last char RXed ? (when address is sent, T = 16bits <> S = 8bits) -\ ------------------------------------\ -0<> WHILE \ 2- TXed char <> last char \ 2 out of loop if TXed char T = last char S to be TXed (goto below REPEAT) -\ ------------------------------------\ - MOV.B @Y+,X \ 2 l get next RXed char - MOV X,T \ 1 T = last TX char for comparaison above, on next loop. -REPEAT \ <-- WHILE2 search "Extended control-flow patterns"... -THEN \ <-- WHILE1 ...in https://forth-standard.org/standard/rationale -\ \ --------------------------------------\ -\ BIC.B #LED1,&LED1_DIR \ red led OFF = endof I2C TX -\ BIC.B #LED1,&LED1_OUT \ red led OFF = endof I2C TX -\ \ --------------------------------------\ -GOTO FW1 \ X > 4 ==> reSTART RX repeated every 1/2s -\ ======================================\ -\ END OF I2C MASTER TX \ SCL is kept low until START RX --┐ -\ ======================================\ | -ENDCODE \ | -\ **************************************\ v +\ ****************************************\ + HDNCODE U2I_TERM_INT \ UART RX interrupt starts on first char of each line sent by TERMINAL +\ ****************************************\ + ADD #4,RSP \ 1 remove unused PC_RET and SR_RET +\ ----------------------------------------\ +\ get one line from UART TERMINAL to PAD \ S = 'CR', T = 0 +\ ----------------------------------------\ + BEGIN \ + MOV.B &TERM_RXBUF,Y \ 3 move char from TERM_RXBUF... + MOV.B Y,PAD_ORG(T) \ 3 ... to input buffer + ADD #1,T \ 1 + CMP.B Y,S \ 1 char = CR ? (if yes goto next REPEAT) + 0<> WHILE \ 2 if <> + CMP #4,W \ 1 HALF_DUPLEX = 4 ? + 0<> IF \ 2 no, echo is ON + BEGIN \ ) + BIT #2,&TERM_IFG \ 3 > Test TX_Buf empty, mandatory for low baudrates + 0<> UNTIL \ 2 ) + MOV.B Y,&TERM_TXBUF \ 3 return all characters to UART_TERMINAL except CR+LF which will be later by I2C_SLAVE + THEN \ + BEGIN \ + BIT #1,&TERM_IFG \ 3 wait for next char received + 0<> UNTIL \ 2 + REPEAT \ 2 2 cycles loop ==> up to UART 2.58 Mbds @ 8MHz + CALL #UART_RXOFF \ stops UART RX still char CR is received, the LF char is being transmitted. + BEGIN \ + BIT #1,&TERM_IFG \ 3 char LF received ? + 0<> UNTIL \ 2 +\ ----------------------------------------\ +BW2 \ <=== KEY input from TERMINAL, via I2C_MASTER +\ ----------------------------------------\ + MOV.B &TERM_RXBUF,S \ 3 S = last char RXed by UART (LF|KEY_input), used by I2C_MASTER_TX as last byte to be TXed. + MOV.B S,PAD_ORG(T) \ 3 store it into buffer +\ ========================================\ here I2C_Slave is sleeping in its ACCEPT routine +\ I2C MASTER TX \ now we transmit UART RX buffer (PAD) to I2C_Slave, S = LF|KEY = last char to transmit +\ ========================================\ +\ ----------------------------------------\ +\ I2C_Master_TX_Start \ S = last char UART RXed +\ ----------------------------------------\ +\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^\ + PUSH PC \ PUSH next address as RET for START with collision detection +\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvv\ + MOV #0,X \ to Start I2C_Master_TX + CALL #I2CM_START \WX use return to I2C_Master_TX_Start if collision detection on I2C address + 0<> ?GOTO FW2 \ if Nack on address +\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\ + BIS.B #LED1,&LED1_OUT \ red led ON = I2C TX +\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^\ + MOV #PAD_ORG,Y \ 2 Y = buffer pointer for I2C_Master TX datas + BEGIN \ + MOV.B @Y,X \ 2 l get first char to be TX +\ ------------------------------------\ +\ I2C_Master_TX Data from PAD \ +\ ------------------------------------\ + MOV.B #8,W \ 1 l count for 8 bits data + BEGIN \ + ADD.B X,X \ 1 l shift one left + U>= IF \ 2 l carry set ? + BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor + ELSE \ 2 l + BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low + THEN \ l _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) +\ --------------------------------\ + BEGIN \ + BIT.B #SM_SCL,&I2CSM_IN \ 3 h TERM2SD" doesn't work if you replace this test by NOP3 ! + 0<> UNTIL \ 2 h +\ --------------------------------\ _ + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low + SUB #1,W \ 1 l bits count-1 + 0= UNTIL \ 2 l +\ ------------------------------------\ + BIC.B #SM_SDA,&I2CSM_DIR \ 3 l after TX byte we must release SDA to read Ack/Nack from Slave +\ ------------------------------------\ +\ I2C_Master_TX get Slave Ack/Nack \ +\ ------------------------------------\ _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) + BEGIN \ + BIT.B #SM_SCL,&I2CSM_IN \ 3 h + 0<> UNTIL \ 2 h + BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA state + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low, to keep I2C_BUS until next I2C_MASTER START (RX|TX) +\ ----------------------------------------\ + 0= WHILE \ 1- Slave Ack received \ 2 l out of loop if Nack on data +\ ----------------------------------------\ +\ I2C_Master_TX_Data_Loop \ +\ ----------------------------------------\ + CMP.B @Y+,S \ 2 last char I2C TXed = last char UART RXed (LF|KEY) ? +\ ----------------------------------------\ + 0= UNTIL \ TXed char = last char \ 2 +\ ----------------------------------------\ + THEN \ <-- WHILE1 case of I2C_Slave Nack on Master_TX +\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvv\ + BIC.B #LED1,&LED1_OUT \ red led OFF = endof I2C TX +\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^\ + GOTO FW1 \ SCL is kept low ──────────┐ +\ ========================================\ | +\ END OF I2C MASTER TX \ | +\ ========================================\ | + ENDCODE \ | +\ ****************************************\ v -\ **************************************\ -HDNCODE HALF_S_INT \ wakes up every 1/2s to listen I2C Slave or break from TERMINAL. -\ **************************************\ -ADD #4,RSP \ 1 remove PC_RET and SR_RET | -\ --------------------------------------\ | -FW1 \ <-- the next of TERM_INT above <--┘ -BW3 \ <-- the next of INI_U2I below <--┐ -\ --------------------------------------\ | -CMP #0,&KERNEL_ADDON \ 3 KERNEL_ADDON(BIT15) = LF XTAL flag -0>= IF \ if no LF XTAL -\ MOV #%0001_0101_0110,&TA0CTL \ 3 (re)starts RX_timer,ACLK=VLO=8kHz,/2=4096Hz,up mode,clear timer,enable TA0 int, clear IFG - MOV #%0001_0101_0110,&TB0CTL \ 3 (re)starts RX_timer,ACLK=VLO=8kHz,/2=4096Hz,up mode,clear timer,enable TB0 int, clear IFG -ELSE \ if LF XTAL -\ MOV #%0001_1101_0110,&TA0CTL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32768,/8=4096Hz,up mode,clear timer,enable TA0 int, clear IFG - MOV #%0001_1101_0110,&TB0CTL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32738,/8=4096Hz,up mode,clear timer,enable TB0 int, clear IFG -THEN \ -\ ======================================\ -\ I2C_MASTER RX \ le driver I2C_Master envoie START RX en boucle continue (X < 4) ou discontinue (X >= 4). -\ ======================================\ le test d'un break en provenance de l'UART est intégré dans cette boucle. -BEGIN \ I2C MASTER START RX \ ABORT|WARM loop back -\ ------------------------------------\ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL to enable ReSTART RX - BIT #8,&TERM_STATW \ 3 break (Alt+B) sent by TERATERM ? - 0<> ?GOTO BW1 \ goto STOP_U2I, exit to WARM+4. -\ ------------------------------------\ -\ I2C_Master_RX_Start_Cond \ here, SDA and SCL must be in idle state -\ ------------------------------------\ _ - BIS.B #SM_SDA,&I2CSM_DIR \ 3 l v_ force SDA as output (low) - MOV.B &I2CS_ADR,Y \ 3 h X = Slave_Address - BIS.B #1,Y \ 1 h set Master RX - NOP2 \ 2 _ - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low) -\ ------------------------------------\ -\ I2C_Master_RX_Send_address \ may be SCL is held low by slave -\ ------------------------------------\ - MOV.B #8,W \ 1 l prepare 8 bits address - BEGIN \ - ADD.B Y,Y \ 1 l shift one left - U>= IF \ 2 l carry set ? - BIC.B #SM_SDA,&I2CSM_DIR \ 3 l yes : SDA as input ==> SDA high because pull up resistor - ELSE \ 2 l - BIS.B #SM_SDA,&I2CSM_DIR \ 3 l no : SDA as output ==> SDA low - THEN \ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) -\ BEGIN \ -\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless -\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low - NOP3 \ 3 replaced by NOP3 -\ \ vvvvvvMulti-Master-Modevvvvvvvvv\ -\ BIT.B #SM_SDA,&I2CSM_IN \ 3 h test SDA -\ \ ^^^^^^Multi-Master-Mode^^^^^^^^^\ _ - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ force SCL as output (low) -\ \ vvvvvvvvvvvvMulti-Master-Modevvvvvvvvvvv\ -\ 0= IF \ 2 l SDA input low -\ BIT.B #SM_SDA,&I2CSM_DIR \ 3 l + SDA command high -\ 0= IF \ 2 l = collision detected -\ BIS.B #SM_SCL,&I2CSM_DIR \ 4 l release SCL first -\ CALL #DO_IDLE \ wait stable idle state -\ GOTO BW3 \ 2 l goto START RX -\ THEN \ -\ THEN \ -\ \ ^^^^^^^^^^^^Multi-Master-Mode^^^^^^^^^^^\ - SUB #1,W \ 1 l bits count - 1 - 0= UNTIL \ 2 l -\ ------------------------------------\ -\ Wait Ack/Nack on address \ -\ ------------------------------------\ _ - BIC.B #SM_SDA,&I2CSM_DIR \ 3 l _^_ after TX address we must release SDA to read Ack/Nack from Slave - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) - BEGIN \ we must wait I2C_Slave software - BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released - 0<> UNTIL \ 2 h (because Slave can strech SCL low) - BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low -\ ------------------------------------\ - 0<> IF \ Nack_On_Address \ 2 l -\ --------------------------------\ -\ I2C_Master Send STOP \ -\ --------------------------------\ - CALL #I2CSTOP \ - MOV #SLEEP,PC \ 4 goto dodo for 1/2 s .. wake up by HALF_S_INT - THEN \ 2 -\ ------------------------------------\ -\ I2C_Master_RX_data \ -\ \ ------------------------------------\ -\ BIS.B #LED2,&LED2_DIR \ green led ON = I2C RX -\ BIS.B #LED2,&LED2_OUT \ green led ON = I2C RX -\ \ ------------------------------------\ - BEGIN - BEGIN - BIC.B #SM_SDA,&I2CSM_DIR \ 4 l after Ack and before RX next byte, we must release SDA - MOV.B #8,W \ 1 l prepare 8 bits transaction -\ ----------------------------\ - BEGIN \ -\ -------------------------\ _ -\ do SCL pulse \ SCL _| |_ -\ -------------------------\ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) -\ BEGIN \ -\ BIT.B #SM_SCL,&I2CSM_IN \ 3 h testing SCL released is useless -\ 0<> UNTIL \ 2 h because no risk of Slave streching SCL low - NOP3 \ 3 replaced by NOP3 - BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low 13~ - ADDC.B X,X \ 1 l C <--- X(7) ... X(0) <--- SDA - SUB #1,W \ 1 l count down of bits - 0= UNTIL \ 2 l here, slave releases SDA -\ ----------------------------\ -\ case of RX data $FF \ -\ ----------------------------\ - CMP.B #-1,X \ 1 - 0= IF \ 2 received char $FF: let's consider that the slave is lost... - MOV #2,X \ to do ABORT action - THEN \ -\ ----------------------------\ - CMP.B #8,X \ 1 l $08 = char BS - U>= WHILE \ 2 l ASCII char received, from char 'BS' up to char $7F. -\ ----------------------------\ - BEGIN \ - BIT #2,&TERM_IFG \ 3 l UART TX buffer empty ? - 0<> UNTIL \ 2 l loop if no -\ ----------------------------\ - BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack -\ ----------------------------\ -\ I2C_Master_RX Send Ack \ on ASCII char >= $08 -\ ----------------------------\ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) - BEGIN \ we must wait I2C_Slave software - BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released - 0<> UNTIL \ 2 h (because Slave can strech SCL low) -\ ----------------------------\ - MOV.B X,&TERM_TXBUF \ 3 h send RXed ASCII char to UART TERMINAL -\ ----------------------------\ _ - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low - REPEAT \ 2 l loop back to I2C_Master_RX_data for chars >= 8 -\ --------------------------------\ -\ case of RX CTRL_Chars < $08 \ here Master holds SCL low, Slave can test it: CMP #8,&TERM_STATW -\ --------------------------------\ see forthMSP430FR_TERM_I2C.asm - CMP.B #4,X \ 1 - U>= IF \ 2 - MOV #0,&{UARTI2CS}+16 \ preset ECHO - 0= IF \ 2 - MOV #-1,&{UARTI2CS}+16 \ 3 set NOECHO if char $04 - THEN - BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack for Ctrl_Chars $04 $05 +\ wakes up every 1/2s by P1.6 int to listen I2C Slave or +\ break from TERMINAL/USB_to_I2C_bridge. +\ ********************************************\ | + HDNCODE 500MS_INT \ | +\ ********************************************\ | + ADD #4,RSP \ 1 remove PC_RET, SR_RET | +\ --------------------------------------------\ | +FW1 \ <────── does START <──────┘ +FW2 \ <────── if Nack on Address Master TX +\ ^^^^^^^^^^^ Multi-Master-Mode ^^^^^^^^^^^^^^\ + PUSH PC \ PUSH next address as RET for START with collision detection +\ vvvvvvvvvvv Multi-Master-Mode vvvvvvvvvvvvvv\ +\ ============================================\ +\ I2C_MASTER RX \ le driver I2C_Master envoie START RX en boucle continue (X < 4) ou discontinue (X >= 4). +\ ============================================\ le test d'un break en provenance de l'UART est intégré dans cette boucle. + BEGIN \ +\ ----------------------------------------\ +\ QUIT on user request tests \ +\ ----------------------------------------\ + BIT #8,&TERM_STATW \ 3 break sent by TERATERM (Alt+B) ? + 0<> ?GOTO BW1 \ 2 goto REMOVE_U2I, RET to WARM+4 with TOS=1. + BIT.B #SW2,&SW2_IN \ 3 USB_to_I2C_bridge(SW2) pressed ? + 0= ?GOTO BW1 \ 2 goto REMOVE_U2I, RET to WARM+4 with TOS=1. +\ ----------------------------------------\ +\ I2C MASTER START RX \ +\ ----------------------------------------\ _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL to enable START RX + MOV #1,X \ to Start I2C_Master as RX + CALL #I2CM_START \ Start MASTER RX + 0<> IF \ if Nack_On_Address + CALL #I2CM_STOP \ I2C_Master Send STOP + MOV #'.',&TERM_TXBUF \ to view the absence of I2C_target at the I2C_Addr provided. + MOV #SLEEP,PC \ which executes SLEEP_U2I then RXON before LPM0 shut down. + THEN \ +\ ----------------------------------------\ +\ I2C_Master_RX_data \ +\ ----------------------------------------\ +\ vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvvvv\ + BIS.B #LED2,&LED2_OUT \ green led ON = I2C RX +\ ^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^^^\ + BEGIN \ + BEGIN \ + BIC.B #SM_SDA,&I2CSM_DIR \ 4 l after Ack and before RX next byte, we must release SDA + MOV.B #8,W \ 1 l prepare 8 bits transaction + BEGIN \ +\ ----------------------------\ _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) +\ ----------------------------\ + BIT.B #SM_SDA,&I2CSM_IN \ 3 h get SDA +\ ----------------------------\ _ + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low 13~ + ADDC.B X,X \ 1 l C <--- X(7) ... X(0) <--- SDA + SUB #1,W \ 1 l count down of bits + 0= UNTIL \ 2 l here, slave has set SDA for next bit +\ --------------------------------\ +\ case of RX data $FF \ case of -1 SYS for example +\ --------------------------------\ + CMP.B #-1,X \ 1 + 0= IF \ 2 received char $FF: let's consider that the slave is lost... + MOV #2,X \ to do ABORT action after Nack sent + THEN \ +\ --------------------------------\ + CMP.B #8,X \ 1 l $08 = char BS + U>= WHILE \ 2 l ASCII char received, from char 'BS' up to char $7F. +\ --------------------------------\ +\ I2C_Master_RX Send Ack \ on ASCII char >= $08 +\ --------------------------------\ + BIS.B #SM_SDA,&I2CSM_DIR \ 3 l _ set SDA as Ack + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) + BEGIN \ we must wait I2C_Slave software (data processing) + BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released, + 0<> UNTIL \ 2 h _ because Slave can strech SCL low + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low +\ --------------------------------\ +\ I2C_Master echoes to TERMINAL \ +\ --------------------------------\ + BEGIN \ + BIT #2,&TERM_IFG \ 3 l UART TX buffer empty ? + 0<> UNTIL \ 2 l loop if no + MOV.B X,&TERM_TXBUF \ 3 h send RXed ASCII char to UART TERMINAL + REPEAT \ 2 l loop back to I2C_Master_RX_data for chars >= 8 +\ ------------------------------------\ +\ case of RX CTRL_Chars < $08 \ here Master holds SCL low, Slave can test it: CMP #8,&TERM_STATW +\ ------------------------------------\ see forthMSP430FR_TERM_I2C.asm + CMP.B #4,X \ 1 + U>= IF \ 2 + MOV.B X,&{UARTI2CS}+9 \ set NOECHO = $04, ECHO = $05 + BIS.B #SM_SDA,&I2CSM_DIR \ 3 l prepare Ack for Ctrl_Chars $04 $05 + THEN \ +\ ------------------------------------\ +\ Master_RX send Ack/Nack on data \ Ack for $04, $05, Nack for $00, $01, $02 +\ ------------------------------------\ _ + BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) + BEGIN \ we must wait I2C_Slave software (data processing) + BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released + 0<> UNTIL \ 2 h (because Slave can strech SCL low) + BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA as TX Ack/Nack state + BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low +\ ------------------------------------\ l + 0<> UNTIL \ if Ack, loop back to Master_RX data for CTRL_Char $04,$05 +\ ----------------------------------------\ +\ Nack is sent by Master \ l case of CTRL-Char {$00|$01|$02} +\ ----------------------------------------\ + CMP.B #2,X \ $02 = ctrl_char for ABORT request + U>= WHILE \ +\ ----------------------------------------\ +\ CTRL_Char $02|$03 \ l if ABORT request, SDA is high, SCL is low +\ ----------------------------------------\ + 0= IF \ if ABORT request $02 : + MOV.B #0,&{UARTI2CS}+9 \ set echo ON I2C_Master side + CALL #UART_RXON \ resume UART downloading source file + BEGIN \ + BIC #UCRXIFG,&TERM_IFG \ clear UCRXIFG + MOV &FREQ_KHZ,X \ 1000, 2000, 4000, 8000, 16000, 240000 +\ BEGIN MOV #32,W \ 2~ <-------+ windows 10 seems very slow... +\ BEGIN SUB #1,W \ 1~ <---+ | ==> ((32*3)+5)*FREQ_KHZ/1000 = 101ms delay +\ 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer +\ SUB #1,X \ 1~ | +\ 0= UNTIL \ 2~ 101~ loop -----+ + BEGIN MOV #65,W \ 2~ <-------+ linux with minicom seems very very slow... + BEGIN SUB #1,W \ 1~ <---+ | ==> ((65*3)+5)*FREQ_KHZ/1000 = 200ms delay + 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer + SUB #1,X \ 1~ | + 0= UNTIL \ 2~ 200~ loop -----+ + BIT #UCRXIFG,&TERM_IFG \ 4 new char in TERMRXBUF during this delay ? + 0= UNTIL \ 2 yes, the input stream may be still active: loop back THEN -\ --------------------------------\ -\ Master_RX send Ack/Nack on data \ Ack for $04, $05, Nack for $00, $01, $02, $03 -\ --------------------------------\ _ - BIC.B #SM_SCL,&I2CSM_DIR \ 3 l _^ release SCL (high) - BEGIN \ we must wait I2C_Slave software - BIT.B #SM_SCL,&I2CSM_IN \ 3 h by testing SCL released - 0<> UNTIL \ 2 h (because Slave can strech SCL low) - BIT.B #SM_SDA,&I2CSM_IN \ 3 h _ get SDA as TX Ack/Nack state - BIS.B #SM_SCL,&I2CSM_DIR \ 3 h v_ SCL as output : force SCL low -\ --------------------------------\ l - 0<> UNTIL \ if Ack, loop back to Master_RX data for CTRL_Char $04,$05 -\ ------------------------------------\ -\ Nack is sent by Master \ l case of CTRL-Char {$00|$01|$02|$03} -\ ------------------------------------\ - CMP.B #2,X \ $02 = ctrl_char for ABORT request -U>= WHILE \ $03 = Ctrl_Char for WARM request -\ ------------------------------------\ -\ CTRL_Char $02|$03 \ l if ABORT|WARM requests, SDA is high, SCL is low -\ ------------------------------------\ - 0= IF \ if ABORT request: - MOV #0,&{UARTI2CS}+16 \ set echo ON I2C_Master side - CALL #UART_RXON \ resume UART downloading source file - BEGIN \ - BIC #UCRXIFG,&TERM_IFG \ clear UCRXIFG - MOV &FREQ_KHZ,Y \ 1000, 2000, 4000, 8000, 16000, 240000 - BEGIN MOV #32,W \ 2~ <-------+ windows 10 seems very slow... - BEGIN SUB #1,W \ 1~ <---+ | ==> ((32*3)+5)*1000 = 101ms delay - 0= UNTIL \ 2~ 3~ loop ---+ | to refill its USB buffer - SUB #1,Y \ 1~ | - 0= UNTIL \ 2~ 101~ loop -----+ -\ BEGIN MOV #65,W \ <-------+ linux with minicom seems very very slow... -\ BEGIN SUB #1,W \ <---+ | ==> ((65*3)+5)*1000 = 200ms delay -\ 0= UNTIL \ 3~ loop ---+ | to refill its USB buffer -\ SUB #1,Y \ | -\ 0= UNTIL \ 200~ loop -----+ - BIT #UCRXIFG,&TERM_IFG \ 4 new char in TERMRXBUF during this delay ? - 0= UNTIL \ 2 yes, the input stream may be still active: loop back - THEN \ -REPEAT \ l loop back to reSTART RX -\ --------------------------------------\ -\ I2C_Master_RX Send STOP \ l remainder: CTRL_Chars $00,$01 -\ --------------------------------------\ -CALL #I2CSTOP \ -\ \ --------------------------------------\ -\ BIC.B #LED2,&LED2_DIR \ green led OFF = endof I2C RX -\ BIC.B #LED2,&LED2_OUT \ green led OFF = endof I2C RX -\ ======================================\ -\ END OF I2C MASTER RX \ here I2C_bus is freed, Nack on Ctrl_char $FF|$00|$01 remains to be processed. -\ ======================================\ -\ I2C_Slave KEY ctl_char $01 \ I2C_Slave request for KEY input -\ --------------------------------------\ -CMP.B #1,X \ -\ Quand I2C_Master reçoit ce caractère de contrôle, -\ il attend un caractère en provenance de TERMINAL UART -\ et une fois ce caractère reçu reSTART TX pour l'envoyer à I2C_Slave -0= IF \ - MOV #PAD_ORG,T \ ready to store KEY char: MOV.B S,0(T) - CALL #UART_RXON \ enables TERMINAL to TX; use no registers - BEGIN \ wait for a char - BIT #UCRXIFG,&TERM_IFG \ received char ? - 0<> UNTIL \ - CALL #UART_RXOFF \ stops UART RX then - GOTO BW2 \ goto end of UART RX line input, for receiving last char -THEN \ -\ --------------------------------------\ -\ I2C_Slave ACCEPT ctrl_char $00 \ I2C_Slave requests I2C_Master to stop RX and start TX -\ --------------------------------------\ -\ en début de sa routine ACCEPT, I2C_Slave envoie sur le bus I2C le caractère de contrôle $00 -\ avant de s'endormir avec SLEEP -\ I2C_Master envoie NACK + STOP pour signifier la fin de la transaction. -\ --------------------------------------\ -\ et si I2C_Slave est sorti de son sommeil par un START RX, idem. -\ --------------------------------------\ -MOV #SLEEP,PC \ executes RXON (that enables TERMINAL to TX) before LPM0 shut down. -\ --------------------------------------\ -\ I2C_Master se réveillera au premier caractère saisi sur le TERMINAL ==> TERM_INT, -\ ou en fin du temps TxIFG ==> HALF_S_INT\ -ENDCODE \ -\ **************************************\ + REPEAT \ loop back to reSTART RX +\ --------------------------------------------\ +\ I2C_Master_RX Send STOP \ remainder: CTRL_Chars $00,$01 +\ --------------------------------------------\ + CALL #I2CM_STOP \ +\ vvvvvvvvvvvvvvv OPTION vvvvvvvvvvvvvvvvvvvvv\ + BIC.B #LED2,&LED2_OUT \ green led OFF = endof I2C RX +\ ^^^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^^^^^^^^\ +\ ============================================\ +\ END OF I2C MASTER RX \ here I2C_bus is freed, Nack on Ctrl_char $00|$01 remains to be processed. +\ ============================================\ + CMP.B #0,X \ +\ --------------------------------------------\ +\ I2C_Slave ACCEPT ctrl_char $00 \ I2C_Slave requests I2C_Master to stop RX +\ --------------------------------------------\ +\ en début de sa routine ACCEPT, I2C_Slave envoie sur le bus I2C le caractère de contrôle $00 +\ avant de s'endormir avec SLEEP. +\ Quand I2C_Slave est sorti de son sommeil par un START RX, il renvoie aussi un $00. +\ I2C_Master envoie alors ce NACK + STOP pour signifier la fin de la transaction. +\ --------------------------------------------\ +\ I2C_Master se réveillera au premier caractère saisi sur le TERMINAL ==> TERM_INT, +\ ou en fin du temps TxIFG ==> 500MS_INT \ + 0= IF \ prepare U2I_TERM_INT environment + MOV #SLEEP,PC \ which executes SLEEP_U2I then RXON, enabling TERMINAL TX, before LPM0 shut down. + THEN \ +\ --------------------------------------------\ +\ I2C_Slave KEY ctl_char $01 \ I2C_Slave request for KEY input +\ --------------------------------------------\ +\ Quand I2C_Master reçoit ce caractère de contrôle, +\ il attend un caractère en provenance de TERMINAL UART +\ et une fois ce caractère reçu ReStart TX pour l'envoyer à I2C_Slave + CALL #UART_RXON \ enables TERMINAL to TX; use no registers + BEGIN \ wait for a char + BIT #UCRXIFG,&TERM_IFG \ received char ? + 0<> UNTIL \ + CALL #UART_RXOFF \ stops UART RX; use no registers + MOV #0,T \ ready to store KEY char as last char to be received + GOTO BW2 \ goto end of UART RX line input + ENDCODE \ +\ ********************************************\ -\---------------------------\ -HDNCODE INI_U2I \ define INI_HARD_APP subroutine called by WARM -\ --------------------------\ -CALL &{UARTI2CS}+10 \ previous INI_APP executing init TERM_UC, activates I/O and sets TOS = RSTIV_MEM. -\ --------------------------\ TOS = SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures -CMP #$0E,TOS \ SVSHIFG SVSH event ? -0<> IF \ if not - CMP #$0A,TOS \ RSTIV_MEM >= violation memory protected areas ? - U>= ?GOTO BW1 \ execute STOP_U2I then RET to BODY of WARM -THEN \ RSTIV_MEM = {$00,$02,$04,$6,$0E} as: {WARM,PWR_ON,RST,COLD,SVSH_Threshold} -BIT.B #SW2,&SW2_IN \ SW2 pressed ? -0= ?GOTO BW1 \ if yes execute STOP_U2I then RET to BODY of WARM -MOV #0,&RSTIV_MEM \ clear RSTIV_MEM before next RST event! -\ --------------------------\ -\ init HALF_S_INT \ used to scan I2C_Slave hard RESET and to slow (re)START RX loop -\ --------------------------\ -MOV #$800,&TB0CCR0 \ time = (2047+1)/4096 = 0.5s -\ MOV #$800,&TA0CCR0 \ time = (2047+1)/4096 = 0.5s -\ --------------------------\ -\ init I2C_MASTER I/O \ see \inc\your_target.pat to find I2C MASTER SDA & SCL pins (as SM_BUS) -\ --------------------------\ -BIC.B #SM_BUS,&I2CSM_REN \ remove internal pullup resistors to avoid pulling down resistors with next instruction: -BIC.B #SM_BUS,&I2CSM_OUT \ preset SDA + SCL output LOW -\ --------------------------\ -GOTO BW3 \ goto I2C_Master START RX loop, with no other return than ALT+B|SW2+RST -\ --------------------------\ -ENDCODE \ -\ --------------------------\ -\ -\ ============================================================== -\ Driver UART to I2CM which does the bridge USB to I2C_FastForth -\ ============================================================== +\ --------------------------------------------\ + HDNCODE SLEEP_U2I \ new SLEEP_APP subroutine called by SLEEP before shutdown +\ --------------------------------------------\ + KERNEL_ADDON LF_XTAL TSTBIT \ + [IF] MOV #%1_1001_0100,&TB0CTL ; if ACLK=LFXTAL \ 3 (re)starts RX_timer,ACLK=LFXTAL=32768/4=8192Hz,up mode,clear timer + [ELSE] MOV #%1_0001_0100,&TB0CTL ; if ACLK=VLO \ 3 (re)starts RX_timer,ACLK=VLO=8kHz, up mode,clear timer + [THEN] \ + MOV.B &{UARTI2CS}+9,W \ 3 W = HALF_DUPLEX = $04 if NOECHO, $05 if ECHO + MOV #'CR',S \ 2 S = 'CR' = penultimate char of line to be RXed by UART + MOV #0,T \ 2 T = init buffer pointer for UART_TERMINAL input + BIC #BIT6,&P1IFG \ 3 clear P1.6 IFG + MOV &{UARTI2CS}+2,PC \ which executes RXON, enabling TERMINAL TX, before LPM0 shut down. + ENDCODE \ +\ --------------------------------------------\ +\ ----------------------------\ + HDNCODE INIT_U2I \ adds the INIT_HARD_APP to HARD_APP called by PUC|WARM +\ ----------------------------\ +\ init 500MS_INT \ used to scan I2C_Slave hard RESET and to slow down (re)START RX loop +\ ----------------------------\ +\ MOV #%10_1101_0100,&TB0_CTL \ ACLK/4=8192Hz, up mode, clear timer + MOV #4096,&TB0CCR0 \ time 0.5s +\ ------------------------------\ +\ set TB0.2 to generate pulse \ +\ ------------------------------\ + MOV #$60,&TB0CCTL2 \ output mode = set/reset + MOV #4095,&TB0CCR2 \ 0.12 ms pulse + BIS.B #BIT7,&P1DIR \ P1.7 as output + BIS.B #BIT7,&P1SEL1 \ P1.7 as TB0.2 output + BIS.B #BIT6,&P1IE +\ ----------------------------\ +\ init I2C_MASTER I/O \ see \inc\your_target.pat to find I2C MASTER SDA & SCL pins (as SM_BUS) +\ ----------------------------\ + BIC.B #SM_BUS,&I2CSM_REN \ remove internal pull up resistors because the next instruction which change them to pull down resistors + BIC.B #SM_BUS,&I2CSM_OUT \ preset SDA + SCL output LOW +\ ----------------------------\ +\ vvvvvvvvv OPTION vvvvvvvvvvv\ + BIS.B #LED1,&LED1_DIR \ set red led (I2C TX) pin as output + BIS.B #LED2,&LED2_DIR \ set green led (I2C RX) pin as output +\ ^^^^^^^^^ OPTION ^^^^^^^^^^^\ +\ ----------------------------\ +\ run previous INIT_HARD_APP \ +\ ----------------------------\ + CALL &{UARTI2CS} \ execute previous INIT_HARD_APP to init TERM_UC, activates I/O. +\ ----------------------------\ TOS = SYSRSTIV = $00|$02|$04|$0E|$xx = POWER_ON|RST|SVSH_threshold|SYS_failures +\ define new SYSRSTIV select \ +\ ----------------------------\ + CMP #$0E,TOS \ SVSHIFG SVSH event ? + 0<> IF \ if not + CMP #$0A,TOS \ SYSRSTIV >= violation memory protected areas ? + U>= ?GOTO BW1 \ if yes goto REMOVE_U2I, RET to WARM+4. + THEN \ else TOS = SYSRSTIV = {$02,$06,$0E} as: {PWR_ON,RST,SVSH_Threshold} + BIS.B #BIT6,&P1IFG \ to force wake up from SLEEP to execute 500MS_INT. +\ ----------------------------\ + MOV #ABORT,PC \ skip WARM message, goto ABORT --> ACCEPT --> SLEEP. + ENDCODE \ +\ ----------------------------\ +\ +\ +\ ============================================================================== +\ Driver UART to I2C to do a bridge USB to I2C_FastForth devices +\ ============================================================================== +\ \ I2C address mini = 10h, maxi = 0EEh (I2C-bus specification and user manual V6) -\ type on TERMINAL "16 UARTI2CS" to link teraterm TERMINAL with FastForth I2C_Slave at address $10 -\ you can also link with last known I2C_Slave address : "I2CS_ADR @ UARTI2CS" -\ -: UARTI2CS \ I2C_Slave_Address_%0 -- -CR I2CS_ADR ! \ -- save I2C_Slave_Address_%0 -HI2LO -CMP #RET_ADR,&{UARTI2CS}+8 \ -0= IF \ save parameters only if MARKER_DOES is not initialized - MOV #STOP_U2I,&{UARTI2CS}+8 \ MARKER_DOES of {UARTI2CS} will do CALL &{UARTI2CS}+8 = CALL #STOP_U2I - MOV &WARM+2,&{UARTI2CS}+10 \ save previous INI_APP from WARM PFA to {UARTI2CS}+10 - MOV &TERM_VEC,&{UARTI2CS}+12 \ save previous TERM_VEC value to {UARTI2CS}+12, see target.pat - MOV &TB0_X_VEC,&{UARTI2CS}+14 \ save previous TB0_X_VEC value to {UARTI2CS}+14 - \ MOV &TA0_X_VEC,&{UARTI2CS}+14 \ save previous TA0_X_VEC value to {UARTI2CS}+14 - MOV #0,&{UARTI2CS}+16 \ reset Half_Duplex variable (set ECHO ON) - MOV #INI_U2I,&WARM+2 \ replace INI_APP by new INI_U2I - MOV #U2I_TERM_INT,&TERM_VEC \ set TERM_VEC with U2I_TERM_INT - MOV #HALF_S_INT,&TB0_X_VEC \ set TB0_X_VEC with HALF_S_INT - \ MOV #HALF_S_INT,&TA0_X_VEC \ set TA0_X_VEC with HALF_S_INT -THEN -MOV #WARM,PC \ execute INI_U2I then goto BW3; abort with Alt-B or SW2+RST. -ENDCODE +\ type on TERMINAL "$12 UARTI2CS" to link teraterm TERMINAL with FastForth I2C_Slave target at address $12 + +\ UARTI2CS starts the USB to I2C bridge, to quit: TERATERM(Alt-B) or USB_to_I2C_bridge(SW2) +\ --------------------------------\ + : UARTI2CS \ I2C_Addr&b0 -- +\ --------------------------------\ init UARTI2CS environment. + 'CR' EMIT 'LF' EMIT \ + HI2LO + MOV @RSP+,IP \ + BEGIN + BIT #1,&TERM_STATW \ uart busy ? + 0= UNTIL \ wait end of 'LF' TX + CMP #RET_ADR,&{UARTI2CS}-2 \ + 0= IF + MOV #REMOVE_U2I,&{UARTI2CS}-2 \ MARKER_DOES of {UARTI2CS} will CALL &{UARTI2CS}-2 = CALL #REMOVE_U2I + MOV &HARD_APP,&{UARTI2CS} \ save previous HARD_APP to {UARTI2CS} + MOV &SLEEP_APP,&{UARTI2CS}+2 \ save previous SLEEP_APP to {UARTI2CS}+2 + MOV &TERM_VEC,&{UARTI2CS}+4 \ save previous TERM_VEC value to {UARTI2CS}+4, see target.pat + MOV &P1_VEC,&{UARTI2CS}+6 \ save previous P1_VEC value to {UARTI2CS}+6 + MOV TOS,&{UARTI2CS}+8 \ -- I2C_Addr&0 save I2C address, set ECHO +\ MOV.B #0,&{UARTI2CS}+9 \ set ECHO ON + THEN + MOV #0,TOS \ -- 0 to enter in INIT_U2I with 0 SYS + MOV #INIT_U2I,&HARD_APP \ replace HARD_APP by new INIT_U2I + MOV #SLEEP_U2I,&SLEEP_APP \ replace HARD_APP by new INIT_U2I + MOV #U2I_TERM_INT,&TERM_VEC \ set TERM_VEC with U2I_TERM_INT + MOV #500MS_INT,&P1_VEC \ set P1_VEC as 500MS_INT + MOV #INIT_U2I,PC \ load INIT_U2I + ENDCODE \ +\ --------------------------------\ + + RST_SET ECHO -RST_HERE ECHO -18 UARTI2CS ; TERATERM(Alt-B) or I2C_Master(SW2+RST) to quit + $12 UARTI2CS ; TERATERM(Alt-B) or USB_to_I2C_bridge(SW2) to quit diff --git a/MSP430-FORTH/UTILITY.f b/MSP430-FORTH/UTILITY.f index b5cd556..3da33ee 100644 --- a/MSP430-FORTH/UTILITY.f +++ b/MSP430-FORTH/UTILITY.f @@ -38,101 +38,99 @@ \ ASSEMBLER conditionnal usage with IF UNTIL WHILE S< S>= U< U>= 0= 0<> 0>= \ ASSEMBLER conditionnal usage with ?JMP ?GOTO S< S>= U< U>= 0= 0<> 0< -; ------------------------------------------------------------------------------ +; -------------------------------- ; UTILITY.f -; ------------------------------------------------------------------------------ +; -------------------------------- \ first, we test for downloading driver only if UART TERMINAL target -CODE ABORT_UTILITY -SUB #2,PSP -MOV TOS,0(PSP) -MOV &VERSION,TOS -SUB #308,TOS \ FastForth V3.8 -COLON -'CR' EMIT \ return to column 1 without 'LF' -ABORT" FastForth V3.8 please!" -PWR_STATE \ remove ABORT_UTILITY definition before resuming -; + CODE ABORT_UTILITY + SUB #2,PSP + MOV TOS,0(PSP) + MOV &VERSION,TOS + SUB #309,TOS \ FastForth V3.9 + COLON + 'CR' EMIT \ return to column 1 without 'LF' + ABORT" FastForth V3.9 please!" + RST_RET \ remove ABORT_UTILITY definition before resuming + ; -ABORT_UTILITY + ABORT_UTILITY -PWR_STATE + MARKER {UTILITY} -[DEFINED] {TOOLS} [IF] {TOOLS} [THEN] - -[UNDEFINED] {TOOLS} [IF] - -MARKER {TOOLS} - -[UNDEFINED] EXIT [IF] \ https://forth-standard.org/standard/core/EXIT \ EXIT -- exit a colon definition; CALL #EXIT performs ASMtoFORTH (10 cycles) \ JMP #EXIT performs EXIT -CODE EXIT -MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack -MOV @IP+,PC \ 4 = NEXT - \ 6 (ITC-2) -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] + [UNDEFINED] EXIT + [IF] + CODE EXIT + MOV @RSP+,IP \ 2 pop previous IP (or next PC) from return stack + MOV @IP+,PC \ 4 = NEXT + \ 6 (ITC-2) + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SWAP \ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] SWAP + [IF] + CODE SWAP + MOV @PSP,W \ 2 + MOV TOS,0(PSP) \ 3 + MOV W,TOS \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] \ https://forth-standard.org/standard/core/Uless \ U< u1 u2 -- flag test u1<u2, unsigned -[UNDEFINED] U< [IF] -CODE U< -SUB @PSP+,TOS \ 2 u2-u1 -0<> IF - MOV #-1,TOS \ 1 - U< IF \ 2 flag - AND #0,TOS \ 1 flag Z = 1 + [UNDEFINED] U< + [IF] + CODE U< + SUB @PSP+,TOS \ 2 u2-u1 + 0<> IF + MOV #-1,TOS \ 1 + U< IF \ 2 flag + AND #0,TOS \ 1 flag Z = 1 + THEN THEN -THEN -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] IF [IF] \ define IF and THEN \ https://forth-standard.org/standard/core/IF \ IF -- IFadr initialize conditional forward branch -CODE IF \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -MOV &DP,TOS \ -- HERE -ADD #4,&DP \ compile one word, reserve one word -MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN -ADD #2,TOS \ -- HERE+2=IFadr -MOV @IP+,PC -ENDCODE IMMEDIATE + [UNDEFINED] IF + [IF] \ define IF and THEN + CODE IF \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + MOV &DP,TOS \ -- HERE + ADD #4,&DP \ compile one word, reserve one word + MOV #QFBRAN,0(TOS) \ -- HERE compile QFBRAN + ADD #2,TOS \ -- HERE+2=IFadr + MOV @IP+,PC + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/THEN \ THEN IFadr -- resolve forward branch -CODE THEN \ immediate -MOV &DP,0(TOS) \ -- IFadr -MOV @PSP+,TOS \ -- -MOV @IP+,PC -ENDCODE IMMEDIATE -[THEN] - -[UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + CODE THEN \ immediate + MOV &DP,0(TOS) \ -- IFadr + MOV @PSP+,TOS \ -- + MOV @IP+,PC + ENDCODE IMMEDIATE + [THEN] + \ https://forth-standard.org/standard/core/BEGIN \ BEGIN -- BEGINadr initialize backward branch -CODE BEGIN + [UNDEFINED] BEGIN [IF] \ define BEGIN UNTIL AGAIN WHILE REPEAT + CODE BEGIN MOV #HEREXEC,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/UNTIL \ UNTIL BEGINadr -- resolve conditional backward branch -CODE UNTIL + CODE UNTIL \ immediate MOV #QFBRAN,X BW1 ADD #4,&DP \ compile two words MOV &DP,W \ W = HERE @@ -140,308 +138,362 @@ BW1 ADD #4,&DP \ compile two words MOV TOS,-2(W) \ compile bakcward adr at HERE+2 MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/AGAIN \ AGAIN BEGINadr -- resolve uncondionnal backward branch -CODE AGAIN -MOV #BRAN,X -GOTO BW1 -ENDCODE IMMEDIATE + CODE AGAIN \ immediate + MOV #BRAN,X + GOTO BW1 + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/WHILE \ WHILE BEGINadr -- WHILEadr BEGINadr -: WHILE -POSTPONE IF SWAP -; IMMEDIATE + : WHILE \ immediate + POSTPONE IF SWAP + ; IMMEDIATE \ https://forth-standard.org/standard/core/REPEAT \ REPEAT WHILEadr BEGINadr -- resolve WHILE loop -: REPEAT -POSTPONE AGAIN POSTPONE THEN -; IMMEDIATE -[THEN] + : REPEAT + POSTPONE AGAIN POSTPONE THEN + ; IMMEDIATE + [THEN] -[UNDEFINED] DO [IF] \ define DO LOOP +LOOP \ https://forth-standard.org/standard/core/DO \ DO -- DOadr L: -- 0 -CODE DO \ immediate -SUB #2,PSP \ -MOV TOS,0(PSP) \ -ADD #2,&DP \ make room to compile xdo -MOV &DP,TOS \ -- HERE+2 -MOV #XDO,-2(TOS) \ compile xdo -ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 -MOV &LEAVEPTR,W \ -MOV #0,0(W) \ -- HERE+2 L-- 0 -MOV @IP+,PC -ENDCODE IMMEDIATE - -\ https://forth-standard.org/standard/core/LOOP -\ LOOP DOadr -- L-- an an-1 .. a1 0 -CODE LOOP \ immediate + [UNDEFINED] DO + [IF] \ define DO LOOP +LOOP + HDNCODE XDO \ DO run time + MOV #$8000,X \ 2 compute 8000h-limit = "fudge factor" + SUB @PSP+,X \ 2 + MOV TOS,Y \ 1 loop ctr = index+fudge + ADD X,Y \ 1 Y = INDEX + PUSHM #2,X \ 4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + + CODE DO \ immediate + SUB #2,PSP \ + MOV TOS,0(PSP) \ + ADD #2,&DP \ make room to compile xdo + MOV &DP,TOS \ -- HERE+2 + MOV #XDO,-2(TOS) \ compile xdo + ADD #2,&LEAVEPTR \ -- HERE+2 LEAVEPTR+2 + MOV &LEAVEPTR,W \ + MOV #0,0(W) \ -- HERE+2 L-- 0 + MOV @IP+,PC + ENDCODE IMMEDIATE + + HDNCODE XLOOP \ LOOP run time + ADD #1,0(RSP) \ 4 increment INDEX +BW1 BIT #$100,SR \ 2 is overflow bit set? + 0= IF \ branch if no overflow + MOV @IP,IP + MOV @IP+,PC + THEN + ADD #4,RSP \ 1 empties RSP + ADD #2,IP \ 1 overflow = loop done, skip branch ofs + MOV @IP+,PC \ 4 14~ taken or not taken xloop/loop + ENDCODE \ + + CODE LOOP MOV #XLOOP,X -BW1 ADD #4,&DP \ make room to compile two words +BW2 ADD #4,&DP \ make room to compile two words MOV &DP,W MOV X,-4(W) \ xloop --> HERE MOV TOS,-2(W) \ DOadr --> HERE+2 -BEGIN \ resolve all "leave" adr - MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR \ -- - MOV @TOS,TOS \ -- first LeaveStack value - CMP #0,TOS \ -- = value left by DO ? -0<> WHILE - MOV W,0(TOS) \ move adr after loop as UNLOOP adr -REPEAT + BEGIN \ resolve all "leave" adr + MOV &LEAVEPTR,TOS \ -- Adr of top LeaveStack cell + SUB #2,&LEAVEPTR \ -- + MOV @TOS,TOS \ -- first LeaveStack value + CMP #0,TOS \ -- = value left by DO ? + 0<> WHILE + MOV W,0(TOS) \ move adr after loop as UNLOOP adr + REPEAT MOV @PSP+,TOS MOV @IP+,PC -ENDCODE IMMEDIATE + ENDCODE IMMEDIATE \ https://forth-standard.org/standard/core/PlusLOOP \ +LOOP adrs -- L-- an an-1 .. a1 0 -CODE +LOOP -MOV #XPLOOP,X -GOTO BW1 \ goto BW1 LOOP -ENDCODE IMMEDIATE -[THEN] + HDNCODE XPLOO \ +LOOP run time + ADD TOS,0(RSP) \ 4 increment INDEX by TOS value + MOV @PSP+,TOS \ 2 get new TOS, doesn't change flags + GOTO BW1 \ 2 + ENDCODE \ + + CODE +LOOP + MOV #XPLOO,X + GOTO BW2 + ENDCODE IMMEDIATE + [THEN] -[UNDEFINED] I [IF] \ https://forth-standard.org/standard/core/I \ I -- n R: sys1 sys2 -- sys1 sys2 \ get the innermost loop index -CODE I -SUB #2,PSP \ 1 make room in TOS -MOV TOS,0(PSP) \ 3 -MOV @RSP,TOS \ 2 index = loopctr - fudge -SUB 2(RSP),TOS \ 3 -MOV @IP+,PC \ 4 13~ -ENDCODE -[THEN] - -[UNDEFINED] DUP [IF] \ define DUP and ?DUP + [UNDEFINED] I + [IF] + CODE I + SUB #2,PSP \ 1 make room in TOS + MOV TOS,0(PSP) \ 3 + MOV @RSP,TOS \ 2 index = loopctr - fudge + SUB 2(RSP),TOS \ 3 + MOV @IP+,PC \ 4 13~ + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/DUP \ DUP x -- x x duplicate top of stack -CODE DUP + [UNDEFINED] DUP + [IF] \ define DUP and ?DUP + CODE DUP BW1 SUB #2,PSP \ 2 push old TOS.. MOV TOS,0(PSP) \ 3 ..onto stack MOV @IP+,PC \ 4 -ENDCODE + ENDCODE \ https://forth-standard.org/standard/core/qDUP \ ?DUP x -- 0 | x x DUP if nonzero -CODE ?DUP -CMP #0,TOS \ 2 test for TOS nonzero -0<> ?GOTO BW1 \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] SWAP [IF] -\ https://forth-standard.org/standard/core/SWAP -\ SWAP x1 x2 -- x2 x1 swap top two items -CODE SWAP -MOV @PSP,W \ 2 -MOV TOS,0(PSP) \ 3 -MOV W,TOS \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - + CODE ?DUP + CMP #0,TOS \ 2 test for TOS nonzero + 0<> ?GOTO BW1 \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] DROP [IF] \ https://forth-standard.org/standard/core/DROP \ DROP x -- drop top of stack -CODE DROP -MOV @PSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] + [UNDEFINED] DROP + [IF] + CODE DROP + MOV @PSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] -[UNDEFINED] >R [IF] \ https://forth-standard.org/standard/core/toR \ >R x -- R: -- x push to return stack -CODE >R -PUSH TOS -MOV @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] R> [IF] + [UNDEFINED] >R + [IF] + CODE >R + PUSH TOS + MOV @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/Rfrom \ R> -- x R: x -- pop from return stack ; CALL #RFROM performs DOVAR -CODE R> -SUB #2,PSP \ 1 -MOV TOS,0(PSP) \ 3 -MOV @RSP+,TOS \ 2 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] SPACE [IF] + [UNDEFINED] R> + [IF] + CODE R> + SUB #2,PSP \ 1 + MOV TOS,0(PSP) \ 3 + MOV @RSP+,TOS \ 2 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/SPACE \ SPACE -- output a space -: SPACE -$20 EMIT ; -[THEN] + [UNDEFINED] SPACE + [IF] + : SPACE + $20 EMIT ; + [THEN] -[UNDEFINED] SPACES [IF] \ https://forth-standard.org/standard/core/SPACES \ SPACES n -- output n spaces -CODE SPACES -CMP #0,TOS -0<> IF - PUSH IP - BEGIN - LO2HI - $20 EMIT - HI2LO - SUB #2,IP - SUB #1,TOS - 0= UNTIL - MOV @RSP+,IP -THEN -MOV @PSP+,TOS \ -- drop n -NEXT -ENDCODE -[THEN] + [UNDEFINED] SPACES + [IF] + CODE SPACES + CMP #0,TOS + 0<> IF + PUSH IP + BEGIN + LO2HI + $20 EMIT + HI2LO + SUB #2,IP + SUB #1,TOS + 0= UNTIL + MOV @RSP+,IP + THEN + MOV @PSP+,TOS \ -- drop n + NEXT + ENDCODE + [THEN] -[UNDEFINED] 2DUP [IF] \ \ https://forth-standard.org/standard/core/TwoDUP \ 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells -CODE 2DUP -MOV TOS,-2(PSP) \ 3 -MOV @PSP,-4(PSP) \ 4 -SUB #4,PSP \ 1 -MOV @IP+,PC \ 4 -ENDCODE -[THEN] - -[UNDEFINED] 1+ [IF] + [UNDEFINED] 2DUP + [IF] \ + CODE 2DUP + MOV TOS,-2(PSP) \ 3 + MOV @PSP,-4(PSP) \ 4 + SUB #4,PSP \ 1 + MOV @IP+,PC \ 4 + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/OnePlus \ 1+ n1/u1 -- n2/u2 add 1 to TOS -CODE 1+ -ADD #1,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] 1+ + [IF] + CODE 1+ + ADD #1,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] + [IF] \ https://forth-standard.org/standard/core/Plus \ + n1/u1 n2/u2 -- n3/u3 add n1+n2 -CODE + -ADD @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] + + [IF] + CODE + + ADD @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] - [IF] \ https://forth-standard.org/standard/core/Minus \ - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 -CODE - -SUB @PSP+,TOS \ 2 -- n2-n1 -XOR #-1,TOS \ 1 -ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] C@ [IF] + [UNDEFINED] - + [IF] + CODE - + SUB @PSP+,TOS \ 2 -- n2-n1 + XOR #-1,TOS \ 1 + ADD #1,TOS \ 1 -- n3 = -(n2-n1) = n1-n2 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/CFetch \ C@ c-addr -- char fetch char from memory -CODE C@ -MOV.B @TOS,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] C@ + [IF] + CODE C@ + MOV.B @TOS,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] AND [IF] \ https://forth-standard.org/standard/core/AND \ C AND x1 x2 -- x3 logical AND -CODE AND -AND @PSP+,TOS -MOV @IP+,PC -ENDCODE -[THEN] + [UNDEFINED] AND + [IF] + CODE AND + AND @PSP+,TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] ROT [IF] \ https://forth-standard.org/standard/core/ROT \ ROT x1 x2 x3 -- x2 x3 x1 -CODE ROT -MOV @PSP,W \ 2 fetch x2 -MOV TOS,0(PSP) \ 3 store x3 -MOV 2(PSP),TOS \ 3 fetch x1 -MOV W,2(PSP) \ 3 store x2 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MAX [IF] \ define MAX and MIN - CODE MAX \ n1 n2 -- n3 signed maximum - CMP @PSP,TOS \ n2-n1 - S< ?GOTO FW1 \ n2<n1 -BW1 ADD #2,PSP - MOV @IP+,PC + [UNDEFINED] ROT + [IF] + CODE ROT + MOV @PSP,W \ 2 fetch x2 + MOV TOS,0(PSP) \ 3 store x3 + MOV 2(PSP),TOS \ 3 fetch x1 + MOV W,2(PSP) \ 3 store x2 + MOV @IP+,PC + ENDCODE + [THEN] + + [UNDEFINED] MAX + [IF] \ define MAX and MIN + CODE MAX \ n1 n2 -- n3 signed maximum + CMP @PSP,TOS \ n2-n1 + S< ?GOTO FW1 \ n2<n1 +BW1 ADD #2,PSP + MOV @IP+,PC ENDCODE - CODE MIN \ n1 n2 -- n3 signed minimum - CMP @PSP,TOS \ n2-n1 - S< ?GOTO BW1 \ n2<n1 -FW1 MOV @PSP+,TOS - MOV @IP+,PC + CODE MIN \ n1 n2 -- n3 signed minimum + CMP @PSP,TOS \ n2-n1 + S< ?GOTO BW1 \ n2<n1 +FW1 MOV @PSP+,TOS + MOV @IP+,PC ENDCODE -[THEN] + [THEN] -[UNDEFINED] OVER [IF] \ https://forth-standard.org/standard/core/OVER \ OVER x1 x2 -- x1 x2 x1 -CODE OVER -MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 -MOV @PSP,TOS \ 2 -- x1 (x2) x1 -SUB #2,PSP \ 1 -- x1 x2 x1 -MOV @IP+,PC -ENDCODE -[THEN] - -[UNDEFINED] MOVE [IF] + [UNDEFINED] OVER + [IF] + CODE OVER + MOV TOS,-2(PSP) \ 3 -- x1 (x2) x2 + MOV @PSP,TOS \ 2 -- x1 (x2) x1 + SUB #2,PSP \ 1 -- x1 x2 x1 + MOV @IP+,PC + ENDCODE + [THEN] + \ https://forth-standard.org/standard/core/MOVE \ MOVE addr1 addr2 u -- smart move \ VERSION FOR 1 ADDRESS UNIT = 1 CHAR -CODE MOVE -MOV TOS,W \ W = cnt -MOV @PSP+,Y \ Y = addr2 = dst -MOV @PSP+,X \ X = addr1 = src -MOV @PSP+,TOS \ pop new TOS -CMP #0,W \ count = 0 ? -0<> IF \ if 0, already done ! - CMP X,Y \ Y-X \ dst - src - 0= ?GOTO FW1 \ already done ! - U< IF \ U< if src > dst - BEGIN \ copy W bytes - MOV.B @X+,0(Y) - ADD #1,Y - SUB #1,W - 0= UNTIL - MOV @IP+,PC - ELSE \ U>= if dst > src - ADD W,Y \ copy W bytes beginning with the end - ADD W,X - BEGIN - SUB #1,X - SUB #1,Y - MOV.B @X,0(Y) - SUB #1,W - 0= UNTIL + [UNDEFINED] MOVE + [IF] + CODE MOVE + MOV TOS,W \ W = cnt + MOV @PSP+,Y \ Y = addr2 = dst + MOV @PSP+,X \ X = addr1 = src + MOV @PSP+,TOS \ pop new TOS + CMP #0,W \ count = 0 ? + 0<> IF \ if 0, already done ! + CMP X,Y \ Y-X \ dst - src + 0= ?GOTO FW1 \ already done ! + U< IF \ U< if src > dst + BEGIN \ copy W bytes + MOV.B @X+,0(Y) + ADD #1,Y + SUB #1,W + 0= UNTIL + MOV @IP+,PC + ELSE \ U>= if dst > src + ADD W,Y \ copy W bytes beginning with the end + ADD W,X + BEGIN + SUB #1,X + SUB #1,Y + MOV.B @X,0(Y) + SUB #1,W + 0= UNTIL + THEN THEN -THEN FW1 MOV @IP+,PC -ENDCODE -[THEN] + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CONSTANT +\ CONSTANT <name> n -- define a Forth CONSTANT + [UNDEFINED] CONSTANT + [IF] + : CONSTANT + CREATE + HI2LO + MOV TOS,-2(W) \ PFA = n + MOV @PSP+,TOS + MOV @RSP+,IP + MOV @IP+,PC + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/BASE +\ BASE -- a-addr holds conversion radix + [UNDEFINED] BASE + [IF] + BASEADR CONSTANT BASE + [THEN] -[UNDEFINED] .S [IF] \ \ https://forth-standard.org/standard/tools/DotS -\ .S TOS -- TOS display <depth> of param Stack and stack contents in hedadecimal if not empty -CODE .S +\ .S TOS -- TOS display <depth> of param Stack and stack contents in hexadecimal if not empty + [UNDEFINED] .S + [IF] \ + CODE .S MOV TOS,-2(PSP) \ -- TOS ( TOS x x ) MOV PSP,TOS \ -- PSP ( TOS x x ) SUB #2,TOS \ -- PSP ( TOS x x ) to take count that TOS is first cell @@ -449,115 +501,144 @@ CODE .S MOV #PSTACK,TOS \ -- P0 ( TOS x PSP ) SUB #2,TOS \ -- P0 ( TOS x PSP ) to take count that TOS is first cell BW1 MOV TOS,-4(PSP) \ -- S0 ( TOS S0 PSP ) | -- TOS ( TOS R0 RSP ) - SUB #6,PSP \ -- TOS S0 PSP S0 | -- TOS R0 RSP R0 - SUB @PSP,TOS \ -- TOS S0 PSP S0-SP | -- TOS R0 RSP R0-RSP - RRA TOS \ -- TOS S0 PSP #cells | -- TOS R0 RSP #cells -COLON + SUB #6,PSP \ -- TOS S0 PSP S0 | -- TOS R0 RSP R0 + SUB @PSP,TOS \ -- TOS S0 PSP S0-SP | -- TOS R0 RSP R0-RSP + RRA TOS \ -- TOS S0 PSP #cells | -- TOS R0 RSP #cells + COLON $3C EMIT \ char '<' . \ display #cells $08 EMIT \ backspace $3E EMIT SPACE \ char '>' SPACE - 2DUP 1+ \ - U< IF + 2DUP 1+ \ + U< IF DROP DROP EXIT THEN \ display content of stack in hexadecimal - BASEADR @ >R - $10 BASEADR ! - DO + BASE @ >R \ base_address @ >R + $10 BASE ! + DO + '$' EMIT I @ U. 2 +LOOP - R> BASEADR ! -; -[THEN] + R> BASE ! + ; + [THEN] -[UNDEFINED] .RS [IF] \ \ .RS TOS -- TOS display <depth> of Return Stack and stack contents if not empty -CODE .RS - MOV TOS,-2(PSP) \ -- TOS ( TOS x x ) + [UNDEFINED] .RS + [IF] \ + CODE .RS + MOV TOS,-2(PSP) \ -- TOS ( TOS x x ) MOV RSP,-6(PSP) \ -- TOS ( TOS x RSP ) MOV #RSTACK,TOS \ -- R0 ( TOS x RSP ) GOTO BW1 -ENDCODE -[THEN] + ENDCODE + [THEN] -[UNDEFINED] ? [IF] \ \ https://forth-standard.org/standard/tools/q \ ? adr -- display the content of adr -CODE ? + [UNDEFINED] ? + [IF] \ + CODE ? MOV @TOS,TOS MOV #U.,PC \ goto U. -ENDCODE -[THEN] + ENDCODE + [THEN] + +\ https://forth-standard.org/standard/core/CR +\ CR -- send CR+LF to the output device + [UNDEFINED] CR + [IF] + +\ DEFER CR \ DEFERed definition, by default executes that of :NONAME + CODE CR \ create a DEFER definition of CR + MOV #NEXT_ADR,PC + ENDCODE + + :NONAME + 'CR' EMIT 'LF' EMIT + ; IS CR + [THEN] + +\ https://forth-standard.org/standard/core/TwoDiv +\ 2/ x1 -- x2 arithmetic right shift + [UNDEFINED] 2/ + [IF] + CODE 2/ + RRA TOS + MOV @IP+,PC + ENDCODE + [THEN] -[UNDEFINED] WORDS [IF] \ https://forth-standard.org/standard/tools/WORDS \ list all words of vocabulary first in CONTEXT. -: WORDS \ -- -CR -CONTEXT @ PAD_ORG \ -- VOC_BODY PAD_ORG MOVE all threads of VOC_BODY in PAD_ORG -THREADS @ DUP + \ -- VOC_BODY PAD_ORG THREAD*2 -MOVE \ -- vocabumary entries are copied in PAD_ORG -BEGIN \ -- - 0 DUP \ -- ptr=0 MAX=0 - THREADS @ DUP + 0 \ -- ptr=0 MAX=0 THREADS*2 0 - DO \ -- ptr MAX I = PAD_ptr = thread*2 - DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx - U< IF \ -- ptr MAX if MAX U< NFAx - DROP DROP \ -- drop ptr and MAX - I DUP PAD_ORG + @ \ -- new_ptr new_MAX - THEN \ - 2 +LOOP \ -- ptr MAX - ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD_ORG = 0) -WHILE \ -- ptr MAX replace it by its LFA - DUP \ -- ptr MAX MAX - 2 - @ \ -- ptr MAX [LFA] - ROT \ -- MAX [LFA] ptr - PAD_ORG + \ -- MAX [LFA] thread - ! \ -- MAX [LFA]=new_NFA updates PAD_ORG+ptr - DUP \ -- MAX MAX - COUNT $7F AND \ -- MAX addr count (with suppr. of immediate bit) - TYPE \ -- MAX - C@ $0F AND \ -- count_of_chars - $10 SWAP - SPACES \ -- complete with spaces modulo 16 chars -REPEAT \ -- -DROP \ ptr -- -; \ all threads in PAD_ORG are filled with 0 -[THEN] - -[UNDEFINED] U.R [IF] -: U.R \ u n -- display u unsigned in n width (n >= 2) ->R <# 0 # #S #> -R> OVER - 0 MAX SPACES TYPE -; -[THEN] - -[UNDEFINED] DUMP [IF] \ + [UNDEFINED] WORDS + [IF] + : WORDS \ -- + CR + CONTEXT @ PAD_ORG \ -- VOC_BODY PAD_ORG MOVE all threads of VOC_BODY in PAD_ORG + THREADS @ DUP + \ -- VOC_BODY PAD_ORG THREAD*2 + MOVE \ -- vocabumary entries are copied in PAD_ORG + BEGIN \ -- + 0 DUP \ -- ptr=0 MAX=0 + THREADS @ DUP + 0 \ -- ptr=0 MAX=0 THREADS*2 0 + DO \ -- ptr MAX I = PAD_ptr = thread*2 + DUP I PAD_ORG + @ \ -- ptr MAX MAX NFAx + U< IF \ -- ptr MAX if MAX U< NFAx + DROP DROP \ -- drop ptr and MAX + I DUP + PAD_ORG + @ \ -- new_ptr new_MAX + THEN \ + 2 +LOOP \ -- ptr MAX + ?DUP \ -- ptr MAX MAX | -- ptr 0 (all threads in PAD_ORG = 0) + WHILE \ -- ptr MAX replace it by its LFA + DUP \ -- ptr MAX MAX + 2 - @ \ -- ptr MAX [LFA] + ROT \ -- MAX [LFA] ptr + PAD_ORG + \ -- MAX [LFA] thread + ! \ -- MAX MAX=highest_NFA [LFA]=new_NFA updates PAD_ORG+ptr + COUNT 2/ \ -- addr count 2/ to hide Immediate flag + DUP >R TYPE \ -- R-- count + R> $10 SWAP - SPACES \ -- R-- complete with spaces modulo 16 chars + REPEAT \ -- + DROP \ ptr -- + ; \ all threads in PAD_ORG are filled with 0 + [THEN] + + [UNDEFINED] U.R + [IF] + : U.R \ u n -- display u unsigned in n width (n >= 2) + >R <# 0 # #S #> + R> OVER - 0 MAX SPACES TYPE + ; + [THEN] + \ https://forth-standard.org/standard/tools/DUMP -CODE DUMP \ adr n -- dump memory -PUSH IP -PUSH &BASEADR \ save current base -MOV #$10,&BASEADR \ HEX base -ADD @PSP,TOS \ -- ORG END -LO2HI - SWAP 2DUP \ -- END ORG END ORG - U. U. \ -- END ORG display org end - $FFF0 AND \ -- END ORG_modulo_16 - DO CR \ generate line - I 4 U.R SPACE \ generate address - I 8 + I \ display first 8 bytes - DO I C@ 3 U.R LOOP - SPACE - I $10 + I 8 + \ display last 8 bytes - DO I C@ 3 U.R LOOP - SPACE SPACE - I $10 + I \ display 16 chars - DO I C@ $7E MIN $20 MAX EMIT LOOP - $10 +LOOP - R> BASEADR ! \ restore current base -; -[THEN] \ endof [UNDEFINED] DUMP - -RST_HERE - -[THEN] \ endof [UNDEFINED] {TOOLS} -ECHO + [UNDEFINED] DUMP + [IF] + CODE DUMP \ adr n -- dump memory + PUSH IP + PUSH &BASEADR \ save current base + MOV #$10,&BASEADR \ HEX base + ADD @PSP,TOS \ -- ORG END + LO2HI + SWAP \ -- END ORG + $FFF0 AND \ -- END ORG_modulo_16 + DO CR \ generate line + I 4 U.R SPACE \ generate address + I 8 + I \ display first 8 bytes + DO I C@ 3 U.R LOOP + SPACE + I $10 + I 8 + \ display last 8 bytes + DO I C@ 3 U.R LOOP + SPACE SPACE + I $10 + I \ display 16 chars + DO I C@ $7E MIN $20 MAX EMIT LOOP + $10 +LOOP + R> BASE ! \ restore current base + ; + [THEN] \ endof [UNDEFINED] DUMP + + RST_SET + + [THEN] ECHO ; endof [UNDEFINED] {TOOLS} + diff --git a/README.md b/README.md index 3fcf3c4..2d91837 100644 --- a/README.md +++ b/README.md @@ -1,46 +1,67 @@ -# FastForth for all MSP430FRxxxx TI's devices, light, fast, efficient, reliable. +## FastForth for MSP430FRxxxx TI's CPUs, light, fast, reliable. -Tested on TI MSP-EXP430FR(5739,5969,5994,6989,4133,2355,2433) launchpads, at 1, 2, 4, 8, 12, 16 MHz plus 20MHz & 24MHz with MSP430FR(23xx,57xx) devices. +Tested on TI MSP-EXP430FR 5739, +[5969](https://duckduckgo.com/?q=MSP-EXP430FR5969), +[5994](https://duckduckgo.com/?q=MSP-EXP430FR5994), +6989, +4133, +[2476](https://duckduckgo.com/?q=Lp-MSP430FR2476), +[2355](https://duckduckgo.com/?q=MSP-EXP430FR2355), +2433) launchpads, at 1, 2, 4, 8, 12, 16 MHz plus 20 & 24 MHz with MSP430FR(23xx,57xx) devices. -FastForth is a **5kB size** "load interpret compile" operating system for MSP430 devices with FRAM which includes: +FastForth is a "load interpret compile execute" operating system for the CPU's MSP430 Texas Instruments with FRAM: -* FORTH kernel with interpreting decimal, hex, binary numbers (#,$,% prefixes), double numbers and Q15.16 numbers, +* LOAD: choice of the TERMINAL (TERATERM.exe) interface: -* the assembler, **label free, with TI's syntax**, + * UART TERMINAL up to 6MBds @ MCLK=24MHz, with software (XON/XOFF) and/or hardware (RTS) control flow, **transmit delay: 0 ms/char, 0 ms/line** -* easy roundtrip between FORTH and ASSEMBLER in definitions, with only 2 switches: `HI2LO` and `LO2HI`, + * a very well designed **I2C TERMINAL up to 1MHz**, with a behaviour full duplex, ready to communicate with all modules **I2C_FastForth** wired onto bus, + +* INTERPRET: with a 16-entry word-set that speeds up the FORTH interpreter by 4, -* conditional compilation, +* COMPILE: in addition to the FORTH engine, the **MSP430 assembler (label free) with syntax TI's**, -* efficient memory management which can be modulated according to these 3 levels: power on, reset, deep reset, +and as result **"load interpret compile" a source file is faster and easier than loading its binary equivalent** via the TI's eZFET interface: +For example, with MCLK=24MHz, THREADS=16, UART=6MBds 8n1, a [PL2303GC](https://duckduckgo.com/?q=DSD+TECH+SH-U06A+PL2303GC) and Teraterm.exe as TERMINAL, the download/interpret/execute process of the file CORETEST is done at an effective rate close to 43KB/s (430kBds). +with a bridge UARTtoI2C and an I2C_Slave target MCLK=24MHz, THREADS=16, the effective rate is the same ( I don't understand but it's like this...) -* automatic memory releasing with MARKER tags, +Despite its **size of 5 kb** FastForth includes: -* robust and visual error handling, +* FORTH kernel with interpreting decimal, hex, binary (#,$,% prefixed) numbers, digits separator '_', 'char', double numbers and Q15.16 numbers, -* choice of the TERMINAL (TERATERM.exe) interface: +* the MSP430 16 bits assembler (1,5 kb), - * UART TERMINAL up to 6MBds @ MCLK=24MHz, with software (XON/XOFF) and/or hardware (RTS) control flow, **transmit delay: 0 ms/char, 0 ms/line** +* a good error management which interrupts the downloading at the slightest error, - * **I2C TERMINAL up to 1MHz**, "full duplex" like, allowing to communicate with several **I2C_FastForth** targets, - -* and therefore, **"loading, interpreting, compiling" a source file is faster and easier than loading its binary equivalent**, +* a memory management which can be modulated according to these 3 levels: MARKER, RESET, DEEP_RESET, + +* everything you need to write a real time application made of a mix of FORTH/assembler: + + * the complete set of the FORTH building words, + + * conditional compilation, + + * thanks to [GEMA preprocessor](http://gema.sourceforge.net/new/index.shtml), the compilation of all symbolic addresses without having to declare them in FORTH, -* transmission errors, if any, are automatically rejected by the on-board interpreter, + * easy roundtrip between FORTH and assembler with only two switches 'one word' `HI2LO` and `LO2HI`, -* CPU in sleep mode LPM0:LPM4, awaiting a command from UART:I2C TERMINAL, or any user interrupt event, + * automatic releasing memory with MARKER tags, -* direct access to all SFR and other symbolic addresses by use of [GEMA preprocessor](https://github.com/NeonMan/gema), + * Fully configurable sequences: reset, initialisation and background, -* Fully configurable reset, initialisation and background sequences. + * CPU in sleep mode LPM0|LPM4 in awaiting a command from UART|I2C TERMINAL, and ready to process any interrupts. -For only 3 kbytes in addition, you have the primitives to access the SD\_CARD FAT16 and FAT32: read, write, del, download source files and also copy them from PC to the SD_Card. It works with all SD\_CARD memories from 64MB to 64GB. The cycle to read/write a byte is below 1 us @ 16 MHz. +For only 3 kbytes in addition, we have the primitives to access the SD_CARD FAT16 and FAT32: read, write, del, download source files and also to copy them from PC to the SD_Card. +It works with all SD\_CARD memories from 64MB to 64GB with FAT32 format. +The cycle to read/write a **byte** is below 1us @ 16 MHz. -With all the kernel addons, including extended\_ASM and SD\_Card driver, FastForth size is **10 kB**. +With all the kernel addons, including the 20 bits MSP430\_X assembler and the SD\_Card driver, FastForth size is **10 kB**. + +After downloading CORE_ANS.f file (+2 kb), FastForth passes successfully the CORE ANS94 + COREPLUSTEST tests. However, if all works well with Windows 10, it works less well with Linux due to the lack of a good alternative to TERATERM... -Note: for every update, download all subdirectories to correctly update the project, without missing configurations files. +Note: please, for each update download all subdirectories to correctly update the project. ## how to connect TERMINAL @@ -51,22 +72,28 @@ Note: for every update, download all subdirectories to correctly update the proj ------------------------------------------------------------------------------------------ (modify this first: open the box and weld red wire on 3.3V pad). -### programming with MSP430Flasher/UniFlash and FET interface +### programming with MSP430Flasher/UniFlash and FET interface: - TI Launchpad <--> CP2102/PL2302TA cable <------> USB <-------------> TERATERM.exe - RX <--- TX ) - GND <--> GND > used by FastForth TERMINAL - TX ---> RX ) - RTS ---> CTS (optionnal) RTS pin Px.y is described in your \inc\launchpad.asm) - + J101 connector + | + v TI Launchpad <--> FET interface <-------------> USB <-------------> MSP430Flasher.exe/UniFlash Vcc <--- 3V3 TST/SBWTCK <--> SBWTCK GND <--> GND RST/SBWTDIO <--> SBWTDIO -### programming with BSL_Scripter.exe + TI Launchpad <--> CP2102/PL2302TA cable <------> USB <-------------> TERATERM.exe + RX <--- TX ) + GND <--> GND > used by FastForth TERMINAL + TX ---> RX ) + RTS ---> CTS (optionnal) RTS pin Px.y is described in your \inc\launchpad.asm) + +### programming with BSL_Scripter.exe (don't work with MSP-EXP430FR2355 launchpad) + J101 connector + | + v MSP430FRxxxx <--> CP2102/PL2303TA cable <------> USB <-------->+<--> TERATERM.exe RX <--- TX ) | GND <--> GND > used by FastForth TERMINAL +<--> BSL_Scripter.exe @@ -91,17 +118,16 @@ A set of .bat files in \MSP430-FORTH folder is furnished to do all this automati To see all specifications of FastForth, download \MSP430-FORTH\FF_SPECS.f. -To change the terminal baudrate on the fly, 9600 Bauds up to 6 MBds, download \MSP430-FORTH\CHNGBAUD.f. +To change the UART TERMINAL baudrate on the fly, 9600 Bauds up to 6 MBds, download \MSP430-FORTH\CHNGBAUD.f. Beyond 1 MBds, shorten the PL2303HXD cable, down to 50 cm for 6MBds. XON/XOFF flow control allows 3.75kV galvanic isolation of terminal input with SOIC8 Si8622EC|ISO7021. -With powered SOIC16W ISOW7821, you have 5kV rms isolation for both XON/XOFF TERMINAL and a 3V3 75mA supply. -If you choose I2C_FastForth for your target, you will need of one more to make the USBtoI2C bridge. +If you choose I2C_FastForth for your project, you will need of one more launchpad to make the USBtoI2C bridge. See driver for I2C_FastForth: \MSP430-FORTH\UARTI2CS.f. After downloading of complementary words in \MSP430-FORTH\ANS_COMP.f, FastForth executes CORETEST.4th -in less than a second, and without errors which ensures its compatibility with the FORTH CORE ANS94 standard. +in one second, and without errors which ensures its compatibility with the FORTH CORE ANS94 standard. Notice that FAST FORTH interprets lines up to 84 chars, only SPACE as delimiter, only CR+LF as End Of Line, and BACKSPACE. @@ -112,22 +138,62 @@ Finally, using the SCITE editor as IDE, all is ready to do everything from its " What is new ? ------------- +### V309 + +* = V308 - 344 bytes. + +* removed `INTERPRET`, `CR` and the useless error line displaying. + +* Removed `PWR_HERE` and `PWR_STATE`, replaced `RST_HERE` by `RST_SET` and `RST_STATE` by `RST_RET`. + +* Replaced `WIPE` by `-1 SYS`, `COLD` by `6 SYS` and `WARM` by `0 SYS` or simply `SYS`. + +* replaced `VOCABULARY` with `WORDSET`. `ALSO` is also :-) removed because the executing of a definition created by `WORDSET` adds it into the CONTEXT stack. For example, typing `FORTH` adds it into CONTEXT. Note that as result the use of ONLY is modified: `FORTH ONLY` instead of `ONLY FORTH`. + +* modified QNUMBER QABORT `ABORT` `QUIT` `HI2LO` `PREVIOUS` `WORD` `FIND` `>NUMBER` `TYPE` `#>` `COUNT` `SWAP` `TICK` `POSTPONE` `COLON` `[ELSE]` plus the assembler. + +* The bootstrap ON/OFF is modified: `BOOT` / `NOBOOT` to enable / disable it. + +* the word-set `ASSEMBLER` is renamed `hidden` because it stores not only the ASM instructions definitions but also HDNCODE definitions. + +* when you executes a `MARKER` definition, it starts by removing its previous definition if exists. + +* Some bugs corrected: + * QNUMBER FORWDOES `TYPE` `WORD`, + * `M*/` in \MSP430-FORTH\DOUBLE.f file, + * the assembler handles correctly argument+/-offset. + +* User can choose floored or symmetric division. See \MSP430-FORTH\ANS_CORE.f + +* the words `:NONAME` `IS` `DOES>` `CODENNM` are added to the core and there is still enough room in its 5kb for the VOCABULARY_SET add-on. + DEFER is not included because too easy to replace by a CODE definition, see CR in file CORE_ANS.f. + +* When used with VOCABULARY_SET activated, `RST_SET`/`RST_RET` and definition/use of `MARKER` tags save/restore the full word-set environment: DP, CURRENT, CONTEXT stack, VOCLINK. + +* FF_SPECS.f displays all word-sets, including the `hidden` one. + +* the SD_Card driver is rewritten. Only FAT32 format is supported. I suggest 4kb sized clusters. + The old WRITE" command is duplicated : + ** `WRITE"` to create a new file (or to overwrite it if exists), + ** `APPEND"` to append to a file (or to create it if not exists) + + ### V308 -* 16 bytes removed from (Kernel + Conditional_Compilation + Assembler). +* = V307 - 16 bytes. * Source file copy from TERMINAL to the SD\_Card of any I2C\_FastForth target works fine. -* The bootstrap call is modified: `' BOOT IS WARM` to enable it, `' BOOT [PFA] IS WARM` to remove it. +* ~~The bootstrap call is modified: `' BOOT IS WARM` to enable it, `' BOOT [PFA] IS WARM` to remove it~~. -* ASM definitions are renamed HDNCODE (HiDdeN CODE), ENDASM is replaced by ENDCODE. +* `ASM` definitions are renamed `HDNCODE` (HiDdeN CODE), `ENDASM` is replaced by `ENDCODE`. - HDNCODE definitions are identical to low level CODE ones, but are hidden because defined in the ASSEMBLER word set, and can be used only + `HDNCODE` definitions are identical to low level `CODE` ones, but are hidden because defined in the ~~`ASSEMBLER`~~ `hidden` word set, and must be used only in the scope of another low level CODE definition. See use in \MSP430-FORTH\UARTI2CS.f. * FastForth passes CORETEST + COREPLUSTEST tests. See modified \MSP430-FORTH\CORETEST.4TH -* Double number word D< corrected in \MSP430-FORTH\DOUBLE.f +* Double number word `D<` corrected in \MSP430-FORTH\DOUBLE.f ### V307 @@ -149,57 +215,58 @@ What is new ? `MOV #RXON,&SLEEP+2` to store RXON addr at SLEEP+2 addr. `MOV.B BUFFER+-1(X),TOS` to load the byte at BUFFER-1(X) addr in the register TOS. -* COLD does same than hardware RST. - WIPE does same than hardware SW1+RST (DEEP_RESET). +* ~~`COLD` does same than hardware RST~~. + `6 SYS` does same than hardware RST. + ~~`WIPE` does same than hardware SW1+RST (DEEP_RESET)~~. + `-1 SYS` does same than hardware SW1+RST (DEEP_RESET). * More complicated: -In the FastForth init process, COLD WARM SLEEP are modified and INI_FORTH is added. -They start each with an immediate call to a paired assembly subroutine: - - RST_SYS failures ->+ +<- ABORT_TERM <- ABORT" <-(error)<-+-<-COMPILE/EXECUTE<-INTERPRET<-+ - | | | ^ - | v v | - SW1+RST->+<-RST | +--> INI_FORTH -> ABORT" ->+->QUIT>-+->ACCEPT->+ +->ACCEPT->+ - | | --------- ^ | ^ - v v | v | - WIPE --->+->COLD-->+--> PUC --> INI_FORTH --> WARM -->+ +->SLEEP->+ - ---- --------- ---- ----- +In the FastForth init process, COLD WARM SLEEP are modified and INIT_FORTH is added. +They start each with a call to a paired assembly subroutine: - subroutine: COLD_APP INI_SOFT_APP INI_HARD_APP BACKGND_APP - default CALL# COLD_TERM RET_ADR INIT_TERM RXON - Default action: wait TERMINAL idle do nothing init TERM UCAx enable TERMINAL TX - + unlock I/O's (send RXON + /RTS) + RST_SYS failures --------->+ +<- ABORT_TERM <--------(error)<------------+<--COMPILE/EXECUTE<-INTERPRET<-+ + | | | ^ + RST ------------>+ | v v | + v | +-> INIT_FORTH -> ABORT" ->+-> ABORT->QUIT->+->ACCEPT->+ +->ACCEPT->+ + SW1+RST -------->+ | ========== ^ | ^ + v v | v | + -n SYS --------->+->COLD-->+->PUC->+-> INIT_FORTH --> WARM" ->+ +->SLEEP->+ + ^ ==== ^ ========== ==== ===== + | | + +n SYS (even) -->+ (NOPUC) + | + +n SYS (odd) --------------------->+ + ^ + [0] SYS -------------------------->+ + + CALL... &COLD_APP &SOFT_APP &HARD_APP &SLEEP_APP + ========= ========= ========= ========== + Default subroutine... COLD_TERM RET_ADR INIT_TERM RXON + Default action... wait TERM idle do nothing init TERM UC, unlock I/O enable TERMINAL to TX + + note: -n SYS|SW1+RST reset the default subroutine of these four calls. - On the other hand, MARKER is modified in such a way that MARKER\_DOES executes a CALL to -the content of BODY+4, by default RET_ADR: +the content of USER_BODY-2, by default RET_ADR: - MARKER [CFA] = DODOES - [PFA] = MARKER_DOES - [BODY] = previous DP (Dictionnary Pointer) - [BODY+2] = previous VOCLINK (if word-set addon) - [BODY+4] = RET_ADR - -By replacing [BODY+4] with the address of a new defined subroutine (named for example: STOP_XXX), -MARKER_DOES will execute it to restore all critical pointers saved at BODY+6, BODY+8... - -Thus, with MARKER and the definition of subroutines COLD_XXX, INI_SOFT_XXX, INI_HARD_XXX, BACKGND_XXX -the programmer has full control of his "XXX" real time application using interrupts, -with everything he needs to start it, stop it, and also to properly remove it with -a 'soft' MARKER word, avoiding the use of a WIPE or a SW1+RST of the last chance. - -See examples in /MSP430-FORTH/UARTI2CS.f, /MSP430-FORTH/RTC.f. + MARKER [CFA] = DODOES + [PFA] = MARKER_DOES + [BODY] = previous DP (Dictionnary Pointer) + ... + [USER_PARAM-2] = RET_ADR as REMOVE_APP by default -notes: -* RST and SW1+RST (deep RST) are hardware redirected to COLD via NMI and the USER\_NMI vector. - -* INI\_SOFT\_SD is used as INI\_SOFT\_APP alias by the SD_CARD driver to reinit handles. +By replacing [USER_PARAM-2] with the address of a new defined subroutine (named for example: REMOVE_XXX), +MARKER_DOES will execute it to restore n critical pointers (room made by 2n ALLOT) at USER_PARAM, USER_PARAM+2, ... -* WIPE|SW1+RST initialises this four APP calls plus TERMINAL\_INT Vector. +Thus, with MARKER and the definition of subroutines STOP_XXX, INIT_SOFT_XXX, INIT_HARD_XXX, BACKGND_XXX, +the programmer has full control of his "XXX" real time application using interrupts, +with everything he needs to start, stop and remove it properly, thanks to a 'soft' MARKER definition, +avoiding the (SW1+RST) of the last chance. +See example in /MSP430-FORTH/UARTI2CS.f. ### V306 @@ -263,13 +330,13 @@ notes: A newcomer: FastForth for I2C TERMINAL. With the driver UART2I2CS running on another FastForth target, we have the USB to I2C_Slave bridge we need: one TERMINAL for up to 112 I2C_FastForth targets. - +---------------------------+ - notebook USB to I2C_Slave bridge +-I2C-| others I2C_slave target | - +-----------+ +-------------------------------------------------+ / +--------------------------+ | - | | ¦ PL2303HXD target running UARTI2CS @24MHz¦ +-I2C-| MSP430FR4133 @ 1 MHz | | - | | ¦------------+ +----------------------------¦ / +--------------------------+ |--+ - | | ¦ | 3wires| MSP430FR2355 @ 24MHz ¦/ | MSP430FR5738 @ 24 MHz | | - | TERATERM -o->USB-o->USB2UART->o->UART-o-> FAST FORTH -> UARTI2CS -o-I2C-o-> FAST FORTH with option |--+ + +-------------------------+ + notebook USB to I2C_Slave bridge +-I2C-| others I2C_slave target | + +-----------+ +-------------------------------------------------+ / +-------------------------+ | + | | ¦ PL2303HXD target running UARTI2CS @24MHz¦ +-I2C-| MSP430FR4133 @ 1 MHz | | + | | ¦------------+ +----------------------------¦ / +--------------------------+ |-+ + | | ¦ | 3wires| MSP430FR2355 @ 24MHz ¦/ | MSP430FR5738 @ 24 MHz | | + | TERATERM -o->USB-o->USB2UART->o->UART-o-> FAST FORTH -> UARTI2CS -o-I2C-o-> FAST FORTH with option |-+ | terminal | ¦ | 6MBds | (I2C MASTER) ¦ | TERMINAL_I2C (I2C SLAVE)| | | ¦------------+ +----------------------------¦ +--------------------------+ | | ¦ |< 20cm>| ¦ up to 112 I2C_Slave targets @@ -277,29 +344,28 @@ notes: With the indicated MCLK and UART speed, Coretest.4th is downloaded to (and executed by) I2C_Slave in 800ms. The driver UARTI2CS works without error from 1MHz to 24MHz MCLK and from 115200Bds up to 6MBds UART. - With I2C_Master running at 24 MHz, the I2C bus frequency is about 1MHz, and it works fine even if I2C_slave is running at 1 MHz. + With I2C_Master running at 24 MHz, the I2C bus frequency is about 1MHz, and it works fine + even if I2C_slave is running at 1 MHz. Don't forget to add two 3k3 pullup resistors on SCL and SDA... the Multi Master Mode works but is not tested in multi master environment. "cerise sur le gâteau": when they wait for a TERMINAL input (idle state), both I2C_Master and I2C_Slave(s) are sleeping in LPMx mode and the bus I2C is freed. - LPM4 mode is available for I2C_Slave devices. - - The driver UART2I2CS doesn't use the UCBx I2C_Master hardware, really too bad, but - profitably its software version, much more faster, which consumes just two I/O (better in the range Px0-Px3), - the UCBx remaining available for another I2C_Slave or SPI driver. + The I2C_slave driver handles LPM4 mode. + The UART2I2CS does not use TI's horrible UCBx_I2C_Master driver, but a much faster software driver, + with the UCBx still available for an I2C_Slave or SPI driver. ##### HOW TO DO ? - first you make a I2C cable (GND,SDA,SCL,3V3) between your 2 LaunchPad, with 3,3k pullup resistors on SDA and SCL lines. - see each of two /inc/target.pat files to know SDA ans SCL pins. + first you make the I2C cable (GND,SDA,SCL,3V3) between your 2 LaunchPad, with 3,3k pullup resistors + on SDA and SCL lines. See in forthMSP430FR_TERM_I2C.asm to select SDA and SCL pins. to compile FastForth for I2C TERMINAL from forthMSP430FR.asm file: - 1- uncomment the line "TERMINAL_I2C". - 2- search "I2CSLAVEADR" line and set your <slave address you want>, i.e. 10h. - 3- compile file then prog your I2C_Slave LaunchPad. + - uncomment the line "TERMINAL_I2C". + - search "I2CSLAVEADR" line and set your <slave address you want>, i.e. 10h. + - compile file then prog your I2C_Slave LaunchPad. with the another LaunchPad running FastForth: At the end of UART2I2CS.f file set the <slave address you want>, i.e. $10. @@ -362,7 +428,7 @@ notes: ### PREVIOUS versions Unlocking I/O's is transfered from RESET to WARM. -Thus, by redirecting WARM, you can add I/O's configuration of your application before unlock them. +Thus, by redirecting WARM, you can add I/O's configuration of your application before unlocking. The structure of primary DEFERred words as KEY,EMIT,CR,WARM... is modified, @@ -406,7 +472,7 @@ to build the primary DEFERred low level definition "machin" : you can obviously mix LOW/HIGH levels in CODENNM and :NONAME -All interpretation/compilation errors now execute PWR_STATE, so any incorrect definition +All interpretation/compilation errors now execute ~~`PWR_RET`~~~ `RST_RET`, so any incorrect definition and all its source file will be automatically erased. @@ -484,32 +550,34 @@ In explorer you should obtain this back your driver letter: \prog(.bat) to do what ?... \config\ - \asm.properties configuration for *.inc,*.asm files - \forth.properties configuration for *.f,*.4th files - \fortran.properties configuration for *.pat files - \SendFile.ttl TERATERM macro file to send source file to FASTFORTH - \SendToSD.ttl TERATERM macro file to send source file to embedded SD_CARD - \build(.bat) called by scite to build target.txt program - \BSL_prog(.bat) to flash target with target.txt file with BSL_Scripter - \FET_prog(.bat) to flash target with target.txt file with MSP430Flasher - \CopyTo_SD_Card(.bat) to copy in your MSP430-FORTH - \SendSource(.bat) to send file to FASTFORTH - \Preprocess(.bat) to convert generic .f file to specific .4th file - \CopySourceFileToTarget_SD_Card.bat copy it in any user folder for drag'n drop use - \SendSourceFileToTarget.bat copy it in any user folder for drag'n drop use - \PreprocessSourceFile.bat copy it in any user folder for drag'n drop use - \SelectTarget.bat called to select target, device and deviceID + \asm.properties configuration for *.inc,*.asm files + \forth.properties configuration for *.f,*.4th files + \fortran.properties configuration for *.pat files + \SciTEDirectory.properties copy it to your project root folder + \SciTEUser.properties copy it in your home directory + \SendFile.ttl TERATERM macro file to send source file to FASTFORTH + \SendToSD.ttl TERATERM macro file to send source file to embedded SD_CARD + \build(.bat) called by scite to build target.txt program + \BSL_prog(.bat) to flash target with target.txt file with BSL_Scripter + \FET_prog(.bat) to flash target with target.txt file with MSP430Flasher + \CopyTo_SD_Card(.bat) to copy in your MSP430-FORTH + \SendSource(.bat) to send file to FASTFORTH + \Preprocess(.bat) to convert generic .f file to specific .4th file + \CopySourceFileToTarget_SD_Card.bat copy it in any user folder for drag'n drop use + \SendSourceFileToTarget.bat copy it in any user folder for drag'n drop use + \PreprocessSourceFile.bat copy it in any user folder for drag'n drop use + \SelectTarget.bat called to select target, device and deviceID \inc\ MACRO ASsembler files.inc, files.asm, GEMA preprocessor files.pat - \MSP430FRxxxx.inc device configuration for AS assembler - \MSP430FRxxxx.asm device init code for AS assembler - \MSP_EXP430FRxxxx.asm target configuration for AS assembler + \TargetInit.asm select target configuration file for AS assembler + \MSP_EXP430FRxxxx.asm target minimalist hardware config to compile FastForth + \ThingsInFirst.inc general configuration for AS assembler + \MSP430FRxxxx.inc device declarations + \ThingsInLast.inc general post configuration for AS assembler \FastForthREGtoTI.pat converts FORTH symbolic registers names to TI Rx registers \tiREGtoFastForth.pat converts TI Rx registers to FORTH symbolic registers names \MSP430FRxxxx.pat device configuration for gema preprocessor \MSP_EXP430FRxxxx.pat target configuration for gema preprocessor - \ThingsInFirst.inc general pre configuration for AS assembler - \ThingsInLast.inc general post configuration for AS assembler \prog\ SciTEGlobal.properties, TERATERM.INI + programs.url @@ -532,7 +600,7 @@ In explorer you should obtain this back your driver letter: \FF_SPECS.f shows all specificities of FAST-FORTH compiled on your target \RTC.f set date and time, one example of MARKER use. \RC5toLCD.f multitasking example - \SD_test.f tests for SD_CARD driver + \SD_TEST.f tests for SD_CARD driver \SD_TOOLS.f same as SD_TOOLS.asm, (but erasable) \TESTASM.f some tests for embedded assembler \TESTXASM.f some tests for embedded extended assembler @@ -540,7 +608,7 @@ In explorer you should obtain this back your driver letter: \UTILITY.f same as UTILITY.asm, (but erasable) -Note: all actions (flashing target, download files) can be made by using bat files directly,. +Note: all actions (flashing target, download files) can be made by using bat files directly. The next is to download IDE (WINDOWS): ## First get TI's programs @@ -559,7 +627,7 @@ install in the suggested directory, then copy MSP430Flasher.exe and MSP430.dll t * [sCiTE single file executable](https://www.scintilla.org/SciTEDownload.html) to drive:\prog\, then rename Scxxx.exe to scite.exe -* [Macro AS](http://john.ccac.rwth-aachen.de:8000/ftp/as/precompiled/i386-unknown-win32/aswcurr.zip), unzip in drive:\prog\ +* [Macro AS](http://john.ccac.rwth-aachen.de:8000/ftp/as/precompiled/i386-unknown-win32/aswcurr-142-bld158.zip), unzip in drive:\prog\ * [srecord](https://sourceforge.net/projects/srecord/files/srecord-win32/1.64/), unzip in drive:\prog\ @@ -622,7 +690,7 @@ IT's done ! See forthMSP430FRxxxx.asm to configure TeraTerm * assemble (CTRL+0). A window asks you for 4 parameters: -* set target as first param, i.e. MSP_EXP430FR5969 +* set your target as first param, i.e. MSP_EXP430FR5969 * then execute. the output will be \binaries\MSP_EXP430FR5969.txt @@ -639,17 +707,17 @@ to same pins of the launchpad, on eZ-FET side of the programming connector. ## Connect the FAST FORTH target to a serial terminal -you will need an USBtoUART cable with a PL2303TA or PL2303HXD device that allows both XON/XOFF +you will need an USBtoUART cable with a PL2303TA|PL2303HXD|PL1303GC device that allows both XON/XOFF and hardware control flow : -[PL2303HXD 3.3V](http://www.google.com/search?q=PL2303HXD+3.3V+cable) +[PL2303GC](https://duckduckgo.com/?q=DSD+TECH+SH-U06A+PL2303GC) [PL2303 driver](http://www.prolific.com.tw/US/ShowProduct.aspx?p_id=225&pcid=41) WARNING! always verify VCC PIN = 3.3V before use to supply your target with. or with a CP2102 device and 3.3V/5V that allows XON/XOFF control flow up to 921600 Bds: -[CP2102 3.3V](https://www.google.com/search?q=cp2102+3.3V+6PIN) +[CP2102 3.3V](https://duckduckgo.com/q=cp2102+3.3V+6PIN) [CP2102 driver](https://www.silabs.com/products/development-tools/software/usb-to-uart-bridge-vcp-drivers) WARNING! always verify VCC PIN = 3.3V before use to supply your target with. @@ -671,7 +739,7 @@ correctly ended with CR+LF. If you have MSP-EXP430FR5994, nothing to do. For the choice of a SD card socket be carefull, pin CD (Card Detect) must be present! -google search: "micro SD card 9 pin" +web search: "micro SD card 9 pin" Look for the good wiring in /Launchpad.asm file #### Compile with SD_Card addon @@ -688,7 +756,8 @@ See "SD_TESTS.f", a FORTH program done for example If you remove the SD memory card reader and then reset, all SD\_IO pins are available except SD_CD. Drive letters are always ignored. - LOAD" path\filename.4th". + LOAD" path\filename.4th" relative path, + LOAD" \path\filename.4th" absolute path. The file is interpreted by FORTH in same manner than from the serial terminal. When EOF is reached, the file is automatically closed. @@ -701,30 +770,34 @@ LOAD" may be used as Change Directory command: LOAD" \" Root becomes the current folder. - READ" path\filename.ext". + READ" filename.ext" reads a file in current directory, + READ" \filename.ext" reads a file in root directory. The first sector of this file is loaded in BUFFER. -To read next sectors, use the command READ that loads the next sector in the buffer, -and leaves on the stack a flag that is true when the EOF is reached. +To read next sectors, use the command READ which loads the next sector in the buffer +and leaves on the stack a true flag when the EOF is reached. The file is automatically closed. See tstwords.4th for basic usage. -The variable BufferLen keep the count of bytes to be read (0 to 512). +The variable BufferLen keep the count of bytes to be read (1 to 512). -If you want to anticipate the end, use the CLOSE command. +If you want to anticipate the end, remove the false flag left by the previous READ then use the CLOSE command. WRITE" path\filename.ext". -If the file does not exist, create it, else open it and set the write pointer at the end of the file, +If the file does not exist, create it else open it, and set the write pointer at the end of the file, ready to append chars. +The command WRITE writes the buffer and increments the current sector. + See example of use in \MSP430-FORTH\SD_TEST.f. -To overwrite an existing file: DEL" file" then WRITE" file". +To overwrite an existing file: -Use CLOSE to close the file. + DEL" path\filename.ext" (no error issued), + WRITE" path\filename.ext". +Use CLOSE to close this file. - DEL" path\filename.ext". If the file is not found, do nothing, no error. #### Copy source file to SD_Card @@ -741,103 +814,88 @@ correctly ended with CR+LF. First, remove the USBtoUART bridge then reconnect it. Perhaps it was in suspend state... -If the system is always freezed, press <reset> button on the MSP-EXP430FR5xxx ; FORTH restarts -as it was after the last RST_HERE command. +If the system is always freezed, press `RST` button on the MSP-EXP430FR5xxx ; FORTH restarts +as it was after the last `RST_SET` command. If the system does not restart again, press `SW1+RESET`. -FORTH restarts in the state it is in its object txt file. - -Here is the FastForth memory management, one of its major assets : +FORTH restarts in the state of its object file. - case 1 : when you type `PWR_STATE` the program beyond PWR_HERE marker is lost. +Here is the FastForth memory management, one of its major assets, with both hardware events and software equivalent for COLD and WIPE levels: - case 1.1 : when you type `WARM`, FORTH interpreter is restarted, the program beyond PWR_HERE is lost. - The WARM display starts with "#0". +* RST_RET - case 1.2 : Power ON performs a reset and the program beyond PWR_HERE is lost. - the WARM display starts with the SYSRSTIV value "#2". - - case 1.3 : SVSHIFG SVSH event, same effects, - the WARM display starts with the SYSRSTIV decimal value "#14". + * when you type `RST_RET` the program beyond the last RST_SET is lost. - - case 2 : when you type `RST_STATE` the program beyond RST_HERE marker is lost. + * Running a `MARKER` definition will remove it and the program beyond. In addition the user can link it a routine to remove modified configuration in system: vectors, hardware, IOs... - case 2.1 : <RESET> performs reset and the program beyond RST_HERE is lost, - the WARM display starts with the SYSRSTIV value "#4". +* WARM level : SYS --> WARM display --> SLEEP. + + * when you type `0 SYS`, FORTH interpreter is restarted without program lost, without WARM display. - case 2.2 : when you type `COLD` (software reset), same effects, - the WARM display starts with the SYSRSTIV value "#6". + * when you type `SYS`, FORTH restarts, the program beyond RST_SET is lost, INIT_FORTH and INIT_HARD_APP (INIT_TERM by default) are executed, the WARM display starts by "#1". - case 2.3 : PUC on failure, same effects, - The WARM display starts with the SYSRSTIV decimal value. + * when you type `+n SYS` (n>0, odd), same effects, the WARM display starts by "#+n". + +* COLD level : PUC --> `SYS` --> WARM display --> SLEEP. + * Power ON : the WARM display starts with the SYSRSTIV value "#2". - case 3 : when you type `WIPE` (software Deep Reset) - * all programs donwloaded from the terminal or the SD_Card are lost, - * the default state of COLD_APP, INI_SOFT_APP, INI_HARD_APP and BACKGND_APP are restored, - * all "defered" words are initialised with their default value, - * same thing for interrupts vectors, - * and SIGNATURES area is cleared (FFh). - The WARM display starts with #-1. + * SVSHIFG SVSH event (dropout supply) : the WARM display starts with the SYSRSTIV value: "#14". - case 3.1 : <SW1+RESET> performs hardware deep reset, same effects. - The WARM display starts with #-1. + * hardware `RST` : the WARM display starts with the SYSRSTIV value "#4". - case 3.2 : after compiling new FastForth, same effects obviously! - The WARM display starts with #-3. + * PUC on failure : the WARM display starts with the SYSRSTIV value: #n. + * `+n SYS` (n>0 and even) is the software RESET : the WARM display starts with the SYSRSTIV value "#+n" (even). + - case 4 : FastForth keeps the memory of all resident definitions. During source file download the - conditionnal compilation allows to compile only non-resident definitions. +* WIPE level : PUC --> `-n SYS` --> WARM display --> SLEEP - case 4.1 : Running a "MARKER" definition will delete anything compiled beyond that. - By starting a source file with this "MARKER" tag, the memory is first cleared of - all the contents of that source file each time it is reloaded. + * `-n SYS` (n<0) performs the software Deep Reset: + + * INIT_FORTH and INIT_HARD_APP (INIT_TERM by default) are executed, + * all programs donwloaded from the terminal or from the SD_Card are lost, + * the default state of COLD_APP, INI_SOFT_APP, INI_HARD_APP and BACKGND_APP is restored, + * all "defered" words are initialised with their default value, + * all interrupts vectors also, + * SIGNATURES area is FFh full filled. + * WARM display = #-n. + * hardware `SW1+RESET` does same effects, WARM display = #-1. + + * recompiling FastForth, too, WARM display = #-3. +* ERROR : ABORT" --> ABORT" display --> SLEEP. + + * when an error occurs, FASTFORTH discards the end of current downloading if any, does same as `SYS` then displays the error message. In this way, any error is followed by the complete erasure of the bad defined word causing this error, and also by discarding the end of downloading of the source file including it. -As all other words FORTH, PWR_STATE PWR_HERE RST_STATE RST_HERE and MARKER defn. may be also used in definitions. + * It is strongly recommended to end any source file with `RST_SET` to protect it program from any subsequent error. -If you have previously set 'NOECHO', there is no WARM display. -With I2C_FastForth, WARM display is preceded by the I2C slave address, example; `@18`. -If an error occurs from the interpreter, FORTH is restarted, the error is always displayed and the program beyond PWR_HERE is lost. +As all other words FORTH, RST_SET RST_RET and MARKER definitions may be freely used in compiling mode. -In this way, any error is followed by the complete erasure of a bad definined word causing this error, -or by that of the downloaded source file including it. +If you have previously set 'NOECHO', there is no WARM, COLD, WIPE display. -It is therefore recommended to end a source file with at least 'PWR_HERE' to protect it -from any subsequent error. +With I2C_FastForth version, WARM display is preceded by the decimal I2C slave address, example: `@18`. ## VOCABULARY ADD-ON -These words are not ANS94 compliant, they are those of F83 standard. - -For example, after loading SD_TOOLS add-on, you can type: ALSO ASSEMBLER WORDS PREVIOUS WORDS +These words are not ANS94 compliant. - With `ALSO ASSEMBLER`, the vocabulary ASSEMBLER is added to the search CONTEXT thus the ASSEMBLER words - become visible, - - WORDS display the words of ASSEMBLER then those of FORTH, - - PREVIOUS remove the vocabulary ASSEMBLER form the CONTEXT, and the ASSEMBLER words become hidden, - - so the last WORDS display only FORTH words. - -In the forthMSP430FR_ASM.asm, see the FORTH word CODE that add ASSEMBLER to the search CONTEXT and the ASSEMBLER word ENDCODE - that remove ASSEMBLER from search CONTEXT. Thus, the assembler words can be used only between CODE and ENDCODE. +The CONTEXT stack is 8 word_set sized. -The CONTEXT can grow up to 6 vocabularies by using the word ALSO. +after typing: WORDSET TRUC \ a new word-set called TRUC is created -If you want add words to the assembler you must type: ALSO ASSEMBLER DEFINITIONS, -The vocabulary ASSEMBLER is added to the search CONTEXT as previously but also becomes the CURRENT vocabulary in which the new words will be stored. + TRUC adds the word-set TRUC first in the CONTEXT stack, the interpreter search existing definitions first in TRUC + PREVIOUS removes TRUC from CONTEXT -Finally, `FORTH ONLY DEFINITIONS` limits the search CONTEXT to FORTH and the CURRENT vocabulary is FORTH. + DEFINITIONS adds news definitions in the first word-set in the CONTEXT stack, i.e. TRUC, + PREVIOUS removes TRUC from CONTEXT but new definitions are still added in TRUC + DEFINITIONS new definitions are added into the previous first word-set in the CONTEXT stack, + after `-1 SYS`: the FORTH word-set. -**WARNING !** it is discouraged to execute any definition included in the assembler word-set. ## EMBEDDED ASSEMBLER @@ -848,16 +906,15 @@ See files \\inc\\Target.pat. FAST FORTH knows three kinds of definitions : -* high level FORTH definitions : <name> ... ; +* high level FORTH definitions `: <name> ... ;` -* low level definitions CODE <name> ... ENDCODE +* low level definitions `CODE <name> ... ENDCODE` -* low level hidden definitions HDNCODE <name> ... ENDCODE - they are hidden because not FORTH executable. +* low level hidden definitions `HDNCODE <name> ... ENDCODE` which are deliberately hidden because they are not executable by FORTH. Examples: - : NOOP \ FORTH definiton "NOOP", do nothing + : NOOP \ FORTH definition "NOOP", does nothing DUP DROP ; @@ -876,18 +933,18 @@ Examples: THEN \ else return to background task SLEEP MOV @RSP+,SR \ restore SR flags - BIC #%1111_1000,SR \ but force CPU Active Mode + BIC #%0111_1000,SR \ but force CPU Active Mode, disable all interrupts RET \ (instead of RETI) ENDCODE -A the end of low level CODE definition, the instruction MOV @IP+,PC jumps to the next definition. +At the end of low level CODE definition, the instruction MOV @IP+,PC jumps to the next definition. This faster (4 cycles) and shorter (one word) instruction replaces the famous pair of assembly instructions : CALL #LABEL ... RET (4+4 cycles, 2+1 words). The register IP is the Interpretative Pointer. -High level FORTH definitions starts with a boot code "DOCOL" that save the IP pointer, reload it with the first address -of a list of execution addresses, then performs a postincrement branch to this first address. -The list ends with the address of another piece of code: EXIT (6 cycles) that restores IP before the instruction MOV @IP+,PC. +High level FORTH definitions starts with a boot code "DOCOL" which saves the IP pointer and loads it with the first address +of a list of execution addresses, then performs a postincrement branch to the first one. +The list ends with the address of another piece of code: EXIT (6 cycles) which restores IP before the instruction MOV @IP+,PC. here, the compilation of low level ADD definition : @@ -898,7 +955,9 @@ here, the compilation of low level ADD definition : and the one of the high level word NOOP : header \ compiled by the word : - execution addr CALL rDOCOL \ boot code "DOCOL" compiled by the word : + execution addr + DOCOL PUSH IP \ boot code "DOCOL"... + CALL rDOCOL \ ...compiled by the word : addr of DUP \ execution addr of DUP addr of DROP \ execution addr of DROP addr of EXIT \ execution addr of EXIT compiled by the word ; @@ -944,7 +1003,8 @@ A little more complex, the case of mixing FORTH and assembly with use of the wor If we see the code "MIX\_FORTH\_ASM" after compilation : header \ compiled by : - exec@ CALL rDOCOL \ boot code "DOCOL" (which saves IP onto stack) compiled by : + exec@ PUSH IP \ + CALL rDOCOL addr of SWAP addr of DUP next addr \ addr of asm1, compiled by HI2LO @@ -970,12 +1030,13 @@ If we see this code "MIX\_ASM\_FORTH" after compilation : header \ compiled by CODE exec@ asm1 asm2 + DOCOL PUSH IP CALL rDOCOL \ "DOCOL" compiled by COLON addr of word1 addr of word2 addr of EXIT \ EXIT restores IP from stack then executes MOV @IP+,PC -A new step +A new step: : MIX_FORTH_ASM_FORTH \ definition of a FORTH word starts with : word1 @@ -992,8 +1053,9 @@ A new step the compiled result - header \ compiled by : - exec@ CALL rDOCOL \ "DOCOL" boot code compiled by : + header \ ) + exec@ PUSH IP \ > compiled by : + CALL rDOCOL \ ) addr of word1 addr of word2 ... @@ -1001,32 +1063,20 @@ the compiled result MOV #0,IP \ IP is free for use asm1 \ assembly instruction ... - CALL #EXIT \ compiled by LO2HI + CALL rDOCOL \ compiled by LO2HI addr of word3 addr of word4 addr of EXIT \ compiled by ; -EXIT is used twice ! - -the first time, by LO2HI : - - EXIT MOV @RSP+,IP \ 2 pop into IP the PC pushed on return stack by CALL #EXIT - MOV @IP+,PC \ 4 execute the routine at addr3 - -then at the end of FORTH word (addr5): - - EXIT MOV @RSP+,IP \ 2 pop old IP from return stack - MOV @IP+,PC \ 4 execute the routine pointed by the old IP - Still another step : CODE MIX_ASM_FORTH_ASM \ CODE starts a low level word asm1 asm2 - COLON \ switch to start FORTH word (COLON saves IP) + COLON \ start high level definition word ... - HI2LO \ FORTH to assembler switch + HI2LO \ switch high to low level asm3 asm4 MOV @RSP+,IP \ restore IP @@ -1039,7 +1089,7 @@ In fact, an exclusive of FAST FORTH, the start of a word FORTH can be placed any asm1 asm2 ... - COLON \ starts high level + COLON \ starts high level definition word1 word2 ... @@ -1058,13 +1108,14 @@ with the compiled result : header \ compiled by CODE exec@ asm asm - CALL rDOCOL \ "DOCOL" compiled by COLON + DOCOL PUSH IP \ compiled... + CALL rDOCOL \ ...by COLON addr addr next address \ compiled by HI2LO asm asm - CALL #EXIT \ compiled by LO2HI + CALL rDOCOL \ compiled by LO2HI addr addr EXIT addr \ that restores IP from return stack and then executes MOV @IP+,PC @@ -1168,7 +1219,7 @@ another nest : you can MIX conditional branches with a mix of FORTH/assembly: see TEST5 in the demo file \MSP430-FORTH\TESTASM.4TH -FAST FORTH have one pass assembler, not able to make forward jump. +FAST FORTH have one pass assembler, not able to resolve forward jumps. I have added possibility of several "non canonical" jumps, up to 3 backward and up to 3 forward jumps to label : @@ -1203,7 +1254,7 @@ I have added possibility of several "non canonical" jumps, up to 3 backward and ENDCODE Forward labels FWx are for single use, backward labels BWx can solve several jumps, -until new definition. +until their new definition. ### SYMBOLIC ASSEMBLER ? YES ! @@ -1216,6 +1267,38 @@ Gema translates FORTH registers in ASM registers (R0 to R15) via \inc\ThingsInFi With the three bat files in \MSP430_FORTH folder all is done automatically. +### WHAT ABOUT VARIABLES, CONSTANTS... + +In addition to the FORTH VARIABLE and CONSTANT definitions, the macroassembler allows to use symbolic variables and constants +which are compiled / executed as number by the FORTH interpreter, also by the assembler, but only in the scope of a source use.f file with their declaration done in a use.pat file. + +On the other hand, the CONSTANT, VARIABLE and MARKER definitions are correctly handled by the assembler which provides for each case the expected argument: the constant, the address of the variable and the address of the first user variable with MARKER. + +Example: + + VARIABLE BASE + $10 BASE ! + 2 CONSTANT TWO + MARKER {MYAPP} + 'ESC' , 'XON' C, 'XOFF' C, + + HDNCODE EXAMPLE \ hidden definition because linked in the hidden word-set + CMP #RET_ADR,&{MYAPP}-2 \ compare content of {MYAPP}-2 address with RET_ADR + MOV &BASE,X \ X = 16 + MOV #BASE,X \ X = address of base + MOV @X,X \ X = 16 + MOV #TWO,Y \ Y = 2 + MOV &{MYAPP},W \ W = $1B + MOV.B &{MYAPP}+2,W \ W = 17 + MOV.B &{MYAPP}+3,W \ W = 19 + MOV @IP+PC + ENDCODE + + CODE RUN_EXAMPLE + MOV #EXAMPLE,PC \ = BR EXAMPLE runs EXAMPLE, without return + ENDCODE + + # COMPILE FAST FORTH FOR YOUR TARGET 1- in forthMSP430FR.asm "TARGET configuration" create a line for your target, example: @@ -1228,7 +1311,7 @@ Notice that you must define here only the necessary for FAST-FORTH compilation. 3- in \inc\ThingsInFirst.inc add one "device.inc" item: .IFDEF MY_MSP430FR5738_1 - UCA0_UART ; defines uart used by FORTH input terminal + UCA0_UART ; defines uart used for TERMINAL LF_XTAL ; defines if your module have a 32768 Hz xtal, to enable it. UCB0_SD ; defines UC used for SD Card driver if any .include "MSP430FR5738.inc" ; include device declarations @@ -1252,14 +1335,14 @@ that is the reset state of FastForth... # ANNEXES -Here you have a good view of MSP430 assembly: +Here you have a good overview of MSP430 assembly: [MSP430 ISA](http://www.ece.utep.edu/courses/web3376/Notes_files/ee3376-isa.pdf) FastForth embedded assembler doesn't recognize the (useless) TI's symbolic addressing mode: ADD.B EDE,TONI. -REGISTERS correspondence (you can use freely ASM or TI or FASTFORTH registers's names). +REGISTERS correspondence (you can freely use ASM or TI or FASTFORTH registers's names). - ASSEMBLER TI FASTFORTH comment + ASM TI FASTFORTH comment R0 PC PC Program Counter R1 SP RSP Return Stack Pointer @@ -1281,13 +1364,32 @@ REGISTERS correspondence (you can use freely ASM or TI or FASTFORTH registers's **REGISTERS use** The FASTFORTH registers rDOCOL, rDOVAR, rDOCON and rDODOES must be preserved. -If you use them you may either PUSHM #4,M before and POPM #4,M after, -or use then restore FastForth default values: -xdocol, xdovar, xdocon, xdodoes. See device.pat. +If you use them you may either `PUSHM #4,M` before and `POPM #4,M after`, +or use them directly then restore FastForth default values: + +`MOV #INIT_DOXXX,X` +`MOV @X+,rDOCOL` +`MOV @X+,rDODOES` +`MOV @X+,rDOCON` +`MOV @X,rDOVAR` + +(Search `INIT_DOXXX` in your \inc\device.pat) + +If you want to restore only rDODOES, rDOCON and rDOVAR: + +`MOV #INIT_DOXXX+4,X` +`MOV @X+,rDODOES` +`MOV @X+,rDOCON` +`MOV @X,rDOVAR` + +If you want to restore only rDODOES and rDOCON: + +`MOV #XDODOES,rDODOES` +`MOV #XDOCON,rDOCON` When you use these registers you can't call any FORTH words created by them at the same time! -don't use R3 and use R2 only with BIC, BIT, BIS instructions in register mode. +don't use R3 and use R2 (SR) only with BIC, BIT, BIS instructions in register mode. The bits 0-11 of SR register are saved by interrupts and restored by the instruction RETI. you can use freely UF9 UF10 and UF11 as SR bits 9-11. @@ -1315,32 +1417,32 @@ don't never pop a byte with instruction MOV.B @PSP+, because it generates a stac register RSP is the Return Stack Pointer (SP). -to push one cell on the RSP stack : `PUSH <what you want>` +to push one cell on the RSP stack: `PUSH <what you want>` -to pop one cell from the RSP stack : `MOV @RSP+,<where you want>` +to pop one cell from the RSP stack: `MOV @RSP+,<where you want>` -don't never pop a byte with instruction `MOV.B @RSP+, ...` +don't never push or pop a byte on RSP stack ! to push multiple registers on the RSP stack : - PUSHM #n,Rx \ with 0 <= x-(n-1) < 16 +`PUSHM #n,Rx`, with 0 <= x-(n-1) < 16 to pop multiple registers from the RSP stack : - POPM #n,Rx \ with 0 <= x-(n-1) < 16 +`POPM #n,Rx`, with 0 <= x-(n-1) < 16 PUSHM order : PSP,TOS, IP, S , T , W , X , Y ,rDOVAR,rDOCON,rDODOES,rDOCOL, R3, SR,RSP, PC PUSHM order : R15,R14,R13,R12,R11,R10, R9, R8, R7 , R6 , R5 , R4 , R3, R2, R1, R0 -example : `PUSHM #6,IP` pushes `IP,S,T,W,X,Y` registers to return stack +example : `PUSHM #6,IP` pushes IP,S,T,W,X,Y registers to return stack POPM order : PC,RSP, SR, R3,rDOCOL,rDODOES,rDOCON,rDOVAR, Y , X , W , T , S , IP,TOS,PSP POPM order : R0, R1, R2, R3, R4 , R5 , R6 , R7 , R8, R9,R10,R11,R12,R13,R14,R15 -example : `POPM #6,IP` pulls `Y,X,W,T,S,IP` registers from return stack +example : `POPM #6,IP` pulls Y,X,W,T,S,IP registers from return stack -Error occurs if `#n` is out of bounds. +Error occurs if #n is out of bounds. **conditionnal jumps use** @@ -1353,187 +1455,145 @@ Error occurs if `#n` is out of bounds. 0>= with IF UNTIL WHILE 0< with ?GOTO - # FAST FORTH resumed - - RETURN-STACK-CELLS = 48 maximum size of the return stack, in cells - STACK-CELLS = 48 maximum size of the data stack, in cells - /COUNTED-STRING = 255 maximum size of a counted string, in characters + RETURN-STACK-CELLS = 48 max size of the return stack, in cells + STACK-CELLS = 48 max size of the data stack, in cells + /COUNTED-STRING = 255 max size of a counted string, in characters /HOLD = 34 size of the pictured numeric output string buffer, in characters /PAD = 84 size of the scratch area pointed to by PAD, in characters - ADDRESS-UNIT-BITS = 16 size of one address unit, in bits - FLOORED = true true if floored division is the default - MAX-CHAR = 255 maximum value of any character in the implementation-defined character set + ADDRESS-UNIT-BITS = 16 size of one address unit, in bits + FLOORED = true true if floored division is the default + MAX-CHAR = 255 max value of any character in the implementation-defined character set MAX-N = 32767 largest usable signed integer MAX-U = 65535 largest usable unsigned integer MAX-D = 2147483647 largest usable signed double number MAX-UD = 4294967295 largest usable unsigned double number - DeFiNiTiOnS aRe CaSe-InSeNsItIvE Strings are case-sensitive - + DeFiNiTiOnS aRe CaSe-InSeNsItIvE they are compiled in their CAPS_ON form. ## FORTH word-set -It is reduced to a minimum, but nevertheless extensible up to ... $FF80 ! - - RST_HERE PWR_HERE RST_STATE PWR_STATE CREATE ; : IMMEDIATE - POSTPONE ] [ \ ' ['] ABORT" INTERPRET - COUNT LITERAL ALLOT , >NUMBER FIND WORD ." - S" . U. SIGN HOLD #> #S # - <# ! @ CR TYPE NOECHO ECHO EMIT - KEY ACCEPT COLD WARM WIPE - -[CREATE ](https://forth-standard.org/standard/core/CREATE) -[; ](https://forth-standard.org/standard/core/Semi) -[: ](https://forth-standard.org/standard/core/Colon) -[IMMEDIATE ](https://forth-standard.org/standard/core/IMMEDIATE) -[POSTPONE ](https://forth-standard.org/standard/core/POSTPONE) -[\] ](https://forth-standard.org/standard/core/right-bracket) -[\[ ](https://forth-standard.org/standard/core/Bracket) -[\\ ](https://forth-standard.org/standard/block/bs) -[\[\'\] ](https://forth-standard.org/standard/core/BracketTick) -[\' ](https://forth-standard.org/standard/core/Tick) -[ABORT" ](https://forth-standard.org/standard/core/ABORTq) -[COUNT ](https://forth-standard.org/standard/core/COUNT) -[LITERAL ](https://forth-standard.org/standard/core/LITERAL) -[ALLOT ](https://forth-standard.org/standard/core/ALLOT) -[, ](https://forth-standard.org/standard/core/Comma) -[>NUMBER ](https://forth-standard.org/standard/core/toNUMBER) -[FIND ](https://forth-standard.org/standard/core/FIND) -[WORD ](https://forth-standard.org/standard/core/WORD) -[." ](https://forth-standard.org/standard/core/Dotq) -[S" ](https://forth-standard.org/standard/core/Sq) -[. ](https://forth-standard.org/standard/core/d) -[U. ](https://forth-standard.org/standard/core/Ud) -[SIGN ](https://forth-standard.org/standard/core/SIGN) -[HOLD ](https://forth-standard.org/standard/core/HOLD) -[#> ](https://forth-standard.org/standard/core/num-end) -[#S ](https://forth-standard.org/standard/core/numS) -[# ](https://forth-standard.org/standard/core/num) -[<# ](https://forth-standard.org/standard/core/num-start) -[! ](https://forth-standard.org/standard/core/Store) -[@ ](https://forth-standard.org/standard/core/Fetch) -[CR ](https://forth-standard.org/standard/core/CR) -[TYPE ](https://forth-standard.org/standard/core/TYPE) -[EMIT ](https://forth-standard.org/standard/core/EMIT) -[KEY ](https://forth-standard.org/standard/core/KEY) -[ACCEPT ](https://forth-standard.org/standard/core/ACCEPT) - - COLD PFA of COLD content = STOP_APP subroutine address, by default --> STOP_TERM - WARM PFA of WARM content = INI_APP subroutine address, by default --> ENABLE_IO - WIPE resets the program memory to its original state (Deep_RST have same effect). - RST_HERE defines the bound of the program memory protected against COLD or hardware reset. - PWR_HERE defines the bound of the program memory protected against ON/OFF and also against any error occurring. - RST_STATE removes all words defined after RST_HERE (COLD or <reset> have same effet) - PWR_STATE removes all words defined after PWR_HERE (an error has same effect) - INTERPRET text interpreter, common part of EVALUATE and QUIT. - NOECHO stop display on output - ECHO start display on output - -### words added by the option MSP430ASSEMBLER: - - HDNCODE CODE HI2LO - - CODE <word> creates a word written in assembler. - this defined <word> must be ended with ENDCODE unless COLON or LO2HI use. - HDNCODE <word> creates a word written in assembler but not interpretable by FORTH (because ended by RET instr.). - Visible only from assembler +Reduced to 53 definitions, but with everything necessary to be expandable up to $FF80. + +RST_SET, +RST_RET, +[MARKER ](https://forth-standard.org/standard/core/MARKER), +HI2LO, +CODENNM, +HDNCODE, +CODE, +[IS ](https://forth-standard.org/standard/core/IS), +[\:NONAME ](https://forth-standard.org/standard/core/ColonNONAME), +[DOES> ](https://forth-standard.org/standard/core/DOES), +[CREATE ](https://forth-standard.org/standard/core/CREATE), +[IMMEDIATE ](https://forth-standard.org/standard/core/IMMEDIATE), +[; ](https://forth-standard.org/standard/core/Semi), +[: ](https://forth-standard.org/standard/core/Colon), +[POSTPONE ](https://forth-standard.org/standard/core/POSTPONE), +[\\ ](https://forth-standard.org/standard/core/bs), +[\] ](https://forth-standard.org/standard/core/right-bracket), +[\[ ](https://forth-standard.org/standard/core/Bracket), +[\[\'\] ](https://forth-standard.org/standard/core/BracketTick), +[\' ](https://forth-standard.org/standard/core/Tick), +[ABORT" ](https://forth-standard.org/standard/core/ABORTq), +[ALLOT ](https://forth-standard.org/standard/core/ALLOT), +[COUNT ](https://forth-standard.org/standard/core/COUNT), +[LITERAL ](https://forth-standard.org/standard/core/LITERAL), +[, ](https://forth-standard.org/standard/core/Comma), +[>NUMBER ](https://forth-standard.org/standard/core/toNUMBER), +[FIND ](https://forth-standard.org/standard/core/FIND), +[WORD ](https://forth-standard.org/standard/core/WORD), +[." ](https://forth-standard.org/standard/core/Dotq), +[S" ](https://forth-standard.org/standard/core/Sq), +[. ](https://forth-standard.org/standard/core/d), +[U. ](https://forth-standard.org/standard/core/Ud), +[SIGN ](https://forth-standard.org/standard/core/SIGN), +[HOLD ](https://forth-standard.org/standard/core/HOLD), +[#> ](https://forth-standard.org/standard/core/num-end), +[#S ](https://forth-standard.org/standard/core/numS), +[# ](https://forth-standard.org/standard/core/num), +[<# ](https://forth-standard.org/standard/core/num-start), +[\[UNDEFINED\] ](https://forth-standard.org/standard/tools/BracketUNDEFINED), +[\[DEFINED\] ](https://forth-standard.org/standard/tools/BracketDEFINED), +[\[IF\] ](https://forth-standard.org/standard/tools/BracketIF), +[\[THEN\] ](https://forth-standard.org/standard/tools/BracketTHEN) +[\[ELSE\] ](https://forth-standard.org/standard/tools/BracketELSE), +[! ](https://forth-standard.org/standard/core/Store), +[@ ](https://forth-standard.org/standard/core/Fetch), +[TYPE ](https://forth-standard.org/standard/core/TYPE), +NOECHO, +ECHO, +[EMIT ](https://forth-standard.org/standard/core/EMIT), +[KEY ](https://forth-standard.org/standard/core/KEY), +[ACCEPT ](https://forth-standard.org/standard/core/ACCEPT), +SYS. + +Words ACCEPT KEY EMIT are DEFERred definitions. ACCEPT doesn't use KEY. + + RST_SET defines the bound of the program memory protected against any PUC. + RST_RET removes all words defined after RST_SET HI2LO used to switch compilation from high level (FORTH) to low level (assembler). - -### Other words are useable in any source_files.f, see \inc\device.pat file : - - SLEEP CODE_WITHOUT_RETURN: CPU shutdown + CODENNM the assembler counterpart of :NONAME. + CODE <name> creates a definition written in assembler. + this defined <name> must be ended with ENDCODE unless COLON or LO2HI use. + HDNCODE <name> creates a word same as CODE but in the hidden word-set to be visible only in the assembly mode. + NOECHO disables display on the TERMINAL + ECHO enables display on the TERMINAL + SYS 0 SYS | SYS restarts the interpreter, + +n (odd) SYS initializes the hardware and restarts the FORTH engine, + +n (even) SYS does software RESET, initializes the hardware and restarts the FORTH engine, + -n SYS same as +n (even) SYS, plus resets the program memory to its original state. + +### Other words/addresses which are usable in any generic source_files.f + +**All constants, variables and definitions included in \inc\device.pat and \inc\target.pat files are usable by +the assembler and also by the FORTH interpreter (except the definitions).** + + see definitions in forthMSP430FR.asm: + SLEEP ASM CODE_WITHOUT_RETURN: CPU shutdown LIT CODE compiled by LITERAL XSQUOTE CODE compiled by S" and S_ HEREXEC CODE HERE and BEGIN execute address QFBRAN CODE compiled by IF UNTIL BRAN CODE compiled by ELSE REPEAT AGAIN NEXT_ADR CODE NEXT instruction (MOV @IP+,PC) - XDO CODE compiled by DO - XPLOOP CODE compiled by +LOOP - XLOOP CODE compiled by LOOP MUSMOD ASM 32/16 unsigned division, used by ?NUMBER, UM/MOD MDIV1DIV2 ASM input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ MDIV1 ASM input for 48/16 unsigned division, see DOUBLE M*/ - RET_ADR ASM content of INI_FORTH_PFA and MARKER+8 definitions, + RET_ADR ASM RET address, SETIB CODE Set Input Buffer with org & len values, reset >IN pointer REFILL CODE accept one line from input and leave org len of input buffer - CIB_ADR [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG + CIB_ORG Current Input Buffer address, default value: TIB_ORG; may be redirected to SDIB_ORG XDODOES to restore rDODOES: `MOV #XDODOES,rDODOES` XDOCON to restore rDOCON: `MOV #XDOCON,rDOCON` XDOVAR to restore rDOVAR: `MOV #XDOVAR,rDOVAR` - ! to restore rDOCOL: `MOV &WIPE_DOCOL,rDOCOL` - INI_FORTH CODE_WITHOUT_RETURN common part of RST and QABORT, starts FORTH engine - QABORT CODE_WITHOUT_RETURN run-time part of ABORT" - ABORT_TERM CODE_WITHOUT_RETURN called by QABORT, also by QREVEAL and INTERPRET - UART_COLD_TERM ASM, content of COLD_PFA by default - UART_INIT_TERM ASM, content of WARM_PFA by default - UART_RXON ASM, content of SLEEP_PFA by default - UART_RXOFF ASM, called by ACCEPT before Receiving char LF. - I2C_COLD_TERM ASM, content of COLD_PFA by default - I2C_INIT_TERM ASM, content of WARM_PFA by default - I2C_RXON ASM, content of SLEEP_PFA by default - I2C_CTRL_CH ASM, used as is: `MOV.B #CTRL_CHAR,Y` - ! `CALL #I2C_CTRL_CH` + to restore rDOCOL: `MOV &INIT_DOCOL,rDOCOL` + INIT_FORTH CODE_WITHOUT_RETURN, common part of SYS and QABORT, starts FORTH engine + QABORT CODE_WITHOUT_RETURN, run-time part of ABORT" ABORT ABORT address QUIT QUIT address + see definitions in forthMSP430FR_TERM_UART.asm: + ABORT_TERM CODE_WITHOUT_RETURN, called by QABORT, QREVEAL and INTERPRET + UART_WARM + UART_INIT_TERM ASM CODE, content of UART_WARM+2 by default + UART_COLD_TERM ASM CODE, content of UART_COLD+2 by default + UART_INIT_SOFT ASM CODE, content of INIT_FORTH+2 by default = RET address + UART_RXON ASM CODE, content of SLEEP+2 by default + UART_RXOFF ASM CODE, called by ACCEPT -### Other variables useable in source_files.f, see \inc\device.pat file : - - FREQ_KHZ FREQUENCY (in kHz) - TERMBRW_RST TERMBRW_RST - TERMMCTLW_RST TERMMCTLW_RST - I2CSLAVEADR I2C_SLAVE address - I2CSLAVEADR1 - LPM_MODE LPM_MODE value, LPM0+GIE is the default value - RSTIV_MEM SYSRSTIV memory, set to -1 to do Deep RESET - RST_DP RST value for DP - RST_VOC RST value for VOClink - VERSION - THREADS - KERNEL_ADDON - - WIPE_INI MOV #WIPE_INI,X - WIPE_COLD WIPE value for PFA_COLD - WIPE_INI_FORTH WIPE value for PFA_INI_FORTH - WIPE_SLEEP WIPE value for PFA_SLEEP - WIPE_WARM WIPE value for PFA_WARM - WIPE_TERM_INT WIPE value for TERMINAL vector - WIPE_DP WIPE value for RST_DP - WIPE_VOC WIPE value for RST_VOC - - INI_FORTH_INI MOV #INI_FORTH_INI,X \ >BODY instruction of default INI_SOFT_APP - INIT_ACCEPT FORTH value for PFAACCEPT - INIT_CR FORTH value for PFACR - INIT_EMIT FORTH value for PFAEMIT - INIT_KEY FORTH value for PFAKEY - INIT_CIB FORTH value for CIB_ADR - HALF_FORTH_INI to preserve the state of DEFERed words, used by user INI_SOFT_APP as: - ! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" - ! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" - ! MOV @RSP+,PC \ then RET - INIT_DOCOL FORTH value for rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL - INIT_DODOES FORTH value for rDODOES (R5) - INIT_DOCON FORTH value for rDOCON (R6) - INIT_DOVAR FORTH value for rDOVAR (R7) - INIT_CAPS FORTH value for CAPS - INIT_BASE FORTH value for BASE - - - -## MSP430ASSEMBLER word-set - - ?GOTO GOTO FW3 FW2 FW1 BW3 BW2 - BW1 REPEAT WHILE AGAIN UNTIL ELSE THEN - IF 0= 0<> U>= U< 0< 0>= - S< S>= RRUM RLAM RRAM RRCM POPM - PUSHM CALL PUSH.B PUSH SXT RRA.B RRA - SWPB RRC.B RRC AND.B AND XOR.B XOR - BIS.B BIS BIC.B BIC BIT.B BIT DADD.B - DADD CMP.B CMP SUB.B SUB SUBC.B SUBC - ADDC.B ADDC ADD.B ADD MOV.B MOV RETI - LO2HI COLON ENDASM ENDCODE + see definitions in forthMSP430FR_TERM_I2C.asm: + ABORT_TERM CODE_WITHOUT_RETURN, called by QABORT, QREVEAL and INTERPRET + I2C_WARM + I2C_INIT_TERM ASM CODE, content of I2C_WARM+2 by default + I2C_COLD_TERM ASM CODE, content of I2C_COLD+2 by default = RET address + I2C_INIT_SOFT ASM CODE, content of INIT_FORTH+2 by default = RET address + I2C_RXON ASM CODE, content of SLEEP+2 by default + I2C_CTRL_CH ASM CODE, used as is: MOV.B #CTRL_CHAR,Y + CALL #I2C_CTRL_CH + + +## MSP430ASSEMBLER word-set (in the hidden word-set) [ADD, ADD.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=135), [ADDC, ADDC.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=136), @@ -1548,18 +1608,44 @@ It is reduced to a minimum, but nevertheless extensible up to ... $FF80 ! [PUSH, PUSH.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=168), [RETI ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=170), [RRA, RRA.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=173), -[RRC, RRC.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=174) -[SUB, SUB.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=179) -[SUBC, SUBC.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=180) -[SWPB ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=181) -[SXT ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=182) -[XOR, XOR.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=184) -[RRUM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=218) -[RLAM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=208) -[RRAM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=211) -[RRCM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=214) -[POPM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=204) -[PUSHM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=205) +[RRC, RRC.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=174), +[SUB, SUB.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=179), +[SUBC, SUBC.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=180), +[SWPB ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=181), +[SXT ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=182), +[XOR, XOR.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=184), +[RRUM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=218), +[RLAM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=208), +[RRAM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=211), +[RRCM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=214), +[POPM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=204), +[PUSHM ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=205), +?GOTO, +GOTO, +BW3, +BW2, +BW1, +FW3, +FW2, +FW1, +REPEAT, +WHILE, +AGAIN, +UNTIL, +ELSE, +THEN, +IF, +0=, +0<>, +U>=, +U<, +0<, +0>=, +S<, +S>=, +LO2HI, +COLON, +ENDCODE. ?GOTO used after a conditionnal (0=,0<>,U>=,U<,0<,S<,S>=) to branch to a label FWx or BWx GOTO used as unconditionnal branch to a label FWx or BWx @@ -1584,8 +1670,8 @@ It is reduced to a minimum, but nevertheless extensible up to ... $FF80 ! 0>= conditionnal, to use only with IF UNTIL WHILE S< conditionnal S>= conditionnal - LO2HI switches compilation between low level and high level modes without saving IP register. - COLON pushes IP then performs LO2HI, used as: CODE <word> ... assembler instr ... COLON ... FORTH words ... ; + LO2HI switches compilation from low level to high level modes without saving IP register. + COLON pushes IP then performs LO2HI. ENDCODE to end a CODE or HDNCODE definition. #### EXTENDED_MEM WORDS set: @@ -1624,187 +1710,177 @@ Full 20 bits address/data assembler [XORX, XORX.A, XORX.B ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=227), [RPT ](http://www.ti.com/lit/ug/slau272d/slau272d.pdf#page=119) -### CONDCOMP ADD-ON - -[MARKER ](https://forth-standard.org/standard/core/MARKER), -[\[DEFINED\] ](https://forth-standard.org/standard/tools/BracketDEFINED), -[\[UNDEFINED\] ](https://forth-standard.org/standard/tools/BracketUNDEFINED), -[\[IF\] ](https://forth-standard.org/standard/tools/BracketIF), -[\[ELSE\] ](https://forth-standard.org/standard/tools/BracketELSE), -[\[THEN\] ](https://forth-standard.org/standard/tools/BracketTHEN) - - ### VOCABULARY ADD-ON [DEFINITIONS ](https://forth-standard.org/standard/search/DEFINITIONS), -[ONLY ](https://forth-standard.org/standard/search/ONLY), [PREVIOUS ](https://forth-standard.org/standard/search/PREVIOUS), -[ALSO ](https://forth-standard.org/standard/search/ALSO) - -ASSEMBLER sets ASSEMBLER as CONTEXT word set -FORTH sets FORTH as CONTEXT word set -VOCABULARY <name> creates a new word-set - +ONLY, +FORTH, +WORDSET. -### NONAME ADD-ON - -[\:NONAME ](https://forth-standard.org/standard/core/ColonNONAME), -[DEFER ](https://forth-standard.org/standard/core/DEFER), -[IS ](https://forth-standard.org/standard/core/IS) - -CODENNM is the assembly counterpart of :NONAME. + FORTH adds FORTH as first CONTEXT word-set + FORTH ONLY clears the CONTEXT stack, same as `-1 SYS` + WORDSET <name> creates a new word-set named <name> + <name> adds this named word-set in the CONTEXT stack ### SD_CARD_LOADER ADD-ON - LOAD" LOAD" SD_TEST.4TH" loads source file SD_TEST.4TH from SD_Card and compile it. + LOAD" SD_TEST.4TH" loads source file SD_TEST.4TH from SD_Card and compile it. + BOOT enable bootstrap + NOBOOT disable bootstrap +Once bootloader is enabled, any PUC event loads (and executes) the file \BOOT.4TH from the SD_Card. ### SD_CARD_READ_WRITE ADD-ON - TERM2SD" SD_EMIT WRITE READ CLOSE DEL" WRITE" - READ" - - TERM2SD" TERM2SD" SD_TEST.4TH" copy input file to SD_CARD (use CopySourceFileToTarget_SD_Card.bat to do) +TERM2SD", +SD_EMIT, +WRITE, +READ, +CLOSE, +DEL", +WRITE", +APPEND", +READ". + + TERM2SD" TERM2SD" SD_TEST.4TH" copy input file to SD_CARD + (use CopySourceFileToTarget_SD_Card.bat to do) SD_EMIT sends output stream at the end of last opened as write file. - WRITE write sequentially BUFFER content to a sector - READ read sequentially a sector to BUFFER + WRITE write sequentially the content of SD_buf to a file + READ read sequentially a file in SD_buf, leave a flag, false when the file is automatically closed. CLOSE close last opened file. DEL" DEL" SD_TEST.4TH" remove this file from SD_CARD. - WRITE" WRITE" TRUC" open or create TRUC file ready to write to the end of this file - READ" READ" TRUC" open TRUC and load its first sector in BUFFER - - - -### BOOTLOADER - -to enable bootloader: `' BOOT IS WARM`, -to disable bootloader: `' BOOT [PFA] IS WARM` - -Once bootloader enabled, any PUC event loads (and executes) the file \BOOT.4TH from the SD_Card. + WRITE" WRITE" TRUC" create or overwrite a file TRUC ready to write to its beginning. + APPEND" APPEND" TRUC" open or create a file TRUC ready to write to the end of this file + READ" READ" TRUC" open TRUC and load its first sector in SD_buf ## OPTIONNAL ADD-ON -* when ADD-ONs are compiled with the kernel, their respective MARKER word identified with braces {} does nothing. - Sources are in the folder \ADDON, as source.asm file. - -* when ADD-ONs are downloaded, their respective MARKER word identified with braces {} removes all ADD-ONs words. +* Their respective MARKER word identified with braces {} removes all ADD-ONs words. Sources are in the folder \MSP430-FORTH\, as source.f file. ### ANS_COMP Adds complement to pass FORTH ANS94 core test. -[VALUE ](https://forth-standard.org/standard/core/VALUE), -[TO ](https://forth-standard.org/standard/core/TO), -[BEGIN ](https://forth-standard.org/standard/core/BEGIN), -[DOES> ](https://forth-standard.org/standard/core/DOES), -[SPACES ](https://forth-standard.org/standard/core/SPACES), -[SPACE ](https://forth-standard.org/standard/core/SPACE), -[BL ](https://forth-standard.org/standard/core/BL), -[PAD ](https://forth-standard.org/standard/core/PAD), -[>IN ](https://forth-standard.org/standard/core/toIN), -[BASE ](https://forth-standard.org/standard/core/BASE), -[STATE ](https://forth-standard.org/standard/core/STATE), -[CONSTANT ](https://forth-standard.org/standard/core/CONSTANT), -[VARIABLE ](https://forth-standard.org/standard/core/VARIABLE), -[SOURCE ](https://forth-standard.org/standard/core/SOURCE), -[RECURSE ](https://forth-standard.org/standard/core/RECURSE), -[EVALUATE ](https://forth-standard.org/standard/core/EVALUATE), -[EXECUTE ](https://forth-standard.org/standard/core/EXECUTE), -[>BODY ](https://forth-standard.org/standard/core/toBODY), -[.( ](https://forth-standard.org/standard/core/Dotp), -[( ](https://forth-standard.org/standard/core/p), -[DECIMAL ](https://forth-standard.org/standard/core/DECIMAL), -[HEX ](https://forth-standard.org/standard/core/HEX), -[HERE ](https://forth-standard.org/standard/core/HERE), -[FILL ](https://forth-standard.org/standard/core/FILL), -[MOVE ](https://forth-standard.org/standard/core/MOVE), -[+! ](https://forth-standard.org/standard/core/PlusStore), -[[CHAR] ](https://forth-standard.org/standard/core/BracketCHAR), -[CHAR ](https://forth-standard.org/standard/core/CHAR), -[CELL+ ](https://forth-standard.org/standard/core/CELLPlus), -[CELLS ](https://forth-standard.org/standard/core/CELLS), -[CHAR+ ](https://forth-standard.org/standard/core/CHARPlus), -[CHARS ](https://forth-standard.org/standard/core/CHARS), -[ALIGN ](https://forth-standard.org/standard/core/ALIGN), -[ALIGNED ](https://forth-standard.org/standard/core/ALIGNED), -[2OVER ](https://forth-standard.org/standard/core/TwoOVER), -[2SWAP ](https://forth-standard.org/standard/core/TwoSWAP), -[2DROP ](https://forth-standard.org/standard/core/TwoDROP), -[2DUP ](https://forth-standard.org/standard/core/TwoDUP), -[2! ](https://forth-standard.org/standard/core/TwoStore), -[2@ ](https://forth-standard.org/standard/core/TwoFetch), -[R@ ](https://forth-standard.org/standard/core/RFetch), -[ROT ](https://forth-standard.org/standard/core/ROT), -[OVER ](https://forth-standard.org/standard/core/OVER), -[*/ ](https://forth-standard.org/standard/core/TimesDiv), -[*/MOD ](https://forth-standard.org/standard/core/TimesDivMOD), -[MOD ](https://forth-standard.org/standard/core/MOD), -[/ ](https://forth-standard.org/standard/core/Div), -[/MOD ](https://forth-standard.org/standard/core/DivMOD), -[* ](https://forth-standard.org/standard/core/Times), -[FM/MOD ](https://forth-standard.org/standard/core/FMDivMOD), -[ABS ](https://forth-standard.org/standard/core/ABS), -[NEGATE ](https://forth-standard.org/standard/core/NEGATE), -[SM/REM ](https://forth-standard.org/standard/core/SMDivREM), -[UM/MOD ](https://forth-standard.org/standard/core/UMDivMOD), -[M* ](https://forth-standard.org/standard/core/MTimes), -[UM* ](https://forth-standard.org/standard/core/UMTimes), -[2/ ](https://forth-standard.org/standard/core/TwoDiv), -[2* ](https://forth-standard.org/standard/core/TwoTimes), -[MIN ](https://forth-standard.org/standard/core/MIN), -[MAX ](https://forth-standard.org/standard/core/MAX), -[RSHIFT ](https://forth-standard.org/standard/core/RSHIFT), -[LSHIFT ](https://forth-standard.org/standard/core/LSHIFT), -[INVERT ](https://forth-standard.org/standard/core/INVERT), -[1- ](https://forth-standard.org/standard/core/OneMinus), -[1+ ](https://forth-standard.org/standard/core/OnePlus), -[S>D ](https://forth-standard.org/standard/core/StoD), -[XOR ](https://forth-standard.org/standard/core/XOR), -[OR ](https://forth-standard.org/standard/core/OR), -[AND ](https://forth-standard.org/standard/core/AND), -[LEAVE ](https://forth-standard.org/standard/core/LEAVE), -[UNLOOP ](https://forth-standard.org/standard/core/UNLOOP), -[J ](https://forth-standard.org/standard/core/J), -[I ](https://forth-standard.org/standard/core/I), -[+LOOP ](https://forth-standard.org/standard/core/PlusLOOP), -[LOOP ](https://forth-standard.org/standard/core/LOOP), -[DO ](https://forth-standard.org/standard/core/DO), -[REPEAT ](https://forth-standard.org/standard/core/REPEAT), -[WHILE ](https://forth-standard.org/standard/core/WHILE), -[AGAIN ](https://forth-standard.org/standard/core/AGAIN), -[UNTIL ](https://forth-standard.org/standard/core/UNTIL), -[THEN ](https://forth-standard.org/standard/core/THEN), -[ELSE ](https://forth-standard.org/standard/core/ELSE), -[IF ](https://forth-standard.org/standard/core/IF), -[> ](https://forth-standard.org/standard/core/more), -[< ](https://forth-standard.org/standard/core/less), -[U< ](https://forth-standard.org/standard/core/Uless), -[= ](https://forth-standard.org/standard/core/Equal), -[0< ](https://forth-standard.org/standard/core/Zeroless), -[0= ](https://forth-standard.org/standard/core/ZeroEqual), -[C, ](https://forth-standard.org/standard/core/CComma), -[C! ](https://forth-standard.org/standard/core/CStore), -[C@ ](https://forth-standard.org/standard/core/CFetch), -[R> ](https://forth-standard.org/standard/core/Rfrom), -[>R ](https://forth-standard.org/standard/core/toR), -[NIP ](https://forth-standard.org/standard/core/NIP), -[DROP ](https://forth-standard.org/standard/core/DROP), -[SWAP ](https://forth-standard.org/standard/core/SWAP), -[DEPTH ](https://forth-standard.org/standard/core/DEPTH), -[EXIT ](https://forth-standard.org/standard/core/EXIT), -[?DUP ](https://forth-standard.org/standard/core/qDUP), -[DUP ](https://forth-standard.org/standard/core/DUP), -[- ](https://forth-standard.org/standard/core/Minus), -[+ ](https://forth-standard.org/standard/core/Plus) +[VALUE ](https://forth-standard.org/standard/core/VALUE), +[TO ](https://forth-standard.org/standard/core/TO), +[DEFER ](https://forth-standard.org/standard/core/DEFER), +[BEGIN ](https://forth-standard.org/standard/core/BEGIN), +[SPACES ](https://forth-standard.org/standard/core/SPACES), +[SPACE ](https://forth-standard.org/standard/core/SPACE), +[BL ](https://forth-standard.org/standard/core/BL), +[PAD ](https://forth-standard.org/standard/core/PAD), +[>IN ](https://forth-standard.org/standard/core/toIN), +[BASE ](https://forth-standard.org/standard/core/BASE), +[STATE ](https://forth-standard.org/standard/core/STATE), +[CONSTANT ](https://forth-standard.org/standard/core/CONSTANT), +[VARIABLE ](https://forth-standard.org/standard/core/VARIABLE), +[SOURCE ](https://forth-standard.org/standard/core/SOURCE), +[RECURSE ](https://forth-standard.org/standard/core/RECURSE), +[EVALUATE ](https://forth-standard.org/standard/core/EVALUATE), +[EXECUTE ](https://forth-standard.org/standard/core/EXECUTE), +[>BODY ](https://forth-standard.org/standard/core/toBODY), +[.( ](https://forth-standard.org/standard/core/Dotp), +[( ](https://forth-standard.org/standard/core/p), +[DECIMAL ](https://forth-standard.org/standard/core/DECIMAL), +[HEX ](https://forth-standard.org/standard/core/HEX), +[HERE ](https://forth-standard.org/standard/core/HERE), +[FILL ](https://forth-standard.org/standard/core/FILL), +[MOVE ](https://forth-standard.org/standard/core/MOVE), +[+! ](https://forth-standard.org/standard/core/PlusStore), +[[CHAR] ](https://forth-standard.org/standard/core/BracketCHAR), +[CHAR ](https://forth-standard.org/standard/core/CHAR), +[CELL+ ](https://forth-standard.org/standard/core/CELLPlus), +[CELLS ](https://forth-standard.org/standard/core/CELLS), +[CHAR+ ](https://forth-standard.org/standard/core/CHARPlus), +[CHARS ](https://forth-standard.org/standard/core/CHARS), +[ALIGN ](https://forth-standard.org/standard/core/ALIGN), +[ALIGNED ](https://forth-standard.org/standard/core/ALIGNED), +[2OVER ](https://forth-standard.org/standard/core/TwoOVER), +[2SWAP ](https://forth-standard.org/standard/core/TwoSWAP), +[2DROP ](https://forth-standard.org/standard/core/TwoDROP), +[2DUP ](https://forth-standard.org/standard/core/TwoDUP), +[2! ](https://forth-standard.org/standard/core/TwoStore), +[2@ ](https://forth-standard.org/standard/core/TwoFetch), +[R@ ](https://forth-standard.org/standard/core/RFetch), +[ROT ](https://forth-standard.org/standard/core/ROT), +[OVER ](https://forth-standard.org/standard/core/OVER), +[*/ ](https://forth-standard.org/standard/core/TimesDiv), +[*/MOD ](https://forth-standard.org/standard/core/TimesDivMOD), +[MOD ](https://forth-standard.org/standard/core/MOD), +[/ ](https://forth-standard.org/standard/core/Div), +[/MOD ](https://forth-standard.org/standard/core/DivMOD), +[* ](https://forth-standard.org/standard/core/Times), +[FM/MOD ](https://forth-standard.org/standard/core/FMDivMOD), +[ABS ](https://forth-standard.org/standard/core/ABS), +[NEGATE ](https://forth-standard.org/standard/core/NEGATE), +[SM/REM ](https://forth-standard.org/standard/core/SMDivREM), +[UM/MOD ](https://forth-standard.org/standard/core/UMDivMOD), +[M* ](https://forth-standard.org/standard/core/MTimes), +[UM* ](https://forth-standard.org/standard/core/UMTimes), +[2/ ](https://forth-standard.org/standard/core/TwoDiv), +[2* ](https://forth-standard.org/standard/core/TwoTimes), +[MIN ](https://forth-standard.org/standard/core/MIN), +[MAX ](https://forth-standard.org/standard/core/MAX), +[RSHIFT ](https://forth-standard.org/standard/core/RSHIFT), +[LSHIFT ](https://forth-standard.org/standard/core/LSHIFT), +[INVERT ](https://forth-standard.org/standard/core/INVERT), +[1- ](https://forth-standard.org/standard/core/OneMinus), +[1+ ](https://forth-standard.org/standard/core/OnePlus), +[S>D ](https://forth-standard.org/standard/core/StoD), +[XOR ](https://forth-standard.org/standard/core/XOR), +[OR ](https://forth-standard.org/standard/core/OR), +[AND ](https://forth-standard.org/standard/core/AND), +[LEAVE ](https://forth-standard.org/standard/core/LEAVE), +[UNLOOP ](https://forth-standard.org/standard/core/UNLOOP), +[J ](https://forth-standard.org/standard/core/J), +[I ](https://forth-standard.org/standard/core/I), +[+LOOP ](https://forth-standard.org/standard/core/PlusLOOP), +[LOOP ](https://forth-standard.org/standard/core/LOOP), +[DO ](https://forth-standard.org/standard/core/DO), +[REPEAT ](https://forth-standard.org/standard/core/REPEAT), +[WHILE ](https://forth-standard.org/standard/core/WHILE), +[AGAIN ](https://forth-standard.org/standard/core/AGAIN), +[UNTIL ](https://forth-standard.org/standard/core/UNTIL), +[THEN ](https://forth-standard.org/standard/core/THEN), +[ELSE ](https://forth-standard.org/standard/core/ELSE), +[IF ](https://forth-standard.org/standard/core/IF), +[> ](https://forth-standard.org/standard/core/more), +[< ](https://forth-standard.org/standard/core/less), +[U< ](https://forth-standard.org/standard/core/Uless), +[= ](https://forth-standard.org/standard/core/Equal), +[0< ](https://forth-standard.org/standard/core/Zeroless), +[0= ](https://forth-standard.org/standard/core/ZeroEqual), +[C, ](https://forth-standard.org/standard/core/CComma), +[C! ](https://forth-standard.org/standard/core/CStore), +[C@ ](https://forth-standard.org/standard/core/CFetch), +[R> ](https://forth-standard.org/standard/core/Rfrom), +[>R ](https://forth-standard.org/standard/core/toR), +[NIP ](https://forth-standard.org/standard/core/NIP), +[DROP ](https://forth-standard.org/standard/core/DROP), +[SWAP ](https://forth-standard.org/standard/core/SWAP), +[DEPTH ](https://forth-standard.org/standard/core/DEPTH), +[EXIT ](https://forth-standard.org/standard/core/EXIT), +[?DUP ](https://forth-standard.org/standard/core/qDUP), +[DUP ](https://forth-standard.org/standard/core/DUP), +[- ](https://forth-standard.org/standard/core/Minus), +[+ ](https://forth-standard.org/standard/core/Plus), +[CR ](https://forth-standard.org/standard/core/CR). ### FIXPOINT - S>F F. F* F#S F/ F- F+ - HOLDS {FIXPOINT} +S>F, +F., +F*, +F#S, +F/, +F-, +F+, +[HOLDS ](https://forth-standard.org/standard/core/HOLDS). S>F u/n -- Qlo Qhi convert u/n in a Q15.16 value F. display a Q15.16 value @@ -1814,29 +1890,25 @@ Adds complement to pass FORTH ANS94 core test. F/ Q15.16 division F- Q15.16 soustraction F+ Q15.16 addition - HOLDS https://forth-standard.org/standard/core/HOLDS ### UTILITY - DUMP U.R WORDS ? .RS .S {TOOLS} - [DUMP ](https://forth-standard.org/standard/tools/DUMP), [U.R ](https://forth-standard.org/standard/core/UDotR), -[WORDS ](https://forth-standard.org/standard/tools/WORDS), +[WORDS ](https://forth-standard.org/standard/tools/WORDS), [? ](https://forth-standard.org/standard/tools/q), [.S ](https://forth-standard.org/standard/tools/DotS), +.RS. .RS displays Return Stack content ### SD_TOOLS - DIR FAT CLUSTER SECTOR {SD_TOOLS} - DIR dump first sector of current directory FAT dump first sector of FAT1 - CLUSTER .123 CLUSTER displays first sector of cluster 123 - SECTOR .123456789 SECTOR displays sector 123456789 + CLUSTER. .123 CLUSTER. displays first sector of cluster 123 + SECTOR. .123456789 SECTOR. displays sector 123456789 ### DOUBLE word set @@ -1873,6 +1945,7 @@ Adds complement to pass FORTH ANS94 core test. First search from ti.com: [MSP430Flasher](http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSP430Flasher/latest/index_FDS.html) untar in a home folder then: +* set executable flag in permission of this file * open MSPFlasher-1.3.16-linux-x64-installer.run * install in MSP430Flasher (under home) diff --git a/SciTEDirectory.properties b/SciTEDirectory.properties index efd288c..6889387 100644 --- a/SciTEDirectory.properties +++ b/SciTEDirectory.properties @@ -1,91 +1,108 @@ -# SciTEDirectoriy.properties +# SciTEDirectory.properties # For Windows, place in your directory project folder # Documentation at http://www.scintilla.org/SciTEDoc.html -# Globals -buffers.zorder.switching=1 +# # Globals +# +# PLAT_WIN=1 +# PLAT_GTK=0 +# position.maximize=1 +# +# save.session=1 +# save.recent=1 +# save.session=1 +# session.bookmarks=1 +# +# buffers.zorder.switching=1 +# properties.directory.enable=1 +# check.if.already.open=1 + + +# +# # Window sizes and visibility +# if PLAT_WIN +# position.left=-1 +# position.top=0 +# if PLAT_GTK +# position.left=5 +# position.top=22 +# +# position.width=1000 +# position.height=768 +# position.maximize=1 +# #position.tile=1 +# #full.screen.hides.menu=1 +# minimize.to.tray=0 +# split.vertical=1 +# output.horizontal.size=400 +# output.vertical.size=600 +# output.initial.hide=1 +# #horizontal.scrollbar=0 +# #horizontal.scroll.width=10000 +# #horizontal.scroll.width.tracking=0 +# #output.horizontal.scrollbar=0 +# #output.horizontal.scroll.width=10000 +# #output.horizontal.scroll.width.tracking=0 +# #output.scroll=0 +# error.select.line=1 +# #end.at.last.line=0 +# tabbar.visible=1 +# #tabbar.hide.one=1 +# tabbar.multiline=0 +# toolbar.large=1 +# toolbar.visible=1 +# #toolbar.detachable=1 +# #toolbar.usestockicons=1 +# #menubar.detachable=1 +# #undo.redo.lazy=1 +# statusbar.visible=1 +# #fileselector.width=800 +# #fileselector.height=600 +# #fileselector.show.hidden=1 +# magnification=0 +# output.magnification=-4 +# +# # Sizes and visibility in edit pane +# line.margin.visible=1 +# line.margin.width=4 +# margin.width=16 +# fold.margin.width=0 +# #fold.margin.colour=#00FF00 +# #fold.margin.highlight.colour=#0000FF +# blank.margin.left=20 +# #blank.margin.right=4 +# buffered.draw=1 +# #two.phase.draw=0 +# use.palette=0 + + +# #Element styles +# +# #view.eol=1 +# #control.char.symbol=. +# caret.period=500 +# view.whitespace=0 +# view.indentation.whitespace=1 +# view.indentation.guides=0 +# view.indentation.examine=3 +# highlight.indentation.guides=1 +# caret.fore=#FF0000 +# #caret.additional.blinks=0 +# caret.width=3 +# caret.line.back=#222222 +# calltip.back=#FFF0FE -# Window sizes and visibility -#if PLAT_WIN -# position.left=-1 -# position.top=0 -#if PLAT_GTK -# position.left=5 -# position.top=22 -#position.width=-1 -#position.height=-1 -#position.maximize=1 -#position.tile=1 -#full.screen.hides.menu=1 -minimize.to.tray=0 -split.vertical=1 -output.horizontal.size=400 -output.vertical.size=600 -output.initial.hide=1 -#horizontal.scrollbar=0 -#horizontal.scroll.width=10000 -#horizontal.scroll.width.tracking=0 -#output.horizontal.scrollbar=0 -#output.horizontal.scroll.width=10000 -#output.horizontal.scroll.width.tracking=0 -#output.scroll=0 -error.select.line=1 -#end.at.last.line=0 -tabbar.visible=1 -#tabbar.hide.one=1 -tabbar.multiline=0 -toolbar.visible=1 -#toolbar.detachable=1 -#toolbar.usestockicons=1 -#menubar.detachable=1 -#undo.redo.lazy=1 -statusbar.visible=1 -#fileselector.width=800 -#fileselector.height=600 -#fileselector.show.hidden=1 -magnification=0 -output.magnification=-4 - -# Sizes and visibility in edit pane -line.margin.visible=1 -line.margin.width=4 -margin.width=16 -fold.margin.width=0 -#fold.margin.colour=#00FF00 -#fold.margin.highlight.colour=#0000FF -blank.margin.left=20 -#blank.margin.right=4 -buffered.draw=1 -#two.phase.draw=0 -use.palette=0 - - -#Element styles - - -#view.eol=1 -#control.char.symbol=. -caret.period=500 -view.whitespace=0 -view.indentation.whitespace=1 -view.indentation.guides=0 -view.indentation.examine=3 -highlight.indentation.guides=1 -caret.fore=#FF0000 -#caret.additional.blinks=0 -caret.width=3 -caret.line.back=#222222 -calltip.back=#FFF0FE edge.column=80 edge.mode=1 edge.colour=#404040 + braces.check=1 braces.sloppy=1 # black background -selection.fore=#000000 -selection.alpha=256 -selection.back=#808080 +selection.fore=#FFFFFF +#selection.alpha=256 +selection.back=#808080A0 #selection.additional.fore=#0000A0 #selection.additional.back=#000080 #selection.additional.alpha=20 @@ -108,11 +125,6 @@ selection.back=#808080 #indicators.under=1 -# Scripting -ext.lua.startup.script=$(SciteUserHome)/SciTEStartup.lua -ext.lua.auto.reload=1 -#ext.lua.reset=1 - # Checking are.you.sure=1 @@ -123,14 +135,13 @@ load.on.activate=1 #save.on.deactivate=1 are.you.sure.on.reload=1 reload.preserves.undo=1 -check.if.already.open=1 +#check.if.already.open=1 #temp.files.sync.load=1 default.file.ext=.txt #source.default.extensions=.h|.cxx|.bat title.full.path=1 title.show.buffers=1 pathbar.visible=1 -#save.session=1 #save.recent=1 #save.session=1 #session.bookmarks=1 @@ -236,13 +247,13 @@ caret.policy.yjumps=0 #visible.policy.lines=4 #time.commands=1 #caret.sticky=1 -properties.directory.enable=1 +#properties.directory.enable=1 # Status Bar statusbar.number=4 -statusbar.text.2=\ -li=$(LineNumber) co=$(ColumnNumber) $(OverType) ($(EOLMode)) $(FileAttr) statusbar.text.1=\ +li=$(LineNumber) co=$(ColumnNumber) $(OverType) ($(EOLMode)) $(FileAttr) +statusbar.text.2=\ $(BufferLength) chars in $(NbOfLines) lines. Sel: $(SelHeight) lines, $(SelLength) chars. statusbar.text.3=\ Now is: Date=$(CurrentDate) Time=$(CurrentTime) @@ -250,56 +261,55 @@ statusbar.text.4=\ $(FileNameExt) : $(FileDate) — $(FileTime) | $(FileAttr) if PLAT_WIN - command.scite.help="https://www.scintilla.org/SciTEDoc.html" - command.scite.help.subsystem=2 + command.scite.help=C:\Program Files\SRWare Iron\iron.exe "C:\Program Files\SciTE\SciTEDoc.html" + command.scite.help.subsystem=2 if PLAT_GTK - command.print.*=a2ps "$(FileNameExt)" - command.scite.help=file://$(SciteDefaultHome)/SciTEDoc.html - -# Internationalisation -# Japanese input code page 932 and ShiftJIS character set 128 -#code.page=932 -#character.set=128 -# Unicode -#code.page=65001 -code.page=0 -#character.set=204 -# Required for Unicode to work on GTK+: -#LC_CTYPE=en_US.UTF-8 -if PLAT_GTK - output.code.page=65001 -if PLAT_MAC - output.code.page=65001 - -# Export -#export.keep.ext=1 -export.html.wysiwyg=1 -#export.html.tabs=1 -#export.html.folding=1 -export.html.styleused=1 -export.html.title.fullpath=1 -#export.rtf.tabs=1 -#export.rtf.font.face=Arial -#export.rtf.font.size=9 -#export.rtf.tabsize=8 -#export.rtf.wysiwyg=0 -#export.tex.title.fullpath=1 -# Magnification (added to default screen font size) -export.pdf.magnification=-2 -# Font: Courier, Helvetica or Times (Courier line-wraps) -export.pdf.font=Courier -# Page size (in points): width, height -# E.g. Letter 612,792; A4 595,842; maximum 14400,14400 -#export.pdf.pagesize=595,842 -export.pdf.pagesize=842,595 -# Margins (in points): left, right, top, bottom -export.pdf.margins=28,28,28,28 -export.xml.collapse.spaces=1 -export.xml.collapse.lines=1 + command.print.*=a2ps "$(FileNameExt)" + command.scite.help=xdg-open "file://$(SciteDefaultHome)/SciTEDoc.html" + +# # Internationalisation +# # Japanese input code page 932 and ShiftJIS character set 128 +# #code.page=932 +# #character.set=128 +# # Unicode +# #code.page=65001 +# code.page=0 +# #character.set=204 +# # Required for Unicode to work on GTK+: +# #LC_CTYPE=en_US.UTF-8 +# if PLAT_GTK +# output.code.page=65001 +# if PLAT_MAC +# output.code.page=65001 + +# # Export +# #export.keep.ext=1 +# export.html.wysiwyg=1 +# #export.html.tabs=1 +# #export.html.folding=1 +# export.html.styleused=1 +# export.html.title.fullpath=1 +# #export.rtf.tabs=1 +# #export.rtf.font.face=Arial +# #export.rtf.font.size=9 +# #export.rtf.tabsize=8 +# #export.rtf.wysiwyg=0 +# #export.tex.title.fullpath=1 +# # Magnification (added to default screen font size) +# export.pdf.magnification=0 +# # Font: Courier, Helvetica or Times (Courier line-wraps) +# export.pdf.font=Courier +# # Page size (in points): width, height +# # E.g. Letter 612,792; A4 595,842; maximum 14400,14400 +# export.pdf.pagesize=595,842 +# # Margins (in points): left, right, top, bottom +# export.pdf.margins=56,28,28,28 +# export.xml.collapse.spaces=1 +# export.xml.collapse.lines=1 # Define values for use in the imported properties files chars.alpha=abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ -chars.numeric=0123456789ABCDEFabcdefx +chars.numeric=0123456789ABCDEFabcdef chars.accented=ŠšŒœŸÿÀàÁáÂâÃãÄäÅåÆæÇçÈèÉéÊêËëÌìÍíÎîÏïÐðÑñÒòÓóÔôÕõÖØøÙùÚúÛûÜüÝýÞþßö # This is a better set for Russian: #chars.accented=ÀàÁáÂâÃãÄäÅ娸ÆæÇçÈèÉéÊêËëÌìÍíÎîÏïÐðÑñÒòÓóÔôÕõÖö×÷ØøÙùÚúÛûÜüÝýÞþßÿ @@ -383,51 +393,49 @@ $(filter.web)\ #save.filter=$(open.filter) # Give symbolic names to the set of fonts used in the standard styles. -if PLAT_WIN - font.base=font:Lucida Console,size:10 - font.small=font:Lucida Console,size:10 - font.comment=font:Lucida Console,size:10 - font.code.comment.box=$(font.comment) - font.code.comment.line=$(font.comment) - font.code.comment.doc=$(font.comment) - font.code.comment.nested=$(font.comment) - font.text=font:Lucida Console,size:10 - font.text.comment=font:Lucida Console,size:10 - font.embedded.base=font:Lucida Console,size:10 - font.embedded.comment=font:Lucida Console,size:10 - font.monospace=font:Lucida Console,size:10 - font.vbs=font:Lucida Sans Unicode,size:10 - -if PLAT_GTK - font.base=font:Bitstream Vera Sans Mono,size:10 - font.small=font:Bitstream Vera Sans Mono,size:10 - font.comment=font:Bitstream Vera Sans Mono,size:10 - font.code.comment.box=$(font.comment) - font.code.comment.line=$(font.comment) - font.code.comment.doc=$(font.comment) - font.code.comment.nested=$(font.comment) - font.text=font:Bitstream Vera Sans Mono,size:10 - font.text.comment=font:Bitstream Vera Sans Mono,size:10 - font.embedded.base=font:Bitstream Vera Sans Mono,size:10 - font.embedded.comment=font:Bitstream Vera Sans Mono,size:10 - font.monospace=font:Bitstream Vera Sans Mono,size:10 - font.vbs=font:Bitstream Vera Sans Mono,size:10 - -if PLAT_MAC - font.base=font:Verdana,size:12 - font.small=font:Verdana,size:10 - font.comment=font:Georgia,size:13 - font.code.comment.box=$(font.comment) - font.code.comment.line=$(font.comment) - font.code.comment.doc=$(font.comment) - font.code.comment.nested=$(font.comment) - font.text=font:Times New Roman,size:13 - font.text.comment=font:Verdana,size:11 - font.embedded.base=font:Verdana,size:11 - font.embedded.comment=font:Comic Sans MS,size:10 - font.monospace=font:Courier New,size:12 - font.vbs=font:Lucida Sans Unicode,size:12 - font.js=$(font.comment) +#if PLAT_WIN +# font.base=font:Lucida Console,size:10 +# font.small=font:Lucida Console,size:10 +# font.comment=font:Lucida Console,size:10 +# font.code.comment.box=$(font.comment) +# font.code.comment.line=$(font.comment) +# font.code.comment.doc=$(font.comment) +# font.code.comment.nested=$(font.comment) +# font.text=font:Lucida Console,size:10 +# font.text.comment=font:Lucida Console,size:10 +# font.embedded.base=font:Lucida Console,size:10 +# font.embedded.comment=font:Lucida Console,size:10 +# font.monospace=font:Lucida Console,size:10 +# font.vbs=font:Lucida Sans Unicode,size:10 +#if PLAT_GTK +# font.base=font:Bitstream Vera Sans Mono,size:10 +# font.small=font:Bitstream Vera Sans Mono,size:10 +# font.comment=font:Bitstream Vera Sans Mono,size:10 +# font.code.comment.box=$(font.comment) +# font.code.comment.line=$(font.comment) +# font.code.comment.doc=$(font.comment) +# font.code.comment.nested=$(font.comment) +# font.text=font:Bitstream Vera Sans Mono,size:10 +# font.text.comment=font:Bitstream Vera Sans Mono,size:10 +# font.embedded.base=font:Bitstream Vera Sans Mono,size:10 +# font.embedded.comment=font:Bitstream Vera Sans Mono,size:10 +# font.monospace=font:Bitstream Vera Sans Mono,size:10 +# font.vbs=font:Bitstream Vera Sans Mono,size:10 +#if PLAT_MAC +# font.base=font:Verdana,size:12 +# font.small=font:Verdana,size:10 +# font.comment=font:Georgia,size:13 +# font.code.comment.box=$(font.comment) +# font.code.comment.line=$(font.comment) +# font.code.comment.doc=$(font.comment) +# font.code.comment.nested=$(font.comment) +# font.text=font:Times New Roman,size:13 +# font.text.comment=font:Verdana,size:11 +# font.embedded.base=font:Verdana,size:11 +# font.embedded.comment=font:Comic Sans MS,size:10 +# font.monospace=font:Courier New,size:12 +# font.vbs=font:Lucida Sans Unicode,size:12 +# font.js=$(font.comment) # Old GTK+ font settings are faster but not antialiased #~ font.base=font:lucidatypewriter,size:12 @@ -443,58 +451,59 @@ if PLAT_MAC #~ font.monospace=font:courier,size:12 #~ font.vbs=font:new century schoolbook,size:12 -# Give symbolic names to the set of colours used in the standard styles. -colour.code.comment.box=fore:#00FF00 -colour.code.comment.line=fore:#00FF00 -colour.code.comment.doc=fore:#3F703F -colour.code.comment.nested=fore:#A0C0A0 -colour.text.comment=fore:#0000FF,back:#FFFFFF -colour.other.comment=fore:#00FF00 -colour.embedded.comment=back:#E0EEFF -colour.embedded.js=back:#F0F0FF -colour.notused=back:#FF0000 -#couleur des nombres -colour.number=fore:#FF00FF -#couleur des instructions du langage -colour.keyword=fore:#FF0000 -#couleur chaînes entre guillemets -colour.string=fore:#00FFFF -colour.char=fore:#7F7F7F -colour.operator=fore:#00FF00 -colour.preproc=fore:#FF7F00 -colour.error=fore:#FFFF00,back:#FF0000 - -# Global default styles for all languages -# Default style, black background -style.*.32=back:#000000,fore:#FFFFFF,font:Lucida Console,size:10 -# Line number -style.*.33=back:#404040,$(font.base)) -# Brace highlight -style.*.34=back:#222222,fore:#8080FF,bold -# Brace incomplete highlight -style.*.35=back:#222222,fore:#FF0000,bold -# Control characters -style.*.36= -# Indentation guides -style.*.37=fore:#C0C0C0,back:#FFFFFF - -# Printing - only works on Windows -if PLAT_WIN - #print.colour.mode=1 - print.magnification=-1 - # Setup: left, right, top, bottom margins, in local units: - # hundredths of millimeters or thousandths of inches - print.margins=2000,1000,1000,1000 - # Header/footer: - # && = &; &p = current page - # &f = file name; &F = full path - # &d = file date; &D = current date - # &t = file time; &T = full time - print.header.format=$(FileNameExt) — Printed on $(CurrentDate), $(CurrentTime) — Page $(CurrentPage) - print.footer.format=$(FilePath) — File date: $(FileDate) — File time: $(FileTime) - # Header/footer style - print.header.style=font:Arial,size:12,bold - print.footer.style=font:Arial Narrow,size:10,italics +## Give symbolic names to the set of colours used in the standard styles. +#colour.code.comment.box=fore:#00FF00 +#colour.code.comment.line=fore:#00FF00 +#colour.code.comment.doc=fore:#3F703F +#colour.code.comment.nested=fore:#A0C0A0 +#colour.text.comment=fore:#0000FF,back:#FFFFFF +#colour.other.comment=fore:#00FF00 +#colour.embedded.comment=back:#E0EEFF +#colour.embedded.js=back:#F0F0FF +#colour.notused=back:#FF0000 +##couleur des nombres +#colour.number=fore:#FF00FF +##couleur des instructions du langage +#colour.keyword=fore:#FF0000 +##couleur chaînes entre guillemets +#colour.string=fore:#00FFFF +#colour.char=fore:#7F7F7F +#colour.operator=fore:#00FF00 +#colour.preproc=fore:#FF7F00 +#colour.error=fore:#FFFF00,back:#FF0000 +# +# command or return status +## Global default styles for all languages +## Default style, black background +#style.*.32=back:#000000,fore:#FFFFFF,font:Lucida Console,size:10 +## Line number +#style.*.33=back:#404040,$(font.base)) +## Brace highlight +#style.*.34=back:#222222,fore:#8080FF,bold +## Brace incomplete highlight +#style.*.35=back:#222222,fore:#FF0000,bold +## Control characters +#style.*.36= +## Indentation guides +#style.*.37=fore:#C0C0C0,back:#FFFFFF + +## Printing - only works on Windows +#if PLAT_WIN +# #print.colour.mode=1 +# print.magnification=-1 +# # Setup: left, right, top, bottom margins, in local units: +# # hundredths of millimeters or thousandths of inches +# print.margins=2000,1000,1000,1000 +# # Header/footer: +# # && = &; &p = current page +# # &f = file name; &F = full path +# # &d = file date; &D = current date +# # &t = file time; &T = full time +# print.header.format=$(FileNameExt) — Printed on $(CurrentDate), $(CurrentTime) — Page $(CurrentPage) +# print.footer.format=$(FilePath) — File date: $(FileDate) — File time: $(FileTime) +# # Header/footer style +# print.header.style=font:Arial,size:12,bold +# print.footer.style=font:Arial Narrow,size:10,italics # Warnings - only works on Windows and needs to be pointed at files on machine #if PLAT_WIN @@ -524,12 +533,74 @@ if PLAT_MAC menu.language=\ Text|txt|Shift+F11|\ +#Ada|ads||\ +#Apache Confi&g|conf||\ +Assembler|asm||\ +#ASN.1|asn1||\ +#Avenue|ave||\ +#Baan|bc||\ &Batch|bat||\ +#Bullant|ant||\ +#&C / C++|c||\ +#CMake|cmake||\ +#C&#|cs||\ +#COBOL|cob||\ +#Csound|orc||\ +#CSS|css||\ +#D|d||\ &Difference|diff||\ +#&Eiffel|e||\ +#Erlang|erl||\ &Errorlist|err||\ +#FlagShip|prg||\ +Forth|forth||\ +&Fortran|f90||\ +#Gap|g||\ +#Haskell|hs||\ H&ypertext|html|F12|\ +#&InnoSetup|iss||\ +#&Java|java||\ +#Java&Script|js||\ +#&Kix|kix||\ +#Lisp|lisp||\ +#Lot|lot||\ +#Lout|lt||\ +#Lu&a|lua||\ +#Matlab|m.matlab||\ &Makefile|mak|Ctrl+Shift+F11|\ +#MetaPost|mp||\ +#MMIXAL|mms||\ +#Modula-3|m3||\ +#&nnCron crontab|tab||\ +#NSIS|nsis||\ +#Objective Caml|ml||\ +#Octave|m.octave||\ +#Opal|impl||\ +#Pascal|pas||\ +#Pe&rl|pl||\ +#P&HP|php||\ +#P&LSQL|spec||\ +#P&ostScript|ps||\ +#P&OV-Ray SDL|pov||\ +#PowerShell|ps1||\ +#PowerPro|powerpro||\ &Properties|properties||\ +#Pytho&n|py||\ +#R|R||\ +#Reso&urce|rc||\ +#Ruby|rb||\ +#Shell|sh||\ +#S&QL|sql||\ +#Specman|e||\ +#&TCL|tcl||\ +#TeX|tex||\ +#&txt2tags|t2t||\ +#&VB|vb||\ +#VBScr&ipt|vbs||\ +#Verilog|v||\ +#VHDL|vhd||\ +#&XML|xml|$(keyXML)|\ +#YAML|yaml|| # User defined key commands user.shortcuts=\ @@ -545,49 +616,30 @@ Ctrl+PageDown|IDM_NEXTFILE| #Next File|IDM_NEXTFILE|\ #Prev File|IDM_PREVFILE| -if PLAT_WIN - import \config\asm - import \config\forth - import \config\fortran - import \config\hex - import \config\others -if PLAT_GTK -FF=$HOME/CloudStation/projets/msp430 -export FF -PATH=/usr/local/MSPFlasher:$PATH -export PATH -# import /home/thoorens/CloudStation/projets/msp430/config/asm -# import /home/thoorens/CloudStation/projets/msp430/config/forth -# import /home/thoorens/CloudStation/projets/msp430/config/fortran -# import /home/thoorens/CloudStation/projets/msp430/config/hex -# import /home/thoorens/CloudStation/projets/msp430/config/others - - - +#if PLAT_WIN +import A:\projets\msp430\config\asm +import A:\projets\msp430\config\forth +import A:\projets\msp430\config\fortran +import A:\projets\msp430\config\hex +import A:\projets\msp430\config\others import Z:\config\asm import Z:\config\forth import Z:\config\fortran import Z:\config\hex import Z:\config\others +#if PLAT_GTK import /home/thoorens/CloudStation/projets/msp430/config/asm import /home/thoorens/CloudStation/projets/msp430/config/forth import /home/thoorens/CloudStation/projets/msp430/config/fortran import /home/thoorens/CloudStation/projets/msp430/config/hex import /home/thoorens/CloudStation/projets/msp430/config/others -# Error list styles - -style.errorlist.32=fore:#B0B000,$(font.small) -# Default -style.errorlist.0=fore:#FFFFFF -# Microsoft Error -style.errorlist.3=fore:#0080FF -# command or return status -style.errorlist.4=fore:#FF00FF - -# Text matched with find in files and message part of GCC errors -style.errorlist.21=fore:#FF0000 +import /home/jean_mi/CloudStation/projets/msp430/config/asm +import /home/jean_mi/CloudStation/projets/msp430/config/forth +import /home/jean_mi/CloudStation/projets/msp430/config/fortran +import /home/jean_mi/CloudStation/projets/msp430/config/hex +import /home/jean_mi/CloudStation/projets/msp430/config/others diff --git a/binaries/CHIPSTICK_FR2433_16MHz_115200.txt b/binaries/CHIPSTICK_FR2433_16MHz_115200.txt new file mode 100644 index 0000000..efa21d8 --- /dev/null +++ b/binaries/CHIPSTICK_FR2433_16MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A0 19 +CA C6 7E C5 84 C5 54 C5 3A C7 28 D7 E0 CF 9A CF +9A CF B0 C6 6E C7 36 C7 3C 21 E0 20 8E C9 B6 C4 +C4 C4 AA C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +3A C7 28 D7 E0 CF 9A CF 9A CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AE C6 B2 49 +6C C7 B2 49 34 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 54 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3A C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 B4 C8 AC C4 52 C5 7C C7 1E C4 04 1B +5B 37 6D 00 9E C7 9E C7 1E C4 04 1B 5B 30 6D 00 +9E C7 EA CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 7C C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 9E C7 02 CA 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9E C7 0A C4 40 FF 32 C4 +CA C8 CE C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 10 00 00 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 +E0 20 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 +26 02 F2 40 FD 00 22 02 E2 D2 24 02 F2 40 A5 00 +A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 +60 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 F2 C3 +82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 39 40 +80 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 C4 +86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 B0 C6 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +0E C7 3C 40 1A C7 5D 15 9B 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D2 22 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 10 C7 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 36 C7 30 12 4C C7 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C2 22 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 D6 C6 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 6E C7 08 4E +3E 4F C7 3F 64 C7 08 45 43 48 4F 00 B2 40 C2 48 +08 C7 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 08 C7 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE C7 29 4F 8F 4E 00 00 7E 49 DE 3F B0 C7 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2E C7 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A C4 00 00 CE C8 C0 C7 +12 CA CC CC B0 C4 3C C8 14 C4 06 5B 54 48 45 4E +5D 00 C4 C7 1A C8 E0 C7 FE C7 14 C4 06 5B 45 4C +53 45 5D 00 C4 C7 2C C8 E0 C7 FC C7 1E C4 04 5B +49 46 5D 00 C4 C7 FE C7 B2 C4 FC C7 1E C4 05 0D +6B 6F 20 0A 9E C7 9A C4 84 C4 B2 C4 FE C7 EC C7 +0D 5B 54 48 45 4E 5D 00 30 4D 50 C8 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C C8 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 C7 12 CA 7A CA +1E CC 8E C9 6C C8 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 C7 12 CA 7A CA 9E C8 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D A4 C6 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A C4 1E C4 7C CC 0A C4 22 00 12 CA +12 C9 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 86 C7 05 2E 22 00 0D 12 84 12 +FC C8 0A C4 9E C7 7C CC 8E C9 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D F8 C8 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 4A C9 04 23 53 00 0D 12 +84 12 4C C9 86 C9 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 C9 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 76 C7 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 C9 C0 C7 +AE C9 7E C9 AA C8 BC C9 98 C9 9E C7 8E C9 28 C9 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 CA 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 84 CB +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C C9 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 C4 C0 C7 12 CA B0 C4 56 CD 7A CA 40 CC +0A 4E 3E 4F 3D 40 5A CC 6D 27 3D 40 34 CC 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 5C CC 3E 4F 3D 40 +34 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 CE 2A 3C 24 CC 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7A CC 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 C9 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC C8 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E C4 02 0D 0A 00 9E C7 94 C4 2E CC BC C8 +E6 C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 C5 32 C4 0A C4 40 FF EE C8 1E C4 09 46 52 41 +4D 20 66 75 6C 6C 08 C5 B2 C4 F2 CC DC CC 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC C8 0A C4 08 C5 +7C CC 8E C9 0C CA 02 27 0D 12 84 12 C0 C7 12 CA +7A CA B0 C4 58 CD 20 C9 64 CC 86 C8 07 5B 27 5D +0D 12 84 12 48 CD 0A C4 0A C4 7C CC 7C CC 8E C9 +5C CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D D4 C8 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 C7 12 CA 7A CA B0 C4 58 CD E6 C8 +AC C4 B0 CD 0A C4 0A C4 7C CC 7C CC 0A C4 7C CC +7C CC 8E C9 00 00 02 3A 30 12 06 CE 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 C0 C7 12 CA CE CD 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 C5 72 CD 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A C4 8E C9 7C CC 18 CE 74 CD 8E C9 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D C6 CC 0C 43 52 45 41 54 45 00 B0 12 +BC CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 C7 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 CD 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 CE 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 CE +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 48 CD +D2 CE 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 CD +0A C4 D4 CE 7C CC 8E C9 66 CE 08 43 4F 44 45 00 +B0 12 BC CD A2 82 C8 21 61 3C A8 C9 0E 48 44 4E +43 4F 44 45 B2 40 C0 CF CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 CE 1E CF 3D 41 +92 42 D0 21 CC 21 5D 3C EA CE 0E 43 4F 44 45 4E +4E 4D 30 12 F4 CE B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FC CE 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 88 CF B2 40 9A CF D0 21 82 4E +CE 21 30 40 20 C9 85 12 86 CF 86 CD 2E CD 18 D0 +2A CF 80 CE CA C9 74 CA 46 CD 6E CF C0 CE 9A CE +36 CE 8E CC A2 D0 CC CA 00 00 00 00 85 12 86 CF +1C D7 A0 D5 00 D7 C8 D4 24 D5 72 D5 4E D6 5A D6 +EA D3 0E D5 00 00 00 00 5C CF DA D2 00 00 76 D6 +BA CF B2 40 9A CF CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 EE CF 30 4D 00 D0 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 EE CF 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 08 C6 FE FF 29 83 B9 40 F2 C5 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E4 FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 CF 82 43 4A 18 +C7 3F 94 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 C0 C7 12 CA 7A CA AC C4 C0 D0 B4 C8 54 CC +C2 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 BC CD BA 40 +85 12 FC FF BA 40 92 D0 FE FF 28 83 8A 48 00 00 +BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 12 CA 7A CA AC C4 2C D1 0C D1 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 D0 +00 00 01 20 3E 52 2E 83 21 53 30 41 24 CB AC C4 +34 D1 28 D1 36 D1 B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 FC D0 15 20 3E 40 +2B 00 B0 12 FC D0 06 20 3E 40 2D 00 B0 12 FC D0 +92 83 C6 21 0E 12 1E 41 02 00 84 12 12 CA 24 CB +AC C4 58 CD 76 D1 3E 51 3A 17 30 41 B0 12 3C D1 +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 12 CA 24 CB +AC C4 AE D1 A6 D1 3E 90 10 00 E6 2B 7C 2D B0 D1 +A2 41 C6 21 E1 3F 03 20 B0 12 94 D1 43 3C 7A 90 +23 00 24 20 B0 12 44 D1 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 D1 F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 D1 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 D1 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C D1 F2 3F 03 20 B0 12 94 D1 F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C D1 +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 7C CC +8E C9 0A C4 2C 00 72 D2 B6 D1 C0 C7 7C D2 54 D2 +C2 D2 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 D2 00 40 CE D2 0A 4D 4F 56 2E 42 +85 12 B2 D2 40 40 00 00 06 41 44 44 85 12 B2 D2 +00 50 E8 D2 0A 41 44 44 2E 42 85 12 B2 D2 40 50 +F4 D2 08 41 44 44 43 00 85 12 B2 D2 00 60 02 D3 +0C 41 44 44 43 2E 42 00 85 12 B2 D2 40 60 3A CF +08 53 55 42 43 00 85 12 B2 D2 00 70 20 D3 0C 53 +55 42 43 2E 42 00 85 12 B2 D2 40 70 2E D3 06 53 +55 42 85 12 B2 D2 00 80 3E D3 0A 53 55 42 2E 42 +85 12 B2 D2 40 80 4A D3 06 43 4D 50 85 12 B2 D2 +00 90 58 D3 0A 43 4D 50 2E 42 85 12 B2 D2 40 90 +00 00 08 44 41 44 44 00 85 12 B2 D2 00 A0 72 D3 +0C 44 41 44 44 2E 42 00 85 12 B2 D2 40 A0 A0 D2 +06 42 49 54 85 12 B2 D2 00 B0 90 D3 0A 42 49 54 +2E 42 85 12 B2 D2 40 B0 9C D3 06 42 49 43 85 12 +B2 D2 00 C0 AA D3 0A 42 49 43 2E 42 85 12 B2 D2 +40 C0 B6 D3 06 42 49 53 85 12 B2 D2 00 D0 C4 D3 +0A 42 49 53 2E 42 85 12 B2 D2 40 D0 00 00 06 58 +4F 52 85 12 B2 D2 00 E0 DE D3 0A 58 4F 52 2E 42 +85 12 B2 D2 40 E0 10 D3 06 41 4E 44 85 12 B2 D2 +00 F0 F8 D3 0A 41 4E 44 2E 42 85 12 B2 D2 40 F0 +C0 C7 72 D2 B6 D1 18 D4 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 D3 06 52 52 43 85 12 +10 D4 00 10 2A D4 0A 52 52 43 2E 42 85 12 10 D4 +40 10 64 D3 08 53 57 50 42 00 85 12 10 D4 80 10 +36 D4 06 52 52 41 85 12 10 D4 00 11 52 D4 0A 52 +52 41 2E 42 85 12 10 D4 40 11 44 D4 06 53 58 54 +85 12 10 D4 80 11 00 00 08 50 55 53 48 00 85 12 +10 D4 00 12 78 D4 0C 50 55 53 48 2E 42 00 85 12 +10 D4 40 12 6C D4 08 43 41 4C 4C 00 85 12 10 D4 +80 12 1A 53 0E 4A 84 12 02 CA 1E C4 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 C5 96 D4 06 53 +3E 3D 86 12 00 38 BE D4 04 53 3C 00 86 12 00 34 +86 D4 06 30 3E 3D 86 12 00 30 D2 D4 04 30 3C 00 +86 12 00 30 0E CF 04 55 3C 00 86 12 00 2C E6 D4 +06 55 3E 3D 86 12 00 28 DC D4 06 30 3C 3E 86 12 +00 24 FA D4 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 80 D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 D4 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 5E D4 0A 42 45 47 49 4E 30 40 32 C4 +48 D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D 04 D4 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 D5 A8 C8 8E C9 +66 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 D5 +2A D5 8E C9 D6 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D C2 D5 06 42 +57 31 85 12 D4 D5 00 00 EE D5 06 42 57 32 85 12 +D4 D5 00 00 FA D5 06 42 57 33 85 12 D4 D5 00 00 +12 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 D6 00 00 +36 D6 06 46 57 32 85 12 10 D6 00 00 42 D6 06 46 +57 33 85 12 10 D6 00 00 B0 D5 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 CD +54 CC 8E C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 7C D2 0A C4 2C 00 12 CA 24 CB AC C4 58 CD +C0 C7 72 D2 54 D2 A8 D6 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 D6 08 52 52 43 4D 00 85 12 92 D6 +50 00 D6 D6 08 52 52 41 4D 00 85 12 92 D6 50 01 +E4 D6 08 52 4C 41 4D 00 85 12 92 D6 50 02 F2 D6 +08 52 52 55 4D 00 85 12 92 D6 50 03 04 D5 0A 50 +55 53 48 4D 85 12 92 D6 00 15 0E D7 08 50 4F 50 +4D 00 85 12 92 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 CA C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 08 C6 +q diff --git a/binaries/CHIPSTICK_FR2433_16MHz_4MBds.txt b/binaries/CHIPSTICK_FR2433_16MHz_4MBds.txt new file mode 100644 index 0000000..34e1696 --- /dev/null +++ b/binaries/CHIPSTICK_FR2433_16MHz_4MBds.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A0 19 +CA C6 7E C5 84 C5 54 C5 3A C7 28 D7 E0 CF 9A CF +9A CF B0 C6 6E C7 36 C7 3C 21 E0 20 8E C9 B6 C4 +C4 C4 AA C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +3A C7 28 D7 E0 CF 9A CF 9A CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AE C6 B2 49 +6C C7 B2 49 34 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 54 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3A C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 B4 C8 AC C4 52 C5 7C C7 1E C4 04 1B +5B 37 6D 00 9E C7 9E C7 1E C4 04 1B 5B 30 6D 00 +9E C7 EA CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 7C C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 9E C7 02 CA 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9E C7 0A C4 40 FF 32 C4 +CA C8 CE C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 10 00 00 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 +E0 20 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 +26 02 F2 40 FD 00 22 02 E2 D2 24 02 F2 40 A5 00 +A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 +60 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 F2 C3 +82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 39 40 +80 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 C4 +86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 B0 C6 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +0E C7 3C 40 1A C7 5D 15 9B 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D2 22 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 10 C7 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 36 C7 30 12 4C C7 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C2 22 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 D6 C6 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 6E C7 08 4E +3E 4F C7 3F 64 C7 08 45 43 48 4F 00 B2 40 C2 48 +08 C7 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 08 C7 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE C7 29 4F 8F 4E 00 00 7E 49 DE 3F B0 C7 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2E C7 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A C4 00 00 CE C8 C0 C7 +12 CA CC CC B0 C4 3C C8 14 C4 06 5B 54 48 45 4E +5D 00 C4 C7 1A C8 E0 C7 FE C7 14 C4 06 5B 45 4C +53 45 5D 00 C4 C7 2C C8 E0 C7 FC C7 1E C4 04 5B +49 46 5D 00 C4 C7 FE C7 B2 C4 FC C7 1E C4 05 0D +6B 6F 20 0A 9E C7 9A C4 84 C4 B2 C4 FE C7 EC C7 +0D 5B 54 48 45 4E 5D 00 30 4D 50 C8 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C C8 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 C7 12 CA 7A CA +1E CC 8E C9 6C C8 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 C7 12 CA 7A CA 9E C8 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D A4 C6 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A C4 1E C4 7C CC 0A C4 22 00 12 CA +12 C9 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 86 C7 05 2E 22 00 0D 12 84 12 +FC C8 0A C4 9E C7 7C CC 8E C9 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D F8 C8 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 4A C9 04 23 53 00 0D 12 +84 12 4C C9 86 C9 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 C9 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 76 C7 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 C9 C0 C7 +AE C9 7E C9 AA C8 BC C9 98 C9 9E C7 8E C9 28 C9 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 CA 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 84 CB +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C C9 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 C4 C0 C7 12 CA B0 C4 56 CD 7A CA 40 CC +0A 4E 3E 4F 3D 40 5A CC 6D 27 3D 40 34 CC 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 5C CC 3E 4F 3D 40 +34 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 CE 2A 3C 24 CC 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7A CC 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 C9 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC C8 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E C4 02 0D 0A 00 9E C7 94 C4 2E CC BC C8 +E6 C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 C5 32 C4 0A C4 40 FF EE C8 1E C4 09 46 52 41 +4D 20 66 75 6C 6C 08 C5 B2 C4 F2 CC DC CC 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC C8 0A C4 08 C5 +7C CC 8E C9 0C CA 02 27 0D 12 84 12 C0 C7 12 CA +7A CA B0 C4 58 CD 20 C9 64 CC 86 C8 07 5B 27 5D +0D 12 84 12 48 CD 0A C4 0A C4 7C CC 7C CC 8E C9 +5C CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D D4 C8 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 C7 12 CA 7A CA B0 C4 58 CD E6 C8 +AC C4 B0 CD 0A C4 0A C4 7C CC 7C CC 0A C4 7C CC +7C CC 8E C9 00 00 02 3A 30 12 06 CE 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 C0 C7 12 CA CE CD 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 C5 72 CD 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A C4 8E C9 7C CC 18 CE 74 CD 8E C9 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D C6 CC 0C 43 52 45 41 54 45 00 B0 12 +BC CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 C7 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 CD 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 CE 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 CE +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 48 CD +D2 CE 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 CD +0A C4 D4 CE 7C CC 8E C9 66 CE 08 43 4F 44 45 00 +B0 12 BC CD A2 82 C8 21 61 3C A8 C9 0E 48 44 4E +43 4F 44 45 B2 40 C0 CF CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 CE 1E CF 3D 41 +92 42 D0 21 CC 21 5D 3C EA CE 0E 43 4F 44 45 4E +4E 4D 30 12 F4 CE B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FC CE 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 88 CF B2 40 9A CF D0 21 82 4E +CE 21 30 40 20 C9 85 12 86 CF 86 CD 2E CD 18 D0 +2A CF 80 CE CA C9 74 CA 46 CD 6E CF C0 CE 9A CE +36 CE 8E CC A2 D0 CC CA 00 00 00 00 85 12 86 CF +1C D7 A0 D5 00 D7 C8 D4 24 D5 72 D5 4E D6 5A D6 +EA D3 0E D5 00 00 00 00 5C CF DA D2 00 00 76 D6 +BA CF B2 40 9A CF CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 EE CF 30 4D 00 D0 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 EE CF 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 08 C6 FE FF 29 83 B9 40 F2 C5 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E4 FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 CF 82 43 4A 18 +C7 3F 94 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 C0 C7 12 CA 7A CA AC C4 C0 D0 B4 C8 54 CC +C2 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 BC CD BA 40 +85 12 FC FF BA 40 92 D0 FE FF 28 83 8A 48 00 00 +BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 12 CA 7A CA AC C4 2C D1 0C D1 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 D0 +00 00 01 20 3E 52 2E 83 21 53 30 41 24 CB AC C4 +34 D1 28 D1 36 D1 B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 FC D0 15 20 3E 40 +2B 00 B0 12 FC D0 06 20 3E 40 2D 00 B0 12 FC D0 +92 83 C6 21 0E 12 1E 41 02 00 84 12 12 CA 24 CB +AC C4 58 CD 76 D1 3E 51 3A 17 30 41 B0 12 3C D1 +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 12 CA 24 CB +AC C4 AE D1 A6 D1 3E 90 10 00 E6 2B 7C 2D B0 D1 +A2 41 C6 21 E1 3F 03 20 B0 12 94 D1 43 3C 7A 90 +23 00 24 20 B0 12 44 D1 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 D1 F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 D1 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 D1 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C D1 F2 3F 03 20 B0 12 94 D1 F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C D1 +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 7C CC +8E C9 0A C4 2C 00 72 D2 B6 D1 C0 C7 7C D2 54 D2 +C2 D2 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 D2 00 40 CE D2 0A 4D 4F 56 2E 42 +85 12 B2 D2 40 40 00 00 06 41 44 44 85 12 B2 D2 +00 50 E8 D2 0A 41 44 44 2E 42 85 12 B2 D2 40 50 +F4 D2 08 41 44 44 43 00 85 12 B2 D2 00 60 02 D3 +0C 41 44 44 43 2E 42 00 85 12 B2 D2 40 60 3A CF +08 53 55 42 43 00 85 12 B2 D2 00 70 20 D3 0C 53 +55 42 43 2E 42 00 85 12 B2 D2 40 70 2E D3 06 53 +55 42 85 12 B2 D2 00 80 3E D3 0A 53 55 42 2E 42 +85 12 B2 D2 40 80 4A D3 06 43 4D 50 85 12 B2 D2 +00 90 58 D3 0A 43 4D 50 2E 42 85 12 B2 D2 40 90 +00 00 08 44 41 44 44 00 85 12 B2 D2 00 A0 72 D3 +0C 44 41 44 44 2E 42 00 85 12 B2 D2 40 A0 A0 D2 +06 42 49 54 85 12 B2 D2 00 B0 90 D3 0A 42 49 54 +2E 42 85 12 B2 D2 40 B0 9C D3 06 42 49 43 85 12 +B2 D2 00 C0 AA D3 0A 42 49 43 2E 42 85 12 B2 D2 +40 C0 B6 D3 06 42 49 53 85 12 B2 D2 00 D0 C4 D3 +0A 42 49 53 2E 42 85 12 B2 D2 40 D0 00 00 06 58 +4F 52 85 12 B2 D2 00 E0 DE D3 0A 58 4F 52 2E 42 +85 12 B2 D2 40 E0 10 D3 06 41 4E 44 85 12 B2 D2 +00 F0 F8 D3 0A 41 4E 44 2E 42 85 12 B2 D2 40 F0 +C0 C7 72 D2 B6 D1 18 D4 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 D3 06 52 52 43 85 12 +10 D4 00 10 2A D4 0A 52 52 43 2E 42 85 12 10 D4 +40 10 64 D3 08 53 57 50 42 00 85 12 10 D4 80 10 +36 D4 06 52 52 41 85 12 10 D4 00 11 52 D4 0A 52 +52 41 2E 42 85 12 10 D4 40 11 44 D4 06 53 58 54 +85 12 10 D4 80 11 00 00 08 50 55 53 48 00 85 12 +10 D4 00 12 78 D4 0C 50 55 53 48 2E 42 00 85 12 +10 D4 40 12 6C D4 08 43 41 4C 4C 00 85 12 10 D4 +80 12 1A 53 0E 4A 84 12 02 CA 1E C4 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 C5 96 D4 06 53 +3E 3D 86 12 00 38 BE D4 04 53 3C 00 86 12 00 34 +86 D4 06 30 3E 3D 86 12 00 30 D2 D4 04 30 3C 00 +86 12 00 30 0E CF 04 55 3C 00 86 12 00 2C E6 D4 +06 55 3E 3D 86 12 00 28 DC D4 06 30 3C 3E 86 12 +00 24 FA D4 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 80 D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 D4 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 5E D4 0A 42 45 47 49 4E 30 40 32 C4 +48 D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D 04 D4 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 D5 A8 C8 8E C9 +66 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 D5 +2A D5 8E C9 D6 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D C2 D5 06 42 +57 31 85 12 D4 D5 00 00 EE D5 06 42 57 32 85 12 +D4 D5 00 00 FA D5 06 42 57 33 85 12 D4 D5 00 00 +12 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 D6 00 00 +36 D6 06 46 57 32 85 12 10 D6 00 00 42 D6 06 46 +57 33 85 12 10 D6 00 00 B0 D5 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 CD +54 CC 8E C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 7C D2 0A C4 2C 00 12 CA 24 CB AC C4 58 CD +C0 C7 72 D2 54 D2 A8 D6 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 D6 08 52 52 43 4D 00 85 12 92 D6 +50 00 D6 D6 08 52 52 41 4D 00 85 12 92 D6 50 01 +E4 D6 08 52 4C 41 4D 00 85 12 92 D6 50 02 F2 D6 +08 52 52 55 4D 00 85 12 92 D6 50 03 04 D5 0A 50 +55 53 48 4D 85 12 92 D6 00 15 0E D7 08 50 4F 50 +4D 00 85 12 92 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 CA C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 08 C6 +q diff --git a/binaries/CHIPSTICK_FR2433_16MHz_I2C.txt b/binaries/CHIPSTICK_FR2433_16MHz_I2C.txt index 2b62606..4261f56 100644 --- a/binaries/CHIPSTICK_FR2433_16MHz_I2C.txt +++ b/binaries/CHIPSTICK_FR2433_16MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF E6 D7 F2 CF 34 01 -10 00 41 07 B6 C5 AA C4 B8 C5 8C C5 84 C6 E6 D7 -F2 CF 72 C6 82 C7 00 C7 DC C6 3C 21 50 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 03 +C4 C6 56 C5 56 C5 58 C5 44 C5 04 D7 BC CF 76 CF +76 CF B2 C6 36 C7 0E C7 3C 21 E0 20 6A C9 B6 C4 +C4 C4 86 C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 04 D7 BC CF 76 CF 76 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 70 C6 B2 49 80 C7 B2 49 FE C6 B2 49 DA C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 D0 C7 18 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 98 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C C7 90 C8 4C C7 -14 C4 04 1B 5B 30 6D 00 4C C7 18 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 -B0 12 8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 -07 0D 0A 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 0A C4 23 00 FC C6 C6 C8 14 C4 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C C7 0A C4 40 FF 28 C4 C4 C7 -90 C8 14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 -3A C4 7E C5 00 00 06 41 43 43 45 50 54 00 30 40 -72 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 -B7 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +83 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 C6 B2 49 +34 C7 B2 49 0C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 30 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 90 C8 AC C4 +42 C5 4E C7 1E C4 05 1B 5B 37 6D 40 7A C7 0A C4 +02 18 B2 C8 DE C9 7A C7 1E C4 04 1B 5B 30 6D 00 +7A C7 C6 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 4E C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 7A C7 0A C4 02 18 B2 C8 DE C9 0A C4 23 00 +32 C7 DE C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7A C7 0A C4 40 FF 32 C4 A6 C8 AA C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +10 00 00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +CC 01 31 40 E0 20 3F 40 80 20 B2 43 02 02 B2 D3 +06 02 D2 43 24 02 F2 D3 26 02 F2 40 FD 00 22 02 +F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 +B2 40 00 A5 60 01 B2 D0 10 00 86 01 B2 40 00 02 +88 01 F2 C3 82 01 F2 D0 0A 00 82 01 B2 40 E8 01 +84 01 39 40 80 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 B0 12 +D0 C4 80 C5 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 9E 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 +97 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC C6 2F 83 8F 4E -00 00 58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 -4C 05 30 4D 00 00 04 45 4D 49 54 00 30 40 00 C7 -08 4E 3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D -F6 C6 04 45 43 48 4F 00 B2 40 C2 48 0A C7 82 43 -DE 21 38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A C7 92 43 DE 21 -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE C6 6A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 -82 C7 0D 12 84 12 14 C4 02 0D 0A 00 4C C7 50 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 C6 01 40 -2E 4E 30 4D CE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 7A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 0A C8 02 23 53 00 0D 12 -84 12 0C C8 46 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 C8 3E C8 EE C4 7E C8 5A C8 4C C7 04 CC FC C6 -50 C8 2E C7 01 2E 0E 93 E3 37 38 43 E2 3F 78 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -4A CB 0A C4 22 00 1C C9 EA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -C4 C8 82 2E 22 00 0D 12 84 12 D4 C8 0A C4 4C C7 -4A CB 50 C8 FA C5 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 0E C7 58 43 +B0 12 46 C5 2F 83 8F 4E 00 00 92 B3 6C 05 FD 27 +1E 42 4C 05 B0 12 44 C5 30 4D 00 00 08 45 4D 49 +54 00 30 40 36 C7 08 4E 3E 4F A2 B3 6C 05 FD 27 +C2 48 4E 05 30 4D 2C C7 08 45 43 48 4F 00 B2 40 +C2 48 40 C7 38 40 05 00 B0 12 46 C5 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 40 C7 28 42 +F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 8A C7 +29 4F 8F 4E 00 00 7E 49 D4 3F 8C C7 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 83 22 F9 98 00 00 +80 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 77 22 9B 24 06 C7 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A C4 00 00 AA C8 9C C7 EE C9 A8 CC +B0 C4 18 C8 14 C4 06 5B 54 48 45 4E 5D 00 A0 C7 +F6 C7 BC C7 DA C7 14 C4 06 5B 45 4C 53 45 5D 00 +A0 C7 08 C8 BC C7 D8 C7 1E C4 04 5B 49 46 5D 00 +A0 C7 DA C7 B2 C4 D8 C7 1E C4 05 0D 6B 6F 20 0A +7A C7 9A C4 84 C4 B2 C4 DA C7 C8 C7 0D 5B 54 48 +45 4E 5D 00 30 4D 2C C8 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 38 C8 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 9C C7 EE C9 56 CA FA CB 6A C9 +48 C8 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 9C C7 EE C9 56 CA 7A C8 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D A6 C6 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 C5 05 53 22 00 82 43 C0 21 0D 12 84 12 +0A C4 1E C4 58 CC 0A C4 22 00 EE C9 EE C8 B2 40 +20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 +30 4D 60 C7 05 2E 22 00 0D 12 84 12 D8 C8 0A C4 +7A C7 58 CC 6A C9 00 00 04 3C 23 00 B2 40 B2 21 +B2 21 30 4D D4 C8 02 23 1B 42 BE 21 2C 4F 2F 83 +B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A +00 00 30 4D 26 C9 04 23 53 00 0D 12 84 12 28 C9 +62 C9 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 56 C9 +04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +70 C9 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 48 C7 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 1C C9 9C C7 8A C9 5A C9 +86 C8 98 C9 74 C9 7A C7 6A C9 04 C9 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 +C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D DC C9 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9E CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 48 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 04 CC 1C C9 C0 CB -9C 26 3D 40 C8 CB DE 3E CA CB 0A 4E 3E 4F 3D 40 -E4 CB 36 27 3D 40 BA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 E6 CB 3E 4F 3D 40 BA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 CD -CC 3F EE CB 86 12 20 00 D6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 7E C7 -BC C4 B4 CB B4 C7 E6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -EE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 2E CC 0A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 C8 0A C4 2A C5 4A CB 50 C8 7E C9 -01 27 0D 12 84 12 04 CC 1C C9 84 C9 34 C4 02 CC -50 C8 00 00 83 5B 27 5D 0D 12 84 12 82 CC 0A C4 -0A C4 4A CB 4A CB 50 C8 94 CC 81 5B 82 43 BE 21 -30 4D FC C7 01 5D B2 43 BE 21 30 4D B4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 CC 1C C9 84 C9 98 C7 -34 C4 02 CC E6 C7 34 C4 F6 CC 0A C4 0A C4 4A CB -4A CB 0A C4 4A CB 4A CB 50 C8 AA CC 01 3A 30 12 -46 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 04 CC -1C C9 14 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 FC CC 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 50 C8 4A CB 58 CD AC CC -50 C8 AA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D 94 CB 06 43 52 45 -41 54 45 00 B0 12 02 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC CD 04 43 4F 44 45 00 B0 12 02 CD -A2 82 C6 21 0D 12 84 12 F4 CF CE CF 50 C8 A4 CD -07 48 44 4E 43 4F 44 45 B2 40 D2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 CD -0E D0 2C D0 50 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 0E D0 2C D0 50 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F F0 CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -9C CF 4A CB AC CC E4 CD 50 C8 8A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 C8 C7 04 CC 1C C9 -9A CB 90 C7 34 C4 04 CF 9E C7 14 C4 06 5B 54 48 -45 4E 5D 00 76 CE DE CE 9A CE BC CE 50 C8 9E C7 -14 C4 06 5B 45 4C 53 45 5D 00 76 CE F4 CE 9A CE -BA CE 50 C8 14 C4 04 5B 49 46 5D 00 76 CE BC CE -3A C4 BA CE 72 C7 14 C4 05 0D 0A 6B 6F 20 4C C7 -BC C4 AC C4 3A C4 BC CE AA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 CC 1C C9 -84 C9 28 CF 50 C8 2E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 CF E0 C7 50 C8 60 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C CB -06 4D 41 52 4B 45 52 00 B0 12 02 CD BA 40 85 12 -FC FF BA 40 5E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 D8 C7 50 C8 85 12 A0 CF 68 CC D6 CD -12 C7 80 CC 54 CE D4 C6 70 CF 02 C9 98 D0 AC D0 -8C C8 16 C9 00 00 48 CF BE CC E4 C9 00 00 85 12 -A0 CF 5C D6 C2 D6 04 D6 12 D7 CA D5 00 00 96 D3 -00 00 DA D7 BE D7 2E D6 6C D6 A6 D4 00 00 00 00 -2E D7 CC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D A8 CF 26 D0 2C D0 3C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA CC 09 50 57 52 5F 53 54 41 54 45 85 12 34 D0 -E6 D7 D0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 D0 F3 3F 72 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 80 D0 30 4D 84 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A D1 FE FF 29 83 -B9 40 E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 02 C6 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 26 02 -F2 40 FD 00 22 02 F2 40 A5 00 A1 01 F2 40 10 00 -A0 01 D2 43 A1 01 B2 40 00 A5 60 01 B2 40 29 01 -80 01 B2 40 0B 00 82 01 B2 40 E9 01 84 01 39 40 -00 01 B2 D0 10 00 86 01 38 40 17 11 18 83 FE 23 -19 83 FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 -B0 12 F8 C4 00 C6 38 40 C0 21 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 -C4 21 84 12 1C C9 84 C9 E0 C7 34 C4 D6 D1 40 CA -34 C4 F0 D1 EA D1 D8 D1 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -F2 D1 B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1C C9 -84 C9 E0 C7 34 C4 0E D2 40 CA 34 C4 02 CC AA C7 -1C C9 40 CA 34 C4 02 CC 1A D2 3E 5F E7 3F 3E 40 -28 00 B0 12 BA D1 19 42 C6 21 A2 53 C6 21 89 4E -00 00 3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 -70 CD 1C 15 12 12 C4 21 92 53 C4 21 84 12 1C C9 -40 CA 34 C4 62 D2 58 D2 21 53 3E 90 10 00 C6 2B -7F 2D 64 D2 B2 41 C4 21 C1 3F 0D 12 84 12 04 CC -96 D1 74 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E -3E 4F 7A 90 23 00 27 20 92 53 C4 21 B0 12 BA D1 -3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 -3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 -3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 -3C 40 30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 -92 53 C4 21 B0 12 BA D1 ED 3F 7A 90 40 00 16 20 -3C 40 20 00 92 53 C4 21 B0 12 42 D2 0C 20 3C 50 -10 00 3E 40 2B 00 B0 12 42 D2 92 92 C0 21 C4 21 -02 24 92 53 C4 21 8E 10 0C 5E DA 3F B0 12 42 D2 -FA 23 3C 50 10 00 B0 12 1E D2 EF 3F 0C 43 1B 42 -C6 21 A2 53 C6 21 0D 12 84 12 04 CC 96 D1 40 D3 -FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 -C7 3F B0 12 42 D2 E0 23 3C 50 80 00 B0 12 1E D2 -DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 -00 13 4A CB 50 C8 0A C4 2C 00 6A D2 36 D3 80 D3 -09 4B 2E 4E 0E DC A2 3F 42 CE 03 4D 4F 56 85 12 -76 D3 00 40 8A D3 05 4D 4F 56 2E 42 85 12 76 D3 -40 40 00 00 03 41 44 44 85 12 76 D3 00 50 A4 D3 -05 41 44 44 2E 42 85 12 76 D3 40 50 B0 D3 04 41 -44 44 43 00 85 12 76 D3 00 60 BE D3 06 41 44 44 -43 2E 42 00 85 12 76 D3 40 60 64 D3 04 53 55 42 -43 00 85 12 76 D3 00 70 DC D3 06 53 55 42 43 2E -42 00 85 12 76 D3 40 70 EA D3 03 53 55 42 85 12 -76 D3 00 80 FA D3 05 53 55 42 2E 42 85 12 76 D3 -40 80 18 CE 03 43 4D 50 85 12 76 D3 00 90 14 D4 -05 43 4D 50 2E 42 85 12 76 D3 40 90 02 CE 04 44 -41 44 44 00 85 12 76 D3 00 A0 2E D4 06 44 41 44 -44 2E 42 00 85 12 76 D3 40 A0 20 D4 03 42 49 54 -85 12 76 D3 00 B0 4C D4 05 42 49 54 2E 42 85 12 -76 D3 40 B0 58 D4 03 42 49 43 85 12 76 D3 00 C0 -66 D4 05 42 49 43 2E 42 85 12 76 D3 40 C0 72 D4 -03 42 49 53 85 12 76 D3 00 D0 80 D4 05 42 49 53 -2E 42 85 12 76 D3 40 D0 00 00 03 58 4F 52 85 12 -76 D3 00 E0 9A D4 05 58 4F 52 2E 42 85 12 76 D3 -40 E0 CC D3 03 41 4E 44 85 12 76 D3 00 F0 B4 D4 -05 41 4E 44 2E 42 85 12 76 D3 40 F0 04 CC 6A D2 -D2 D4 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA -4F 3F 06 D4 03 52 52 43 85 12 CC D4 00 10 E4 D4 -05 52 52 43 2E 42 85 12 CC D4 40 10 F0 D4 04 53 -57 50 42 00 85 12 CC D4 80 10 FE D4 03 52 52 41 -85 12 CC D4 00 11 0C D5 05 52 52 41 2E 42 85 12 -CC D4 40 11 18 D5 03 53 58 54 85 12 CC D4 80 11 -00 00 04 50 55 53 48 00 85 12 CC D4 00 12 32 D5 -06 50 55 53 48 2E 42 00 85 12 CC D4 40 12 8C D4 -04 43 41 4C 4C 00 85 12 CC D4 80 12 1A 53 0E 4A -0D 12 84 12 C6 C8 14 C4 0D 6F 75 74 20 6F 66 20 -62 6F 75 6E 64 73 36 C5 26 D5 03 53 3E 3D 86 12 -00 38 7A D5 02 53 3C 00 86 12 00 34 40 D5 03 30 -3E 3D 86 12 00 30 8E D5 02 30 3C 00 86 12 00 30 -00 00 02 55 3C 00 86 12 00 2C A2 D5 03 55 3E 3D -86 12 00 28 98 D5 03 30 3C 3E 86 12 00 24 B6 D5 -02 30 3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 -C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D AC D5 -04 54 48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 -29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 -30 4D 3C D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 -00 3C 00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F -50 D5 05 42 45 47 49 4E 30 40 28 C4 E0 D5 05 55 -4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 -0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA -89 48 00 00 A2 53 C6 21 30 4D C0 D4 05 41 47 41 -49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 -4C 45 0D 12 84 12 CE D5 AA C7 50 C8 84 D5 06 52 -45 50 45 41 54 00 0D 12 84 12 62 D6 E6 D5 50 C8 -92 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F -98 42 C6 21 00 00 30 4D 22 D6 03 42 57 31 85 12 -90 D6 00 00 AA D6 03 42 57 32 85 12 90 D6 00 00 -B6 D6 03 42 57 33 85 12 90 D6 00 00 CE D6 3D 41 -1A 42 C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 -A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 -57 31 85 12 CC D6 00 00 EE D6 03 46 57 32 85 12 -CC D6 00 00 FA D6 03 46 57 33 85 12 CC D6 00 00 -06 D7 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 -00 3C 0D 12 84 12 82 CC DE CB 50 C8 00 00 05 3F -47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 -00 10 EF 27 3E E0 00 08 EC 3F 04 CC 96 D1 50 D7 -92 53 C4 21 3E 40 2C 00 84 12 1C C9 40 CA 34 C4 -02 CC 2C D3 66 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E -59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 -10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 -A6 3E 7E D6 04 52 52 43 4D 00 85 12 4A D7 50 00 -94 D7 04 52 52 41 4D 00 85 12 4A D7 50 01 A2 D7 -04 52 4C 41 4D 00 85 12 4A D7 50 02 B0 D7 04 52 -52 55 4D 00 85 12 4A D7 50 03 C0 D5 05 50 55 53 -48 4D 85 12 4A D7 00 15 CC D7 04 50 4F 50 4D 00 -85 12 4A D7 00 17 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 21 0C 4E 0E 43 1E 15 3D 40 60 CB 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +62 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 18 C9 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 C4 +9C C7 EE C9 B0 C4 32 CD 56 CA 1C CC 0A 4E 3E 4F +3D 40 36 CC 6D 27 3D 40 10 CC 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 38 CC 3E 4F 3D 40 10 CC 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +0E CE 2A 3C 00 CC 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D 56 CC 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 +00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D +92 C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D B8 C8 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E C4 +02 0D 0A 00 7A C7 94 C4 0A CC 98 C8 C2 C8 1E C4 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 32 C4 +0A C4 40 FF CA C8 1E C4 09 46 52 41 4D 20 66 75 +6C 6C 08 C5 B2 C4 CE CC B8 CC 0D 41 42 4F 52 54 +22 00 0D 12 84 12 D8 C8 0A C4 08 C5 58 CC 6A C9 +E8 C9 02 27 0D 12 84 12 9C C7 EE C9 56 CA B0 C4 +34 CD FC C8 40 CC 62 C8 07 5B 27 5D 0D 12 84 12 +24 CD 0A C4 0A C4 58 CC 58 CC 6A C9 38 CD 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +B0 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +9C C7 EE C9 56 CA B0 C4 34 CD C2 C8 AC C4 8C CD +0A C4 0A C4 58 CC 58 CC 0A C4 58 CC 58 CC 6A C9 +00 00 02 3A 30 12 E2 CD 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 9C C7 EE C9 AA CD 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 C5 +4E CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A C4 +6A C9 58 CC F4 CD 50 CD 6A C9 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +A2 CC 0C 43 52 45 41 54 45 00 B0 12 98 CD BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 74 C7 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 92 CD 0E 3A 4E 4F 4E 41 4D 45 30 12 +E2 CD 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 2C CE 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 24 CD AE CE 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 3C CD 0A C4 B0 CE +58 CC 6A C9 42 CE 08 43 4F 44 45 00 B0 12 98 CD +A2 82 C8 21 61 3C 84 C9 0E 48 44 4E 43 4F 44 45 +B2 40 9C CF CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 F4 CD FA CE 3D 41 92 42 D0 21 +CC 21 5D 3C C6 CE 0E 43 4F 44 45 4E 4E 4D 30 12 +D0 CE B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F D8 CE 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F 64 CF B2 40 76 CF D0 21 82 4E CE 21 30 40 +FC C8 85 12 62 CF 62 CD 0A CD F4 CF 06 CF 5C CE +A6 C9 50 CA 22 CD 4A CF 9C CE 76 CE 12 CE 6A CC +7E D0 A8 CA 00 00 00 00 85 12 62 CF F8 D6 7C D5 +DC D6 A4 D4 00 D5 4E D5 2A D6 36 D6 C6 D3 EA D4 +00 00 00 00 38 CF B6 D2 00 00 52 D6 96 CF B2 40 +76 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 CA CF +30 4D DC CF 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 CA CF 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 10 C6 FE FF 29 83 B9 40 FA C5 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 10 00 +3A 40 3A 18 B0 12 CE CF 82 43 4A 18 C7 3F 70 D0 +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 58 CD 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 9C C7 +EE C9 56 CA AC C4 9C D0 90 C8 30 CC 9E D0 3E 4F +3D 41 B2 41 C6 21 B0 12 98 CD BA 40 85 12 FC FF +BA 40 6E D0 FE FF 28 83 8A 48 00 00 BA 40 82 C4 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 EE C9 +56 CA AC C4 08 D1 E8 D0 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 6E D0 00 00 01 20 +3E 52 2E 83 21 53 30 41 00 CB AC C4 10 D1 04 D1 +12 D1 B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 D8 D0 15 20 3E 40 2B 00 B0 12 +D8 D0 06 20 3E 40 2D 00 B0 12 D8 D0 92 83 C6 21 +0E 12 1E 41 02 00 84 12 EE C9 00 CB AC C4 34 CD +52 D1 3E 51 3A 17 30 41 B0 12 18 D1 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 EE C9 00 CB AC C4 8A D1 +82 D1 3E 90 10 00 E6 2B 7C 2D 8C D1 A2 41 C6 21 +E1 3F 03 20 B0 12 70 D1 43 3C 7A 90 23 00 24 20 +B0 12 20 D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 20 D1 F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 6C D1 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 70 D1 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 58 D1 F2 3F +03 20 B0 12 70 D1 F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 58 D1 EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A C4 00 13 58 CC 6A C9 0A C4 +2C 00 4E D2 92 D1 9C C7 58 D2 30 D2 9E D2 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +8E D2 00 40 AA D2 0A 4D 4F 56 2E 42 85 12 8E D2 +40 40 00 00 06 41 44 44 85 12 8E D2 00 50 C4 D2 +0A 41 44 44 2E 42 85 12 8E D2 40 50 D0 D2 08 41 +44 44 43 00 85 12 8E D2 00 60 DE D2 0C 41 44 44 +43 2E 42 00 85 12 8E D2 40 60 16 CF 08 53 55 42 +43 00 85 12 8E D2 00 70 FC D2 0C 53 55 42 43 2E +42 00 85 12 8E D2 40 70 0A D3 06 53 55 42 85 12 +8E D2 00 80 1A D3 0A 53 55 42 2E 42 85 12 8E D2 +40 80 26 D3 06 43 4D 50 85 12 8E D2 00 90 34 D3 +0A 43 4D 50 2E 42 85 12 8E D2 40 90 00 00 08 44 +41 44 44 00 85 12 8E D2 00 A0 4E D3 0C 44 41 44 +44 2E 42 00 85 12 8E D2 40 A0 7C D2 06 42 49 54 +85 12 8E D2 00 B0 6C D3 0A 42 49 54 2E 42 85 12 +8E D2 40 B0 78 D3 06 42 49 43 85 12 8E D2 00 C0 +86 D3 0A 42 49 43 2E 42 85 12 8E D2 40 C0 92 D3 +06 42 49 53 85 12 8E D2 00 D0 A0 D3 0A 42 49 53 +2E 42 85 12 8E D2 40 D0 00 00 06 58 4F 52 85 12 +8E D2 00 E0 BA D3 0A 58 4F 52 2E 42 85 12 8E D2 +40 E0 EC D2 06 41 4E 44 85 12 8E D2 00 F0 D4 D3 +0A 41 4E 44 2E 42 85 12 8E D2 40 F0 9C C7 4E D2 +92 D1 F4 D3 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F AC D3 06 52 52 43 85 12 EC D3 00 10 +06 D4 0A 52 52 43 2E 42 85 12 EC D3 40 10 40 D3 +08 53 57 50 42 00 85 12 EC D3 80 10 12 D4 06 52 +52 41 85 12 EC D3 00 11 2E D4 0A 52 52 41 2E 42 +85 12 EC D3 40 11 20 D4 06 53 58 54 85 12 EC D3 +80 11 00 00 08 50 55 53 48 00 85 12 EC D3 00 12 +54 D4 0C 50 55 53 48 2E 42 00 85 12 EC D3 40 12 +48 D4 08 43 41 4C 4C 00 85 12 EC D3 80 12 1A 53 +0E 4A 84 12 DE C9 1E C4 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 C5 72 D4 06 53 3E 3D 86 12 +00 38 9A D4 04 53 3C 00 86 12 00 34 62 D4 06 30 +3E 3D 86 12 00 30 AE D4 04 30 3C 00 86 12 00 30 +EA CE 04 55 3C 00 86 12 00 2C C2 D4 06 55 3E 3D +86 12 00 28 B8 D4 06 30 3C 3E 86 12 00 24 D6 D4 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 5C D3 +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D CC D4 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +3A D4 0A 42 45 47 49 4E 30 40 32 C4 24 D5 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D E0 D3 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 EE D4 84 C8 6A C9 42 D5 0C 52 +45 50 45 41 54 00 0D 12 84 12 82 D5 06 D5 6A C9 +B2 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D 9E D5 06 42 57 31 85 12 +B0 D5 00 00 CA D5 06 42 57 32 85 12 B0 D5 00 00 +D6 D5 06 42 57 33 85 12 B0 D5 00 00 EE D5 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 EC D5 00 00 12 D6 06 46 +57 32 85 12 EC D5 00 00 1E D6 06 46 57 33 85 12 +EC D5 00 00 8C D5 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 24 CD 30 CC 6A C9 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 58 D2 +0A C4 2C 00 EE C9 00 CB AC C4 34 CD 9C C7 4E D2 +30 D2 84 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +E2 D5 08 52 52 43 4D 00 85 12 6E D6 50 00 B2 D6 +08 52 52 41 4D 00 85 12 6E D6 50 01 C0 D6 08 52 +4C 41 4D 00 85 12 6E D6 50 02 CE D6 08 52 52 55 +4D 00 85 12 6E D6 50 03 E0 D4 0A 50 55 53 48 4D +85 12 6E D6 00 15 EA D6 08 50 4F 50 4D 00 85 12 +6E D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -84 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 0A D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +C4 C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 10 C6 q diff --git a/binaries/CHIPSTICK_FR2433_16MHz_UART.txt b/binaries/CHIPSTICK_FR2433_16MHz_UART.txt deleted file mode 100644 index 52235ad..0000000 --- a/binaries/CHIPSTICK_FR2433_16MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF FC D7 04 D0 34 01 -10 00 41 33 94 C5 AA C4 DA C5 9C C5 96 C6 FC D7 -04 D0 7C C6 94 C7 26 C7 00 C7 3C 21 62 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 7A C6 B2 49 92 C7 B2 49 24 C7 B2 49 FE C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 D0 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E2 C7 34 C7 -14 C4 04 1B 5B 37 6D 00 5E C7 AA C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E C7 A2 C8 5E C7 14 C4 04 1B 5B 30 6D 00 -5E C7 2A CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D2 22 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C2 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 -B0 12 9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 -5E C7 D8 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E C7 0A C4 40 FF 28 C4 D6 C7 A2 C8 14 C4 0A 62 -79 74 65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 -06 41 43 43 45 50 54 00 30 40 7C C6 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 C6 3C 40 -D4 C6 5D 15 B5 3E 21 52 3A 17 58 42 0C 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 -FD 27 C2 48 0E 05 30 4D CA C6 2D 83 92 B3 1C 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -1C 05 FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 -DE 21 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 C7 -2F 83 8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 -1E 42 0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 C7 08 4E 3E 4F C8 3F 1C C7 04 45 -43 48 4F 00 B2 40 C2 48 C2 C6 82 43 DE 21 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 C6 -92 43 DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A C7 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 C7 7C C7 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 -30 40 94 C7 0D 12 84 12 14 C4 02 0D 0A 00 5E C7 -62 C8 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 C6 -01 40 2E 4E 30 4D E0 C7 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 21 B2 21 30 4D 8C C7 01 23 1B 42 -DC 21 2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 -18 42 B2 21 C8 4A 00 00 30 4D 1C C8 02 23 53 00 -0D 12 84 12 1E C8 58 C8 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C C8 02 23 3E 00 9F 42 B2 21 -00 00 3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 C7 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 C8 50 C8 EE C4 90 C8 6C C8 5E C7 16 CC -22 C7 62 C8 42 C7 01 2E 0E 93 E3 37 38 43 E2 3F -8A C8 82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 -14 C4 5C CB 0A C4 22 00 2E C9 FC C8 B2 40 20 00 -B4 21 6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 -30 4D D6 C8 82 2E 22 00 0D 12 84 12 E6 C8 0A C4 -5E C7 5C CB 62 C8 1A C6 04 57 4F 52 44 00 3C 40 -C0 21 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A -C4 21 1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 -D4 C4 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 -B0 CA 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 CA 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 3E 4F 30 4D 5A CB 87 4C -49 54 45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 -C6 21 A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 C8 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C C8 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC C4 16 CC 2E C9 -D2 CB 9C 26 3D 40 DA CB DE 3E DC CB 0A 4E 3E 4F -3D 40 F6 CB 36 27 3D 40 CC CB 1A E2 BE 21 B6 27 -0E 12 3E 4F 30 41 F8 CB 3E 4F 3D 40 CC CB BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 CD CC 3F 00 CC 86 12 20 00 E8 C7 05 41 4C 4C -4F 54 82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 -31 40 E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 -90 C7 BC C4 C6 CB C6 C7 F8 C7 14 C4 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF -28 C4 00 C8 14 C4 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A C5 3A C4 40 CC 1C CC 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 C8 0A C4 2A C5 5C CB 62 C8 -90 C9 01 27 0D 12 84 12 16 CC 2E C9 96 C9 34 C4 -14 CC 62 C8 00 00 83 5B 27 5D 0D 12 84 12 94 CC -0A C4 0A C4 5C CB 5C CB 62 C8 A6 CC 81 5B 82 43 -BE 21 30 4D 0E C8 01 5D B2 43 BE 21 30 4D C6 CC -81 5C 92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 CC 2E C9 96 C9 -AA C7 34 C4 14 CC F8 C7 34 C4 08 CD 0A C4 0A C4 -5C CB 5C CB 0A C4 5C CB 5C CB 62 C8 BC CC 01 3A -30 12 58 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 -16 CC 2E C9 26 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 -2A 52 82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 -18 42 B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 C5 0E CD 81 3B 82 93 -BE 21 97 27 0D 12 84 12 0A C4 62 C8 5C CB 6A CD -BE CC 62 C8 BC CB 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 21 F8 D0 80 00 00 00 30 4D A6 CB 06 43 -52 45 41 54 45 00 B0 12 14 CD BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE CD 04 43 4F 44 45 00 B0 12 -14 CD A2 82 C6 21 0D 12 84 12 06 D0 E0 CF 62 C8 -B6 CD 07 48 44 4E 43 4F 44 45 B2 40 E4 CF DA 21 -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A CD 20 D0 3E D0 62 C8 00 00 05 43 4F 4C 4F 4E -1A 42 C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 21 B2 43 BE 21 0D 12 84 12 20 D0 3E D0 -62 C8 00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 -C6 21 EB 3F 02 CE 85 48 49 32 4C 4F 0D 12 84 12 -28 C4 AE CF 5C CB BE CC F6 CD 62 C8 9C CD 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E CE 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A C4 00 00 DA C7 16 CC -2E C9 AC CB A2 C7 34 C4 16 CF B0 C7 14 C4 06 5B -54 48 45 4E 5D 00 88 CE F0 CE AC CE CE CE 62 C8 -B0 C7 14 C4 06 5B 45 4C 53 45 5D 00 88 CE 06 CF -AC CE CC CE 62 C8 14 C4 04 5B 49 46 5D 00 88 CE -CE CE 3A C4 CC CE 84 C7 14 C4 05 0D 0A 6B 6F 20 -5E C7 BC C4 AC C4 3A C4 CE CE BC CE 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C CF -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 CC -2E C9 96 C9 3A CF 62 C8 40 CF 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A CF F2 C7 62 C8 -72 CF B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E CB 06 4D 41 52 4B 45 52 00 B0 12 14 CD BA 40 -85 12 FC FF BA 40 70 CF FE FF 28 83 8A 48 00 00 -BA 40 AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 -30 4D 0A C4 CA 21 EA C7 62 C8 85 12 B2 CF 7A CC -E8 CD 2E C7 92 CC 66 CE F8 C6 82 CF 14 C9 AA D0 -BE D0 9E C8 28 C9 00 00 5A CF D0 CC F6 C9 00 00 -85 12 B2 CF 72 D6 D8 D6 1A D6 28 D7 E0 D5 00 00 -AC D3 00 00 F0 D7 D4 D7 44 D6 82 D6 BC D4 00 00 -00 00 44 D7 DE CF 3A 40 0C 00 39 40 D6 21 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 -CA 21 DA 21 30 4D BA CF 38 D0 3E D0 4E D0 1A 42 -20 18 82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC CC 09 50 57 52 5F 53 54 41 54 45 85 12 -46 D0 FC D7 E2 C8 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 D0 F3 3F 84 D0 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 21 92 D0 30 4D 96 D0 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C D1 FE FF -29 83 B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 -22 C6 B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 -E0 20 3F 40 80 20 39 40 00 10 29 83 89 43 00 20 -FC 23 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 -26 02 F2 40 FD 00 22 02 E2 D2 24 02 F2 40 A5 00 -A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 -60 01 B2 40 29 01 80 01 B2 40 0B 00 82 01 B2 40 -E9 01 84 01 39 40 00 01 B2 D0 10 00 86 01 38 40 -17 11 18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 -08 18 1E D2 5E 01 B0 12 F8 C4 20 C6 38 40 C0 21 -0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D -1C 15 0E 12 12 12 C4 21 84 12 2E C9 96 C9 F2 C7 -34 C4 EC D1 52 CA 34 C4 06 D2 00 D2 EE D1 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 08 D2 B2 41 C4 21 3E 41 84 12 -0A C4 2B 00 2E C9 96 C9 F2 C7 34 C4 24 D2 52 CA -34 C4 14 CC BC C7 2E C9 52 CA 34 C4 14 CC 30 D2 -3E 5F E7 3F 3E 40 28 00 B0 12 D0 D1 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 -C4 21 02 20 30 40 82 CD 1C 15 12 12 C4 21 92 53 -C4 21 84 12 2E C9 52 CA 34 C4 78 D2 6E D2 21 53 -3E 90 10 00 C6 2B 7F 2D 7A D2 B2 41 C4 21 C1 3F -0D 12 84 12 16 CC AC D1 8A D2 0C 43 1B 42 C6 21 -A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 -C4 21 B0 12 D0 D1 3C 40 00 03 0E 93 1C 24 3C 40 -10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 -20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 -30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 -07 20 3C 40 10 02 92 53 C4 21 B0 12 D0 D1 ED 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 -58 D2 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 58 D2 -92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E -DA 3F B0 12 58 D2 FA 23 3C 50 10 00 B0 12 34 D2 -EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 -16 CC AC D1 56 D3 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C7 3F B0 12 58 D2 E0 23 3C 50 -80 00 B0 12 34 D2 DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A C4 00 13 5C CB 62 C8 0A C4 2C 00 -80 D2 4C D3 96 D3 09 4B 2E 4E 0E DC A2 3F 54 CE -03 4D 4F 56 85 12 8C D3 00 40 A0 D3 05 4D 4F 56 -2E 42 85 12 8C D3 40 40 00 00 03 41 44 44 85 12 -8C D3 00 50 BA D3 05 41 44 44 2E 42 85 12 8C D3 -40 50 C6 D3 04 41 44 44 43 00 85 12 8C D3 00 60 -D4 D3 06 41 44 44 43 2E 42 00 85 12 8C D3 40 60 -7A D3 04 53 55 42 43 00 85 12 8C D3 00 70 F2 D3 -06 53 55 42 43 2E 42 00 85 12 8C D3 40 70 00 D4 -03 53 55 42 85 12 8C D3 00 80 10 D4 05 53 55 42 -2E 42 85 12 8C D3 40 80 2A CE 03 43 4D 50 85 12 -8C D3 00 90 2A D4 05 43 4D 50 2E 42 85 12 8C D3 -40 90 14 CE 04 44 41 44 44 00 85 12 8C D3 00 A0 -44 D4 06 44 41 44 44 2E 42 00 85 12 8C D3 40 A0 -36 D4 03 42 49 54 85 12 8C D3 00 B0 62 D4 05 42 -49 54 2E 42 85 12 8C D3 40 B0 6E D4 03 42 49 43 -85 12 8C D3 00 C0 7C D4 05 42 49 43 2E 42 85 12 -8C D3 40 C0 88 D4 03 42 49 53 85 12 8C D3 00 D0 -96 D4 05 42 49 53 2E 42 85 12 8C D3 40 D0 00 00 -03 58 4F 52 85 12 8C D3 00 E0 B0 D4 05 58 4F 52 -2E 42 85 12 8C D3 40 E0 E2 D3 03 41 4E 44 85 12 -8C D3 00 F0 CA D4 05 41 4E 44 2E 42 85 12 8C D3 -40 F0 16 CC 80 D2 E8 D4 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F 1C D4 03 52 52 43 85 12 -E2 D4 00 10 FA D4 05 52 52 43 2E 42 85 12 E2 D4 -40 10 06 D5 04 53 57 50 42 00 85 12 E2 D4 80 10 -14 D5 03 52 52 41 85 12 E2 D4 00 11 22 D5 05 52 -52 41 2E 42 85 12 E2 D4 40 11 2E D5 03 53 58 54 -85 12 E2 D4 80 11 00 00 04 50 55 53 48 00 85 12 -E2 D4 00 12 48 D5 06 50 55 53 48 2E 42 00 85 12 -E2 D4 40 12 A2 D4 04 43 41 4C 4C 00 85 12 E2 D4 -80 12 1A 53 0E 4A 0D 12 84 12 D8 C8 14 C4 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C5 3C D5 -03 53 3E 3D 86 12 00 38 90 D5 02 53 3C 00 86 12 -00 34 56 D5 03 30 3E 3D 86 12 00 30 A4 D5 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -B8 D5 03 55 3E 3D 86 12 00 28 AE D5 03 30 3C 3E -86 12 00 24 CC D5 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 -0E 4A 30 4D C2 D5 04 54 48 45 4E 00 1A 42 C6 21 -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D 52 D4 04 45 4C 53 45 00 -1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 -8F 4A 00 00 E3 3F 66 D5 05 42 45 47 49 4E 30 40 -28 C4 F6 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D -D6 D4 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 E4 D5 BC C7 -62 C8 9A D5 06 52 45 50 45 41 54 00 0D 12 84 12 -78 D6 FC D5 62 C8 A8 D6 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D 38 D6 -03 42 57 31 85 12 A6 D6 00 00 C0 D6 03 42 57 32 -85 12 A6 D6 00 00 CC D6 03 42 57 33 85 12 A6 D6 -00 00 E4 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 -88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 E2 D6 00 00 04 D7 -03 46 57 32 85 12 E2 D6 00 00 10 D7 03 46 57 33 -85 12 E2 D6 00 00 1C D7 04 47 4F 54 4F 00 2F 83 -8F 4E 00 00 3E 40 00 3C 0D 12 84 12 94 CC F0 CB -62 C8 00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 -3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F -16 CC AC D1 66 D7 92 53 C4 21 3E 40 2C 00 84 12 -2E C9 52 CA 34 C4 14 CC 42 D3 7C D7 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 94 D6 04 52 52 43 4D 00 -85 12 60 D7 50 00 AA D7 04 52 52 41 4D 00 85 12 -60 D7 50 01 B8 D7 04 52 4C 41 4D 00 85 12 60 D7 -50 02 C6 D7 04 52 52 55 4D 00 85 12 60 D7 50 03 -D6 D5 05 50 55 53 48 4D 85 12 60 D7 00 15 E2 D7 -04 50 4F 50 4D 00 85 12 60 D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 96 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1C D1 -q diff --git a/binaries/CHIPSTICK_FR2433_1MHz_115200.txt b/binaries/CHIPSTICK_FR2433_1MHz_115200.txt new file mode 100644 index 0000000..4c48e10 --- /dev/null +++ b/binaries/CHIPSTICK_FR2433_1MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A0 19 +B4 C6 7E C5 84 C5 54 C5 24 C7 12 D7 CA CF 84 CF +84 CF 9A C6 58 C7 20 C7 3C 21 E0 20 78 C9 B6 C4 +C4 C4 94 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +24 C7 12 D7 CA CF 84 CF 84 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F5 3C 0E 93 3E 4F +8A 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 98 C6 B2 49 +56 C7 B2 49 1E C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 3E D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 24 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 9E C8 AC C4 52 C5 66 C7 1E C4 04 1B +5B 37 6D 00 88 C7 88 C7 1E C4 04 1B 5B 30 6D 00 +88 C7 D4 CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 66 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 88 C7 EC C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 88 C7 0A C4 40 FF 32 C4 +B4 C8 B8 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 10 00 00 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 +E0 20 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 +26 02 F2 40 FD 00 22 02 E2 D2 24 02 B2 40 00 A5 +60 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 F2 C3 +82 01 B2 40 1E 00 84 01 39 40 80 00 18 42 00 18 +18 83 FE 23 19 83 FA 23 39 40 00 10 29 83 89 43 +00 20 FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 +3E F3 01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 +43 43 45 50 54 00 30 40 9A C6 08 4E 2E 4F 08 5E +39 40 0D 00 3A 40 20 00 3B 40 F8 C6 3C 40 04 C7 +5D 15 A6 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 +A2 B3 1C 05 FD 27 B2 40 13 00 0E 05 E2 D2 22 02 +30 41 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 +05 3C 0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 +FD 27 C2 48 0E 05 30 4D FA C6 2D 83 92 B3 1C 05 +DB 23 FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 +0C 05 08 4C EB 3F 00 00 06 4B 45 59 30 40 20 C7 +30 12 36 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 +E2 C2 22 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 +FD 27 B0 12 C0 C6 1E 42 0C 05 30 4D 00 00 08 45 +4D 49 54 00 30 40 58 C7 08 4E 3E 4F C7 3F 4E C7 +08 45 43 48 4F 00 B2 40 C2 48 F2 C6 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D F2 C6 30 4D +00 00 08 54 59 50 45 00 0D 12 3D 40 98 C7 29 4F +8F 4E 00 00 7E 49 DE 3F 9A C7 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 7C 22 F9 98 00 00 79 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +70 22 9B 24 18 C7 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A C4 00 00 B8 C8 AA C7 FC C9 B6 CC B0 C4 +26 C8 14 C4 06 5B 54 48 45 4E 5D 00 AE C7 04 C8 +CA C7 E8 C7 14 C4 06 5B 45 4C 53 45 5D 00 AE C7 +16 C8 CA C7 E6 C7 1E C4 04 5B 49 46 5D 00 AE C7 +E8 C7 B2 C4 E6 C7 1E C4 05 0D 6B 6F 20 0A 88 C7 +9A C4 84 C4 B2 C4 E8 C7 D6 C7 0D 5B 54 48 45 4E +5D 00 30 4D 3A C8 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D 46 C8 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 AA C7 FC C9 64 CA 08 CC 78 C9 56 C8 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +AA C7 FC C9 64 CA 88 C8 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D 8E C6 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +D8 C5 05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 +1E C4 66 CC 0A C4 22 00 FC C9 FC C8 B2 40 20 00 +C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D +70 C7 05 2E 22 00 0D 12 84 12 E6 C8 0A C4 88 C7 +66 CC 78 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 +30 4D E2 C8 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 +46 C4 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 +30 4D 34 C9 04 23 53 00 0D 12 84 12 36 C9 70 C9 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D 64 C9 04 23 +3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 7E C9 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 60 C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 2A C9 AA C7 98 C9 68 C9 94 C8 +A6 C9 82 C9 88 C7 78 C9 12 C9 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 +1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D EA C9 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 +8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 +0C 4E 0E 43 1E 15 3D 40 6E CB 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 70 CB +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 +0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E C4 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D 26 C9 03 5C +92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 C4 AA C7 +FC C9 B0 C4 40 CD 64 CA 2A CC 0A 4E 3E 4F 3D 40 +44 CC 6D 27 3D 40 1E CC 1A E2 BC 21 14 24 0E 12 +3E 4F 30 41 46 CC 3E 4F 3D 40 1E CC 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 1C CE +2A 3C 0E CC 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E +FE FF 3E 4F 30 4D 64 CC 0F 4C 49 54 45 52 41 4C +82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 +BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D A0 C9 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D C6 C8 0A 41 4C 4C 4F 54 82 5E C8 21 +3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E C4 02 0D +0A 00 88 C7 94 C4 18 CC A6 C8 D0 C8 1E C4 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 C5 32 C4 0A C4 +40 FF D8 C8 1E C4 09 46 52 41 4D 20 66 75 6C 6C +08 C5 B2 C4 DC CC C6 CC 0D 41 42 4F 52 54 22 00 +0D 12 84 12 E6 C8 0A C4 08 C5 66 CC 78 C9 F6 C9 +02 27 0D 12 84 12 AA C7 FC C9 64 CA B0 C4 42 CD +0A C9 4E CC 70 C8 07 5B 27 5D 0D 12 84 12 32 CD +0A C4 0A C4 66 CC 66 CC 78 C9 46 CD 03 5B 82 43 +BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D BE C8 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 AA C7 +FC C9 64 CA B0 C4 42 CD D0 C8 AC C4 9A CD 0A C4 +0A C4 66 CC 66 CC 0A C4 66 CC 66 CC 78 C9 00 00 +02 3A 30 12 F0 CD 92 B3 C8 21 A2 63 C8 21 0D 12 +84 12 AA C7 FC C9 B8 CD 3D 41 5A D3 5A 53 0A 5E +19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 +82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 +30 4D 82 9F BA 21 66 25 84 12 1E C4 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 C5 5C CD +03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A C4 78 C9 +66 CC 02 CE 5E CD 78 C9 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D B0 CC +0C 43 52 45 41 54 45 00 B0 12 A6 CD BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D 82 C7 0A 44 4F 45 53 3E +1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D A0 CD 0E 3A 4E 4F 4E 41 4D 45 30 12 F0 CD +2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F 3A CE 05 49 53 00 0D 12 +82 93 BC 21 08 20 84 12 32 CD BC CE 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 4A CD 0A C4 BE CE 66 CC +78 C9 50 CE 08 43 4F 44 45 00 B0 12 A6 CD A2 82 +C8 21 61 3C 92 C9 0E 48 44 4E 43 4F 44 45 B2 40 +AA CF CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 02 CE 08 CF 3D 41 92 42 D0 21 CC 21 +5D 3C D4 CE 0E 43 4F 44 45 4E 4E 4D 30 12 DE CE +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 +BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 +1A 42 C8 21 EF 3F E6 CE 0B 48 49 32 4C 4F A2 53 +C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F +72 CF B2 40 84 CF D0 21 82 4E CE 21 30 40 0A C9 +85 12 70 CF 70 CD 18 CD 02 D0 14 CF 6A CE B4 C9 +5E CA 30 CD 58 CF AA CE 84 CE 20 CE 78 CC 8C D0 +B6 CA 00 00 00 00 85 12 70 CF 06 D7 8A D5 EA D6 +B2 D4 0E D5 5C D5 38 D6 44 D6 D4 D3 F8 D4 00 00 +00 00 46 CF C4 D2 00 00 60 D6 A4 CF B2 40 84 CF +CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 21 3A 40 42 18 B0 12 D8 CF 30 4D +EA CF 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 21 B0 12 D8 CF 1A 42 CA 21 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +08 C6 FE FF 29 83 B9 40 F2 C5 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 E4 FF 3B 40 10 00 3A 40 +3A 18 B0 12 DC CF 82 43 4A 18 C7 3F 7E D0 B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F 66 CD 0C 4D 41 52 +4B 45 52 00 12 12 C6 21 0D 12 84 12 AA C7 FC C9 +64 CA AC C4 AA D0 9E C8 3E CC AC D0 3E 4F 3D 41 +B2 41 C6 21 B0 12 A6 CD BA 40 85 12 FC FF BA 40 +7C D0 FE FF 28 83 8A 48 00 00 BA 40 82 C4 02 00 +A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 21 84 12 FC C9 64 CA +AC C4 16 D1 F6 D0 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 7C D0 00 00 01 20 3E 52 +2E 83 21 53 30 41 0E CB AC C4 1E D1 12 D1 20 D1 +B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E +3D 15 B0 12 E6 D0 15 20 3E 40 2B 00 B0 12 E6 D0 +06 20 3E 40 2D 00 B0 12 E6 D0 92 83 C6 21 0E 12 +1E 41 02 00 84 12 FC C9 0E CB AC C4 42 CD 60 D1 +3E 51 3A 17 30 41 B0 12 26 D1 19 42 C8 21 89 4E +00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 +C6 21 3D 15 84 12 FC C9 0E CB AC C4 98 D1 90 D1 +3E 90 10 00 E6 2B 7C 2D 9A D1 A2 41 C6 21 E1 3F +03 20 B0 12 7E D1 43 3C 7A 90 23 00 24 20 B0 12 +2E D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 +10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 +08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 2E D1 F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 7A D1 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +7E D1 92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 66 D1 F2 3F 03 20 +B0 12 7E D1 F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 66 D1 EA 3F 0C 43 1B 42 +C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 +C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 +C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A C4 00 13 66 CC 78 C9 0A C4 2C 00 +5C D2 A0 D1 AA C7 66 D2 3E D2 AC D2 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 9C D2 +00 40 B8 D2 0A 4D 4F 56 2E 42 85 12 9C D2 40 40 +00 00 06 41 44 44 85 12 9C D2 00 50 D2 D2 0A 41 +44 44 2E 42 85 12 9C D2 40 50 DE D2 08 41 44 44 +43 00 85 12 9C D2 00 60 EC D2 0C 41 44 44 43 2E +42 00 85 12 9C D2 40 60 24 CF 08 53 55 42 43 00 +85 12 9C D2 00 70 0A D3 0C 53 55 42 43 2E 42 00 +85 12 9C D2 40 70 18 D3 06 53 55 42 85 12 9C D2 +00 80 28 D3 0A 53 55 42 2E 42 85 12 9C D2 40 80 +34 D3 06 43 4D 50 85 12 9C D2 00 90 42 D3 0A 43 +4D 50 2E 42 85 12 9C D2 40 90 00 00 08 44 41 44 +44 00 85 12 9C D2 00 A0 5C D3 0C 44 41 44 44 2E +42 00 85 12 9C D2 40 A0 8A D2 06 42 49 54 85 12 +9C D2 00 B0 7A D3 0A 42 49 54 2E 42 85 12 9C D2 +40 B0 86 D3 06 42 49 43 85 12 9C D2 00 C0 94 D3 +0A 42 49 43 2E 42 85 12 9C D2 40 C0 A0 D3 06 42 +49 53 85 12 9C D2 00 D0 AE D3 0A 42 49 53 2E 42 +85 12 9C D2 40 D0 00 00 06 58 4F 52 85 12 9C D2 +00 E0 C8 D3 0A 58 4F 52 2E 42 85 12 9C D2 40 E0 +FA D2 06 41 4E 44 85 12 9C D2 00 F0 E2 D3 0A 41 +4E 44 2E 42 85 12 9C D2 40 F0 AA C7 5C D2 A0 D1 +02 D4 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F BA D3 06 52 52 43 85 12 FA D3 00 10 14 D4 +0A 52 52 43 2E 42 85 12 FA D3 40 10 4E D3 08 53 +57 50 42 00 85 12 FA D3 80 10 20 D4 06 52 52 41 +85 12 FA D3 00 11 3C D4 0A 52 52 41 2E 42 85 12 +FA D3 40 11 2E D4 06 53 58 54 85 12 FA D3 80 11 +00 00 08 50 55 53 48 00 85 12 FA D3 00 12 62 D4 +0C 50 55 53 48 2E 42 00 85 12 FA D3 40 12 56 D4 +08 43 41 4C 4C 00 85 12 FA D3 80 12 1A 53 0E 4A +84 12 EC C9 1E C4 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 C5 80 D4 06 53 3E 3D 86 12 00 38 +A8 D4 04 53 3C 00 86 12 00 34 70 D4 06 30 3E 3D +86 12 00 30 BC D4 04 30 3C 00 86 12 00 30 F8 CE +04 55 3C 00 86 12 00 2C D0 D4 06 55 3E 3D 86 12 +00 28 C6 D4 06 30 3C 3E 86 12 00 24 E4 D4 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 +8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 6A D3 08 54 +48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +DA D4 08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C +00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 48 D4 +0A 42 45 47 49 4E 30 40 32 C4 32 D5 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 21 30 4D EE D3 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 FC D4 92 C8 78 C9 50 D5 0C 52 45 50 +45 41 54 00 0D 12 84 12 90 D5 14 D5 78 C9 C0 D5 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 +C8 21 00 00 30 4D AC D5 06 42 57 31 85 12 BE D5 +00 00 D8 D5 06 42 57 32 85 12 BE D5 00 00 E4 D5 +06 42 57 33 85 12 BE D5 00 00 FC D5 3D 41 1A 42 +C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F +00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 FA D5 00 00 20 D6 06 46 57 32 +85 12 FA D5 00 00 2C D6 06 46 57 33 85 12 FA D5 +00 00 9A D5 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 32 CD 3E CC 78 C9 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F 66 D2 0A C4 +2C 00 FC C9 0E CB AC C4 42 CD AA C7 5C D2 3E D2 +92 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E F0 D5 +08 52 52 43 4D 00 85 12 7C D6 50 00 C0 D6 08 52 +52 41 4D 00 85 12 7C D6 50 01 CE D6 08 52 4C 41 +4D 00 85 12 7C D6 50 02 DC D6 08 52 52 55 4D 00 +85 12 7C D6 50 03 EE D4 0A 50 55 53 48 4D 85 12 +7C D6 00 15 F8 D6 08 50 4F 50 4D 00 85 12 7C D6 +00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 B4 C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 08 C6 +q diff --git a/binaries/CHIPSTICK_FR2433_1MHz_I2C.txt b/binaries/CHIPSTICK_FR2433_1MHz_I2C.txt index 342233d..204b997 100644 --- a/binaries/CHIPSTICK_FR2433_1MHz_I2C.txt +++ b/binaries/CHIPSTICK_FR2433_1MHz_I2C.txt @@ -1,334 +1,321 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF D4 D7 F2 CF 34 01 -10 00 41 07 B6 C5 AA C4 B8 C5 8C C5 84 C6 D4 D7 -F2 CF 72 C6 82 C7 00 C7 DC C6 3C 21 50 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 03 +AE C6 56 C5 56 C5 58 C5 44 C5 EE D6 A6 CF 60 CF +60 CF 9C C6 20 C7 F8 C6 3C 21 E0 20 54 C9 B6 C4 +C4 C4 70 C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 EE D6 A6 CF 60 CF 60 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 70 C6 B2 49 80 C7 B2 49 FE C6 B2 49 DA C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 D0 C7 18 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 98 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C C7 90 C8 4C C7 -14 C4 04 1B 5B 30 6D 00 4C C7 18 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 -B0 12 8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 -07 0D 0A 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 0A C4 23 00 FC C6 C6 C8 14 C4 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C C7 0A C4 40 FF 28 C4 C4 C7 -90 C8 14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 -3A C4 7E C5 00 00 06 41 43 43 45 50 54 00 30 40 -72 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 -B7 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC C6 2F 83 8F 4E -00 00 58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 -4C 05 30 4D 00 00 04 45 4D 49 54 00 30 40 00 C7 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F6 3C 0E 93 3E 4F +78 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9A C6 B2 49 +1E C7 B2 49 F6 C6 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 1A D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 7A C8 AC C4 +42 C5 38 C7 1E C4 05 1B 5B 37 6D 40 64 C7 0A C4 +02 18 9C C8 C8 C9 64 C7 1E C4 04 1B 5B 30 6D 00 +64 C7 B0 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 38 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 64 C7 0A C4 02 18 9C C8 C8 C9 0A C4 23 00 +1C C7 C8 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +64 C7 0A C4 40 FF 32 C4 90 C8 94 C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +10 00 00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +CC 01 31 40 E0 20 3F 40 80 20 B2 43 02 02 B2 D3 +06 02 D2 43 24 02 F2 D3 26 02 F2 40 FD 00 22 02 +B2 40 00 A5 60 01 B2 D0 10 00 86 01 B2 40 00 02 +88 01 F2 C3 82 01 B2 40 1E 00 84 01 39 40 80 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 00 10 +29 83 89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 +3E F3 02 20 1E 42 5E 01 B0 12 D0 C4 80 C5 00 00 +0C 41 43 43 45 50 54 00 30 40 9C C6 0A 4E 2E 4F +0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 A9 3E 21 52 +A2 C2 6C 05 B2 B0 10 00 40 05 A2 22 3A 17 92 B3 +6C 05 FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C +78 92 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F +CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 +06 4B 45 59 30 40 F8 C6 58 43 B0 12 46 C5 2F 83 +8F 4E 00 00 92 B3 6C 05 FD 27 1E 42 4C 05 B0 12 +44 C5 30 4D 00 00 08 45 4D 49 54 00 30 40 20 C7 08 4E 3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D -F6 C6 04 45 43 48 4F 00 B2 40 C2 48 0A C7 82 43 -DE 21 38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A C7 92 43 DE 21 -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE C6 6A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 -82 C7 0D 12 84 12 14 C4 02 0D 0A 00 4C C7 50 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 C6 01 40 -2E 4E 30 4D CE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 7A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 0A C8 02 23 53 00 0D 12 -84 12 0C C8 46 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 C8 3E C8 EE C4 7E C8 5A C8 4C C7 04 CC FC C6 -50 C8 2E C7 01 2E 0E 93 E3 37 38 43 E2 3F 78 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -4A CB 0A C4 22 00 1C C9 EA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -C4 C8 82 2E 22 00 0D 12 84 12 D4 C8 0A C4 4C C7 -4A CB 50 C8 FA C5 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9E CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 48 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 04 CC 1C C9 C0 CB -9C 26 3D 40 C8 CB DE 3E CA CB 0A 4E 3E 4F 3D 40 -E4 CB 36 27 3D 40 BA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 E6 CB 3E 4F 3D 40 BA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 CD -CC 3F EE CB 86 12 20 00 D6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 7E C7 -BC C4 B4 CB B4 C7 E6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -EE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 2E CC 0A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 C8 0A C4 2A C5 4A CB 50 C8 7E C9 -01 27 0D 12 84 12 04 CC 1C C9 84 C9 34 C4 02 CC -50 C8 00 00 83 5B 27 5D 0D 12 84 12 82 CC 0A C4 -0A C4 4A CB 4A CB 50 C8 94 CC 81 5B 82 43 BE 21 -30 4D FC C7 01 5D B2 43 BE 21 30 4D B4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 CC 1C C9 84 C9 98 C7 -34 C4 02 CC E6 C7 34 C4 F6 CC 0A C4 0A C4 4A CB -4A CB 0A C4 4A CB 4A CB 50 C8 AA CC 01 3A 30 12 -46 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 04 CC -1C C9 14 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 FC CC 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 50 C8 4A CB 58 CD AC CC -50 C8 AA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D 94 CB 06 43 52 45 -41 54 45 00 B0 12 02 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC CD 04 43 4F 44 45 00 B0 12 02 CD -A2 82 C6 21 0D 12 84 12 F4 CF CE CF 50 C8 A4 CD -07 48 44 4E 43 4F 44 45 B2 40 D2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 CD -0E D0 2C D0 50 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 0E D0 2C D0 50 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F F0 CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -9C CF 4A CB AC CC E4 CD 50 C8 8A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 C8 C7 04 CC 1C C9 -9A CB 90 C7 34 C4 04 CF 9E C7 14 C4 06 5B 54 48 -45 4E 5D 00 76 CE DE CE 9A CE BC CE 50 C8 9E C7 -14 C4 06 5B 45 4C 53 45 5D 00 76 CE F4 CE 9A CE -BA CE 50 C8 14 C4 04 5B 49 46 5D 00 76 CE BC CE -3A C4 BA CE 72 C7 14 C4 05 0D 0A 6B 6F 20 4C C7 -BC C4 AC C4 3A C4 BC CE AA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 CC 1C C9 -84 C9 28 CF 50 C8 2E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 CF E0 C7 50 C8 60 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C CB -06 4D 41 52 4B 45 52 00 B0 12 02 CD BA 40 85 12 -FC FF BA 40 5E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 D8 C7 50 C8 85 12 A0 CF 68 CC D6 CD -12 C7 80 CC 54 CE D4 C6 70 CF 02 C9 98 D0 AC D0 -8C C8 16 C9 00 00 48 CF BE CC E4 C9 00 00 85 12 -A0 CF 4A D6 B0 D6 F2 D5 00 D7 B8 D5 00 00 84 D3 -00 00 C8 D7 AC D7 1C D6 5A D6 94 D4 00 00 00 00 -1C D7 CC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D A8 CF 26 D0 2C D0 3C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA CC 09 50 57 52 5F 53 54 41 54 45 85 12 34 D0 -D4 D7 D0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 D0 F3 3F 72 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 80 D0 30 4D 84 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A D1 FE FF 29 83 -B9 40 E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 02 C6 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 26 02 -F2 40 FD 00 22 02 B2 40 00 A5 60 01 B2 40 B4 00 -80 01 92 43 82 01 B2 40 1E 00 84 01 39 40 10 00 -B2 D0 10 00 86 01 38 40 17 11 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 00 C6 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 1C C9 84 C9 E0 C7 34 C4 C4 D1 40 CA 34 C4 -DE D1 D8 D1 C6 D1 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 E0 D1 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1C C9 84 C9 -E0 C7 34 C4 FC D1 40 CA 34 C4 02 CC AA C7 1C C9 -40 CA 34 C4 02 CC 08 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 A8 D1 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 70 CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 1C C9 40 CA -34 C4 50 D2 46 D2 21 53 3E 90 10 00 C6 2B 7F 2D -52 D2 B2 41 C4 21 C1 3F 0D 12 84 12 04 CC 84 D1 -62 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 A8 D1 3C 40 +16 C7 08 45 43 48 4F 00 B2 40 C2 48 2A C7 38 40 +05 00 B0 12 46 C5 30 4D 00 00 0C 4E 4F 45 43 48 +4F 00 B2 40 30 4D 2A C7 28 42 F3 3F 00 00 08 54 +59 50 45 00 0D 12 3D 40 74 C7 29 4F 8F 4E 00 00 +7E 49 D4 3F 76 C7 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 8E 22 F9 98 00 00 8B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 82 22 9B 24 +F0 C6 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 +00 00 94 C8 86 C7 D8 C9 92 CC B0 C4 02 C8 14 C4 +06 5B 54 48 45 4E 5D 00 8A C7 E0 C7 A6 C7 C4 C7 +14 C4 06 5B 45 4C 53 45 5D 00 8A C7 F2 C7 A6 C7 +C2 C7 1E C4 04 5B 49 46 5D 00 8A C7 C4 C7 B2 C4 +C2 C7 1E C4 05 0D 6B 6F 20 0A 64 C7 9A C4 84 C4 +B2 C4 C4 C7 B2 C7 0D 5B 54 48 45 4E 5D 00 30 4D +16 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +22 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +86 C7 D8 C9 40 CA E4 CB 54 C9 32 C8 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 86 C7 D8 C9 +40 CA 64 C8 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +90 C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D E0 C5 05 53 +22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 42 CC +0A C4 22 00 D8 C9 D8 C8 B2 40 20 00 C0 21 1A 53 +1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 4A C7 05 2E +22 00 0D 12 84 12 C2 C8 0A C4 64 C7 42 CC 54 C9 +00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D BE C8 +02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D 10 C9 +04 23 53 00 0D 12 84 12 12 C9 4C C9 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 40 C9 04 23 3E 00 9F 42 +B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 5A C9 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 32 C7 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 06 C9 86 C7 74 C9 44 C9 70 C8 82 C9 5E C9 +64 C7 54 C9 EE C8 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +C6 C9 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E 0E 43 +1E 15 3D 40 4A CB 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 4C CB 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 02 C9 03 5C 92 42 C2 21 +C6 21 30 4D 0D 12 84 12 84 C4 86 C7 D8 C9 B0 C4 +1C CD 40 CA 06 CC 0A 4E 3E 4F 3D 40 20 CC 6D 27 +3D 40 FA CB 1A E2 BC 21 14 24 0E 12 3E 4F 30 41 +22 CC 3E 4F 3D 40 FA CB 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 F8 CD 2A 3C EA CB +02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F +30 4D 40 CC 0F 4C 49 54 45 52 41 4C 82 93 BC 21 +0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D 7C C9 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +A2 C8 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D +3F 40 80 20 0E 43 84 12 1E C4 02 0D 0A 00 64 C7 +94 C4 F4 CB 82 C8 AC C8 1E C4 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 C5 32 C4 0A C4 40 FF B4 C8 +1E C4 09 46 52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 +B8 CC A2 CC 0D 41 42 4F 52 54 22 00 0D 12 84 12 +C2 C8 0A C4 08 C5 42 CC 54 C9 D2 C9 02 27 0D 12 +84 12 86 C7 D8 C9 40 CA B0 C4 1E CD E6 C8 2A CC +4C C8 07 5B 27 5D 0D 12 84 12 0E CD 0A C4 0A C4 +42 CC 42 CC 54 C9 22 CD 03 5B 82 43 BC 21 30 4D +00 00 02 5D B2 43 BC 21 30 4D 9A C8 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 86 C7 D8 C9 40 CA +B0 C4 1E CD AC C8 AC C4 76 CD 0A C4 0A C4 42 CC +42 CC 0A C4 42 CC 42 CC 54 C9 00 00 02 3A 30 12 +CC CD 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 86 C7 +D8 C9 94 CD 3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A B8 21 +82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D 82 9F +BA 21 66 25 84 12 1E C4 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 C5 38 CD 03 3B 82 93 +BC 21 F4 26 0D 12 84 12 0A C4 54 C9 42 CC DE CD +3A CD 54 C9 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 21 D8 D3 00 00 30 4D 8C CC 0C 43 52 45 +41 54 45 00 B0 12 82 CD BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 5E C7 0A 44 4F 45 53 3E 1A 42 B8 21 +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D 7C CD +0E 3A 4E 4F 4E 41 4D 45 30 12 CC CD 2F 83 8F 4E +00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 16 CE 05 49 53 00 0D 12 82 93 BC 21 +08 20 84 12 0E CD 98 CE 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 26 CD 0A C4 9A CE 42 CC 54 C9 2C CE +08 43 4F 44 45 00 B0 12 82 CD A2 82 C8 21 61 3C +6E C9 0E 48 44 4E 43 4F 44 45 B2 40 86 CF CC 21 +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +DE CD E4 CE 3D 41 92 42 D0 21 CC 21 5D 3C B0 CE +0E 43 4F 44 45 4E 4E 4D 30 12 BA CE B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 C8 21 +EF 3F C2 CE 0B 48 49 32 4C 4F A2 53 C8 21 1A 42 +C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 4E CF B2 40 +60 CF D0 21 82 4E CE 21 30 40 E6 C8 85 12 4C CF +4C CD F4 CC DE CF F0 CE 46 CE 90 C9 3A CA 0C CD +34 CF 86 CE 60 CE FC CD 54 CC 68 D0 92 CA 00 00 +00 00 85 12 4C CF E2 D6 66 D5 C6 D6 8E D4 EA D4 +38 D5 14 D6 20 D6 B0 D3 D4 D4 00 00 00 00 22 CF +A0 D2 00 00 3C D6 80 CF B2 40 60 CF CE 21 82 43 +D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 21 3A 40 42 18 B0 12 B4 CF 30 4D C6 CF 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 21 +B0 12 B4 CF 1A 42 CA 21 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 10 C6 FE FF +29 83 B9 40 FA C5 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 E0 FF 3B 40 10 00 3A 40 3A 18 B0 12 +B8 CF 82 43 4A 18 C7 3F 5A D0 B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 42 CD 0C 4D 41 52 4B 45 52 00 +12 12 C6 21 0D 12 84 12 86 C7 D8 C9 40 CA AC C4 +86 D0 7A C8 1A CC 88 D0 3E 4F 3D 41 B2 41 C6 21 +B0 12 82 CD BA 40 85 12 FC FF BA 40 58 D0 FE FF +28 83 8A 48 00 00 BA 40 82 C4 02 00 A2 52 C8 21 +18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 21 84 12 D8 C9 40 CA AC C4 F2 D0 +D2 D0 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 58 D0 00 00 01 20 3E 52 2E 83 21 53 +30 41 EA CA AC C4 FA D0 EE D0 FC D0 B2 41 C6 21 +30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 +C2 D0 15 20 3E 40 2B 00 B0 12 C2 D0 06 20 3E 40 +2D 00 B0 12 C2 D0 92 83 C6 21 0E 12 1E 41 02 00 +84 12 D8 C9 EA CA AC C4 1E CD 3C D1 3E 51 3A 17 +30 41 B0 12 02 D1 19 42 C8 21 89 4E 00 00 A2 53 +C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 3D 15 +84 12 D8 C9 EA CA AC C4 74 D1 6C D1 3E 90 10 00 +E6 2B 7C 2D 76 D1 A2 41 C6 21 E1 3F 03 20 B0 12 +5A D1 43 3C 7A 90 23 00 24 20 B0 12 0A D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 A8 D1 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 30 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 30 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 30 D2 FA 23 -3C 50 10 00 B0 12 0C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 04 CC 84 D1 2E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 30 D2 E0 23 3C 50 80 00 B0 12 0C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -4A CB 50 C8 0A C4 2C 00 58 D2 24 D3 6E D3 09 4B -2E 4E 0E DC A2 3F 42 CE 03 4D 4F 56 85 12 64 D3 -00 40 78 D3 05 4D 4F 56 2E 42 85 12 64 D3 40 40 -00 00 03 41 44 44 85 12 64 D3 00 50 92 D3 05 41 -44 44 2E 42 85 12 64 D3 40 50 9E D3 04 41 44 44 -43 00 85 12 64 D3 00 60 AC D3 06 41 44 44 43 2E -42 00 85 12 64 D3 40 60 52 D3 04 53 55 42 43 00 -85 12 64 D3 00 70 CA D3 06 53 55 42 43 2E 42 00 -85 12 64 D3 40 70 D8 D3 03 53 55 42 85 12 64 D3 -00 80 E8 D3 05 53 55 42 2E 42 85 12 64 D3 40 80 -18 CE 03 43 4D 50 85 12 64 D3 00 90 02 D4 05 43 -4D 50 2E 42 85 12 64 D3 40 90 02 CE 04 44 41 44 -44 00 85 12 64 D3 00 A0 1C D4 06 44 41 44 44 2E -42 00 85 12 64 D3 40 A0 0E D4 03 42 49 54 85 12 -64 D3 00 B0 3A D4 05 42 49 54 2E 42 85 12 64 D3 -40 B0 46 D4 03 42 49 43 85 12 64 D3 00 C0 54 D4 -05 42 49 43 2E 42 85 12 64 D3 40 C0 60 D4 03 42 -49 53 85 12 64 D3 00 D0 6E D4 05 42 49 53 2E 42 -85 12 64 D3 40 D0 00 00 03 58 4F 52 85 12 64 D3 -00 E0 88 D4 05 58 4F 52 2E 42 85 12 64 D3 40 E0 -BA D3 03 41 4E 44 85 12 64 D3 00 F0 A2 D4 05 41 -4E 44 2E 42 85 12 64 D3 40 F0 04 CC 58 D2 C0 D4 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -F4 D3 03 52 52 43 85 12 BA D4 00 10 D2 D4 05 52 -52 43 2E 42 85 12 BA D4 40 10 DE D4 04 53 57 50 -42 00 85 12 BA D4 80 10 EC D4 03 52 52 41 85 12 -BA D4 00 11 FA D4 05 52 52 41 2E 42 85 12 BA D4 -40 11 06 D5 03 53 58 54 85 12 BA D4 80 11 00 00 -04 50 55 53 48 00 85 12 BA D4 00 12 20 D5 06 50 -55 53 48 2E 42 00 85 12 BA D4 40 12 7A D4 04 43 -41 4C 4C 00 85 12 BA D4 80 12 1A 53 0E 4A 0D 12 -84 12 C6 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 14 D5 03 53 3E 3D 86 12 00 38 -68 D5 02 53 3C 00 86 12 00 34 2E D5 03 30 3E 3D -86 12 00 30 7C D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C 90 D5 03 55 3E 3D 86 12 -00 28 86 D5 03 30 3C 3E 86 12 00 24 A4 D5 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D 9A D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -2A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 3E D5 -05 42 45 47 49 4E 30 40 28 C4 CE D5 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D AE D4 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 BC D5 AA C7 50 C8 72 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 50 D6 D4 D5 50 C8 80 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 10 D6 03 42 57 31 85 12 7E D6 -00 00 98 D6 03 42 57 32 85 12 7E D6 00 00 A4 D6 -03 42 57 33 85 12 7E D6 00 00 BC D6 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 BA D6 00 00 DC D6 03 46 57 32 85 12 BA D6 -00 00 E8 D6 03 46 57 33 85 12 BA D6 00 00 F4 D6 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 82 CC DE CB 50 C8 00 00 05 3F 47 4F +30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 0A D1 +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 56 D1 +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 5A D1 92 92 +C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 42 D1 F2 3F 03 20 B0 12 5A D1 +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 42 D1 EA 3F 0C 43 1B 42 C8 21 A2 53 +C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 7A 99 +FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A C4 00 13 42 CC 54 C9 0A C4 2C 00 38 D2 7C D1 +86 C7 42 D2 1A D2 88 D2 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 78 D2 00 40 94 D2 +0A 4D 4F 56 2E 42 85 12 78 D2 40 40 00 00 06 41 +44 44 85 12 78 D2 00 50 AE D2 0A 41 44 44 2E 42 +85 12 78 D2 40 50 BA D2 08 41 44 44 43 00 85 12 +78 D2 00 60 C8 D2 0C 41 44 44 43 2E 42 00 85 12 +78 D2 40 60 00 CF 08 53 55 42 43 00 85 12 78 D2 +00 70 E6 D2 0C 53 55 42 43 2E 42 00 85 12 78 D2 +40 70 F4 D2 06 53 55 42 85 12 78 D2 00 80 04 D3 +0A 53 55 42 2E 42 85 12 78 D2 40 80 10 D3 06 43 +4D 50 85 12 78 D2 00 90 1E D3 0A 43 4D 50 2E 42 +85 12 78 D2 40 90 00 00 08 44 41 44 44 00 85 12 +78 D2 00 A0 38 D3 0C 44 41 44 44 2E 42 00 85 12 +78 D2 40 A0 66 D2 06 42 49 54 85 12 78 D2 00 B0 +56 D3 0A 42 49 54 2E 42 85 12 78 D2 40 B0 62 D3 +06 42 49 43 85 12 78 D2 00 C0 70 D3 0A 42 49 43 +2E 42 85 12 78 D2 40 C0 7C D3 06 42 49 53 85 12 +78 D2 00 D0 8A D3 0A 42 49 53 2E 42 85 12 78 D2 +40 D0 00 00 06 58 4F 52 85 12 78 D2 00 E0 A4 D3 +0A 58 4F 52 2E 42 85 12 78 D2 40 E0 D6 D2 06 41 +4E 44 85 12 78 D2 00 F0 BE D3 0A 41 4E 44 2E 42 +85 12 78 D2 40 F0 86 C7 38 D2 7C D1 DE D3 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F 96 D3 +06 52 52 43 85 12 D6 D3 00 10 F0 D3 0A 52 52 43 +2E 42 85 12 D6 D3 40 10 2A D3 08 53 57 50 42 00 +85 12 D6 D3 80 10 FC D3 06 52 52 41 85 12 D6 D3 +00 11 18 D4 0A 52 52 41 2E 42 85 12 D6 D3 40 11 +0A D4 06 53 58 54 85 12 D6 D3 80 11 00 00 08 50 +55 53 48 00 85 12 D6 D3 00 12 3E D4 0C 50 55 53 +48 2E 42 00 85 12 D6 D3 40 12 32 D4 08 43 41 4C +4C 00 85 12 D6 D3 80 12 1A 53 0E 4A 84 12 C8 C9 +1E C4 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 C5 5C D4 06 53 3E 3D 86 12 00 38 84 D4 04 53 +3C 00 86 12 00 34 4C D4 06 30 3E 3D 86 12 00 30 +98 D4 04 30 3C 00 86 12 00 30 D4 CE 04 55 3C 00 +86 12 00 2C AC D4 06 55 3E 3D 86 12 00 28 A2 D4 +06 30 3C 3E 86 12 00 24 C0 D4 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E 00 00 +A2 53 C8 21 0E 4A 30 4D 46 D3 08 54 48 45 4E 00 +1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D B6 D4 08 45 +4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 A2 53 +C8 21 2F 83 8F 4A 00 00 E3 3F 24 D4 0A 42 45 47 +49 4E 30 40 32 C4 0E D5 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 21 30 4D CA D3 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +D8 D4 6E C8 54 C9 2C D5 0C 52 45 50 45 41 54 00 +0D 12 84 12 6C D5 F0 D4 54 C9 9C D5 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 00 00 +30 4D 88 D5 06 42 57 31 85 12 9A D5 00 00 B4 D5 +06 42 57 32 85 12 9A D5 00 00 C0 D5 06 42 57 33 +85 12 9A D5 00 00 D8 D5 3D 41 1A 42 C8 21 28 4E +8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 A2 53 +C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 D6 D5 00 00 FC D5 06 46 57 32 85 12 D6 D5 +00 00 08 D6 06 46 57 33 85 12 D6 D5 00 00 76 D5 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 0E CD 1A CC 54 C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 04 CC 84 D1 3E D7 92 53 -C4 21 3E 40 2C 00 84 12 1C C9 40 CA 34 C4 02 CC -1A D3 54 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -6C D6 04 52 52 43 4D 00 85 12 38 D7 50 00 82 D7 -04 52 52 41 4D 00 85 12 38 D7 50 01 90 D7 04 52 -4C 41 4D 00 85 12 38 D7 50 02 9E D7 04 52 52 55 -4D 00 85 12 38 D7 50 03 AE D5 05 50 55 53 48 4D -85 12 38 D7 00 15 BA D7 04 50 4F 50 4D 00 85 12 -38 D7 00 17 +EF 27 3E E0 00 08 EC 3F 42 D2 0A C4 2C 00 D8 C9 +EA CA AC C4 1E CD 86 C7 38 D2 1A D2 6E D6 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E CC D5 08 52 52 43 +4D 00 85 12 58 D6 50 00 9C D6 08 52 52 41 4D 00 +85 12 58 D6 50 01 AA D6 08 52 4C 41 4D 00 85 12 +58 D6 50 02 B8 D6 08 52 52 55 4D 00 85 12 58 D6 +50 03 CA D4 0A 50 55 53 48 4D 85 12 58 D6 00 15 +D4 D6 08 50 4F 50 4D 00 85 12 58 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -84 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 0A D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +AE C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 10 C6 q diff --git a/binaries/CHIPSTICK_FR2433_1MHz_UART.txt b/binaries/CHIPSTICK_FR2433_1MHz_UART.txt deleted file mode 100644 index 9449611..0000000 --- a/binaries/CHIPSTICK_FR2433_1MHz_UART.txt +++ /dev/null @@ -1,335 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF EA D7 04 D0 34 01 -10 00 41 33 94 C5 AA C4 DA C5 9C C5 96 C6 EA D7 -04 D0 7C C6 94 C7 26 C7 00 C7 3C 21 62 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 7A C6 B2 49 92 C7 B2 49 24 C7 B2 49 FE C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 D0 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E2 C7 34 C7 -14 C4 04 1B 5B 37 6D 00 5E C7 AA C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E C7 A2 C8 5E C7 14 C4 04 1B 5B 30 6D 00 -5E C7 2A CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D2 22 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C2 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 -B0 12 9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 -5E C7 D8 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E C7 0A C4 40 FF 28 C4 D6 C7 A2 C8 14 C4 0A 62 -79 74 65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 -06 41 43 43 45 50 54 00 30 40 7C C6 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 C6 3C 40 -D4 C6 5D 15 B5 3E 21 52 3A 17 58 42 0C 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 -FD 27 C2 48 0E 05 30 4D CA C6 2D 83 92 B3 1C 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -1C 05 FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 -DE 21 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 C7 -2F 83 8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 -1E 42 0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 C7 08 4E 3E 4F C8 3F 1C C7 04 45 -43 48 4F 00 B2 40 C2 48 C2 C6 82 43 DE 21 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 C6 -92 43 DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A C7 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 C7 7C C7 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 -30 40 94 C7 0D 12 84 12 14 C4 02 0D 0A 00 5E C7 -62 C8 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 C6 -01 40 2E 4E 30 4D E0 C7 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 21 B2 21 30 4D 8C C7 01 23 1B 42 -DC 21 2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 -18 42 B2 21 C8 4A 00 00 30 4D 1C C8 02 23 53 00 -0D 12 84 12 1E C8 58 C8 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C C8 02 23 3E 00 9F 42 B2 21 -00 00 3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 C7 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 C8 50 C8 EE C4 90 C8 6C C8 5E C7 16 CC -22 C7 62 C8 42 C7 01 2E 0E 93 E3 37 38 43 E2 3F -8A C8 82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 -14 C4 5C CB 0A C4 22 00 2E C9 FC C8 B2 40 20 00 -B4 21 6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 -30 4D D6 C8 82 2E 22 00 0D 12 84 12 E6 C8 0A C4 -5E C7 5C CB 62 C8 1A C6 04 57 4F 52 44 00 3C 40 -C0 21 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A -C4 21 1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 -D4 C4 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 -B0 CA 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 CA 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 3E 4F 30 4D 5A CB 87 4C -49 54 45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 -C6 21 A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 C8 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C C8 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC C4 16 CC 2E C9 -D2 CB 9C 26 3D 40 DA CB DE 3E DC CB 0A 4E 3E 4F -3D 40 F6 CB 36 27 3D 40 CC CB 1A E2 BE 21 B6 27 -0E 12 3E 4F 30 41 F8 CB 3E 4F 3D 40 CC CB BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 CD CC 3F 00 CC 86 12 20 00 E8 C7 05 41 4C 4C -4F 54 82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 -31 40 E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 -90 C7 BC C4 C6 CB C6 C7 F8 C7 14 C4 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF -28 C4 00 C8 14 C4 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A C5 3A C4 40 CC 1C CC 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 C8 0A C4 2A C5 5C CB 62 C8 -90 C9 01 27 0D 12 84 12 16 CC 2E C9 96 C9 34 C4 -14 CC 62 C8 00 00 83 5B 27 5D 0D 12 84 12 94 CC -0A C4 0A C4 5C CB 5C CB 62 C8 A6 CC 81 5B 82 43 -BE 21 30 4D 0E C8 01 5D B2 43 BE 21 30 4D C6 CC -81 5C 92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 CC 2E C9 96 C9 -AA C7 34 C4 14 CC F8 C7 34 C4 08 CD 0A C4 0A C4 -5C CB 5C CB 0A C4 5C CB 5C CB 62 C8 BC CC 01 3A -30 12 58 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 -16 CC 2E C9 26 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 -2A 52 82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 -18 42 B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 C5 0E CD 81 3B 82 93 -BE 21 97 27 0D 12 84 12 0A C4 62 C8 5C CB 6A CD -BE CC 62 C8 BC CB 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 21 F8 D0 80 00 00 00 30 4D A6 CB 06 43 -52 45 41 54 45 00 B0 12 14 CD BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE CD 04 43 4F 44 45 00 B0 12 -14 CD A2 82 C6 21 0D 12 84 12 06 D0 E0 CF 62 C8 -B6 CD 07 48 44 4E 43 4F 44 45 B2 40 E4 CF DA 21 -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A CD 20 D0 3E D0 62 C8 00 00 05 43 4F 4C 4F 4E -1A 42 C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 21 B2 43 BE 21 0D 12 84 12 20 D0 3E D0 -62 C8 00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 -C6 21 EB 3F 02 CE 85 48 49 32 4C 4F 0D 12 84 12 -28 C4 AE CF 5C CB BE CC F6 CD 62 C8 9C CD 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E CE 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A C4 00 00 DA C7 16 CC -2E C9 AC CB A2 C7 34 C4 16 CF B0 C7 14 C4 06 5B -54 48 45 4E 5D 00 88 CE F0 CE AC CE CE CE 62 C8 -B0 C7 14 C4 06 5B 45 4C 53 45 5D 00 88 CE 06 CF -AC CE CC CE 62 C8 14 C4 04 5B 49 46 5D 00 88 CE -CE CE 3A C4 CC CE 84 C7 14 C4 05 0D 0A 6B 6F 20 -5E C7 BC C4 AC C4 3A C4 CE CE BC CE 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C CF -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 CC -2E C9 96 C9 3A CF 62 C8 40 CF 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A CF F2 C7 62 C8 -72 CF B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E CB 06 4D 41 52 4B 45 52 00 B0 12 14 CD BA 40 -85 12 FC FF BA 40 70 CF FE FF 28 83 8A 48 00 00 -BA 40 AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 -30 4D 0A C4 CA 21 EA C7 62 C8 85 12 B2 CF 7A CC -E8 CD 2E C7 92 CC 66 CE F8 C6 82 CF 14 C9 AA D0 -BE D0 9E C8 28 C9 00 00 5A CF D0 CC F6 C9 00 00 -85 12 B2 CF 60 D6 C6 D6 08 D6 16 D7 CE D5 00 00 -9A D3 00 00 DE D7 C2 D7 32 D6 70 D6 AA D4 00 00 -00 00 32 D7 DE CF 3A 40 0C 00 39 40 D6 21 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 -CA 21 DA 21 30 4D BA CF 38 D0 3E D0 4E D0 1A 42 -20 18 82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC CC 09 50 57 52 5F 53 54 41 54 45 85 12 -46 D0 EA D7 E2 C8 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 D0 F3 3F 84 D0 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 21 92 D0 30 4D 96 D0 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C D1 FE FF -29 83 B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 -22 C6 B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 -E0 20 3F 40 80 20 39 40 00 10 29 83 89 43 00 20 -FC 23 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 -26 02 F2 40 FD 00 22 02 E2 D2 24 02 B2 40 00 A5 -60 01 B2 40 B4 00 80 01 92 43 82 01 B2 40 1E 00 -84 01 39 40 10 00 B2 D0 10 00 86 01 38 40 17 11 -18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 -1E D2 5E 01 B0 12 F8 C4 20 C6 38 40 C0 21 0A 4E -39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E -FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 -0E 12 12 12 C4 21 84 12 2E C9 96 C9 F2 C7 34 C4 -DA D1 52 CA 34 C4 F4 D1 EE D1 DC D1 3C 4E 3C 80 -87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 -1B 17 30 41 F6 D1 B2 41 C4 21 3E 41 84 12 0A C4 -2B 00 2E C9 96 C9 F2 C7 34 C4 12 D2 52 CA 34 C4 -14 CC BC C7 2E C9 52 CA 34 C4 14 CC 1E D2 3E 5F -E7 3F 3E 40 28 00 B0 12 BE D1 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 -02 20 30 40 82 CD 1C 15 12 12 C4 21 92 53 C4 21 -84 12 2E C9 52 CA 34 C4 66 D2 5C D2 21 53 3E 90 -10 00 C6 2B 7F 2D 68 D2 B2 41 C4 21 C1 3F 0D 12 -84 12 16 CC 9A D1 78 D2 0C 43 1B 42 C6 21 A2 53 -C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 -B0 12 BE D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 -1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 -2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 -3C 40 10 02 92 53 C4 21 B0 12 BE D1 ED 3F 7A 90 -40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 46 D2 -0C 20 3C 50 10 00 3E 40 2B 00 B0 12 46 D2 92 92 -C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F -B0 12 46 D2 FA 23 3C 50 10 00 B0 12 22 D2 EF 3F -0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 16 CC -9A D1 44 D3 FE 90 26 00 00 00 3E 40 20 00 03 20 -3C 50 82 00 C7 3F B0 12 46 D2 E0 23 3C 50 80 00 -B0 12 22 D2 DB 3F 00 00 04 52 45 54 49 00 0D 12 -84 12 0A C4 00 13 5C CB 62 C8 0A C4 2C 00 6E D2 -3A D3 84 D3 09 4B 2E 4E 0E DC A2 3F 54 CE 03 4D -4F 56 85 12 7A D3 00 40 8E D3 05 4D 4F 56 2E 42 -85 12 7A D3 40 40 00 00 03 41 44 44 85 12 7A D3 -00 50 A8 D3 05 41 44 44 2E 42 85 12 7A D3 40 50 -B4 D3 04 41 44 44 43 00 85 12 7A D3 00 60 C2 D3 -06 41 44 44 43 2E 42 00 85 12 7A D3 40 60 68 D3 -04 53 55 42 43 00 85 12 7A D3 00 70 E0 D3 06 53 -55 42 43 2E 42 00 85 12 7A D3 40 70 EE D3 03 53 -55 42 85 12 7A D3 00 80 FE D3 05 53 55 42 2E 42 -85 12 7A D3 40 80 2A CE 03 43 4D 50 85 12 7A D3 -00 90 18 D4 05 43 4D 50 2E 42 85 12 7A D3 40 90 -14 CE 04 44 41 44 44 00 85 12 7A D3 00 A0 32 D4 -06 44 41 44 44 2E 42 00 85 12 7A D3 40 A0 24 D4 -03 42 49 54 85 12 7A D3 00 B0 50 D4 05 42 49 54 -2E 42 85 12 7A D3 40 B0 5C D4 03 42 49 43 85 12 -7A D3 00 C0 6A D4 05 42 49 43 2E 42 85 12 7A D3 -40 C0 76 D4 03 42 49 53 85 12 7A D3 00 D0 84 D4 -05 42 49 53 2E 42 85 12 7A D3 40 D0 00 00 03 58 -4F 52 85 12 7A D3 00 E0 9E D4 05 58 4F 52 2E 42 -85 12 7A D3 40 E0 D0 D3 03 41 4E 44 85 12 7A D3 -00 F0 B8 D4 05 41 4E 44 2E 42 85 12 7A D3 40 F0 -16 CC 6E D2 D6 D4 0A 4C 3C F0 70 00 8A 10 3A F0 -0F 00 0C DA 4F 3F 0A D4 03 52 52 43 85 12 D0 D4 -00 10 E8 D4 05 52 52 43 2E 42 85 12 D0 D4 40 10 -F4 D4 04 53 57 50 42 00 85 12 D0 D4 80 10 02 D5 -03 52 52 41 85 12 D0 D4 00 11 10 D5 05 52 52 41 -2E 42 85 12 D0 D4 40 11 1C D5 03 53 58 54 85 12 -D0 D4 80 11 00 00 04 50 55 53 48 00 85 12 D0 D4 -00 12 36 D5 06 50 55 53 48 2E 42 00 85 12 D0 D4 -40 12 90 D4 04 43 41 4C 4C 00 85 12 D0 D4 80 12 -1A 53 0E 4A 0D 12 84 12 D8 C8 14 C4 0D 6F 75 74 -20 6F 66 20 62 6F 75 6E 64 73 36 C5 2A D5 03 53 -3E 3D 86 12 00 38 7E D5 02 53 3C 00 86 12 00 34 -44 D5 03 30 3E 3D 86 12 00 30 92 D5 02 30 3C 00 -86 12 00 30 00 00 02 55 3C 00 86 12 00 2C A6 D5 -03 55 3E 3D 86 12 00 28 9C D5 03 30 3C 3E 86 12 -00 24 BA D5 02 30 3D 00 86 12 00 20 00 00 02 49 -46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A -30 4D B0 D5 04 54 48 45 4E 00 1A 42 C6 21 08 4E -3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F -88 DA 00 00 30 4D 40 D4 04 45 4C 53 45 00 1A 42 -C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A -00 00 E3 3F 54 D5 05 42 45 47 49 4E 30 40 28 C4 -E4 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 -C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 -FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D C4 D4 -05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 -05 57 48 49 4C 45 0D 12 84 12 D2 D5 BC C7 62 C8 -88 D5 06 52 45 50 45 41 54 00 0D 12 84 12 66 D6 -EA D5 62 C8 96 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 -C4 21 CB 2F 98 42 C6 21 00 00 30 4D 26 D6 03 42 -57 31 85 12 94 D6 00 00 AE D6 03 42 57 32 85 12 -94 D6 00 00 BA D6 03 42 57 33 85 12 94 D6 00 00 -D2 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B -BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D -00 00 03 46 57 31 85 12 D0 D6 00 00 F2 D6 03 46 -57 32 85 12 D0 D6 00 00 FE D6 03 46 57 33 85 12 -D0 D6 00 00 0A D7 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C 0D 12 84 12 94 CC F0 CB 62 C8 -00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 -00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 16 CC -9A D1 54 D7 92 53 C4 21 3E 40 2C 00 84 12 2E C9 -52 CA 34 C4 14 CC 30 D3 6A D7 0A 4E 3E 4F 1A 83 -F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A -08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E -8A 10 5A 06 A6 3E 82 D6 04 52 52 43 4D 00 85 12 -4E D7 50 00 98 D7 04 52 52 41 4D 00 85 12 4E D7 -50 01 A6 D7 04 52 4C 41 4D 00 85 12 4E D7 50 02 -B4 D7 04 52 52 55 4D 00 85 12 4E D7 50 03 C4 D5 -05 50 55 53 48 4D 85 12 4E D7 00 15 D0 D7 04 50 -4F 50 4D 00 85 12 4E D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 96 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1C D1 -q diff --git a/binaries/CHIPSTICK_FR2433_8MHz_115200.txt b/binaries/CHIPSTICK_FR2433_8MHz_115200.txt new file mode 100644 index 0000000..a5a2cef --- /dev/null +++ b/binaries/CHIPSTICK_FR2433_8MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A0 19 +BA C6 7E C5 84 C5 54 C5 2A C7 18 D7 D0 CF 8A CF +8A CF A0 C6 5E C7 26 C7 3C 21 E0 20 7E C9 B6 C4 +C4 C4 9A C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +2A C7 18 D7 D0 CF 8A CF 8A CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F8 3C 0E 93 3E 4F +8D 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9E C6 B2 49 +5C C7 B2 49 24 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 44 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 2A C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 A4 C8 AC C4 52 C5 6C C7 1E C4 04 1B +5B 37 6D 00 8E C7 8E C7 1E C4 04 1B 5B 30 6D 00 +8E C7 DA CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 6C C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 8E C7 F2 C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 8E C7 0A C4 40 FF 32 C4 +BA C8 BE C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 10 00 00 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 +E0 20 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 +26 02 F2 40 FD 00 22 02 E2 D2 24 02 B2 40 00 A5 +60 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 F2 C3 +82 01 F2 D0 06 00 82 01 B2 40 F4 00 84 01 39 40 +80 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 C4 +86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 A0 C6 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +FE C6 3C 40 0A C7 5D 15 A3 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D2 22 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 00 C7 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 26 C7 30 12 3C C7 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C2 22 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 C6 C6 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 5E C7 08 4E +3E 4F C7 3F 54 C7 08 45 43 48 4F 00 B2 40 C2 48 +F8 C6 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D F8 C6 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 9E C7 29 4F 8F 4E 00 00 7E 49 DE 3F A0 C7 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 79 22 +F9 98 00 00 76 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 6D 22 9B 24 1E C7 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A C4 00 00 BE C8 B0 C7 +02 CA BC CC B0 C4 2C C8 14 C4 06 5B 54 48 45 4E +5D 00 B4 C7 0A C8 D0 C7 EE C7 14 C4 06 5B 45 4C +53 45 5D 00 B4 C7 1C C8 D0 C7 EC C7 1E C4 04 5B +49 46 5D 00 B4 C7 EE C7 B2 C4 EC C7 1E C4 05 0D +6B 6F 20 0A 8E C7 9A C4 84 C4 B2 C4 EE C7 DC C7 +0D 5B 54 48 45 4E 5D 00 30 4D 40 C8 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 4C C8 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 B0 C7 02 CA 6A CA +0E CC 7E C9 5C C8 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 B0 C7 02 CA 6A CA 8E C8 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D 94 C6 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A C4 1E C4 6C CC 0A C4 22 00 02 CA +02 C9 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 76 C7 05 2E 22 00 0D 12 84 12 +EC C8 0A C4 8E C7 6C CC 7E C9 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D E8 C8 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 3A C9 04 23 53 00 0D 12 +84 12 3C C9 76 C9 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 6A C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 84 C9 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 66 C7 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 30 C9 B0 C7 +9E C9 6E C9 9A C8 AC C9 88 C9 8E C7 7E C9 18 C9 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D F0 C9 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 74 CB +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 76 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 2C C9 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 C4 B0 C7 02 CA B0 C4 46 CD 6A CA 30 CC +0A 4E 3E 4F 3D 40 4A CC 6D 27 3D 40 24 CC 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 4C CC 3E 4F 3D 40 +24 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 22 CE 2A 3C 14 CC 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 6A CC 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D A6 C9 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D CC C8 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E C4 02 0D 0A 00 8E C7 94 C4 1E CC AC C8 +D6 C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 C5 32 C4 0A C4 40 FF DE C8 1E C4 09 46 52 41 +4D 20 66 75 6C 6C 08 C5 B2 C4 E2 CC CC CC 0D 41 +42 4F 52 54 22 00 0D 12 84 12 EC C8 0A C4 08 C5 +6C CC 7E C9 FC C9 02 27 0D 12 84 12 B0 C7 02 CA +6A CA B0 C4 48 CD 10 C9 54 CC 76 C8 07 5B 27 5D +0D 12 84 12 38 CD 0A C4 0A C4 6C CC 6C CC 7E C9 +4C CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D C4 C8 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 B0 C7 02 CA 6A CA B0 C4 48 CD D6 C8 +AC C4 A0 CD 0A C4 0A C4 6C CC 6C CC 0A C4 6C CC +6C CC 7E C9 00 00 02 3A 30 12 F6 CD 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 B0 C7 02 CA BE CD 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 C5 62 CD 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A C4 7E C9 6C CC 08 CE 64 CD 7E C9 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D B6 CC 0C 43 52 45 41 54 45 00 B0 12 +AC CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 88 C7 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D A6 CD 0E 3A 4E 4F 4E 41 +4D 45 30 12 F6 CD 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 40 CE +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 38 CD +C2 CE 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 50 CD +0A C4 C4 CE 6C CC 7E C9 56 CE 08 43 4F 44 45 00 +B0 12 AC CD A2 82 C8 21 61 3C 98 C9 0E 48 44 4E +43 4F 44 45 B2 40 B0 CF CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 08 CE 0E CF 3D 41 +92 42 D0 21 CC 21 5D 3C DA CE 0E 43 4F 44 45 4E +4E 4D 30 12 E4 CE B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F EC CE 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 78 CF B2 40 8A CF D0 21 82 4E +CE 21 30 40 10 C9 85 12 76 CF 76 CD 1E CD 08 D0 +1A CF 70 CE BA C9 64 CA 36 CD 5E CF B0 CE 8A CE +26 CE 7E CC 92 D0 BC CA 00 00 00 00 85 12 76 CF +0C D7 90 D5 F0 D6 B8 D4 14 D5 62 D5 3E D6 4A D6 +DA D3 FE D4 00 00 00 00 4C CF CA D2 00 00 66 D6 +AA CF B2 40 8A CF CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 DE CF 30 4D F0 CF 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 DE CF 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 08 C6 FE FF 29 83 B9 40 F2 C5 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E4 FF +3B 40 10 00 3A 40 3A 18 B0 12 E2 CF 82 43 4A 18 +C7 3F 84 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +6C CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 B0 C7 02 CA 6A CA AC C4 B0 D0 A4 C8 44 CC +B2 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 AC CD BA 40 +85 12 FC FF BA 40 82 D0 FE FF 28 83 8A 48 00 00 +BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 02 CA 6A CA AC C4 1C D1 FC D0 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 82 D0 +00 00 01 20 3E 52 2E 83 21 53 30 41 14 CB AC C4 +24 D1 18 D1 26 D1 B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 EC D0 15 20 3E 40 +2B 00 B0 12 EC D0 06 20 3E 40 2D 00 B0 12 EC D0 +92 83 C6 21 0E 12 1E 41 02 00 84 12 02 CA 14 CB +AC C4 48 CD 66 D1 3E 51 3A 17 30 41 B0 12 2C D1 +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 02 CA 14 CB +AC C4 9E D1 96 D1 3E 90 10 00 E6 2B 7C 2D A0 D1 +A2 41 C6 21 E1 3F 03 20 B0 12 84 D1 43 3C 7A 90 +23 00 24 20 B0 12 34 D1 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 34 D1 F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 80 D1 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 84 D1 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +6C D1 F2 3F 03 20 B0 12 84 D1 F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 6C D1 +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 6C CC +7E C9 0A C4 2C 00 62 D2 A6 D1 B0 C7 6C D2 44 D2 +B2 D2 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 A2 D2 00 40 BE D2 0A 4D 4F 56 2E 42 +85 12 A2 D2 40 40 00 00 06 41 44 44 85 12 A2 D2 +00 50 D8 D2 0A 41 44 44 2E 42 85 12 A2 D2 40 50 +E4 D2 08 41 44 44 43 00 85 12 A2 D2 00 60 F2 D2 +0C 41 44 44 43 2E 42 00 85 12 A2 D2 40 60 2A CF +08 53 55 42 43 00 85 12 A2 D2 00 70 10 D3 0C 53 +55 42 43 2E 42 00 85 12 A2 D2 40 70 1E D3 06 53 +55 42 85 12 A2 D2 00 80 2E D3 0A 53 55 42 2E 42 +85 12 A2 D2 40 80 3A D3 06 43 4D 50 85 12 A2 D2 +00 90 48 D3 0A 43 4D 50 2E 42 85 12 A2 D2 40 90 +00 00 08 44 41 44 44 00 85 12 A2 D2 00 A0 62 D3 +0C 44 41 44 44 2E 42 00 85 12 A2 D2 40 A0 90 D2 +06 42 49 54 85 12 A2 D2 00 B0 80 D3 0A 42 49 54 +2E 42 85 12 A2 D2 40 B0 8C D3 06 42 49 43 85 12 +A2 D2 00 C0 9A D3 0A 42 49 43 2E 42 85 12 A2 D2 +40 C0 A6 D3 06 42 49 53 85 12 A2 D2 00 D0 B4 D3 +0A 42 49 53 2E 42 85 12 A2 D2 40 D0 00 00 06 58 +4F 52 85 12 A2 D2 00 E0 CE D3 0A 58 4F 52 2E 42 +85 12 A2 D2 40 E0 00 D3 06 41 4E 44 85 12 A2 D2 +00 F0 E8 D3 0A 41 4E 44 2E 42 85 12 A2 D2 40 F0 +B0 C7 62 D2 A6 D1 08 D4 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F C0 D3 06 52 52 43 85 12 +00 D4 00 10 1A D4 0A 52 52 43 2E 42 85 12 00 D4 +40 10 54 D3 08 53 57 50 42 00 85 12 00 D4 80 10 +26 D4 06 52 52 41 85 12 00 D4 00 11 42 D4 0A 52 +52 41 2E 42 85 12 00 D4 40 11 34 D4 06 53 58 54 +85 12 00 D4 80 11 00 00 08 50 55 53 48 00 85 12 +00 D4 00 12 68 D4 0C 50 55 53 48 2E 42 00 85 12 +00 D4 40 12 5C D4 08 43 41 4C 4C 00 85 12 00 D4 +80 12 1A 53 0E 4A 84 12 F2 C9 1E C4 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 C5 86 D4 06 53 +3E 3D 86 12 00 38 AE D4 04 53 3C 00 86 12 00 34 +76 D4 06 30 3E 3D 86 12 00 30 C2 D4 04 30 3C 00 +86 12 00 30 FE CE 04 55 3C 00 86 12 00 2C D6 D4 +06 55 3E 3D 86 12 00 28 CC D4 06 30 3C 3E 86 12 +00 24 EA D4 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 70 D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D E0 D4 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 4E D4 0A 42 45 47 49 4E 30 40 32 C4 +38 D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D F4 D3 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 02 D5 98 C8 7E C9 +56 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 96 D5 +1A D5 7E C9 C6 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D B2 D5 06 42 +57 31 85 12 C4 D5 00 00 DE D5 06 42 57 32 85 12 +C4 D5 00 00 EA D5 06 42 57 33 85 12 C4 D5 00 00 +02 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 00 D6 00 00 +26 D6 06 46 57 32 85 12 00 D6 00 00 32 D6 06 46 +57 33 85 12 00 D6 00 00 A0 D5 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 38 CD +44 CC 7E C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 6C D2 0A C4 2C 00 02 CA 14 CB AC C4 48 CD +B0 C7 62 D2 44 D2 98 D6 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E F6 D5 08 52 52 43 4D 00 85 12 82 D6 +50 00 C6 D6 08 52 52 41 4D 00 85 12 82 D6 50 01 +D4 D6 08 52 4C 41 4D 00 85 12 82 D6 50 02 E2 D6 +08 52 52 55 4D 00 85 12 82 D6 50 03 F4 D4 0A 50 +55 53 48 4D 85 12 82 D6 00 15 FE D6 08 50 4F 50 +4D 00 85 12 82 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 BA C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 08 C6 +q diff --git a/binaries/CHIPSTICK_FR2433_8MHz_I2C.txt b/binaries/CHIPSTICK_FR2433_8MHz_I2C.txt index d287915..1a9cf6e 100644 --- a/binaries/CHIPSTICK_FR2433_8MHz_I2C.txt +++ b/binaries/CHIPSTICK_FR2433_8MHz_I2C.txt @@ -1,334 +1,322 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF D6 D7 F2 CF 34 01 -10 00 41 07 B6 C5 AA C4 B8 C5 8C C5 84 C6 D6 D7 -F2 CF 72 C6 82 C7 00 C7 DC C6 3C 21 50 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 03 +B4 C6 56 C5 56 C5 58 C5 44 C5 F4 D6 AC CF 66 CF +66 CF A2 C6 26 C7 FE C6 3C 21 E0 20 5A C9 B6 C4 +C4 C4 76 C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 F4 D6 AC CF 66 CF 66 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 70 C6 B2 49 80 C7 B2 49 FE C6 B2 49 DA C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 D0 C7 18 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 98 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C C7 90 C8 4C C7 -14 C4 04 1B 5B 30 6D 00 4C C7 18 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 -B0 12 8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 -07 0D 0A 1B 5B 37 6D 40 4C C7 0A C4 02 18 D0 C7 -C6 C8 0A C4 23 00 FC C6 C6 C8 14 C4 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C C7 0A C4 40 FF 28 C4 C4 C7 -90 C8 14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 -3A C4 7E C5 00 00 06 41 43 43 45 50 54 00 30 40 -72 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 -B7 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F9 3C 0E 93 3E 4F +7B 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A0 C6 B2 49 +24 C7 B2 49 FC C6 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 20 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 80 C8 AC C4 +42 C5 3E C7 1E C4 05 1B 5B 37 6D 40 6A C7 0A C4 +02 18 A2 C8 CE C9 6A C7 1E C4 04 1B 5B 30 6D 00 +6A C7 B6 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 3E C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 6A C7 0A C4 02 18 A2 C8 CE C9 0A C4 23 00 +22 C7 CE C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +6A C7 0A C4 40 FF 32 C4 96 C8 9A C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +10 00 00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +CC 01 31 40 E0 20 3F 40 80 20 B2 43 02 02 B2 D3 +06 02 D2 43 24 02 F2 D3 26 02 F2 40 FD 00 22 02 +B2 40 00 A5 60 01 B2 D0 10 00 86 01 B2 40 00 02 +88 01 F2 C3 82 01 F2 D0 06 00 82 01 B2 40 F4 00 +84 01 39 40 80 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 B0 12 +D0 C4 80 C5 00 00 0C 41 43 43 45 50 54 00 30 40 +A2 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 A6 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 +9F 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC C6 2F 83 8F 4E -00 00 58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 -4C 05 30 4D 00 00 04 45 4D 49 54 00 30 40 00 C7 -08 4E 3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D -F6 C6 04 45 43 48 4F 00 B2 40 C2 48 0A C7 82 43 -DE 21 38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A C7 92 43 DE 21 -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE C6 6A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 -82 C7 0D 12 84 12 14 C4 02 0D 0A 00 4C C7 50 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 C6 01 40 -2E 4E 30 4D CE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 7A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 0A C8 02 23 53 00 0D 12 -84 12 0C C8 46 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 C8 3E C8 EE C4 7E C8 5A C8 4C C7 04 CC FC C6 -50 C8 2E C7 01 2E 0E 93 E3 37 38 43 E2 3F 78 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -4A CB 0A C4 22 00 1C C9 EA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -C4 C8 82 2E 22 00 0D 12 84 12 D4 C8 0A C4 4C C7 -4A CB 50 C8 FA C5 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 FE C6 58 43 +B0 12 46 C5 2F 83 8F 4E 00 00 92 B3 6C 05 FD 27 +1E 42 4C 05 B0 12 44 C5 30 4D 00 00 08 45 4D 49 +54 00 30 40 26 C7 08 4E 3E 4F A2 B3 6C 05 FD 27 +C2 48 4E 05 30 4D 1C C7 08 45 43 48 4F 00 B2 40 +C2 48 30 C7 38 40 05 00 B0 12 46 C5 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 30 C7 28 42 +F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 7A C7 +29 4F 8F 4E 00 00 7E 49 D4 3F 7C C7 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 8B 22 F9 98 00 00 +88 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 7F 22 9B 24 F6 C6 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A C4 00 00 9A C8 8C C7 DE C9 98 CC +B0 C4 08 C8 14 C4 06 5B 54 48 45 4E 5D 00 90 C7 +E6 C7 AC C7 CA C7 14 C4 06 5B 45 4C 53 45 5D 00 +90 C7 F8 C7 AC C7 C8 C7 1E C4 04 5B 49 46 5D 00 +90 C7 CA C7 B2 C4 C8 C7 1E C4 05 0D 6B 6F 20 0A +6A C7 9A C4 84 C4 B2 C4 CA C7 B8 C7 0D 5B 54 48 +45 4E 5D 00 30 4D 1C C8 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 28 C8 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 8C C7 DE C9 46 CA EA CB 5A C9 +38 C8 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 8C C7 DE C9 46 CA 6A C8 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D 96 C6 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 C5 05 53 22 00 82 43 C0 21 0D 12 84 12 +0A C4 1E C4 48 CC 0A C4 22 00 DE C9 DE C8 B2 40 +20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 +30 4D 50 C7 05 2E 22 00 0D 12 84 12 C8 C8 0A C4 +6A C7 48 CC 5A C9 00 00 04 3C 23 00 B2 40 B2 21 +B2 21 30 4D C4 C8 02 23 1B 42 BE 21 2C 4F 2F 83 +B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A +00 00 30 4D 16 C9 04 23 53 00 0D 12 84 12 18 C9 +52 C9 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 46 C9 +04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +60 C9 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 38 C7 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 0C C9 8C C7 7A C9 4A C9 +76 C8 88 C9 64 C9 6A C7 5A C9 F4 C8 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 +C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D CC C9 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9E CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 48 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 04 CC 1C C9 C0 CB -9C 26 3D 40 C8 CB DE 3E CA CB 0A 4E 3E 4F 3D 40 -E4 CB 36 27 3D 40 BA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 E6 CB 3E 4F 3D 40 BA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 CD -CC 3F EE CB 86 12 20 00 D6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 7E C7 -BC C4 B4 CB B4 C7 E6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -EE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 2E CC 0A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 C8 0A C4 2A C5 4A CB 50 C8 7E C9 -01 27 0D 12 84 12 04 CC 1C C9 84 C9 34 C4 02 CC -50 C8 00 00 83 5B 27 5D 0D 12 84 12 82 CC 0A C4 -0A C4 4A CB 4A CB 50 C8 94 CC 81 5B 82 43 BE 21 -30 4D FC C7 01 5D B2 43 BE 21 30 4D B4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 CC 1C C9 84 C9 98 C7 -34 C4 02 CC E6 C7 34 C4 F6 CC 0A C4 0A C4 4A CB -4A CB 0A C4 4A CB 4A CB 50 C8 AA CC 01 3A 30 12 -46 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 04 CC -1C C9 14 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 FC CC 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 50 C8 4A CB 58 CD AC CC -50 C8 AA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D 94 CB 06 43 52 45 -41 54 45 00 B0 12 02 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC CD 04 43 4F 44 45 00 B0 12 02 CD -A2 82 C6 21 0D 12 84 12 F4 CF CE CF 50 C8 A4 CD -07 48 44 4E 43 4F 44 45 B2 40 D2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 CD -0E D0 2C D0 50 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 0E D0 2C D0 50 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F F0 CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -9C CF 4A CB AC CC E4 CD 50 C8 8A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 C8 C7 04 CC 1C C9 -9A CB 90 C7 34 C4 04 CF 9E C7 14 C4 06 5B 54 48 -45 4E 5D 00 76 CE DE CE 9A CE BC CE 50 C8 9E C7 -14 C4 06 5B 45 4C 53 45 5D 00 76 CE F4 CE 9A CE -BA CE 50 C8 14 C4 04 5B 49 46 5D 00 76 CE BC CE -3A C4 BA CE 72 C7 14 C4 05 0D 0A 6B 6F 20 4C C7 -BC C4 AC C4 3A C4 BC CE AA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 CC 1C C9 -84 C9 28 CF 50 C8 2E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 CF E0 C7 50 C8 60 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C CB -06 4D 41 52 4B 45 52 00 B0 12 02 CD BA 40 85 12 -FC FF BA 40 5E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 D8 C7 50 C8 85 12 A0 CF 68 CC D6 CD -12 C7 80 CC 54 CE D4 C6 70 CF 02 C9 98 D0 AC D0 -8C C8 16 C9 00 00 48 CF BE CC E4 C9 00 00 85 12 -A0 CF 4C D6 B2 D6 F4 D5 02 D7 BA D5 00 00 86 D3 -00 00 CA D7 AE D7 1E D6 5C D6 96 D4 00 00 00 00 -1E D7 CC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D A8 CF 26 D0 2C D0 3C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA CC 09 50 57 52 5F 53 54 41 54 45 85 12 34 D0 -D6 D7 D0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 D0 F3 3F 72 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 80 D0 30 4D 84 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A D1 FE FF 29 83 -B9 40 E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 02 C6 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 26 02 -F2 40 FD 00 22 02 B2 40 00 A5 60 01 B2 40 F3 00 -80 01 B2 40 07 00 82 01 B2 40 FC 00 84 01 39 40 -80 00 B2 D0 10 00 86 01 38 40 17 11 18 83 FE 23 -19 83 FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 -B0 12 F8 C4 00 C6 38 40 C0 21 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 -C4 21 84 12 1C C9 84 C9 E0 C7 34 C4 C6 D1 40 CA -34 C4 E0 D1 DA D1 C8 D1 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -E2 D1 B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1C C9 -84 C9 E0 C7 34 C4 FE D1 40 CA 34 C4 02 CC AA C7 -1C C9 40 CA 34 C4 02 CC 0A D2 3E 5F E7 3F 3E 40 -28 00 B0 12 AA D1 19 42 C6 21 A2 53 C6 21 89 4E -00 00 3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 -70 CD 1C 15 12 12 C4 21 92 53 C4 21 84 12 1C C9 -40 CA 34 C4 52 D2 48 D2 21 53 3E 90 10 00 C6 2B -7F 2D 54 D2 B2 41 C4 21 C1 3F 0D 12 84 12 04 CC -86 D1 64 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E -3E 4F 7A 90 23 00 27 20 92 53 C4 21 B0 12 AA D1 -3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 -3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 -3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 -3C 40 30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 -92 53 C4 21 B0 12 AA D1 ED 3F 7A 90 40 00 16 20 -3C 40 20 00 92 53 C4 21 B0 12 32 D2 0C 20 3C 50 -10 00 3E 40 2B 00 B0 12 32 D2 92 92 C0 21 C4 21 -02 24 92 53 C4 21 8E 10 0C 5E DA 3F B0 12 32 D2 -FA 23 3C 50 10 00 B0 12 0E D2 EF 3F 0C 43 1B 42 -C6 21 A2 53 C6 21 0D 12 84 12 04 CC 86 D1 30 D3 -FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 -C7 3F B0 12 32 D2 E0 23 3C 50 80 00 B0 12 0E D2 -DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 -00 13 4A CB 50 C8 0A C4 2C 00 5A D2 26 D3 70 D3 -09 4B 2E 4E 0E DC A2 3F 42 CE 03 4D 4F 56 85 12 -66 D3 00 40 7A D3 05 4D 4F 56 2E 42 85 12 66 D3 -40 40 00 00 03 41 44 44 85 12 66 D3 00 50 94 D3 -05 41 44 44 2E 42 85 12 66 D3 40 50 A0 D3 04 41 -44 44 43 00 85 12 66 D3 00 60 AE D3 06 41 44 44 -43 2E 42 00 85 12 66 D3 40 60 54 D3 04 53 55 42 -43 00 85 12 66 D3 00 70 CC D3 06 53 55 42 43 2E -42 00 85 12 66 D3 40 70 DA D3 03 53 55 42 85 12 -66 D3 00 80 EA D3 05 53 55 42 2E 42 85 12 66 D3 -40 80 18 CE 03 43 4D 50 85 12 66 D3 00 90 04 D4 -05 43 4D 50 2E 42 85 12 66 D3 40 90 02 CE 04 44 -41 44 44 00 85 12 66 D3 00 A0 1E D4 06 44 41 44 -44 2E 42 00 85 12 66 D3 40 A0 10 D4 03 42 49 54 -85 12 66 D3 00 B0 3C D4 05 42 49 54 2E 42 85 12 -66 D3 40 B0 48 D4 03 42 49 43 85 12 66 D3 00 C0 -56 D4 05 42 49 43 2E 42 85 12 66 D3 40 C0 62 D4 -03 42 49 53 85 12 66 D3 00 D0 70 D4 05 42 49 53 -2E 42 85 12 66 D3 40 D0 00 00 03 58 4F 52 85 12 -66 D3 00 E0 8A D4 05 58 4F 52 2E 42 85 12 66 D3 -40 E0 BC D3 03 41 4E 44 85 12 66 D3 00 F0 A4 D4 -05 41 4E 44 2E 42 85 12 66 D3 40 F0 04 CC 5A D2 -C2 D4 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA -4F 3F F6 D3 03 52 52 43 85 12 BC D4 00 10 D4 D4 -05 52 52 43 2E 42 85 12 BC D4 40 10 E0 D4 04 53 -57 50 42 00 85 12 BC D4 80 10 EE D4 03 52 52 41 -85 12 BC D4 00 11 FC D4 05 52 52 41 2E 42 85 12 -BC D4 40 11 08 D5 03 53 58 54 85 12 BC D4 80 11 -00 00 04 50 55 53 48 00 85 12 BC D4 00 12 22 D5 -06 50 55 53 48 2E 42 00 85 12 BC D4 40 12 7C D4 -04 43 41 4C 4C 00 85 12 BC D4 80 12 1A 53 0E 4A -0D 12 84 12 C6 C8 14 C4 0D 6F 75 74 20 6F 66 20 -62 6F 75 6E 64 73 36 C5 16 D5 03 53 3E 3D 86 12 -00 38 6A D5 02 53 3C 00 86 12 00 34 30 D5 03 30 -3E 3D 86 12 00 30 7E D5 02 30 3C 00 86 12 00 30 -00 00 02 55 3C 00 86 12 00 2C 92 D5 03 55 3E 3D -86 12 00 28 88 D5 03 30 3C 3E 86 12 00 24 A6 D5 -02 30 3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 -C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D 9C D5 -04 54 48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 -29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 -30 4D 2C D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 -00 3C 00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F -40 D5 05 42 45 47 49 4E 30 40 28 C4 D0 D5 05 55 -4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 -0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA -89 48 00 00 A2 53 C6 21 30 4D B0 D4 05 41 47 41 -49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 -4C 45 0D 12 84 12 BE D5 AA C7 50 C8 74 D5 06 52 -45 50 45 41 54 00 0D 12 84 12 52 D6 D6 D5 50 C8 -82 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F -98 42 C6 21 00 00 30 4D 12 D6 03 42 57 31 85 12 -80 D6 00 00 9A D6 03 42 57 32 85 12 80 D6 00 00 -A6 D6 03 42 57 33 85 12 80 D6 00 00 BE D6 3D 41 -1A 42 C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 -A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 -57 31 85 12 BC D6 00 00 DE D6 03 46 57 32 85 12 -BC D6 00 00 EA D6 03 46 57 33 85 12 BC D6 00 00 -F6 D6 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 -00 3C 0D 12 84 12 82 CC DE CB 50 C8 00 00 05 3F -47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 -00 10 EF 27 3E E0 00 08 EC 3F 04 CC 86 D1 40 D7 -92 53 C4 21 3E 40 2C 00 84 12 1C C9 40 CA 34 C4 -02 CC 1C D3 56 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E -59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 -10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 -A6 3E 6E D6 04 52 52 43 4D 00 85 12 3A D7 50 00 -84 D7 04 52 52 41 4D 00 85 12 3A D7 50 01 92 D7 -04 52 4C 41 4D 00 85 12 3A D7 50 02 A0 D7 04 52 -52 55 4D 00 85 12 3A D7 50 03 B0 D5 05 50 55 53 -48 4D 85 12 3A D7 00 15 BC D7 04 50 4F 50 4D 00 -85 12 3A D7 00 17 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 21 0C 4E 0E 43 1E 15 3D 40 50 CB 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +52 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 08 C9 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 C4 +8C C7 DE C9 B0 C4 22 CD 46 CA 0C CC 0A 4E 3E 4F +3D 40 26 CC 6D 27 3D 40 00 CC 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 28 CC 3E 4F 3D 40 00 CC 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +FE CD 2A 3C F0 CB 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D 46 CC 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 +00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D +82 C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D A8 C8 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E C4 +02 0D 0A 00 6A C7 94 C4 FA CB 88 C8 B2 C8 1E C4 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 32 C4 +0A C4 40 FF BA C8 1E C4 09 46 52 41 4D 20 66 75 +6C 6C 08 C5 B2 C4 BE CC A8 CC 0D 41 42 4F 52 54 +22 00 0D 12 84 12 C8 C8 0A C4 08 C5 48 CC 5A C9 +D8 C9 02 27 0D 12 84 12 8C C7 DE C9 46 CA B0 C4 +24 CD EC C8 30 CC 52 C8 07 5B 27 5D 0D 12 84 12 +14 CD 0A C4 0A C4 48 CC 48 CC 5A C9 28 CD 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +A0 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +8C C7 DE C9 46 CA B0 C4 24 CD B2 C8 AC C4 7C CD +0A C4 0A C4 48 CC 48 CC 0A C4 48 CC 48 CC 5A C9 +00 00 02 3A 30 12 D2 CD 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 8C C7 DE C9 9A CD 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 C5 +3E CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A C4 +5A C9 48 CC E4 CD 40 CD 5A C9 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +92 CC 0C 43 52 45 41 54 45 00 B0 12 88 CD BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 64 C7 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 82 CD 0E 3A 4E 4F 4E 41 4D 45 30 12 +D2 CD 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 1C CE 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 14 CD 9E CE 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 2C CD 0A C4 A0 CE +48 CC 5A C9 32 CE 08 43 4F 44 45 00 B0 12 88 CD +A2 82 C8 21 61 3C 74 C9 0E 48 44 4E 43 4F 44 45 +B2 40 8C CF CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 E4 CD EA CE 3D 41 92 42 D0 21 +CC 21 5D 3C B6 CE 0E 43 4F 44 45 4E 4E 4D 30 12 +C0 CE B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F C8 CE 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F 54 CF B2 40 66 CF D0 21 82 4E CE 21 30 40 +EC C8 85 12 52 CF 52 CD FA CC E4 CF F6 CE 4C CE +96 C9 40 CA 12 CD 3A CF 8C CE 66 CE 02 CE 5A CC +6E D0 98 CA 00 00 00 00 85 12 52 CF E8 D6 6C D5 +CC D6 94 D4 F0 D4 3E D5 1A D6 26 D6 B6 D3 DA D4 +00 00 00 00 28 CF A6 D2 00 00 42 D6 86 CF B2 40 +66 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 BA CF +30 4D CC CF 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 BA CF 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 10 C6 FE FF 29 83 B9 40 FA C5 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 10 00 +3A 40 3A 18 B0 12 BE CF 82 43 4A 18 C7 3F 60 D0 +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 48 CD 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 8C C7 +DE C9 46 CA AC C4 8C D0 80 C8 20 CC 8E D0 3E 4F +3D 41 B2 41 C6 21 B0 12 88 CD BA 40 85 12 FC FF +BA 40 5E D0 FE FF 28 83 8A 48 00 00 BA 40 82 C4 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 DE C9 +46 CA AC C4 F8 D0 D8 D0 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 5E D0 00 00 01 20 +3E 52 2E 83 21 53 30 41 F0 CA AC C4 00 D1 F4 D0 +02 D1 B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 C8 D0 15 20 3E 40 2B 00 B0 12 +C8 D0 06 20 3E 40 2D 00 B0 12 C8 D0 92 83 C6 21 +0E 12 1E 41 02 00 84 12 DE C9 F0 CA AC C4 24 CD +42 D1 3E 51 3A 17 30 41 B0 12 08 D1 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 DE C9 F0 CA AC C4 7A D1 +72 D1 3E 90 10 00 E6 2B 7C 2D 7C D1 A2 41 C6 21 +E1 3F 03 20 B0 12 60 D1 43 3C 7A 90 23 00 24 20 +B0 12 10 D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 10 D1 F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 5C D1 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 60 D1 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 48 D1 F2 3F +03 20 B0 12 60 D1 F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 48 D1 EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A C4 00 13 48 CC 5A C9 0A C4 +2C 00 3E D2 82 D1 8C C7 48 D2 20 D2 8E D2 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +7E D2 00 40 9A D2 0A 4D 4F 56 2E 42 85 12 7E D2 +40 40 00 00 06 41 44 44 85 12 7E D2 00 50 B4 D2 +0A 41 44 44 2E 42 85 12 7E D2 40 50 C0 D2 08 41 +44 44 43 00 85 12 7E D2 00 60 CE D2 0C 41 44 44 +43 2E 42 00 85 12 7E D2 40 60 06 CF 08 53 55 42 +43 00 85 12 7E D2 00 70 EC D2 0C 53 55 42 43 2E +42 00 85 12 7E D2 40 70 FA D2 06 53 55 42 85 12 +7E D2 00 80 0A D3 0A 53 55 42 2E 42 85 12 7E D2 +40 80 16 D3 06 43 4D 50 85 12 7E D2 00 90 24 D3 +0A 43 4D 50 2E 42 85 12 7E D2 40 90 00 00 08 44 +41 44 44 00 85 12 7E D2 00 A0 3E D3 0C 44 41 44 +44 2E 42 00 85 12 7E D2 40 A0 6C D2 06 42 49 54 +85 12 7E D2 00 B0 5C D3 0A 42 49 54 2E 42 85 12 +7E D2 40 B0 68 D3 06 42 49 43 85 12 7E D2 00 C0 +76 D3 0A 42 49 43 2E 42 85 12 7E D2 40 C0 82 D3 +06 42 49 53 85 12 7E D2 00 D0 90 D3 0A 42 49 53 +2E 42 85 12 7E D2 40 D0 00 00 06 58 4F 52 85 12 +7E D2 00 E0 AA D3 0A 58 4F 52 2E 42 85 12 7E D2 +40 E0 DC D2 06 41 4E 44 85 12 7E D2 00 F0 C4 D3 +0A 41 4E 44 2E 42 85 12 7E D2 40 F0 8C C7 3E D2 +82 D1 E4 D3 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F 9C D3 06 52 52 43 85 12 DC D3 00 10 +F6 D3 0A 52 52 43 2E 42 85 12 DC D3 40 10 30 D3 +08 53 57 50 42 00 85 12 DC D3 80 10 02 D4 06 52 +52 41 85 12 DC D3 00 11 1E D4 0A 52 52 41 2E 42 +85 12 DC D3 40 11 10 D4 06 53 58 54 85 12 DC D3 +80 11 00 00 08 50 55 53 48 00 85 12 DC D3 00 12 +44 D4 0C 50 55 53 48 2E 42 00 85 12 DC D3 40 12 +38 D4 08 43 41 4C 4C 00 85 12 DC D3 80 12 1A 53 +0E 4A 84 12 CE C9 1E C4 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 C5 62 D4 06 53 3E 3D 86 12 +00 38 8A D4 04 53 3C 00 86 12 00 34 52 D4 06 30 +3E 3D 86 12 00 30 9E D4 04 30 3C 00 86 12 00 30 +DA CE 04 55 3C 00 86 12 00 2C B2 D4 06 55 3E 3D +86 12 00 28 A8 D4 06 30 3C 3E 86 12 00 24 C6 D4 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 4C D3 +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D BC D4 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +2A D4 0A 42 45 47 49 4E 30 40 32 C4 14 D5 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D D0 D3 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 DE D4 74 C8 5A C9 32 D5 0C 52 +45 50 45 41 54 00 0D 12 84 12 72 D5 F6 D4 5A C9 +A2 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D 8E D5 06 42 57 31 85 12 +A0 D5 00 00 BA D5 06 42 57 32 85 12 A0 D5 00 00 +C6 D5 06 42 57 33 85 12 A0 D5 00 00 DE D5 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 DC D5 00 00 02 D6 06 46 +57 32 85 12 DC D5 00 00 0E D6 06 46 57 33 85 12 +DC D5 00 00 7C D5 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 14 CD 20 CC 5A C9 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 48 D2 +0A C4 2C 00 DE C9 F0 CA AC C4 24 CD 8C C7 3E D2 +20 D2 74 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +D2 D5 08 52 52 43 4D 00 85 12 5E D6 50 00 A2 D6 +08 52 52 41 4D 00 85 12 5E D6 50 01 B0 D6 08 52 +4C 41 4D 00 85 12 5E D6 50 02 BE D6 08 52 52 55 +4D 00 85 12 5E D6 50 03 D0 D4 0A 50 55 53 48 4D +85 12 5E D6 00 15 DA D6 08 50 4F 50 4D 00 85 12 +5E D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -84 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 0A D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +B4 C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 10 C6 q diff --git a/binaries/CHIPSTICK_FR2433_8MHz_UART.txt b/binaries/CHIPSTICK_FR2433_8MHz_UART.txt deleted file mode 100644 index b6fc881..0000000 --- a/binaries/CHIPSTICK_FR2433_8MHz_UART.txt +++ /dev/null @@ -1,335 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF EC D7 04 D0 34 01 -10 00 41 33 94 C5 AA C4 DA C5 9C C5 96 C6 EC D7 -04 D0 7C C6 94 C7 26 C7 00 C7 3C 21 62 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 7A C6 B2 49 92 C7 B2 49 24 C7 B2 49 FE C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 D0 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E2 C7 34 C7 -14 C4 04 1B 5B 37 6D 00 5E C7 AA C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E C7 A2 C8 5E C7 14 C4 04 1B 5B 30 6D 00 -5E C7 2A CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D2 22 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C2 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B0 10 00 00 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 -B0 12 9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 -5E C7 D8 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E C7 0A C4 40 FF 28 C4 D6 C7 A2 C8 14 C4 0A 62 -79 74 65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 -06 41 43 43 45 50 54 00 30 40 7C C6 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 C6 3C 40 -D4 C6 5D 15 B5 3E 21 52 3A 17 58 42 0C 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 -FD 27 C2 48 0E 05 30 4D CA C6 2D 83 92 B3 1C 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -1C 05 FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 -DE 21 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 C7 -2F 83 8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 -1E 42 0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 C7 08 4E 3E 4F C8 3F 1C C7 04 45 -43 48 4F 00 B2 40 C2 48 C2 C6 82 43 DE 21 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 C6 -92 43 DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A C7 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 C7 7C C7 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 -30 40 94 C7 0D 12 84 12 14 C4 02 0D 0A 00 5E C7 -62 C8 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 C6 -01 40 2E 4E 30 4D E0 C7 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 21 B2 21 30 4D 8C C7 01 23 1B 42 -DC 21 2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 -18 42 B2 21 C8 4A 00 00 30 4D 1C C8 02 23 53 00 -0D 12 84 12 1E C8 58 C8 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C C8 02 23 3E 00 9F 42 B2 21 -00 00 3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 C7 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 C8 50 C8 EE C4 90 C8 6C C8 5E C7 16 CC -22 C7 62 C8 42 C7 01 2E 0E 93 E3 37 38 43 E2 3F -8A C8 82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 -14 C4 5C CB 0A C4 22 00 2E C9 FC C8 B2 40 20 00 -B4 21 6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 -30 4D D6 C8 82 2E 22 00 0D 12 84 12 E6 C8 0A C4 -5E C7 5C CB 62 C8 1A C6 04 57 4F 52 44 00 3C 40 -C0 21 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A -C4 21 1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 -D4 C4 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 -B0 CA 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 CA 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 3E 4F 30 4D 5A CB 87 4C -49 54 45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 -C6 21 A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 C8 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C C8 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC C4 16 CC 2E C9 -D2 CB 9C 26 3D 40 DA CB DE 3E DC CB 0A 4E 3E 4F -3D 40 F6 CB 36 27 3D 40 CC CB 1A E2 BE 21 B6 27 -0E 12 3E 4F 30 41 F8 CB 3E 4F 3D 40 CC CB BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 CD CC 3F 00 CC 86 12 20 00 E8 C7 05 41 4C 4C -4F 54 82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 -31 40 E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 -90 C7 BC C4 C6 CB C6 C7 F8 C7 14 C4 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF -28 C4 00 C8 14 C4 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A C5 3A C4 40 CC 1C CC 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 C8 0A C4 2A C5 5C CB 62 C8 -90 C9 01 27 0D 12 84 12 16 CC 2E C9 96 C9 34 C4 -14 CC 62 C8 00 00 83 5B 27 5D 0D 12 84 12 94 CC -0A C4 0A C4 5C CB 5C CB 62 C8 A6 CC 81 5B 82 43 -BE 21 30 4D 0E C8 01 5D B2 43 BE 21 30 4D C6 CC -81 5C 92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 CC 2E C9 96 C9 -AA C7 34 C4 14 CC F8 C7 34 C4 08 CD 0A C4 0A C4 -5C CB 5C CB 0A C4 5C CB 5C CB 62 C8 BC CC 01 3A -30 12 58 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 -16 CC 2E C9 26 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 -2A 52 82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 -18 42 B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 C5 0E CD 81 3B 82 93 -BE 21 97 27 0D 12 84 12 0A C4 62 C8 5C CB 6A CD -BE CC 62 C8 BC CB 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 21 F8 D0 80 00 00 00 30 4D A6 CB 06 43 -52 45 41 54 45 00 B0 12 14 CD BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE CD 04 43 4F 44 45 00 B0 12 -14 CD A2 82 C6 21 0D 12 84 12 06 D0 E0 CF 62 C8 -B6 CD 07 48 44 4E 43 4F 44 45 B2 40 E4 CF DA 21 -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A CD 20 D0 3E D0 62 C8 00 00 05 43 4F 4C 4F 4E -1A 42 C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 21 B2 43 BE 21 0D 12 84 12 20 D0 3E D0 -62 C8 00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 -C6 21 EB 3F 02 CE 85 48 49 32 4C 4F 0D 12 84 12 -28 C4 AE CF 5C CB BE CC F6 CD 62 C8 9C CD 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E CE 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A C4 00 00 DA C7 16 CC -2E C9 AC CB A2 C7 34 C4 16 CF B0 C7 14 C4 06 5B -54 48 45 4E 5D 00 88 CE F0 CE AC CE CE CE 62 C8 -B0 C7 14 C4 06 5B 45 4C 53 45 5D 00 88 CE 06 CF -AC CE CC CE 62 C8 14 C4 04 5B 49 46 5D 00 88 CE -CE CE 3A C4 CC CE 84 C7 14 C4 05 0D 0A 6B 6F 20 -5E C7 BC C4 AC C4 3A C4 CE CE BC CE 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C CF -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 CC -2E C9 96 C9 3A CF 62 C8 40 CF 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A CF F2 C7 62 C8 -72 CF B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E CB 06 4D 41 52 4B 45 52 00 B0 12 14 CD BA 40 -85 12 FC FF BA 40 70 CF FE FF 28 83 8A 48 00 00 -BA 40 AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 -30 4D 0A C4 CA 21 EA C7 62 C8 85 12 B2 CF 7A CC -E8 CD 2E C7 92 CC 66 CE F8 C6 82 CF 14 C9 AA D0 -BE D0 9E C8 28 C9 00 00 5A CF D0 CC F6 C9 00 00 -85 12 B2 CF 62 D6 C8 D6 0A D6 18 D7 D0 D5 00 00 -9C D3 00 00 E0 D7 C4 D7 34 D6 72 D6 AC D4 00 00 -00 00 34 D7 DE CF 3A 40 0C 00 39 40 D6 21 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 -CA 21 DA 21 30 4D BA CF 38 D0 3E D0 4E D0 1A 42 -20 18 82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC CC 09 50 57 52 5F 53 54 41 54 45 85 12 -46 D0 EC D7 E2 C8 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 D0 F3 3F 84 D0 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 21 92 D0 30 4D 96 D0 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C D1 FE FF -29 83 B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 -22 C6 B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 -E0 20 3F 40 80 20 39 40 00 10 29 83 89 43 00 20 -FC 23 B2 43 02 02 B2 D3 06 02 D2 43 24 02 F2 D3 -26 02 F2 40 FD 00 22 02 E2 D2 24 02 B2 40 00 A5 -60 01 B2 40 F3 00 80 01 B2 40 07 00 82 01 B2 40 -FC 00 84 01 39 40 80 00 B2 D0 10 00 86 01 38 40 -17 11 18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 -08 18 1E D2 5E 01 B0 12 F8 C4 20 C6 38 40 C0 21 -0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D -1C 15 0E 12 12 12 C4 21 84 12 2E C9 96 C9 F2 C7 -34 C4 DC D1 52 CA 34 C4 F6 D1 F0 D1 DE D1 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 F8 D1 B2 41 C4 21 3E 41 84 12 -0A C4 2B 00 2E C9 96 C9 F2 C7 34 C4 14 D2 52 CA -34 C4 14 CC BC C7 2E C9 52 CA 34 C4 14 CC 20 D2 -3E 5F E7 3F 3E 40 28 00 B0 12 C0 D1 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 -C4 21 02 20 30 40 82 CD 1C 15 12 12 C4 21 92 53 -C4 21 84 12 2E C9 52 CA 34 C4 68 D2 5E D2 21 53 -3E 90 10 00 C6 2B 7F 2D 6A D2 B2 41 C4 21 C1 3F -0D 12 84 12 16 CC 9C D1 7A D2 0C 43 1B 42 C6 21 -A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 -C4 21 B0 12 C0 D1 3C 40 00 03 0E 93 1C 24 3C 40 -10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 -20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 -30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 -07 20 3C 40 10 02 92 53 C4 21 B0 12 C0 D1 ED 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 -48 D2 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 48 D2 -92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E -DA 3F B0 12 48 D2 FA 23 3C 50 10 00 B0 12 24 D2 -EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 -16 CC 9C D1 46 D3 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C7 3F B0 12 48 D2 E0 23 3C 50 -80 00 B0 12 24 D2 DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A C4 00 13 5C CB 62 C8 0A C4 2C 00 -70 D2 3C D3 86 D3 09 4B 2E 4E 0E DC A2 3F 54 CE -03 4D 4F 56 85 12 7C D3 00 40 90 D3 05 4D 4F 56 -2E 42 85 12 7C D3 40 40 00 00 03 41 44 44 85 12 -7C D3 00 50 AA D3 05 41 44 44 2E 42 85 12 7C D3 -40 50 B6 D3 04 41 44 44 43 00 85 12 7C D3 00 60 -C4 D3 06 41 44 44 43 2E 42 00 85 12 7C D3 40 60 -6A D3 04 53 55 42 43 00 85 12 7C D3 00 70 E2 D3 -06 53 55 42 43 2E 42 00 85 12 7C D3 40 70 F0 D3 -03 53 55 42 85 12 7C D3 00 80 00 D4 05 53 55 42 -2E 42 85 12 7C D3 40 80 2A CE 03 43 4D 50 85 12 -7C D3 00 90 1A D4 05 43 4D 50 2E 42 85 12 7C D3 -40 90 14 CE 04 44 41 44 44 00 85 12 7C D3 00 A0 -34 D4 06 44 41 44 44 2E 42 00 85 12 7C D3 40 A0 -26 D4 03 42 49 54 85 12 7C D3 00 B0 52 D4 05 42 -49 54 2E 42 85 12 7C D3 40 B0 5E D4 03 42 49 43 -85 12 7C D3 00 C0 6C D4 05 42 49 43 2E 42 85 12 -7C D3 40 C0 78 D4 03 42 49 53 85 12 7C D3 00 D0 -86 D4 05 42 49 53 2E 42 85 12 7C D3 40 D0 00 00 -03 58 4F 52 85 12 7C D3 00 E0 A0 D4 05 58 4F 52 -2E 42 85 12 7C D3 40 E0 D2 D3 03 41 4E 44 85 12 -7C D3 00 F0 BA D4 05 41 4E 44 2E 42 85 12 7C D3 -40 F0 16 CC 70 D2 D8 D4 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F 0C D4 03 52 52 43 85 12 -D2 D4 00 10 EA D4 05 52 52 43 2E 42 85 12 D2 D4 -40 10 F6 D4 04 53 57 50 42 00 85 12 D2 D4 80 10 -04 D5 03 52 52 41 85 12 D2 D4 00 11 12 D5 05 52 -52 41 2E 42 85 12 D2 D4 40 11 1E D5 03 53 58 54 -85 12 D2 D4 80 11 00 00 04 50 55 53 48 00 85 12 -D2 D4 00 12 38 D5 06 50 55 53 48 2E 42 00 85 12 -D2 D4 40 12 92 D4 04 43 41 4C 4C 00 85 12 D2 D4 -80 12 1A 53 0E 4A 0D 12 84 12 D8 C8 14 C4 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C5 2C D5 -03 53 3E 3D 86 12 00 38 80 D5 02 53 3C 00 86 12 -00 34 46 D5 03 30 3E 3D 86 12 00 30 94 D5 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -A8 D5 03 55 3E 3D 86 12 00 28 9E D5 03 30 3C 3E -86 12 00 24 BC D5 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 -0E 4A 30 4D B2 D5 04 54 48 45 4E 00 1A 42 C6 21 -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D 42 D4 04 45 4C 53 45 00 -1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 -8F 4A 00 00 E3 3F 56 D5 05 42 45 47 49 4E 30 40 -28 C4 E6 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D -C6 D4 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 D4 D5 BC C7 -62 C8 8A D5 06 52 45 50 45 41 54 00 0D 12 84 12 -68 D6 EC D5 62 C8 98 D6 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D 28 D6 -03 42 57 31 85 12 96 D6 00 00 B0 D6 03 42 57 32 -85 12 96 D6 00 00 BC D6 03 42 57 33 85 12 96 D6 -00 00 D4 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 -88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 D2 D6 00 00 F4 D6 -03 46 57 32 85 12 D2 D6 00 00 00 D7 03 46 57 33 -85 12 D2 D6 00 00 0C D7 04 47 4F 54 4F 00 2F 83 -8F 4E 00 00 3E 40 00 3C 0D 12 84 12 94 CC F0 CB -62 C8 00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 -3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F -16 CC 9C D1 56 D7 92 53 C4 21 3E 40 2C 00 84 12 -2E C9 52 CA 34 C4 14 CC 32 D3 6C D7 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 84 D6 04 52 52 43 4D 00 -85 12 50 D7 50 00 9A D7 04 52 52 41 4D 00 85 12 -50 D7 50 01 A8 D7 04 52 4C 41 4D 00 85 12 50 D7 -50 02 B6 D7 04 52 52 55 4D 00 85 12 50 D7 50 03 -C6 D5 05 50 55 53 48 4D 85 12 50 D7 00 15 D2 D7 -04 50 4F 50 4D 00 85 12 50 D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 96 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1C D1 -q diff --git a/binaries/LP_MSP430FR2476_16MHz_115200.txt b/binaries/LP_MSP430FR2476_16MHz_115200.txt new file mode 100644 index 0000000..65ef647 --- /dev/null +++ b/binaries/LP_MSP430FR2476_16MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 19 +CA 82 7E 81 84 81 54 81 3A 83 28 93 E0 8B 9A 8B +9A 8B B0 82 6E 83 36 83 3C 21 E0 20 8E 85 B6 80 +C4 80 AA 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3A 83 28 93 E0 8B 9A 8B 9A 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AE 82 B2 49 +6C 83 B2 49 34 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 54 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3A 83 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 80 B4 84 AC 80 52 81 7C 83 1E 80 04 1B +5B 37 6D 00 9E 83 9E 83 1E 80 04 1B 5B 30 6D 00 +9E 83 EA 88 B0 12 7E 81 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 7C 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 9E 83 02 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9E 83 0A 80 40 FF 32 80 +CA 84 CE 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 +FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 +45 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 +A1 01 B2 40 00 A5 60 01 B2 D0 10 00 86 01 F2 C3 +82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 39 40 +5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 20 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 80 +86 81 00 00 0C 41 43 43 45 50 54 00 30 40 B0 82 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +0E 83 3C 40 1A 83 5D 15 9B 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D3 43 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 10 83 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 36 83 30 12 4C 83 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C3 43 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 D6 82 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 6E 83 08 4E +3E 4F C7 3F 64 83 08 45 43 48 4F 00 B2 40 C2 48 +08 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 08 83 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE 83 29 4F 8F 4E 00 00 7E 49 DE 3F B0 83 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2E 83 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 80 00 00 CE 84 C0 83 +12 86 CC 88 B0 80 3C 84 14 80 06 5B 54 48 45 4E +5D 00 C4 83 1A 84 E0 83 FE 83 14 80 06 5B 45 4C +53 45 5D 00 C4 83 2C 84 E0 83 FC 83 1E 80 04 5B +49 46 5D 00 C4 83 FE 83 B2 80 FC 83 1E 80 05 0D +6B 6F 20 0A 9E 83 9A 80 84 80 B2 80 FE 83 EC 83 +0D 5B 54 48 45 4E 5D 00 30 4D 50 84 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C 84 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 83 12 86 7A 86 +1E 88 8E 85 6C 84 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 83 12 86 7A 86 9E 84 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D A4 82 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A 80 1E 80 7C 88 0A 80 22 00 12 86 +12 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 86 83 05 2E 22 00 0D 12 84 12 +FC 84 0A 80 9E 83 7C 88 8E 85 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D F8 84 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 4A 85 04 23 53 00 0D 12 +84 12 4C 85 86 85 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 85 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 76 83 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 85 C0 83 +AE 85 7E 85 AA 84 BC 85 98 85 9E 83 8E 85 28 85 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 86 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 84 87 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 87 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 80 C0 83 12 86 B0 80 56 89 7A 86 40 88 +0A 4E 3E 4F 3D 40 5A 88 6D 27 3D 40 34 88 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 5C 88 3E 4F 3D 40 +34 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 8A 2A 3C 24 88 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7A 88 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 85 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC 84 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E 80 02 0D 0A 00 9E 83 94 80 2E 88 BC 84 +E6 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 81 32 80 0A 80 40 FF EE 84 1E 80 09 46 52 41 +4D 20 66 75 6C 6C 08 81 B2 80 F2 88 DC 88 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC 84 0A 80 08 81 +7C 88 8E 85 0C 86 02 27 0D 12 84 12 C0 83 12 86 +7A 86 B0 80 58 89 20 85 64 88 86 84 07 5B 27 5D +0D 12 84 12 48 89 0A 80 0A 80 7C 88 7C 88 8E 85 +5C 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D D4 84 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 83 12 86 7A 86 B0 80 58 89 E6 84 +AC 80 B0 89 0A 80 0A 80 7C 88 7C 88 0A 80 7C 88 +7C 88 8E 85 00 00 02 3A 30 12 06 8A 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 C0 83 12 86 CE 89 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 81 72 89 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A 80 8E 85 7C 88 18 8A 74 89 8E 85 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D C6 88 0C 43 52 45 41 54 45 00 B0 12 +BC 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 83 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 89 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 8A 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 8A +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 48 89 +D2 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 89 +0A 80 D4 8A 7C 88 8E 85 66 8A 08 43 4F 44 45 00 +B0 12 BC 89 A2 82 C8 21 61 3C A8 85 0E 48 44 4E +43 4F 44 45 B2 40 C0 8B CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 8A 1E 8B 3D 41 +92 42 D0 21 CC 21 5D 3C EA 8A 0E 43 4F 44 45 4E +4E 4D 30 12 F4 8A B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FC 8A 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 88 8B B2 40 9A 8B D0 21 82 4E +CE 21 30 40 20 85 85 12 86 8B 86 89 2E 89 18 8C +2A 8B 80 8A CA 85 74 86 46 89 6E 8B C0 8A 9A 8A +36 8A 8E 88 A2 8C CC 86 00 00 00 00 85 12 86 8B +1C 93 A0 91 00 93 C8 90 24 91 72 91 4E 92 5A 92 +EA 8F 0E 91 00 00 00 00 5C 8B DA 8E 00 00 76 92 +BA 8B B2 40 9A 8B CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 EE 8B 30 4D 00 8C 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 EE 8B 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 F2 81 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 8B 82 43 4A 18 +C7 3F 94 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 C0 83 12 86 7A 86 AC 80 C0 8C B4 84 54 88 +C2 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BC 89 BA 40 +85 12 FC FF BA 40 92 8C FE FF 28 83 8A 48 00 00 +BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 12 86 7A 86 AC 80 2C 8D 0C 8D 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 8C +00 00 01 20 3E 52 2E 83 21 53 30 41 24 87 AC 80 +34 8D 28 8D 36 8D B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 FC 8C 15 20 3E 40 +2B 00 B0 12 FC 8C 06 20 3E 40 2D 00 B0 12 FC 8C +92 83 C6 21 0E 12 1E 41 02 00 84 12 12 86 24 87 +AC 80 58 89 76 8D 3E 51 3A 17 30 41 B0 12 3C 8D +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 12 86 24 87 +AC 80 AE 8D A6 8D 3E 90 10 00 E6 2B 7C 2D B0 8D +A2 41 C6 21 E1 3F 03 20 B0 12 94 8D 43 3C 7A 90 +23 00 24 20 B0 12 44 8D 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 8D F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 8D 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 8D 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C 8D F2 3F 03 20 B0 12 94 8D F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C 8D +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 7C 88 +8E 85 0A 80 2C 00 72 8E B6 8D C0 83 7C 8E 54 8E +C2 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 8E 00 40 CE 8E 0A 4D 4F 56 2E 42 +85 12 B2 8E 40 40 00 00 06 41 44 44 85 12 B2 8E +00 50 E8 8E 0A 41 44 44 2E 42 85 12 B2 8E 40 50 +F4 8E 08 41 44 44 43 00 85 12 B2 8E 00 60 02 8F +0C 41 44 44 43 2E 42 00 85 12 B2 8E 40 60 3A 8B +08 53 55 42 43 00 85 12 B2 8E 00 70 20 8F 0C 53 +55 42 43 2E 42 00 85 12 B2 8E 40 70 2E 8F 06 53 +55 42 85 12 B2 8E 00 80 3E 8F 0A 53 55 42 2E 42 +85 12 B2 8E 40 80 4A 8F 06 43 4D 50 85 12 B2 8E +00 90 58 8F 0A 43 4D 50 2E 42 85 12 B2 8E 40 90 +00 00 08 44 41 44 44 00 85 12 B2 8E 00 A0 72 8F +0C 44 41 44 44 2E 42 00 85 12 B2 8E 40 A0 A0 8E +06 42 49 54 85 12 B2 8E 00 B0 90 8F 0A 42 49 54 +2E 42 85 12 B2 8E 40 B0 9C 8F 06 42 49 43 85 12 +B2 8E 00 C0 AA 8F 0A 42 49 43 2E 42 85 12 B2 8E +40 C0 B6 8F 06 42 49 53 85 12 B2 8E 00 D0 C4 8F +0A 42 49 53 2E 42 85 12 B2 8E 40 D0 00 00 06 58 +4F 52 85 12 B2 8E 00 E0 DE 8F 0A 58 4F 52 2E 42 +85 12 B2 8E 40 E0 10 8F 06 41 4E 44 85 12 B2 8E +00 F0 F8 8F 0A 41 4E 44 2E 42 85 12 B2 8E 40 F0 +C0 83 72 8E B6 8D 18 90 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 8F 06 52 52 43 85 12 +10 90 00 10 2A 90 0A 52 52 43 2E 42 85 12 10 90 +40 10 64 8F 08 53 57 50 42 00 85 12 10 90 80 10 +36 90 06 52 52 41 85 12 10 90 00 11 52 90 0A 52 +52 41 2E 42 85 12 10 90 40 11 44 90 06 53 58 54 +85 12 10 90 80 11 00 00 08 50 55 53 48 00 85 12 +10 90 00 12 78 90 0C 50 55 53 48 2E 42 00 85 12 +10 90 40 12 6C 90 08 43 41 4C 4C 00 85 12 10 90 +80 12 1A 53 0E 4A 84 12 02 86 1E 80 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 81 96 90 06 53 +3E 3D 86 12 00 38 BE 90 04 53 3C 00 86 12 00 34 +86 90 06 30 3E 3D 86 12 00 30 D2 90 04 30 3C 00 +86 12 00 30 0E 8B 04 55 3C 00 86 12 00 2C E6 90 +06 55 3E 3D 86 12 00 28 DC 90 06 30 3C 3E 86 12 +00 24 FA 90 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 80 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 90 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 5E 90 0A 42 45 47 49 4E 30 40 32 80 +48 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D 04 90 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 91 A8 84 8E 85 +66 91 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 91 +2A 91 8E 85 D6 91 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D C2 91 06 42 +57 31 85 12 D4 91 00 00 EE 91 06 42 57 32 85 12 +D4 91 00 00 FA 91 06 42 57 33 85 12 D4 91 00 00 +12 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 92 00 00 +36 92 06 46 57 32 85 12 10 92 00 00 42 92 06 46 +57 33 85 12 10 92 00 00 B0 91 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 89 +54 88 8E 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 7C 8E 0A 80 2C 00 12 86 24 87 AC 80 58 89 +C0 83 72 8E 54 8E A8 92 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 92 08 52 52 43 4D 00 85 12 92 92 +50 00 D6 92 08 52 52 41 4D 00 85 12 92 92 50 01 +E4 92 08 52 4C 41 4D 00 85 12 92 92 50 02 F2 92 +08 52 52 55 4D 00 85 12 92 92 50 03 04 91 0A 50 +55 53 48 4D 85 12 92 92 00 15 0E 93 08 50 4F 50 +4D 00 85 12 92 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +CA 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/LP_MSP430FR2476_16MHz_4MBds.txt b/binaries/LP_MSP430FR2476_16MHz_4MBds.txt new file mode 100644 index 0000000..9368694 --- /dev/null +++ b/binaries/LP_MSP430FR2476_16MHz_4MBds.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 19 +CA 82 7E 81 84 81 54 81 3A 83 28 93 E0 8B 9A 8B +9A 8B B0 82 6E 83 36 83 3C 21 E0 20 8E 85 B6 80 +C4 80 AA 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3A 83 28 93 E0 8B 9A 8B 9A 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AE 82 B2 49 +6C 83 B2 49 34 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 54 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3A 83 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 80 B4 84 AC 80 52 81 7C 83 1E 80 04 1B +5B 37 6D 00 9E 83 9E 83 1E 80 04 1B 5B 30 6D 00 +9E 83 EA 88 B0 12 7E 81 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 7C 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 9E 83 02 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9E 83 0A 80 40 FF 32 80 +CA 84 CE 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 +FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 +45 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 +A1 01 B2 40 00 A5 60 01 B2 D0 10 00 86 01 F2 C3 +82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 39 40 +5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 20 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 80 +86 81 00 00 0C 41 43 43 45 50 54 00 30 40 B0 82 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +0E 83 3C 40 1A 83 5D 15 9B 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D3 43 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 10 83 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 36 83 30 12 4C 83 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C3 43 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 D6 82 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 6E 83 08 4E +3E 4F C7 3F 64 83 08 45 43 48 4F 00 B2 40 C2 48 +08 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 08 83 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE 83 29 4F 8F 4E 00 00 7E 49 DE 3F B0 83 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2E 83 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 80 00 00 CE 84 C0 83 +12 86 CC 88 B0 80 3C 84 14 80 06 5B 54 48 45 4E +5D 00 C4 83 1A 84 E0 83 FE 83 14 80 06 5B 45 4C +53 45 5D 00 C4 83 2C 84 E0 83 FC 83 1E 80 04 5B +49 46 5D 00 C4 83 FE 83 B2 80 FC 83 1E 80 05 0D +6B 6F 20 0A 9E 83 9A 80 84 80 B2 80 FE 83 EC 83 +0D 5B 54 48 45 4E 5D 00 30 4D 50 84 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C 84 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 83 12 86 7A 86 +1E 88 8E 85 6C 84 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 83 12 86 7A 86 9E 84 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D A4 82 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A 80 1E 80 7C 88 0A 80 22 00 12 86 +12 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 86 83 05 2E 22 00 0D 12 84 12 +FC 84 0A 80 9E 83 7C 88 8E 85 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D F8 84 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 4A 85 04 23 53 00 0D 12 +84 12 4C 85 86 85 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 85 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 76 83 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 85 C0 83 +AE 85 7E 85 AA 84 BC 85 98 85 9E 83 8E 85 28 85 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 86 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 84 87 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 87 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 80 C0 83 12 86 B0 80 56 89 7A 86 40 88 +0A 4E 3E 4F 3D 40 5A 88 6D 27 3D 40 34 88 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 5C 88 3E 4F 3D 40 +34 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 8A 2A 3C 24 88 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7A 88 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 85 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC 84 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E 80 02 0D 0A 00 9E 83 94 80 2E 88 BC 84 +E6 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 81 32 80 0A 80 40 FF EE 84 1E 80 09 46 52 41 +4D 20 66 75 6C 6C 08 81 B2 80 F2 88 DC 88 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC 84 0A 80 08 81 +7C 88 8E 85 0C 86 02 27 0D 12 84 12 C0 83 12 86 +7A 86 B0 80 58 89 20 85 64 88 86 84 07 5B 27 5D +0D 12 84 12 48 89 0A 80 0A 80 7C 88 7C 88 8E 85 +5C 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D D4 84 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 83 12 86 7A 86 B0 80 58 89 E6 84 +AC 80 B0 89 0A 80 0A 80 7C 88 7C 88 0A 80 7C 88 +7C 88 8E 85 00 00 02 3A 30 12 06 8A 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 C0 83 12 86 CE 89 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 81 72 89 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A 80 8E 85 7C 88 18 8A 74 89 8E 85 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D C6 88 0C 43 52 45 41 54 45 00 B0 12 +BC 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 83 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 89 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 8A 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 8A +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 48 89 +D2 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 89 +0A 80 D4 8A 7C 88 8E 85 66 8A 08 43 4F 44 45 00 +B0 12 BC 89 A2 82 C8 21 61 3C A8 85 0E 48 44 4E +43 4F 44 45 B2 40 C0 8B CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 8A 1E 8B 3D 41 +92 42 D0 21 CC 21 5D 3C EA 8A 0E 43 4F 44 45 4E +4E 4D 30 12 F4 8A B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FC 8A 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 88 8B B2 40 9A 8B D0 21 82 4E +CE 21 30 40 20 85 85 12 86 8B 86 89 2E 89 18 8C +2A 8B 80 8A CA 85 74 86 46 89 6E 8B C0 8A 9A 8A +36 8A 8E 88 A2 8C CC 86 00 00 00 00 85 12 86 8B +1C 93 A0 91 00 93 C8 90 24 91 72 91 4E 92 5A 92 +EA 8F 0E 91 00 00 00 00 5C 8B DA 8E 00 00 76 92 +BA 8B B2 40 9A 8B CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 EE 8B 30 4D 00 8C 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 EE 8B 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 F2 81 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 8B 82 43 4A 18 +C7 3F 94 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 C0 83 12 86 7A 86 AC 80 C0 8C B4 84 54 88 +C2 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BC 89 BA 40 +85 12 FC FF BA 40 92 8C FE FF 28 83 8A 48 00 00 +BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 12 86 7A 86 AC 80 2C 8D 0C 8D 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 8C +00 00 01 20 3E 52 2E 83 21 53 30 41 24 87 AC 80 +34 8D 28 8D 36 8D B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 FC 8C 15 20 3E 40 +2B 00 B0 12 FC 8C 06 20 3E 40 2D 00 B0 12 FC 8C +92 83 C6 21 0E 12 1E 41 02 00 84 12 12 86 24 87 +AC 80 58 89 76 8D 3E 51 3A 17 30 41 B0 12 3C 8D +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 12 86 24 87 +AC 80 AE 8D A6 8D 3E 90 10 00 E6 2B 7C 2D B0 8D +A2 41 C6 21 E1 3F 03 20 B0 12 94 8D 43 3C 7A 90 +23 00 24 20 B0 12 44 8D 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 8D F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 8D 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 8D 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C 8D F2 3F 03 20 B0 12 94 8D F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C 8D +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 7C 88 +8E 85 0A 80 2C 00 72 8E B6 8D C0 83 7C 8E 54 8E +C2 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 8E 00 40 CE 8E 0A 4D 4F 56 2E 42 +85 12 B2 8E 40 40 00 00 06 41 44 44 85 12 B2 8E +00 50 E8 8E 0A 41 44 44 2E 42 85 12 B2 8E 40 50 +F4 8E 08 41 44 44 43 00 85 12 B2 8E 00 60 02 8F +0C 41 44 44 43 2E 42 00 85 12 B2 8E 40 60 3A 8B +08 53 55 42 43 00 85 12 B2 8E 00 70 20 8F 0C 53 +55 42 43 2E 42 00 85 12 B2 8E 40 70 2E 8F 06 53 +55 42 85 12 B2 8E 00 80 3E 8F 0A 53 55 42 2E 42 +85 12 B2 8E 40 80 4A 8F 06 43 4D 50 85 12 B2 8E +00 90 58 8F 0A 43 4D 50 2E 42 85 12 B2 8E 40 90 +00 00 08 44 41 44 44 00 85 12 B2 8E 00 A0 72 8F +0C 44 41 44 44 2E 42 00 85 12 B2 8E 40 A0 A0 8E +06 42 49 54 85 12 B2 8E 00 B0 90 8F 0A 42 49 54 +2E 42 85 12 B2 8E 40 B0 9C 8F 06 42 49 43 85 12 +B2 8E 00 C0 AA 8F 0A 42 49 43 2E 42 85 12 B2 8E +40 C0 B6 8F 06 42 49 53 85 12 B2 8E 00 D0 C4 8F +0A 42 49 53 2E 42 85 12 B2 8E 40 D0 00 00 06 58 +4F 52 85 12 B2 8E 00 E0 DE 8F 0A 58 4F 52 2E 42 +85 12 B2 8E 40 E0 10 8F 06 41 4E 44 85 12 B2 8E +00 F0 F8 8F 0A 41 4E 44 2E 42 85 12 B2 8E 40 F0 +C0 83 72 8E B6 8D 18 90 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 8F 06 52 52 43 85 12 +10 90 00 10 2A 90 0A 52 52 43 2E 42 85 12 10 90 +40 10 64 8F 08 53 57 50 42 00 85 12 10 90 80 10 +36 90 06 52 52 41 85 12 10 90 00 11 52 90 0A 52 +52 41 2E 42 85 12 10 90 40 11 44 90 06 53 58 54 +85 12 10 90 80 11 00 00 08 50 55 53 48 00 85 12 +10 90 00 12 78 90 0C 50 55 53 48 2E 42 00 85 12 +10 90 40 12 6C 90 08 43 41 4C 4C 00 85 12 10 90 +80 12 1A 53 0E 4A 84 12 02 86 1E 80 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 81 96 90 06 53 +3E 3D 86 12 00 38 BE 90 04 53 3C 00 86 12 00 34 +86 90 06 30 3E 3D 86 12 00 30 D2 90 04 30 3C 00 +86 12 00 30 0E 8B 04 55 3C 00 86 12 00 2C E6 90 +06 55 3E 3D 86 12 00 28 DC 90 06 30 3C 3E 86 12 +00 24 FA 90 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 80 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 90 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 5E 90 0A 42 45 47 49 4E 30 40 32 80 +48 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D 04 90 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 91 A8 84 8E 85 +66 91 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 91 +2A 91 8E 85 D6 91 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D C2 91 06 42 +57 31 85 12 D4 91 00 00 EE 91 06 42 57 32 85 12 +D4 91 00 00 FA 91 06 42 57 33 85 12 D4 91 00 00 +12 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 92 00 00 +36 92 06 46 57 32 85 12 10 92 00 00 42 92 06 46 +57 33 85 12 10 92 00 00 B0 91 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 89 +54 88 8E 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 7C 8E 0A 80 2C 00 12 86 24 87 AC 80 58 89 +C0 83 72 8E 54 8E A8 92 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 92 08 52 52 43 4D 00 85 12 92 92 +50 00 D6 92 08 52 52 41 4D 00 85 12 92 92 50 01 +E4 92 08 52 4C 41 4D 00 85 12 92 92 50 02 F2 92 +08 52 52 55 4D 00 85 12 92 92 50 03 04 91 0A 50 +55 53 48 4D 85 12 92 92 00 15 0E 93 08 50 4F 50 +4D 00 85 12 92 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +CA 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/LP_MSP430FR2476_16MHz_I2C.txt b/binaries/LP_MSP430FR2476_16MHz_I2C.txt index 91ddc16..8d3cee8 100644 --- a/binaries/LP_MSP430FR2476_16MHz_I2C.txt +++ b/binaries/LP_MSP430FR2476_16MHz_I2C.txt @@ -1,336 +1,323 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF F2 93 F0 8B 34 01 -10 00 41 07 B6 81 AA 80 B8 81 8C 81 82 82 F2 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 03 +C4 82 56 81 56 81 58 81 44 81 04 93 BC 8B 76 8B +76 8B B2 82 36 83 0E 83 3C 21 E0 20 6A 85 B6 80 +C4 80 86 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 04 93 BC 8B 76 8B 76 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 80 05 18 42 02 18 08 11 38 D0 00 04 -82 48 94 05 F2 D0 0C 00 2A 02 92 C3 80 05 A2 D2 -AA 05 92 C3 30 01 30 41 48 43 A2 B3 AC 05 FD 27 -C2 48 8E 05 A2 B2 AC 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 AC 05 B2 B0 10 00 80 05 B8 22 -3A 17 92 B3 AC 05 FD 27 58 42 8C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 AC 05 FD 27 1E 42 8C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 AC 05 FD 27 C2 48 8E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +83 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 82 B2 49 +34 83 B2 49 0C 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 30 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 90 84 AC 80 +42 81 4E 83 1E 80 05 1B 5B 37 6D 40 7A 83 0A 80 +02 18 B2 84 DE 85 7A 83 1E 80 04 1B 5B 30 6D 00 +7A 83 C6 88 48 43 A2 B3 AC 05 FD 27 C2 48 8E 05 +A2 B2 AC 05 FD 27 30 41 B2 D0 C0 07 80 05 18 42 +02 18 08 11 38 D0 00 04 82 48 94 05 F2 D0 0C 00 +2A 02 92 C3 80 05 A2 D2 AA 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 4E 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 7A 83 0A 80 02 18 B2 84 DE 85 0A 80 23 00 +32 83 DE 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7A 83 0A 80 40 FF 32 80 A6 84 AA 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 40 FF 7F 22 02 B2 D3 46 02 +B2 40 FC FF 42 02 F2 40 A5 00 A1 01 F2 40 10 00 +A0 01 D2 43 A1 01 B2 40 00 A5 60 01 B2 D0 10 00 +86 01 F2 C3 82 01 F2 D0 0A 00 82 01 B2 40 E8 01 +84 01 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 39 40 00 20 29 83 89 43 00 20 FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 B0 12 +D0 80 80 81 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 82 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 9E 3E 21 52 A2 C2 AC 05 B2 B0 10 00 80 05 +97 22 3A 17 92 B3 AC 05 FD 27 58 42 8C 05 48 9B +0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 0E 83 58 43 +B0 12 46 81 2F 83 8F 4E 00 00 92 B3 AC 05 FD 27 +1E 42 8C 05 B0 12 44 81 30 4D 00 00 08 45 4D 49 +54 00 30 40 36 83 08 4E 3E 4F A2 B3 AC 05 FD 27 +C2 48 8E 05 30 4D 2C 83 08 45 43 48 4F 00 B2 40 +C2 48 40 83 38 40 05 00 B0 12 46 81 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 40 83 28 42 +F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 8A 83 +29 4F 8F 4E 00 00 7E 49 D4 3F 8C 83 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 83 22 F9 98 00 00 +80 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 77 22 9B 24 06 83 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A 80 00 00 AA 84 9C 83 EE 85 A8 88 +B0 80 18 84 14 80 06 5B 54 48 45 4E 5D 00 A0 83 +F6 83 BC 83 DA 83 14 80 06 5B 45 4C 53 45 5D 00 +A0 83 08 84 BC 83 D8 83 1E 80 04 5B 49 46 5D 00 +A0 83 DA 83 B2 80 D8 83 1E 80 05 0D 6B 6F 20 0A +7A 83 9A 80 84 80 B2 80 DA 83 C8 83 0D 5B 54 48 +45 4E 5D 00 30 4D 2C 84 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 38 84 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 9C 83 EE 85 56 86 FA 87 6A 85 +48 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 9C 83 EE 85 56 86 7A 84 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D A6 82 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 81 05 53 22 00 82 43 C0 21 0D 12 84 12 +0A 80 1E 80 58 88 0A 80 22 00 EE 85 EE 84 B2 40 +20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 +30 4D 60 83 05 2E 22 00 0D 12 84 12 D8 84 0A 80 +7A 83 58 88 6A 85 00 00 04 3C 23 00 B2 40 B2 21 +B2 21 30 4D D4 84 02 23 1B 42 BE 21 2C 4F 2F 83 +B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A +00 00 30 4D 26 85 04 23 53 00 0D 12 84 12 28 85 +62 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 56 85 +04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +70 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 48 83 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 1C 85 9C 83 8A 85 5A 85 +86 84 98 85 74 85 7A 83 6A 85 04 85 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 +C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D DC 85 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 21 0C 4E 0E 43 1E 15 3D 40 60 87 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +62 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 18 85 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 80 +9C 83 EE 85 B0 80 32 89 56 86 1C 88 0A 4E 3E 4F +3D 40 36 88 6D 27 3D 40 10 88 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 38 88 3E 4F 3D 40 10 88 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +0E 8A 2A 3C 00 88 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D 56 88 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -68 92 CE 92 10 92 1E 93 D6 91 00 00 A2 8F 00 00 -E6 93 CA 93 3A 92 78 92 B2 90 00 00 00 00 3A 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C F2 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -DA FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 20 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 FF 7F -22 02 B2 D3 46 02 B2 40 FC FF 42 02 F2 40 A5 00 -A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 -60 01 B2 40 FF 1E 80 01 B2 40 BA 00 82 01 B2 40 -E8 01 84 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 -39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 F8 80 -FE 81 38 40 C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 84 12 -1A 85 82 85 DE 83 34 80 E2 8D 3E 86 34 80 FC 8D -F6 8D E4 8D 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 FE 8D B2 41 -C4 21 3E 41 84 12 0A 80 2B 00 1A 85 82 85 DE 83 -34 80 1A 8E 3E 86 34 80 00 88 A8 83 1A 85 3E 86 -34 80 00 88 26 8E 3E 5F E7 3F 3E 40 28 00 B0 12 -C6 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 40 -29 00 92 92 C0 21 C4 21 02 20 30 40 6E 89 1C 15 -12 12 C4 21 92 53 C4 21 84 12 1A 85 3E 86 34 80 -6E 8E 64 8E 21 53 3E 90 10 00 C6 2B 7F 2D 70 8E -B2 41 C4 21 C1 3F 0D 12 84 12 02 88 A2 8D 80 8E -0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 21 B0 12 C6 8D 3C 40 00 03 -0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 -2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 -3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 21 -B0 12 C6 8D ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 21 B0 12 4E 8E 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 4E 8E 92 92 C0 21 C4 21 02 24 92 53 -C4 21 8E 10 0C 5E DA 3F B0 12 4E 8E FA 23 3C 50 -10 00 B0 12 2A 8E EF 3F 0C 43 1B 42 C6 21 A2 53 -C6 21 0D 12 84 12 02 88 A2 8D 4C 8F FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -4E 8E E0 23 3C 50 80 00 B0 12 2A 8E DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 48 87 -4E 84 0A 80 2C 00 76 8E 42 8F 8C 8F 09 4B 2E 4E -0E DC A2 3F 40 8A 03 4D 4F 56 85 12 82 8F 00 40 -96 8F 05 4D 4F 56 2E 42 85 12 82 8F 40 40 00 00 -03 41 44 44 85 12 82 8F 00 50 B0 8F 05 41 44 44 -2E 42 85 12 82 8F 40 50 BC 8F 04 41 44 44 43 00 -85 12 82 8F 00 60 CA 8F 06 41 44 44 43 2E 42 00 -85 12 82 8F 40 60 70 8F 04 53 55 42 43 00 85 12 -82 8F 00 70 E8 8F 06 53 55 42 43 2E 42 00 85 12 -82 8F 40 70 F6 8F 03 53 55 42 85 12 82 8F 00 80 -06 90 05 53 55 42 2E 42 85 12 82 8F 40 80 16 8A -03 43 4D 50 85 12 82 8F 00 90 20 90 05 43 4D 50 -2E 42 85 12 82 8F 40 90 00 8A 04 44 41 44 44 00 -85 12 82 8F 00 A0 3A 90 06 44 41 44 44 2E 42 00 -85 12 82 8F 40 A0 2C 90 03 42 49 54 85 12 82 8F -00 B0 58 90 05 42 49 54 2E 42 85 12 82 8F 40 B0 -64 90 03 42 49 43 85 12 82 8F 00 C0 72 90 05 42 -49 43 2E 42 85 12 82 8F 40 C0 7E 90 03 42 49 53 -85 12 82 8F 00 D0 8C 90 05 42 49 53 2E 42 85 12 -82 8F 40 D0 00 00 03 58 4F 52 85 12 82 8F 00 E0 -A6 90 05 58 4F 52 2E 42 85 12 82 8F 40 E0 D8 8F -03 41 4E 44 85 12 82 8F 00 F0 C0 90 05 41 4E 44 -2E 42 85 12 82 8F 40 F0 02 88 76 8E DE 90 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 12 90 -03 52 52 43 85 12 D8 90 00 10 F0 90 05 52 52 43 -2E 42 85 12 D8 90 40 10 FC 90 04 53 57 50 42 00 -85 12 D8 90 80 10 0A 91 03 52 52 41 85 12 D8 90 -00 11 18 91 05 52 52 41 2E 42 85 12 D8 90 40 11 -24 91 03 53 58 54 85 12 D8 90 80 11 00 00 04 50 -55 53 48 00 85 12 D8 90 00 12 3E 91 06 50 55 53 -48 2E 42 00 85 12 D8 90 40 12 98 90 04 43 41 4C -4C 00 85 12 D8 90 80 12 1A 53 0E 4A 0D 12 84 12 -C4 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 81 32 91 03 53 3E 3D 86 12 00 38 86 91 -02 53 3C 00 86 12 00 34 4C 91 03 30 3E 3D 86 12 -00 30 9A 91 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C AE 91 03 55 3E 3D 86 12 00 28 -A4 91 03 30 3C 3E 86 12 00 24 C2 91 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 0E 4A 30 4D B8 91 04 54 48 45 -4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 48 90 -04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C 00 00 -A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 5C 91 05 42 -45 47 49 4E 30 40 28 80 EC 91 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 21 30 4D CC 90 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 DA 91 A8 83 4E 84 90 91 06 52 45 50 45 41 -54 00 0D 12 84 12 6E 92 F2 91 4E 84 9E 92 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 -00 00 30 4D 2E 92 03 42 57 31 85 12 9C 92 00 00 -B6 92 03 42 57 32 85 12 9C 92 00 00 C2 92 03 42 -57 33 85 12 9C 92 00 00 DA 92 3D 41 1A 42 C6 21 -28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 C6 21 -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -D8 92 00 00 FA 92 03 46 57 32 85 12 D8 92 00 00 -06 93 03 46 57 33 85 12 D8 92 00 00 12 93 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 80 88 DC 87 4E 84 00 00 05 3F 47 4F 54 4F -3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 02 88 A2 8D 5C 93 92 53 C4 21 -3E 40 2C 00 84 12 1A 85 3E 86 34 80 00 88 38 8F -72 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 8A 92 -04 52 52 43 4D 00 85 12 56 93 50 00 A0 93 04 52 -52 41 4D 00 85 12 56 93 50 01 AE 93 04 52 4C 41 -4D 00 85 12 56 93 50 02 BC 93 04 52 52 55 4D 00 -85 12 56 93 50 03 CC 91 05 50 55 53 48 4D 85 12 -56 93 00 15 D8 93 04 50 4F 50 4D 00 85 12 56 93 -00 17 +92 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D B8 84 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E 80 +02 0D 0A 00 7A 83 94 80 0A 88 98 84 C2 84 1E 80 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 32 80 +0A 80 40 FF CA 84 1E 80 09 46 52 41 4D 20 66 75 +6C 6C 08 81 B2 80 CE 88 B8 88 0D 41 42 4F 52 54 +22 00 0D 12 84 12 D8 84 0A 80 08 81 58 88 6A 85 +E8 85 02 27 0D 12 84 12 9C 83 EE 85 56 86 B0 80 +34 89 FC 84 40 88 62 84 07 5B 27 5D 0D 12 84 12 +24 89 0A 80 0A 80 58 88 58 88 6A 85 38 89 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +B0 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +9C 83 EE 85 56 86 B0 80 34 89 C2 84 AC 80 8C 89 +0A 80 0A 80 58 88 58 88 0A 80 58 88 58 88 6A 85 +00 00 02 3A 30 12 E2 89 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 9C 83 EE 85 AA 89 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 81 +4E 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A 80 +6A 85 58 88 F4 89 50 89 6A 85 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +A2 88 0C 43 52 45 41 54 45 00 B0 12 98 89 BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 74 83 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 92 89 0E 3A 4E 4F 4E 41 4D 45 30 12 +E2 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 2C 8A 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 24 89 AE 8A 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 3C 89 0A 80 B0 8A +58 88 6A 85 42 8A 08 43 4F 44 45 00 B0 12 98 89 +A2 82 C8 21 61 3C 84 85 0E 48 44 4E 43 4F 44 45 +B2 40 9C 8B CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 F4 89 FA 8A 3D 41 92 42 D0 21 +CC 21 5D 3C C6 8A 0E 43 4F 44 45 4E 4E 4D 30 12 +D0 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F D8 8A 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F 64 8B B2 40 76 8B D0 21 82 4E CE 21 30 40 +FC 84 85 12 62 8B 62 89 0A 89 F4 8B 06 8B 5C 8A +A6 85 50 86 22 89 4A 8B 9C 8A 76 8A 12 8A 6A 88 +7E 8C A8 86 00 00 00 00 85 12 62 8B F8 92 7C 91 +DC 92 A4 90 00 91 4E 91 2A 92 36 92 C6 8F EA 90 +00 00 00 00 38 8B B6 8E 00 00 52 92 96 8B B2 40 +76 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 CA 8B +30 4D DC 8B 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 CA 8B 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 0E 82 FE FF 29 83 B9 40 FA 81 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 DA FF 3B 40 10 00 +3A 40 3A 18 B0 12 CE 8B 82 43 4A 18 C7 3F 70 8C +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 58 89 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 9C 83 +EE 85 56 86 AC 80 9C 8C 90 84 30 88 9E 8C 3E 4F +3D 41 B2 41 C6 21 B0 12 98 89 BA 40 85 12 FC FF +BA 40 6E 8C FE FF 28 83 8A 48 00 00 BA 40 82 80 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 EE 85 +56 86 AC 80 08 8D E8 8C 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 6E 8C 00 00 01 20 +3E 52 2E 83 21 53 30 41 00 87 AC 80 10 8D 04 8D +12 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 D8 8C 15 20 3E 40 2B 00 B0 12 +D8 8C 06 20 3E 40 2D 00 B0 12 D8 8C 92 83 C6 21 +0E 12 1E 41 02 00 84 12 EE 85 00 87 AC 80 34 89 +52 8D 3E 51 3A 17 30 41 B0 12 18 8D 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 EE 85 00 87 AC 80 8A 8D +82 8D 3E 90 10 00 E6 2B 7C 2D 8C 8D A2 41 C6 21 +E1 3F 03 20 B0 12 70 8D 43 3C 7A 90 23 00 24 20 +B0 12 20 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 20 8D F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 6C 8D 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 70 8D 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 58 8D F2 3F +03 20 B0 12 70 8D F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 58 8D EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A 80 00 13 58 88 6A 85 0A 80 +2C 00 4E 8E 92 8D 9C 83 58 8E 30 8E 9E 8E 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +8E 8E 00 40 AA 8E 0A 4D 4F 56 2E 42 85 12 8E 8E +40 40 00 00 06 41 44 44 85 12 8E 8E 00 50 C4 8E +0A 41 44 44 2E 42 85 12 8E 8E 40 50 D0 8E 08 41 +44 44 43 00 85 12 8E 8E 00 60 DE 8E 0C 41 44 44 +43 2E 42 00 85 12 8E 8E 40 60 16 8B 08 53 55 42 +43 00 85 12 8E 8E 00 70 FC 8E 0C 53 55 42 43 2E +42 00 85 12 8E 8E 40 70 0A 8F 06 53 55 42 85 12 +8E 8E 00 80 1A 8F 0A 53 55 42 2E 42 85 12 8E 8E +40 80 26 8F 06 43 4D 50 85 12 8E 8E 00 90 34 8F +0A 43 4D 50 2E 42 85 12 8E 8E 40 90 00 00 08 44 +41 44 44 00 85 12 8E 8E 00 A0 4E 8F 0C 44 41 44 +44 2E 42 00 85 12 8E 8E 40 A0 7C 8E 06 42 49 54 +85 12 8E 8E 00 B0 6C 8F 0A 42 49 54 2E 42 85 12 +8E 8E 40 B0 78 8F 06 42 49 43 85 12 8E 8E 00 C0 +86 8F 0A 42 49 43 2E 42 85 12 8E 8E 40 C0 92 8F +06 42 49 53 85 12 8E 8E 00 D0 A0 8F 0A 42 49 53 +2E 42 85 12 8E 8E 40 D0 00 00 06 58 4F 52 85 12 +8E 8E 00 E0 BA 8F 0A 58 4F 52 2E 42 85 12 8E 8E +40 E0 EC 8E 06 41 4E 44 85 12 8E 8E 00 F0 D4 8F +0A 41 4E 44 2E 42 85 12 8E 8E 40 F0 9C 83 4E 8E +92 8D F4 8F 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F AC 8F 06 52 52 43 85 12 EC 8F 00 10 +06 90 0A 52 52 43 2E 42 85 12 EC 8F 40 10 40 8F +08 53 57 50 42 00 85 12 EC 8F 80 10 12 90 06 52 +52 41 85 12 EC 8F 00 11 2E 90 0A 52 52 41 2E 42 +85 12 EC 8F 40 11 20 90 06 53 58 54 85 12 EC 8F +80 11 00 00 08 50 55 53 48 00 85 12 EC 8F 00 12 +54 90 0C 50 55 53 48 2E 42 00 85 12 EC 8F 40 12 +48 90 08 43 41 4C 4C 00 85 12 EC 8F 80 12 1A 53 +0E 4A 84 12 DE 85 1E 80 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 81 72 90 06 53 3E 3D 86 12 +00 38 9A 90 04 53 3C 00 86 12 00 34 62 90 06 30 +3E 3D 86 12 00 30 AE 90 04 30 3C 00 86 12 00 30 +EA 8A 04 55 3C 00 86 12 00 2C C2 90 06 55 3E 3D +86 12 00 28 B8 90 06 30 3C 3E 86 12 00 24 D6 90 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 5C 8F +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D CC 90 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +3A 90 0A 42 45 47 49 4E 30 40 32 80 24 91 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D E0 8F 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 EE 90 84 84 6A 85 42 91 0C 52 +45 50 45 41 54 00 0D 12 84 12 82 91 06 91 6A 85 +B2 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D 9E 91 06 42 57 31 85 12 +B0 91 00 00 CA 91 06 42 57 32 85 12 B0 91 00 00 +D6 91 06 42 57 33 85 12 B0 91 00 00 EE 91 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 EC 91 00 00 12 92 06 46 +57 32 85 12 EC 91 00 00 1E 92 06 46 57 33 85 12 +EC 91 00 00 8C 91 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 24 89 30 88 6A 85 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 58 8E +0A 80 2C 00 EE 85 00 87 AC 80 34 89 9C 83 4E 8E +30 8E 84 92 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +E2 91 08 52 52 43 4D 00 85 12 6E 92 50 00 B2 92 +08 52 52 41 4D 00 85 12 6E 92 50 01 C0 92 08 52 +4C 41 4D 00 85 12 6E 92 50 02 CE 92 08 52 52 55 +4D 00 85 12 6E 92 50 03 E0 90 0A 50 55 53 48 4D +85 12 6E 92 00 15 EA 92 08 50 4F 50 4D 00 85 12 +6E 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 82 82 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 C4 82 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/LP_MSP430FR2476_16MHz_UART.txt b/binaries/LP_MSP430FR2476_16MHz_UART.txt deleted file mode 100644 index f2080ab..0000000 --- a/binaries/LP_MSP430FR2476_16MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 08 94 02 8C 34 01 -10 00 41 33 94 81 AA 80 DA 81 9C 81 94 82 08 94 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D3 43 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C3 43 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 82 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 7E 92 E4 92 26 92 34 93 EC 91 00 00 B8 8F -00 00 FC 93 E0 93 50 92 8E 92 C8 90 00 00 00 00 -50 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -08 94 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 20 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 -FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 -45 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 -A1 01 B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 -BA 00 82 01 B2 40 E8 01 84 01 B2 D0 10 00 86 01 -B2 40 00 02 88 01 39 40 5C 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 1E D2 -5E 01 B0 12 F8 80 1E 82 38 40 C0 21 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 0E 12 -12 12 C4 21 84 12 2C 85 94 85 F0 83 34 80 F8 8D -50 86 34 80 12 8E 0C 8E FA 8D 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 14 8E B2 41 C4 21 3E 41 84 12 0A 80 2B 00 -2C 85 94 85 F0 83 34 80 30 8E 50 86 34 80 12 88 -BA 83 2C 85 50 86 34 80 12 88 3C 8E 3E 5F E7 3F -3E 40 28 00 B0 12 DC 8D 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 02 20 -30 40 80 89 1C 15 12 12 C4 21 92 53 C4 21 84 12 -2C 85 50 86 34 80 84 8E 7A 8E 21 53 3E 90 10 00 -C6 2B 7F 2D 86 8E B2 41 C4 21 C1 3F 0D 12 84 12 -14 88 B8 8D 96 8E 0C 43 1B 42 C6 21 A2 53 C6 21 -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 B0 12 -DC 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 -18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 -10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 21 B0 12 DC 8D ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 21 B0 12 64 8E 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 64 8E 92 92 C0 21 -C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F B0 12 -64 8E FA 23 3C 50 10 00 B0 12 40 8E EF 3F 0C 43 -1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 88 B8 8D -62 8F FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 64 8E E0 23 3C 50 80 00 B0 12 -40 8E DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 80 00 13 5A 87 60 84 0A 80 2C 00 8C 8E 58 8F -A2 8F 09 4B 2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 -85 12 98 8F 00 40 AC 8F 05 4D 4F 56 2E 42 85 12 -98 8F 40 40 00 00 03 41 44 44 85 12 98 8F 00 50 -C6 8F 05 41 44 44 2E 42 85 12 98 8F 40 50 D2 8F -04 41 44 44 43 00 85 12 98 8F 00 60 E0 8F 06 41 -44 44 43 2E 42 00 85 12 98 8F 40 60 86 8F 04 53 -55 42 43 00 85 12 98 8F 00 70 FE 8F 06 53 55 42 -43 2E 42 00 85 12 98 8F 40 70 0C 90 03 53 55 42 -85 12 98 8F 00 80 1C 90 05 53 55 42 2E 42 85 12 -98 8F 40 80 28 8A 03 43 4D 50 85 12 98 8F 00 90 -36 90 05 43 4D 50 2E 42 85 12 98 8F 40 90 12 8A -04 44 41 44 44 00 85 12 98 8F 00 A0 50 90 06 44 -41 44 44 2E 42 00 85 12 98 8F 40 A0 42 90 03 42 -49 54 85 12 98 8F 00 B0 6E 90 05 42 49 54 2E 42 -85 12 98 8F 40 B0 7A 90 03 42 49 43 85 12 98 8F -00 C0 88 90 05 42 49 43 2E 42 85 12 98 8F 40 C0 -94 90 03 42 49 53 85 12 98 8F 00 D0 A2 90 05 42 -49 53 2E 42 85 12 98 8F 40 D0 00 00 03 58 4F 52 -85 12 98 8F 00 E0 BC 90 05 58 4F 52 2E 42 85 12 -98 8F 40 E0 EE 8F 03 41 4E 44 85 12 98 8F 00 F0 -D6 90 05 41 4E 44 2E 42 85 12 98 8F 40 F0 14 88 -8C 8E F4 90 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 28 90 03 52 52 43 85 12 EE 90 00 10 -06 91 05 52 52 43 2E 42 85 12 EE 90 40 10 12 91 -04 53 57 50 42 00 85 12 EE 90 80 10 20 91 03 52 -52 41 85 12 EE 90 00 11 2E 91 05 52 52 41 2E 42 -85 12 EE 90 40 11 3A 91 03 53 58 54 85 12 EE 90 -80 11 00 00 04 50 55 53 48 00 85 12 EE 90 00 12 -54 91 06 50 55 53 48 2E 42 00 85 12 EE 90 40 12 -AE 90 04 43 41 4C 4C 00 85 12 EE 90 80 12 1A 53 -0E 4A 0D 12 84 12 D6 84 14 80 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 81 48 91 03 53 3E 3D -86 12 00 38 9C 91 02 53 3C 00 86 12 00 34 62 91 -03 30 3E 3D 86 12 00 30 B0 91 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C C4 91 03 55 -3E 3D 86 12 00 28 BA 91 03 30 3C 3E 86 12 00 24 -D8 91 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D -CE 91 04 54 48 45 4E 00 1A 42 C6 21 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 5E 90 04 45 4C 53 45 00 1A 42 C6 21 -BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A 00 00 -E3 3F 72 91 05 42 45 47 49 4E 30 40 28 80 02 92 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 21 30 4D E2 90 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 F0 91 BA 83 60 84 A6 91 -06 52 45 50 45 41 54 00 0D 12 84 12 84 92 08 92 -60 84 B4 92 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 -CB 2F 98 42 C6 21 00 00 30 4D 44 92 03 42 57 31 -85 12 B2 92 00 00 CC 92 03 42 57 32 85 12 B2 92 -00 00 D8 92 03 42 57 33 85 12 B2 92 00 00 F0 92 -3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B BA 4F -00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 EE 92 00 00 10 93 03 46 57 32 -85 12 EE 92 00 00 1C 93 03 46 57 33 85 12 EE 92 -00 00 28 93 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 92 88 EE 87 60 84 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 88 B8 8D -72 93 92 53 C4 21 3E 40 2C 00 84 12 2C 85 50 86 -34 80 12 88 4E 8F 88 93 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E A0 92 04 52 52 43 4D 00 85 12 6C 93 -50 00 B6 93 04 52 52 41 4D 00 85 12 6C 93 50 01 -C4 93 04 52 4C 41 4D 00 85 12 6C 93 50 02 D2 93 -04 52 52 55 4D 00 85 12 6C 93 50 03 E2 91 05 50 -55 53 48 4D 85 12 6C 93 00 15 EE 93 04 50 4F 50 -4D 00 85 12 6C 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -94 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/LP_MSP430FR2476_1MHz_115200.txt b/binaries/LP_MSP430FR2476_1MHz_115200.txt new file mode 100644 index 0000000..967989f --- /dev/null +++ b/binaries/LP_MSP430FR2476_1MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 19 +B4 82 7E 81 84 81 54 81 24 83 12 93 CA 8B 84 8B +84 8B 9A 82 58 83 20 83 3C 21 E0 20 78 85 B6 80 +C4 80 94 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +24 83 12 93 CA 8B 84 8B 84 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F5 3C 0E 93 3E 4F +8A 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 98 82 B2 49 +56 83 B2 49 1E 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 3E 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 24 83 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 80 9E 84 AC 80 52 81 66 83 1E 80 04 1B +5B 37 6D 00 88 83 88 83 1E 80 04 1B 5B 30 6D 00 +88 83 D4 88 B0 12 7E 81 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 66 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 88 83 EC 85 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 88 83 0A 80 40 FF 32 80 +B4 84 B8 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 +FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 +45 02 B2 40 00 A5 60 01 B2 D0 10 00 86 01 F2 C3 +82 01 B2 40 1E 00 84 01 39 40 5C 00 18 42 00 18 +18 83 FE 23 19 83 FA 23 39 40 00 20 29 83 89 43 +00 20 FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 +3E F3 01 20 0E 49 B0 12 D0 80 86 81 00 00 0C 41 +43 43 45 50 54 00 30 40 9A 82 08 4E 2E 4F 08 5E +39 40 0D 00 3A 40 20 00 3B 40 F8 82 3C 40 04 83 +5D 15 A6 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 +A2 B3 1C 05 FD 27 B2 40 13 00 0E 05 E2 D3 43 02 +30 41 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 +05 3C 0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 +FD 27 C2 48 0E 05 30 4D FA 82 2D 83 92 B3 1C 05 +DB 23 FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 +0C 05 08 4C EB 3F 00 00 06 4B 45 59 30 40 20 83 +30 12 36 83 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 +E2 C3 43 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 +FD 27 B0 12 C0 82 1E 42 0C 05 30 4D 00 00 08 45 +4D 49 54 00 30 40 58 83 08 4E 3E 4F C7 3F 4E 83 +08 45 43 48 4F 00 B2 40 C2 48 F2 82 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D F2 82 30 4D +00 00 08 54 59 50 45 00 0D 12 3D 40 98 83 29 4F +8F 4E 00 00 7E 49 DE 3F 9A 83 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 7C 22 F9 98 00 00 79 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +70 22 9B 24 18 83 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A 80 00 00 B8 84 AA 83 FC 85 B6 88 B0 80 +26 84 14 80 06 5B 54 48 45 4E 5D 00 AE 83 04 84 +CA 83 E8 83 14 80 06 5B 45 4C 53 45 5D 00 AE 83 +16 84 CA 83 E6 83 1E 80 04 5B 49 46 5D 00 AE 83 +E8 83 B2 80 E6 83 1E 80 05 0D 6B 6F 20 0A 88 83 +9A 80 84 80 B2 80 E8 83 D6 83 0D 5B 54 48 45 4E +5D 00 30 4D 3A 84 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D 46 84 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 AA 83 FC 85 64 86 08 88 78 85 56 84 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +AA 83 FC 85 64 86 88 84 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D 8E 82 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +D8 81 05 53 22 00 82 43 C0 21 0D 12 84 12 0A 80 +1E 80 66 88 0A 80 22 00 FC 85 FC 84 B2 40 20 00 +C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D +70 83 05 2E 22 00 0D 12 84 12 E6 84 0A 80 88 83 +66 88 78 85 00 00 04 3C 23 00 B2 40 B2 21 B2 21 +30 4D E2 84 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 +46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 +30 4D 34 85 04 23 53 00 0D 12 84 12 36 85 70 85 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D 64 85 04 23 +3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 7E 85 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 60 83 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 2A 85 AA 83 98 85 68 85 94 84 +A6 85 82 85 88 83 78 85 12 85 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 +1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D EA 85 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 +8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 +0C 4E 0E 43 1E 15 3D 40 6E 87 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 70 87 +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 +0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 80 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D 26 85 03 5C +92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 80 AA 83 +FC 85 B0 80 40 89 64 86 2A 88 0A 4E 3E 4F 3D 40 +44 88 6D 27 3D 40 1E 88 1A E2 BC 21 14 24 0E 12 +3E 4F 30 41 46 88 3E 4F 3D 40 1E 88 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 1C 8A +2A 3C 0E 88 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E +FE FF 3E 4F 30 4D 64 88 0F 4C 49 54 45 52 41 4C +82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 +BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D A0 85 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D C6 84 0A 41 4C 4C 4F 54 82 5E C8 21 +3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E 80 02 0D +0A 00 88 83 94 80 18 88 A6 84 D0 84 1E 80 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 81 32 80 0A 80 +40 FF D8 84 1E 80 09 46 52 41 4D 20 66 75 6C 6C +08 81 B2 80 DC 88 C6 88 0D 41 42 4F 52 54 22 00 +0D 12 84 12 E6 84 0A 80 08 81 66 88 78 85 F6 85 +02 27 0D 12 84 12 AA 83 FC 85 64 86 B0 80 42 89 +0A 85 4E 88 70 84 07 5B 27 5D 0D 12 84 12 32 89 +0A 80 0A 80 66 88 66 88 78 85 46 89 03 5B 82 43 +BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D BE 84 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 AA 83 +FC 85 64 86 B0 80 42 89 D0 84 AC 80 9A 89 0A 80 +0A 80 66 88 66 88 0A 80 66 88 66 88 78 85 00 00 +02 3A 30 12 F0 89 92 B3 C8 21 A2 63 C8 21 0D 12 +84 12 AA 83 FC 85 B8 89 3D 41 5A D3 5A 53 0A 5E +19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 +82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 +30 4D 82 9F BA 21 66 25 84 12 1E 80 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 81 5C 89 +03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A 80 78 85 +66 88 02 8A 5E 89 78 85 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D B0 88 +0C 43 52 45 41 54 45 00 B0 12 A6 89 BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D 82 83 0A 44 4F 45 53 3E +1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D A0 89 0E 3A 4E 4F 4E 41 4D 45 30 12 F0 89 +2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F 3A 8A 05 49 53 00 0D 12 +82 93 BC 21 08 20 84 12 32 89 BC 8A 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 4A 89 0A 80 BE 8A 66 88 +78 85 50 8A 08 43 4F 44 45 00 B0 12 A6 89 A2 82 +C8 21 61 3C 92 85 0E 48 44 4E 43 4F 44 45 B2 40 +AA 8B CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 02 8A 08 8B 3D 41 92 42 D0 21 CC 21 +5D 3C D4 8A 0E 43 4F 44 45 4E 4E 4D 30 12 DE 8A +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 +BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 +1A 42 C8 21 EF 3F E6 8A 0B 48 49 32 4C 4F A2 53 +C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F +72 8B B2 40 84 8B D0 21 82 4E CE 21 30 40 0A 85 +85 12 70 8B 70 89 18 89 02 8C 14 8B 6A 8A B4 85 +5E 86 30 89 58 8B AA 8A 84 8A 20 8A 78 88 8C 8C +B6 86 00 00 00 00 85 12 70 8B 06 93 8A 91 EA 92 +B2 90 0E 91 5C 91 38 92 44 92 D4 8F F8 90 00 00 +00 00 46 8B C4 8E 00 00 60 92 A4 8B B2 40 84 8B +CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 21 3A 40 42 18 B0 12 D8 8B 30 4D +EA 8B 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 21 B0 12 D8 8B 1A 42 CA 21 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +06 82 FE FF 29 83 B9 40 F2 81 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 E0 FF 3B 40 10 00 3A 40 +3A 18 B0 12 DC 8B 82 43 4A 18 C7 3F 7E 8C B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F 66 89 0C 4D 41 52 +4B 45 52 00 12 12 C6 21 0D 12 84 12 AA 83 FC 85 +64 86 AC 80 AA 8C 9E 84 3E 88 AC 8C 3E 4F 3D 41 +B2 41 C6 21 B0 12 A6 89 BA 40 85 12 FC FF BA 40 +7C 8C FE FF 28 83 8A 48 00 00 BA 40 82 80 02 00 +A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 21 84 12 FC 85 64 86 +AC 80 16 8D F6 8C 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 7C 8C 00 00 01 20 3E 52 +2E 83 21 53 30 41 0E 87 AC 80 1E 8D 12 8D 20 8D +B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E +3D 15 B0 12 E6 8C 15 20 3E 40 2B 00 B0 12 E6 8C +06 20 3E 40 2D 00 B0 12 E6 8C 92 83 C6 21 0E 12 +1E 41 02 00 84 12 FC 85 0E 87 AC 80 42 89 60 8D +3E 51 3A 17 30 41 B0 12 26 8D 19 42 C8 21 89 4E +00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 +C6 21 3D 15 84 12 FC 85 0E 87 AC 80 98 8D 90 8D +3E 90 10 00 E6 2B 7C 2D 9A 8D A2 41 C6 21 E1 3F +03 20 B0 12 7E 8D 43 3C 7A 90 23 00 24 20 B0 12 +2E 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 +10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 +08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 2E 8D F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 7A 8D 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +7E 8D 92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 66 8D F2 3F 03 20 +B0 12 7E 8D F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 66 8D EA 3F 0C 43 1B 42 +C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 +C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 +C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A 80 00 13 66 88 78 85 0A 80 2C 00 +5C 8E A0 8D AA 83 66 8E 3E 8E AC 8E 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 9C 8E +00 40 B8 8E 0A 4D 4F 56 2E 42 85 12 9C 8E 40 40 +00 00 06 41 44 44 85 12 9C 8E 00 50 D2 8E 0A 41 +44 44 2E 42 85 12 9C 8E 40 50 DE 8E 08 41 44 44 +43 00 85 12 9C 8E 00 60 EC 8E 0C 41 44 44 43 2E +42 00 85 12 9C 8E 40 60 24 8B 08 53 55 42 43 00 +85 12 9C 8E 00 70 0A 8F 0C 53 55 42 43 2E 42 00 +85 12 9C 8E 40 70 18 8F 06 53 55 42 85 12 9C 8E +00 80 28 8F 0A 53 55 42 2E 42 85 12 9C 8E 40 80 +34 8F 06 43 4D 50 85 12 9C 8E 00 90 42 8F 0A 43 +4D 50 2E 42 85 12 9C 8E 40 90 00 00 08 44 41 44 +44 00 85 12 9C 8E 00 A0 5C 8F 0C 44 41 44 44 2E +42 00 85 12 9C 8E 40 A0 8A 8E 06 42 49 54 85 12 +9C 8E 00 B0 7A 8F 0A 42 49 54 2E 42 85 12 9C 8E +40 B0 86 8F 06 42 49 43 85 12 9C 8E 00 C0 94 8F +0A 42 49 43 2E 42 85 12 9C 8E 40 C0 A0 8F 06 42 +49 53 85 12 9C 8E 00 D0 AE 8F 0A 42 49 53 2E 42 +85 12 9C 8E 40 D0 00 00 06 58 4F 52 85 12 9C 8E +00 E0 C8 8F 0A 58 4F 52 2E 42 85 12 9C 8E 40 E0 +FA 8E 06 41 4E 44 85 12 9C 8E 00 F0 E2 8F 0A 41 +4E 44 2E 42 85 12 9C 8E 40 F0 AA 83 5C 8E A0 8D +02 90 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F BA 8F 06 52 52 43 85 12 FA 8F 00 10 14 90 +0A 52 52 43 2E 42 85 12 FA 8F 40 10 4E 8F 08 53 +57 50 42 00 85 12 FA 8F 80 10 20 90 06 52 52 41 +85 12 FA 8F 00 11 3C 90 0A 52 52 41 2E 42 85 12 +FA 8F 40 11 2E 90 06 53 58 54 85 12 FA 8F 80 11 +00 00 08 50 55 53 48 00 85 12 FA 8F 00 12 62 90 +0C 50 55 53 48 2E 42 00 85 12 FA 8F 40 12 56 90 +08 43 41 4C 4C 00 85 12 FA 8F 80 12 1A 53 0E 4A +84 12 EC 85 1E 80 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 81 80 90 06 53 3E 3D 86 12 00 38 +A8 90 04 53 3C 00 86 12 00 34 70 90 06 30 3E 3D +86 12 00 30 BC 90 04 30 3C 00 86 12 00 30 F8 8A +04 55 3C 00 86 12 00 2C D0 90 06 55 3E 3D 86 12 +00 28 C6 90 06 30 3C 3E 86 12 00 24 E4 90 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 +8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 6A 8F 08 54 +48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +DA 90 08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C +00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 48 90 +0A 42 45 47 49 4E 30 40 32 80 32 91 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 21 30 4D EE 8F 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 FC 90 92 84 78 85 50 91 0C 52 45 50 +45 41 54 00 0D 12 84 12 90 91 14 91 78 85 C0 91 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 +C8 21 00 00 30 4D AC 91 06 42 57 31 85 12 BE 91 +00 00 D8 91 06 42 57 32 85 12 BE 91 00 00 E4 91 +06 42 57 33 85 12 BE 91 00 00 FC 91 3D 41 1A 42 +C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F +00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 FA 91 00 00 20 92 06 46 57 32 +85 12 FA 91 00 00 2C 92 06 46 57 33 85 12 FA 91 +00 00 9A 91 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 32 89 3E 88 78 85 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F 66 8E 0A 80 +2C 00 FC 85 0E 87 AC 80 42 89 AA 83 5C 8E 3E 8E +92 92 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E F0 91 +08 52 52 43 4D 00 85 12 7C 92 50 00 C0 92 08 52 +52 41 4D 00 85 12 7C 92 50 01 CE 92 08 52 4C 41 +4D 00 85 12 7C 92 50 02 DC 92 08 52 52 55 4D 00 +85 12 7C 92 50 03 EE 90 0A 50 55 53 48 4D 85 12 +7C 92 00 15 F8 92 08 50 4F 50 4D 00 85 12 7C 92 +00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +B4 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/LP_MSP430FR2476_1MHz_I2C.txt b/binaries/LP_MSP430FR2476_1MHz_I2C.txt index 064f592..fbc7a2a 100644 --- a/binaries/LP_MSP430FR2476_1MHz_I2C.txt +++ b/binaries/LP_MSP430FR2476_1MHz_I2C.txt @@ -1,335 +1,321 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF E2 93 F0 8B 34 01 -10 00 41 07 B6 81 AA 80 B8 81 8C 81 82 82 E2 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 03 +AE 82 56 81 56 81 58 81 44 81 EE 92 A6 8B 60 8B +60 8B 9C 82 20 83 F8 82 3C 21 E0 20 54 85 B6 80 +C4 80 70 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 EE 92 A6 8B 60 8B 60 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 80 05 18 42 02 18 08 11 38 D0 00 04 -82 48 94 05 F2 D0 0C 00 2A 02 92 C3 80 05 A2 D2 -AA 05 92 C3 30 01 30 41 48 43 A2 B3 AC 05 FD 27 -C2 48 8E 05 A2 B2 AC 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 AC 05 B2 B0 10 00 80 05 B8 22 -3A 17 92 B3 AC 05 FD 27 58 42 8C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 AC 05 FD 27 1E 42 8C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 AC 05 FD 27 C2 48 8E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -58 92 BE 92 00 92 0E 93 C6 91 00 00 92 8F 00 00 -D6 93 BA 93 2A 92 68 92 A2 90 00 00 00 00 2A 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C E2 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -DA FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 20 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 FF 7F -22 02 B2 D3 46 02 B2 40 FC FF 42 02 B2 40 00 A5 -60 01 B2 40 FF 1E 80 01 B2 40 B0 00 82 01 B2 40 -1E 00 84 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 -39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 F8 80 -FE 81 38 40 C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 84 12 -1A 85 82 85 DE 83 34 80 D2 8D 3E 86 34 80 EC 8D -E6 8D D4 8D 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 EE 8D B2 41 -C4 21 3E 41 84 12 0A 80 2B 00 1A 85 82 85 DE 83 -34 80 0A 8E 3E 86 34 80 00 88 A8 83 1A 85 3E 86 -34 80 00 88 16 8E 3E 5F E7 3F 3E 40 28 00 B0 12 -B6 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 40 -29 00 92 92 C0 21 C4 21 02 20 30 40 6E 89 1C 15 -12 12 C4 21 92 53 C4 21 84 12 1A 85 3E 86 34 80 -5E 8E 54 8E 21 53 3E 90 10 00 C6 2B 7F 2D 60 8E -B2 41 C4 21 C1 3F 0D 12 84 12 02 88 92 8D 70 8E -0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 21 B0 12 B6 8D 3C 40 00 03 -0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 -2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 -3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 21 -B0 12 B6 8D ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 21 B0 12 3E 8E 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 3E 8E 92 92 C0 21 C4 21 02 24 92 53 -C4 21 8E 10 0C 5E DA 3F B0 12 3E 8E FA 23 3C 50 -10 00 B0 12 1A 8E EF 3F 0C 43 1B 42 C6 21 A2 53 -C6 21 0D 12 84 12 02 88 92 8D 3C 8F FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -3E 8E E0 23 3C 50 80 00 B0 12 1A 8E DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 48 87 -4E 84 0A 80 2C 00 66 8E 32 8F 7C 8F 09 4B 2E 4E -0E DC A2 3F 40 8A 03 4D 4F 56 85 12 72 8F 00 40 -86 8F 05 4D 4F 56 2E 42 85 12 72 8F 40 40 00 00 -03 41 44 44 85 12 72 8F 00 50 A0 8F 05 41 44 44 -2E 42 85 12 72 8F 40 50 AC 8F 04 41 44 44 43 00 -85 12 72 8F 00 60 BA 8F 06 41 44 44 43 2E 42 00 -85 12 72 8F 40 60 60 8F 04 53 55 42 43 00 85 12 -72 8F 00 70 D8 8F 06 53 55 42 43 2E 42 00 85 12 -72 8F 40 70 E6 8F 03 53 55 42 85 12 72 8F 00 80 -F6 8F 05 53 55 42 2E 42 85 12 72 8F 40 80 16 8A -03 43 4D 50 85 12 72 8F 00 90 10 90 05 43 4D 50 -2E 42 85 12 72 8F 40 90 00 8A 04 44 41 44 44 00 -85 12 72 8F 00 A0 2A 90 06 44 41 44 44 2E 42 00 -85 12 72 8F 40 A0 1C 90 03 42 49 54 85 12 72 8F -00 B0 48 90 05 42 49 54 2E 42 85 12 72 8F 40 B0 -54 90 03 42 49 43 85 12 72 8F 00 C0 62 90 05 42 -49 43 2E 42 85 12 72 8F 40 C0 6E 90 03 42 49 53 -85 12 72 8F 00 D0 7C 90 05 42 49 53 2E 42 85 12 -72 8F 40 D0 00 00 03 58 4F 52 85 12 72 8F 00 E0 -96 90 05 58 4F 52 2E 42 85 12 72 8F 40 E0 C8 8F -03 41 4E 44 85 12 72 8F 00 F0 B0 90 05 41 4E 44 -2E 42 85 12 72 8F 40 F0 02 88 66 8E CE 90 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 02 90 -03 52 52 43 85 12 C8 90 00 10 E0 90 05 52 52 43 -2E 42 85 12 C8 90 40 10 EC 90 04 53 57 50 42 00 -85 12 C8 90 80 10 FA 90 03 52 52 41 85 12 C8 90 -00 11 08 91 05 52 52 41 2E 42 85 12 C8 90 40 11 -14 91 03 53 58 54 85 12 C8 90 80 11 00 00 04 50 -55 53 48 00 85 12 C8 90 00 12 2E 91 06 50 55 53 -48 2E 42 00 85 12 C8 90 40 12 88 90 04 43 41 4C -4C 00 85 12 C8 90 80 12 1A 53 0E 4A 0D 12 84 12 -C4 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 81 22 91 03 53 3E 3D 86 12 00 38 76 91 -02 53 3C 00 86 12 00 34 3C 91 03 30 3E 3D 86 12 -00 30 8A 91 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C 9E 91 03 55 3E 3D 86 12 00 28 -94 91 03 30 3C 3E 86 12 00 24 B2 91 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 0E 4A 30 4D A8 91 04 54 48 45 -4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 38 90 -04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C 00 00 -A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 4C 91 05 42 -45 47 49 4E 30 40 28 80 DC 91 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 21 30 4D BC 90 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 CA 91 A8 83 4E 84 80 91 06 52 45 50 45 41 -54 00 0D 12 84 12 5E 92 E2 91 4E 84 8E 92 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 -00 00 30 4D 1E 92 03 42 57 31 85 12 8C 92 00 00 -A6 92 03 42 57 32 85 12 8C 92 00 00 B2 92 03 42 -57 33 85 12 8C 92 00 00 CA 92 3D 41 1A 42 C6 21 -28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 C6 21 -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -C8 92 00 00 EA 92 03 46 57 32 85 12 C8 92 00 00 -F6 92 03 46 57 33 85 12 C8 92 00 00 02 93 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 80 88 DC 87 4E 84 00 00 05 3F 47 4F 54 4F -3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 02 88 92 8D 4C 93 92 53 C4 21 -3E 40 2C 00 84 12 1A 85 3E 86 34 80 00 88 28 8F -62 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 7A 92 -04 52 52 43 4D 00 85 12 46 93 50 00 90 93 04 52 -52 41 4D 00 85 12 46 93 50 01 9E 93 04 52 4C 41 -4D 00 85 12 46 93 50 02 AC 93 04 52 52 55 4D 00 -85 12 46 93 50 03 BC 91 05 50 55 53 48 4D 85 12 -46 93 00 15 C8 93 04 50 4F 50 4D 00 85 12 46 93 -00 17 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F6 3C 0E 93 3E 4F +78 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9A 82 B2 49 +1E 83 B2 49 F6 82 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 1A 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 7A 84 AC 80 +42 81 38 83 1E 80 05 1B 5B 37 6D 40 64 83 0A 80 +02 18 9C 84 C8 85 64 83 1E 80 04 1B 5B 30 6D 00 +64 83 B0 88 48 43 A2 B3 AC 05 FD 27 C2 48 8E 05 +A2 B2 AC 05 FD 27 30 41 B2 D0 C0 07 80 05 18 42 +02 18 08 11 38 D0 00 04 82 48 94 05 F2 D0 0C 00 +2A 02 92 C3 80 05 A2 D2 AA 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 38 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 64 83 0A 80 02 18 9C 84 C8 85 0A 80 23 00 +1C 83 C8 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +64 83 0A 80 40 FF 32 80 90 84 94 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 40 FF 7F 22 02 B2 D3 46 02 +B2 40 FC FF 42 02 B2 40 00 A5 60 01 B2 D0 10 00 +86 01 F2 C3 82 01 B2 40 1E 00 84 01 39 40 5C 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 00 20 +29 83 89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 +3E F3 02 20 1E 42 5E 01 B0 12 D0 80 80 81 00 00 +0C 41 43 43 45 50 54 00 30 40 9C 82 0A 4E 2E 4F +0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 A9 3E 21 52 +A2 C2 AC 05 B2 B0 10 00 80 05 A2 22 3A 17 92 B3 +AC 05 FD 27 58 42 8C 05 48 9B 0E 24 48 9C 06 2C +78 92 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F +CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 +06 4B 45 59 30 40 F8 82 58 43 B0 12 46 81 2F 83 +8F 4E 00 00 92 B3 AC 05 FD 27 1E 42 8C 05 B0 12 +44 81 30 4D 00 00 08 45 4D 49 54 00 30 40 20 83 +08 4E 3E 4F A2 B3 AC 05 FD 27 C2 48 8E 05 30 4D +16 83 08 45 43 48 4F 00 B2 40 C2 48 2A 83 38 40 +05 00 B0 12 46 81 30 4D 00 00 0C 4E 4F 45 43 48 +4F 00 B2 40 30 4D 2A 83 28 42 F3 3F 00 00 08 54 +59 50 45 00 0D 12 3D 40 74 83 29 4F 8F 4E 00 00 +7E 49 D4 3F 76 83 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 8E 22 F9 98 00 00 8B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 82 22 9B 24 +F0 82 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 80 +00 00 94 84 86 83 D8 85 92 88 B0 80 02 84 14 80 +06 5B 54 48 45 4E 5D 00 8A 83 E0 83 A6 83 C4 83 +14 80 06 5B 45 4C 53 45 5D 00 8A 83 F2 83 A6 83 +C2 83 1E 80 04 5B 49 46 5D 00 8A 83 C4 83 B2 80 +C2 83 1E 80 05 0D 6B 6F 20 0A 64 83 9A 80 84 80 +B2 80 C4 83 B2 83 0D 5B 54 48 45 4E 5D 00 30 4D +16 84 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +22 84 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +86 83 D8 85 40 86 E4 87 54 85 32 84 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 86 83 D8 85 +40 86 64 84 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +90 82 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D E0 81 05 53 +22 00 82 43 C0 21 0D 12 84 12 0A 80 1E 80 42 88 +0A 80 22 00 D8 85 D8 84 B2 40 20 00 C0 21 1A 53 +1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 4A 83 05 2E +22 00 0D 12 84 12 C2 84 0A 80 64 83 42 88 54 85 +00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D BE 84 +02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D 10 85 +04 23 53 00 0D 12 84 12 12 85 4C 85 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 40 85 04 23 3E 00 9F 42 +B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 5A 85 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 32 83 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 06 85 86 83 74 85 44 85 70 84 82 85 5E 85 +64 83 54 85 EE 84 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +C6 85 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E 0E 43 +1E 15 3D 40 4A 87 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 4C 87 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 02 85 03 5C 92 42 C2 21 +C6 21 30 4D 0D 12 84 12 84 80 86 83 D8 85 B0 80 +1C 89 40 86 06 88 0A 4E 3E 4F 3D 40 20 88 6D 27 +3D 40 FA 87 1A E2 BC 21 14 24 0E 12 3E 4F 30 41 +22 88 3E 4F 3D 40 FA 87 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 F8 89 2A 3C EA 87 +02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F +30 4D 40 88 0F 4C 49 54 45 52 41 4C 82 93 BC 21 +0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D 7C 85 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +A2 84 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D +3F 40 80 20 0E 43 84 12 1E 80 02 0D 0A 00 64 83 +94 80 F4 87 82 84 AC 84 1E 80 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 81 32 80 0A 80 40 FF B4 84 +1E 80 09 46 52 41 4D 20 66 75 6C 6C 08 81 B2 80 +B8 88 A2 88 0D 41 42 4F 52 54 22 00 0D 12 84 12 +C2 84 0A 80 08 81 42 88 54 85 D2 85 02 27 0D 12 +84 12 86 83 D8 85 40 86 B0 80 1E 89 E6 84 2A 88 +4C 84 07 5B 27 5D 0D 12 84 12 0E 89 0A 80 0A 80 +42 88 42 88 54 85 22 89 03 5B 82 43 BC 21 30 4D +00 00 02 5D B2 43 BC 21 30 4D 9A 84 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 86 83 D8 85 40 86 +B0 80 1E 89 AC 84 AC 80 76 89 0A 80 0A 80 42 88 +42 88 0A 80 42 88 42 88 54 85 00 00 02 3A 30 12 +CC 89 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 86 83 +D8 85 94 89 3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A B8 21 +82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D 82 9F +BA 21 66 25 84 12 1E 80 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 81 38 89 03 3B 82 93 +BC 21 F4 26 0D 12 84 12 0A 80 54 85 42 88 DE 89 +3A 89 54 85 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 21 D8 D3 00 00 30 4D 8C 88 0C 43 52 45 +41 54 45 00 B0 12 82 89 BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 5E 83 0A 44 4F 45 53 3E 1A 42 B8 21 +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D 7C 89 +0E 3A 4E 4F 4E 41 4D 45 30 12 CC 89 2F 83 8F 4E +00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 16 8A 05 49 53 00 0D 12 82 93 BC 21 +08 20 84 12 0E 89 98 8A 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 26 89 0A 80 9A 8A 42 88 54 85 2C 8A +08 43 4F 44 45 00 B0 12 82 89 A2 82 C8 21 61 3C +6E 85 0E 48 44 4E 43 4F 44 45 B2 40 86 8B CC 21 +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +DE 89 E4 8A 3D 41 92 42 D0 21 CC 21 5D 3C B0 8A +0E 43 4F 44 45 4E 4E 4D 30 12 BA 8A B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 C8 21 +EF 3F C2 8A 0B 48 49 32 4C 4F A2 53 C8 21 1A 42 +C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 4E 8B B2 40 +60 8B D0 21 82 4E CE 21 30 40 E6 84 85 12 4C 8B +4C 89 F4 88 DE 8B F0 8A 46 8A 90 85 3A 86 0C 89 +34 8B 86 8A 60 8A FC 89 54 88 68 8C 92 86 00 00 +00 00 85 12 4C 8B E2 92 66 91 C6 92 8E 90 EA 90 +38 91 14 92 20 92 B0 8F D4 90 00 00 00 00 22 8B +A0 8E 00 00 3C 92 80 8B B2 40 60 8B CE 21 82 43 +D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 21 3A 40 42 18 B0 12 B4 8B 30 4D C6 8B 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 21 +B0 12 B4 8B 1A 42 CA 21 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 0E 82 FE FF +29 83 B9 40 FA 81 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 DA FF 3B 40 10 00 3A 40 3A 18 B0 12 +B8 8B 82 43 4A 18 C7 3F 5A 8C B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 42 89 0C 4D 41 52 4B 45 52 00 +12 12 C6 21 0D 12 84 12 86 83 D8 85 40 86 AC 80 +86 8C 7A 84 1A 88 88 8C 3E 4F 3D 41 B2 41 C6 21 +B0 12 82 89 BA 40 85 12 FC FF BA 40 58 8C FE FF +28 83 8A 48 00 00 BA 40 82 80 02 00 A2 52 C8 21 +18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 21 84 12 D8 85 40 86 AC 80 F2 8C +D2 8C 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 58 8C 00 00 01 20 3E 52 2E 83 21 53 +30 41 EA 86 AC 80 FA 8C EE 8C FC 8C B2 41 C6 21 +30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 +C2 8C 15 20 3E 40 2B 00 B0 12 C2 8C 06 20 3E 40 +2D 00 B0 12 C2 8C 92 83 C6 21 0E 12 1E 41 02 00 +84 12 D8 85 EA 86 AC 80 1E 89 3C 8D 3E 51 3A 17 +30 41 B0 12 02 8D 19 42 C8 21 89 4E 00 00 A2 53 +C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 3D 15 +84 12 D8 85 EA 86 AC 80 74 8D 6C 8D 3E 90 10 00 +E6 2B 7C 2D 76 8D A2 41 C6 21 E1 3F 03 20 B0 12 +5A 8D 43 3C 7A 90 23 00 24 20 B0 12 0A 8D 3C 40 +00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 +20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 +30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 +30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 0A 8D +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 56 8D +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 5A 8D 92 92 +C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 42 8D F2 3F 03 20 B0 12 5A 8D +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 42 8D EA 3F 0C 43 1B 42 C8 21 A2 53 +C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 7A 99 +FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A 80 00 13 42 88 54 85 0A 80 2C 00 38 8E 7C 8D +86 83 42 8E 1A 8E 88 8E 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 78 8E 00 40 94 8E +0A 4D 4F 56 2E 42 85 12 78 8E 40 40 00 00 06 41 +44 44 85 12 78 8E 00 50 AE 8E 0A 41 44 44 2E 42 +85 12 78 8E 40 50 BA 8E 08 41 44 44 43 00 85 12 +78 8E 00 60 C8 8E 0C 41 44 44 43 2E 42 00 85 12 +78 8E 40 60 00 8B 08 53 55 42 43 00 85 12 78 8E +00 70 E6 8E 0C 53 55 42 43 2E 42 00 85 12 78 8E +40 70 F4 8E 06 53 55 42 85 12 78 8E 00 80 04 8F +0A 53 55 42 2E 42 85 12 78 8E 40 80 10 8F 06 43 +4D 50 85 12 78 8E 00 90 1E 8F 0A 43 4D 50 2E 42 +85 12 78 8E 40 90 00 00 08 44 41 44 44 00 85 12 +78 8E 00 A0 38 8F 0C 44 41 44 44 2E 42 00 85 12 +78 8E 40 A0 66 8E 06 42 49 54 85 12 78 8E 00 B0 +56 8F 0A 42 49 54 2E 42 85 12 78 8E 40 B0 62 8F +06 42 49 43 85 12 78 8E 00 C0 70 8F 0A 42 49 43 +2E 42 85 12 78 8E 40 C0 7C 8F 06 42 49 53 85 12 +78 8E 00 D0 8A 8F 0A 42 49 53 2E 42 85 12 78 8E +40 D0 00 00 06 58 4F 52 85 12 78 8E 00 E0 A4 8F +0A 58 4F 52 2E 42 85 12 78 8E 40 E0 D6 8E 06 41 +4E 44 85 12 78 8E 00 F0 BE 8F 0A 41 4E 44 2E 42 +85 12 78 8E 40 F0 86 83 38 8E 7C 8D DE 8F 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F 96 8F +06 52 52 43 85 12 D6 8F 00 10 F0 8F 0A 52 52 43 +2E 42 85 12 D6 8F 40 10 2A 8F 08 53 57 50 42 00 +85 12 D6 8F 80 10 FC 8F 06 52 52 41 85 12 D6 8F +00 11 18 90 0A 52 52 41 2E 42 85 12 D6 8F 40 11 +0A 90 06 53 58 54 85 12 D6 8F 80 11 00 00 08 50 +55 53 48 00 85 12 D6 8F 00 12 3E 90 0C 50 55 53 +48 2E 42 00 85 12 D6 8F 40 12 32 90 08 43 41 4C +4C 00 85 12 D6 8F 80 12 1A 53 0E 4A 84 12 C8 85 +1E 80 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 81 5C 90 06 53 3E 3D 86 12 00 38 84 90 04 53 +3C 00 86 12 00 34 4C 90 06 30 3E 3D 86 12 00 30 +98 90 04 30 3C 00 86 12 00 30 D4 8A 04 55 3C 00 +86 12 00 2C AC 90 06 55 3E 3D 86 12 00 28 A2 90 +06 30 3C 3E 86 12 00 24 C0 90 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E 00 00 +A2 53 C8 21 0E 4A 30 4D 46 8F 08 54 48 45 4E 00 +1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D B6 90 08 45 +4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 A2 53 +C8 21 2F 83 8F 4A 00 00 E3 3F 24 90 0A 42 45 47 +49 4E 30 40 32 80 0E 91 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 21 30 4D CA 8F 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +D8 90 6E 84 54 85 2C 91 0C 52 45 50 45 41 54 00 +0D 12 84 12 6C 91 F0 90 54 85 9C 91 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 00 00 +30 4D 88 91 06 42 57 31 85 12 9A 91 00 00 B4 91 +06 42 57 32 85 12 9A 91 00 00 C0 91 06 42 57 33 +85 12 9A 91 00 00 D8 91 3D 41 1A 42 C8 21 28 4E +8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 A2 53 +C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 D6 91 00 00 FC 91 06 46 57 32 85 12 D6 91 +00 00 08 92 06 46 57 33 85 12 D6 91 00 00 76 91 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 0E 89 1A 88 54 85 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F 42 8E 0A 80 2C 00 D8 85 +EA 86 AC 80 1E 89 86 83 38 8E 1A 8E 6E 92 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E CC 91 08 52 52 43 +4D 00 85 12 58 92 50 00 9C 92 08 52 52 41 4D 00 +85 12 58 92 50 01 AA 92 08 52 4C 41 4D 00 85 12 +58 92 50 02 B8 92 08 52 52 55 4D 00 85 12 58 92 +50 03 CA 90 0A 50 55 53 48 4D 85 12 58 92 00 15 +D4 92 08 50 4F 50 4D 00 85 12 58 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 82 82 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 AE 82 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/LP_MSP430FR2476_1MHz_UART.txt b/binaries/LP_MSP430FR2476_1MHz_UART.txt deleted file mode 100644 index 8dcc6e6..0000000 --- a/binaries/LP_MSP430FR2476_1MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF F8 93 02 8C 34 01 -10 00 41 33 94 81 AA 80 DA 81 9C 81 94 82 F8 93 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D3 43 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C3 43 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 82 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 6E 92 D4 92 16 92 24 93 DC 91 00 00 A8 8F -00 00 EC 93 D0 93 40 92 7E 92 B8 90 00 00 00 00 -40 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -F8 93 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 20 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 -FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 -45 02 B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 -B0 00 82 01 B2 40 1E 00 84 01 B2 D0 10 00 86 01 -B2 40 00 02 88 01 39 40 5C 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 1E D2 -5E 01 B0 12 F8 80 1E 82 38 40 C0 21 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 0E 12 -12 12 C4 21 84 12 2C 85 94 85 F0 83 34 80 E8 8D -50 86 34 80 02 8E FC 8D EA 8D 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 04 8E B2 41 C4 21 3E 41 84 12 0A 80 2B 00 -2C 85 94 85 F0 83 34 80 20 8E 50 86 34 80 12 88 -BA 83 2C 85 50 86 34 80 12 88 2C 8E 3E 5F E7 3F -3E 40 28 00 B0 12 CC 8D 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 02 20 -30 40 80 89 1C 15 12 12 C4 21 92 53 C4 21 84 12 -2C 85 50 86 34 80 74 8E 6A 8E 21 53 3E 90 10 00 -C6 2B 7F 2D 76 8E B2 41 C4 21 C1 3F 0D 12 84 12 -14 88 A8 8D 86 8E 0C 43 1B 42 C6 21 A2 53 C6 21 -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 B0 12 -CC 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 -18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 -10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 21 B0 12 CC 8D ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 21 B0 12 54 8E 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 54 8E 92 92 C0 21 -C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F B0 12 -54 8E FA 23 3C 50 10 00 B0 12 30 8E EF 3F 0C 43 -1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 88 A8 8D -52 8F FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 54 8E E0 23 3C 50 80 00 B0 12 -30 8E DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 80 00 13 5A 87 60 84 0A 80 2C 00 7C 8E 48 8F -92 8F 09 4B 2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 -85 12 88 8F 00 40 9C 8F 05 4D 4F 56 2E 42 85 12 -88 8F 40 40 00 00 03 41 44 44 85 12 88 8F 00 50 -B6 8F 05 41 44 44 2E 42 85 12 88 8F 40 50 C2 8F -04 41 44 44 43 00 85 12 88 8F 00 60 D0 8F 06 41 -44 44 43 2E 42 00 85 12 88 8F 40 60 76 8F 04 53 -55 42 43 00 85 12 88 8F 00 70 EE 8F 06 53 55 42 -43 2E 42 00 85 12 88 8F 40 70 FC 8F 03 53 55 42 -85 12 88 8F 00 80 0C 90 05 53 55 42 2E 42 85 12 -88 8F 40 80 28 8A 03 43 4D 50 85 12 88 8F 00 90 -26 90 05 43 4D 50 2E 42 85 12 88 8F 40 90 12 8A -04 44 41 44 44 00 85 12 88 8F 00 A0 40 90 06 44 -41 44 44 2E 42 00 85 12 88 8F 40 A0 32 90 03 42 -49 54 85 12 88 8F 00 B0 5E 90 05 42 49 54 2E 42 -85 12 88 8F 40 B0 6A 90 03 42 49 43 85 12 88 8F -00 C0 78 90 05 42 49 43 2E 42 85 12 88 8F 40 C0 -84 90 03 42 49 53 85 12 88 8F 00 D0 92 90 05 42 -49 53 2E 42 85 12 88 8F 40 D0 00 00 03 58 4F 52 -85 12 88 8F 00 E0 AC 90 05 58 4F 52 2E 42 85 12 -88 8F 40 E0 DE 8F 03 41 4E 44 85 12 88 8F 00 F0 -C6 90 05 41 4E 44 2E 42 85 12 88 8F 40 F0 14 88 -7C 8E E4 90 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 18 90 03 52 52 43 85 12 DE 90 00 10 -F6 90 05 52 52 43 2E 42 85 12 DE 90 40 10 02 91 -04 53 57 50 42 00 85 12 DE 90 80 10 10 91 03 52 -52 41 85 12 DE 90 00 11 1E 91 05 52 52 41 2E 42 -85 12 DE 90 40 11 2A 91 03 53 58 54 85 12 DE 90 -80 11 00 00 04 50 55 53 48 00 85 12 DE 90 00 12 -44 91 06 50 55 53 48 2E 42 00 85 12 DE 90 40 12 -9E 90 04 43 41 4C 4C 00 85 12 DE 90 80 12 1A 53 -0E 4A 0D 12 84 12 D6 84 14 80 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 81 38 91 03 53 3E 3D -86 12 00 38 8C 91 02 53 3C 00 86 12 00 34 52 91 -03 30 3E 3D 86 12 00 30 A0 91 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C B4 91 03 55 -3E 3D 86 12 00 28 AA 91 03 30 3C 3E 86 12 00 24 -C8 91 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D -BE 91 04 54 48 45 4E 00 1A 42 C6 21 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 4E 90 04 45 4C 53 45 00 1A 42 C6 21 -BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A 00 00 -E3 3F 62 91 05 42 45 47 49 4E 30 40 28 80 F2 91 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 21 30 4D D2 90 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 E0 91 BA 83 60 84 96 91 -06 52 45 50 45 41 54 00 0D 12 84 12 74 92 F8 91 -60 84 A4 92 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 -CB 2F 98 42 C6 21 00 00 30 4D 34 92 03 42 57 31 -85 12 A2 92 00 00 BC 92 03 42 57 32 85 12 A2 92 -00 00 C8 92 03 42 57 33 85 12 A2 92 00 00 E0 92 -3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B BA 4F -00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 DE 92 00 00 00 93 03 46 57 32 -85 12 DE 92 00 00 0C 93 03 46 57 33 85 12 DE 92 -00 00 18 93 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 92 88 EE 87 60 84 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 88 A8 8D -62 93 92 53 C4 21 3E 40 2C 00 84 12 2C 85 50 86 -34 80 12 88 3E 8F 78 93 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 90 92 04 52 52 43 4D 00 85 12 5C 93 -50 00 A6 93 04 52 52 41 4D 00 85 12 5C 93 50 01 -B4 93 04 52 4C 41 4D 00 85 12 5C 93 50 02 C2 93 -04 52 52 55 4D 00 85 12 5C 93 50 03 D2 91 05 50 -55 53 48 4D 85 12 5C 93 00 15 DE 93 04 50 4F 50 -4D 00 85 12 5C 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -94 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/LP_MSP430FR2476_8MHz_115200.txt b/binaries/LP_MSP430FR2476_8MHz_115200.txt new file mode 100644 index 0000000..e20da29 --- /dev/null +++ b/binaries/LP_MSP430FR2476_8MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 19 +BA 82 7E 81 84 81 54 81 2A 83 18 93 D0 8B 8A 8B +8A 8B A0 82 5E 83 26 83 3C 21 E0 20 7E 85 B6 80 +C4 80 9A 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +2A 83 18 93 D0 8B 8A 8B 8A 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F8 3C 0E 93 3E 4F +8D 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9E 82 B2 49 +5C 83 B2 49 24 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 44 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 2A 83 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 80 A4 84 AC 80 52 81 6C 83 1E 80 04 1B +5B 37 6D 00 8E 83 8E 83 1E 80 04 1B 5B 30 6D 00 +8E 83 DA 88 B0 12 7E 81 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 6C 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 8E 83 F2 85 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 8E 83 0A 80 40 FF 32 80 +BA 84 BE 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 +FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 +45 02 B2 40 00 A5 60 01 B2 D0 10 00 86 01 F2 C3 +82 01 F2 D0 06 00 82 01 B2 40 F4 00 84 01 39 40 +5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 20 29 83 89 43 00 20 FC 23 19 42 5E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 80 +86 81 00 00 0C 41 43 43 45 50 54 00 30 40 A0 82 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +FE 82 3C 40 0A 83 5D 15 A3 3E 21 52 3A 17 58 42 +0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 13 00 +0E 05 E2 D3 43 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D 00 83 +2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 26 83 30 12 3C 83 A2 B3 1C 05 FD 27 +B2 40 11 00 0E 05 E2 C3 43 02 30 41 2F 83 8F 4E +00 00 92 B3 1C 05 FD 27 B0 12 C6 82 1E 42 0C 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 5E 83 08 4E +3E 4F C7 3F 54 83 08 45 43 48 4F 00 B2 40 C2 48 +F8 82 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D F8 82 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 9E 83 29 4F 8F 4E 00 00 7E 49 DE 3F A0 83 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 79 22 +F9 98 00 00 76 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 6D 22 9B 24 1E 83 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 80 00 00 BE 84 B0 83 +02 86 BC 88 B0 80 2C 84 14 80 06 5B 54 48 45 4E +5D 00 B4 83 0A 84 D0 83 EE 83 14 80 06 5B 45 4C +53 45 5D 00 B4 83 1C 84 D0 83 EC 83 1E 80 04 5B +49 46 5D 00 B4 83 EE 83 B2 80 EC 83 1E 80 05 0D +6B 6F 20 0A 8E 83 9A 80 84 80 B2 80 EE 83 DC 83 +0D 5B 54 48 45 4E 5D 00 30 4D 40 84 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 4C 84 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 B0 83 02 86 6A 86 +0E 88 7E 85 5C 84 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 B0 83 02 86 6A 86 8E 84 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D 94 82 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 C0 21 +0D 12 84 12 0A 80 1E 80 6C 88 0A 80 22 00 02 86 +02 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 +3E 4F 3D 41 30 4D 76 83 05 2E 22 00 0D 12 84 12 +EC 84 0A 80 8E 83 6C 88 7E 85 00 00 04 3C 23 00 +B2 40 B2 21 B2 21 30 4D E8 84 02 23 1B 42 BE 21 +2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 +B2 21 C8 4A 00 00 30 4D 3A 85 04 23 53 00 0D 12 +84 12 3C 85 76 85 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 6A 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 +B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 84 85 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 66 83 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 30 85 B0 83 +9E 85 6E 85 9A 84 AC 85 88 85 8E 83 7E 85 18 85 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D F0 85 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 74 87 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 76 87 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 2C 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 +84 12 84 80 B0 83 02 86 B0 80 46 89 6A 86 30 88 +0A 4E 3E 4F 3D 40 4A 88 6D 27 3D 40 24 88 1A E2 +BC 21 14 24 0E 12 3E 4F 30 41 4C 88 3E 4F 3D 40 +24 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 22 8A 2A 3C 14 88 02 2C A2 53 C8 21 +1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 6A 88 0F 4C +49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 +C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D A6 85 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D CC 84 0A 41 4C 4C +4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 +84 12 1E 80 02 0D 0A 00 8E 83 94 80 1E 88 AC 84 +D6 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 81 32 80 0A 80 40 FF DE 84 1E 80 09 46 52 41 +4D 20 66 75 6C 6C 08 81 B2 80 E2 88 CC 88 0D 41 +42 4F 52 54 22 00 0D 12 84 12 EC 84 0A 80 08 81 +6C 88 7E 85 FC 85 02 27 0D 12 84 12 B0 83 02 86 +6A 86 B0 80 48 89 10 85 54 88 76 84 07 5B 27 5D +0D 12 84 12 38 89 0A 80 0A 80 6C 88 6C 88 7E 85 +4C 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 +BC 21 30 4D C4 84 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 B0 83 02 86 6A 86 B0 80 48 89 D6 84 +AC 80 A0 89 0A 80 0A 80 6C 88 6C 88 0A 80 6C 88 +6C 88 7E 85 00 00 02 3A 30 12 F6 89 92 B3 C8 21 +A2 63 C8 21 0D 12 84 12 B0 83 02 86 BE 89 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 +82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 +1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 81 62 89 03 3B 82 93 BC 21 F4 26 0D 12 +84 12 0A 80 7E 85 6C 88 08 8A 64 89 7E 85 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 +00 00 30 4D B6 88 0C 43 52 45 41 54 45 00 B0 12 +AC 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 88 83 +0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D A6 89 0E 3A 4E 4F 4E 41 +4D 45 30 12 F6 89 2F 83 8F 4E 00 00 1A 42 C8 21 +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 40 8A +05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 38 89 +C2 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 50 89 +0A 80 C4 8A 6C 88 7E 85 56 8A 08 43 4F 44 45 00 +B0 12 AC 89 A2 82 C8 21 61 3C 98 85 0E 48 44 4E +43 4F 44 45 B2 40 B0 8B CC 21 F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 08 8A 0E 8B 3D 41 +92 42 D0 21 CC 21 5D 3C DA 8A 0E 43 4F 44 45 4E +4E 4D 30 12 E4 8A B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 21 1A 42 C8 21 EF 3F EC 8A 0B 48 +49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF +82 43 BC 21 B9 3F 78 8B B2 40 8A 8B D0 21 82 4E +CE 21 30 40 10 85 85 12 76 8B 76 89 1E 89 08 8C +1A 8B 70 8A BA 85 64 86 36 89 5E 8B B0 8A 8A 8A +26 8A 7E 88 92 8C BC 86 00 00 00 00 85 12 76 8B +0C 93 90 91 F0 92 B8 90 14 91 62 91 3E 92 4A 92 +DA 8F FE 90 00 00 00 00 4C 8B CA 8E 00 00 66 92 +AA 8B B2 40 8A 8B CE 21 82 43 D0 21 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 +B0 12 DE 8B 30 4D F0 8B 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 21 B0 12 DE 8B 1A 42 +CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 F2 81 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF +3B 40 10 00 3A 40 3A 18 B0 12 E2 8B 82 43 4A 18 +C7 3F 84 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +6C 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 +84 12 B0 83 02 86 6A 86 AC 80 B0 8C A4 84 44 88 +B2 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 AC 89 BA 40 +85 12 FC FF BA 40 82 8C FE FF 28 83 8A 48 00 00 +BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 +B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 +84 12 02 86 6A 86 AC 80 1C 8D FC 8C 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 82 8C +00 00 01 20 3E 52 2E 83 21 53 30 41 14 87 AC 80 +24 8D 18 8D 26 8D B2 41 C6 21 30 41 92 83 C6 21 +3E 40 28 00 0A 4E 3D 15 B0 12 EC 8C 15 20 3E 40 +2B 00 B0 12 EC 8C 06 20 3E 40 2D 00 B0 12 EC 8C +92 83 C6 21 0E 12 1E 41 02 00 84 12 02 86 14 87 +AC 80 48 89 66 8D 3E 51 3A 17 30 41 B0 12 2C 8D +19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 +92 53 C6 21 1A 42 C6 21 3D 15 84 12 02 86 14 87 +AC 80 9E 8D 96 8D 3E 90 10 00 E6 2B 7C 2D A0 8D +A2 41 C6 21 E1 3F 03 20 B0 12 84 8D 43 3C 7A 90 +23 00 24 20 B0 12 34 8D 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 +A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 34 8D F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 80 8D 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 84 8D 92 92 C2 21 C6 21 02 24 +92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +6C 8D F2 3F 03 20 B0 12 84 8D F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 6C 8D +EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 +19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF +19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 6C 88 +7E 85 0A 80 2C 00 62 8E A6 8D B0 83 6C 8E 44 8E +B2 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 A2 8E 00 40 BE 8E 0A 4D 4F 56 2E 42 +85 12 A2 8E 40 40 00 00 06 41 44 44 85 12 A2 8E +00 50 D8 8E 0A 41 44 44 2E 42 85 12 A2 8E 40 50 +E4 8E 08 41 44 44 43 00 85 12 A2 8E 00 60 F2 8E +0C 41 44 44 43 2E 42 00 85 12 A2 8E 40 60 2A 8B +08 53 55 42 43 00 85 12 A2 8E 00 70 10 8F 0C 53 +55 42 43 2E 42 00 85 12 A2 8E 40 70 1E 8F 06 53 +55 42 85 12 A2 8E 00 80 2E 8F 0A 53 55 42 2E 42 +85 12 A2 8E 40 80 3A 8F 06 43 4D 50 85 12 A2 8E +00 90 48 8F 0A 43 4D 50 2E 42 85 12 A2 8E 40 90 +00 00 08 44 41 44 44 00 85 12 A2 8E 00 A0 62 8F +0C 44 41 44 44 2E 42 00 85 12 A2 8E 40 A0 90 8E +06 42 49 54 85 12 A2 8E 00 B0 80 8F 0A 42 49 54 +2E 42 85 12 A2 8E 40 B0 8C 8F 06 42 49 43 85 12 +A2 8E 00 C0 9A 8F 0A 42 49 43 2E 42 85 12 A2 8E +40 C0 A6 8F 06 42 49 53 85 12 A2 8E 00 D0 B4 8F +0A 42 49 53 2E 42 85 12 A2 8E 40 D0 00 00 06 58 +4F 52 85 12 A2 8E 00 E0 CE 8F 0A 58 4F 52 2E 42 +85 12 A2 8E 40 E0 00 8F 06 41 4E 44 85 12 A2 8E +00 F0 E8 8F 0A 41 4E 44 2E 42 85 12 A2 8E 40 F0 +B0 83 62 8E A6 8D 08 90 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F C0 8F 06 52 52 43 85 12 +00 90 00 10 1A 90 0A 52 52 43 2E 42 85 12 00 90 +40 10 54 8F 08 53 57 50 42 00 85 12 00 90 80 10 +26 90 06 52 52 41 85 12 00 90 00 11 42 90 0A 52 +52 41 2E 42 85 12 00 90 40 11 34 90 06 53 58 54 +85 12 00 90 80 11 00 00 08 50 55 53 48 00 85 12 +00 90 00 12 68 90 0C 50 55 53 48 2E 42 00 85 12 +00 90 40 12 5C 90 08 43 41 4C 4C 00 85 12 00 90 +80 12 1A 53 0E 4A 84 12 F2 85 1E 80 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 81 86 90 06 53 +3E 3D 86 12 00 38 AE 90 04 53 3C 00 86 12 00 34 +76 90 06 30 3E 3D 86 12 00 30 C2 90 04 30 3C 00 +86 12 00 30 FE 8A 04 55 3C 00 86 12 00 2C D6 90 +06 55 3E 3D 86 12 00 28 CC 90 06 30 3C 3E 86 12 +00 24 EA 90 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A +30 4D 70 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D E0 90 08 45 4C 53 45 00 1A 42 +C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A +00 00 E3 3F 4E 90 0A 42 45 47 49 4E 30 40 32 80 +38 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D F4 8F +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 02 91 98 84 7E 85 +56 91 0C 52 45 50 45 41 54 00 0D 12 84 12 96 91 +1A 91 7E 85 C6 91 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 21 CB 2F 98 42 C8 21 00 00 30 4D B2 91 06 42 +57 31 85 12 C4 91 00 00 DE 91 06 42 57 32 85 12 +C4 91 00 00 EA 91 06 42 57 33 85 12 C4 91 00 00 +02 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 +C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 00 92 00 00 +26 92 06 46 57 32 85 12 00 92 00 00 32 92 06 46 +57 33 85 12 00 92 00 00 A0 91 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 38 89 +44 88 7E 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 6C 8E 0A 80 2C 00 02 86 14 87 AC 80 48 89 +B0 83 62 8E 44 8E 98 92 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E F6 91 08 52 52 43 4D 00 85 12 82 92 +50 00 C6 92 08 52 52 41 4D 00 85 12 82 92 50 01 +D4 92 08 52 4C 41 4D 00 85 12 82 92 50 02 E2 92 +08 52 52 55 4D 00 85 12 82 92 50 03 F4 90 0A 50 +55 53 48 4D 85 12 82 92 00 15 FE 92 08 50 4F 50 +4D 00 85 12 82 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +BA 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/LP_MSP430FR2476_8MHz_I2C.txt b/binaries/LP_MSP430FR2476_8MHz_I2C.txt index 6d0fa68..9a3d114 100644 --- a/binaries/LP_MSP430FR2476_8MHz_I2C.txt +++ b/binaries/LP_MSP430FR2476_8MHz_I2C.txt @@ -1,335 +1,322 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF E2 93 F0 8B 34 01 -10 00 41 07 B6 81 AA 80 B8 81 8C 81 82 82 E2 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 03 +B4 82 56 81 56 81 58 81 44 81 F4 92 AC 8B 66 8B +66 8B A2 82 26 83 FE 82 3C 21 E0 20 5A 85 B6 80 +C4 80 76 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 F4 92 AC 8B 66 8B 66 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 80 05 18 42 02 18 08 11 38 D0 00 04 -82 48 94 05 F2 D0 0C 00 2A 02 92 C3 80 05 A2 D2 -AA 05 92 C3 30 01 30 41 48 43 A2 B3 AC 05 FD 27 -C2 48 8E 05 A2 B2 AC 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 AC 05 B2 B0 10 00 80 05 B8 22 -3A 17 92 B3 AC 05 FD 27 58 42 8C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 AC 05 FD 27 1E 42 8C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 AC 05 FD 27 C2 48 8E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F9 3C 0E 93 3E 4F +7B 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A0 82 B2 49 +24 83 B2 49 FC 82 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 20 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 80 84 AC 80 +42 81 3E 83 1E 80 05 1B 5B 37 6D 40 6A 83 0A 80 +02 18 A2 84 CE 85 6A 83 1E 80 04 1B 5B 30 6D 00 +6A 83 B6 88 48 43 A2 B3 AC 05 FD 27 C2 48 8E 05 +A2 B2 AC 05 FD 27 30 41 B2 D0 C0 07 80 05 18 42 +02 18 08 11 38 D0 00 04 82 48 94 05 F2 D0 0C 00 +2A 02 92 C3 80 05 A2 D2 AA 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 3E 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 6A 83 0A 80 02 18 A2 84 CE 85 0A 80 23 00 +22 83 CE 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +6A 83 0A 80 40 FF 32 80 96 84 9A 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 40 FF 7F 22 02 B2 D3 46 02 +B2 40 FC FF 42 02 B2 40 00 A5 60 01 B2 D0 10 00 +86 01 F2 C3 82 01 F2 D0 06 00 82 01 B2 40 F4 00 +84 01 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 39 40 00 20 29 83 89 43 00 20 FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 B0 12 +D0 80 80 81 00 00 0C 41 43 43 45 50 54 00 30 40 +A2 82 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 A6 3E 21 52 A2 C2 AC 05 B2 B0 10 00 80 05 +9F 22 3A 17 92 B3 AC 05 FD 27 58 42 8C 05 48 9B +0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 FE 82 58 43 +B0 12 46 81 2F 83 8F 4E 00 00 92 B3 AC 05 FD 27 +1E 42 8C 05 B0 12 44 81 30 4D 00 00 08 45 4D 49 +54 00 30 40 26 83 08 4E 3E 4F A2 B3 AC 05 FD 27 +C2 48 8E 05 30 4D 1C 83 08 45 43 48 4F 00 B2 40 +C2 48 30 83 38 40 05 00 B0 12 46 81 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 30 83 28 42 +F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 7A 83 +29 4F 8F 4E 00 00 7E 49 D4 3F 7C 83 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 8B 22 F9 98 00 00 +88 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 7F 22 9B 24 F6 82 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A 80 00 00 9A 84 8C 83 DE 85 98 88 +B0 80 08 84 14 80 06 5B 54 48 45 4E 5D 00 90 83 +E6 83 AC 83 CA 83 14 80 06 5B 45 4C 53 45 5D 00 +90 83 F8 83 AC 83 C8 83 1E 80 04 5B 49 46 5D 00 +90 83 CA 83 B2 80 C8 83 1E 80 05 0D 6B 6F 20 0A +6A 83 9A 80 84 80 B2 80 CA 83 B8 83 0D 5B 54 48 +45 4E 5D 00 30 4D 1C 84 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 28 84 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 8C 83 DE 85 46 86 EA 87 5A 85 +38 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 8C 83 DE 85 46 86 6A 84 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D 96 82 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 81 05 53 22 00 82 43 C0 21 0D 12 84 12 +0A 80 1E 80 48 88 0A 80 22 00 DE 85 DE 84 B2 40 +20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 +30 4D 50 83 05 2E 22 00 0D 12 84 12 C8 84 0A 80 +6A 83 48 88 5A 85 00 00 04 3C 23 00 B2 40 B2 21 +B2 21 30 4D C4 84 02 23 1B 42 BE 21 2C 4F 2F 83 +B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A +00 00 30 4D 16 85 04 23 53 00 0D 12 84 12 18 85 +52 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 46 85 +04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +60 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 38 83 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 0C 85 8C 83 7A 85 4A 85 +76 84 88 85 64 85 6A 83 5A 85 F4 84 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 +C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D CC 85 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 21 0C 4E 0E 43 1E 15 3D 40 50 87 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +52 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 08 85 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 80 +8C 83 DE 85 B0 80 22 89 46 86 0C 88 0A 4E 3E 4F +3D 40 26 88 6D 27 3D 40 00 88 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 28 88 3E 4F 3D 40 00 88 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +FE 89 2A 3C F0 87 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D 46 88 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -58 92 BE 92 00 92 0E 93 C6 91 00 00 92 8F 00 00 -D6 93 BA 93 2A 92 68 92 A2 90 00 00 00 00 2A 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C E2 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -DA FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 20 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 FF 7F -22 02 B2 D3 46 02 B2 40 FC FF 42 02 B2 40 00 A5 -60 01 B2 40 FF 1E 80 01 B2 40 B6 00 82 01 B2 40 -F4 00 84 01 B2 D0 10 00 86 01 B2 40 00 02 88 01 -39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 F8 80 -FE 81 38 40 C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 84 12 -1A 85 82 85 DE 83 34 80 D2 8D 3E 86 34 80 EC 8D -E6 8D D4 8D 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 EE 8D B2 41 -C4 21 3E 41 84 12 0A 80 2B 00 1A 85 82 85 DE 83 -34 80 0A 8E 3E 86 34 80 00 88 A8 83 1A 85 3E 86 -34 80 00 88 16 8E 3E 5F E7 3F 3E 40 28 00 B0 12 -B6 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 40 -29 00 92 92 C0 21 C4 21 02 20 30 40 6E 89 1C 15 -12 12 C4 21 92 53 C4 21 84 12 1A 85 3E 86 34 80 -5E 8E 54 8E 21 53 3E 90 10 00 C6 2B 7F 2D 60 8E -B2 41 C4 21 C1 3F 0D 12 84 12 02 88 92 8D 70 8E -0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 21 B0 12 B6 8D 3C 40 00 03 -0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 -2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 -3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 21 -B0 12 B6 8D ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 21 B0 12 3E 8E 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 3E 8E 92 92 C0 21 C4 21 02 24 92 53 -C4 21 8E 10 0C 5E DA 3F B0 12 3E 8E FA 23 3C 50 -10 00 B0 12 1A 8E EF 3F 0C 43 1B 42 C6 21 A2 53 -C6 21 0D 12 84 12 02 88 92 8D 3C 8F FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -3E 8E E0 23 3C 50 80 00 B0 12 1A 8E DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 48 87 -4E 84 0A 80 2C 00 66 8E 32 8F 7C 8F 09 4B 2E 4E -0E DC A2 3F 40 8A 03 4D 4F 56 85 12 72 8F 00 40 -86 8F 05 4D 4F 56 2E 42 85 12 72 8F 40 40 00 00 -03 41 44 44 85 12 72 8F 00 50 A0 8F 05 41 44 44 -2E 42 85 12 72 8F 40 50 AC 8F 04 41 44 44 43 00 -85 12 72 8F 00 60 BA 8F 06 41 44 44 43 2E 42 00 -85 12 72 8F 40 60 60 8F 04 53 55 42 43 00 85 12 -72 8F 00 70 D8 8F 06 53 55 42 43 2E 42 00 85 12 -72 8F 40 70 E6 8F 03 53 55 42 85 12 72 8F 00 80 -F6 8F 05 53 55 42 2E 42 85 12 72 8F 40 80 16 8A -03 43 4D 50 85 12 72 8F 00 90 10 90 05 43 4D 50 -2E 42 85 12 72 8F 40 90 00 8A 04 44 41 44 44 00 -85 12 72 8F 00 A0 2A 90 06 44 41 44 44 2E 42 00 -85 12 72 8F 40 A0 1C 90 03 42 49 54 85 12 72 8F -00 B0 48 90 05 42 49 54 2E 42 85 12 72 8F 40 B0 -54 90 03 42 49 43 85 12 72 8F 00 C0 62 90 05 42 -49 43 2E 42 85 12 72 8F 40 C0 6E 90 03 42 49 53 -85 12 72 8F 00 D0 7C 90 05 42 49 53 2E 42 85 12 -72 8F 40 D0 00 00 03 58 4F 52 85 12 72 8F 00 E0 -96 90 05 58 4F 52 2E 42 85 12 72 8F 40 E0 C8 8F -03 41 4E 44 85 12 72 8F 00 F0 B0 90 05 41 4E 44 -2E 42 85 12 72 8F 40 F0 02 88 66 8E CE 90 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 02 90 -03 52 52 43 85 12 C8 90 00 10 E0 90 05 52 52 43 -2E 42 85 12 C8 90 40 10 EC 90 04 53 57 50 42 00 -85 12 C8 90 80 10 FA 90 03 52 52 41 85 12 C8 90 -00 11 08 91 05 52 52 41 2E 42 85 12 C8 90 40 11 -14 91 03 53 58 54 85 12 C8 90 80 11 00 00 04 50 -55 53 48 00 85 12 C8 90 00 12 2E 91 06 50 55 53 -48 2E 42 00 85 12 C8 90 40 12 88 90 04 43 41 4C -4C 00 85 12 C8 90 80 12 1A 53 0E 4A 0D 12 84 12 -C4 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 81 22 91 03 53 3E 3D 86 12 00 38 76 91 -02 53 3C 00 86 12 00 34 3C 91 03 30 3E 3D 86 12 -00 30 8A 91 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C 9E 91 03 55 3E 3D 86 12 00 28 -94 91 03 30 3C 3E 86 12 00 24 B2 91 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 0E 4A 30 4D A8 91 04 54 48 45 -4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 38 90 -04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C 00 00 -A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 4C 91 05 42 -45 47 49 4E 30 40 28 80 DC 91 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 21 30 4D BC 90 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 CA 91 A8 83 4E 84 80 91 06 52 45 50 45 41 -54 00 0D 12 84 12 5E 92 E2 91 4E 84 8E 92 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 -00 00 30 4D 1E 92 03 42 57 31 85 12 8C 92 00 00 -A6 92 03 42 57 32 85 12 8C 92 00 00 B2 92 03 42 -57 33 85 12 8C 92 00 00 CA 92 3D 41 1A 42 C6 21 -28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 C6 21 -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -C8 92 00 00 EA 92 03 46 57 32 85 12 C8 92 00 00 -F6 92 03 46 57 33 85 12 C8 92 00 00 02 93 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 80 88 DC 87 4E 84 00 00 05 3F 47 4F 54 4F -3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 02 88 92 8D 4C 93 92 53 C4 21 -3E 40 2C 00 84 12 1A 85 3E 86 34 80 00 88 28 8F -62 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 7A 92 -04 52 52 43 4D 00 85 12 46 93 50 00 90 93 04 52 -52 41 4D 00 85 12 46 93 50 01 9E 93 04 52 4C 41 -4D 00 85 12 46 93 50 02 AC 93 04 52 52 55 4D 00 -85 12 46 93 50 03 BC 91 05 50 55 53 48 4D 85 12 -46 93 00 15 C8 93 04 50 4F 50 4D 00 85 12 46 93 -00 17 +82 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D A8 84 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E 80 +02 0D 0A 00 6A 83 94 80 FA 87 88 84 B2 84 1E 80 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 32 80 +0A 80 40 FF BA 84 1E 80 09 46 52 41 4D 20 66 75 +6C 6C 08 81 B2 80 BE 88 A8 88 0D 41 42 4F 52 54 +22 00 0D 12 84 12 C8 84 0A 80 08 81 48 88 5A 85 +D8 85 02 27 0D 12 84 12 8C 83 DE 85 46 86 B0 80 +24 89 EC 84 30 88 52 84 07 5B 27 5D 0D 12 84 12 +14 89 0A 80 0A 80 48 88 48 88 5A 85 28 89 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +A0 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +8C 83 DE 85 46 86 B0 80 24 89 B2 84 AC 80 7C 89 +0A 80 0A 80 48 88 48 88 0A 80 48 88 48 88 5A 85 +00 00 02 3A 30 12 D2 89 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 8C 83 DE 85 9A 89 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 81 +3E 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A 80 +5A 85 48 88 E4 89 40 89 5A 85 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +92 88 0C 43 52 45 41 54 45 00 B0 12 88 89 BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 64 83 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 82 89 0E 3A 4E 4F 4E 41 4D 45 30 12 +D2 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 1C 8A 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 14 89 9E 8A 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 2C 89 0A 80 A0 8A +48 88 5A 85 32 8A 08 43 4F 44 45 00 B0 12 88 89 +A2 82 C8 21 61 3C 74 85 0E 48 44 4E 43 4F 44 45 +B2 40 8C 8B CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 E4 89 EA 8A 3D 41 92 42 D0 21 +CC 21 5D 3C B6 8A 0E 43 4F 44 45 4E 4E 4D 30 12 +C0 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F C8 8A 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F 54 8B B2 40 66 8B D0 21 82 4E CE 21 30 40 +EC 84 85 12 52 8B 52 89 FA 88 E4 8B F6 8A 4C 8A +96 85 40 86 12 89 3A 8B 8C 8A 66 8A 02 8A 5A 88 +6E 8C 98 86 00 00 00 00 85 12 52 8B E8 92 6C 91 +CC 92 94 90 F0 90 3E 91 1A 92 26 92 B6 8F DA 90 +00 00 00 00 28 8B A6 8E 00 00 42 92 86 8B B2 40 +66 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 BA 8B +30 4D CC 8B 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 BA 8B 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 0E 82 FE FF 29 83 B9 40 FA 81 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 DA FF 3B 40 10 00 +3A 40 3A 18 B0 12 BE 8B 82 43 4A 18 C7 3F 60 8C +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 48 89 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 8C 83 +DE 85 46 86 AC 80 8C 8C 80 84 20 88 8E 8C 3E 4F +3D 41 B2 41 C6 21 B0 12 88 89 BA 40 85 12 FC FF +BA 40 5E 8C FE FF 28 83 8A 48 00 00 BA 40 82 80 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 DE 85 +46 86 AC 80 F8 8C D8 8C 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 5E 8C 00 00 01 20 +3E 52 2E 83 21 53 30 41 F0 86 AC 80 00 8D F4 8C +02 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 C8 8C 15 20 3E 40 2B 00 B0 12 +C8 8C 06 20 3E 40 2D 00 B0 12 C8 8C 92 83 C6 21 +0E 12 1E 41 02 00 84 12 DE 85 F0 86 AC 80 24 89 +42 8D 3E 51 3A 17 30 41 B0 12 08 8D 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 DE 85 F0 86 AC 80 7A 8D +72 8D 3E 90 10 00 E6 2B 7C 2D 7C 8D A2 41 C6 21 +E1 3F 03 20 B0 12 60 8D 43 3C 7A 90 23 00 24 20 +B0 12 10 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 10 8D F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 5C 8D 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 60 8D 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 48 8D F2 3F +03 20 B0 12 60 8D F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 48 8D EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A 80 00 13 48 88 5A 85 0A 80 +2C 00 3E 8E 82 8D 8C 83 48 8E 20 8E 8E 8E 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +7E 8E 00 40 9A 8E 0A 4D 4F 56 2E 42 85 12 7E 8E +40 40 00 00 06 41 44 44 85 12 7E 8E 00 50 B4 8E +0A 41 44 44 2E 42 85 12 7E 8E 40 50 C0 8E 08 41 +44 44 43 00 85 12 7E 8E 00 60 CE 8E 0C 41 44 44 +43 2E 42 00 85 12 7E 8E 40 60 06 8B 08 53 55 42 +43 00 85 12 7E 8E 00 70 EC 8E 0C 53 55 42 43 2E +42 00 85 12 7E 8E 40 70 FA 8E 06 53 55 42 85 12 +7E 8E 00 80 0A 8F 0A 53 55 42 2E 42 85 12 7E 8E +40 80 16 8F 06 43 4D 50 85 12 7E 8E 00 90 24 8F +0A 43 4D 50 2E 42 85 12 7E 8E 40 90 00 00 08 44 +41 44 44 00 85 12 7E 8E 00 A0 3E 8F 0C 44 41 44 +44 2E 42 00 85 12 7E 8E 40 A0 6C 8E 06 42 49 54 +85 12 7E 8E 00 B0 5C 8F 0A 42 49 54 2E 42 85 12 +7E 8E 40 B0 68 8F 06 42 49 43 85 12 7E 8E 00 C0 +76 8F 0A 42 49 43 2E 42 85 12 7E 8E 40 C0 82 8F +06 42 49 53 85 12 7E 8E 00 D0 90 8F 0A 42 49 53 +2E 42 85 12 7E 8E 40 D0 00 00 06 58 4F 52 85 12 +7E 8E 00 E0 AA 8F 0A 58 4F 52 2E 42 85 12 7E 8E +40 E0 DC 8E 06 41 4E 44 85 12 7E 8E 00 F0 C4 8F +0A 41 4E 44 2E 42 85 12 7E 8E 40 F0 8C 83 3E 8E +82 8D E4 8F 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F 9C 8F 06 52 52 43 85 12 DC 8F 00 10 +F6 8F 0A 52 52 43 2E 42 85 12 DC 8F 40 10 30 8F +08 53 57 50 42 00 85 12 DC 8F 80 10 02 90 06 52 +52 41 85 12 DC 8F 00 11 1E 90 0A 52 52 41 2E 42 +85 12 DC 8F 40 11 10 90 06 53 58 54 85 12 DC 8F +80 11 00 00 08 50 55 53 48 00 85 12 DC 8F 00 12 +44 90 0C 50 55 53 48 2E 42 00 85 12 DC 8F 40 12 +38 90 08 43 41 4C 4C 00 85 12 DC 8F 80 12 1A 53 +0E 4A 84 12 CE 85 1E 80 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 81 62 90 06 53 3E 3D 86 12 +00 38 8A 90 04 53 3C 00 86 12 00 34 52 90 06 30 +3E 3D 86 12 00 30 9E 90 04 30 3C 00 86 12 00 30 +DA 8A 04 55 3C 00 86 12 00 2C B2 90 06 55 3E 3D +86 12 00 28 A8 90 06 30 3C 3E 86 12 00 24 C6 90 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 4C 8F +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D BC 90 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +2A 90 0A 42 45 47 49 4E 30 40 32 80 14 91 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D D0 8F 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 DE 90 74 84 5A 85 32 91 0C 52 +45 50 45 41 54 00 0D 12 84 12 72 91 F6 90 5A 85 +A2 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D 8E 91 06 42 57 31 85 12 +A0 91 00 00 BA 91 06 42 57 32 85 12 A0 91 00 00 +C6 91 06 42 57 33 85 12 A0 91 00 00 DE 91 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 DC 91 00 00 02 92 06 46 +57 32 85 12 DC 91 00 00 0E 92 06 46 57 33 85 12 +DC 91 00 00 7C 91 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 14 89 20 88 5A 85 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 48 8E +0A 80 2C 00 DE 85 F0 86 AC 80 24 89 8C 83 3E 8E +20 8E 74 92 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +D2 91 08 52 52 43 4D 00 85 12 5E 92 50 00 A2 92 +08 52 52 41 4D 00 85 12 5E 92 50 01 B0 92 08 52 +4C 41 4D 00 85 12 5E 92 50 02 BE 92 08 52 52 55 +4D 00 85 12 5E 92 50 03 D0 90 0A 50 55 53 48 4D +85 12 5E 92 00 15 DA 92 08 50 4F 50 4D 00 85 12 +5E 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 82 82 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 B4 82 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/LP_MSP430FR2476_8MHz_UART.txt b/binaries/LP_MSP430FR2476_8MHz_UART.txt deleted file mode 100644 index a353f80..0000000 --- a/binaries/LP_MSP430FR2476_8MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF F8 93 02 8C 34 01 -10 00 41 33 94 81 AA 80 DA 81 9C 81 94 82 F8 93 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 E2 D3 43 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 E2 C3 43 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 82 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 6E 92 D4 92 16 92 24 93 DC 91 00 00 A8 8F -00 00 EC 93 D0 93 40 92 7E 92 B8 90 00 00 00 00 -40 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -F8 93 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 20 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 40 -FF 7F 22 02 B2 D3 46 02 B2 40 FC FF 42 02 E2 D3 -45 02 B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 -B6 00 82 01 B2 40 F4 00 84 01 B2 D0 10 00 86 01 -B2 40 00 02 88 01 39 40 5C 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 1E D2 -5E 01 B0 12 F8 80 1E 82 38 40 C0 21 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 0E 12 -12 12 C4 21 84 12 2C 85 94 85 F0 83 34 80 E8 8D -50 86 34 80 02 8E FC 8D EA 8D 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 04 8E B2 41 C4 21 3E 41 84 12 0A 80 2B 00 -2C 85 94 85 F0 83 34 80 20 8E 50 86 34 80 12 88 -BA 83 2C 85 50 86 34 80 12 88 2C 8E 3E 5F E7 3F -3E 40 28 00 B0 12 CC 8D 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 02 20 -30 40 80 89 1C 15 12 12 C4 21 92 53 C4 21 84 12 -2C 85 50 86 34 80 74 8E 6A 8E 21 53 3E 90 10 00 -C6 2B 7F 2D 76 8E B2 41 C4 21 C1 3F 0D 12 84 12 -14 88 A8 8D 86 8E 0C 43 1B 42 C6 21 A2 53 C6 21 -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 B0 12 -CC 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 -18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 -10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 21 B0 12 CC 8D ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 21 B0 12 54 8E 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 54 8E 92 92 C0 21 -C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F B0 12 -54 8E FA 23 3C 50 10 00 B0 12 30 8E EF 3F 0C 43 -1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 88 A8 8D -52 8F FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 54 8E E0 23 3C 50 80 00 B0 12 -30 8E DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 80 00 13 5A 87 60 84 0A 80 2C 00 7C 8E 48 8F -92 8F 09 4B 2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 -85 12 88 8F 00 40 9C 8F 05 4D 4F 56 2E 42 85 12 -88 8F 40 40 00 00 03 41 44 44 85 12 88 8F 00 50 -B6 8F 05 41 44 44 2E 42 85 12 88 8F 40 50 C2 8F -04 41 44 44 43 00 85 12 88 8F 00 60 D0 8F 06 41 -44 44 43 2E 42 00 85 12 88 8F 40 60 76 8F 04 53 -55 42 43 00 85 12 88 8F 00 70 EE 8F 06 53 55 42 -43 2E 42 00 85 12 88 8F 40 70 FC 8F 03 53 55 42 -85 12 88 8F 00 80 0C 90 05 53 55 42 2E 42 85 12 -88 8F 40 80 28 8A 03 43 4D 50 85 12 88 8F 00 90 -26 90 05 43 4D 50 2E 42 85 12 88 8F 40 90 12 8A -04 44 41 44 44 00 85 12 88 8F 00 A0 40 90 06 44 -41 44 44 2E 42 00 85 12 88 8F 40 A0 32 90 03 42 -49 54 85 12 88 8F 00 B0 5E 90 05 42 49 54 2E 42 -85 12 88 8F 40 B0 6A 90 03 42 49 43 85 12 88 8F -00 C0 78 90 05 42 49 43 2E 42 85 12 88 8F 40 C0 -84 90 03 42 49 53 85 12 88 8F 00 D0 92 90 05 42 -49 53 2E 42 85 12 88 8F 40 D0 00 00 03 58 4F 52 -85 12 88 8F 00 E0 AC 90 05 58 4F 52 2E 42 85 12 -88 8F 40 E0 DE 8F 03 41 4E 44 85 12 88 8F 00 F0 -C6 90 05 41 4E 44 2E 42 85 12 88 8F 40 F0 14 88 -7C 8E E4 90 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 18 90 03 52 52 43 85 12 DE 90 00 10 -F6 90 05 52 52 43 2E 42 85 12 DE 90 40 10 02 91 -04 53 57 50 42 00 85 12 DE 90 80 10 10 91 03 52 -52 41 85 12 DE 90 00 11 1E 91 05 52 52 41 2E 42 -85 12 DE 90 40 11 2A 91 03 53 58 54 85 12 DE 90 -80 11 00 00 04 50 55 53 48 00 85 12 DE 90 00 12 -44 91 06 50 55 53 48 2E 42 00 85 12 DE 90 40 12 -9E 90 04 43 41 4C 4C 00 85 12 DE 90 80 12 1A 53 -0E 4A 0D 12 84 12 D6 84 14 80 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 81 38 91 03 53 3E 3D -86 12 00 38 8C 91 02 53 3C 00 86 12 00 34 52 91 -03 30 3E 3D 86 12 00 30 A0 91 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C B4 91 03 55 -3E 3D 86 12 00 28 AA 91 03 30 3C 3E 86 12 00 24 -C8 91 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D -BE 91 04 54 48 45 4E 00 1A 42 C6 21 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 4E 90 04 45 4C 53 45 00 1A 42 C6 21 -BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A 00 00 -E3 3F 62 91 05 42 45 47 49 4E 30 40 28 80 F2 91 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 21 30 4D D2 90 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 E0 91 BA 83 60 84 96 91 -06 52 45 50 45 41 54 00 0D 12 84 12 74 92 F8 91 -60 84 A4 92 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 -CB 2F 98 42 C6 21 00 00 30 4D 34 92 03 42 57 31 -85 12 A2 92 00 00 BC 92 03 42 57 32 85 12 A2 92 -00 00 C8 92 03 42 57 33 85 12 A2 92 00 00 E0 92 -3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B BA 4F -00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 DE 92 00 00 00 93 03 46 57 32 -85 12 DE 92 00 00 0C 93 03 46 57 33 85 12 DE 92 -00 00 18 93 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 92 88 EE 87 60 84 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 88 A8 8D -62 93 92 53 C4 21 3E 40 2C 00 84 12 2C 85 50 86 -34 80 12 88 3E 8F 78 93 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 90 92 04 52 52 43 4D 00 85 12 5C 93 -50 00 A6 93 04 52 52 41 4D 00 85 12 5C 93 50 01 -B4 93 04 52 4C 41 4D 00 85 12 5C 93 50 02 C2 93 -04 52 52 55 4D 00 85 12 5C 93 50 03 D2 91 05 50 -55 53 48 4D 85 12 5C 93 00 15 DE 93 04 50 4F 50 -4D 00 85 12 5C 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -94 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/Log/log.txt b/binaries/Log/log.txt deleted file mode 100644 index 9faef68..0000000 --- a/binaries/Log/log.txt +++ /dev/null @@ -1,75 +0,0 @@ -Fri Nov 6 19:33:33 2020: * -----/|-------------------------------------------------------------------- * -Fri Nov 6 19:33:33 2020: * / |__ * -Fri Nov 6 19:33:33 2020: * /_ / MSP Flasher v1.3.20 * -Fri Nov 6 19:33:33 2020: * | / * -Fri Nov 6 19:33:33 2020: * -----|/-------------------------------------------------------------------- * -Fri Nov 6 19:33:33 2020: * -Fri Nov 6 19:33:33 2020: * Evaluating triggers...done -Fri Nov 6 19:33:34 2020: * Checking for available FET debuggers: -Fri Nov 6 19:33:34 2020: * Found USB FET @ COM11 <- Selected -Fri Nov 6 19:33:34 2020: * Initializing interface @ COM11...done -Fri Nov 6 19:33:35 2020: * Checking firmware compatibility: -Fri Nov 6 19:33:35 2020: * FET firmware is up to date. -Fri Nov 6 19:33:35 2020: * Reading FW version... -Fri Nov 6 19:33:35 2020: * Debugger does not support target voltages other than 3000 mV! -Fri Nov 6 19:33:35 2020: * Setting VCC to 3000 mV...done -Fri Nov 6 19:33:35 2020: * Accessing device...done -Fri Nov 6 19:33:35 2020: * Reading device information... -Fri Nov 6 19:33:35 2020: * Warning: Found device does not match -n selection: -Fri Nov 6 19:33:35 2020: - Selected: MSP430FR6989 -Fri Nov 6 19:33:35 2020: - Found: MSP430FR5994 -Fri Nov 6 19:33:35 2020: - Continue? (Y/N): Fri Nov 6 19:33:41 2020: n -Fri Nov 6 19:33:41 2020: * Resetting device (RST/NMI)...done -Fri Nov 6 19:33:42 2020: * Starting target code execution...done -Fri Nov 6 19:33:43 2020: * Disconnecting from device...done -Fri Nov 6 19:33:43 2020: * -Fri Nov 6 19:33:43 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:43 2020: * Driver : closed (No error) -Fri Nov 6 19:33:43 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:43 2020: */ -Fri Nov 6 19:33:53 2020: * -----/|-------------------------------------------------------------------- * -Fri Nov 6 19:33:53 2020: * / |__ * -Fri Nov 6 19:33:53 2020: * /_ / MSP Flasher v1.3.20 * -Fri Nov 6 19:33:53 2020: * | / * -Fri Nov 6 19:33:53 2020: * -----|/-------------------------------------------------------------------- * -Fri Nov 6 19:33:53 2020: * -Fri Nov 6 19:33:53 2020: * Evaluating triggers...done -Fri Nov 6 19:33:53 2020: * Checking for available FET debuggers: -Fri Nov 6 19:33:53 2020: * Found USB FET @ COM11 <- Selected -Fri Nov 6 19:33:53 2020: * Initializing interface @ COM11...done -Fri Nov 6 19:33:54 2020: * Checking firmware compatibility: -Fri Nov 6 19:33:54 2020: * FET firmware is up to date. -Fri Nov 6 19:33:54 2020: * Reading FW version... -Fri Nov 6 19:33:54 2020: * Debugger does not support target voltages other than 3000 mV! -Fri Nov 6 19:33:54 2020: * Setting VCC to 3000 mV...done -Fri Nov 6 19:33:54 2020: * Accessing device...done -Fri Nov 6 19:33:54 2020: * Reading device information...done -Fri Nov 6 19:33:54 2020: * Loading file into device...done -Fri Nov 6 19:33:56 2020: * Verifying memory (B:\binaries\MSP_EXP430FR5994_16MHz_I2C.txt)...done -Fri Nov 6 19:33:58 2020: * -Fri Nov 6 19:33:58 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:58 2020: * Arguments : -s -m SBW2 -n MSP430FR5994 -v -w B:\binaries\MSP_EXP430FR5994_16MHz_I2C.txt -z [RESET,VCC] -Fri Nov 6 19:33:58 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:58 2020: * Driver : loaded -Fri Nov 6 19:33:58 2020: * Dll Version : 31400000 -Fri Nov 6 19:33:58 2020: * FwVersion : 31200000 -Fri Nov 6 19:33:58 2020: * Interface : TIUSB -Fri Nov 6 19:33:58 2020: * HwVersion : E 4.0 -Fri Nov 6 19:33:58 2020: * JTAG Mode : AUTO -Fri Nov 6 19:33:58 2020: * Device : MSP430FR5994 -Fri Nov 6 19:33:58 2020: * EEM : Level 5, ClockCntrl 2 -Fri Nov 6 19:33:58 2020: * Erase Mode : ERASE_ALL -Fri Nov 6 19:33:58 2020: * Prog.File : B:\binaries\MSP_EXP430FR5994_16MHz_I2C.txt -Fri Nov 6 19:33:58 2020: * Verified : TRUE -Fri Nov 6 19:33:58 2020: * BSL Unlock : FALSE -Fri Nov 6 19:33:58 2020: * InfoA Access: FALSE -Fri Nov 6 19:33:58 2020: * VCC ON : 3000 mV -Fri Nov 6 19:33:58 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:58 2020: * Resetting device (RST/NMI)...done -Fri Nov 6 19:33:59 2020: * Starting target code execution...done -Fri Nov 6 19:33:59 2020: * Disconnecting from device...done -Fri Nov 6 19:33:59 2020: * -Fri Nov 6 19:33:59 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:59 2020: * Driver : closed (No error) -Fri Nov 6 19:33:59 2020: * ---------------------------------------------------------------------------- -Fri Nov 6 19:33:59 2020: */ diff --git a/binaries/MSP_EXP430FR2355_16MHz_115200.txt b/binaries/MSP_EXP430FR2355_16MHz_115200.txt new file mode 100644 index 0000000..ecb3bd3 --- /dev/null +++ b/binaries/MSP_EXP430FR2355_16MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 59 +CC 82 7E 81 84 81 54 81 3C 83 2A 93 E2 8B 9C 8B +9C 8B B2 82 70 83 38 83 3C 21 E0 20 90 85 B6 80 +C4 80 AC 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3C 83 2A 93 E2 8B 9C 8B 9C 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +96 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 82 B2 49 +6E 83 B2 49 36 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 56 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3C 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 B6 84 AC 80 52 81 7E 83 1E 80 04 1B +5B 37 6D 00 A0 83 A0 83 1E 80 04 1B 5B 30 6D 00 +A0 83 EC 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 7E 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 A0 83 04 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A0 83 0A 80 40 FF 32 80 +CC 84 D0 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 +39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 80 86 81 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 82 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 10 83 3C 40 1C 83 5D 15 9A 3E 21 52 3A 17 +58 42 8C 05 48 9B 09 20 A2 B3 9C 05 FD 27 B2 40 +13 00 8E 05 D2 D3 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 9C 05 FD 27 C2 48 8E 05 30 4D +12 83 2D 83 92 B3 9C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 9C 05 FD 27 58 42 8C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 38 83 30 12 4E 83 A2 B3 9C 05 +FD 27 B2 40 11 00 8E 05 D2 C3 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 9C 05 FD 27 B0 12 D8 82 1E 42 +8C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 70 83 +08 4E 3E 4F C7 3F 66 83 08 45 43 48 4F 00 B2 40 +C2 48 0A 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 0A 83 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 B0 83 29 4F 8F 4E 00 00 7E 49 DE 3F +B2 83 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +70 22 F9 98 00 00 6D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 64 22 9B 24 30 83 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 80 00 00 D0 84 +C2 83 14 86 CE 88 B0 80 3E 84 14 80 06 5B 54 48 +45 4E 5D 00 C6 83 1C 84 E2 83 00 84 14 80 06 5B +45 4C 53 45 5D 00 C6 83 2E 84 E2 83 FE 83 1E 80 +04 5B 49 46 5D 00 C6 83 00 84 B2 80 FE 83 1E 80 +05 0D 6B 6F 20 0A A0 83 9A 80 84 80 B2 80 00 84 +EE 83 0D 5B 54 48 45 4E 5D 00 30 4D 52 84 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 5E 84 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 C2 83 14 86 +7C 86 20 88 90 85 6E 84 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 C2 83 14 86 7C 86 A0 84 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D A6 82 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A 80 1E 80 7E 88 0A 80 22 00 +14 86 14 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 88 83 05 2E 22 00 0D 12 +84 12 FE 84 0A 80 A0 83 7E 88 90 85 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D FA 84 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 4C 85 04 23 53 00 +0D 12 84 12 4E 85 88 85 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 7C 85 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 96 85 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 78 83 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 42 85 +C2 83 B0 85 80 85 AC 84 BE 85 9A 85 A0 83 90 85 +2A 85 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 02 86 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +86 87 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 88 87 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 3E 85 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 80 C2 83 14 86 B0 80 58 89 7C 86 +42 88 0A 4E 3E 4F 3D 40 5C 88 6D 27 3D 40 36 88 +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 5E 88 3E 4F +3D 40 36 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 34 8A 2A 3C 26 88 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7C 88 +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D B8 85 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D DE 84 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E 80 02 0D 0A 00 A0 83 94 80 30 88 +BE 84 E8 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 81 32 80 0A 80 40 FF F0 84 1E 80 09 46 +52 41 4D 20 66 75 6C 6C 08 81 B2 80 F4 88 DE 88 +0D 41 42 4F 52 54 22 00 0D 12 84 12 FE 84 0A 80 +08 81 7E 88 90 85 0E 86 02 27 0D 12 84 12 C2 83 +14 86 7C 86 B0 80 5A 89 22 85 66 88 88 84 07 5B +27 5D 0D 12 84 12 4A 89 0A 80 0A 80 7E 88 7E 88 +90 85 5E 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D D6 84 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C2 83 14 86 7C 86 B0 80 5A 89 +E8 84 AC 80 B2 89 0A 80 0A 80 7E 88 7E 88 0A 80 +7E 88 7E 88 90 85 00 00 02 3A 30 12 08 8A 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C2 83 14 86 D0 89 +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 81 74 89 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A 80 90 85 7E 88 1A 8A 76 89 90 85 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D C8 88 0C 43 52 45 41 54 45 00 +B0 12 BE 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +9A 83 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D B8 89 0E 3A 4E 4F +4E 41 4D 45 30 12 08 8A 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +52 8A 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +4A 89 D4 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +62 89 0A 80 D6 8A 7E 88 90 85 68 8A 08 43 4F 44 +45 00 B0 12 BE 89 A2 82 C8 21 61 3C AA 85 0E 48 +44 4E 43 4F 44 45 B2 40 C2 8B CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 1A 8A 20 8B +3D 41 92 42 D0 21 CC 21 5D 3C EC 8A 0E 43 4F 44 +45 4E 4E 4D 30 12 F6 8A B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FE 8A +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 8A 8B B2 40 9C 8B D0 21 +82 4E CE 21 30 40 22 85 85 12 88 8B 88 89 30 89 +1A 8C 2C 8B 82 8A CC 85 76 86 48 89 70 8B C2 8A +9C 8A 38 8A 90 88 A4 8C CE 86 00 00 00 00 85 12 +88 8B 1E 93 A2 91 02 93 CA 90 26 91 74 91 50 92 +5C 92 EC 8F 10 91 00 00 00 00 5E 8B DC 8E 00 00 +78 92 BC 8B B2 40 9C 8B CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 F0 8B 30 4D 02 8C 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 F0 8B +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 +F2 81 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E2 FF 3B 40 10 00 3A 40 3A 18 B0 12 F4 8B 82 43 +4A 18 C7 3F 96 8C B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 7E 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C2 83 14 86 7C 86 AC 80 C2 8C B6 84 +56 88 C4 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BE 89 +BA 40 85 12 FC FF BA 40 94 8C FE FF 28 83 8A 48 +00 00 BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 14 86 7C 86 AC 80 2E 8D 0E 8D 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +94 8C 00 00 01 20 3E 52 2E 83 21 53 30 41 26 87 +AC 80 36 8D 2A 8D 38 8D B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 FE 8C 15 20 +3E 40 2B 00 B0 12 FE 8C 06 20 3E 40 2D 00 B0 12 +FE 8C 92 83 C6 21 0E 12 1E 41 02 00 84 12 14 86 +26 87 AC 80 5A 89 78 8D 3E 51 3A 17 30 41 B0 12 +3E 8D 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 14 86 +26 87 AC 80 B0 8D A8 8D 3E 90 10 00 E6 2B 7C 2D +B2 8D A2 41 C6 21 E1 3F 03 20 B0 12 96 8D 43 3C +7A 90 23 00 24 20 B0 12 46 8D 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 46 8D F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 92 8D 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 96 8D 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 7E 8D F2 3F 03 20 B0 12 96 8D F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +7E 8D EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 +7E 88 90 85 0A 80 2C 00 74 8E B8 8D C2 83 7E 8E +56 8E C4 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 B4 8E 00 40 D0 8E 0A 4D 4F 56 +2E 42 85 12 B4 8E 40 40 00 00 06 41 44 44 85 12 +B4 8E 00 50 EA 8E 0A 41 44 44 2E 42 85 12 B4 8E +40 50 F6 8E 08 41 44 44 43 00 85 12 B4 8E 00 60 +04 8F 0C 41 44 44 43 2E 42 00 85 12 B4 8E 40 60 +3C 8B 08 53 55 42 43 00 85 12 B4 8E 00 70 22 8F +0C 53 55 42 43 2E 42 00 85 12 B4 8E 40 70 30 8F +06 53 55 42 85 12 B4 8E 00 80 40 8F 0A 53 55 42 +2E 42 85 12 B4 8E 40 80 4C 8F 06 43 4D 50 85 12 +B4 8E 00 90 5A 8F 0A 43 4D 50 2E 42 85 12 B4 8E +40 90 00 00 08 44 41 44 44 00 85 12 B4 8E 00 A0 +74 8F 0C 44 41 44 44 2E 42 00 85 12 B4 8E 40 A0 +A2 8E 06 42 49 54 85 12 B4 8E 00 B0 92 8F 0A 42 +49 54 2E 42 85 12 B4 8E 40 B0 9E 8F 06 42 49 43 +85 12 B4 8E 00 C0 AC 8F 0A 42 49 43 2E 42 85 12 +B4 8E 40 C0 B8 8F 06 42 49 53 85 12 B4 8E 00 D0 +C6 8F 0A 42 49 53 2E 42 85 12 B4 8E 40 D0 00 00 +06 58 4F 52 85 12 B4 8E 00 E0 E0 8F 0A 58 4F 52 +2E 42 85 12 B4 8E 40 E0 12 8F 06 41 4E 44 85 12 +B4 8E 00 F0 FA 8F 0A 41 4E 44 2E 42 85 12 B4 8E +40 F0 C2 83 74 8E B8 8D 1A 90 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F D2 8F 06 52 52 43 +85 12 12 90 00 10 2C 90 0A 52 52 43 2E 42 85 12 +12 90 40 10 66 8F 08 53 57 50 42 00 85 12 12 90 +80 10 38 90 06 52 52 41 85 12 12 90 00 11 54 90 +0A 52 52 41 2E 42 85 12 12 90 40 11 46 90 06 53 +58 54 85 12 12 90 80 11 00 00 08 50 55 53 48 00 +85 12 12 90 00 12 7A 90 0C 50 55 53 48 2E 42 00 +85 12 12 90 40 12 6E 90 08 43 41 4C 4C 00 85 12 +12 90 80 12 1A 53 0E 4A 84 12 04 86 1E 80 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 81 98 90 +06 53 3E 3D 86 12 00 38 C0 90 04 53 3C 00 86 12 +00 34 88 90 06 30 3E 3D 86 12 00 30 D4 90 04 30 +3C 00 86 12 00 30 10 8B 04 55 3C 00 86 12 00 2C +E8 90 06 55 3E 3D 86 12 00 28 DE 90 06 30 3C 3E +86 12 00 24 FC 90 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 82 8F 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D F2 90 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 60 90 0A 42 45 47 49 4E 30 40 +32 80 4A 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +06 90 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 14 91 AA 84 +90 85 68 91 0C 52 45 50 45 41 54 00 0D 12 84 12 +A8 91 2C 91 90 85 D8 91 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D C4 91 +06 42 57 31 85 12 D6 91 00 00 F0 91 06 42 57 32 +85 12 D6 91 00 00 FC 91 06 42 57 33 85 12 D6 91 +00 00 14 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 12 92 +00 00 38 92 06 46 57 32 85 12 12 92 00 00 44 92 +06 46 57 33 85 12 12 92 00 00 B2 91 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +4A 89 56 88 90 85 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 7E 8E 0A 80 2C 00 14 86 26 87 AC 80 +5A 89 C2 83 74 8E 56 8E AA 92 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 08 92 08 52 52 43 4D 00 85 12 +94 92 50 00 D8 92 08 52 52 41 4D 00 85 12 94 92 +50 01 E6 92 08 52 4C 41 4D 00 85 12 94 92 50 02 +F4 92 08 52 52 55 4D 00 85 12 94 92 50 03 06 91 +0A 50 55 53 48 4D 85 12 94 92 00 15 10 93 08 50 +4F 50 4D 00 85 12 94 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 CC 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_16MHz_4MBds.txt b/binaries/MSP_EXP430FR2355_16MHz_4MBds.txt new file mode 100644 index 0000000..dd65ce7 --- /dev/null +++ b/binaries/MSP_EXP430FR2355_16MHz_4MBds.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +CC 82 7E 81 84 81 54 81 3C 83 2A 93 E2 8B 9C 8B +9C 8B B2 82 70 83 38 83 3C 21 E0 20 90 85 B6 80 +C4 80 AC 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3C 83 2A 93 E2 8B 9C 8B 9C 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +96 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 82 B2 49 +6E 83 B2 49 36 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 56 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3C 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 B6 84 AC 80 52 81 7E 83 1E 80 04 1B +5B 37 6D 00 A0 83 A0 83 1E 80 04 1B 5B 30 6D 00 +A0 83 EC 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 7E 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 A0 83 04 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A0 83 0A 80 40 FF 32 80 +CC 84 D0 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 F2 D0 0A 00 82 01 B2 40 E8 01 84 01 +39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 80 86 81 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 82 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 10 83 3C 40 1C 83 5D 15 9A 3E 21 52 3A 17 +58 42 8C 05 48 9B 09 20 A2 B3 9C 05 FD 27 B2 40 +13 00 8E 05 D2 D3 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 9C 05 FD 27 C2 48 8E 05 30 4D +12 83 2D 83 92 B3 9C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 9C 05 FD 27 58 42 8C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 38 83 30 12 4E 83 A2 B3 9C 05 +FD 27 B2 40 11 00 8E 05 D2 C3 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 9C 05 FD 27 B0 12 D8 82 1E 42 +8C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 70 83 +08 4E 3E 4F C7 3F 66 83 08 45 43 48 4F 00 B2 40 +C2 48 0A 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 0A 83 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 B0 83 29 4F 8F 4E 00 00 7E 49 DE 3F +B2 83 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +70 22 F9 98 00 00 6D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 64 22 9B 24 30 83 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 80 00 00 D0 84 +C2 83 14 86 CE 88 B0 80 3E 84 14 80 06 5B 54 48 +45 4E 5D 00 C6 83 1C 84 E2 83 00 84 14 80 06 5B +45 4C 53 45 5D 00 C6 83 2E 84 E2 83 FE 83 1E 80 +04 5B 49 46 5D 00 C6 83 00 84 B2 80 FE 83 1E 80 +05 0D 6B 6F 20 0A A0 83 9A 80 84 80 B2 80 00 84 +EE 83 0D 5B 54 48 45 4E 5D 00 30 4D 52 84 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 5E 84 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 C2 83 14 86 +7C 86 20 88 90 85 6E 84 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 C2 83 14 86 7C 86 A0 84 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D A6 82 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A 80 1E 80 7E 88 0A 80 22 00 +14 86 14 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 88 83 05 2E 22 00 0D 12 +84 12 FE 84 0A 80 A0 83 7E 88 90 85 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D FA 84 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 4C 85 04 23 53 00 +0D 12 84 12 4E 85 88 85 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 7C 85 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 96 85 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 78 83 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 42 85 +C2 83 B0 85 80 85 AC 84 BE 85 9A 85 A0 83 90 85 +2A 85 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 02 86 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +86 87 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 88 87 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 3E 85 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 80 C2 83 14 86 B0 80 58 89 7C 86 +42 88 0A 4E 3E 4F 3D 40 5C 88 6D 27 3D 40 36 88 +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 5E 88 3E 4F +3D 40 36 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 34 8A 2A 3C 26 88 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7C 88 +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D B8 85 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D DE 84 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E 80 02 0D 0A 00 A0 83 94 80 30 88 +BE 84 E8 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 81 32 80 0A 80 40 FF F0 84 1E 80 09 46 +52 41 4D 20 66 75 6C 6C 08 81 B2 80 F4 88 DE 88 +0D 41 42 4F 52 54 22 00 0D 12 84 12 FE 84 0A 80 +08 81 7E 88 90 85 0E 86 02 27 0D 12 84 12 C2 83 +14 86 7C 86 B0 80 5A 89 22 85 66 88 88 84 07 5B +27 5D 0D 12 84 12 4A 89 0A 80 0A 80 7E 88 7E 88 +90 85 5E 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D D6 84 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C2 83 14 86 7C 86 B0 80 5A 89 +E8 84 AC 80 B2 89 0A 80 0A 80 7E 88 7E 88 0A 80 +7E 88 7E 88 90 85 00 00 02 3A 30 12 08 8A 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C2 83 14 86 D0 89 +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 81 74 89 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A 80 90 85 7E 88 1A 8A 76 89 90 85 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D C8 88 0C 43 52 45 41 54 45 00 +B0 12 BE 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +9A 83 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D B8 89 0E 3A 4E 4F +4E 41 4D 45 30 12 08 8A 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +52 8A 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +4A 89 D4 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +62 89 0A 80 D6 8A 7E 88 90 85 68 8A 08 43 4F 44 +45 00 B0 12 BE 89 A2 82 C8 21 61 3C AA 85 0E 48 +44 4E 43 4F 44 45 B2 40 C2 8B CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 1A 8A 20 8B +3D 41 92 42 D0 21 CC 21 5D 3C EC 8A 0E 43 4F 44 +45 4E 4E 4D 30 12 F6 8A B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FE 8A +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 8A 8B B2 40 9C 8B D0 21 +82 4E CE 21 30 40 22 85 85 12 88 8B 88 89 30 89 +1A 8C 2C 8B 82 8A CC 85 76 86 48 89 70 8B C2 8A +9C 8A 38 8A 90 88 A4 8C CE 86 00 00 00 00 85 12 +88 8B 1E 93 A2 91 02 93 CA 90 26 91 74 91 50 92 +5C 92 EC 8F 10 91 00 00 00 00 5E 8B DC 8E 00 00 +78 92 BC 8B B2 40 9C 8B CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 F0 8B 30 4D 02 8C 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 F0 8B +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 +F2 81 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E2 FF 3B 40 10 00 3A 40 3A 18 B0 12 F4 8B 82 43 +4A 18 C7 3F 96 8C B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 7E 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C2 83 14 86 7C 86 AC 80 C2 8C B6 84 +56 88 C4 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BE 89 +BA 40 85 12 FC FF BA 40 94 8C FE FF 28 83 8A 48 +00 00 BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 14 86 7C 86 AC 80 2E 8D 0E 8D 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +94 8C 00 00 01 20 3E 52 2E 83 21 53 30 41 26 87 +AC 80 36 8D 2A 8D 38 8D B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 FE 8C 15 20 +3E 40 2B 00 B0 12 FE 8C 06 20 3E 40 2D 00 B0 12 +FE 8C 92 83 C6 21 0E 12 1E 41 02 00 84 12 14 86 +26 87 AC 80 5A 89 78 8D 3E 51 3A 17 30 41 B0 12 +3E 8D 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 14 86 +26 87 AC 80 B0 8D A8 8D 3E 90 10 00 E6 2B 7C 2D +B2 8D A2 41 C6 21 E1 3F 03 20 B0 12 96 8D 43 3C +7A 90 23 00 24 20 B0 12 46 8D 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 46 8D F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 92 8D 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 96 8D 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 7E 8D F2 3F 03 20 B0 12 96 8D F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +7E 8D EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 +7E 88 90 85 0A 80 2C 00 74 8E B8 8D C2 83 7E 8E +56 8E C4 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 B4 8E 00 40 D0 8E 0A 4D 4F 56 +2E 42 85 12 B4 8E 40 40 00 00 06 41 44 44 85 12 +B4 8E 00 50 EA 8E 0A 41 44 44 2E 42 85 12 B4 8E +40 50 F6 8E 08 41 44 44 43 00 85 12 B4 8E 00 60 +04 8F 0C 41 44 44 43 2E 42 00 85 12 B4 8E 40 60 +3C 8B 08 53 55 42 43 00 85 12 B4 8E 00 70 22 8F +0C 53 55 42 43 2E 42 00 85 12 B4 8E 40 70 30 8F +06 53 55 42 85 12 B4 8E 00 80 40 8F 0A 53 55 42 +2E 42 85 12 B4 8E 40 80 4C 8F 06 43 4D 50 85 12 +B4 8E 00 90 5A 8F 0A 43 4D 50 2E 42 85 12 B4 8E +40 90 00 00 08 44 41 44 44 00 85 12 B4 8E 00 A0 +74 8F 0C 44 41 44 44 2E 42 00 85 12 B4 8E 40 A0 +A2 8E 06 42 49 54 85 12 B4 8E 00 B0 92 8F 0A 42 +49 54 2E 42 85 12 B4 8E 40 B0 9E 8F 06 42 49 43 +85 12 B4 8E 00 C0 AC 8F 0A 42 49 43 2E 42 85 12 +B4 8E 40 C0 B8 8F 06 42 49 53 85 12 B4 8E 00 D0 +C6 8F 0A 42 49 53 2E 42 85 12 B4 8E 40 D0 00 00 +06 58 4F 52 85 12 B4 8E 00 E0 E0 8F 0A 58 4F 52 +2E 42 85 12 B4 8E 40 E0 12 8F 06 41 4E 44 85 12 +B4 8E 00 F0 FA 8F 0A 41 4E 44 2E 42 85 12 B4 8E +40 F0 C2 83 74 8E B8 8D 1A 90 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F D2 8F 06 52 52 43 +85 12 12 90 00 10 2C 90 0A 52 52 43 2E 42 85 12 +12 90 40 10 66 8F 08 53 57 50 42 00 85 12 12 90 +80 10 38 90 06 52 52 41 85 12 12 90 00 11 54 90 +0A 52 52 41 2E 42 85 12 12 90 40 11 46 90 06 53 +58 54 85 12 12 90 80 11 00 00 08 50 55 53 48 00 +85 12 12 90 00 12 7A 90 0C 50 55 53 48 2E 42 00 +85 12 12 90 40 12 6E 90 08 43 41 4C 4C 00 85 12 +12 90 80 12 1A 53 0E 4A 84 12 04 86 1E 80 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 81 98 90 +06 53 3E 3D 86 12 00 38 C0 90 04 53 3C 00 86 12 +00 34 88 90 06 30 3E 3D 86 12 00 30 D4 90 04 30 +3C 00 86 12 00 30 10 8B 04 55 3C 00 86 12 00 2C +E8 90 06 55 3E 3D 86 12 00 28 DE 90 06 30 3C 3E +86 12 00 24 FC 90 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 82 8F 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D F2 90 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 60 90 0A 42 45 47 49 4E 30 40 +32 80 4A 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +06 90 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 14 91 AA 84 +90 85 68 91 0C 52 45 50 45 41 54 00 0D 12 84 12 +A8 91 2C 91 90 85 D8 91 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D C4 91 +06 42 57 31 85 12 D6 91 00 00 F0 91 06 42 57 32 +85 12 D6 91 00 00 FC 91 06 42 57 33 85 12 D6 91 +00 00 14 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 12 92 +00 00 38 92 06 46 57 32 85 12 12 92 00 00 44 92 +06 46 57 33 85 12 12 92 00 00 B2 91 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +4A 89 56 88 90 85 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 7E 8E 0A 80 2C 00 14 86 26 87 AC 80 +5A 89 C2 83 74 8E 56 8E AA 92 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 08 92 08 52 52 43 4D 00 85 12 +94 92 50 00 D8 92 08 52 52 41 4D 00 85 12 94 92 +50 01 E6 92 08 52 4C 41 4D 00 85 12 94 92 50 02 +F4 92 08 52 52 55 4D 00 85 12 94 92 50 03 06 91 +0A 50 55 53 48 4D 85 12 94 92 00 15 10 93 08 50 +4F 50 4D 00 85 12 94 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 CC 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_16MHz_I2C.txt b/binaries/MSP_EXP430FR2355_16MHz_I2C.txt index f2dc6f8..bee3c4b 100644 --- a/binaries/MSP_EXP430FR2355_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2355_16MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF EE 93 F0 8B 34 01 -10 00 41 87 B6 81 AA 80 B8 81 8C 81 82 82 EE 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +C6 82 56 81 56 81 58 81 44 81 06 93 BE 8B 78 8B +78 8B B4 82 38 83 10 83 3C 21 E0 20 6C 85 B6 80 +C4 80 88 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 06 93 BE 8B 78 8B 78 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 02 3D 0E 93 3E 4F +84 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B2 82 B2 49 +36 83 B2 49 0E 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 32 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 92 84 AC 80 +42 81 50 83 1E 80 05 1B 5B 37 6D 40 7C 83 0A 80 +02 18 B4 84 E0 85 7C 83 1E 80 04 1B 5B 30 6D 00 +7C 83 C8 88 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 50 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 7C 83 0A 80 02 18 B4 84 E0 85 0A 80 23 00 +34 83 E0 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7C 83 0A 80 40 FF 32 80 A8 84 AC 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 43 22 02 F2 D3 47 02 F2 40 +BF 00 43 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 +D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 F2 D0 +C0 00 0D 02 F2 C3 82 01 F2 D0 0A 00 82 01 B2 40 +E8 01 84 01 39 40 5C 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 +B0 12 D0 80 80 81 00 00 0C 41 43 43 45 50 54 00 +30 40 B4 82 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 9D 3E 21 52 A2 C2 6C 05 B2 B0 10 00 +40 05 96 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 10 83 +58 43 B0 12 46 81 2F 83 8F 4E 00 00 92 B3 6C 05 +FD 27 1E 42 4C 05 B0 12 44 81 30 4D 00 00 08 45 +4D 49 54 00 30 40 38 83 08 4E 3E 4F A2 B3 6C 05 +FD 27 C2 48 4E 05 30 4D 2E 83 08 45 43 48 4F 00 +B2 40 C2 48 42 83 38 40 05 00 B0 12 46 81 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 42 83 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +8C 83 29 4F 8F 4E 00 00 7E 49 D4 3F 8E 83 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 82 22 F9 98 +00 00 7F 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 76 22 9B 24 08 83 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 80 00 00 AC 84 9E 83 F0 85 +AA 88 B0 80 1A 84 14 80 06 5B 54 48 45 4E 5D 00 +A2 83 F8 83 BE 83 DC 83 14 80 06 5B 45 4C 53 45 +5D 00 A2 83 0A 84 BE 83 DA 83 1E 80 04 5B 49 46 +5D 00 A2 83 DC 83 B2 80 DA 83 1E 80 05 0D 6B 6F +20 0A 7C 83 9A 80 84 80 B2 80 DC 83 CA 83 0D 5B +54 48 45 4E 5D 00 30 4D 2E 84 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 3A 84 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 9E 83 F0 85 58 86 FC 87 +6C 85 4A 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 9E 83 F0 85 58 86 7C 84 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D A8 82 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 81 05 53 22 00 82 43 C0 21 0D 12 +84 12 0A 80 1E 80 5A 88 0A 80 22 00 F0 85 F0 84 +B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F +3D 41 30 4D 62 83 05 2E 22 00 0D 12 84 12 DA 84 +0A 80 7C 83 5A 88 6C 85 00 00 04 3C 23 00 B2 40 +B2 21 B2 21 30 4D D6 84 02 23 1B 42 BE 21 2C 4F +2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -64 92 CA 92 0C 92 1A 93 D2 91 00 00 9E 8F 00 00 -E2 93 C6 93 36 92 74 92 AE 90 00 00 00 00 36 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C EE 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 43 22 02 -F2 D3 47 02 F2 40 BF 00 43 02 F2 40 A5 00 A1 01 -F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 BA 00 82 01 B2 40 E8 01 -84 01 82 43 88 01 F2 D0 C0 00 0D 02 39 40 5C 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 80 FE 81 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A 85 82 85 -DE 83 34 80 DE 8D 3E 86 34 80 F8 8D F2 8D E0 8D -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 FA 8D B2 41 C4 21 3E 41 -84 12 0A 80 2B 00 1A 85 82 85 DE 83 34 80 16 8E -3E 86 34 80 00 88 A8 83 1A 85 3E 86 34 80 00 88 -22 8E 3E 5F E7 3F 3E 40 28 00 B0 12 C2 8D 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 6E 89 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A 85 3E 86 34 80 6A 8E 60 8E -21 53 3E 90 10 00 C6 2B 7F 2D 6C 8E B2 41 C4 21 -C1 3F 0D 12 84 12 02 88 9E 8D 7C 8E 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 C2 8D 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 C2 8D -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 4A 8E 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -4A 8E 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 4A 8E FA 23 3C 50 10 00 B0 12 -26 8E EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 02 88 9E 8D 48 8F FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 4A 8E E0 23 -3C 50 80 00 B0 12 26 8E DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 80 00 13 48 87 4E 84 0A 80 -2C 00 72 8E 3E 8F 88 8F 09 4B 2E 4E 0E DC A2 3F -40 8A 03 4D 4F 56 85 12 7E 8F 00 40 92 8F 05 4D -4F 56 2E 42 85 12 7E 8F 40 40 00 00 03 41 44 44 -85 12 7E 8F 00 50 AC 8F 05 41 44 44 2E 42 85 12 -7E 8F 40 50 B8 8F 04 41 44 44 43 00 85 12 7E 8F -00 60 C6 8F 06 41 44 44 43 2E 42 00 85 12 7E 8F -40 60 6C 8F 04 53 55 42 43 00 85 12 7E 8F 00 70 -E4 8F 06 53 55 42 43 2E 42 00 85 12 7E 8F 40 70 -F2 8F 03 53 55 42 85 12 7E 8F 00 80 02 90 05 53 -55 42 2E 42 85 12 7E 8F 40 80 16 8A 03 43 4D 50 -85 12 7E 8F 00 90 1C 90 05 43 4D 50 2E 42 85 12 -7E 8F 40 90 00 8A 04 44 41 44 44 00 85 12 7E 8F -00 A0 36 90 06 44 41 44 44 2E 42 00 85 12 7E 8F -40 A0 28 90 03 42 49 54 85 12 7E 8F 00 B0 54 90 -05 42 49 54 2E 42 85 12 7E 8F 40 B0 60 90 03 42 -49 43 85 12 7E 8F 00 C0 6E 90 05 42 49 43 2E 42 -85 12 7E 8F 40 C0 7A 90 03 42 49 53 85 12 7E 8F -00 D0 88 90 05 42 49 53 2E 42 85 12 7E 8F 40 D0 -00 00 03 58 4F 52 85 12 7E 8F 00 E0 A2 90 05 58 -4F 52 2E 42 85 12 7E 8F 40 E0 D4 8F 03 41 4E 44 -85 12 7E 8F 00 F0 BC 90 05 41 4E 44 2E 42 85 12 -7E 8F 40 F0 02 88 72 8E DA 90 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 0E 90 03 52 52 43 -85 12 D4 90 00 10 EC 90 05 52 52 43 2E 42 85 12 -D4 90 40 10 F8 90 04 53 57 50 42 00 85 12 D4 90 -80 10 06 91 03 52 52 41 85 12 D4 90 00 11 14 91 -05 52 52 41 2E 42 85 12 D4 90 40 11 20 91 03 53 -58 54 85 12 D4 90 80 11 00 00 04 50 55 53 48 00 -85 12 D4 90 00 12 3A 91 06 50 55 53 48 2E 42 00 -85 12 D4 90 40 12 94 90 04 43 41 4C 4C 00 85 12 -D4 90 80 12 1A 53 0E 4A 0D 12 84 12 C4 84 14 80 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 81 -2E 91 03 53 3E 3D 86 12 00 38 82 91 02 53 3C 00 -86 12 00 34 48 91 03 30 3E 3D 86 12 00 30 96 91 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C AA 91 03 55 3E 3D 86 12 00 28 A0 91 03 30 -3C 3E 86 12 00 24 BE 91 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D B4 91 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 44 90 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 58 91 05 42 45 47 49 4E -30 40 28 80 E8 91 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D C8 90 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 D6 91 -A8 83 4E 84 8C 91 06 52 45 50 45 41 54 00 0D 12 -84 12 6A 92 EE 91 4E 84 9A 92 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -2A 92 03 42 57 31 85 12 98 92 00 00 B2 92 03 42 -57 32 85 12 98 92 00 00 BE 92 03 42 57 33 85 12 -98 92 00 00 D6 92 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 D4 92 00 00 -F6 92 03 46 57 32 85 12 D4 92 00 00 02 93 03 46 -57 33 85 12 D4 92 00 00 0E 93 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 88 -DC 87 4E 84 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 02 88 9E 8D 58 93 92 53 C4 21 3E 40 2C 00 -84 12 1A 85 3E 86 34 80 00 88 34 8F 6E 93 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 86 92 04 52 52 43 -4D 00 85 12 52 93 50 00 9C 93 04 52 52 41 4D 00 -85 12 52 93 50 01 AA 93 04 52 4C 41 4D 00 85 12 -52 93 50 02 B8 93 04 52 52 55 4D 00 85 12 52 93 -50 03 C8 91 05 50 55 53 48 4D 85 12 52 93 00 15 -D4 93 04 50 4F 50 4D 00 85 12 52 93 00 17 +C8 4A 00 00 30 4D 28 85 04 23 53 00 0D 12 84 12 +2A 85 64 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +58 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 72 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 4A 83 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 1E 85 9E 83 8C 85 +5C 85 88 84 9A 85 76 85 7C 83 6C 85 06 85 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 +82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D DE 85 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 62 87 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 64 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +1A 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 80 9E 83 F0 85 B0 80 34 89 58 86 1E 88 0A 4E +3E 4F 3D 40 38 88 6D 27 3D 40 12 88 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 3A 88 3E 4F 3D 40 12 88 +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 10 8A 2A 3C 02 88 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 58 88 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 94 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D BA 84 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E 80 02 0D 0A 00 7C 83 94 80 0C 88 9A 84 C4 84 +1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 +32 80 0A 80 40 FF CC 84 1E 80 09 46 52 41 4D 20 +66 75 6C 6C 08 81 B2 80 D0 88 BA 88 0D 41 42 4F +52 54 22 00 0D 12 84 12 DA 84 0A 80 08 81 5A 88 +6C 85 EA 85 02 27 0D 12 84 12 9E 83 F0 85 58 86 +B0 80 36 89 FE 84 42 88 64 84 07 5B 27 5D 0D 12 +84 12 26 89 0A 80 0A 80 5A 88 5A 88 6C 85 3A 89 +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D B2 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 9E 83 F0 85 58 86 B0 80 36 89 C4 84 AC 80 +8E 89 0A 80 0A 80 5A 88 5A 88 0A 80 5A 88 5A 88 +6C 85 00 00 02 3A 30 12 E4 89 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 9E 83 F0 85 AC 89 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 81 50 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A 80 6C 85 5A 88 F6 89 52 89 6C 85 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D A4 88 0C 43 52 45 41 54 45 00 B0 12 9A 89 +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 76 83 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 94 89 0E 3A 4E 4F 4E 41 4D 45 +30 12 E4 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 2E 8A 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 26 89 B0 8A +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 3E 89 0A 80 +B2 8A 5A 88 6C 85 44 8A 08 43 4F 44 45 00 B0 12 +9A 89 A2 82 C8 21 61 3C 86 85 0E 48 44 4E 43 4F +44 45 B2 40 9E 8B CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 F6 89 FC 8A 3D 41 92 42 +D0 21 CC 21 5D 3C C8 8A 0E 43 4F 44 45 4E 4E 4D +30 12 D2 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F DA 8A 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F 66 8B B2 40 78 8B D0 21 82 4E CE 21 +30 40 FE 84 85 12 64 8B 64 89 0C 89 F6 8B 08 8B +5E 8A A8 85 52 86 24 89 4C 8B 9E 8A 78 8A 14 8A +6C 88 80 8C AA 86 00 00 00 00 85 12 64 8B FA 92 +7E 91 DE 92 A6 90 02 91 50 91 2C 92 38 92 C8 8F +EC 90 00 00 00 00 3A 8B B8 8E 00 00 54 92 98 8B +B2 40 78 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +CC 8B 30 4D DE 8B 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 CC 8B 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E 82 FE FF 29 83 B9 40 FA 81 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 D0 8B 82 43 4A 18 C7 3F +72 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 5A 89 +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +9E 83 F0 85 58 86 AC 80 9E 8C 92 84 32 88 A0 8C +3E 4F 3D 41 B2 41 C6 21 B0 12 9A 89 BA 40 85 12 +FC FF BA 40 70 8C FE FF 28 83 8A 48 00 00 BA 40 +82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +F0 85 58 86 AC 80 0A 8D EA 8C 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 70 8C 00 00 +01 20 3E 52 2E 83 21 53 30 41 02 87 AC 80 12 8D +06 8D 14 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 DA 8C 15 20 3E 40 2B 00 +B0 12 DA 8C 06 20 3E 40 2D 00 B0 12 DA 8C 92 83 +C6 21 0E 12 1E 41 02 00 84 12 F0 85 02 87 AC 80 +36 89 54 8D 3E 51 3A 17 30 41 B0 12 1A 8D 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 F0 85 02 87 AC 80 +8C 8D 84 8D 3E 90 10 00 E6 2B 7C 2D 8E 8D A2 41 +C6 21 E1 3F 03 20 B0 12 72 8D 43 3C 7A 90 23 00 +24 20 B0 12 22 8D 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 22 8D F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 6E 8D 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 72 8D 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 5A 8D +F2 3F 03 20 B0 12 72 8D F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 5A 8D EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 80 00 13 5A 88 6C 85 +0A 80 2C 00 50 8E 94 8D 9E 83 5A 8E 32 8E A0 8E +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 90 8E 00 40 AC 8E 0A 4D 4F 56 2E 42 85 12 +90 8E 40 40 00 00 06 41 44 44 85 12 90 8E 00 50 +C6 8E 0A 41 44 44 2E 42 85 12 90 8E 40 50 D2 8E +08 41 44 44 43 00 85 12 90 8E 00 60 E0 8E 0C 41 +44 44 43 2E 42 00 85 12 90 8E 40 60 18 8B 08 53 +55 42 43 00 85 12 90 8E 00 70 FE 8E 0C 53 55 42 +43 2E 42 00 85 12 90 8E 40 70 0C 8F 06 53 55 42 +85 12 90 8E 00 80 1C 8F 0A 53 55 42 2E 42 85 12 +90 8E 40 80 28 8F 06 43 4D 50 85 12 90 8E 00 90 +36 8F 0A 43 4D 50 2E 42 85 12 90 8E 40 90 00 00 +08 44 41 44 44 00 85 12 90 8E 00 A0 50 8F 0C 44 +41 44 44 2E 42 00 85 12 90 8E 40 A0 7E 8E 06 42 +49 54 85 12 90 8E 00 B0 6E 8F 0A 42 49 54 2E 42 +85 12 90 8E 40 B0 7A 8F 06 42 49 43 85 12 90 8E +00 C0 88 8F 0A 42 49 43 2E 42 85 12 90 8E 40 C0 +94 8F 06 42 49 53 85 12 90 8E 00 D0 A2 8F 0A 42 +49 53 2E 42 85 12 90 8E 40 D0 00 00 06 58 4F 52 +85 12 90 8E 00 E0 BC 8F 0A 58 4F 52 2E 42 85 12 +90 8E 40 E0 EE 8E 06 41 4E 44 85 12 90 8E 00 F0 +D6 8F 0A 41 4E 44 2E 42 85 12 90 8E 40 F0 9E 83 +50 8E 94 8D F6 8F 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F AE 8F 06 52 52 43 85 12 EE 8F +00 10 08 90 0A 52 52 43 2E 42 85 12 EE 8F 40 10 +42 8F 08 53 57 50 42 00 85 12 EE 8F 80 10 14 90 +06 52 52 41 85 12 EE 8F 00 11 30 90 0A 52 52 41 +2E 42 85 12 EE 8F 40 11 22 90 06 53 58 54 85 12 +EE 8F 80 11 00 00 08 50 55 53 48 00 85 12 EE 8F +00 12 56 90 0C 50 55 53 48 2E 42 00 85 12 EE 8F +40 12 4A 90 08 43 41 4C 4C 00 85 12 EE 8F 80 12 +1A 53 0E 4A 84 12 E0 85 1E 80 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 81 74 90 06 53 3E 3D +86 12 00 38 9C 90 04 53 3C 00 86 12 00 34 64 90 +06 30 3E 3D 86 12 00 30 B0 90 04 30 3C 00 86 12 +00 30 EC 8A 04 55 3C 00 86 12 00 2C C4 90 06 55 +3E 3D 86 12 00 28 BA 90 06 30 3C 3E 86 12 00 24 +D8 90 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +5E 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D CE 90 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 3C 90 0A 42 45 47 49 4E 30 40 32 80 26 91 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D E2 8F 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 F0 90 86 84 6C 85 44 91 +0C 52 45 50 45 41 54 00 0D 12 84 12 84 91 08 91 +6C 85 B4 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D A0 91 06 42 57 31 +85 12 B2 91 00 00 CC 91 06 42 57 32 85 12 B2 91 +00 00 D8 91 06 42 57 33 85 12 B2 91 00 00 F0 91 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 EE 91 00 00 14 92 +06 46 57 32 85 12 EE 91 00 00 20 92 06 46 57 33 +85 12 EE 91 00 00 8E 91 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 26 89 32 88 +6C 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +5A 8E 0A 80 2C 00 F0 85 02 87 AC 80 36 89 9E 83 +50 8E 32 8E 86 92 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E E4 91 08 52 52 43 4D 00 85 12 70 92 50 00 +B4 92 08 52 52 41 4D 00 85 12 70 92 50 01 C2 92 +08 52 4C 41 4D 00 85 12 70 92 50 02 D0 92 08 52 +52 55 4D 00 85 12 70 92 50 03 E2 90 0A 50 55 53 +48 4D 85 12 70 92 00 15 EC 92 08 50 4F 50 4D 00 +85 12 70 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -82 82 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +C6 82 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/MSP_EXP430FR2355_16MHz_UART.txt b/binaries/MSP_EXP430FR2355_16MHz_UART.txt deleted file mode 100644 index 08f3f28..0000000 --- a/binaries/MSP_EXP430FR2355_16MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 04 94 02 8C 34 01 -10 00 41 B3 94 81 AA 80 DA 81 9C 81 94 82 04 94 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 9C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -9C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 8A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 80 05 92 42 02 18 86 05 92 42 04 18 -88 05 F2 D0 0C 00 2B 02 92 C3 80 05 92 D3 9A 05 -92 C3 30 01 30 41 09 3C A2 B3 9C 05 FD 27 B2 40 -13 00 8E 05 D2 D3 03 02 30 41 A2 B3 9C 05 FD 27 -B2 40 11 00 8E 05 D2 C3 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 8C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 9C 05 FD 27 -C2 48 8E 05 30 4D C8 82 2D 83 92 B3 9C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 9C 05 -FD 27 58 42 8C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 9C 05 FD 27 1E 42 -8C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 7A 92 E0 92 22 92 30 93 E8 91 00 00 B4 8F -00 00 F8 93 DC 93 4C 92 8A 92 C4 90 00 00 00 00 -4C 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -04 94 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E2 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 -26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 -F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 BA 00 -82 01 B2 40 E8 01 84 01 82 43 88 01 F2 D0 C0 00 -0D 02 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 80 1E 82 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C 85 94 85 F0 83 34 80 F4 8D 50 86 34 80 -0E 8E 08 8E F6 8D 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 10 8E -B2 41 C4 21 3E 41 84 12 0A 80 2B 00 2C 85 94 85 -F0 83 34 80 2C 8E 50 86 34 80 12 88 BA 83 2C 85 -50 86 34 80 12 88 38 8E 3E 5F E7 3F 3E 40 28 00 -B0 12 D8 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 80 89 -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C 85 50 86 -34 80 80 8E 76 8E 21 53 3E 90 10 00 C6 2B 7F 2D -82 8E B2 41 C4 21 C1 3F 0D 12 84 12 14 88 B4 8D -92 8E 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 D8 8D 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 D8 8D ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 60 8E 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 60 8E 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 60 8E FA 23 -3C 50 10 00 B0 12 3C 8E EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 14 88 B4 8D 5E 8F FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 60 8E E0 23 3C 50 80 00 B0 12 3C 8E DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 -5A 87 60 84 0A 80 2C 00 88 8E 54 8F 9E 8F 09 4B -2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 85 12 94 8F -00 40 A8 8F 05 4D 4F 56 2E 42 85 12 94 8F 40 40 -00 00 03 41 44 44 85 12 94 8F 00 50 C2 8F 05 41 -44 44 2E 42 85 12 94 8F 40 50 CE 8F 04 41 44 44 -43 00 85 12 94 8F 00 60 DC 8F 06 41 44 44 43 2E -42 00 85 12 94 8F 40 60 82 8F 04 53 55 42 43 00 -85 12 94 8F 00 70 FA 8F 06 53 55 42 43 2E 42 00 -85 12 94 8F 40 70 08 90 03 53 55 42 85 12 94 8F -00 80 18 90 05 53 55 42 2E 42 85 12 94 8F 40 80 -28 8A 03 43 4D 50 85 12 94 8F 00 90 32 90 05 43 -4D 50 2E 42 85 12 94 8F 40 90 12 8A 04 44 41 44 -44 00 85 12 94 8F 00 A0 4C 90 06 44 41 44 44 2E -42 00 85 12 94 8F 40 A0 3E 90 03 42 49 54 85 12 -94 8F 00 B0 6A 90 05 42 49 54 2E 42 85 12 94 8F -40 B0 76 90 03 42 49 43 85 12 94 8F 00 C0 84 90 -05 42 49 43 2E 42 85 12 94 8F 40 C0 90 90 03 42 -49 53 85 12 94 8F 00 D0 9E 90 05 42 49 53 2E 42 -85 12 94 8F 40 D0 00 00 03 58 4F 52 85 12 94 8F -00 E0 B8 90 05 58 4F 52 2E 42 85 12 94 8F 40 E0 -EA 8F 03 41 4E 44 85 12 94 8F 00 F0 D2 90 05 41 -4E 44 2E 42 85 12 94 8F 40 F0 14 88 88 8E F0 90 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -24 90 03 52 52 43 85 12 EA 90 00 10 02 91 05 52 -52 43 2E 42 85 12 EA 90 40 10 0E 91 04 53 57 50 -42 00 85 12 EA 90 80 10 1C 91 03 52 52 41 85 12 -EA 90 00 11 2A 91 05 52 52 41 2E 42 85 12 EA 90 -40 11 36 91 03 53 58 54 85 12 EA 90 80 11 00 00 -04 50 55 53 48 00 85 12 EA 90 00 12 50 91 06 50 -55 53 48 2E 42 00 85 12 EA 90 40 12 AA 90 04 43 -41 4C 4C 00 85 12 EA 90 80 12 1A 53 0E 4A 0D 12 -84 12 D6 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 81 44 91 03 53 3E 3D 86 12 00 38 -98 91 02 53 3C 00 86 12 00 34 5E 91 03 30 3E 3D -86 12 00 30 AC 91 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C C0 91 03 55 3E 3D 86 12 -00 28 B6 91 03 30 3C 3E 86 12 00 24 D4 91 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D CA 91 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -5A 90 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 6E 91 -05 42 45 47 49 4E 30 40 28 80 FE 91 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D DE 90 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 EC 91 BA 83 60 84 A2 91 06 52 45 50 -45 41 54 00 0D 12 84 12 80 92 04 92 60 84 B0 92 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 40 92 03 42 57 31 85 12 AE 92 -00 00 C8 92 03 42 57 32 85 12 AE 92 00 00 D4 92 -03 42 57 33 85 12 AE 92 00 00 EC 92 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 EA 92 00 00 0C 93 03 46 57 32 85 12 EA 92 -00 00 18 93 03 46 57 33 85 12 EA 92 00 00 24 93 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 92 88 EE 87 60 84 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 14 88 B4 8D 6E 93 92 53 -C4 21 3E 40 2C 00 84 12 2C 85 50 86 34 80 12 88 -4A 8F 84 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -9C 92 04 52 52 43 4D 00 85 12 68 93 50 00 B2 93 -04 52 52 41 4D 00 85 12 68 93 50 01 C0 93 04 52 -4C 41 4D 00 85 12 68 93 50 02 CE 93 04 52 52 55 -4D 00 85 12 68 93 50 03 DE 91 05 50 55 53 48 4D -85 12 68 93 00 15 EA 93 04 50 4F 50 4D 00 85 12 -68 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 94 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/MSP_EXP430FR2355_1MHz_115200.txt b/binaries/MSP_EXP430FR2355_1MHz_115200.txt new file mode 100644 index 0000000..221d37c --- /dev/null +++ b/binaries/MSP_EXP430FR2355_1MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 59 +B6 82 7E 81 84 81 54 81 26 83 14 93 CC 8B 86 8B +86 8B 9C 82 5A 83 22 83 3C 21 E0 20 7A 85 B6 80 +C4 80 96 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +26 83 14 93 CC 8B 86 8B 86 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F6 3C 0E 93 3E 4F +8B 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9A 82 B2 49 +58 83 B2 49 20 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 40 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 26 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 A0 84 AC 80 52 81 68 83 1E 80 04 1B +5B 37 6D 00 8A 83 8A 83 1E 80 04 1B 5B 30 6D 00 +8A 83 D6 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 68 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 8A 83 EE 85 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 8A 83 0A 80 40 FF 32 80 +B6 84 BA 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 B2 40 1E 00 84 01 39 40 5C 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 39 40 00 10 29 83 +89 43 00 20 FC 23 19 42 5E 01 1E 42 08 18 82 43 +08 18 3E F3 01 20 0E 49 B0 12 D0 80 86 81 00 00 +0C 41 43 43 45 50 54 00 30 40 9C 82 08 4E 2E 4F +08 5E 39 40 0D 00 3A 40 20 00 3B 40 FA 82 3C 40 +06 83 5D 15 A5 3E 21 52 3A 17 58 42 8C 05 48 9B +09 20 A2 B3 9C 05 FD 27 B2 40 13 00 8E 05 D2 D3 +03 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 +1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 +9C 05 FD 27 C2 48 8E 05 30 4D FC 82 2D 83 92 B3 +9C 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 9C 05 FD 27 +58 42 8C 05 08 4C EB 3F 00 00 06 4B 45 59 30 40 +22 83 30 12 38 83 A2 B3 9C 05 FD 27 B2 40 11 00 +8E 05 D2 C3 03 02 30 41 2F 83 8F 4E 00 00 92 B3 +9C 05 FD 27 B0 12 C2 82 1E 42 8C 05 30 4D 00 00 +08 45 4D 49 54 00 30 40 5A 83 08 4E 3E 4F C7 3F +50 83 08 45 43 48 4F 00 B2 40 C2 48 F4 82 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D F4 82 +30 4D 00 00 08 54 59 50 45 00 0D 12 3D 40 9A 83 +29 4F 8F 4E 00 00 7E 49 DE 3F 9C 83 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 7B 22 F9 98 00 00 +78 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 6F 22 9B 24 1A 83 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A 80 00 00 BA 84 AC 83 FE 85 B8 88 +B0 80 28 84 14 80 06 5B 54 48 45 4E 5D 00 B0 83 +06 84 CC 83 EA 83 14 80 06 5B 45 4C 53 45 5D 00 +B0 83 18 84 CC 83 E8 83 1E 80 04 5B 49 46 5D 00 +B0 83 EA 83 B2 80 E8 83 1E 80 05 0D 6B 6F 20 0A +8A 83 9A 80 84 80 B2 80 EA 83 D8 83 0D 5B 54 48 +45 4E 5D 00 30 4D 3C 84 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 48 84 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 AC 83 FE 85 66 86 0A 88 7A 85 +58 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 AC 83 FE 85 66 86 8A 84 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 20 +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D 90 82 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D D8 81 05 53 22 00 82 43 C0 21 0D 12 84 12 +0A 80 1E 80 68 88 0A 80 22 00 FE 85 FE 84 B2 40 +20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 +30 4D 72 83 05 2E 22 00 0D 12 84 12 E8 84 0A 80 +8A 83 68 88 7A 85 00 00 04 3C 23 00 B2 40 B2 21 +B2 21 30 4D E4 84 02 23 1B 42 BE 21 2C 4F 2F 83 +B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 C8 4A +00 00 30 4D 36 85 04 23 53 00 0D 12 84 12 38 85 +72 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 66 85 +04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +80 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 62 83 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 2C 85 AC 83 9A 85 6A 85 +96 84 A8 85 84 85 8A 83 7A 85 14 85 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 +C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D EC 85 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 21 0C 4E 0E 43 1E 15 3D 40 70 87 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +72 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 28 85 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 80 +AC 83 FE 85 B0 80 42 89 66 86 2C 88 0A 4E 3E 4F +3D 40 46 88 6D 27 3D 40 20 88 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 48 88 3E 4F 3D 40 20 88 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +1E 8A 2A 3C 10 88 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D 66 88 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 +00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D +A2 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D C8 84 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E 80 +02 0D 0A 00 8A 83 94 80 1A 88 A8 84 D2 84 1E 80 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 32 80 +0A 80 40 FF DA 84 1E 80 09 46 52 41 4D 20 66 75 +6C 6C 08 81 B2 80 DE 88 C8 88 0D 41 42 4F 52 54 +22 00 0D 12 84 12 E8 84 0A 80 08 81 68 88 7A 85 +F8 85 02 27 0D 12 84 12 AC 83 FE 85 66 86 B0 80 +44 89 0C 85 50 88 72 84 07 5B 27 5D 0D 12 84 12 +34 89 0A 80 0A 80 68 88 68 88 7A 85 48 89 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +C0 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +AC 83 FE 85 66 86 B0 80 44 89 D2 84 AC 80 9C 89 +0A 80 0A 80 68 88 68 88 0A 80 68 88 68 88 7A 85 +00 00 02 3A 30 12 F2 89 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 AC 83 FE 85 BA 89 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 81 +5E 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A 80 +7A 85 68 88 04 8A 60 89 7A 85 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +B2 88 0C 43 52 45 41 54 45 00 B0 12 A8 89 BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 84 83 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D A2 89 0E 3A 4E 4F 4E 41 4D 45 30 12 +F2 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 3C 8A 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 34 89 BE 8A 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 4C 89 0A 80 C0 8A +68 88 7A 85 52 8A 08 43 4F 44 45 00 B0 12 A8 89 +A2 82 C8 21 61 3C 94 85 0E 48 44 4E 43 4F 44 45 +B2 40 AC 8B CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 04 8A 0A 8B 3D 41 92 42 D0 21 +CC 21 5D 3C D6 8A 0E 43 4F 44 45 4E 4E 4D 30 12 +E0 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F E8 8A 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F 74 8B B2 40 86 8B D0 21 82 4E CE 21 30 40 +0C 85 85 12 72 8B 72 89 1A 89 04 8C 16 8B 6C 8A +B6 85 60 86 32 89 5A 8B AC 8A 86 8A 22 8A 7A 88 +8E 8C B8 86 00 00 00 00 85 12 72 8B 08 93 8C 91 +EC 92 B4 90 10 91 5E 91 3A 92 46 92 D6 8F FA 90 +00 00 00 00 48 8B C6 8E 00 00 62 92 A6 8B B2 40 +86 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 DA 8B +30 4D EC 8B 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 DA 8B 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 06 82 FE FF 29 83 B9 40 F2 81 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 E2 FF 3B 40 10 00 +3A 40 3A 18 B0 12 DE 8B 82 43 4A 18 C7 3F 80 8C +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 68 89 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 AC 83 +FE 85 66 86 AC 80 AC 8C A0 84 40 88 AE 8C 3E 4F +3D 41 B2 41 C6 21 B0 12 A8 89 BA 40 85 12 FC FF +BA 40 7E 8C FE FF 28 83 8A 48 00 00 BA 40 82 80 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 FE 85 +66 86 AC 80 18 8D F8 8C 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 7E 8C 00 00 01 20 +3E 52 2E 83 21 53 30 41 10 87 AC 80 20 8D 14 8D +22 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 E8 8C 15 20 3E 40 2B 00 B0 12 +E8 8C 06 20 3E 40 2D 00 B0 12 E8 8C 92 83 C6 21 +0E 12 1E 41 02 00 84 12 FE 85 10 87 AC 80 44 89 +62 8D 3E 51 3A 17 30 41 B0 12 28 8D 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 FE 85 10 87 AC 80 9A 8D +92 8D 3E 90 10 00 E6 2B 7C 2D 9C 8D A2 41 C6 21 +E1 3F 03 20 B0 12 80 8D 43 3C 7A 90 23 00 24 20 +B0 12 30 8D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 30 8D F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 7C 8D 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 80 8D 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 68 8D F2 3F +03 20 B0 12 80 8D F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 68 8D EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A 80 00 13 68 88 7A 85 0A 80 +2C 00 5E 8E A2 8D AC 83 68 8E 40 8E AE 8E 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +9E 8E 00 40 BA 8E 0A 4D 4F 56 2E 42 85 12 9E 8E +40 40 00 00 06 41 44 44 85 12 9E 8E 00 50 D4 8E +0A 41 44 44 2E 42 85 12 9E 8E 40 50 E0 8E 08 41 +44 44 43 00 85 12 9E 8E 00 60 EE 8E 0C 41 44 44 +43 2E 42 00 85 12 9E 8E 40 60 26 8B 08 53 55 42 +43 00 85 12 9E 8E 00 70 0C 8F 0C 53 55 42 43 2E +42 00 85 12 9E 8E 40 70 1A 8F 06 53 55 42 85 12 +9E 8E 00 80 2A 8F 0A 53 55 42 2E 42 85 12 9E 8E +40 80 36 8F 06 43 4D 50 85 12 9E 8E 00 90 44 8F +0A 43 4D 50 2E 42 85 12 9E 8E 40 90 00 00 08 44 +41 44 44 00 85 12 9E 8E 00 A0 5E 8F 0C 44 41 44 +44 2E 42 00 85 12 9E 8E 40 A0 8C 8E 06 42 49 54 +85 12 9E 8E 00 B0 7C 8F 0A 42 49 54 2E 42 85 12 +9E 8E 40 B0 88 8F 06 42 49 43 85 12 9E 8E 00 C0 +96 8F 0A 42 49 43 2E 42 85 12 9E 8E 40 C0 A2 8F +06 42 49 53 85 12 9E 8E 00 D0 B0 8F 0A 42 49 53 +2E 42 85 12 9E 8E 40 D0 00 00 06 58 4F 52 85 12 +9E 8E 00 E0 CA 8F 0A 58 4F 52 2E 42 85 12 9E 8E +40 E0 FC 8E 06 41 4E 44 85 12 9E 8E 00 F0 E4 8F +0A 41 4E 44 2E 42 85 12 9E 8E 40 F0 AC 83 5E 8E +A2 8D 04 90 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F BC 8F 06 52 52 43 85 12 FC 8F 00 10 +16 90 0A 52 52 43 2E 42 85 12 FC 8F 40 10 50 8F +08 53 57 50 42 00 85 12 FC 8F 80 10 22 90 06 52 +52 41 85 12 FC 8F 00 11 3E 90 0A 52 52 41 2E 42 +85 12 FC 8F 40 11 30 90 06 53 58 54 85 12 FC 8F +80 11 00 00 08 50 55 53 48 00 85 12 FC 8F 00 12 +64 90 0C 50 55 53 48 2E 42 00 85 12 FC 8F 40 12 +58 90 08 43 41 4C 4C 00 85 12 FC 8F 80 12 1A 53 +0E 4A 84 12 EE 85 1E 80 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 81 82 90 06 53 3E 3D 86 12 +00 38 AA 90 04 53 3C 00 86 12 00 34 72 90 06 30 +3E 3D 86 12 00 30 BE 90 04 30 3C 00 86 12 00 30 +FA 8A 04 55 3C 00 86 12 00 2C D2 90 06 55 3E 3D +86 12 00 28 C8 90 06 30 3C 3E 86 12 00 24 E6 90 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D 6C 8F +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D DC 90 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +4A 90 0A 42 45 47 49 4E 30 40 32 80 34 91 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D F0 8F 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 FE 90 94 84 7A 85 52 91 0C 52 +45 50 45 41 54 00 0D 12 84 12 92 91 16 91 7A 85 +C2 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D AE 91 06 42 57 31 85 12 +C0 91 00 00 DA 91 06 42 57 32 85 12 C0 91 00 00 +E6 91 06 42 57 33 85 12 C0 91 00 00 FE 91 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 FC 91 00 00 22 92 06 46 +57 32 85 12 FC 91 00 00 2E 92 06 46 57 33 85 12 +FC 91 00 00 9C 91 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 34 89 40 88 7A 85 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 68 8E +0A 80 2C 00 FE 85 10 87 AC 80 44 89 AC 83 5E 8E +40 8E 94 92 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +F2 91 08 52 52 43 4D 00 85 12 7E 92 50 00 C2 92 +08 52 52 41 4D 00 85 12 7E 92 50 01 D0 92 08 52 +4C 41 4D 00 85 12 7E 92 50 02 DE 92 08 52 52 55 +4D 00 85 12 7E 92 50 03 F0 90 0A 50 55 53 48 4D +85 12 7E 92 00 15 FA 92 08 50 4F 50 4D 00 85 12 +7E 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 B6 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_1MHz_I2C.txt b/binaries/MSP_EXP430FR2355_1MHz_I2C.txt index b8ae925..e8eaa7d 100644 --- a/binaries/MSP_EXP430FR2355_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2355_1MHz_I2C.txt @@ -1,334 +1,321 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF DE 93 F0 8B 34 01 -10 00 41 87 B6 81 AA 80 B8 81 8C 81 82 82 DE 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +B0 82 56 81 56 81 58 81 44 81 F0 92 A8 8B 62 8B +62 8B 9E 82 22 83 FA 82 3C 21 E0 20 56 85 B6 80 +C4 80 72 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 F0 92 A8 8B 62 8B 62 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F7 3C 0E 93 3E 4F +79 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 9C 82 B2 49 +20 83 B2 49 F8 82 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 1C 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 7C 84 AC 80 +42 81 3A 83 1E 80 05 1B 5B 37 6D 40 66 83 0A 80 +02 18 9E 84 CA 85 66 83 1E 80 04 1B 5B 30 6D 00 +66 83 B2 88 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 3A 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 66 83 0A 80 02 18 9E 84 CA 85 0A 80 23 00 +1E 83 CA 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +66 83 0A 80 40 FF 32 80 92 84 96 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 43 22 02 F2 D3 47 02 F2 40 +BF 00 43 02 B2 40 00 A5 60 01 82 43 88 01 F2 D0 +C0 00 0D 02 F2 C3 82 01 B2 40 1E 00 84 01 39 40 +5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 39 40 +00 10 29 83 89 43 00 20 FC 23 1E 42 08 18 82 43 +08 18 3E F3 02 20 1E 42 5E 01 B0 12 D0 80 80 81 +00 00 0C 41 43 43 45 50 54 00 30 40 9E 82 0A 4E +2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 A8 3E +21 52 A2 C2 6C 05 B2 B0 10 00 40 05 A1 22 3A 17 +92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 48 9C +06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A +EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C +00 00 06 4B 45 59 30 40 FA 82 58 43 B0 12 46 81 +2F 83 8F 4E 00 00 92 B3 6C 05 FD 27 1E 42 4C 05 +B0 12 44 81 30 4D 00 00 08 45 4D 49 54 00 30 40 +22 83 08 4E 3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 +30 4D 18 83 08 45 43 48 4F 00 B2 40 C2 48 2C 83 +38 40 05 00 B0 12 46 81 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 2C 83 28 42 F3 3F 00 00 +08 54 59 50 45 00 0D 12 3D 40 76 83 29 4F 8F 4E +00 00 7E 49 D4 3F 78 83 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 8D 22 F9 98 00 00 8A 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 81 22 +9B 24 F2 82 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A 80 00 00 96 84 88 83 DA 85 94 88 B0 80 04 84 +14 80 06 5B 54 48 45 4E 5D 00 8C 83 E2 83 A8 83 +C6 83 14 80 06 5B 45 4C 53 45 5D 00 8C 83 F4 83 +A8 83 C4 83 1E 80 04 5B 49 46 5D 00 8C 83 C6 83 +B2 80 C4 83 1E 80 05 0D 6B 6F 20 0A 66 83 9A 80 +84 80 B2 80 C6 83 B4 83 0D 5B 54 48 45 4E 5D 00 +30 4D 18 84 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 24 84 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 88 83 DA 85 42 86 E6 87 56 85 34 84 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 88 83 +DA 85 42 86 66 84 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 92 82 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D E0 81 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A 80 1E 80 +44 88 0A 80 22 00 DA 85 DA 84 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 4C 83 +05 2E 22 00 0D 12 84 12 C4 84 0A 80 66 83 44 88 +56 85 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +C0 84 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 80 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +12 85 04 23 53 00 0D 12 84 12 14 85 4E 85 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 42 85 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 5C 85 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +34 83 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 08 85 88 83 76 85 46 85 72 84 84 85 +60 85 66 83 56 85 F0 84 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D C8 85 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E +0E 43 1E 15 3D 40 4C 87 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 4E 87 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -54 92 BA 92 FC 91 0A 93 C2 91 00 00 8E 8F 00 00 -D2 93 B6 93 26 92 64 92 9E 90 00 00 00 00 26 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C DE 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 43 22 02 -F2 D3 47 02 F2 40 BF 00 43 02 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 B0 00 82 01 B2 40 1E 00 -84 01 82 43 88 01 F2 D0 C0 00 0D 02 39 40 5C 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 80 FE 81 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A 85 82 85 -DE 83 34 80 CE 8D 3E 86 34 80 E8 8D E2 8D D0 8D -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 EA 8D B2 41 C4 21 3E 41 -84 12 0A 80 2B 00 1A 85 82 85 DE 83 34 80 06 8E -3E 86 34 80 00 88 A8 83 1A 85 3E 86 34 80 00 88 -12 8E 3E 5F E7 3F 3E 40 28 00 B0 12 B2 8D 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 6E 89 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A 85 3E 86 34 80 5A 8E 50 8E -21 53 3E 90 10 00 C6 2B 7F 2D 5C 8E B2 41 C4 21 -C1 3F 0D 12 84 12 02 88 8E 8D 6C 8E 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 B2 8D 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 B2 8D -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 3A 8E 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -3A 8E 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 3A 8E FA 23 3C 50 10 00 B0 12 -16 8E EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 02 88 8E 8D 38 8F FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 3A 8E E0 23 -3C 50 80 00 B0 12 16 8E DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 80 00 13 48 87 4E 84 0A 80 -2C 00 62 8E 2E 8F 78 8F 09 4B 2E 4E 0E DC A2 3F -40 8A 03 4D 4F 56 85 12 6E 8F 00 40 82 8F 05 4D -4F 56 2E 42 85 12 6E 8F 40 40 00 00 03 41 44 44 -85 12 6E 8F 00 50 9C 8F 05 41 44 44 2E 42 85 12 -6E 8F 40 50 A8 8F 04 41 44 44 43 00 85 12 6E 8F -00 60 B6 8F 06 41 44 44 43 2E 42 00 85 12 6E 8F -40 60 5C 8F 04 53 55 42 43 00 85 12 6E 8F 00 70 -D4 8F 06 53 55 42 43 2E 42 00 85 12 6E 8F 40 70 -E2 8F 03 53 55 42 85 12 6E 8F 00 80 F2 8F 05 53 -55 42 2E 42 85 12 6E 8F 40 80 16 8A 03 43 4D 50 -85 12 6E 8F 00 90 0C 90 05 43 4D 50 2E 42 85 12 -6E 8F 40 90 00 8A 04 44 41 44 44 00 85 12 6E 8F -00 A0 26 90 06 44 41 44 44 2E 42 00 85 12 6E 8F -40 A0 18 90 03 42 49 54 85 12 6E 8F 00 B0 44 90 -05 42 49 54 2E 42 85 12 6E 8F 40 B0 50 90 03 42 -49 43 85 12 6E 8F 00 C0 5E 90 05 42 49 43 2E 42 -85 12 6E 8F 40 C0 6A 90 03 42 49 53 85 12 6E 8F -00 D0 78 90 05 42 49 53 2E 42 85 12 6E 8F 40 D0 -00 00 03 58 4F 52 85 12 6E 8F 00 E0 92 90 05 58 -4F 52 2E 42 85 12 6E 8F 40 E0 C4 8F 03 41 4E 44 -85 12 6E 8F 00 F0 AC 90 05 41 4E 44 2E 42 85 12 -6E 8F 40 F0 02 88 62 8E CA 90 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F FE 8F 03 52 52 43 -85 12 C4 90 00 10 DC 90 05 52 52 43 2E 42 85 12 -C4 90 40 10 E8 90 04 53 57 50 42 00 85 12 C4 90 -80 10 F6 90 03 52 52 41 85 12 C4 90 00 11 04 91 -05 52 52 41 2E 42 85 12 C4 90 40 11 10 91 03 53 -58 54 85 12 C4 90 80 11 00 00 04 50 55 53 48 00 -85 12 C4 90 00 12 2A 91 06 50 55 53 48 2E 42 00 -85 12 C4 90 40 12 84 90 04 43 41 4C 4C 00 85 12 -C4 90 80 12 1A 53 0E 4A 0D 12 84 12 C4 84 14 80 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 81 -1E 91 03 53 3E 3D 86 12 00 38 72 91 02 53 3C 00 -86 12 00 34 38 91 03 30 3E 3D 86 12 00 30 86 91 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C 9A 91 03 55 3E 3D 86 12 00 28 90 91 03 30 -3C 3E 86 12 00 24 AE 91 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D A4 91 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 34 90 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 48 91 05 42 45 47 49 4E -30 40 28 80 D8 91 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D B8 90 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 C6 91 -A8 83 4E 84 7C 91 06 52 45 50 45 41 54 00 0D 12 -84 12 5A 92 DE 91 4E 84 8A 92 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -1A 92 03 42 57 31 85 12 88 92 00 00 A2 92 03 42 -57 32 85 12 88 92 00 00 AE 92 03 42 57 33 85 12 -88 92 00 00 C6 92 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 C4 92 00 00 -E6 92 03 46 57 32 85 12 C4 92 00 00 F2 92 03 46 -57 33 85 12 C4 92 00 00 FE 92 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 88 -DC 87 4E 84 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 02 88 8E 8D 48 93 92 53 C4 21 3E 40 2C 00 -84 12 1A 85 3E 86 34 80 00 88 24 8F 5E 93 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 76 92 04 52 52 43 -4D 00 85 12 42 93 50 00 8C 93 04 52 52 41 4D 00 -85 12 42 93 50 01 9A 93 04 52 4C 41 4D 00 85 12 -42 93 50 02 A8 93 04 52 52 55 4D 00 85 12 42 93 -50 03 B8 91 05 50 55 53 48 4D 85 12 42 93 00 15 -C4 93 04 50 4F 50 4D 00 85 12 42 93 00 17 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 80 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 04 85 03 5C 92 42 +C2 21 C6 21 30 4D 0D 12 84 12 84 80 88 83 DA 85 +B0 80 1E 89 42 86 08 88 0A 4E 3E 4F 3D 40 22 88 +6D 27 3D 40 FC 87 1A E2 BC 21 14 24 0E 12 3E 4F +30 41 24 88 3E 4F 3D 40 FC 87 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 FA 89 2A 3C +EC 87 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF +3E 4F 30 4D 42 88 0F 4C 49 54 45 52 41 4C 82 93 +BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 +0A 80 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D 7E 85 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D A4 84 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F +30 4D 3F 40 80 20 0E 43 84 12 1E 80 02 0D 0A 00 +66 83 94 80 F6 87 84 84 AE 84 1E 80 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 81 32 80 0A 80 40 FF +B6 84 1E 80 09 46 52 41 4D 20 66 75 6C 6C 08 81 +B2 80 BA 88 A4 88 0D 41 42 4F 52 54 22 00 0D 12 +84 12 C4 84 0A 80 08 81 44 88 56 85 D4 85 02 27 +0D 12 84 12 88 83 DA 85 42 86 B0 80 20 89 E8 84 +2C 88 4E 84 07 5B 27 5D 0D 12 84 12 10 89 0A 80 +0A 80 44 88 44 88 56 85 24 89 03 5B 82 43 BC 21 +30 4D 00 00 02 5D B2 43 BC 21 30 4D 9C 84 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 88 83 DA 85 +42 86 B0 80 20 89 AE 84 AC 80 78 89 0A 80 0A 80 +44 88 44 88 0A 80 44 88 44 88 56 85 00 00 02 3A +30 12 CE 89 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 +88 83 DA 85 96 89 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A +B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D +82 9F BA 21 66 25 84 12 1E 80 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 81 3A 89 03 3B +82 93 BC 21 F4 26 0D 12 84 12 0A 80 56 85 44 88 +E0 89 3C 89 56 85 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 21 D8 D3 00 00 30 4D 8E 88 0C 43 +52 45 41 54 45 00 B0 12 84 89 BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 60 83 0A 44 4F 45 53 3E 1A 42 +B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +7E 89 0E 3A 4E 4F 4E 41 4D 45 30 12 CE 89 2F 83 +8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 18 8A 05 49 53 00 0D 12 82 93 +BC 21 08 20 84 12 10 89 9A 8A 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 28 89 0A 80 9C 8A 44 88 56 85 +2E 8A 08 43 4F 44 45 00 B0 12 84 89 A2 82 C8 21 +61 3C 70 85 0E 48 44 4E 43 4F 44 45 B2 40 88 8B +CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 E0 89 E6 8A 3D 41 92 42 D0 21 CC 21 5D 3C +B2 8A 0E 43 4F 44 45 4E 4E 4D 30 12 BC 8A B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 +C8 21 EF 3F C4 8A 0B 48 49 32 4C 4F A2 53 C8 21 +1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 50 8B +B2 40 62 8B D0 21 82 4E CE 21 30 40 E8 84 85 12 +4E 8B 4E 89 F6 88 E0 8B F2 8A 48 8A 92 85 3C 86 +0E 89 36 8B 88 8A 62 8A FE 89 56 88 6A 8C 94 86 +00 00 00 00 85 12 4E 8B E4 92 68 91 C8 92 90 90 +EC 90 3A 91 16 92 22 92 B2 8F D6 90 00 00 00 00 +24 8B A2 8E 00 00 3E 92 82 8B B2 40 62 8B CE 21 +82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 21 3A 40 42 18 B0 12 B6 8B 30 4D C8 8B +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 21 B0 12 B6 8B 1A 42 CA 21 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 0E 82 +FE FF 29 83 B9 40 FA 81 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 E0 FF 3B 40 10 00 3A 40 3A 18 +B0 12 BA 8B 82 43 4A 18 C7 3F 5C 8C B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 44 89 0C 4D 41 52 4B 45 +52 00 12 12 C6 21 0D 12 84 12 88 83 DA 85 42 86 +AC 80 88 8C 7C 84 1C 88 8A 8C 3E 4F 3D 41 B2 41 +C6 21 B0 12 84 89 BA 40 85 12 FC FF BA 40 5A 8C +FE FF 28 83 8A 48 00 00 BA 40 82 80 02 00 A2 52 +C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 21 84 12 DA 85 42 86 AC 80 +F4 8C D4 8C 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 5A 8C 00 00 01 20 3E 52 2E 83 +21 53 30 41 EC 86 AC 80 FC 8C F0 8C FE 8C B2 41 +C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 +B0 12 C4 8C 15 20 3E 40 2B 00 B0 12 C4 8C 06 20 +3E 40 2D 00 B0 12 C4 8C 92 83 C6 21 0E 12 1E 41 +02 00 84 12 DA 85 EC 86 AC 80 20 89 3E 8D 3E 51 +3A 17 30 41 B0 12 04 8D 19 42 C8 21 89 4E 00 00 +A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 +3D 15 84 12 DA 85 EC 86 AC 80 76 8D 6E 8D 3E 90 +10 00 E6 2B 7C 2D 78 8D A2 41 C6 21 E1 3F 03 20 +B0 12 5C 8D 43 3C 7A 90 23 00 24 20 B0 12 0C 8D +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +0C 8D F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +58 8D 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 5C 8D +92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 44 8D F2 3F 03 20 B0 12 +5C 8D F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 44 8D EA 3F 0C 43 1B 42 C8 21 +A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 +7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A 80 00 13 44 88 56 85 0A 80 2C 00 3A 8E +7E 8D 88 83 44 8E 1C 8E 8A 8E 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 7A 8E 00 40 +96 8E 0A 4D 4F 56 2E 42 85 12 7A 8E 40 40 00 00 +06 41 44 44 85 12 7A 8E 00 50 B0 8E 0A 41 44 44 +2E 42 85 12 7A 8E 40 50 BC 8E 08 41 44 44 43 00 +85 12 7A 8E 00 60 CA 8E 0C 41 44 44 43 2E 42 00 +85 12 7A 8E 40 60 02 8B 08 53 55 42 43 00 85 12 +7A 8E 00 70 E8 8E 0C 53 55 42 43 2E 42 00 85 12 +7A 8E 40 70 F6 8E 06 53 55 42 85 12 7A 8E 00 80 +06 8F 0A 53 55 42 2E 42 85 12 7A 8E 40 80 12 8F +06 43 4D 50 85 12 7A 8E 00 90 20 8F 0A 43 4D 50 +2E 42 85 12 7A 8E 40 90 00 00 08 44 41 44 44 00 +85 12 7A 8E 00 A0 3A 8F 0C 44 41 44 44 2E 42 00 +85 12 7A 8E 40 A0 68 8E 06 42 49 54 85 12 7A 8E +00 B0 58 8F 0A 42 49 54 2E 42 85 12 7A 8E 40 B0 +64 8F 06 42 49 43 85 12 7A 8E 00 C0 72 8F 0A 42 +49 43 2E 42 85 12 7A 8E 40 C0 7E 8F 06 42 49 53 +85 12 7A 8E 00 D0 8C 8F 0A 42 49 53 2E 42 85 12 +7A 8E 40 D0 00 00 06 58 4F 52 85 12 7A 8E 00 E0 +A6 8F 0A 58 4F 52 2E 42 85 12 7A 8E 40 E0 D8 8E +06 41 4E 44 85 12 7A 8E 00 F0 C0 8F 0A 41 4E 44 +2E 42 85 12 7A 8E 40 F0 88 83 3A 8E 7E 8D E0 8F +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +98 8F 06 52 52 43 85 12 D8 8F 00 10 F2 8F 0A 52 +52 43 2E 42 85 12 D8 8F 40 10 2C 8F 08 53 57 50 +42 00 85 12 D8 8F 80 10 FE 8F 06 52 52 41 85 12 +D8 8F 00 11 1A 90 0A 52 52 41 2E 42 85 12 D8 8F +40 11 0C 90 06 53 58 54 85 12 D8 8F 80 11 00 00 +08 50 55 53 48 00 85 12 D8 8F 00 12 40 90 0C 50 +55 53 48 2E 42 00 85 12 D8 8F 40 12 34 90 08 43 +41 4C 4C 00 85 12 D8 8F 80 12 1A 53 0E 4A 84 12 +CA 85 1E 80 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 81 5E 90 06 53 3E 3D 86 12 00 38 86 90 +04 53 3C 00 86 12 00 34 4E 90 06 30 3E 3D 86 12 +00 30 9A 90 04 30 3C 00 86 12 00 30 D6 8A 04 55 +3C 00 86 12 00 2C AE 90 06 55 3E 3D 86 12 00 28 +A4 90 06 30 3C 3E 86 12 00 24 C2 90 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E +00 00 A2 53 C8 21 0E 4A 30 4D 48 8F 08 54 48 45 +4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D B8 90 +08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 +A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 26 90 0A 42 +45 47 49 4E 30 40 32 80 10 91 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 21 30 4D CC 8F 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 DA 90 70 84 56 85 2E 91 0C 52 45 50 45 41 +54 00 0D 12 84 12 6E 91 F2 90 56 85 9E 91 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 +00 00 30 4D 8A 91 06 42 57 31 85 12 9C 91 00 00 +B6 91 06 42 57 32 85 12 9C 91 00 00 C2 91 06 42 +57 33 85 12 9C 91 00 00 DA 91 3D 41 1A 42 C8 21 +28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 +A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 D8 91 00 00 FE 91 06 46 57 32 85 12 +D8 91 00 00 0A 92 06 46 57 33 85 12 D8 91 00 00 +78 91 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 10 89 1C 88 56 85 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 44 8E 0A 80 2C 00 +DA 85 EC 86 AC 80 20 89 88 83 3A 8E 1C 8E 70 92 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E CE 91 08 52 +52 43 4D 00 85 12 5A 92 50 00 9E 92 08 52 52 41 +4D 00 85 12 5A 92 50 01 AC 92 08 52 4C 41 4D 00 +85 12 5A 92 50 02 BA 92 08 52 52 55 4D 00 85 12 +5A 92 50 03 CC 90 0A 50 55 53 48 4D 85 12 5A 92 +00 15 D6 92 08 50 4F 50 4D 00 85 12 5A 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -82 82 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +B0 82 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/MSP_EXP430FR2355_1MHz_UART.txt b/binaries/MSP_EXP430FR2355_1MHz_UART.txt deleted file mode 100644 index 601cd93..0000000 --- a/binaries/MSP_EXP430FR2355_1MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF F4 93 02 8C 34 01 -10 00 41 B3 94 81 AA 80 DA 81 9C 81 94 82 F4 93 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 9C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -9C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 8A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 80 05 92 42 02 18 86 05 92 42 04 18 -88 05 F2 D0 0C 00 2B 02 92 C3 80 05 92 D3 9A 05 -92 C3 30 01 30 41 09 3C A2 B3 9C 05 FD 27 B2 40 -13 00 8E 05 D2 D3 03 02 30 41 A2 B3 9C 05 FD 27 -B2 40 11 00 8E 05 D2 C3 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 8C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 9C 05 FD 27 -C2 48 8E 05 30 4D C8 82 2D 83 92 B3 9C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 9C 05 -FD 27 58 42 8C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 9C 05 FD 27 1E 42 -8C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 6A 92 D0 92 12 92 20 93 D8 91 00 00 A4 8F -00 00 E8 93 CC 93 3C 92 7A 92 B4 90 00 00 00 00 -3C 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -F4 93 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E2 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 -26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B0 00 -82 01 B2 40 1E 00 84 01 82 43 88 01 F2 D0 C0 00 -0D 02 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 80 1E 82 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C 85 94 85 F0 83 34 80 E4 8D 50 86 34 80 -FE 8D F8 8D E6 8D 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 00 8E -B2 41 C4 21 3E 41 84 12 0A 80 2B 00 2C 85 94 85 -F0 83 34 80 1C 8E 50 86 34 80 12 88 BA 83 2C 85 -50 86 34 80 12 88 28 8E 3E 5F E7 3F 3E 40 28 00 -B0 12 C8 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 80 89 -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C 85 50 86 -34 80 70 8E 66 8E 21 53 3E 90 10 00 C6 2B 7F 2D -72 8E B2 41 C4 21 C1 3F 0D 12 84 12 14 88 A4 8D -82 8E 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 C8 8D 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 C8 8D ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 50 8E 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 50 8E 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 50 8E FA 23 -3C 50 10 00 B0 12 2C 8E EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 14 88 A4 8D 4E 8F FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 50 8E E0 23 3C 50 80 00 B0 12 2C 8E DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 -5A 87 60 84 0A 80 2C 00 78 8E 44 8F 8E 8F 09 4B -2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 85 12 84 8F -00 40 98 8F 05 4D 4F 56 2E 42 85 12 84 8F 40 40 -00 00 03 41 44 44 85 12 84 8F 00 50 B2 8F 05 41 -44 44 2E 42 85 12 84 8F 40 50 BE 8F 04 41 44 44 -43 00 85 12 84 8F 00 60 CC 8F 06 41 44 44 43 2E -42 00 85 12 84 8F 40 60 72 8F 04 53 55 42 43 00 -85 12 84 8F 00 70 EA 8F 06 53 55 42 43 2E 42 00 -85 12 84 8F 40 70 F8 8F 03 53 55 42 85 12 84 8F -00 80 08 90 05 53 55 42 2E 42 85 12 84 8F 40 80 -28 8A 03 43 4D 50 85 12 84 8F 00 90 22 90 05 43 -4D 50 2E 42 85 12 84 8F 40 90 12 8A 04 44 41 44 -44 00 85 12 84 8F 00 A0 3C 90 06 44 41 44 44 2E -42 00 85 12 84 8F 40 A0 2E 90 03 42 49 54 85 12 -84 8F 00 B0 5A 90 05 42 49 54 2E 42 85 12 84 8F -40 B0 66 90 03 42 49 43 85 12 84 8F 00 C0 74 90 -05 42 49 43 2E 42 85 12 84 8F 40 C0 80 90 03 42 -49 53 85 12 84 8F 00 D0 8E 90 05 42 49 53 2E 42 -85 12 84 8F 40 D0 00 00 03 58 4F 52 85 12 84 8F -00 E0 A8 90 05 58 4F 52 2E 42 85 12 84 8F 40 E0 -DA 8F 03 41 4E 44 85 12 84 8F 00 F0 C2 90 05 41 -4E 44 2E 42 85 12 84 8F 40 F0 14 88 78 8E E0 90 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -14 90 03 52 52 43 85 12 DA 90 00 10 F2 90 05 52 -52 43 2E 42 85 12 DA 90 40 10 FE 90 04 53 57 50 -42 00 85 12 DA 90 80 10 0C 91 03 52 52 41 85 12 -DA 90 00 11 1A 91 05 52 52 41 2E 42 85 12 DA 90 -40 11 26 91 03 53 58 54 85 12 DA 90 80 11 00 00 -04 50 55 53 48 00 85 12 DA 90 00 12 40 91 06 50 -55 53 48 2E 42 00 85 12 DA 90 40 12 9A 90 04 43 -41 4C 4C 00 85 12 DA 90 80 12 1A 53 0E 4A 0D 12 -84 12 D6 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 81 34 91 03 53 3E 3D 86 12 00 38 -88 91 02 53 3C 00 86 12 00 34 4E 91 03 30 3E 3D -86 12 00 30 9C 91 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C B0 91 03 55 3E 3D 86 12 -00 28 A6 91 03 30 3C 3E 86 12 00 24 C4 91 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D BA 91 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -4A 90 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 5E 91 -05 42 45 47 49 4E 30 40 28 80 EE 91 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D CE 90 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 DC 91 BA 83 60 84 92 91 06 52 45 50 -45 41 54 00 0D 12 84 12 70 92 F4 91 60 84 A0 92 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 30 92 03 42 57 31 85 12 9E 92 -00 00 B8 92 03 42 57 32 85 12 9E 92 00 00 C4 92 -03 42 57 33 85 12 9E 92 00 00 DC 92 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 DA 92 00 00 FC 92 03 46 57 32 85 12 DA 92 -00 00 08 93 03 46 57 33 85 12 DA 92 00 00 14 93 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 92 88 EE 87 60 84 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 14 88 A4 8D 5E 93 92 53 -C4 21 3E 40 2C 00 84 12 2C 85 50 86 34 80 12 88 -3A 8F 74 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -8C 92 04 52 52 43 4D 00 85 12 58 93 50 00 A2 93 -04 52 52 41 4D 00 85 12 58 93 50 01 B0 93 04 52 -4C 41 4D 00 85 12 58 93 50 02 BE 93 04 52 52 55 -4D 00 85 12 58 93 50 03 CE 91 05 50 55 53 48 4D -85 12 58 93 00 15 DA 93 04 50 4F 50 4D 00 85 12 -58 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 94 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/MSP_EXP430FR2355_24MHz_115200.txt b/binaries/MSP_EXP430FR2355_24MHz_115200.txt new file mode 100644 index 0000000..9a11363 --- /dev/null +++ b/binaries/MSP_EXP430FR2355_24MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +C0 5D 0D 00 01 49 18 00 FD FF 35 01 10 00 A1 59 +CC 82 7E 81 84 81 54 81 3C 83 2A 93 E2 8B 9C 8B +9C 8B B2 82 70 83 38 83 3C 21 E0 20 90 85 B6 80 +C4 80 AC 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3C 83 2A 93 E2 8B 9C 8B 9C 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +96 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 82 B2 49 +6E 83 B2 49 36 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 56 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3C 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 B6 84 AC 80 52 81 7E 83 1E 80 04 1B +5B 37 6D 00 A0 83 A0 83 1E 80 04 1B 5B 30 6D 00 +A0 83 EC 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 7E 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 A0 83 04 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A0 83 0A 80 40 FF 32 80 +CC 84 D0 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +F2 40 A5 00 A1 01 F2 40 20 00 A0 01 D2 43 A1 01 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 F2 D0 0E 00 82 01 B2 40 DC 02 84 01 +39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 80 86 81 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 82 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 10 83 3C 40 1C 83 5D 15 9A 3E 21 52 3A 17 +58 42 8C 05 48 9B 09 20 A2 B3 9C 05 FD 27 B2 40 +13 00 8E 05 D2 D3 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 9C 05 FD 27 C2 48 8E 05 30 4D +12 83 2D 83 92 B3 9C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 9C 05 FD 27 58 42 8C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 38 83 30 12 4E 83 A2 B3 9C 05 +FD 27 B2 40 11 00 8E 05 D2 C3 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 9C 05 FD 27 B0 12 D8 82 1E 42 +8C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 70 83 +08 4E 3E 4F C7 3F 66 83 08 45 43 48 4F 00 B2 40 +C2 48 0A 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 0A 83 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 B0 83 29 4F 8F 4E 00 00 7E 49 DE 3F +B2 83 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +70 22 F9 98 00 00 6D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 64 22 9B 24 30 83 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 80 00 00 D0 84 +C2 83 14 86 CE 88 B0 80 3E 84 14 80 06 5B 54 48 +45 4E 5D 00 C6 83 1C 84 E2 83 00 84 14 80 06 5B +45 4C 53 45 5D 00 C6 83 2E 84 E2 83 FE 83 1E 80 +04 5B 49 46 5D 00 C6 83 00 84 B2 80 FE 83 1E 80 +05 0D 6B 6F 20 0A A0 83 9A 80 84 80 B2 80 00 84 +EE 83 0D 5B 54 48 45 4E 5D 00 30 4D 52 84 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 5E 84 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 C2 83 14 86 +7C 86 20 88 90 85 6E 84 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 C2 83 14 86 7C 86 A0 84 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D A6 82 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A 80 1E 80 7E 88 0A 80 22 00 +14 86 14 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 88 83 05 2E 22 00 0D 12 +84 12 FE 84 0A 80 A0 83 7E 88 90 85 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D FA 84 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 4C 85 04 23 53 00 +0D 12 84 12 4E 85 88 85 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 7C 85 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 96 85 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 78 83 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 42 85 +C2 83 B0 85 80 85 AC 84 BE 85 9A 85 A0 83 90 85 +2A 85 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 02 86 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +86 87 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 88 87 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 3E 85 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 80 C2 83 14 86 B0 80 58 89 7C 86 +42 88 0A 4E 3E 4F 3D 40 5C 88 6D 27 3D 40 36 88 +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 5E 88 3E 4F +3D 40 36 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 34 8A 2A 3C 26 88 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7C 88 +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D B8 85 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D DE 84 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E 80 02 0D 0A 00 A0 83 94 80 30 88 +BE 84 E8 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 81 32 80 0A 80 40 FF F0 84 1E 80 09 46 +52 41 4D 20 66 75 6C 6C 08 81 B2 80 F4 88 DE 88 +0D 41 42 4F 52 54 22 00 0D 12 84 12 FE 84 0A 80 +08 81 7E 88 90 85 0E 86 02 27 0D 12 84 12 C2 83 +14 86 7C 86 B0 80 5A 89 22 85 66 88 88 84 07 5B +27 5D 0D 12 84 12 4A 89 0A 80 0A 80 7E 88 7E 88 +90 85 5E 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D D6 84 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C2 83 14 86 7C 86 B0 80 5A 89 +E8 84 AC 80 B2 89 0A 80 0A 80 7E 88 7E 88 0A 80 +7E 88 7E 88 90 85 00 00 02 3A 30 12 08 8A 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C2 83 14 86 D0 89 +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 81 74 89 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A 80 90 85 7E 88 1A 8A 76 89 90 85 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D C8 88 0C 43 52 45 41 54 45 00 +B0 12 BE 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +9A 83 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D B8 89 0E 3A 4E 4F +4E 41 4D 45 30 12 08 8A 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +52 8A 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +4A 89 D4 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +62 89 0A 80 D6 8A 7E 88 90 85 68 8A 08 43 4F 44 +45 00 B0 12 BE 89 A2 82 C8 21 61 3C AA 85 0E 48 +44 4E 43 4F 44 45 B2 40 C2 8B CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 1A 8A 20 8B +3D 41 92 42 D0 21 CC 21 5D 3C EC 8A 0E 43 4F 44 +45 4E 4E 4D 30 12 F6 8A B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FE 8A +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 8A 8B B2 40 9C 8B D0 21 +82 4E CE 21 30 40 22 85 85 12 88 8B 88 89 30 89 +1A 8C 2C 8B 82 8A CC 85 76 86 48 89 70 8B C2 8A +9C 8A 38 8A 90 88 A4 8C CE 86 00 00 00 00 85 12 +88 8B 1E 93 A2 91 02 93 CA 90 26 91 74 91 50 92 +5C 92 EC 8F 10 91 00 00 00 00 5E 8B DC 8E 00 00 +78 92 BC 8B B2 40 9C 8B CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 F0 8B 30 4D 02 8C 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 F0 8B +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 +F2 81 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E2 FF 3B 40 10 00 3A 40 3A 18 B0 12 F4 8B 82 43 +4A 18 C7 3F 96 8C B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 7E 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C2 83 14 86 7C 86 AC 80 C2 8C B6 84 +56 88 C4 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BE 89 +BA 40 85 12 FC FF BA 40 94 8C FE FF 28 83 8A 48 +00 00 BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 14 86 7C 86 AC 80 2E 8D 0E 8D 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +94 8C 00 00 01 20 3E 52 2E 83 21 53 30 41 26 87 +AC 80 36 8D 2A 8D 38 8D B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 FE 8C 15 20 +3E 40 2B 00 B0 12 FE 8C 06 20 3E 40 2D 00 B0 12 +FE 8C 92 83 C6 21 0E 12 1E 41 02 00 84 12 14 86 +26 87 AC 80 5A 89 78 8D 3E 51 3A 17 30 41 B0 12 +3E 8D 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 14 86 +26 87 AC 80 B0 8D A8 8D 3E 90 10 00 E6 2B 7C 2D +B2 8D A2 41 C6 21 E1 3F 03 20 B0 12 96 8D 43 3C +7A 90 23 00 24 20 B0 12 46 8D 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 46 8D F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 92 8D 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 96 8D 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 7E 8D F2 3F 03 20 B0 12 96 8D F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +7E 8D EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 +7E 88 90 85 0A 80 2C 00 74 8E B8 8D C2 83 7E 8E +56 8E C4 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 B4 8E 00 40 D0 8E 0A 4D 4F 56 +2E 42 85 12 B4 8E 40 40 00 00 06 41 44 44 85 12 +B4 8E 00 50 EA 8E 0A 41 44 44 2E 42 85 12 B4 8E +40 50 F6 8E 08 41 44 44 43 00 85 12 B4 8E 00 60 +04 8F 0C 41 44 44 43 2E 42 00 85 12 B4 8E 40 60 +3C 8B 08 53 55 42 43 00 85 12 B4 8E 00 70 22 8F +0C 53 55 42 43 2E 42 00 85 12 B4 8E 40 70 30 8F +06 53 55 42 85 12 B4 8E 00 80 40 8F 0A 53 55 42 +2E 42 85 12 B4 8E 40 80 4C 8F 06 43 4D 50 85 12 +B4 8E 00 90 5A 8F 0A 43 4D 50 2E 42 85 12 B4 8E +40 90 00 00 08 44 41 44 44 00 85 12 B4 8E 00 A0 +74 8F 0C 44 41 44 44 2E 42 00 85 12 B4 8E 40 A0 +A2 8E 06 42 49 54 85 12 B4 8E 00 B0 92 8F 0A 42 +49 54 2E 42 85 12 B4 8E 40 B0 9E 8F 06 42 49 43 +85 12 B4 8E 00 C0 AC 8F 0A 42 49 43 2E 42 85 12 +B4 8E 40 C0 B8 8F 06 42 49 53 85 12 B4 8E 00 D0 +C6 8F 0A 42 49 53 2E 42 85 12 B4 8E 40 D0 00 00 +06 58 4F 52 85 12 B4 8E 00 E0 E0 8F 0A 58 4F 52 +2E 42 85 12 B4 8E 40 E0 12 8F 06 41 4E 44 85 12 +B4 8E 00 F0 FA 8F 0A 41 4E 44 2E 42 85 12 B4 8E +40 F0 C2 83 74 8E B8 8D 1A 90 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F D2 8F 06 52 52 43 +85 12 12 90 00 10 2C 90 0A 52 52 43 2E 42 85 12 +12 90 40 10 66 8F 08 53 57 50 42 00 85 12 12 90 +80 10 38 90 06 52 52 41 85 12 12 90 00 11 54 90 +0A 52 52 41 2E 42 85 12 12 90 40 11 46 90 06 53 +58 54 85 12 12 90 80 11 00 00 08 50 55 53 48 00 +85 12 12 90 00 12 7A 90 0C 50 55 53 48 2E 42 00 +85 12 12 90 40 12 6E 90 08 43 41 4C 4C 00 85 12 +12 90 80 12 1A 53 0E 4A 84 12 04 86 1E 80 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 81 98 90 +06 53 3E 3D 86 12 00 38 C0 90 04 53 3C 00 86 12 +00 34 88 90 06 30 3E 3D 86 12 00 30 D4 90 04 30 +3C 00 86 12 00 30 10 8B 04 55 3C 00 86 12 00 2C +E8 90 06 55 3E 3D 86 12 00 28 DE 90 06 30 3C 3E +86 12 00 24 FC 90 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 82 8F 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D F2 90 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 60 90 0A 42 45 47 49 4E 30 40 +32 80 4A 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +06 90 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 14 91 AA 84 +90 85 68 91 0C 52 45 50 45 41 54 00 0D 12 84 12 +A8 91 2C 91 90 85 D8 91 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D C4 91 +06 42 57 31 85 12 D6 91 00 00 F0 91 06 42 57 32 +85 12 D6 91 00 00 FC 91 06 42 57 33 85 12 D6 91 +00 00 14 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 12 92 +00 00 38 92 06 46 57 32 85 12 12 92 00 00 44 92 +06 46 57 33 85 12 12 92 00 00 B2 91 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +4A 89 56 88 90 85 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 7E 8E 0A 80 2C 00 14 86 26 87 AC 80 +5A 89 C2 83 74 8E 56 8E AA 92 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 08 92 08 52 52 43 4D 00 85 12 +94 92 50 00 D8 92 08 52 52 41 4D 00 85 12 94 92 +50 01 E6 92 08 52 4C 41 4D 00 85 12 94 92 50 02 +F4 92 08 52 52 55 4D 00 85 12 94 92 50 03 06 91 +0A 50 55 53 48 4D 85 12 94 92 00 15 10 93 08 50 +4F 50 4D 00 85 12 94 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 CC 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_24MHz_6MBds.txt b/binaries/MSP_EXP430FR2355_24MHz_6MBds.txt new file mode 100644 index 0000000..c2eb376 --- /dev/null +++ b/binaries/MSP_EXP430FR2355_24MHz_6MBds.txt @@ -0,0 +1,325 @@ +@1800 +C0 5D 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +CC 82 7E 81 84 81 54 81 3C 83 2A 93 E2 8B 9C 8B +9C 8B B2 82 70 83 38 83 3C 21 E0 20 90 85 B6 80 +C4 80 AC 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +3C 83 2A 93 E2 8B 9C 8B 9C 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +96 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 82 B2 49 +6E 83 B2 49 36 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 56 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3C 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 B6 84 AC 80 52 81 7E 83 1E 80 04 1B +5B 37 6D 00 A0 83 A0 83 1E 80 04 1B 5B 30 6D 00 +A0 83 EC 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 7E 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 A0 83 04 86 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A0 83 0A 80 40 FF 32 80 +CC 84 D0 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +F2 40 A5 00 A1 01 F2 40 20 00 A0 01 D2 43 A1 01 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 F2 D0 0E 00 82 01 B2 40 DC 02 84 01 +39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 80 86 81 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 82 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 10 83 3C 40 1C 83 5D 15 9A 3E 21 52 3A 17 +58 42 8C 05 48 9B 09 20 A2 B3 9C 05 FD 27 B2 40 +13 00 8E 05 D2 D3 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 9C 05 FD 27 C2 48 8E 05 30 4D +12 83 2D 83 92 B3 9C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 9C 05 FD 27 58 42 8C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 38 83 30 12 4E 83 A2 B3 9C 05 +FD 27 B2 40 11 00 8E 05 D2 C3 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 9C 05 FD 27 B0 12 D8 82 1E 42 +8C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 70 83 +08 4E 3E 4F C7 3F 66 83 08 45 43 48 4F 00 B2 40 +C2 48 0A 83 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 0A 83 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 B0 83 29 4F 8F 4E 00 00 7E 49 DE 3F +B2 83 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +70 22 F9 98 00 00 6D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 64 22 9B 24 30 83 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 80 00 00 D0 84 +C2 83 14 86 CE 88 B0 80 3E 84 14 80 06 5B 54 48 +45 4E 5D 00 C6 83 1C 84 E2 83 00 84 14 80 06 5B +45 4C 53 45 5D 00 C6 83 2E 84 E2 83 FE 83 1E 80 +04 5B 49 46 5D 00 C6 83 00 84 B2 80 FE 83 1E 80 +05 0D 6B 6F 20 0A A0 83 9A 80 84 80 B2 80 00 84 +EE 83 0D 5B 54 48 45 4E 5D 00 30 4D 52 84 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 5E 84 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 C2 83 14 86 +7C 86 20 88 90 85 6E 84 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 C2 83 14 86 7C 86 A0 84 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D A6 82 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A 80 1E 80 7E 88 0A 80 22 00 +14 86 14 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 88 83 05 2E 22 00 0D 12 +84 12 FE 84 0A 80 A0 83 7E 88 90 85 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D FA 84 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 4C 85 04 23 53 00 +0D 12 84 12 4E 85 88 85 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 7C 85 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 96 85 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 78 83 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 42 85 +C2 83 B0 85 80 85 AC 84 BE 85 9A 85 A0 83 90 85 +2A 85 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 02 86 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +86 87 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 88 87 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 3E 85 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 80 C2 83 14 86 B0 80 58 89 7C 86 +42 88 0A 4E 3E 4F 3D 40 5C 88 6D 27 3D 40 36 88 +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 5E 88 3E 4F +3D 40 36 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 34 8A 2A 3C 26 88 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 7C 88 +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D B8 85 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D DE 84 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E 80 02 0D 0A 00 A0 83 94 80 30 88 +BE 84 E8 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 81 32 80 0A 80 40 FF F0 84 1E 80 09 46 +52 41 4D 20 66 75 6C 6C 08 81 B2 80 F4 88 DE 88 +0D 41 42 4F 52 54 22 00 0D 12 84 12 FE 84 0A 80 +08 81 7E 88 90 85 0E 86 02 27 0D 12 84 12 C2 83 +14 86 7C 86 B0 80 5A 89 22 85 66 88 88 84 07 5B +27 5D 0D 12 84 12 4A 89 0A 80 0A 80 7E 88 7E 88 +90 85 5E 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D D6 84 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C2 83 14 86 7C 86 B0 80 5A 89 +E8 84 AC 80 B2 89 0A 80 0A 80 7E 88 7E 88 0A 80 +7E 88 7E 88 90 85 00 00 02 3A 30 12 08 8A 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C2 83 14 86 D0 89 +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 81 74 89 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A 80 90 85 7E 88 1A 8A 76 89 90 85 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D C8 88 0C 43 52 45 41 54 45 00 +B0 12 BE 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +9A 83 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D B8 89 0E 3A 4E 4F +4E 41 4D 45 30 12 08 8A 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +52 8A 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +4A 89 D4 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +62 89 0A 80 D6 8A 7E 88 90 85 68 8A 08 43 4F 44 +45 00 B0 12 BE 89 A2 82 C8 21 61 3C AA 85 0E 48 +44 4E 43 4F 44 45 B2 40 C2 8B CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 1A 8A 20 8B +3D 41 92 42 D0 21 CC 21 5D 3C EC 8A 0E 43 4F 44 +45 4E 4E 4D 30 12 F6 8A B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F FE 8A +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 8A 8B B2 40 9C 8B D0 21 +82 4E CE 21 30 40 22 85 85 12 88 8B 88 89 30 89 +1A 8C 2C 8B 82 8A CC 85 76 86 48 89 70 8B C2 8A +9C 8A 38 8A 90 88 A4 8C CE 86 00 00 00 00 85 12 +88 8B 1E 93 A2 91 02 93 CA 90 26 91 74 91 50 92 +5C 92 EC 8F 10 91 00 00 00 00 5E 8B DC 8E 00 00 +78 92 BC 8B B2 40 9C 8B CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 F0 8B 30 4D 02 8C 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 F0 8B +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 +F2 81 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E2 FF 3B 40 10 00 3A 40 3A 18 B0 12 F4 8B 82 43 +4A 18 C7 3F 96 8C B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 7E 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C2 83 14 86 7C 86 AC 80 C2 8C B6 84 +56 88 C4 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 BE 89 +BA 40 85 12 FC FF BA 40 94 8C FE FF 28 83 8A 48 +00 00 BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 14 86 7C 86 AC 80 2E 8D 0E 8D 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +94 8C 00 00 01 20 3E 52 2E 83 21 53 30 41 26 87 +AC 80 36 8D 2A 8D 38 8D B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 FE 8C 15 20 +3E 40 2B 00 B0 12 FE 8C 06 20 3E 40 2D 00 B0 12 +FE 8C 92 83 C6 21 0E 12 1E 41 02 00 84 12 14 86 +26 87 AC 80 5A 89 78 8D 3E 51 3A 17 30 41 B0 12 +3E 8D 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 14 86 +26 87 AC 80 B0 8D A8 8D 3E 90 10 00 E6 2B 7C 2D +B2 8D A2 41 C6 21 E1 3F 03 20 B0 12 96 8D 43 3C +7A 90 23 00 24 20 B0 12 46 8D 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 46 8D F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 92 8D 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 96 8D 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 7E 8D F2 3F 03 20 B0 12 96 8D F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +7E 8D EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 +7E 88 90 85 0A 80 2C 00 74 8E B8 8D C2 83 7E 8E +56 8E C4 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 B4 8E 00 40 D0 8E 0A 4D 4F 56 +2E 42 85 12 B4 8E 40 40 00 00 06 41 44 44 85 12 +B4 8E 00 50 EA 8E 0A 41 44 44 2E 42 85 12 B4 8E +40 50 F6 8E 08 41 44 44 43 00 85 12 B4 8E 00 60 +04 8F 0C 41 44 44 43 2E 42 00 85 12 B4 8E 40 60 +3C 8B 08 53 55 42 43 00 85 12 B4 8E 00 70 22 8F +0C 53 55 42 43 2E 42 00 85 12 B4 8E 40 70 30 8F +06 53 55 42 85 12 B4 8E 00 80 40 8F 0A 53 55 42 +2E 42 85 12 B4 8E 40 80 4C 8F 06 43 4D 50 85 12 +B4 8E 00 90 5A 8F 0A 43 4D 50 2E 42 85 12 B4 8E +40 90 00 00 08 44 41 44 44 00 85 12 B4 8E 00 A0 +74 8F 0C 44 41 44 44 2E 42 00 85 12 B4 8E 40 A0 +A2 8E 06 42 49 54 85 12 B4 8E 00 B0 92 8F 0A 42 +49 54 2E 42 85 12 B4 8E 40 B0 9E 8F 06 42 49 43 +85 12 B4 8E 00 C0 AC 8F 0A 42 49 43 2E 42 85 12 +B4 8E 40 C0 B8 8F 06 42 49 53 85 12 B4 8E 00 D0 +C6 8F 0A 42 49 53 2E 42 85 12 B4 8E 40 D0 00 00 +06 58 4F 52 85 12 B4 8E 00 E0 E0 8F 0A 58 4F 52 +2E 42 85 12 B4 8E 40 E0 12 8F 06 41 4E 44 85 12 +B4 8E 00 F0 FA 8F 0A 41 4E 44 2E 42 85 12 B4 8E +40 F0 C2 83 74 8E B8 8D 1A 90 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F D2 8F 06 52 52 43 +85 12 12 90 00 10 2C 90 0A 52 52 43 2E 42 85 12 +12 90 40 10 66 8F 08 53 57 50 42 00 85 12 12 90 +80 10 38 90 06 52 52 41 85 12 12 90 00 11 54 90 +0A 52 52 41 2E 42 85 12 12 90 40 11 46 90 06 53 +58 54 85 12 12 90 80 11 00 00 08 50 55 53 48 00 +85 12 12 90 00 12 7A 90 0C 50 55 53 48 2E 42 00 +85 12 12 90 40 12 6E 90 08 43 41 4C 4C 00 85 12 +12 90 80 12 1A 53 0E 4A 84 12 04 86 1E 80 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 81 98 90 +06 53 3E 3D 86 12 00 38 C0 90 04 53 3C 00 86 12 +00 34 88 90 06 30 3E 3D 86 12 00 30 D4 90 04 30 +3C 00 86 12 00 30 10 8B 04 55 3C 00 86 12 00 2C +E8 90 06 55 3E 3D 86 12 00 28 DE 90 06 30 3C 3E +86 12 00 24 FC 90 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 82 8F 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D F2 90 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 60 90 0A 42 45 47 49 4E 30 40 +32 80 4A 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +06 90 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 14 91 AA 84 +90 85 68 91 0C 52 45 50 45 41 54 00 0D 12 84 12 +A8 91 2C 91 90 85 D8 91 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D C4 91 +06 42 57 31 85 12 D6 91 00 00 F0 91 06 42 57 32 +85 12 D6 91 00 00 FC 91 06 42 57 33 85 12 D6 91 +00 00 14 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 12 92 +00 00 38 92 06 46 57 32 85 12 12 92 00 00 44 92 +06 46 57 33 85 12 12 92 00 00 B2 91 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +4A 89 56 88 90 85 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 7E 8E 0A 80 2C 00 14 86 26 87 AC 80 +5A 89 C2 83 74 8E 56 8E AA 92 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 08 92 08 52 52 43 4D 00 85 12 +94 92 50 00 D8 92 08 52 52 41 4D 00 85 12 94 92 +50 01 E6 92 08 52 4C 41 4D 00 85 12 94 92 50 02 +F4 92 08 52 52 55 4D 00 85 12 94 92 50 03 06 91 +0A 50 55 53 48 4D 85 12 94 92 00 15 10 93 08 50 +4F 50 4D 00 85 12 94 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 CC 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_24MHz_I2C.txt b/binaries/MSP_EXP430FR2355_24MHz_I2C.txt index aaaec9a..23efc5d 100644 --- a/binaries/MSP_EXP430FR2355_24MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2355_24MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -C0 5D 12 00 00 00 F8 00 F9 FF EE 93 F0 8B 34 01 -10 00 41 87 B6 81 AA 80 B8 81 8C 81 82 82 EE 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +C0 5D 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +C6 82 56 81 56 81 58 81 44 81 06 93 BE 8B 78 8B +78 8B B4 82 38 83 10 83 3C 21 E0 20 6C 85 B6 80 +C4 80 88 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 06 93 BE 8B 78 8B 78 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 02 3D 0E 93 3E 4F +84 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B2 82 B2 49 +36 83 B2 49 0E 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 32 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 92 84 AC 80 +42 81 50 83 1E 80 05 1B 5B 37 6D 40 7C 83 0A 80 +02 18 B4 84 E0 85 7C 83 1E 80 04 1B 5B 30 6D 00 +7C 83 C8 88 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 50 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 7C 83 0A 80 02 18 B4 84 E0 85 0A 80 23 00 +34 83 E0 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7C 83 0A 80 40 FF 32 80 A8 84 AC 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 43 22 02 F2 D3 47 02 F2 40 +BF 00 43 02 F2 40 A5 00 A1 01 F2 40 20 00 A0 01 +D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 F2 D0 +C0 00 0D 02 F2 C3 82 01 F2 D0 0E 00 82 01 B2 40 +DC 02 84 01 39 40 5C 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 +B0 12 D0 80 80 81 00 00 0C 41 43 43 45 50 54 00 +30 40 B4 82 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 9D 3E 21 52 A2 C2 6C 05 B2 B0 10 00 +40 05 96 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 10 83 +58 43 B0 12 46 81 2F 83 8F 4E 00 00 92 B3 6C 05 +FD 27 1E 42 4C 05 B0 12 44 81 30 4D 00 00 08 45 +4D 49 54 00 30 40 38 83 08 4E 3E 4F A2 B3 6C 05 +FD 27 C2 48 4E 05 30 4D 2E 83 08 45 43 48 4F 00 +B2 40 C2 48 42 83 38 40 05 00 B0 12 46 81 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 42 83 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +8C 83 29 4F 8F 4E 00 00 7E 49 D4 3F 8E 83 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 82 22 F9 98 +00 00 7F 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 76 22 9B 24 08 83 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 80 00 00 AC 84 9E 83 F0 85 +AA 88 B0 80 1A 84 14 80 06 5B 54 48 45 4E 5D 00 +A2 83 F8 83 BE 83 DC 83 14 80 06 5B 45 4C 53 45 +5D 00 A2 83 0A 84 BE 83 DA 83 1E 80 04 5B 49 46 +5D 00 A2 83 DC 83 B2 80 DA 83 1E 80 05 0D 6B 6F +20 0A 7C 83 9A 80 84 80 B2 80 DC 83 CA 83 0D 5B +54 48 45 4E 5D 00 30 4D 2E 84 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 3A 84 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 9E 83 F0 85 58 86 FC 87 +6C 85 4A 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 9E 83 F0 85 58 86 7C 84 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D A8 82 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 81 05 53 22 00 82 43 C0 21 0D 12 +84 12 0A 80 1E 80 5A 88 0A 80 22 00 F0 85 F0 84 +B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F +3D 41 30 4D 62 83 05 2E 22 00 0D 12 84 12 DA 84 +0A 80 7C 83 5A 88 6C 85 00 00 04 3C 23 00 B2 40 +B2 21 B2 21 30 4D D6 84 02 23 1B 42 BE 21 2C 4F +2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -64 92 CA 92 0C 92 1A 93 D2 91 00 00 9E 8F 00 00 -E2 93 C6 93 36 92 74 92 AE 90 00 00 00 00 36 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C EE 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 43 22 02 -F2 D3 47 02 F2 40 BF 00 43 02 F2 40 A5 00 A1 01 -F2 40 20 00 A0 01 D2 43 A1 01 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 BE 00 82 01 B2 40 DC 02 -84 01 82 43 88 01 F2 D0 C0 00 0D 02 39 40 5C 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 80 FE 81 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A 85 82 85 -DE 83 34 80 DE 8D 3E 86 34 80 F8 8D F2 8D E0 8D -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 FA 8D B2 41 C4 21 3E 41 -84 12 0A 80 2B 00 1A 85 82 85 DE 83 34 80 16 8E -3E 86 34 80 00 88 A8 83 1A 85 3E 86 34 80 00 88 -22 8E 3E 5F E7 3F 3E 40 28 00 B0 12 C2 8D 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 6E 89 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A 85 3E 86 34 80 6A 8E 60 8E -21 53 3E 90 10 00 C6 2B 7F 2D 6C 8E B2 41 C4 21 -C1 3F 0D 12 84 12 02 88 9E 8D 7C 8E 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 C2 8D 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 C2 8D -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 4A 8E 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -4A 8E 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 4A 8E FA 23 3C 50 10 00 B0 12 -26 8E EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 02 88 9E 8D 48 8F FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 4A 8E E0 23 -3C 50 80 00 B0 12 26 8E DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 80 00 13 48 87 4E 84 0A 80 -2C 00 72 8E 3E 8F 88 8F 09 4B 2E 4E 0E DC A2 3F -40 8A 03 4D 4F 56 85 12 7E 8F 00 40 92 8F 05 4D -4F 56 2E 42 85 12 7E 8F 40 40 00 00 03 41 44 44 -85 12 7E 8F 00 50 AC 8F 05 41 44 44 2E 42 85 12 -7E 8F 40 50 B8 8F 04 41 44 44 43 00 85 12 7E 8F -00 60 C6 8F 06 41 44 44 43 2E 42 00 85 12 7E 8F -40 60 6C 8F 04 53 55 42 43 00 85 12 7E 8F 00 70 -E4 8F 06 53 55 42 43 2E 42 00 85 12 7E 8F 40 70 -F2 8F 03 53 55 42 85 12 7E 8F 00 80 02 90 05 53 -55 42 2E 42 85 12 7E 8F 40 80 16 8A 03 43 4D 50 -85 12 7E 8F 00 90 1C 90 05 43 4D 50 2E 42 85 12 -7E 8F 40 90 00 8A 04 44 41 44 44 00 85 12 7E 8F -00 A0 36 90 06 44 41 44 44 2E 42 00 85 12 7E 8F -40 A0 28 90 03 42 49 54 85 12 7E 8F 00 B0 54 90 -05 42 49 54 2E 42 85 12 7E 8F 40 B0 60 90 03 42 -49 43 85 12 7E 8F 00 C0 6E 90 05 42 49 43 2E 42 -85 12 7E 8F 40 C0 7A 90 03 42 49 53 85 12 7E 8F -00 D0 88 90 05 42 49 53 2E 42 85 12 7E 8F 40 D0 -00 00 03 58 4F 52 85 12 7E 8F 00 E0 A2 90 05 58 -4F 52 2E 42 85 12 7E 8F 40 E0 D4 8F 03 41 4E 44 -85 12 7E 8F 00 F0 BC 90 05 41 4E 44 2E 42 85 12 -7E 8F 40 F0 02 88 72 8E DA 90 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 0E 90 03 52 52 43 -85 12 D4 90 00 10 EC 90 05 52 52 43 2E 42 85 12 -D4 90 40 10 F8 90 04 53 57 50 42 00 85 12 D4 90 -80 10 06 91 03 52 52 41 85 12 D4 90 00 11 14 91 -05 52 52 41 2E 42 85 12 D4 90 40 11 20 91 03 53 -58 54 85 12 D4 90 80 11 00 00 04 50 55 53 48 00 -85 12 D4 90 00 12 3A 91 06 50 55 53 48 2E 42 00 -85 12 D4 90 40 12 94 90 04 43 41 4C 4C 00 85 12 -D4 90 80 12 1A 53 0E 4A 0D 12 84 12 C4 84 14 80 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 81 -2E 91 03 53 3E 3D 86 12 00 38 82 91 02 53 3C 00 -86 12 00 34 48 91 03 30 3E 3D 86 12 00 30 96 91 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C AA 91 03 55 3E 3D 86 12 00 28 A0 91 03 30 -3C 3E 86 12 00 24 BE 91 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D B4 91 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 44 90 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 58 91 05 42 45 47 49 4E -30 40 28 80 E8 91 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D C8 90 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 D6 91 -A8 83 4E 84 8C 91 06 52 45 50 45 41 54 00 0D 12 -84 12 6A 92 EE 91 4E 84 9A 92 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -2A 92 03 42 57 31 85 12 98 92 00 00 B2 92 03 42 -57 32 85 12 98 92 00 00 BE 92 03 42 57 33 85 12 -98 92 00 00 D6 92 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 D4 92 00 00 -F6 92 03 46 57 32 85 12 D4 92 00 00 02 93 03 46 -57 33 85 12 D4 92 00 00 0E 93 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 88 -DC 87 4E 84 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 02 88 9E 8D 58 93 92 53 C4 21 3E 40 2C 00 -84 12 1A 85 3E 86 34 80 00 88 34 8F 6E 93 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 86 92 04 52 52 43 -4D 00 85 12 52 93 50 00 9C 93 04 52 52 41 4D 00 -85 12 52 93 50 01 AA 93 04 52 4C 41 4D 00 85 12 -52 93 50 02 B8 93 04 52 52 55 4D 00 85 12 52 93 -50 03 C8 91 05 50 55 53 48 4D 85 12 52 93 00 15 -D4 93 04 50 4F 50 4D 00 85 12 52 93 00 17 +C8 4A 00 00 30 4D 28 85 04 23 53 00 0D 12 84 12 +2A 85 64 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +58 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 72 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 4A 83 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 1E 85 9E 83 8C 85 +5C 85 88 84 9A 85 76 85 7C 83 6C 85 06 85 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 +82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D DE 85 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 62 87 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 64 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +1A 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 80 9E 83 F0 85 B0 80 34 89 58 86 1E 88 0A 4E +3E 4F 3D 40 38 88 6D 27 3D 40 12 88 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 3A 88 3E 4F 3D 40 12 88 +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 10 8A 2A 3C 02 88 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 58 88 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 94 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D BA 84 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E 80 02 0D 0A 00 7C 83 94 80 0C 88 9A 84 C4 84 +1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 +32 80 0A 80 40 FF CC 84 1E 80 09 46 52 41 4D 20 +66 75 6C 6C 08 81 B2 80 D0 88 BA 88 0D 41 42 4F +52 54 22 00 0D 12 84 12 DA 84 0A 80 08 81 5A 88 +6C 85 EA 85 02 27 0D 12 84 12 9E 83 F0 85 58 86 +B0 80 36 89 FE 84 42 88 64 84 07 5B 27 5D 0D 12 +84 12 26 89 0A 80 0A 80 5A 88 5A 88 6C 85 3A 89 +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D B2 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 9E 83 F0 85 58 86 B0 80 36 89 C4 84 AC 80 +8E 89 0A 80 0A 80 5A 88 5A 88 0A 80 5A 88 5A 88 +6C 85 00 00 02 3A 30 12 E4 89 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 9E 83 F0 85 AC 89 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 81 50 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A 80 6C 85 5A 88 F6 89 52 89 6C 85 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D A4 88 0C 43 52 45 41 54 45 00 B0 12 9A 89 +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 76 83 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 94 89 0E 3A 4E 4F 4E 41 4D 45 +30 12 E4 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 2E 8A 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 26 89 B0 8A +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 3E 89 0A 80 +B2 8A 5A 88 6C 85 44 8A 08 43 4F 44 45 00 B0 12 +9A 89 A2 82 C8 21 61 3C 86 85 0E 48 44 4E 43 4F +44 45 B2 40 9E 8B CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 F6 89 FC 8A 3D 41 92 42 +D0 21 CC 21 5D 3C C8 8A 0E 43 4F 44 45 4E 4E 4D +30 12 D2 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F DA 8A 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F 66 8B B2 40 78 8B D0 21 82 4E CE 21 +30 40 FE 84 85 12 64 8B 64 89 0C 89 F6 8B 08 8B +5E 8A A8 85 52 86 24 89 4C 8B 9E 8A 78 8A 14 8A +6C 88 80 8C AA 86 00 00 00 00 85 12 64 8B FA 92 +7E 91 DE 92 A6 90 02 91 50 91 2C 92 38 92 C8 8F +EC 90 00 00 00 00 3A 8B B8 8E 00 00 54 92 98 8B +B2 40 78 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +CC 8B 30 4D DE 8B 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 CC 8B 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E 82 FE FF 29 83 B9 40 FA 81 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 D0 8B 82 43 4A 18 C7 3F +72 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 5A 89 +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +9E 83 F0 85 58 86 AC 80 9E 8C 92 84 32 88 A0 8C +3E 4F 3D 41 B2 41 C6 21 B0 12 9A 89 BA 40 85 12 +FC FF BA 40 70 8C FE FF 28 83 8A 48 00 00 BA 40 +82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +F0 85 58 86 AC 80 0A 8D EA 8C 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 70 8C 00 00 +01 20 3E 52 2E 83 21 53 30 41 02 87 AC 80 12 8D +06 8D 14 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 DA 8C 15 20 3E 40 2B 00 +B0 12 DA 8C 06 20 3E 40 2D 00 B0 12 DA 8C 92 83 +C6 21 0E 12 1E 41 02 00 84 12 F0 85 02 87 AC 80 +36 89 54 8D 3E 51 3A 17 30 41 B0 12 1A 8D 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 F0 85 02 87 AC 80 +8C 8D 84 8D 3E 90 10 00 E6 2B 7C 2D 8E 8D A2 41 +C6 21 E1 3F 03 20 B0 12 72 8D 43 3C 7A 90 23 00 +24 20 B0 12 22 8D 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 22 8D F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 6E 8D 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 72 8D 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 5A 8D +F2 3F 03 20 B0 12 72 8D F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 5A 8D EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 80 00 13 5A 88 6C 85 +0A 80 2C 00 50 8E 94 8D 9E 83 5A 8E 32 8E A0 8E +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 90 8E 00 40 AC 8E 0A 4D 4F 56 2E 42 85 12 +90 8E 40 40 00 00 06 41 44 44 85 12 90 8E 00 50 +C6 8E 0A 41 44 44 2E 42 85 12 90 8E 40 50 D2 8E +08 41 44 44 43 00 85 12 90 8E 00 60 E0 8E 0C 41 +44 44 43 2E 42 00 85 12 90 8E 40 60 18 8B 08 53 +55 42 43 00 85 12 90 8E 00 70 FE 8E 0C 53 55 42 +43 2E 42 00 85 12 90 8E 40 70 0C 8F 06 53 55 42 +85 12 90 8E 00 80 1C 8F 0A 53 55 42 2E 42 85 12 +90 8E 40 80 28 8F 06 43 4D 50 85 12 90 8E 00 90 +36 8F 0A 43 4D 50 2E 42 85 12 90 8E 40 90 00 00 +08 44 41 44 44 00 85 12 90 8E 00 A0 50 8F 0C 44 +41 44 44 2E 42 00 85 12 90 8E 40 A0 7E 8E 06 42 +49 54 85 12 90 8E 00 B0 6E 8F 0A 42 49 54 2E 42 +85 12 90 8E 40 B0 7A 8F 06 42 49 43 85 12 90 8E +00 C0 88 8F 0A 42 49 43 2E 42 85 12 90 8E 40 C0 +94 8F 06 42 49 53 85 12 90 8E 00 D0 A2 8F 0A 42 +49 53 2E 42 85 12 90 8E 40 D0 00 00 06 58 4F 52 +85 12 90 8E 00 E0 BC 8F 0A 58 4F 52 2E 42 85 12 +90 8E 40 E0 EE 8E 06 41 4E 44 85 12 90 8E 00 F0 +D6 8F 0A 41 4E 44 2E 42 85 12 90 8E 40 F0 9E 83 +50 8E 94 8D F6 8F 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F AE 8F 06 52 52 43 85 12 EE 8F +00 10 08 90 0A 52 52 43 2E 42 85 12 EE 8F 40 10 +42 8F 08 53 57 50 42 00 85 12 EE 8F 80 10 14 90 +06 52 52 41 85 12 EE 8F 00 11 30 90 0A 52 52 41 +2E 42 85 12 EE 8F 40 11 22 90 06 53 58 54 85 12 +EE 8F 80 11 00 00 08 50 55 53 48 00 85 12 EE 8F +00 12 56 90 0C 50 55 53 48 2E 42 00 85 12 EE 8F +40 12 4A 90 08 43 41 4C 4C 00 85 12 EE 8F 80 12 +1A 53 0E 4A 84 12 E0 85 1E 80 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 81 74 90 06 53 3E 3D +86 12 00 38 9C 90 04 53 3C 00 86 12 00 34 64 90 +06 30 3E 3D 86 12 00 30 B0 90 04 30 3C 00 86 12 +00 30 EC 8A 04 55 3C 00 86 12 00 2C C4 90 06 55 +3E 3D 86 12 00 28 BA 90 06 30 3C 3E 86 12 00 24 +D8 90 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +5E 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D CE 90 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 3C 90 0A 42 45 47 49 4E 30 40 32 80 26 91 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D E2 8F 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 F0 90 86 84 6C 85 44 91 +0C 52 45 50 45 41 54 00 0D 12 84 12 84 91 08 91 +6C 85 B4 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D A0 91 06 42 57 31 +85 12 B2 91 00 00 CC 91 06 42 57 32 85 12 B2 91 +00 00 D8 91 06 42 57 33 85 12 B2 91 00 00 F0 91 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 EE 91 00 00 14 92 +06 46 57 32 85 12 EE 91 00 00 20 92 06 46 57 33 +85 12 EE 91 00 00 8E 91 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 26 89 32 88 +6C 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +5A 8E 0A 80 2C 00 F0 85 02 87 AC 80 36 89 9E 83 +50 8E 32 8E 86 92 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E E4 91 08 52 52 43 4D 00 85 12 70 92 50 00 +B4 92 08 52 52 41 4D 00 85 12 70 92 50 01 C2 92 +08 52 4C 41 4D 00 85 12 70 92 50 02 D0 92 08 52 +52 55 4D 00 85 12 70 92 50 03 E2 90 0A 50 55 53 +48 4D 85 12 70 92 00 15 EC 92 08 50 4F 50 4D 00 +85 12 70 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -82 82 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +C6 82 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/MSP_EXP430FR2355_24MHz_UART.txt b/binaries/MSP_EXP430FR2355_24MHz_UART.txt deleted file mode 100644 index 869679f..0000000 --- a/binaries/MSP_EXP430FR2355_24MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -C0 5D 0D 00 01 49 18 00 F9 FF 04 94 02 8C 34 01 -10 00 41 B3 94 81 AA 80 DA 81 9C 81 94 82 04 94 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 9C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -9C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 8A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 80 05 92 42 02 18 86 05 92 42 04 18 -88 05 F2 D0 0C 00 2B 02 92 C3 80 05 92 D3 9A 05 -92 C3 30 01 30 41 09 3C A2 B3 9C 05 FD 27 B2 40 -13 00 8E 05 D2 D3 03 02 30 41 A2 B3 9C 05 FD 27 -B2 40 11 00 8E 05 D2 C3 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 8C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 9C 05 FD 27 -C2 48 8E 05 30 4D C8 82 2D 83 92 B3 9C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 9C 05 -FD 27 58 42 8C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 9C 05 FD 27 1E 42 -8C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 7A 92 E0 92 22 92 30 93 E8 91 00 00 B4 8F -00 00 F8 93 DC 93 4C 92 8A 92 C4 90 00 00 00 00 -4C 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -04 94 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E2 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 -26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 -F2 40 A5 00 A1 01 F2 40 20 00 A0 01 D2 43 A1 01 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 BE 00 -82 01 B2 40 DC 02 84 01 82 43 88 01 F2 D0 C0 00 -0D 02 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 80 1E 82 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C 85 94 85 F0 83 34 80 F4 8D 50 86 34 80 -0E 8E 08 8E F6 8D 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 10 8E -B2 41 C4 21 3E 41 84 12 0A 80 2B 00 2C 85 94 85 -F0 83 34 80 2C 8E 50 86 34 80 12 88 BA 83 2C 85 -50 86 34 80 12 88 38 8E 3E 5F E7 3F 3E 40 28 00 -B0 12 D8 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 80 89 -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C 85 50 86 -34 80 80 8E 76 8E 21 53 3E 90 10 00 C6 2B 7F 2D -82 8E B2 41 C4 21 C1 3F 0D 12 84 12 14 88 B4 8D -92 8E 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 D8 8D 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 D8 8D ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 60 8E 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 60 8E 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 60 8E FA 23 -3C 50 10 00 B0 12 3C 8E EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 14 88 B4 8D 5E 8F FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 60 8E E0 23 3C 50 80 00 B0 12 3C 8E DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 -5A 87 60 84 0A 80 2C 00 88 8E 54 8F 9E 8F 09 4B -2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 85 12 94 8F -00 40 A8 8F 05 4D 4F 56 2E 42 85 12 94 8F 40 40 -00 00 03 41 44 44 85 12 94 8F 00 50 C2 8F 05 41 -44 44 2E 42 85 12 94 8F 40 50 CE 8F 04 41 44 44 -43 00 85 12 94 8F 00 60 DC 8F 06 41 44 44 43 2E -42 00 85 12 94 8F 40 60 82 8F 04 53 55 42 43 00 -85 12 94 8F 00 70 FA 8F 06 53 55 42 43 2E 42 00 -85 12 94 8F 40 70 08 90 03 53 55 42 85 12 94 8F -00 80 18 90 05 53 55 42 2E 42 85 12 94 8F 40 80 -28 8A 03 43 4D 50 85 12 94 8F 00 90 32 90 05 43 -4D 50 2E 42 85 12 94 8F 40 90 12 8A 04 44 41 44 -44 00 85 12 94 8F 00 A0 4C 90 06 44 41 44 44 2E -42 00 85 12 94 8F 40 A0 3E 90 03 42 49 54 85 12 -94 8F 00 B0 6A 90 05 42 49 54 2E 42 85 12 94 8F -40 B0 76 90 03 42 49 43 85 12 94 8F 00 C0 84 90 -05 42 49 43 2E 42 85 12 94 8F 40 C0 90 90 03 42 -49 53 85 12 94 8F 00 D0 9E 90 05 42 49 53 2E 42 -85 12 94 8F 40 D0 00 00 03 58 4F 52 85 12 94 8F -00 E0 B8 90 05 58 4F 52 2E 42 85 12 94 8F 40 E0 -EA 8F 03 41 4E 44 85 12 94 8F 00 F0 D2 90 05 41 -4E 44 2E 42 85 12 94 8F 40 F0 14 88 88 8E F0 90 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -24 90 03 52 52 43 85 12 EA 90 00 10 02 91 05 52 -52 43 2E 42 85 12 EA 90 40 10 0E 91 04 53 57 50 -42 00 85 12 EA 90 80 10 1C 91 03 52 52 41 85 12 -EA 90 00 11 2A 91 05 52 52 41 2E 42 85 12 EA 90 -40 11 36 91 03 53 58 54 85 12 EA 90 80 11 00 00 -04 50 55 53 48 00 85 12 EA 90 00 12 50 91 06 50 -55 53 48 2E 42 00 85 12 EA 90 40 12 AA 90 04 43 -41 4C 4C 00 85 12 EA 90 80 12 1A 53 0E 4A 0D 12 -84 12 D6 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 81 44 91 03 53 3E 3D 86 12 00 38 -98 91 02 53 3C 00 86 12 00 34 5E 91 03 30 3E 3D -86 12 00 30 AC 91 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C C0 91 03 55 3E 3D 86 12 -00 28 B6 91 03 30 3C 3E 86 12 00 24 D4 91 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D CA 91 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -5A 90 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 6E 91 -05 42 45 47 49 4E 30 40 28 80 FE 91 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D DE 90 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 EC 91 BA 83 60 84 A2 91 06 52 45 50 -45 41 54 00 0D 12 84 12 80 92 04 92 60 84 B0 92 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 40 92 03 42 57 31 85 12 AE 92 -00 00 C8 92 03 42 57 32 85 12 AE 92 00 00 D4 92 -03 42 57 33 85 12 AE 92 00 00 EC 92 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 EA 92 00 00 0C 93 03 46 57 32 85 12 EA 92 -00 00 18 93 03 46 57 33 85 12 EA 92 00 00 24 93 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 92 88 EE 87 60 84 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 14 88 B4 8D 6E 93 92 53 -C4 21 3E 40 2C 00 84 12 2C 85 50 86 34 80 12 88 -4A 8F 84 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -9C 92 04 52 52 43 4D 00 85 12 68 93 50 00 B2 93 -04 52 52 41 4D 00 85 12 68 93 50 01 C0 93 04 52 -4C 41 4D 00 85 12 68 93 50 02 CE 93 04 52 52 55 -4D 00 85 12 68 93 50 03 DE 91 05 50 55 53 48 4D -85 12 68 93 00 15 EA 93 04 50 4F 50 4D 00 85 12 -68 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 94 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/MSP_EXP430FR2355_8MHz_115200.txt b/binaries/MSP_EXP430FR2355_8MHz_115200.txt new file mode 100644 index 0000000..625dfb5 --- /dev/null +++ b/binaries/MSP_EXP430FR2355_8MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 59 +BC 82 7E 81 84 81 54 81 2C 83 1A 93 D2 8B 8C 8B +8C 8B A2 82 60 83 28 83 3C 21 E0 20 80 85 B6 80 +C4 80 9C 84 20 00 0A 00 00 20 7E 81 84 81 54 81 +2C 83 1A 93 D2 8B 8C 8B 8C 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@8000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F9 3C 0E 93 3E 4F +8E 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A0 82 B2 49 +5E 83 B2 49 26 83 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 46 8C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 2C 83 92 C3 9C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 9C 05 F3 23 +B0 12 D0 80 A6 84 AC 80 52 81 6E 83 1E 80 04 1B +5B 37 6D 00 90 83 90 83 1E 80 04 1B 5B 30 6D 00 +90 83 DC 88 B0 12 7E 81 B2 40 81 00 80 05 92 42 +02 18 86 05 92 42 04 18 88 05 F2 D0 0C 00 2B 02 +92 C3 80 05 92 D3 9A 05 92 C3 30 01 30 41 92 B3 +8A 05 FD 23 30 41 92 12 3E 18 84 12 6E 83 1E 80 +07 0D 0A 1B 5B 37 6D 23 90 83 F4 85 1E 80 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 90 83 0A 80 40 FF 32 80 +BC 84 C0 85 1E 80 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 80 46 81 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 81 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 +26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 +B2 40 00 A5 60 01 82 43 88 01 F2 D0 C0 00 0D 02 +F2 C3 82 01 F2 D0 06 00 82 01 B2 40 F4 00 84 01 +39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 80 86 81 00 00 0C 41 43 43 45 50 54 00 30 40 +A2 82 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 00 83 3C 40 0C 83 5D 15 A2 3E 21 52 3A 17 +58 42 8C 05 48 9B 09 20 A2 B3 9C 05 FD 27 B2 40 +13 00 8E 05 D2 D3 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 9C 05 FD 27 C2 48 8E 05 30 4D +02 83 2D 83 92 B3 9C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 9C 05 FD 27 58 42 8C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 28 83 30 12 3E 83 A2 B3 9C 05 +FD 27 B2 40 11 00 8E 05 D2 C3 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 9C 05 FD 27 B0 12 C8 82 1E 42 +8C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 60 83 +08 4E 3E 4F C7 3F 56 83 08 45 43 48 4F 00 B2 40 +C2 48 FA 82 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D FA 82 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 A0 83 29 4F 8F 4E 00 00 7E 49 DE 3F +A2 83 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +78 22 F9 98 00 00 75 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 6C 22 9B 24 20 83 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 80 00 00 C0 84 +B2 83 04 86 BE 88 B0 80 2E 84 14 80 06 5B 54 48 +45 4E 5D 00 B6 83 0C 84 D2 83 F0 83 14 80 06 5B +45 4C 53 45 5D 00 B6 83 1E 84 D2 83 EE 83 1E 80 +04 5B 49 46 5D 00 B6 83 F0 83 B2 80 EE 83 1E 80 +05 0D 6B 6F 20 0A 90 83 9A 80 84 80 B2 80 F0 83 +DE 83 0D 5B 54 48 45 4E 5D 00 30 4D 42 84 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 4E 84 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 B2 83 04 86 +6C 86 10 88 80 85 5E 84 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 B2 83 04 86 6C 86 90 84 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D 96 82 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 81 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A 80 1E 80 6E 88 0A 80 22 00 +04 86 04 85 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 78 83 05 2E 22 00 0D 12 +84 12 EE 84 0A 80 90 83 6E 88 80 85 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D EA 84 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 80 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 3C 85 04 23 53 00 +0D 12 84 12 3E 85 78 85 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 6C 85 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 86 85 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 68 83 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 32 85 +B2 83 A0 85 70 85 9C 84 AE 85 8A 85 90 83 80 85 +1A 85 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D F2 85 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +76 87 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 78 87 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 2E 85 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 80 B2 83 04 86 B0 80 48 89 6C 86 +32 88 0A 4E 3E 4F 3D 40 4C 88 6D 27 3D 40 26 88 +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 4E 88 3E 4F +3D 40 26 88 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 24 8A 2A 3C 16 88 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 6C 88 +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A 80 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D A8 85 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D CE 84 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E 80 02 0D 0A 00 90 83 94 80 20 88 +AE 84 D8 84 1E 80 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 81 32 80 0A 80 40 FF E0 84 1E 80 09 46 +52 41 4D 20 66 75 6C 6C 08 81 B2 80 E4 88 CE 88 +0D 41 42 4F 52 54 22 00 0D 12 84 12 EE 84 0A 80 +08 81 6E 88 80 85 FE 85 02 27 0D 12 84 12 B2 83 +04 86 6C 86 B0 80 4A 89 12 85 56 88 78 84 07 5B +27 5D 0D 12 84 12 3A 89 0A 80 0A 80 6E 88 6E 88 +80 85 4E 89 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D C6 84 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 B2 83 04 86 6C 86 B0 80 4A 89 +D8 84 AC 80 A2 89 0A 80 0A 80 6E 88 6E 88 0A 80 +6E 88 6E 88 80 85 00 00 02 3A 30 12 F8 89 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 B2 83 04 86 C0 89 +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 81 64 89 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A 80 80 85 6E 88 0A 8A 66 89 80 85 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D B8 88 0C 43 52 45 41 54 45 00 +B0 12 AE 89 BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +8A 83 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D A8 89 0E 3A 4E 4F +4E 41 4D 45 30 12 F8 89 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +42 8A 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +3A 89 C4 8A 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +52 89 0A 80 C6 8A 6E 88 80 85 58 8A 08 43 4F 44 +45 00 B0 12 AE 89 A2 82 C8 21 61 3C 9A 85 0E 48 +44 4E 43 4F 44 45 B2 40 B2 8B CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 0A 8A 10 8B +3D 41 92 42 D0 21 CC 21 5D 3C DC 8A 0E 43 4F 44 +45 4E 4E 4D 30 12 E6 8A B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F EE 8A +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 7A 8B B2 40 8C 8B D0 21 +82 4E CE 21 30 40 12 85 85 12 78 8B 78 89 20 89 +0A 8C 1C 8B 72 8A BC 85 66 86 38 89 60 8B B2 8A +8C 8A 28 8A 80 88 94 8C BE 86 00 00 00 00 85 12 +78 8B 0E 93 92 91 F2 92 BA 90 16 91 64 91 40 92 +4C 92 DC 8F 00 91 00 00 00 00 4E 8B CC 8E 00 00 +68 92 AC 8B B2 40 8C 8B CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 E0 8B 30 4D F2 8B 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 E0 8B +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 82 FE FF 29 83 B9 40 +F2 81 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E2 FF 3B 40 10 00 3A 40 3A 18 B0 12 E4 8B 82 43 +4A 18 C7 3F 86 8C B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 6E 89 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 B2 83 04 86 6C 86 AC 80 B2 8C A6 84 +46 88 B4 8C 3E 4F 3D 41 B2 41 C6 21 B0 12 AE 89 +BA 40 85 12 FC FF BA 40 84 8C FE FF 28 83 8A 48 +00 00 BA 40 82 80 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 04 86 6C 86 AC 80 1E 8D FE 8C 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +84 8C 00 00 01 20 3E 52 2E 83 21 53 30 41 16 87 +AC 80 26 8D 1A 8D 28 8D B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 EE 8C 15 20 +3E 40 2B 00 B0 12 EE 8C 06 20 3E 40 2D 00 B0 12 +EE 8C 92 83 C6 21 0E 12 1E 41 02 00 84 12 04 86 +16 87 AC 80 4A 89 68 8D 3E 51 3A 17 30 41 B0 12 +2E 8D 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 04 86 +16 87 AC 80 A0 8D 98 8D 3E 90 10 00 E6 2B 7C 2D +A2 8D A2 41 C6 21 E1 3F 03 20 B0 12 86 8D 43 3C +7A 90 23 00 24 20 B0 12 36 8D 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 36 8D F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 82 8D 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 86 8D 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 6E 8D F2 3F 03 20 B0 12 86 8D F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +6E 8D EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 80 00 13 +6E 88 80 85 0A 80 2C 00 64 8E A8 8D B2 83 6E 8E +46 8E B4 8E 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 A4 8E 00 40 C0 8E 0A 4D 4F 56 +2E 42 85 12 A4 8E 40 40 00 00 06 41 44 44 85 12 +A4 8E 00 50 DA 8E 0A 41 44 44 2E 42 85 12 A4 8E +40 50 E6 8E 08 41 44 44 43 00 85 12 A4 8E 00 60 +F4 8E 0C 41 44 44 43 2E 42 00 85 12 A4 8E 40 60 +2C 8B 08 53 55 42 43 00 85 12 A4 8E 00 70 12 8F +0C 53 55 42 43 2E 42 00 85 12 A4 8E 40 70 20 8F +06 53 55 42 85 12 A4 8E 00 80 30 8F 0A 53 55 42 +2E 42 85 12 A4 8E 40 80 3C 8F 06 43 4D 50 85 12 +A4 8E 00 90 4A 8F 0A 43 4D 50 2E 42 85 12 A4 8E +40 90 00 00 08 44 41 44 44 00 85 12 A4 8E 00 A0 +64 8F 0C 44 41 44 44 2E 42 00 85 12 A4 8E 40 A0 +92 8E 06 42 49 54 85 12 A4 8E 00 B0 82 8F 0A 42 +49 54 2E 42 85 12 A4 8E 40 B0 8E 8F 06 42 49 43 +85 12 A4 8E 00 C0 9C 8F 0A 42 49 43 2E 42 85 12 +A4 8E 40 C0 A8 8F 06 42 49 53 85 12 A4 8E 00 D0 +B6 8F 0A 42 49 53 2E 42 85 12 A4 8E 40 D0 00 00 +06 58 4F 52 85 12 A4 8E 00 E0 D0 8F 0A 58 4F 52 +2E 42 85 12 A4 8E 40 E0 02 8F 06 41 4E 44 85 12 +A4 8E 00 F0 EA 8F 0A 41 4E 44 2E 42 85 12 A4 8E +40 F0 B2 83 64 8E A8 8D 0A 90 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F C2 8F 06 52 52 43 +85 12 02 90 00 10 1C 90 0A 52 52 43 2E 42 85 12 +02 90 40 10 56 8F 08 53 57 50 42 00 85 12 02 90 +80 10 28 90 06 52 52 41 85 12 02 90 00 11 44 90 +0A 52 52 41 2E 42 85 12 02 90 40 11 36 90 06 53 +58 54 85 12 02 90 80 11 00 00 08 50 55 53 48 00 +85 12 02 90 00 12 6A 90 0C 50 55 53 48 2E 42 00 +85 12 02 90 40 12 5E 90 08 43 41 4C 4C 00 85 12 +02 90 80 12 1A 53 0E 4A 84 12 F4 85 1E 80 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 81 88 90 +06 53 3E 3D 86 12 00 38 B0 90 04 53 3C 00 86 12 +00 34 78 90 06 30 3E 3D 86 12 00 30 C4 90 04 30 +3C 00 86 12 00 30 00 8B 04 55 3C 00 86 12 00 2C +D8 90 06 55 3E 3D 86 12 00 28 CE 90 06 30 3C 3E +86 12 00 24 EC 90 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 72 8F 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D E2 90 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 50 90 0A 42 45 47 49 4E 30 40 +32 80 3A 91 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +F6 8F 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 04 91 9A 84 +80 85 58 91 0C 52 45 50 45 41 54 00 0D 12 84 12 +98 91 1C 91 80 85 C8 91 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D B4 91 +06 42 57 31 85 12 C6 91 00 00 E0 91 06 42 57 32 +85 12 C6 91 00 00 EC 91 06 42 57 33 85 12 C6 91 +00 00 04 92 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 02 92 +00 00 28 92 06 46 57 32 85 12 02 92 00 00 34 92 +06 46 57 33 85 12 02 92 00 00 A2 91 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +3A 89 46 88 80 85 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 6E 8E 0A 80 2C 00 04 86 16 87 AC 80 +4A 89 B2 83 64 8E 46 8E 9A 92 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E F8 91 08 52 52 43 4D 00 85 12 +84 92 50 00 C8 92 08 52 52 41 4D 00 85 12 84 92 +50 01 D6 92 08 52 4C 41 4D 00 85 12 84 92 50 02 +E4 92 08 52 52 55 4D 00 85 12 84 92 50 03 F6 90 +0A 50 55 53 48 4D 85 12 84 92 00 15 00 93 08 50 +4F 50 4D 00 85 12 84 92 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 BC 82 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 +F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 F2 81 06 82 +q diff --git a/binaries/MSP_EXP430FR2355_8MHz_I2C.txt b/binaries/MSP_EXP430FR2355_8MHz_I2C.txt index 09d9f81..c98de54 100644 --- a/binaries/MSP_EXP430FR2355_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2355_8MHz_I2C.txt @@ -1,334 +1,322 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF DE 93 F0 8B 34 01 -10 00 41 87 B6 81 AA 80 B8 81 8C 81 82 82 DE 93 -F0 8B 70 82 80 83 FE 82 DA 82 3C 21 4E 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +B6 82 56 81 56 81 58 81 44 81 F6 92 AE 8B 68 8B +68 8B A4 82 28 83 00 83 3C 21 E0 20 5C 85 B6 80 +C4 80 78 84 20 00 0A 00 00 20 56 81 56 81 58 81 +44 81 F6 92 AE 8B 68 8B 68 8B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @8000 -B0 12 B8 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 6E 82 B2 49 7E 83 B2 49 FC 82 B2 49 D8 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 81 0E 12 B0 12 -F8 80 0A 80 DE 21 CE 83 16 83 EE 80 34 80 8A 81 -14 80 05 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 -C4 84 96 83 34 80 7E 81 14 80 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 83 8E 84 4A 83 -14 80 04 1B 5B 30 6D 00 4A 83 16 88 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 81 04 57 41 52 4D 00 B0 12 -8C 81 78 40 03 00 B0 12 BA 81 84 12 14 80 07 0D -0A 1B 5B 37 6D 40 4A 83 0A 80 02 18 CE 83 C4 84 -0A 80 23 00 FA 82 C4 84 14 80 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 83 0A 80 40 FF 28 80 C2 83 8E 84 -14 80 0A 62 79 74 65 73 20 66 72 65 65 00 3A 80 -7E 81 00 00 06 41 43 43 45 50 54 00 30 40 70 82 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 81 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 82 2F 83 8F 4E 00 00 -58 43 B0 12 BA 81 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 82 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 82 -04 45 43 48 4F 00 B2 40 C2 48 08 83 82 43 DE 21 -38 40 05 00 B0 12 BA 81 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 83 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 83 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 82 68 83 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 81 02 43 52 00 30 40 80 83 -0D 12 84 12 14 80 02 0D 0A 00 4A 83 4E 84 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 82 01 40 2E 4E -30 4D CC 83 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 83 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 80 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FA 3C 0E 93 3E 4F +7C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A2 82 B2 49 +26 83 B2 49 FE 82 B2 49 A0 80 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 22 8C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 81 B0 12 D0 80 82 84 AC 80 +42 81 40 83 1E 80 05 1B 5B 37 6D 40 6C 83 0A 80 +02 18 A4 84 D0 85 6C 83 1E 80 04 1B 5B 30 6D 00 +6C 83 B8 88 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 40 83 1E 80 07 0D 0A 1B 5B 37 +6D 40 6C 83 0A 80 02 18 A4 84 D0 85 0A 80 23 00 +24 83 D0 85 1E 80 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +6C 83 0A 80 40 FF 32 80 98 84 9C 85 1E 80 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 80 36 81 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 81 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 40 FE FF +02 02 B2 D3 26 02 B2 43 22 02 F2 D3 47 02 F2 40 +BF 00 43 02 B2 40 00 A5 60 01 82 43 88 01 F2 D0 +C0 00 0D 02 F2 C3 82 01 F2 D0 06 00 82 01 B2 40 +F4 00 84 01 39 40 5C 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 +B0 12 D0 80 80 81 00 00 0C 41 43 43 45 50 54 00 +30 40 A4 82 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 A5 3E 21 52 A2 C2 6C 05 B2 B0 10 00 +40 05 9E 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 00 83 +58 43 B0 12 46 81 2F 83 8F 4E 00 00 92 B3 6C 05 +FD 27 1E 42 4C 05 B0 12 44 81 30 4D 00 00 08 45 +4D 49 54 00 30 40 28 83 08 4E 3E 4F A2 B3 6C 05 +FD 27 C2 48 4E 05 30 4D 1E 83 08 45 43 48 4F 00 +B2 40 C2 48 32 83 38 40 05 00 B0 12 46 81 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 32 83 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +7C 83 29 4F 8F 4E 00 00 7E 49 D4 3F 7E 83 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 8A 22 F9 98 +00 00 87 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 7E 22 9B 24 F8 82 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 80 00 00 9C 84 8E 83 E0 85 +9A 88 B0 80 0A 84 14 80 06 5B 54 48 45 4E 5D 00 +92 83 E8 83 AE 83 CC 83 14 80 06 5B 45 4C 53 45 +5D 00 92 83 FA 83 AE 83 CA 83 1E 80 04 5B 49 46 +5D 00 92 83 CC 83 B2 80 CA 83 1E 80 05 0D 6B 6F +20 0A 6C 83 9A 80 84 80 B2 80 CC 83 BA 83 0D 5B +54 48 45 4E 5D 00 30 4D 1E 84 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 2A 84 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 8E 83 E0 85 48 86 EC 87 +5C 85 3A 84 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 8E 83 E0 85 48 86 6C 84 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D 98 82 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 81 05 53 22 00 82 43 C0 21 0D 12 +84 12 0A 80 1E 80 4A 88 0A 80 22 00 E0 85 E0 84 +B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F +3D 41 30 4D 52 83 05 2E 22 00 0D 12 84 12 CA 84 +0A 80 6C 83 4A 88 5C 85 00 00 04 3C 23 00 B2 40 +B2 21 B2 21 30 4D C6 84 02 23 1B 42 BE 21 2C 4F +2F 83 B0 12 46 80 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 84 02 23 53 00 0D 12 84 12 -0A 84 44 84 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 84 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 83 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 83 -3C 84 EE 80 7C 84 58 84 4A 83 02 88 FA 82 4E 84 -2C 83 01 2E 0E 93 E3 37 38 43 E2 3F 76 84 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 48 87 -0A 80 22 00 1A 85 E8 84 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 84 -82 2E 22 00 0D 12 84 12 D2 84 0A 80 4A 83 48 87 -4E 84 F8 81 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C 86 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 86 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 87 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 84 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 80 02 88 1A 85 BE 87 9C 26 -3D 40 C6 87 DE 3E C8 87 0A 4E 3E 4F 3D 40 E2 87 -36 27 3D 40 B8 87 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 87 3E 4F 3D 40 B8 87 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 89 CC 3F -EC 87 86 12 20 00 D4 83 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C 83 BC 80 -B2 87 B2 83 E4 83 14 80 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 EC 83 -14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 81 -3A 80 2C 88 08 88 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 84 0A 80 2A 81 48 87 4E 84 7C 85 01 27 -0D 12 84 12 02 88 1A 85 82 85 34 80 00 88 4E 84 -00 00 83 5B 27 5D 0D 12 84 12 80 88 0A 80 0A 80 -48 87 48 87 4E 84 92 88 81 5B 82 43 BE 21 30 4D -FA 83 01 5D B2 43 BE 21 30 4D B2 88 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 88 1A 85 82 85 96 83 34 80 -00 88 E4 83 34 80 F4 88 0A 80 0A 80 48 87 48 87 -0A 80 48 87 48 87 4E 84 A8 88 01 3A 30 12 44 89 -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 88 1A 85 -12 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 81 FA 88 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A 80 4E 84 48 87 56 89 AA 88 4E 84 -A8 87 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 87 06 43 52 45 41 54 -45 00 B0 12 00 89 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 89 04 43 4F 44 45 00 B0 12 00 89 A2 82 -C6 21 0D 12 84 12 F2 8B CC 8B 4E 84 A2 89 07 48 -44 4E 43 4F 44 45 B2 40 D0 8B DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 89 0C 8C -2A 8C 4E 84 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C 8C 2A 8C 4E 84 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE 89 85 48 49 32 4C 4F 0D 12 84 12 28 80 9A 8B -48 87 AA 88 E2 89 4E 84 88 89 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 8A 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 80 00 00 C6 83 02 88 1A 85 98 87 -8E 83 34 80 02 8B 9C 83 14 80 06 5B 54 48 45 4E -5D 00 74 8A DC 8A 98 8A BA 8A 4E 84 9C 83 14 80 -06 5B 45 4C 53 45 5D 00 74 8A F2 8A 98 8A B8 8A -4E 84 14 80 04 5B 49 46 5D 00 74 8A BA 8A 3A 80 -B8 8A 70 83 14 80 05 0D 0A 6B 6F 20 4A 83 BC 80 -AC 80 3A 80 BA 8A A8 8A 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 8B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 88 1A 85 82 85 -26 8B 4E 84 2C 8B 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 8B DE 83 4E 84 5E 8B B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 87 06 4D -41 52 4B 45 52 00 B0 12 00 89 BA 40 85 12 FC FF -BA 40 5C 8B FE FF 28 83 8A 48 00 00 BA 40 AA 80 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A 80 -CA 21 D6 83 4E 84 85 12 9E 8B 66 88 D4 89 10 83 -7E 88 52 8A D2 82 6E 8B 00 85 96 8C AA 8C 8A 84 -14 85 00 00 46 8B BC 88 E2 85 00 00 85 12 9E 8B -54 92 BA 92 FC 91 0A 93 C2 91 00 00 8E 8F 00 00 -D2 93 B6 93 26 92 64 92 9E 90 00 00 00 00 26 93 -CA 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 8B 24 8C 2A 8C 3A 8C 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 88 -09 50 57 52 5F 53 54 41 54 45 85 12 32 8C DE 93 -CE 84 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 8C F3 3F 70 8C 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E 8C 30 4D 82 8C 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 8D FE FF 29 83 B9 40 -E2 81 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 81 B2 49 FA 80 B2 49 02 80 B2 49 00 82 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 D3 26 02 B2 43 22 02 -F2 D3 47 02 F2 40 BF 00 43 02 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 B6 00 82 01 B2 40 F3 00 -84 01 82 43 88 01 F2 D0 C0 00 0D 02 39 40 5C 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 80 FE 81 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A 85 82 85 -DE 83 34 80 CE 8D 3E 86 34 80 E8 8D E2 8D D0 8D -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 EA 8D B2 41 C4 21 3E 41 -84 12 0A 80 2B 00 1A 85 82 85 DE 83 34 80 06 8E -3E 86 34 80 00 88 A8 83 1A 85 3E 86 34 80 00 88 -12 8E 3E 5F E7 3F 3E 40 28 00 B0 12 B2 8D 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 6E 89 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A 85 3E 86 34 80 5A 8E 50 8E -21 53 3E 90 10 00 C6 2B 7F 2D 5C 8E B2 41 C4 21 -C1 3F 0D 12 84 12 02 88 8E 8D 6C 8E 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 B2 8D 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 B2 8D -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 3A 8E 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -3A 8E 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 3A 8E FA 23 3C 50 10 00 B0 12 -16 8E EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 02 88 8E 8D 38 8F FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 3A 8E E0 23 -3C 50 80 00 B0 12 16 8E DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 80 00 13 48 87 4E 84 0A 80 -2C 00 62 8E 2E 8F 78 8F 09 4B 2E 4E 0E DC A2 3F -40 8A 03 4D 4F 56 85 12 6E 8F 00 40 82 8F 05 4D -4F 56 2E 42 85 12 6E 8F 40 40 00 00 03 41 44 44 -85 12 6E 8F 00 50 9C 8F 05 41 44 44 2E 42 85 12 -6E 8F 40 50 A8 8F 04 41 44 44 43 00 85 12 6E 8F -00 60 B6 8F 06 41 44 44 43 2E 42 00 85 12 6E 8F -40 60 5C 8F 04 53 55 42 43 00 85 12 6E 8F 00 70 -D4 8F 06 53 55 42 43 2E 42 00 85 12 6E 8F 40 70 -E2 8F 03 53 55 42 85 12 6E 8F 00 80 F2 8F 05 53 -55 42 2E 42 85 12 6E 8F 40 80 16 8A 03 43 4D 50 -85 12 6E 8F 00 90 0C 90 05 43 4D 50 2E 42 85 12 -6E 8F 40 90 00 8A 04 44 41 44 44 00 85 12 6E 8F -00 A0 26 90 06 44 41 44 44 2E 42 00 85 12 6E 8F -40 A0 18 90 03 42 49 54 85 12 6E 8F 00 B0 44 90 -05 42 49 54 2E 42 85 12 6E 8F 40 B0 50 90 03 42 -49 43 85 12 6E 8F 00 C0 5E 90 05 42 49 43 2E 42 -85 12 6E 8F 40 C0 6A 90 03 42 49 53 85 12 6E 8F -00 D0 78 90 05 42 49 53 2E 42 85 12 6E 8F 40 D0 -00 00 03 58 4F 52 85 12 6E 8F 00 E0 92 90 05 58 -4F 52 2E 42 85 12 6E 8F 40 E0 C4 8F 03 41 4E 44 -85 12 6E 8F 00 F0 AC 90 05 41 4E 44 2E 42 85 12 -6E 8F 40 F0 02 88 62 8E CA 90 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F FE 8F 03 52 52 43 -85 12 C4 90 00 10 DC 90 05 52 52 43 2E 42 85 12 -C4 90 40 10 E8 90 04 53 57 50 42 00 85 12 C4 90 -80 10 F6 90 03 52 52 41 85 12 C4 90 00 11 04 91 -05 52 52 41 2E 42 85 12 C4 90 40 11 10 91 03 53 -58 54 85 12 C4 90 80 11 00 00 04 50 55 53 48 00 -85 12 C4 90 00 12 2A 91 06 50 55 53 48 2E 42 00 -85 12 C4 90 40 12 84 90 04 43 41 4C 4C 00 85 12 -C4 90 80 12 1A 53 0E 4A 0D 12 84 12 C4 84 14 80 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 81 -1E 91 03 53 3E 3D 86 12 00 38 72 91 02 53 3C 00 -86 12 00 34 38 91 03 30 3E 3D 86 12 00 30 86 91 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C 9A 91 03 55 3E 3D 86 12 00 28 90 91 03 30 -3C 3E 86 12 00 24 AE 91 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D A4 91 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 34 90 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 48 91 05 42 45 47 49 4E -30 40 28 80 D8 91 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D B8 90 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 C6 91 -A8 83 4E 84 7C 91 06 52 45 50 45 41 54 00 0D 12 -84 12 5A 92 DE 91 4E 84 8A 92 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -1A 92 03 42 57 31 85 12 88 92 00 00 A2 92 03 42 -57 32 85 12 88 92 00 00 AE 92 03 42 57 33 85 12 -88 92 00 00 C6 92 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 C4 92 00 00 -E6 92 03 46 57 32 85 12 C4 92 00 00 F2 92 03 46 -57 33 85 12 C4 92 00 00 FE 92 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 88 -DC 87 4E 84 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 02 88 8E 8D 48 93 92 53 C4 21 3E 40 2C 00 -84 12 1A 85 3E 86 34 80 00 88 24 8F 5E 93 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 76 92 04 52 52 43 -4D 00 85 12 42 93 50 00 8C 93 04 52 52 41 4D 00 -85 12 42 93 50 01 9A 93 04 52 4C 41 4D 00 85 12 -42 93 50 02 A8 93 04 52 52 55 4D 00 85 12 42 93 -50 03 B8 91 05 50 55 53 48 4D 85 12 42 93 00 15 -C4 93 04 50 4F 50 4D 00 85 12 42 93 00 17 +C8 4A 00 00 30 4D 18 85 04 23 53 00 0D 12 84 12 +1A 85 54 85 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +48 85 04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 62 85 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 3A 83 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 0E 85 8E 83 7C 85 +4C 85 78 84 8A 85 66 85 6C 83 5C 85 F6 84 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 +82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D CE 85 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 52 87 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 54 87 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 80 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +0A 85 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 80 8E 83 E0 85 B0 80 24 89 48 86 0E 88 0A 4E +3E 4F 3D 40 28 88 6D 27 3D 40 02 88 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 2A 88 3E 4F 3D 40 02 88 +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 00 8A 2A 3C F2 87 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 48 88 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 84 85 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D AA 84 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E 80 02 0D 0A 00 6C 83 94 80 FC 87 8A 84 B4 84 +1E 80 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 81 +32 80 0A 80 40 FF BC 84 1E 80 09 46 52 41 4D 20 +66 75 6C 6C 08 81 B2 80 C0 88 AA 88 0D 41 42 4F +52 54 22 00 0D 12 84 12 CA 84 0A 80 08 81 4A 88 +5C 85 DA 85 02 27 0D 12 84 12 8E 83 E0 85 48 86 +B0 80 26 89 EE 84 32 88 54 84 07 5B 27 5D 0D 12 +84 12 16 89 0A 80 0A 80 4A 88 4A 88 5C 85 2A 89 +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D A2 84 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 8E 83 E0 85 48 86 B0 80 26 89 B4 84 AC 80 +7E 89 0A 80 0A 80 4A 88 4A 88 0A 80 4A 88 4A 88 +5C 85 00 00 02 3A 30 12 D4 89 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 8E 83 E0 85 9C 89 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E 80 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 81 40 89 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A 80 5C 85 4A 88 E6 89 42 89 5C 85 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D 94 88 0C 43 52 45 41 54 45 00 B0 12 8A 89 +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 66 83 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 84 89 0E 3A 4E 4F 4E 41 4D 45 +30 12 D4 89 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 1E 8A 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 16 89 A0 8A +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 2E 89 0A 80 +A2 8A 4A 88 5C 85 34 8A 08 43 4F 44 45 00 B0 12 +8A 89 A2 82 C8 21 61 3C 76 85 0E 48 44 4E 43 4F +44 45 B2 40 8E 8B CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 E6 89 EC 8A 3D 41 92 42 +D0 21 CC 21 5D 3C B8 8A 0E 43 4F 44 45 4E 4E 4D +30 12 C2 8A B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F CA 8A 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F 56 8B B2 40 68 8B D0 21 82 4E CE 21 +30 40 EE 84 85 12 54 8B 54 89 FC 88 E6 8B F8 8A +4E 8A 98 85 42 86 14 89 3C 8B 8E 8A 68 8A 04 8A +5C 88 70 8C 9A 86 00 00 00 00 85 12 54 8B EA 92 +6E 91 CE 92 96 90 F2 90 40 91 1C 92 28 92 B8 8F +DC 90 00 00 00 00 2A 8B A8 8E 00 00 44 92 88 8B +B2 40 68 8B CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +BC 8B 30 4D CE 8B 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 BC 8B 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E 82 FE FF 29 83 B9 40 FA 81 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 C0 8B 82 43 4A 18 C7 3F +62 8C B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 4A 89 +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +8E 83 E0 85 48 86 AC 80 8E 8C 82 84 22 88 90 8C +3E 4F 3D 41 B2 41 C6 21 B0 12 8A 89 BA 40 85 12 +FC FF BA 40 60 8C FE FF 28 83 8A 48 00 00 BA 40 +82 80 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +E0 85 48 86 AC 80 FA 8C DA 8C 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 60 8C 00 00 +01 20 3E 52 2E 83 21 53 30 41 F2 86 AC 80 02 8D +F6 8C 04 8D B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 CA 8C 15 20 3E 40 2B 00 +B0 12 CA 8C 06 20 3E 40 2D 00 B0 12 CA 8C 92 83 +C6 21 0E 12 1E 41 02 00 84 12 E0 85 F2 86 AC 80 +26 89 44 8D 3E 51 3A 17 30 41 B0 12 0A 8D 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 E0 85 F2 86 AC 80 +7C 8D 74 8D 3E 90 10 00 E6 2B 7C 2D 7E 8D A2 41 +C6 21 E1 3F 03 20 B0 12 62 8D 43 3C 7A 90 23 00 +24 20 B0 12 12 8D 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 12 8D F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 5E 8D 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 62 8D 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 4A 8D +F2 3F 03 20 B0 12 62 8D F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 4A 8D EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 80 00 13 4A 88 5C 85 +0A 80 2C 00 40 8E 84 8D 8E 83 4A 8E 22 8E 90 8E +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 80 8E 00 40 9C 8E 0A 4D 4F 56 2E 42 85 12 +80 8E 40 40 00 00 06 41 44 44 85 12 80 8E 00 50 +B6 8E 0A 41 44 44 2E 42 85 12 80 8E 40 50 C2 8E +08 41 44 44 43 00 85 12 80 8E 00 60 D0 8E 0C 41 +44 44 43 2E 42 00 85 12 80 8E 40 60 08 8B 08 53 +55 42 43 00 85 12 80 8E 00 70 EE 8E 0C 53 55 42 +43 2E 42 00 85 12 80 8E 40 70 FC 8E 06 53 55 42 +85 12 80 8E 00 80 0C 8F 0A 53 55 42 2E 42 85 12 +80 8E 40 80 18 8F 06 43 4D 50 85 12 80 8E 00 90 +26 8F 0A 43 4D 50 2E 42 85 12 80 8E 40 90 00 00 +08 44 41 44 44 00 85 12 80 8E 00 A0 40 8F 0C 44 +41 44 44 2E 42 00 85 12 80 8E 40 A0 6E 8E 06 42 +49 54 85 12 80 8E 00 B0 5E 8F 0A 42 49 54 2E 42 +85 12 80 8E 40 B0 6A 8F 06 42 49 43 85 12 80 8E +00 C0 78 8F 0A 42 49 43 2E 42 85 12 80 8E 40 C0 +84 8F 06 42 49 53 85 12 80 8E 00 D0 92 8F 0A 42 +49 53 2E 42 85 12 80 8E 40 D0 00 00 06 58 4F 52 +85 12 80 8E 00 E0 AC 8F 0A 58 4F 52 2E 42 85 12 +80 8E 40 E0 DE 8E 06 41 4E 44 85 12 80 8E 00 F0 +C6 8F 0A 41 4E 44 2E 42 85 12 80 8E 40 F0 8E 83 +40 8E 84 8D E6 8F 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F 9E 8F 06 52 52 43 85 12 DE 8F +00 10 F8 8F 0A 52 52 43 2E 42 85 12 DE 8F 40 10 +32 8F 08 53 57 50 42 00 85 12 DE 8F 80 10 04 90 +06 52 52 41 85 12 DE 8F 00 11 20 90 0A 52 52 41 +2E 42 85 12 DE 8F 40 11 12 90 06 53 58 54 85 12 +DE 8F 80 11 00 00 08 50 55 53 48 00 85 12 DE 8F +00 12 46 90 0C 50 55 53 48 2E 42 00 85 12 DE 8F +40 12 3A 90 08 43 41 4C 4C 00 85 12 DE 8F 80 12 +1A 53 0E 4A 84 12 D0 85 1E 80 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 81 64 90 06 53 3E 3D +86 12 00 38 8C 90 04 53 3C 00 86 12 00 34 54 90 +06 30 3E 3D 86 12 00 30 A0 90 04 30 3C 00 86 12 +00 30 DC 8A 04 55 3C 00 86 12 00 2C B4 90 06 55 +3E 3D 86 12 00 28 AA 90 06 30 3C 3E 86 12 00 24 +C8 90 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +4E 8F 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D BE 90 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 2C 90 0A 42 45 47 49 4E 30 40 32 80 16 91 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D D2 8F 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 E0 90 76 84 5C 85 34 91 +0C 52 45 50 45 41 54 00 0D 12 84 12 74 91 F8 90 +5C 85 A4 91 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D 90 91 06 42 57 31 +85 12 A2 91 00 00 BC 91 06 42 57 32 85 12 A2 91 +00 00 C8 91 06 42 57 33 85 12 A2 91 00 00 E0 91 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 DE 91 00 00 04 92 +06 46 57 32 85 12 DE 91 00 00 10 92 06 46 57 33 +85 12 DE 91 00 00 7E 91 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 16 89 22 88 +5C 85 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +4A 8E 0A 80 2C 00 E0 85 F2 86 AC 80 26 89 8E 83 +40 8E 22 8E 76 92 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E D4 91 08 52 52 43 4D 00 85 12 60 92 50 00 +A4 92 08 52 52 41 4D 00 85 12 60 92 50 01 B2 92 +08 52 4C 41 4D 00 85 12 60 92 50 02 C0 92 08 52 +52 55 4D 00 85 12 60 92 50 03 D2 90 0A 50 55 53 +48 4D 85 12 60 92 00 15 DC 92 08 50 4F 50 4D 00 +85 12 60 92 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -82 82 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 -E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 E2 81 08 8D +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +B6 82 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 +FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 FA 81 0E 82 q diff --git a/binaries/MSP_EXP430FR2355_8MHz_UART.txt b/binaries/MSP_EXP430FR2355_8MHz_UART.txt deleted file mode 100644 index 933fdc7..0000000 --- a/binaries/MSP_EXP430FR2355_8MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF F4 93 02 8C 34 01 -10 00 41 B3 94 81 AA 80 DA 81 9C 81 94 82 F4 93 -02 8C 7A 82 92 83 24 83 FE 82 3C 21 60 84 D4 80 -E2 80 EE 80 20 00 0A 00 00 00 00 00 00 00 00 00 -@8000 -B0 12 DA 81 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 80 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 80 39 40 22 18 -B2 49 78 82 B2 49 90 83 B2 49 22 83 B2 49 FC 82 -B2 49 CA 80 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE 8C 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 81 92 C3 9C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -9C 05 F3 23 B0 12 F8 80 0A 80 DE 21 E0 83 32 83 -14 80 04 1B 5B 37 6D 00 5C 83 A8 83 34 80 86 81 -14 80 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 83 A0 84 5C 83 14 80 04 1B 5B 30 6D 00 -5C 83 28 88 92 B3 8A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 80 05 92 42 02 18 86 05 92 42 04 18 -88 05 F2 D0 0C 00 2B 02 92 C3 80 05 92 D3 9A 05 -92 C3 30 01 30 41 09 3C A2 B3 9C 05 FD 27 B2 40 -13 00 8E 05 D2 D3 03 02 30 41 A2 B3 9C 05 FD 27 -B2 40 11 00 8E 05 D2 C3 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 81 E2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 81 04 57 41 52 4D 00 B0 12 -9C 81 84 12 14 80 07 0D 0A 1B 5B 37 6D 23 5C 83 -D6 84 14 80 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 83 -0A 80 40 FF 28 80 D4 83 A0 84 14 80 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 80 86 81 00 00 06 41 -43 43 45 50 54 00 30 40 7A 82 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 82 3C 40 D2 82 -5D 15 B6 3E 21 52 3A 17 58 42 8C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 9C 05 FD 27 -C2 48 8E 05 30 4D C8 82 2D 83 92 B3 9C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 9C 05 -FD 27 58 42 8C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 82 2F 83 -8F 4E 00 00 B0 12 DA 81 92 B3 9C 05 FD 27 1E 42 -8C 05 B0 12 C8 81 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 83 08 4E 3E 4F C8 3F 1A 83 04 45 43 48 -4F 00 B2 40 C2 48 C0 82 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 82 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 83 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 83 7A 83 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 81 02 43 52 00 30 40 -92 83 0D 12 84 12 14 80 02 0D 0A 00 5C 83 60 84 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 82 01 40 -2E 4E 30 4D DE 83 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A 83 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E 80 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A 84 02 23 53 00 0D 12 -84 12 1C 84 56 84 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 84 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 83 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 84 4E 84 EE 80 8E 84 6A 84 5C 83 14 88 20 83 -60 84 40 83 01 2E 0E 93 E3 37 38 43 E2 3F 88 84 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A 80 14 80 -5A 87 0A 80 22 00 2C 85 FA 84 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 84 82 2E 22 00 0D 12 84 12 E4 84 0A 80 5C 83 -5A 87 60 84 18 82 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 80 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 80 35 40 D4 80 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE 86 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 86 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 80 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 87 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A 80 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 84 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 84 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 80 14 88 2C 85 D0 87 -9C 26 3D 40 D8 87 DE 3E DA 87 0A 4E 3E 4F 3D 40 -F4 87 36 27 3D 40 CA 87 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 87 3E 4F 3D 40 CA 87 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 89 -CC 3F FE 87 86 12 20 00 E6 83 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E 83 -BC 80 C4 87 C4 83 F6 83 14 80 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 81 0A 80 40 FF 28 80 -FE 83 14 80 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 81 3A 80 3E 88 1A 88 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 84 0A 80 2A 81 5A 87 60 84 8E 85 -01 27 0D 12 84 12 14 88 2C 85 94 85 34 80 12 88 -60 84 00 00 83 5B 27 5D 0D 12 84 12 92 88 0A 80 -0A 80 5A 87 5A 87 60 84 A4 88 81 5B 82 43 BE 21 -30 4D 0C 84 01 5D B2 43 BE 21 30 4D C4 88 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 88 2C 85 94 85 A8 83 -34 80 12 88 F6 83 34 80 06 89 0A 80 0A 80 5A 87 -5A 87 0A 80 5A 87 5A 87 60 84 BA 88 01 3A 30 12 -56 89 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 88 -2C 85 24 89 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 80 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 81 0C 89 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A 80 60 84 5A 87 68 89 BC 88 -60 84 BA 87 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 87 06 43 52 45 -41 54 45 00 B0 12 12 89 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 89 04 43 4F 44 45 00 B0 12 12 89 -A2 82 C6 21 0D 12 84 12 04 8C DE 8B 60 84 B4 89 -07 48 44 4E 43 4F 44 45 B2 40 E2 8B DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 89 -1E 8C 3C 8C 60 84 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E 8C 3C 8C 60 84 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 8A 85 48 49 32 4C 4F 0D 12 84 12 28 80 -AC 8B 5A 87 BC 88 F4 89 60 84 9A 89 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 8A 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 80 00 00 D8 83 14 88 2C 85 -AA 87 A0 83 34 80 14 8B AE 83 14 80 06 5B 54 48 -45 4E 5D 00 86 8A EE 8A AA 8A CC 8A 60 84 AE 83 -14 80 06 5B 45 4C 53 45 5D 00 86 8A 04 8B AA 8A -CA 8A 60 84 14 80 04 5B 49 46 5D 00 86 8A CC 8A -3A 80 CA 8A 82 83 14 80 05 0D 0A 6B 6F 20 5C 83 -BC 80 AC 80 3A 80 CC 8A BA 8A 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 8B 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 88 2C 85 -94 85 38 8B 60 84 3E 8B 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 8B F0 83 60 84 70 8B -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 87 -06 4D 41 52 4B 45 52 00 B0 12 12 89 BA 40 85 12 -FC FF BA 40 6E 8B FE FF 28 83 8A 48 00 00 BA 40 -AA 80 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A 80 CA 21 E8 83 60 84 85 12 B0 8B 78 88 E6 89 -2C 83 90 88 64 8A F6 82 80 8B 12 85 A8 8C BC 8C -9C 84 26 85 00 00 58 8B CE 88 F4 85 00 00 85 12 -B0 8B 6A 92 D0 92 12 92 20 93 D8 91 00 00 A4 8F -00 00 E8 93 CC 93 3C 92 7A 92 B4 90 00 00 00 00 -3C 93 DC 8B 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 8B 36 8C 3C 8C 4C 8C 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 88 09 50 57 52 5F 53 54 41 54 45 85 12 44 8C -F4 93 E0 84 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 8C F3 3F 82 8C 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 8C 30 4D 94 8C 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 8D FE FF 29 83 -B9 40 02 82 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 82 B2 49 FA 80 B2 49 02 80 B2 49 20 82 -B2 49 E2 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 D2 D3 05 02 B2 D3 -26 02 B2 43 22 02 F2 D3 47 02 F2 40 BF 00 43 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B6 00 -82 01 B2 40 F3 00 84 01 82 43 88 01 F2 D0 C0 00 -0D 02 39 40 5C 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 80 1E 82 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C 85 94 85 F0 83 34 80 E4 8D 50 86 34 80 -FE 8D F8 8D E6 8D 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 00 8E -B2 41 C4 21 3E 41 84 12 0A 80 2B 00 2C 85 94 85 -F0 83 34 80 1C 8E 50 86 34 80 12 88 BA 83 2C 85 -50 86 34 80 12 88 28 8E 3E 5F E7 3F 3E 40 28 00 -B0 12 C8 8D 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 80 89 -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C 85 50 86 -34 80 70 8E 66 8E 21 53 3E 90 10 00 C6 2B 7F 2D -72 8E B2 41 C4 21 C1 3F 0D 12 84 12 14 88 A4 8D -82 8E 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 C8 8D 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 C8 8D ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 50 8E 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 50 8E 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 50 8E FA 23 -3C 50 10 00 B0 12 2C 8E EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 14 88 A4 8D 4E 8F FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 50 8E E0 23 3C 50 80 00 B0 12 2C 8E DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 80 00 13 -5A 87 60 84 0A 80 2C 00 78 8E 44 8F 8E 8F 09 4B -2E 4E 0E DC A2 3F 52 8A 03 4D 4F 56 85 12 84 8F -00 40 98 8F 05 4D 4F 56 2E 42 85 12 84 8F 40 40 -00 00 03 41 44 44 85 12 84 8F 00 50 B2 8F 05 41 -44 44 2E 42 85 12 84 8F 40 50 BE 8F 04 41 44 44 -43 00 85 12 84 8F 00 60 CC 8F 06 41 44 44 43 2E -42 00 85 12 84 8F 40 60 72 8F 04 53 55 42 43 00 -85 12 84 8F 00 70 EA 8F 06 53 55 42 43 2E 42 00 -85 12 84 8F 40 70 F8 8F 03 53 55 42 85 12 84 8F -00 80 08 90 05 53 55 42 2E 42 85 12 84 8F 40 80 -28 8A 03 43 4D 50 85 12 84 8F 00 90 22 90 05 43 -4D 50 2E 42 85 12 84 8F 40 90 12 8A 04 44 41 44 -44 00 85 12 84 8F 00 A0 3C 90 06 44 41 44 44 2E -42 00 85 12 84 8F 40 A0 2E 90 03 42 49 54 85 12 -84 8F 00 B0 5A 90 05 42 49 54 2E 42 85 12 84 8F -40 B0 66 90 03 42 49 43 85 12 84 8F 00 C0 74 90 -05 42 49 43 2E 42 85 12 84 8F 40 C0 80 90 03 42 -49 53 85 12 84 8F 00 D0 8E 90 05 42 49 53 2E 42 -85 12 84 8F 40 D0 00 00 03 58 4F 52 85 12 84 8F -00 E0 A8 90 05 58 4F 52 2E 42 85 12 84 8F 40 E0 -DA 8F 03 41 4E 44 85 12 84 8F 00 F0 C2 90 05 41 -4E 44 2E 42 85 12 84 8F 40 F0 14 88 78 8E E0 90 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -14 90 03 52 52 43 85 12 DA 90 00 10 F2 90 05 52 -52 43 2E 42 85 12 DA 90 40 10 FE 90 04 53 57 50 -42 00 85 12 DA 90 80 10 0C 91 03 52 52 41 85 12 -DA 90 00 11 1A 91 05 52 52 41 2E 42 85 12 DA 90 -40 11 26 91 03 53 58 54 85 12 DA 90 80 11 00 00 -04 50 55 53 48 00 85 12 DA 90 00 12 40 91 06 50 -55 53 48 2E 42 00 85 12 DA 90 40 12 9A 90 04 43 -41 4C 4C 00 85 12 DA 90 80 12 1A 53 0E 4A 0D 12 -84 12 D6 84 14 80 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 81 34 91 03 53 3E 3D 86 12 00 38 -88 91 02 53 3C 00 86 12 00 34 4E 91 03 30 3E 3D -86 12 00 30 9C 91 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C B0 91 03 55 3E 3D 86 12 -00 28 A6 91 03 30 3C 3E 86 12 00 24 C4 91 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D BA 91 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -4A 90 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 5E 91 -05 42 45 47 49 4E 30 40 28 80 EE 91 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D CE 90 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 DC 91 BA 83 60 84 92 91 06 52 45 50 -45 41 54 00 0D 12 84 12 70 92 F4 91 60 84 A0 92 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 30 92 03 42 57 31 85 12 9E 92 -00 00 B8 92 03 42 57 32 85 12 9E 92 00 00 C4 92 -03 42 57 33 85 12 9E 92 00 00 DC 92 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 DA 92 00 00 FC 92 03 46 57 32 85 12 DA 92 -00 00 08 93 03 46 57 33 85 12 DA 92 00 00 14 93 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 92 88 EE 87 60 84 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 14 88 A4 8D 5E 93 92 53 -C4 21 3E 40 2C 00 84 12 2C 85 50 86 34 80 12 88 -3A 8F 74 93 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -8C 92 04 52 52 43 4D 00 85 12 58 93 50 00 A2 93 -04 52 52 41 4D 00 85 12 58 93 50 01 B0 93 04 52 -4C 41 4D 00 85 12 58 93 50 02 BE 93 04 52 52 55 -4D 00 85 12 58 93 50 03 CE 91 05 50 55 53 48 4D -85 12 58 93 00 15 DA 93 04 50 4F 50 4D 00 85 12 -58 93 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 94 82 02 82 02 82 02 82 02 82 02 82 02 82 -02 82 02 82 02 82 02 82 02 82 02 82 02 82 1A 8D -q diff --git a/binaries/MSP_EXP430FR2433_16MHz_115200.txt b/binaries/MSP_EXP430FR2433_16MHz_115200.txt new file mode 100644 index 0000000..d76dd56 --- /dev/null +++ b/binaries/MSP_EXP430FR2433_16MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A0 59 +C2 C6 7E C5 84 C5 54 C5 32 C7 20 D7 D8 CF 92 CF +92 CF A8 C6 66 C7 2E C7 3C 21 E0 20 86 C9 B6 C4 +C4 C4 A2 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +32 C7 20 D7 D8 CF 92 CF 92 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FC 3C 0E 93 3E 4F +91 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A6 C6 B2 49 +64 C7 B2 49 2C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 4C D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 32 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 AC C8 AC C4 52 C5 74 C7 1E C4 04 1B +5B 37 6D 00 96 C7 96 C7 1E C4 04 1B 5B 30 6D 00 +96 C7 E2 CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 74 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 96 C7 FA C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 96 C7 0A C4 40 FF 32 C4 +C2 C8 C6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B2 01 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 +26 02 F2 43 22 02 F2 40 A5 00 A1 01 F2 40 10 00 +A0 01 D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 03 00 0B 02 F2 C3 82 01 F2 D0 0A 00 82 01 +B2 40 E8 01 84 01 39 40 80 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 10 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 A8 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 06 C7 3C 40 12 C7 5D 15 +9F 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 D2 D3 02 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D 08 C7 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 2E C7 30 12 +44 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 D2 C3 +02 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 CE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 66 C7 08 4E 3E 4F C7 3F 5C C7 08 45 +43 48 4F 00 B2 40 C2 48 00 C7 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 00 C7 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 A6 C7 29 4F 8F 4E +00 00 7E 49 DE 3F A8 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 75 22 F9 98 00 00 72 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 69 22 +9B 24 26 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 C6 C8 B8 C7 0A CA C4 CC B0 C4 34 C8 +14 C4 06 5B 54 48 45 4E 5D 00 BC C7 12 C8 D8 C7 +F6 C7 14 C4 06 5B 45 4C 53 45 5D 00 BC C7 24 C8 +D8 C7 F4 C7 1E C4 04 5B 49 46 5D 00 BC C7 F6 C7 +B2 C4 F4 C7 1E C4 05 0D 6B 6F 20 0A 96 C7 9A C4 +84 C4 B2 C4 F6 C7 E4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 48 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 54 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 B8 C7 0A CA 72 CA 16 CC 86 C9 64 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 B8 C7 +0A CA 72 CA 96 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 9C C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +74 CC 0A C4 22 00 0A CA 0A C9 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 7E C7 +05 2E 22 00 0D 12 84 12 F4 C8 0A C4 96 C7 74 CC +86 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +F0 C8 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +42 C9 04 23 53 00 0D 12 84 12 44 C9 7E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 72 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 8C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +6E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 38 C9 B8 C7 A6 C9 76 C9 A2 C8 B4 C9 +90 C9 96 C7 86 C9 20 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D F8 C9 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E +0E 43 1E 15 3D 40 7C CB 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 7E CB 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E +09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 34 C9 03 5C 92 42 +C2 21 C6 21 30 4D 0D 12 84 12 84 C4 B8 C7 0A CA +B0 C4 4E CD 72 CA 38 CC 0A 4E 3E 4F 3D 40 52 CC +6D 27 3D 40 2C CC 1A E2 BC 21 14 24 0E 12 3E 4F +30 41 54 CC 3E 4F 3D 40 2C CC 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 2A CE 2A 3C +1C CC 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF +3E 4F 30 4D 72 CC 0F 4C 49 54 45 52 41 4C 82 93 +BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 +0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D AE C9 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D D4 C8 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F +30 4D 3F 40 80 20 0E 43 84 12 1E C4 02 0D 0A 00 +96 C7 94 C4 26 CC B4 C8 DE C8 1E C4 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 C5 32 C4 0A C4 40 FF +E6 C8 1E C4 09 46 52 41 4D 20 66 75 6C 6C 08 C5 +B2 C4 EA CC D4 CC 0D 41 42 4F 52 54 22 00 0D 12 +84 12 F4 C8 0A C4 08 C5 74 CC 86 C9 04 CA 02 27 +0D 12 84 12 B8 C7 0A CA 72 CA B0 C4 50 CD 18 C9 +5C CC 7E C8 07 5B 27 5D 0D 12 84 12 40 CD 0A C4 +0A C4 74 CC 74 CC 86 C9 54 CD 03 5B 82 43 BC 21 +30 4D 00 00 02 5D B2 43 BC 21 30 4D CC C8 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 B8 C7 0A CA +72 CA B0 C4 50 CD DE C8 AC C4 A8 CD 0A C4 0A C4 +74 CC 74 CC 0A C4 74 CC 74 CC 86 C9 00 00 02 3A +30 12 FE CD 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 +B8 C7 0A CA C6 CD 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A +B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D +82 9F BA 21 66 25 84 12 1E C4 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 C5 6A CD 03 3B +82 93 BC 21 F4 26 0D 12 84 12 0A C4 86 C9 74 CC +10 CE 6C CD 86 C9 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 21 D8 D3 00 00 30 4D BE CC 0C 43 +52 45 41 54 45 00 B0 12 B4 CD BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 90 C7 0A 44 4F 45 53 3E 1A 42 +B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +AE CD 0E 3A 4E 4F 4E 41 4D 45 30 12 FE CD 2F 83 +8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 48 CE 05 49 53 00 0D 12 82 93 +BC 21 08 20 84 12 40 CD CA CE 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 58 CD 0A C4 CC CE 74 CC 86 C9 +5E CE 08 43 4F 44 45 00 B0 12 B4 CD A2 82 C8 21 +61 3C A0 C9 0E 48 44 4E 43 4F 44 45 B2 40 B8 CF +CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 10 CE 16 CF 3D 41 92 42 D0 21 CC 21 5D 3C +E2 CE 0E 43 4F 44 45 4E 4E 4D 30 12 EC CE B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 +C8 21 EF 3F F4 CE 0B 48 49 32 4C 4F A2 53 C8 21 +1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 80 CF +B2 40 92 CF D0 21 82 4E CE 21 30 40 18 C9 85 12 +7E CF 7E CD 26 CD 10 D0 22 CF 78 CE C2 C9 6C CA +3E CD 66 CF B8 CE 92 CE 2E CE 86 CC 9A D0 C4 CA +00 00 00 00 85 12 7E CF 14 D7 98 D5 F8 D6 C0 D4 +1C D5 6A D5 46 D6 52 D6 E2 D3 06 D5 00 00 00 00 +54 CF D2 D2 00 00 6E D6 B2 CF B2 40 92 CF CE 21 +82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 21 3A 40 42 18 B0 12 E6 CF 30 4D F8 CF +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 21 B0 12 E6 CF 1A 42 CA 21 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C6 +FE FF 29 83 B9 40 F2 C5 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 E4 FF 3B 40 10 00 3A 40 3A 18 +B0 12 EA CF 82 43 4A 18 C7 3F 8C D0 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 74 CD 0C 4D 41 52 4B 45 +52 00 12 12 C6 21 0D 12 84 12 B8 C7 0A CA 72 CA +AC C4 B8 D0 AC C8 4C CC BA D0 3E 4F 3D 41 B2 41 +C6 21 B0 12 B4 CD BA 40 85 12 FC FF BA 40 8A D0 +FE FF 28 83 8A 48 00 00 BA 40 82 C4 02 00 A2 52 +C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 21 84 12 0A CA 72 CA AC C4 +24 D1 04 D1 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 8A D0 00 00 01 20 3E 52 2E 83 +21 53 30 41 1C CB AC C4 2C D1 20 D1 2E D1 B2 41 +C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 +B0 12 F4 D0 15 20 3E 40 2B 00 B0 12 F4 D0 06 20 +3E 40 2D 00 B0 12 F4 D0 92 83 C6 21 0E 12 1E 41 +02 00 84 12 0A CA 1C CB AC C4 50 CD 6E D1 3E 51 +3A 17 30 41 B0 12 34 D1 19 42 C8 21 89 4E 00 00 +A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 +3D 15 84 12 0A CA 1C CB AC C4 A6 D1 9E D1 3E 90 +10 00 E6 2B 7C 2D A8 D1 A2 41 C6 21 E1 3F 03 20 +B0 12 8C D1 43 3C 7A 90 23 00 24 20 B0 12 3C D1 +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +3C D1 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +88 D1 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 8C D1 +92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 74 D1 F2 3F 03 20 B0 12 +8C D1 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 74 D1 EA 3F 0C 43 1B 42 C8 21 +A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 +7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A C4 00 13 74 CC 86 C9 0A C4 2C 00 6A D2 +AE D1 B8 C7 74 D2 4C D2 BA D2 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 AA D2 00 40 +C6 D2 0A 4D 4F 56 2E 42 85 12 AA D2 40 40 00 00 +06 41 44 44 85 12 AA D2 00 50 E0 D2 0A 41 44 44 +2E 42 85 12 AA D2 40 50 EC D2 08 41 44 44 43 00 +85 12 AA D2 00 60 FA D2 0C 41 44 44 43 2E 42 00 +85 12 AA D2 40 60 32 CF 08 53 55 42 43 00 85 12 +AA D2 00 70 18 D3 0C 53 55 42 43 2E 42 00 85 12 +AA D2 40 70 26 D3 06 53 55 42 85 12 AA D2 00 80 +36 D3 0A 53 55 42 2E 42 85 12 AA D2 40 80 42 D3 +06 43 4D 50 85 12 AA D2 00 90 50 D3 0A 43 4D 50 +2E 42 85 12 AA D2 40 90 00 00 08 44 41 44 44 00 +85 12 AA D2 00 A0 6A D3 0C 44 41 44 44 2E 42 00 +85 12 AA D2 40 A0 98 D2 06 42 49 54 85 12 AA D2 +00 B0 88 D3 0A 42 49 54 2E 42 85 12 AA D2 40 B0 +94 D3 06 42 49 43 85 12 AA D2 00 C0 A2 D3 0A 42 +49 43 2E 42 85 12 AA D2 40 C0 AE D3 06 42 49 53 +85 12 AA D2 00 D0 BC D3 0A 42 49 53 2E 42 85 12 +AA D2 40 D0 00 00 06 58 4F 52 85 12 AA D2 00 E0 +D6 D3 0A 58 4F 52 2E 42 85 12 AA D2 40 E0 08 D3 +06 41 4E 44 85 12 AA D2 00 F0 F0 D3 0A 41 4E 44 +2E 42 85 12 AA D2 40 F0 B8 C7 6A D2 AE D1 10 D4 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +C8 D3 06 52 52 43 85 12 08 D4 00 10 22 D4 0A 52 +52 43 2E 42 85 12 08 D4 40 10 5C D3 08 53 57 50 +42 00 85 12 08 D4 80 10 2E D4 06 52 52 41 85 12 +08 D4 00 11 4A D4 0A 52 52 41 2E 42 85 12 08 D4 +40 11 3C D4 06 53 58 54 85 12 08 D4 80 11 00 00 +08 50 55 53 48 00 85 12 08 D4 00 12 70 D4 0C 50 +55 53 48 2E 42 00 85 12 08 D4 40 12 64 D4 08 43 +41 4C 4C 00 85 12 08 D4 80 12 1A 53 0E 4A 84 12 +FA C9 1E C4 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 C5 8E D4 06 53 3E 3D 86 12 00 38 B6 D4 +04 53 3C 00 86 12 00 34 7E D4 06 30 3E 3D 86 12 +00 30 CA D4 04 30 3C 00 86 12 00 30 06 CF 04 55 +3C 00 86 12 00 2C DE D4 06 55 3E 3D 86 12 00 28 +D4 D4 06 30 3C 3E 86 12 00 24 F2 D4 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E +00 00 A2 53 C8 21 0E 4A 30 4D 78 D3 08 54 48 45 +4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D E8 D4 +08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 +A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 56 D4 0A 42 +45 47 49 4E 30 40 32 C4 40 D5 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 21 30 4D FC D3 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 0A D5 A0 C8 86 C9 5E D5 0C 52 45 50 45 41 +54 00 0D 12 84 12 9E D5 22 D5 86 C9 CE D5 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 +00 00 30 4D BA D5 06 42 57 31 85 12 CC D5 00 00 +E6 D5 06 42 57 32 85 12 CC D5 00 00 F2 D5 06 42 +57 33 85 12 CC D5 00 00 0A D6 3D 41 1A 42 C8 21 +28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 +A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 08 D6 00 00 2E D6 06 46 57 32 85 12 +08 D6 00 00 3A D6 06 46 57 33 85 12 08 D6 00 00 +A8 D5 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 40 CD 4C CC 86 C9 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 74 D2 0A C4 2C 00 +0A CA 1C CB AC C4 50 CD B8 C7 6A D2 4C D2 A0 D6 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E FE D5 08 52 +52 43 4D 00 85 12 8A D6 50 00 CE D6 08 52 52 41 +4D 00 85 12 8A D6 50 01 DC D6 08 52 4C 41 4D 00 +85 12 8A D6 50 02 EA D6 08 52 52 55 4D 00 85 12 +8A D6 50 03 FC D4 0A 50 55 53 48 4D 85 12 8A D6 +00 15 06 D7 08 50 4F 50 4D 00 85 12 8A D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 C2 C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR2433_16MHz_4MBds.txt b/binaries/MSP_EXP430FR2433_16MHz_4MBds.txt new file mode 100644 index 0000000..f6946da --- /dev/null +++ b/binaries/MSP_EXP430FR2433_16MHz_4MBds.txt @@ -0,0 +1,324 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A0 59 +C2 C6 7E C5 84 C5 54 C5 32 C7 20 D7 D8 CF 92 CF +92 CF A8 C6 66 C7 2E C7 3C 21 E0 20 86 C9 B6 C4 +C4 C4 A2 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +32 C7 20 D7 D8 CF 92 CF 92 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FC 3C 0E 93 3E 4F +91 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A6 C6 B2 49 +64 C7 B2 49 2C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 4C D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 32 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 AC C8 AC C4 52 C5 74 C7 1E C4 04 1B +5B 37 6D 00 96 C7 96 C7 1E C4 04 1B 5B 30 6D 00 +96 C7 E2 CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 74 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 96 C7 FA C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 96 C7 0A C4 40 FF 32 C4 +C2 C8 C6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B2 01 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 +26 02 F2 43 22 02 F2 40 A5 00 A1 01 F2 40 10 00 +A0 01 D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 03 00 0B 02 F2 C3 82 01 F2 D0 0A 00 82 01 +B2 40 E8 01 84 01 39 40 80 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 10 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 A8 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 06 C7 3C 40 12 C7 5D 15 +9F 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 D2 D3 02 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D 08 C7 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 2E C7 30 12 +44 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 D2 C3 +02 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 CE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 66 C7 08 4E 3E 4F C7 3F 5C C7 08 45 +43 48 4F 00 B2 40 C2 48 00 C7 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 00 C7 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 A6 C7 29 4F 8F 4E +00 00 7E 49 DE 3F A8 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 75 22 F9 98 00 00 72 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 69 22 +9B 24 26 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 C6 C8 B8 C7 0A CA C4 CC B0 C4 34 C8 +14 C4 06 5B 54 48 45 4E 5D 00 BC C7 12 C8 D8 C7 +F6 C7 14 C4 06 5B 45 4C 53 45 5D 00 BC C7 24 C8 +D8 C7 F4 C7 1E C4 04 5B 49 46 5D 00 BC C7 F6 C7 +B2 C4 F4 C7 1E C4 05 0D 6B 6F 20 0A 96 C7 9A C4 +84 C4 B2 C4 F6 C7 E4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 48 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 54 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 B8 C7 0A CA 72 CA 16 CC 86 C9 64 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 B8 C7 +0A CA 72 CA 96 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 9C C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +74 CC 0A C4 22 00 0A CA 0A C9 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 7E C7 +05 2E 22 00 0D 12 84 12 F4 C8 0A C4 96 C7 74 CC +86 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +F0 C8 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +42 C9 04 23 53 00 0D 12 84 12 44 C9 7E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 72 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 8C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +6E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 38 C9 B8 C7 A6 C9 76 C9 A2 C8 B4 C9 +90 C9 96 C7 86 C9 20 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D F8 C9 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E +0E 43 1E 15 3D 40 7C CB 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 7E CB 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E +09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 34 C9 03 5C 92 42 +C2 21 C6 21 30 4D 0D 12 84 12 84 C4 B8 C7 0A CA +B0 C4 4E CD 72 CA 38 CC 0A 4E 3E 4F 3D 40 52 CC +6D 27 3D 40 2C CC 1A E2 BC 21 14 24 0E 12 3E 4F +30 41 54 CC 3E 4F 3D 40 2C CC 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 2A CE 2A 3C +1C CC 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF +3E 4F 30 4D 72 CC 0F 4C 49 54 45 52 41 4C 82 93 +BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 +0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D AE C9 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D D4 C8 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F +30 4D 3F 40 80 20 0E 43 84 12 1E C4 02 0D 0A 00 +96 C7 94 C4 26 CC B4 C8 DE C8 1E C4 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 C5 32 C4 0A C4 40 FF +E6 C8 1E C4 09 46 52 41 4D 20 66 75 6C 6C 08 C5 +B2 C4 EA CC D4 CC 0D 41 42 4F 52 54 22 00 0D 12 +84 12 F4 C8 0A C4 08 C5 74 CC 86 C9 04 CA 02 27 +0D 12 84 12 B8 C7 0A CA 72 CA B0 C4 50 CD 18 C9 +5C CC 7E C8 07 5B 27 5D 0D 12 84 12 40 CD 0A C4 +0A C4 74 CC 74 CC 86 C9 54 CD 03 5B 82 43 BC 21 +30 4D 00 00 02 5D B2 43 BC 21 30 4D CC C8 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 B8 C7 0A CA +72 CA B0 C4 50 CD DE C8 AC C4 A8 CD 0A C4 0A C4 +74 CC 74 CC 0A C4 74 CC 74 CC 86 C9 00 00 02 3A +30 12 FE CD 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 +B8 C7 0A CA C6 CD 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A +B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D +82 9F BA 21 66 25 84 12 1E C4 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 C5 6A CD 03 3B +82 93 BC 21 F4 26 0D 12 84 12 0A C4 86 C9 74 CC +10 CE 6C CD 86 C9 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 21 D8 D3 00 00 30 4D BE CC 0C 43 +52 45 41 54 45 00 B0 12 B4 CD BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 90 C7 0A 44 4F 45 53 3E 1A 42 +B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +AE CD 0E 3A 4E 4F 4E 41 4D 45 30 12 FE CD 2F 83 +8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 48 CE 05 49 53 00 0D 12 82 93 +BC 21 08 20 84 12 40 CD CA CE 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 58 CD 0A C4 CC CE 74 CC 86 C9 +5E CE 08 43 4F 44 45 00 B0 12 B4 CD A2 82 C8 21 +61 3C A0 C9 0E 48 44 4E 43 4F 44 45 B2 40 B8 CF +CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 10 CE 16 CF 3D 41 92 42 D0 21 CC 21 5D 3C +E2 CE 0E 43 4F 44 45 4E 4E 4D 30 12 EC CE B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 +C8 21 EF 3F F4 CE 0B 48 49 32 4C 4F A2 53 C8 21 +1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 80 CF +B2 40 92 CF D0 21 82 4E CE 21 30 40 18 C9 85 12 +7E CF 7E CD 26 CD 10 D0 22 CF 78 CE C2 C9 6C CA +3E CD 66 CF B8 CE 92 CE 2E CE 86 CC 9A D0 C4 CA +00 00 00 00 85 12 7E CF 14 D7 98 D5 F8 D6 C0 D4 +1C D5 6A D5 46 D6 52 D6 E2 D3 06 D5 00 00 00 00 +54 CF D2 D2 00 00 6E D6 B2 CF B2 40 92 CF CE 21 +82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 21 3A 40 42 18 B0 12 E6 CF 30 4D F8 CF +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 21 B0 12 E6 CF 1A 42 CA 21 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C6 +FE FF 29 83 B9 40 F2 C5 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 E4 FF 3B 40 10 00 3A 40 3A 18 +B0 12 EA CF 82 43 4A 18 C7 3F 8C D0 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 74 CD 0C 4D 41 52 4B 45 +52 00 12 12 C6 21 0D 12 84 12 B8 C7 0A CA 72 CA +AC C4 B8 D0 AC C8 4C CC BA D0 3E 4F 3D 41 B2 41 +C6 21 B0 12 B4 CD BA 40 85 12 FC FF BA 40 8A D0 +FE FF 28 83 8A 48 00 00 BA 40 82 C4 02 00 A2 52 +C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 21 84 12 0A CA 72 CA AC C4 +24 D1 04 D1 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 8A D0 00 00 01 20 3E 52 2E 83 +21 53 30 41 1C CB AC C4 2C D1 20 D1 2E D1 B2 41 +C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 +B0 12 F4 D0 15 20 3E 40 2B 00 B0 12 F4 D0 06 20 +3E 40 2D 00 B0 12 F4 D0 92 83 C6 21 0E 12 1E 41 +02 00 84 12 0A CA 1C CB AC C4 50 CD 6E D1 3E 51 +3A 17 30 41 B0 12 34 D1 19 42 C8 21 89 4E 00 00 +A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 +3D 15 84 12 0A CA 1C CB AC C4 A6 D1 9E D1 3E 90 +10 00 E6 2B 7C 2D A8 D1 A2 41 C6 21 E1 3F 03 20 +B0 12 8C D1 43 3C 7A 90 23 00 24 20 B0 12 3C D1 +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +3C D1 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +88 D1 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 8C D1 +92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 74 D1 F2 3F 03 20 B0 12 +8C D1 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 74 D1 EA 3F 0C 43 1B 42 C8 21 +A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 +7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A C4 00 13 74 CC 86 C9 0A C4 2C 00 6A D2 +AE D1 B8 C7 74 D2 4C D2 BA D2 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 AA D2 00 40 +C6 D2 0A 4D 4F 56 2E 42 85 12 AA D2 40 40 00 00 +06 41 44 44 85 12 AA D2 00 50 E0 D2 0A 41 44 44 +2E 42 85 12 AA D2 40 50 EC D2 08 41 44 44 43 00 +85 12 AA D2 00 60 FA D2 0C 41 44 44 43 2E 42 00 +85 12 AA D2 40 60 32 CF 08 53 55 42 43 00 85 12 +AA D2 00 70 18 D3 0C 53 55 42 43 2E 42 00 85 12 +AA D2 40 70 26 D3 06 53 55 42 85 12 AA D2 00 80 +36 D3 0A 53 55 42 2E 42 85 12 AA D2 40 80 42 D3 +06 43 4D 50 85 12 AA D2 00 90 50 D3 0A 43 4D 50 +2E 42 85 12 AA D2 40 90 00 00 08 44 41 44 44 00 +85 12 AA D2 00 A0 6A D3 0C 44 41 44 44 2E 42 00 +85 12 AA D2 40 A0 98 D2 06 42 49 54 85 12 AA D2 +00 B0 88 D3 0A 42 49 54 2E 42 85 12 AA D2 40 B0 +94 D3 06 42 49 43 85 12 AA D2 00 C0 A2 D3 0A 42 +49 43 2E 42 85 12 AA D2 40 C0 AE D3 06 42 49 53 +85 12 AA D2 00 D0 BC D3 0A 42 49 53 2E 42 85 12 +AA D2 40 D0 00 00 06 58 4F 52 85 12 AA D2 00 E0 +D6 D3 0A 58 4F 52 2E 42 85 12 AA D2 40 E0 08 D3 +06 41 4E 44 85 12 AA D2 00 F0 F0 D3 0A 41 4E 44 +2E 42 85 12 AA D2 40 F0 B8 C7 6A D2 AE D1 10 D4 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +C8 D3 06 52 52 43 85 12 08 D4 00 10 22 D4 0A 52 +52 43 2E 42 85 12 08 D4 40 10 5C D3 08 53 57 50 +42 00 85 12 08 D4 80 10 2E D4 06 52 52 41 85 12 +08 D4 00 11 4A D4 0A 52 52 41 2E 42 85 12 08 D4 +40 11 3C D4 06 53 58 54 85 12 08 D4 80 11 00 00 +08 50 55 53 48 00 85 12 08 D4 00 12 70 D4 0C 50 +55 53 48 2E 42 00 85 12 08 D4 40 12 64 D4 08 43 +41 4C 4C 00 85 12 08 D4 80 12 1A 53 0E 4A 84 12 +FA C9 1E C4 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 C5 8E D4 06 53 3E 3D 86 12 00 38 B6 D4 +04 53 3C 00 86 12 00 34 7E D4 06 30 3E 3D 86 12 +00 30 CA D4 04 30 3C 00 86 12 00 30 06 CF 04 55 +3C 00 86 12 00 2C DE D4 06 55 3E 3D 86 12 00 28 +D4 D4 06 30 3C 3E 86 12 00 24 F2 D4 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E +00 00 A2 53 C8 21 0E 4A 30 4D 78 D3 08 54 48 45 +4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D E8 D4 +08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 +A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 56 D4 0A 42 +45 47 49 4E 30 40 32 C4 40 D5 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 21 30 4D FC D3 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 0A D5 A0 C8 86 C9 5E D5 0C 52 45 50 45 41 +54 00 0D 12 84 12 9E D5 22 D5 86 C9 CE D5 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 +00 00 30 4D BA D5 06 42 57 31 85 12 CC D5 00 00 +E6 D5 06 42 57 32 85 12 CC D5 00 00 F2 D5 06 42 +57 33 85 12 CC D5 00 00 0A D6 3D 41 1A 42 C8 21 +28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 +A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 08 D6 00 00 2E D6 06 46 57 32 85 12 +08 D6 00 00 3A D6 06 46 57 33 85 12 08 D6 00 00 +A8 D5 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 40 CD 4C CC 86 C9 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 74 D2 0A C4 2C 00 +0A CA 1C CB AC C4 50 CD B8 C7 6A D2 4C D2 A0 D6 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E FE D5 08 52 +52 43 4D 00 85 12 8A D6 50 00 CE D6 08 52 52 41 +4D 00 85 12 8A D6 50 01 DC D6 08 52 4C 41 4D 00 +85 12 8A D6 50 02 EA D6 08 52 52 55 4D 00 85 12 +8A D6 50 03 FC D4 0A 50 55 53 48 4D 85 12 8A D6 +00 15 06 D7 08 50 4F 50 4D 00 85 12 8A D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 C2 C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR2433_16MHz_I2C.txt b/binaries/MSP_EXP430FR2433_16MHz_I2C.txt index 91f43b5..a82fc2c 100644 --- a/binaries/MSP_EXP430FR2433_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2433_16MHz_I2C.txt @@ -1,335 +1,322 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF E4 D7 F0 CF 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 E4 D7 -F0 CF 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +BC C6 56 C5 56 C5 58 C5 44 C5 FC D6 B4 CF 6E CF +6E CF AA C6 2E C7 06 C7 3C 21 E0 20 62 C9 B6 C4 +C4 C4 7E C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 FC D6 B4 CF 6E CF 6E CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 16 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 02 CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 48 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 48 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C CA 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E CA 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 CB 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C8 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C4 02 CC 1A C9 BE CB 9C 26 -3D 40 C6 CB DE 3E C8 CB 0A 4E 3E 4F 3D 40 E2 CB -36 27 3D 40 B8 CB 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 CB 3E 4F 3D 40 B8 CB BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CD CC 3F -EC CB 86 12 20 00 D4 C7 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C C7 BC C4 -B2 CB B2 C7 E4 C7 14 C4 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 EC C7 -14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C5 -3A C4 2C CC 08 CC 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C8 0A C4 2A C5 48 CB 4E C8 7C C9 01 27 -0D 12 84 12 02 CC 1A C9 82 C9 34 C4 00 CC 4E C8 -00 00 83 5B 27 5D 0D 12 84 12 80 CC 0A C4 0A C4 -48 CB 48 CB 4E C8 92 CC 81 5B 82 43 BE 21 30 4D -FA C7 01 5D B2 43 BE 21 30 4D B2 CC 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CC 1A C9 82 C9 96 C7 34 C4 -00 CC E4 C7 34 C4 F4 CC 0A C4 0A C4 48 CB 48 CB -0A C4 48 CB 48 CB 4E C8 A8 CC 01 3A 30 12 44 CD -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 CC 1A C9 -12 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C5 FA CC 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A C4 4E C8 48 CB 56 CD AA CC 4E C8 -A8 CB 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 CB 06 43 52 45 41 54 -45 00 B0 12 00 CD BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CD 04 43 4F 44 45 00 B0 12 00 CD A2 82 -C6 21 0D 12 84 12 F2 CF CC CF 4E C8 A2 CD 07 48 -44 4E 43 4F 44 45 B2 40 D0 CF DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CD 0C D0 -2A D0 4E C8 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C D0 2A D0 4E C8 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 9A CF -48 CB AA CC E2 CD 4E C8 88 CD 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CE 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C4 00 00 C6 C7 02 CC 1A C9 98 CB -8E C7 34 C4 02 CF 9C C7 14 C4 06 5B 54 48 45 4E -5D 00 74 CE DC CE 98 CE BA CE 4E C8 9C C7 14 C4 -06 5B 45 4C 53 45 5D 00 74 CE F2 CE 98 CE B8 CE -4E C8 14 C4 04 5B 49 46 5D 00 74 CE BA CE 3A C4 -B8 CE 70 C7 14 C4 05 0D 0A 6B 6F 20 4A C7 BC C4 -AC C4 3A C4 BA CE A8 CE 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CF 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CC 1A C9 82 C9 -26 CF 4E C8 2C CF 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CF DE C7 4E C8 5E CF B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A CB 06 4D -41 52 4B 45 52 00 B0 12 00 CD BA 40 85 12 FC FF -BA 40 5C CF FE FF 28 83 8A 48 00 00 BA 40 AA C4 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 -CA 21 D6 C7 4E C8 85 12 9E CF 66 CC D4 CD 10 C7 -7E CC 52 CE D2 C6 6E CF 00 C9 96 D0 AA D0 8A C8 -14 C9 00 00 46 CF BC CC E2 C9 00 00 85 12 9E CF -5A D6 C0 D6 02 D6 10 D7 C8 D5 00 00 94 D3 00 00 -D8 D7 BC D7 2C D6 6A D6 A4 D4 00 00 00 00 2C D7 -CA CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 CF 24 D0 2A D0 3A D0 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CC -09 50 57 52 5F 53 54 41 54 45 85 12 32 D0 E4 D7 -CE C8 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E D0 F3 3F 70 D0 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E D0 30 4D 82 D0 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 D1 FE FF 29 83 B9 40 -E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 00 C6 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 43 -06 02 B2 40 FC FF 02 02 F2 D3 26 02 F2 43 22 02 -F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 BA 00 -82 01 B2 40 E8 01 84 01 82 43 88 01 F2 D0 03 00 -0B 02 39 40 80 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 FE C5 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 1A C9 82 C9 DE C7 34 C4 D4 D1 3E CA 34 C4 -EE D1 E8 D1 D6 D1 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 F0 D1 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1A C9 82 C9 -DE C7 34 C4 0C D2 3E CA 34 C4 00 CC A8 C7 1A C9 -3E CA 34 C4 00 CC 18 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 B8 D1 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 6E CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 1A C9 3E CA -34 C4 60 D2 56 D2 21 53 3E 90 10 00 C6 2B 7F 2D -62 D2 B2 41 C4 21 C1 3F 0D 12 84 12 02 CC 94 D1 -72 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 B8 D1 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 B8 D1 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 40 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 40 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 40 D2 FA 23 -3C 50 10 00 B0 12 1C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 02 CC 94 D1 3E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 40 D2 E0 23 3C 50 80 00 B0 12 1C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -48 CB 4E C8 0A C4 2C 00 68 D2 34 D3 7E D3 09 4B -2E 4E 0E DC A2 3F 40 CE 03 4D 4F 56 85 12 74 D3 -00 40 88 D3 05 4D 4F 56 2E 42 85 12 74 D3 40 40 -00 00 03 41 44 44 85 12 74 D3 00 50 A2 D3 05 41 -44 44 2E 42 85 12 74 D3 40 50 AE D3 04 41 44 44 -43 00 85 12 74 D3 00 60 BC D3 06 41 44 44 43 2E -42 00 85 12 74 D3 40 60 62 D3 04 53 55 42 43 00 -85 12 74 D3 00 70 DA D3 06 53 55 42 43 2E 42 00 -85 12 74 D3 40 70 E8 D3 03 53 55 42 85 12 74 D3 -00 80 F8 D3 05 53 55 42 2E 42 85 12 74 D3 40 80 -16 CE 03 43 4D 50 85 12 74 D3 00 90 12 D4 05 43 -4D 50 2E 42 85 12 74 D3 40 90 00 CE 04 44 41 44 -44 00 85 12 74 D3 00 A0 2C D4 06 44 41 44 44 2E -42 00 85 12 74 D3 40 A0 1E D4 03 42 49 54 85 12 -74 D3 00 B0 4A D4 05 42 49 54 2E 42 85 12 74 D3 -40 B0 56 D4 03 42 49 43 85 12 74 D3 00 C0 64 D4 -05 42 49 43 2E 42 85 12 74 D3 40 C0 70 D4 03 42 -49 53 85 12 74 D3 00 D0 7E D4 05 42 49 53 2E 42 -85 12 74 D3 40 D0 00 00 03 58 4F 52 85 12 74 D3 -00 E0 98 D4 05 58 4F 52 2E 42 85 12 74 D3 40 E0 -CA D3 03 41 4E 44 85 12 74 D3 00 F0 B2 D4 05 41 -4E 44 2E 42 85 12 74 D3 40 F0 02 CC 68 D2 D0 D4 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -04 D4 03 52 52 43 85 12 CA D4 00 10 E2 D4 05 52 -52 43 2E 42 85 12 CA D4 40 10 EE D4 04 53 57 50 -42 00 85 12 CA D4 80 10 FC D4 03 52 52 41 85 12 -CA D4 00 11 0A D5 05 52 52 41 2E 42 85 12 CA D4 -40 11 16 D5 03 53 58 54 85 12 CA D4 80 11 00 00 -04 50 55 53 48 00 85 12 CA D4 00 12 30 D5 06 50 -55 53 48 2E 42 00 85 12 CA D4 40 12 8A D4 04 43 -41 4C 4C 00 85 12 CA D4 80 12 1A 53 0E 4A 0D 12 -84 12 C4 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 24 D5 03 53 3E 3D 86 12 00 38 -78 D5 02 53 3C 00 86 12 00 34 3E D5 03 30 3E 3D -86 12 00 30 8C D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C A0 D5 03 55 3E 3D 86 12 -00 28 96 D5 03 30 3C 3E 86 12 00 24 B4 D5 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D AA D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -3A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 4E D5 -05 42 45 47 49 4E 30 40 28 C4 DE D5 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D BE D4 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 CC D5 A8 C7 4E C8 82 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 60 D6 E4 D5 4E C8 90 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 20 D6 03 42 57 31 85 12 8E D6 -00 00 A8 D6 03 42 57 32 85 12 8E D6 00 00 B4 D6 -03 42 57 33 85 12 8E D6 00 00 CC D6 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 CA D6 00 00 EC D6 03 46 57 32 85 12 CA D6 -00 00 F8 D6 03 46 57 33 85 12 CA D6 00 00 04 D7 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 80 CC DC CB 4E C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 02 CC 94 D1 4E D7 92 53 -C4 21 3E 40 2C 00 84 12 1A C9 3E CA 34 C4 00 CC -2A D3 64 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -7C D6 04 52 52 43 4D 00 85 12 48 D7 50 00 92 D7 -04 52 52 41 4D 00 85 12 48 D7 50 01 A0 D7 04 52 -4C 41 4D 00 85 12 48 D7 50 02 AE D7 04 52 52 55 -4D 00 85 12 48 D7 50 03 BE D5 05 50 55 53 48 4D -85 12 48 D7 00 15 CA D7 04 50 4F 50 4D 00 85 12 -48 D7 00 17 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FD 3C 0E 93 3E 4F +7F 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A8 C6 B2 49 +2C C7 B2 49 04 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 28 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 88 C8 AC C4 +42 C5 46 C7 1E C4 05 1B 5B 37 6D 40 72 C7 0A C4 +02 18 AA C8 D6 C9 72 C7 1E C4 04 1B 5B 30 6D 00 +72 C7 BE CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 46 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 72 C7 0A C4 02 18 AA C8 D6 C9 0A C4 23 00 +2A C7 D6 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +72 C7 0A C4 40 FF 32 C4 9E C8 A2 C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B2 +01 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 43 06 02 B2 40 FC FF +02 02 F2 D3 26 02 F2 43 22 02 F2 40 A5 00 A1 01 +F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 60 01 +82 43 88 01 F2 D0 03 00 0B 02 F2 C3 82 01 F2 D0 +0A 00 82 01 B2 40 E8 01 84 01 39 40 80 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 39 40 00 10 29 83 +89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 3E F3 +02 20 1E 42 5E 01 B0 12 D0 C4 80 C5 00 00 0C 41 +43 43 45 50 54 00 30 40 AA C6 0A 4E 2E 4F 0A 5E +3B 40 0A 00 3C 40 20 00 3D 15 A2 3E 21 52 A2 C2 +6C 05 B2 B0 10 00 40 05 9B 22 3A 17 92 B3 6C 05 +FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 +F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B +45 59 30 40 06 C7 58 43 B0 12 46 C5 2F 83 8F 4E +00 00 92 B3 6C 05 FD 27 1E 42 4C 05 B0 12 44 C5 +30 4D 00 00 08 45 4D 49 54 00 30 40 2E C7 08 4E +3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D 24 C7 +08 45 43 48 4F 00 B2 40 C2 48 38 C7 38 40 05 00 +B0 12 46 C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 38 C7 28 42 F3 3F 00 00 08 54 59 50 +45 00 0D 12 3D 40 82 C7 29 4F 8F 4E 00 00 7E 49 +D4 3F 84 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 87 22 F9 98 00 00 84 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 7B 22 9B 24 FE C6 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 +A2 C8 94 C7 E6 C9 A0 CC B0 C4 10 C8 14 C4 06 5B +54 48 45 4E 5D 00 98 C7 EE C7 B4 C7 D2 C7 14 C4 +06 5B 45 4C 53 45 5D 00 98 C7 00 C8 B4 C7 D0 C7 +1E C4 04 5B 49 46 5D 00 98 C7 D2 C7 B2 C4 D0 C7 +1E C4 05 0D 6B 6F 20 0A 72 C7 9A C4 84 C4 B2 C4 +D2 C7 C0 C7 0D 5B 54 48 45 4E 5D 00 30 4D 24 C8 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 30 C8 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 94 C7 +E6 C9 4E CA F2 CB 62 C9 40 C8 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 94 C7 E6 C9 4E CA +72 C8 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D 9E C6 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D E0 C5 05 53 22 00 +82 43 C0 21 0D 12 84 12 0A C4 1E C4 50 CC 0A C4 +22 00 E6 C9 E6 C8 B2 40 20 00 C0 21 1A 53 1A B3 +82 6A C8 21 3E 4F 3D 41 30 4D 58 C7 05 2E 22 00 +0D 12 84 12 D0 C8 0A C4 72 C7 50 CC 62 C9 00 00 +04 3C 23 00 B2 40 B2 21 B2 21 30 4D CC C8 02 23 +1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 21 18 42 B2 21 C8 4A 00 00 30 4D 1E C9 04 23 +53 00 0D 12 84 12 20 C9 5A C9 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 4E C9 04 23 3E 00 9F 42 B2 21 +00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F 68 C9 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 40 C7 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +14 C9 94 C7 82 C9 52 C9 7E C8 90 C9 6C C9 72 C7 +62 C9 FC C8 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D D4 C9 +0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F +29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 +7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C +82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 +09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 +02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E +06 00 08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 +3D 40 58 CB 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F +2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 +5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C +01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 +FC 9C 00 00 E0 23 AE 27 5A CB 2F 24 2D 83 6A 4C +7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 +7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 +02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F +04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 +00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 +04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 +BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 +01 20 2F 53 30 4D 10 C9 03 5C 92 42 C2 21 C6 21 +30 4D 0D 12 84 12 84 C4 94 C7 E6 C9 B0 C4 2A CD +4E CA 14 CC 0A 4E 3E 4F 3D 40 2E CC 6D 27 3D 40 +08 CC 1A E2 BC 21 14 24 0E 12 3E 4F 30 41 30 CC +3E 4F 3D 40 08 CC 19 20 DE 53 00 00 68 4E 08 5E +F8 40 3F 00 00 00 3D 40 06 CE 2A 3C F8 CB 02 2C +A2 53 C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D +4E CC 0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 +09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 +8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +8A 4E 02 00 EE 3F 30 4D 8A C9 0A 43 4F 55 4E 54 +2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D B0 C8 +0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 +80 20 0E 43 84 12 1E C4 02 0D 0A 00 72 C7 94 C4 +02 CC 90 C8 BA C8 1E C4 0B 73 74 61 63 6B 20 65 +6D 70 74 79 08 C5 32 C4 0A C4 40 FF C2 C8 1E C4 +09 46 52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 C6 CC +B0 CC 0D 41 42 4F 52 54 22 00 0D 12 84 12 D0 C8 +0A C4 08 C5 50 CC 62 C9 E0 C9 02 27 0D 12 84 12 +94 C7 E6 C9 4E CA B0 C4 2C CD F4 C8 38 CC 5A C8 +07 5B 27 5D 0D 12 84 12 1C CD 0A C4 0A C4 50 CC +50 CC 62 C9 30 CD 03 5B 82 43 BC 21 30 4D 00 00 +02 5D B2 43 BC 21 30 4D A8 C8 11 50 4F 53 54 50 +4F 4E 45 00 0D 12 84 12 94 C7 E6 C9 4E CA B0 C4 +2C CD BA C8 AC C4 84 CD 0A C4 0A C4 50 CC 50 CC +0A C4 50 CC 50 CC 62 C9 00 00 02 3A 30 12 DA CD +92 B3 C8 21 A2 63 C8 21 0D 12 84 12 94 C7 E6 C9 +A2 CD 3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E +5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +00 00 82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F +BA 21 2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF +BA 40 84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 +66 25 84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 +6D 61 74 63 68 21 12 C5 46 CD 03 3B 82 93 BC 21 +F4 26 0D 12 84 12 0A C4 62 C9 50 CC EC CD 48 CD +62 C9 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +B4 21 D8 D3 00 00 30 4D 9A CC 0C 43 52 45 41 54 +45 00 B0 12 90 CD BA 40 86 12 FC FF 8A 4A FE FF +3A 3D 6C C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 +85 12 00 00 8A 4D 02 00 3D 41 30 4D 8A CD 0E 3A +4E 4F 4E 41 4D 45 30 12 DA CD 2F 83 8F 4E 00 00 +1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +98 3F 24 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 +84 12 1C CD A6 CE 3D 41 BE 4F 02 00 3E 4F 30 4D +84 12 34 CD 0A C4 A8 CE 50 CC 62 C9 3A CE 08 43 +4F 44 45 00 B0 12 90 CD A2 82 C8 21 61 3C 7C C9 +0E 48 44 4E 43 4F 44 45 B2 40 94 CF CC 21 F2 3F +00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 EC CD +F2 CE 3D 41 92 42 D0 21 CC 21 5D 3C BE CE 0E 43 +4F 44 45 4E 4E 4D 30 12 C8 CE B7 3F 00 00 0A 43 +4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 +84 12 02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 +0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F +D0 CE 0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 +8A 4A FE FF 82 43 BC 21 B9 3F 5C CF B2 40 6E CF +D0 21 82 4E CE 21 30 40 F4 C8 85 12 5A CF 5A CD +02 CD EC CF FE CE 54 CE 9E C9 48 CA 1A CD 42 CF +94 CE 6E CE 0A CE 62 CC 76 D0 A0 CA 00 00 00 00 +85 12 5A CF F0 D6 74 D5 D4 D6 9C D4 F8 D4 46 D5 +22 D6 2E D6 BE D3 E2 D4 00 00 00 00 30 CF AE D2 +00 00 4A D6 8E CF B2 40 6E CF CE 21 82 43 D0 21 +30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 +30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 +3A 40 42 18 B0 12 C2 CF 30 4D D4 CF 0E 52 53 54 +5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 +C2 CF 1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 +18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 +2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 +29 83 B9 43 80 FF FC 23 B9 40 0E C6 FE FF 29 83 +B9 40 FA C5 FE FF 39 90 AE FF F9 23 39 40 10 18 +B2 49 E0 FF 3B 40 10 00 3A 40 3A 18 B0 12 C6 CF +82 43 4A 18 C7 3F 68 D0 B2 4E 42 18 BE 12 3E 4F +3D 41 C0 3F 50 CD 0C 4D 41 52 4B 45 52 00 12 12 +C6 21 0D 12 84 12 94 C7 E6 C9 4E CA AC C4 94 D0 +88 C8 28 CC 96 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 +90 CD BA 40 85 12 FC FF BA 40 66 D0 FE FF 28 83 +8A 48 00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 +B4 21 19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D +12 12 C6 21 84 12 E6 C9 4E CA AC C4 00 D1 E0 D0 +3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C +BE 90 66 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 +F8 CA AC C4 08 D1 FC D0 0A D1 B2 41 C6 21 30 41 +92 83 C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 D0 D0 +15 20 3E 40 2B 00 B0 12 D0 D0 06 20 3E 40 2D 00 +B0 12 D0 D0 92 83 C6 21 0E 12 1E 41 02 00 84 12 +E6 C9 F8 CA AC C4 2C CD 4A D1 3E 51 3A 17 30 41 +B0 12 10 D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 +3E 40 29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 +E6 C9 F8 CA AC C4 82 D1 7A D1 3E 90 10 00 E6 2B +7C 2D 84 D1 A2 41 C6 21 E1 3F 03 20 B0 12 68 D1 +43 3C 7A 90 23 00 24 20 B0 12 18 D1 3C 40 00 03 +0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 +2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 +3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 +19 42 C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D +7A 90 26 00 05 20 3C 40 10 02 B0 12 18 D1 F0 3F +7A 90 40 00 14 20 3C 40 20 00 B0 12 64 D1 0C 20 +3C D0 10 00 3E 40 2B 00 B0 12 68 D1 92 92 C2 21 +C6 21 02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 +10 00 B0 12 50 D1 F2 3F 03 20 B0 12 68 D1 F5 3F +7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 +B0 12 50 D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 +3A 40 20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 +5A 49 FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 +30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 +00 13 50 CC 62 C9 0A C4 2C 00 46 D2 8A D1 94 C7 +50 D2 28 D2 96 D2 3D 41 2C DE 8B 4C 00 00 9E 3F +00 00 06 4D 4F 56 85 12 86 D2 00 40 A2 D2 0A 4D +4F 56 2E 42 85 12 86 D2 40 40 00 00 06 41 44 44 +85 12 86 D2 00 50 BC D2 0A 41 44 44 2E 42 85 12 +86 D2 40 50 C8 D2 08 41 44 44 43 00 85 12 86 D2 +00 60 D6 D2 0C 41 44 44 43 2E 42 00 85 12 86 D2 +40 60 0E CF 08 53 55 42 43 00 85 12 86 D2 00 70 +F4 D2 0C 53 55 42 43 2E 42 00 85 12 86 D2 40 70 +02 D3 06 53 55 42 85 12 86 D2 00 80 12 D3 0A 53 +55 42 2E 42 85 12 86 D2 40 80 1E D3 06 43 4D 50 +85 12 86 D2 00 90 2C D3 0A 43 4D 50 2E 42 85 12 +86 D2 40 90 00 00 08 44 41 44 44 00 85 12 86 D2 +00 A0 46 D3 0C 44 41 44 44 2E 42 00 85 12 86 D2 +40 A0 74 D2 06 42 49 54 85 12 86 D2 00 B0 64 D3 +0A 42 49 54 2E 42 85 12 86 D2 40 B0 70 D3 06 42 +49 43 85 12 86 D2 00 C0 7E D3 0A 42 49 43 2E 42 +85 12 86 D2 40 C0 8A D3 06 42 49 53 85 12 86 D2 +00 D0 98 D3 0A 42 49 53 2E 42 85 12 86 D2 40 D0 +00 00 06 58 4F 52 85 12 86 D2 00 E0 B2 D3 0A 58 +4F 52 2E 42 85 12 86 D2 40 E0 E4 D2 06 41 4E 44 +85 12 86 D2 00 F0 CC D3 0A 41 4E 44 2E 42 85 12 +86 D2 40 F0 94 C7 46 D2 8A D1 EC D3 0A 4C 3C F0 +70 00 8A 10 3A F0 0F 00 0C DA 4D 3F A4 D3 06 52 +52 43 85 12 E4 D3 00 10 FE D3 0A 52 52 43 2E 42 +85 12 E4 D3 40 10 38 D3 08 53 57 50 42 00 85 12 +E4 D3 80 10 0A D4 06 52 52 41 85 12 E4 D3 00 11 +26 D4 0A 52 52 41 2E 42 85 12 E4 D3 40 11 18 D4 +06 53 58 54 85 12 E4 D3 80 11 00 00 08 50 55 53 +48 00 85 12 E4 D3 00 12 4C D4 0C 50 55 53 48 2E +42 00 85 12 E4 D3 40 12 40 D4 08 43 41 4C 4C 00 +85 12 E4 D3 80 12 1A 53 0E 4A 84 12 D6 C9 1E C4 +0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 +6A D4 06 53 3E 3D 86 12 00 38 92 D4 04 53 3C 00 +86 12 00 34 5A D4 06 30 3E 3D 86 12 00 30 A6 D4 +04 30 3C 00 86 12 00 30 E2 CE 04 55 3C 00 86 12 +00 2C BA D4 06 55 3E 3D 86 12 00 28 B0 D4 06 30 +3C 3E 86 12 00 24 CE D4 04 30 3D 00 86 12 00 20 +00 00 04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 +C8 21 0E 4A 30 4D 54 D3 08 54 48 45 4E 00 1A 42 +C8 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 +00 02 B2 2F 88 DA 00 00 30 4D C4 D4 08 45 4C 53 +45 00 1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 +2F 83 8F 4A 00 00 E3 3F 32 D4 0A 42 45 47 49 4E +30 40 32 C4 1C D5 0A 55 4E 54 49 4C 3A 4F 08 4E +3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE +8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 +30 4D D8 D3 0A 41 47 41 49 4E 0A 4E 38 40 00 3C +E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 E6 D4 +7C C8 62 C9 3A D5 0C 52 45 50 45 41 54 00 0D 12 +84 12 7A D5 FE D4 62 C9 AA D5 3D 41 08 4E 3E 4F +2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D +96 D5 06 42 57 31 85 12 A8 D5 00 00 C2 D5 06 42 +57 32 85 12 A8 D5 00 00 CE D5 06 42 57 33 85 12 +A8 D5 00 00 E6 D5 3D 41 1A 42 C8 21 28 4E 8E 43 +00 00 B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 +8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 +E4 D5 00 00 0A D6 06 46 57 32 85 12 E4 D5 00 00 +16 D6 06 46 57 33 85 12 E4 D5 00 00 84 D5 08 47 +4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 +84 12 1C CD 28 CC 62 C9 00 00 0A 3F 47 4F 54 4F +3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 +3E E0 00 08 EC 3F 50 D2 0A C4 2C 00 E6 C9 F8 CA +AC C4 2C CD 94 C7 46 D2 28 D2 7C D6 0A 4E 3E 4F +1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 +0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 +EA 2E 8A 10 5A 06 A8 3E DA D5 08 52 52 43 4D 00 +85 12 66 D6 50 00 AA D6 08 52 52 41 4D 00 85 12 +66 D6 50 01 B8 D6 08 52 4C 41 4D 00 85 12 66 D6 +50 02 C6 D6 08 52 52 55 4D 00 85 12 66 D6 50 03 +D8 D4 0A 50 55 53 48 4D 85 12 66 D6 00 15 E2 D6 +08 50 4F 50 4D 00 85 12 66 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -82 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 08 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +BC C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR2433_16MHz_UART.txt b/binaries/MSP_EXP430FR2433_16MHz_UART.txt deleted file mode 100644 index b5bfa6c..0000000 --- a/binaries/MSP_EXP430FR2433_16MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF FA D7 02 D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 FA D7 -02 D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 28 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 D2 D3 02 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 D2 C3 02 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 14 CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -5A CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -5A CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 14 CC 2C C9 D0 CB -9C 26 3D 40 D8 CB DE 3E DA CB 0A 4E 3E 4F 3D 40 -F4 CB 36 27 3D 40 CA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 CB 3E 4F 3D 40 CA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CD -CC 3F FE CB 86 12 20 00 E6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E C7 -BC C4 C4 CB C4 C7 F6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -FE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 3E CC 1A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C8 0A C4 2A C5 5A CB 60 C8 8E C9 -01 27 0D 12 84 12 14 CC 2C C9 94 C9 34 C4 12 CC -60 C8 00 00 83 5B 27 5D 0D 12 84 12 92 CC 0A C4 -0A C4 5A CB 5A CB 60 C8 A4 CC 81 5B 82 43 BE 21 -30 4D 0C C8 01 5D B2 43 BE 21 30 4D C4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CC 2C C9 94 C9 A8 C7 -34 C4 12 CC F6 C7 34 C4 06 CD 0A C4 0A C4 5A CB -5A CB 0A C4 5A CB 5A CB 60 C8 BA CC 01 3A 30 12 -56 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 CC -2C C9 24 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 0C CD 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 60 C8 5A CB 68 CD BC CC -60 C8 BA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 CB 06 43 52 45 -41 54 45 00 B0 12 12 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CD 04 43 4F 44 45 00 B0 12 12 CD -A2 82 C6 21 0D 12 84 12 04 D0 DE CF 60 C8 B4 CD -07 48 44 4E 43 4F 44 45 B2 40 E2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CD -1E D0 3C D0 60 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E D0 3C D0 60 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 CE 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -AC CF 5A CB BC CC F4 CD 60 C8 9A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 D8 C7 14 CC 2C C9 -AA CB A0 C7 34 C4 14 CF AE C7 14 C4 06 5B 54 48 -45 4E 5D 00 86 CE EE CE AA CE CC CE 60 C8 AE C7 -14 C4 06 5B 45 4C 53 45 5D 00 86 CE 04 CF AA CE -CA CE 60 C8 14 C4 04 5B 49 46 5D 00 86 CE CC CE -3A C4 CA CE 82 C7 14 C4 05 0D 0A 6B 6F 20 5C C7 -BC C4 AC C4 3A C4 CC CE BA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CC 2C C9 -94 C9 38 CF 60 C8 3E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CF F0 C7 60 C8 70 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C CB -06 4D 41 52 4B 45 52 00 B0 12 12 CD BA 40 85 12 -FC FF BA 40 6E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 E8 C7 60 C8 85 12 B0 CF 78 CC E6 CD -2C C7 90 CC 64 CE F6 C6 80 CF 12 C9 A8 D0 BC D0 -9C C8 26 C9 00 00 58 CF CE CC F4 C9 00 00 85 12 -B0 CF 70 D6 D6 D6 18 D6 26 D7 DE D5 00 00 AA D3 -00 00 EE D7 D2 D7 42 D6 80 D6 BA D4 00 00 00 00 -42 D7 DC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 CF 36 D0 3C D0 4C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CC 09 50 57 52 5F 53 54 41 54 45 85 12 44 D0 -FA D7 E0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 D0 F3 3F 82 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 D0 30 4D 94 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A D1 FE FF 29 83 -B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 20 C6 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 -26 02 F2 43 22 02 F2 40 A5 00 A1 01 F2 40 10 00 -A0 01 D2 43 A1 01 B2 40 00 A5 60 01 B2 40 FF 1E -80 01 B2 40 BA 00 82 01 B2 40 E8 01 84 01 82 43 -88 01 F2 D0 03 00 0B 02 39 40 80 00 18 42 00 18 -18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 -1E D2 5E 01 B0 12 F8 C4 1E C6 38 40 C0 21 0A 4E -39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E -FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 -0E 12 12 12 C4 21 84 12 2C C9 94 C9 F0 C7 34 C4 -EA D1 50 CA 34 C4 04 D2 FE D1 EC D1 3C 4E 3C 80 -87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 -1B 17 30 41 06 D2 B2 41 C4 21 3E 41 84 12 0A C4 -2B 00 2C C9 94 C9 F0 C7 34 C4 22 D2 50 CA 34 C4 -12 CC BA C7 2C C9 50 CA 34 C4 12 CC 2E D2 3E 5F -E7 3F 3E 40 28 00 B0 12 CE D1 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 -02 20 30 40 80 CD 1C 15 12 12 C4 21 92 53 C4 21 -84 12 2C C9 50 CA 34 C4 76 D2 6C D2 21 53 3E 90 -10 00 C6 2B 7F 2D 78 D2 B2 41 C4 21 C1 3F 0D 12 -84 12 14 CC AA D1 88 D2 0C 43 1B 42 C6 21 A2 53 -C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 -B0 12 CE D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 -1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 -2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 -3C 40 10 02 92 53 C4 21 B0 12 CE D1 ED 3F 7A 90 -40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 56 D2 -0C 20 3C 50 10 00 3E 40 2B 00 B0 12 56 D2 92 92 -C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F -B0 12 56 D2 FA 23 3C 50 10 00 B0 12 32 D2 EF 3F -0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 CC -AA D1 54 D3 FE 90 26 00 00 00 3E 40 20 00 03 20 -3C 50 82 00 C7 3F B0 12 56 D2 E0 23 3C 50 80 00 -B0 12 32 D2 DB 3F 00 00 04 52 45 54 49 00 0D 12 -84 12 0A C4 00 13 5A CB 60 C8 0A C4 2C 00 7E D2 -4A D3 94 D3 09 4B 2E 4E 0E DC A2 3F 52 CE 03 4D -4F 56 85 12 8A D3 00 40 9E D3 05 4D 4F 56 2E 42 -85 12 8A D3 40 40 00 00 03 41 44 44 85 12 8A D3 -00 50 B8 D3 05 41 44 44 2E 42 85 12 8A D3 40 50 -C4 D3 04 41 44 44 43 00 85 12 8A D3 00 60 D2 D3 -06 41 44 44 43 2E 42 00 85 12 8A D3 40 60 78 D3 -04 53 55 42 43 00 85 12 8A D3 00 70 F0 D3 06 53 -55 42 43 2E 42 00 85 12 8A D3 40 70 FE D3 03 53 -55 42 85 12 8A D3 00 80 0E D4 05 53 55 42 2E 42 -85 12 8A D3 40 80 28 CE 03 43 4D 50 85 12 8A D3 -00 90 28 D4 05 43 4D 50 2E 42 85 12 8A D3 40 90 -12 CE 04 44 41 44 44 00 85 12 8A D3 00 A0 42 D4 -06 44 41 44 44 2E 42 00 85 12 8A D3 40 A0 34 D4 -03 42 49 54 85 12 8A D3 00 B0 60 D4 05 42 49 54 -2E 42 85 12 8A D3 40 B0 6C D4 03 42 49 43 85 12 -8A D3 00 C0 7A D4 05 42 49 43 2E 42 85 12 8A D3 -40 C0 86 D4 03 42 49 53 85 12 8A D3 00 D0 94 D4 -05 42 49 53 2E 42 85 12 8A D3 40 D0 00 00 03 58 -4F 52 85 12 8A D3 00 E0 AE D4 05 58 4F 52 2E 42 -85 12 8A D3 40 E0 E0 D3 03 41 4E 44 85 12 8A D3 -00 F0 C8 D4 05 41 4E 44 2E 42 85 12 8A D3 40 F0 -14 CC 7E D2 E6 D4 0A 4C 3C F0 70 00 8A 10 3A F0 -0F 00 0C DA 4F 3F 1A D4 03 52 52 43 85 12 E0 D4 -00 10 F8 D4 05 52 52 43 2E 42 85 12 E0 D4 40 10 -04 D5 04 53 57 50 42 00 85 12 E0 D4 80 10 12 D5 -03 52 52 41 85 12 E0 D4 00 11 20 D5 05 52 52 41 -2E 42 85 12 E0 D4 40 11 2C D5 03 53 58 54 85 12 -E0 D4 80 11 00 00 04 50 55 53 48 00 85 12 E0 D4 -00 12 46 D5 06 50 55 53 48 2E 42 00 85 12 E0 D4 -40 12 A0 D4 04 43 41 4C 4C 00 85 12 E0 D4 80 12 -1A 53 0E 4A 0D 12 84 12 D6 C8 14 C4 0D 6F 75 74 -20 6F 66 20 62 6F 75 6E 64 73 36 C5 3A D5 03 53 -3E 3D 86 12 00 38 8E D5 02 53 3C 00 86 12 00 34 -54 D5 03 30 3E 3D 86 12 00 30 A2 D5 02 30 3C 00 -86 12 00 30 00 00 02 55 3C 00 86 12 00 2C B6 D5 -03 55 3E 3D 86 12 00 28 AC D5 03 30 3C 3E 86 12 -00 24 CA D5 02 30 3D 00 86 12 00 20 00 00 02 49 -46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A -30 4D C0 D5 04 54 48 45 4E 00 1A 42 C6 21 08 4E -3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F -88 DA 00 00 30 4D 50 D4 04 45 4C 53 45 00 1A 42 -C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A -00 00 E3 3F 64 D5 05 42 45 47 49 4E 30 40 28 C4 -F4 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 -C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 -FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D D4 D4 -05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 -05 57 48 49 4C 45 0D 12 84 12 E2 D5 BA C7 60 C8 -98 D5 06 52 45 50 45 41 54 00 0D 12 84 12 76 D6 -FA D5 60 C8 A6 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 -C4 21 CB 2F 98 42 C6 21 00 00 30 4D 36 D6 03 42 -57 31 85 12 A4 D6 00 00 BE D6 03 42 57 32 85 12 -A4 D6 00 00 CA D6 03 42 57 33 85 12 A4 D6 00 00 -E2 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B -BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D -00 00 03 46 57 31 85 12 E0 D6 00 00 02 D7 03 46 -57 32 85 12 E0 D6 00 00 0E D7 03 46 57 33 85 12 -E0 D6 00 00 1A D7 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C 0D 12 84 12 92 CC EE CB 60 C8 -00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 -00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 CC -AA D1 64 D7 92 53 C4 21 3E 40 2C 00 84 12 2C C9 -50 CA 34 C4 12 CC 40 D3 7A D7 0A 4E 3E 4F 1A 83 -F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A -08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E -8A 10 5A 06 A6 3E 92 D6 04 52 52 43 4D 00 85 12 -5E D7 50 00 A8 D7 04 52 52 41 4D 00 85 12 5E D7 -50 01 B6 D7 04 52 4C 41 4D 00 85 12 5E D7 50 02 -C4 D7 04 52 52 55 4D 00 85 12 5E D7 50 03 D4 D5 -05 50 55 53 48 4D 85 12 5E D7 00 15 E0 D7 04 50 -4F 50 4D 00 85 12 5E D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 94 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1A D1 -q diff --git a/binaries/MSP_EXP430FR2433_1MHz_115200.txt b/binaries/MSP_EXP430FR2433_1MHz_115200.txt new file mode 100644 index 0000000..3c6b20e --- /dev/null +++ b/binaries/MSP_EXP430FR2433_1MHz_115200.txt @@ -0,0 +1,323 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A0 59 +AC C6 7E C5 84 C5 54 C5 1C C7 0A D7 C2 CF 7C CF +7C CF 92 C6 50 C7 18 C7 3C 21 E0 20 70 C9 B6 C4 +C4 C4 8C C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +1C C7 0A D7 C2 CF 7C CF 7C CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F1 3C 0E 93 3E 4F +86 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 90 C6 B2 49 +4E C7 B2 49 16 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 36 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 1C C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 96 C8 AC C4 52 C5 5E C7 1E C4 04 1B +5B 37 6D 00 80 C7 80 C7 1E C4 04 1B 5B 30 6D 00 +80 C7 CC CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 5E C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 80 C7 E4 C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 80 C7 0A C4 40 FF 32 C4 +AC C8 B0 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B2 01 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 +26 02 F2 43 22 02 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 03 00 0B 02 F2 C3 82 01 B2 40 1E 00 84 01 +39 40 80 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 10 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 C4 86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 +92 C6 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 F0 C6 3C 40 FC C6 5D 15 AA 3E 21 52 3A 17 +58 42 0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 +13 00 0E 05 D2 D3 02 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D +F2 C6 2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 18 C7 30 12 2E C7 A2 B3 1C 05 +FD 27 B2 40 11 00 0E 05 D2 C3 02 02 30 41 2F 83 +8F 4E 00 00 92 B3 1C 05 FD 27 B0 12 B8 C6 1E 42 +0C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 50 C7 +08 4E 3E 4F C7 3F 46 C7 08 45 43 48 4F 00 B2 40 +C2 48 EA C6 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D EA C6 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 90 C7 29 4F 8F 4E 00 00 7E 49 DE 3F +92 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +80 22 F9 98 00 00 7D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 74 22 9B 24 10 C7 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 B0 C8 +A2 C7 F4 C9 AE CC B0 C4 1E C8 14 C4 06 5B 54 48 +45 4E 5D 00 A6 C7 FC C7 C2 C7 E0 C7 14 C4 06 5B +45 4C 53 45 5D 00 A6 C7 0E C8 C2 C7 DE C7 1E C4 +04 5B 49 46 5D 00 A6 C7 E0 C7 B2 C4 DE C7 1E C4 +05 0D 6B 6F 20 0A 80 C7 9A C4 84 C4 B2 C4 E0 C7 +CE C7 0D 5B 54 48 45 4E 5D 00 30 4D 32 C8 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 3E C8 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 A2 C7 F4 C9 +5C CA 00 CC 70 C9 4E C8 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 A2 C7 F4 C9 5C CA 80 C8 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D 86 C6 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A C4 1E C4 5E CC 0A C4 22 00 +F4 C9 F4 C8 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 68 C7 05 2E 22 00 0D 12 +84 12 DE C8 0A C4 80 C7 5E CC 70 C9 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D DA C8 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 2C C9 04 23 53 00 +0D 12 84 12 2E C9 68 C9 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 5C C9 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 76 C9 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 58 C7 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 22 C9 +A2 C7 90 C9 60 C9 8C C8 9E C9 7A C9 80 C7 70 C9 +0A C9 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D E2 C9 0E 3E +4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 +66 CB 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 68 CB 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 1E C9 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 C4 A2 C7 F4 C9 B0 C4 38 CD 5C CA +22 CC 0A 4E 3E 4F 3D 40 3C CC 6D 27 3D 40 16 CC +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 3E CC 3E 4F +3D 40 16 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 14 CE 2A 3C 06 CC 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D 5C CC +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D 98 C9 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D BE C8 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E C4 02 0D 0A 00 80 C7 94 C4 10 CC +9E C8 C8 C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C5 32 C4 0A C4 40 FF D0 C8 1E C4 09 46 +52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 D4 CC BE CC +0D 41 42 4F 52 54 22 00 0D 12 84 12 DE C8 0A C4 +08 C5 5E CC 70 C9 EE C9 02 27 0D 12 84 12 A2 C7 +F4 C9 5C CA B0 C4 3A CD 02 C9 46 CC 68 C8 07 5B +27 5D 0D 12 84 12 2A CD 0A C4 0A C4 5E CC 5E CC +70 C9 3E CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D B6 C8 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 A2 C7 F4 C9 5C CA B0 C4 3A CD +C8 C8 AC C4 92 CD 0A C4 0A C4 5E CC 5E CC 0A C4 +5E CC 5E CC 70 C9 00 00 02 3A 30 12 E8 CD 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 A2 C7 F4 C9 B0 CD +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C5 54 CD 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A C4 70 C9 5E CC FA CD 56 CD 70 C9 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D A8 CC 0C 43 52 45 41 54 45 00 +B0 12 9E CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +7A C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D 98 CD 0E 3A 4E 4F +4E 41 4D 45 30 12 E8 CD 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +32 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +2A CD B4 CE 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +42 CD 0A C4 B6 CE 5E CC 70 C9 48 CE 08 43 4F 44 +45 00 B0 12 9E CD A2 82 C8 21 61 3C 8A C9 0E 48 +44 4E 43 4F 44 45 B2 40 A2 CF CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 FA CD 00 CF +3D 41 92 42 D0 21 CC 21 5D 3C CC CE 0E 43 4F 44 +45 4E 4E 4D 30 12 D6 CE B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F DE CE +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F 6A CF B2 40 7C CF D0 21 +82 4E CE 21 30 40 02 C9 85 12 68 CF 68 CD 10 CD +FA CF 0C CF 62 CE AC C9 56 CA 28 CD 50 CF A2 CE +7C CE 18 CE 70 CC 84 D0 AE CA 00 00 00 00 85 12 +68 CF FE D6 82 D5 E2 D6 AA D4 06 D5 54 D5 30 D6 +3C D6 CC D3 F0 D4 00 00 00 00 3E CF BC D2 00 00 +58 D6 9C CF B2 40 7C CF CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 D0 CF 30 4D E2 CF 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 D0 CF +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 C6 FE FF 29 83 B9 40 +F2 C5 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E4 FF 3B 40 10 00 3A 40 3A 18 B0 12 D4 CF 82 43 +4A 18 C7 3F 76 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 5E CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 A2 C7 F4 C9 5C CA AC C4 A2 D0 96 C8 +36 CC A4 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 9E CD +BA 40 85 12 FC FF BA 40 74 D0 FE FF 28 83 8A 48 +00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 F4 C9 5C CA AC C4 0E D1 EE D0 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +74 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 06 CB +AC C4 16 D1 0A D1 18 D1 B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 DE D0 15 20 +3E 40 2B 00 B0 12 DE D0 06 20 3E 40 2D 00 B0 12 +DE D0 92 83 C6 21 0E 12 1E 41 02 00 84 12 F4 C9 +06 CB AC C4 3A CD 58 D1 3E 51 3A 17 30 41 B0 12 +1E D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 F4 C9 +06 CB AC C4 90 D1 88 D1 3E 90 10 00 E6 2B 7C 2D +92 D1 A2 41 C6 21 E1 3F 03 20 B0 12 76 D1 43 3C +7A 90 23 00 24 20 B0 12 26 D1 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 26 D1 F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 72 D1 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 76 D1 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 5E D1 F2 3F 03 20 B0 12 76 D1 F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +5E D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 +5E CC 70 C9 0A C4 2C 00 54 D2 98 D1 A2 C7 5E D2 +36 D2 A4 D2 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 94 D2 00 40 B0 D2 0A 4D 4F 56 +2E 42 85 12 94 D2 40 40 00 00 06 41 44 44 85 12 +94 D2 00 50 CA D2 0A 41 44 44 2E 42 85 12 94 D2 +40 50 D6 D2 08 41 44 44 43 00 85 12 94 D2 00 60 +E4 D2 0C 41 44 44 43 2E 42 00 85 12 94 D2 40 60 +1C CF 08 53 55 42 43 00 85 12 94 D2 00 70 02 D3 +0C 53 55 42 43 2E 42 00 85 12 94 D2 40 70 10 D3 +06 53 55 42 85 12 94 D2 00 80 20 D3 0A 53 55 42 +2E 42 85 12 94 D2 40 80 2C D3 06 43 4D 50 85 12 +94 D2 00 90 3A D3 0A 43 4D 50 2E 42 85 12 94 D2 +40 90 00 00 08 44 41 44 44 00 85 12 94 D2 00 A0 +54 D3 0C 44 41 44 44 2E 42 00 85 12 94 D2 40 A0 +82 D2 06 42 49 54 85 12 94 D2 00 B0 72 D3 0A 42 +49 54 2E 42 85 12 94 D2 40 B0 7E D3 06 42 49 43 +85 12 94 D2 00 C0 8C D3 0A 42 49 43 2E 42 85 12 +94 D2 40 C0 98 D3 06 42 49 53 85 12 94 D2 00 D0 +A6 D3 0A 42 49 53 2E 42 85 12 94 D2 40 D0 00 00 +06 58 4F 52 85 12 94 D2 00 E0 C0 D3 0A 58 4F 52 +2E 42 85 12 94 D2 40 E0 F2 D2 06 41 4E 44 85 12 +94 D2 00 F0 DA D3 0A 41 4E 44 2E 42 85 12 94 D2 +40 F0 A2 C7 54 D2 98 D1 FA D3 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F B2 D3 06 52 52 43 +85 12 F2 D3 00 10 0C D4 0A 52 52 43 2E 42 85 12 +F2 D3 40 10 46 D3 08 53 57 50 42 00 85 12 F2 D3 +80 10 18 D4 06 52 52 41 85 12 F2 D3 00 11 34 D4 +0A 52 52 41 2E 42 85 12 F2 D3 40 11 26 D4 06 53 +58 54 85 12 F2 D3 80 11 00 00 08 50 55 53 48 00 +85 12 F2 D3 00 12 5A D4 0C 50 55 53 48 2E 42 00 +85 12 F2 D3 40 12 4E D4 08 43 41 4C 4C 00 85 12 +F2 D3 80 12 1A 53 0E 4A 84 12 E4 C9 1E C4 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 78 D4 +06 53 3E 3D 86 12 00 38 A0 D4 04 53 3C 00 86 12 +00 34 68 D4 06 30 3E 3D 86 12 00 30 B4 D4 04 30 +3C 00 86 12 00 30 F0 CE 04 55 3C 00 86 12 00 2C +C8 D4 06 55 3E 3D 86 12 00 28 BE D4 06 30 3C 3E +86 12 00 24 DC D4 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D 62 D3 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D D2 D4 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 40 D4 0A 42 45 47 49 4E 30 40 +32 C4 2A D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +E6 D3 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 F4 D4 8A C8 +70 C9 48 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 +88 D5 0C D5 70 C9 B8 D5 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D A4 D5 +06 42 57 31 85 12 B6 D5 00 00 D0 D5 06 42 57 32 +85 12 B6 D5 00 00 DC D5 06 42 57 33 85 12 B6 D5 +00 00 F4 D5 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 F2 D5 +00 00 18 D6 06 46 57 32 85 12 F2 D5 00 00 24 D6 +06 46 57 33 85 12 F2 D5 00 00 92 D5 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +2A CD 36 CC 70 C9 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 5E D2 0A C4 2C 00 F4 C9 06 CB AC C4 +3A CD A2 C7 54 D2 36 D2 8A D6 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E E8 D5 08 52 52 43 4D 00 85 12 +74 D6 50 00 B8 D6 08 52 52 41 4D 00 85 12 74 D6 +50 01 C6 D6 08 52 4C 41 4D 00 85 12 74 D6 50 02 +D4 D6 08 52 52 55 4D 00 85 12 74 D6 50 03 E6 D4 +0A 50 55 53 48 4D 85 12 74 D6 00 15 F0 D6 08 50 +4F 50 4D 00 85 12 74 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 AC C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR2433_1MHz_I2C.txt b/binaries/MSP_EXP430FR2433_1MHz_I2C.txt index 8e2adf1..93b1202 100644 --- a/binaries/MSP_EXP430FR2433_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2433_1MHz_I2C.txt @@ -1,334 +1,321 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF D4 D7 F0 CF 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 D4 D7 -F0 CF 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +A6 C6 56 C5 56 C5 58 C5 44 C5 E6 D6 9E CF 58 CF +58 CF 94 C6 18 C7 F0 C6 3C 21 E0 20 4C C9 B6 C4 +C4 C4 68 C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 E6 D6 9E CF 58 CF 58 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 16 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F2 3C 0E 93 3E 4F +74 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 92 C6 B2 49 +16 C7 B2 49 EE C6 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 12 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 72 C8 AC C4 +42 C5 30 C7 1E C4 05 1B 5B 37 6D 40 5C C7 0A C4 +02 18 94 C8 C0 C9 5C C7 1E C4 04 1B 5B 30 6D 00 +5C C7 A8 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 30 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 5C C7 0A C4 02 18 94 C8 C0 C9 0A C4 23 00 +14 C7 C0 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +5C C7 0A C4 40 FF 32 C4 88 C8 8C C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B2 +01 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 43 06 02 B2 40 FC FF +02 02 F2 D3 26 02 F2 43 22 02 B2 40 00 A5 60 01 +82 43 88 01 F2 D0 03 00 0B 02 F2 C3 82 01 B2 40 +1E 00 84 01 39 40 80 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 39 40 00 10 29 83 89 43 00 20 FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 +B0 12 D0 C4 80 C5 00 00 0C 41 43 43 45 50 54 00 +30 40 94 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 AD 3E 21 52 A2 C2 6C 05 B2 B0 10 00 +40 05 A6 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 F0 C6 +58 43 B0 12 46 C5 2F 83 8F 4E 00 00 92 B3 6C 05 +FD 27 1E 42 4C 05 B0 12 44 C5 30 4D 00 00 08 45 +4D 49 54 00 30 40 18 C7 08 4E 3E 4F A2 B3 6C 05 +FD 27 C2 48 4E 05 30 4D 0E C7 08 45 43 48 4F 00 +B2 40 C2 48 22 C7 38 40 05 00 B0 12 46 C5 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 22 C7 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +6C C7 29 4F 8F 4E 00 00 7E 49 D4 3F 6E C7 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 92 22 F9 98 +00 00 8F 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 86 22 9B 24 E8 C6 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A C4 00 00 8C C8 7E C7 D0 C9 +8A CC B0 C4 FA C7 14 C4 06 5B 54 48 45 4E 5D 00 +82 C7 D8 C7 9E C7 BC C7 14 C4 06 5B 45 4C 53 45 +5D 00 82 C7 EA C7 9E C7 BA C7 1E C4 04 5B 49 46 +5D 00 82 C7 BC C7 B2 C4 BA C7 1E C4 05 0D 6B 6F +20 0A 5C C7 9A C4 84 C4 B2 C4 BC C7 AA C7 0D 5B +54 48 45 4E 5D 00 30 4D 0E C8 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 1A C8 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 7E C7 D0 C9 38 CA DC CB +4C C9 2A C8 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 7E C7 D0 C9 38 CA 5C C8 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D 88 C6 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 C5 05 53 22 00 82 43 C0 21 0D 12 +84 12 0A C4 1E C4 3A CC 0A C4 22 00 D0 C9 D0 C8 +B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F +3D 41 30 4D 42 C7 05 2E 22 00 0D 12 84 12 BA C8 +0A C4 5C C7 3A CC 4C C9 00 00 04 3C 23 00 B2 40 +B2 21 B2 21 30 4D B6 C8 02 23 1B 42 BE 21 2C 4F +2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 02 CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 48 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 48 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C CA 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E CA 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 CB 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C8 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C4 02 CC 1A C9 BE CB 9C 26 -3D 40 C6 CB DE 3E C8 CB 0A 4E 3E 4F 3D 40 E2 CB -36 27 3D 40 B8 CB 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 CB 3E 4F 3D 40 B8 CB BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CD CC 3F -EC CB 86 12 20 00 D4 C7 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C C7 BC C4 -B2 CB B2 C7 E4 C7 14 C4 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 EC C7 -14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C5 -3A C4 2C CC 08 CC 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C8 0A C4 2A C5 48 CB 4E C8 7C C9 01 27 -0D 12 84 12 02 CC 1A C9 82 C9 34 C4 00 CC 4E C8 -00 00 83 5B 27 5D 0D 12 84 12 80 CC 0A C4 0A C4 -48 CB 48 CB 4E C8 92 CC 81 5B 82 43 BE 21 30 4D -FA C7 01 5D B2 43 BE 21 30 4D B2 CC 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CC 1A C9 82 C9 96 C7 34 C4 -00 CC E4 C7 34 C4 F4 CC 0A C4 0A C4 48 CB 48 CB -0A C4 48 CB 48 CB 4E C8 A8 CC 01 3A 30 12 44 CD -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 CC 1A C9 -12 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C5 FA CC 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A C4 4E C8 48 CB 56 CD AA CC 4E C8 -A8 CB 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 CB 06 43 52 45 41 54 -45 00 B0 12 00 CD BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CD 04 43 4F 44 45 00 B0 12 00 CD A2 82 -C6 21 0D 12 84 12 F2 CF CC CF 4E C8 A2 CD 07 48 -44 4E 43 4F 44 45 B2 40 D0 CF DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CD 0C D0 -2A D0 4E C8 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C D0 2A D0 4E C8 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 9A CF -48 CB AA CC E2 CD 4E C8 88 CD 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CE 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C4 00 00 C6 C7 02 CC 1A C9 98 CB -8E C7 34 C4 02 CF 9C C7 14 C4 06 5B 54 48 45 4E -5D 00 74 CE DC CE 98 CE BA CE 4E C8 9C C7 14 C4 -06 5B 45 4C 53 45 5D 00 74 CE F2 CE 98 CE B8 CE -4E C8 14 C4 04 5B 49 46 5D 00 74 CE BA CE 3A C4 -B8 CE 70 C7 14 C4 05 0D 0A 6B 6F 20 4A C7 BC C4 -AC C4 3A C4 BA CE A8 CE 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CF 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CC 1A C9 82 C9 -26 CF 4E C8 2C CF 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CF DE C7 4E C8 5E CF B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A CB 06 4D -41 52 4B 45 52 00 B0 12 00 CD BA 40 85 12 FC FF -BA 40 5C CF FE FF 28 83 8A 48 00 00 BA 40 AA C4 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 -CA 21 D6 C7 4E C8 85 12 9E CF 66 CC D4 CD 10 C7 -7E CC 52 CE D2 C6 6E CF 00 C9 96 D0 AA D0 8A C8 -14 C9 00 00 46 CF BC CC E2 C9 00 00 85 12 9E CF -4A D6 B0 D6 F2 D5 00 D7 B8 D5 00 00 84 D3 00 00 -C8 D7 AC D7 1C D6 5A D6 94 D4 00 00 00 00 1C D7 -CA CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 CF 24 D0 2A D0 3A D0 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CC -09 50 57 52 5F 53 54 41 54 45 85 12 32 D0 D4 D7 -CE C8 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E D0 F3 3F 70 D0 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E D0 30 4D 82 D0 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 D1 FE FF 29 83 B9 40 -E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 00 C6 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 43 -06 02 B2 40 FC FF 02 02 F2 D3 26 02 F2 43 22 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B0 00 -82 01 B2 40 1E 00 84 01 82 43 88 01 F2 D0 03 00 -0B 02 39 40 80 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 FE C5 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 1A C9 82 C9 DE C7 34 C4 C4 D1 3E CA 34 C4 -DE D1 D8 D1 C6 D1 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 E0 D1 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1A C9 82 C9 -DE C7 34 C4 FC D1 3E CA 34 C4 00 CC A8 C7 1A C9 -3E CA 34 C4 00 CC 08 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 A8 D1 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 6E CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 1A C9 3E CA -34 C4 50 D2 46 D2 21 53 3E 90 10 00 C6 2B 7F 2D -52 D2 B2 41 C4 21 C1 3F 0D 12 84 12 02 CC 84 D1 -62 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 A8 D1 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 A8 D1 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 30 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 30 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 30 D2 FA 23 -3C 50 10 00 B0 12 0C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 02 CC 84 D1 2E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 30 D2 E0 23 3C 50 80 00 B0 12 0C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -48 CB 4E C8 0A C4 2C 00 58 D2 24 D3 6E D3 09 4B -2E 4E 0E DC A2 3F 40 CE 03 4D 4F 56 85 12 64 D3 -00 40 78 D3 05 4D 4F 56 2E 42 85 12 64 D3 40 40 -00 00 03 41 44 44 85 12 64 D3 00 50 92 D3 05 41 -44 44 2E 42 85 12 64 D3 40 50 9E D3 04 41 44 44 -43 00 85 12 64 D3 00 60 AC D3 06 41 44 44 43 2E -42 00 85 12 64 D3 40 60 52 D3 04 53 55 42 43 00 -85 12 64 D3 00 70 CA D3 06 53 55 42 43 2E 42 00 -85 12 64 D3 40 70 D8 D3 03 53 55 42 85 12 64 D3 -00 80 E8 D3 05 53 55 42 2E 42 85 12 64 D3 40 80 -16 CE 03 43 4D 50 85 12 64 D3 00 90 02 D4 05 43 -4D 50 2E 42 85 12 64 D3 40 90 00 CE 04 44 41 44 -44 00 85 12 64 D3 00 A0 1C D4 06 44 41 44 44 2E -42 00 85 12 64 D3 40 A0 0E D4 03 42 49 54 85 12 -64 D3 00 B0 3A D4 05 42 49 54 2E 42 85 12 64 D3 -40 B0 46 D4 03 42 49 43 85 12 64 D3 00 C0 54 D4 -05 42 49 43 2E 42 85 12 64 D3 40 C0 60 D4 03 42 -49 53 85 12 64 D3 00 D0 6E D4 05 42 49 53 2E 42 -85 12 64 D3 40 D0 00 00 03 58 4F 52 85 12 64 D3 -00 E0 88 D4 05 58 4F 52 2E 42 85 12 64 D3 40 E0 -BA D3 03 41 4E 44 85 12 64 D3 00 F0 A2 D4 05 41 -4E 44 2E 42 85 12 64 D3 40 F0 02 CC 58 D2 C0 D4 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -F4 D3 03 52 52 43 85 12 BA D4 00 10 D2 D4 05 52 -52 43 2E 42 85 12 BA D4 40 10 DE D4 04 53 57 50 -42 00 85 12 BA D4 80 10 EC D4 03 52 52 41 85 12 -BA D4 00 11 FA D4 05 52 52 41 2E 42 85 12 BA D4 -40 11 06 D5 03 53 58 54 85 12 BA D4 80 11 00 00 -04 50 55 53 48 00 85 12 BA D4 00 12 20 D5 06 50 -55 53 48 2E 42 00 85 12 BA D4 40 12 7A D4 04 43 -41 4C 4C 00 85 12 BA D4 80 12 1A 53 0E 4A 0D 12 -84 12 C4 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 14 D5 03 53 3E 3D 86 12 00 38 -68 D5 02 53 3C 00 86 12 00 34 2E D5 03 30 3E 3D -86 12 00 30 7C D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C 90 D5 03 55 3E 3D 86 12 -00 28 86 D5 03 30 3C 3E 86 12 00 24 A4 D5 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D 9A D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -2A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 3E D5 -05 42 45 47 49 4E 30 40 28 C4 CE D5 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D AE D4 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 BC D5 A8 C7 4E C8 72 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 50 D6 D4 D5 4E C8 80 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 10 D6 03 42 57 31 85 12 7E D6 -00 00 98 D6 03 42 57 32 85 12 7E D6 00 00 A4 D6 -03 42 57 33 85 12 7E D6 00 00 BC D6 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 BA D6 00 00 DC D6 03 46 57 32 85 12 BA D6 -00 00 E8 D6 03 46 57 33 85 12 BA D6 00 00 F4 D6 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 80 CC DC CB 4E C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 02 CC 84 D1 3E D7 92 53 -C4 21 3E 40 2C 00 84 12 1A C9 3E CA 34 C4 00 CC -1A D3 54 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -6C D6 04 52 52 43 4D 00 85 12 38 D7 50 00 82 D7 -04 52 52 41 4D 00 85 12 38 D7 50 01 90 D7 04 52 -4C 41 4D 00 85 12 38 D7 50 02 9E D7 04 52 52 55 -4D 00 85 12 38 D7 50 03 AE D5 05 50 55 53 48 4D -85 12 38 D7 00 15 BA D7 04 50 4F 50 4D 00 85 12 -38 D7 00 17 +C8 4A 00 00 30 4D 08 C9 04 23 53 00 0D 12 84 12 +0A C9 44 C9 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +38 C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 52 C9 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 2A C7 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 FE C8 7E C7 6C C9 +3C C9 68 C8 7A C9 56 C9 5C C7 4C C9 E6 C8 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 +82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D BE C9 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 21 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 21 0C 4E 0E 43 1E 15 3D 40 42 CB 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 44 CB 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +FA C8 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 C4 7E C7 D0 C9 B0 C4 14 CD 38 CA FE CB 0A 4E +3E 4F 3D 40 18 CC 6D 27 3D 40 F2 CB 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 1A CC 3E 4F 3D 40 F2 CB +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 F0 CD 2A 3C E2 CB 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 38 CC 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 74 C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D 9A C8 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E C4 02 0D 0A 00 5C C7 94 C4 EC CB 7A C8 A4 C8 +1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 +32 C4 0A C4 40 FF AC C8 1E C4 09 46 52 41 4D 20 +66 75 6C 6C 08 C5 B2 C4 B0 CC 9A CC 0D 41 42 4F +52 54 22 00 0D 12 84 12 BA C8 0A C4 08 C5 3A CC +4C C9 CA C9 02 27 0D 12 84 12 7E C7 D0 C9 38 CA +B0 C4 16 CD DE C8 22 CC 44 C8 07 5B 27 5D 0D 12 +84 12 06 CD 0A C4 0A C4 3A CC 3A CC 4C C9 1A CD +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D 92 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 7E C7 D0 C9 38 CA B0 C4 16 CD A4 C8 AC C4 +6E CD 0A C4 0A C4 3A CC 3A CC 0A C4 3A CC 3A CC +4C C9 00 00 02 3A 30 12 C4 CD 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 7E C7 D0 C9 8C CD 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 C5 30 CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A C4 4C C9 3A CC D6 CD 32 CD 4C C9 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D 84 CC 0C 43 52 45 41 54 45 00 B0 12 7A CD +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 56 C7 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 74 CD 0E 3A 4E 4F 4E 41 4D 45 +30 12 C4 CD 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 0E CE 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 06 CD 90 CE +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 1E CD 0A C4 +92 CE 3A CC 4C C9 24 CE 08 43 4F 44 45 00 B0 12 +7A CD A2 82 C8 21 61 3C 66 C9 0E 48 44 4E 43 4F +44 45 B2 40 7E CF CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 D6 CD DC CE 3D 41 92 42 +D0 21 CC 21 5D 3C A8 CE 0E 43 4F 44 45 4E 4E 4D +30 12 B2 CE B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F BA CE 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F 46 CF B2 40 58 CF D0 21 82 4E CE 21 +30 40 DE C8 85 12 44 CF 44 CD EC CC D6 CF E8 CE +3E CE 88 C9 32 CA 04 CD 2C CF 7E CE 58 CE F4 CD +4C CC 60 D0 8A CA 00 00 00 00 85 12 44 CF DA D6 +5E D5 BE D6 86 D4 E2 D4 30 D5 0C D6 18 D6 A8 D3 +CC D4 00 00 00 00 1A CF 98 D2 00 00 34 D6 78 CF +B2 40 58 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +AC CF 30 4D BE CF 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 AC CF 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E C6 FE FF 29 83 B9 40 FA C5 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 E0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 B0 CF 82 43 4A 18 C7 3F +52 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 3A CD +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +7E C7 D0 C9 38 CA AC C4 7E D0 72 C8 12 CC 80 D0 +3E 4F 3D 41 B2 41 C6 21 B0 12 7A CD BA 40 85 12 +FC FF BA 40 50 D0 FE FF 28 83 8A 48 00 00 BA 40 +82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +D0 C9 38 CA AC C4 EA D0 CA D0 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 50 D0 00 00 +01 20 3E 52 2E 83 21 53 30 41 E2 CA AC C4 F2 D0 +E6 D0 F4 D0 B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 BA D0 15 20 3E 40 2B 00 +B0 12 BA D0 06 20 3E 40 2D 00 B0 12 BA D0 92 83 +C6 21 0E 12 1E 41 02 00 84 12 D0 C9 E2 CA AC C4 +16 CD 34 D1 3E 51 3A 17 30 41 B0 12 FA D0 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 D0 C9 E2 CA AC C4 +6C D1 64 D1 3E 90 10 00 E6 2B 7C 2D 6E D1 A2 41 +C6 21 E1 3F 03 20 B0 12 52 D1 43 3C 7A 90 23 00 +24 20 B0 12 02 D1 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 02 D1 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 4E D1 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 52 D1 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 3A D1 +F2 3F 03 20 B0 12 52 D1 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 3A D1 EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A C4 00 13 3A CC 4C C9 +0A C4 2C 00 30 D2 74 D1 7E C7 3A D2 12 D2 80 D2 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 70 D2 00 40 8C D2 0A 4D 4F 56 2E 42 85 12 +70 D2 40 40 00 00 06 41 44 44 85 12 70 D2 00 50 +A6 D2 0A 41 44 44 2E 42 85 12 70 D2 40 50 B2 D2 +08 41 44 44 43 00 85 12 70 D2 00 60 C0 D2 0C 41 +44 44 43 2E 42 00 85 12 70 D2 40 60 F8 CE 08 53 +55 42 43 00 85 12 70 D2 00 70 DE D2 0C 53 55 42 +43 2E 42 00 85 12 70 D2 40 70 EC D2 06 53 55 42 +85 12 70 D2 00 80 FC D2 0A 53 55 42 2E 42 85 12 +70 D2 40 80 08 D3 06 43 4D 50 85 12 70 D2 00 90 +16 D3 0A 43 4D 50 2E 42 85 12 70 D2 40 90 00 00 +08 44 41 44 44 00 85 12 70 D2 00 A0 30 D3 0C 44 +41 44 44 2E 42 00 85 12 70 D2 40 A0 5E D2 06 42 +49 54 85 12 70 D2 00 B0 4E D3 0A 42 49 54 2E 42 +85 12 70 D2 40 B0 5A D3 06 42 49 43 85 12 70 D2 +00 C0 68 D3 0A 42 49 43 2E 42 85 12 70 D2 40 C0 +74 D3 06 42 49 53 85 12 70 D2 00 D0 82 D3 0A 42 +49 53 2E 42 85 12 70 D2 40 D0 00 00 06 58 4F 52 +85 12 70 D2 00 E0 9C D3 0A 58 4F 52 2E 42 85 12 +70 D2 40 E0 CE D2 06 41 4E 44 85 12 70 D2 00 F0 +B6 D3 0A 41 4E 44 2E 42 85 12 70 D2 40 F0 7E C7 +30 D2 74 D1 D6 D3 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F 8E D3 06 52 52 43 85 12 CE D3 +00 10 E8 D3 0A 52 52 43 2E 42 85 12 CE D3 40 10 +22 D3 08 53 57 50 42 00 85 12 CE D3 80 10 F4 D3 +06 52 52 41 85 12 CE D3 00 11 10 D4 0A 52 52 41 +2E 42 85 12 CE D3 40 11 02 D4 06 53 58 54 85 12 +CE D3 80 11 00 00 08 50 55 53 48 00 85 12 CE D3 +00 12 36 D4 0C 50 55 53 48 2E 42 00 85 12 CE D3 +40 12 2A D4 08 43 41 4C 4C 00 85 12 CE D3 80 12 +1A 53 0E 4A 84 12 C0 C9 1E C4 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 C5 54 D4 06 53 3E 3D +86 12 00 38 7C D4 04 53 3C 00 86 12 00 34 44 D4 +06 30 3E 3D 86 12 00 30 90 D4 04 30 3C 00 86 12 +00 30 CC CE 04 55 3C 00 86 12 00 2C A4 D4 06 55 +3E 3D 86 12 00 28 9A D4 06 30 3C 3E 86 12 00 24 +B8 D4 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +3E D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D AE D4 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 1C D4 0A 42 45 47 49 4E 30 40 32 C4 06 D5 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D C2 D3 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 D0 D4 66 C8 4C C9 24 D5 +0C 52 45 50 45 41 54 00 0D 12 84 12 64 D5 E8 D4 +4C C9 94 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D 80 D5 06 42 57 31 +85 12 92 D5 00 00 AC D5 06 42 57 32 85 12 92 D5 +00 00 B8 D5 06 42 57 33 85 12 92 D5 00 00 D0 D5 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 CE D5 00 00 F4 D5 +06 46 57 32 85 12 CE D5 00 00 00 D6 06 46 57 33 +85 12 CE D5 00 00 6E D5 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 06 CD 12 CC +4C C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +3A D2 0A C4 2C 00 D0 C9 E2 CA AC C4 16 CD 7E C7 +30 D2 12 D2 66 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E C4 D5 08 52 52 43 4D 00 85 12 50 D6 50 00 +94 D6 08 52 52 41 4D 00 85 12 50 D6 50 01 A2 D6 +08 52 4C 41 4D 00 85 12 50 D6 50 02 B0 D6 08 52 +52 55 4D 00 85 12 50 D6 50 03 C2 D4 0A 50 55 53 +48 4D 85 12 50 D6 00 15 CC D6 08 50 4F 50 4D 00 +85 12 50 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -82 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 08 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +A6 C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR2433_1MHz_UART.txt b/binaries/MSP_EXP430FR2433_1MHz_UART.txt deleted file mode 100644 index 6b62c01..0000000 --- a/binaries/MSP_EXP430FR2433_1MHz_UART.txt +++ /dev/null @@ -1,335 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF EA D7 02 D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 EA D7 -02 D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 28 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 D2 D3 02 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 D2 C3 02 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 14 CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -5A CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -5A CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 14 CC 2C C9 D0 CB -9C 26 3D 40 D8 CB DE 3E DA CB 0A 4E 3E 4F 3D 40 -F4 CB 36 27 3D 40 CA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 CB 3E 4F 3D 40 CA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CD -CC 3F FE CB 86 12 20 00 E6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E C7 -BC C4 C4 CB C4 C7 F6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -FE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 3E CC 1A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C8 0A C4 2A C5 5A CB 60 C8 8E C9 -01 27 0D 12 84 12 14 CC 2C C9 94 C9 34 C4 12 CC -60 C8 00 00 83 5B 27 5D 0D 12 84 12 92 CC 0A C4 -0A C4 5A CB 5A CB 60 C8 A4 CC 81 5B 82 43 BE 21 -30 4D 0C C8 01 5D B2 43 BE 21 30 4D C4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CC 2C C9 94 C9 A8 C7 -34 C4 12 CC F6 C7 34 C4 06 CD 0A C4 0A C4 5A CB -5A CB 0A C4 5A CB 5A CB 60 C8 BA CC 01 3A 30 12 -56 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 CC -2C C9 24 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 0C CD 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 60 C8 5A CB 68 CD BC CC -60 C8 BA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 CB 06 43 52 45 -41 54 45 00 B0 12 12 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CD 04 43 4F 44 45 00 B0 12 12 CD -A2 82 C6 21 0D 12 84 12 04 D0 DE CF 60 C8 B4 CD -07 48 44 4E 43 4F 44 45 B2 40 E2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CD -1E D0 3C D0 60 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E D0 3C D0 60 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 CE 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -AC CF 5A CB BC CC F4 CD 60 C8 9A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 D8 C7 14 CC 2C C9 -AA CB A0 C7 34 C4 14 CF AE C7 14 C4 06 5B 54 48 -45 4E 5D 00 86 CE EE CE AA CE CC CE 60 C8 AE C7 -14 C4 06 5B 45 4C 53 45 5D 00 86 CE 04 CF AA CE -CA CE 60 C8 14 C4 04 5B 49 46 5D 00 86 CE CC CE -3A C4 CA CE 82 C7 14 C4 05 0D 0A 6B 6F 20 5C C7 -BC C4 AC C4 3A C4 CC CE BA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CC 2C C9 -94 C9 38 CF 60 C8 3E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CF F0 C7 60 C8 70 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C CB -06 4D 41 52 4B 45 52 00 B0 12 12 CD BA 40 85 12 -FC FF BA 40 6E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 E8 C7 60 C8 85 12 B0 CF 78 CC E6 CD -2C C7 90 CC 64 CE F6 C6 80 CF 12 C9 A8 D0 BC D0 -9C C8 26 C9 00 00 58 CF CE CC F4 C9 00 00 85 12 -B0 CF 60 D6 C6 D6 08 D6 16 D7 CE D5 00 00 9A D3 -00 00 DE D7 C2 D7 32 D6 70 D6 AA D4 00 00 00 00 -32 D7 DC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 CF 36 D0 3C D0 4C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CC 09 50 57 52 5F 53 54 41 54 45 85 12 44 D0 -EA D7 E0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 D0 F3 3F 82 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 D0 30 4D 94 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A D1 FE FF 29 83 -B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 20 C6 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 -26 02 F2 43 22 02 B2 40 00 A5 60 01 B2 40 FF 1E -80 01 B2 40 B0 00 82 01 B2 40 1E 00 84 01 82 43 -88 01 F2 D0 03 00 0B 02 39 40 80 00 18 42 00 18 -18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 -1E D2 5E 01 B0 12 F8 C4 1E C6 38 40 C0 21 0A 4E -39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E -FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 -0E 12 12 12 C4 21 84 12 2C C9 94 C9 F0 C7 34 C4 -DA D1 50 CA 34 C4 F4 D1 EE D1 DC D1 3C 4E 3C 80 -87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 -1B 17 30 41 F6 D1 B2 41 C4 21 3E 41 84 12 0A C4 -2B 00 2C C9 94 C9 F0 C7 34 C4 12 D2 50 CA 34 C4 -12 CC BA C7 2C C9 50 CA 34 C4 12 CC 1E D2 3E 5F -E7 3F 3E 40 28 00 B0 12 BE D1 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 -02 20 30 40 80 CD 1C 15 12 12 C4 21 92 53 C4 21 -84 12 2C C9 50 CA 34 C4 66 D2 5C D2 21 53 3E 90 -10 00 C6 2B 7F 2D 68 D2 B2 41 C4 21 C1 3F 0D 12 -84 12 14 CC 9A D1 78 D2 0C 43 1B 42 C6 21 A2 53 -C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 -B0 12 BE D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 -1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 -2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 -3C 40 10 02 92 53 C4 21 B0 12 BE D1 ED 3F 7A 90 -40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 46 D2 -0C 20 3C 50 10 00 3E 40 2B 00 B0 12 46 D2 92 92 -C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F -B0 12 46 D2 FA 23 3C 50 10 00 B0 12 22 D2 EF 3F -0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 CC -9A D1 44 D3 FE 90 26 00 00 00 3E 40 20 00 03 20 -3C 50 82 00 C7 3F B0 12 46 D2 E0 23 3C 50 80 00 -B0 12 22 D2 DB 3F 00 00 04 52 45 54 49 00 0D 12 -84 12 0A C4 00 13 5A CB 60 C8 0A C4 2C 00 6E D2 -3A D3 84 D3 09 4B 2E 4E 0E DC A2 3F 52 CE 03 4D -4F 56 85 12 7A D3 00 40 8E D3 05 4D 4F 56 2E 42 -85 12 7A D3 40 40 00 00 03 41 44 44 85 12 7A D3 -00 50 A8 D3 05 41 44 44 2E 42 85 12 7A D3 40 50 -B4 D3 04 41 44 44 43 00 85 12 7A D3 00 60 C2 D3 -06 41 44 44 43 2E 42 00 85 12 7A D3 40 60 68 D3 -04 53 55 42 43 00 85 12 7A D3 00 70 E0 D3 06 53 -55 42 43 2E 42 00 85 12 7A D3 40 70 EE D3 03 53 -55 42 85 12 7A D3 00 80 FE D3 05 53 55 42 2E 42 -85 12 7A D3 40 80 28 CE 03 43 4D 50 85 12 7A D3 -00 90 18 D4 05 43 4D 50 2E 42 85 12 7A D3 40 90 -12 CE 04 44 41 44 44 00 85 12 7A D3 00 A0 32 D4 -06 44 41 44 44 2E 42 00 85 12 7A D3 40 A0 24 D4 -03 42 49 54 85 12 7A D3 00 B0 50 D4 05 42 49 54 -2E 42 85 12 7A D3 40 B0 5C D4 03 42 49 43 85 12 -7A D3 00 C0 6A D4 05 42 49 43 2E 42 85 12 7A D3 -40 C0 76 D4 03 42 49 53 85 12 7A D3 00 D0 84 D4 -05 42 49 53 2E 42 85 12 7A D3 40 D0 00 00 03 58 -4F 52 85 12 7A D3 00 E0 9E D4 05 58 4F 52 2E 42 -85 12 7A D3 40 E0 D0 D3 03 41 4E 44 85 12 7A D3 -00 F0 B8 D4 05 41 4E 44 2E 42 85 12 7A D3 40 F0 -14 CC 6E D2 D6 D4 0A 4C 3C F0 70 00 8A 10 3A F0 -0F 00 0C DA 4F 3F 0A D4 03 52 52 43 85 12 D0 D4 -00 10 E8 D4 05 52 52 43 2E 42 85 12 D0 D4 40 10 -F4 D4 04 53 57 50 42 00 85 12 D0 D4 80 10 02 D5 -03 52 52 41 85 12 D0 D4 00 11 10 D5 05 52 52 41 -2E 42 85 12 D0 D4 40 11 1C D5 03 53 58 54 85 12 -D0 D4 80 11 00 00 04 50 55 53 48 00 85 12 D0 D4 -00 12 36 D5 06 50 55 53 48 2E 42 00 85 12 D0 D4 -40 12 90 D4 04 43 41 4C 4C 00 85 12 D0 D4 80 12 -1A 53 0E 4A 0D 12 84 12 D6 C8 14 C4 0D 6F 75 74 -20 6F 66 20 62 6F 75 6E 64 73 36 C5 2A D5 03 53 -3E 3D 86 12 00 38 7E D5 02 53 3C 00 86 12 00 34 -44 D5 03 30 3E 3D 86 12 00 30 92 D5 02 30 3C 00 -86 12 00 30 00 00 02 55 3C 00 86 12 00 2C A6 D5 -03 55 3E 3D 86 12 00 28 9C D5 03 30 3C 3E 86 12 -00 24 BA D5 02 30 3D 00 86 12 00 20 00 00 02 49 -46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A -30 4D B0 D5 04 54 48 45 4E 00 1A 42 C6 21 08 4E -3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F -88 DA 00 00 30 4D 40 D4 04 45 4C 53 45 00 1A 42 -C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A -00 00 E3 3F 54 D5 05 42 45 47 49 4E 30 40 28 C4 -E4 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 -C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 -FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D C4 D4 -05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 -05 57 48 49 4C 45 0D 12 84 12 D2 D5 BA C7 60 C8 -88 D5 06 52 45 50 45 41 54 00 0D 12 84 12 66 D6 -EA D5 60 C8 96 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 -C4 21 CB 2F 98 42 C6 21 00 00 30 4D 26 D6 03 42 -57 31 85 12 94 D6 00 00 AE D6 03 42 57 32 85 12 -94 D6 00 00 BA D6 03 42 57 33 85 12 94 D6 00 00 -D2 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B -BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D -00 00 03 46 57 31 85 12 D0 D6 00 00 F2 D6 03 46 -57 32 85 12 D0 D6 00 00 FE D6 03 46 57 33 85 12 -D0 D6 00 00 0A D7 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C 0D 12 84 12 92 CC EE CB 60 C8 -00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 -00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 CC -9A D1 54 D7 92 53 C4 21 3E 40 2C 00 84 12 2C C9 -50 CA 34 C4 12 CC 30 D3 6A D7 0A 4E 3E 4F 1A 83 -F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A -08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E -8A 10 5A 06 A6 3E 82 D6 04 52 52 43 4D 00 85 12 -4E D7 50 00 98 D7 04 52 52 41 4D 00 85 12 4E D7 -50 01 A6 D7 04 52 4C 41 4D 00 85 12 4E D7 50 02 -B4 D7 04 52 52 55 4D 00 85 12 4E D7 50 03 C4 D5 -05 50 55 53 48 4D 85 12 4E D7 00 15 D0 D7 04 50 -4F 50 4D 00 85 12 4E D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 94 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1A D1 -q diff --git a/binaries/MSP_EXP430FR2433_8MHz_115200.txt b/binaries/MSP_EXP430FR2433_8MHz_115200.txt new file mode 100644 index 0000000..3055563 --- /dev/null +++ b/binaries/MSP_EXP430FR2433_8MHz_115200.txt @@ -0,0 +1,323 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A0 59 +B2 C6 7E C5 84 C5 54 C5 22 C7 10 D7 C8 CF 82 CF +82 CF 98 C6 56 C7 1E C7 3C 21 E0 20 76 C9 B6 C4 +C4 C4 92 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +22 C7 10 D7 C8 CF 82 CF 82 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F4 3C 0E 93 3E 4F +89 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 96 C6 B2 49 +54 C7 B2 49 1C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 3C D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 22 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 9C C8 AC C4 52 C5 64 C7 1E C4 04 1B +5B 37 6D 00 86 C7 86 C7 1E C4 04 1B 5B 30 6D 00 +86 C7 D2 CC B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 30 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 64 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 86 C7 EA C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 86 C7 0A C4 40 FF 32 C4 +B2 C8 B6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B2 01 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 +26 02 F2 43 22 02 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 03 00 0B 02 F2 C3 82 01 F2 D0 06 00 82 01 +B2 40 F4 00 84 01 39 40 80 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 10 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 98 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 F6 C6 3C 40 02 C7 5D 15 +A7 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 D2 D3 02 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D F8 C6 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 1E C7 30 12 +34 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 D2 C3 +02 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 BE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 56 C7 08 4E 3E 4F C7 3F 4C C7 08 45 +43 48 4F 00 B2 40 C2 48 F0 C6 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D F0 C6 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 96 C7 29 4F 8F 4E +00 00 7E 49 DE 3F 98 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 7D 22 F9 98 00 00 7A 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 71 22 +9B 24 16 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 B6 C8 A8 C7 FA C9 B4 CC B0 C4 24 C8 +14 C4 06 5B 54 48 45 4E 5D 00 AC C7 02 C8 C8 C7 +E6 C7 14 C4 06 5B 45 4C 53 45 5D 00 AC C7 14 C8 +C8 C7 E4 C7 1E C4 04 5B 49 46 5D 00 AC C7 E6 C7 +B2 C4 E4 C7 1E C4 05 0D 6B 6F 20 0A 86 C7 9A C4 +84 C4 B2 C4 E6 C7 D4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 38 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 44 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 A8 C7 FA C9 62 CA 06 CC 76 C9 54 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 A8 C7 +FA C9 62 CA 86 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 8C C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +64 CC 0A C4 22 00 FA C9 FA C8 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 6E C7 +05 2E 22 00 0D 12 84 12 E4 C8 0A C4 86 C7 64 CC +76 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +E0 C8 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +32 C9 04 23 53 00 0D 12 84 12 34 C9 6E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 62 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 7C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +5E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 28 C9 A8 C7 96 C9 66 C9 92 C8 A4 C9 +80 C9 86 C7 76 C9 10 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D E8 C9 0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 21 0C 4E +0E 43 1E 15 3D 40 6C CB 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 6E CB 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E +09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 24 C9 03 5C 92 42 +C2 21 C6 21 30 4D 0D 12 84 12 84 C4 A8 C7 FA C9 +B0 C4 3E CD 62 CA 28 CC 0A 4E 3E 4F 3D 40 42 CC +6D 27 3D 40 1C CC 1A E2 BC 21 14 24 0E 12 3E 4F +30 41 44 CC 3E 4F 3D 40 1C CC 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 1A CE 2A 3C +0C CC 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF +3E 4F 30 4D 62 CC 0F 4C 49 54 45 52 41 4C 82 93 +BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 +0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D 9E C9 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D C4 C8 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F +30 4D 3F 40 80 20 0E 43 84 12 1E C4 02 0D 0A 00 +86 C7 94 C4 16 CC A4 C8 CE C8 1E C4 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 C5 32 C4 0A C4 40 FF +D6 C8 1E C4 09 46 52 41 4D 20 66 75 6C 6C 08 C5 +B2 C4 DA CC C4 CC 0D 41 42 4F 52 54 22 00 0D 12 +84 12 E4 C8 0A C4 08 C5 64 CC 76 C9 F4 C9 02 27 +0D 12 84 12 A8 C7 FA C9 62 CA B0 C4 40 CD 08 C9 +4C CC 6E C8 07 5B 27 5D 0D 12 84 12 30 CD 0A C4 +0A C4 64 CC 64 CC 76 C9 44 CD 03 5B 82 43 BC 21 +30 4D 00 00 02 5D B2 43 BC 21 30 4D BC C8 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 A8 C7 FA C9 +62 CA B0 C4 40 CD CE C8 AC C4 98 CD 0A C4 0A C4 +64 CC 64 CC 0A C4 64 CC 64 CC 76 C9 00 00 02 3A +30 12 EE CD 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 +A8 C7 FA C9 B6 CD 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A +B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D +82 9F BA 21 66 25 84 12 1E C4 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 C5 5A CD 03 3B +82 93 BC 21 F4 26 0D 12 84 12 0A C4 76 C9 64 CC +00 CE 5C CD 76 C9 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 21 D8 D3 00 00 30 4D AE CC 0C 43 +52 45 41 54 45 00 B0 12 A4 CD BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 80 C7 0A 44 4F 45 53 3E 1A 42 +B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +9E CD 0E 3A 4E 4F 4E 41 4D 45 30 12 EE CD 2F 83 +8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 38 CE 05 49 53 00 0D 12 82 93 +BC 21 08 20 84 12 30 CD BA CE 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 48 CD 0A C4 BC CE 64 CC 76 C9 +4E CE 08 43 4F 44 45 00 B0 12 A4 CD A2 82 C8 21 +61 3C 90 C9 0E 48 44 4E 43 4F 44 45 B2 40 A8 CF +CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 00 CE 06 CF 3D 41 92 42 D0 21 CC 21 5D 3C +D2 CE 0E 43 4F 44 45 4E 4E 4D 30 12 DC CE B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 +C8 21 EF 3F E4 CE 0B 48 49 32 4C 4F A2 53 C8 21 +1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 70 CF +B2 40 82 CF D0 21 82 4E CE 21 30 40 08 C9 85 12 +6E CF 6E CD 16 CD 00 D0 12 CF 68 CE B2 C9 5C CA +2E CD 56 CF A8 CE 82 CE 1E CE 76 CC 8A D0 B4 CA +00 00 00 00 85 12 6E CF 04 D7 88 D5 E8 D6 B0 D4 +0C D5 5A D5 36 D6 42 D6 D2 D3 F6 D4 00 00 00 00 +44 CF C2 D2 00 00 5E D6 A2 CF B2 40 82 CF CE 21 +82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 21 3A 40 42 18 B0 12 D6 CF 30 4D E8 CF +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 21 B0 12 D6 CF 1A 42 CA 21 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C6 +FE FF 29 83 B9 40 F2 C5 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 E4 FF 3B 40 10 00 3A 40 3A 18 +B0 12 DA CF 82 43 4A 18 C7 3F 7C D0 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 64 CD 0C 4D 41 52 4B 45 +52 00 12 12 C6 21 0D 12 84 12 A8 C7 FA C9 62 CA +AC C4 A8 D0 9C C8 3C CC AA D0 3E 4F 3D 41 B2 41 +C6 21 B0 12 A4 CD BA 40 85 12 FC FF BA 40 7A D0 +FE FF 28 83 8A 48 00 00 BA 40 82 C4 02 00 A2 52 +C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 21 84 12 FA C9 62 CA AC C4 +14 D1 F4 D0 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 7A D0 00 00 01 20 3E 52 2E 83 +21 53 30 41 0C CB AC C4 1C D1 10 D1 1E D1 B2 41 +C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 +B0 12 E4 D0 15 20 3E 40 2B 00 B0 12 E4 D0 06 20 +3E 40 2D 00 B0 12 E4 D0 92 83 C6 21 0E 12 1E 41 +02 00 84 12 FA C9 0C CB AC C4 40 CD 5E D1 3E 51 +3A 17 30 41 B0 12 24 D1 19 42 C8 21 89 4E 00 00 +A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 +3D 15 84 12 FA C9 0C CB AC C4 96 D1 8E D1 3E 90 +10 00 E6 2B 7C 2D 98 D1 A2 41 C6 21 E1 3F 03 20 +B0 12 7C D1 43 3C 7A 90 23 00 24 20 B0 12 2C D1 +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +2C D1 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +78 D1 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 7C D1 +92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 64 D1 F2 3F 03 20 B0 12 +7C D1 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 64 D1 EA 3F 0C 43 1B 42 C8 21 +A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 +7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A C4 00 13 64 CC 76 C9 0A C4 2C 00 5A D2 +9E D1 A8 C7 64 D2 3C D2 AA D2 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 9A D2 00 40 +B6 D2 0A 4D 4F 56 2E 42 85 12 9A D2 40 40 00 00 +06 41 44 44 85 12 9A D2 00 50 D0 D2 0A 41 44 44 +2E 42 85 12 9A D2 40 50 DC D2 08 41 44 44 43 00 +85 12 9A D2 00 60 EA D2 0C 41 44 44 43 2E 42 00 +85 12 9A D2 40 60 22 CF 08 53 55 42 43 00 85 12 +9A D2 00 70 08 D3 0C 53 55 42 43 2E 42 00 85 12 +9A D2 40 70 16 D3 06 53 55 42 85 12 9A D2 00 80 +26 D3 0A 53 55 42 2E 42 85 12 9A D2 40 80 32 D3 +06 43 4D 50 85 12 9A D2 00 90 40 D3 0A 43 4D 50 +2E 42 85 12 9A D2 40 90 00 00 08 44 41 44 44 00 +85 12 9A D2 00 A0 5A D3 0C 44 41 44 44 2E 42 00 +85 12 9A D2 40 A0 88 D2 06 42 49 54 85 12 9A D2 +00 B0 78 D3 0A 42 49 54 2E 42 85 12 9A D2 40 B0 +84 D3 06 42 49 43 85 12 9A D2 00 C0 92 D3 0A 42 +49 43 2E 42 85 12 9A D2 40 C0 9E D3 06 42 49 53 +85 12 9A D2 00 D0 AC D3 0A 42 49 53 2E 42 85 12 +9A D2 40 D0 00 00 06 58 4F 52 85 12 9A D2 00 E0 +C6 D3 0A 58 4F 52 2E 42 85 12 9A D2 40 E0 F8 D2 +06 41 4E 44 85 12 9A D2 00 F0 E0 D3 0A 41 4E 44 +2E 42 85 12 9A D2 40 F0 A8 C7 5A D2 9E D1 00 D4 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +B8 D3 06 52 52 43 85 12 F8 D3 00 10 12 D4 0A 52 +52 43 2E 42 85 12 F8 D3 40 10 4C D3 08 53 57 50 +42 00 85 12 F8 D3 80 10 1E D4 06 52 52 41 85 12 +F8 D3 00 11 3A D4 0A 52 52 41 2E 42 85 12 F8 D3 +40 11 2C D4 06 53 58 54 85 12 F8 D3 80 11 00 00 +08 50 55 53 48 00 85 12 F8 D3 00 12 60 D4 0C 50 +55 53 48 2E 42 00 85 12 F8 D3 40 12 54 D4 08 43 +41 4C 4C 00 85 12 F8 D3 80 12 1A 53 0E 4A 84 12 +EA C9 1E C4 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 C5 7E D4 06 53 3E 3D 86 12 00 38 A6 D4 +04 53 3C 00 86 12 00 34 6E D4 06 30 3E 3D 86 12 +00 30 BA D4 04 30 3C 00 86 12 00 30 F6 CE 04 55 +3C 00 86 12 00 2C CE D4 06 55 3E 3D 86 12 00 28 +C4 D4 06 30 3C 3E 86 12 00 24 E2 D4 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E +00 00 A2 53 C8 21 0E 4A 30 4D 68 D3 08 54 48 45 +4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D D8 D4 +08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 +A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 46 D4 0A 42 +45 47 49 4E 30 40 32 C4 30 D5 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 21 30 4D EC D3 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 FA D4 90 C8 76 C9 4E D5 0C 52 45 50 45 41 +54 00 0D 12 84 12 8E D5 12 D5 76 C9 BE D5 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 +00 00 30 4D AA D5 06 42 57 31 85 12 BC D5 00 00 +D6 D5 06 42 57 32 85 12 BC D5 00 00 E2 D5 06 42 +57 33 85 12 BC D5 00 00 FA D5 3D 41 1A 42 C8 21 +28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 +A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 F8 D5 00 00 1E D6 06 46 57 32 85 12 +F8 D5 00 00 2A D6 06 46 57 33 85 12 F8 D5 00 00 +98 D5 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 30 CD 3C CC 76 C9 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 64 D2 0A C4 2C 00 +FA C9 0C CB AC C4 40 CD A8 C7 5A D2 3C D2 90 D6 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E EE D5 08 52 +52 43 4D 00 85 12 7A D6 50 00 BE D6 08 52 52 41 +4D 00 85 12 7A D6 50 01 CC D6 08 52 4C 41 4D 00 +85 12 7A D6 50 02 DA D6 08 52 52 55 4D 00 85 12 +7A D6 50 03 EC D4 0A 50 55 53 48 4D 85 12 7A D6 +00 15 F6 D6 08 50 4F 50 4D 00 85 12 7A D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 B2 C6 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR2433_8MHz_I2C.txt b/binaries/MSP_EXP430FR2433_8MHz_I2C.txt index 452bea6..93bb7dd 100644 --- a/binaries/MSP_EXP430FR2433_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR2433_8MHz_I2C.txt @@ -1,334 +1,321 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF D4 D7 F0 CF 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 D4 D7 -F0 CF 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +AC C6 56 C5 56 C5 58 C5 44 C5 EC D6 A4 CF 5E CF +5E CF 9A C6 1E C7 F6 C6 3C 21 E0 20 52 C9 B6 C4 +C4 C4 6E C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 EC D6 A4 CF 5E CF 5E CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 BC D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 16 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 0A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 02 CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 48 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 48 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 21 0C 43 2D 15 3D 40 9C CA 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E CA 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E 00 00 -A2 53 C6 21 3E 4F 30 4D 46 CB 87 4C 49 54 45 52 -41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 -C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C8 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C4 02 CC 1A C9 BE CB 9C 26 -3D 40 C6 CB DE 3E C8 CB 0A 4E 3E 4F 3D 40 E2 CB -36 27 3D 40 B8 CB 1A E2 BE 21 B6 27 0E 12 3E 4F -30 41 E4 CB 3E 4F 3D 40 B8 CB BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CD CC 3F -EC CB 86 12 20 00 D4 C7 05 41 4C 4C 4F 54 82 5E -C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 E0 20 -B2 40 00 20 00 20 82 43 BE 21 84 12 7C C7 BC C4 -B2 CB B2 C7 E4 C7 14 C4 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 EC C7 -14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C5 -3A C4 2C CC 08 CC 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C8 0A C4 2A C5 48 CB 4E C8 7C C9 01 27 -0D 12 84 12 02 CC 1A C9 82 C9 34 C4 00 CC 4E C8 -00 00 83 5B 27 5D 0D 12 84 12 80 CC 0A C4 0A C4 -48 CB 48 CB 4E C8 92 CC 81 5B 82 43 BE 21 30 4D -FA C7 01 5D B2 43 BE 21 30 4D B2 CC 81 5C 92 42 -C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CC 1A C9 82 C9 96 C7 34 C4 -00 CC E4 C7 34 C4 F4 CC 0A C4 0A C4 48 CB 48 CB -0A C4 48 CB 48 CB 4E C8 A8 CC 01 3A 30 12 44 CD -92 B3 C6 21 A2 63 C6 21 0D 12 84 12 02 CC 1A C9 -12 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 -82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 82 4A -C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 B6 21 -19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C5 FA CC 81 3B 82 93 BE 21 97 27 -0D 12 84 12 0A C4 4E C8 48 CB 56 CD AA CC 4E C8 -A8 CB 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 21 -F8 D0 80 00 00 00 30 4D 92 CB 06 43 52 45 41 54 -45 00 B0 12 00 CD BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CD 04 43 4F 44 45 00 B0 12 00 CD A2 82 -C6 21 0D 12 84 12 F2 CF CC CF 4E C8 A2 CD 07 48 -44 4E 43 4F 44 45 B2 40 D0 CF DA 21 EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CD 0C D0 -2A D0 4E C8 00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 21 -B2 43 BE 21 0D 12 84 12 0C D0 2A D0 4E C8 00 00 -05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 EB 3F -EE CD 85 48 49 32 4C 4F 0D 12 84 12 28 C4 9A CF -48 CB AA CC E2 CD 4E C8 88 CD 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CE 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C4 00 00 C6 C7 02 CC 1A C9 98 CB -8E C7 34 C4 02 CF 9C C7 14 C4 06 5B 54 48 45 4E -5D 00 74 CE DC CE 98 CE BA CE 4E C8 9C C7 14 C4 -06 5B 45 4C 53 45 5D 00 74 CE F2 CE 98 CE B8 CE -4E C8 14 C4 04 5B 49 46 5D 00 74 CE BA CE 3A C4 -B8 CE 70 C7 14 C4 05 0D 0A 6B 6F 20 4A C7 BC C4 -AC C4 3A C4 BA CE A8 CE 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CF 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CC 1A C9 82 C9 -26 CF 4E C8 2C CF 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CF DE C7 4E C8 5E CF B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A CB 06 4D -41 52 4B 45 52 00 B0 12 00 CD BA 40 85 12 FC FF -BA 40 5C CF FE FF 28 83 8A 48 00 00 BA 40 AA C4 -04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 -CA 21 D6 C7 4E C8 85 12 9E CF 66 CC D4 CD 10 C7 -7E CC 52 CE D2 C6 6E CF 00 C9 96 D0 AA D0 8A C8 -14 C9 00 00 46 CF BC CC E2 C9 00 00 85 12 9E CF -4A D6 B0 D6 F2 D5 00 D7 B8 D5 00 00 84 D3 00 00 -C8 D7 AC D7 1C D6 5A D6 94 D4 00 00 00 00 1C D7 -CA CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 DA 21 -30 4D A6 CF 24 D0 2A D0 3A D0 1A 42 20 18 82 4A -C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CC -09 50 57 52 5F 53 54 41 54 45 85 12 32 D0 D4 D7 -CE C8 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E D0 F3 3F 70 D0 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 21 7E D0 30 4D 82 D0 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 D1 FE FF 29 83 B9 40 -E2 C5 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C5 B2 49 FA C4 B2 49 02 C4 B2 49 00 C6 B2 49 -E0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 3F 40 -80 20 39 40 00 10 29 83 89 43 00 20 FC 23 B2 43 -06 02 B2 40 FC FF 02 02 F2 D3 26 02 F2 43 22 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B6 00 -82 01 B2 40 F4 00 84 01 82 43 88 01 F2 D0 03 00 -0B 02 39 40 80 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 FE C5 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 1A C9 82 C9 DE C7 34 C4 C4 D1 3E CA 34 C4 -DE D1 D8 D1 C6 D1 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 E0 D1 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 1A C9 82 C9 -DE C7 34 C4 FC D1 3E CA 34 C4 00 CC A8 C7 1A C9 -3E CA 34 C4 00 CC 08 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 A8 D1 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 6E CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 1A C9 3E CA -34 C4 50 D2 46 D2 21 53 3E 90 10 00 C6 2B 7F 2D -52 D2 B2 41 C4 21 C1 3F 0D 12 84 12 02 CC 84 D1 -62 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 A8 D1 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 A8 D1 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 30 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 30 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 30 D2 FA 23 -3C 50 10 00 B0 12 0C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 02 CC 84 D1 2E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 30 D2 E0 23 3C 50 80 00 B0 12 0C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -48 CB 4E C8 0A C4 2C 00 58 D2 24 D3 6E D3 09 4B -2E 4E 0E DC A2 3F 40 CE 03 4D 4F 56 85 12 64 D3 -00 40 78 D3 05 4D 4F 56 2E 42 85 12 64 D3 40 40 -00 00 03 41 44 44 85 12 64 D3 00 50 92 D3 05 41 -44 44 2E 42 85 12 64 D3 40 50 9E D3 04 41 44 44 -43 00 85 12 64 D3 00 60 AC D3 06 41 44 44 43 2E -42 00 85 12 64 D3 40 60 52 D3 04 53 55 42 43 00 -85 12 64 D3 00 70 CA D3 06 53 55 42 43 2E 42 00 -85 12 64 D3 40 70 D8 D3 03 53 55 42 85 12 64 D3 -00 80 E8 D3 05 53 55 42 2E 42 85 12 64 D3 40 80 -16 CE 03 43 4D 50 85 12 64 D3 00 90 02 D4 05 43 -4D 50 2E 42 85 12 64 D3 40 90 00 CE 04 44 41 44 -44 00 85 12 64 D3 00 A0 1C D4 06 44 41 44 44 2E -42 00 85 12 64 D3 40 A0 0E D4 03 42 49 54 85 12 -64 D3 00 B0 3A D4 05 42 49 54 2E 42 85 12 64 D3 -40 B0 46 D4 03 42 49 43 85 12 64 D3 00 C0 54 D4 -05 42 49 43 2E 42 85 12 64 D3 40 C0 60 D4 03 42 -49 53 85 12 64 D3 00 D0 6E D4 05 42 49 53 2E 42 -85 12 64 D3 40 D0 00 00 03 58 4F 52 85 12 64 D3 -00 E0 88 D4 05 58 4F 52 2E 42 85 12 64 D3 40 E0 -BA D3 03 41 4E 44 85 12 64 D3 00 F0 A2 D4 05 41 -4E 44 2E 42 85 12 64 D3 40 F0 02 CC 58 D2 C0 D4 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -F4 D3 03 52 52 43 85 12 BA D4 00 10 D2 D4 05 52 -52 43 2E 42 85 12 BA D4 40 10 DE D4 04 53 57 50 -42 00 85 12 BA D4 80 10 EC D4 03 52 52 41 85 12 -BA D4 00 11 FA D4 05 52 52 41 2E 42 85 12 BA D4 -40 11 06 D5 03 53 58 54 85 12 BA D4 80 11 00 00 -04 50 55 53 48 00 85 12 BA D4 00 12 20 D5 06 50 -55 53 48 2E 42 00 85 12 BA D4 40 12 7A D4 04 43 -41 4C 4C 00 85 12 BA D4 80 12 1A 53 0E 4A 0D 12 -84 12 C4 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 14 D5 03 53 3E 3D 86 12 00 38 -68 D5 02 53 3C 00 86 12 00 34 2E D5 03 30 3E 3D -86 12 00 30 7C D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C 90 D5 03 55 3E 3D 86 12 -00 28 86 D5 03 30 3C 3E 86 12 00 24 A4 D5 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D 9A D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -2A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 3E D5 -05 42 45 47 49 4E 30 40 28 C4 CE D5 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D AE D4 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 BC D5 A8 C7 4E C8 72 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 50 D6 D4 D5 4E C8 80 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 10 D6 03 42 57 31 85 12 7E D6 -00 00 98 D6 03 42 57 32 85 12 7E D6 00 00 A4 D6 -03 42 57 33 85 12 7E D6 00 00 BC D6 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 BA D6 00 00 DC D6 03 46 57 32 85 12 BA D6 -00 00 E8 D6 03 46 57 33 85 12 BA D6 00 00 F4 D6 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 80 CC DC CB 4E C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 02 CC 84 D1 3E D7 92 53 -C4 21 3E 40 2C 00 84 12 1A C9 3E CA 34 C4 00 CC -1A D3 54 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -6C D6 04 52 52 43 4D 00 85 12 38 D7 50 00 82 D7 -04 52 52 41 4D 00 85 12 38 D7 50 01 90 D7 04 52 -4C 41 4D 00 85 12 38 D7 50 02 9E D7 04 52 52 55 -4D 00 85 12 38 D7 50 03 AE D5 05 50 55 53 48 4D -85 12 38 D7 00 15 BA D7 04 50 4F 50 4D 00 85 12 -38 D7 00 17 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F5 3C 0E 93 3E 4F +77 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 98 C6 B2 49 +1C C7 B2 49 F4 C6 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 18 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 78 C8 AC C4 +42 C5 36 C7 1E C4 05 1B 5B 37 6D 40 62 C7 0A C4 +02 18 9A C8 C6 C9 62 C7 1E C4 04 1B 5B 30 6D 00 +62 C7 AE CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +0A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 36 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 62 C7 0A C4 02 18 9A C8 C6 C9 0A C4 23 00 +1A C7 C6 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +62 C7 0A C4 40 FF 32 C4 8E C8 92 C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B2 +01 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 43 06 02 B2 40 FC FF +02 02 F2 D3 26 02 F2 43 22 02 B2 40 00 A5 60 01 +82 43 88 01 F2 D0 03 00 0B 02 F2 C3 82 01 F2 D0 +06 00 82 01 B2 40 F4 00 84 01 39 40 80 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 39 40 00 10 29 83 +89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 3E F3 +02 20 1E 42 5E 01 B0 12 D0 C4 80 C5 00 00 0C 41 +43 43 45 50 54 00 30 40 9A C6 0A 4E 2E 4F 0A 5E +3B 40 0A 00 3C 40 20 00 3D 15 AA 3E 21 52 A2 C2 +6C 05 B2 B0 10 00 40 05 A3 22 3A 17 92 B3 6C 05 +FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 +F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B +45 59 30 40 F6 C6 58 43 B0 12 46 C5 2F 83 8F 4E +00 00 92 B3 6C 05 FD 27 1E 42 4C 05 B0 12 44 C5 +30 4D 00 00 08 45 4D 49 54 00 30 40 1E C7 08 4E +3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D 14 C7 +08 45 43 48 4F 00 B2 40 C2 48 28 C7 38 40 05 00 +B0 12 46 C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 28 C7 28 42 F3 3F 00 00 08 54 59 50 +45 00 0D 12 3D 40 72 C7 29 4F 8F 4E 00 00 7E 49 +D4 3F 74 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 8F 22 F9 98 00 00 8C 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 83 22 9B 24 EE C6 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 +92 C8 84 C7 D6 C9 90 CC B0 C4 00 C8 14 C4 06 5B +54 48 45 4E 5D 00 88 C7 DE C7 A4 C7 C2 C7 14 C4 +06 5B 45 4C 53 45 5D 00 88 C7 F0 C7 A4 C7 C0 C7 +1E C4 04 5B 49 46 5D 00 88 C7 C2 C7 B2 C4 C0 C7 +1E C4 05 0D 6B 6F 20 0A 62 C7 9A C4 84 C4 B2 C4 +C2 C7 B0 C7 0D 5B 54 48 45 4E 5D 00 30 4D 14 C8 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 20 C8 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 84 C7 +D6 C9 3E CA E2 CB 52 C9 30 C8 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 84 C7 D6 C9 3E CA +62 C8 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D 8E C6 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D E0 C5 05 53 22 00 +82 43 C0 21 0D 12 84 12 0A C4 1E C4 40 CC 0A C4 +22 00 D6 C9 D6 C8 B2 40 20 00 C0 21 1A 53 1A B3 +82 6A C8 21 3E 4F 3D 41 30 4D 48 C7 05 2E 22 00 +0D 12 84 12 C0 C8 0A C4 62 C7 40 CC 52 C9 00 00 +04 3C 23 00 B2 40 B2 21 B2 21 30 4D BC C8 02 23 +1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 21 18 42 B2 21 C8 4A 00 00 30 4D 0E C9 04 23 +53 00 0D 12 84 12 10 C9 4A C9 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 3E C9 04 23 3E 00 9F 42 B2 21 +00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F 58 C9 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 30 C7 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +04 C9 84 C7 72 C9 42 C9 6E C8 80 C9 5C C9 62 C7 +52 C9 EC C8 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D C4 C9 +0E 3E 4E 55 4D 42 45 52 1B 42 BE 21 3C 4F 38 4F +29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 +7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C +82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 +09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 +02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E +06 00 08 43 09 43 1B 42 BE 21 0C 4E 0E 43 1E 15 +3D 40 48 CB 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F +2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 +5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C +01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 +FC 9C 00 00 E0 23 AE 27 4A CB 2F 24 2D 83 6A 4C +7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 +7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 +02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +00 00 0E 4B 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F +04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 +00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 +04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 +BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 +01 20 2F 53 30 4D 00 C9 03 5C 92 42 C2 21 C6 21 +30 4D 0D 12 84 12 84 C4 84 C7 D6 C9 B0 C4 1A CD +3E CA 04 CC 0A 4E 3E 4F 3D 40 1E CC 6D 27 3D 40 +F8 CB 1A E2 BC 21 14 24 0E 12 3E 4F 30 41 20 CC +3E 4F 3D 40 F8 CB 19 20 DE 53 00 00 68 4E 08 5E +F8 40 3F 00 00 00 3D 40 F6 CD 2A 3C E8 CB 02 2C +A2 53 C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D +3E CC 0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 +09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 +8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +8A 4E 02 00 EE 3F 30 4D 7A C9 0A 43 4F 55 4E 54 +2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D A0 C8 +0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 +80 20 0E 43 84 12 1E C4 02 0D 0A 00 62 C7 94 C4 +F2 CB 80 C8 AA C8 1E C4 0B 73 74 61 63 6B 20 65 +6D 70 74 79 08 C5 32 C4 0A C4 40 FF B2 C8 1E C4 +09 46 52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 B6 CC +A0 CC 0D 41 42 4F 52 54 22 00 0D 12 84 12 C0 C8 +0A C4 08 C5 40 CC 52 C9 D0 C9 02 27 0D 12 84 12 +84 C7 D6 C9 3E CA B0 C4 1C CD E4 C8 28 CC 4A C8 +07 5B 27 5D 0D 12 84 12 0C CD 0A C4 0A C4 40 CC +40 CC 52 C9 20 CD 03 5B 82 43 BC 21 30 4D 00 00 +02 5D B2 43 BC 21 30 4D 98 C8 11 50 4F 53 54 50 +4F 4E 45 00 0D 12 84 12 84 C7 D6 C9 3E CA B0 C4 +1C CD AA C8 AC C4 74 CD 0A C4 0A C4 40 CC 40 CC +0A C4 40 CC 40 CC 52 C9 00 00 02 3A 30 12 CA CD +92 B3 C8 21 A2 63 C8 21 0D 12 84 12 84 C7 D6 C9 +92 CD 3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E +5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +00 00 82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F +BA 21 2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF +BA 40 84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 +66 25 84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 +6D 61 74 63 68 21 12 C5 36 CD 03 3B 82 93 BC 21 +F4 26 0D 12 84 12 0A C4 52 C9 40 CC DC CD 38 CD +52 C9 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +B4 21 D8 D3 00 00 30 4D 8A CC 0C 43 52 45 41 54 +45 00 B0 12 80 CD BA 40 86 12 FC FF 8A 4A FE FF +3A 3D 5C C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 +85 12 00 00 8A 4D 02 00 3D 41 30 4D 7A CD 0E 3A +4E 4F 4E 41 4D 45 30 12 CA CD 2F 83 8F 4E 00 00 +1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +98 3F 14 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 +84 12 0C CD 96 CE 3D 41 BE 4F 02 00 3E 4F 30 4D +84 12 24 CD 0A C4 98 CE 40 CC 52 C9 2A CE 08 43 +4F 44 45 00 B0 12 80 CD A2 82 C8 21 61 3C 6C C9 +0E 48 44 4E 43 4F 44 45 B2 40 84 CF CC 21 F2 3F +00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 DC CD +E2 CE 3D 41 92 42 D0 21 CC 21 5D 3C AE CE 0E 43 +4F 44 45 4E 4E 4D 30 12 B8 CE B7 3F 00 00 0A 43 +4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 +84 12 02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 +0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F +C0 CE 0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 +8A 4A FE FF 82 43 BC 21 B9 3F 4C CF B2 40 5E CF +D0 21 82 4E CE 21 30 40 E4 C8 85 12 4A CF 4A CD +F2 CC DC CF EE CE 44 CE 8E C9 38 CA 0A CD 32 CF +84 CE 5E CE FA CD 52 CC 66 D0 90 CA 00 00 00 00 +85 12 4A CF E0 D6 64 D5 C4 D6 8C D4 E8 D4 36 D5 +12 D6 1E D6 AE D3 D2 D4 00 00 00 00 20 CF 9E D2 +00 00 3A D6 7E CF B2 40 5E CF CE 21 82 43 D0 21 +30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 +30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 +3A 40 42 18 B0 12 B2 CF 30 4D C4 CF 0E 52 53 54 +5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 +B2 CF 1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 +18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 +2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 +29 83 B9 43 80 FF FC 23 B9 40 0E C6 FE FF 29 83 +B9 40 FA C5 FE FF 39 90 AE FF F9 23 39 40 10 18 +B2 49 E0 FF 3B 40 10 00 3A 40 3A 18 B0 12 B6 CF +82 43 4A 18 C7 3F 58 D0 B2 4E 42 18 BE 12 3E 4F +3D 41 C0 3F 40 CD 0C 4D 41 52 4B 45 52 00 12 12 +C6 21 0D 12 84 12 84 C7 D6 C9 3E CA AC C4 84 D0 +78 C8 18 CC 86 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 +80 CD BA 40 85 12 FC FF BA 40 56 D0 FE FF 28 83 +8A 48 00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 +B4 21 19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D +12 12 C6 21 84 12 D6 C9 3E CA AC C4 F0 D0 D0 D0 +3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C +BE 90 56 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 +E8 CA AC C4 F8 D0 EC D0 FA D0 B2 41 C6 21 30 41 +92 83 C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 C0 D0 +15 20 3E 40 2B 00 B0 12 C0 D0 06 20 3E 40 2D 00 +B0 12 C0 D0 92 83 C6 21 0E 12 1E 41 02 00 84 12 +D6 C9 E8 CA AC C4 1C CD 3A D1 3E 51 3A 17 30 41 +B0 12 00 D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 +3E 40 29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 +D6 C9 E8 CA AC C4 72 D1 6A D1 3E 90 10 00 E6 2B +7C 2D 74 D1 A2 41 C6 21 E1 3F 03 20 B0 12 58 D1 +43 3C 7A 90 23 00 24 20 B0 12 08 D1 3C 40 00 03 +0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 +2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 +3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 +19 42 C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D +7A 90 26 00 05 20 3C 40 10 02 B0 12 08 D1 F0 3F +7A 90 40 00 14 20 3C 40 20 00 B0 12 54 D1 0C 20 +3C D0 10 00 3E 40 2B 00 B0 12 58 D1 92 92 C2 21 +C6 21 02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 +10 00 B0 12 40 D1 F2 3F 03 20 B0 12 58 D1 F5 3F +7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 +B0 12 40 D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 +3A 40 20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 +5A 49 FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 +30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 +00 13 40 CC 52 C9 0A C4 2C 00 36 D2 7A D1 84 C7 +40 D2 18 D2 86 D2 3D 41 2C DE 8B 4C 00 00 9E 3F +00 00 06 4D 4F 56 85 12 76 D2 00 40 92 D2 0A 4D +4F 56 2E 42 85 12 76 D2 40 40 00 00 06 41 44 44 +85 12 76 D2 00 50 AC D2 0A 41 44 44 2E 42 85 12 +76 D2 40 50 B8 D2 08 41 44 44 43 00 85 12 76 D2 +00 60 C6 D2 0C 41 44 44 43 2E 42 00 85 12 76 D2 +40 60 FE CE 08 53 55 42 43 00 85 12 76 D2 00 70 +E4 D2 0C 53 55 42 43 2E 42 00 85 12 76 D2 40 70 +F2 D2 06 53 55 42 85 12 76 D2 00 80 02 D3 0A 53 +55 42 2E 42 85 12 76 D2 40 80 0E D3 06 43 4D 50 +85 12 76 D2 00 90 1C D3 0A 43 4D 50 2E 42 85 12 +76 D2 40 90 00 00 08 44 41 44 44 00 85 12 76 D2 +00 A0 36 D3 0C 44 41 44 44 2E 42 00 85 12 76 D2 +40 A0 64 D2 06 42 49 54 85 12 76 D2 00 B0 54 D3 +0A 42 49 54 2E 42 85 12 76 D2 40 B0 60 D3 06 42 +49 43 85 12 76 D2 00 C0 6E D3 0A 42 49 43 2E 42 +85 12 76 D2 40 C0 7A D3 06 42 49 53 85 12 76 D2 +00 D0 88 D3 0A 42 49 53 2E 42 85 12 76 D2 40 D0 +00 00 06 58 4F 52 85 12 76 D2 00 E0 A2 D3 0A 58 +4F 52 2E 42 85 12 76 D2 40 E0 D4 D2 06 41 4E 44 +85 12 76 D2 00 F0 BC D3 0A 41 4E 44 2E 42 85 12 +76 D2 40 F0 84 C7 36 D2 7A D1 DC D3 0A 4C 3C F0 +70 00 8A 10 3A F0 0F 00 0C DA 4D 3F 94 D3 06 52 +52 43 85 12 D4 D3 00 10 EE D3 0A 52 52 43 2E 42 +85 12 D4 D3 40 10 28 D3 08 53 57 50 42 00 85 12 +D4 D3 80 10 FA D3 06 52 52 41 85 12 D4 D3 00 11 +16 D4 0A 52 52 41 2E 42 85 12 D4 D3 40 11 08 D4 +06 53 58 54 85 12 D4 D3 80 11 00 00 08 50 55 53 +48 00 85 12 D4 D3 00 12 3C D4 0C 50 55 53 48 2E +42 00 85 12 D4 D3 40 12 30 D4 08 43 41 4C 4C 00 +85 12 D4 D3 80 12 1A 53 0E 4A 84 12 C6 C9 1E C4 +0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 +5A D4 06 53 3E 3D 86 12 00 38 82 D4 04 53 3C 00 +86 12 00 34 4A D4 06 30 3E 3D 86 12 00 30 96 D4 +04 30 3C 00 86 12 00 30 D2 CE 04 55 3C 00 86 12 +00 2C AA D4 06 55 3E 3D 86 12 00 28 A0 D4 06 30 +3C 3E 86 12 00 24 BE D4 04 30 3D 00 86 12 00 20 +00 00 04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 +C8 21 0E 4A 30 4D 44 D3 08 54 48 45 4E 00 1A 42 +C8 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 +00 02 B2 2F 88 DA 00 00 30 4D B4 D4 08 45 4C 53 +45 00 1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 +2F 83 8F 4A 00 00 E3 3F 22 D4 0A 42 45 47 49 4E +30 40 32 C4 0C D5 0A 55 4E 54 49 4C 3A 4F 08 4E +3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE +8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 +30 4D C8 D3 0A 41 47 41 49 4E 0A 4E 38 40 00 3C +E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 D6 D4 +6C C8 52 C9 2A D5 0C 52 45 50 45 41 54 00 0D 12 +84 12 6A D5 EE D4 52 C9 9A D5 3D 41 08 4E 3E 4F +2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D +86 D5 06 42 57 31 85 12 98 D5 00 00 B2 D5 06 42 +57 32 85 12 98 D5 00 00 BE D5 06 42 57 33 85 12 +98 D5 00 00 D6 D5 3D 41 1A 42 C8 21 28 4E 8E 43 +00 00 B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 +8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 +D4 D5 00 00 FA D5 06 46 57 32 85 12 D4 D5 00 00 +06 D6 06 46 57 33 85 12 D4 D5 00 00 74 D5 08 47 +4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 +84 12 0C CD 18 CC 52 C9 00 00 0A 3F 47 4F 54 4F +3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 +3E E0 00 08 EC 3F 40 D2 0A C4 2C 00 D6 C9 E8 CA +AC C4 1C CD 84 C7 36 D2 18 D2 6C D6 0A 4E 3E 4F +1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 +0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 +EA 2E 8A 10 5A 06 A8 3E CA D5 08 52 52 43 4D 00 +85 12 56 D6 50 00 9A D6 08 52 52 41 4D 00 85 12 +56 D6 50 01 A8 D6 08 52 4C 41 4D 00 85 12 56 D6 +50 02 B6 D6 08 52 52 55 4D 00 85 12 56 D6 50 03 +C8 D4 0A 50 55 53 48 4D 85 12 56 D6 00 15 D2 D6 +08 50 4F 50 4D 00 85 12 56 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -82 C6 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 08 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +AC C6 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR2433_8MHz_UART.txt b/binaries/MSP_EXP430FR2433_8MHz_UART.txt deleted file mode 100644 index 56b4116..0000000 --- a/binaries/MSP_EXP430FR2433_8MHz_UART.txt +++ /dev/null @@ -1,335 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF EA D7 02 D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 EA D7 -02 D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 CE D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 28 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 30 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 D2 D3 02 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 D2 C3 02 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 F2 B2 01 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 14 CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -5A CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -5A CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 21 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 21 0C 43 2D 15 3D 40 AE CA -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 CA -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C4 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 21 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 21 8A 4E -00 00 A2 53 C6 21 3E 4F 30 4D 58 CB 87 4C 49 54 -45 52 41 4C 82 93 BE 21 0D 24 09 4E 1A 42 C6 21 -A2 52 C6 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C8 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C8 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C4 14 CC 2C C9 D0 CB -9C 26 3D 40 D8 CB DE 3E DA CB 0A 4E 3E 4F 3D 40 -F4 CB 36 27 3D 40 CA CB 1A E2 BE 21 B6 27 0E 12 -3E 4F 30 41 F6 CB 3E 4F 3D 40 CA CB BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CD -CC 3F FE CB 86 12 20 00 E6 C7 05 41 4C 4C 4F 54 -82 5E C6 21 3E 4F 30 4D 3F 40 80 20 0E 43 31 40 -E0 20 B2 40 00 20 00 20 82 43 BE 21 84 12 8E C7 -BC C4 C4 CB C4 C7 F6 C7 14 C4 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C5 0A C4 40 FF 28 C4 -FE C7 14 C4 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C5 3A C4 3E CC 1A CC 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C8 0A C4 2A C5 5A CB 60 C8 8E C9 -01 27 0D 12 84 12 14 CC 2C C9 94 C9 34 C4 12 CC -60 C8 00 00 83 5B 27 5D 0D 12 84 12 92 CC 0A C4 -0A C4 5A CB 5A CB 60 C8 A4 CC 81 5B 82 43 BE 21 -30 4D 0C C8 01 5D B2 43 BE 21 30 4D C4 CC 81 5C -92 42 C0 21 C4 21 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CC 2C C9 94 C9 A8 C7 -34 C4 12 CC F6 C7 34 C4 06 CD 0A C4 0A C4 5A CB -5A CB 0A C4 5A CB 5A CB 60 C8 BA CC 01 3A 30 12 -56 CD 92 B3 C6 21 A2 63 C6 21 0D 12 84 12 14 CC -2C C9 24 CD 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 21 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 21 82 49 B8 21 82 4A BA 21 82 4F BC 21 2A 52 -82 4A C6 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 21 30 4D 82 9F BC 21 09 20 18 42 -B6 21 19 42 B8 21 A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C4 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C5 0C CD 81 3B 82 93 BE 21 -97 27 0D 12 84 12 0A C4 60 C8 5A CB 68 CD BC CC -60 C8 BA CB 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 21 F8 D0 80 00 00 00 30 4D A4 CB 06 43 52 45 -41 54 45 00 B0 12 12 CD BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CD 04 43 4F 44 45 00 B0 12 12 CD -A2 82 C6 21 0D 12 84 12 04 D0 DE CF 60 C8 B4 CD -07 48 44 4E 43 4F 44 45 B2 40 E2 CF DA 21 EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CD -1E D0 3C D0 60 C8 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 21 B2 43 BE 21 0D 12 84 12 1E D0 3C D0 60 C8 -00 00 05 4C 4F 32 48 49 A2 83 C6 21 1A 42 C6 21 -EB 3F 00 CE 85 48 49 32 4C 4F 0D 12 84 12 28 C4 -AC CF 5A CB BC CC F4 CD 60 C8 9A CD 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CE 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C4 00 00 D8 C7 14 CC 2C C9 -AA CB A0 C7 34 C4 14 CF AE C7 14 C4 06 5B 54 48 -45 4E 5D 00 86 CE EE CE AA CE CC CE 60 C8 AE C7 -14 C4 06 5B 45 4C 53 45 5D 00 86 CE 04 CF AA CE -CA CE 60 C8 14 C4 04 5B 49 46 5D 00 86 CE CC CE -3A C4 CA CE 82 C7 14 C4 05 0D 0A 6B 6F 20 5C C7 -BC C4 AC C4 3A C4 CC CE BA CE 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CF 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CC 2C C9 -94 C9 38 CF 60 C8 3E CF 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CF F0 C7 60 C8 70 CF -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C CB -06 4D 41 52 4B 45 52 00 B0 12 12 CD BA 40 85 12 -FC FF BA 40 6E CF FE FF 28 83 8A 48 00 00 BA 40 -AA C4 04 00 B2 50 06 00 C6 21 E1 3E 2E 53 30 4D -0A C4 CA 21 E8 C7 60 C8 85 12 B0 CF 78 CC E6 CD -2C C7 90 CC 64 CE F6 C6 80 CF 12 C9 A8 D0 BC D0 -9C C8 26 C9 00 00 58 CF CE CC F4 C9 00 00 85 12 -B0 CF 60 D6 C6 D6 08 D6 16 D7 CE D5 00 00 9A D3 -00 00 DE D7 C2 D7 32 D6 70 D6 AA D4 00 00 00 00 -32 D7 DC CF 3A 40 0C 00 39 40 D6 21 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 21 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 21 30 4D 92 42 CA 21 -DA 21 30 4D B8 CF 36 D0 3C D0 4C D0 1A 42 20 18 -82 4A C8 21 2E 4E 82 4E C6 21 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CC 09 50 57 52 5F 53 54 41 54 45 85 12 44 D0 -EA D7 E0 C8 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 D0 F3 3F 82 D0 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 21 90 D0 30 4D 94 D0 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 21 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A D1 FE FF 29 83 -B9 40 02 C6 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C6 B2 49 FA C4 B2 49 02 C4 B2 49 20 C6 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A CC 01 31 40 E0 20 -3F 40 80 20 39 40 00 10 29 83 89 43 00 20 FC 23 -B2 43 06 02 B2 40 FC FF 02 02 D2 D3 04 02 F2 D3 -26 02 F2 43 22 02 B2 40 00 A5 60 01 B2 40 FF 1E -80 01 B2 40 B6 00 82 01 B2 40 F4 00 84 01 82 43 -88 01 F2 D0 03 00 0B 02 39 40 80 00 18 42 00 18 -18 83 FE 23 19 83 FA 23 1E 42 08 18 82 43 08 18 -1E D2 5E 01 B0 12 F8 C4 1E C6 38 40 C0 21 0A 4E -39 48 2E 48 09 5E 1E 52 C4 21 09 9E 03 24 7A 9E -FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 30 4D 1C 15 -0E 12 12 12 C4 21 84 12 2C C9 94 C9 F0 C7 34 C4 -DA D1 50 CA 34 C4 F4 D1 EE D1 DC D1 3C 4E 3C 80 -87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 -1B 17 30 41 F6 D1 B2 41 C4 21 3E 41 84 12 0A C4 -2B 00 2C C9 94 C9 F0 C7 34 C4 12 D2 50 CA 34 C4 -12 CC BA C7 2C C9 50 CA 34 C4 12 CC 1E D2 3E 5F -E7 3F 3E 40 28 00 B0 12 BE D1 19 42 C6 21 A2 53 -C6 21 89 4E 00 00 3E 40 29 00 92 92 C0 21 C4 21 -02 20 30 40 80 CD 1C 15 12 12 C4 21 92 53 C4 21 -84 12 2C C9 50 CA 34 C4 66 D2 5C D2 21 53 3E 90 -10 00 C6 2B 7F 2D 68 D2 B2 41 C4 21 C1 3F 0D 12 -84 12 14 CC 9A D1 78 D2 0C 43 1B 42 C6 21 A2 53 -C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 21 -B0 12 BE D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 -1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 -2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 21 A2 53 C6 21 -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 -3C 40 10 02 92 53 C4 21 B0 12 BE D1 ED 3F 7A 90 -40 00 16 20 3C 40 20 00 92 53 C4 21 B0 12 46 D2 -0C 20 3C 50 10 00 3E 40 2B 00 B0 12 46 D2 92 92 -C0 21 C4 21 02 24 92 53 C4 21 8E 10 0C 5E DA 3F -B0 12 46 D2 FA 23 3C 50 10 00 B0 12 22 D2 EF 3F -0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 84 12 14 CC -9A D1 44 D3 FE 90 26 00 00 00 3E 40 20 00 03 20 -3C 50 82 00 C7 3F B0 12 46 D2 E0 23 3C 50 80 00 -B0 12 22 D2 DB 3F 00 00 04 52 45 54 49 00 0D 12 -84 12 0A C4 00 13 5A CB 60 C8 0A C4 2C 00 6E D2 -3A D3 84 D3 09 4B 2E 4E 0E DC A2 3F 52 CE 03 4D -4F 56 85 12 7A D3 00 40 8E D3 05 4D 4F 56 2E 42 -85 12 7A D3 40 40 00 00 03 41 44 44 85 12 7A D3 -00 50 A8 D3 05 41 44 44 2E 42 85 12 7A D3 40 50 -B4 D3 04 41 44 44 43 00 85 12 7A D3 00 60 C2 D3 -06 41 44 44 43 2E 42 00 85 12 7A D3 40 60 68 D3 -04 53 55 42 43 00 85 12 7A D3 00 70 E0 D3 06 53 -55 42 43 2E 42 00 85 12 7A D3 40 70 EE D3 03 53 -55 42 85 12 7A D3 00 80 FE D3 05 53 55 42 2E 42 -85 12 7A D3 40 80 28 CE 03 43 4D 50 85 12 7A D3 -00 90 18 D4 05 43 4D 50 2E 42 85 12 7A D3 40 90 -12 CE 04 44 41 44 44 00 85 12 7A D3 00 A0 32 D4 -06 44 41 44 44 2E 42 00 85 12 7A D3 40 A0 24 D4 -03 42 49 54 85 12 7A D3 00 B0 50 D4 05 42 49 54 -2E 42 85 12 7A D3 40 B0 5C D4 03 42 49 43 85 12 -7A D3 00 C0 6A D4 05 42 49 43 2E 42 85 12 7A D3 -40 C0 76 D4 03 42 49 53 85 12 7A D3 00 D0 84 D4 -05 42 49 53 2E 42 85 12 7A D3 40 D0 00 00 03 58 -4F 52 85 12 7A D3 00 E0 9E D4 05 58 4F 52 2E 42 -85 12 7A D3 40 E0 D0 D3 03 41 4E 44 85 12 7A D3 -00 F0 B8 D4 05 41 4E 44 2E 42 85 12 7A D3 40 F0 -14 CC 6E D2 D6 D4 0A 4C 3C F0 70 00 8A 10 3A F0 -0F 00 0C DA 4F 3F 0A D4 03 52 52 43 85 12 D0 D4 -00 10 E8 D4 05 52 52 43 2E 42 85 12 D0 D4 40 10 -F4 D4 04 53 57 50 42 00 85 12 D0 D4 80 10 02 D5 -03 52 52 41 85 12 D0 D4 00 11 10 D5 05 52 52 41 -2E 42 85 12 D0 D4 40 11 1C D5 03 53 58 54 85 12 -D0 D4 80 11 00 00 04 50 55 53 48 00 85 12 D0 D4 -00 12 36 D5 06 50 55 53 48 2E 42 00 85 12 D0 D4 -40 12 90 D4 04 43 41 4C 4C 00 85 12 D0 D4 80 12 -1A 53 0E 4A 0D 12 84 12 D6 C8 14 C4 0D 6F 75 74 -20 6F 66 20 62 6F 75 6E 64 73 36 C5 2A D5 03 53 -3E 3D 86 12 00 38 7E D5 02 53 3C 00 86 12 00 34 -44 D5 03 30 3E 3D 86 12 00 30 92 D5 02 30 3C 00 -86 12 00 30 00 00 02 55 3C 00 86 12 00 2C A6 D5 -03 55 3E 3D 86 12 00 28 9C D5 03 30 3C 3E 86 12 -00 24 BA D5 02 30 3D 00 86 12 00 20 00 00 02 49 -46 00 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 0E 4A -30 4D B0 D5 04 54 48 45 4E 00 1A 42 C6 21 08 4E -3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F -88 DA 00 00 30 4D 40 D4 04 45 4C 53 45 00 1A 42 -C6 21 BA 40 00 3C 00 00 A2 53 C6 21 2F 83 8F 4A -00 00 E3 3F 54 D5 05 42 45 47 49 4E 30 40 28 C4 -E4 D5 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 -C6 21 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 -FF 03 08 DA 89 48 00 00 A2 53 C6 21 30 4D C4 D4 -05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 -05 57 48 49 4C 45 0D 12 84 12 D2 D5 BA C7 60 C8 -88 D5 06 52 45 50 45 41 54 00 0D 12 84 12 66 D6 -EA D5 60 C8 96 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 -C4 21 CB 2F 98 42 C6 21 00 00 30 4D 26 D6 03 42 -57 31 85 12 94 D6 00 00 AE D6 03 42 57 32 85 12 -94 D6 00 00 BA D6 03 42 57 33 85 12 94 D6 00 00 -D2 D6 3D 41 1A 42 C6 21 28 4E B2 92 C4 21 88 2B -BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 3E 4F 30 4D -00 00 03 46 57 31 85 12 D0 D6 00 00 F2 D6 03 46 -57 32 85 12 D0 D6 00 00 FE D6 03 46 57 33 85 12 -D0 D6 00 00 0A D7 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C 0D 12 84 12 92 CC EE CB 60 C8 -00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 -00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 14 CC -9A D1 54 D7 92 53 C4 21 3E 40 2C 00 84 12 2C C9 -50 CA 34 C4 12 CC 30 D3 6A D7 0A 4E 3E 4F 1A 83 -F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A -08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E -8A 10 5A 06 A6 3E 82 D6 04 52 52 43 4D 00 85 12 -4E D7 50 00 98 D7 04 52 52 41 4D 00 85 12 4E D7 -50 01 A6 D7 04 52 4C 41 4D 00 85 12 4E D7 50 02 -B4 D7 04 52 52 55 4D 00 85 12 4E D7 50 03 C4 D5 -05 50 55 53 48 4D 85 12 4E D7 00 15 D0 D7 04 50 -4F 50 4D 00 85 12 4E D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 94 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 1A D1 -q diff --git a/binaries/MSP_EXP430FR4133_16MHz_115200.txt b/binaries/MSP_EXP430FR4133_16MHz_115200.txt new file mode 100644 index 0000000..80d9649 --- /dev/null +++ b/binaries/MSP_EXP430FR4133_16MHz_115200.txt @@ -0,0 +1,329 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A0 59 +D2 C6 7E C5 84 C5 54 C5 42 C7 6A D7 22 D0 DC CF +DC CF B8 C6 76 C7 3E C7 3C 21 E0 20 96 C9 B6 C4 +C4 C4 B2 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +42 C7 6A D7 22 D0 DC CF DC CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 04 3D 0E 93 3E 4F +99 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B6 C6 B2 49 +74 C7 B2 49 3C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 96 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 42 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 BC C8 AC C4 52 C5 84 C7 1E C4 04 1B +5B 37 6D 00 A6 C7 A6 C7 1E C4 04 1B 5B 30 6D 00 +A6 C7 2C CD B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 03 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 84 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 A6 C7 0A CA 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A6 C7 0A C4 40 FF 32 C4 +D2 C8 D6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B2 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 D3 02 02 F2 D2 05 02 B2 D0 FF FE +26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 +66 02 B2 43 62 02 F2 40 A5 00 A1 01 F2 40 10 00 +A0 01 D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 06 00 2B 02 F2 C3 82 01 F2 D0 0A 00 82 01 +B2 40 E8 01 84 01 39 40 40 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 08 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 B8 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 16 C7 3C 40 22 C7 5D 15 +97 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 F2 D2 03 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D 18 C7 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 3E C7 30 12 +54 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 F2 C2 +03 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 DE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 76 C7 08 4E 3E 4F C7 3F 6C C7 08 45 +43 48 4F 00 B2 40 C2 48 10 C7 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 10 C7 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 B6 C7 29 4F 8F 4E +00 00 7E 49 DE 3F B8 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 6D 22 F9 98 00 00 6A 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 61 22 +9B 24 36 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 D6 C8 C8 C7 1A CA 0E CD B0 C4 44 C8 +14 C4 06 5B 54 48 45 4E 5D 00 CC C7 22 C8 E8 C7 +06 C8 14 C4 06 5B 45 4C 53 45 5D 00 CC C7 34 C8 +E8 C7 04 C8 1E C4 04 5B 49 46 5D 00 CC C7 06 C8 +B2 C4 04 C8 1E C4 05 0D 6B 6F 20 0A A6 C7 9A C4 +84 C4 B2 C4 06 C8 F4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 58 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 64 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 C8 C7 1A CA 82 CA 60 CC 96 C9 74 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 C8 C7 +1A CA 82 CA A6 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D AC C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +BE CC 0A C4 22 00 1A CA 1A C9 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 8E C7 +05 2E 22 00 0D 12 84 12 04 C9 0A C4 A6 C7 BE CC +96 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +00 C9 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +52 C9 04 23 53 00 0D 12 84 12 54 C9 8E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 82 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 9C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +7E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 48 C9 C8 C7 B6 C9 86 C9 B2 C8 C4 C9 +A0 C9 A6 C7 96 C9 30 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D D2 C9 06 55 4D 2A 2C 4F 0B 43 09 43 08 43 +1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A +F8 2B 8F 49 00 00 0E 48 30 4D 08 CA 0E 3E 4E 55 +4D 42 45 52 1A 42 BE 21 2C 4F 0B 4E 68 4C 78 80 +3A 00 03 28 78 80 07 00 21 28 78 50 0A 00 08 9A +22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 32 CB +D4 3F 34 CB 81 49 02 00 1C 4F 04 00 1E 41 04 00 +3D 40 46 CB CA 3F 48 CB 39 51 3E 61 8F 49 04 00 +8F 4E 02 00 3A 17 1C 53 1B 83 D8 23 8F 4C 00 00 +0E 4B 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 8F 43 +04 00 8F 43 02 00 1A 42 BE 21 0C 4E 0E 43 1E 15 +3D 40 C8 CB 7B 4C 68 4C 78 80 2D 00 16 24 BE 2F +2A 43 78 52 14 24 3A 52 68 53 11 24 3A 40 10 00 +58 93 0D 24 68 92 40 20 3E 90 03 00 3D 20 FC 9C +01 00 6C 4C 8F 4C 04 00 37 3C B1 43 02 00 1B 83 +FC 9C 00 00 E0 23 A2 27 CA CB 2E 24 2D 83 68 4C +78 90 5F 00 C0 27 32 B0 00 02 26 20 32 D0 00 02 +78 80 2E 00 B8 27 68 53 1F 20 09 43 8F 49 02 00 +5B 83 09 4B 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9A 08 2C 8F 49 00 00 +0E 4A 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4B 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 44 C9 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 C4 C8 C7 1A CA B0 C4 98 CD 82 CA +82 CC 0A 4E 3E 4F 3D 40 9C CC 6C 27 3D 40 76 CC +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 9E CC 3E 4F +3D 40 76 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 74 CE 2A 3C 66 CC 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D BC CC +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D BE C9 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D E4 C8 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E C4 02 0D 0A 00 A6 C7 94 C4 70 CC +C4 C8 EE C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C5 32 C4 0A C4 40 FF F6 C8 1E C4 09 46 +52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 34 CD 1E CD +0D 41 42 4F 52 54 22 00 0D 12 84 12 04 C9 0A C4 +08 C5 BE CC 96 C9 14 CA 02 27 0D 12 84 12 C8 C7 +1A CA 82 CA B0 C4 9A CD 28 C9 A6 CC 8E C8 07 5B +27 5D 0D 12 84 12 8A CD 0A C4 0A C4 BE CC BE CC +96 C9 9E CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D DC C8 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C8 C7 1A CA 82 CA B0 C4 9A CD +EE C8 AC C4 F2 CD 0A C4 0A C4 BE CC BE CC 0A C4 +BE CC BE CC 96 C9 00 00 02 3A 30 12 48 CE 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C8 C7 1A CA 10 CE +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C5 B4 CD 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A C4 96 C9 BE CC 5A CE B6 CD 96 C9 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D 08 CD 0C 43 52 45 41 54 45 00 +B0 12 FE CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +A0 C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D F8 CD 0E 3A 4E 4F +4E 41 4D 45 30 12 48 CE 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +92 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +8A CD 14 CF 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +A2 CD 0A C4 16 CF BE CC 96 C9 A8 CE 08 43 4F 44 +45 00 B0 12 FE CD A2 82 C8 21 61 3C B0 C9 0E 48 +44 4E 43 4F 44 45 B2 40 02 D0 CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 5A CE 60 CF +3D 41 92 42 D0 21 CC 21 5D 3C 2C CF 0E 43 4F 44 +45 4E 4E 4D 30 12 36 CF B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F 3E CF +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F CA CF B2 40 DC CF D0 21 +82 4E CE 21 30 40 28 C9 85 12 C8 CF C8 CD 70 CD +5A D0 6C CF C2 CE D4 CA 7C CA 88 CD B0 CF 02 CF +DC CE 78 CE D0 CC E4 D0 FC CA 00 00 00 00 85 12 +C8 CF 5E D7 E2 D5 42 D7 0A D5 66 D5 B4 D5 90 D6 +9C D6 2C D4 50 D5 00 00 00 00 9E CF 1C D3 00 00 +B8 D6 FC CF B2 40 DC CF CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 30 D0 30 4D 42 D0 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 30 D0 +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 C6 FE FF 29 83 B9 40 +F2 C5 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +EC FF 3B 40 10 00 3A 40 3A 18 B0 12 34 D0 82 43 +4A 18 C7 3F D6 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F BE CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C8 C7 1A CA 82 CA AC C4 02 D1 BC C8 +96 CC 04 D1 3E 4F 3D 41 B2 41 C6 21 B0 12 FE CD +BA 40 85 12 FC FF BA 40 D4 D0 FE FF 28 83 8A 48 +00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 1A CA 82 CA AC C4 6E D1 4E D1 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +D4 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 64 CB +AC C4 76 D1 6A D1 78 D1 B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 3E D1 15 20 +3E 40 2B 00 B0 12 3E D1 06 20 3E 40 2D 00 B0 12 +3E D1 92 83 C6 21 0E 12 1E 41 02 00 84 12 1A CA +64 CB AC C4 9A CD B8 D1 3E 51 3A 17 30 41 B0 12 +7E D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 1A CA +64 CB AC C4 F0 D1 E8 D1 3E 90 10 00 E6 2B 7C 2D +F2 D1 A2 41 C6 21 E1 3F 03 20 B0 12 D6 D1 43 3C +7A 90 23 00 24 20 B0 12 86 D1 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 86 D1 F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 D2 D1 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 D6 D1 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 BE D1 F2 3F 03 20 B0 12 D6 D1 F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +BE D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 +BE CC 96 C9 0A C4 2C 00 B4 D2 F8 D1 C8 C7 BE D2 +96 D2 04 D3 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 F4 D2 00 40 10 D3 0A 4D 4F 56 +2E 42 85 12 F4 D2 40 40 00 00 06 41 44 44 85 12 +F4 D2 00 50 2A D3 0A 41 44 44 2E 42 85 12 F4 D2 +40 50 36 D3 08 41 44 44 43 00 85 12 F4 D2 00 60 +44 D3 0C 41 44 44 43 2E 42 00 85 12 F4 D2 40 60 +7C CF 08 53 55 42 43 00 85 12 F4 D2 00 70 62 D3 +0C 53 55 42 43 2E 42 00 85 12 F4 D2 40 70 70 D3 +06 53 55 42 85 12 F4 D2 00 80 80 D3 0A 53 55 42 +2E 42 85 12 F4 D2 40 80 8C D3 06 43 4D 50 85 12 +F4 D2 00 90 9A D3 0A 43 4D 50 2E 42 85 12 F4 D2 +40 90 00 00 08 44 41 44 44 00 85 12 F4 D2 00 A0 +B4 D3 0C 44 41 44 44 2E 42 00 85 12 F4 D2 40 A0 +E2 D2 06 42 49 54 85 12 F4 D2 00 B0 D2 D3 0A 42 +49 54 2E 42 85 12 F4 D2 40 B0 DE D3 06 42 49 43 +85 12 F4 D2 00 C0 EC D3 0A 42 49 43 2E 42 85 12 +F4 D2 40 C0 F8 D3 06 42 49 53 85 12 F4 D2 00 D0 +06 D4 0A 42 49 53 2E 42 85 12 F4 D2 40 D0 00 00 +06 58 4F 52 85 12 F4 D2 00 E0 20 D4 0A 58 4F 52 +2E 42 85 12 F4 D2 40 E0 52 D3 06 41 4E 44 85 12 +F4 D2 00 F0 3A D4 0A 41 4E 44 2E 42 85 12 F4 D2 +40 F0 C8 C7 B4 D2 F8 D1 5A D4 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F 12 D4 06 52 52 43 +85 12 52 D4 00 10 6C D4 0A 52 52 43 2E 42 85 12 +52 D4 40 10 A6 D3 08 53 57 50 42 00 85 12 52 D4 +80 10 78 D4 06 52 52 41 85 12 52 D4 00 11 94 D4 +0A 52 52 41 2E 42 85 12 52 D4 40 11 86 D4 06 53 +58 54 85 12 52 D4 80 11 00 00 08 50 55 53 48 00 +85 12 52 D4 00 12 BA D4 0C 50 55 53 48 2E 42 00 +85 12 52 D4 40 12 AE D4 08 43 41 4C 4C 00 85 12 +52 D4 80 12 1A 53 0E 4A 84 12 0A CA 1E C4 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 D8 D4 +06 53 3E 3D 86 12 00 38 00 D5 04 53 3C 00 86 12 +00 34 C8 D4 06 30 3E 3D 86 12 00 30 14 D5 04 30 +3C 00 86 12 00 30 50 CF 04 55 3C 00 86 12 00 2C +28 D5 06 55 3E 3D 86 12 00 28 1E D5 06 30 3C 3E +86 12 00 24 3C D5 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D C2 D3 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D 32 D5 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F A0 D4 0A 42 45 47 49 4E 30 40 +32 C4 8A D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +46 D4 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 54 D5 B0 C8 +96 C9 A8 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 +E8 D5 6C D5 96 C9 18 D6 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D 04 D6 +06 42 57 31 85 12 16 D6 00 00 30 D6 06 42 57 32 +85 12 16 D6 00 00 3C D6 06 42 57 33 85 12 16 D6 +00 00 54 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 52 D6 +00 00 78 D6 06 46 57 32 85 12 52 D6 00 00 84 D6 +06 46 57 33 85 12 52 D6 00 00 F2 D5 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +8A CD 96 CC 96 C9 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F BE D2 0A C4 2C 00 1A CA 64 CB AC C4 +9A CD C8 C7 B4 D2 96 D2 EA D6 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 48 D6 08 52 52 43 4D 00 85 12 +D4 D6 50 00 18 D7 08 52 52 41 4D 00 85 12 D4 D6 +50 01 26 D7 08 52 4C 41 4D 00 85 12 D4 D6 50 02 +34 D7 08 52 52 55 4D 00 85 12 D4 D6 50 03 46 D5 +0A 50 55 53 48 4D 85 12 D4 D6 00 15 50 D7 08 50 +4F 50 4D 00 85 12 D4 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 D2 C6 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR4133_16MHz_4MBds.txt b/binaries/MSP_EXP430FR4133_16MHz_4MBds.txt new file mode 100644 index 0000000..6392de8 --- /dev/null +++ b/binaries/MSP_EXP430FR4133_16MHz_4MBds.txt @@ -0,0 +1,329 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A0 59 +D2 C6 7E C5 84 C5 54 C5 42 C7 6A D7 22 D0 DC CF +DC CF B8 C6 76 C7 3E C7 3C 21 E0 20 96 C9 B6 C4 +C4 C4 B2 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +42 C7 6A D7 22 D0 DC CF DC CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 04 3D 0E 93 3E 4F +99 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B6 C6 B2 49 +74 C7 B2 49 3C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 96 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 42 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 BC C8 AC C4 52 C5 84 C7 1E C4 04 1B +5B 37 6D 00 A6 C7 A6 C7 1E C4 04 1B 5B 30 6D 00 +A6 C7 2C CD B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 03 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 84 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 A6 C7 0A CA 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A6 C7 0A C4 40 FF 32 C4 +D2 C8 D6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B2 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 D3 02 02 F2 D2 05 02 B2 D0 FF FE +26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 +66 02 B2 43 62 02 F2 40 A5 00 A1 01 F2 40 10 00 +A0 01 D2 43 A1 01 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 06 00 2B 02 F2 C3 82 01 F2 D0 0A 00 82 01 +B2 40 E8 01 84 01 39 40 40 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 08 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 B8 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 16 C7 3C 40 22 C7 5D 15 +97 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 F2 D2 03 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D 18 C7 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 3E C7 30 12 +54 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 F2 C2 +03 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 DE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 76 C7 08 4E 3E 4F C7 3F 6C C7 08 45 +43 48 4F 00 B2 40 C2 48 10 C7 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 10 C7 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 B6 C7 29 4F 8F 4E +00 00 7E 49 DE 3F B8 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 6D 22 F9 98 00 00 6A 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 61 22 +9B 24 36 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 D6 C8 C8 C7 1A CA 0E CD B0 C4 44 C8 +14 C4 06 5B 54 48 45 4E 5D 00 CC C7 22 C8 E8 C7 +06 C8 14 C4 06 5B 45 4C 53 45 5D 00 CC C7 34 C8 +E8 C7 04 C8 1E C4 04 5B 49 46 5D 00 CC C7 06 C8 +B2 C4 04 C8 1E C4 05 0D 6B 6F 20 0A A6 C7 9A C4 +84 C4 B2 C4 06 C8 F4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 58 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 64 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 C8 C7 1A CA 82 CA 60 CC 96 C9 74 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 C8 C7 +1A CA 82 CA A6 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D AC C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +BE CC 0A C4 22 00 1A CA 1A C9 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 8E C7 +05 2E 22 00 0D 12 84 12 04 C9 0A C4 A6 C7 BE CC +96 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +00 C9 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +52 C9 04 23 53 00 0D 12 84 12 54 C9 8E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 82 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 9C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +7E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 48 C9 C8 C7 B6 C9 86 C9 B2 C8 C4 C9 +A0 C9 A6 C7 96 C9 30 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D D2 C9 06 55 4D 2A 2C 4F 0B 43 09 43 08 43 +1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A +F8 2B 8F 49 00 00 0E 48 30 4D 08 CA 0E 3E 4E 55 +4D 42 45 52 1A 42 BE 21 2C 4F 0B 4E 68 4C 78 80 +3A 00 03 28 78 80 07 00 21 28 78 50 0A 00 08 9A +22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 32 CB +D4 3F 34 CB 81 49 02 00 1C 4F 04 00 1E 41 04 00 +3D 40 46 CB CA 3F 48 CB 39 51 3E 61 8F 49 04 00 +8F 4E 02 00 3A 17 1C 53 1B 83 D8 23 8F 4C 00 00 +0E 4B 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 8F 43 +04 00 8F 43 02 00 1A 42 BE 21 0C 4E 0E 43 1E 15 +3D 40 C8 CB 7B 4C 68 4C 78 80 2D 00 16 24 BE 2F +2A 43 78 52 14 24 3A 52 68 53 11 24 3A 40 10 00 +58 93 0D 24 68 92 40 20 3E 90 03 00 3D 20 FC 9C +01 00 6C 4C 8F 4C 04 00 37 3C B1 43 02 00 1B 83 +FC 9C 00 00 E0 23 A2 27 CA CB 2E 24 2D 83 68 4C +78 90 5F 00 C0 27 32 B0 00 02 26 20 32 D0 00 02 +78 80 2E 00 B8 27 68 53 1F 20 09 43 8F 49 02 00 +5B 83 09 4B 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9A 08 2C 8F 49 00 00 +0E 4A 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4B 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 44 C9 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 C4 C8 C7 1A CA B0 C4 98 CD 82 CA +82 CC 0A 4E 3E 4F 3D 40 9C CC 6C 27 3D 40 76 CC +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 9E CC 3E 4F +3D 40 76 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 74 CE 2A 3C 66 CC 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D BC CC +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D BE C9 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D E4 C8 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E C4 02 0D 0A 00 A6 C7 94 C4 70 CC +C4 C8 EE C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C5 32 C4 0A C4 40 FF F6 C8 1E C4 09 46 +52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 34 CD 1E CD +0D 41 42 4F 52 54 22 00 0D 12 84 12 04 C9 0A C4 +08 C5 BE CC 96 C9 14 CA 02 27 0D 12 84 12 C8 C7 +1A CA 82 CA B0 C4 9A CD 28 C9 A6 CC 8E C8 07 5B +27 5D 0D 12 84 12 8A CD 0A C4 0A C4 BE CC BE CC +96 C9 9E CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D DC C8 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C8 C7 1A CA 82 CA B0 C4 9A CD +EE C8 AC C4 F2 CD 0A C4 0A C4 BE CC BE CC 0A C4 +BE CC BE CC 96 C9 00 00 02 3A 30 12 48 CE 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 C8 C7 1A CA 10 CE +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C5 B4 CD 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A C4 96 C9 BE CC 5A CE B6 CD 96 C9 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D 08 CD 0C 43 52 45 41 54 45 00 +B0 12 FE CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +A0 C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D F8 CD 0E 3A 4E 4F +4E 41 4D 45 30 12 48 CE 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +92 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +8A CD 14 CF 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +A2 CD 0A C4 16 CF BE CC 96 C9 A8 CE 08 43 4F 44 +45 00 B0 12 FE CD A2 82 C8 21 61 3C B0 C9 0E 48 +44 4E 43 4F 44 45 B2 40 02 D0 CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 5A CE 60 CF +3D 41 92 42 D0 21 CC 21 5D 3C 2C CF 0E 43 4F 44 +45 4E 4E 4D 30 12 36 CF B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F 3E CF +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F CA CF B2 40 DC CF D0 21 +82 4E CE 21 30 40 28 C9 85 12 C8 CF C8 CD 70 CD +5A D0 6C CF C2 CE D4 CA 7C CA 88 CD B0 CF 02 CF +DC CE 78 CE D0 CC E4 D0 FC CA 00 00 00 00 85 12 +C8 CF 5E D7 E2 D5 42 D7 0A D5 66 D5 B4 D5 90 D6 +9C D6 2C D4 50 D5 00 00 00 00 9E CF 1C D3 00 00 +B8 D6 FC CF B2 40 DC CF CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 30 D0 30 4D 42 D0 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 30 D0 +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 C6 FE FF 29 83 B9 40 +F2 C5 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +EC FF 3B 40 10 00 3A 40 3A 18 B0 12 34 D0 82 43 +4A 18 C7 3F D6 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F BE CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 C8 C7 1A CA 82 CA AC C4 02 D1 BC C8 +96 CC 04 D1 3E 4F 3D 41 B2 41 C6 21 B0 12 FE CD +BA 40 85 12 FC FF BA 40 D4 D0 FE FF 28 83 8A 48 +00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 1A CA 82 CA AC C4 6E D1 4E D1 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +D4 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 64 CB +AC C4 76 D1 6A D1 78 D1 B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 3E D1 15 20 +3E 40 2B 00 B0 12 3E D1 06 20 3E 40 2D 00 B0 12 +3E D1 92 83 C6 21 0E 12 1E 41 02 00 84 12 1A CA +64 CB AC C4 9A CD B8 D1 3E 51 3A 17 30 41 B0 12 +7E D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 1A CA +64 CB AC C4 F0 D1 E8 D1 3E 90 10 00 E6 2B 7C 2D +F2 D1 A2 41 C6 21 E1 3F 03 20 B0 12 D6 D1 43 3C +7A 90 23 00 24 20 B0 12 86 D1 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 86 D1 F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 D2 D1 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 D6 D1 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 BE D1 F2 3F 03 20 B0 12 D6 D1 F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +BE D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 +BE CC 96 C9 0A C4 2C 00 B4 D2 F8 D1 C8 C7 BE D2 +96 D2 04 D3 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 F4 D2 00 40 10 D3 0A 4D 4F 56 +2E 42 85 12 F4 D2 40 40 00 00 06 41 44 44 85 12 +F4 D2 00 50 2A D3 0A 41 44 44 2E 42 85 12 F4 D2 +40 50 36 D3 08 41 44 44 43 00 85 12 F4 D2 00 60 +44 D3 0C 41 44 44 43 2E 42 00 85 12 F4 D2 40 60 +7C CF 08 53 55 42 43 00 85 12 F4 D2 00 70 62 D3 +0C 53 55 42 43 2E 42 00 85 12 F4 D2 40 70 70 D3 +06 53 55 42 85 12 F4 D2 00 80 80 D3 0A 53 55 42 +2E 42 85 12 F4 D2 40 80 8C D3 06 43 4D 50 85 12 +F4 D2 00 90 9A D3 0A 43 4D 50 2E 42 85 12 F4 D2 +40 90 00 00 08 44 41 44 44 00 85 12 F4 D2 00 A0 +B4 D3 0C 44 41 44 44 2E 42 00 85 12 F4 D2 40 A0 +E2 D2 06 42 49 54 85 12 F4 D2 00 B0 D2 D3 0A 42 +49 54 2E 42 85 12 F4 D2 40 B0 DE D3 06 42 49 43 +85 12 F4 D2 00 C0 EC D3 0A 42 49 43 2E 42 85 12 +F4 D2 40 C0 F8 D3 06 42 49 53 85 12 F4 D2 00 D0 +06 D4 0A 42 49 53 2E 42 85 12 F4 D2 40 D0 00 00 +06 58 4F 52 85 12 F4 D2 00 E0 20 D4 0A 58 4F 52 +2E 42 85 12 F4 D2 40 E0 52 D3 06 41 4E 44 85 12 +F4 D2 00 F0 3A D4 0A 41 4E 44 2E 42 85 12 F4 D2 +40 F0 C8 C7 B4 D2 F8 D1 5A D4 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F 12 D4 06 52 52 43 +85 12 52 D4 00 10 6C D4 0A 52 52 43 2E 42 85 12 +52 D4 40 10 A6 D3 08 53 57 50 42 00 85 12 52 D4 +80 10 78 D4 06 52 52 41 85 12 52 D4 00 11 94 D4 +0A 52 52 41 2E 42 85 12 52 D4 40 11 86 D4 06 53 +58 54 85 12 52 D4 80 11 00 00 08 50 55 53 48 00 +85 12 52 D4 00 12 BA D4 0C 50 55 53 48 2E 42 00 +85 12 52 D4 40 12 AE D4 08 43 41 4C 4C 00 85 12 +52 D4 80 12 1A 53 0E 4A 84 12 0A CA 1E C4 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 D8 D4 +06 53 3E 3D 86 12 00 38 00 D5 04 53 3C 00 86 12 +00 34 C8 D4 06 30 3E 3D 86 12 00 30 14 D5 04 30 +3C 00 86 12 00 30 50 CF 04 55 3C 00 86 12 00 2C +28 D5 06 55 3E 3D 86 12 00 28 1E D5 06 30 3C 3E +86 12 00 24 3C D5 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D C2 D3 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D 32 D5 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F A0 D4 0A 42 45 47 49 4E 30 40 +32 C4 8A D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +46 D4 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 54 D5 B0 C8 +96 C9 A8 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 +E8 D5 6C D5 96 C9 18 D6 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D 04 D6 +06 42 57 31 85 12 16 D6 00 00 30 D6 06 42 57 32 +85 12 16 D6 00 00 3C D6 06 42 57 33 85 12 16 D6 +00 00 54 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 52 D6 +00 00 78 D6 06 46 57 32 85 12 52 D6 00 00 84 D6 +06 46 57 33 85 12 52 D6 00 00 F2 D5 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +8A CD 96 CC 96 C9 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F BE D2 0A C4 2C 00 1A CA 64 CB AC C4 +9A CD C8 C7 B4 D2 96 D2 EA D6 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 48 D6 08 52 52 43 4D 00 85 12 +D4 D6 50 00 18 D7 08 52 52 41 4D 00 85 12 D4 D6 +50 01 26 D7 08 52 4C 41 4D 00 85 12 D4 D6 50 02 +34 D7 08 52 52 55 4D 00 85 12 D4 D6 50 03 46 D5 +0A 50 55 53 48 4D 85 12 D4 D6 00 15 50 D7 08 50 +4F 50 4D 00 85 12 D4 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 D2 C6 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR4133_16MHz_I2C.txt b/binaries/MSP_EXP430FR4133_16MHz_I2C.txt index 1b36a1a..af84ef9 100644 --- a/binaries/MSP_EXP430FR4133_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR4133_16MHz_I2C.txt @@ -1,339 +1,327 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF 2E D8 2A D0 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 2E D8 -2A D0 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +CC C6 56 C5 56 C5 58 C5 44 C5 46 D7 FE CF B8 CF +B8 CF BA C6 3E C7 16 C7 3C 21 E0 20 72 C9 B6 C4 +C4 C4 8E C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 46 D7 FE CF B8 CF B8 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 F6 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 50 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 4A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 3C CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 82 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 82 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -8A C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 -0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B -8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 4D 42 -45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 30 00 -78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 1F 28 -08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 -44 CA D2 3F 46 CA 81 49 02 00 1C 4F 04 00 1E 41 -04 00 3D 40 58 CA C8 3F 5A CA 39 51 3E 61 8F 49 -04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 8F 4C -00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 0C 43 -2D 15 3D 40 D8 CA 0A 4B 3F 82 8F 4E 06 00 8F 43 -04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 00 00 -06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C 68 4C -78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C 2A 43 -78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 78 53 -35 20 1C 53 1B 83 EB 3F DA CA 30 24 2D 83 78 90 -28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 78 90 -F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 02 00 -5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 0A 00 -05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A 08 2C -8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 E6 3F -9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 0E 4C -82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 0E F3 -30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 -09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 -8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 00 00 -01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 3E 4F -30 4D 80 CB 87 4C 49 54 45 52 41 4C 82 93 BE 21 -0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 0A C4 -00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 -03 24 8A 4E 02 00 EE 3F 30 4D 54 C8 05 43 4F 55 -4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF 30 4D -68 C8 09 49 4E 54 45 52 50 52 45 54 0D 12 84 12 -AC C4 3C CC 1A C9 F8 CB 7F 26 3D 40 00 CC C1 3E -02 CC 0A 4E 3E 4F 3D 40 1C CC 35 27 3D 40 F2 CB -1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 1E CC 3E 4F -3D 40 F2 CB BB 23 DE 53 00 00 68 4E 08 5E F8 40 -3F 00 00 00 3D 40 BE CD CC 3F 26 CC 86 12 20 00 -D4 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F 30 4D -3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 00 20 -82 43 BE 21 84 12 7C C7 BC C4 EC CB B2 C7 E4 C7 -14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 21 00 -2A C5 0A C4 40 FF 28 C4 EC C7 14 C4 0A 46 52 41 -4D 20 66 75 6C 6C 21 00 2A C5 3A C4 66 CC 42 CC -86 41 42 4F 52 54 22 00 0D 12 84 12 D2 C8 0A C4 -2A C5 82 CB 4E C8 7C C9 01 27 0D 12 84 12 3C CC -1A C9 82 C9 34 C4 3A CC 4E C8 00 00 83 5B 27 5D -0D 12 84 12 BA CC 0A C4 0A C4 82 CB 82 CB 4E C8 -CC CC 81 5B 82 43 BE 21 30 4D FA C7 01 5D B2 43 -BE 21 30 4D EC CC 81 5C 92 42 C0 21 C4 21 30 4D -00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 -3C CC 1A C9 82 C9 96 C7 34 C4 3A CC E4 C7 34 C4 -2E CD 0A C4 0A C4 82 CB 82 CB 0A C4 82 CB 82 CB -4E C8 E2 CC 01 3A 30 12 7E CD 92 B3 C6 21 A2 63 -C6 21 0D 12 84 12 3C CC 1A C9 4C CD 3D 41 08 4E -7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E 3E F0 -1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 82 4A -BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 BA 40 -0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 30 4D -82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 A8 49 -FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 0F 73 -74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 36 C5 -34 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 0A C4 -4E C8 82 CB 90 CD E4 CC 4E C8 E2 CB 09 49 4D 4D -45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 00 00 -30 4D CC CB 06 43 52 45 41 54 45 00 B0 12 3A CD -BA 40 86 12 FC FF 8A 4A FE FF C9 3F F4 CD 04 43 -4F 44 45 00 B0 12 3A CD A2 82 C6 21 0D 12 84 12 -2C D0 06 D0 4E C8 DC CD 07 48 44 4E 43 4F 44 45 -B2 40 0A D0 DA 21 EE 3F 00 00 07 45 4E 44 43 4F -44 45 0D 12 84 12 90 CD 46 D0 64 D0 4E C8 00 00 -05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 00 00 -BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 0D 12 -84 12 46 D0 64 D0 4E C8 00 00 05 4C 4F 32 48 49 -A2 83 C6 21 1A 42 C6 21 EB 3F 28 CE 85 48 49 32 -4C 4F 0D 12 84 12 28 C4 D4 CF 82 CB E4 CC 1C CE -4E C8 C2 CD 86 5B 54 48 45 4E 5D 00 30 4D 0C 4E -38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 06 30 -1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D 3E 4F -30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 F7 3F -A4 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 -00 00 C6 C7 3C CC 1A C9 D2 CB 8E C7 34 C4 3C CF -9C C7 14 C4 06 5B 54 48 45 4E 5D 00 AE CE 16 CF -D2 CE F4 CE 4E C8 9C C7 14 C4 06 5B 45 4C 53 45 -5D 00 AE CE 2C CF D2 CE F2 CE 4E C8 14 C4 04 5B -49 46 5D 00 AE CE F4 CE 3A C4 F2 CE 70 C7 14 C4 -05 0D 0A 6B 6F 20 4A C7 BC C4 AC C4 3A C4 F4 CE -E2 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D -2F 53 30 4D 52 CF 89 5B 44 45 46 49 4E 45 44 5D -0D 12 84 12 3C CC 1A C9 82 C9 60 CF 4E C8 66 CF -8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 -70 CF DE C7 4E C8 98 CF B2 4E 0A 18 2E 53 BE 12 -3E 4F 3D 41 90 3C 94 CB 06 4D 41 52 4B 45 52 00 -B0 12 3A CD BA 40 85 12 FC FF BA 40 96 CF FE FF -28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 06 00 -C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 D6 C7 4E C8 -85 12 D8 CF A0 CC 0E CE 10 C7 B8 CC 8C CE D2 C6 -A8 CF 00 C9 D0 D0 E4 D0 E2 C9 14 C9 00 00 80 CF -F6 CC 0A CA 00 00 85 12 D8 CF A4 D6 0A D7 4C D6 -5A D7 12 D6 00 00 DE D3 00 00 22 D8 06 D8 76 D6 -B4 D6 EE D4 00 00 00 00 76 D7 04 D0 3A 40 0C 00 -39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 00 00 -1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 09 48 -29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D 82 43 -CC 21 30 4D 92 42 CA 21 DA 21 30 4D E0 CF 5E D0 -64 D0 74 D0 1A 42 20 18 82 4A C8 21 2E 4E 82 4E -C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF -0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 -F0 23 3E 4F 3D 41 30 4D 02 CD 09 50 57 52 5F 53 -54 41 54 45 85 12 6C D0 2E D8 CE C8 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 B8 D0 F3 3F AA D0 -08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 B8 D0 -30 4D BC D0 08 52 53 54 5F 48 45 52 45 00 92 42 -C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 E3 37 -0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 42 D1 FE FF 29 83 B9 40 E2 C5 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 C5 B2 49 FA C4 -B2 49 02 C4 B2 49 00 C6 B2 49 EA FF B2 49 0A 18 -C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 -80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 00 08 -29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 02 02 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 05 3D 0E 93 3E 4F +87 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B8 C6 B2 49 +3C C7 B2 49 14 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 72 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 98 C8 AC C4 +42 C5 56 C7 1E C4 05 1B 5B 37 6D 40 82 C7 0A C4 +02 18 BA C8 E6 C9 82 C7 1E C4 04 1B 5B 30 6D 00 +82 C7 08 CD 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +4A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 56 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 82 C7 0A C4 02 18 BA C8 E6 C9 0A C4 23 00 +3A C7 E6 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +82 C7 0A C4 40 FF 32 C4 AE C8 B2 C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B2 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 D3 02 02 B2 D0 FF FE 26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 BA 00 82 01 B2 40 E8 01 -84 01 82 43 88 01 F2 D0 06 00 2B 02 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 C4 FE C5 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A C9 82 C9 -DE C7 34 C4 1E D2 76 CA 34 C4 38 D2 32 D2 20 D2 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 3A D2 B2 41 C4 21 3E 41 -84 12 0A C4 2B 00 1A C9 82 C9 DE C7 34 C4 56 D2 -76 CA 34 C4 3A CC A8 C7 1A C9 76 CA 34 C4 3A CC -62 D2 3E 5F E7 3F 3E 40 28 00 B0 12 02 D2 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 A8 CD 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A C9 76 CA 34 C4 AA D2 A0 D2 -21 53 3E 90 10 00 C6 2B 7F 2D AC D2 B2 41 C4 21 -C1 3F 0D 12 84 12 3C CC DE D1 BC D2 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 02 D2 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 02 D2 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 8A D2 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -8A D2 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 8A D2 FA 23 3C 50 10 00 B0 12 -66 D2 EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 3C CC DE D1 88 D3 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 8A D2 E0 23 -3C 50 80 00 B0 12 66 D2 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A C4 00 13 82 CB 4E C8 0A C4 -2C 00 B2 D2 7E D3 C8 D3 09 4B 2E 4E 0E DC A2 3F -7A CE 03 4D 4F 56 85 12 BE D3 00 40 D2 D3 05 4D -4F 56 2E 42 85 12 BE D3 40 40 00 00 03 41 44 44 -85 12 BE D3 00 50 EC D3 05 41 44 44 2E 42 85 12 -BE D3 40 50 F8 D3 04 41 44 44 43 00 85 12 BE D3 -00 60 06 D4 06 41 44 44 43 2E 42 00 85 12 BE D3 -40 60 AC D3 04 53 55 42 43 00 85 12 BE D3 00 70 -24 D4 06 53 55 42 43 2E 42 00 85 12 BE D3 40 70 -32 D4 03 53 55 42 85 12 BE D3 00 80 42 D4 05 53 -55 42 2E 42 85 12 BE D3 40 80 50 CE 03 43 4D 50 -85 12 BE D3 00 90 5C D4 05 43 4D 50 2E 42 85 12 -BE D3 40 90 3A CE 04 44 41 44 44 00 85 12 BE D3 -00 A0 76 D4 06 44 41 44 44 2E 42 00 85 12 BE D3 -40 A0 68 D4 03 42 49 54 85 12 BE D3 00 B0 94 D4 -05 42 49 54 2E 42 85 12 BE D3 40 B0 A0 D4 03 42 -49 43 85 12 BE D3 00 C0 AE D4 05 42 49 43 2E 42 -85 12 BE D3 40 C0 BA D4 03 42 49 53 85 12 BE D3 -00 D0 C8 D4 05 42 49 53 2E 42 85 12 BE D3 40 D0 -00 00 03 58 4F 52 85 12 BE D3 00 E0 E2 D4 05 58 -4F 52 2E 42 85 12 BE D3 40 E0 14 D4 03 41 4E 44 -85 12 BE D3 00 F0 FC D4 05 41 4E 44 2E 42 85 12 -BE D3 40 F0 3C CC B2 D2 1A D5 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 4E D4 03 52 52 43 -85 12 14 D5 00 10 2C D5 05 52 52 43 2E 42 85 12 -14 D5 40 10 38 D5 04 53 57 50 42 00 85 12 14 D5 -80 10 46 D5 03 52 52 41 85 12 14 D5 00 11 54 D5 -05 52 52 41 2E 42 85 12 14 D5 40 11 60 D5 03 53 -58 54 85 12 14 D5 80 11 00 00 04 50 55 53 48 00 -85 12 14 D5 00 12 7A D5 06 50 55 53 48 2E 42 00 -85 12 14 D5 40 12 D4 D4 04 43 41 4C 4C 00 85 12 -14 D5 80 12 1A 53 0E 4A 0D 12 84 12 C4 C8 14 C4 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C5 -6E D5 03 53 3E 3D 86 12 00 38 C2 D5 02 53 3C 00 -86 12 00 34 88 D5 03 30 3E 3D 86 12 00 30 D6 D5 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C EA D5 03 55 3E 3D 86 12 00 28 E0 D5 03 30 -3C 3E 86 12 00 24 FE D5 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D F4 D5 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 84 D4 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 98 D5 05 42 45 47 49 4E -30 40 28 C4 28 D6 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D 08 D5 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 16 D6 -A8 C7 4E C8 CC D5 06 52 45 50 45 41 54 00 0D 12 -84 12 AA D6 2E D6 4E C8 DA D6 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -6A D6 03 42 57 31 85 12 D8 D6 00 00 F2 D6 03 42 -57 32 85 12 D8 D6 00 00 FE D6 03 42 57 33 85 12 -D8 D6 00 00 16 D7 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 14 D7 00 00 -36 D7 03 46 57 32 85 12 14 D7 00 00 42 D7 03 46 -57 33 85 12 14 D7 00 00 4E D7 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 BA CC -16 CC 4E C8 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 3C CC DE D1 98 D7 92 53 C4 21 3E 40 2C 00 -84 12 1A C9 76 CA 34 C4 3A CC 74 D3 AE D7 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E C6 D6 04 52 52 43 -4D 00 85 12 92 D7 50 00 DC D7 04 52 52 41 4D 00 -85 12 92 D7 50 01 EA D7 04 52 4C 41 4D 00 85 12 -92 D7 50 02 F8 D7 04 52 52 55 4D 00 85 12 92 D7 -50 03 08 D6 05 50 55 53 48 4D 85 12 92 D7 00 15 -14 D8 04 50 4F 50 4D 00 85 12 92 D7 00 17 +82 43 88 01 F2 D0 06 00 2B 02 F2 C3 82 01 F2 D0 +0A 00 82 01 B2 40 E8 01 84 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 39 40 00 08 29 83 +89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 3E F3 +02 20 1E 42 5E 01 B0 12 D0 C4 80 C5 00 00 0C 41 +43 43 45 50 54 00 30 40 BA C6 0A 4E 2E 4F 0A 5E +3B 40 0A 00 3C 40 20 00 3D 15 9A 3E 21 52 A2 C2 +6C 05 B2 B0 10 00 40 05 93 22 3A 17 92 B3 6C 05 +FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 +F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B +45 59 30 40 16 C7 58 43 B0 12 46 C5 2F 83 8F 4E +00 00 92 B3 6C 05 FD 27 1E 42 4C 05 B0 12 44 C5 +30 4D 00 00 08 45 4D 49 54 00 30 40 3E C7 08 4E +3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D 34 C7 +08 45 43 48 4F 00 B2 40 C2 48 48 C7 38 40 05 00 +B0 12 46 C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 48 C7 28 42 F3 3F 00 00 08 54 59 50 +45 00 0D 12 3D 40 92 C7 29 4F 8F 4E 00 00 7E 49 +D4 3F 94 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 7F 22 F9 98 00 00 7C 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 73 22 9B 24 0E C7 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 +B2 C8 A4 C7 F6 C9 EA CC B0 C4 20 C8 14 C4 06 5B +54 48 45 4E 5D 00 A8 C7 FE C7 C4 C7 E2 C7 14 C4 +06 5B 45 4C 53 45 5D 00 A8 C7 10 C8 C4 C7 E0 C7 +1E C4 04 5B 49 46 5D 00 A8 C7 E2 C7 B2 C4 E0 C7 +1E C4 05 0D 6B 6F 20 0A 82 C7 9A C4 84 C4 B2 C4 +E2 C7 D0 C7 0D 5B 54 48 45 4E 5D 00 30 4D 34 C8 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 40 C8 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 A4 C7 +F6 C9 5E CA 3C CC 72 C9 50 C8 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 A4 C7 F6 C9 5E CA +82 C8 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D AE C6 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D E0 C5 05 53 22 00 +82 43 C0 21 0D 12 84 12 0A C4 1E C4 9A CC 0A C4 +22 00 F6 C9 F6 C8 B2 40 20 00 C0 21 1A 53 1A B3 +82 6A C8 21 3E 4F 3D 41 30 4D 68 C7 05 2E 22 00 +0D 12 84 12 E0 C8 0A C4 82 C7 9A CC 72 C9 00 00 +04 3C 23 00 B2 40 B2 21 B2 21 30 4D DC C8 02 23 +1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 21 18 42 B2 21 C8 4A 00 00 30 4D 2E C9 04 23 +53 00 0D 12 84 12 30 C9 6A C9 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 5E C9 04 23 3E 00 9F 42 B2 21 +00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F 78 C9 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 50 C7 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +24 C9 A4 C7 92 C9 62 C9 8E C8 A0 C9 7C C9 82 C7 +72 C9 0C C9 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D AE C9 +06 55 4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 0E BA +02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B 8F 49 +00 00 0E 48 30 4D E4 C9 0E 3E 4E 55 4D 42 45 52 +1A 42 BE 21 2C 4F 0B 4E 68 4C 78 80 3A 00 03 28 +78 80 07 00 21 28 78 50 0A 00 08 9A 22 C3 1C 2C +5D 15 1C 4F 02 00 0E 4A 3D 40 0E CB D4 3F 10 CB +81 49 02 00 1C 4F 04 00 1E 41 04 00 3D 40 22 CB +CA 3F 24 CB 39 51 3E 61 8F 49 04 00 8F 4E 02 00 +3A 17 1C 53 1B 83 D8 23 8F 4C 00 00 0E 4B 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 8F 43 04 00 8F 43 +02 00 1A 42 BE 21 0C 4E 0E 43 1E 15 3D 40 A4 CB +7B 4C 68 4C 78 80 2D 00 16 24 BE 2F 2A 43 78 52 +14 24 3A 52 68 53 11 24 3A 40 10 00 58 93 0D 24 +68 92 40 20 3E 90 03 00 3D 20 FC 9C 01 00 6C 4C +8F 4C 04 00 37 3C B1 43 02 00 1B 83 FC 9C 00 00 +E0 23 A2 27 A6 CB 2E 24 2D 83 68 4C 78 90 5F 00 +C0 27 32 B0 00 02 26 20 32 D0 00 02 78 80 2E 00 +B8 27 68 53 1F 20 09 43 8F 49 02 00 5B 83 09 4B +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9A 08 2C 8F 49 00 00 0E 4A 2C 15 +B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4B 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +20 C9 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 C4 A4 C7 F6 C9 B0 C4 74 CD 5E CA 5E CC 0A 4E +3E 4F 3D 40 78 CC 6C 27 3D 40 52 CC 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 7A CC 3E 4F 3D 40 52 CC +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 50 CE 2A 3C 42 CC 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 98 CC 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 9A C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D C0 C8 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E C4 02 0D 0A 00 82 C7 94 C4 4C CC A0 C8 CA C8 +1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 +32 C4 0A C4 40 FF D2 C8 1E C4 09 46 52 41 4D 20 +66 75 6C 6C 08 C5 B2 C4 10 CD FA CC 0D 41 42 4F +52 54 22 00 0D 12 84 12 E0 C8 0A C4 08 C5 9A CC +72 C9 F0 C9 02 27 0D 12 84 12 A4 C7 F6 C9 5E CA +B0 C4 76 CD 04 C9 82 CC 6A C8 07 5B 27 5D 0D 12 +84 12 66 CD 0A C4 0A C4 9A CC 9A CC 72 C9 7A CD +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D B8 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 A4 C7 F6 C9 5E CA B0 C4 76 CD CA C8 AC C4 +CE CD 0A C4 0A C4 9A CC 9A CC 0A C4 9A CC 9A CC +72 C9 00 00 02 3A 30 12 24 CE 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 A4 C7 F6 C9 EC CD 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 C5 90 CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A C4 72 C9 9A CC 36 CE 92 CD 72 C9 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D E4 CC 0C 43 52 45 41 54 45 00 B0 12 DA CD +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 7C C7 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D D4 CD 0E 3A 4E 4F 4E 41 4D 45 +30 12 24 CE 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 6E CE 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 66 CD F0 CE +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 7E CD 0A C4 +F2 CE 9A CC 72 C9 84 CE 08 43 4F 44 45 00 B0 12 +DA CD A2 82 C8 21 61 3C 8C C9 0E 48 44 4E 43 4F +44 45 B2 40 DE CF CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 36 CE 3C CF 3D 41 92 42 +D0 21 CC 21 5D 3C 08 CF 0E 43 4F 44 45 4E 4E 4D +30 12 12 CF B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F 1A CF 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F A6 CF B2 40 B8 CF D0 21 82 4E CE 21 +30 40 04 C9 85 12 A4 CF A4 CD 4C CD 36 D0 48 CF +9E CE B0 CA 58 CA 64 CD 8C CF DE CE B8 CE 54 CE +AC CC C0 D0 D8 CA 00 00 00 00 85 12 A4 CF 3A D7 +BE D5 1E D7 E6 D4 42 D5 90 D5 6C D6 78 D6 08 D4 +2C D5 00 00 00 00 7A CF F8 D2 00 00 94 D6 D8 CF +B2 40 B8 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +0C D0 30 4D 1E D0 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 0C D0 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E C6 FE FF 29 83 B9 40 FA C5 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 EA FF 3B 40 +10 00 3A 40 3A 18 B0 12 10 D0 82 43 4A 18 C7 3F +B2 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 9A CD +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +A4 C7 F6 C9 5E CA AC C4 DE D0 98 C8 72 CC E0 D0 +3E 4F 3D 41 B2 41 C6 21 B0 12 DA CD BA 40 85 12 +FC FF BA 40 B0 D0 FE FF 28 83 8A 48 00 00 BA 40 +82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +F6 C9 5E CA AC C4 4A D1 2A D1 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 B0 D0 00 00 +01 20 3E 52 2E 83 21 53 30 41 40 CB AC C4 52 D1 +46 D1 54 D1 B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 1A D1 15 20 3E 40 2B 00 +B0 12 1A D1 06 20 3E 40 2D 00 B0 12 1A D1 92 83 +C6 21 0E 12 1E 41 02 00 84 12 F6 C9 40 CB AC C4 +76 CD 94 D1 3E 51 3A 17 30 41 B0 12 5A D1 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 F6 C9 40 CB AC C4 +CC D1 C4 D1 3E 90 10 00 E6 2B 7C 2D CE D1 A2 41 +C6 21 E1 3F 03 20 B0 12 B2 D1 43 3C 7A 90 23 00 +24 20 B0 12 62 D1 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 62 D1 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 AE D1 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 B2 D1 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 9A D1 +F2 3F 03 20 B0 12 B2 D1 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 9A D1 EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A C4 00 13 9A CC 72 C9 +0A C4 2C 00 90 D2 D4 D1 A4 C7 9A D2 72 D2 E0 D2 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 D0 D2 00 40 EC D2 0A 4D 4F 56 2E 42 85 12 +D0 D2 40 40 00 00 06 41 44 44 85 12 D0 D2 00 50 +06 D3 0A 41 44 44 2E 42 85 12 D0 D2 40 50 12 D3 +08 41 44 44 43 00 85 12 D0 D2 00 60 20 D3 0C 41 +44 44 43 2E 42 00 85 12 D0 D2 40 60 58 CF 08 53 +55 42 43 00 85 12 D0 D2 00 70 3E D3 0C 53 55 42 +43 2E 42 00 85 12 D0 D2 40 70 4C D3 06 53 55 42 +85 12 D0 D2 00 80 5C D3 0A 53 55 42 2E 42 85 12 +D0 D2 40 80 68 D3 06 43 4D 50 85 12 D0 D2 00 90 +76 D3 0A 43 4D 50 2E 42 85 12 D0 D2 40 90 00 00 +08 44 41 44 44 00 85 12 D0 D2 00 A0 90 D3 0C 44 +41 44 44 2E 42 00 85 12 D0 D2 40 A0 BE D2 06 42 +49 54 85 12 D0 D2 00 B0 AE D3 0A 42 49 54 2E 42 +85 12 D0 D2 40 B0 BA D3 06 42 49 43 85 12 D0 D2 +00 C0 C8 D3 0A 42 49 43 2E 42 85 12 D0 D2 40 C0 +D4 D3 06 42 49 53 85 12 D0 D2 00 D0 E2 D3 0A 42 +49 53 2E 42 85 12 D0 D2 40 D0 00 00 06 58 4F 52 +85 12 D0 D2 00 E0 FC D3 0A 58 4F 52 2E 42 85 12 +D0 D2 40 E0 2E D3 06 41 4E 44 85 12 D0 D2 00 F0 +16 D4 0A 41 4E 44 2E 42 85 12 D0 D2 40 F0 A4 C7 +90 D2 D4 D1 36 D4 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F EE D3 06 52 52 43 85 12 2E D4 +00 10 48 D4 0A 52 52 43 2E 42 85 12 2E D4 40 10 +82 D3 08 53 57 50 42 00 85 12 2E D4 80 10 54 D4 +06 52 52 41 85 12 2E D4 00 11 70 D4 0A 52 52 41 +2E 42 85 12 2E D4 40 11 62 D4 06 53 58 54 85 12 +2E D4 80 11 00 00 08 50 55 53 48 00 85 12 2E D4 +00 12 96 D4 0C 50 55 53 48 2E 42 00 85 12 2E D4 +40 12 8A D4 08 43 41 4C 4C 00 85 12 2E D4 80 12 +1A 53 0E 4A 84 12 E6 C9 1E C4 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 C5 B4 D4 06 53 3E 3D +86 12 00 38 DC D4 04 53 3C 00 86 12 00 34 A4 D4 +06 30 3E 3D 86 12 00 30 F0 D4 04 30 3C 00 86 12 +00 30 2C CF 04 55 3C 00 86 12 00 2C 04 D5 06 55 +3E 3D 86 12 00 28 FA D4 06 30 3C 3E 86 12 00 24 +18 D5 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +9E D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D 0E D5 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 7C D4 0A 42 45 47 49 4E 30 40 32 C4 66 D5 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D 22 D4 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 30 D5 8C C8 72 C9 84 D5 +0C 52 45 50 45 41 54 00 0D 12 84 12 C4 D5 48 D5 +72 C9 F4 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D E0 D5 06 42 57 31 +85 12 F2 D5 00 00 0C D6 06 42 57 32 85 12 F2 D5 +00 00 18 D6 06 42 57 33 85 12 F2 D5 00 00 30 D6 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 2E D6 00 00 54 D6 +06 46 57 32 85 12 2E D6 00 00 60 D6 06 46 57 33 +85 12 2E D6 00 00 CE D5 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 66 CD 72 CC +72 C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +9A D2 0A C4 2C 00 F6 C9 40 CB AC C4 76 CD A4 C7 +90 D2 72 D2 C6 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 24 D6 08 52 52 43 4D 00 85 12 B0 D6 50 00 +F4 D6 08 52 52 41 4D 00 85 12 B0 D6 50 01 02 D7 +08 52 4C 41 4D 00 85 12 B0 D6 50 02 10 D7 08 52 +52 55 4D 00 85 12 B0 D6 50 03 22 D5 0A 50 55 53 +48 4D 85 12 B0 D6 00 15 2C D7 08 50 4F 50 4D 00 +85 12 B0 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 82 C6 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 42 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 CC C6 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR4133_16MHz_UART.txt b/binaries/MSP_EXP430FR4133_16MHz_UART.txt deleted file mode 100644 index 0366e88..0000000 --- a/binaries/MSP_EXP430FR4133_16MHz_UART.txt +++ /dev/null @@ -1,341 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 44 D8 3C D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 44 D8 -3C D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 08 D1 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 62 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 03 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 F2 D2 03 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 F2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 4E CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -94 CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -94 CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 9C C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 -1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A -F8 2B 8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 -4D 42 45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 -30 00 78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 -1F 28 08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A -3D 40 56 CA D2 3F 58 CA 81 49 02 00 1C 4F 04 00 -1E 41 04 00 3D 40 6A CA C8 3F 6C CA 39 51 3E 61 -8F 49 04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 -8F 4C 00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 -0C 43 2D 15 3D 40 EA CA 0A 4B 3F 82 8F 4E 06 00 -8F 43 04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 -00 00 06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C -68 4C 78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C -2A 43 78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 -78 53 35 20 1C 53 1B 83 EB 3F EC CA 30 24 2D 83 -78 90 28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 -78 90 F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 -02 00 5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 -0A 00 05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A -08 2C 8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 -E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 -0E 4C 82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 -0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 -3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 -02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D -00 00 01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 -3E 4F 30 4D 92 CB 87 4C 49 54 45 52 41 4C 82 93 -BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 -0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 -00 02 03 24 8A 4E 02 00 EE 3F 30 4D 66 C8 05 43 -4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF -30 4D 7A C8 09 49 4E 54 45 52 50 52 45 54 0D 12 -84 12 AC C4 4E CC 2C C9 0A CC 7F 26 3D 40 12 CC -C1 3E 14 CC 0A 4E 3E 4F 3D 40 2E CC 35 27 3D 40 -04 CC 1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 30 CC -3E 4F 3D 40 04 CC BB 23 DE 53 00 00 68 4E 08 5E -F8 40 3F 00 00 00 3D 40 D0 CD CC 3F 38 CC 86 12 -20 00 E6 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F -30 4D 3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 -00 20 82 43 BE 21 84 12 8E C7 BC C4 FE CB C4 C7 -F6 C7 14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 -21 00 2A C5 0A C4 40 FF 28 C4 FE C7 14 C4 0A 46 -52 41 4D 20 66 75 6C 6C 21 00 2A C5 3A C4 78 CC -54 CC 86 41 42 4F 52 54 22 00 0D 12 84 12 E4 C8 -0A C4 2A C5 94 CB 60 C8 8E C9 01 27 0D 12 84 12 -4E CC 2C C9 94 C9 34 C4 4C CC 60 C8 00 00 83 5B -27 5D 0D 12 84 12 CC CC 0A C4 0A C4 94 CB 94 CB -60 C8 DE CC 81 5B 82 43 BE 21 30 4D 0C C8 01 5D -B2 43 BE 21 30 4D FE CC 81 5C 92 42 C0 21 C4 21 -30 4D 00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 -84 12 4E CC 2C C9 94 C9 A8 C7 34 C4 4C CC F6 C7 -34 C4 40 CD 0A C4 0A C4 94 CB 94 CB 0A C4 94 CB -94 CB 60 C8 F4 CC 01 3A 30 12 90 CD 92 B3 C6 21 -A2 63 C6 21 0D 12 84 12 4E CC 2C C9 5E CD 3D 41 -08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E -3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 -82 4A BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 -BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 -30 4D 82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 -A8 49 FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 -0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 -36 C5 46 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 -0A C4 60 C8 94 CB A2 CD F6 CC 60 C8 F4 CB 09 49 -4D 4D 45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 -00 00 30 4D DE CB 06 43 52 45 41 54 45 00 B0 12 -4C CD BA 40 86 12 FC FF 8A 4A FE FF C9 3F 06 CE -04 43 4F 44 45 00 B0 12 4C CD A2 82 C6 21 0D 12 -84 12 3E D0 18 D0 60 C8 EE CD 07 48 44 4E 43 4F -44 45 B2 40 1C D0 DA 21 EE 3F 00 00 07 45 4E 44 -43 4F 44 45 0D 12 84 12 A2 CD 58 D0 76 D0 60 C8 -00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 -00 00 BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 -0D 12 84 12 58 D0 76 D0 60 C8 00 00 05 4C 4F 32 -48 49 A2 83 C6 21 1A 42 C6 21 EB 3F 3A CE 85 48 -49 32 4C 4F 0D 12 84 12 28 C4 E6 CF 94 CB F6 CC -2E CE 60 C8 D4 CD 86 5B 54 48 45 4E 5D 00 30 4D -0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 -06 30 1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D -3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 -F7 3F B6 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 -0A C4 00 00 D8 C7 4E CC 2C C9 E4 CB A0 C7 34 C4 -4E CF AE C7 14 C4 06 5B 54 48 45 4E 5D 00 C0 CE -28 CF E4 CE 06 CF 60 C8 AE C7 14 C4 06 5B 45 4C -53 45 5D 00 C0 CE 3E CF E4 CE 04 CF 60 C8 14 C4 -04 5B 49 46 5D 00 C0 CE 06 CF 3A C4 04 CF 82 C7 -14 C4 05 0D 0A 6B 6F 20 5C C7 BC C4 AC C4 3A C4 -06 CF F4 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 -30 4D 2F 53 30 4D 64 CF 89 5B 44 45 46 49 4E 45 -44 5D 0D 12 84 12 4E CC 2C C9 94 C9 72 CF 60 C8 -78 CF 8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 -84 12 82 CF F0 C7 60 C8 AA CF B2 4E 0A 18 2E 53 -BE 12 3E 4F 3D 41 90 3C A6 CB 06 4D 41 52 4B 45 -52 00 B0 12 4C CD BA 40 85 12 FC FF BA 40 A8 CF -FE FF 28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 -06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 E8 C7 -60 C8 85 12 EA CF B2 CC 20 CE 2C C7 CA CC 9E CE -F6 C6 BA CF 12 C9 E2 D0 F6 D0 F4 C9 26 C9 00 00 -92 CF 08 CD 1C CA 00 00 85 12 EA CF BA D6 20 D7 -62 D6 70 D7 28 D6 00 00 F4 D3 00 00 38 D8 1C D8 -8C D6 CA D6 04 D5 00 00 00 00 8C D7 16 D0 3A 40 -0C 00 39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 -00 00 1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 -09 48 29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D -82 43 CC 21 30 4D 92 42 CA 21 DA 21 30 4D F2 CF -70 D0 76 D0 86 D0 1A 42 20 18 82 4A C8 21 2E 4E -82 4E C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 -FE FF 0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A -0A 93 F0 23 3E 4F 3D 41 30 4D 14 CD 09 50 57 52 -5F 53 54 41 54 45 85 12 7E D0 44 D8 E0 C8 09 52 -53 54 5F 53 54 41 54 45 92 42 0A 18 CA D0 F3 3F -BC D0 08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 -CA D0 30 4D CE D0 08 52 53 54 5F 48 45 52 45 00 -92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 -E3 37 0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 54 D1 FE FF 29 83 B9 40 02 C6 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 C6 B2 49 -FA C4 B2 49 02 C4 B2 49 20 C6 B2 49 EC FF B2 49 -0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 -B2 40 80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 -00 08 29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 -02 02 F2 D2 05 02 B2 D0 FF FE 26 02 B2 43 22 02 -B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 -F2 40 A5 00 A1 01 F2 40 10 00 A0 01 D2 43 A1 01 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 BA 00 -82 01 B2 40 E8 01 84 01 82 43 88 01 F2 D0 06 00 -2B 02 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 1E C6 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C C9 94 C9 F0 C7 34 C4 34 D2 88 CA 34 C4 -4E D2 48 D2 36 D2 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 50 D2 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 2C C9 94 C9 -F0 C7 34 C4 6C D2 88 CA 34 C4 4C CC BA C7 2C C9 -88 CA 34 C4 4C CC 78 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 18 D2 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 BA CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C C9 88 CA -34 C4 C0 D2 B6 D2 21 53 3E 90 10 00 C6 2B 7F 2D -C2 D2 B2 41 C4 21 C1 3F 0D 12 84 12 4E CC F4 D1 -D2 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 18 D2 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 18 D2 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 A0 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 A0 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 A0 D2 FA 23 -3C 50 10 00 B0 12 7C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 4E CC F4 D1 9E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 A0 D2 E0 23 3C 50 80 00 B0 12 7C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -94 CB 60 C8 0A C4 2C 00 C8 D2 94 D3 DE D3 09 4B -2E 4E 0E DC A2 3F 8C CE 03 4D 4F 56 85 12 D4 D3 -00 40 E8 D3 05 4D 4F 56 2E 42 85 12 D4 D3 40 40 -00 00 03 41 44 44 85 12 D4 D3 00 50 02 D4 05 41 -44 44 2E 42 85 12 D4 D3 40 50 0E D4 04 41 44 44 -43 00 85 12 D4 D3 00 60 1C D4 06 41 44 44 43 2E -42 00 85 12 D4 D3 40 60 C2 D3 04 53 55 42 43 00 -85 12 D4 D3 00 70 3A D4 06 53 55 42 43 2E 42 00 -85 12 D4 D3 40 70 48 D4 03 53 55 42 85 12 D4 D3 -00 80 58 D4 05 53 55 42 2E 42 85 12 D4 D3 40 80 -62 CE 03 43 4D 50 85 12 D4 D3 00 90 72 D4 05 43 -4D 50 2E 42 85 12 D4 D3 40 90 4C CE 04 44 41 44 -44 00 85 12 D4 D3 00 A0 8C D4 06 44 41 44 44 2E -42 00 85 12 D4 D3 40 A0 7E D4 03 42 49 54 85 12 -D4 D3 00 B0 AA D4 05 42 49 54 2E 42 85 12 D4 D3 -40 B0 B6 D4 03 42 49 43 85 12 D4 D3 00 C0 C4 D4 -05 42 49 43 2E 42 85 12 D4 D3 40 C0 D0 D4 03 42 -49 53 85 12 D4 D3 00 D0 DE D4 05 42 49 53 2E 42 -85 12 D4 D3 40 D0 00 00 03 58 4F 52 85 12 D4 D3 -00 E0 F8 D4 05 58 4F 52 2E 42 85 12 D4 D3 40 E0 -2A D4 03 41 4E 44 85 12 D4 D3 00 F0 12 D5 05 41 -4E 44 2E 42 85 12 D4 D3 40 F0 4E CC C8 D2 30 D5 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -64 D4 03 52 52 43 85 12 2A D5 00 10 42 D5 05 52 -52 43 2E 42 85 12 2A D5 40 10 4E D5 04 53 57 50 -42 00 85 12 2A D5 80 10 5C D5 03 52 52 41 85 12 -2A D5 00 11 6A D5 05 52 52 41 2E 42 85 12 2A D5 -40 11 76 D5 03 53 58 54 85 12 2A D5 80 11 00 00 -04 50 55 53 48 00 85 12 2A D5 00 12 90 D5 06 50 -55 53 48 2E 42 00 85 12 2A D5 40 12 EA D4 04 43 -41 4C 4C 00 85 12 2A D5 80 12 1A 53 0E 4A 0D 12 -84 12 D6 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 84 D5 03 53 3E 3D 86 12 00 38 -D8 D5 02 53 3C 00 86 12 00 34 9E D5 03 30 3E 3D -86 12 00 30 EC D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C 00 D6 03 55 3E 3D 86 12 -00 28 F6 D5 03 30 3C 3E 86 12 00 24 14 D6 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D 0A D6 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -9A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F AE D5 -05 42 45 47 49 4E 30 40 28 C4 3E D6 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D 1E D5 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 2C D6 BA C7 60 C8 E2 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 C0 D6 44 D6 60 C8 F0 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 80 D6 03 42 57 31 85 12 EE D6 -00 00 08 D7 03 42 57 32 85 12 EE D6 00 00 14 D7 -03 42 57 33 85 12 EE D6 00 00 2C D7 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 2A D7 00 00 4C D7 03 46 57 32 85 12 2A D7 -00 00 58 D7 03 46 57 33 85 12 2A D7 00 00 64 D7 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 CC CC 28 CC 60 C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 4E CC F4 D1 AE D7 92 53 -C4 21 3E 40 2C 00 84 12 2C C9 88 CA 34 C4 4C CC -8A D3 C4 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -DC D6 04 52 52 43 4D 00 85 12 A8 D7 50 00 F2 D7 -04 52 52 41 4D 00 85 12 A8 D7 50 01 00 D8 04 52 -4C 41 4D 00 85 12 A8 D7 50 02 0E D8 04 52 52 55 -4D 00 85 12 A8 D7 50 03 1E D6 05 50 55 53 48 4D -85 12 A8 D7 00 15 2A D8 04 50 4F 50 4D 00 85 12 -A8 D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 94 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 54 D1 -q diff --git a/binaries/MSP_EXP430FR4133_1MHz_115200.txt b/binaries/MSP_EXP430FR4133_1MHz_115200.txt new file mode 100644 index 0000000..6fd1b5e --- /dev/null +++ b/binaries/MSP_EXP430FR4133_1MHz_115200.txt @@ -0,0 +1,328 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A0 59 +BC C6 7E C5 84 C5 54 C5 2C C7 54 D7 0C D0 C6 CF +C6 CF A2 C6 60 C7 28 C7 3C 21 E0 20 80 C9 B6 C4 +C4 C4 9C C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +2C C7 54 D7 0C D0 C6 CF C6 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 F9 3C 0E 93 3E 4F +8E 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A0 C6 B2 49 +5E C7 B2 49 26 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 80 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 2C C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 A6 C8 AC C4 52 C5 6E C7 1E C4 04 1B +5B 37 6D 00 90 C7 90 C7 1E C4 04 1B 5B 30 6D 00 +90 C7 16 CD B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 03 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 6E C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 90 C7 F4 C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 90 C7 0A C4 40 FF 32 C4 +BC C8 C0 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B2 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 D3 02 02 F2 D2 05 02 B2 D0 FF FE +26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 +66 02 B2 43 62 02 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 06 00 2B 02 F2 C3 82 01 B2 40 1E 00 84 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +39 40 00 08 29 83 89 43 00 20 FC 23 19 42 5E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 C4 86 C5 00 00 0C 41 43 43 45 50 54 00 30 40 +A2 C6 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 00 C7 3C 40 0C C7 5D 15 A2 3E 21 52 3A 17 +58 42 0C 05 48 9B 09 20 A2 B3 1C 05 FD 27 B2 40 +13 00 0E 05 F2 D2 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 1C 05 FD 27 C2 48 0E 05 30 4D +02 C7 2D 83 92 B3 1C 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 1C 05 FD 27 58 42 0C 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 28 C7 30 12 3E C7 A2 B3 1C 05 +FD 27 B2 40 11 00 0E 05 F2 C2 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 1C 05 FD 27 B0 12 C8 C6 1E 42 +0C 05 30 4D 00 00 08 45 4D 49 54 00 30 40 60 C7 +08 4E 3E 4F C7 3F 56 C7 08 45 43 48 4F 00 B2 40 +C2 48 FA C6 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D FA C6 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 A0 C7 29 4F 8F 4E 00 00 7E 49 DE 3F +A2 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +78 22 F9 98 00 00 75 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 6C 22 9B 24 20 C7 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 C0 C8 +B2 C7 04 CA F8 CC B0 C4 2E C8 14 C4 06 5B 54 48 +45 4E 5D 00 B6 C7 0C C8 D2 C7 F0 C7 14 C4 06 5B +45 4C 53 45 5D 00 B6 C7 1E C8 D2 C7 EE C7 1E C4 +04 5B 49 46 5D 00 B6 C7 F0 C7 B2 C4 EE C7 1E C4 +05 0D 6B 6F 20 0A 90 C7 9A C4 84 C4 B2 C4 F0 C7 +DE C7 0D 5B 54 48 45 4E 5D 00 30 4D 42 C8 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 4E C8 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 B2 C7 04 CA +6C CA 4A CC 80 C9 5E C8 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 B2 C7 04 CA 6C CA 90 C8 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D 96 C6 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 C5 05 53 22 00 82 43 +C0 21 0D 12 84 12 0A C4 1E C4 A8 CC 0A C4 22 00 +04 CA 04 C9 B2 40 20 00 C0 21 1A 53 1A B3 82 6A +C8 21 3E 4F 3D 41 30 4D 78 C7 05 2E 22 00 0D 12 +84 12 EE C8 0A C4 90 C7 A8 CC 80 C9 00 00 04 3C +23 00 B2 40 B2 21 B2 21 30 4D EA C8 02 23 1B 42 +BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 +18 42 B2 21 C8 4A 00 00 30 4D 3C C9 04 23 53 00 +0D 12 84 12 3E C9 78 C9 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 6C C9 04 23 3E 00 9F 42 B2 21 00 00 +3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 86 C9 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 68 C7 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 32 C9 +B2 C7 A0 C9 70 C9 9C C8 AE C9 8A C9 90 C7 80 C9 +1A C9 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 21 +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D BC C9 06 55 +4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 0E BA 02 24 +09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B 8F 49 00 00 +0E 48 30 4D F2 C9 0E 3E 4E 55 4D 42 45 52 1A 42 +BE 21 2C 4F 0B 4E 68 4C 78 80 3A 00 03 28 78 80 +07 00 21 28 78 50 0A 00 08 9A 22 C3 1C 2C 5D 15 +1C 4F 02 00 0E 4A 3D 40 1C CB D4 3F 1E CB 81 49 +02 00 1C 4F 04 00 1E 41 04 00 3D 40 30 CB CA 3F +32 CB 39 51 3E 61 8F 49 04 00 8F 4E 02 00 3A 17 +1C 53 1B 83 D8 23 8F 4C 00 00 0E 4B 30 4D 32 C0 +00 02 3F 82 8F 4E 06 00 8F 43 04 00 8F 43 02 00 +1A 42 BE 21 0C 4E 0E 43 1E 15 3D 40 B2 CB 7B 4C +68 4C 78 80 2D 00 16 24 BE 2F 2A 43 78 52 14 24 +3A 52 68 53 11 24 3A 40 10 00 58 93 0D 24 68 92 +40 20 3E 90 03 00 3D 20 FC 9C 01 00 6C 4C 8F 4C +04 00 37 3C B1 43 02 00 1B 83 FC 9C 00 00 E0 23 +A2 27 B4 CB 2E 24 2D 83 68 4C 78 90 5F 00 C0 27 +32 B0 00 02 26 20 32 D0 00 02 78 80 2E 00 B8 27 +68 53 1F 20 09 43 8F 49 02 00 5B 83 09 4B 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9A 08 2C 8F 49 00 00 0E 4A 2C 15 B0 12 +3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4B 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 2E C9 +03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 84 C4 +B2 C7 04 CA B0 C4 82 CD 6C CA 6C CC 0A 4E 3E 4F +3D 40 86 CC 6C 27 3D 40 60 CC 1A E2 BC 21 14 24 +0E 12 3E 4F 30 41 88 CC 3E 4F 3D 40 60 CC 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +5E CE 2A 3C 50 CC 02 2C A2 53 C8 21 1A 42 C8 21 +8A 4E FE FF 3E 4F 30 4D A6 CC 0F 4C 49 54 45 52 +41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 +C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F 32 B0 +00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D +A8 C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D CE C8 0A 41 4C 4C 4F 54 82 5E +C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 1E C4 +02 0D 0A 00 90 C7 94 C4 5A CC AE C8 D8 C8 1E C4 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 32 C4 +0A C4 40 FF E0 C8 1E C4 09 46 52 41 4D 20 66 75 +6C 6C 08 C5 B2 C4 1E CD 08 CD 0D 41 42 4F 52 54 +22 00 0D 12 84 12 EE C8 0A C4 08 C5 A8 CC 80 C9 +FE C9 02 27 0D 12 84 12 B2 C7 04 CA 6C CA B0 C4 +84 CD 12 C9 90 CC 78 C8 07 5B 27 5D 0D 12 84 12 +74 CD 0A C4 0A C4 A8 CC A8 CC 80 C9 88 CD 03 5B +82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 30 4D +C6 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +B2 C7 04 CA 6C CA B0 C4 84 CD D8 C8 AC C4 DC CD +0A C4 0A C4 A8 CC A8 CC 0A C4 A8 CC A8 CC 80 C9 +00 00 02 3A 30 12 32 CE 92 B3 C8 21 A2 63 C8 21 +0D 12 84 12 B2 C7 04 CA FA CD 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 82 49 +B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A C8 21 +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 C5 +9E CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 0A C4 +80 C9 A8 CC 44 CE A0 CD 80 C9 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 30 4D +F2 CC 0C 43 52 45 41 54 45 00 B0 12 E8 CD BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 8A C7 0A 44 4F 45 +53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D E2 CD 0E 3A 4E 4F 4E 41 4D 45 30 12 +32 CE 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 7C CE 05 49 53 00 +0D 12 82 93 BC 21 08 20 84 12 74 CD FE CE 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 8C CD 0A C4 00 CF +A8 CC 80 C9 92 CE 08 43 4F 44 45 00 B0 12 E8 CD +A2 82 C8 21 61 3C 9A C9 0E 48 44 4E 43 4F 44 45 +B2 40 EC CF CC 21 F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 44 CE 4A CF 3D 41 92 42 D0 21 +CC 21 5D 3C 16 CF 0E 43 4F 44 45 4E 4E 4D 30 12 +20 CF B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 21 +B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 21 1A 42 C8 21 EF 3F 28 CF 0B 48 49 32 4C 4F +A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 BC 21 +B9 3F B4 CF B2 40 C6 CF D0 21 82 4E CE 21 30 40 +12 C9 85 12 B2 CF B2 CD 5A CD 44 D0 56 CF AC CE +BE CA 66 CA 72 CD 9A CF EC CE C6 CE 62 CE BA CC +CE D0 E6 CA 00 00 00 00 85 12 B2 CF 48 D7 CC D5 +2C D7 F4 D4 50 D5 9E D5 7A D6 86 D6 16 D4 3A D5 +00 00 00 00 88 CF 06 D3 00 00 A2 D6 E6 CF B2 40 +C6 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 1A D0 +30 4D 2C D0 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 21 B0 12 1A D0 1A 42 CA 21 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 06 C6 FE FF 29 83 B9 40 F2 C5 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 EC FF 3B 40 10 00 +3A 40 3A 18 B0 12 1E D0 82 43 4A 18 C7 3F C0 D0 +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F A8 CD 0C 4D +41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 B2 C7 +04 CA 6C CA AC C4 EC D0 A6 C8 80 CC EE D0 3E 4F +3D 41 B2 41 C6 21 B0 12 E8 CD BA 40 85 12 FC FF +BA 40 BE D0 FE FF 28 83 8A 48 00 00 BA 40 82 C4 +02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 04 CA +6C CA AC C4 58 D1 38 D1 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 BE D0 00 00 01 20 +3E 52 2E 83 21 53 30 41 4E CB AC C4 60 D1 54 D1 +62 D1 B2 41 C6 21 30 41 92 83 C6 21 3E 40 28 00 +0A 4E 3D 15 B0 12 28 D1 15 20 3E 40 2B 00 B0 12 +28 D1 06 20 3E 40 2D 00 B0 12 28 D1 92 83 C6 21 +0E 12 1E 41 02 00 84 12 04 CA 4E CB AC C4 84 CD +A2 D1 3E 51 3A 17 30 41 B0 12 68 D1 19 42 C8 21 +89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 C6 21 +1A 42 C6 21 3D 15 84 12 04 CA 4E CB AC C4 DA D1 +D2 D1 3E 90 10 00 E6 2B 7C 2D DC D1 A2 41 C6 21 +E1 3F 03 20 B0 12 C0 D1 43 3C 7A 90 23 00 24 20 +B0 12 70 D1 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 C8 21 +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 70 D1 F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 BC D1 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 C0 D1 92 92 C2 21 C6 21 02 24 92 53 C6 21 +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 A8 D1 F2 3F +03 20 B0 12 C0 D1 F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 A8 D1 EA 3F 0C 43 +1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 C6 21 +19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 C4 21 +82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A C4 00 13 A8 CC 80 C9 0A C4 +2C 00 9E D2 E2 D1 B2 C7 A8 D2 80 D2 EE D2 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +DE D2 00 40 FA D2 0A 4D 4F 56 2E 42 85 12 DE D2 +40 40 00 00 06 41 44 44 85 12 DE D2 00 50 14 D3 +0A 41 44 44 2E 42 85 12 DE D2 40 50 20 D3 08 41 +44 44 43 00 85 12 DE D2 00 60 2E D3 0C 41 44 44 +43 2E 42 00 85 12 DE D2 40 60 66 CF 08 53 55 42 +43 00 85 12 DE D2 00 70 4C D3 0C 53 55 42 43 2E +42 00 85 12 DE D2 40 70 5A D3 06 53 55 42 85 12 +DE D2 00 80 6A D3 0A 53 55 42 2E 42 85 12 DE D2 +40 80 76 D3 06 43 4D 50 85 12 DE D2 00 90 84 D3 +0A 43 4D 50 2E 42 85 12 DE D2 40 90 00 00 08 44 +41 44 44 00 85 12 DE D2 00 A0 9E D3 0C 44 41 44 +44 2E 42 00 85 12 DE D2 40 A0 CC D2 06 42 49 54 +85 12 DE D2 00 B0 BC D3 0A 42 49 54 2E 42 85 12 +DE D2 40 B0 C8 D3 06 42 49 43 85 12 DE D2 00 C0 +D6 D3 0A 42 49 43 2E 42 85 12 DE D2 40 C0 E2 D3 +06 42 49 53 85 12 DE D2 00 D0 F0 D3 0A 42 49 53 +2E 42 85 12 DE D2 40 D0 00 00 06 58 4F 52 85 12 +DE D2 00 E0 0A D4 0A 58 4F 52 2E 42 85 12 DE D2 +40 E0 3C D3 06 41 4E 44 85 12 DE D2 00 F0 24 D4 +0A 41 4E 44 2E 42 85 12 DE D2 40 F0 B2 C7 9E D2 +E2 D1 44 D4 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F FC D3 06 52 52 43 85 12 3C D4 00 10 +56 D4 0A 52 52 43 2E 42 85 12 3C D4 40 10 90 D3 +08 53 57 50 42 00 85 12 3C D4 80 10 62 D4 06 52 +52 41 85 12 3C D4 00 11 7E D4 0A 52 52 41 2E 42 +85 12 3C D4 40 11 70 D4 06 53 58 54 85 12 3C D4 +80 11 00 00 08 50 55 53 48 00 85 12 3C D4 00 12 +A4 D4 0C 50 55 53 48 2E 42 00 85 12 3C D4 40 12 +98 D4 08 43 41 4C 4C 00 85 12 3C D4 80 12 1A 53 +0E 4A 84 12 F4 C9 1E C4 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 C5 C2 D4 06 53 3E 3D 86 12 +00 38 EA D4 04 53 3C 00 86 12 00 34 B2 D4 06 30 +3E 3D 86 12 00 30 FE D4 04 30 3C 00 86 12 00 30 +3A CF 04 55 3C 00 86 12 00 2C 12 D5 06 55 3E 3D +86 12 00 28 08 D5 06 30 3C 3E 86 12 00 24 26 D5 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D AC D3 +08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D 1C D5 08 45 4C 53 45 00 1A 42 C8 21 BA 40 +00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F +8A D4 0A 42 45 47 49 4E 30 40 32 C4 74 D5 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 21 30 4D 30 D4 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 3E D5 9A C8 80 C9 92 D5 0C 52 +45 50 45 41 54 00 0D 12 84 12 D2 D5 56 D5 80 C9 +02 D6 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F +98 42 C8 21 00 00 30 4D EE D5 06 42 57 31 85 12 +00 D6 00 00 1A D6 06 42 57 32 85 12 00 D6 00 00 +26 D6 06 42 57 33 85 12 00 D6 00 00 3E D6 3D 41 +1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 86 2B +BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 3C D6 00 00 62 D6 06 46 +57 32 85 12 3C D6 00 00 6E D6 06 46 57 33 85 12 +3C D6 00 00 DC D5 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 74 CD 80 CC 80 C9 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F A8 D2 +0A C4 2C 00 04 CA 4E CB AC C4 84 CD B2 C7 9E D2 +80 D2 D4 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +32 D6 08 52 52 43 4D 00 85 12 BE D6 50 00 02 D7 +08 52 52 41 4D 00 85 12 BE D6 50 01 10 D7 08 52 +4C 41 4D 00 85 12 BE D6 50 02 1E D7 08 52 52 55 +4D 00 85 12 BE D6 50 03 30 D5 0A 50 55 53 48 4D +85 12 BE D6 00 15 3A D7 08 50 4F 50 4D 00 85 12 +BE D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 BC C6 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR4133_1MHz_I2C.txt b/binaries/MSP_EXP430FR4133_1MHz_I2C.txt index d7ad25d..1dd7746 100644 --- a/binaries/MSP_EXP430FR4133_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR4133_1MHz_I2C.txt @@ -1,338 +1,325 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF 1E D8 2A D0 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 1E D8 -2A D0 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +B6 C6 56 C5 56 C5 58 C5 44 C5 30 D7 E8 CF A2 CF +A2 CF A4 C6 28 C7 00 C7 3C 21 E0 20 5C C9 B6 C4 +C4 C4 78 C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 30 D7 E8 CF A2 CF A2 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 F6 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 50 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 4A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 3C CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 82 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 82 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -8A C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 -0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B -8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 4D 42 -45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 30 00 -78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 1F 28 -08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 -44 CA D2 3F 46 CA 81 49 02 00 1C 4F 04 00 1E 41 -04 00 3D 40 58 CA C8 3F 5A CA 39 51 3E 61 8F 49 -04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 8F 4C -00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 0C 43 -2D 15 3D 40 D8 CA 0A 4B 3F 82 8F 4E 06 00 8F 43 -04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 00 00 -06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C 68 4C -78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C 2A 43 -78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 78 53 -35 20 1C 53 1B 83 EB 3F DA CA 30 24 2D 83 78 90 -28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 78 90 -F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 02 00 -5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 0A 00 -05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A 08 2C -8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 E6 3F -9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 0E 4C -82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 0E F3 -30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 -09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 -8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 00 00 -01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 3E 4F -30 4D 80 CB 87 4C 49 54 45 52 41 4C 82 93 BE 21 -0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 0A C4 -00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 -03 24 8A 4E 02 00 EE 3F 30 4D 54 C8 05 43 4F 55 -4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF 30 4D -68 C8 09 49 4E 54 45 52 50 52 45 54 0D 12 84 12 -AC C4 3C CC 1A C9 F8 CB 7F 26 3D 40 00 CC C1 3E -02 CC 0A 4E 3E 4F 3D 40 1C CC 35 27 3D 40 F2 CB -1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 1E CC 3E 4F -3D 40 F2 CB BB 23 DE 53 00 00 68 4E 08 5E F8 40 -3F 00 00 00 3D 40 BE CD CC 3F 26 CC 86 12 20 00 -D4 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F 30 4D -3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 00 20 -82 43 BE 21 84 12 7C C7 BC C4 EC CB B2 C7 E4 C7 -14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 21 00 -2A C5 0A C4 40 FF 28 C4 EC C7 14 C4 0A 46 52 41 -4D 20 66 75 6C 6C 21 00 2A C5 3A C4 66 CC 42 CC -86 41 42 4F 52 54 22 00 0D 12 84 12 D2 C8 0A C4 -2A C5 82 CB 4E C8 7C C9 01 27 0D 12 84 12 3C CC -1A C9 82 C9 34 C4 3A CC 4E C8 00 00 83 5B 27 5D -0D 12 84 12 BA CC 0A C4 0A C4 82 CB 82 CB 4E C8 -CC CC 81 5B 82 43 BE 21 30 4D FA C7 01 5D B2 43 -BE 21 30 4D EC CC 81 5C 92 42 C0 21 C4 21 30 4D -00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 -3C CC 1A C9 82 C9 96 C7 34 C4 3A CC E4 C7 34 C4 -2E CD 0A C4 0A C4 82 CB 82 CB 0A C4 82 CB 82 CB -4E C8 E2 CC 01 3A 30 12 7E CD 92 B3 C6 21 A2 63 -C6 21 0D 12 84 12 3C CC 1A C9 4C CD 3D 41 08 4E -7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E 3E F0 -1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 82 4A -BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 BA 40 -0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 30 4D -82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 A8 49 -FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 0F 73 -74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 36 C5 -34 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 0A C4 -4E C8 82 CB 90 CD E4 CC 4E C8 E2 CB 09 49 4D 4D -45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 00 00 -30 4D CC CB 06 43 52 45 41 54 45 00 B0 12 3A CD -BA 40 86 12 FC FF 8A 4A FE FF C9 3F F4 CD 04 43 -4F 44 45 00 B0 12 3A CD A2 82 C6 21 0D 12 84 12 -2C D0 06 D0 4E C8 DC CD 07 48 44 4E 43 4F 44 45 -B2 40 0A D0 DA 21 EE 3F 00 00 07 45 4E 44 43 4F -44 45 0D 12 84 12 90 CD 46 D0 64 D0 4E C8 00 00 -05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 00 00 -BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 0D 12 -84 12 46 D0 64 D0 4E C8 00 00 05 4C 4F 32 48 49 -A2 83 C6 21 1A 42 C6 21 EB 3F 28 CE 85 48 49 32 -4C 4F 0D 12 84 12 28 C4 D4 CF 82 CB E4 CC 1C CE -4E C8 C2 CD 86 5B 54 48 45 4E 5D 00 30 4D 0C 4E -38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 06 30 -1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D 3E 4F -30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 F7 3F -A4 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 -00 00 C6 C7 3C CC 1A C9 D2 CB 8E C7 34 C4 3C CF -9C C7 14 C4 06 5B 54 48 45 4E 5D 00 AE CE 16 CF -D2 CE F4 CE 4E C8 9C C7 14 C4 06 5B 45 4C 53 45 -5D 00 AE CE 2C CF D2 CE F2 CE 4E C8 14 C4 04 5B -49 46 5D 00 AE CE F4 CE 3A C4 F2 CE 70 C7 14 C4 -05 0D 0A 6B 6F 20 4A C7 BC C4 AC C4 3A C4 F4 CE -E2 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D -2F 53 30 4D 52 CF 89 5B 44 45 46 49 4E 45 44 5D -0D 12 84 12 3C CC 1A C9 82 C9 60 CF 4E C8 66 CF -8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 -70 CF DE C7 4E C8 98 CF B2 4E 0A 18 2E 53 BE 12 -3E 4F 3D 41 90 3C 94 CB 06 4D 41 52 4B 45 52 00 -B0 12 3A CD BA 40 85 12 FC FF BA 40 96 CF FE FF -28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 06 00 -C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 D6 C7 4E C8 -85 12 D8 CF A0 CC 0E CE 10 C7 B8 CC 8C CE D2 C6 -A8 CF 00 C9 D0 D0 E4 D0 E2 C9 14 C9 00 00 80 CF -F6 CC 0A CA 00 00 85 12 D8 CF 94 D6 FA D6 3C D6 -4A D7 02 D6 00 00 CE D3 00 00 12 D8 F6 D7 66 D6 -A4 D6 DE D4 00 00 00 00 66 D7 04 D0 3A 40 0C 00 -39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 00 00 -1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 09 48 -29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D 82 43 -CC 21 30 4D 92 42 CA 21 DA 21 30 4D E0 CF 5E D0 -64 D0 74 D0 1A 42 20 18 82 4A C8 21 2E 4E 82 4E -C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF -0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 -F0 23 3E 4F 3D 41 30 4D 02 CD 09 50 57 52 5F 53 -54 41 54 45 85 12 6C D0 1E D8 CE C8 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 B8 D0 F3 3F AA D0 -08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 B8 D0 -30 4D BC D0 08 52 53 54 5F 48 45 52 45 00 92 42 -C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 E3 37 -0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 42 D1 FE FF 29 83 B9 40 E2 C5 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 C5 B2 49 FA C4 -B2 49 02 C4 B2 49 00 C6 B2 49 EA FF B2 49 0A 18 -C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 -80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 00 08 -29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 02 02 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FA 3C 0E 93 3E 4F +7C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A2 C6 B2 49 +26 C7 B2 49 FE C6 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 5C D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 82 C8 AC C4 +42 C5 40 C7 1E C4 05 1B 5B 37 6D 40 6C C7 0A C4 +02 18 A4 C8 D0 C9 6C C7 1E C4 04 1B 5B 30 6D 00 +6C C7 F2 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +4A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 40 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 6C C7 0A C4 02 18 A4 C8 D0 C9 0A C4 23 00 +24 C7 D0 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +6C C7 0A C4 40 FF 32 C4 98 C8 9C C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B2 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 D3 02 02 B2 D0 FF FE 26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 B0 00 82 01 B2 40 1E 00 -84 01 82 43 88 01 F2 D0 06 00 2B 02 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 C4 FE C5 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A C9 82 C9 -DE C7 34 C4 0E D2 76 CA 34 C4 28 D2 22 D2 10 D2 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 2A D2 B2 41 C4 21 3E 41 -84 12 0A C4 2B 00 1A C9 82 C9 DE C7 34 C4 46 D2 -76 CA 34 C4 3A CC A8 C7 1A C9 76 CA 34 C4 3A CC -52 D2 3E 5F E7 3F 3E 40 28 00 B0 12 F2 D1 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 A8 CD 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A C9 76 CA 34 C4 9A D2 90 D2 -21 53 3E 90 10 00 C6 2B 7F 2D 9C D2 B2 41 C4 21 -C1 3F 0D 12 84 12 3C CC CE D1 AC D2 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 F2 D1 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 F2 D1 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 7A D2 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -7A D2 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 7A D2 FA 23 3C 50 10 00 B0 12 -56 D2 EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 3C CC CE D1 78 D3 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 7A D2 E0 23 -3C 50 80 00 B0 12 56 D2 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A C4 00 13 82 CB 4E C8 0A C4 -2C 00 A2 D2 6E D3 B8 D3 09 4B 2E 4E 0E DC A2 3F -7A CE 03 4D 4F 56 85 12 AE D3 00 40 C2 D3 05 4D -4F 56 2E 42 85 12 AE D3 40 40 00 00 03 41 44 44 -85 12 AE D3 00 50 DC D3 05 41 44 44 2E 42 85 12 -AE D3 40 50 E8 D3 04 41 44 44 43 00 85 12 AE D3 -00 60 F6 D3 06 41 44 44 43 2E 42 00 85 12 AE D3 -40 60 9C D3 04 53 55 42 43 00 85 12 AE D3 00 70 -14 D4 06 53 55 42 43 2E 42 00 85 12 AE D3 40 70 -22 D4 03 53 55 42 85 12 AE D3 00 80 32 D4 05 53 -55 42 2E 42 85 12 AE D3 40 80 50 CE 03 43 4D 50 -85 12 AE D3 00 90 4C D4 05 43 4D 50 2E 42 85 12 -AE D3 40 90 3A CE 04 44 41 44 44 00 85 12 AE D3 -00 A0 66 D4 06 44 41 44 44 2E 42 00 85 12 AE D3 -40 A0 58 D4 03 42 49 54 85 12 AE D3 00 B0 84 D4 -05 42 49 54 2E 42 85 12 AE D3 40 B0 90 D4 03 42 -49 43 85 12 AE D3 00 C0 9E D4 05 42 49 43 2E 42 -85 12 AE D3 40 C0 AA D4 03 42 49 53 85 12 AE D3 -00 D0 B8 D4 05 42 49 53 2E 42 85 12 AE D3 40 D0 -00 00 03 58 4F 52 85 12 AE D3 00 E0 D2 D4 05 58 -4F 52 2E 42 85 12 AE D3 40 E0 04 D4 03 41 4E 44 -85 12 AE D3 00 F0 EC D4 05 41 4E 44 2E 42 85 12 -AE D3 40 F0 3C CC A2 D2 0A D5 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 3E D4 03 52 52 43 -85 12 04 D5 00 10 1C D5 05 52 52 43 2E 42 85 12 -04 D5 40 10 28 D5 04 53 57 50 42 00 85 12 04 D5 -80 10 36 D5 03 52 52 41 85 12 04 D5 00 11 44 D5 -05 52 52 41 2E 42 85 12 04 D5 40 11 50 D5 03 53 -58 54 85 12 04 D5 80 11 00 00 04 50 55 53 48 00 -85 12 04 D5 00 12 6A D5 06 50 55 53 48 2E 42 00 -85 12 04 D5 40 12 C4 D4 04 43 41 4C 4C 00 85 12 -04 D5 80 12 1A 53 0E 4A 0D 12 84 12 C4 C8 14 C4 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C5 -5E D5 03 53 3E 3D 86 12 00 38 B2 D5 02 53 3C 00 -86 12 00 34 78 D5 03 30 3E 3D 86 12 00 30 C6 D5 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C DA D5 03 55 3E 3D 86 12 00 28 D0 D5 03 30 -3C 3E 86 12 00 24 EE D5 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D E4 D5 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 74 D4 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 88 D5 05 42 45 47 49 4E -30 40 28 C4 18 D6 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D F8 D4 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 06 D6 -A8 C7 4E C8 BC D5 06 52 45 50 45 41 54 00 0D 12 -84 12 9A D6 1E D6 4E C8 CA D6 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -5A D6 03 42 57 31 85 12 C8 D6 00 00 E2 D6 03 42 -57 32 85 12 C8 D6 00 00 EE D6 03 42 57 33 85 12 -C8 D6 00 00 06 D7 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 04 D7 00 00 -26 D7 03 46 57 32 85 12 04 D7 00 00 32 D7 03 46 -57 33 85 12 04 D7 00 00 3E D7 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 BA CC -16 CC 4E C8 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 3C CC CE D1 88 D7 92 53 C4 21 3E 40 2C 00 -84 12 1A C9 76 CA 34 C4 3A CC 64 D3 9E D7 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E B6 D6 04 52 52 43 -4D 00 85 12 82 D7 50 00 CC D7 04 52 52 41 4D 00 -85 12 82 D7 50 01 DA D7 04 52 4C 41 4D 00 85 12 -82 D7 50 02 E8 D7 04 52 52 55 4D 00 85 12 82 D7 -50 03 F8 D5 05 50 55 53 48 4D 85 12 82 D7 00 15 -04 D8 04 50 4F 50 4D 00 85 12 82 D7 00 17 +82 43 88 01 F2 D0 06 00 2B 02 F2 C3 82 01 B2 40 +1E 00 84 01 39 40 40 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 39 40 00 08 29 83 89 43 00 20 FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 5E 01 +B0 12 D0 C4 80 C5 00 00 0C 41 43 43 45 50 54 00 +30 40 A4 C6 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 A5 3E 21 52 A2 C2 6C 05 B2 B0 10 00 +40 05 9E 22 3A 17 92 B3 6C 05 FD 27 58 42 4C 05 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 00 C7 +58 43 B0 12 46 C5 2F 83 8F 4E 00 00 92 B3 6C 05 +FD 27 1E 42 4C 05 B0 12 44 C5 30 4D 00 00 08 45 +4D 49 54 00 30 40 28 C7 08 4E 3E 4F A2 B3 6C 05 +FD 27 C2 48 4E 05 30 4D 1E C7 08 45 43 48 4F 00 +B2 40 C2 48 32 C7 38 40 05 00 B0 12 46 C5 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 32 C7 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +7C C7 29 4F 8F 4E 00 00 7E 49 D4 3F 7E C7 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 8A 22 F9 98 +00 00 87 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 7E 22 9B 24 F8 C6 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A C4 00 00 9C C8 8E C7 E0 C9 +D4 CC B0 C4 0A C8 14 C4 06 5B 54 48 45 4E 5D 00 +92 C7 E8 C7 AE C7 CC C7 14 C4 06 5B 45 4C 53 45 +5D 00 92 C7 FA C7 AE C7 CA C7 1E C4 04 5B 49 46 +5D 00 92 C7 CC C7 B2 C4 CA C7 1E C4 05 0D 6B 6F +20 0A 6C C7 9A C4 84 C4 B2 C4 CC C7 BA C7 0D 5B +54 48 45 4E 5D 00 30 4D 1E C8 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 2A C8 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 8E C7 E0 C9 48 CA 26 CC +5C C9 3A C8 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 8E C7 E0 C9 48 CA 6C C8 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 20 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D 98 C6 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 C5 05 53 22 00 82 43 C0 21 0D 12 +84 12 0A C4 1E C4 84 CC 0A C4 22 00 E0 C9 E0 C8 +B2 40 20 00 C0 21 1A 53 1A B3 82 6A C8 21 3E 4F +3D 41 30 4D 52 C7 05 2E 22 00 0D 12 84 12 CA C8 +0A C4 6C C7 84 CC 5C C9 00 00 04 3C 23 00 B2 40 +B2 21 B2 21 30 4D C6 C8 02 23 1B 42 BE 21 2C 4F +2F 83 B0 12 46 C4 BF 4F 00 00 7A 90 0A 00 02 28 +7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 +C8 4A 00 00 30 4D 18 C9 04 23 53 00 0D 12 84 12 +1A C9 54 C9 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +48 C9 04 23 3E 00 9F 42 B2 21 00 00 3E 40 B2 21 +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 62 C9 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 3A C7 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 0E C9 8E C7 7C C9 +4C C9 78 C8 8A C9 66 C9 6C C7 5C C9 F6 C8 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 21 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 21 F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 21 +82 48 C6 21 1E 42 C8 21 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 21 +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D 98 C9 06 55 4D 2A 2C 4F +0B 43 09 43 08 43 1A 43 0E BA 02 24 09 5C 08 6B +0C 5C 0B 6B 0A 5A F8 2B 8F 49 00 00 0E 48 30 4D +CE C9 0E 3E 4E 55 4D 42 45 52 1A 42 BE 21 2C 4F +0B 4E 68 4C 78 80 3A 00 03 28 78 80 07 00 21 28 +78 50 0A 00 08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 +0E 4A 3D 40 F8 CA D4 3F FA CA 81 49 02 00 1C 4F +04 00 1E 41 04 00 3D 40 0C CB CA 3F 0E CB 39 51 +3E 61 8F 49 04 00 8F 4E 02 00 3A 17 1C 53 1B 83 +D8 23 8F 4C 00 00 0E 4B 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 8F 43 04 00 8F 43 02 00 1A 42 BE 21 +0C 4E 0E 43 1E 15 3D 40 8E CB 7B 4C 68 4C 78 80 +2D 00 16 24 BE 2F 2A 43 78 52 14 24 3A 52 68 53 +11 24 3A 40 10 00 58 93 0D 24 68 92 40 20 3E 90 +03 00 3D 20 FC 9C 01 00 6C 4C 8F 4C 04 00 37 3C +B1 43 02 00 1B 83 FC 9C 00 00 E0 23 A2 27 90 CB +2E 24 2D 83 68 4C 78 90 5F 00 C0 27 32 B0 00 02 +26 20 32 D0 00 02 78 80 2E 00 B8 27 68 53 1F 20 +09 43 8F 49 02 00 5B 83 09 4B 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9A +08 2C 8F 49 00 00 0E 4A 2C 15 B0 12 3E C4 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4B 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 0A C9 03 5C 92 42 +C2 21 C6 21 30 4D 0D 12 84 12 84 C4 8E C7 E0 C9 +B0 C4 5E CD 48 CA 48 CC 0A 4E 3E 4F 3D 40 62 CC +6C 27 3D 40 3C CC 1A E2 BC 21 14 24 0E 12 3E 4F +30 41 64 CC 3E 4F 3D 40 3C CC 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 3A CE 2A 3C +2C CC 02 2C A2 53 C8 21 1A 42 C8 21 8A 4E FE FF +3E 4F 30 4D 82 CC 0F 4C 49 54 45 52 41 4C 82 93 +BC 21 0D 24 09 4E 1A 42 C8 21 A2 52 C8 21 BA 40 +0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D 84 C9 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D AA C8 0A 41 4C 4C 4F 54 82 5E C8 21 3E 4F +30 4D 3F 40 80 20 0E 43 84 12 1E C4 02 0D 0A 00 +6C C7 94 C4 36 CC 8A C8 B4 C8 1E C4 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 C5 32 C4 0A C4 40 FF +BC C8 1E C4 09 46 52 41 4D 20 66 75 6C 6C 08 C5 +B2 C4 FA CC E4 CC 0D 41 42 4F 52 54 22 00 0D 12 +84 12 CA C8 0A C4 08 C5 84 CC 5C C9 DA C9 02 27 +0D 12 84 12 8E C7 E0 C9 48 CA B0 C4 60 CD EE C8 +6C CC 54 C8 07 5B 27 5D 0D 12 84 12 50 CD 0A C4 +0A C4 84 CC 84 CC 5C C9 64 CD 03 5B 82 43 BC 21 +30 4D 00 00 02 5D B2 43 BC 21 30 4D A2 C8 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 8E C7 E0 C9 +48 CA B0 C4 60 CD B4 C8 AC C4 B8 CD 0A C4 0A C4 +84 CC 84 CC 0A C4 84 CC 84 CC 5C C9 00 00 02 3A +30 12 0E CE 92 B3 C8 21 A2 63 C8 21 0D 12 84 12 +8E C7 E0 C9 D6 CD 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 21 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 21 82 49 B6 21 82 4A +B8 21 82 4F BA 21 2A 52 82 4A C8 21 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 21 30 4D +82 9F BA 21 66 25 84 12 1E C4 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 C5 7A CD 03 3B +82 93 BC 21 F4 26 0D 12 84 12 0A C4 5C C9 84 CC +20 CE 7C CD 5C C9 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 21 D8 D3 00 00 30 4D CE CC 0C 43 +52 45 41 54 45 00 B0 12 C4 CD BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 66 C7 0A 44 4F 45 53 3E 1A 42 +B8 21 BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +BE CD 0E 3A 4E 4F 4E 41 4D 45 30 12 0E CE 2F 83 +8F 4E 00 00 1A 42 C8 21 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 58 CE 05 49 53 00 0D 12 82 93 +BC 21 08 20 84 12 50 CD DA CE 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 68 CD 0A C4 DC CE 84 CC 5C C9 +6E CE 08 43 4F 44 45 00 B0 12 C4 CD A2 82 C8 21 +61 3C 76 C9 0E 48 44 4E 43 4F 44 45 B2 40 C8 CF +CC 21 F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 20 CE 26 CF 3D 41 92 42 D0 21 CC 21 5D 3C +F2 CE 0E 43 4F 44 45 4E 4E 4D 30 12 FC CE B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 21 BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 21 B2 43 BC 21 +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 21 1A 42 +C8 21 EF 3F 04 CF 0B 48 49 32 4C 4F A2 53 C8 21 +1A 42 C8 21 8A 4A FE FF 82 43 BC 21 B9 3F 90 CF +B2 40 A2 CF D0 21 82 4E CE 21 30 40 EE C8 85 12 +8E CF 8E CD 36 CD 20 D0 32 CF 88 CE 9A CA 42 CA +4E CD 76 CF C8 CE A2 CE 3E CE 96 CC AA D0 C2 CA +00 00 00 00 85 12 8E CF 24 D7 A8 D5 08 D7 D0 D4 +2C D5 7A D5 56 D6 62 D6 F2 D3 16 D5 00 00 00 00 +64 CF E2 D2 00 00 7E D6 C2 CF B2 40 A2 CF CE 21 +82 43 D0 21 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 21 3A 40 42 18 B0 12 F6 CF 30 4D 08 D0 +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 21 B0 12 F6 CF 1A 42 CA 21 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 0E C6 +FE FF 29 83 B9 40 FA C5 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 EA FF 3B 40 10 00 3A 40 3A 18 +B0 12 FA CF 82 43 4A 18 C7 3F 9C D0 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 84 CD 0C 4D 41 52 4B 45 +52 00 12 12 C6 21 0D 12 84 12 8E C7 E0 C9 48 CA +AC C4 C8 D0 82 C8 5C CC CA D0 3E 4F 3D 41 B2 41 +C6 21 B0 12 C4 CD BA 40 85 12 FC FF BA 40 9A D0 +FE FF 28 83 8A 48 00 00 BA 40 82 C4 02 00 A2 52 +C8 21 18 42 B4 21 19 42 B6 21 A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 21 84 12 E0 C9 48 CA AC C4 +34 D1 14 D1 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 9A D0 00 00 01 20 3E 52 2E 83 +21 53 30 41 2A CB AC C4 3C D1 30 D1 3E D1 B2 41 +C6 21 30 41 92 83 C6 21 3E 40 28 00 0A 4E 3D 15 +B0 12 04 D1 15 20 3E 40 2B 00 B0 12 04 D1 06 20 +3E 40 2D 00 B0 12 04 D1 92 83 C6 21 0E 12 1E 41 +02 00 84 12 E0 C9 2A CB AC C4 60 CD 7E D1 3E 51 +3A 17 30 41 B0 12 44 D1 19 42 C8 21 89 4E 00 00 +A2 53 C8 21 3E 40 29 00 92 53 C6 21 1A 42 C6 21 +3D 15 84 12 E0 C9 2A CB AC C4 B6 D1 AE D1 3E 90 +10 00 E6 2B 7C 2D B8 D1 A2 41 C6 21 E1 3F 03 20 +B0 12 9C D1 43 3C 7A 90 23 00 24 20 B0 12 4C D1 +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 21 A2 53 C8 21 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +4C D1 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +98 D1 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 9C D1 +92 92 C2 21 C6 21 02 24 92 53 C6 21 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 84 D1 F2 3F 03 20 B0 12 +9C D1 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 84 D1 EA 3F 0C 43 1B 42 C8 21 +A2 53 C8 21 3A 40 20 00 19 42 C6 21 19 52 C4 21 +7A 99 FE 27 5A 49 FF FF 19 82 C4 21 82 49 C6 21 +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A C4 00 13 84 CC 5C C9 0A C4 2C 00 7A D2 +BE D1 8E C7 84 D2 5C D2 CA D2 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 BA D2 00 40 +D6 D2 0A 4D 4F 56 2E 42 85 12 BA D2 40 40 00 00 +06 41 44 44 85 12 BA D2 00 50 F0 D2 0A 41 44 44 +2E 42 85 12 BA D2 40 50 FC D2 08 41 44 44 43 00 +85 12 BA D2 00 60 0A D3 0C 41 44 44 43 2E 42 00 +85 12 BA D2 40 60 42 CF 08 53 55 42 43 00 85 12 +BA D2 00 70 28 D3 0C 53 55 42 43 2E 42 00 85 12 +BA D2 40 70 36 D3 06 53 55 42 85 12 BA D2 00 80 +46 D3 0A 53 55 42 2E 42 85 12 BA D2 40 80 52 D3 +06 43 4D 50 85 12 BA D2 00 90 60 D3 0A 43 4D 50 +2E 42 85 12 BA D2 40 90 00 00 08 44 41 44 44 00 +85 12 BA D2 00 A0 7A D3 0C 44 41 44 44 2E 42 00 +85 12 BA D2 40 A0 A8 D2 06 42 49 54 85 12 BA D2 +00 B0 98 D3 0A 42 49 54 2E 42 85 12 BA D2 40 B0 +A4 D3 06 42 49 43 85 12 BA D2 00 C0 B2 D3 0A 42 +49 43 2E 42 85 12 BA D2 40 C0 BE D3 06 42 49 53 +85 12 BA D2 00 D0 CC D3 0A 42 49 53 2E 42 85 12 +BA D2 40 D0 00 00 06 58 4F 52 85 12 BA D2 00 E0 +E6 D3 0A 58 4F 52 2E 42 85 12 BA D2 40 E0 18 D3 +06 41 4E 44 85 12 BA D2 00 F0 00 D4 0A 41 4E 44 +2E 42 85 12 BA D2 40 F0 8E C7 7A D2 BE D1 20 D4 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +D8 D3 06 52 52 43 85 12 18 D4 00 10 32 D4 0A 52 +52 43 2E 42 85 12 18 D4 40 10 6C D3 08 53 57 50 +42 00 85 12 18 D4 80 10 3E D4 06 52 52 41 85 12 +18 D4 00 11 5A D4 0A 52 52 41 2E 42 85 12 18 D4 +40 11 4C D4 06 53 58 54 85 12 18 D4 80 11 00 00 +08 50 55 53 48 00 85 12 18 D4 00 12 80 D4 0C 50 +55 53 48 2E 42 00 85 12 18 D4 40 12 74 D4 08 43 +41 4C 4C 00 85 12 18 D4 80 12 1A 53 0E 4A 84 12 +D0 C9 1E C4 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 C5 9E D4 06 53 3E 3D 86 12 00 38 C6 D4 +04 53 3C 00 86 12 00 34 8E D4 06 30 3E 3D 86 12 +00 30 DA D4 04 30 3C 00 86 12 00 30 16 CF 04 55 +3C 00 86 12 00 2C EE D4 06 55 3E 3D 86 12 00 28 +E4 D4 06 30 3C 3E 86 12 00 24 02 D5 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 21 8A 4E +00 00 A2 53 C8 21 0E 4A 30 4D 88 D3 08 54 48 45 +4E 00 1A 42 C8 21 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D F8 D4 +08 45 4C 53 45 00 1A 42 C8 21 BA 40 00 3C 00 00 +A2 53 C8 21 2F 83 8F 4A 00 00 E3 3F 66 D4 0A 42 +45 47 49 4E 30 40 32 C4 50 D5 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 21 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 21 30 4D 0C D4 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 1A D5 76 C8 5C C9 6E D5 0C 52 45 50 45 41 +54 00 0D 12 84 12 AE D5 32 D5 5C C9 DE D5 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 21 CB 2F 98 42 C8 21 +00 00 30 4D CA D5 06 42 57 31 85 12 DC D5 00 00 +F6 D5 06 42 57 32 85 12 DC D5 00 00 02 D6 06 42 +57 33 85 12 DC D5 00 00 1A D6 3D 41 1A 42 C8 21 +28 4E 8E 43 00 00 B2 92 C6 21 86 2B BA 4F 00 00 +A2 53 C8 21 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 18 D6 00 00 3E D6 06 46 57 32 85 12 +18 D6 00 00 4A D6 06 46 57 33 85 12 18 D6 00 00 +B8 D5 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 50 CD 5C CC 5C C9 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 84 D2 0A C4 2C 00 +E0 C9 2A CB AC C4 60 CD 8E C7 7A D2 5C D2 B0 D6 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E 0E D6 08 52 +52 43 4D 00 85 12 9A D6 50 00 DE D6 08 52 52 41 +4D 00 85 12 9A D6 50 01 EC D6 08 52 4C 41 4D 00 +85 12 9A D6 50 02 FA D6 08 52 52 55 4D 00 85 12 +9A D6 50 03 0C D5 0A 50 55 53 48 4D 85 12 9A D6 +00 15 16 D7 08 50 4F 50 4D 00 85 12 9A D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 82 C6 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 42 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 B6 C6 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR4133_1MHz_UART.txt b/binaries/MSP_EXP430FR4133_1MHz_UART.txt deleted file mode 100644 index d7f6e4e..0000000 --- a/binaries/MSP_EXP430FR4133_1MHz_UART.txt +++ /dev/null @@ -1,340 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF 34 D8 3C D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 34 D8 -3C D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 08 D1 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 62 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 03 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 F2 D2 03 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 F2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 4E CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -94 CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -94 CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 9C C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 -1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A -F8 2B 8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 -4D 42 45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 -30 00 78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 -1F 28 08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A -3D 40 56 CA D2 3F 58 CA 81 49 02 00 1C 4F 04 00 -1E 41 04 00 3D 40 6A CA C8 3F 6C CA 39 51 3E 61 -8F 49 04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 -8F 4C 00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 -0C 43 2D 15 3D 40 EA CA 0A 4B 3F 82 8F 4E 06 00 -8F 43 04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 -00 00 06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C -68 4C 78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C -2A 43 78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 -78 53 35 20 1C 53 1B 83 EB 3F EC CA 30 24 2D 83 -78 90 28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 -78 90 F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 -02 00 5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 -0A 00 05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A -08 2C 8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 -E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 -0E 4C 82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 -0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 -3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 -02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D -00 00 01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 -3E 4F 30 4D 92 CB 87 4C 49 54 45 52 41 4C 82 93 -BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 -0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 -00 02 03 24 8A 4E 02 00 EE 3F 30 4D 66 C8 05 43 -4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF -30 4D 7A C8 09 49 4E 54 45 52 50 52 45 54 0D 12 -84 12 AC C4 4E CC 2C C9 0A CC 7F 26 3D 40 12 CC -C1 3E 14 CC 0A 4E 3E 4F 3D 40 2E CC 35 27 3D 40 -04 CC 1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 30 CC -3E 4F 3D 40 04 CC BB 23 DE 53 00 00 68 4E 08 5E -F8 40 3F 00 00 00 3D 40 D0 CD CC 3F 38 CC 86 12 -20 00 E6 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F -30 4D 3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 -00 20 82 43 BE 21 84 12 8E C7 BC C4 FE CB C4 C7 -F6 C7 14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 -21 00 2A C5 0A C4 40 FF 28 C4 FE C7 14 C4 0A 46 -52 41 4D 20 66 75 6C 6C 21 00 2A C5 3A C4 78 CC -54 CC 86 41 42 4F 52 54 22 00 0D 12 84 12 E4 C8 -0A C4 2A C5 94 CB 60 C8 8E C9 01 27 0D 12 84 12 -4E CC 2C C9 94 C9 34 C4 4C CC 60 C8 00 00 83 5B -27 5D 0D 12 84 12 CC CC 0A C4 0A C4 94 CB 94 CB -60 C8 DE CC 81 5B 82 43 BE 21 30 4D 0C C8 01 5D -B2 43 BE 21 30 4D FE CC 81 5C 92 42 C0 21 C4 21 -30 4D 00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 -84 12 4E CC 2C C9 94 C9 A8 C7 34 C4 4C CC F6 C7 -34 C4 40 CD 0A C4 0A C4 94 CB 94 CB 0A C4 94 CB -94 CB 60 C8 F4 CC 01 3A 30 12 90 CD 92 B3 C6 21 -A2 63 C6 21 0D 12 84 12 4E CC 2C C9 5E CD 3D 41 -08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E -3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 -82 4A BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 -BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 -30 4D 82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 -A8 49 FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 -0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 -36 C5 46 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 -0A C4 60 C8 94 CB A2 CD F6 CC 60 C8 F4 CB 09 49 -4D 4D 45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 -00 00 30 4D DE CB 06 43 52 45 41 54 45 00 B0 12 -4C CD BA 40 86 12 FC FF 8A 4A FE FF C9 3F 06 CE -04 43 4F 44 45 00 B0 12 4C CD A2 82 C6 21 0D 12 -84 12 3E D0 18 D0 60 C8 EE CD 07 48 44 4E 43 4F -44 45 B2 40 1C D0 DA 21 EE 3F 00 00 07 45 4E 44 -43 4F 44 45 0D 12 84 12 A2 CD 58 D0 76 D0 60 C8 -00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 -00 00 BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 -0D 12 84 12 58 D0 76 D0 60 C8 00 00 05 4C 4F 32 -48 49 A2 83 C6 21 1A 42 C6 21 EB 3F 3A CE 85 48 -49 32 4C 4F 0D 12 84 12 28 C4 E6 CF 94 CB F6 CC -2E CE 60 C8 D4 CD 86 5B 54 48 45 4E 5D 00 30 4D -0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 -06 30 1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D -3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 -F7 3F B6 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 -0A C4 00 00 D8 C7 4E CC 2C C9 E4 CB A0 C7 34 C4 -4E CF AE C7 14 C4 06 5B 54 48 45 4E 5D 00 C0 CE -28 CF E4 CE 06 CF 60 C8 AE C7 14 C4 06 5B 45 4C -53 45 5D 00 C0 CE 3E CF E4 CE 04 CF 60 C8 14 C4 -04 5B 49 46 5D 00 C0 CE 06 CF 3A C4 04 CF 82 C7 -14 C4 05 0D 0A 6B 6F 20 5C C7 BC C4 AC C4 3A C4 -06 CF F4 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 -30 4D 2F 53 30 4D 64 CF 89 5B 44 45 46 49 4E 45 -44 5D 0D 12 84 12 4E CC 2C C9 94 C9 72 CF 60 C8 -78 CF 8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 -84 12 82 CF F0 C7 60 C8 AA CF B2 4E 0A 18 2E 53 -BE 12 3E 4F 3D 41 90 3C A6 CB 06 4D 41 52 4B 45 -52 00 B0 12 4C CD BA 40 85 12 FC FF BA 40 A8 CF -FE FF 28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 -06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 E8 C7 -60 C8 85 12 EA CF B2 CC 20 CE 2C C7 CA CC 9E CE -F6 C6 BA CF 12 C9 E2 D0 F6 D0 F4 C9 26 C9 00 00 -92 CF 08 CD 1C CA 00 00 85 12 EA CF AA D6 10 D7 -52 D6 60 D7 18 D6 00 00 E4 D3 00 00 28 D8 0C D8 -7C D6 BA D6 F4 D4 00 00 00 00 7C D7 16 D0 3A 40 -0C 00 39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 -00 00 1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 -09 48 29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D -82 43 CC 21 30 4D 92 42 CA 21 DA 21 30 4D F2 CF -70 D0 76 D0 86 D0 1A 42 20 18 82 4A C8 21 2E 4E -82 4E C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 -FE FF 0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A -0A 93 F0 23 3E 4F 3D 41 30 4D 14 CD 09 50 57 52 -5F 53 54 41 54 45 85 12 7E D0 34 D8 E0 C8 09 52 -53 54 5F 53 54 41 54 45 92 42 0A 18 CA D0 F3 3F -BC D0 08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 -CA D0 30 4D CE D0 08 52 53 54 5F 48 45 52 45 00 -92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 -E3 37 0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 54 D1 FE FF 29 83 B9 40 02 C6 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 C6 B2 49 -FA C4 B2 49 02 C4 B2 49 20 C6 B2 49 EC FF B2 49 -0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 -B2 40 80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 -00 08 29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 -02 02 F2 D2 05 02 B2 D0 FF FE 26 02 B2 43 22 02 -B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B0 00 -82 01 B2 40 1E 00 84 01 82 43 88 01 F2 D0 06 00 -2B 02 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 1E C6 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C C9 94 C9 F0 C7 34 C4 24 D2 88 CA 34 C4 -3E D2 38 D2 26 D2 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 40 D2 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 2C C9 94 C9 -F0 C7 34 C4 5C D2 88 CA 34 C4 4C CC BA C7 2C C9 -88 CA 34 C4 4C CC 68 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 08 D2 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 BA CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C C9 88 CA -34 C4 B0 D2 A6 D2 21 53 3E 90 10 00 C6 2B 7F 2D -B2 D2 B2 41 C4 21 C1 3F 0D 12 84 12 4E CC E4 D1 -C2 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 08 D2 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 08 D2 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 90 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 90 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 90 D2 FA 23 -3C 50 10 00 B0 12 6C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 4E CC E4 D1 8E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 90 D2 E0 23 3C 50 80 00 B0 12 6C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -94 CB 60 C8 0A C4 2C 00 B8 D2 84 D3 CE D3 09 4B -2E 4E 0E DC A2 3F 8C CE 03 4D 4F 56 85 12 C4 D3 -00 40 D8 D3 05 4D 4F 56 2E 42 85 12 C4 D3 40 40 -00 00 03 41 44 44 85 12 C4 D3 00 50 F2 D3 05 41 -44 44 2E 42 85 12 C4 D3 40 50 FE D3 04 41 44 44 -43 00 85 12 C4 D3 00 60 0C D4 06 41 44 44 43 2E -42 00 85 12 C4 D3 40 60 B2 D3 04 53 55 42 43 00 -85 12 C4 D3 00 70 2A D4 06 53 55 42 43 2E 42 00 -85 12 C4 D3 40 70 38 D4 03 53 55 42 85 12 C4 D3 -00 80 48 D4 05 53 55 42 2E 42 85 12 C4 D3 40 80 -62 CE 03 43 4D 50 85 12 C4 D3 00 90 62 D4 05 43 -4D 50 2E 42 85 12 C4 D3 40 90 4C CE 04 44 41 44 -44 00 85 12 C4 D3 00 A0 7C D4 06 44 41 44 44 2E -42 00 85 12 C4 D3 40 A0 6E D4 03 42 49 54 85 12 -C4 D3 00 B0 9A D4 05 42 49 54 2E 42 85 12 C4 D3 -40 B0 A6 D4 03 42 49 43 85 12 C4 D3 00 C0 B4 D4 -05 42 49 43 2E 42 85 12 C4 D3 40 C0 C0 D4 03 42 -49 53 85 12 C4 D3 00 D0 CE D4 05 42 49 53 2E 42 -85 12 C4 D3 40 D0 00 00 03 58 4F 52 85 12 C4 D3 -00 E0 E8 D4 05 58 4F 52 2E 42 85 12 C4 D3 40 E0 -1A D4 03 41 4E 44 85 12 C4 D3 00 F0 02 D5 05 41 -4E 44 2E 42 85 12 C4 D3 40 F0 4E CC B8 D2 20 D5 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -54 D4 03 52 52 43 85 12 1A D5 00 10 32 D5 05 52 -52 43 2E 42 85 12 1A D5 40 10 3E D5 04 53 57 50 -42 00 85 12 1A D5 80 10 4C D5 03 52 52 41 85 12 -1A D5 00 11 5A D5 05 52 52 41 2E 42 85 12 1A D5 -40 11 66 D5 03 53 58 54 85 12 1A D5 80 11 00 00 -04 50 55 53 48 00 85 12 1A D5 00 12 80 D5 06 50 -55 53 48 2E 42 00 85 12 1A D5 40 12 DA D4 04 43 -41 4C 4C 00 85 12 1A D5 80 12 1A 53 0E 4A 0D 12 -84 12 D6 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 74 D5 03 53 3E 3D 86 12 00 38 -C8 D5 02 53 3C 00 86 12 00 34 8E D5 03 30 3E 3D -86 12 00 30 DC D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C F0 D5 03 55 3E 3D 86 12 -00 28 E6 D5 03 30 3C 3E 86 12 00 24 04 D6 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D FA D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -8A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 9E D5 -05 42 45 47 49 4E 30 40 28 C4 2E D6 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D 0E D5 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 1C D6 BA C7 60 C8 D2 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 B0 D6 34 D6 60 C8 E0 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 70 D6 03 42 57 31 85 12 DE D6 -00 00 F8 D6 03 42 57 32 85 12 DE D6 00 00 04 D7 -03 42 57 33 85 12 DE D6 00 00 1C D7 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 1A D7 00 00 3C D7 03 46 57 32 85 12 1A D7 -00 00 48 D7 03 46 57 33 85 12 1A D7 00 00 54 D7 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 CC CC 28 CC 60 C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 4E CC E4 D1 9E D7 92 53 -C4 21 3E 40 2C 00 84 12 2C C9 88 CA 34 C4 4C CC -7A D3 B4 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -CC D6 04 52 52 43 4D 00 85 12 98 D7 50 00 E2 D7 -04 52 52 41 4D 00 85 12 98 D7 50 01 F0 D7 04 52 -4C 41 4D 00 85 12 98 D7 50 02 FE D7 04 52 52 55 -4D 00 85 12 98 D7 50 03 0E D6 05 50 55 53 48 4D -85 12 98 D7 00 15 1A D8 04 50 4F 50 4D 00 85 12 -98 D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 94 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 54 D1 -q diff --git a/binaries/MSP_EXP430FR4133_8MHz_115200.txt b/binaries/MSP_EXP430FR4133_8MHz_115200.txt new file mode 100644 index 0000000..3cf90d5 --- /dev/null +++ b/binaries/MSP_EXP430FR4133_8MHz_115200.txt @@ -0,0 +1,328 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A0 59 +C2 C6 7E C5 84 C5 54 C5 32 C7 5A D7 12 D0 CC CF +CC CF A8 C6 66 C7 2E C7 3C 21 E0 20 86 C9 B6 C4 +C4 C4 A2 C8 20 00 0A 00 00 20 7E C5 84 C5 54 C5 +32 C7 5A D7 12 D0 CC CF CC CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FC 3C 0E 93 3E 4F +91 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A6 C6 B2 49 +64 C7 B2 49 2C C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 86 D0 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 32 C7 92 C3 1C 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 1C 05 F3 23 +B0 12 D0 C4 AC C8 AC C4 52 C5 74 C7 1E C4 04 1B +5B 37 6D 00 96 C7 96 C7 1E C4 04 1B 5B 30 6D 00 +96 C7 1C CD B0 12 7E C5 B2 40 81 00 00 05 92 42 +02 18 06 05 92 42 04 18 08 05 F2 D0 03 00 0A 02 +92 C3 00 05 92 D3 1A 05 92 C3 30 01 30 41 92 B3 +0A 05 FD 23 30 41 92 12 3E 18 84 12 74 C7 1E C4 +07 0D 0A 1B 5B 37 6D 23 96 C7 FA C9 1E C4 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 96 C7 0A C4 40 FF 32 C4 +C2 C8 C6 C9 1E C4 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C4 46 C5 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C5 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B2 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A CC 01 3F 40 80 20 31 40 E0 20 +B2 D3 06 02 B2 D3 02 02 F2 D2 05 02 B2 D0 FF FE +26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 +66 02 B2 43 62 02 B2 40 00 A5 60 01 82 43 88 01 +F2 D0 06 00 2B 02 F2 C3 82 01 F2 D0 06 00 82 01 +B2 40 F4 00 84 01 39 40 40 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 39 40 00 08 29 83 89 43 00 20 +FC 23 19 42 5E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 C4 86 C5 00 00 0C 41 43 43 +45 50 54 00 30 40 A8 C6 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 06 C7 3C 40 12 C7 5D 15 +9F 3E 21 52 3A 17 58 42 0C 05 48 9B 09 20 A2 B3 +1C 05 FD 27 B2 40 13 00 0E 05 F2 D2 03 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 +C2 48 0E 05 30 4D 08 C7 2D 83 92 B3 1C 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 1C 05 FD 27 58 42 0C 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 2E C7 30 12 +44 C7 A2 B3 1C 05 FD 27 B2 40 11 00 0E 05 F2 C2 +03 02 30 41 2F 83 8F 4E 00 00 92 B3 1C 05 FD 27 +B0 12 CE C6 1E 42 0C 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 66 C7 08 4E 3E 4F C7 3F 5C C7 08 45 +43 48 4F 00 B2 40 C2 48 00 C7 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 00 C7 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 A6 C7 29 4F 8F 4E +00 00 7E 49 DE 3F A8 C7 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 75 22 F9 98 00 00 72 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 69 22 +9B 24 26 C7 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A C4 00 00 C6 C8 B8 C7 0A CA FE CC B0 C4 34 C8 +14 C4 06 5B 54 48 45 4E 5D 00 BC C7 12 C8 D8 C7 +F6 C7 14 C4 06 5B 45 4C 53 45 5D 00 BC C7 24 C8 +D8 C7 F4 C7 1E C4 04 5B 49 46 5D 00 BC C7 F6 C7 +B2 C4 F4 C7 1E C4 05 0D 6B 6F 20 0A 96 C7 9A C4 +84 C4 B2 C4 F6 C7 E4 C7 0D 5B 54 48 45 4E 5D 00 +30 4D 48 C8 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 54 C8 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 B8 C7 0A CA 72 CA 50 CC 86 C9 64 C8 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 B8 C7 +0A CA 72 CA 96 C8 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 9C C6 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C5 +05 53 22 00 82 43 C0 21 0D 12 84 12 0A C4 1E C4 +AE CC 0A C4 22 00 0A CA 0A C9 B2 40 20 00 C0 21 +1A 53 1A B3 82 6A C8 21 3E 4F 3D 41 30 4D 7E C7 +05 2E 22 00 0D 12 84 12 F4 C8 0A C4 96 C7 AE CC +86 C9 00 00 04 3C 23 00 B2 40 B2 21 B2 21 30 4D +F0 C8 02 23 1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 21 18 42 B2 21 C8 4A 00 00 30 4D +42 C9 04 23 53 00 0D 12 84 12 44 C9 7E C9 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 72 C9 04 23 3E 00 +9F 42 B2 21 00 00 3E 40 B2 21 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 8C C9 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +6E C7 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 38 C9 B8 C7 A6 C9 76 C9 A2 C8 B4 C9 +90 C9 96 C7 86 C9 20 C9 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 21 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 21 F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 21 82 48 C6 21 1E 42 +C8 21 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D C2 C9 06 55 4D 2A 2C 4F 0B 43 09 43 08 43 +1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A +F8 2B 8F 49 00 00 0E 48 30 4D F8 C9 0E 3E 4E 55 +4D 42 45 52 1A 42 BE 21 2C 4F 0B 4E 68 4C 78 80 +3A 00 03 28 78 80 07 00 21 28 78 50 0A 00 08 9A +22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 22 CB +D4 3F 24 CB 81 49 02 00 1C 4F 04 00 1E 41 04 00 +3D 40 36 CB CA 3F 38 CB 39 51 3E 61 8F 49 04 00 +8F 4E 02 00 3A 17 1C 53 1B 83 D8 23 8F 4C 00 00 +0E 4B 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 8F 43 +04 00 8F 43 02 00 1A 42 BE 21 0C 4E 0E 43 1E 15 +3D 40 B8 CB 7B 4C 68 4C 78 80 2D 00 16 24 BE 2F +2A 43 78 52 14 24 3A 52 68 53 11 24 3A 40 10 00 +58 93 0D 24 68 92 40 20 3E 90 03 00 3D 20 FC 9C +01 00 6C 4C 8F 4C 04 00 37 3C B1 43 02 00 1B 83 +FC 9C 00 00 E0 23 A2 27 BA CB 2E 24 2D 83 68 4C +78 90 5F 00 C0 27 32 B0 00 02 26 20 32 D0 00 02 +78 80 2E 00 B8 27 68 53 1F 20 09 43 8F 49 02 00 +5B 83 09 4B 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9A 08 2C 8F 49 00 00 +0E 4A 2C 15 B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4B 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 34 C9 03 5C 92 42 C2 21 C6 21 30 4D +0D 12 84 12 84 C4 B8 C7 0A CA B0 C4 88 CD 72 CA +72 CC 0A 4E 3E 4F 3D 40 8C CC 6C 27 3D 40 66 CC +1A E2 BC 21 14 24 0E 12 3E 4F 30 41 8E CC 3E 4F +3D 40 66 CC 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 64 CE 2A 3C 56 CC 02 2C A2 53 +C8 21 1A 42 C8 21 8A 4E FE FF 3E 4F 30 4D AC CC +0F 4C 49 54 45 52 41 4C 82 93 BC 21 0D 24 09 4E +1A 42 C8 21 A2 52 C8 21 BA 40 0A C4 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D AE C9 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D D4 C8 0A 41 +4C 4C 4F 54 82 5E C8 21 3E 4F 30 4D 3F 40 80 20 +0E 43 84 12 1E C4 02 0D 0A 00 96 C7 94 C4 60 CC +B4 C8 DE C8 1E C4 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C5 32 C4 0A C4 40 FF E6 C8 1E C4 09 46 +52 41 4D 20 66 75 6C 6C 08 C5 B2 C4 24 CD 0E CD +0D 41 42 4F 52 54 22 00 0D 12 84 12 F4 C8 0A C4 +08 C5 AE CC 86 C9 04 CA 02 27 0D 12 84 12 B8 C7 +0A CA 72 CA B0 C4 8A CD 18 C9 96 CC 7E C8 07 5B +27 5D 0D 12 84 12 7A CD 0A C4 0A C4 AE CC AE CC +86 C9 8E CD 03 5B 82 43 BC 21 30 4D 00 00 02 5D +B2 43 BC 21 30 4D CC C8 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 B8 C7 0A CA 72 CA B0 C4 8A CD +DE C8 AC C4 E2 CD 0A C4 0A C4 AE CC AE CC 0A C4 +AE CC AE CC 86 C9 00 00 02 3A 30 12 38 CE 92 B3 +C8 21 A2 63 C8 21 0D 12 84 12 B8 C7 0A CA 00 CE +3D 41 5A D3 5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 21 82 49 B6 21 82 4A B8 21 82 4F BA 21 +2A 52 82 4A C8 21 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 21 30 4D 82 9F BA 21 66 25 +84 12 1E C4 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C5 A4 CD 03 3B 82 93 BC 21 F4 26 +0D 12 84 12 0A C4 86 C9 AE CC 4A CE A6 CD 86 C9 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 21 +D8 D3 00 00 30 4D F8 CC 0C 43 52 45 41 54 45 00 +B0 12 EE CD BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +90 C7 0A 44 4F 45 53 3E 1A 42 B8 21 BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D E8 CD 0E 3A 4E 4F +4E 41 4D 45 30 12 38 CE 2F 83 8F 4E 00 00 1A 42 +C8 21 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +82 CE 05 49 53 00 0D 12 82 93 BC 21 08 20 84 12 +7A CD 04 CF 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +92 CD 0A C4 06 CF AE CC 86 C9 98 CE 08 43 4F 44 +45 00 B0 12 EE CD A2 82 C8 21 61 3C A0 C9 0E 48 +44 4E 43 4F 44 45 B2 40 F2 CF CC 21 F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 4A CE 50 CF +3D 41 92 42 D0 21 CC 21 5D 3C 1C CF 0E 43 4F 44 +45 4E 4E 4D 30 12 26 CF B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 21 BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 21 1A 42 C8 21 EF 3F 2E CF +0B 48 49 32 4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A +FE FF 82 43 BC 21 B9 3F BA CF B2 40 CC CF D0 21 +82 4E CE 21 30 40 18 C9 85 12 B8 CF B8 CD 60 CD +4A D0 5C CF B2 CE C4 CA 6C CA 78 CD A0 CF F2 CE +CC CE 68 CE C0 CC D4 D0 EC CA 00 00 00 00 85 12 +B8 CF 4E D7 D2 D5 32 D7 FA D4 56 D5 A4 D5 80 D6 +8C D6 1C D4 40 D5 00 00 00 00 8E CF 0C D3 00 00 +A8 D6 EC CF B2 40 CC CF CE 21 82 43 D0 21 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 21 3A 40 +42 18 B0 12 20 D0 30 4D 32 D0 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 21 B0 12 20 D0 +1A 42 CA 21 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 C6 FE FF 29 83 B9 40 +F2 C5 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +EC FF 3B 40 10 00 3A 40 3A 18 B0 12 24 D0 82 43 +4A 18 C7 3F C6 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F AE CD 0C 4D 41 52 4B 45 52 00 12 12 C6 21 +0D 12 84 12 B8 C7 0A CA 72 CA AC C4 F2 D0 AC C8 +86 CC F4 D0 3E 4F 3D 41 B2 41 C6 21 B0 12 EE CD +BA 40 85 12 FC FF BA 40 C4 D0 FE FF 28 83 8A 48 +00 00 BA 40 82 C4 02 00 A2 52 C8 21 18 42 B4 21 +19 42 B6 21 A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 21 84 12 0A CA 72 CA AC C4 5E D1 3E D1 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +C4 D0 00 00 01 20 3E 52 2E 83 21 53 30 41 54 CB +AC C4 66 D1 5A D1 68 D1 B2 41 C6 21 30 41 92 83 +C6 21 3E 40 28 00 0A 4E 3D 15 B0 12 2E D1 15 20 +3E 40 2B 00 B0 12 2E D1 06 20 3E 40 2D 00 B0 12 +2E D1 92 83 C6 21 0E 12 1E 41 02 00 84 12 0A CA +54 CB AC C4 8A CD A8 D1 3E 51 3A 17 30 41 B0 12 +6E D1 19 42 C8 21 89 4E 00 00 A2 53 C8 21 3E 40 +29 00 92 53 C6 21 1A 42 C6 21 3D 15 84 12 0A CA +54 CB AC C4 E0 D1 D8 D1 3E 90 10 00 E6 2B 7C 2D +E2 D1 A2 41 C6 21 E1 3F 03 20 B0 12 C6 D1 43 3C +7A 90 23 00 24 20 B0 12 76 D1 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 21 A2 53 C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 76 D1 F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 C2 D1 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 C6 D1 92 92 C2 21 C6 21 +02 24 92 53 C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 AE D1 F2 3F 03 20 B0 12 C6 D1 F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +AE D1 EA 3F 0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 +20 00 19 42 C6 21 19 52 C4 21 7A 99 FE 27 5A 49 +FF FF 19 82 C4 21 82 49 C6 21 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C4 00 13 +AE CC 86 C9 0A C4 2C 00 A4 D2 E8 D1 B8 C7 AE D2 +86 D2 F4 D2 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 E4 D2 00 40 00 D3 0A 4D 4F 56 +2E 42 85 12 E4 D2 40 40 00 00 06 41 44 44 85 12 +E4 D2 00 50 1A D3 0A 41 44 44 2E 42 85 12 E4 D2 +40 50 26 D3 08 41 44 44 43 00 85 12 E4 D2 00 60 +34 D3 0C 41 44 44 43 2E 42 00 85 12 E4 D2 40 60 +6C CF 08 53 55 42 43 00 85 12 E4 D2 00 70 52 D3 +0C 53 55 42 43 2E 42 00 85 12 E4 D2 40 70 60 D3 +06 53 55 42 85 12 E4 D2 00 80 70 D3 0A 53 55 42 +2E 42 85 12 E4 D2 40 80 7C D3 06 43 4D 50 85 12 +E4 D2 00 90 8A D3 0A 43 4D 50 2E 42 85 12 E4 D2 +40 90 00 00 08 44 41 44 44 00 85 12 E4 D2 00 A0 +A4 D3 0C 44 41 44 44 2E 42 00 85 12 E4 D2 40 A0 +D2 D2 06 42 49 54 85 12 E4 D2 00 B0 C2 D3 0A 42 +49 54 2E 42 85 12 E4 D2 40 B0 CE D3 06 42 49 43 +85 12 E4 D2 00 C0 DC D3 0A 42 49 43 2E 42 85 12 +E4 D2 40 C0 E8 D3 06 42 49 53 85 12 E4 D2 00 D0 +F6 D3 0A 42 49 53 2E 42 85 12 E4 D2 40 D0 00 00 +06 58 4F 52 85 12 E4 D2 00 E0 10 D4 0A 58 4F 52 +2E 42 85 12 E4 D2 40 E0 42 D3 06 41 4E 44 85 12 +E4 D2 00 F0 2A D4 0A 41 4E 44 2E 42 85 12 E4 D2 +40 F0 B8 C7 A4 D2 E8 D1 4A D4 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F 02 D4 06 52 52 43 +85 12 42 D4 00 10 5C D4 0A 52 52 43 2E 42 85 12 +42 D4 40 10 96 D3 08 53 57 50 42 00 85 12 42 D4 +80 10 68 D4 06 52 52 41 85 12 42 D4 00 11 84 D4 +0A 52 52 41 2E 42 85 12 42 D4 40 11 76 D4 06 53 +58 54 85 12 42 D4 80 11 00 00 08 50 55 53 48 00 +85 12 42 D4 00 12 AA D4 0C 50 55 53 48 2E 42 00 +85 12 42 D4 40 12 9E D4 08 43 41 4C 4C 00 85 12 +42 D4 80 12 1A 53 0E 4A 84 12 FA C9 1E C4 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C5 C8 D4 +06 53 3E 3D 86 12 00 38 F0 D4 04 53 3C 00 86 12 +00 34 B8 D4 06 30 3E 3D 86 12 00 30 04 D5 04 30 +3C 00 86 12 00 30 40 CF 04 55 3C 00 86 12 00 2C +18 D5 06 55 3E 3D 86 12 00 28 0E D5 06 30 3C 3E +86 12 00 24 2C D5 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 +0E 4A 30 4D B2 D3 08 54 48 45 4E 00 1A 42 C8 21 +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D 22 D5 08 45 4C 53 45 00 +1A 42 C8 21 BA 40 00 3C 00 00 A2 53 C8 21 2F 83 +8F 4A 00 00 E3 3F 90 D4 0A 42 45 47 49 4E 30 40 +32 C4 7A D5 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 21 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 21 30 4D +36 D4 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 44 D5 A0 C8 +86 C9 98 D5 0C 52 45 50 45 41 54 00 0D 12 84 12 +D8 D5 5C D5 86 C9 08 D6 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 21 CB 2F 98 42 C8 21 00 00 30 4D F4 D5 +06 42 57 31 85 12 06 D6 00 00 20 D6 06 42 57 32 +85 12 06 D6 00 00 2C D6 06 42 57 33 85 12 06 D6 +00 00 44 D6 3D 41 1A 42 C8 21 28 4E 8E 43 00 00 +B2 92 C6 21 86 2B BA 4F 00 00 A2 53 C8 21 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 42 D6 +00 00 68 D6 06 46 57 32 85 12 42 D6 00 00 74 D6 +06 46 57 33 85 12 42 D6 00 00 E2 D5 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +7A CD 86 CC 86 C9 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F AE D2 0A C4 2C 00 0A CA 54 CB AC C4 +8A CD B8 C7 A4 D2 86 D2 DA D6 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 38 D6 08 52 52 43 4D 00 85 12 +C4 D6 50 00 08 D7 08 52 52 41 4D 00 85 12 C4 D6 +50 01 16 D7 08 52 4C 41 4D 00 85 12 C4 D6 50 02 +24 D7 08 52 52 55 4D 00 85 12 C4 D6 50 03 36 D5 +0A 50 55 53 48 4D 85 12 C4 D6 00 15 40 D7 08 50 +4F 50 4D 00 85 12 C4 D6 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 C2 C6 F2 C5 +F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 F2 C5 06 C6 +q diff --git a/binaries/MSP_EXP430FR4133_8MHz_I2C.txt b/binaries/MSP_EXP430FR4133_8MHz_I2C.txt index 8839cdb..6c97e6f 100644 --- a/binaries/MSP_EXP430FR4133_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR4133_8MHz_I2C.txt @@ -1,338 +1,326 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF 1E D8 2A D0 34 01 -10 00 41 87 B6 C5 AA C4 B8 C5 8C C5 82 C6 1E D8 -2A D0 70 C6 80 C7 FE C6 DA C6 3C 21 4E C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A0 43 +BC C6 56 C5 56 C5 58 C5 44 C5 36 D7 EE CF A8 CF +A8 CF AA C6 2E C7 06 C7 3C 21 E0 20 62 C9 B6 C4 +C4 C4 7E C8 20 00 0A 00 00 20 56 C5 56 C5 58 C5 +44 C5 36 D7 EE CF A8 CF A8 CF 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C400 -B0 12 B8 C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 6E C6 B2 49 7E C7 B2 49 FC C6 B2 49 D8 C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 F6 D0 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C5 0E 12 B0 12 -F8 C4 0A C4 DE 21 CE C7 16 C7 EE C4 34 C4 8A C5 -14 C4 05 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 -C4 C8 96 C7 34 C4 7E C5 14 C4 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C7 8E C8 4A C7 -14 C4 04 1B 5B 30 6D 00 4A C7 50 CC 2E 93 13 28 -B2 D0 C0 07 40 05 18 42 02 18 08 11 38 D0 00 04 -82 48 54 05 F2 D0 0C 00 4A 02 92 C3 40 05 A2 D2 -6A 05 92 C3 30 01 30 41 48 43 A2 B3 6C 05 FD 27 -C2 48 4E 05 A2 B2 6C 05 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C5 04 57 41 52 4D 00 B0 12 -8C C5 78 40 03 00 B0 12 BA C5 84 12 14 C4 07 0D -0A 1B 5B 37 6D 40 4A C7 0A C4 02 18 CE C7 C4 C8 -0A C4 23 00 FA C6 C4 C8 14 C4 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C7 0A C4 40 FF 28 C4 C2 C7 8E C8 -14 C4 0A 62 79 74 65 73 20 66 72 65 65 00 3A C4 -7E C5 00 00 06 41 43 43 45 50 54 00 30 40 70 C6 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 05 B2 B0 10 00 40 05 B8 22 -3A 17 92 B3 6C 05 FD 27 58 42 4C 05 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C5 82 93 DE 21 02 24 92 53 DE 21 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C6 2F 83 8F 4E 00 00 -58 43 B0 12 BA C5 92 B3 6C 05 FD 27 1E 42 4C 05 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C6 08 4E -3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D F4 C6 -04 45 43 48 4F 00 B2 40 C2 48 08 C7 82 43 DE 21 -38 40 05 00 B0 12 BA C5 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C7 92 43 DE 21 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C7 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C6 68 C7 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C5 02 43 52 00 30 40 80 C7 -0D 12 84 12 14 C4 02 0D 0A 00 4A C7 4E C8 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C6 01 40 2E 4E -30 4D CC C7 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 21 B2 21 30 4D 78 C7 01 23 1B 42 DC 21 2C 4F -2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 B2 21 -C8 4A 00 00 30 4D 08 C8 02 23 53 00 0D 12 84 12 -0A C8 44 C8 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C8 02 23 3E 00 9F 42 B2 21 00 00 3E 40 -B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C7 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C7 -3C C8 EE C4 7C C8 58 C8 4A C7 3C CC FA C6 4E C8 -2C C7 01 2E 0E 93 E3 37 38 43 E2 3F 76 C8 82 53 -22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 82 CB -0A C4 22 00 1A C9 E8 C8 B2 40 20 00 B4 21 6E 4E -1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D C2 C8 -82 2E 22 00 0D 12 84 12 D2 C8 0A C4 4A C7 82 CB -4E C8 F8 C5 04 57 4F 52 44 00 3C 40 C0 21 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 1E 42 -C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 21 -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 30 4D -8A C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 -0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B -8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 4D 42 -45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 30 00 -78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 1F 28 -08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A 3D 40 -44 CA D2 3F 46 CA 81 49 02 00 1C 4F 04 00 1E 41 -04 00 3D 40 58 CA C8 3F 5A CA 39 51 3E 61 8F 49 -04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 8F 4C -00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 0C 43 -2D 15 3D 40 D8 CA 0A 4B 3F 82 8F 4E 06 00 8F 43 -04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 00 00 -06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C 68 4C -78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C 2A 43 -78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 78 53 -35 20 1C 53 1B 83 EB 3F DA CA 30 24 2D 83 78 90 -28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 78 90 -F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 02 00 -5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 0A 00 -05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A 08 2C -8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 E6 3F -9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 0E 4C -82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 0E F3 -30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 -09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 -8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 00 00 -01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 3E 4F -30 4D 80 CB 87 4C 49 54 45 52 41 4C 82 93 BE 21 -0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 0A C4 -00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 -03 24 8A 4E 02 00 EE 3F 30 4D 54 C8 05 43 4F 55 -4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF 30 4D -68 C8 09 49 4E 54 45 52 50 52 45 54 0D 12 84 12 -AC C4 3C CC 1A C9 F8 CB 7F 26 3D 40 00 CC C1 3E -02 CC 0A 4E 3E 4F 3D 40 1C CC 35 27 3D 40 F2 CB -1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 1E CC 3E 4F -3D 40 F2 CB BB 23 DE 53 00 00 68 4E 08 5E F8 40 -3F 00 00 00 3D 40 BE CD CC 3F 26 CC 86 12 20 00 -D4 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F 30 4D -3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 00 20 -82 43 BE 21 84 12 7C C7 BC C4 EC CB B2 C7 E4 C7 -14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 21 00 -2A C5 0A C4 40 FF 28 C4 EC C7 14 C4 0A 46 52 41 -4D 20 66 75 6C 6C 21 00 2A C5 3A C4 66 CC 42 CC -86 41 42 4F 52 54 22 00 0D 12 84 12 D2 C8 0A C4 -2A C5 82 CB 4E C8 7C C9 01 27 0D 12 84 12 3C CC -1A C9 82 C9 34 C4 3A CC 4E C8 00 00 83 5B 27 5D -0D 12 84 12 BA CC 0A C4 0A C4 82 CB 82 CB 4E C8 -CC CC 81 5B 82 43 BE 21 30 4D FA C7 01 5D B2 43 -BE 21 30 4D EC CC 81 5C 92 42 C0 21 C4 21 30 4D -00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 -3C CC 1A C9 82 C9 96 C7 34 C4 3A CC E4 C7 34 C4 -2E CD 0A C4 0A C4 82 CB 82 CB 0A C4 82 CB 82 CB -4E C8 E2 CC 01 3A 30 12 7E CD 92 B3 C6 21 A2 63 -C6 21 0D 12 84 12 3C CC 1A C9 4C CD 3D 41 08 4E -7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E 3E F0 -1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 82 4A -BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 BA 40 -0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 30 4D -82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 A8 49 -FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 0F 73 -74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 36 C5 -34 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 0A C4 -4E C8 82 CB 90 CD E4 CC 4E C8 E2 CB 09 49 4D 4D -45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 00 00 -30 4D CC CB 06 43 52 45 41 54 45 00 B0 12 3A CD -BA 40 86 12 FC FF 8A 4A FE FF C9 3F F4 CD 04 43 -4F 44 45 00 B0 12 3A CD A2 82 C6 21 0D 12 84 12 -2C D0 06 D0 4E C8 DC CD 07 48 44 4E 43 4F 44 45 -B2 40 0A D0 DA 21 EE 3F 00 00 07 45 4E 44 43 4F -44 45 0D 12 84 12 90 CD 46 D0 64 D0 4E C8 00 00 -05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 00 00 -BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 0D 12 -84 12 46 D0 64 D0 4E C8 00 00 05 4C 4F 32 48 49 -A2 83 C6 21 1A 42 C6 21 EB 3F 28 CE 85 48 49 32 -4C 4F 0D 12 84 12 28 C4 D4 CF 82 CB E4 CC 1C CE -4E C8 C2 CD 86 5B 54 48 45 4E 5D 00 30 4D 0C 4E -38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 06 30 -1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D 3E 4F -30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 F7 3F -A4 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 -00 00 C6 C7 3C CC 1A C9 D2 CB 8E C7 34 C4 3C CF -9C C7 14 C4 06 5B 54 48 45 4E 5D 00 AE CE 16 CF -D2 CE F4 CE 4E C8 9C C7 14 C4 06 5B 45 4C 53 45 -5D 00 AE CE 2C CF D2 CE F2 CE 4E C8 14 C4 04 5B -49 46 5D 00 AE CE F4 CE 3A C4 F2 CE 70 C7 14 C4 -05 0D 0A 6B 6F 20 4A C7 BC C4 AC C4 3A C4 F4 CE -E2 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D -2F 53 30 4D 52 CF 89 5B 44 45 46 49 4E 45 44 5D -0D 12 84 12 3C CC 1A C9 82 C9 60 CF 4E C8 66 CF -8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 -70 CF DE C7 4E C8 98 CF B2 4E 0A 18 2E 53 BE 12 -3E 4F 3D 41 90 3C 94 CB 06 4D 41 52 4B 45 52 00 -B0 12 3A CD BA 40 85 12 FC FF BA 40 96 CF FE FF -28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 06 00 -C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 D6 C7 4E C8 -85 12 D8 CF A0 CC 0E CE 10 C7 B8 CC 8C CE D2 C6 -A8 CF 00 C9 D0 D0 E4 D0 E2 C9 14 C9 00 00 80 CF -F6 CC 0A CA 00 00 85 12 D8 CF 94 D6 FA D6 3C D6 -4A D7 02 D6 00 00 CE D3 00 00 12 D8 F6 D7 66 D6 -A4 D6 DE D4 00 00 00 00 66 D7 04 D0 3A 40 0C 00 -39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 00 00 -1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 09 48 -29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D 82 43 -CC 21 30 4D 92 42 CA 21 DA 21 30 4D E0 CF 5E D0 -64 D0 74 D0 1A 42 20 18 82 4A C8 21 2E 4E 82 4E -C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF -0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 -F0 23 3E 4F 3D 41 30 4D 02 CD 09 50 57 52 5F 53 -54 41 54 45 85 12 6C D0 1E D8 CE C8 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 B8 D0 F3 3F AA D0 -08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 B8 D0 -30 4D BC D0 08 52 53 54 5F 48 45 52 45 00 92 42 -C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 E3 37 -0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 42 D1 FE FF 29 83 B9 40 E2 C5 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 C5 B2 49 FA C4 -B2 49 02 C4 B2 49 00 C6 B2 49 EA FF B2 49 0A 18 -C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 -80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 00 08 -29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 02 02 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 21 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C4 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 21 B2 4F C4 21 82 43 C6 21 +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 21 00 00 AF 4F FE FF 2F 83 FD 3C 0E 93 3E 4F +7F 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A8 C6 B2 49 +2C C7 B2 49 04 C7 B2 49 A0 C4 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 21 B2 49 BE 21 B2 49 00 20 +82 43 BC 21 30 40 62 D0 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C5 B0 12 D0 C4 88 C8 AC C4 +42 C5 46 C7 1E C4 05 1B 5B 37 6D 40 72 C7 0A C4 +02 18 AA C8 D6 C9 72 C7 1E C4 04 1B 5B 30 6D 00 +72 C7 F8 CC 48 43 A2 B3 6C 05 FD 27 C2 48 4E 05 +A2 B2 6C 05 FD 27 30 41 B2 D0 C0 07 40 05 18 42 +02 18 08 11 38 D0 00 04 82 48 54 05 F2 D0 0C 00 +4A 02 92 C3 40 05 A2 D2 6A 05 92 C3 30 01 30 41 +92 12 3E 18 84 12 46 C7 1E C4 07 0D 0A 1B 5B 37 +6D 40 72 C7 0A C4 02 18 AA C8 D6 C9 0A C4 23 00 +2A C7 D6 C9 1E C4 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +72 C7 0A C4 40 FF 32 C4 9E C8 A2 C9 1E C4 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C4 36 C5 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C5 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B2 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A CC 01 +31 40 E0 20 3F 40 80 20 B2 D3 06 02 B2 D3 02 02 B2 D0 FF FE 26 02 B2 43 22 02 B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 B2 40 00 A5 60 01 -B2 40 FF 1E 80 01 B2 40 B6 00 82 01 B2 40 F4 00 -84 01 82 43 88 01 F2 D0 06 00 2B 02 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 1E 42 08 18 -82 43 08 18 1E D2 5E 01 B0 12 F8 C4 FE C5 38 40 -C0 21 0A 4E 39 48 2E 48 09 5E 1E 52 C4 21 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 21 -30 4D 1C 15 0E 12 12 12 C4 21 84 12 1A C9 82 C9 -DE C7 34 C4 0E D2 76 CA 34 C4 28 D2 22 D2 10 D2 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 2A D2 B2 41 C4 21 3E 41 -84 12 0A C4 2B 00 1A C9 82 C9 DE C7 34 C4 46 D2 -76 CA 34 C4 3A CC A8 C7 1A C9 76 CA 34 C4 3A CC -52 D2 3E 5F E7 3F 3E 40 28 00 B0 12 F2 D1 19 42 -C6 21 A2 53 C6 21 89 4E 00 00 3E 40 29 00 92 92 -C0 21 C4 21 02 20 30 40 A8 CD 1C 15 12 12 C4 21 -92 53 C4 21 84 12 1A C9 76 CA 34 C4 9A D2 90 D2 -21 53 3E 90 10 00 C6 2B 7F 2D 9C D2 B2 41 C4 21 -C1 3F 0D 12 84 12 3C CC CE D1 AC D2 0C 43 1B 42 -C6 21 A2 53 C6 21 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 21 B0 12 F2 D1 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 21 -A2 53 C6 21 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 21 B0 12 F2 D1 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 21 -B0 12 7A D2 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -7A D2 92 92 C0 21 C4 21 02 24 92 53 C4 21 8E 10 -0C 5E DA 3F B0 12 7A D2 FA 23 3C 50 10 00 B0 12 -56 D2 EF 3F 0C 43 1B 42 C6 21 A2 53 C6 21 0D 12 -84 12 3C CC CE D1 78 D3 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 7A D2 E0 23 -3C 50 80 00 B0 12 56 D2 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A C4 00 13 82 CB 4E C8 0A C4 -2C 00 A2 D2 6E D3 B8 D3 09 4B 2E 4E 0E DC A2 3F -7A CE 03 4D 4F 56 85 12 AE D3 00 40 C2 D3 05 4D -4F 56 2E 42 85 12 AE D3 40 40 00 00 03 41 44 44 -85 12 AE D3 00 50 DC D3 05 41 44 44 2E 42 85 12 -AE D3 40 50 E8 D3 04 41 44 44 43 00 85 12 AE D3 -00 60 F6 D3 06 41 44 44 43 2E 42 00 85 12 AE D3 -40 60 9C D3 04 53 55 42 43 00 85 12 AE D3 00 70 -14 D4 06 53 55 42 43 2E 42 00 85 12 AE D3 40 70 -22 D4 03 53 55 42 85 12 AE D3 00 80 32 D4 05 53 -55 42 2E 42 85 12 AE D3 40 80 50 CE 03 43 4D 50 -85 12 AE D3 00 90 4C D4 05 43 4D 50 2E 42 85 12 -AE D3 40 90 3A CE 04 44 41 44 44 00 85 12 AE D3 -00 A0 66 D4 06 44 41 44 44 2E 42 00 85 12 AE D3 -40 A0 58 D4 03 42 49 54 85 12 AE D3 00 B0 84 D4 -05 42 49 54 2E 42 85 12 AE D3 40 B0 90 D4 03 42 -49 43 85 12 AE D3 00 C0 9E D4 05 42 49 43 2E 42 -85 12 AE D3 40 C0 AA D4 03 42 49 53 85 12 AE D3 -00 D0 B8 D4 05 42 49 53 2E 42 85 12 AE D3 40 D0 -00 00 03 58 4F 52 85 12 AE D3 00 E0 D2 D4 05 58 -4F 52 2E 42 85 12 AE D3 40 E0 04 D4 03 41 4E 44 -85 12 AE D3 00 F0 EC D4 05 41 4E 44 2E 42 85 12 -AE D3 40 F0 3C CC A2 D2 0A D5 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 3E D4 03 52 52 43 -85 12 04 D5 00 10 1C D5 05 52 52 43 2E 42 85 12 -04 D5 40 10 28 D5 04 53 57 50 42 00 85 12 04 D5 -80 10 36 D5 03 52 52 41 85 12 04 D5 00 11 44 D5 -05 52 52 41 2E 42 85 12 04 D5 40 11 50 D5 03 53 -58 54 85 12 04 D5 80 11 00 00 04 50 55 53 48 00 -85 12 04 D5 00 12 6A D5 06 50 55 53 48 2E 42 00 -85 12 04 D5 40 12 C4 D4 04 43 41 4C 4C 00 85 12 -04 D5 80 12 1A 53 0E 4A 0D 12 84 12 C4 C8 14 C4 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C5 -5E D5 03 53 3E 3D 86 12 00 38 B2 D5 02 53 3C 00 -86 12 00 34 78 D5 03 30 3E 3D 86 12 00 30 C6 D5 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C DA D5 03 55 3E 3D 86 12 00 28 D0 D5 03 30 -3C 3E 86 12 00 24 EE D5 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 21 8A 4E 00 00 A2 53 -C6 21 0E 4A 30 4D E4 D5 04 54 48 45 4E 00 1A 42 -C6 21 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 74 D4 04 45 4C 53 -45 00 1A 42 C6 21 BA 40 00 3C 00 00 A2 53 C6 21 -2F 83 8F 4A 00 00 E3 3F 88 D5 05 42 45 47 49 4E -30 40 28 C4 18 D6 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 21 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 21 -30 4D F8 D4 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 06 D6 -A8 C7 4E C8 BC D5 06 52 45 50 45 41 54 00 0D 12 -84 12 9A D6 1E D6 4E C8 CA D6 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 21 CB 2F 98 42 C6 21 00 00 30 4D -5A D6 03 42 57 31 85 12 C8 D6 00 00 E2 D6 03 42 -57 32 85 12 C8 D6 00 00 EE D6 03 42 57 33 85 12 -C8 D6 00 00 06 D7 3D 41 1A 42 C6 21 28 4E B2 92 -C4 21 88 2B BA 4F 00 00 A2 53 C6 21 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 04 D7 00 00 -26 D7 03 46 57 32 85 12 04 D7 00 00 32 D7 03 46 -57 33 85 12 04 D7 00 00 3E D7 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 BA CC -16 CC 4E C8 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 3C CC CE D1 88 D7 92 53 C4 21 3E 40 2C 00 -84 12 1A C9 76 CA 34 C4 3A CC 64 D3 9E D7 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E B6 D6 04 52 52 43 -4D 00 85 12 82 D7 50 00 CC D7 04 52 52 41 4D 00 -85 12 82 D7 50 01 DA D7 04 52 4C 41 4D 00 85 12 -82 D7 50 02 E8 D7 04 52 52 55 4D 00 85 12 82 D7 -50 03 F8 D5 05 50 55 53 48 4D 85 12 82 D7 00 15 -04 D8 04 50 4F 50 4D 00 85 12 82 D7 00 17 +82 43 88 01 F2 D0 06 00 2B 02 F2 C3 82 01 F2 D0 +06 00 82 01 B2 40 F4 00 84 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 39 40 00 08 29 83 +89 43 00 20 FC 23 1E 42 08 18 82 43 08 18 3E F3 +02 20 1E 42 5E 01 B0 12 D0 C4 80 C5 00 00 0C 41 +43 43 45 50 54 00 30 40 AA C6 0A 4E 2E 4F 0A 5E +3B 40 0A 00 3C 40 20 00 3D 15 A2 3E 21 52 A2 C2 +6C 05 B2 B0 10 00 40 05 9B 22 3A 17 92 B3 6C 05 +FD 27 58 42 4C 05 48 9B 0E 24 48 9C 06 2C 78 92 +F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B +45 59 30 40 06 C7 58 43 B0 12 46 C5 2F 83 8F 4E +00 00 92 B3 6C 05 FD 27 1E 42 4C 05 B0 12 44 C5 +30 4D 00 00 08 45 4D 49 54 00 30 40 2E C7 08 4E +3E 4F A2 B3 6C 05 FD 27 C2 48 4E 05 30 4D 24 C7 +08 45 43 48 4F 00 B2 40 C2 48 38 C7 38 40 05 00 +B0 12 46 C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 38 C7 28 42 F3 3F 00 00 08 54 59 50 +45 00 0D 12 3D 40 82 C7 29 4F 8F 4E 00 00 7E 49 +D4 3F 84 C7 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 87 22 F9 98 00 00 84 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 7B 22 9B 24 FE C6 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C4 00 00 +A2 C8 94 C7 E6 C9 DA CC B0 C4 10 C8 14 C4 06 5B +54 48 45 4E 5D 00 98 C7 EE C7 B4 C7 D2 C7 14 C4 +06 5B 45 4C 53 45 5D 00 98 C7 00 C8 B4 C7 D0 C7 +1E C4 04 5B 49 46 5D 00 98 C7 D2 C7 B2 C4 D0 C7 +1E C4 05 0D 6B 6F 20 0A 72 C7 9A C4 84 C4 B2 C4 +D2 C7 C0 C7 0D 5B 54 48 45 4E 5D 00 30 4D 24 C8 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 30 C8 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 94 C7 +E6 C9 4E CA 2C CC 62 C9 40 C8 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 94 C7 E6 C9 4E CA +72 C8 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D 9E C6 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D E0 C5 05 53 22 00 +82 43 C0 21 0D 12 84 12 0A C4 1E C4 8A CC 0A C4 +22 00 E6 C9 E6 C8 B2 40 20 00 C0 21 1A 53 1A B3 +82 6A C8 21 3E 4F 3D 41 30 4D 58 C7 05 2E 22 00 +0D 12 84 12 D0 C8 0A C4 72 C7 8A CC 62 C9 00 00 +04 3C 23 00 B2 40 B2 21 B2 21 30 4D CC C8 02 23 +1B 42 BE 21 2C 4F 2F 83 B0 12 46 C4 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 21 18 42 B2 21 C8 4A 00 00 30 4D 1E C9 04 23 +53 00 0D 12 84 12 20 C9 5A C9 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 4E C9 04 23 3E 00 9F 42 B2 21 +00 00 3E 40 B2 21 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F 68 C9 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 40 C7 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +14 C9 94 C7 82 C9 52 C9 7E C8 90 C9 6C C9 72 C7 +62 C9 FC C8 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 21 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 21 F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 21 82 48 C6 21 1E 42 C8 21 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 21 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D 9E C9 +06 55 4D 2A 2C 4F 0B 43 09 43 08 43 1A 43 0E BA +02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A F8 2B 8F 49 +00 00 0E 48 30 4D D4 C9 0E 3E 4E 55 4D 42 45 52 +1A 42 BE 21 2C 4F 0B 4E 68 4C 78 80 3A 00 03 28 +78 80 07 00 21 28 78 50 0A 00 08 9A 22 C3 1C 2C +5D 15 1C 4F 02 00 0E 4A 3D 40 FE CA D4 3F 00 CB +81 49 02 00 1C 4F 04 00 1E 41 04 00 3D 40 12 CB +CA 3F 14 CB 39 51 3E 61 8F 49 04 00 8F 4E 02 00 +3A 17 1C 53 1B 83 D8 23 8F 4C 00 00 0E 4B 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 8F 43 04 00 8F 43 +02 00 1A 42 BE 21 0C 4E 0E 43 1E 15 3D 40 94 CB +7B 4C 68 4C 78 80 2D 00 16 24 BE 2F 2A 43 78 52 +14 24 3A 52 68 53 11 24 3A 40 10 00 58 93 0D 24 +68 92 40 20 3E 90 03 00 3D 20 FC 9C 01 00 6C 4C +8F 4C 04 00 37 3C B1 43 02 00 1B 83 FC 9C 00 00 +E0 23 A2 27 96 CB 2E 24 2D 83 68 4C 78 90 5F 00 +C0 27 32 B0 00 02 26 20 32 D0 00 02 78 80 2E 00 +B8 27 68 53 1F 20 09 43 8F 49 02 00 5B 83 09 4B +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9A 08 2C 8F 49 00 00 0E 4A 2C 15 +B0 12 3E C4 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4B 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +10 C9 03 5C 92 42 C2 21 C6 21 30 4D 0D 12 84 12 +84 C4 94 C7 E6 C9 B0 C4 64 CD 4E CA 4E CC 0A 4E +3E 4F 3D 40 68 CC 6C 27 3D 40 42 CC 1A E2 BC 21 +14 24 0E 12 3E 4F 30 41 6A CC 3E 4F 3D 40 42 CC +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 40 CE 2A 3C 32 CC 02 2C A2 53 C8 21 1A 42 +C8 21 8A 4E FE FF 3E 4F 30 4D 88 CC 0F 4C 49 54 +45 52 41 4C 82 93 BC 21 0D 24 09 4E 1A 42 C8 21 +A2 52 C8 21 BA 40 0A C4 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 8A C9 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D B0 C8 0A 41 4C 4C 4F 54 +82 5E C8 21 3E 4F 30 4D 3F 40 80 20 0E 43 84 12 +1E C4 02 0D 0A 00 72 C7 94 C4 3C CC 90 C8 BA C8 +1E C4 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C5 +32 C4 0A C4 40 FF C2 C8 1E C4 09 46 52 41 4D 20 +66 75 6C 6C 08 C5 B2 C4 00 CD EA CC 0D 41 42 4F +52 54 22 00 0D 12 84 12 D0 C8 0A C4 08 C5 8A CC +62 C9 E0 C9 02 27 0D 12 84 12 94 C7 E6 C9 4E CA +B0 C4 66 CD F4 C8 72 CC 5A C8 07 5B 27 5D 0D 12 +84 12 56 CD 0A C4 0A C4 8A CC 8A CC 62 C9 6A CD +03 5B 82 43 BC 21 30 4D 00 00 02 5D B2 43 BC 21 +30 4D A8 C8 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 94 C7 E6 C9 4E CA B0 C4 66 CD BA C8 AC C4 +BE CD 0A C4 0A C4 8A CC 8A CC 0A C4 8A CC 8A CC +62 C9 00 00 02 3A 30 12 14 CE 92 B3 C8 21 A2 63 +C8 21 0D 12 84 12 94 C7 E6 C9 DC CD 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 21 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 21 +82 49 B6 21 82 4A B8 21 82 4F BA 21 2A 52 82 4A +C8 21 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 21 30 4D 82 9F BA 21 66 25 84 12 1E C4 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 C5 80 CD 03 3B 82 93 BC 21 F4 26 0D 12 84 12 +0A C4 62 C9 8A CC 26 CE 82 CD 62 C9 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 21 D8 D3 00 00 +30 4D D4 CC 0C 43 52 45 41 54 45 00 B0 12 CA CD +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 6C C7 0A 44 +4F 45 53 3E 1A 42 B8 21 BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D C4 CD 0E 3A 4E 4F 4E 41 4D 45 +30 12 14 CE 2F 83 8F 4E 00 00 1A 42 C8 21 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 5E CE 05 49 +53 00 0D 12 82 93 BC 21 08 20 84 12 56 CD E0 CE +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 6E CD 0A C4 +E2 CE 8A CC 62 C9 74 CE 08 43 4F 44 45 00 B0 12 +CA CD A2 82 C8 21 61 3C 7C C9 0E 48 44 4E 43 4F +44 45 B2 40 CE CF CC 21 F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 26 CE 2C CF 3D 41 92 42 +D0 21 CC 21 5D 3C F8 CE 0E 43 4F 44 45 4E 4E 4D +30 12 02 CF B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 21 BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 21 B2 43 BC 21 E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 21 1A 42 C8 21 EF 3F 0A CF 0B 48 49 32 +4C 4F A2 53 C8 21 1A 42 C8 21 8A 4A FE FF 82 43 +BC 21 B9 3F 96 CF B2 40 A8 CF D0 21 82 4E CE 21 +30 40 F4 C8 85 12 94 CF 94 CD 3C CD 26 D0 38 CF +8E CE A0 CA 48 CA 54 CD 7C CF CE CE A8 CE 44 CE +9C CC B0 D0 C8 CA 00 00 00 00 85 12 94 CF 2A D7 +AE D5 0E D7 D6 D4 32 D5 80 D5 5C D6 68 D6 F8 D3 +1C D5 00 00 00 00 6A CF E8 D2 00 00 84 D6 C8 CF +B2 40 A8 CF CE 21 82 43 D0 21 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 21 3A 40 42 18 B0 12 +FC CF 30 4D 0E D0 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 21 B0 12 FC CF 1A 42 CA 21 +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E C6 FE FF 29 83 B9 40 FA C5 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 EA FF 3B 40 +10 00 3A 40 3A 18 B0 12 00 D0 82 43 4A 18 C7 3F +A2 D0 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 8A CD +0C 4D 41 52 4B 45 52 00 12 12 C6 21 0D 12 84 12 +94 C7 E6 C9 4E CA AC C4 CE D0 88 C8 62 CC D0 D0 +3E 4F 3D 41 B2 41 C6 21 B0 12 CA CD BA 40 85 12 +FC FF BA 40 A0 D0 FE FF 28 83 8A 48 00 00 BA 40 +82 C4 02 00 A2 52 C8 21 18 42 B4 21 19 42 B6 21 +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 21 84 12 +E6 C9 4E CA AC C4 3A D1 1A D1 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 A0 D0 00 00 +01 20 3E 52 2E 83 21 53 30 41 30 CB AC C4 42 D1 +36 D1 44 D1 B2 41 C6 21 30 41 92 83 C6 21 3E 40 +28 00 0A 4E 3D 15 B0 12 0A D1 15 20 3E 40 2B 00 +B0 12 0A D1 06 20 3E 40 2D 00 B0 12 0A D1 92 83 +C6 21 0E 12 1E 41 02 00 84 12 E6 C9 30 CB AC C4 +66 CD 84 D1 3E 51 3A 17 30 41 B0 12 4A D1 19 42 +C8 21 89 4E 00 00 A2 53 C8 21 3E 40 29 00 92 53 +C6 21 1A 42 C6 21 3D 15 84 12 E6 C9 30 CB AC C4 +BC D1 B4 D1 3E 90 10 00 E6 2B 7C 2D BE D1 A2 41 +C6 21 E1 3F 03 20 B0 12 A2 D1 43 3C 7A 90 23 00 +24 20 B0 12 52 D1 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 21 A2 53 +C8 21 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 52 D1 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 9E D1 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 A2 D1 92 92 C2 21 C6 21 02 24 92 53 +C6 21 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 8A D1 +F2 3F 03 20 B0 12 A2 D1 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 8A D1 EA 3F +0C 43 1B 42 C8 21 A2 53 C8 21 3A 40 20 00 19 42 +C6 21 19 52 C4 21 7A 99 FE 27 5A 49 FF FF 19 82 +C4 21 82 49 C6 21 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A C4 00 13 8A CC 62 C9 +0A C4 2C 00 80 D2 C4 D1 94 C7 8A D2 62 D2 D0 D2 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 C0 D2 00 40 DC D2 0A 4D 4F 56 2E 42 85 12 +C0 D2 40 40 00 00 06 41 44 44 85 12 C0 D2 00 50 +F6 D2 0A 41 44 44 2E 42 85 12 C0 D2 40 50 02 D3 +08 41 44 44 43 00 85 12 C0 D2 00 60 10 D3 0C 41 +44 44 43 2E 42 00 85 12 C0 D2 40 60 48 CF 08 53 +55 42 43 00 85 12 C0 D2 00 70 2E D3 0C 53 55 42 +43 2E 42 00 85 12 C0 D2 40 70 3C D3 06 53 55 42 +85 12 C0 D2 00 80 4C D3 0A 53 55 42 2E 42 85 12 +C0 D2 40 80 58 D3 06 43 4D 50 85 12 C0 D2 00 90 +66 D3 0A 43 4D 50 2E 42 85 12 C0 D2 40 90 00 00 +08 44 41 44 44 00 85 12 C0 D2 00 A0 80 D3 0C 44 +41 44 44 2E 42 00 85 12 C0 D2 40 A0 AE D2 06 42 +49 54 85 12 C0 D2 00 B0 9E D3 0A 42 49 54 2E 42 +85 12 C0 D2 40 B0 AA D3 06 42 49 43 85 12 C0 D2 +00 C0 B8 D3 0A 42 49 43 2E 42 85 12 C0 D2 40 C0 +C4 D3 06 42 49 53 85 12 C0 D2 00 D0 D2 D3 0A 42 +49 53 2E 42 85 12 C0 D2 40 D0 00 00 06 58 4F 52 +85 12 C0 D2 00 E0 EC D3 0A 58 4F 52 2E 42 85 12 +C0 D2 40 E0 1E D3 06 41 4E 44 85 12 C0 D2 00 F0 +06 D4 0A 41 4E 44 2E 42 85 12 C0 D2 40 F0 94 C7 +80 D2 C4 D1 26 D4 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F DE D3 06 52 52 43 85 12 1E D4 +00 10 38 D4 0A 52 52 43 2E 42 85 12 1E D4 40 10 +72 D3 08 53 57 50 42 00 85 12 1E D4 80 10 44 D4 +06 52 52 41 85 12 1E D4 00 11 60 D4 0A 52 52 41 +2E 42 85 12 1E D4 40 11 52 D4 06 53 58 54 85 12 +1E D4 80 11 00 00 08 50 55 53 48 00 85 12 1E D4 +00 12 86 D4 0C 50 55 53 48 2E 42 00 85 12 1E D4 +40 12 7A D4 08 43 41 4C 4C 00 85 12 1E D4 80 12 +1A 53 0E 4A 84 12 D6 C9 1E C4 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 C5 A4 D4 06 53 3E 3D +86 12 00 38 CC D4 04 53 3C 00 86 12 00 34 94 D4 +06 30 3E 3D 86 12 00 30 E0 D4 04 30 3C 00 86 12 +00 30 1C CF 04 55 3C 00 86 12 00 2C F4 D4 06 55 +3E 3D 86 12 00 28 EA D4 06 30 3C 3E 86 12 00 24 +08 D5 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 21 8A 4E 00 00 A2 53 C8 21 0E 4A 30 4D +8E D3 08 54 48 45 4E 00 1A 42 C8 21 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D FE D4 08 45 4C 53 45 00 1A 42 C8 21 +BA 40 00 3C 00 00 A2 53 C8 21 2F 83 8F 4A 00 00 +E3 3F 6C D4 0A 42 45 47 49 4E 30 40 32 C4 56 D5 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 21 +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 21 30 4D 12 D4 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 20 D5 7C C8 62 C9 74 D5 +0C 52 45 50 45 41 54 00 0D 12 84 12 B4 D5 38 D5 +62 C9 E4 D5 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 21 +CB 2F 98 42 C8 21 00 00 30 4D D0 D5 06 42 57 31 +85 12 E2 D5 00 00 FC D5 06 42 57 32 85 12 E2 D5 +00 00 08 D6 06 42 57 33 85 12 E2 D5 00 00 20 D6 +3D 41 1A 42 C8 21 28 4E 8E 43 00 00 B2 92 C6 21 +86 2B BA 4F 00 00 A2 53 C8 21 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 1E D6 00 00 44 D6 +06 46 57 32 85 12 1E D6 00 00 50 D6 06 46 57 33 +85 12 1E D6 00 00 BE D5 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 56 CD 62 CC +62 C9 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +8A D2 0A C4 2C 00 E6 C9 30 CB AC C4 66 CD 94 C7 +80 D2 62 D2 B6 D6 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 14 D6 08 52 52 43 4D 00 85 12 A0 D6 50 00 +E4 D6 08 52 52 41 4D 00 85 12 A0 D6 50 01 F2 D6 +08 52 4C 41 4D 00 85 12 A0 D6 50 02 00 D7 08 52 +52 55 4D 00 85 12 A0 D6 50 03 12 D5 0A 50 55 53 +48 4D 85 12 A0 D6 00 15 1C D7 08 50 4F 50 4D 00 +85 12 A0 D6 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 82 C6 E2 C5 E2 C5 -E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 E2 C5 42 D1 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 BC C6 FA C5 FA C5 +FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 FA C5 0E C6 q diff --git a/binaries/MSP_EXP430FR4133_8MHz_UART.txt b/binaries/MSP_EXP430FR4133_8MHz_UART.txt deleted file mode 100644 index 0123f28..0000000 --- a/binaries/MSP_EXP430FR4133_8MHz_UART.txt +++ /dev/null @@ -1,340 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF 34 D8 3C D0 34 01 -10 00 41 B3 94 C5 AA C4 DA C5 9C C5 94 C6 34 D8 -3C D0 7A C6 92 C7 24 C7 FE C6 3C 21 60 C8 D4 C4 -E2 C4 EE C4 20 00 0A 00 00 00 00 00 00 00 00 00 -@C400 -B0 12 DA C5 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 21 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C4 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 21 -B2 4F C2 21 82 43 C4 21 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 21 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C4 39 40 22 18 -B2 49 78 C6 B2 49 90 C7 B2 49 22 C7 B2 49 FC C6 -B2 49 CA C4 34 49 35 49 36 49 37 49 B2 49 B4 21 -B2 49 DC 21 3D 41 30 40 08 D1 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C5 92 C3 1C 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -1C 05 F3 23 B0 12 F8 C4 0A C4 DE 21 E0 C7 32 C7 -14 C4 04 1B 5B 37 6D 00 5C C7 A8 C7 34 C4 86 C5 -14 C4 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C7 A0 C8 5C C7 14 C4 04 1B 5B 30 6D 00 -5C C7 62 CC 92 B3 0A 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 00 05 92 42 02 18 06 05 92 42 04 18 -08 05 F2 D0 03 00 0A 02 92 C3 00 05 92 D3 1A 05 -92 C3 30 01 30 41 09 3C A2 B3 1C 05 FD 27 B2 40 -13 00 0E 05 F2 D2 03 02 30 41 A2 B3 1C 05 FD 27 -B2 40 11 00 0E 05 F2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C5 E2 B2 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C5 04 57 41 52 4D 00 B0 12 -9C C5 84 12 14 C4 07 0D 0A 1B 5B 37 6D 23 5C C7 -D6 C8 14 C4 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C7 -0A C4 40 FF 28 C4 D4 C7 A0 C8 14 C4 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C4 86 C5 00 00 06 41 -43 43 45 50 54 00 30 40 7A C6 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C6 3C 40 D2 C6 -5D 15 B6 3E 21 52 3A 17 58 42 0C 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 1C 05 FD 27 -C2 48 0E 05 30 4D C8 C6 2D 83 92 B3 1C 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 1C 05 -FD 27 58 42 0C 05 82 93 DE 21 02 24 92 53 DE 21 -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C6 2F 83 -8F 4E 00 00 B0 12 DA C5 92 B3 1C 05 FD 27 1E 42 -0C 05 B0 12 C8 C5 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C7 08 4E 3E 4F C8 3F 1A C7 04 45 43 48 -4F 00 B2 40 C2 48 C0 C6 82 43 DE 21 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C6 92 43 -DE 21 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C7 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C7 7A C7 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C5 02 43 52 00 30 40 -92 C7 0D 12 84 12 14 C4 02 0D 0A 00 5C C7 60 C8 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 20 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C6 01 40 -2E 4E 30 4D DE C7 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 21 B2 21 30 4D 8A C7 01 23 1B 42 DC 21 -2C 4F 2F 83 B0 12 6E C4 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 21 18 42 -B2 21 C8 4A 00 00 30 4D 1A C8 02 23 53 00 0D 12 -84 12 1C C8 56 C8 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C8 02 23 3E 00 9F 42 B2 21 00 00 -3E 40 B2 21 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C7 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C8 4E C8 EE C4 8E C8 6A C8 5C C7 4E CC 20 C7 -60 C8 40 C7 01 2E 0E 93 E3 37 38 43 E2 3F 88 C8 -82 53 22 00 82 43 B4 21 0D 12 84 12 0A C4 14 C4 -94 CB 0A C4 22 00 2C C9 FA C8 B2 40 20 00 B4 21 -6E 4E 1E 53 1E B3 82 6E C6 21 3E 4F 3D 41 30 4D -D4 C8 82 2E 22 00 0D 12 84 12 E4 C8 0A C4 5C C7 -94 CB 60 C8 18 C6 04 57 4F 52 44 00 3C 40 C0 21 -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 21 FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C4 1A 82 C2 21 82 4A C4 21 -1E 42 C6 21 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 21 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C4 35 40 D4 C4 -30 4D 9C C8 03 55 4D 2A 2C 4F 0B 43 09 43 08 43 -1A 43 0E BA 02 24 09 5C 08 6B 0C 5C 0B 6B 0A 5A -F8 2B 8F 49 00 00 0E 48 30 4D 00 00 07 3E 4E 55 -4D 42 45 52 2C 4F 0B 4E 1A 42 DC 21 68 4C 78 80 -30 00 78 90 0A 00 05 28 78 80 07 00 78 90 0A 00 -1F 28 08 9A 22 C3 1C 2C 5D 15 1C 4F 02 00 0E 4A -3D 40 56 CA D2 3F 58 CA 81 49 02 00 1C 4F 04 00 -1E 41 04 00 3D 40 6A CA C8 3F 6C CA 39 51 3E 61 -8F 49 04 00 8F 4E 02 00 3A 17 1C 53 1B 83 D6 23 -8F 4C 00 00 0E 4B 30 4D 32 C0 00 02 1B 42 DC 21 -0C 43 2D 15 3D 40 EA CA 0A 4B 3F 82 8F 4E 06 00 -8F 43 04 00 8F 43 02 00 0C 4E 7B 4C FC 90 27 00 -00 00 06 20 DF 4C 01 00 04 00 7E 90 03 00 47 3C -68 4C 78 80 2D 00 04 28 B1 23 B1 43 02 00 0A 3C -2A 43 78 52 07 24 3A 52 68 53 04 24 3A 40 10 00 -78 53 35 20 1C 53 1B 83 EB 3F EC CA 30 24 2D 83 -78 90 28 00 C2 27 32 B0 00 02 29 20 32 D0 00 02 -78 90 F7 00 BA 27 78 90 F5 00 21 20 09 43 8F 49 -02 00 5B 83 09 4B 09 5C 69 49 79 80 30 00 79 90 -0A 00 05 28 79 80 07 00 79 90 0A 00 0A 28 09 9A -08 2C 8F 49 00 00 0E 4A 2C 15 B0 12 66 C4 2A 17 -E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 4B 93 2B 17 -0E 4C 82 4B DC 21 06 24 32 C0 00 02 3F 50 06 00 -0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 -3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 -02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D -00 00 01 2C 1A 42 C6 21 8A 4E 00 00 A2 53 C6 21 -3E 4F 30 4D 92 CB 87 4C 49 54 45 52 41 4C 82 93 -BE 21 0D 24 09 4E 1A 42 C6 21 A2 52 C6 21 BA 40 -0A C4 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 -00 02 03 24 8A 4E 02 00 EE 3F 30 4D 66 C8 05 43 -4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 5E 4E FF FF -30 4D 7A C8 09 49 4E 54 45 52 50 52 45 54 0D 12 -84 12 AC C4 4E CC 2C C9 0A CC 7F 26 3D 40 12 CC -C1 3E 14 CC 0A 4E 3E 4F 3D 40 2E CC 35 27 3D 40 -04 CC 1A E2 BE 21 B6 27 0E 12 3E 4F 30 41 30 CC -3E 4F 3D 40 04 CC BB 23 DE 53 00 00 68 4E 08 5E -F8 40 3F 00 00 00 3D 40 D0 CD CC 3F 38 CC 86 12 -20 00 E6 C7 05 41 4C 4C 4F 54 82 5E C6 21 3E 4F -30 4D 3F 40 80 20 0E 43 31 40 E0 20 B2 40 00 20 -00 20 82 43 BE 21 84 12 8E C7 BC C4 FE CB C4 C7 -F6 C7 14 C4 0C 73 74 61 63 6B 20 65 6D 70 74 79 -21 00 2A C5 0A C4 40 FF 28 C4 FE C7 14 C4 0A 46 -52 41 4D 20 66 75 6C 6C 21 00 2A C5 3A C4 78 CC -54 CC 86 41 42 4F 52 54 22 00 0D 12 84 12 E4 C8 -0A C4 2A C5 94 CB 60 C8 8E C9 01 27 0D 12 84 12 -4E CC 2C C9 94 C9 34 C4 4C CC 60 C8 00 00 83 5B -27 5D 0D 12 84 12 CC CC 0A C4 0A C4 94 CB 94 CB -60 C8 DE CC 81 5B 82 43 BE 21 30 4D 0C C8 01 5D -B2 43 BE 21 30 4D FE CC 81 5C 92 42 C0 21 C4 21 -30 4D 00 00 88 50 4F 53 54 50 4F 4E 45 00 0D 12 -84 12 4E CC 2C C9 94 C9 A8 C7 34 C4 4C CC F6 C7 -34 C4 40 CD 0A C4 0A C4 94 CB 94 CB 0A C4 94 CB -94 CB 60 C8 F4 CC 01 3A 30 12 90 CD 92 B3 C6 21 -A2 63 C6 21 0D 12 84 12 4E CC 2C C9 5E CD 3D 41 -08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 DA 21 6E 4E -3E F0 1E 00 09 5E 3E 4F 82 48 B6 21 82 49 B8 21 -82 4A BA 21 82 4F BC 21 2A 52 82 4A C6 21 30 41 -BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BE 21 -30 4D 82 9F BC 21 09 20 18 42 B6 21 19 42 B8 21 -A8 49 FE FF 89 48 00 00 30 4D 0D 12 84 12 14 C4 -0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 -36 C5 46 CD 81 3B 82 93 BE 21 97 27 0D 12 84 12 -0A C4 60 C8 94 CB A2 CD F6 CC 60 C8 F4 CB 09 49 -4D 4D 45 44 49 41 54 45 18 42 B6 21 F8 D0 80 00 -00 00 30 4D DE CB 06 43 52 45 41 54 45 00 B0 12 -4C CD BA 40 86 12 FC FF 8A 4A FE FF C9 3F 06 CE -04 43 4F 44 45 00 B0 12 4C CD A2 82 C6 21 0D 12 -84 12 3E D0 18 D0 60 C8 EE CD 07 48 44 4E 43 4F -44 45 B2 40 1C D0 DA 21 EE 3F 00 00 07 45 4E 44 -43 4F 44 45 0D 12 84 12 A2 CD 58 D0 76 D0 60 C8 -00 00 05 43 4F 4C 4F 4E 1A 42 C6 21 BA 40 0D 12 -00 00 BA 40 84 12 02 00 A2 52 C6 21 B2 43 BE 21 -0D 12 84 12 58 D0 76 D0 60 C8 00 00 05 4C 4F 32 -48 49 A2 83 C6 21 1A 42 C6 21 EB 3F 3A CE 85 48 -49 32 4C 4F 0D 12 84 12 28 C4 E6 CF 94 CB F6 CC -2E CE 60 C8 D4 CD 86 5B 54 48 45 4E 5D 00 30 4D -0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C 10 24 1B 83 -06 30 1C 83 04 30 19 53 F9 98 FF FF F5 27 2D 4D -3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 2F 53 2D 53 -F7 3F B6 CE 86 5B 45 4C 53 45 5D 00 0D 12 84 12 -0A C4 00 00 D8 C7 4E CC 2C C9 E4 CB A0 C7 34 C4 -4E CF AE C7 14 C4 06 5B 54 48 45 4E 5D 00 C0 CE -28 CF E4 CE 06 CF 60 C8 AE C7 14 C4 06 5B 45 4C -53 45 5D 00 C0 CE 3E CF E4 CE 04 CF 60 C8 14 C4 -04 5B 49 46 5D 00 C0 CE 06 CF 3A C4 04 CF 82 C7 -14 C4 05 0D 0A 6B 6F 20 5C C7 BC C4 AC C4 3A C4 -06 CF F4 CE 84 5B 49 46 5D 00 0E 93 3E 4F C6 27 -30 4D 2F 53 30 4D 64 CF 89 5B 44 45 46 49 4E 45 -44 5D 0D 12 84 12 4E CC 2C C9 94 C9 72 CF 60 C8 -78 CF 8B 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 -84 12 82 CF F0 C7 60 C8 AA CF B2 4E 0A 18 2E 53 -BE 12 3E 4F 3D 41 90 3C A6 CB 06 4D 41 52 4B 45 -52 00 B0 12 4C CD BA 40 85 12 FC FF BA 40 A8 CF -FE FF 28 83 8A 48 00 00 BA 40 AA C4 04 00 B2 50 -06 00 C6 21 E1 3E 2E 53 30 4D 0A C4 CA 21 E8 C7 -60 C8 85 12 EA CF B2 CC 20 CE 2C C7 CA CC 9E CE -F6 C6 BA CF 12 C9 E2 D0 F6 D0 F4 C9 26 C9 00 00 -92 CF 08 CD 1C CA 00 00 85 12 EA CF AA D6 10 D7 -52 D6 60 D7 18 D6 00 00 E4 D3 00 00 28 D8 0C D8 -7C D6 BA D6 F4 D4 00 00 00 00 7C D7 16 D0 3A 40 -0C 00 39 40 D6 21 08 49 28 53 19 83 18 83 E8 49 -00 00 1A 83 FA 23 30 4D 3A 40 0E 00 38 40 CA 21 -09 48 29 53 F8 49 00 00 18 53 1A 83 FB 23 30 4D -82 43 CC 21 30 4D 92 42 CA 21 DA 21 30 4D F2 CF -70 D0 76 D0 86 D0 1A 42 20 18 82 4A C8 21 2E 4E -82 4E C6 21 3D 40 10 00 09 4A 08 49 29 83 18 48 -FE FF 0E 98 FC 2B 89 48 00 00 1D 83 F6 23 2A 4A -0A 93 F0 23 3E 4F 3D 41 30 4D 14 CD 09 50 57 52 -5F 53 54 41 54 45 85 12 7E D0 34 D8 E0 C8 09 52 -53 54 5F 53 54 41 54 45 92 42 0A 18 CA D0 F3 3F -BC D0 08 50 57 52 5F 48 45 52 45 00 92 42 C6 21 -CA D0 30 4D CE D0 08 52 53 54 5F 48 45 52 45 00 -92 42 C6 21 0A 18 F2 3F 3E 90 0E 00 DC 27 2E 92 -E3 37 0E 93 D8 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 54 D1 FE FF 29 83 B9 40 02 C6 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 C6 B2 49 -FA C4 B2 49 02 C4 B2 49 20 C6 B2 49 EC FF B2 49 -0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 10 00 00 01 -B2 40 80 5A CC 01 31 40 E0 20 3F 40 80 20 39 40 -00 08 29 83 89 43 00 20 FC 23 B2 D3 06 02 B2 D3 -02 02 F2 D2 05 02 B2 D0 FF FE 26 02 B2 43 22 02 -B2 D3 46 02 B2 43 42 02 B2 D3 66 02 B2 43 62 02 -B2 40 00 A5 60 01 B2 40 FF 1E 80 01 B2 40 B6 00 -82 01 B2 40 F4 00 84 01 82 43 88 01 F2 D0 06 00 -2B 02 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 1E 42 08 18 82 43 08 18 1E D2 5E 01 B0 12 -F8 C4 1E C6 38 40 C0 21 0A 4E 39 48 2E 48 09 5E -1E 52 C4 21 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 21 30 4D 1C 15 0E 12 12 12 C4 21 -84 12 2C C9 94 C9 F0 C7 34 C4 24 D2 88 CA 34 C4 -3E D2 38 D2 26 D2 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 40 D2 -B2 41 C4 21 3E 41 84 12 0A C4 2B 00 2C C9 94 C9 -F0 C7 34 C4 5C D2 88 CA 34 C4 4C CC BA C7 2C C9 -88 CA 34 C4 4C CC 68 D2 3E 5F E7 3F 3E 40 28 00 -B0 12 08 D2 19 42 C6 21 A2 53 C6 21 89 4E 00 00 -3E 40 29 00 92 92 C0 21 C4 21 02 20 30 40 BA CD -1C 15 12 12 C4 21 92 53 C4 21 84 12 2C C9 88 CA -34 C4 B0 D2 A6 D2 21 53 3E 90 10 00 C6 2B 7F 2D -B2 D2 B2 41 C4 21 C1 3F 0D 12 84 12 4E CC E4 D1 -C2 D2 0C 43 1B 42 C6 21 A2 53 C6 21 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 21 B0 12 08 D2 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 21 A2 53 C6 21 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 21 B0 12 08 D2 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 21 B0 12 90 D2 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 90 D2 92 92 C0 21 C4 21 02 24 -92 53 C4 21 8E 10 0C 5E DA 3F B0 12 90 D2 FA 23 -3C 50 10 00 B0 12 6C D2 EF 3F 0C 43 1B 42 C6 21 -A2 53 C6 21 0D 12 84 12 4E CC E4 D1 8E D3 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 90 D2 E0 23 3C 50 80 00 B0 12 6C D2 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A C4 00 13 -94 CB 60 C8 0A C4 2C 00 B8 D2 84 D3 CE D3 09 4B -2E 4E 0E DC A2 3F 8C CE 03 4D 4F 56 85 12 C4 D3 -00 40 D8 D3 05 4D 4F 56 2E 42 85 12 C4 D3 40 40 -00 00 03 41 44 44 85 12 C4 D3 00 50 F2 D3 05 41 -44 44 2E 42 85 12 C4 D3 40 50 FE D3 04 41 44 44 -43 00 85 12 C4 D3 00 60 0C D4 06 41 44 44 43 2E -42 00 85 12 C4 D3 40 60 B2 D3 04 53 55 42 43 00 -85 12 C4 D3 00 70 2A D4 06 53 55 42 43 2E 42 00 -85 12 C4 D3 40 70 38 D4 03 53 55 42 85 12 C4 D3 -00 80 48 D4 05 53 55 42 2E 42 85 12 C4 D3 40 80 -62 CE 03 43 4D 50 85 12 C4 D3 00 90 62 D4 05 43 -4D 50 2E 42 85 12 C4 D3 40 90 4C CE 04 44 41 44 -44 00 85 12 C4 D3 00 A0 7C D4 06 44 41 44 44 2E -42 00 85 12 C4 D3 40 A0 6E D4 03 42 49 54 85 12 -C4 D3 00 B0 9A D4 05 42 49 54 2E 42 85 12 C4 D3 -40 B0 A6 D4 03 42 49 43 85 12 C4 D3 00 C0 B4 D4 -05 42 49 43 2E 42 85 12 C4 D3 40 C0 C0 D4 03 42 -49 53 85 12 C4 D3 00 D0 CE D4 05 42 49 53 2E 42 -85 12 C4 D3 40 D0 00 00 03 58 4F 52 85 12 C4 D3 -00 E0 E8 D4 05 58 4F 52 2E 42 85 12 C4 D3 40 E0 -1A D4 03 41 4E 44 85 12 C4 D3 00 F0 02 D5 05 41 -4E 44 2E 42 85 12 C4 D3 40 F0 4E CC B8 D2 20 D5 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -54 D4 03 52 52 43 85 12 1A D5 00 10 32 D5 05 52 -52 43 2E 42 85 12 1A D5 40 10 3E D5 04 53 57 50 -42 00 85 12 1A D5 80 10 4C D5 03 52 52 41 85 12 -1A D5 00 11 5A D5 05 52 52 41 2E 42 85 12 1A D5 -40 11 66 D5 03 53 58 54 85 12 1A D5 80 11 00 00 -04 50 55 53 48 00 85 12 1A D5 00 12 80 D5 06 50 -55 53 48 2E 42 00 85 12 1A D5 40 12 DA D4 04 43 -41 4C 4C 00 85 12 1A D5 80 12 1A 53 0E 4A 0D 12 -84 12 D6 C8 14 C4 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 C5 74 D5 03 53 3E 3D 86 12 00 38 -C8 D5 02 53 3C 00 86 12 00 34 8E D5 03 30 3E 3D -86 12 00 30 DC D5 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C F0 D5 03 55 3E 3D 86 12 -00 28 E6 D5 03 30 3C 3E 86 12 00 24 04 D6 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 21 -8A 4E 00 00 A2 53 C6 21 0E 4A 30 4D FA D5 04 54 -48 45 4E 00 1A 42 C6 21 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -8A D4 04 45 4C 53 45 00 1A 42 C6 21 BA 40 00 3C -00 00 A2 53 C6 21 2F 83 8F 4A 00 00 E3 3F 9E D5 -05 42 45 47 49 4E 30 40 28 C4 2E D6 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 21 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 21 30 4D 0E D5 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 1C D6 BA C7 60 C8 D2 D5 06 52 45 50 -45 41 54 00 0D 12 84 12 B0 D6 34 D6 60 C8 E0 D6 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 21 CB 2F 98 42 -C6 21 00 00 30 4D 70 D6 03 42 57 31 85 12 DE D6 -00 00 F8 D6 03 42 57 32 85 12 DE D6 00 00 04 D7 -03 42 57 33 85 12 DE D6 00 00 1C D7 3D 41 1A 42 -C6 21 28 4E B2 92 C4 21 88 2B BA 4F 00 00 A2 53 -C6 21 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 1A D7 00 00 3C D7 03 46 57 32 85 12 1A D7 -00 00 48 D7 03 46 57 33 85 12 1A D7 00 00 54 D7 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 CC CC 28 CC 60 C8 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 4E CC E4 D1 9E D7 92 53 -C4 21 3E 40 2C 00 84 12 2C C9 88 CA 34 C4 4C CC -7A D3 B4 D7 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -CC D6 04 52 52 43 4D 00 85 12 98 D7 50 00 E2 D7 -04 52 52 41 4D 00 85 12 98 D7 50 01 F0 D7 04 52 -4C 41 4D 00 85 12 98 D7 50 02 FE D7 04 52 52 55 -4D 00 85 12 98 D7 50 03 0E D6 05 50 55 53 48 4D -85 12 98 D7 00 15 1A D8 04 50 4F 50 4D 00 85 12 -98 D7 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 94 C6 02 C6 -02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 02 C6 54 D1 -q diff --git a/binaries/MSP_EXP430FR5739_16MHz_115200.txt b/binaries/MSP_EXP430FR5739_16MHz_115200.txt new file mode 100644 index 0000000..afdbc08 --- /dev/null +++ b/binaries/MSP_EXP430FR5739_16MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 59 +D0 C4 7E C3 84 C3 54 C3 40 C5 2E D5 E6 CD A0 CD +A0 CD B6 C4 74 C5 3C C5 3C 1D E0 1C 94 C7 B6 C2 +C4 C2 B0 C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +40 C5 2E D5 E6 CD A0 CD A0 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 03 3D 0E 93 3E 4F +98 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B4 C4 B2 49 +72 C5 B2 49 3A C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 5A CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 40 C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 BA C6 AC C2 52 C3 82 C5 1E C2 04 1B +5B 37 6D 00 A4 C5 A4 C5 1E C2 04 1B 5B 30 6D 00 +A4 C5 F0 CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 82 C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 A4 C5 08 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A4 C5 0A C2 40 FF 32 C2 +D0 C6 D4 C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 80 00 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 +19 42 9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 +0E 49 B0 12 D0 C2 86 C3 00 00 0C 41 43 43 45 50 +54 00 30 40 B6 C4 08 4E 2E 4F 08 5E 39 40 0D 00 +3A 40 20 00 3B 40 14 C5 3C 40 20 C5 5D 15 98 3E +21 52 3A 17 58 42 CC 05 48 9B 09 20 A2 B3 DC 05 +FD 27 B2 40 13 00 CE 05 E2 D2 03 02 30 41 48 9C +06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A +03 2C CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 +CE 05 30 4D 16 C5 2D 83 92 B3 DC 05 DB 23 FC 3F +3E 8F 3D 41 92 B3 DC 05 FD 27 58 42 CC 05 08 4C +EB 3F 00 00 06 4B 45 59 30 40 3C C5 30 12 52 C5 +A2 B3 DC 05 FD 27 B2 40 11 00 CE 05 E2 C2 03 02 +30 41 2F 83 8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 +DC C4 1E 42 CC 05 30 4D 00 00 08 45 4D 49 54 00 +30 40 74 C5 08 4E 3E 4F C7 3F 6A C5 08 45 43 48 +4F 00 B2 40 C2 48 0E C5 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 0E C5 30 4D 00 00 08 54 +59 50 45 00 0D 12 3D 40 B4 C5 29 4F 8F 4E 00 00 +7E 49 DE 3F B6 C5 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 6E 22 F9 98 00 00 6B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 62 22 9B 24 +34 C5 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C2 +00 00 D4 C6 C6 C5 18 C8 D2 CA B0 C2 42 C6 14 C2 +06 5B 54 48 45 4E 5D 00 CA C5 20 C6 E6 C5 04 C6 +14 C2 06 5B 45 4C 53 45 5D 00 CA C5 32 C6 E6 C5 +02 C6 1E C2 04 5B 49 46 5D 00 CA C5 04 C6 B2 C2 +02 C6 1E C2 05 0D 6B 6F 20 0A A4 C5 9A C2 84 C2 +B2 C2 04 C6 F2 C5 0D 5B 54 48 45 4E 5D 00 30 4D +56 C6 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +62 C6 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +C6 C5 18 C8 80 C8 24 CA 94 C7 72 C6 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 C6 C5 18 C8 +80 C8 A4 C6 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +AA C4 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C3 05 53 +22 00 82 43 C0 1D 0D 12 84 12 0A C2 1E C2 82 CA +0A C2 22 00 18 C8 18 C7 B2 40 20 00 C0 1D 1A 53 +1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 8C C5 05 2E +22 00 0D 12 84 12 02 C7 0A C2 A4 C5 82 CA 94 C7 +00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D FE C6 +02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 50 C7 +04 23 53 00 0D 12 84 12 52 C7 8C C7 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 80 C7 04 23 3E 00 9F 42 +B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 9A C7 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 7C C5 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 46 C7 C6 C5 B4 C7 84 C7 B0 C6 C2 C7 9E C7 +A4 C5 94 C7 2E C7 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +06 C8 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 +1E 15 3D 40 8A C9 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 8C C9 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 42 C7 03 5C 92 42 C2 1D +C6 1D 30 4D 0D 12 84 12 84 C2 C6 C5 18 C8 B0 C2 +5C CB 80 C8 46 CA 0A 4E 3E 4F 3D 40 60 CA 6D 27 +3D 40 3A CA 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 +62 CA 3E 4F 3D 40 3A CA 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 38 CC 2A 3C 2A CA +02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F +30 4D 80 CA 0F 4C 49 54 45 52 41 4C 82 93 BC 1D +0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D BC C7 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +E2 C6 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D +3F 40 80 1C 0E 43 84 12 1E C2 02 0D 0A 00 A4 C5 +94 C2 34 CA C2 C6 EC C6 1E C2 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 C3 32 C2 0A C2 40 FF F4 C6 +1E C2 09 46 52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 +F8 CA E2 CA 0D 41 42 4F 52 54 22 00 0D 12 84 12 +02 C7 0A C2 08 C3 82 CA 94 C7 12 C8 02 27 0D 12 +84 12 C6 C5 18 C8 80 C8 B0 C2 5E CB 26 C7 6A CA +8C C6 07 5B 27 5D 0D 12 84 12 4E CB 0A C2 0A C2 +82 CA 82 CA 94 C7 62 CB 03 5B 82 43 BC 1D 30 4D +00 00 02 5D B2 43 BC 1D 30 4D DA C6 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 C6 C5 18 C8 80 C8 +B0 C2 5E CB EC C6 AC C2 B6 CB 0A C2 0A C2 82 CA +82 CA 0A C2 82 CA 82 CA 94 C7 00 00 02 3A 30 12 +0C CC 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 C6 C5 +18 C8 D4 CB 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D +82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F +BA 1D 66 25 84 12 1E C2 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 C3 78 CB 03 3B 82 93 +BC 1D F4 26 0D 12 84 12 0A C2 94 C7 82 CA 1E CC +7A CB 94 C7 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 1D D8 D3 00 00 30 4D CC CA 0C 43 52 45 +41 54 45 00 B0 12 C2 CB BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 9E C5 0A 44 4F 45 53 3E 1A 42 B8 1D +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D BC CB +0E 3A 4E 4F 4E 41 4D 45 30 12 0C CC 2F 83 8F 4E +00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 56 CC 05 49 53 00 0D 12 82 93 BC 1D +08 20 84 12 4E CB D8 CC 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 66 CB 0A C2 DA CC 82 CA 94 C7 6C CC +08 43 4F 44 45 00 B0 12 C2 CB A2 82 C8 1D 61 3C +AE C7 0E 48 44 4E 43 4F 44 45 B2 40 C6 CD CC 1D +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +1E CC 24 CD 3D 41 92 42 D0 1D CC 1D 5D 3C F0 CC +0E 43 4F 44 45 4E 4E 4D 30 12 FA CC B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +EF 3F 02 CD 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 8E CD B2 40 +A0 CD D0 1D 82 4E CE 1D 30 40 26 C7 85 12 8C CD +8C CB 34 CB 1E CE 30 CD 86 CC D0 C7 7A C8 4C CB +74 CD C6 CC A0 CC 3C CC 94 CA A8 CE D2 C8 00 00 +00 00 85 12 8C CD 22 D5 A6 D3 06 D5 CE D2 2A D3 +78 D3 54 D4 60 D4 F0 D1 14 D3 00 00 00 00 62 CD +E0 D0 00 00 7C D4 C0 CD B2 40 A0 CD CE 1D 82 43 +D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 1D 3A 40 42 18 B0 12 F4 CD 30 4D 06 CE 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D +B0 12 F4 CD 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C4 FE FF +29 83 B9 40 F2 C3 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 F0 FF 3B 40 10 00 3A 40 3A 18 B0 12 +F8 CD 82 43 4A 18 C7 3F 9A CE B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 82 CB 0C 4D 41 52 4B 45 52 00 +12 12 C6 1D 0D 12 84 12 C6 C5 18 C8 80 C8 AC C2 +C6 CE BA C6 5A CA C8 CE 3E 4F 3D 41 B2 41 C6 1D +B0 12 C2 CB BA 40 85 12 FC FF BA 40 98 CE FE FF +28 83 8A 48 00 00 BA 40 82 C2 02 00 A2 52 C8 1D +18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 1D 84 12 18 C8 80 C8 AC C2 32 CF +12 CF 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 98 CE 00 00 01 20 3E 52 2E 83 21 53 +30 41 2A C9 AC C2 3A CF 2E CF 3C CF B2 41 C6 1D +30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 +02 CF 15 20 3E 40 2B 00 B0 12 02 CF 06 20 3E 40 +2D 00 B0 12 02 CF 92 83 C6 1D 0E 12 1E 41 02 00 +84 12 18 C8 2A C9 AC C2 5E CB 7C CF 3E 51 3A 17 +30 41 B0 12 42 CF 19 42 C8 1D 89 4E 00 00 A2 53 +C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 +84 12 18 C8 2A C9 AC C2 B4 CF AC CF 3E 90 10 00 +E6 2B 7C 2D B6 CF A2 41 C6 1D E1 3F 03 20 B0 12 +9A CF 43 3C 7A 90 23 00 24 20 B0 12 4A CF 3C 40 +00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 +20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 +30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 +30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 4A CF +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 96 CF +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 9A CF 92 92 +C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 82 CF F2 3F 03 20 B0 12 9A CF +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 82 CF EA 3F 0C 43 1B 42 C8 1D A2 53 +C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 +FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A C2 00 13 82 CA 94 C7 0A C2 2C 00 78 D0 BC CF +C6 C5 82 D0 5A D0 C8 D0 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 B8 D0 00 40 D4 D0 +0A 4D 4F 56 2E 42 85 12 B8 D0 40 40 00 00 06 41 +44 44 85 12 B8 D0 00 50 EE D0 0A 41 44 44 2E 42 +85 12 B8 D0 40 50 FA D0 08 41 44 44 43 00 85 12 +B8 D0 00 60 08 D1 0C 41 44 44 43 2E 42 00 85 12 +B8 D0 40 60 40 CD 08 53 55 42 43 00 85 12 B8 D0 +00 70 26 D1 0C 53 55 42 43 2E 42 00 85 12 B8 D0 +40 70 34 D1 06 53 55 42 85 12 B8 D0 00 80 44 D1 +0A 53 55 42 2E 42 85 12 B8 D0 40 80 50 D1 06 43 +4D 50 85 12 B8 D0 00 90 5E D1 0A 43 4D 50 2E 42 +85 12 B8 D0 40 90 00 00 08 44 41 44 44 00 85 12 +B8 D0 00 A0 78 D1 0C 44 41 44 44 2E 42 00 85 12 +B8 D0 40 A0 A6 D0 06 42 49 54 85 12 B8 D0 00 B0 +96 D1 0A 42 49 54 2E 42 85 12 B8 D0 40 B0 A2 D1 +06 42 49 43 85 12 B8 D0 00 C0 B0 D1 0A 42 49 43 +2E 42 85 12 B8 D0 40 C0 BC D1 06 42 49 53 85 12 +B8 D0 00 D0 CA D1 0A 42 49 53 2E 42 85 12 B8 D0 +40 D0 00 00 06 58 4F 52 85 12 B8 D0 00 E0 E4 D1 +0A 58 4F 52 2E 42 85 12 B8 D0 40 E0 16 D1 06 41 +4E 44 85 12 B8 D0 00 F0 FE D1 0A 41 4E 44 2E 42 +85 12 B8 D0 40 F0 C6 C5 78 D0 BC CF 1E D2 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F D6 D1 +06 52 52 43 85 12 16 D2 00 10 30 D2 0A 52 52 43 +2E 42 85 12 16 D2 40 10 6A D1 08 53 57 50 42 00 +85 12 16 D2 80 10 3C D2 06 52 52 41 85 12 16 D2 +00 11 58 D2 0A 52 52 41 2E 42 85 12 16 D2 40 11 +4A D2 06 53 58 54 85 12 16 D2 80 11 00 00 08 50 +55 53 48 00 85 12 16 D2 00 12 7E D2 0C 50 55 53 +48 2E 42 00 85 12 16 D2 40 12 72 D2 08 43 41 4C +4C 00 85 12 16 D2 80 12 1A 53 0E 4A 84 12 08 C8 +1E C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 C3 9C D2 06 53 3E 3D 86 12 00 38 C4 D2 04 53 +3C 00 86 12 00 34 8C D2 06 30 3E 3D 86 12 00 30 +D8 D2 04 30 3C 00 86 12 00 30 14 CD 04 55 3C 00 +86 12 00 2C EC D2 06 55 3E 3D 86 12 00 28 E2 D2 +06 30 3C 3E 86 12 00 24 00 D3 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 +A2 53 C8 1D 0E 4A 30 4D 86 D1 08 54 48 45 4E 00 +1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D F6 D2 08 45 +4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 +C8 1D 2F 83 8F 4A 00 00 E3 3F 64 D2 0A 42 45 47 +49 4E 30 40 32 C2 4E D3 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 1D 30 4D 0A D2 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +18 D3 AE C6 94 C7 6C D3 0C 52 45 50 45 41 54 00 +0D 12 84 12 AC D3 30 D3 94 C7 DC D3 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 +30 4D C8 D3 06 42 57 31 85 12 DA D3 00 00 F4 D3 +06 42 57 32 85 12 DA D3 00 00 00 D4 06 42 57 33 +85 12 DA D3 00 00 18 D4 3D 41 1A 42 C8 1D 28 4E +8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 +C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 16 D4 00 00 3C D4 06 46 57 32 85 12 16 D4 +00 00 48 D4 06 46 57 33 85 12 16 D4 00 00 B6 D3 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 4E CB 5A CA 94 C7 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F 82 D0 0A C2 2C 00 18 C8 +2A C9 AC C2 5E CB C6 C5 78 D0 5A D0 AE D4 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E 0C D4 08 52 52 43 +4D 00 85 12 98 D4 50 00 DC D4 08 52 52 41 4D 00 +85 12 98 D4 50 01 EA D4 08 52 4C 41 4D 00 85 12 +98 D4 50 02 F8 D4 08 52 52 55 4D 00 85 12 98 D4 +50 03 0A D3 0A 50 55 53 48 4D 85 12 98 D4 00 15 +14 D5 08 50 4F 50 4D 00 85 12 98 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +D0 C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_16MHz_4MBds.txt b/binaries/MSP_EXP430FR5739_16MHz_4MBds.txt new file mode 100644 index 0000000..e2973c2 --- /dev/null +++ b/binaries/MSP_EXP430FR5739_16MHz_4MBds.txt @@ -0,0 +1,325 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +D0 C4 7E C3 84 C3 54 C3 40 C5 2E D5 E6 CD A0 CD +A0 CD B6 C4 74 C5 3C C5 3C 1D E0 1C 94 C7 B6 C2 +C4 C2 B0 C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +40 C5 2E D5 E6 CD A0 CD A0 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 03 3D 0E 93 3E 4F +98 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B4 C4 B2 49 +72 C5 B2 49 3A C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 5A CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 40 C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 BA C6 AC C2 52 C3 82 C5 1E C2 04 1B +5B 37 6D 00 A4 C5 A4 C5 1E C2 04 1B 5B 30 6D 00 +A4 C5 F0 CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 82 C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 A4 C5 08 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A4 C5 0A C2 40 FF 32 C2 +D0 C6 D4 C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 80 00 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 +19 42 9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 +0E 49 B0 12 D0 C2 86 C3 00 00 0C 41 43 43 45 50 +54 00 30 40 B6 C4 08 4E 2E 4F 08 5E 39 40 0D 00 +3A 40 20 00 3B 40 14 C5 3C 40 20 C5 5D 15 98 3E +21 52 3A 17 58 42 CC 05 48 9B 09 20 A2 B3 DC 05 +FD 27 B2 40 13 00 CE 05 E2 D2 03 02 30 41 48 9C +06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A +03 2C CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 +CE 05 30 4D 16 C5 2D 83 92 B3 DC 05 DB 23 FC 3F +3E 8F 3D 41 92 B3 DC 05 FD 27 58 42 CC 05 08 4C +EB 3F 00 00 06 4B 45 59 30 40 3C C5 30 12 52 C5 +A2 B3 DC 05 FD 27 B2 40 11 00 CE 05 E2 C2 03 02 +30 41 2F 83 8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 +DC C4 1E 42 CC 05 30 4D 00 00 08 45 4D 49 54 00 +30 40 74 C5 08 4E 3E 4F C7 3F 6A C5 08 45 43 48 +4F 00 B2 40 C2 48 0E C5 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 0E C5 30 4D 00 00 08 54 +59 50 45 00 0D 12 3D 40 B4 C5 29 4F 8F 4E 00 00 +7E 49 DE 3F B6 C5 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 6E 22 F9 98 00 00 6B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 62 22 9B 24 +34 C5 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C2 +00 00 D4 C6 C6 C5 18 C8 D2 CA B0 C2 42 C6 14 C2 +06 5B 54 48 45 4E 5D 00 CA C5 20 C6 E6 C5 04 C6 +14 C2 06 5B 45 4C 53 45 5D 00 CA C5 32 C6 E6 C5 +02 C6 1E C2 04 5B 49 46 5D 00 CA C5 04 C6 B2 C2 +02 C6 1E C2 05 0D 6B 6F 20 0A A4 C5 9A C2 84 C2 +B2 C2 04 C6 F2 C5 0D 5B 54 48 45 4E 5D 00 30 4D +56 C6 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +62 C6 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +C6 C5 18 C8 80 C8 24 CA 94 C7 72 C6 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 C6 C5 18 C8 +80 C8 A4 C6 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +AA C4 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C3 05 53 +22 00 82 43 C0 1D 0D 12 84 12 0A C2 1E C2 82 CA +0A C2 22 00 18 C8 18 C7 B2 40 20 00 C0 1D 1A 53 +1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 8C C5 05 2E +22 00 0D 12 84 12 02 C7 0A C2 A4 C5 82 CA 94 C7 +00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D FE C6 +02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 50 C7 +04 23 53 00 0D 12 84 12 52 C7 8C C7 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 80 C7 04 23 3E 00 9F 42 +B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 9A C7 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 7C C5 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 46 C7 C6 C5 B4 C7 84 C7 B0 C6 C2 C7 9E C7 +A4 C5 94 C7 2E C7 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +06 C8 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 +1E 15 3D 40 8A C9 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 8C C9 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 42 C7 03 5C 92 42 C2 1D +C6 1D 30 4D 0D 12 84 12 84 C2 C6 C5 18 C8 B0 C2 +5C CB 80 C8 46 CA 0A 4E 3E 4F 3D 40 60 CA 6D 27 +3D 40 3A CA 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 +62 CA 3E 4F 3D 40 3A CA 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 38 CC 2A 3C 2A CA +02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F +30 4D 80 CA 0F 4C 49 54 45 52 41 4C 82 93 BC 1D +0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D BC C7 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +E2 C6 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D +3F 40 80 1C 0E 43 84 12 1E C2 02 0D 0A 00 A4 C5 +94 C2 34 CA C2 C6 EC C6 1E C2 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 C3 32 C2 0A C2 40 FF F4 C6 +1E C2 09 46 52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 +F8 CA E2 CA 0D 41 42 4F 52 54 22 00 0D 12 84 12 +02 C7 0A C2 08 C3 82 CA 94 C7 12 C8 02 27 0D 12 +84 12 C6 C5 18 C8 80 C8 B0 C2 5E CB 26 C7 6A CA +8C C6 07 5B 27 5D 0D 12 84 12 4E CB 0A C2 0A C2 +82 CA 82 CA 94 C7 62 CB 03 5B 82 43 BC 1D 30 4D +00 00 02 5D B2 43 BC 1D 30 4D DA C6 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 C6 C5 18 C8 80 C8 +B0 C2 5E CB EC C6 AC C2 B6 CB 0A C2 0A C2 82 CA +82 CA 0A C2 82 CA 82 CA 94 C7 00 00 02 3A 30 12 +0C CC 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 C6 C5 +18 C8 D4 CB 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D +82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F +BA 1D 66 25 84 12 1E C2 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 C3 78 CB 03 3B 82 93 +BC 1D F4 26 0D 12 84 12 0A C2 94 C7 82 CA 1E CC +7A CB 94 C7 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 1D D8 D3 00 00 30 4D CC CA 0C 43 52 45 +41 54 45 00 B0 12 C2 CB BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 9E C5 0A 44 4F 45 53 3E 1A 42 B8 1D +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D BC CB +0E 3A 4E 4F 4E 41 4D 45 30 12 0C CC 2F 83 8F 4E +00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 56 CC 05 49 53 00 0D 12 82 93 BC 1D +08 20 84 12 4E CB D8 CC 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 66 CB 0A C2 DA CC 82 CA 94 C7 6C CC +08 43 4F 44 45 00 B0 12 C2 CB A2 82 C8 1D 61 3C +AE C7 0E 48 44 4E 43 4F 44 45 B2 40 C6 CD CC 1D +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +1E CC 24 CD 3D 41 92 42 D0 1D CC 1D 5D 3C F0 CC +0E 43 4F 44 45 4E 4E 4D 30 12 FA CC B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +EF 3F 02 CD 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 8E CD B2 40 +A0 CD D0 1D 82 4E CE 1D 30 40 26 C7 85 12 8C CD +8C CB 34 CB 1E CE 30 CD 86 CC D0 C7 7A C8 4C CB +74 CD C6 CC A0 CC 3C CC 94 CA A8 CE D2 C8 00 00 +00 00 85 12 8C CD 22 D5 A6 D3 06 D5 CE D2 2A D3 +78 D3 54 D4 60 D4 F0 D1 14 D3 00 00 00 00 62 CD +E0 D0 00 00 7C D4 C0 CD B2 40 A0 CD CE 1D 82 43 +D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 1D 3A 40 42 18 B0 12 F4 CD 30 4D 06 CE 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D +B0 12 F4 CD 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C4 FE FF +29 83 B9 40 F2 C3 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 F0 FF 3B 40 10 00 3A 40 3A 18 B0 12 +F8 CD 82 43 4A 18 C7 3F 9A CE B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 82 CB 0C 4D 41 52 4B 45 52 00 +12 12 C6 1D 0D 12 84 12 C6 C5 18 C8 80 C8 AC C2 +C6 CE BA C6 5A CA C8 CE 3E 4F 3D 41 B2 41 C6 1D +B0 12 C2 CB BA 40 85 12 FC FF BA 40 98 CE FE FF +28 83 8A 48 00 00 BA 40 82 C2 02 00 A2 52 C8 1D +18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 1D 84 12 18 C8 80 C8 AC C2 32 CF +12 CF 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 98 CE 00 00 01 20 3E 52 2E 83 21 53 +30 41 2A C9 AC C2 3A CF 2E CF 3C CF B2 41 C6 1D +30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 +02 CF 15 20 3E 40 2B 00 B0 12 02 CF 06 20 3E 40 +2D 00 B0 12 02 CF 92 83 C6 1D 0E 12 1E 41 02 00 +84 12 18 C8 2A C9 AC C2 5E CB 7C CF 3E 51 3A 17 +30 41 B0 12 42 CF 19 42 C8 1D 89 4E 00 00 A2 53 +C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 +84 12 18 C8 2A C9 AC C2 B4 CF AC CF 3E 90 10 00 +E6 2B 7C 2D B6 CF A2 41 C6 1D E1 3F 03 20 B0 12 +9A CF 43 3C 7A 90 23 00 24 20 B0 12 4A CF 3C 40 +00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 +20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 +30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 +30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 4A CF +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 96 CF +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 9A CF 92 92 +C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 82 CF F2 3F 03 20 B0 12 9A CF +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 82 CF EA 3F 0C 43 1B 42 C8 1D A2 53 +C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 +FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A C2 00 13 82 CA 94 C7 0A C2 2C 00 78 D0 BC CF +C6 C5 82 D0 5A D0 C8 D0 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 B8 D0 00 40 D4 D0 +0A 4D 4F 56 2E 42 85 12 B8 D0 40 40 00 00 06 41 +44 44 85 12 B8 D0 00 50 EE D0 0A 41 44 44 2E 42 +85 12 B8 D0 40 50 FA D0 08 41 44 44 43 00 85 12 +B8 D0 00 60 08 D1 0C 41 44 44 43 2E 42 00 85 12 +B8 D0 40 60 40 CD 08 53 55 42 43 00 85 12 B8 D0 +00 70 26 D1 0C 53 55 42 43 2E 42 00 85 12 B8 D0 +40 70 34 D1 06 53 55 42 85 12 B8 D0 00 80 44 D1 +0A 53 55 42 2E 42 85 12 B8 D0 40 80 50 D1 06 43 +4D 50 85 12 B8 D0 00 90 5E D1 0A 43 4D 50 2E 42 +85 12 B8 D0 40 90 00 00 08 44 41 44 44 00 85 12 +B8 D0 00 A0 78 D1 0C 44 41 44 44 2E 42 00 85 12 +B8 D0 40 A0 A6 D0 06 42 49 54 85 12 B8 D0 00 B0 +96 D1 0A 42 49 54 2E 42 85 12 B8 D0 40 B0 A2 D1 +06 42 49 43 85 12 B8 D0 00 C0 B0 D1 0A 42 49 43 +2E 42 85 12 B8 D0 40 C0 BC D1 06 42 49 53 85 12 +B8 D0 00 D0 CA D1 0A 42 49 53 2E 42 85 12 B8 D0 +40 D0 00 00 06 58 4F 52 85 12 B8 D0 00 E0 E4 D1 +0A 58 4F 52 2E 42 85 12 B8 D0 40 E0 16 D1 06 41 +4E 44 85 12 B8 D0 00 F0 FE D1 0A 41 4E 44 2E 42 +85 12 B8 D0 40 F0 C6 C5 78 D0 BC CF 1E D2 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F D6 D1 +06 52 52 43 85 12 16 D2 00 10 30 D2 0A 52 52 43 +2E 42 85 12 16 D2 40 10 6A D1 08 53 57 50 42 00 +85 12 16 D2 80 10 3C D2 06 52 52 41 85 12 16 D2 +00 11 58 D2 0A 52 52 41 2E 42 85 12 16 D2 40 11 +4A D2 06 53 58 54 85 12 16 D2 80 11 00 00 08 50 +55 53 48 00 85 12 16 D2 00 12 7E D2 0C 50 55 53 +48 2E 42 00 85 12 16 D2 40 12 72 D2 08 43 41 4C +4C 00 85 12 16 D2 80 12 1A 53 0E 4A 84 12 08 C8 +1E C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 C3 9C D2 06 53 3E 3D 86 12 00 38 C4 D2 04 53 +3C 00 86 12 00 34 8C D2 06 30 3E 3D 86 12 00 30 +D8 D2 04 30 3C 00 86 12 00 30 14 CD 04 55 3C 00 +86 12 00 2C EC D2 06 55 3E 3D 86 12 00 28 E2 D2 +06 30 3C 3E 86 12 00 24 00 D3 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 +A2 53 C8 1D 0E 4A 30 4D 86 D1 08 54 48 45 4E 00 +1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D F6 D2 08 45 +4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 +C8 1D 2F 83 8F 4A 00 00 E3 3F 64 D2 0A 42 45 47 +49 4E 30 40 32 C2 4E D3 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 1D 30 4D 0A D2 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +18 D3 AE C6 94 C7 6C D3 0C 52 45 50 45 41 54 00 +0D 12 84 12 AC D3 30 D3 94 C7 DC D3 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 +30 4D C8 D3 06 42 57 31 85 12 DA D3 00 00 F4 D3 +06 42 57 32 85 12 DA D3 00 00 00 D4 06 42 57 33 +85 12 DA D3 00 00 18 D4 3D 41 1A 42 C8 1D 28 4E +8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 +C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 16 D4 00 00 3C D4 06 46 57 32 85 12 16 D4 +00 00 48 D4 06 46 57 33 85 12 16 D4 00 00 B6 D3 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 4E CB 5A CA 94 C7 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F 82 D0 0A C2 2C 00 18 C8 +2A C9 AC C2 5E CB C6 C5 78 D0 5A D0 AE D4 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E 0C D4 08 52 52 43 +4D 00 85 12 98 D4 50 00 DC D4 08 52 52 41 4D 00 +85 12 98 D4 50 01 EA D4 08 52 4C 41 4D 00 85 12 +98 D4 50 02 F8 D4 08 52 52 55 4D 00 85 12 98 D4 +50 03 0A D3 0A 50 55 53 48 4D 85 12 98 D4 00 15 +14 D5 08 50 4F 50 4D 00 85 12 98 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +D0 C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_16MHz_I2C.txt b/binaries/MSP_EXP430FR5739_16MHz_I2C.txt index 5aa599c..cd30cc7 100644 --- a/binaries/MSP_EXP430FR5739_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5739_16MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF F0 D5 F0 CD 34 01 -10 00 41 87 B6 C3 AA C2 B8 C3 8C C3 82 C4 F0 D5 -F0 CD 70 C4 80 C5 FE C4 DA C4 3C 1D 4E C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +CA C4 56 C3 56 C3 58 C3 44 C3 0A D5 C2 CD 7C CD +7C CD B8 C4 3C C5 14 C5 3C 1D E0 1C 70 C7 B6 C2 +C4 C2 8C C6 20 00 0A 00 00 1C 56 C3 56 C3 58 C3 +44 C3 0A D5 C2 CD 7C CD 7C CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C200 -B0 12 B8 C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 6E C4 B2 49 7E C5 B2 49 FC C4 B2 49 D8 C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C3 0E 12 B0 12 -F8 C2 0A C2 DE 1D CE C5 16 C5 EE C2 34 C2 8A C3 -14 C2 05 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 -C4 C6 96 C5 34 C2 7E C3 14 C2 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C5 8E C6 4A C5 -14 C2 04 1B 5B 30 6D 00 4A C5 16 CA 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C3 04 57 41 52 4D 00 B0 12 -8C C3 78 40 03 00 B0 12 BA C3 84 12 14 C2 07 0D -0A 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 C4 C6 -0A C2 23 00 FA C4 C4 C6 14 C2 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C5 0A C2 40 FF 28 C2 C2 C5 8E C6 -14 C2 0A 62 79 74 65 73 20 66 72 65 65 00 3A C2 -7E C3 00 00 06 41 43 43 45 50 54 00 30 40 70 C4 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C3 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C4 2F 83 8F 4E 00 00 -58 43 B0 12 BA C3 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C4 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 C4 -04 45 43 48 4F 00 B2 40 C2 48 08 C5 82 43 DE 1D -38 40 05 00 B0 12 BA C3 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C5 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C5 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C4 68 C5 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C3 02 43 52 00 30 40 80 C5 -0D 12 84 12 14 C2 02 0D 0A 00 4A C5 4E C6 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C4 01 40 2E 4E -30 4D CC C5 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 C5 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 C6 02 23 53 00 0D 12 84 12 -0A C6 44 C6 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C6 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C5 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C5 -3C C6 EE C2 7C C6 58 C6 4A C5 02 CA FA C4 4E C6 -2C C5 01 2E 0E 93 E3 37 38 43 E2 3F 76 C6 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 48 C9 -0A C2 22 00 1A C7 E8 C6 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 C6 -82 2E 22 00 0D 12 84 12 D2 C6 0A C2 4A C5 48 C9 -4E C6 F8 C3 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C C8 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E C8 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 04 3D 0E 93 3E 4F +86 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B6 C4 B2 49 +3A C5 B2 49 12 C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 36 CE 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C3 B0 12 D0 C2 96 C6 AC C2 +42 C3 54 C5 1E C2 05 1B 5B 37 6D 40 80 C5 0A C2 +02 18 B8 C6 E4 C7 80 C5 1E C2 04 1B 5B 30 6D 00 +80 C5 CC CA 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 54 C5 1E C2 07 0D 0A 1B 5B 37 +6D 40 80 C5 0A C2 02 18 B8 C6 E4 C7 0A C2 23 00 +38 C5 E4 C7 1E C2 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +80 C5 0A C2 40 FF 32 C2 AC C6 B0 C7 1E C2 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C2 36 C3 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C3 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C 92 D3 30 01 B2 43 06 02 +B2 40 EF 7F 02 02 B2 43 26 02 B2 D0 08 FF 22 02 +F2 D3 26 03 F2 40 F0 00 22 03 F2 40 A5 00 61 01 +B2 40 80 00 62 01 82 43 66 01 B2 40 33 00 64 01 +D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 +2A 03 F2 C0 40 00 A1 04 39 40 00 04 29 83 89 43 +00 1C FC 23 1E 42 08 18 82 43 08 18 3E F3 02 20 +1E 42 9E 01 B0 12 D0 C2 80 C3 00 00 0C 41 43 43 +45 50 54 00 30 40 B8 C4 0A 4E 2E 4F 0A 5E 3B 40 +0A 00 3C 40 20 00 3D 15 9B 3E 21 52 A2 C2 6C 06 +B2 B0 10 00 40 06 94 22 3A 17 92 B3 6C 06 FD 27 +58 42 4C 06 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 +2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 +1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 +30 40 14 C5 58 43 B0 12 46 C3 2F 83 8F 4E 00 00 +92 B3 6C 06 FD 27 1E 42 4C 06 B0 12 44 C3 30 4D +00 00 08 45 4D 49 54 00 30 40 3C C5 08 4E 3E 4F +A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D 32 C5 08 45 +43 48 4F 00 B2 40 C2 48 46 C5 38 40 05 00 B0 12 +46 C3 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 46 C5 28 42 F3 3F 00 00 08 54 59 50 45 00 +0D 12 3D 40 90 C5 29 4F 8F 4E 00 00 7E 49 D4 3F +92 C5 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +80 22 F9 98 00 00 7D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 74 22 9B 24 0C C5 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A C2 00 00 B0 C6 +A2 C5 F4 C7 AE CA B0 C2 1E C6 14 C2 06 5B 54 48 +45 4E 5D 00 A6 C5 FC C5 C2 C5 E0 C5 14 C2 06 5B +45 4C 53 45 5D 00 A6 C5 0E C6 C2 C5 DE C5 1E C2 +04 5B 49 46 5D 00 A6 C5 E0 C5 B2 C2 DE C5 1E C2 +05 0D 6B 6F 20 0A 80 C5 9A C2 84 C2 B2 C2 E0 C5 +CE C5 0D 5B 54 48 45 4E 5D 00 30 4D 32 C6 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 3E C6 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 A2 C5 F4 C7 +5C C8 00 CA 70 C7 4E C6 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 A2 C5 F4 C7 5C C8 80 C6 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D AC C4 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D E0 C3 05 53 22 00 82 43 +C0 1D 0D 12 84 12 0A C2 1E C2 5E CA 0A C2 22 00 +F4 C7 F4 C6 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A +C8 1D 3E 4F 3D 41 30 4D 66 C5 05 2E 22 00 0D 12 +84 12 DE C6 0A C2 80 C5 5E CA 70 C7 00 00 04 3C +23 00 B2 40 B2 1D B2 1D 30 4D DA C6 02 23 1B 42 +BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D +18 42 B2 1D C8 4A 00 00 30 4D 2C C7 04 23 53 00 +0D 12 84 12 2E C7 68 C7 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 5C C7 04 23 3E 00 9F 42 B2 1D 00 00 +3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 76 C7 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 4E C5 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 22 C7 +A2 C5 90 C7 60 C7 8C C6 9E C7 7A C7 80 C5 70 C7 +0A C7 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D E2 C7 0E 3E +4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 +66 C9 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 68 C9 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 C9 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C6 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C2 02 CA 1A C7 BE C9 9C 26 -3D 40 C6 C9 DE 3E C8 C9 0A 4E 3E 4F 3D 40 E2 C9 -36 27 3D 40 B8 C9 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 C9 3E 4F 3D 40 B8 C9 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CB CC 3F -EC C9 86 12 20 00 D4 C5 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C C5 BC C2 -B2 C9 B2 C5 E4 C5 14 C2 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 EC C5 -14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C3 -3A C2 2C CA 08 CA 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C6 0A C2 2A C3 48 C9 4E C6 7C C7 01 27 -0D 12 84 12 02 CA 1A C7 82 C7 34 C2 00 CA 4E C6 -00 00 83 5B 27 5D 0D 12 84 12 80 CA 0A C2 0A C2 -48 C9 48 C9 4E C6 92 CA 81 5B 82 43 BE 1D 30 4D -FA C5 01 5D B2 43 BE 1D 30 4D B2 CA 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CA 1A C7 82 C7 96 C5 34 C2 -00 CA E4 C5 34 C2 F4 CA 0A C2 0A C2 48 C9 48 C9 -0A C2 48 C9 48 C9 4E C6 A8 CA 01 3A 30 12 44 CB -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 CA 1A C7 -12 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C3 FA CA 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A C2 4E C6 48 C9 56 CB AA CA 4E C6 -A8 C9 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 C9 06 43 52 45 41 54 -45 00 B0 12 00 CB BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CB 04 43 4F 44 45 00 B0 12 00 CB A2 82 -C6 1D 0D 12 84 12 F2 CD CC CD 4E C6 A2 CB 07 48 -44 4E 43 4F 44 45 B2 40 D0 CD DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CB 0C CE -2A CE 4E C6 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C CE 2A CE 4E C6 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE CB 85 48 49 32 4C 4F 0D 12 84 12 28 C2 9A CD -48 C9 AA CA E2 CB 4E C6 88 CB 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CC 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C2 00 00 C6 C5 02 CA 1A C7 98 C9 -8E C5 34 C2 02 CD 9C C5 14 C2 06 5B 54 48 45 4E -5D 00 74 CC DC CC 98 CC BA CC 4E C6 9C C5 14 C2 -06 5B 45 4C 53 45 5D 00 74 CC F2 CC 98 CC B8 CC -4E C6 14 C2 04 5B 49 46 5D 00 74 CC BA CC 3A C2 -B8 CC 70 C5 14 C2 05 0D 0A 6B 6F 20 4A C5 BC C2 -AC C2 3A C2 BA CC A8 CC 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CD 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CA 1A C7 82 C7 -26 CD 4E C6 2C CD 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CD DE C5 4E C6 5E CD B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A C9 06 4D -41 52 4B 45 52 00 B0 12 00 CB BA 40 85 12 FC FF -BA 40 5C CD FE FF 28 83 8A 48 00 00 BA 40 AA C2 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A C2 -CA 1D D6 C5 4E C6 85 12 9E CD 66 CA D4 CB 10 C5 -7E CA 52 CC D2 C4 6E CD 00 C7 96 CE AA CE 8A C6 -14 C7 00 00 46 CD BC CA E2 C7 00 00 85 12 9E CD -66 D4 CC D4 0E D4 1C D5 D4 D3 00 00 A0 D1 00 00 -E4 D5 C8 D5 38 D4 76 D4 B0 D2 00 00 00 00 38 D5 -CA CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 CD 24 CE 2A CE 3A CE 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CA -09 50 57 52 5F 53 54 41 54 45 85 12 32 CE F0 D5 -CE C6 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E CE F3 3F 70 CE 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E CE 30 4D 82 CE 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 CF FE FF 29 83 B9 40 -E2 C3 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C3 B2 49 FA C2 B2 49 02 C2 B2 49 00 C4 B2 49 -EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 92 D3 -30 01 B2 43 06 02 B2 40 EF 7F 02 02 B2 43 26 02 -B2 D0 08 FF 22 02 F2 D3 26 03 F2 40 F0 00 22 03 -F2 40 A5 00 61 01 B2 40 80 00 62 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 92 C3 -B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 1E 42 -08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 C2 FE C3 -38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D -09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A -C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 1A C7 -82 C7 DE C5 34 C2 E0 CF 3E C8 34 C2 FA CF F4 CF -E2 CF 3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E -01 3C 2E 83 21 52 1B 17 30 41 FC CF B2 41 C4 1D -3E 41 84 12 0A C2 2B 00 1A C7 82 C7 DE C5 34 C2 -18 D0 3E C8 34 C2 00 CA A8 C5 1A C7 3E C8 34 C2 -00 CA 24 D0 3E 5F E7 3F 3E 40 28 00 B0 12 C4 CF -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 -92 92 C0 1D C4 1D 02 20 30 40 6E CB 1C 15 12 12 -C4 1D 92 53 C4 1D 84 12 1A C7 3E C8 34 C2 6C D0 -62 D0 21 53 3E 90 10 00 C6 2B 7F 2D 6E D0 B2 41 -C4 1D C1 3F 0D 12 84 12 02 CA A0 CF 7E D0 0C 43 -1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 -27 20 92 53 C4 1D B0 12 C4 CF 3C 40 00 03 0E 93 +2F 53 30 4D 1E C7 03 5C 92 42 C2 1D C6 1D 30 4D +0D 12 84 12 84 C2 A2 C5 F4 C7 B0 C2 38 CB 5C C8 +22 CA 0A 4E 3E 4F 3D 40 3C CA 6D 27 3D 40 16 CA +1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 3E CA 3E 4F +3D 40 16 CA 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 14 CC 2A 3C 06 CA 02 2C A2 53 +C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 5C CA +0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E +1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D 98 C7 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D BE C6 0A 41 +4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C +0E 43 84 12 1E C2 02 0D 0A 00 80 C5 94 C2 10 CA +9E C6 C8 C6 1E C2 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C3 32 C2 0A C2 40 FF D0 C6 1E C2 09 46 +52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 D4 CA BE CA +0D 41 42 4F 52 54 22 00 0D 12 84 12 DE C6 0A C2 +08 C3 5E CA 70 C7 EE C7 02 27 0D 12 84 12 A2 C5 +F4 C7 5C C8 B0 C2 3A CB 02 C7 46 CA 68 C6 07 5B +27 5D 0D 12 84 12 2A CB 0A C2 0A C2 5E CA 5E CA +70 C7 3E CB 03 5B 82 43 BC 1D 30 4D 00 00 02 5D +B2 43 BC 1D 30 4D B6 C6 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 A2 C5 F4 C7 5C C8 B0 C2 3A CB +C8 C6 AC C2 92 CB 0A C2 0A C2 5E CA 5E CA 0A C2 +5E CA 5E CA 70 C7 00 00 02 3A 30 12 E8 CB 92 B3 +C8 1D A2 63 C8 1D 0D 12 84 12 A2 C5 F4 C7 B0 CB +3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D +2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 +84 12 1E C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C3 54 CB 03 3B 82 93 BC 1D F4 26 +0D 12 84 12 0A C2 70 C7 5E CA FA CB 56 CB 70 C7 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D +D8 D3 00 00 30 4D A8 CA 0C 43 52 45 41 54 45 00 +B0 12 9E CB BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +7A C5 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D 98 CB 0E 3A 4E 4F +4E 41 4D 45 30 12 E8 CB 2F 83 8F 4E 00 00 1A 42 +C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +32 CC 05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 +2A CB B4 CC 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +42 CB 0A C2 B6 CC 5E CA 70 C7 48 CC 08 43 4F 44 +45 00 B0 12 9E CB A2 82 C8 1D 61 3C 8A C7 0E 48 +44 4E 43 4F 44 45 B2 40 A2 CD CC 1D F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 FA CB 00 CD +3D 41 92 42 D0 1D CC 1D 5D 3C CC CC 0E 43 4F 44 +45 4E 4E 4D 30 12 D6 CC B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F DE CC +0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A +FE FF 82 43 BC 1D B9 3F 6A CD B2 40 7C CD D0 1D +82 4E CE 1D 30 40 02 C7 85 12 68 CD 68 CB 10 CB +FA CD 0C CD 62 CC AC C7 56 C8 28 CB 50 CD A2 CC +7C CC 18 CC 70 CA 84 CE AE C8 00 00 00 00 85 12 +68 CD FE D4 82 D3 E2 D4 AA D2 06 D3 54 D3 30 D4 +3C D4 CC D1 F0 D2 00 00 00 00 3E CD BC D0 00 00 +58 D4 9C CD B2 40 7C CD CE 1D 82 43 D0 1D 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 +42 18 B0 12 D0 CD 30 4D E2 CD 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 D0 CD +1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 0E C4 FE FF 29 83 B9 40 +FA C3 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +EE FF 3B 40 10 00 3A 40 3A 18 B0 12 D4 CD 82 43 +4A 18 C7 3F 76 CE B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 5E CB 0C 4D 41 52 4B 45 52 00 12 12 C6 1D +0D 12 84 12 A2 C5 F4 C7 5C C8 AC C2 A2 CE 96 C6 +36 CA A4 CE 3E 4F 3D 41 B2 41 C6 1D B0 12 9E CB +BA 40 85 12 FC FF BA 40 74 CE FE FF 28 83 8A 48 +00 00 BA 40 82 C2 02 00 A2 52 C8 1D 18 42 B4 1D +19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 1D 84 12 F4 C7 5C C8 AC C2 0E CF EE CE 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +74 CE 00 00 01 20 3E 52 2E 83 21 53 30 41 06 C9 +AC C2 16 CF 0A CF 18 CF B2 41 C6 1D 30 41 92 83 +C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 DE CE 15 20 +3E 40 2B 00 B0 12 DE CE 06 20 3E 40 2D 00 B0 12 +DE CE 92 83 C6 1D 0E 12 1E 41 02 00 84 12 F4 C7 +06 C9 AC C2 3A CB 58 CF 3E 51 3A 17 30 41 B0 12 +1E CF 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 +29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 F4 C7 +06 C9 AC C2 90 CF 88 CF 3E 90 10 00 E6 2B 7C 2D +92 CF A2 41 C6 1D E1 3F 03 20 B0 12 76 CF 43 3C +7A 90 23 00 24 20 B0 12 26 CF 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D -7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 -C4 CF ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 -C4 1D B0 12 4C D0 0C 20 3C 50 10 00 3E 40 2B 00 -B0 12 4C D0 92 92 C0 1D C4 1D 02 24 92 53 C4 1D -8E 10 0C 5E DA 3F B0 12 4C D0 FA 23 3C 50 10 00 -B0 12 28 D0 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D -0D 12 84 12 02 CA A0 CF 4A D1 FE 90 26 00 00 00 -3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 4C D0 -E0 23 3C 50 80 00 B0 12 28 D0 DB 3F 00 00 04 52 -45 54 49 00 0D 12 84 12 0A C2 00 13 48 C9 4E C6 -0A C2 2C 00 74 D0 40 D1 8A D1 09 4B 2E 4E 0E DC -A2 3F 40 CC 03 4D 4F 56 85 12 80 D1 00 40 94 D1 -05 4D 4F 56 2E 42 85 12 80 D1 40 40 00 00 03 41 -44 44 85 12 80 D1 00 50 AE D1 05 41 44 44 2E 42 -85 12 80 D1 40 50 BA D1 04 41 44 44 43 00 85 12 -80 D1 00 60 C8 D1 06 41 44 44 43 2E 42 00 85 12 -80 D1 40 60 6E D1 04 53 55 42 43 00 85 12 80 D1 -00 70 E6 D1 06 53 55 42 43 2E 42 00 85 12 80 D1 -40 70 F4 D1 03 53 55 42 85 12 80 D1 00 80 04 D2 -05 53 55 42 2E 42 85 12 80 D1 40 80 16 CC 03 43 -4D 50 85 12 80 D1 00 90 1E D2 05 43 4D 50 2E 42 -85 12 80 D1 40 90 00 CC 04 44 41 44 44 00 85 12 -80 D1 00 A0 38 D2 06 44 41 44 44 2E 42 00 85 12 -80 D1 40 A0 2A D2 03 42 49 54 85 12 80 D1 00 B0 -56 D2 05 42 49 54 2E 42 85 12 80 D1 40 B0 62 D2 -03 42 49 43 85 12 80 D1 00 C0 70 D2 05 42 49 43 -2E 42 85 12 80 D1 40 C0 7C D2 03 42 49 53 85 12 -80 D1 00 D0 8A D2 05 42 49 53 2E 42 85 12 80 D1 -40 D0 00 00 03 58 4F 52 85 12 80 D1 00 E0 A4 D2 -05 58 4F 52 2E 42 85 12 80 D1 40 E0 D6 D1 03 41 -4E 44 85 12 80 D1 00 F0 BE D2 05 41 4E 44 2E 42 -85 12 80 D1 40 F0 02 CA 74 D0 DC D2 0A 4C 3C F0 -70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 10 D2 03 52 -52 43 85 12 D6 D2 00 10 EE D2 05 52 52 43 2E 42 -85 12 D6 D2 40 10 FA D2 04 53 57 50 42 00 85 12 -D6 D2 80 10 08 D3 03 52 52 41 85 12 D6 D2 00 11 -16 D3 05 52 52 41 2E 42 85 12 D6 D2 40 11 22 D3 -03 53 58 54 85 12 D6 D2 80 11 00 00 04 50 55 53 -48 00 85 12 D6 D2 00 12 3C D3 06 50 55 53 48 2E -42 00 85 12 D6 D2 40 12 96 D2 04 43 41 4C 4C 00 -85 12 D6 D2 80 12 1A 53 0E 4A 0D 12 84 12 C4 C6 -14 C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 -36 C3 30 D3 03 53 3E 3D 86 12 00 38 84 D3 02 53 -3C 00 86 12 00 34 4A D3 03 30 3E 3D 86 12 00 30 -98 D3 02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 -86 12 00 2C AC D3 03 55 3E 3D 86 12 00 28 A2 D3 -03 30 3C 3E 86 12 00 24 C0 D3 02 30 3D 00 86 12 -00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 0E 4A 30 4D B6 D3 04 54 48 45 4E 00 -1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 -3A 90 00 02 B1 2F 88 DA 00 00 30 4D 46 D2 04 45 -4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 -C6 1D 2F 83 8F 4A 00 00 E3 3F 5A D3 05 42 45 47 -49 4E 30 40 28 C2 EA D3 05 55 4E 54 49 4C 3A 4F -08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 -00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 -C6 1D 30 4D CA D2 05 41 47 41 49 4E 0A 4E 38 40 -00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 -D8 D3 A8 C5 4E C6 8E D3 06 52 45 50 45 41 54 00 -0D 12 84 12 6C D4 F0 D3 4E C6 9C D4 3D 41 08 4E -3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 -30 4D 2C D4 03 42 57 31 85 12 9A D4 00 00 B4 D4 -03 42 57 32 85 12 9A D4 00 00 C0 D4 03 42 57 33 -85 12 9A D4 00 00 D8 D4 3D 41 1A 42 C6 1D 28 4E -B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A -00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 D6 D4 -00 00 F8 D4 03 46 57 32 85 12 D6 D4 00 00 04 D5 -03 46 57 33 85 12 D6 D4 00 00 10 D5 04 47 4F 54 +C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 26 CF F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 72 CF 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 76 CF 92 92 C2 1D C6 1D +02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 5E CF F2 3F 03 20 B0 12 76 CF F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +5E CF EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 +20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 +FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C2 00 13 +5E CA 70 C7 0A C2 2C 00 54 D0 98 CF A2 C5 5E D0 +36 D0 A4 D0 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 94 D0 00 40 B0 D0 0A 4D 4F 56 +2E 42 85 12 94 D0 40 40 00 00 06 41 44 44 85 12 +94 D0 00 50 CA D0 0A 41 44 44 2E 42 85 12 94 D0 +40 50 D6 D0 08 41 44 44 43 00 85 12 94 D0 00 60 +E4 D0 0C 41 44 44 43 2E 42 00 85 12 94 D0 40 60 +1C CD 08 53 55 42 43 00 85 12 94 D0 00 70 02 D1 +0C 53 55 42 43 2E 42 00 85 12 94 D0 40 70 10 D1 +06 53 55 42 85 12 94 D0 00 80 20 D1 0A 53 55 42 +2E 42 85 12 94 D0 40 80 2C D1 06 43 4D 50 85 12 +94 D0 00 90 3A D1 0A 43 4D 50 2E 42 85 12 94 D0 +40 90 00 00 08 44 41 44 44 00 85 12 94 D0 00 A0 +54 D1 0C 44 41 44 44 2E 42 00 85 12 94 D0 40 A0 +82 D0 06 42 49 54 85 12 94 D0 00 B0 72 D1 0A 42 +49 54 2E 42 85 12 94 D0 40 B0 7E D1 06 42 49 43 +85 12 94 D0 00 C0 8C D1 0A 42 49 43 2E 42 85 12 +94 D0 40 C0 98 D1 06 42 49 53 85 12 94 D0 00 D0 +A6 D1 0A 42 49 53 2E 42 85 12 94 D0 40 D0 00 00 +06 58 4F 52 85 12 94 D0 00 E0 C0 D1 0A 58 4F 52 +2E 42 85 12 94 D0 40 E0 F2 D0 06 41 4E 44 85 12 +94 D0 00 F0 DA D1 0A 41 4E 44 2E 42 85 12 94 D0 +40 F0 A2 C5 54 D0 98 CF FA D1 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F B2 D1 06 52 52 43 +85 12 F2 D1 00 10 0C D2 0A 52 52 43 2E 42 85 12 +F2 D1 40 10 46 D1 08 53 57 50 42 00 85 12 F2 D1 +80 10 18 D2 06 52 52 41 85 12 F2 D1 00 11 34 D2 +0A 52 52 41 2E 42 85 12 F2 D1 40 11 26 D2 06 53 +58 54 85 12 F2 D1 80 11 00 00 08 50 55 53 48 00 +85 12 F2 D1 00 12 5A D2 0C 50 55 53 48 2E 42 00 +85 12 F2 D1 40 12 4E D2 08 43 41 4C 4C 00 85 12 +F2 D1 80 12 1A 53 0E 4A 84 12 E4 C7 1E C2 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C3 78 D2 +06 53 3E 3D 86 12 00 38 A0 D2 04 53 3C 00 86 12 +00 34 68 D2 06 30 3E 3D 86 12 00 30 B4 D2 04 30 +3C 00 86 12 00 30 F0 CC 04 55 3C 00 86 12 00 2C +C8 D2 06 55 3E 3D 86 12 00 28 BE D2 06 30 3C 3E +86 12 00 24 DC D2 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D +0E 4A 30 4D 62 D1 08 54 48 45 4E 00 1A 42 C8 1D +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D D2 D2 08 45 4C 53 45 00 +1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 +8F 4A 00 00 E3 3F 40 D2 0A 42 45 47 49 4E 30 40 +32 C2 2A D3 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D +E6 D1 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 F4 D2 8A C6 +70 C7 48 D3 0C 52 45 50 45 41 54 00 0D 12 84 12 +88 D3 0C D3 70 C7 B8 D3 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D A4 D3 +06 42 57 31 85 12 B6 D3 00 00 D0 D3 06 42 57 32 +85 12 B6 D3 00 00 DC D3 06 42 57 33 85 12 B6 D3 +00 00 F4 D3 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 +B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 F2 D3 +00 00 18 D4 06 46 57 32 85 12 F2 D3 00 00 24 D4 +06 46 57 33 85 12 F2 D3 00 00 92 D3 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 -80 CA DC C9 4E C6 00 00 05 3F 47 4F 54 4F 3E 90 +2A CB 36 CA 70 C7 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 -00 08 EC 3F 02 CA A0 CF 5A D5 92 53 C4 1D 3E 40 -2C 00 84 12 1A C7 3E C8 34 C2 00 CA 36 D1 70 D5 -0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C -59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E -AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 88 D4 04 52 -52 43 4D 00 85 12 54 D5 50 00 9E D5 04 52 52 41 -4D 00 85 12 54 D5 50 01 AC D5 04 52 4C 41 4D 00 -85 12 54 D5 50 02 BA D5 04 52 52 55 4D 00 85 12 -54 D5 50 03 CA D3 05 50 55 53 48 4D 85 12 54 D5 -00 15 D6 D5 04 50 4F 50 4D 00 85 12 54 D5 00 17 +00 08 EC 3F 5E D0 0A C2 2C 00 F4 C7 06 C9 AC C2 +3A CB A2 C5 54 D0 36 D0 8A D4 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E E8 D3 08 52 52 43 4D 00 85 12 +74 D4 50 00 B8 D4 08 52 52 41 4D 00 85 12 74 D4 +50 01 C6 D4 08 52 4C 41 4D 00 85 12 74 D4 50 02 +D4 D4 08 52 52 55 4D 00 85 12 74 D4 50 03 E6 D2 +0A 50 55 53 48 4D 85 12 74 D4 00 15 F0 D4 08 50 +4F 50 4D 00 85 12 74 D4 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 82 C4 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 08 CF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 CA C4 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 0E C4 q diff --git a/binaries/MSP_EXP430FR5739_16MHz_UART.txt b/binaries/MSP_EXP430FR5739_16MHz_UART.txt deleted file mode 100644 index 720a181..0000000 --- a/binaries/MSP_EXP430FR5739_16MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 06 D6 02 CE 34 01 -10 00 41 B3 94 C3 AA C2 DA C3 9C C3 94 C4 06 D6 -02 CE 7A C4 92 C5 24 C5 FE C4 3C 1D 60 C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 -@C200 -B0 12 DA C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 78 C4 B2 49 90 C5 B2 49 22 C5 B2 49 FC C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C3 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 C2 0A C2 DE 1D E0 C5 32 C5 -14 C2 04 1B 5B 37 6D 00 5C C5 A8 C5 34 C2 86 C3 -14 C2 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C5 A0 C6 5C C5 14 C2 04 1B 5B 30 6D 00 -5C C5 28 CA 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 03 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C3 04 57 41 52 4D 00 B0 12 -9C C3 84 12 14 C2 07 0D 0A 1B 5B 37 6D 23 5C C5 -D6 C6 14 C2 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C5 -0A C2 40 FF 28 C2 D4 C5 A0 C6 14 C2 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C2 86 C3 00 00 06 41 -43 43 45 50 54 00 30 40 7A C4 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C4 3C 40 D2 C4 -5D 15 B6 3E 21 52 3A 17 58 42 CC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 -C2 48 CE 05 30 4D C8 C4 2D 83 92 B3 DC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 DC 05 -FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C4 2F 83 -8F 4E 00 00 B0 12 DA C3 92 B3 DC 05 FD 27 1E 42 -CC 05 B0 12 C8 C3 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C5 08 4E 3E 4F C8 3F 1A C5 04 45 43 48 -4F 00 B2 40 C2 48 C0 C4 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C4 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C5 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C5 7A C5 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C3 02 43 52 00 30 40 -92 C5 0D 12 84 12 14 C2 02 0D 0A 00 5C C5 60 C6 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C4 01 40 -2E 4E 30 4D DE C5 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A C5 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A C6 02 23 53 00 0D 12 -84 12 1C C6 56 C6 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C6 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C5 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C6 4E C6 EE C2 8E C6 6A C6 5C C5 14 CA 20 C5 -60 C6 40 C5 01 2E 0E 93 E3 37 38 43 E2 3F 88 C6 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 -5A C9 0A C2 22 00 2C C7 FA C6 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 C6 82 2E 22 00 0D 12 84 12 E4 C6 0A C2 5C C5 -5A C9 60 C6 18 C4 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE C8 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 C8 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 C9 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C6 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C2 14 CA 2C C7 D0 C9 -9C 26 3D 40 D8 C9 DE 3E DA C9 0A 4E 3E 4F 3D 40 -F4 C9 36 27 3D 40 CA C9 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 C9 3E 4F 3D 40 CA C9 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CB -CC 3F FE C9 86 12 20 00 E6 C5 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E C5 -BC C2 C4 C9 C4 C5 F6 C5 14 C2 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 -FE C5 14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C3 3A C2 3E CA 1A CA 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C6 0A C2 2A C3 5A C9 60 C6 8E C7 -01 27 0D 12 84 12 14 CA 2C C7 94 C7 34 C2 12 CA -60 C6 00 00 83 5B 27 5D 0D 12 84 12 92 CA 0A C2 -0A C2 5A C9 5A C9 60 C6 A4 CA 81 5B 82 43 BE 1D -30 4D 0C C6 01 5D B2 43 BE 1D 30 4D C4 CA 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CA 2C C7 94 C7 A8 C5 -34 C2 12 CA F6 C5 34 C2 06 CB 0A C2 0A C2 5A C9 -5A C9 0A C2 5A C9 5A C9 60 C6 BA CA 01 3A 30 12 -56 CB 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 CA -2C C7 24 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C3 0C CB 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A C2 60 C6 5A C9 68 CB BC CA -60 C6 BA C9 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 C9 06 43 52 45 -41 54 45 00 B0 12 12 CB BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CB 04 43 4F 44 45 00 B0 12 12 CB -A2 82 C6 1D 0D 12 84 12 04 CE DE CD 60 C6 B4 CB -07 48 44 4E 43 4F 44 45 B2 40 E2 CD DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CB -1E CE 3C CE 60 C6 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E CE 3C CE 60 C6 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 CC 85 48 49 32 4C 4F 0D 12 84 12 28 C2 -AC CD 5A C9 BC CA F4 CB 60 C6 9A CB 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CC 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C2 00 00 D8 C5 14 CA 2C C7 -AA C9 A0 C5 34 C2 14 CD AE C5 14 C2 06 5B 54 48 -45 4E 5D 00 86 CC EE CC AA CC CC CC 60 C6 AE C5 -14 C2 06 5B 45 4C 53 45 5D 00 86 CC 04 CD AA CC -CA CC 60 C6 14 C2 04 5B 49 46 5D 00 86 CC CC CC -3A C2 CA CC 82 C5 14 C2 05 0D 0A 6B 6F 20 5C C5 -BC C2 AC C2 3A C2 CC CC BA CC 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CD 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CA 2C C7 -94 C7 38 CD 60 C6 3E CD 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CD F0 C5 60 C6 70 CD -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C C9 -06 4D 41 52 4B 45 52 00 B0 12 12 CB BA 40 85 12 -FC FF BA 40 6E CD FE FF 28 83 8A 48 00 00 BA 40 -AA C2 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A C2 CA 1D E8 C5 60 C6 85 12 B0 CD 78 CA E6 CB -2C C5 90 CA 64 CC F6 C4 80 CD 12 C7 A8 CE BC CE -9C C6 26 C7 00 00 58 CD CE CA F4 C7 00 00 85 12 -B0 CD 7C D4 E2 D4 24 D4 32 D5 EA D3 00 00 B6 D1 -00 00 FA D5 DE D5 4E D4 8C D4 C6 D2 00 00 00 00 -4E D5 DC CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 CD 36 CE 3C CE 4C CE 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CA 09 50 57 52 5F 53 54 41 54 45 85 12 44 CE -06 D6 E0 C6 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 CE F3 3F 82 CE 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 CE 30 4D 94 CE 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A CF FE FF 29 83 -B9 40 02 C4 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C4 B2 49 FA C2 B2 49 02 C2 B2 49 20 C4 -B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 -92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 -05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 -F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 80 00 -62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 -40 00 A1 04 1E 42 08 18 82 43 08 18 1E D2 9E 01 -B0 12 F8 C2 1E C4 38 40 C0 1D 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 12 12 -C4 1D 84 12 2C C7 94 C7 F0 C5 34 C2 F6 CF 50 C8 -34 C2 10 D0 0A D0 F8 CF 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -12 D0 B2 41 C4 1D 3E 41 84 12 0A C2 2B 00 2C C7 -94 C7 F0 C5 34 C2 2E D0 50 C8 34 C2 12 CA BA C5 -2C C7 50 C8 34 C2 12 CA 3A D0 3E 5F E7 3F 3E 40 -28 00 B0 12 DA CF 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 30 40 -80 CB 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 2C C7 -50 C8 34 C2 82 D0 78 D0 21 53 3E 90 10 00 C6 2B -7F 2D 84 D0 B2 41 C4 1D C1 3F 0D 12 84 12 14 CA -B6 CF 94 D0 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E -3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 DA CF -3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 -3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 -3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 -3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 -3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 -92 53 C4 1D B0 12 DA CF ED 3F 7A 90 40 00 16 20 -3C 40 20 00 92 53 C4 1D B0 12 62 D0 0C 20 3C 50 -10 00 3E 40 2B 00 B0 12 62 D0 92 92 C0 1D C4 1D -02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 62 D0 -FA 23 3C 50 10 00 B0 12 3E D0 EF 3F 0C 43 1B 42 -C6 1D A2 53 C6 1D 0D 12 84 12 14 CA B6 CF 60 D1 -FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 -C7 3F B0 12 62 D0 E0 23 3C 50 80 00 B0 12 3E D0 -DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 0A C2 -00 13 5A C9 60 C6 0A C2 2C 00 8A D0 56 D1 A0 D1 -09 4B 2E 4E 0E DC A2 3F 52 CC 03 4D 4F 56 85 12 -96 D1 00 40 AA D1 05 4D 4F 56 2E 42 85 12 96 D1 -40 40 00 00 03 41 44 44 85 12 96 D1 00 50 C4 D1 -05 41 44 44 2E 42 85 12 96 D1 40 50 D0 D1 04 41 -44 44 43 00 85 12 96 D1 00 60 DE D1 06 41 44 44 -43 2E 42 00 85 12 96 D1 40 60 84 D1 04 53 55 42 -43 00 85 12 96 D1 00 70 FC D1 06 53 55 42 43 2E -42 00 85 12 96 D1 40 70 0A D2 03 53 55 42 85 12 -96 D1 00 80 1A D2 05 53 55 42 2E 42 85 12 96 D1 -40 80 28 CC 03 43 4D 50 85 12 96 D1 00 90 34 D2 -05 43 4D 50 2E 42 85 12 96 D1 40 90 12 CC 04 44 -41 44 44 00 85 12 96 D1 00 A0 4E D2 06 44 41 44 -44 2E 42 00 85 12 96 D1 40 A0 40 D2 03 42 49 54 -85 12 96 D1 00 B0 6C D2 05 42 49 54 2E 42 85 12 -96 D1 40 B0 78 D2 03 42 49 43 85 12 96 D1 00 C0 -86 D2 05 42 49 43 2E 42 85 12 96 D1 40 C0 92 D2 -03 42 49 53 85 12 96 D1 00 D0 A0 D2 05 42 49 53 -2E 42 85 12 96 D1 40 D0 00 00 03 58 4F 52 85 12 -96 D1 00 E0 BA D2 05 58 4F 52 2E 42 85 12 96 D1 -40 E0 EC D1 03 41 4E 44 85 12 96 D1 00 F0 D4 D2 -05 41 4E 44 2E 42 85 12 96 D1 40 F0 14 CA 8A D0 -F2 D2 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA -4F 3F 26 D2 03 52 52 43 85 12 EC D2 00 10 04 D3 -05 52 52 43 2E 42 85 12 EC D2 40 10 10 D3 04 53 -57 50 42 00 85 12 EC D2 80 10 1E D3 03 52 52 41 -85 12 EC D2 00 11 2C D3 05 52 52 41 2E 42 85 12 -EC D2 40 11 38 D3 03 53 58 54 85 12 EC D2 80 11 -00 00 04 50 55 53 48 00 85 12 EC D2 00 12 52 D3 -06 50 55 53 48 2E 42 00 85 12 EC D2 40 12 AC D2 -04 43 41 4C 4C 00 85 12 EC D2 80 12 1A 53 0E 4A -0D 12 84 12 D6 C6 14 C2 0D 6F 75 74 20 6F 66 20 -62 6F 75 6E 64 73 36 C3 46 D3 03 53 3E 3D 86 12 -00 38 9A D3 02 53 3C 00 86 12 00 34 60 D3 03 30 -3E 3D 86 12 00 30 AE D3 02 30 3C 00 86 12 00 30 -00 00 02 55 3C 00 86 12 00 2C C2 D3 03 55 3E 3D -86 12 00 28 B8 D3 03 30 3C 3E 86 12 00 24 D6 D3 -02 30 3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 -C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D CC D3 -04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 -29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 -30 4D 5C D2 04 45 4C 53 45 00 1A 42 C6 1D BA 40 -00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F -70 D3 05 42 45 47 49 4E 30 40 28 C2 00 D4 05 55 -4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 -0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA -89 48 00 00 A2 53 C6 1D 30 4D E0 D2 05 41 47 41 -49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 -4C 45 0D 12 84 12 EE D3 BA C5 60 C6 A4 D3 06 52 -45 50 45 41 54 00 0D 12 84 12 82 D4 06 D4 60 C6 -B2 D4 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F -98 42 C6 1D 00 00 30 4D 42 D4 03 42 57 31 85 12 -B0 D4 00 00 CA D4 03 42 57 32 85 12 B0 D4 00 00 -D6 D4 03 42 57 33 85 12 B0 D4 00 00 EE D4 3D 41 -1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F 00 00 -A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 -57 31 85 12 EC D4 00 00 0E D5 03 46 57 32 85 12 -EC D4 00 00 1A D5 03 46 57 33 85 12 EC D4 00 00 -26 D5 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 -00 3C 0D 12 84 12 92 CA EE C9 60 C6 00 00 05 3F -47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 -00 10 EF 27 3E E0 00 08 EC 3F 14 CA B6 CF 70 D5 -92 53 C4 1D 3E 40 2C 00 84 12 2C C7 50 C8 34 C2 -12 CA 4C D1 86 D5 0A 4E 3E 4F 1A 83 F7 32 29 4E -59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 -10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 -A6 3E 9E D4 04 52 52 43 4D 00 85 12 6A D5 50 00 -B4 D5 04 52 52 41 4D 00 85 12 6A D5 50 01 C2 D5 -04 52 4C 41 4D 00 85 12 6A D5 50 02 D0 D5 04 52 -52 55 4D 00 85 12 6A D5 50 03 E0 D3 05 50 55 53 -48 4D 85 12 6A D5 00 15 EC D5 04 50 4F 50 4D 00 -85 12 6A D5 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -94 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 1A CF -q diff --git a/binaries/MSP_EXP430FR5739_1MHz_115200.txt b/binaries/MSP_EXP430FR5739_1MHz_115200.txt new file mode 100644 index 0000000..18c5883 --- /dev/null +++ b/binaries/MSP_EXP430FR5739_1MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 59 +CC C4 7E C3 84 C3 54 C3 3C C5 2A D5 E2 CD 9C CD +9C CD B2 C4 70 C5 38 C5 3C 1D E0 1C 90 C7 B6 C2 +C4 C2 AC C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +3C C5 2A D5 E2 CD 9C CD 9C CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +96 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 C4 B2 49 +6E C5 B2 49 36 C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 56 CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3C C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 B6 C6 AC C2 52 C3 7E C5 1E C2 04 1B +5B 37 6D 00 A0 C5 A0 C5 1E C2 04 1B 5B 30 6D 00 +A0 C5 EC CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 7E C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 A0 C5 04 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A0 C5 0A C2 40 FF 32 C2 +CC C6 D0 C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 33 00 +66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 +92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 +39 40 00 04 29 83 89 43 00 1C FC 23 19 42 9E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 C2 86 C3 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 C4 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 10 C5 3C 40 1C C5 5D 15 9A 3E 21 52 3A 17 +58 42 CC 05 48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 +13 00 CE 05 E2 D2 03 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D +12 C5 2D 83 92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 DC 05 FD 27 58 42 CC 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 38 C5 30 12 4E C5 A2 B3 DC 05 +FD 27 B2 40 11 00 CE 05 E2 C2 03 02 30 41 2F 83 +8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 D8 C4 1E 42 +CC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 70 C5 +08 4E 3E 4F C7 3F 66 C5 08 45 43 48 4F 00 B2 40 +C2 48 0A C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 0A C5 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 B0 C5 29 4F 8F 4E 00 00 7E 49 DE 3F +B2 C5 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +70 22 F9 98 00 00 6D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 64 22 9B 24 30 C5 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A C2 00 00 D0 C6 +C2 C5 14 C8 CE CA B0 C2 3E C6 14 C2 06 5B 54 48 +45 4E 5D 00 C6 C5 1C C6 E2 C5 00 C6 14 C2 06 5B +45 4C 53 45 5D 00 C6 C5 2E C6 E2 C5 FE C5 1E C2 +04 5B 49 46 5D 00 C6 C5 00 C6 B2 C2 FE C5 1E C2 +05 0D 6B 6F 20 0A A0 C5 9A C2 84 C2 B2 C2 00 C6 +EE C5 0D 5B 54 48 45 4E 5D 00 30 4D 52 C6 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 5E C6 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 C2 C5 14 C8 +7C C8 20 CA 90 C7 6E C6 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 C2 C5 14 C8 7C C8 A0 C6 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D A6 C4 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 C3 05 53 22 00 82 43 +C0 1D 0D 12 84 12 0A C2 1E C2 7E CA 0A C2 22 00 +14 C8 14 C7 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A +C8 1D 3E 4F 3D 41 30 4D 88 C5 05 2E 22 00 0D 12 +84 12 FE C6 0A C2 A0 C5 7E CA 90 C7 00 00 04 3C +23 00 B2 40 B2 1D B2 1D 30 4D FA C6 02 23 1B 42 +BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D +18 42 B2 1D C8 4A 00 00 30 4D 4C C7 04 23 53 00 +0D 12 84 12 4E C7 88 C7 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 7C C7 04 23 3E 00 9F 42 B2 1D 00 00 +3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 96 C7 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 78 C5 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 42 C7 +C2 C5 B0 C7 80 C7 AC C6 BE C7 9A C7 A0 C5 90 C7 +2A C7 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 02 C8 0E 3E +4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 +86 C9 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 88 C9 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 3E C7 03 5C 92 42 C2 1D C6 1D 30 4D +0D 12 84 12 84 C2 C2 C5 14 C8 B0 C2 58 CB 7C C8 +42 CA 0A 4E 3E 4F 3D 40 5C CA 6D 27 3D 40 36 CA +1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 5E CA 3E 4F +3D 40 36 CA 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 34 CC 2A 3C 26 CA 02 2C A2 53 +C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 7C CA +0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E +1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D B8 C7 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D DE C6 0A 41 +4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C +0E 43 84 12 1E C2 02 0D 0A 00 A0 C5 94 C2 30 CA +BE C6 E8 C6 1E C2 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C3 32 C2 0A C2 40 FF F0 C6 1E C2 09 46 +52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 F4 CA DE CA +0D 41 42 4F 52 54 22 00 0D 12 84 12 FE C6 0A C2 +08 C3 7E CA 90 C7 0E C8 02 27 0D 12 84 12 C2 C5 +14 C8 7C C8 B0 C2 5A CB 22 C7 66 CA 88 C6 07 5B +27 5D 0D 12 84 12 4A CB 0A C2 0A C2 7E CA 7E CA +90 C7 5E CB 03 5B 82 43 BC 1D 30 4D 00 00 02 5D +B2 43 BC 1D 30 4D D6 C6 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 C2 C5 14 C8 7C C8 B0 C2 5A CB +E8 C6 AC C2 B2 CB 0A C2 0A C2 7E CA 7E CA 0A C2 +7E CA 7E CA 90 C7 00 00 02 3A 30 12 08 CC 92 B3 +C8 1D A2 63 C8 1D 0D 12 84 12 C2 C5 14 C8 D0 CB +3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D +2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 +84 12 1E C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C3 74 CB 03 3B 82 93 BC 1D F4 26 +0D 12 84 12 0A C2 90 C7 7E CA 1A CC 76 CB 90 C7 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D +D8 D3 00 00 30 4D C8 CA 0C 43 52 45 41 54 45 00 +B0 12 BE CB BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +9A C5 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D B8 CB 0E 3A 4E 4F +4E 41 4D 45 30 12 08 CC 2F 83 8F 4E 00 00 1A 42 +C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +52 CC 05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 +4A CB D4 CC 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +62 CB 0A C2 D6 CC 7E CA 90 C7 68 CC 08 43 4F 44 +45 00 B0 12 BE CB A2 82 C8 1D 61 3C AA C7 0E 48 +44 4E 43 4F 44 45 B2 40 C2 CD CC 1D F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 1A CC 20 CD +3D 41 92 42 D0 1D CC 1D 5D 3C EC CC 0E 43 4F 44 +45 4E 4E 4D 30 12 F6 CC B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F FE CC +0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A +FE FF 82 43 BC 1D B9 3F 8A CD B2 40 9C CD D0 1D +82 4E CE 1D 30 40 22 C7 85 12 88 CD 88 CB 30 CB +1A CE 2C CD 82 CC CC C7 76 C8 48 CB 70 CD C2 CC +9C CC 38 CC 90 CA A4 CE CE C8 00 00 00 00 85 12 +88 CD 1E D5 A2 D3 02 D5 CA D2 26 D3 74 D3 50 D4 +5C D4 EC D1 10 D3 00 00 00 00 5E CD DC D0 00 00 +78 D4 BC CD B2 40 9C CD CE 1D 82 43 D0 1D 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 +42 18 B0 12 F0 CD 30 4D 02 CE 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 F0 CD +1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 C4 FE FF 29 83 B9 40 +F2 C3 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +F0 FF 3B 40 10 00 3A 40 3A 18 B0 12 F4 CD 82 43 +4A 18 C7 3F 96 CE B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 7E CB 0C 4D 41 52 4B 45 52 00 12 12 C6 1D +0D 12 84 12 C2 C5 14 C8 7C C8 AC C2 C2 CE B6 C6 +56 CA C4 CE 3E 4F 3D 41 B2 41 C6 1D B0 12 BE CB +BA 40 85 12 FC FF BA 40 94 CE FE FF 28 83 8A 48 +00 00 BA 40 82 C2 02 00 A2 52 C8 1D 18 42 B4 1D +19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 1D 84 12 14 C8 7C C8 AC C2 2E CF 0E CF 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +94 CE 00 00 01 20 3E 52 2E 83 21 53 30 41 26 C9 +AC C2 36 CF 2A CF 38 CF B2 41 C6 1D 30 41 92 83 +C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 FE CE 15 20 +3E 40 2B 00 B0 12 FE CE 06 20 3E 40 2D 00 B0 12 +FE CE 92 83 C6 1D 0E 12 1E 41 02 00 84 12 14 C8 +26 C9 AC C2 5A CB 78 CF 3E 51 3A 17 30 41 B0 12 +3E CF 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 +29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 14 C8 +26 C9 AC C2 B0 CF A8 CF 3E 90 10 00 E6 2B 7C 2D +B2 CF A2 41 C6 1D E1 3F 03 20 B0 12 96 CF 43 3C +7A 90 23 00 24 20 B0 12 46 CF 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 46 CF F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 92 CF 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 96 CF 92 92 C2 1D C6 1D +02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 7E CF F2 3F 03 20 B0 12 96 CF F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +7E CF EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 +20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 +FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C2 00 13 +7E CA 90 C7 0A C2 2C 00 74 D0 B8 CF C2 C5 7E D0 +56 D0 C4 D0 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 B4 D0 00 40 D0 D0 0A 4D 4F 56 +2E 42 85 12 B4 D0 40 40 00 00 06 41 44 44 85 12 +B4 D0 00 50 EA D0 0A 41 44 44 2E 42 85 12 B4 D0 +40 50 F6 D0 08 41 44 44 43 00 85 12 B4 D0 00 60 +04 D1 0C 41 44 44 43 2E 42 00 85 12 B4 D0 40 60 +3C CD 08 53 55 42 43 00 85 12 B4 D0 00 70 22 D1 +0C 53 55 42 43 2E 42 00 85 12 B4 D0 40 70 30 D1 +06 53 55 42 85 12 B4 D0 00 80 40 D1 0A 53 55 42 +2E 42 85 12 B4 D0 40 80 4C D1 06 43 4D 50 85 12 +B4 D0 00 90 5A D1 0A 43 4D 50 2E 42 85 12 B4 D0 +40 90 00 00 08 44 41 44 44 00 85 12 B4 D0 00 A0 +74 D1 0C 44 41 44 44 2E 42 00 85 12 B4 D0 40 A0 +A2 D0 06 42 49 54 85 12 B4 D0 00 B0 92 D1 0A 42 +49 54 2E 42 85 12 B4 D0 40 B0 9E D1 06 42 49 43 +85 12 B4 D0 00 C0 AC D1 0A 42 49 43 2E 42 85 12 +B4 D0 40 C0 B8 D1 06 42 49 53 85 12 B4 D0 00 D0 +C6 D1 0A 42 49 53 2E 42 85 12 B4 D0 40 D0 00 00 +06 58 4F 52 85 12 B4 D0 00 E0 E0 D1 0A 58 4F 52 +2E 42 85 12 B4 D0 40 E0 12 D1 06 41 4E 44 85 12 +B4 D0 00 F0 FA D1 0A 41 4E 44 2E 42 85 12 B4 D0 +40 F0 C2 C5 74 D0 B8 CF 1A D2 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F D2 D1 06 52 52 43 +85 12 12 D2 00 10 2C D2 0A 52 52 43 2E 42 85 12 +12 D2 40 10 66 D1 08 53 57 50 42 00 85 12 12 D2 +80 10 38 D2 06 52 52 41 85 12 12 D2 00 11 54 D2 +0A 52 52 41 2E 42 85 12 12 D2 40 11 46 D2 06 53 +58 54 85 12 12 D2 80 11 00 00 08 50 55 53 48 00 +85 12 12 D2 00 12 7A D2 0C 50 55 53 48 2E 42 00 +85 12 12 D2 40 12 6E D2 08 43 41 4C 4C 00 85 12 +12 D2 80 12 1A 53 0E 4A 84 12 04 C8 1E C2 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C3 98 D2 +06 53 3E 3D 86 12 00 38 C0 D2 04 53 3C 00 86 12 +00 34 88 D2 06 30 3E 3D 86 12 00 30 D4 D2 04 30 +3C 00 86 12 00 30 10 CD 04 55 3C 00 86 12 00 2C +E8 D2 06 55 3E 3D 86 12 00 28 DE D2 06 30 3C 3E +86 12 00 24 FC D2 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D +0E 4A 30 4D 82 D1 08 54 48 45 4E 00 1A 42 C8 1D +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D F2 D2 08 45 4C 53 45 00 +1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 +8F 4A 00 00 E3 3F 60 D2 0A 42 45 47 49 4E 30 40 +32 C2 4A D3 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D +06 D2 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 14 D3 AA C6 +90 C7 68 D3 0C 52 45 50 45 41 54 00 0D 12 84 12 +A8 D3 2C D3 90 C7 D8 D3 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D C4 D3 +06 42 57 31 85 12 D6 D3 00 00 F0 D3 06 42 57 32 +85 12 D6 D3 00 00 FC D3 06 42 57 33 85 12 D6 D3 +00 00 14 D4 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 +B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 12 D4 +00 00 38 D4 06 46 57 32 85 12 12 D4 00 00 44 D4 +06 46 57 33 85 12 12 D4 00 00 B2 D3 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +4A CB 56 CA 90 C7 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 7E D0 0A C2 2C 00 14 C8 26 C9 AC C2 +5A CB C2 C5 74 D0 56 D0 AA D4 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 08 D4 08 52 52 43 4D 00 85 12 +94 D4 50 00 D8 D4 08 52 52 41 4D 00 85 12 94 D4 +50 01 E6 D4 08 52 4C 41 4D 00 85 12 94 D4 50 02 +F4 D4 08 52 52 55 4D 00 85 12 94 D4 50 03 06 D3 +0A 50 55 53 48 4D 85 12 94 D4 00 15 10 D5 08 50 +4F 50 4D 00 85 12 94 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +CC C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_1MHz_I2C.txt b/binaries/MSP_EXP430FR5739_1MHz_I2C.txt index 32ff7d0..5eb46e5 100644 --- a/binaries/MSP_EXP430FR5739_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5739_1MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF EC D5 F0 CD 34 01 -10 00 41 87 B6 C3 AA C2 B8 C3 8C C3 82 C4 EC D5 -F0 CD 70 C4 80 C5 FE C4 DA C4 3C 1D 4E C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +C6 C4 56 C3 56 C3 58 C3 44 C3 06 D5 BE CD 78 CD +78 CD B4 C4 38 C5 10 C5 3C 1D E0 1C 6C C7 B6 C2 +C4 C2 88 C6 20 00 0A 00 00 1C 56 C3 56 C3 58 C3 +44 C3 06 D5 BE CD 78 CD 78 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C200 -B0 12 B8 C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 6E C4 B2 49 7E C5 B2 49 FC C4 B2 49 D8 C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C3 0E 12 B0 12 -F8 C2 0A C2 DE 1D CE C5 16 C5 EE C2 34 C2 8A C3 -14 C2 05 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 -C4 C6 96 C5 34 C2 7E C3 14 C2 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C5 8E C6 4A C5 -14 C2 04 1B 5B 30 6D 00 4A C5 16 CA 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C3 04 57 41 52 4D 00 B0 12 -8C C3 78 40 03 00 B0 12 BA C3 84 12 14 C2 07 0D -0A 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 C4 C6 -0A C2 23 00 FA C4 C4 C6 14 C2 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C5 0A C2 40 FF 28 C2 C2 C5 8E C6 -14 C2 0A 62 79 74 65 73 20 66 72 65 65 00 3A C2 -7E C3 00 00 06 41 43 43 45 50 54 00 30 40 70 C4 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C3 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C4 2F 83 8F 4E 00 00 -58 43 B0 12 BA C3 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C4 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 C4 -04 45 43 48 4F 00 B2 40 C2 48 08 C5 82 43 DE 1D -38 40 05 00 B0 12 BA C3 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C5 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C5 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C4 68 C5 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C3 02 43 52 00 30 40 80 C5 -0D 12 84 12 14 C2 02 0D 0A 00 4A C5 4E C6 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C4 01 40 2E 4E -30 4D CC C5 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 C5 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 02 3D 0E 93 3E 4F +84 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B2 C4 B2 49 +36 C5 B2 49 0E C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 32 CE 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C3 B0 12 D0 C2 92 C6 AC C2 +42 C3 50 C5 1E C2 05 1B 5B 37 6D 40 7C C5 0A C2 +02 18 B4 C6 E0 C7 7C C5 1E C2 04 1B 5B 30 6D 00 +7C C5 C8 CA 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 50 C5 1E C2 07 0D 0A 1B 5B 37 +6D 40 7C C5 0A C2 02 18 B4 C6 E0 C7 0A C2 23 00 +34 C5 E0 C7 1E C2 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7C C5 0A C2 40 FF 32 C2 A8 C6 AC C7 1E C2 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C2 36 C3 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C3 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C 92 D3 30 01 B2 43 06 02 +B2 40 EF 7F 02 02 B2 43 26 02 B2 D0 08 FF 22 02 +F2 D3 26 03 F2 40 F0 00 22 03 F2 40 A5 00 61 01 +B2 40 33 00 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 9E 01 +B0 12 D0 C2 80 C3 00 00 0C 41 43 43 45 50 54 00 +30 40 B4 C4 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 9D 3E 21 52 A2 C2 6C 06 B2 B0 10 00 +40 06 96 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 10 C5 +58 43 B0 12 46 C3 2F 83 8F 4E 00 00 92 B3 6C 06 +FD 27 1E 42 4C 06 B0 12 44 C3 30 4D 00 00 08 45 +4D 49 54 00 30 40 38 C5 08 4E 3E 4F A2 B3 6C 06 +FD 27 C2 48 4E 06 30 4D 2E C5 08 45 43 48 4F 00 +B2 40 C2 48 42 C5 38 40 05 00 B0 12 46 C3 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 42 C5 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +8C C5 29 4F 8F 4E 00 00 7E 49 D4 3F 8E C5 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 82 22 F9 98 +00 00 7F 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 76 22 9B 24 08 C5 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A C2 00 00 AC C6 9E C5 F0 C7 +AA CA B0 C2 1A C6 14 C2 06 5B 54 48 45 4E 5D 00 +A2 C5 F8 C5 BE C5 DC C5 14 C2 06 5B 45 4C 53 45 +5D 00 A2 C5 0A C6 BE C5 DA C5 1E C2 04 5B 49 46 +5D 00 A2 C5 DC C5 B2 C2 DA C5 1E C2 05 0D 6B 6F +20 0A 7C C5 9A C2 84 C2 B2 C2 DC C5 CA C5 0D 5B +54 48 45 4E 5D 00 30 4D 2E C6 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 3A C6 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 9E C5 F0 C7 58 C8 FC C9 +6C C7 4A C6 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 9E C5 F0 C7 58 C8 7C C6 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D A8 C4 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 C3 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A C2 1E C2 5A CA 0A C2 22 00 F0 C7 F0 C6 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 62 C5 05 2E 22 00 0D 12 84 12 DA C6 +0A C2 7C C5 5A CA 6C C7 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D D6 C6 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 C2 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 C6 02 23 53 00 0D 12 84 12 -0A C6 44 C6 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C6 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C5 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C5 -3C C6 EE C2 7C C6 58 C6 4A C5 02 CA FA C4 4E C6 -2C C5 01 2E 0E 93 E3 37 38 43 E2 3F 76 C6 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 48 C9 -0A C2 22 00 1A C7 E8 C6 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 C6 -82 2E 22 00 0D 12 84 12 D2 C6 0A C2 4A C5 48 C9 -4E C6 F8 C3 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C C8 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E C8 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 C9 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C6 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C2 02 CA 1A C7 BE C9 9C 26 -3D 40 C6 C9 DE 3E C8 C9 0A 4E 3E 4F 3D 40 E2 C9 -36 27 3D 40 B8 C9 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 C9 3E 4F 3D 40 B8 C9 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CB CC 3F -EC C9 86 12 20 00 D4 C5 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C C5 BC C2 -B2 C9 B2 C5 E4 C5 14 C2 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 EC C5 -14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C3 -3A C2 2C CA 08 CA 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C6 0A C2 2A C3 48 C9 4E C6 7C C7 01 27 -0D 12 84 12 02 CA 1A C7 82 C7 34 C2 00 CA 4E C6 -00 00 83 5B 27 5D 0D 12 84 12 80 CA 0A C2 0A C2 -48 C9 48 C9 4E C6 92 CA 81 5B 82 43 BE 1D 30 4D -FA C5 01 5D B2 43 BE 1D 30 4D B2 CA 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CA 1A C7 82 C7 96 C5 34 C2 -00 CA E4 C5 34 C2 F4 CA 0A C2 0A C2 48 C9 48 C9 -0A C2 48 C9 48 C9 4E C6 A8 CA 01 3A 30 12 44 CB -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 CA 1A C7 -12 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C3 FA CA 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A C2 4E C6 48 C9 56 CB AA CA 4E C6 -A8 C9 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 C9 06 43 52 45 41 54 -45 00 B0 12 00 CB BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CB 04 43 4F 44 45 00 B0 12 00 CB A2 82 -C6 1D 0D 12 84 12 F2 CD CC CD 4E C6 A2 CB 07 48 -44 4E 43 4F 44 45 B2 40 D0 CD DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CB 0C CE -2A CE 4E C6 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C CE 2A CE 4E C6 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE CB 85 48 49 32 4C 4F 0D 12 84 12 28 C2 9A CD -48 C9 AA CA E2 CB 4E C6 88 CB 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CC 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C2 00 00 C6 C5 02 CA 1A C7 98 C9 -8E C5 34 C2 02 CD 9C C5 14 C2 06 5B 54 48 45 4E -5D 00 74 CC DC CC 98 CC BA CC 4E C6 9C C5 14 C2 -06 5B 45 4C 53 45 5D 00 74 CC F2 CC 98 CC B8 CC -4E C6 14 C2 04 5B 49 46 5D 00 74 CC BA CC 3A C2 -B8 CC 70 C5 14 C2 05 0D 0A 6B 6F 20 4A C5 BC C2 -AC C2 3A C2 BA CC A8 CC 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CD 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CA 1A C7 82 C7 -26 CD 4E C6 2C CD 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CD DE C5 4E C6 5E CD B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A C9 06 4D -41 52 4B 45 52 00 B0 12 00 CB BA 40 85 12 FC FF -BA 40 5C CD FE FF 28 83 8A 48 00 00 BA 40 AA C2 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A C2 -CA 1D D6 C5 4E C6 85 12 9E CD 66 CA D4 CB 10 C5 -7E CA 52 CC D2 C4 6E CD 00 C7 96 CE AA CE 8A C6 -14 C7 00 00 46 CD BC CA E2 C7 00 00 85 12 9E CD -62 D4 C8 D4 0A D4 18 D5 D0 D3 00 00 9C D1 00 00 -E0 D5 C4 D5 34 D4 72 D4 AC D2 00 00 00 00 34 D5 -CA CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 CD 24 CE 2A CE 3A CE 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CA -09 50 57 52 5F 53 54 41 54 45 85 12 32 CE EC D5 -CE C6 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E CE F3 3F 70 CE 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E CE 30 4D 82 CE 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 CF FE FF 29 83 B9 40 -E2 C3 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C3 B2 49 FA C2 B2 49 02 C2 B2 49 00 C4 B2 49 -EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 92 D3 -30 01 B2 43 06 02 B2 40 EF 7F 02 02 B2 43 26 02 -B2 D0 08 FF 22 02 F2 D3 26 03 F2 40 F0 00 22 03 -F2 40 A5 00 61 01 B2 40 33 00 66 01 B2 40 33 00 -64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 B2 D2 B0 01 92 C3 B0 01 F2 D0 -10 00 2A 03 F2 C0 40 00 A1 04 1E 42 08 18 82 43 -08 18 1E D2 9E 01 B0 12 F8 C2 FE C3 38 40 C0 1D -0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D -1C 15 0E 12 12 12 C4 1D 84 12 1A C7 82 C7 DE C5 -34 C2 DC CF 3E C8 34 C2 F6 CF F0 CF DE CF 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 F8 CF B2 41 C4 1D 3E 41 84 12 -0A C2 2B 00 1A C7 82 C7 DE C5 34 C2 14 D0 3E C8 -34 C2 00 CA A8 C5 1A C7 3E C8 34 C2 00 CA 20 D0 -3E 5F E7 3F 3E 40 28 00 B0 12 C0 CF 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 C0 1D -C4 1D 02 20 30 40 6E CB 1C 15 12 12 C4 1D 92 53 -C4 1D 84 12 1A C7 3E C8 34 C2 68 D0 5E D0 21 53 -3E 90 10 00 C6 2B 7F 2D 6A D0 B2 41 C4 1D C1 3F -0D 12 84 12 02 CA 9C CF 7A D0 0C 43 1B 42 C6 1D -A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 -C4 1D B0 12 C0 CF 3C 40 00 03 0E 93 1C 24 3C 40 +C8 4A 00 00 30 4D 28 C7 04 23 53 00 0D 12 84 12 +2A C7 64 C7 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +58 C7 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 72 C7 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 4A C5 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 1E C7 9E C5 8C C7 +5C C7 88 C6 9A C7 76 C7 7C C5 6C C7 06 C7 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D DE C7 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 62 C9 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 64 C9 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E C2 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +1A C7 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 C2 9E C5 F0 C7 B0 C2 34 CB 58 C8 1E CA 0A 4E +3E 4F 3D 40 38 CA 6D 27 3D 40 12 CA 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 3A CA 3E 4F 3D 40 12 CA +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 10 CC 2A 3C 02 CA 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D 58 CA 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 94 C7 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D BA C6 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E C2 02 0D 0A 00 7C C5 94 C2 0C CA 9A C6 C4 C6 +1E C2 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C3 +32 C2 0A C2 40 FF CC C6 1E C2 09 46 52 41 4D 20 +66 75 6C 6C 08 C3 B2 C2 D0 CA BA CA 0D 41 42 4F +52 54 22 00 0D 12 84 12 DA C6 0A C2 08 C3 5A CA +6C C7 EA C7 02 27 0D 12 84 12 9E C5 F0 C7 58 C8 +B0 C2 36 CB FE C6 42 CA 64 C6 07 5B 27 5D 0D 12 +84 12 26 CB 0A C2 0A C2 5A CA 5A CA 6C C7 3A CB +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D B2 C6 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 9E C5 F0 C7 58 C8 B0 C2 36 CB C4 C6 AC C2 +8E CB 0A C2 0A C2 5A CA 5A CA 0A C2 5A CA 5A CA +6C C7 00 00 02 3A 30 12 E4 CB 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 9E C5 F0 C7 AC CB 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E C2 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 C3 50 CB 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A C2 6C C7 5A CA F6 CB 52 CB 6C C7 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D A4 CA 0C 43 52 45 41 54 45 00 B0 12 9A CB +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 76 C5 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 94 CB 0E 3A 4E 4F 4E 41 4D 45 +30 12 E4 CB 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 2E CC 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 26 CB B0 CC +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 3E CB 0A C2 +B2 CC 5A CA 6C C7 44 CC 08 43 4F 44 45 00 B0 12 +9A CB A2 82 C8 1D 61 3C 86 C7 0E 48 44 4E 43 4F +44 45 B2 40 9E CD CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 F6 CB FC CC 3D 41 92 42 +D0 1D CC 1D 5D 3C C8 CC 0E 43 4F 44 45 4E 4E 4D +30 12 D2 CC B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F DA CC 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F 66 CD B2 40 78 CD D0 1D 82 4E CE 1D +30 40 FE C6 85 12 64 CD 64 CB 0C CB F6 CD 08 CD +5E CC A8 C7 52 C8 24 CB 4C CD 9E CC 78 CC 14 CC +6C CA 80 CE AA C8 00 00 00 00 85 12 64 CD FA D4 +7E D3 DE D4 A6 D2 02 D3 50 D3 2C D4 38 D4 C8 D1 +EC D2 00 00 00 00 3A CD B8 D0 00 00 54 D4 98 CD +B2 40 78 CD CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +CC CD 30 4D DE CD 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 CC CD 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E C4 FE FF 29 83 B9 40 FA C3 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 EE FF 3B 40 +10 00 3A 40 3A 18 B0 12 D0 CD 82 43 4A 18 C7 3F +72 CE B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 5A CB +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +9E C5 F0 C7 58 C8 AC C2 9E CE 92 C6 32 CA A0 CE +3E 4F 3D 41 B2 41 C6 1D B0 12 9A CB BA 40 85 12 +FC FF BA 40 70 CE FE FF 28 83 8A 48 00 00 BA 40 +82 C2 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +F0 C7 58 C8 AC C2 0A CF EA CE 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 70 CE 00 00 +01 20 3E 52 2E 83 21 53 30 41 02 C9 AC C2 12 CF +06 CF 14 CF B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 DA CE 15 20 3E 40 2B 00 +B0 12 DA CE 06 20 3E 40 2D 00 B0 12 DA CE 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 F0 C7 02 C9 AC C2 +36 CB 54 CF 3E 51 3A 17 30 41 B0 12 1A CF 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 F0 C7 02 C9 AC C2 +8C CF 84 CF 3E 90 10 00 E6 2B 7C 2D 8E CF A2 41 +C6 1D E1 3F 03 20 B0 12 72 CF 43 3C 7A 90 23 00 +24 20 B0 12 22 CF 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 -30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 -C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 -07 20 3C 40 10 02 92 53 C4 1D B0 12 C0 CF ED 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D B0 12 -48 D0 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 48 D0 -92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E -DA 3F B0 12 48 D0 FA 23 3C 50 10 00 B0 12 24 D0 -EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 -02 CA 9C CF 46 D1 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C7 3F B0 12 48 D0 E0 23 3C 50 -80 00 B0 12 24 D0 DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A C2 00 13 48 C9 4E C6 0A C2 2C 00 -70 D0 3C D1 86 D1 09 4B 2E 4E 0E DC A2 3F 40 CC -03 4D 4F 56 85 12 7C D1 00 40 90 D1 05 4D 4F 56 -2E 42 85 12 7C D1 40 40 00 00 03 41 44 44 85 12 -7C D1 00 50 AA D1 05 41 44 44 2E 42 85 12 7C D1 -40 50 B6 D1 04 41 44 44 43 00 85 12 7C D1 00 60 -C4 D1 06 41 44 44 43 2E 42 00 85 12 7C D1 40 60 -6A D1 04 53 55 42 43 00 85 12 7C D1 00 70 E2 D1 -06 53 55 42 43 2E 42 00 85 12 7C D1 40 70 F0 D1 -03 53 55 42 85 12 7C D1 00 80 00 D2 05 53 55 42 -2E 42 85 12 7C D1 40 80 16 CC 03 43 4D 50 85 12 -7C D1 00 90 1A D2 05 43 4D 50 2E 42 85 12 7C D1 -40 90 00 CC 04 44 41 44 44 00 85 12 7C D1 00 A0 -34 D2 06 44 41 44 44 2E 42 00 85 12 7C D1 40 A0 -26 D2 03 42 49 54 85 12 7C D1 00 B0 52 D2 05 42 -49 54 2E 42 85 12 7C D1 40 B0 5E D2 03 42 49 43 -85 12 7C D1 00 C0 6C D2 05 42 49 43 2E 42 85 12 -7C D1 40 C0 78 D2 03 42 49 53 85 12 7C D1 00 D0 -86 D2 05 42 49 53 2E 42 85 12 7C D1 40 D0 00 00 -03 58 4F 52 85 12 7C D1 00 E0 A0 D2 05 58 4F 52 -2E 42 85 12 7C D1 40 E0 D2 D1 03 41 4E 44 85 12 -7C D1 00 F0 BA D2 05 41 4E 44 2E 42 85 12 7C D1 -40 F0 02 CA 70 D0 D8 D2 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F 0C D2 03 52 52 43 85 12 -D2 D2 00 10 EA D2 05 52 52 43 2E 42 85 12 D2 D2 -40 10 F6 D2 04 53 57 50 42 00 85 12 D2 D2 80 10 -04 D3 03 52 52 41 85 12 D2 D2 00 11 12 D3 05 52 -52 41 2E 42 85 12 D2 D2 40 11 1E D3 03 53 58 54 -85 12 D2 D2 80 11 00 00 04 50 55 53 48 00 85 12 -D2 D2 00 12 38 D3 06 50 55 53 48 2E 42 00 85 12 -D2 D2 40 12 92 D2 04 43 41 4C 4C 00 85 12 D2 D2 -80 12 1A 53 0E 4A 0D 12 84 12 C4 C6 14 C2 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 C3 2C D3 -03 53 3E 3D 86 12 00 38 80 D3 02 53 3C 00 86 12 -00 34 46 D3 03 30 3E 3D 86 12 00 30 94 D3 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -A8 D3 03 55 3E 3D 86 12 00 28 9E D3 03 30 3C 3E -86 12 00 24 BC D3 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D -0E 4A 30 4D B2 D3 04 54 48 45 4E 00 1A 42 C6 1D -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D 42 D2 04 45 4C 53 45 00 -1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 -8F 4A 00 00 E3 3F 56 D3 05 42 45 47 49 4E 30 40 -28 C2 E6 D3 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D 30 4D -C6 D2 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 D4 D3 A8 C5 -4E C6 8A D3 06 52 45 50 45 41 54 00 0D 12 84 12 -68 D4 EC D3 4E C6 98 D4 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D 28 D4 -03 42 57 31 85 12 96 D4 00 00 B0 D4 03 42 57 32 -85 12 96 D4 00 00 BC D4 03 42 57 33 85 12 96 D4 -00 00 D4 D4 3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D -88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 D2 D4 00 00 F4 D4 -03 46 57 32 85 12 D2 D4 00 00 00 D5 03 46 57 33 -85 12 D2 D4 00 00 0C D5 04 47 4F 54 4F 00 2F 83 -8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 CA DC C9 -4E C6 00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 22 CF F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 6E CF 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 72 CF 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 5A CF +F2 3F 03 20 B0 12 72 CF F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 5A CF EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A C2 00 13 5A CA 6C C7 +0A C2 2C 00 50 D0 94 CF 9E C5 5A D0 32 D0 A0 D0 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 90 D0 00 40 AC D0 0A 4D 4F 56 2E 42 85 12 +90 D0 40 40 00 00 06 41 44 44 85 12 90 D0 00 50 +C6 D0 0A 41 44 44 2E 42 85 12 90 D0 40 50 D2 D0 +08 41 44 44 43 00 85 12 90 D0 00 60 E0 D0 0C 41 +44 44 43 2E 42 00 85 12 90 D0 40 60 18 CD 08 53 +55 42 43 00 85 12 90 D0 00 70 FE D0 0C 53 55 42 +43 2E 42 00 85 12 90 D0 40 70 0C D1 06 53 55 42 +85 12 90 D0 00 80 1C D1 0A 53 55 42 2E 42 85 12 +90 D0 40 80 28 D1 06 43 4D 50 85 12 90 D0 00 90 +36 D1 0A 43 4D 50 2E 42 85 12 90 D0 40 90 00 00 +08 44 41 44 44 00 85 12 90 D0 00 A0 50 D1 0C 44 +41 44 44 2E 42 00 85 12 90 D0 40 A0 7E D0 06 42 +49 54 85 12 90 D0 00 B0 6E D1 0A 42 49 54 2E 42 +85 12 90 D0 40 B0 7A D1 06 42 49 43 85 12 90 D0 +00 C0 88 D1 0A 42 49 43 2E 42 85 12 90 D0 40 C0 +94 D1 06 42 49 53 85 12 90 D0 00 D0 A2 D1 0A 42 +49 53 2E 42 85 12 90 D0 40 D0 00 00 06 58 4F 52 +85 12 90 D0 00 E0 BC D1 0A 58 4F 52 2E 42 85 12 +90 D0 40 E0 EE D0 06 41 4E 44 85 12 90 D0 00 F0 +D6 D1 0A 41 4E 44 2E 42 85 12 90 D0 40 F0 9E C5 +50 D0 94 CF F6 D1 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F AE D1 06 52 52 43 85 12 EE D1 +00 10 08 D2 0A 52 52 43 2E 42 85 12 EE D1 40 10 +42 D1 08 53 57 50 42 00 85 12 EE D1 80 10 14 D2 +06 52 52 41 85 12 EE D1 00 11 30 D2 0A 52 52 41 +2E 42 85 12 EE D1 40 11 22 D2 06 53 58 54 85 12 +EE D1 80 11 00 00 08 50 55 53 48 00 85 12 EE D1 +00 12 56 D2 0C 50 55 53 48 2E 42 00 85 12 EE D1 +40 12 4A D2 08 43 41 4C 4C 00 85 12 EE D1 80 12 +1A 53 0E 4A 84 12 E0 C7 1E C2 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 C3 74 D2 06 53 3E 3D +86 12 00 38 9C D2 04 53 3C 00 86 12 00 34 64 D2 +06 30 3E 3D 86 12 00 30 B0 D2 04 30 3C 00 86 12 +00 30 EC CC 04 55 3C 00 86 12 00 2C C4 D2 06 55 +3E 3D 86 12 00 28 BA D2 06 30 3C 3E 86 12 00 24 +D8 D2 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +5E D1 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D CE D2 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F 3C D2 0A 42 45 47 49 4E 30 40 32 C2 26 D3 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D E2 D1 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 F0 D2 86 C6 6C C7 44 D3 +0C 52 45 50 45 41 54 00 0D 12 84 12 84 D3 08 D3 +6C C7 B4 D3 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D A0 D3 06 42 57 31 +85 12 B2 D3 00 00 CC D3 06 42 57 32 85 12 B2 D3 +00 00 D8 D3 06 42 57 33 85 12 B2 D3 00 00 F0 D3 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 EE D3 00 00 14 D4 +06 46 57 32 85 12 EE D3 00 00 20 D4 06 46 57 33 +85 12 EE D3 00 00 8E D3 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 26 CB 32 CA +6C C7 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F -02 CA 9C CF 56 D5 92 53 C4 1D 3E 40 2C 00 84 12 -1A C7 3E C8 34 C2 00 CA 32 D1 6C D5 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 84 D4 04 52 52 43 4D 00 -85 12 50 D5 50 00 9A D5 04 52 52 41 4D 00 85 12 -50 D5 50 01 A8 D5 04 52 4C 41 4D 00 85 12 50 D5 -50 02 B6 D5 04 52 52 55 4D 00 85 12 50 D5 50 03 -C6 D3 05 50 55 53 48 4D 85 12 50 D5 00 15 D2 D5 -04 50 4F 50 4D 00 85 12 50 D5 00 17 +5A D0 0A C2 2C 00 F0 C7 02 C9 AC C2 36 CB 9E C5 +50 D0 32 D0 86 D4 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E E4 D3 08 52 52 43 4D 00 85 12 70 D4 50 00 +B4 D4 08 52 52 41 4D 00 85 12 70 D4 50 01 C2 D4 +08 52 4C 41 4D 00 85 12 70 D4 50 02 D0 D4 08 52 +52 55 4D 00 85 12 70 D4 50 03 E2 D2 0A 50 55 53 +48 4D 85 12 70 D4 00 15 EC D4 08 50 4F 50 4D 00 +85 12 70 D4 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 82 C4 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 08 CF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 C6 C4 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 0E C4 q diff --git a/binaries/MSP_EXP430FR5739_1MHz_UART.txt b/binaries/MSP_EXP430FR5739_1MHz_UART.txt deleted file mode 100644 index 24d8651..0000000 --- a/binaries/MSP_EXP430FR5739_1MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF 02 D6 02 CE 34 01 -10 00 41 B3 94 C3 AA C2 DA C3 9C C3 94 C4 02 D6 -02 CE 7A C4 92 C5 24 C5 FE C4 3C 1D 60 C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 -@C200 -B0 12 DA C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 78 C4 B2 49 90 C5 B2 49 22 C5 B2 49 FC C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C3 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 C2 0A C2 DE 1D E0 C5 32 C5 -14 C2 04 1B 5B 37 6D 00 5C C5 A8 C5 34 C2 86 C3 -14 C2 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C5 A0 C6 5C C5 14 C2 04 1B 5B 30 6D 00 -5C C5 28 CA 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 03 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C3 04 57 41 52 4D 00 B0 12 -9C C3 84 12 14 C2 07 0D 0A 1B 5B 37 6D 23 5C C5 -D6 C6 14 C2 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C5 -0A C2 40 FF 28 C2 D4 C5 A0 C6 14 C2 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C2 86 C3 00 00 06 41 -43 43 45 50 54 00 30 40 7A C4 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C4 3C 40 D2 C4 -5D 15 B6 3E 21 52 3A 17 58 42 CC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 -C2 48 CE 05 30 4D C8 C4 2D 83 92 B3 DC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 DC 05 -FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C4 2F 83 -8F 4E 00 00 B0 12 DA C3 92 B3 DC 05 FD 27 1E 42 -CC 05 B0 12 C8 C3 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C5 08 4E 3E 4F C8 3F 1A C5 04 45 43 48 -4F 00 B2 40 C2 48 C0 C4 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C4 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C5 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C5 7A C5 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C3 02 43 52 00 30 40 -92 C5 0D 12 84 12 14 C2 02 0D 0A 00 5C C5 60 C6 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C4 01 40 -2E 4E 30 4D DE C5 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A C5 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A C6 02 23 53 00 0D 12 -84 12 1C C6 56 C6 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C6 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C5 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C6 4E C6 EE C2 8E C6 6A C6 5C C5 14 CA 20 C5 -60 C6 40 C5 01 2E 0E 93 E3 37 38 43 E2 3F 88 C6 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 -5A C9 0A C2 22 00 2C C7 FA C6 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 C6 82 2E 22 00 0D 12 84 12 E4 C6 0A C2 5C C5 -5A C9 60 C6 18 C4 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE C8 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 C8 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 C9 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C6 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C2 14 CA 2C C7 D0 C9 -9C 26 3D 40 D8 C9 DE 3E DA C9 0A 4E 3E 4F 3D 40 -F4 C9 36 27 3D 40 CA C9 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 C9 3E 4F 3D 40 CA C9 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CB -CC 3F FE C9 86 12 20 00 E6 C5 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E C5 -BC C2 C4 C9 C4 C5 F6 C5 14 C2 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 -FE C5 14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C3 3A C2 3E CA 1A CA 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C6 0A C2 2A C3 5A C9 60 C6 8E C7 -01 27 0D 12 84 12 14 CA 2C C7 94 C7 34 C2 12 CA -60 C6 00 00 83 5B 27 5D 0D 12 84 12 92 CA 0A C2 -0A C2 5A C9 5A C9 60 C6 A4 CA 81 5B 82 43 BE 1D -30 4D 0C C6 01 5D B2 43 BE 1D 30 4D C4 CA 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CA 2C C7 94 C7 A8 C5 -34 C2 12 CA F6 C5 34 C2 06 CB 0A C2 0A C2 5A C9 -5A C9 0A C2 5A C9 5A C9 60 C6 BA CA 01 3A 30 12 -56 CB 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 CA -2C C7 24 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C3 0C CB 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A C2 60 C6 5A C9 68 CB BC CA -60 C6 BA C9 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 C9 06 43 52 45 -41 54 45 00 B0 12 12 CB BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CB 04 43 4F 44 45 00 B0 12 12 CB -A2 82 C6 1D 0D 12 84 12 04 CE DE CD 60 C6 B4 CB -07 48 44 4E 43 4F 44 45 B2 40 E2 CD DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CB -1E CE 3C CE 60 C6 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E CE 3C CE 60 C6 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 CC 85 48 49 32 4C 4F 0D 12 84 12 28 C2 -AC CD 5A C9 BC CA F4 CB 60 C6 9A CB 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CC 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C2 00 00 D8 C5 14 CA 2C C7 -AA C9 A0 C5 34 C2 14 CD AE C5 14 C2 06 5B 54 48 -45 4E 5D 00 86 CC EE CC AA CC CC CC 60 C6 AE C5 -14 C2 06 5B 45 4C 53 45 5D 00 86 CC 04 CD AA CC -CA CC 60 C6 14 C2 04 5B 49 46 5D 00 86 CC CC CC -3A C2 CA CC 82 C5 14 C2 05 0D 0A 6B 6F 20 5C C5 -BC C2 AC C2 3A C2 CC CC BA CC 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CD 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CA 2C C7 -94 C7 38 CD 60 C6 3E CD 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CD F0 C5 60 C6 70 CD -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C C9 -06 4D 41 52 4B 45 52 00 B0 12 12 CB BA 40 85 12 -FC FF BA 40 6E CD FE FF 28 83 8A 48 00 00 BA 40 -AA C2 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A C2 CA 1D E8 C5 60 C6 85 12 B0 CD 78 CA E6 CB -2C C5 90 CA 64 CC F6 C4 80 CD 12 C7 A8 CE BC CE -9C C6 26 C7 00 00 58 CD CE CA F4 C7 00 00 85 12 -B0 CD 78 D4 DE D4 20 D4 2E D5 E6 D3 00 00 B2 D1 -00 00 F6 D5 DA D5 4A D4 88 D4 C2 D2 00 00 00 00 -4A D5 DC CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 CD 36 CE 3C CE 4C CE 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CA 09 50 57 52 5F 53 54 41 54 45 85 12 44 CE -02 D6 E0 C6 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 CE F3 3F 82 CE 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 CE 30 4D 94 CE 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A CF FE FF 29 83 -B9 40 02 C4 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C4 B2 49 FA C2 B2 49 02 C2 B2 49 20 C4 -B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 -92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 -05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 -F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 33 00 -66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 -92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 -1E 42 08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 C2 -1E C4 38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 -2C C7 94 C7 F0 C5 34 C2 F2 CF 50 C8 34 C2 0C D0 -06 D0 F4 CF 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 0E D0 B2 41 -C4 1D 3E 41 84 12 0A C2 2B 00 2C C7 94 C7 F0 C5 -34 C2 2A D0 50 C8 34 C2 12 CA BA C5 2C C7 50 C8 -34 C2 12 CA 36 D0 3E 5F E7 3F 3E 40 28 00 B0 12 -D6 CF 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 -29 00 92 92 C0 1D C4 1D 02 20 30 40 80 CB 1C 15 -12 12 C4 1D 92 53 C4 1D 84 12 2C C7 50 C8 34 C2 -7E D0 74 D0 21 53 3E 90 10 00 C6 2B 7F 2D 80 D0 -B2 41 C4 1D C1 3F 0D 12 84 12 14 CA B2 CF 90 D0 -0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 1D B0 12 D6 CF 3C 40 00 03 -0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 -2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 -3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D -B0 12 D6 CF ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 1D B0 12 5E D0 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 5E D0 92 92 C0 1D C4 1D 02 24 92 53 -C4 1D 8E 10 0C 5E DA 3F B0 12 5E D0 FA 23 3C 50 -10 00 B0 12 3A D0 EF 3F 0C 43 1B 42 C6 1D A2 53 -C6 1D 0D 12 84 12 14 CA B2 CF 5C D1 FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -5E D0 E0 23 3C 50 80 00 B0 12 3A D0 DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A C2 00 13 5A C9 -60 C6 0A C2 2C 00 86 D0 52 D1 9C D1 09 4B 2E 4E -0E DC A2 3F 52 CC 03 4D 4F 56 85 12 92 D1 00 40 -A6 D1 05 4D 4F 56 2E 42 85 12 92 D1 40 40 00 00 -03 41 44 44 85 12 92 D1 00 50 C0 D1 05 41 44 44 -2E 42 85 12 92 D1 40 50 CC D1 04 41 44 44 43 00 -85 12 92 D1 00 60 DA D1 06 41 44 44 43 2E 42 00 -85 12 92 D1 40 60 80 D1 04 53 55 42 43 00 85 12 -92 D1 00 70 F8 D1 06 53 55 42 43 2E 42 00 85 12 -92 D1 40 70 06 D2 03 53 55 42 85 12 92 D1 00 80 -16 D2 05 53 55 42 2E 42 85 12 92 D1 40 80 28 CC -03 43 4D 50 85 12 92 D1 00 90 30 D2 05 43 4D 50 -2E 42 85 12 92 D1 40 90 12 CC 04 44 41 44 44 00 -85 12 92 D1 00 A0 4A D2 06 44 41 44 44 2E 42 00 -85 12 92 D1 40 A0 3C D2 03 42 49 54 85 12 92 D1 -00 B0 68 D2 05 42 49 54 2E 42 85 12 92 D1 40 B0 -74 D2 03 42 49 43 85 12 92 D1 00 C0 82 D2 05 42 -49 43 2E 42 85 12 92 D1 40 C0 8E D2 03 42 49 53 -85 12 92 D1 00 D0 9C D2 05 42 49 53 2E 42 85 12 -92 D1 40 D0 00 00 03 58 4F 52 85 12 92 D1 00 E0 -B6 D2 05 58 4F 52 2E 42 85 12 92 D1 40 E0 E8 D1 -03 41 4E 44 85 12 92 D1 00 F0 D0 D2 05 41 4E 44 -2E 42 85 12 92 D1 40 F0 14 CA 86 D0 EE D2 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 22 D2 -03 52 52 43 85 12 E8 D2 00 10 00 D3 05 52 52 43 -2E 42 85 12 E8 D2 40 10 0C D3 04 53 57 50 42 00 -85 12 E8 D2 80 10 1A D3 03 52 52 41 85 12 E8 D2 -00 11 28 D3 05 52 52 41 2E 42 85 12 E8 D2 40 11 -34 D3 03 53 58 54 85 12 E8 D2 80 11 00 00 04 50 -55 53 48 00 85 12 E8 D2 00 12 4E D3 06 50 55 53 -48 2E 42 00 85 12 E8 D2 40 12 A8 D2 04 43 41 4C -4C 00 85 12 E8 D2 80 12 1A 53 0E 4A 0D 12 84 12 -D6 C6 14 C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 C3 42 D3 03 53 3E 3D 86 12 00 38 96 D3 -02 53 3C 00 86 12 00 34 5C D3 03 30 3E 3D 86 12 -00 30 AA D3 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C BE D3 03 55 3E 3D 86 12 00 28 -B4 D3 03 30 3C 3E 86 12 00 24 D2 D3 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 0E 4A 30 4D C8 D3 04 54 48 45 -4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 58 D2 -04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 -A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 6C D3 05 42 -45 47 49 4E 30 40 28 C2 FC D3 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 1D 30 4D DC D2 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 EA D3 BA C5 60 C6 A0 D3 06 52 45 50 45 41 -54 00 0D 12 84 12 7E D4 02 D4 60 C6 AE D4 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D -00 00 30 4D 3E D4 03 42 57 31 85 12 AC D4 00 00 -C6 D4 03 42 57 32 85 12 AC D4 00 00 D2 D4 03 42 -57 33 85 12 AC D4 00 00 EA D4 3D 41 1A 42 C6 1D -28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -E8 D4 00 00 0A D5 03 46 57 32 85 12 E8 D4 00 00 -16 D5 03 46 57 33 85 12 E8 D4 00 00 22 D5 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 92 CA EE C9 60 C6 00 00 05 3F 47 4F 54 4F -3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 14 CA B2 CF 6C D5 92 53 C4 1D -3E 40 2C 00 84 12 2C C7 50 C8 34 C2 12 CA 48 D1 -82 D5 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 9A D4 -04 52 52 43 4D 00 85 12 66 D5 50 00 B0 D5 04 52 -52 41 4D 00 85 12 66 D5 50 01 BE D5 04 52 4C 41 -4D 00 85 12 66 D5 50 02 CC D5 04 52 52 55 4D 00 -85 12 66 D5 50 03 DC D3 05 50 55 53 48 4D 85 12 -66 D5 00 15 E8 D5 04 50 4F 50 4D 00 85 12 66 D5 -00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -94 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 1A CF -q diff --git a/binaries/MSP_EXP430FR5739_24MHz_115200.txt b/binaries/MSP_EXP430FR5739_24MHz_115200.txt new file mode 100644 index 0000000..6d30d43 --- /dev/null +++ b/binaries/MSP_EXP430FR5739_24MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +C0 5D 0D 00 01 49 18 00 FD FF 35 01 10 00 A1 59 +D0 C4 7E C3 84 C3 54 C3 40 C5 2E D5 E6 CD A0 CD +A0 CD B6 C4 74 C5 3C C5 3C 1D E0 1C 94 C7 B6 C2 +C4 C2 B0 C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +40 C5 2E D5 E6 CD A0 CD A0 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 03 3D 0E 93 3E 4F +98 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B4 C4 B2 49 +72 C5 B2 49 3A C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 5A CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 40 C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 BA C6 AC C2 52 C3 82 C5 1E C2 04 1B +5B 37 6D 00 A4 C5 A4 C5 1E C2 04 1B 5B 30 6D 00 +A4 C5 F0 CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 82 C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 A4 C5 08 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A4 C5 0A C2 40 FF 32 C2 +D0 C6 D4 C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 86 00 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 +19 42 9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 +0E 49 B0 12 D0 C2 86 C3 00 00 0C 41 43 43 45 50 +54 00 30 40 B6 C4 08 4E 2E 4F 08 5E 39 40 0D 00 +3A 40 20 00 3B 40 14 C5 3C 40 20 C5 5D 15 98 3E +21 52 3A 17 58 42 CC 05 48 9B 09 20 A2 B3 DC 05 +FD 27 B2 40 13 00 CE 05 E2 D2 03 02 30 41 48 9C +06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A +03 2C CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 +CE 05 30 4D 16 C5 2D 83 92 B3 DC 05 DB 23 FC 3F +3E 8F 3D 41 92 B3 DC 05 FD 27 58 42 CC 05 08 4C +EB 3F 00 00 06 4B 45 59 30 40 3C C5 30 12 52 C5 +A2 B3 DC 05 FD 27 B2 40 11 00 CE 05 E2 C2 03 02 +30 41 2F 83 8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 +DC C4 1E 42 CC 05 30 4D 00 00 08 45 4D 49 54 00 +30 40 74 C5 08 4E 3E 4F C7 3F 6A C5 08 45 43 48 +4F 00 B2 40 C2 48 0E C5 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 0E C5 30 4D 00 00 08 54 +59 50 45 00 0D 12 3D 40 B4 C5 29 4F 8F 4E 00 00 +7E 49 DE 3F B6 C5 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 6E 22 F9 98 00 00 6B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 62 22 9B 24 +34 C5 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C2 +00 00 D4 C6 C6 C5 18 C8 D2 CA B0 C2 42 C6 14 C2 +06 5B 54 48 45 4E 5D 00 CA C5 20 C6 E6 C5 04 C6 +14 C2 06 5B 45 4C 53 45 5D 00 CA C5 32 C6 E6 C5 +02 C6 1E C2 04 5B 49 46 5D 00 CA C5 04 C6 B2 C2 +02 C6 1E C2 05 0D 6B 6F 20 0A A4 C5 9A C2 84 C2 +B2 C2 04 C6 F2 C5 0D 5B 54 48 45 4E 5D 00 30 4D +56 C6 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +62 C6 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +C6 C5 18 C8 80 C8 24 CA 94 C7 72 C6 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 C6 C5 18 C8 +80 C8 A4 C6 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +AA C4 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C3 05 53 +22 00 82 43 C0 1D 0D 12 84 12 0A C2 1E C2 82 CA +0A C2 22 00 18 C8 18 C7 B2 40 20 00 C0 1D 1A 53 +1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 8C C5 05 2E +22 00 0D 12 84 12 02 C7 0A C2 A4 C5 82 CA 94 C7 +00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D FE C6 +02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 50 C7 +04 23 53 00 0D 12 84 12 52 C7 8C C7 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 80 C7 04 23 3E 00 9F 42 +B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 9A C7 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 7C C5 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 46 C7 C6 C5 B4 C7 84 C7 B0 C6 C2 C7 9E C7 +A4 C5 94 C7 2E C7 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +06 C8 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 +1E 15 3D 40 8A C9 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 8C C9 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 42 C7 03 5C 92 42 C2 1D +C6 1D 30 4D 0D 12 84 12 84 C2 C6 C5 18 C8 B0 C2 +5C CB 80 C8 46 CA 0A 4E 3E 4F 3D 40 60 CA 6D 27 +3D 40 3A CA 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 +62 CA 3E 4F 3D 40 3A CA 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 38 CC 2A 3C 2A CA +02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F +30 4D 80 CA 0F 4C 49 54 45 52 41 4C 82 93 BC 1D +0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D BC C7 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +E2 C6 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D +3F 40 80 1C 0E 43 84 12 1E C2 02 0D 0A 00 A4 C5 +94 C2 34 CA C2 C6 EC C6 1E C2 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 C3 32 C2 0A C2 40 FF F4 C6 +1E C2 09 46 52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 +F8 CA E2 CA 0D 41 42 4F 52 54 22 00 0D 12 84 12 +02 C7 0A C2 08 C3 82 CA 94 C7 12 C8 02 27 0D 12 +84 12 C6 C5 18 C8 80 C8 B0 C2 5E CB 26 C7 6A CA +8C C6 07 5B 27 5D 0D 12 84 12 4E CB 0A C2 0A C2 +82 CA 82 CA 94 C7 62 CB 03 5B 82 43 BC 1D 30 4D +00 00 02 5D B2 43 BC 1D 30 4D DA C6 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 C6 C5 18 C8 80 C8 +B0 C2 5E CB EC C6 AC C2 B6 CB 0A C2 0A C2 82 CA +82 CA 0A C2 82 CA 82 CA 94 C7 00 00 02 3A 30 12 +0C CC 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 C6 C5 +18 C8 D4 CB 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D +82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F +BA 1D 66 25 84 12 1E C2 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 C3 78 CB 03 3B 82 93 +BC 1D F4 26 0D 12 84 12 0A C2 94 C7 82 CA 1E CC +7A CB 94 C7 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 1D D8 D3 00 00 30 4D CC CA 0C 43 52 45 +41 54 45 00 B0 12 C2 CB BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 9E C5 0A 44 4F 45 53 3E 1A 42 B8 1D +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D BC CB +0E 3A 4E 4F 4E 41 4D 45 30 12 0C CC 2F 83 8F 4E +00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 56 CC 05 49 53 00 0D 12 82 93 BC 1D +08 20 84 12 4E CB D8 CC 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 66 CB 0A C2 DA CC 82 CA 94 C7 6C CC +08 43 4F 44 45 00 B0 12 C2 CB A2 82 C8 1D 61 3C +AE C7 0E 48 44 4E 43 4F 44 45 B2 40 C6 CD CC 1D +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +1E CC 24 CD 3D 41 92 42 D0 1D CC 1D 5D 3C F0 CC +0E 43 4F 44 45 4E 4E 4D 30 12 FA CC B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +EF 3F 02 CD 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 8E CD B2 40 +A0 CD D0 1D 82 4E CE 1D 30 40 26 C7 85 12 8C CD +8C CB 34 CB 1E CE 30 CD 86 CC D0 C7 7A C8 4C CB +74 CD C6 CC A0 CC 3C CC 94 CA A8 CE D2 C8 00 00 +00 00 85 12 8C CD 22 D5 A6 D3 06 D5 CE D2 2A D3 +78 D3 54 D4 60 D4 F0 D1 14 D3 00 00 00 00 62 CD +E0 D0 00 00 7C D4 C0 CD B2 40 A0 CD CE 1D 82 43 +D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 1D 3A 40 42 18 B0 12 F4 CD 30 4D 06 CE 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D +B0 12 F4 CD 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C4 FE FF +29 83 B9 40 F2 C3 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 F0 FF 3B 40 10 00 3A 40 3A 18 B0 12 +F8 CD 82 43 4A 18 C7 3F 9A CE B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 82 CB 0C 4D 41 52 4B 45 52 00 +12 12 C6 1D 0D 12 84 12 C6 C5 18 C8 80 C8 AC C2 +C6 CE BA C6 5A CA C8 CE 3E 4F 3D 41 B2 41 C6 1D +B0 12 C2 CB BA 40 85 12 FC FF BA 40 98 CE FE FF +28 83 8A 48 00 00 BA 40 82 C2 02 00 A2 52 C8 1D +18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 1D 84 12 18 C8 80 C8 AC C2 32 CF +12 CF 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 98 CE 00 00 01 20 3E 52 2E 83 21 53 +30 41 2A C9 AC C2 3A CF 2E CF 3C CF B2 41 C6 1D +30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 +02 CF 15 20 3E 40 2B 00 B0 12 02 CF 06 20 3E 40 +2D 00 B0 12 02 CF 92 83 C6 1D 0E 12 1E 41 02 00 +84 12 18 C8 2A C9 AC C2 5E CB 7C CF 3E 51 3A 17 +30 41 B0 12 42 CF 19 42 C8 1D 89 4E 00 00 A2 53 +C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 +84 12 18 C8 2A C9 AC C2 B4 CF AC CF 3E 90 10 00 +E6 2B 7C 2D B6 CF A2 41 C6 1D E1 3F 03 20 B0 12 +9A CF 43 3C 7A 90 23 00 24 20 B0 12 4A CF 3C 40 +00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 +20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 +30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 +30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 4A CF +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 96 CF +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 9A CF 92 92 +C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 82 CF F2 3F 03 20 B0 12 9A CF +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 82 CF EA 3F 0C 43 1B 42 C8 1D A2 53 +C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 +FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A C2 00 13 82 CA 94 C7 0A C2 2C 00 78 D0 BC CF +C6 C5 82 D0 5A D0 C8 D0 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 B8 D0 00 40 D4 D0 +0A 4D 4F 56 2E 42 85 12 B8 D0 40 40 00 00 06 41 +44 44 85 12 B8 D0 00 50 EE D0 0A 41 44 44 2E 42 +85 12 B8 D0 40 50 FA D0 08 41 44 44 43 00 85 12 +B8 D0 00 60 08 D1 0C 41 44 44 43 2E 42 00 85 12 +B8 D0 40 60 40 CD 08 53 55 42 43 00 85 12 B8 D0 +00 70 26 D1 0C 53 55 42 43 2E 42 00 85 12 B8 D0 +40 70 34 D1 06 53 55 42 85 12 B8 D0 00 80 44 D1 +0A 53 55 42 2E 42 85 12 B8 D0 40 80 50 D1 06 43 +4D 50 85 12 B8 D0 00 90 5E D1 0A 43 4D 50 2E 42 +85 12 B8 D0 40 90 00 00 08 44 41 44 44 00 85 12 +B8 D0 00 A0 78 D1 0C 44 41 44 44 2E 42 00 85 12 +B8 D0 40 A0 A6 D0 06 42 49 54 85 12 B8 D0 00 B0 +96 D1 0A 42 49 54 2E 42 85 12 B8 D0 40 B0 A2 D1 +06 42 49 43 85 12 B8 D0 00 C0 B0 D1 0A 42 49 43 +2E 42 85 12 B8 D0 40 C0 BC D1 06 42 49 53 85 12 +B8 D0 00 D0 CA D1 0A 42 49 53 2E 42 85 12 B8 D0 +40 D0 00 00 06 58 4F 52 85 12 B8 D0 00 E0 E4 D1 +0A 58 4F 52 2E 42 85 12 B8 D0 40 E0 16 D1 06 41 +4E 44 85 12 B8 D0 00 F0 FE D1 0A 41 4E 44 2E 42 +85 12 B8 D0 40 F0 C6 C5 78 D0 BC CF 1E D2 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F D6 D1 +06 52 52 43 85 12 16 D2 00 10 30 D2 0A 52 52 43 +2E 42 85 12 16 D2 40 10 6A D1 08 53 57 50 42 00 +85 12 16 D2 80 10 3C D2 06 52 52 41 85 12 16 D2 +00 11 58 D2 0A 52 52 41 2E 42 85 12 16 D2 40 11 +4A D2 06 53 58 54 85 12 16 D2 80 11 00 00 08 50 +55 53 48 00 85 12 16 D2 00 12 7E D2 0C 50 55 53 +48 2E 42 00 85 12 16 D2 40 12 72 D2 08 43 41 4C +4C 00 85 12 16 D2 80 12 1A 53 0E 4A 84 12 08 C8 +1E C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 C3 9C D2 06 53 3E 3D 86 12 00 38 C4 D2 04 53 +3C 00 86 12 00 34 8C D2 06 30 3E 3D 86 12 00 30 +D8 D2 04 30 3C 00 86 12 00 30 14 CD 04 55 3C 00 +86 12 00 2C EC D2 06 55 3E 3D 86 12 00 28 E2 D2 +06 30 3C 3E 86 12 00 24 00 D3 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 +A2 53 C8 1D 0E 4A 30 4D 86 D1 08 54 48 45 4E 00 +1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D F6 D2 08 45 +4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 +C8 1D 2F 83 8F 4A 00 00 E3 3F 64 D2 0A 42 45 47 +49 4E 30 40 32 C2 4E D3 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 1D 30 4D 0A D2 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +18 D3 AE C6 94 C7 6C D3 0C 52 45 50 45 41 54 00 +0D 12 84 12 AC D3 30 D3 94 C7 DC D3 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 +30 4D C8 D3 06 42 57 31 85 12 DA D3 00 00 F4 D3 +06 42 57 32 85 12 DA D3 00 00 00 D4 06 42 57 33 +85 12 DA D3 00 00 18 D4 3D 41 1A 42 C8 1D 28 4E +8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 +C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 16 D4 00 00 3C D4 06 46 57 32 85 12 16 D4 +00 00 48 D4 06 46 57 33 85 12 16 D4 00 00 B6 D3 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 4E CB 5A CA 94 C7 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F 82 D0 0A C2 2C 00 18 C8 +2A C9 AC C2 5E CB C6 C5 78 D0 5A D0 AE D4 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E 0C D4 08 52 52 43 +4D 00 85 12 98 D4 50 00 DC D4 08 52 52 41 4D 00 +85 12 98 D4 50 01 EA D4 08 52 4C 41 4D 00 85 12 +98 D4 50 02 F8 D4 08 52 52 55 4D 00 85 12 98 D4 +50 03 0A D3 0A 50 55 53 48 4D 85 12 98 D4 00 15 +14 D5 08 50 4F 50 4D 00 85 12 98 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +D0 C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_24MHz_6MBds.txt b/binaries/MSP_EXP430FR5739_24MHz_6MBds.txt new file mode 100644 index 0000000..f32dbcd --- /dev/null +++ b/binaries/MSP_EXP430FR5739_24MHz_6MBds.txt @@ -0,0 +1,325 @@ +@1800 +C0 5D 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +D0 C4 7E C3 84 C3 54 C3 40 C5 2E D5 E6 CD A0 CD +A0 CD B6 C4 74 C5 3C C5 3C 1D E0 1C 94 C7 B6 C2 +C4 C2 B0 C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +40 C5 2E D5 E6 CD A0 CD A0 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 03 3D 0E 93 3E 4F +98 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B4 C4 B2 49 +72 C5 B2 49 3A C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 5A CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 40 C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 BA C6 AC C2 52 C3 82 C5 1E C2 04 1B +5B 37 6D 00 A4 C5 A4 C5 1E C2 04 1B 5B 30 6D 00 +A4 C5 F0 CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 82 C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 A4 C5 08 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 A4 C5 0A C2 40 FF 32 C2 +D0 C6 D4 C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 86 00 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 +19 42 9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 +0E 49 B0 12 D0 C2 86 C3 00 00 0C 41 43 43 45 50 +54 00 30 40 B6 C4 08 4E 2E 4F 08 5E 39 40 0D 00 +3A 40 20 00 3B 40 14 C5 3C 40 20 C5 5D 15 98 3E +21 52 3A 17 58 42 CC 05 48 9B 09 20 A2 B3 DC 05 +FD 27 B2 40 13 00 CE 05 E2 D2 03 02 30 41 48 9C +06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A +03 2C CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 +CE 05 30 4D 16 C5 2D 83 92 B3 DC 05 DB 23 FC 3F +3E 8F 3D 41 92 B3 DC 05 FD 27 58 42 CC 05 08 4C +EB 3F 00 00 06 4B 45 59 30 40 3C C5 30 12 52 C5 +A2 B3 DC 05 FD 27 B2 40 11 00 CE 05 E2 C2 03 02 +30 41 2F 83 8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 +DC C4 1E 42 CC 05 30 4D 00 00 08 45 4D 49 54 00 +30 40 74 C5 08 4E 3E 4F C7 3F 6A C5 08 45 43 48 +4F 00 B2 40 C2 48 0E C5 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 0E C5 30 4D 00 00 08 54 +59 50 45 00 0D 12 3D 40 B4 C5 29 4F 8F 4E 00 00 +7E 49 DE 3F B6 C5 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 6E 22 F9 98 00 00 6B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 62 22 9B 24 +34 C5 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A C2 +00 00 D4 C6 C6 C5 18 C8 D2 CA B0 C2 42 C6 14 C2 +06 5B 54 48 45 4E 5D 00 CA C5 20 C6 E6 C5 04 C6 +14 C2 06 5B 45 4C 53 45 5D 00 CA C5 32 C6 E6 C5 +02 C6 1E C2 04 5B 49 46 5D 00 CA C5 04 C6 B2 C2 +02 C6 1E C2 05 0D 6B 6F 20 0A A4 C5 9A C2 84 C2 +B2 C2 04 C6 F2 C5 0D 5B 54 48 45 4E 5D 00 30 4D +56 C6 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +62 C6 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +C6 C5 18 C8 80 C8 24 CA 94 C7 72 C6 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 C6 C5 18 C8 +80 C8 A4 C6 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +AA C4 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 C3 05 53 +22 00 82 43 C0 1D 0D 12 84 12 0A C2 1E C2 82 CA +0A C2 22 00 18 C8 18 C7 B2 40 20 00 C0 1D 1A 53 +1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 8C C5 05 2E +22 00 0D 12 84 12 02 C7 0A C2 A4 C5 82 CA 94 C7 +00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D FE C6 +02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 50 C7 +04 23 53 00 0D 12 84 12 52 C7 8C C7 2D 83 09 DE +09 93 E1 23 3D 41 30 4D 80 C7 04 23 3E 00 9F 42 +B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F 9A C7 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 7C C5 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 46 C7 C6 C5 B4 C7 84 C7 B0 C6 C2 C7 9E C7 +A4 C5 94 C7 2E C7 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +06 C8 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 +1E 15 3D 40 8A C9 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 8C C9 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 42 C7 03 5C 92 42 C2 1D +C6 1D 30 4D 0D 12 84 12 84 C2 C6 C5 18 C8 B0 C2 +5C CB 80 C8 46 CA 0A 4E 3E 4F 3D 40 60 CA 6D 27 +3D 40 3A CA 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 +62 CA 3E 4F 3D 40 3A CA 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 38 CC 2A 3C 2A CA +02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F +30 4D 80 CA 0F 4C 49 54 45 52 41 4C 82 93 BC 1D +0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D BC C7 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +E2 C6 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D +3F 40 80 1C 0E 43 84 12 1E C2 02 0D 0A 00 A4 C5 +94 C2 34 CA C2 C6 EC C6 1E C2 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 C3 32 C2 0A C2 40 FF F4 C6 +1E C2 09 46 52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 +F8 CA E2 CA 0D 41 42 4F 52 54 22 00 0D 12 84 12 +02 C7 0A C2 08 C3 82 CA 94 C7 12 C8 02 27 0D 12 +84 12 C6 C5 18 C8 80 C8 B0 C2 5E CB 26 C7 6A CA +8C C6 07 5B 27 5D 0D 12 84 12 4E CB 0A C2 0A C2 +82 CA 82 CA 94 C7 62 CB 03 5B 82 43 BC 1D 30 4D +00 00 02 5D B2 43 BC 1D 30 4D DA C6 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 C6 C5 18 C8 80 C8 +B0 C2 5E CB EC C6 AC C2 B6 CB 0A C2 0A C2 82 CA +82 CA 0A C2 82 CA 82 CA 94 C7 00 00 02 3A 30 12 +0C CC 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 C6 C5 +18 C8 D4 CB 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D +82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F +BA 1D 66 25 84 12 1E C2 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 C3 78 CB 03 3B 82 93 +BC 1D F4 26 0D 12 84 12 0A C2 94 C7 82 CA 1E CC +7A CB 94 C7 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 1D D8 D3 00 00 30 4D CC CA 0C 43 52 45 +41 54 45 00 B0 12 C2 CB BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D 9E C5 0A 44 4F 45 53 3E 1A 42 B8 1D +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D BC CB +0E 3A 4E 4F 4E 41 4D 45 30 12 0C CC 2F 83 8F 4E +00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 56 CC 05 49 53 00 0D 12 82 93 BC 1D +08 20 84 12 4E CB D8 CC 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 66 CB 0A C2 DA CC 82 CA 94 C7 6C CC +08 43 4F 44 45 00 B0 12 C2 CB A2 82 C8 1D 61 3C +AE C7 0E 48 44 4E 43 4F 44 45 B2 40 C6 CD CC 1D +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +1E CC 24 CD 3D 41 92 42 D0 1D CC 1D 5D 3C F0 CC +0E 43 4F 44 45 4E 4E 4D 30 12 FA CC B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +EF 3F 02 CD 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 8E CD B2 40 +A0 CD D0 1D 82 4E CE 1D 30 40 26 C7 85 12 8C CD +8C CB 34 CB 1E CE 30 CD 86 CC D0 C7 7A C8 4C CB +74 CD C6 CC A0 CC 3C CC 94 CA A8 CE D2 C8 00 00 +00 00 85 12 8C CD 22 D5 A6 D3 06 D5 CE D2 2A D3 +78 D3 54 D4 60 D4 F0 D1 14 D3 00 00 00 00 62 CD +E0 D0 00 00 7C D4 C0 CD B2 40 A0 CD CE 1D 82 43 +D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 1D 3A 40 42 18 B0 12 F4 CD 30 4D 06 CE 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D +B0 12 F4 CD 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 06 C4 FE FF +29 83 B9 40 F2 C3 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 F0 FF 3B 40 10 00 3A 40 3A 18 B0 12 +F8 CD 82 43 4A 18 C7 3F 9A CE B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F 82 CB 0C 4D 41 52 4B 45 52 00 +12 12 C6 1D 0D 12 84 12 C6 C5 18 C8 80 C8 AC C2 +C6 CE BA C6 5A CA C8 CE 3E 4F 3D 41 B2 41 C6 1D +B0 12 C2 CB BA 40 85 12 FC FF BA 40 98 CE FE FF +28 83 8A 48 00 00 BA 40 82 C2 02 00 A2 52 C8 1D +18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 1D 84 12 18 C8 80 C8 AC C2 32 CF +12 CF 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 98 CE 00 00 01 20 3E 52 2E 83 21 53 +30 41 2A C9 AC C2 3A CF 2E CF 3C CF B2 41 C6 1D +30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 +02 CF 15 20 3E 40 2B 00 B0 12 02 CF 06 20 3E 40 +2D 00 B0 12 02 CF 92 83 C6 1D 0E 12 1E 41 02 00 +84 12 18 C8 2A C9 AC C2 5E CB 7C CF 3E 51 3A 17 +30 41 B0 12 42 CF 19 42 C8 1D 89 4E 00 00 A2 53 +C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 +84 12 18 C8 2A C9 AC C2 B4 CF AC CF 3E 90 10 00 +E6 2B 7C 2D B6 CF A2 41 C6 1D E1 3F 03 20 B0 12 +9A CF 43 3C 7A 90 23 00 24 20 B0 12 4A CF 3C 40 +00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 +20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 +30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 +30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 4A CF +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 96 CF +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 9A CF 92 92 +C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 82 CF F2 3F 03 20 B0 12 9A CF +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 82 CF EA 3F 0C 43 1B 42 C8 1D A2 53 +C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 +FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A C2 00 13 82 CA 94 C7 0A C2 2C 00 78 D0 BC CF +C6 C5 82 D0 5A D0 C8 D0 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 B8 D0 00 40 D4 D0 +0A 4D 4F 56 2E 42 85 12 B8 D0 40 40 00 00 06 41 +44 44 85 12 B8 D0 00 50 EE D0 0A 41 44 44 2E 42 +85 12 B8 D0 40 50 FA D0 08 41 44 44 43 00 85 12 +B8 D0 00 60 08 D1 0C 41 44 44 43 2E 42 00 85 12 +B8 D0 40 60 40 CD 08 53 55 42 43 00 85 12 B8 D0 +00 70 26 D1 0C 53 55 42 43 2E 42 00 85 12 B8 D0 +40 70 34 D1 06 53 55 42 85 12 B8 D0 00 80 44 D1 +0A 53 55 42 2E 42 85 12 B8 D0 40 80 50 D1 06 43 +4D 50 85 12 B8 D0 00 90 5E D1 0A 43 4D 50 2E 42 +85 12 B8 D0 40 90 00 00 08 44 41 44 44 00 85 12 +B8 D0 00 A0 78 D1 0C 44 41 44 44 2E 42 00 85 12 +B8 D0 40 A0 A6 D0 06 42 49 54 85 12 B8 D0 00 B0 +96 D1 0A 42 49 54 2E 42 85 12 B8 D0 40 B0 A2 D1 +06 42 49 43 85 12 B8 D0 00 C0 B0 D1 0A 42 49 43 +2E 42 85 12 B8 D0 40 C0 BC D1 06 42 49 53 85 12 +B8 D0 00 D0 CA D1 0A 42 49 53 2E 42 85 12 B8 D0 +40 D0 00 00 06 58 4F 52 85 12 B8 D0 00 E0 E4 D1 +0A 58 4F 52 2E 42 85 12 B8 D0 40 E0 16 D1 06 41 +4E 44 85 12 B8 D0 00 F0 FE D1 0A 41 4E 44 2E 42 +85 12 B8 D0 40 F0 C6 C5 78 D0 BC CF 1E D2 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F D6 D1 +06 52 52 43 85 12 16 D2 00 10 30 D2 0A 52 52 43 +2E 42 85 12 16 D2 40 10 6A D1 08 53 57 50 42 00 +85 12 16 D2 80 10 3C D2 06 52 52 41 85 12 16 D2 +00 11 58 D2 0A 52 52 41 2E 42 85 12 16 D2 40 11 +4A D2 06 53 58 54 85 12 16 D2 80 11 00 00 08 50 +55 53 48 00 85 12 16 D2 00 12 7E D2 0C 50 55 53 +48 2E 42 00 85 12 16 D2 40 12 72 D2 08 43 41 4C +4C 00 85 12 16 D2 80 12 1A 53 0E 4A 84 12 08 C8 +1E C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 C3 9C D2 06 53 3E 3D 86 12 00 38 C4 D2 04 53 +3C 00 86 12 00 34 8C D2 06 30 3E 3D 86 12 00 30 +D8 D2 04 30 3C 00 86 12 00 30 14 CD 04 55 3C 00 +86 12 00 2C EC D2 06 55 3E 3D 86 12 00 28 E2 D2 +06 30 3C 3E 86 12 00 24 00 D3 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 +A2 53 C8 1D 0E 4A 30 4D 86 D1 08 54 48 45 4E 00 +1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D F6 D2 08 45 +4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 +C8 1D 2F 83 8F 4A 00 00 E3 3F 64 D2 0A 42 45 47 +49 4E 30 40 32 C2 4E D3 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 1D 30 4D 0A D2 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +18 D3 AE C6 94 C7 6C D3 0C 52 45 50 45 41 54 00 +0D 12 84 12 AC D3 30 D3 94 C7 DC D3 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 +30 4D C8 D3 06 42 57 31 85 12 DA D3 00 00 F4 D3 +06 42 57 32 85 12 DA D3 00 00 00 D4 06 42 57 33 +85 12 DA D3 00 00 18 D4 3D 41 1A 42 C8 1D 28 4E +8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 +C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 16 D4 00 00 3C D4 06 46 57 32 85 12 16 D4 +00 00 48 D4 06 46 57 33 85 12 16 D4 00 00 B6 D3 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 4E CB 5A CA 94 C7 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F 82 D0 0A C2 2C 00 18 C8 +2A C9 AC C2 5E CB C6 C5 78 D0 5A D0 AE D4 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E 0C D4 08 52 52 43 +4D 00 85 12 98 D4 50 00 DC D4 08 52 52 41 4D 00 +85 12 98 D4 50 01 EA D4 08 52 4C 41 4D 00 85 12 +98 D4 50 02 F8 D4 08 52 52 55 4D 00 85 12 98 D4 +50 03 0A D3 0A 50 55 53 48 4D 85 12 98 D4 00 15 +14 D5 08 50 4F 50 4D 00 85 12 98 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +D0 C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_24MHz_I2C.txt b/binaries/MSP_EXP430FR5739_24MHz_I2C.txt index 7c67a8a..a3ea903 100644 --- a/binaries/MSP_EXP430FR5739_24MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5739_24MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -C0 5D 12 00 00 00 F8 00 F9 FF F0 D5 F0 CD 34 01 -10 00 41 87 B6 C3 AA C2 B8 C3 8C C3 82 C4 F0 D5 -F0 CD 70 C4 80 C5 FE C4 DA C4 3C 1D 4E C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 +C0 5D 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +CA C4 56 C3 56 C3 58 C3 44 C3 0A D5 C2 CD 7C CD +7C CD B8 C4 3C C5 14 C5 3C 1D E0 1C 70 C7 B6 C2 +C4 C2 8C C6 20 00 0A 00 00 1C 56 C3 56 C3 58 C3 +44 C3 0A D5 C2 CD 7C CD 7C CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C200 -B0 12 B8 C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 6E C4 B2 49 7E C5 B2 49 FC C4 B2 49 D8 C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C3 0E 12 B0 12 -F8 C2 0A C2 DE 1D CE C5 16 C5 EE C2 34 C2 8A C3 -14 C2 05 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 -C4 C6 96 C5 34 C2 7E C3 14 C2 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C5 8E C6 4A C5 -14 C2 04 1B 5B 30 6D 00 4A C5 16 CA 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C3 04 57 41 52 4D 00 B0 12 -8C C3 78 40 03 00 B0 12 BA C3 84 12 14 C2 07 0D -0A 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 C4 C6 -0A C2 23 00 FA C4 C4 C6 14 C2 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C5 0A C2 40 FF 28 C2 C2 C5 8E C6 -14 C2 0A 62 79 74 65 73 20 66 72 65 65 00 3A C2 -7E C3 00 00 06 41 43 43 45 50 54 00 30 40 70 C4 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C3 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C4 2F 83 8F 4E 00 00 -58 43 B0 12 BA C3 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C4 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 C4 -04 45 43 48 4F 00 B2 40 C2 48 08 C5 82 43 DE 1D -38 40 05 00 B0 12 BA C3 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C5 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C5 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C4 68 C5 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C3 02 43 52 00 30 40 80 C5 -0D 12 84 12 14 C2 02 0D 0A 00 4A C5 4E C6 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C4 01 40 2E 4E -30 4D CC C5 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 C5 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 C6 02 23 53 00 0D 12 84 12 -0A C6 44 C6 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C6 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C5 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C5 -3C C6 EE C2 7C C6 58 C6 4A C5 02 CA FA C4 4E C6 -2C C5 01 2E 0E 93 E3 37 38 43 E2 3F 76 C6 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 48 C9 -0A C2 22 00 1A C7 E8 C6 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 C6 -82 2E 22 00 0D 12 84 12 D2 C6 0A C2 4A C5 48 C9 -4E C6 F8 C3 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C C8 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E C8 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 04 3D 0E 93 3E 4F +86 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B6 C4 B2 49 +3A C5 B2 49 12 C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 36 CE 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C3 B0 12 D0 C2 96 C6 AC C2 +42 C3 54 C5 1E C2 05 1B 5B 37 6D 40 80 C5 0A C2 +02 18 B8 C6 E4 C7 80 C5 1E C2 04 1B 5B 30 6D 00 +80 C5 CC CA 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 54 C5 1E C2 07 0D 0A 1B 5B 37 +6D 40 80 C5 0A C2 02 18 B8 C6 E4 C7 0A C2 23 00 +38 C5 E4 C7 1E C2 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +80 C5 0A C2 40 FF 32 C2 AC C6 B0 C7 1E C2 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C2 36 C3 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C3 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C 92 D3 30 01 B2 43 06 02 +B2 40 EF 7F 02 02 B2 43 26 02 B2 D0 08 FF 22 02 +F2 D3 26 03 F2 40 F0 00 22 03 F2 40 A5 00 61 01 +B2 40 86 00 62 01 82 43 66 01 B2 40 33 00 64 01 +D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 +2A 03 F2 C0 40 00 A1 04 39 40 00 04 29 83 89 43 +00 1C FC 23 1E 42 08 18 82 43 08 18 3E F3 02 20 +1E 42 9E 01 B0 12 D0 C2 80 C3 00 00 0C 41 43 43 +45 50 54 00 30 40 B8 C4 0A 4E 2E 4F 0A 5E 3B 40 +0A 00 3C 40 20 00 3D 15 9B 3E 21 52 A2 C2 6C 06 +B2 B0 10 00 40 06 94 22 3A 17 92 B3 6C 06 FD 27 +58 42 4C 06 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 +2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 +1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 +30 40 14 C5 58 43 B0 12 46 C3 2F 83 8F 4E 00 00 +92 B3 6C 06 FD 27 1E 42 4C 06 B0 12 44 C3 30 4D +00 00 08 45 4D 49 54 00 30 40 3C C5 08 4E 3E 4F +A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D 32 C5 08 45 +43 48 4F 00 B2 40 C2 48 46 C5 38 40 05 00 B0 12 +46 C3 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 46 C5 28 42 F3 3F 00 00 08 54 59 50 45 00 +0D 12 3D 40 90 C5 29 4F 8F 4E 00 00 7E 49 D4 3F +92 C5 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +80 22 F9 98 00 00 7D 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 74 22 9B 24 0C C5 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A C2 00 00 B0 C6 +A2 C5 F4 C7 AE CA B0 C2 1E C6 14 C2 06 5B 54 48 +45 4E 5D 00 A6 C5 FC C5 C2 C5 E0 C5 14 C2 06 5B +45 4C 53 45 5D 00 A6 C5 0E C6 C2 C5 DE C5 1E C2 +04 5B 49 46 5D 00 A6 C5 E0 C5 B2 C2 DE C5 1E C2 +05 0D 6B 6F 20 0A 80 C5 9A C2 84 C2 B2 C2 E0 C5 +CE C5 0D 5B 54 48 45 4E 5D 00 30 4D 32 C6 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 3E C6 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 A2 C5 F4 C7 +5C C8 00 CA 70 C7 4E C6 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 A2 C5 F4 C7 5C C8 80 C6 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D AC C4 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D E0 C3 05 53 22 00 82 43 +C0 1D 0D 12 84 12 0A C2 1E C2 5E CA 0A C2 22 00 +F4 C7 F4 C6 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A +C8 1D 3E 4F 3D 41 30 4D 66 C5 05 2E 22 00 0D 12 +84 12 DE C6 0A C2 80 C5 5E CA 70 C7 00 00 04 3C +23 00 B2 40 B2 1D B2 1D 30 4D DA C6 02 23 1B 42 +BE 1D 2C 4F 2F 83 B0 12 46 C2 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D +18 42 B2 1D C8 4A 00 00 30 4D 2C C7 04 23 53 00 +0D 12 84 12 2E C7 68 C7 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 5C C7 04 23 3E 00 9F 42 B2 1D 00 00 +3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F 76 C7 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 4E C5 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 22 C7 +A2 C5 90 C7 60 C7 8C C6 9E C7 7A C7 80 C5 70 C7 +0A C7 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D E2 C7 0E 3E +4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 +66 C9 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 68 C9 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E C2 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 C9 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C6 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C2 02 CA 1A C7 BE C9 9C 26 -3D 40 C6 C9 DE 3E C8 C9 0A 4E 3E 4F 3D 40 E2 C9 -36 27 3D 40 B8 C9 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 C9 3E 4F 3D 40 B8 C9 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CB CC 3F -EC C9 86 12 20 00 D4 C5 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C C5 BC C2 -B2 C9 B2 C5 E4 C5 14 C2 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 EC C5 -14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C3 -3A C2 2C CA 08 CA 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C6 0A C2 2A C3 48 C9 4E C6 7C C7 01 27 -0D 12 84 12 02 CA 1A C7 82 C7 34 C2 00 CA 4E C6 -00 00 83 5B 27 5D 0D 12 84 12 80 CA 0A C2 0A C2 -48 C9 48 C9 4E C6 92 CA 81 5B 82 43 BE 1D 30 4D -FA C5 01 5D B2 43 BE 1D 30 4D B2 CA 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CA 1A C7 82 C7 96 C5 34 C2 -00 CA E4 C5 34 C2 F4 CA 0A C2 0A C2 48 C9 48 C9 -0A C2 48 C9 48 C9 4E C6 A8 CA 01 3A 30 12 44 CB -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 CA 1A C7 -12 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C3 FA CA 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A C2 4E C6 48 C9 56 CB AA CA 4E C6 -A8 C9 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 C9 06 43 52 45 41 54 -45 00 B0 12 00 CB BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CB 04 43 4F 44 45 00 B0 12 00 CB A2 82 -C6 1D 0D 12 84 12 F2 CD CC CD 4E C6 A2 CB 07 48 -44 4E 43 4F 44 45 B2 40 D0 CD DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CB 0C CE -2A CE 4E C6 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C CE 2A CE 4E C6 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE CB 85 48 49 32 4C 4F 0D 12 84 12 28 C2 9A CD -48 C9 AA CA E2 CB 4E C6 88 CB 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CC 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C2 00 00 C6 C5 02 CA 1A C7 98 C9 -8E C5 34 C2 02 CD 9C C5 14 C2 06 5B 54 48 45 4E -5D 00 74 CC DC CC 98 CC BA CC 4E C6 9C C5 14 C2 -06 5B 45 4C 53 45 5D 00 74 CC F2 CC 98 CC B8 CC -4E C6 14 C2 04 5B 49 46 5D 00 74 CC BA CC 3A C2 -B8 CC 70 C5 14 C2 05 0D 0A 6B 6F 20 4A C5 BC C2 -AC C2 3A C2 BA CC A8 CC 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CD 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CA 1A C7 82 C7 -26 CD 4E C6 2C CD 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CD DE C5 4E C6 5E CD B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A C9 06 4D -41 52 4B 45 52 00 B0 12 00 CB BA 40 85 12 FC FF -BA 40 5C CD FE FF 28 83 8A 48 00 00 BA 40 AA C2 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A C2 -CA 1D D6 C5 4E C6 85 12 9E CD 66 CA D4 CB 10 C5 -7E CA 52 CC D2 C4 6E CD 00 C7 96 CE AA CE 8A C6 -14 C7 00 00 46 CD BC CA E2 C7 00 00 85 12 9E CD -66 D4 CC D4 0E D4 1C D5 D4 D3 00 00 A0 D1 00 00 -E4 D5 C8 D5 38 D4 76 D4 B0 D2 00 00 00 00 38 D5 -CA CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 CD 24 CE 2A CE 3A CE 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CA -09 50 57 52 5F 53 54 41 54 45 85 12 32 CE F0 D5 -CE C6 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E CE F3 3F 70 CE 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E CE 30 4D 82 CE 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 CF FE FF 29 83 B9 40 -E2 C3 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C3 B2 49 FA C2 B2 49 02 C2 B2 49 00 C4 B2 49 -EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 92 D3 -30 01 B2 43 06 02 B2 40 EF 7F 02 02 B2 43 26 02 -B2 D0 08 FF 22 02 F2 D3 26 03 F2 40 F0 00 22 03 -F2 40 A5 00 61 01 B2 40 86 00 62 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 92 C3 -B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 1E 42 -08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 C2 FE C3 -38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D -09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A -C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 1A C7 -82 C7 DE C5 34 C2 E0 CF 3E C8 34 C2 FA CF F4 CF -E2 CF 3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E -01 3C 2E 83 21 52 1B 17 30 41 FC CF B2 41 C4 1D -3E 41 84 12 0A C2 2B 00 1A C7 82 C7 DE C5 34 C2 -18 D0 3E C8 34 C2 00 CA A8 C5 1A C7 3E C8 34 C2 -00 CA 24 D0 3E 5F E7 3F 3E 40 28 00 B0 12 C4 CF -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 -92 92 C0 1D C4 1D 02 20 30 40 6E CB 1C 15 12 12 -C4 1D 92 53 C4 1D 84 12 1A C7 3E C8 34 C2 6C D0 -62 D0 21 53 3E 90 10 00 C6 2B 7F 2D 6E D0 B2 41 -C4 1D C1 3F 0D 12 84 12 02 CA A0 CF 7E D0 0C 43 -1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 -27 20 92 53 C4 1D B0 12 C4 CF 3C 40 00 03 0E 93 +2F 53 30 4D 1E C7 03 5C 92 42 C2 1D C6 1D 30 4D +0D 12 84 12 84 C2 A2 C5 F4 C7 B0 C2 38 CB 5C C8 +22 CA 0A 4E 3E 4F 3D 40 3C CA 6D 27 3D 40 16 CA +1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 3E CA 3E 4F +3D 40 16 CA 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 14 CC 2A 3C 06 CA 02 2C A2 53 +C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 5C CA +0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E +1A 42 C8 1D A2 52 C8 1D BA 40 0A C2 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D 98 C7 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D BE C6 0A 41 +4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C +0E 43 84 12 1E C2 02 0D 0A 00 80 C5 94 C2 10 CA +9E C6 C8 C6 1E C2 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 C3 32 C2 0A C2 40 FF D0 C6 1E C2 09 46 +52 41 4D 20 66 75 6C 6C 08 C3 B2 C2 D4 CA BE CA +0D 41 42 4F 52 54 22 00 0D 12 84 12 DE C6 0A C2 +08 C3 5E CA 70 C7 EE C7 02 27 0D 12 84 12 A2 C5 +F4 C7 5C C8 B0 C2 3A CB 02 C7 46 CA 68 C6 07 5B +27 5D 0D 12 84 12 2A CB 0A C2 0A C2 5E CA 5E CA +70 C7 3E CB 03 5B 82 43 BC 1D 30 4D 00 00 02 5D +B2 43 BC 1D 30 4D B6 C6 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 A2 C5 F4 C7 5C C8 B0 C2 3A CB +C8 C6 AC C2 92 CB 0A C2 0A C2 5E CA 5E CA 0A C2 +5E CA 5E CA 70 C7 00 00 02 3A 30 12 E8 CB 92 B3 +C8 1D A2 63 C8 1D 0D 12 84 12 A2 C5 F4 C7 B0 CB +3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D +2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 +84 12 1E C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 C3 54 CB 03 3B 82 93 BC 1D F4 26 +0D 12 84 12 0A C2 70 C7 5E CA FA CB 56 CB 70 C7 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D +D8 D3 00 00 30 4D A8 CA 0C 43 52 45 41 54 45 00 +B0 12 9E CB BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +7A C5 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D 98 CB 0E 3A 4E 4F +4E 41 4D 45 30 12 E8 CB 2F 83 8F 4E 00 00 1A 42 +C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +32 CC 05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 +2A CB B4 CC 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +42 CB 0A C2 B6 CC 5E CA 70 C7 48 CC 08 43 4F 44 +45 00 B0 12 9E CB A2 82 C8 1D 61 3C 8A C7 0E 48 +44 4E 43 4F 44 45 B2 40 A2 CD CC 1D F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 FA CB 00 CD +3D 41 92 42 D0 1D CC 1D 5D 3C CC CC 0E 43 4F 44 +45 4E 4E 4D 30 12 D6 CC B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F DE CC +0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A +FE FF 82 43 BC 1D B9 3F 6A CD B2 40 7C CD D0 1D +82 4E CE 1D 30 40 02 C7 85 12 68 CD 68 CB 10 CB +FA CD 0C CD 62 CC AC C7 56 C8 28 CB 50 CD A2 CC +7C CC 18 CC 70 CA 84 CE AE C8 00 00 00 00 85 12 +68 CD FE D4 82 D3 E2 D4 AA D2 06 D3 54 D3 30 D4 +3C D4 CC D1 F0 D2 00 00 00 00 3E CD BC D0 00 00 +58 D4 9C CD B2 40 7C CD CE 1D 82 43 D0 1D 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 +42 18 B0 12 D0 CD 30 4D E2 CD 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 D0 CD +1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 0E C4 FE FF 29 83 B9 40 +FA C3 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +EE FF 3B 40 10 00 3A 40 3A 18 B0 12 D4 CD 82 43 +4A 18 C7 3F 76 CE B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 5E CB 0C 4D 41 52 4B 45 52 00 12 12 C6 1D +0D 12 84 12 A2 C5 F4 C7 5C C8 AC C2 A2 CE 96 C6 +36 CA A4 CE 3E 4F 3D 41 B2 41 C6 1D B0 12 9E CB +BA 40 85 12 FC FF BA 40 74 CE FE FF 28 83 8A 48 +00 00 BA 40 82 C2 02 00 A2 52 C8 1D 18 42 B4 1D +19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 1D 84 12 F4 C7 5C C8 AC C2 0E CF EE CE 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +74 CE 00 00 01 20 3E 52 2E 83 21 53 30 41 06 C9 +AC C2 16 CF 0A CF 18 CF B2 41 C6 1D 30 41 92 83 +C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 DE CE 15 20 +3E 40 2B 00 B0 12 DE CE 06 20 3E 40 2D 00 B0 12 +DE CE 92 83 C6 1D 0E 12 1E 41 02 00 84 12 F4 C7 +06 C9 AC C2 3A CB 58 CF 3E 51 3A 17 30 41 B0 12 +1E CF 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 +29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 F4 C7 +06 C9 AC C2 90 CF 88 CF 3E 90 10 00 E6 2B 7C 2D +92 CF A2 41 C6 1D E1 3F 03 20 B0 12 76 CF 43 3C +7A 90 23 00 24 20 B0 12 26 CF 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D -7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 -C4 CF ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 -C4 1D B0 12 4C D0 0C 20 3C 50 10 00 3E 40 2B 00 -B0 12 4C D0 92 92 C0 1D C4 1D 02 24 92 53 C4 1D -8E 10 0C 5E DA 3F B0 12 4C D0 FA 23 3C 50 10 00 -B0 12 28 D0 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D -0D 12 84 12 02 CA A0 CF 4A D1 FE 90 26 00 00 00 -3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 4C D0 -E0 23 3C 50 80 00 B0 12 28 D0 DB 3F 00 00 04 52 -45 54 49 00 0D 12 84 12 0A C2 00 13 48 C9 4E C6 -0A C2 2C 00 74 D0 40 D1 8A D1 09 4B 2E 4E 0E DC -A2 3F 40 CC 03 4D 4F 56 85 12 80 D1 00 40 94 D1 -05 4D 4F 56 2E 42 85 12 80 D1 40 40 00 00 03 41 -44 44 85 12 80 D1 00 50 AE D1 05 41 44 44 2E 42 -85 12 80 D1 40 50 BA D1 04 41 44 44 43 00 85 12 -80 D1 00 60 C8 D1 06 41 44 44 43 2E 42 00 85 12 -80 D1 40 60 6E D1 04 53 55 42 43 00 85 12 80 D1 -00 70 E6 D1 06 53 55 42 43 2E 42 00 85 12 80 D1 -40 70 F4 D1 03 53 55 42 85 12 80 D1 00 80 04 D2 -05 53 55 42 2E 42 85 12 80 D1 40 80 16 CC 03 43 -4D 50 85 12 80 D1 00 90 1E D2 05 43 4D 50 2E 42 -85 12 80 D1 40 90 00 CC 04 44 41 44 44 00 85 12 -80 D1 00 A0 38 D2 06 44 41 44 44 2E 42 00 85 12 -80 D1 40 A0 2A D2 03 42 49 54 85 12 80 D1 00 B0 -56 D2 05 42 49 54 2E 42 85 12 80 D1 40 B0 62 D2 -03 42 49 43 85 12 80 D1 00 C0 70 D2 05 42 49 43 -2E 42 85 12 80 D1 40 C0 7C D2 03 42 49 53 85 12 -80 D1 00 D0 8A D2 05 42 49 53 2E 42 85 12 80 D1 -40 D0 00 00 03 58 4F 52 85 12 80 D1 00 E0 A4 D2 -05 58 4F 52 2E 42 85 12 80 D1 40 E0 D6 D1 03 41 -4E 44 85 12 80 D1 00 F0 BE D2 05 41 4E 44 2E 42 -85 12 80 D1 40 F0 02 CA 74 D0 DC D2 0A 4C 3C F0 -70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 10 D2 03 52 -52 43 85 12 D6 D2 00 10 EE D2 05 52 52 43 2E 42 -85 12 D6 D2 40 10 FA D2 04 53 57 50 42 00 85 12 -D6 D2 80 10 08 D3 03 52 52 41 85 12 D6 D2 00 11 -16 D3 05 52 52 41 2E 42 85 12 D6 D2 40 11 22 D3 -03 53 58 54 85 12 D6 D2 80 11 00 00 04 50 55 53 -48 00 85 12 D6 D2 00 12 3C D3 06 50 55 53 48 2E -42 00 85 12 D6 D2 40 12 96 D2 04 43 41 4C 4C 00 -85 12 D6 D2 80 12 1A 53 0E 4A 0D 12 84 12 C4 C6 -14 C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 -36 C3 30 D3 03 53 3E 3D 86 12 00 38 84 D3 02 53 -3C 00 86 12 00 34 4A D3 03 30 3E 3D 86 12 00 30 -98 D3 02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 -86 12 00 2C AC D3 03 55 3E 3D 86 12 00 28 A2 D3 -03 30 3C 3E 86 12 00 24 C0 D3 02 30 3D 00 86 12 -00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 0E 4A 30 4D B6 D3 04 54 48 45 4E 00 -1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 -3A 90 00 02 B1 2F 88 DA 00 00 30 4D 46 D2 04 45 -4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 -C6 1D 2F 83 8F 4A 00 00 E3 3F 5A D3 05 42 45 47 -49 4E 30 40 28 C2 EA D3 05 55 4E 54 49 4C 3A 4F -08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 -00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 -C6 1D 30 4D CA D2 05 41 47 41 49 4E 0A 4E 38 40 -00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 -D8 D3 A8 C5 4E C6 8E D3 06 52 45 50 45 41 54 00 -0D 12 84 12 6C D4 F0 D3 4E C6 9C D4 3D 41 08 4E -3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 -30 4D 2C D4 03 42 57 31 85 12 9A D4 00 00 B4 D4 -03 42 57 32 85 12 9A D4 00 00 C0 D4 03 42 57 33 -85 12 9A D4 00 00 D8 D4 3D 41 1A 42 C6 1D 28 4E -B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A -00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 D6 D4 -00 00 F8 D4 03 46 57 32 85 12 D6 D4 00 00 04 D5 -03 46 57 33 85 12 D6 D4 00 00 10 D5 04 47 4F 54 +C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 26 CF F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 72 CF 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 76 CF 92 92 C2 1D C6 1D +02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 5E CF F2 3F 03 20 B0 12 76 CF F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +5E CF EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 +20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 +FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A C2 00 13 +5E CA 70 C7 0A C2 2C 00 54 D0 98 CF A2 C5 5E D0 +36 D0 A4 D0 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 94 D0 00 40 B0 D0 0A 4D 4F 56 +2E 42 85 12 94 D0 40 40 00 00 06 41 44 44 85 12 +94 D0 00 50 CA D0 0A 41 44 44 2E 42 85 12 94 D0 +40 50 D6 D0 08 41 44 44 43 00 85 12 94 D0 00 60 +E4 D0 0C 41 44 44 43 2E 42 00 85 12 94 D0 40 60 +1C CD 08 53 55 42 43 00 85 12 94 D0 00 70 02 D1 +0C 53 55 42 43 2E 42 00 85 12 94 D0 40 70 10 D1 +06 53 55 42 85 12 94 D0 00 80 20 D1 0A 53 55 42 +2E 42 85 12 94 D0 40 80 2C D1 06 43 4D 50 85 12 +94 D0 00 90 3A D1 0A 43 4D 50 2E 42 85 12 94 D0 +40 90 00 00 08 44 41 44 44 00 85 12 94 D0 00 A0 +54 D1 0C 44 41 44 44 2E 42 00 85 12 94 D0 40 A0 +82 D0 06 42 49 54 85 12 94 D0 00 B0 72 D1 0A 42 +49 54 2E 42 85 12 94 D0 40 B0 7E D1 06 42 49 43 +85 12 94 D0 00 C0 8C D1 0A 42 49 43 2E 42 85 12 +94 D0 40 C0 98 D1 06 42 49 53 85 12 94 D0 00 D0 +A6 D1 0A 42 49 53 2E 42 85 12 94 D0 40 D0 00 00 +06 58 4F 52 85 12 94 D0 00 E0 C0 D1 0A 58 4F 52 +2E 42 85 12 94 D0 40 E0 F2 D0 06 41 4E 44 85 12 +94 D0 00 F0 DA D1 0A 41 4E 44 2E 42 85 12 94 D0 +40 F0 A2 C5 54 D0 98 CF FA D1 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F B2 D1 06 52 52 43 +85 12 F2 D1 00 10 0C D2 0A 52 52 43 2E 42 85 12 +F2 D1 40 10 46 D1 08 53 57 50 42 00 85 12 F2 D1 +80 10 18 D2 06 52 52 41 85 12 F2 D1 00 11 34 D2 +0A 52 52 41 2E 42 85 12 F2 D1 40 11 26 D2 06 53 +58 54 85 12 F2 D1 80 11 00 00 08 50 55 53 48 00 +85 12 F2 D1 00 12 5A D2 0C 50 55 53 48 2E 42 00 +85 12 F2 D1 40 12 4E D2 08 43 41 4C 4C 00 85 12 +F2 D1 80 12 1A 53 0E 4A 84 12 E4 C7 1E C2 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 C3 78 D2 +06 53 3E 3D 86 12 00 38 A0 D2 04 53 3C 00 86 12 +00 34 68 D2 06 30 3E 3D 86 12 00 30 B4 D2 04 30 +3C 00 86 12 00 30 F0 CC 04 55 3C 00 86 12 00 2C +C8 D2 06 55 3E 3D 86 12 00 28 BE D2 06 30 3C 3E +86 12 00 24 DC D2 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D +0E 4A 30 4D 62 D1 08 54 48 45 4E 00 1A 42 C8 1D +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D D2 D2 08 45 4C 53 45 00 +1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 +8F 4A 00 00 E3 3F 40 D2 0A 42 45 47 49 4E 30 40 +32 C2 2A D3 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D +E6 D1 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 F4 D2 8A C6 +70 C7 48 D3 0C 52 45 50 45 41 54 00 0D 12 84 12 +88 D3 0C D3 70 C7 B8 D3 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D A4 D3 +06 42 57 31 85 12 B6 D3 00 00 D0 D3 06 42 57 32 +85 12 B6 D3 00 00 DC D3 06 42 57 33 85 12 B6 D3 +00 00 F4 D3 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 +B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 F2 D3 +00 00 18 D4 06 46 57 32 85 12 F2 D3 00 00 24 D4 +06 46 57 33 85 12 F2 D3 00 00 92 D3 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 -80 CA DC C9 4E C6 00 00 05 3F 47 4F 54 4F 3E 90 +2A CB 36 CA 70 C7 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 -00 08 EC 3F 02 CA A0 CF 5A D5 92 53 C4 1D 3E 40 -2C 00 84 12 1A C7 3E C8 34 C2 00 CA 36 D1 70 D5 -0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C -59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E -AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 88 D4 04 52 -52 43 4D 00 85 12 54 D5 50 00 9E D5 04 52 52 41 -4D 00 85 12 54 D5 50 01 AC D5 04 52 4C 41 4D 00 -85 12 54 D5 50 02 BA D5 04 52 52 55 4D 00 85 12 -54 D5 50 03 CA D3 05 50 55 53 48 4D 85 12 54 D5 -00 15 D6 D5 04 50 4F 50 4D 00 85 12 54 D5 00 17 +00 08 EC 3F 5E D0 0A C2 2C 00 F4 C7 06 C9 AC C2 +3A CB A2 C5 54 D0 36 D0 8A D4 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E E8 D3 08 52 52 43 4D 00 85 12 +74 D4 50 00 B8 D4 08 52 52 41 4D 00 85 12 74 D4 +50 01 C6 D4 08 52 4C 41 4D 00 85 12 74 D4 50 02 +D4 D4 08 52 52 55 4D 00 85 12 74 D4 50 03 E6 D2 +0A 50 55 53 48 4D 85 12 74 D4 00 15 F0 D4 08 50 +4F 50 4D 00 85 12 74 D4 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 82 C4 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 08 CF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 CA C4 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 0E C4 q diff --git a/binaries/MSP_EXP430FR5739_24MHz_UART.txt b/binaries/MSP_EXP430FR5739_24MHz_UART.txt deleted file mode 100644 index 59902a7..0000000 --- a/binaries/MSP_EXP430FR5739_24MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -C0 5D 0D 00 01 49 18 00 F9 FF 06 D6 02 CE 34 01 -10 00 41 B3 94 C3 AA C2 DA C3 9C C3 94 C4 06 D6 -02 CE 7A C4 92 C5 24 C5 FE C4 3C 1D 60 C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 -@C200 -B0 12 DA C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 78 C4 B2 49 90 C5 B2 49 22 C5 B2 49 FC C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C3 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 C2 0A C2 DE 1D E0 C5 32 C5 -14 C2 04 1B 5B 37 6D 00 5C C5 A8 C5 34 C2 86 C3 -14 C2 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C5 A0 C6 5C C5 14 C2 04 1B 5B 30 6D 00 -5C C5 28 CA 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 03 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C3 04 57 41 52 4D 00 B0 12 -9C C3 84 12 14 C2 07 0D 0A 1B 5B 37 6D 23 5C C5 -D6 C6 14 C2 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C5 -0A C2 40 FF 28 C2 D4 C5 A0 C6 14 C2 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C2 86 C3 00 00 06 41 -43 43 45 50 54 00 30 40 7A C4 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C4 3C 40 D2 C4 -5D 15 B6 3E 21 52 3A 17 58 42 CC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 -C2 48 CE 05 30 4D C8 C4 2D 83 92 B3 DC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 DC 05 -FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C4 2F 83 -8F 4E 00 00 B0 12 DA C3 92 B3 DC 05 FD 27 1E 42 -CC 05 B0 12 C8 C3 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C5 08 4E 3E 4F C8 3F 1A C5 04 45 43 48 -4F 00 B2 40 C2 48 C0 C4 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C4 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C5 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C5 7A C5 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C3 02 43 52 00 30 40 -92 C5 0D 12 84 12 14 C2 02 0D 0A 00 5C C5 60 C6 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C4 01 40 -2E 4E 30 4D DE C5 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A C5 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A C6 02 23 53 00 0D 12 -84 12 1C C6 56 C6 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C6 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C5 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C6 4E C6 EE C2 8E C6 6A C6 5C C5 14 CA 20 C5 -60 C6 40 C5 01 2E 0E 93 E3 37 38 43 E2 3F 88 C6 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 -5A C9 0A C2 22 00 2C C7 FA C6 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 C6 82 2E 22 00 0D 12 84 12 E4 C6 0A C2 5C C5 -5A C9 60 C6 18 C4 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE C8 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 C8 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 C9 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C6 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C2 14 CA 2C C7 D0 C9 -9C 26 3D 40 D8 C9 DE 3E DA C9 0A 4E 3E 4F 3D 40 -F4 C9 36 27 3D 40 CA C9 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 C9 3E 4F 3D 40 CA C9 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CB -CC 3F FE C9 86 12 20 00 E6 C5 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E C5 -BC C2 C4 C9 C4 C5 F6 C5 14 C2 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 -FE C5 14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C3 3A C2 3E CA 1A CA 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C6 0A C2 2A C3 5A C9 60 C6 8E C7 -01 27 0D 12 84 12 14 CA 2C C7 94 C7 34 C2 12 CA -60 C6 00 00 83 5B 27 5D 0D 12 84 12 92 CA 0A C2 -0A C2 5A C9 5A C9 60 C6 A4 CA 81 5B 82 43 BE 1D -30 4D 0C C6 01 5D B2 43 BE 1D 30 4D C4 CA 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CA 2C C7 94 C7 A8 C5 -34 C2 12 CA F6 C5 34 C2 06 CB 0A C2 0A C2 5A C9 -5A C9 0A C2 5A C9 5A C9 60 C6 BA CA 01 3A 30 12 -56 CB 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 CA -2C C7 24 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C3 0C CB 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A C2 60 C6 5A C9 68 CB BC CA -60 C6 BA C9 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 C9 06 43 52 45 -41 54 45 00 B0 12 12 CB BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CB 04 43 4F 44 45 00 B0 12 12 CB -A2 82 C6 1D 0D 12 84 12 04 CE DE CD 60 C6 B4 CB -07 48 44 4E 43 4F 44 45 B2 40 E2 CD DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CB -1E CE 3C CE 60 C6 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E CE 3C CE 60 C6 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 CC 85 48 49 32 4C 4F 0D 12 84 12 28 C2 -AC CD 5A C9 BC CA F4 CB 60 C6 9A CB 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CC 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C2 00 00 D8 C5 14 CA 2C C7 -AA C9 A0 C5 34 C2 14 CD AE C5 14 C2 06 5B 54 48 -45 4E 5D 00 86 CC EE CC AA CC CC CC 60 C6 AE C5 -14 C2 06 5B 45 4C 53 45 5D 00 86 CC 04 CD AA CC -CA CC 60 C6 14 C2 04 5B 49 46 5D 00 86 CC CC CC -3A C2 CA CC 82 C5 14 C2 05 0D 0A 6B 6F 20 5C C5 -BC C2 AC C2 3A C2 CC CC BA CC 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CD 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CA 2C C7 -94 C7 38 CD 60 C6 3E CD 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CD F0 C5 60 C6 70 CD -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C C9 -06 4D 41 52 4B 45 52 00 B0 12 12 CB BA 40 85 12 -FC FF BA 40 6E CD FE FF 28 83 8A 48 00 00 BA 40 -AA C2 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A C2 CA 1D E8 C5 60 C6 85 12 B0 CD 78 CA E6 CB -2C C5 90 CA 64 CC F6 C4 80 CD 12 C7 A8 CE BC CE -9C C6 26 C7 00 00 58 CD CE CA F4 C7 00 00 85 12 -B0 CD 7C D4 E2 D4 24 D4 32 D5 EA D3 00 00 B6 D1 -00 00 FA D5 DE D5 4E D4 8C D4 C6 D2 00 00 00 00 -4E D5 DC CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 CD 36 CE 3C CE 4C CE 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CA 09 50 57 52 5F 53 54 41 54 45 85 12 44 CE -06 D6 E0 C6 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 CE F3 3F 82 CE 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 CE 30 4D 94 CE 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A CF FE FF 29 83 -B9 40 02 C4 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C4 B2 49 FA C2 B2 49 02 C2 B2 49 20 C4 -B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 -92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 -05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 -F2 40 F0 00 22 03 F2 40 A5 00 61 01 B2 40 86 00 -62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 -40 00 A1 04 1E 42 08 18 82 43 08 18 1E D2 9E 01 -B0 12 F8 C2 1E C4 38 40 C0 1D 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 12 12 -C4 1D 84 12 2C C7 94 C7 F0 C5 34 C2 F6 CF 50 C8 -34 C2 10 D0 0A D0 F8 CF 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -12 D0 B2 41 C4 1D 3E 41 84 12 0A C2 2B 00 2C C7 -94 C7 F0 C5 34 C2 2E D0 50 C8 34 C2 12 CA BA C5 -2C C7 50 C8 34 C2 12 CA 3A D0 3E 5F E7 3F 3E 40 -28 00 B0 12 DA CF 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 30 40 -80 CB 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 2C C7 -50 C8 34 C2 82 D0 78 D0 21 53 3E 90 10 00 C6 2B -7F 2D 84 D0 B2 41 C4 1D C1 3F 0D 12 84 12 14 CA -B6 CF 94 D0 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E -3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 DA CF -3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 -3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 -3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 -3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 -3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 -92 53 C4 1D B0 12 DA CF ED 3F 7A 90 40 00 16 20 -3C 40 20 00 92 53 C4 1D B0 12 62 D0 0C 20 3C 50 -10 00 3E 40 2B 00 B0 12 62 D0 92 92 C0 1D C4 1D -02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 62 D0 -FA 23 3C 50 10 00 B0 12 3E D0 EF 3F 0C 43 1B 42 -C6 1D A2 53 C6 1D 0D 12 84 12 14 CA B6 CF 60 D1 -FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 -C7 3F B0 12 62 D0 E0 23 3C 50 80 00 B0 12 3E D0 -DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 0A C2 -00 13 5A C9 60 C6 0A C2 2C 00 8A D0 56 D1 A0 D1 -09 4B 2E 4E 0E DC A2 3F 52 CC 03 4D 4F 56 85 12 -96 D1 00 40 AA D1 05 4D 4F 56 2E 42 85 12 96 D1 -40 40 00 00 03 41 44 44 85 12 96 D1 00 50 C4 D1 -05 41 44 44 2E 42 85 12 96 D1 40 50 D0 D1 04 41 -44 44 43 00 85 12 96 D1 00 60 DE D1 06 41 44 44 -43 2E 42 00 85 12 96 D1 40 60 84 D1 04 53 55 42 -43 00 85 12 96 D1 00 70 FC D1 06 53 55 42 43 2E -42 00 85 12 96 D1 40 70 0A D2 03 53 55 42 85 12 -96 D1 00 80 1A D2 05 53 55 42 2E 42 85 12 96 D1 -40 80 28 CC 03 43 4D 50 85 12 96 D1 00 90 34 D2 -05 43 4D 50 2E 42 85 12 96 D1 40 90 12 CC 04 44 -41 44 44 00 85 12 96 D1 00 A0 4E D2 06 44 41 44 -44 2E 42 00 85 12 96 D1 40 A0 40 D2 03 42 49 54 -85 12 96 D1 00 B0 6C D2 05 42 49 54 2E 42 85 12 -96 D1 40 B0 78 D2 03 42 49 43 85 12 96 D1 00 C0 -86 D2 05 42 49 43 2E 42 85 12 96 D1 40 C0 92 D2 -03 42 49 53 85 12 96 D1 00 D0 A0 D2 05 42 49 53 -2E 42 85 12 96 D1 40 D0 00 00 03 58 4F 52 85 12 -96 D1 00 E0 BA D2 05 58 4F 52 2E 42 85 12 96 D1 -40 E0 EC D1 03 41 4E 44 85 12 96 D1 00 F0 D4 D2 -05 41 4E 44 2E 42 85 12 96 D1 40 F0 14 CA 8A D0 -F2 D2 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA -4F 3F 26 D2 03 52 52 43 85 12 EC D2 00 10 04 D3 -05 52 52 43 2E 42 85 12 EC D2 40 10 10 D3 04 53 -57 50 42 00 85 12 EC D2 80 10 1E D3 03 52 52 41 -85 12 EC D2 00 11 2C D3 05 52 52 41 2E 42 85 12 -EC D2 40 11 38 D3 03 53 58 54 85 12 EC D2 80 11 -00 00 04 50 55 53 48 00 85 12 EC D2 00 12 52 D3 -06 50 55 53 48 2E 42 00 85 12 EC D2 40 12 AC D2 -04 43 41 4C 4C 00 85 12 EC D2 80 12 1A 53 0E 4A -0D 12 84 12 D6 C6 14 C2 0D 6F 75 74 20 6F 66 20 -62 6F 75 6E 64 73 36 C3 46 D3 03 53 3E 3D 86 12 -00 38 9A D3 02 53 3C 00 86 12 00 34 60 D3 03 30 -3E 3D 86 12 00 30 AE D3 02 30 3C 00 86 12 00 30 -00 00 02 55 3C 00 86 12 00 2C C2 D3 03 55 3E 3D -86 12 00 28 B8 D3 03 30 3C 3E 86 12 00 24 D6 D3 -02 30 3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 -C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D CC D3 -04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 -29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 -30 4D 5C D2 04 45 4C 53 45 00 1A 42 C6 1D BA 40 -00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F -70 D3 05 42 45 47 49 4E 30 40 28 C2 00 D4 05 55 -4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 -0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA -89 48 00 00 A2 53 C6 1D 30 4D E0 D2 05 41 47 41 -49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 -4C 45 0D 12 84 12 EE D3 BA C5 60 C6 A4 D3 06 52 -45 50 45 41 54 00 0D 12 84 12 82 D4 06 D4 60 C6 -B2 D4 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F -98 42 C6 1D 00 00 30 4D 42 D4 03 42 57 31 85 12 -B0 D4 00 00 CA D4 03 42 57 32 85 12 B0 D4 00 00 -D6 D4 03 42 57 33 85 12 B0 D4 00 00 EE D4 3D 41 -1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F 00 00 -A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 -57 31 85 12 EC D4 00 00 0E D5 03 46 57 32 85 12 -EC D4 00 00 1A D5 03 46 57 33 85 12 EC D4 00 00 -26 D5 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 -00 3C 0D 12 84 12 92 CA EE C9 60 C6 00 00 05 3F -47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 -00 10 EF 27 3E E0 00 08 EC 3F 14 CA B6 CF 70 D5 -92 53 C4 1D 3E 40 2C 00 84 12 2C C7 50 C8 34 C2 -12 CA 4C D1 86 D5 0A 4E 3E 4F 1A 83 F7 32 29 4E -59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 -10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 -A6 3E 9E D4 04 52 52 43 4D 00 85 12 6A D5 50 00 -B4 D5 04 52 52 41 4D 00 85 12 6A D5 50 01 C2 D5 -04 52 4C 41 4D 00 85 12 6A D5 50 02 D0 D5 04 52 -52 55 4D 00 85 12 6A D5 50 03 E0 D3 05 50 55 53 -48 4D 85 12 6A D5 00 15 EC D5 04 50 4F 50 4D 00 -85 12 6A D5 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -94 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 1A CF -q diff --git a/binaries/MSP_EXP430FR5739_8MHz_115200.txt b/binaries/MSP_EXP430FR5739_8MHz_115200.txt new file mode 100644 index 0000000..df51f29 --- /dev/null +++ b/binaries/MSP_EXP430FR5739_8MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 59 +CA C4 7E C3 84 C3 54 C3 3A C5 28 D5 E0 CD 9A CD +9A CD B0 C4 6E C5 36 C5 3C 1D E0 1C 8E C7 B6 C2 +C4 C2 AA C6 20 00 0A 00 00 1C 7E C3 84 C3 54 C3 +3A C5 28 D5 E0 CD 9A CD 9A CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@C200 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 00 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AE C4 B2 49 +6C C5 B2 49 34 C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 54 CE 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 3A C5 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 C2 B4 C6 AC C2 52 C3 7C C5 1E C2 04 1B +5B 37 6D 00 9E C5 9E C5 1E C2 04 1B 5B 30 6D 00 +9E C5 EA CA B0 12 7E C3 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 7C C5 1E C2 +07 0D 0A 1B 5B 37 6D 23 9E C5 02 C8 1E C2 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9E C5 0A C2 40 FF 32 C2 +CA C6 CE C7 1E C2 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 C2 46 C3 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 C3 01 12 71 3F 82 4E +08 18 92 12 3A 18 D2 B3 21 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 +05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 +F2 40 F0 00 22 03 F2 40 A5 00 61 01 82 43 66 01 +B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 92 C3 +B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 39 40 +00 04 29 83 89 43 00 1C FC 23 19 42 9E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 C2 +86 C3 00 00 0C 41 43 43 45 50 54 00 30 40 B0 C4 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +0E C5 3C 40 1A C5 5D 15 9B 3E 21 52 3A 17 58 42 +CC 05 48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 13 00 +CE 05 E2 D2 03 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D 10 C5 +2D 83 92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +DC 05 FD 27 58 42 CC 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 36 C5 30 12 4C C5 A2 B3 DC 05 FD 27 +B2 40 11 00 CE 05 E2 C2 03 02 30 41 2F 83 8F 4E +00 00 92 B3 DC 05 FD 27 B0 12 D6 C4 1E 42 CC 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 6E C5 08 4E +3E 4F C7 3F 64 C5 08 45 43 48 4F 00 B2 40 C2 48 +08 C5 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 08 C5 30 4D 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE C5 29 4F 8F 4E 00 00 7E 49 DE 3F B0 C5 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2E C5 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A C2 00 00 CE C6 C0 C5 +12 C8 CC CA B0 C2 3C C6 14 C2 06 5B 54 48 45 4E +5D 00 C4 C5 1A C6 E0 C5 FE C5 14 C2 06 5B 45 4C +53 45 5D 00 C4 C5 2C C6 E0 C5 FC C5 1E C2 04 5B +49 46 5D 00 C4 C5 FE C5 B2 C2 FC C5 1E C2 05 0D +6B 6F 20 0A 9E C5 9A C2 84 C2 B2 C2 FE C5 EC C5 +0D 5B 54 48 45 4E 5D 00 30 4D 50 C6 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C C6 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 C5 12 C8 7A C8 +1E CA 8E C7 6C C6 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 C5 12 C8 7A C8 9E C6 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D A4 C4 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 C3 05 53 22 00 82 43 C0 1D +0D 12 84 12 0A C2 1E C2 7C CA 0A C2 22 00 12 C8 +12 C7 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D +3E 4F 3D 41 30 4D 86 C5 05 2E 22 00 0D 12 84 12 +FC C6 0A C2 9E C5 7C CA 8E C7 00 00 04 3C 23 00 +B2 40 B2 1D B2 1D 30 4D F8 C6 02 23 1B 42 BE 1D +2C 4F 2F 83 B0 12 46 C2 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 +B2 1D C8 4A 00 00 30 4D 4A C7 04 23 53 00 0D 12 +84 12 4C C7 86 C7 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A C7 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 +B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 C7 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 76 C5 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 C7 C0 C5 +AE C7 7E C7 AA C6 BC C7 98 C7 9E C5 8E C7 28 C7 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 C8 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 84 C9 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 C9 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E C2 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C C7 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 +84 12 84 C2 C0 C5 12 C8 B0 C2 56 CB 7A C8 40 CA +0A 4E 3E 4F 3D 40 5A CA 6D 27 3D 40 34 CA 1A E2 +BC 1D 14 24 0E 12 3E 4F 30 41 5C CA 3E 4F 3D 40 +34 CA 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 CC 2A 3C 24 CA 02 2C A2 53 C8 1D +1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 7A CA 0F 4C +49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 +C8 1D A2 52 C8 1D BA 40 0A C2 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 C7 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC C6 0A 41 4C 4C +4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 +84 12 1E C2 02 0D 0A 00 9E C5 94 C2 2E CA BC C6 +E6 C6 1E C2 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 C3 32 C2 0A C2 40 FF EE C6 1E C2 09 46 52 41 +4D 20 66 75 6C 6C 08 C3 B2 C2 F2 CA DC CA 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC C6 0A C2 08 C3 +7C CA 8E C7 0C C8 02 27 0D 12 84 12 C0 C5 12 C8 +7A C8 B0 C2 58 CB 20 C7 64 CA 86 C6 07 5B 27 5D +0D 12 84 12 48 CB 0A C2 0A C2 7C CA 7C CA 8E C7 +5C CB 03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 +BC 1D 30 4D D4 C6 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 C5 12 C8 7A C8 B0 C2 58 CB E6 C6 +AC C2 B0 CB 0A C2 0A C2 7C CA 7C CA 0A C2 7C CA +7C CA 8E C7 00 00 02 3A 30 12 06 CC 92 B3 C8 1D +A2 63 C8 1D 0D 12 84 12 C0 C5 12 C8 CE CB 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 +82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 +1E C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 C3 72 CB 03 3B 82 93 BC 1D F4 26 0D 12 +84 12 0A C2 8E C7 7C CA 18 CC 74 CB 8E C7 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 +00 00 30 4D C6 CA 0C 43 52 45 41 54 45 00 B0 12 +BC CB BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 C5 +0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 CB 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 CC 2F 83 8F 4E 00 00 1A 42 C8 1D +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 CC +05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 48 CB +D2 CC 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 CB +0A C2 D4 CC 7C CA 8E C7 66 CC 08 43 4F 44 45 00 +B0 12 BC CB A2 82 C8 1D 61 3C A8 C7 0E 48 44 4E +43 4F 44 45 B2 40 C0 CD CC 1D F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 CC 1E CD 3D 41 +92 42 D0 1D CC 1D 5D 3C EA CC 0E 43 4F 44 45 4E +4E 4D 30 12 F4 CC B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F FC CC 0B 48 +49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF +82 43 BC 1D B9 3F 88 CD B2 40 9A CD D0 1D 82 4E +CE 1D 30 40 20 C7 85 12 86 CD 86 CB 2E CB 18 CE +2A CD 80 CC CA C7 74 C8 46 CB 6E CD C0 CC 9A CC +36 CC 8E CA A2 CE CC C8 00 00 00 00 85 12 86 CD +1C D5 A0 D3 00 D5 C8 D2 24 D3 72 D3 4E D4 5A D4 +EA D1 0E D3 00 00 00 00 5C CD DA D0 00 00 76 D4 +BA CD B2 40 9A CD CE 1D 82 43 D0 1D 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 +B0 12 EE CD 30 4D 00 CE 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 1D B0 12 EE CD 1A 42 +CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 06 C4 FE FF 29 83 B9 40 F2 C3 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 CD 82 43 4A 18 +C7 3F 94 CE B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C CB 0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 +84 12 C0 C5 12 C8 7A C8 AC C2 C0 CE B4 C6 54 CA +C2 CE 3E 4F 3D 41 B2 41 C6 1D B0 12 BC CB BA 40 +85 12 FC FF BA 40 92 CE FE FF 28 83 8A 48 00 00 +BA 40 82 C2 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 +B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D +84 12 12 C8 7A C8 AC C2 2C CF 0C CF 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 CE +00 00 01 20 3E 52 2E 83 21 53 30 41 24 C9 AC C2 +34 CF 28 CF 36 CF B2 41 C6 1D 30 41 92 83 C6 1D +3E 40 28 00 0A 4E 3D 15 B0 12 FC CE 15 20 3E 40 +2B 00 B0 12 FC CE 06 20 3E 40 2D 00 B0 12 FC CE +92 83 C6 1D 0E 12 1E 41 02 00 84 12 12 C8 24 C9 +AC C2 58 CB 76 CF 3E 51 3A 17 30 41 B0 12 3C CF +19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 +92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 12 C8 24 C9 +AC C2 AE CF A6 CF 3E 90 10 00 E6 2B 7C 2D B0 CF +A2 41 C6 1D E1 3F 03 20 B0 12 94 CF 43 3C 7A 90 +23 00 24 20 B0 12 44 CF 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D +A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 CF F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 CF 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 CF 92 92 C2 1D C6 1D 02 24 +92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C CF F2 3F 03 20 B0 12 94 CF F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C CF +EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 +19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF +19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A C2 00 13 7C CA +8E C7 0A C2 2C 00 72 D0 B6 CF C0 C5 7C D0 54 D0 +C2 D0 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 D0 00 40 CE D0 0A 4D 4F 56 2E 42 +85 12 B2 D0 40 40 00 00 06 41 44 44 85 12 B2 D0 +00 50 E8 D0 0A 41 44 44 2E 42 85 12 B2 D0 40 50 +F4 D0 08 41 44 44 43 00 85 12 B2 D0 00 60 02 D1 +0C 41 44 44 43 2E 42 00 85 12 B2 D0 40 60 3A CD +08 53 55 42 43 00 85 12 B2 D0 00 70 20 D1 0C 53 +55 42 43 2E 42 00 85 12 B2 D0 40 70 2E D1 06 53 +55 42 85 12 B2 D0 00 80 3E D1 0A 53 55 42 2E 42 +85 12 B2 D0 40 80 4A D1 06 43 4D 50 85 12 B2 D0 +00 90 58 D1 0A 43 4D 50 2E 42 85 12 B2 D0 40 90 +00 00 08 44 41 44 44 00 85 12 B2 D0 00 A0 72 D1 +0C 44 41 44 44 2E 42 00 85 12 B2 D0 40 A0 A0 D0 +06 42 49 54 85 12 B2 D0 00 B0 90 D1 0A 42 49 54 +2E 42 85 12 B2 D0 40 B0 9C D1 06 42 49 43 85 12 +B2 D0 00 C0 AA D1 0A 42 49 43 2E 42 85 12 B2 D0 +40 C0 B6 D1 06 42 49 53 85 12 B2 D0 00 D0 C4 D1 +0A 42 49 53 2E 42 85 12 B2 D0 40 D0 00 00 06 58 +4F 52 85 12 B2 D0 00 E0 DE D1 0A 58 4F 52 2E 42 +85 12 B2 D0 40 E0 10 D1 06 41 4E 44 85 12 B2 D0 +00 F0 F8 D1 0A 41 4E 44 2E 42 85 12 B2 D0 40 F0 +C0 C5 72 D0 B6 CF 18 D2 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 D1 06 52 52 43 85 12 +10 D2 00 10 2A D2 0A 52 52 43 2E 42 85 12 10 D2 +40 10 64 D1 08 53 57 50 42 00 85 12 10 D2 80 10 +36 D2 06 52 52 41 85 12 10 D2 00 11 52 D2 0A 52 +52 41 2E 42 85 12 10 D2 40 11 44 D2 06 53 58 54 +85 12 10 D2 80 11 00 00 08 50 55 53 48 00 85 12 +10 D2 00 12 78 D2 0C 50 55 53 48 2E 42 00 85 12 +10 D2 40 12 6C D2 08 43 41 4C 4C 00 85 12 10 D2 +80 12 1A 53 0E 4A 84 12 02 C8 1E C2 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 C3 96 D2 06 53 +3E 3D 86 12 00 38 BE D2 04 53 3C 00 86 12 00 34 +86 D2 06 30 3E 3D 86 12 00 30 D2 D2 04 30 3C 00 +86 12 00 30 0E CD 04 55 3C 00 86 12 00 2C E6 D2 +06 55 3E 3D 86 12 00 28 DC D2 06 30 3C 3E 86 12 +00 24 FA D2 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A +30 4D 80 D1 08 54 48 45 4E 00 1A 42 C8 1D 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 D2 08 45 4C 53 45 00 1A 42 +C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A +00 00 E3 3F 5E D2 0A 42 45 47 49 4E 30 40 32 C2 +48 D3 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D 04 D2 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 D3 A8 C6 8E C7 +66 D3 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 D3 +2A D3 8E C7 D6 D3 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 1D CB 2F 98 42 C8 1D 00 00 30 4D C2 D3 06 42 +57 31 85 12 D4 D3 00 00 EE D3 06 42 57 32 85 12 +D4 D3 00 00 FA D3 06 42 57 33 85 12 D4 D3 00 00 +12 D4 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 +C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 D4 00 00 +36 D4 06 46 57 32 85 12 10 D4 00 00 42 D4 06 46 +57 33 85 12 10 D4 00 00 B0 D3 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 CB +54 CA 8E C7 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F 7C D0 0A C2 2C 00 12 C8 24 C9 AC C2 58 CB +C0 C5 72 D0 54 D0 A8 D4 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 D4 08 52 52 43 4D 00 85 12 92 D4 +50 00 D6 D4 08 52 52 41 4D 00 85 12 92 D4 50 01 +E4 D4 08 52 4C 41 4D 00 85 12 92 D4 50 02 F2 D4 +08 52 52 55 4D 00 85 12 92 D4 50 03 04 D3 0A 50 +55 53 48 4D 85 12 92 D4 00 15 0E D5 08 50 4F 50 +4D 00 85 12 92 D4 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 +CA C4 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 F2 C3 06 C4 +q diff --git a/binaries/MSP_EXP430FR5739_8MHz_I2C.txt b/binaries/MSP_EXP430FR5739_8MHz_I2C.txt index 1504ea3..e7d2275 100644 --- a/binaries/MSP_EXP430FR5739_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5739_8MHz_I2C.txt @@ -1,335 +1,323 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF EA D5 F0 CD 34 01 -10 00 41 87 B6 C3 AA C2 B8 C3 8C C3 82 C4 EA D5 -F0 CD 70 C4 80 C5 FE C4 DA C4 3C 1D 4E C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +C4 C4 56 C3 56 C3 58 C3 44 C3 04 D5 BC CD 76 CD +76 CD B2 C4 36 C5 0E C5 3C 1D E0 1C 6A C7 B6 C2 +C4 C2 86 C6 20 00 0A 00 00 1C 56 C3 56 C3 58 C3 +44 C3 04 D5 BC CD 76 CD 76 CD 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @C200 -B0 12 B8 C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 6E C4 B2 49 7E C5 B2 49 FC C4 B2 49 D8 C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA C3 0E 12 B0 12 -F8 C2 0A C2 DE 1D CE C5 16 C5 EE C2 34 C2 8A C3 -14 C2 05 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 -C4 C6 96 C5 34 C2 7E C3 14 C2 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A C5 8E C6 4A C5 -14 C2 04 1B 5B 30 6D 00 4A C5 16 CA 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE C3 04 57 41 52 4D 00 B0 12 -8C C3 78 40 03 00 B0 12 BA C3 84 12 14 C2 07 0D -0A 1B 5B 37 6D 40 4A C5 0A C2 02 18 CE C5 C4 C6 -0A C2 23 00 FA C4 C4 C6 14 C2 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A C5 0A C2 40 FF 28 C2 C2 C5 8E C6 -14 C2 0A 62 79 74 65 73 20 66 72 65 65 00 3A C2 -7E C3 00 00 06 41 43 43 45 50 54 00 30 40 70 C4 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 C3 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA C4 2F 83 8F 4E 00 00 -58 43 B0 12 BA C3 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE C4 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 C4 -04 45 43 48 4F 00 B2 40 C2 48 08 C5 82 43 DE 1D -38 40 05 00 B0 12 BA C3 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 C5 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 C5 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC C4 68 C5 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC C3 02 43 52 00 30 40 80 C5 -0D 12 84 12 14 C2 02 0D 0A 00 4A C5 4E C6 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 C4 01 40 2E 4E -30 4D CC C5 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 C5 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 C6 02 23 53 00 0D 12 84 12 -0A C6 44 C6 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 C6 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 C5 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE C5 -3C C6 EE C2 7C C6 58 C6 4A C5 02 CA FA C4 4E C6 -2C C5 01 2E 0E 93 E3 37 38 43 E2 3F 76 C6 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 48 C9 -0A C2 22 00 1A C7 E8 C6 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 C6 -82 2E 22 00 0D 12 84 12 D2 C6 0A C2 4A C5 48 C9 -4E C6 F8 C3 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C C8 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E C8 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 C9 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F 32 B0 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 C2 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 01 3D 0E 93 3E 4F +83 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 B0 C4 B2 49 +34 C5 B2 49 0C C5 B2 49 A0 C2 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 30 CE 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 C3 B0 12 D0 C2 90 C6 AC C2 +42 C3 4E C5 1E C2 05 1B 5B 37 6D 40 7A C5 0A C2 +02 18 B2 C6 DE C7 7A C5 1E C2 04 1B 5B 30 6D 00 +7A C5 C6 CA 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 4E C5 1E C2 07 0D 0A 1B 5B 37 +6D 40 7A C5 0A C2 02 18 B2 C6 DE C7 0A C2 23 00 +32 C5 DE C7 1E C2 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +7A C5 0A C2 40 FF 32 C2 A6 C6 AA C7 1E C2 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 C2 36 C3 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 C3 01 12 6D 3F 82 4E 08 18 92 12 3A 18 D2 B3 +21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C 92 D3 30 01 B2 43 06 02 +B2 40 EF 7F 02 02 B2 43 26 02 B2 D0 08 FF 22 02 +F2 D3 26 03 F2 40 F0 00 22 03 F2 40 A5 00 61 01 +82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 +40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 +B0 01 92 C3 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 +A1 04 39 40 00 04 29 83 89 43 00 1C FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 9E 01 B0 12 +D0 C2 80 C3 00 00 0C 41 43 43 45 50 54 00 30 40 +B2 C4 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 9E 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 +97 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B +0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 0E C5 58 43 +B0 12 46 C3 2F 83 8F 4E 00 00 92 B3 6C 06 FD 27 +1E 42 4C 06 B0 12 44 C3 30 4D 00 00 08 45 4D 49 +54 00 30 40 36 C5 08 4E 3E 4F A2 B3 6C 06 FD 27 +C2 48 4E 06 30 4D 2C C5 08 45 43 48 4F 00 B2 40 +C2 48 40 C5 38 40 05 00 B0 12 46 C3 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 40 C5 28 42 +F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 8A C5 +29 4F 8F 4E 00 00 7E 49 D4 3F 8C C5 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 83 22 F9 98 00 00 +80 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 77 22 9B 24 06 C5 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A C2 00 00 AA C6 9C C5 EE C7 A8 CA +B0 C2 18 C6 14 C2 06 5B 54 48 45 4E 5D 00 A0 C5 +F6 C5 BC C5 DA C5 14 C2 06 5B 45 4C 53 45 5D 00 +A0 C5 08 C6 BC C5 D8 C5 1E C2 04 5B 49 46 5D 00 +A0 C5 DA C5 B2 C2 D8 C5 1E C2 05 0D 6B 6F 20 0A +7A C5 9A C2 84 C2 B2 C2 DA C5 C8 C5 0D 5B 54 48 +45 4E 5D 00 30 4D 2C C6 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 38 C6 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 9C C5 EE C7 56 C8 FA C9 6A C7 +48 C6 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 9C C5 EE C7 56 C8 7A C6 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D A6 C4 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 C3 05 53 22 00 82 43 C0 1D 0D 12 84 12 +0A C2 1E C2 58 CA 0A C2 22 00 EE C7 EE C6 B2 40 +20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 +30 4D 60 C5 05 2E 22 00 0D 12 84 12 D8 C6 0A C2 +7A C5 58 CA 6A C7 00 00 04 3C 23 00 B2 40 B2 1D +B2 1D 30 4D D4 C6 02 23 1B 42 BE 1D 2C 4F 2F 83 +B0 12 46 C2 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A +00 00 30 4D 26 C7 04 23 53 00 0D 12 84 12 28 C7 +62 C7 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 56 C7 +04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +70 C7 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 48 C5 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 1C C7 9C C5 8A C7 5A C7 +86 C6 98 C7 74 C7 7A C5 6A C7 04 C7 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 +C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D DC C7 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 1D 0C 4E 0E 43 1E 15 3D 40 60 C9 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +62 C9 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E C2 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 18 C7 +03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 C2 +9C C5 EE C7 B0 C2 32 CB 56 C8 1C CA 0A 4E 3E 4F +3D 40 36 CA 6D 27 3D 40 10 CA 1A E2 BC 1D 14 24 +0E 12 3E 4F 30 41 38 CA 3E 4F 3D 40 10 CA 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +0E CC 2A 3C 00 CA 02 2C A2 53 C8 1D 1A 42 C8 1D +8A 4E FE FF 3E 4F 30 4D 56 CA 0F 4C 49 54 45 52 +41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 +C8 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 C6 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC C2 02 CA 1A C7 BE C9 9C 26 -3D 40 C6 C9 DE 3E C8 C9 0A 4E 3E 4F 3D 40 E2 C9 -36 27 3D 40 B8 C9 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 C9 3E 4F 3D 40 B8 C9 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 CB CC 3F -EC C9 86 12 20 00 D4 C5 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C C5 BC C2 -B2 C9 B2 C5 E4 C5 14 C2 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 EC C5 -14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A C3 -3A C2 2C CA 08 CA 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 C6 0A C2 2A C3 48 C9 4E C6 7C C7 01 27 -0D 12 84 12 02 CA 1A C7 82 C7 34 C2 00 CA 4E C6 -00 00 83 5B 27 5D 0D 12 84 12 80 CA 0A C2 0A C2 -48 C9 48 C9 4E C6 92 CA 81 5B 82 43 BE 1D 30 4D -FA C5 01 5D B2 43 BE 1D 30 4D B2 CA 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 CA 1A C7 82 C7 96 C5 34 C2 -00 CA E4 C5 34 C2 F4 CA 0A C2 0A C2 48 C9 48 C9 -0A C2 48 C9 48 C9 4E C6 A8 CA 01 3A 30 12 44 CB -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 CA 1A C7 -12 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 C3 FA CA 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A C2 4E C6 48 C9 56 CB AA CA 4E C6 -A8 C9 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 C9 06 43 52 45 41 54 -45 00 B0 12 00 CB BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA CB 04 43 4F 44 45 00 B0 12 00 CB A2 82 -C6 1D 0D 12 84 12 F2 CD CC CD 4E C6 A2 CB 07 48 -44 4E 43 4F 44 45 B2 40 D0 CD DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 CB 0C CE -2A CE 4E C6 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C CE 2A CE 4E C6 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE CB 85 48 49 32 4C 4F 0D 12 84 12 28 C2 9A CD -48 C9 AA CA E2 CB 4E C6 88 CB 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A CC 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A C2 00 00 C6 C5 02 CA 1A C7 98 C9 -8E C5 34 C2 02 CD 9C C5 14 C2 06 5B 54 48 45 4E -5D 00 74 CC DC CC 98 CC BA CC 4E C6 9C C5 14 C2 -06 5B 45 4C 53 45 5D 00 74 CC F2 CC 98 CC B8 CC -4E C6 14 C2 04 5B 49 46 5D 00 74 CC BA CC 3A C2 -B8 CC 70 C5 14 C2 05 0D 0A 6B 6F 20 4A C5 BC C2 -AC C2 3A C2 BA CC A8 CC 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 CD 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 CA 1A C7 82 C7 -26 CD 4E C6 2C CD 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 CD DE C5 4E C6 5E CD B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A C9 06 4D -41 52 4B 45 52 00 B0 12 00 CB BA 40 85 12 FC FF -BA 40 5C CD FE FF 28 83 8A 48 00 00 BA 40 AA C2 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A C2 -CA 1D D6 C5 4E C6 85 12 9E CD 66 CA D4 CB 10 C5 -7E CA 52 CC D2 C4 6E CD 00 C7 96 CE AA CE 8A C6 -14 C7 00 00 46 CD BC CA E2 C7 00 00 85 12 9E CD -60 D4 C6 D4 08 D4 16 D5 CE D3 00 00 9A D1 00 00 -DE D5 C2 D5 32 D4 70 D4 AA D2 00 00 00 00 32 D5 -CA CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 CD 24 CE 2A CE 3A CE 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 CA -09 50 57 52 5F 53 54 41 54 45 85 12 32 CE EA D5 -CE C6 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E CE F3 3F 70 CE 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E CE 30 4D 82 CE 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 CF FE FF 29 83 B9 40 -E2 C3 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 C3 B2 49 FA C2 B2 49 02 C2 B2 49 00 C4 B2 49 -EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 92 D3 -30 01 B2 43 06 02 B2 40 EF 7F 02 02 B2 43 26 02 -B2 D0 08 FF 22 02 F2 D3 26 03 F2 40 F0 00 22 03 -F2 40 A5 00 61 01 82 43 66 01 B2 40 33 00 64 01 -D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 -19 83 FA 23 B2 D2 B0 01 92 C3 B0 01 F2 D0 10 00 -2A 03 F2 C0 40 00 A1 04 1E 42 08 18 82 43 08 18 -1E D2 9E 01 B0 12 F8 C2 FE C3 38 40 C0 1D 0A 4E -39 48 2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E -FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 -0E 12 12 12 C4 1D 84 12 1A C7 82 C7 DE C5 34 C2 -DA CF 3E C8 34 C2 F4 CF EE CF DC CF 3C 4E 3C 80 -87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 -1B 17 30 41 F6 CF B2 41 C4 1D 3E 41 84 12 0A C2 -2B 00 1A C7 82 C7 DE C5 34 C2 12 D0 3E C8 34 C2 -00 CA A8 C5 1A C7 3E C8 34 C2 00 CA 1E D0 3E 5F -E7 3F 3E 40 28 00 B0 12 BE CF 19 42 C6 1D A2 53 -C6 1D 89 4E 00 00 3E 40 29 00 92 92 C0 1D C4 1D -02 20 30 40 6E CB 1C 15 12 12 C4 1D 92 53 C4 1D -84 12 1A C7 3E C8 34 C2 66 D0 5C D0 21 53 3E 90 -10 00 C6 2B 7F 2D 68 D0 B2 41 C4 1D C1 3F 0D 12 -84 12 02 CA 9A CF 78 D0 0C 43 1B 42 C6 1D A2 53 -C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 1D -B0 12 BE CF 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +92 C7 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D B8 C6 0A 41 4C 4C 4F 54 82 5E +C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E C2 +02 0D 0A 00 7A C5 94 C2 0A CA 98 C6 C2 C6 1E C2 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 C3 32 C2 +0A C2 40 FF CA C6 1E C2 09 46 52 41 4D 20 66 75 +6C 6C 08 C3 B2 C2 CE CA B8 CA 0D 41 42 4F 52 54 +22 00 0D 12 84 12 D8 C6 0A C2 08 C3 58 CA 6A C7 +E8 C7 02 27 0D 12 84 12 9C C5 EE C7 56 C8 B0 C2 +34 CB FC C6 40 CA 62 C6 07 5B 27 5D 0D 12 84 12 +24 CB 0A C2 0A C2 58 CA 58 CA 6A C7 38 CB 03 5B +82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D +B0 C6 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +9C C5 EE C7 56 C8 B0 C2 34 CB C2 C6 AC C2 8C CB +0A C2 0A C2 58 CA 58 CA 0A C2 58 CA 58 CA 6A C7 +00 00 02 3A 30 12 E2 CB 92 B3 C8 1D A2 63 C8 1D +0D 12 84 12 9C C5 EE C7 AA CB 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 +B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E C2 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 C3 +4E CB 03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A C2 +6A C7 58 CA F4 CB 50 CB 6A C7 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D +A2 CA 0C 43 52 45 41 54 45 00 B0 12 98 CB BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 74 C5 0A 44 4F 45 +53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 92 CB 0E 3A 4E 4F 4E 41 4D 45 30 12 +E2 CB 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 2C CC 05 49 53 00 +0D 12 82 93 BC 1D 08 20 84 12 24 CB AE CC 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 3C CB 0A C2 B0 CC +58 CA 6A C7 42 CC 08 43 4F 44 45 00 B0 12 98 CB +A2 82 C8 1D 61 3C 84 C7 0E 48 44 4E 43 4F 44 45 +B2 40 9C CD CC 1D F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 F4 CB FA CC 3D 41 92 42 D0 1D +CC 1D 5D 3C C6 CC 0E 43 4F 44 45 4E 4E 4D 30 12 +D0 CC B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D +B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 1D 1A 42 C8 1D EF 3F D8 CC 0B 48 49 32 4C 4F +A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D +B9 3F 64 CD B2 40 76 CD D0 1D 82 4E CE 1D 30 40 +FC C6 85 12 62 CD 62 CB 0A CB F4 CD 06 CD 5C CC +A6 C7 50 C8 22 CB 4A CD 9C CC 76 CC 12 CC 6A CA +7E CE A8 C8 00 00 00 00 85 12 62 CD F8 D4 7C D3 +DC D4 A4 D2 00 D3 4E D3 2A D4 36 D4 C6 D1 EA D2 +00 00 00 00 38 CD B6 D0 00 00 52 D4 96 CD B2 40 +76 CD CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 CA CD +30 4D DC CD 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 1D B0 12 CA CD 1A 42 CA 1D 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 0E C4 FE FF 29 83 B9 40 FA C3 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 EE FF 3B 40 10 00 +3A 40 3A 18 B0 12 CE CD 82 43 4A 18 C7 3F 70 CE +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 58 CB 0C 4D +41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 9C C5 +EE C7 56 C8 AC C2 9C CE 90 C6 30 CA 9E CE 3E 4F +3D 41 B2 41 C6 1D B0 12 98 CB BA 40 85 12 FC FF +BA 40 6E CE FE FF 28 83 8A 48 00 00 BA 40 82 C2 +02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 EE C7 +56 C8 AC C2 08 CF E8 CE 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 6E CE 00 00 01 20 +3E 52 2E 83 21 53 30 41 00 C9 AC C2 10 CF 04 CF +12 CF B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 +0A 4E 3D 15 B0 12 D8 CE 15 20 3E 40 2B 00 B0 12 +D8 CE 06 20 3E 40 2D 00 B0 12 D8 CE 92 83 C6 1D +0E 12 1E 41 02 00 84 12 EE C7 00 C9 AC C2 34 CB +52 CF 3E 51 3A 17 30 41 B0 12 18 CF 19 42 C8 1D +89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D +1A 42 C6 1D 3D 15 84 12 EE C7 00 C9 AC C2 8A CF +82 CF 3E 90 10 00 E6 2B 7C 2D 8C CF A2 41 C6 1D +E1 3F 03 20 B0 12 70 CF 43 3C 7A 90 23 00 24 20 +B0 12 20 CF 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 -3C 40 10 02 92 53 C4 1D B0 12 BE CF ED 3F 7A 90 -40 00 16 20 3C 40 20 00 92 53 C4 1D B0 12 46 D0 -0C 20 3C 50 10 00 3E 40 2B 00 B0 12 46 D0 92 92 -C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E DA 3F -B0 12 46 D0 FA 23 3C 50 10 00 B0 12 22 D0 EF 3F -0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 02 CA -9A CF 44 D1 FE 90 26 00 00 00 3E 40 20 00 03 20 -3C 50 82 00 C7 3F B0 12 46 D0 E0 23 3C 50 80 00 -B0 12 22 D0 DB 3F 00 00 04 52 45 54 49 00 0D 12 -84 12 0A C2 00 13 48 C9 4E C6 0A C2 2C 00 6E D0 -3A D1 84 D1 09 4B 2E 4E 0E DC A2 3F 40 CC 03 4D -4F 56 85 12 7A D1 00 40 8E D1 05 4D 4F 56 2E 42 -85 12 7A D1 40 40 00 00 03 41 44 44 85 12 7A D1 -00 50 A8 D1 05 41 44 44 2E 42 85 12 7A D1 40 50 -B4 D1 04 41 44 44 43 00 85 12 7A D1 00 60 C2 D1 -06 41 44 44 43 2E 42 00 85 12 7A D1 40 60 68 D1 -04 53 55 42 43 00 85 12 7A D1 00 70 E0 D1 06 53 -55 42 43 2E 42 00 85 12 7A D1 40 70 EE D1 03 53 -55 42 85 12 7A D1 00 80 FE D1 05 53 55 42 2E 42 -85 12 7A D1 40 80 16 CC 03 43 4D 50 85 12 7A D1 -00 90 18 D2 05 43 4D 50 2E 42 85 12 7A D1 40 90 -00 CC 04 44 41 44 44 00 85 12 7A D1 00 A0 32 D2 -06 44 41 44 44 2E 42 00 85 12 7A D1 40 A0 24 D2 -03 42 49 54 85 12 7A D1 00 B0 50 D2 05 42 49 54 -2E 42 85 12 7A D1 40 B0 5C D2 03 42 49 43 85 12 -7A D1 00 C0 6A D2 05 42 49 43 2E 42 85 12 7A D1 -40 C0 76 D2 03 42 49 53 85 12 7A D1 00 D0 84 D2 -05 42 49 53 2E 42 85 12 7A D1 40 D0 00 00 03 58 -4F 52 85 12 7A D1 00 E0 9E D2 05 58 4F 52 2E 42 -85 12 7A D1 40 E0 D0 D1 03 41 4E 44 85 12 7A D1 -00 F0 B8 D2 05 41 4E 44 2E 42 85 12 7A D1 40 F0 -02 CA 6E D0 D6 D2 0A 4C 3C F0 70 00 8A 10 3A F0 -0F 00 0C DA 4F 3F 0A D2 03 52 52 43 85 12 D0 D2 -00 10 E8 D2 05 52 52 43 2E 42 85 12 D0 D2 40 10 -F4 D2 04 53 57 50 42 00 85 12 D0 D2 80 10 02 D3 -03 52 52 41 85 12 D0 D2 00 11 10 D3 05 52 52 41 -2E 42 85 12 D0 D2 40 11 1C D3 03 53 58 54 85 12 -D0 D2 80 11 00 00 04 50 55 53 48 00 85 12 D0 D2 -00 12 36 D3 06 50 55 53 48 2E 42 00 85 12 D0 D2 -40 12 90 D2 04 43 41 4C 4C 00 85 12 D0 D2 80 12 -1A 53 0E 4A 0D 12 84 12 C4 C6 14 C2 0D 6F 75 74 -20 6F 66 20 62 6F 75 6E 64 73 36 C3 2A D3 03 53 -3E 3D 86 12 00 38 7E D3 02 53 3C 00 86 12 00 34 -44 D3 03 30 3E 3D 86 12 00 30 92 D3 02 30 3C 00 -86 12 00 30 00 00 02 55 3C 00 86 12 00 2C A6 D3 -03 55 3E 3D 86 12 00 28 9C D3 03 30 3C 3E 86 12 -00 24 BA D3 02 30 3D 00 86 12 00 20 00 00 02 49 -46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A -30 4D B0 D3 04 54 48 45 4E 00 1A 42 C6 1D 08 4E -3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F -88 DA 00 00 30 4D 40 D2 04 45 4C 53 45 00 1A 42 -C6 1D BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A -00 00 E3 3F 54 D3 05 42 45 47 49 4E 30 40 28 C2 -E4 D3 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 -C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 -FF 03 08 DA 89 48 00 00 A2 53 C6 1D 30 4D C4 D2 -05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 -05 57 48 49 4C 45 0D 12 84 12 D2 D3 A8 C5 4E C6 -88 D3 06 52 45 50 45 41 54 00 0D 12 84 12 66 D4 -EA D3 4E C6 96 D4 3D 41 08 4E 3E 4F 2A 48 B2 92 -C4 1D CB 2F 98 42 C6 1D 00 00 30 4D 26 D4 03 42 -57 31 85 12 94 D4 00 00 AE D4 03 42 57 32 85 12 -94 D4 00 00 BA D4 03 42 57 33 85 12 94 D4 00 00 -D2 D4 3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B -BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D -00 00 03 46 57 31 85 12 D0 D4 00 00 F2 D4 03 46 -57 32 85 12 D0 D4 00 00 FE D4 03 46 57 33 85 12 -D0 D4 00 00 0A D5 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C 0D 12 84 12 80 CA DC C9 4E C6 -00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 -00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 02 CA -9A CF 54 D5 92 53 C4 1D 3E 40 2C 00 84 12 1A C7 -3E C8 34 C2 00 CA 30 D1 6A D5 0A 4E 3E 4F 1A 83 -F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A -08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E -8A 10 5A 06 A6 3E 82 D4 04 52 52 43 4D 00 85 12 -4E D5 50 00 98 D5 04 52 52 41 4D 00 85 12 4E D5 -50 01 A6 D5 04 52 4C 41 4D 00 85 12 4E D5 50 02 -B4 D5 04 52 52 55 4D 00 85 12 4E D5 50 03 C4 D3 -05 50 55 53 48 4D 85 12 4E D5 00 15 D0 D5 04 50 -4F 50 4D 00 85 12 4E D5 00 17 +3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 20 CF F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 6C CF 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 70 CF 92 92 C2 1D C6 1D 02 24 92 53 C6 1D +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 58 CF F2 3F +03 20 B0 12 70 CF F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 58 CF EA 3F 0C 43 +1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D +19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D +82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A C2 00 13 58 CA 6A C7 0A C2 +2C 00 4E D0 92 CF 9C C5 58 D0 30 D0 9E D0 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +8E D0 00 40 AA D0 0A 4D 4F 56 2E 42 85 12 8E D0 +40 40 00 00 06 41 44 44 85 12 8E D0 00 50 C4 D0 +0A 41 44 44 2E 42 85 12 8E D0 40 50 D0 D0 08 41 +44 44 43 00 85 12 8E D0 00 60 DE D0 0C 41 44 44 +43 2E 42 00 85 12 8E D0 40 60 16 CD 08 53 55 42 +43 00 85 12 8E D0 00 70 FC D0 0C 53 55 42 43 2E +42 00 85 12 8E D0 40 70 0A D1 06 53 55 42 85 12 +8E D0 00 80 1A D1 0A 53 55 42 2E 42 85 12 8E D0 +40 80 26 D1 06 43 4D 50 85 12 8E D0 00 90 34 D1 +0A 43 4D 50 2E 42 85 12 8E D0 40 90 00 00 08 44 +41 44 44 00 85 12 8E D0 00 A0 4E D1 0C 44 41 44 +44 2E 42 00 85 12 8E D0 40 A0 7C D0 06 42 49 54 +85 12 8E D0 00 B0 6C D1 0A 42 49 54 2E 42 85 12 +8E D0 40 B0 78 D1 06 42 49 43 85 12 8E D0 00 C0 +86 D1 0A 42 49 43 2E 42 85 12 8E D0 40 C0 92 D1 +06 42 49 53 85 12 8E D0 00 D0 A0 D1 0A 42 49 53 +2E 42 85 12 8E D0 40 D0 00 00 06 58 4F 52 85 12 +8E D0 00 E0 BA D1 0A 58 4F 52 2E 42 85 12 8E D0 +40 E0 EC D0 06 41 4E 44 85 12 8E D0 00 F0 D4 D1 +0A 41 4E 44 2E 42 85 12 8E D0 40 F0 9C C5 4E D0 +92 CF F4 D1 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F AC D1 06 52 52 43 85 12 EC D1 00 10 +06 D2 0A 52 52 43 2E 42 85 12 EC D1 40 10 40 D1 +08 53 57 50 42 00 85 12 EC D1 80 10 12 D2 06 52 +52 41 85 12 EC D1 00 11 2E D2 0A 52 52 41 2E 42 +85 12 EC D1 40 11 20 D2 06 53 58 54 85 12 EC D1 +80 11 00 00 08 50 55 53 48 00 85 12 EC D1 00 12 +54 D2 0C 50 55 53 48 2E 42 00 85 12 EC D1 40 12 +48 D2 08 43 41 4C 4C 00 85 12 EC D1 80 12 1A 53 +0E 4A 84 12 DE C7 1E C2 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 C3 72 D2 06 53 3E 3D 86 12 +00 38 9A D2 04 53 3C 00 86 12 00 34 62 D2 06 30 +3E 3D 86 12 00 30 AE D2 04 30 3C 00 86 12 00 30 +EA CC 04 55 3C 00 86 12 00 2C C2 D2 06 55 3E 3D +86 12 00 28 B8 D2 06 30 3C 3E 86 12 00 24 D6 D2 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D 5C D1 +08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D CC D2 08 45 4C 53 45 00 1A 42 C8 1D BA 40 +00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F +3A D2 0A 42 45 47 49 4E 30 40 32 C2 24 D3 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 1D 30 4D E0 D1 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 EE D2 84 C6 6A C7 42 D3 0C 52 +45 50 45 41 54 00 0D 12 84 12 82 D3 06 D3 6A C7 +B2 D3 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F +98 42 C8 1D 00 00 30 4D 9E D3 06 42 57 31 85 12 +B0 D3 00 00 CA D3 06 42 57 32 85 12 B0 D3 00 00 +D6 D3 06 42 57 33 85 12 B0 D3 00 00 EE D3 3D 41 +1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B +BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 EC D3 00 00 12 D4 06 46 +57 32 85 12 EC D3 00 00 1E D4 06 46 57 33 85 12 +EC D3 00 00 8C D3 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 24 CB 30 CA 6A C7 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 58 D0 +0A C2 2C 00 EE C7 00 C9 AC C2 34 CB 9C C5 4E D0 +30 D0 84 D4 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +E2 D3 08 52 52 43 4D 00 85 12 6E D4 50 00 B2 D4 +08 52 52 41 4D 00 85 12 6E D4 50 01 C0 D4 08 52 +4C 41 4D 00 85 12 6E D4 50 02 CE D4 08 52 52 55 +4D 00 85 12 6E D4 50 03 E0 D2 0A 50 55 53 48 4D +85 12 6E D4 00 15 EA D4 08 50 4F 50 4D 00 85 12 +6E D4 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 82 C4 -E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 E2 C3 08 CF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 C4 C4 +FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 FA C3 0E C4 q diff --git a/binaries/MSP_EXP430FR5739_8MHz_UART.txt b/binaries/MSP_EXP430FR5739_8MHz_UART.txt deleted file mode 100644 index d16a623..0000000 --- a/binaries/MSP_EXP430FR5739_8MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF 00 D6 02 CE 34 01 -10 00 41 B3 94 C3 AA C2 DA C3 9C C3 94 C4 00 D6 -02 CE 7A C4 92 C5 24 C5 FE C4 3C 1D 60 C6 D4 C2 -E2 C2 EE C2 20 00 0A 00 00 00 00 00 00 00 00 00 -@C200 -B0 12 DA C3 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 C2 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA C2 39 40 22 18 -B2 49 78 C4 B2 49 90 C5 B2 49 22 C5 B2 49 FC C4 -B2 49 CA C2 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE CE 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA C3 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 C2 0A C2 DE 1D E0 C5 32 C5 -14 C2 04 1B 5B 37 6D 00 5C C5 A8 C5 34 C2 86 C3 -14 C2 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C C5 A0 C6 5C C5 14 C2 04 1B 5B 30 6D 00 -5C C5 28 CA 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 03 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 03 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 C3 D2 B3 21 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE C3 04 57 41 52 4D 00 B0 12 -9C C3 84 12 14 C2 07 0D 0A 1B 5B 37 6D 23 5C C5 -D6 C6 14 C2 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C C5 -0A C2 40 FF 28 C2 D4 C5 A0 C6 14 C2 0A 62 79 74 -65 73 20 66 72 65 65 00 3A C2 86 C3 00 00 06 41 -43 43 45 50 54 00 30 40 7A C4 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 C4 3C 40 D2 C4 -5D 15 B6 3E 21 52 3A 17 58 42 CC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 -C2 48 CE 05 30 4D C8 C4 2D 83 92 B3 DC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 DC 05 -FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE C4 2F 83 -8F 4E 00 00 B0 12 DA C3 92 B3 DC 05 FD 27 1E 42 -CC 05 B0 12 C8 C3 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 C5 08 4E 3E 4F C8 3F 1A C5 04 45 43 48 -4F 00 B2 40 C2 48 C0 C4 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 C4 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 C5 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 C5 7A C5 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC C3 02 43 52 00 30 40 -92 C5 0D 12 84 12 14 C2 02 0D 0A 00 5C C5 60 C6 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E C4 01 40 -2E 4E 30 4D DE C5 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A C5 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E C2 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A C6 02 23 53 00 0D 12 -84 12 1C C6 56 C6 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A C6 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 C5 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 C6 4E C6 EE C2 8E C6 6A C6 5C C5 14 CA 20 C5 -60 C6 40 C5 01 2E 0E 93 E3 37 38 43 E2 3F 88 C6 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A C2 14 C2 -5A C9 0A C2 22 00 2C C7 FA C6 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 C6 82 2E 22 00 0D 12 84 12 E4 C6 0A C2 5C C5 -5A C9 60 C6 18 C4 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 C2 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 C2 35 40 D4 C2 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE C8 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 C8 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 C2 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 C9 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A C2 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 C6 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A C6 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC C2 14 CA 2C C7 D0 C9 -9C 26 3D 40 D8 C9 DE 3E DA C9 0A 4E 3E 4F 3D 40 -F4 C9 36 27 3D 40 CA C9 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 C9 3E 4F 3D 40 CA C9 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 CB -CC 3F FE C9 86 12 20 00 E6 C5 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E C5 -BC C2 C4 C9 C4 C5 F6 C5 14 C2 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A C3 0A C2 40 FF 28 C2 -FE C5 14 C2 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A C3 3A C2 3E CA 1A CA 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 C6 0A C2 2A C3 5A C9 60 C6 8E C7 -01 27 0D 12 84 12 14 CA 2C C7 94 C7 34 C2 12 CA -60 C6 00 00 83 5B 27 5D 0D 12 84 12 92 CA 0A C2 -0A C2 5A C9 5A C9 60 C6 A4 CA 81 5B 82 43 BE 1D -30 4D 0C C6 01 5D B2 43 BE 1D 30 4D C4 CA 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 CA 2C C7 94 C7 A8 C5 -34 C2 12 CA F6 C5 34 C2 06 CB 0A C2 0A C2 5A C9 -5A C9 0A C2 5A C9 5A C9 60 C6 BA CA 01 3A 30 12 -56 CB 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 CA -2C C7 24 CB 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 C2 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 C3 0C CB 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A C2 60 C6 5A C9 68 CB BC CA -60 C6 BA C9 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 C9 06 43 52 45 -41 54 45 00 B0 12 12 CB BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC CB 04 43 4F 44 45 00 B0 12 12 CB -A2 82 C6 1D 0D 12 84 12 04 CE DE CD 60 C6 B4 CB -07 48 44 4E 43 4F 44 45 B2 40 E2 CD DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 CB -1E CE 3C CE 60 C6 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E CE 3C CE 60 C6 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 CC 85 48 49 32 4C 4F 0D 12 84 12 28 C2 -AC CD 5A C9 BC CA F4 CB 60 C6 9A CB 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C CC 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A C2 00 00 D8 C5 14 CA 2C C7 -AA C9 A0 C5 34 C2 14 CD AE C5 14 C2 06 5B 54 48 -45 4E 5D 00 86 CC EE CC AA CC CC CC 60 C6 AE C5 -14 C2 06 5B 45 4C 53 45 5D 00 86 CC 04 CD AA CC -CA CC 60 C6 14 C2 04 5B 49 46 5D 00 86 CC CC CC -3A C2 CA CC 82 C5 14 C2 05 0D 0A 6B 6F 20 5C C5 -BC C2 AC C2 3A C2 CC CC BA CC 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A CD 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 CA 2C C7 -94 C7 38 CD 60 C6 3E CD 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 CD F0 C5 60 C6 70 CD -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C C9 -06 4D 41 52 4B 45 52 00 B0 12 12 CB BA 40 85 12 -FC FF BA 40 6E CD FE FF 28 83 8A 48 00 00 BA 40 -AA C2 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A C2 CA 1D E8 C5 60 C6 85 12 B0 CD 78 CA E6 CB -2C C5 90 CA 64 CC F6 C4 80 CD 12 C7 A8 CE BC CE -9C C6 26 C7 00 00 58 CD CE CA F4 C7 00 00 85 12 -B0 CD 76 D4 DC D4 1E D4 2C D5 E4 D3 00 00 B0 D1 -00 00 F4 D5 D8 D5 48 D4 86 D4 C0 D2 00 00 00 00 -48 D5 DC CD 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 CD 36 CE 3C CE 4C CE 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA CA 09 50 57 52 5F 53 54 41 54 45 85 12 44 CE -00 D6 E0 C6 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 CE F3 3F 82 CE 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 CE 30 4D 94 CE 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A CF FE FF 29 83 -B9 40 02 C4 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 C4 B2 49 FA C2 B2 49 02 C2 B2 49 20 C4 -B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 04 29 83 89 43 00 1C FC 23 -92 D3 30 01 B2 43 06 02 B2 40 EF 7F 02 02 E2 D2 -05 02 B2 43 26 02 B2 D0 08 FF 22 02 F2 D3 26 03 -F2 40 F0 00 22 03 F2 40 A5 00 61 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 92 C3 -B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 1E 42 -08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 C2 1E C4 -38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D -09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A -C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 2C C7 -94 C7 F0 C5 34 C2 F0 CF 50 C8 34 C2 0A D0 04 D0 -F2 CF 3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E -01 3C 2E 83 21 52 1B 17 30 41 0C D0 B2 41 C4 1D -3E 41 84 12 0A C2 2B 00 2C C7 94 C7 F0 C5 34 C2 -28 D0 50 C8 34 C2 12 CA BA C5 2C C7 50 C8 34 C2 -12 CA 34 D0 3E 5F E7 3F 3E 40 28 00 B0 12 D4 CF -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 -92 92 C0 1D C4 1D 02 20 30 40 80 CB 1C 15 12 12 -C4 1D 92 53 C4 1D 84 12 2C C7 50 C8 34 C2 7C D0 -72 D0 21 53 3E 90 10 00 C6 2B 7F 2D 7E D0 B2 41 -C4 1D C1 3F 0D 12 84 12 14 CA B0 CF 8E D0 0C 43 -1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 -27 20 92 53 C4 1D B0 12 D4 CF 3C 40 00 03 0E 93 -1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 -14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 -0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D -7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 -D4 CF ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 -C4 1D B0 12 5C D0 0C 20 3C 50 10 00 3E 40 2B 00 -B0 12 5C D0 92 92 C0 1D C4 1D 02 24 92 53 C4 1D -8E 10 0C 5E DA 3F B0 12 5C D0 FA 23 3C 50 10 00 -B0 12 38 D0 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D -0D 12 84 12 14 CA B0 CF 5A D1 FE 90 26 00 00 00 -3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 5C D0 -E0 23 3C 50 80 00 B0 12 38 D0 DB 3F 00 00 04 52 -45 54 49 00 0D 12 84 12 0A C2 00 13 5A C9 60 C6 -0A C2 2C 00 84 D0 50 D1 9A D1 09 4B 2E 4E 0E DC -A2 3F 52 CC 03 4D 4F 56 85 12 90 D1 00 40 A4 D1 -05 4D 4F 56 2E 42 85 12 90 D1 40 40 00 00 03 41 -44 44 85 12 90 D1 00 50 BE D1 05 41 44 44 2E 42 -85 12 90 D1 40 50 CA D1 04 41 44 44 43 00 85 12 -90 D1 00 60 D8 D1 06 41 44 44 43 2E 42 00 85 12 -90 D1 40 60 7E D1 04 53 55 42 43 00 85 12 90 D1 -00 70 F6 D1 06 53 55 42 43 2E 42 00 85 12 90 D1 -40 70 04 D2 03 53 55 42 85 12 90 D1 00 80 14 D2 -05 53 55 42 2E 42 85 12 90 D1 40 80 28 CC 03 43 -4D 50 85 12 90 D1 00 90 2E D2 05 43 4D 50 2E 42 -85 12 90 D1 40 90 12 CC 04 44 41 44 44 00 85 12 -90 D1 00 A0 48 D2 06 44 41 44 44 2E 42 00 85 12 -90 D1 40 A0 3A D2 03 42 49 54 85 12 90 D1 00 B0 -66 D2 05 42 49 54 2E 42 85 12 90 D1 40 B0 72 D2 -03 42 49 43 85 12 90 D1 00 C0 80 D2 05 42 49 43 -2E 42 85 12 90 D1 40 C0 8C D2 03 42 49 53 85 12 -90 D1 00 D0 9A D2 05 42 49 53 2E 42 85 12 90 D1 -40 D0 00 00 03 58 4F 52 85 12 90 D1 00 E0 B4 D2 -05 58 4F 52 2E 42 85 12 90 D1 40 E0 E6 D1 03 41 -4E 44 85 12 90 D1 00 F0 CE D2 05 41 4E 44 2E 42 -85 12 90 D1 40 F0 14 CA 84 D0 EC D2 0A 4C 3C F0 -70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 20 D2 03 52 -52 43 85 12 E6 D2 00 10 FE D2 05 52 52 43 2E 42 -85 12 E6 D2 40 10 0A D3 04 53 57 50 42 00 85 12 -E6 D2 80 10 18 D3 03 52 52 41 85 12 E6 D2 00 11 -26 D3 05 52 52 41 2E 42 85 12 E6 D2 40 11 32 D3 -03 53 58 54 85 12 E6 D2 80 11 00 00 04 50 55 53 -48 00 85 12 E6 D2 00 12 4C D3 06 50 55 53 48 2E -42 00 85 12 E6 D2 40 12 A6 D2 04 43 41 4C 4C 00 -85 12 E6 D2 80 12 1A 53 0E 4A 0D 12 84 12 D6 C6 -14 C2 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 -36 C3 40 D3 03 53 3E 3D 86 12 00 38 94 D3 02 53 -3C 00 86 12 00 34 5A D3 03 30 3E 3D 86 12 00 30 -A8 D3 02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 -86 12 00 2C BC D3 03 55 3E 3D 86 12 00 28 B2 D3 -03 30 3C 3E 86 12 00 24 D0 D3 02 30 3D 00 86 12 -00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 0E 4A 30 4D C6 D3 04 54 48 45 4E 00 -1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 -3A 90 00 02 B1 2F 88 DA 00 00 30 4D 56 D2 04 45 -4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 -C6 1D 2F 83 8F 4A 00 00 E3 3F 6A D3 05 42 45 47 -49 4E 30 40 28 C2 FA D3 05 55 4E 54 49 4C 3A 4F -08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 -00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 -C6 1D 30 4D DA D2 05 41 47 41 49 4E 0A 4E 38 40 -00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 -E8 D3 BA C5 60 C6 9E D3 06 52 45 50 45 41 54 00 -0D 12 84 12 7C D4 00 D4 60 C6 AC D4 3D 41 08 4E -3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 -30 4D 3C D4 03 42 57 31 85 12 AA D4 00 00 C4 D4 -03 42 57 32 85 12 AA D4 00 00 D0 D4 03 42 57 33 -85 12 AA D4 00 00 E8 D4 3D 41 1A 42 C6 1D 28 4E -B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A -00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 E6 D4 -00 00 08 D5 03 46 57 32 85 12 E6 D4 00 00 14 D5 -03 46 57 33 85 12 E6 D4 00 00 20 D5 04 47 4F 54 -4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 -92 CA EE C9 60 C6 00 00 05 3F 47 4F 54 4F 3E 90 -00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 -00 08 EC 3F 14 CA B0 CF 6A D5 92 53 C4 1D 3E 40 -2C 00 84 12 2C C7 50 C8 34 C2 12 CA 46 D1 80 D5 -0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C -59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E -AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 98 D4 04 52 -52 43 4D 00 85 12 64 D5 50 00 AE D5 04 52 52 41 -4D 00 85 12 64 D5 50 01 BC D5 04 52 4C 41 4D 00 -85 12 64 D5 50 02 CA D5 04 52 52 55 4D 00 85 12 -64 D5 50 03 DA D3 05 50 55 53 48 4D 85 12 64 D5 -00 15 E6 D5 04 50 4F 50 4D 00 85 12 64 D5 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 -94 C4 02 C4 02 C4 02 C4 02 C4 02 C4 02 C4 1A CF -q diff --git a/binaries/MSP_EXP430FR5969_16MHz_115200.txt b/binaries/MSP_EXP430FR5969_16MHz_115200.txt new file mode 100644 index 0000000..28d6b63 --- /dev/null +++ b/binaries/MSP_EXP430FR5969_16MHz_115200.txt @@ -0,0 +1,326 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 59 +D8 46 7E 45 84 45 54 45 48 47 36 57 EE 4F A8 4F +A8 4F BE 46 7C 47 44 47 3C 1D E0 1C 9C 49 B6 44 +C4 44 B8 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +48 47 36 57 EE 4F A8 4F A8 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 07 3D 0E 93 3E 4F +9C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BC 46 B2 49 +7A 47 B2 49 42 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 62 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 48 47 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 44 C2 48 AC 44 52 45 8A 47 1E 44 04 1B +5B 37 6D 00 AC 47 AC 47 1E 44 04 1B 5B 30 6D 00 +AC 47 F8 4C B0 12 7E 45 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 8A 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 AC 47 10 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 AC 47 0A 44 40 FF 32 44 +D8 48 DC 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 20 00 21 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 +B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 +26 03 F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 +41 01 F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 +66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 +F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 39 40 00 08 +29 83 89 43 00 1C FC 23 19 42 9E 01 1E 42 08 18 +82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 44 86 45 +00 00 0C 41 43 43 45 50 54 00 30 40 BE 46 08 4E +2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 1C 47 +3C 40 28 47 5D 15 94 3E 21 52 3A 17 58 42 CC 05 +48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 13 00 CE 05 +E2 D3 23 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F +0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 +A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D 1E 47 2D 83 +92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 DC 05 +FD 27 58 42 CC 05 08 4C EB 3F 00 00 06 4B 45 59 +30 40 44 47 30 12 5A 47 A2 B3 DC 05 FD 27 B2 40 +11 00 CE 05 E2 C3 23 02 30 41 2F 83 8F 4E 00 00 +92 B3 DC 05 FD 27 B0 12 E4 46 1E 42 CC 05 30 4D +00 00 08 45 4D 49 54 00 30 40 7C 47 08 4E 3E 4F +C7 3F 72 47 08 45 43 48 4F 00 B2 40 C2 48 16 47 +30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D +16 47 30 4D 00 00 08 54 59 50 45 00 0D 12 3D 40 +BC 47 29 4F 8F 4E 00 00 7E 49 DE 3F BE 47 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 6A 22 F9 98 +00 00 67 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 5E 22 9B 24 3C 47 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 44 00 00 DC 48 CE 47 20 4A +DA 4C B0 44 4A 48 14 44 06 5B 54 48 45 4E 5D 00 +D2 47 28 48 EE 47 0C 48 14 44 06 5B 45 4C 53 45 +5D 00 D2 47 3A 48 EE 47 0A 48 1E 44 04 5B 49 46 +5D 00 D2 47 0C 48 B2 44 0A 48 1E 44 05 0D 6B 6F +20 0A AC 47 9A 44 84 44 B2 44 0C 48 FA 47 0D 5B +54 48 45 4E 5D 00 30 4D 5E 48 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 6A 48 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 CE 47 20 4A 88 4A 2C 4C +9C 49 7A 48 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 CE 47 20 4A 88 4A AC 48 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D B2 46 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D D8 45 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A 44 1E 44 8A 4C 0A 44 22 00 20 4A 20 49 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 94 47 05 2E 22 00 0D 12 84 12 0A 49 +0A 44 AC 47 8A 4C 9C 49 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D 06 49 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 44 BF 4F 00 00 7A 90 0A 00 02 28 +7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D +C8 4A 00 00 30 4D 58 49 04 23 53 00 0D 12 84 12 +5A 49 94 49 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +88 49 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F A2 49 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 84 47 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 4E 49 CE 47 BC 49 +8C 49 B8 48 CA 49 A6 49 AC 47 9C 49 36 49 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D 0E 4A 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 92 4B 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 94 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +4A 49 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 44 CE 47 20 4A B0 44 64 4D 88 4A 4E 4C 0A 4E +3E 4F 3D 40 68 4C 6D 27 3D 40 42 4C 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 6A 4C 3E 4F 3D 40 42 4C +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 40 4E 2A 3C 32 4C 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D 88 4C 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D C4 49 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D EA 48 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E 44 02 0D 0A 00 AC 47 94 44 3C 4C CA 48 F4 48 +1E 44 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 45 +32 44 0A 44 40 FF FC 48 1E 44 09 46 52 41 4D 20 +66 75 6C 6C 08 45 B2 44 00 4D EA 4C 0D 41 42 4F +52 54 22 00 0D 12 84 12 0A 49 0A 44 08 45 8A 4C +9C 49 1A 4A 02 27 0D 12 84 12 CE 47 20 4A 88 4A +B0 44 66 4D 2E 49 72 4C 94 48 07 5B 27 5D 0D 12 +84 12 56 4D 0A 44 0A 44 8A 4C 8A 4C 9C 49 6A 4D +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D E2 48 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 CE 47 20 4A 88 4A B0 44 66 4D F4 48 AC 44 +BE 4D 0A 44 0A 44 8A 4C 8A 4C 0A 44 8A 4C 8A 4C +9C 49 00 00 02 3A 30 12 14 4E 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 CE 47 20 4A DC 4D 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 44 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 45 80 4D 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A 44 9C 49 8A 4C 26 4E 82 4D 9C 49 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D D4 4C 0C 43 52 45 41 54 45 00 B0 12 CA 4D +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D A6 47 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D C4 4D 0E 3A 4E 4F 4E 41 4D 45 +30 12 14 4E 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 5E 4E 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 56 4D E0 4E +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 6E 4D 0A 44 +E2 4E 8A 4C 9C 49 74 4E 08 43 4F 44 45 00 B0 12 +CA 4D A2 82 C8 1D 61 3C B6 49 0E 48 44 4E 43 4F +44 45 B2 40 CE 4F CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 26 4E 2C 4F 3D 41 92 42 +D0 1D CC 1D 5D 3C F8 4E 0E 43 4F 44 45 4E 4E 4D +30 12 02 4F B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F 0A 4F 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F 96 4F B2 40 A8 4F D0 1D 82 4E CE 1D +30 40 2E 49 85 12 94 4F 94 4D 3C 4D 26 50 38 4F +8E 4E D8 49 82 4A 54 4D 7C 4F CE 4E A8 4E 44 4E +9C 4C B0 50 DA 4A 00 00 00 00 85 12 94 4F 2A 57 +AE 55 0E 57 D6 54 32 55 80 55 5C 56 68 56 F8 53 +1C 55 00 00 00 00 6A 4F E8 52 00 00 84 56 C8 4F +B2 40 A8 4F CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +FC 4F 30 4D 0E 50 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 FC 4F 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 08 46 FE FF 29 83 B9 40 F2 45 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 00 50 82 43 4A 18 C7 3F +A2 50 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 8A 4D +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +CE 47 20 4A 88 4A AC 44 CE 50 C2 48 62 4C D0 50 +3E 4F 3D 41 B2 41 C6 1D B0 12 CA 4D BA 40 85 12 +FC FF BA 40 A0 50 FE FF 28 83 8A 48 00 00 BA 40 +82 44 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +20 4A 88 4A AC 44 3A 51 1A 51 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 A0 50 00 00 +01 20 3E 52 2E 83 21 53 30 41 32 4B AC 44 42 51 +36 51 44 51 B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 0A 51 15 20 3E 40 2B 00 +B0 12 0A 51 06 20 3E 40 2D 00 B0 12 0A 51 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 20 4A 32 4B AC 44 +66 4D 84 51 3E 51 3A 17 30 41 B0 12 4A 51 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 20 4A 32 4B AC 44 +BC 51 B4 51 3E 90 10 00 E6 2B 7C 2D BE 51 A2 41 +C6 1D E1 3F 03 20 B0 12 A2 51 43 3C 7A 90 23 00 +24 20 B0 12 52 51 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 52 51 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 9E 51 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 A2 51 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 8A 51 +F2 3F 03 20 B0 12 A2 51 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 8A 51 EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 44 00 13 8A 4C 9C 49 +0A 44 2C 00 80 52 C4 51 CE 47 8A 52 62 52 D0 52 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 C0 52 00 40 DC 52 0A 4D 4F 56 2E 42 85 12 +C0 52 40 40 00 00 06 41 44 44 85 12 C0 52 00 50 +F6 52 0A 41 44 44 2E 42 85 12 C0 52 40 50 02 53 +08 41 44 44 43 00 85 12 C0 52 00 60 10 53 0C 41 +44 44 43 2E 42 00 85 12 C0 52 40 60 48 4F 08 53 +55 42 43 00 85 12 C0 52 00 70 2E 53 0C 53 55 42 +43 2E 42 00 85 12 C0 52 40 70 3C 53 06 53 55 42 +85 12 C0 52 00 80 4C 53 0A 53 55 42 2E 42 85 12 +C0 52 40 80 58 53 06 43 4D 50 85 12 C0 52 00 90 +66 53 0A 43 4D 50 2E 42 85 12 C0 52 40 90 00 00 +08 44 41 44 44 00 85 12 C0 52 00 A0 80 53 0C 44 +41 44 44 2E 42 00 85 12 C0 52 40 A0 AE 52 06 42 +49 54 85 12 C0 52 00 B0 9E 53 0A 42 49 54 2E 42 +85 12 C0 52 40 B0 AA 53 06 42 49 43 85 12 C0 52 +00 C0 B8 53 0A 42 49 43 2E 42 85 12 C0 52 40 C0 +C4 53 06 42 49 53 85 12 C0 52 00 D0 D2 53 0A 42 +49 53 2E 42 85 12 C0 52 40 D0 00 00 06 58 4F 52 +85 12 C0 52 00 E0 EC 53 0A 58 4F 52 2E 42 85 12 +C0 52 40 E0 1E 53 06 41 4E 44 85 12 C0 52 00 F0 +06 54 0A 41 4E 44 2E 42 85 12 C0 52 40 F0 CE 47 +80 52 C4 51 26 54 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F DE 53 06 52 52 43 85 12 1E 54 +00 10 38 54 0A 52 52 43 2E 42 85 12 1E 54 40 10 +72 53 08 53 57 50 42 00 85 12 1E 54 80 10 44 54 +06 52 52 41 85 12 1E 54 00 11 60 54 0A 52 52 41 +2E 42 85 12 1E 54 40 11 52 54 06 53 58 54 85 12 +1E 54 80 11 00 00 08 50 55 53 48 00 85 12 1E 54 +00 12 86 54 0C 50 55 53 48 2E 42 00 85 12 1E 54 +40 12 7A 54 08 43 41 4C 4C 00 85 12 1E 54 80 12 +1A 53 0E 4A 84 12 10 4A 1E 44 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 45 A4 54 06 53 3E 3D +86 12 00 38 CC 54 04 53 3C 00 86 12 00 34 94 54 +06 30 3E 3D 86 12 00 30 E0 54 04 30 3C 00 86 12 +00 30 1C 4F 04 55 3C 00 86 12 00 2C F4 54 06 55 +3E 3D 86 12 00 28 EA 54 06 30 3C 3E 86 12 00 24 +08 55 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +8E 53 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D FE 54 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F 6C 54 0A 42 45 47 49 4E 30 40 32 44 56 55 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D 12 54 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 20 55 B6 48 9C 49 74 55 +0C 52 45 50 45 41 54 00 0D 12 84 12 B4 55 38 55 +9C 49 E4 55 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D D0 55 06 42 57 31 +85 12 E2 55 00 00 FC 55 06 42 57 32 85 12 E2 55 +00 00 08 56 06 42 57 33 85 12 E2 55 00 00 20 56 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 1E 56 00 00 44 56 +06 46 57 32 85 12 1E 56 00 00 50 56 06 46 57 33 +85 12 1E 56 00 00 BE 55 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 56 4D 62 4C +9C 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +8A 52 0A 44 2C 00 20 4A 32 4B AC 44 66 4D CE 47 +80 52 62 52 B6 56 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 14 56 08 52 52 43 4D 00 85 12 A0 56 50 00 +E4 56 08 52 52 41 4D 00 85 12 A0 56 50 01 F2 56 +08 52 4C 41 4D 00 85 12 A0 56 50 02 00 57 08 52 +52 55 4D 00 85 12 A0 56 50 03 12 55 0A 50 55 53 +48 4D 85 12 A0 56 00 15 1C 57 08 50 4F 50 4D 00 +85 12 A0 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +D8 46 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 08 46 +q diff --git a/binaries/MSP_EXP430FR5969_16MHz_4MBds.txt b/binaries/MSP_EXP430FR5969_16MHz_4MBds.txt new file mode 100644 index 0000000..80d6900 --- /dev/null +++ b/binaries/MSP_EXP430FR5969_16MHz_4MBds.txt @@ -0,0 +1,326 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +D8 46 7E 45 84 45 54 45 48 47 36 57 EE 4F A8 4F +A8 4F BE 46 7C 47 44 47 3C 1D E0 1C 9C 49 B6 44 +C4 44 B8 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +48 47 36 57 EE 4F A8 4F A8 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 07 3D 0E 93 3E 4F +9C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BC 46 B2 49 +7A 47 B2 49 42 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 62 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 48 47 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 44 C2 48 AC 44 52 45 8A 47 1E 44 04 1B +5B 37 6D 00 AC 47 AC 47 1E 44 04 1B 5B 30 6D 00 +AC 47 F8 4C B0 12 7E 45 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 8A 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 AC 47 10 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 AC 47 0A 44 40 FF 32 44 +D8 48 DC 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 20 00 21 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 +B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 +26 03 F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 +41 01 F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 +66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 +F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 39 40 00 08 +29 83 89 43 00 1C FC 23 19 42 9E 01 1E 42 08 18 +82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 44 86 45 +00 00 0C 41 43 43 45 50 54 00 30 40 BE 46 08 4E +2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 1C 47 +3C 40 28 47 5D 15 94 3E 21 52 3A 17 58 42 CC 05 +48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 13 00 CE 05 +E2 D3 23 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F +0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 +A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D 1E 47 2D 83 +92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 DC 05 +FD 27 58 42 CC 05 08 4C EB 3F 00 00 06 4B 45 59 +30 40 44 47 30 12 5A 47 A2 B3 DC 05 FD 27 B2 40 +11 00 CE 05 E2 C3 23 02 30 41 2F 83 8F 4E 00 00 +92 B3 DC 05 FD 27 B0 12 E4 46 1E 42 CC 05 30 4D +00 00 08 45 4D 49 54 00 30 40 7C 47 08 4E 3E 4F +C7 3F 72 47 08 45 43 48 4F 00 B2 40 C2 48 16 47 +30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D +16 47 30 4D 00 00 08 54 59 50 45 00 0D 12 3D 40 +BC 47 29 4F 8F 4E 00 00 7E 49 DE 3F BE 47 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 6A 22 F9 98 +00 00 67 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 5E 22 9B 24 3C 47 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 44 00 00 DC 48 CE 47 20 4A +DA 4C B0 44 4A 48 14 44 06 5B 54 48 45 4E 5D 00 +D2 47 28 48 EE 47 0C 48 14 44 06 5B 45 4C 53 45 +5D 00 D2 47 3A 48 EE 47 0A 48 1E 44 04 5B 49 46 +5D 00 D2 47 0C 48 B2 44 0A 48 1E 44 05 0D 6B 6F +20 0A AC 47 9A 44 84 44 B2 44 0C 48 FA 47 0D 5B +54 48 45 4E 5D 00 30 4D 5E 48 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 6A 48 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 CE 47 20 4A 88 4A 2C 4C +9C 49 7A 48 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 CE 47 20 4A 88 4A AC 48 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D B2 46 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D D8 45 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A 44 1E 44 8A 4C 0A 44 22 00 20 4A 20 49 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 94 47 05 2E 22 00 0D 12 84 12 0A 49 +0A 44 AC 47 8A 4C 9C 49 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D 06 49 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 44 BF 4F 00 00 7A 90 0A 00 02 28 +7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D +C8 4A 00 00 30 4D 58 49 04 23 53 00 0D 12 84 12 +5A 49 94 49 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +88 49 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F A2 49 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 84 47 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 4E 49 CE 47 BC 49 +8C 49 B8 48 CA 49 A6 49 AC 47 9C 49 36 49 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D 0E 4A 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 92 4B 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 94 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +4A 49 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 44 CE 47 20 4A B0 44 64 4D 88 4A 4E 4C 0A 4E +3E 4F 3D 40 68 4C 6D 27 3D 40 42 4C 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 6A 4C 3E 4F 3D 40 42 4C +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 40 4E 2A 3C 32 4C 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D 88 4C 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D C4 49 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D EA 48 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E 44 02 0D 0A 00 AC 47 94 44 3C 4C CA 48 F4 48 +1E 44 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 45 +32 44 0A 44 40 FF FC 48 1E 44 09 46 52 41 4D 20 +66 75 6C 6C 08 45 B2 44 00 4D EA 4C 0D 41 42 4F +52 54 22 00 0D 12 84 12 0A 49 0A 44 08 45 8A 4C +9C 49 1A 4A 02 27 0D 12 84 12 CE 47 20 4A 88 4A +B0 44 66 4D 2E 49 72 4C 94 48 07 5B 27 5D 0D 12 +84 12 56 4D 0A 44 0A 44 8A 4C 8A 4C 9C 49 6A 4D +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D E2 48 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 CE 47 20 4A 88 4A B0 44 66 4D F4 48 AC 44 +BE 4D 0A 44 0A 44 8A 4C 8A 4C 0A 44 8A 4C 8A 4C +9C 49 00 00 02 3A 30 12 14 4E 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 CE 47 20 4A DC 4D 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 44 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 45 80 4D 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A 44 9C 49 8A 4C 26 4E 82 4D 9C 49 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D D4 4C 0C 43 52 45 41 54 45 00 B0 12 CA 4D +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D A6 47 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D C4 4D 0E 3A 4E 4F 4E 41 4D 45 +30 12 14 4E 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 5E 4E 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 56 4D E0 4E +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 6E 4D 0A 44 +E2 4E 8A 4C 9C 49 74 4E 08 43 4F 44 45 00 B0 12 +CA 4D A2 82 C8 1D 61 3C B6 49 0E 48 44 4E 43 4F +44 45 B2 40 CE 4F CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 26 4E 2C 4F 3D 41 92 42 +D0 1D CC 1D 5D 3C F8 4E 0E 43 4F 44 45 4E 4E 4D +30 12 02 4F B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F 0A 4F 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F 96 4F B2 40 A8 4F D0 1D 82 4E CE 1D +30 40 2E 49 85 12 94 4F 94 4D 3C 4D 26 50 38 4F +8E 4E D8 49 82 4A 54 4D 7C 4F CE 4E A8 4E 44 4E +9C 4C B0 50 DA 4A 00 00 00 00 85 12 94 4F 2A 57 +AE 55 0E 57 D6 54 32 55 80 55 5C 56 68 56 F8 53 +1C 55 00 00 00 00 6A 4F E8 52 00 00 84 56 C8 4F +B2 40 A8 4F CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +FC 4F 30 4D 0E 50 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 FC 4F 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 08 46 FE FF 29 83 B9 40 F2 45 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 00 50 82 43 4A 18 C7 3F +A2 50 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 8A 4D +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +CE 47 20 4A 88 4A AC 44 CE 50 C2 48 62 4C D0 50 +3E 4F 3D 41 B2 41 C6 1D B0 12 CA 4D BA 40 85 12 +FC FF BA 40 A0 50 FE FF 28 83 8A 48 00 00 BA 40 +82 44 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +20 4A 88 4A AC 44 3A 51 1A 51 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 A0 50 00 00 +01 20 3E 52 2E 83 21 53 30 41 32 4B AC 44 42 51 +36 51 44 51 B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 0A 51 15 20 3E 40 2B 00 +B0 12 0A 51 06 20 3E 40 2D 00 B0 12 0A 51 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 20 4A 32 4B AC 44 +66 4D 84 51 3E 51 3A 17 30 41 B0 12 4A 51 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 20 4A 32 4B AC 44 +BC 51 B4 51 3E 90 10 00 E6 2B 7C 2D BE 51 A2 41 +C6 1D E1 3F 03 20 B0 12 A2 51 43 3C 7A 90 23 00 +24 20 B0 12 52 51 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 52 51 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 9E 51 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 A2 51 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 8A 51 +F2 3F 03 20 B0 12 A2 51 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 8A 51 EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 44 00 13 8A 4C 9C 49 +0A 44 2C 00 80 52 C4 51 CE 47 8A 52 62 52 D0 52 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 C0 52 00 40 DC 52 0A 4D 4F 56 2E 42 85 12 +C0 52 40 40 00 00 06 41 44 44 85 12 C0 52 00 50 +F6 52 0A 41 44 44 2E 42 85 12 C0 52 40 50 02 53 +08 41 44 44 43 00 85 12 C0 52 00 60 10 53 0C 41 +44 44 43 2E 42 00 85 12 C0 52 40 60 48 4F 08 53 +55 42 43 00 85 12 C0 52 00 70 2E 53 0C 53 55 42 +43 2E 42 00 85 12 C0 52 40 70 3C 53 06 53 55 42 +85 12 C0 52 00 80 4C 53 0A 53 55 42 2E 42 85 12 +C0 52 40 80 58 53 06 43 4D 50 85 12 C0 52 00 90 +66 53 0A 43 4D 50 2E 42 85 12 C0 52 40 90 00 00 +08 44 41 44 44 00 85 12 C0 52 00 A0 80 53 0C 44 +41 44 44 2E 42 00 85 12 C0 52 40 A0 AE 52 06 42 +49 54 85 12 C0 52 00 B0 9E 53 0A 42 49 54 2E 42 +85 12 C0 52 40 B0 AA 53 06 42 49 43 85 12 C0 52 +00 C0 B8 53 0A 42 49 43 2E 42 85 12 C0 52 40 C0 +C4 53 06 42 49 53 85 12 C0 52 00 D0 D2 53 0A 42 +49 53 2E 42 85 12 C0 52 40 D0 00 00 06 58 4F 52 +85 12 C0 52 00 E0 EC 53 0A 58 4F 52 2E 42 85 12 +C0 52 40 E0 1E 53 06 41 4E 44 85 12 C0 52 00 F0 +06 54 0A 41 4E 44 2E 42 85 12 C0 52 40 F0 CE 47 +80 52 C4 51 26 54 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F DE 53 06 52 52 43 85 12 1E 54 +00 10 38 54 0A 52 52 43 2E 42 85 12 1E 54 40 10 +72 53 08 53 57 50 42 00 85 12 1E 54 80 10 44 54 +06 52 52 41 85 12 1E 54 00 11 60 54 0A 52 52 41 +2E 42 85 12 1E 54 40 11 52 54 06 53 58 54 85 12 +1E 54 80 11 00 00 08 50 55 53 48 00 85 12 1E 54 +00 12 86 54 0C 50 55 53 48 2E 42 00 85 12 1E 54 +40 12 7A 54 08 43 41 4C 4C 00 85 12 1E 54 80 12 +1A 53 0E 4A 84 12 10 4A 1E 44 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 45 A4 54 06 53 3E 3D +86 12 00 38 CC 54 04 53 3C 00 86 12 00 34 94 54 +06 30 3E 3D 86 12 00 30 E0 54 04 30 3C 00 86 12 +00 30 1C 4F 04 55 3C 00 86 12 00 2C F4 54 06 55 +3E 3D 86 12 00 28 EA 54 06 30 3C 3E 86 12 00 24 +08 55 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +8E 53 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D FE 54 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F 6C 54 0A 42 45 47 49 4E 30 40 32 44 56 55 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D 12 54 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 20 55 B6 48 9C 49 74 55 +0C 52 45 50 45 41 54 00 0D 12 84 12 B4 55 38 55 +9C 49 E4 55 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D D0 55 06 42 57 31 +85 12 E2 55 00 00 FC 55 06 42 57 32 85 12 E2 55 +00 00 08 56 06 42 57 33 85 12 E2 55 00 00 20 56 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 1E 56 00 00 44 56 +06 46 57 32 85 12 1E 56 00 00 50 56 06 46 57 33 +85 12 1E 56 00 00 BE 55 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 56 4D 62 4C +9C 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +8A 52 0A 44 2C 00 20 4A 32 4B AC 44 66 4D CE 47 +80 52 62 52 B6 56 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 14 56 08 52 52 43 4D 00 85 12 A0 56 50 00 +E4 56 08 52 52 41 4D 00 85 12 A0 56 50 01 F2 56 +08 52 4C 41 4D 00 85 12 A0 56 50 02 00 57 08 52 +52 55 4D 00 85 12 A0 56 50 03 12 55 0A 50 55 53 +48 4D 85 12 A0 56 00 15 1C 57 08 50 4F 50 4D 00 +85 12 A0 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +D8 46 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 08 46 +q diff --git a/binaries/MSP_EXP430FR5969_16MHz_I2C.txt b/binaries/MSP_EXP430FR5969_16MHz_I2C.txt index c0003bf..f1177bf 100644 --- a/binaries/MSP_EXP430FR5969_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5969_16MHz_I2C.txt @@ -1,336 +1,324 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF F8 57 F2 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 84 46 F8 57 -F2 4F 72 46 82 47 00 47 DC 46 3C 1D 50 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +D2 46 56 45 56 45 58 45 44 45 12 57 CA 4F 84 4F +84 4F C0 46 44 47 1C 47 3C 1D E0 1C 78 49 B6 44 +C4 44 94 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 12 57 CA 4F 84 4F 84 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 70 46 B2 49 80 47 B2 49 FE 46 B2 49 DA 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D D0 47 18 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 98 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C 47 90 48 4C 47 -14 44 04 1B 5B 30 6D 00 4C 47 18 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 -B0 12 8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 -07 0D 0A 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 0A 44 23 00 FC 46 C6 48 14 44 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C 47 0A 44 40 FF 28 44 C4 47 -90 48 14 44 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 44 7E 45 00 00 06 41 43 43 45 50 54 00 30 40 -72 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 -B7 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 46 2F 83 8F 4E -00 00 58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 -4C 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 47 -08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D -F6 46 04 45 43 48 4F 00 B2 40 C2 48 0A 47 82 43 -DE 1D 38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 47 92 43 DE 1D -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE 46 6A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 -82 47 0D 12 84 12 14 44 02 0D 0A 00 4C 47 50 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 46 01 40 -2E 4E 30 4D CE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 7A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 0A 48 02 23 53 00 0D 12 -84 12 0C 48 46 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 48 3E 48 EE 44 7E 48 5A 48 4C 47 04 4C FC 46 -50 48 2E 47 01 2E 0E 93 E3 37 38 43 E2 3F 78 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -4A 4B 0A 44 22 00 1C 49 EA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -C4 48 82 2E 22 00 0D 12 84 12 D4 48 0A 44 4C 47 -4A 4B 50 48 FA 45 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9E 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 08 3D 0E 93 3E 4F +8A 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BE 46 B2 49 +42 47 B2 49 1A 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 3E 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 9E 48 AC 44 +42 45 5C 47 1E 44 05 1B 5B 37 6D 40 88 47 0A 44 +02 18 C0 48 EC 49 88 47 1E 44 04 1B 5B 30 6D 00 +88 47 D4 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 5C 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 88 47 0A 44 02 18 C0 48 EC 49 0A 44 23 00 +40 47 EC 49 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +88 47 0A 44 40 FF 32 44 B4 48 B8 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +20 00 21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 40 FE FF 02 02 +B2 D3 06 02 B2 D3 26 02 B2 40 FF BF 22 02 F2 43 +22 03 F2 D3 26 03 F2 40 A5 00 41 01 F2 40 10 00 +40 01 D2 43 41 01 F2 40 A5 00 61 01 B2 40 48 00 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 D2 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 +39 40 00 08 29 83 89 43 00 1C FC 23 1E 42 08 18 +82 43 08 18 3E F3 02 20 1E 42 9E 01 B0 12 D0 44 +80 45 00 00 0C 41 43 43 45 50 54 00 30 40 C0 46 +0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 +97 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 90 22 +3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 +48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F +0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C +1B 3C 00 00 06 4B 45 59 30 40 1C 47 58 43 B0 12 +46 45 2F 83 8F 4E 00 00 92 B3 6C 06 FD 27 1E 42 +4C 06 B0 12 44 45 30 4D 00 00 08 45 4D 49 54 00 +30 40 44 47 08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 +4E 06 30 4D 3A 47 08 45 43 48 4F 00 B2 40 C2 48 +4E 47 38 40 05 00 B0 12 46 45 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 4E 47 28 42 F3 3F +00 00 08 54 59 50 45 00 0D 12 3D 40 98 47 29 4F +8F 4E 00 00 7E 49 D4 3F 9A 47 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 7C 22 F9 98 00 00 79 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +70 22 9B 24 14 47 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A 44 00 00 B8 48 AA 47 FC 49 B6 4C B0 44 +26 48 14 44 06 5B 54 48 45 4E 5D 00 AE 47 04 48 +CA 47 E8 47 14 44 06 5B 45 4C 53 45 5D 00 AE 47 +16 48 CA 47 E6 47 1E 44 04 5B 49 46 5D 00 AE 47 +E8 47 B2 44 E6 47 1E 44 05 0D 6B 6F 20 0A 88 47 +9A 44 84 44 B2 44 E8 47 D6 47 0D 5B 54 48 45 4E +5D 00 30 4D 3A 48 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D 46 48 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 AA 47 FC 49 64 4A 08 4C 78 49 56 48 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +AA 47 FC 49 64 4A 88 48 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D B4 46 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +E0 45 05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 44 +1E 44 66 4C 0A 44 22 00 FC 49 FC 48 B2 40 20 00 +C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D +6E 47 05 2E 22 00 0D 12 84 12 E6 48 0A 44 88 47 +66 4C 78 49 00 00 04 3C 23 00 B2 40 B2 1D B2 1D +30 4D E2 48 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 +46 44 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 +30 4D 34 49 04 23 53 00 0D 12 84 12 36 49 70 49 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D 64 49 04 23 +3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 7E 49 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 56 47 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 2A 49 AA 47 98 49 68 49 94 48 +A6 49 82 49 88 47 78 49 12 49 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D +1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D EA 49 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 +8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D +0C 4E 0E 43 1E 15 3D 40 6E 4B 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 70 4B +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 48 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 04 4C 1C 49 C0 4B -9C 26 3D 40 C8 4B DE 3E CA 4B 0A 4E 3E 4F 3D 40 -E4 4B 36 27 3D 40 BA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 E6 4B 3E 4F 3D 40 BA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 4D -CC 3F EE 4B 86 12 20 00 D6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7E 47 -BC 44 B4 4B B4 47 E6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -EE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 2E 4C 0A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 48 0A 44 2A 45 4A 4B 50 48 7E 49 -01 27 0D 12 84 12 04 4C 1C 49 84 49 34 44 02 4C -50 48 00 00 83 5B 27 5D 0D 12 84 12 82 4C 0A 44 -0A 44 4A 4B 4A 4B 50 48 94 4C 81 5B 82 43 BE 1D -30 4D FC 47 01 5D B2 43 BE 1D 30 4D B4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 4C 1C 49 84 49 98 47 -34 44 02 4C E6 47 34 44 F6 4C 0A 44 0A 44 4A 4B -4A 4B 0A 44 4A 4B 4A 4B 50 48 AA 4C 01 3A 30 12 -46 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 04 4C -1C 49 14 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 FC 4C 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 50 48 4A 4B 58 4D AC 4C -50 48 AA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 94 4B 06 43 52 45 -41 54 45 00 B0 12 02 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC 4D 04 43 4F 44 45 00 B0 12 02 4D -A2 82 C6 1D 0D 12 84 12 F4 4F CE 4F 50 48 A4 4D -07 48 44 4E 43 4F 44 45 B2 40 D2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 4D -0E 50 2C 50 50 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 0E 50 2C 50 50 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F F0 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 -9C 4F 4A 4B AC 4C E4 4D 50 48 8A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 C8 47 04 4C 1C 49 -9A 4B 90 47 34 44 04 4F 9E 47 14 44 06 5B 54 48 -45 4E 5D 00 76 4E DE 4E 9A 4E BC 4E 50 48 9E 47 -14 44 06 5B 45 4C 53 45 5D 00 76 4E F4 4E 9A 4E -BA 4E 50 48 14 44 04 5B 49 46 5D 00 76 4E BC 4E -3A 44 BA 4E 72 47 14 44 05 0D 0A 6B 6F 20 4C 47 -BC 44 AC 44 3A 44 BC 4E AA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 4C 1C 49 -84 49 28 4F 50 48 2E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 4F E0 47 50 48 60 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C 4B -06 4D 41 52 4B 45 52 00 B0 12 02 4D BA 40 85 12 -FC FF BA 40 5E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D D8 47 50 48 85 12 A0 4F 68 4C D6 4D -12 47 80 4C 54 4E D4 46 70 4F 02 49 98 50 AC 50 -8C 48 16 49 00 00 48 4F BE 4C E4 49 00 00 85 12 -A0 4F 6E 56 D4 56 16 56 24 57 DC 55 00 00 A8 53 -00 00 EC 57 D0 57 40 56 7E 56 B8 54 00 00 00 00 -40 57 CC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D A8 4F 26 50 2C 50 3C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 34 50 -F8 57 D0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 50 F3 3F 72 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 80 50 30 4D 84 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A 51 FE FF 29 83 -B9 40 E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 45 B2 49 FA 44 B2 49 02 44 B2 49 02 46 -B2 49 EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 B2 40 -FF BF 22 02 F2 43 22 03 F2 D3 26 03 F2 40 A5 00 -41 01 F2 40 10 00 40 01 D2 43 41 01 F2 40 A5 00 -61 01 B2 40 48 00 62 01 82 43 66 01 B2 40 33 00 -64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 10 00 2A 03 -F2 C0 40 00 A1 04 1E 42 08 18 82 43 08 18 1E D2 -9E 01 B0 12 F8 44 00 46 38 40 C0 1D 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 -12 12 C4 1D 84 12 1C 49 84 49 E0 47 34 44 E8 51 -40 4A 34 44 02 52 FC 51 EA 51 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 04 52 B2 41 C4 1D 3E 41 84 12 0A 44 2B 00 -1C 49 84 49 E0 47 34 44 20 52 40 4A 34 44 02 4C -AA 47 1C 49 40 4A 34 44 02 4C 2C 52 3E 5F E7 3F -3E 40 28 00 B0 12 CC 51 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 -30 40 70 4D 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 -1C 49 40 4A 34 44 74 52 6A 52 21 53 3E 90 10 00 -C6 2B 7F 2D 76 52 B2 41 C4 1D C1 3F 0D 12 84 12 -04 4C A8 51 86 52 0C 43 1B 42 C6 1D A2 53 C6 1D -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 -CC 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 44 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D 26 49 03 5C +92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 44 AA 47 +FC 49 B0 44 40 4D 64 4A 2A 4C 0A 4E 3E 4F 3D 40 +44 4C 6D 27 3D 40 1E 4C 1A E2 BC 1D 14 24 0E 12 +3E 4F 30 41 46 4C 3E 4F 3D 40 1E 4C 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 1C 4E +2A 3C 0E 4C 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E +FE FF 3E 4F 30 4D 64 4C 0F 4C 49 54 45 52 41 4C +82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D +BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D A0 49 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D C6 48 0A 41 4C 4C 4F 54 82 5E C8 1D +3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 44 02 0D +0A 00 88 47 94 44 18 4C A6 48 D0 48 1E 44 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 45 32 44 0A 44 +40 FF D8 48 1E 44 09 46 52 41 4D 20 66 75 6C 6C +08 45 B2 44 DC 4C C6 4C 0D 41 42 4F 52 54 22 00 +0D 12 84 12 E6 48 0A 44 08 45 66 4C 78 49 F6 49 +02 27 0D 12 84 12 AA 47 FC 49 64 4A B0 44 42 4D +0A 49 4E 4C 70 48 07 5B 27 5D 0D 12 84 12 32 4D +0A 44 0A 44 66 4C 66 4C 78 49 46 4D 03 5B 82 43 +BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D BE 48 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 AA 47 +FC 49 64 4A B0 44 42 4D D0 48 AC 44 9A 4D 0A 44 +0A 44 66 4C 66 4C 0A 44 66 4C 66 4C 78 49 00 00 +02 3A 30 12 F0 4D 92 B3 C8 1D A2 63 C8 1D 0D 12 +84 12 AA 47 FC 49 B8 4D 3D 41 5A D3 5A 53 0A 5E +19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D +82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D +30 4D 82 9F BA 1D 66 25 84 12 1E 44 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 45 5C 4D +03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 44 78 49 +66 4C 02 4E 5E 4D 78 49 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D B0 4C +0C 43 52 45 41 54 45 00 B0 12 A6 4D BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D 82 47 0A 44 4F 45 53 3E +1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D A0 4D 0E 3A 4E 4F 4E 41 4D 45 30 12 F0 4D +2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F 3A 4E 05 49 53 00 0D 12 +82 93 BC 1D 08 20 84 12 32 4D BC 4E 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 4A 4D 0A 44 BE 4E 66 4C +78 49 50 4E 08 43 4F 44 45 00 B0 12 A6 4D A2 82 +C8 1D 61 3C 92 49 0E 48 44 4E 43 4F 44 45 B2 40 +AA 4F CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 02 4E 08 4F 3D 41 92 42 D0 1D CC 1D +5D 3C D4 4E 0E 43 4F 44 45 4E 4E 4D 30 12 DE 4E +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 +BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D +1A 42 C8 1D EF 3F E6 4E 0B 48 49 32 4C 4F A2 53 +C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F +72 4F B2 40 84 4F D0 1D 82 4E CE 1D 30 40 0A 49 +85 12 70 4F 70 4D 18 4D 02 50 14 4F 6A 4E B4 49 +5E 4A 30 4D 58 4F AA 4E 84 4E 20 4E 78 4C 8C 50 +B6 4A 00 00 00 00 85 12 70 4F 06 57 8A 55 EA 56 +B2 54 0E 55 5C 55 38 56 44 56 D4 53 F8 54 00 00 +00 00 46 4F C4 52 00 00 60 56 A4 4F B2 40 84 4F +CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 1D 3A 40 42 18 B0 12 D8 4F 30 4D +EA 4F 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 1D B0 12 D8 4F 1A 42 CA 1D 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +10 46 FE FF 29 83 B9 40 FA 45 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 EE FF 3B 40 10 00 3A 40 +3A 18 B0 12 DC 4F 82 43 4A 18 C7 3F 7E 50 B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F 66 4D 0C 4D 41 52 +4B 45 52 00 12 12 C6 1D 0D 12 84 12 AA 47 FC 49 +64 4A AC 44 AA 50 9E 48 3E 4C AC 50 3E 4F 3D 41 +B2 41 C6 1D B0 12 A6 4D BA 40 85 12 FC FF BA 40 +7C 50 FE FF 28 83 8A 48 00 00 BA 40 82 44 02 00 +A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 1D 84 12 FC 49 64 4A +AC 44 16 51 F6 50 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 7C 50 00 00 01 20 3E 52 +2E 83 21 53 30 41 0E 4B AC 44 1E 51 12 51 20 51 +B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E +3D 15 B0 12 E6 50 15 20 3E 40 2B 00 B0 12 E6 50 +06 20 3E 40 2D 00 B0 12 E6 50 92 83 C6 1D 0E 12 +1E 41 02 00 84 12 FC 49 0E 4B AC 44 42 4D 60 51 +3E 51 3A 17 30 41 B0 12 26 51 19 42 C8 1D 89 4E +00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 +C6 1D 3D 15 84 12 FC 49 0E 4B AC 44 98 51 90 51 +3E 90 10 00 E6 2B 7C 2D 9A 51 A2 41 C6 1D E1 3F +03 20 B0 12 7E 51 43 3C 7A 90 23 00 24 20 B0 12 +2E 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 1D B0 12 CC 51 ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 1D B0 12 54 52 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 54 52 92 92 C0 1D -C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 -54 52 FA 23 3C 50 10 00 B0 12 30 52 EF 3F 0C 43 -1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 04 4C A8 51 -52 53 FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 54 52 E0 23 3C 50 80 00 B0 12 -30 52 DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 44 00 13 4A 4B 50 48 0A 44 2C 00 7C 52 48 53 -92 53 09 4B 2E 4E 0E DC A2 3F 42 4E 03 4D 4F 56 -85 12 88 53 00 40 9C 53 05 4D 4F 56 2E 42 85 12 -88 53 40 40 00 00 03 41 44 44 85 12 88 53 00 50 -B6 53 05 41 44 44 2E 42 85 12 88 53 40 50 C2 53 -04 41 44 44 43 00 85 12 88 53 00 60 D0 53 06 41 -44 44 43 2E 42 00 85 12 88 53 40 60 76 53 04 53 -55 42 43 00 85 12 88 53 00 70 EE 53 06 53 55 42 -43 2E 42 00 85 12 88 53 40 70 FC 53 03 53 55 42 -85 12 88 53 00 80 0C 54 05 53 55 42 2E 42 85 12 -88 53 40 80 18 4E 03 43 4D 50 85 12 88 53 00 90 -26 54 05 43 4D 50 2E 42 85 12 88 53 40 90 02 4E -04 44 41 44 44 00 85 12 88 53 00 A0 40 54 06 44 -41 44 44 2E 42 00 85 12 88 53 40 A0 32 54 03 42 -49 54 85 12 88 53 00 B0 5E 54 05 42 49 54 2E 42 -85 12 88 53 40 B0 6A 54 03 42 49 43 85 12 88 53 -00 C0 78 54 05 42 49 43 2E 42 85 12 88 53 40 C0 -84 54 03 42 49 53 85 12 88 53 00 D0 92 54 05 42 -49 53 2E 42 85 12 88 53 40 D0 00 00 03 58 4F 52 -85 12 88 53 00 E0 AC 54 05 58 4F 52 2E 42 85 12 -88 53 40 E0 DE 53 03 41 4E 44 85 12 88 53 00 F0 -C6 54 05 41 4E 44 2E 42 85 12 88 53 40 F0 04 4C -7C 52 E4 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 18 54 03 52 52 43 85 12 DE 54 00 10 -F6 54 05 52 52 43 2E 42 85 12 DE 54 40 10 02 55 -04 53 57 50 42 00 85 12 DE 54 80 10 10 55 03 52 -52 41 85 12 DE 54 00 11 1E 55 05 52 52 41 2E 42 -85 12 DE 54 40 11 2A 55 03 53 58 54 85 12 DE 54 -80 11 00 00 04 50 55 53 48 00 85 12 DE 54 00 12 -44 55 06 50 55 53 48 2E 42 00 85 12 DE 54 40 12 -9E 54 04 43 41 4C 4C 00 85 12 DE 54 80 12 1A 53 -0E 4A 0D 12 84 12 C6 48 14 44 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 45 38 55 03 53 3E 3D -86 12 00 38 8C 55 02 53 3C 00 86 12 00 34 52 55 -03 30 3E 3D 86 12 00 30 A0 55 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C B4 55 03 55 -3E 3D 86 12 00 28 AA 55 03 30 3C 3E 86 12 00 24 -C8 55 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D -BE 55 04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 4E 54 04 45 4C 53 45 00 1A 42 C6 1D -BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 -E3 3F 62 55 05 42 45 47 49 4E 30 40 28 44 F2 55 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 1D 30 4D D2 54 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 E0 55 AA 47 50 48 96 55 -06 52 45 50 45 41 54 00 0D 12 84 12 74 56 F8 55 -50 48 A4 56 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D -CB 2F 98 42 C6 1D 00 00 30 4D 34 56 03 42 57 31 -85 12 A2 56 00 00 BC 56 03 42 57 32 85 12 A2 56 -00 00 C8 56 03 42 57 33 85 12 A2 56 00 00 E0 56 -3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F -00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 DE 56 00 00 00 57 03 46 57 32 -85 12 DE 56 00 00 0C 57 03 46 57 33 85 12 DE 56 -00 00 18 57 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 82 4C DE 4B 50 48 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 04 4C A8 51 -62 57 92 53 C4 1D 3E 40 2C 00 84 12 1C 49 40 4A -34 44 02 4C 3E 53 78 57 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 90 56 04 52 52 43 4D 00 85 12 5C 57 -50 00 A6 57 04 52 52 41 4D 00 85 12 5C 57 50 01 -B4 57 04 52 4C 41 4D 00 85 12 5C 57 50 02 C2 57 -04 52 52 55 4D 00 85 12 5C 57 50 03 D2 55 05 50 -55 53 48 4D 85 12 5C 57 00 15 DE 57 04 50 4F 50 -4D 00 85 12 5C 57 00 17 +08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 2E 51 F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 7A 51 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +7E 51 92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 66 51 F2 3F 03 20 +B0 12 7E 51 F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 66 51 EA 3F 0C 43 1B 42 +C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 +C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 +C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A 44 00 13 66 4C 78 49 0A 44 2C 00 +5C 52 A0 51 AA 47 66 52 3E 52 AC 52 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 9C 52 +00 40 B8 52 0A 4D 4F 56 2E 42 85 12 9C 52 40 40 +00 00 06 41 44 44 85 12 9C 52 00 50 D2 52 0A 41 +44 44 2E 42 85 12 9C 52 40 50 DE 52 08 41 44 44 +43 00 85 12 9C 52 00 60 EC 52 0C 41 44 44 43 2E +42 00 85 12 9C 52 40 60 24 4F 08 53 55 42 43 00 +85 12 9C 52 00 70 0A 53 0C 53 55 42 43 2E 42 00 +85 12 9C 52 40 70 18 53 06 53 55 42 85 12 9C 52 +00 80 28 53 0A 53 55 42 2E 42 85 12 9C 52 40 80 +34 53 06 43 4D 50 85 12 9C 52 00 90 42 53 0A 43 +4D 50 2E 42 85 12 9C 52 40 90 00 00 08 44 41 44 +44 00 85 12 9C 52 00 A0 5C 53 0C 44 41 44 44 2E +42 00 85 12 9C 52 40 A0 8A 52 06 42 49 54 85 12 +9C 52 00 B0 7A 53 0A 42 49 54 2E 42 85 12 9C 52 +40 B0 86 53 06 42 49 43 85 12 9C 52 00 C0 94 53 +0A 42 49 43 2E 42 85 12 9C 52 40 C0 A0 53 06 42 +49 53 85 12 9C 52 00 D0 AE 53 0A 42 49 53 2E 42 +85 12 9C 52 40 D0 00 00 06 58 4F 52 85 12 9C 52 +00 E0 C8 53 0A 58 4F 52 2E 42 85 12 9C 52 40 E0 +FA 52 06 41 4E 44 85 12 9C 52 00 F0 E2 53 0A 41 +4E 44 2E 42 85 12 9C 52 40 F0 AA 47 5C 52 A0 51 +02 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F BA 53 06 52 52 43 85 12 FA 53 00 10 14 54 +0A 52 52 43 2E 42 85 12 FA 53 40 10 4E 53 08 53 +57 50 42 00 85 12 FA 53 80 10 20 54 06 52 52 41 +85 12 FA 53 00 11 3C 54 0A 52 52 41 2E 42 85 12 +FA 53 40 11 2E 54 06 53 58 54 85 12 FA 53 80 11 +00 00 08 50 55 53 48 00 85 12 FA 53 00 12 62 54 +0C 50 55 53 48 2E 42 00 85 12 FA 53 40 12 56 54 +08 43 41 4C 4C 00 85 12 FA 53 80 12 1A 53 0E 4A +84 12 EC 49 1E 44 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 45 80 54 06 53 3E 3D 86 12 00 38 +A8 54 04 53 3C 00 86 12 00 34 70 54 06 30 3E 3D +86 12 00 30 BC 54 04 30 3C 00 86 12 00 30 F8 4E +04 55 3C 00 86 12 00 2C D0 54 06 55 3E 3D 86 12 +00 28 C6 54 06 30 3C 3E 86 12 00 24 E4 54 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D +8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D 6A 53 08 54 +48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +DA 54 08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C +00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F 48 54 +0A 42 45 47 49 4E 30 40 32 44 32 55 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 1D 30 4D EE 53 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 FC 54 92 48 78 49 50 55 0C 52 45 50 +45 41 54 00 0D 12 84 12 90 55 14 55 78 49 C0 55 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 +C8 1D 00 00 30 4D AC 55 06 42 57 31 85 12 BE 55 +00 00 D8 55 06 42 57 32 85 12 BE 55 00 00 E4 55 +06 42 57 33 85 12 BE 55 00 00 FC 55 3D 41 1A 42 +C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F +00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 FA 55 00 00 20 56 06 46 57 32 +85 12 FA 55 00 00 2C 56 06 46 57 33 85 12 FA 55 +00 00 9A 55 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 32 4D 3E 4C 78 49 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F 66 52 0A 44 +2C 00 FC 49 0E 4B AC 44 42 4D AA 47 5C 52 3E 52 +92 56 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E F0 55 +08 52 52 43 4D 00 85 12 7C 56 50 00 C0 56 08 52 +52 41 4D 00 85 12 7C 56 50 01 CE 56 08 52 4C 41 +4D 00 85 12 7C 56 50 02 DC 56 08 52 52 55 4D 00 +85 12 7C 56 50 03 EE 54 0A 50 55 53 48 4D 85 12 +7C 56 00 15 F8 56 08 50 4F 50 4D 00 85 12 7C 56 +00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 84 46 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 0A 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 D2 46 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 10 46 q diff --git a/binaries/MSP_EXP430FR5969_16MHz_UART.txt b/binaries/MSP_EXP430FR5969_16MHz_UART.txt deleted file mode 100644 index 9d0e833..0000000 --- a/binaries/MSP_EXP430FR5969_16MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 0E 58 04 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 96 46 0E 58 -04 50 7C 46 94 47 26 47 00 47 3C 1D 62 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 7A 46 B2 49 92 47 B2 49 24 47 B2 49 FE 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 D0 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E2 47 34 47 -14 44 04 1B 5B 37 6D 00 5E 47 AA 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E 47 A2 48 5E 47 14 44 04 1B 5B 30 6D 00 -5E 47 2A 4C 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D3 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C3 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 -B0 12 9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 -5E 47 D8 48 14 44 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E 47 0A 44 40 FF 28 44 D6 47 A2 48 14 44 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 44 86 45 00 00 -06 41 43 43 45 50 54 00 30 40 7C 46 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 46 3C 40 -D4 46 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 46 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 47 -2F 83 8F 4E 00 00 B0 12 DA 45 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 47 08 4E 3E 4F C8 3F 1C 47 04 45 -43 48 4F 00 B2 40 C2 48 C2 46 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 46 -92 43 DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A 47 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 47 7C 47 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 -30 40 94 47 0D 12 84 12 14 44 02 0D 0A 00 5E 47 -62 48 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 46 -01 40 2E 4E 30 4D E0 47 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 1D B2 1D 30 4D 8C 47 01 23 1B 42 -DC 1D 2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D -18 42 B2 1D C8 4A 00 00 30 4D 1C 48 02 23 53 00 -0D 12 84 12 1E 48 58 48 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C 48 02 23 3E 00 9F 42 B2 1D -00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 47 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 48 50 48 EE 44 90 48 6C 48 5E 47 16 4C -22 47 62 48 42 47 01 2E 0E 93 E3 37 38 43 E2 3F -8A 48 82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 -14 44 5C 4B 0A 44 22 00 2E 49 FC 48 B2 40 20 00 -B4 1D 6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 -30 4D D6 48 82 2E 22 00 0D 12 84 12 E6 48 0A 44 -5E 47 5C 4B 62 48 1A 46 04 57 4F 52 44 00 3C 40 -C0 1D 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A -C4 1D 1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 -D4 44 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 -B0 4A 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 4A 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D -8A 4E 00 00 A2 53 C6 1D 3E 4F 30 4D 5A 4B 87 4C -49 54 45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 -C6 1D A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 48 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C 48 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC 44 16 4C 2E 49 -D2 4B 9C 26 3D 40 DA 4B DE 3E DC 4B 0A 4E 3E 4F -3D 40 F6 4B 36 27 3D 40 CC 4B 1A E2 BE 1D B6 27 -0E 12 3E 4F 30 41 F8 4B 3E 4F 3D 40 CC 4B BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 4D CC 3F 00 4C 86 12 20 00 E8 47 05 41 4C 4C -4F 54 82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 -31 40 E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 -90 47 BC 44 C6 4B C6 47 F8 47 14 44 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF -28 44 00 48 14 44 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A 45 3A 44 40 4C 1C 4C 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 48 0A 44 2A 45 5C 4B 62 48 -90 49 01 27 0D 12 84 12 16 4C 2E 49 96 49 34 44 -14 4C 62 48 00 00 83 5B 27 5D 0D 12 84 12 94 4C -0A 44 0A 44 5C 4B 5C 4B 62 48 A6 4C 81 5B 82 43 -BE 1D 30 4D 0E 48 01 5D B2 43 BE 1D 30 4D C6 4C -81 5C 92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 4C 2E 49 96 49 -AA 47 34 44 14 4C F8 47 34 44 08 4D 0A 44 0A 44 -5C 4B 5C 4B 0A 44 5C 4B 5C 4B 62 48 BC 4C 01 3A -30 12 58 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 -16 4C 2E 49 26 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D -2A 52 82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 -18 42 B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 45 0E 4D 81 3B 82 93 -BE 1D 97 27 0D 12 84 12 0A 44 62 48 5C 4B 6A 4D -BE 4C 62 48 BC 4B 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 1D F8 D0 80 00 00 00 30 4D A6 4B 06 43 -52 45 41 54 45 00 B0 12 14 4D BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE 4D 04 43 4F 44 45 00 B0 12 -14 4D A2 82 C6 1D 0D 12 84 12 06 50 E0 4F 62 48 -B6 4D 07 48 44 4E 43 4F 44 45 B2 40 E4 4F DA 1D -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A 4D 20 50 3E 50 62 48 00 00 05 43 4F 4C 4F 4E -1A 42 C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 1D B2 43 BE 1D 0D 12 84 12 20 50 3E 50 -62 48 00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 -C6 1D EB 3F 02 4E 85 48 49 32 4C 4F 0D 12 84 12 -28 44 AE 4F 5C 4B BE 4C F6 4D 62 48 9C 4D 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E 4E 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A 44 00 00 DA 47 16 4C -2E 49 AC 4B A2 47 34 44 16 4F B0 47 14 44 06 5B -54 48 45 4E 5D 00 88 4E F0 4E AC 4E CE 4E 62 48 -B0 47 14 44 06 5B 45 4C 53 45 5D 00 88 4E 06 4F -AC 4E CC 4E 62 48 14 44 04 5B 49 46 5D 00 88 4E -CE 4E 3A 44 CC 4E 84 47 14 44 05 0D 0A 6B 6F 20 -5E 47 BC 44 AC 44 3A 44 CE 4E BC 4E 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C 4F -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 4C -2E 49 96 49 3A 4F 62 48 40 4F 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A 4F F2 47 62 48 -72 4F B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E 4B 06 4D 41 52 4B 45 52 00 B0 12 14 4D BA 40 -85 12 FC FF BA 40 70 4F FE FF 28 83 8A 48 00 00 -BA 40 AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 -30 4D 0A 44 CA 1D EA 47 62 48 85 12 B2 4F 7A 4C -E8 4D 2E 47 92 4C 66 4E F8 46 82 4F 14 49 AA 50 -BE 50 9E 48 28 49 00 00 5A 4F D0 4C F6 49 00 00 -85 12 B2 4F 84 56 EA 56 2C 56 3A 57 F2 55 00 00 -BE 53 00 00 02 58 E6 57 56 56 94 56 CE 54 00 00 -00 00 56 57 DE 4F 3A 40 0C 00 39 40 D6 1D 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 -CA 1D DA 1D 30 4D BA 4F 38 50 3E 50 4E 50 1A 42 -20 18 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC 4C 09 50 57 52 5F 53 54 41 54 45 85 12 -46 50 0E 58 E2 48 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 50 F3 3F 84 50 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 1D 92 50 30 4D 96 50 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C 51 FE FF -29 83 B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 -22 46 B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 -E0 1C 3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C -FC 23 B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 -B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 -26 03 F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 -41 01 F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 -66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 -F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 1E 42 08 18 -82 43 08 18 1E D2 9E 01 B0 12 F8 44 20 46 38 40 -C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D -30 4D 1C 15 0E 12 12 12 C4 1D 84 12 2E 49 96 49 -F2 47 34 44 FE 51 52 4A 34 44 18 52 12 52 00 52 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 1A 52 B2 41 C4 1D 3E 41 -84 12 0A 44 2B 00 2E 49 96 49 F2 47 34 44 36 52 -52 4A 34 44 14 4C BC 47 2E 49 52 4A 34 44 14 4C -42 52 3E 5F E7 3F 3E 40 28 00 B0 12 E2 51 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 -C0 1D C4 1D 02 20 30 40 82 4D 1C 15 12 12 C4 1D -92 53 C4 1D 84 12 2E 49 52 4A 34 44 8A 52 80 52 -21 53 3E 90 10 00 C6 2B 7F 2D 8C 52 B2 41 C4 1D -C1 3F 0D 12 84 12 16 4C BE 51 9C 52 0C 43 1B 42 -C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 1D B0 12 E2 51 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 E2 51 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D -B0 12 6A 52 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -6A 52 92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 -0C 5E DA 3F B0 12 6A 52 FA 23 3C 50 10 00 B0 12 -46 52 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 -84 12 16 4C BE 51 68 53 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 6A 52 E0 23 -3C 50 80 00 B0 12 46 52 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 44 00 13 5C 4B 62 48 0A 44 -2C 00 92 52 5E 53 A8 53 09 4B 2E 4E 0E DC A2 3F -54 4E 03 4D 4F 56 85 12 9E 53 00 40 B2 53 05 4D -4F 56 2E 42 85 12 9E 53 40 40 00 00 03 41 44 44 -85 12 9E 53 00 50 CC 53 05 41 44 44 2E 42 85 12 -9E 53 40 50 D8 53 04 41 44 44 43 00 85 12 9E 53 -00 60 E6 53 06 41 44 44 43 2E 42 00 85 12 9E 53 -40 60 8C 53 04 53 55 42 43 00 85 12 9E 53 00 70 -04 54 06 53 55 42 43 2E 42 00 85 12 9E 53 40 70 -12 54 03 53 55 42 85 12 9E 53 00 80 22 54 05 53 -55 42 2E 42 85 12 9E 53 40 80 2A 4E 03 43 4D 50 -85 12 9E 53 00 90 3C 54 05 43 4D 50 2E 42 85 12 -9E 53 40 90 14 4E 04 44 41 44 44 00 85 12 9E 53 -00 A0 56 54 06 44 41 44 44 2E 42 00 85 12 9E 53 -40 A0 48 54 03 42 49 54 85 12 9E 53 00 B0 74 54 -05 42 49 54 2E 42 85 12 9E 53 40 B0 80 54 03 42 -49 43 85 12 9E 53 00 C0 8E 54 05 42 49 43 2E 42 -85 12 9E 53 40 C0 9A 54 03 42 49 53 85 12 9E 53 -00 D0 A8 54 05 42 49 53 2E 42 85 12 9E 53 40 D0 -00 00 03 58 4F 52 85 12 9E 53 00 E0 C2 54 05 58 -4F 52 2E 42 85 12 9E 53 40 E0 F4 53 03 41 4E 44 -85 12 9E 53 00 F0 DC 54 05 41 4E 44 2E 42 85 12 -9E 53 40 F0 16 4C 92 52 FA 54 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 2E 54 03 52 52 43 -85 12 F4 54 00 10 0C 55 05 52 52 43 2E 42 85 12 -F4 54 40 10 18 55 04 53 57 50 42 00 85 12 F4 54 -80 10 26 55 03 52 52 41 85 12 F4 54 00 11 34 55 -05 52 52 41 2E 42 85 12 F4 54 40 11 40 55 03 53 -58 54 85 12 F4 54 80 11 00 00 04 50 55 53 48 00 -85 12 F4 54 00 12 5A 55 06 50 55 53 48 2E 42 00 -85 12 F4 54 40 12 B4 54 04 43 41 4C 4C 00 85 12 -F4 54 80 12 1A 53 0E 4A 0D 12 84 12 D8 48 14 44 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 45 -4E 55 03 53 3E 3D 86 12 00 38 A2 55 02 53 3C 00 -86 12 00 34 68 55 03 30 3E 3D 86 12 00 30 B6 55 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C CA 55 03 55 3E 3D 86 12 00 28 C0 55 03 30 -3C 3E 86 12 00 24 DE 55 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 -C6 1D 0E 4A 30 4D D4 55 04 54 48 45 4E 00 1A 42 -C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 64 54 04 45 4C 53 -45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D -2F 83 8F 4A 00 00 E3 3F 78 55 05 42 45 47 49 4E -30 40 28 44 08 56 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D -30 4D E8 54 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 F6 55 -BC 47 62 48 AC 55 06 52 45 50 45 41 54 00 0D 12 -84 12 8A 56 0E 56 62 48 BA 56 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D -4A 56 03 42 57 31 85 12 B8 56 00 00 D2 56 03 42 -57 32 85 12 B8 56 00 00 DE 56 03 42 57 33 85 12 -B8 56 00 00 F6 56 3D 41 1A 42 C6 1D 28 4E B2 92 -C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 F4 56 00 00 -16 57 03 46 57 32 85 12 F4 56 00 00 22 57 03 46 -57 33 85 12 F4 56 00 00 2E 57 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 94 4C -F0 4B 62 48 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 16 4C BE 51 78 57 92 53 C4 1D 3E 40 2C 00 -84 12 2E 49 52 4A 34 44 14 4C 54 53 8E 57 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E A6 56 04 52 52 43 -4D 00 85 12 72 57 50 00 BC 57 04 52 52 41 4D 00 -85 12 72 57 50 01 CA 57 04 52 4C 41 4D 00 85 12 -72 57 50 02 D8 57 04 52 52 55 4D 00 85 12 72 57 -50 03 E8 55 05 50 55 53 48 4D 85 12 72 57 00 15 -F4 57 04 50 4F 50 4D 00 85 12 72 57 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -96 46 02 46 02 46 02 46 02 46 02 46 02 46 1C 51 -q diff --git a/binaries/MSP_EXP430FR5969_1MHz_115200.txt b/binaries/MSP_EXP430FR5969_1MHz_115200.txt new file mode 100644 index 0000000..cad4430 --- /dev/null +++ b/binaries/MSP_EXP430FR5969_1MHz_115200.txt @@ -0,0 +1,325 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 59 +C6 46 7E 45 84 45 54 45 36 47 24 57 DC 4F 96 4F +96 4F AC 46 6A 47 32 47 3C 1D E0 1C 8A 49 B6 44 +C4 44 A6 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +36 47 24 57 DC 4F 96 4F 96 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 FE 3C 0E 93 3E 4F +93 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AA 46 B2 49 +68 47 B2 49 30 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 50 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 36 47 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 44 B0 48 AC 44 52 45 78 47 1E 44 04 1B +5B 37 6D 00 9A 47 9A 47 1E 44 04 1B 5B 30 6D 00 +9A 47 E6 4C B0 12 7E 45 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 78 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 9A 47 FE 49 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 9A 47 0A 44 40 FF 32 44 +C6 48 CA 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 20 00 21 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 +B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 +26 03 F2 40 A5 00 61 01 82 43 62 01 82 43 66 01 +B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 +10 00 2A 03 F2 C0 40 00 A1 04 39 40 00 08 29 83 +89 43 00 1C FC 23 19 42 9E 01 1E 42 08 18 82 43 +08 18 3E F3 01 20 0E 49 B0 12 D0 44 86 45 00 00 +0C 41 43 43 45 50 54 00 30 40 AC 46 08 4E 2E 4F +08 5E 39 40 0D 00 3A 40 20 00 3B 40 0A 47 3C 40 +16 47 5D 15 9D 3E 21 52 3A 17 58 42 CC 05 48 9B +09 20 A2 B3 DC 05 FD 27 B2 40 13 00 CE 05 E2 D3 +23 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 +1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 +DC 05 FD 27 C2 48 CE 05 30 4D 0C 47 2D 83 92 B3 +DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 DC 05 FD 27 +58 42 CC 05 08 4C EB 3F 00 00 06 4B 45 59 30 40 +32 47 30 12 48 47 A2 B3 DC 05 FD 27 B2 40 11 00 +CE 05 E2 C3 23 02 30 41 2F 83 8F 4E 00 00 92 B3 +DC 05 FD 27 B0 12 D2 46 1E 42 CC 05 30 4D 00 00 +08 45 4D 49 54 00 30 40 6A 47 08 4E 3E 4F C7 3F +60 47 08 45 43 48 4F 00 B2 40 C2 48 04 47 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 04 47 +30 4D 00 00 08 54 59 50 45 00 0D 12 3D 40 AA 47 +29 4F 8F 4E 00 00 7E 49 DE 3F AC 47 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 73 22 F9 98 00 00 +70 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 67 22 9B 24 2A 47 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A 44 00 00 CA 48 BC 47 0E 4A C8 4C +B0 44 38 48 14 44 06 5B 54 48 45 4E 5D 00 C0 47 +16 48 DC 47 FA 47 14 44 06 5B 45 4C 53 45 5D 00 +C0 47 28 48 DC 47 F8 47 1E 44 04 5B 49 46 5D 00 +C0 47 FA 47 B2 44 F8 47 1E 44 05 0D 6B 6F 20 0A +9A 47 9A 44 84 44 B2 44 FA 47 E8 47 0D 5B 54 48 +45 4E 5D 00 30 4D 4C 48 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D 58 48 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 BC 47 0E 4A 76 4A 1A 4C 8A 49 +68 48 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 BC 47 0E 4A 76 4A 9A 48 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D A0 46 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D D8 45 05 53 22 00 82 43 C0 1D 0D 12 84 12 +0A 44 1E 44 78 4C 0A 44 22 00 0E 4A 0E 49 B2 40 +20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 +30 4D 82 47 05 2E 22 00 0D 12 84 12 F8 48 0A 44 +9A 47 78 4C 8A 49 00 00 04 3C 23 00 B2 40 B2 1D +B2 1D 30 4D F4 48 02 23 1B 42 BE 1D 2C 4F 2F 83 +B0 12 46 44 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A +00 00 30 4D 46 49 04 23 53 00 0D 12 84 12 48 49 +82 49 2D 83 09 DE 09 93 E1 23 3D 41 30 4D 76 49 +04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +90 49 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 72 47 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 3C 49 BC 47 AA 49 7A 49 +A6 48 B8 49 94 49 9A 47 8A 49 24 49 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 +C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D FC 49 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 1D 0C 4E 0E 43 1E 15 3D 40 80 4B 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +82 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 38 49 +03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 44 +BC 47 0E 4A B0 44 52 4D 76 4A 3C 4C 0A 4E 3E 4F +3D 40 56 4C 6D 27 3D 40 30 4C 1A E2 BC 1D 14 24 +0E 12 3E 4F 30 41 58 4C 3E 4F 3D 40 30 4C 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +2E 4E 2A 3C 20 4C 02 2C A2 53 C8 1D 1A 42 C8 1D +8A 4E FE FF 3E 4F 30 4D 76 4C 0F 4C 49 54 45 52 +41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 +C8 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 +00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D +B2 49 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D D8 48 0A 41 4C 4C 4F 54 82 5E +C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 44 +02 0D 0A 00 9A 47 94 44 2A 4C B8 48 E2 48 1E 44 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 45 32 44 +0A 44 40 FF EA 48 1E 44 09 46 52 41 4D 20 66 75 +6C 6C 08 45 B2 44 EE 4C D8 4C 0D 41 42 4F 52 54 +22 00 0D 12 84 12 F8 48 0A 44 08 45 78 4C 8A 49 +08 4A 02 27 0D 12 84 12 BC 47 0E 4A 76 4A B0 44 +54 4D 1C 49 60 4C 82 48 07 5B 27 5D 0D 12 84 12 +44 4D 0A 44 0A 44 78 4C 78 4C 8A 49 58 4D 03 5B +82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D +D0 48 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +BC 47 0E 4A 76 4A B0 44 54 4D E2 48 AC 44 AC 4D +0A 44 0A 44 78 4C 78 4C 0A 44 78 4C 78 4C 8A 49 +00 00 02 3A 30 12 02 4E 92 B3 C8 1D A2 63 C8 1D +0D 12 84 12 BC 47 0E 4A CA 4D 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 +B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 44 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 45 +6E 4D 03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 44 +8A 49 78 4C 14 4E 70 4D 8A 49 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D +C2 4C 0C 43 52 45 41 54 45 00 B0 12 B8 4D BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D 94 47 0A 44 4F 45 +53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D B2 4D 0E 3A 4E 4F 4E 41 4D 45 30 12 +02 4E 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F 4C 4E 05 49 53 00 +0D 12 82 93 BC 1D 08 20 84 12 44 4D CE 4E 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 5C 4D 0A 44 D0 4E +78 4C 8A 49 62 4E 08 43 4F 44 45 00 B0 12 B8 4D +A2 82 C8 1D 61 3C A4 49 0E 48 44 4E 43 4F 44 45 +B2 40 BC 4F CC 1D F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 14 4E 1A 4F 3D 41 92 42 D0 1D +CC 1D 5D 3C E6 4E 0E 43 4F 44 45 4E 4E 4D 30 12 +F0 4E B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D +B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 1D 1A 42 C8 1D EF 3F F8 4E 0B 48 49 32 4C 4F +A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D +B9 3F 84 4F B2 40 96 4F D0 1D 82 4E CE 1D 30 40 +1C 49 85 12 82 4F 82 4D 2A 4D 14 50 26 4F 7C 4E +C6 49 70 4A 42 4D 6A 4F BC 4E 96 4E 32 4E 8A 4C +9E 50 C8 4A 00 00 00 00 85 12 82 4F 18 57 9C 55 +FC 56 C4 54 20 55 6E 55 4A 56 56 56 E6 53 0A 55 +00 00 00 00 58 4F D6 52 00 00 72 56 B6 4F B2 40 +96 4F CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 EA 4F +30 4D FC 4F 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 1D B0 12 EA 4F 1A 42 CA 1D 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 08 46 FE FF 29 83 B9 40 F2 45 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 F0 FF 3B 40 10 00 +3A 40 3A 18 B0 12 EE 4F 82 43 4A 18 C7 3F 90 50 +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 78 4D 0C 4D +41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 BC 47 +0E 4A 76 4A AC 44 BC 50 B0 48 50 4C BE 50 3E 4F +3D 41 B2 41 C6 1D B0 12 B8 4D BA 40 85 12 FC FF +BA 40 8E 50 FE FF 28 83 8A 48 00 00 BA 40 82 44 +02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 0E 4A +76 4A AC 44 28 51 08 51 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 8E 50 00 00 01 20 +3E 52 2E 83 21 53 30 41 20 4B AC 44 30 51 24 51 +32 51 B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 +0A 4E 3D 15 B0 12 F8 50 15 20 3E 40 2B 00 B0 12 +F8 50 06 20 3E 40 2D 00 B0 12 F8 50 92 83 C6 1D +0E 12 1E 41 02 00 84 12 0E 4A 20 4B AC 44 54 4D +72 51 3E 51 3A 17 30 41 B0 12 38 51 19 42 C8 1D +89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D +1A 42 C6 1D 3D 15 84 12 0E 4A 20 4B AC 44 AA 51 +A2 51 3E 90 10 00 E6 2B 7C 2D AC 51 A2 41 C6 1D +E1 3F 03 20 B0 12 90 51 43 3C 7A 90 23 00 24 20 +B0 12 40 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 +2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 +3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 40 51 F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 8C 51 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 90 51 92 92 C2 1D C6 1D 02 24 92 53 C6 1D +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 78 51 F2 3F +03 20 B0 12 90 51 F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 78 51 EA 3F 0C 43 +1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D +19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D +82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A 44 00 13 78 4C 8A 49 0A 44 +2C 00 6E 52 B2 51 BC 47 78 52 50 52 BE 52 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +AE 52 00 40 CA 52 0A 4D 4F 56 2E 42 85 12 AE 52 +40 40 00 00 06 41 44 44 85 12 AE 52 00 50 E4 52 +0A 41 44 44 2E 42 85 12 AE 52 40 50 F0 52 08 41 +44 44 43 00 85 12 AE 52 00 60 FE 52 0C 41 44 44 +43 2E 42 00 85 12 AE 52 40 60 36 4F 08 53 55 42 +43 00 85 12 AE 52 00 70 1C 53 0C 53 55 42 43 2E +42 00 85 12 AE 52 40 70 2A 53 06 53 55 42 85 12 +AE 52 00 80 3A 53 0A 53 55 42 2E 42 85 12 AE 52 +40 80 46 53 06 43 4D 50 85 12 AE 52 00 90 54 53 +0A 43 4D 50 2E 42 85 12 AE 52 40 90 00 00 08 44 +41 44 44 00 85 12 AE 52 00 A0 6E 53 0C 44 41 44 +44 2E 42 00 85 12 AE 52 40 A0 9C 52 06 42 49 54 +85 12 AE 52 00 B0 8C 53 0A 42 49 54 2E 42 85 12 +AE 52 40 B0 98 53 06 42 49 43 85 12 AE 52 00 C0 +A6 53 0A 42 49 43 2E 42 85 12 AE 52 40 C0 B2 53 +06 42 49 53 85 12 AE 52 00 D0 C0 53 0A 42 49 53 +2E 42 85 12 AE 52 40 D0 00 00 06 58 4F 52 85 12 +AE 52 00 E0 DA 53 0A 58 4F 52 2E 42 85 12 AE 52 +40 E0 0C 53 06 41 4E 44 85 12 AE 52 00 F0 F4 53 +0A 41 4E 44 2E 42 85 12 AE 52 40 F0 BC 47 6E 52 +B2 51 14 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F CC 53 06 52 52 43 85 12 0C 54 00 10 +26 54 0A 52 52 43 2E 42 85 12 0C 54 40 10 60 53 +08 53 57 50 42 00 85 12 0C 54 80 10 32 54 06 52 +52 41 85 12 0C 54 00 11 4E 54 0A 52 52 41 2E 42 +85 12 0C 54 40 11 40 54 06 53 58 54 85 12 0C 54 +80 11 00 00 08 50 55 53 48 00 85 12 0C 54 00 12 +74 54 0C 50 55 53 48 2E 42 00 85 12 0C 54 40 12 +68 54 08 43 41 4C 4C 00 85 12 0C 54 80 12 1A 53 +0E 4A 84 12 FE 49 1E 44 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 45 92 54 06 53 3E 3D 86 12 +00 38 BA 54 04 53 3C 00 86 12 00 34 82 54 06 30 +3E 3D 86 12 00 30 CE 54 04 30 3C 00 86 12 00 30 +0A 4F 04 55 3C 00 86 12 00 2C E2 54 06 55 3E 3D +86 12 00 28 D8 54 06 30 3C 3E 86 12 00 24 F6 54 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D 7C 53 +08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D EC 54 08 45 4C 53 45 00 1A 42 C8 1D BA 40 +00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F +5A 54 0A 42 45 47 49 4E 30 40 32 44 44 55 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 1D 30 4D 00 54 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 0E 55 A4 48 8A 49 62 55 0C 52 +45 50 45 41 54 00 0D 12 84 12 A2 55 26 55 8A 49 +D2 55 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F +98 42 C8 1D 00 00 30 4D BE 55 06 42 57 31 85 12 +D0 55 00 00 EA 55 06 42 57 32 85 12 D0 55 00 00 +F6 55 06 42 57 33 85 12 D0 55 00 00 0E 56 3D 41 +1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B +BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 0C 56 00 00 32 56 06 46 +57 32 85 12 0C 56 00 00 3E 56 06 46 57 33 85 12 +0C 56 00 00 AC 55 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 44 4D 50 4C 8A 49 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F 78 52 +0A 44 2C 00 0E 4A 20 4B AC 44 54 4D BC 47 6E 52 +50 52 A4 56 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +02 56 08 52 52 43 4D 00 85 12 8E 56 50 00 D2 56 +08 52 52 41 4D 00 85 12 8E 56 50 01 E0 56 08 52 +4C 41 4D 00 85 12 8E 56 50 02 EE 56 08 52 52 55 +4D 00 85 12 8E 56 50 03 00 55 0A 50 55 53 48 4D +85 12 8E 56 00 15 0A 57 08 50 4F 50 4D 00 85 12 +8E 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +C6 46 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 08 46 +q diff --git a/binaries/MSP_EXP430FR5969_1MHz_I2C.txt b/binaries/MSP_EXP430FR5969_1MHz_I2C.txt index 34de458..5e8066a 100644 --- a/binaries/MSP_EXP430FR5969_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5969_1MHz_I2C.txt @@ -1,335 +1,322 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF E6 57 F2 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 84 46 E6 57 -F2 4F 72 46 82 47 00 47 DC 46 3C 1D 50 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +C0 46 56 45 56 45 58 45 44 45 00 57 B8 4F 72 4F +72 4F AE 46 32 47 0A 47 3C 1D E0 1C 66 49 B6 44 +C4 44 82 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 00 57 B8 4F 72 4F 72 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 70 46 B2 49 80 47 B2 49 FE 46 B2 49 DA 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D D0 47 18 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 98 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C 47 90 48 4C 47 -14 44 04 1B 5B 30 6D 00 4C 47 18 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 -B0 12 8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 -07 0D 0A 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 0A 44 23 00 FC 46 C6 48 14 44 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C 47 0A 44 40 FF 28 44 C4 47 -90 48 14 44 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 44 7E 45 00 00 06 41 43 43 45 50 54 00 30 40 -72 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 -B7 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 46 2F 83 8F 4E -00 00 58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 -4C 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 47 -08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D -F6 46 04 45 43 48 4F 00 B2 40 C2 48 0A 47 82 43 -DE 1D 38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 47 92 43 DE 1D -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE 46 6A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 -82 47 0D 12 84 12 14 44 02 0D 0A 00 4C 47 50 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 46 01 40 -2E 4E 30 4D CE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 7A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 0A 48 02 23 53 00 0D 12 -84 12 0C 48 46 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 48 3E 48 EE 44 7E 48 5A 48 4C 47 04 4C FC 46 -50 48 2E 47 01 2E 0E 93 E3 37 38 43 E2 3F 78 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -4A 4B 0A 44 22 00 1C 49 EA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -C4 48 82 2E 22 00 0D 12 84 12 D4 48 0A 44 4C 47 -4A 4B 50 48 FA 45 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9E 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 48 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 04 4C 1C 49 C0 4B -9C 26 3D 40 C8 4B DE 3E CA 4B 0A 4E 3E 4F 3D 40 -E4 4B 36 27 3D 40 BA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 E6 4B 3E 4F 3D 40 BA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 4D -CC 3F EE 4B 86 12 20 00 D6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7E 47 -BC 44 B4 4B B4 47 E6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -EE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 2E 4C 0A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 48 0A 44 2A 45 4A 4B 50 48 7E 49 -01 27 0D 12 84 12 04 4C 1C 49 84 49 34 44 02 4C -50 48 00 00 83 5B 27 5D 0D 12 84 12 82 4C 0A 44 -0A 44 4A 4B 4A 4B 50 48 94 4C 81 5B 82 43 BE 1D -30 4D FC 47 01 5D B2 43 BE 1D 30 4D B4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 4C 1C 49 84 49 98 47 -34 44 02 4C E6 47 34 44 F6 4C 0A 44 0A 44 4A 4B -4A 4B 0A 44 4A 4B 4A 4B 50 48 AA 4C 01 3A 30 12 -46 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 04 4C -1C 49 14 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 FC 4C 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 50 48 4A 4B 58 4D AC 4C -50 48 AA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 94 4B 06 43 52 45 -41 54 45 00 B0 12 02 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC 4D 04 43 4F 44 45 00 B0 12 02 4D -A2 82 C6 1D 0D 12 84 12 F4 4F CE 4F 50 48 A4 4D -07 48 44 4E 43 4F 44 45 B2 40 D2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 4D -0E 50 2C 50 50 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 0E 50 2C 50 50 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F F0 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 -9C 4F 4A 4B AC 4C E4 4D 50 48 8A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 C8 47 04 4C 1C 49 -9A 4B 90 47 34 44 04 4F 9E 47 14 44 06 5B 54 48 -45 4E 5D 00 76 4E DE 4E 9A 4E BC 4E 50 48 9E 47 -14 44 06 5B 45 4C 53 45 5D 00 76 4E F4 4E 9A 4E -BA 4E 50 48 14 44 04 5B 49 46 5D 00 76 4E BC 4E -3A 44 BA 4E 72 47 14 44 05 0D 0A 6B 6F 20 4C 47 -BC 44 AC 44 3A 44 BC 4E AA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 4C 1C 49 -84 49 28 4F 50 48 2E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 4F E0 47 50 48 60 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C 4B -06 4D 41 52 4B 45 52 00 B0 12 02 4D BA 40 85 12 -FC FF BA 40 5E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D D8 47 50 48 85 12 A0 4F 68 4C D6 4D -12 47 80 4C 54 4E D4 46 70 4F 02 49 98 50 AC 50 -8C 48 16 49 00 00 48 4F BE 4C E4 49 00 00 85 12 -A0 4F 5C 56 C2 56 04 56 12 57 CA 55 00 00 96 53 -00 00 DA 57 BE 57 2E 56 6C 56 A6 54 00 00 00 00 -2E 57 CC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D A8 4F 26 50 2C 50 3C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 34 50 -E6 57 D0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 50 F3 3F 72 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 80 50 30 4D 84 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A 51 FE FF 29 83 -B9 40 E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 45 B2 49 FA 44 B2 49 02 44 B2 49 02 46 -B2 49 EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 B2 40 -FF BF 22 02 F2 43 22 03 F2 D3 26 03 F2 40 A5 00 -61 01 82 43 62 01 82 43 66 01 B2 40 33 00 64 01 -D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 -19 83 FA 23 B2 D2 B0 01 F2 D0 10 00 2A 03 F2 C0 -40 00 A1 04 1E 42 08 18 82 43 08 18 1E D2 9E 01 -B0 12 F8 44 00 46 38 40 C0 1D 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 12 12 -C4 1D 84 12 1C 49 84 49 E0 47 34 44 D6 51 40 4A -34 44 F0 51 EA 51 D8 51 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -F2 51 B2 41 C4 1D 3E 41 84 12 0A 44 2B 00 1C 49 -84 49 E0 47 34 44 0E 52 40 4A 34 44 02 4C AA 47 -1C 49 40 4A 34 44 02 4C 1A 52 3E 5F E7 3F 3E 40 -28 00 B0 12 BA 51 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 30 40 -70 4D 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 1C 49 -40 4A 34 44 62 52 58 52 21 53 3E 90 10 00 C6 2B -7F 2D 64 52 B2 41 C4 1D C1 3F 0D 12 84 12 04 4C -96 51 74 52 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E -3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 BA 51 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 FF 3C 0E 93 3E 4F +81 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 AC 46 B2 49 +30 47 B2 49 08 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 2C 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 8C 48 AC 44 +42 45 4A 47 1E 44 05 1B 5B 37 6D 40 76 47 0A 44 +02 18 AE 48 DA 49 76 47 1E 44 04 1B 5B 30 6D 00 +76 47 C2 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 4A 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 76 47 0A 44 02 18 AE 48 DA 49 0A 44 23 00 +2E 47 DA 49 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +76 47 0A 44 40 FF 32 44 A2 48 A6 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +20 00 21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 40 FE FF 02 02 +B2 D3 06 02 B2 D3 26 02 B2 40 FF BF 22 02 F2 43 +22 03 F2 D3 26 03 F2 40 A5 00 61 01 82 43 62 01 +82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 +40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 B2 D2 +B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 39 40 +00 08 29 83 89 43 00 1C FC 23 1E 42 08 18 82 43 +08 18 3E F3 02 20 1E 42 9E 01 B0 12 D0 44 80 45 +00 00 0C 41 43 43 45 50 54 00 30 40 AE 46 0A 4E +2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 A0 3E +21 52 A2 C2 6C 06 B2 B0 10 00 40 06 99 22 3A 17 +92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 48 9C +06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A +EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C +00 00 06 4B 45 59 30 40 0A 47 58 43 B0 12 46 45 +2F 83 8F 4E 00 00 92 B3 6C 06 FD 27 1E 42 4C 06 +B0 12 44 45 30 4D 00 00 08 45 4D 49 54 00 30 40 +32 47 08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 +30 4D 28 47 08 45 43 48 4F 00 B2 40 C2 48 3C 47 +38 40 05 00 B0 12 46 45 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 3C 47 28 42 F3 3F 00 00 +08 54 59 50 45 00 0D 12 3D 40 86 47 29 4F 8F 4E +00 00 7E 49 D4 3F 88 47 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 85 22 F9 98 00 00 82 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 79 22 +9B 24 02 47 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A 44 00 00 A6 48 98 47 EA 49 A4 4C B0 44 14 48 +14 44 06 5B 54 48 45 4E 5D 00 9C 47 F2 47 B8 47 +D6 47 14 44 06 5B 45 4C 53 45 5D 00 9C 47 04 48 +B8 47 D4 47 1E 44 04 5B 49 46 5D 00 9C 47 D6 47 +B2 44 D4 47 1E 44 05 0D 6B 6F 20 0A 76 47 9A 44 +84 44 B2 44 D6 47 C4 47 0D 5B 54 48 45 4E 5D 00 +30 4D 28 48 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 34 48 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 98 47 EA 49 52 4A F6 4B 66 49 44 48 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 98 47 +EA 49 52 4A 76 48 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D A2 46 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D E0 45 +05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 44 1E 44 +54 4C 0A 44 22 00 EA 49 EA 48 B2 40 20 00 C0 1D +1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 5C 47 +05 2E 22 00 0D 12 84 12 D4 48 0A 44 76 47 54 4C +66 49 00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D +D0 48 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 44 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D +22 49 04 23 53 00 0D 12 84 12 24 49 5E 49 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 52 49 04 23 3E 00 +9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 6C 49 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +44 47 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 18 49 98 47 86 49 56 49 82 48 94 49 +70 49 76 47 66 49 00 49 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 +C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D D8 49 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E +0E 43 1E 15 3D 40 5C 4B 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 5E 4B 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E +09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 44 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 14 49 03 5C 92 42 +C2 1D C6 1D 30 4D 0D 12 84 12 84 44 98 47 EA 49 +B0 44 2E 4D 52 4A 18 4C 0A 4E 3E 4F 3D 40 32 4C +6D 27 3D 40 0C 4C 1A E2 BC 1D 14 24 0E 12 3E 4F +30 41 34 4C 3E 4F 3D 40 0C 4C 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 0A 4E 2A 3C +FC 4B 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF +3E 4F 30 4D 52 4C 0F 4C 49 54 45 52 41 4C 82 93 +BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 +0A 44 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D 8E 49 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D B4 48 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F +30 4D 3F 40 80 1C 0E 43 84 12 1E 44 02 0D 0A 00 +76 47 94 44 06 4C 94 48 BE 48 1E 44 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 45 32 44 0A 44 40 FF +C6 48 1E 44 09 46 52 41 4D 20 66 75 6C 6C 08 45 +B2 44 CA 4C B4 4C 0D 41 42 4F 52 54 22 00 0D 12 +84 12 D4 48 0A 44 08 45 54 4C 66 49 E4 49 02 27 +0D 12 84 12 98 47 EA 49 52 4A B0 44 30 4D F8 48 +3C 4C 5E 48 07 5B 27 5D 0D 12 84 12 20 4D 0A 44 +0A 44 54 4C 54 4C 66 49 34 4D 03 5B 82 43 BC 1D +30 4D 00 00 02 5D B2 43 BC 1D 30 4D AC 48 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 98 47 EA 49 +52 4A B0 44 30 4D BE 48 AC 44 88 4D 0A 44 0A 44 +54 4C 54 4C 0A 44 54 4C 54 4C 66 49 00 00 02 3A +30 12 DE 4D 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 +98 47 EA 49 A6 4D 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A +B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D +82 9F BA 1D 66 25 84 12 1E 44 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 45 4A 4D 03 3B +82 93 BC 1D F4 26 0D 12 84 12 0A 44 66 49 54 4C +F0 4D 4C 4D 66 49 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 1D D8 D3 00 00 30 4D 9E 4C 0C 43 +52 45 41 54 45 00 B0 12 94 4D BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 70 47 0A 44 4F 45 53 3E 1A 42 +B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +8E 4D 0E 3A 4E 4F 4E 41 4D 45 30 12 DE 4D 2F 83 +8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 28 4E 05 49 53 00 0D 12 82 93 +BC 1D 08 20 84 12 20 4D AA 4E 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 38 4D 0A 44 AC 4E 54 4C 66 49 +3E 4E 08 43 4F 44 45 00 B0 12 94 4D A2 82 C8 1D +61 3C 80 49 0E 48 44 4E 43 4F 44 45 B2 40 98 4F +CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 F0 4D F6 4E 3D 41 92 42 D0 1D CC 1D 5D 3C +C2 4E 0E 43 4F 44 45 4E 4E 4D 30 12 CC 4E B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 +C8 1D EF 3F D4 4E 0B 48 49 32 4C 4F A2 53 C8 1D +1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 60 4F +B2 40 72 4F D0 1D 82 4E CE 1D 30 40 F8 48 85 12 +5E 4F 5E 4D 06 4D F0 4F 02 4F 58 4E A2 49 4C 4A +1E 4D 46 4F 98 4E 72 4E 0E 4E 66 4C 7A 50 A4 4A +00 00 00 00 85 12 5E 4F F4 56 78 55 D8 56 A0 54 +FC 54 4A 55 26 56 32 56 C2 53 E6 54 00 00 00 00 +34 4F B2 52 00 00 4E 56 92 4F B2 40 72 4F CE 1D +82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 1D 3A 40 42 18 B0 12 C6 4F 30 4D D8 4F +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 1D B0 12 C6 4F 1A 42 CA 1D 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 10 46 +FE FF 29 83 B9 40 FA 45 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 EE FF 3B 40 10 00 3A 40 3A 18 +B0 12 CA 4F 82 43 4A 18 C7 3F 6C 50 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 54 4D 0C 4D 41 52 4B 45 +52 00 12 12 C6 1D 0D 12 84 12 98 47 EA 49 52 4A +AC 44 98 50 8C 48 2C 4C 9A 50 3E 4F 3D 41 B2 41 +C6 1D B0 12 94 4D BA 40 85 12 FC FF BA 40 6A 50 +FE FF 28 83 8A 48 00 00 BA 40 82 44 02 00 A2 52 +C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 1D 84 12 EA 49 52 4A AC 44 +04 51 E4 50 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 6A 50 00 00 01 20 3E 52 2E 83 +21 53 30 41 FC 4A AC 44 0C 51 00 51 0E 51 B2 41 +C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 +B0 12 D4 50 15 20 3E 40 2B 00 B0 12 D4 50 06 20 +3E 40 2D 00 B0 12 D4 50 92 83 C6 1D 0E 12 1E 41 +02 00 84 12 EA 49 FC 4A AC 44 30 4D 4E 51 3E 51 +3A 17 30 41 B0 12 14 51 19 42 C8 1D 89 4E 00 00 +A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D +3D 15 84 12 EA 49 FC 4A AC 44 86 51 7E 51 3E 90 +10 00 E6 2B 7C 2D 88 51 A2 41 C6 1D E1 3F 03 20 +B0 12 6C 51 43 3C 7A 90 23 00 24 20 B0 12 1C 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 -3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 -3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 -92 53 C4 1D B0 12 BA 51 ED 3F 7A 90 40 00 16 20 -3C 40 20 00 92 53 C4 1D B0 12 42 52 0C 20 3C 50 -10 00 3E 40 2B 00 B0 12 42 52 92 92 C0 1D C4 1D -02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 42 52 -FA 23 3C 50 10 00 B0 12 1E 52 EF 3F 0C 43 1B 42 -C6 1D A2 53 C6 1D 0D 12 84 12 04 4C 96 51 40 53 -FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 -C7 3F B0 12 42 52 E0 23 3C 50 80 00 B0 12 1E 52 -DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 0A 44 -00 13 4A 4B 50 48 0A 44 2C 00 6A 52 36 53 80 53 -09 4B 2E 4E 0E DC A2 3F 42 4E 03 4D 4F 56 85 12 -76 53 00 40 8A 53 05 4D 4F 56 2E 42 85 12 76 53 -40 40 00 00 03 41 44 44 85 12 76 53 00 50 A4 53 -05 41 44 44 2E 42 85 12 76 53 40 50 B0 53 04 41 -44 44 43 00 85 12 76 53 00 60 BE 53 06 41 44 44 -43 2E 42 00 85 12 76 53 40 60 64 53 04 53 55 42 -43 00 85 12 76 53 00 70 DC 53 06 53 55 42 43 2E -42 00 85 12 76 53 40 70 EA 53 03 53 55 42 85 12 -76 53 00 80 FA 53 05 53 55 42 2E 42 85 12 76 53 -40 80 18 4E 03 43 4D 50 85 12 76 53 00 90 14 54 -05 43 4D 50 2E 42 85 12 76 53 40 90 02 4E 04 44 -41 44 44 00 85 12 76 53 00 A0 2E 54 06 44 41 44 -44 2E 42 00 85 12 76 53 40 A0 20 54 03 42 49 54 -85 12 76 53 00 B0 4C 54 05 42 49 54 2E 42 85 12 -76 53 40 B0 58 54 03 42 49 43 85 12 76 53 00 C0 -66 54 05 42 49 43 2E 42 85 12 76 53 40 C0 72 54 -03 42 49 53 85 12 76 53 00 D0 80 54 05 42 49 53 -2E 42 85 12 76 53 40 D0 00 00 03 58 4F 52 85 12 -76 53 00 E0 9A 54 05 58 4F 52 2E 42 85 12 76 53 -40 E0 CC 53 03 41 4E 44 85 12 76 53 00 F0 B4 54 -05 41 4E 44 2E 42 85 12 76 53 40 F0 04 4C 6A 52 -D2 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA -4F 3F 06 54 03 52 52 43 85 12 CC 54 00 10 E4 54 -05 52 52 43 2E 42 85 12 CC 54 40 10 F0 54 04 53 -57 50 42 00 85 12 CC 54 80 10 FE 54 03 52 52 41 -85 12 CC 54 00 11 0C 55 05 52 52 41 2E 42 85 12 -CC 54 40 11 18 55 03 53 58 54 85 12 CC 54 80 11 -00 00 04 50 55 53 48 00 85 12 CC 54 00 12 32 55 -06 50 55 53 48 2E 42 00 85 12 CC 54 40 12 8C 54 -04 43 41 4C 4C 00 85 12 CC 54 80 12 1A 53 0E 4A -0D 12 84 12 C6 48 14 44 0D 6F 75 74 20 6F 66 20 -62 6F 75 6E 64 73 36 45 26 55 03 53 3E 3D 86 12 -00 38 7A 55 02 53 3C 00 86 12 00 34 40 55 03 30 -3E 3D 86 12 00 30 8E 55 02 30 3C 00 86 12 00 30 -00 00 02 55 3C 00 86 12 00 2C A2 55 03 55 3E 3D -86 12 00 28 98 55 03 30 3C 3E 86 12 00 24 B6 55 -02 30 3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 -C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D AC 55 -04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 -29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 -30 4D 3C 54 04 45 4C 53 45 00 1A 42 C6 1D BA 40 -00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F -50 55 05 42 45 47 49 4E 30 40 28 44 E0 55 05 55 -4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 -0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA -89 48 00 00 A2 53 C6 1D 30 4D C0 54 05 41 47 41 -49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 -4C 45 0D 12 84 12 CE 55 AA 47 50 48 84 55 06 52 -45 50 45 41 54 00 0D 12 84 12 62 56 E6 55 50 48 -92 56 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F -98 42 C6 1D 00 00 30 4D 22 56 03 42 57 31 85 12 -90 56 00 00 AA 56 03 42 57 32 85 12 90 56 00 00 -B6 56 03 42 57 33 85 12 90 56 00 00 CE 56 3D 41 -1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F 00 00 -A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 -57 31 85 12 CC 56 00 00 EE 56 03 46 57 32 85 12 -CC 56 00 00 FA 56 03 46 57 33 85 12 CC 56 00 00 -06 57 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 -00 3C 0D 12 84 12 82 4C DE 4B 50 48 00 00 05 3F +3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +1C 51 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +68 51 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 6C 51 +92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 54 51 F2 3F 03 20 B0 12 +6C 51 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 54 51 EA 3F 0C 43 1B 42 C8 1D +A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D +7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A 44 00 13 54 4C 66 49 0A 44 2C 00 4A 52 +8E 51 98 47 54 52 2C 52 9A 52 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 8A 52 00 40 +A6 52 0A 4D 4F 56 2E 42 85 12 8A 52 40 40 00 00 +06 41 44 44 85 12 8A 52 00 50 C0 52 0A 41 44 44 +2E 42 85 12 8A 52 40 50 CC 52 08 41 44 44 43 00 +85 12 8A 52 00 60 DA 52 0C 41 44 44 43 2E 42 00 +85 12 8A 52 40 60 12 4F 08 53 55 42 43 00 85 12 +8A 52 00 70 F8 52 0C 53 55 42 43 2E 42 00 85 12 +8A 52 40 70 06 53 06 53 55 42 85 12 8A 52 00 80 +16 53 0A 53 55 42 2E 42 85 12 8A 52 40 80 22 53 +06 43 4D 50 85 12 8A 52 00 90 30 53 0A 43 4D 50 +2E 42 85 12 8A 52 40 90 00 00 08 44 41 44 44 00 +85 12 8A 52 00 A0 4A 53 0C 44 41 44 44 2E 42 00 +85 12 8A 52 40 A0 78 52 06 42 49 54 85 12 8A 52 +00 B0 68 53 0A 42 49 54 2E 42 85 12 8A 52 40 B0 +74 53 06 42 49 43 85 12 8A 52 00 C0 82 53 0A 42 +49 43 2E 42 85 12 8A 52 40 C0 8E 53 06 42 49 53 +85 12 8A 52 00 D0 9C 53 0A 42 49 53 2E 42 85 12 +8A 52 40 D0 00 00 06 58 4F 52 85 12 8A 52 00 E0 +B6 53 0A 58 4F 52 2E 42 85 12 8A 52 40 E0 E8 52 +06 41 4E 44 85 12 8A 52 00 F0 D0 53 0A 41 4E 44 +2E 42 85 12 8A 52 40 F0 98 47 4A 52 8E 51 F0 53 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +A8 53 06 52 52 43 85 12 E8 53 00 10 02 54 0A 52 +52 43 2E 42 85 12 E8 53 40 10 3C 53 08 53 57 50 +42 00 85 12 E8 53 80 10 0E 54 06 52 52 41 85 12 +E8 53 00 11 2A 54 0A 52 52 41 2E 42 85 12 E8 53 +40 11 1C 54 06 53 58 54 85 12 E8 53 80 11 00 00 +08 50 55 53 48 00 85 12 E8 53 00 12 50 54 0C 50 +55 53 48 2E 42 00 85 12 E8 53 40 12 44 54 08 43 +41 4C 4C 00 85 12 E8 53 80 12 1A 53 0E 4A 84 12 +DA 49 1E 44 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 45 6E 54 06 53 3E 3D 86 12 00 38 96 54 +04 53 3C 00 86 12 00 34 5E 54 06 30 3E 3D 86 12 +00 30 AA 54 04 30 3C 00 86 12 00 30 E6 4E 04 55 +3C 00 86 12 00 2C BE 54 06 55 3E 3D 86 12 00 28 +B4 54 06 30 3C 3E 86 12 00 24 D2 54 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E +00 00 A2 53 C8 1D 0E 4A 30 4D 58 53 08 54 48 45 +4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D C8 54 +08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 +A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F 36 54 0A 42 +45 47 49 4E 30 40 32 44 20 55 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 1D 30 4D DC 53 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 EA 54 80 48 66 49 3E 55 0C 52 45 50 45 41 +54 00 0D 12 84 12 7E 55 02 55 66 49 AE 55 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D +00 00 30 4D 9A 55 06 42 57 31 85 12 AC 55 00 00 +C6 55 06 42 57 32 85 12 AC 55 00 00 D2 55 06 42 +57 33 85 12 AC 55 00 00 EA 55 3D 41 1A 42 C8 1D +28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 +A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 E8 55 00 00 0E 56 06 46 57 32 85 12 +E8 55 00 00 1A 56 06 46 57 33 85 12 E8 55 00 00 +88 55 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 20 4D 2C 4C 66 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 -00 10 EF 27 3E E0 00 08 EC 3F 04 4C 96 51 50 57 -92 53 C4 1D 3E 40 2C 00 84 12 1C 49 40 4A 34 44 -02 4C 2C 53 66 57 0A 4E 3E 4F 1A 83 F7 32 29 4E -59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 -10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 -A6 3E 7E 56 04 52 52 43 4D 00 85 12 4A 57 50 00 -94 57 04 52 52 41 4D 00 85 12 4A 57 50 01 A2 57 -04 52 4C 41 4D 00 85 12 4A 57 50 02 B0 57 04 52 -52 55 4D 00 85 12 4A 57 50 03 C0 55 05 50 55 53 -48 4D 85 12 4A 57 00 15 CC 57 04 50 4F 50 4D 00 -85 12 4A 57 00 17 +00 10 EF 27 3E E0 00 08 EC 3F 54 52 0A 44 2C 00 +EA 49 FC 4A AC 44 30 4D 98 47 4A 52 2C 52 80 56 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E DE 55 08 52 +52 43 4D 00 85 12 6A 56 50 00 AE 56 08 52 52 41 +4D 00 85 12 6A 56 50 01 BC 56 08 52 4C 41 4D 00 +85 12 6A 56 50 02 CA 56 08 52 52 55 4D 00 85 12 +6A 56 50 03 DC 54 0A 50 55 53 48 4D 85 12 6A 56 +00 15 E6 56 08 50 4F 50 4D 00 85 12 6A 56 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 84 46 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 0A 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 C0 46 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 10 46 q diff --git a/binaries/MSP_EXP430FR5969_1MHz_UART.txt b/binaries/MSP_EXP430FR5969_1MHz_UART.txt deleted file mode 100644 index ed3d074..0000000 --- a/binaries/MSP_EXP430FR5969_1MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF FC 57 04 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 96 46 FC 57 -04 50 7C 46 94 47 26 47 00 47 3C 1D 62 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 7A 46 B2 49 92 47 B2 49 24 47 B2 49 FE 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 D0 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E2 47 34 47 -14 44 04 1B 5B 37 6D 00 5E 47 AA 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E 47 A2 48 5E 47 14 44 04 1B 5B 30 6D 00 -5E 47 2A 4C 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D3 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C3 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 -B0 12 9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 -5E 47 D8 48 14 44 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E 47 0A 44 40 FF 28 44 D6 47 A2 48 14 44 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 44 86 45 00 00 -06 41 43 43 45 50 54 00 30 40 7C 46 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 46 3C 40 -D4 46 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 46 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 47 -2F 83 8F 4E 00 00 B0 12 DA 45 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 47 08 4E 3E 4F C8 3F 1C 47 04 45 -43 48 4F 00 B2 40 C2 48 C2 46 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 46 -92 43 DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A 47 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 47 7C 47 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 -30 40 94 47 0D 12 84 12 14 44 02 0D 0A 00 5E 47 -62 48 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 46 -01 40 2E 4E 30 4D E0 47 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 1D B2 1D 30 4D 8C 47 01 23 1B 42 -DC 1D 2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D -18 42 B2 1D C8 4A 00 00 30 4D 1C 48 02 23 53 00 -0D 12 84 12 1E 48 58 48 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C 48 02 23 3E 00 9F 42 B2 1D -00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 47 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 48 50 48 EE 44 90 48 6C 48 5E 47 16 4C -22 47 62 48 42 47 01 2E 0E 93 E3 37 38 43 E2 3F -8A 48 82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 -14 44 5C 4B 0A 44 22 00 2E 49 FC 48 B2 40 20 00 -B4 1D 6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 -30 4D D6 48 82 2E 22 00 0D 12 84 12 E6 48 0A 44 -5E 47 5C 4B 62 48 1A 46 04 57 4F 52 44 00 3C 40 -C0 1D 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A -C4 1D 1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 -D4 44 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 -B0 4A 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 4A 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D -8A 4E 00 00 A2 53 C6 1D 3E 4F 30 4D 5A 4B 87 4C -49 54 45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 -C6 1D A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 48 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C 48 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC 44 16 4C 2E 49 -D2 4B 9C 26 3D 40 DA 4B DE 3E DC 4B 0A 4E 3E 4F -3D 40 F6 4B 36 27 3D 40 CC 4B 1A E2 BE 1D B6 27 -0E 12 3E 4F 30 41 F8 4B 3E 4F 3D 40 CC 4B BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 4D CC 3F 00 4C 86 12 20 00 E8 47 05 41 4C 4C -4F 54 82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 -31 40 E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 -90 47 BC 44 C6 4B C6 47 F8 47 14 44 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF -28 44 00 48 14 44 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A 45 3A 44 40 4C 1C 4C 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 48 0A 44 2A 45 5C 4B 62 48 -90 49 01 27 0D 12 84 12 16 4C 2E 49 96 49 34 44 -14 4C 62 48 00 00 83 5B 27 5D 0D 12 84 12 94 4C -0A 44 0A 44 5C 4B 5C 4B 62 48 A6 4C 81 5B 82 43 -BE 1D 30 4D 0E 48 01 5D B2 43 BE 1D 30 4D C6 4C -81 5C 92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 4C 2E 49 96 49 -AA 47 34 44 14 4C F8 47 34 44 08 4D 0A 44 0A 44 -5C 4B 5C 4B 0A 44 5C 4B 5C 4B 62 48 BC 4C 01 3A -30 12 58 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 -16 4C 2E 49 26 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D -2A 52 82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 -18 42 B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 45 0E 4D 81 3B 82 93 -BE 1D 97 27 0D 12 84 12 0A 44 62 48 5C 4B 6A 4D -BE 4C 62 48 BC 4B 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 1D F8 D0 80 00 00 00 30 4D A6 4B 06 43 -52 45 41 54 45 00 B0 12 14 4D BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE 4D 04 43 4F 44 45 00 B0 12 -14 4D A2 82 C6 1D 0D 12 84 12 06 50 E0 4F 62 48 -B6 4D 07 48 44 4E 43 4F 44 45 B2 40 E4 4F DA 1D -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A 4D 20 50 3E 50 62 48 00 00 05 43 4F 4C 4F 4E -1A 42 C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 1D B2 43 BE 1D 0D 12 84 12 20 50 3E 50 -62 48 00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 -C6 1D EB 3F 02 4E 85 48 49 32 4C 4F 0D 12 84 12 -28 44 AE 4F 5C 4B BE 4C F6 4D 62 48 9C 4D 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E 4E 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A 44 00 00 DA 47 16 4C -2E 49 AC 4B A2 47 34 44 16 4F B0 47 14 44 06 5B -54 48 45 4E 5D 00 88 4E F0 4E AC 4E CE 4E 62 48 -B0 47 14 44 06 5B 45 4C 53 45 5D 00 88 4E 06 4F -AC 4E CC 4E 62 48 14 44 04 5B 49 46 5D 00 88 4E -CE 4E 3A 44 CC 4E 84 47 14 44 05 0D 0A 6B 6F 20 -5E 47 BC 44 AC 44 3A 44 CE 4E BC 4E 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C 4F -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 4C -2E 49 96 49 3A 4F 62 48 40 4F 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A 4F F2 47 62 48 -72 4F B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E 4B 06 4D 41 52 4B 45 52 00 B0 12 14 4D BA 40 -85 12 FC FF BA 40 70 4F FE FF 28 83 8A 48 00 00 -BA 40 AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 -30 4D 0A 44 CA 1D EA 47 62 48 85 12 B2 4F 7A 4C -E8 4D 2E 47 92 4C 66 4E F8 46 82 4F 14 49 AA 50 -BE 50 9E 48 28 49 00 00 5A 4F D0 4C F6 49 00 00 -85 12 B2 4F 72 56 D8 56 1A 56 28 57 E0 55 00 00 -AC 53 00 00 F0 57 D4 57 44 56 82 56 BC 54 00 00 -00 00 44 57 DE 4F 3A 40 0C 00 39 40 D6 1D 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 -CA 1D DA 1D 30 4D BA 4F 38 50 3E 50 4E 50 1A 42 -20 18 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC 4C 09 50 57 52 5F 53 54 41 54 45 85 12 -46 50 FC 57 E2 48 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 50 F3 3F 84 50 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 1D 92 50 30 4D 96 50 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C 51 FE FF -29 83 B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 -22 46 B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 -E0 1C 3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C -FC 23 B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 -B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 -26 03 F2 40 A5 00 61 01 82 43 62 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 -10 00 2A 03 F2 C0 40 00 A1 04 1E 42 08 18 82 43 -08 18 1E D2 9E 01 B0 12 F8 44 20 46 38 40 C0 1D -0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D -1C 15 0E 12 12 12 C4 1D 84 12 2E 49 96 49 F2 47 -34 44 EC 51 52 4A 34 44 06 52 00 52 EE 51 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 08 52 B2 41 C4 1D 3E 41 84 12 -0A 44 2B 00 2E 49 96 49 F2 47 34 44 24 52 52 4A -34 44 14 4C BC 47 2E 49 52 4A 34 44 14 4C 30 52 -3E 5F E7 3F 3E 40 28 00 B0 12 D0 51 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 C0 1D -C4 1D 02 20 30 40 82 4D 1C 15 12 12 C4 1D 92 53 -C4 1D 84 12 2E 49 52 4A 34 44 78 52 6E 52 21 53 -3E 90 10 00 C6 2B 7F 2D 7A 52 B2 41 C4 1D C1 3F -0D 12 84 12 16 4C AC 51 8A 52 0C 43 1B 42 C6 1D -A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 -C4 1D B0 12 D0 51 3C 40 00 03 0E 93 1C 24 3C 40 -10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 -20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 -30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 -C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 -07 20 3C 40 10 02 92 53 C4 1D B0 12 D0 51 ED 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D B0 12 -58 52 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 58 52 -92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E -DA 3F B0 12 58 52 FA 23 3C 50 10 00 B0 12 34 52 -EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 -16 4C AC 51 56 53 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C7 3F B0 12 58 52 E0 23 3C 50 -80 00 B0 12 34 52 DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A 44 00 13 5C 4B 62 48 0A 44 2C 00 -80 52 4C 53 96 53 09 4B 2E 4E 0E DC A2 3F 54 4E -03 4D 4F 56 85 12 8C 53 00 40 A0 53 05 4D 4F 56 -2E 42 85 12 8C 53 40 40 00 00 03 41 44 44 85 12 -8C 53 00 50 BA 53 05 41 44 44 2E 42 85 12 8C 53 -40 50 C6 53 04 41 44 44 43 00 85 12 8C 53 00 60 -D4 53 06 41 44 44 43 2E 42 00 85 12 8C 53 40 60 -7A 53 04 53 55 42 43 00 85 12 8C 53 00 70 F2 53 -06 53 55 42 43 2E 42 00 85 12 8C 53 40 70 00 54 -03 53 55 42 85 12 8C 53 00 80 10 54 05 53 55 42 -2E 42 85 12 8C 53 40 80 2A 4E 03 43 4D 50 85 12 -8C 53 00 90 2A 54 05 43 4D 50 2E 42 85 12 8C 53 -40 90 14 4E 04 44 41 44 44 00 85 12 8C 53 00 A0 -44 54 06 44 41 44 44 2E 42 00 85 12 8C 53 40 A0 -36 54 03 42 49 54 85 12 8C 53 00 B0 62 54 05 42 -49 54 2E 42 85 12 8C 53 40 B0 6E 54 03 42 49 43 -85 12 8C 53 00 C0 7C 54 05 42 49 43 2E 42 85 12 -8C 53 40 C0 88 54 03 42 49 53 85 12 8C 53 00 D0 -96 54 05 42 49 53 2E 42 85 12 8C 53 40 D0 00 00 -03 58 4F 52 85 12 8C 53 00 E0 B0 54 05 58 4F 52 -2E 42 85 12 8C 53 40 E0 E2 53 03 41 4E 44 85 12 -8C 53 00 F0 CA 54 05 41 4E 44 2E 42 85 12 8C 53 -40 F0 16 4C 80 52 E8 54 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F 1C 54 03 52 52 43 85 12 -E2 54 00 10 FA 54 05 52 52 43 2E 42 85 12 E2 54 -40 10 06 55 04 53 57 50 42 00 85 12 E2 54 80 10 -14 55 03 52 52 41 85 12 E2 54 00 11 22 55 05 52 -52 41 2E 42 85 12 E2 54 40 11 2E 55 03 53 58 54 -85 12 E2 54 80 11 00 00 04 50 55 53 48 00 85 12 -E2 54 00 12 48 55 06 50 55 53 48 2E 42 00 85 12 -E2 54 40 12 A2 54 04 43 41 4C 4C 00 85 12 E2 54 -80 12 1A 53 0E 4A 0D 12 84 12 D8 48 14 44 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 45 3C 55 -03 53 3E 3D 86 12 00 38 90 55 02 53 3C 00 86 12 -00 34 56 55 03 30 3E 3D 86 12 00 30 A4 55 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -B8 55 03 55 3E 3D 86 12 00 28 AE 55 03 30 3C 3E -86 12 00 24 CC 55 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D -0E 4A 30 4D C2 55 04 54 48 45 4E 00 1A 42 C6 1D -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D 52 54 04 45 4C 53 45 00 -1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 -8F 4A 00 00 E3 3F 66 55 05 42 45 47 49 4E 30 40 -28 44 F6 55 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D 30 4D -D6 54 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 E4 55 BC 47 -62 48 9A 55 06 52 45 50 45 41 54 00 0D 12 84 12 -78 56 FC 55 62 48 A8 56 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D 38 56 -03 42 57 31 85 12 A6 56 00 00 C0 56 03 42 57 32 -85 12 A6 56 00 00 CC 56 03 42 57 33 85 12 A6 56 -00 00 E4 56 3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D -88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 E2 56 00 00 04 57 -03 46 57 32 85 12 E2 56 00 00 10 57 03 46 57 33 -85 12 E2 56 00 00 1C 57 04 47 4F 54 4F 00 2F 83 -8F 4E 00 00 3E 40 00 3C 0D 12 84 12 94 4C F0 4B -62 48 00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 -3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F -16 4C AC 51 66 57 92 53 C4 1D 3E 40 2C 00 84 12 -2E 49 52 4A 34 44 14 4C 42 53 7C 57 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 94 56 04 52 52 43 4D 00 -85 12 60 57 50 00 AA 57 04 52 52 41 4D 00 85 12 -60 57 50 01 B8 57 04 52 4C 41 4D 00 85 12 60 57 -50 02 C6 57 04 52 52 55 4D 00 85 12 60 57 50 03 -D6 55 05 50 55 53 48 4D 85 12 60 57 00 15 E2 57 -04 50 4F 50 4D 00 85 12 60 57 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -96 46 02 46 02 46 02 46 02 46 02 46 02 46 1C 51 -q diff --git a/binaries/MSP_EXP430FR5969_8MHz_115200.txt b/binaries/MSP_EXP430FR5969_8MHz_115200.txt new file mode 100644 index 0000000..67502d6 --- /dev/null +++ b/binaries/MSP_EXP430FR5969_8MHz_115200.txt @@ -0,0 +1,324 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 59 +C2 46 7E 45 84 45 54 45 32 47 20 57 D8 4F 92 4F +92 4F A8 46 66 47 2E 47 3C 1D E0 1C 86 49 B6 44 +C4 44 A2 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +32 47 20 57 D8 4F 92 4F 92 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 FC 3C 0E 93 3E 4F +91 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A6 46 B2 49 +64 47 B2 49 2C 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 4C 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 32 47 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 44 AC 48 AC 44 52 45 74 47 1E 44 04 1B +5B 37 6D 00 96 47 96 47 1E 44 04 1B 5B 30 6D 00 +96 47 E2 4C B0 12 7E 45 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 74 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 96 47 FA 49 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 96 47 0A 44 40 FF 32 44 +C2 48 C6 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 20 00 21 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 +B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 +26 03 F2 40 A5 00 61 01 82 43 66 01 B2 40 33 00 +64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 10 00 2A 03 +F2 C0 40 00 A1 04 39 40 00 08 29 83 89 43 00 1C +FC 23 19 42 9E 01 1E 42 08 18 82 43 08 18 3E F3 +01 20 0E 49 B0 12 D0 44 86 45 00 00 0C 41 43 43 +45 50 54 00 30 40 A8 46 08 4E 2E 4F 08 5E 39 40 +0D 00 3A 40 20 00 3B 40 06 47 3C 40 12 47 5D 15 +9F 3E 21 52 3A 17 58 42 CC 05 48 9B 09 20 A2 B3 +DC 05 FD 27 B2 40 13 00 CE 05 E2 D3 23 02 30 41 +48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C +0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 DC 05 FD 27 +C2 48 CE 05 30 4D 08 47 2D 83 92 B3 DC 05 DB 23 +FC 3F 3E 8F 3D 41 92 B3 DC 05 FD 27 58 42 CC 05 +08 4C EB 3F 00 00 06 4B 45 59 30 40 2E 47 30 12 +44 47 A2 B3 DC 05 FD 27 B2 40 11 00 CE 05 E2 C3 +23 02 30 41 2F 83 8F 4E 00 00 92 B3 DC 05 FD 27 +B0 12 CE 46 1E 42 CC 05 30 4D 00 00 08 45 4D 49 +54 00 30 40 66 47 08 4E 3E 4F C7 3F 5C 47 08 45 +43 48 4F 00 B2 40 C2 48 00 47 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 00 47 30 4D 00 00 +08 54 59 50 45 00 0D 12 3D 40 A6 47 29 4F 8F 4E +00 00 7E 49 DE 3F A8 47 2D 83 2F 83 5E 83 F7 23 +3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F +3C 9F 39 4F 3E 4F 75 22 F9 98 00 00 72 22 19 53 +1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 69 22 +9B 24 26 47 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 +0A 44 00 00 C6 48 B8 47 0A 4A C4 4C B0 44 34 48 +14 44 06 5B 54 48 45 4E 5D 00 BC 47 12 48 D8 47 +F6 47 14 44 06 5B 45 4C 53 45 5D 00 BC 47 24 48 +D8 47 F4 47 1E 44 04 5B 49 46 5D 00 BC 47 F6 47 +B2 44 F4 47 1E 44 05 0D 6B 6F 20 0A 96 47 9A 44 +84 44 B2 44 F6 47 E4 47 0D 5B 54 48 45 4E 5D 00 +30 4D 48 48 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 +30 4D 54 48 13 5B 44 45 46 49 4E 45 44 5D 0D 12 +84 12 B8 47 0A 4A 72 4A 16 4C 86 49 64 48 17 5B +55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 B8 47 +0A 4A 72 4A 96 48 3D 41 2F 53 1E 83 0E 7E 30 4D +3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF +2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 +F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E +30 4D 9C 46 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E +0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D D8 45 +05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 44 1E 44 +74 4C 0A 44 22 00 0A 4A 0A 49 B2 40 20 00 C0 1D +1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 7E 47 +05 2E 22 00 0D 12 84 12 F4 48 0A 44 96 47 74 4C +86 49 00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D +F0 48 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 44 +BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 +30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D +42 49 04 23 53 00 0D 12 84 12 44 49 7E 49 2D 83 +09 DE 09 93 E1 23 3D 41 30 4D 72 49 04 23 3E 00 +9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 +08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 8C 49 08 53 +49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D +6E 47 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C +1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +0E 63 84 12 38 49 B8 47 A6 49 76 49 A2 48 B4 49 +90 49 96 47 86 49 20 49 02 2E 0E 93 E4 37 3C 43 +E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C +38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 +18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 +02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 +C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 +58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +30 4D F8 49 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D +3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E +0E 43 1E 15 3D 40 7C 4B 7E 4C 6A 4C 7A 80 2D 00 +16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 +3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 +3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 +02 00 1E 83 FC 9C 00 00 E0 23 AE 27 7E 4B 2F 24 +2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 +32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E +09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 +3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B +08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 44 2A 17 +E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 +06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 +9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 +BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 +32 B0 00 02 01 20 2F 53 30 4D 34 49 03 5C 92 42 +C2 1D C6 1D 30 4D 0D 12 84 12 84 44 B8 47 0A 4A +B0 44 4E 4D 72 4A 38 4C 0A 4E 3E 4F 3D 40 52 4C +6D 27 3D 40 2C 4C 1A E2 BC 1D 14 24 0E 12 3E 4F +30 41 54 4C 3E 4F 3D 40 2C 4C 19 20 DE 53 00 00 +68 4E 08 5E F8 40 3F 00 00 00 3D 40 2A 4E 2A 3C +1C 4C 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF +3E 4F 30 4D 72 4C 0F 4C 49 54 45 52 41 4C 82 93 +BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 +0A 44 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 +00 02 03 24 8A 4E 02 00 EE 3F 30 4D AE 49 0A 43 +4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 +30 4D D4 48 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F +30 4D 3F 40 80 1C 0E 43 84 12 1E 44 02 0D 0A 00 +96 47 94 44 26 4C B4 48 DE 48 1E 44 0B 73 74 61 +63 6B 20 65 6D 70 74 79 08 45 32 44 0A 44 40 FF +E6 48 1E 44 09 46 52 41 4D 20 66 75 6C 6C 08 45 +B2 44 EA 4C D4 4C 0D 41 42 4F 52 54 22 00 0D 12 +84 12 F4 48 0A 44 08 45 74 4C 86 49 04 4A 02 27 +0D 12 84 12 B8 47 0A 4A 72 4A B0 44 50 4D 18 49 +5C 4C 7E 48 07 5B 27 5D 0D 12 84 12 40 4D 0A 44 +0A 44 74 4C 74 4C 86 49 54 4D 03 5B 82 43 BC 1D +30 4D 00 00 02 5D B2 43 BC 1D 30 4D CC 48 11 50 +4F 53 54 50 4F 4E 45 00 0D 12 84 12 B8 47 0A 4A +72 4A B0 44 50 4D DE 48 AC 44 A8 4D 0A 44 0A 44 +74 4C 74 4C 0A 44 74 4C 74 4C 86 49 00 00 02 3A +30 12 FE 4D 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 +B8 47 0A 4A C6 4D 3D 41 5A D3 5A 53 0A 5E 19 42 +CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E +3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A +B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 +0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D +82 9F BA 1D 66 25 84 12 1E 44 0F 73 74 61 63 6B +20 6D 69 73 6D 61 74 63 68 21 12 45 6A 4D 03 3B +82 93 BC 1D F4 26 0D 12 84 12 0A 44 86 49 74 4C +10 4E 6C 4D 86 49 00 00 12 49 4D 4D 45 44 49 41 +54 45 18 42 B4 1D D8 D3 00 00 30 4D BE 4C 0C 43 +52 45 41 54 45 00 B0 12 B4 4D BA 40 86 12 FC FF +8A 4A FE FF 3A 3D 90 47 0A 44 4F 45 53 3E 1A 42 +B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D +AE 4D 0E 3A 4E 4F 4E 41 4D 45 30 12 FE 4D 2F 83 +8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 +12 02 08 49 98 3F 48 4E 05 49 53 00 0D 12 82 93 +BC 1D 08 20 84 12 40 4D CA 4E 3D 41 BE 4F 02 00 +3E 4F 30 4D 84 12 58 4D 0A 44 CC 4E 74 4C 86 49 +5E 4E 08 43 4F 44 45 00 B0 12 B4 4D A2 82 C8 1D +61 3C A0 49 0E 48 44 4E 43 4F 44 45 B2 40 B8 4F +CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 +84 12 10 4E 16 4F 3D 41 92 42 D0 1D CC 1D 5D 3C +E2 4E 0E 43 4F 44 45 4E 4E 4D 30 12 EC 4E B7 3F +00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 +00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D +E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 +C8 1D EF 3F F4 4E 0B 48 49 32 4C 4F A2 53 C8 1D +1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F 80 4F +B2 40 92 4F D0 1D 82 4E CE 1D 30 40 18 49 85 12 +7E 4F 7E 4D 26 4D 10 50 22 4F 78 4E C2 49 6C 4A +3E 4D 66 4F B8 4E 92 4E 2E 4E 86 4C 9A 50 C4 4A +00 00 00 00 85 12 7E 4F 14 57 98 55 F8 56 C0 54 +1C 55 6A 55 46 56 52 56 E2 53 06 55 00 00 00 00 +54 4F D2 52 00 00 6E 56 B2 4F B2 40 92 4F CE 1D +82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 +2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 +39 40 C8 1D 3A 40 42 18 B0 12 E6 4F 30 4D F8 4F +0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 +C8 1D B0 12 E6 4F 1A 42 CA 1D 3B 40 10 00 09 4A +08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 +1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 +39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 08 46 +FE FF 29 83 B9 40 F2 45 FE FF 39 90 AE FF F9 23 +39 40 10 18 B2 49 F0 FF 3B 40 10 00 3A 40 3A 18 +B0 12 EA 4F 82 43 4A 18 C7 3F 8C 50 B2 4E 42 18 +BE 12 3E 4F 3D 41 C0 3F 74 4D 0C 4D 41 52 4B 45 +52 00 12 12 C6 1D 0D 12 84 12 B8 47 0A 4A 72 4A +AC 44 B8 50 AC 48 4C 4C BA 50 3E 4F 3D 41 B2 41 +C6 1D B0 12 B4 4D BA 40 85 12 FC FF BA 40 8A 50 +FE FF 28 83 8A 48 00 00 BA 40 82 44 02 00 A2 52 +C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 +00 00 30 4D 12 12 C6 1D 84 12 0A 4A 72 4A AC 44 +24 51 04 51 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 +2E 4E 06 3C BE 90 8A 50 00 00 01 20 3E 52 2E 83 +21 53 30 41 1C 4B AC 44 2C 51 20 51 2E 51 B2 41 +C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 +B0 12 F4 50 15 20 3E 40 2B 00 B0 12 F4 50 06 20 +3E 40 2D 00 B0 12 F4 50 92 83 C6 1D 0E 12 1E 41 +02 00 84 12 0A 4A 1C 4B AC 44 50 4D 6E 51 3E 51 +3A 17 30 41 B0 12 34 51 19 42 C8 1D 89 4E 00 00 +A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D +3D 15 84 12 0A 4A 1C 4B AC 44 A6 51 9E 51 3E 90 +10 00 E6 2B 7C 2D A8 51 A2 41 C6 1D E1 3F 03 20 +B0 12 8C 51 43 3C 7A 90 23 00 24 20 B0 12 3C 51 +3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 +3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 +3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 +3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 +3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 +3C 51 F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 +88 51 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 8C 51 +92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E +DF 3F 3C D0 10 00 B0 12 74 51 F2 3F 03 20 B0 12 +8C 51 F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F +3C D0 80 00 B0 12 74 51 EA 3F 0C 43 1B 42 C8 1D +A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D +7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D +7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 +84 12 0A 44 00 13 74 4C 86 49 0A 44 2C 00 6A 52 +AE 51 B8 47 74 52 4C 52 BA 52 3D 41 2C DE 8B 4C +00 00 9E 3F 00 00 06 4D 4F 56 85 12 AA 52 00 40 +C6 52 0A 4D 4F 56 2E 42 85 12 AA 52 40 40 00 00 +06 41 44 44 85 12 AA 52 00 50 E0 52 0A 41 44 44 +2E 42 85 12 AA 52 40 50 EC 52 08 41 44 44 43 00 +85 12 AA 52 00 60 FA 52 0C 41 44 44 43 2E 42 00 +85 12 AA 52 40 60 32 4F 08 53 55 42 43 00 85 12 +AA 52 00 70 18 53 0C 53 55 42 43 2E 42 00 85 12 +AA 52 40 70 26 53 06 53 55 42 85 12 AA 52 00 80 +36 53 0A 53 55 42 2E 42 85 12 AA 52 40 80 42 53 +06 43 4D 50 85 12 AA 52 00 90 50 53 0A 43 4D 50 +2E 42 85 12 AA 52 40 90 00 00 08 44 41 44 44 00 +85 12 AA 52 00 A0 6A 53 0C 44 41 44 44 2E 42 00 +85 12 AA 52 40 A0 98 52 06 42 49 54 85 12 AA 52 +00 B0 88 53 0A 42 49 54 2E 42 85 12 AA 52 40 B0 +94 53 06 42 49 43 85 12 AA 52 00 C0 A2 53 0A 42 +49 43 2E 42 85 12 AA 52 40 C0 AE 53 06 42 49 53 +85 12 AA 52 00 D0 BC 53 0A 42 49 53 2E 42 85 12 +AA 52 40 D0 00 00 06 58 4F 52 85 12 AA 52 00 E0 +D6 53 0A 58 4F 52 2E 42 85 12 AA 52 40 E0 08 53 +06 41 4E 44 85 12 AA 52 00 F0 F0 53 0A 41 4E 44 +2E 42 85 12 AA 52 40 F0 B8 47 6A 52 AE 51 10 54 +0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F +C8 53 06 52 52 43 85 12 08 54 00 10 22 54 0A 52 +52 43 2E 42 85 12 08 54 40 10 5C 53 08 53 57 50 +42 00 85 12 08 54 80 10 2E 54 06 52 52 41 85 12 +08 54 00 11 4A 54 0A 52 52 41 2E 42 85 12 08 54 +40 11 3C 54 06 53 58 54 85 12 08 54 80 11 00 00 +08 50 55 53 48 00 85 12 08 54 00 12 70 54 0C 50 +55 53 48 2E 42 00 85 12 08 54 40 12 64 54 08 43 +41 4C 4C 00 85 12 08 54 80 12 1A 53 0E 4A 84 12 +FA 49 1E 44 0D 6F 75 74 20 6F 66 20 62 6F 75 6E +64 73 12 45 8E 54 06 53 3E 3D 86 12 00 38 B6 54 +04 53 3C 00 86 12 00 34 7E 54 06 30 3E 3D 86 12 +00 30 CA 54 04 30 3C 00 86 12 00 30 06 4F 04 55 +3C 00 86 12 00 2C DE 54 06 55 3E 3D 86 12 00 28 +D4 54 06 30 3C 3E 86 12 00 24 F2 54 04 30 3D 00 +86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E +00 00 A2 53 C8 1D 0E 4A 30 4D 78 53 08 54 48 45 +4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 +0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D E8 54 +08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 +A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F 56 54 0A 42 +45 47 49 4E 30 40 32 44 40 55 0A 55 4E 54 49 4C +3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 +3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 +A2 53 C8 1D 30 4D FC 53 0A 41 47 41 49 4E 0A 4E +38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 +84 12 0A 55 A0 48 86 49 5E 55 0C 52 45 50 45 41 +54 00 0D 12 84 12 9E 55 22 55 86 49 CE 55 3D 41 +08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D +00 00 30 4D BA 55 06 42 57 31 85 12 CC 55 00 00 +E6 55 06 42 57 32 85 12 CC 55 00 00 F2 55 06 42 +57 33 85 12 CC 55 00 00 0A 56 3D 41 1A 42 C8 1D +28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 +A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 +57 31 85 12 08 56 00 00 2E 56 06 46 57 32 85 12 +08 56 00 00 3A 56 06 46 57 33 85 12 08 56 00 00 +A8 55 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 +00 3C 0D 12 84 12 40 4D 4C 4C 86 49 00 00 0A 3F +47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 +00 10 EF 27 3E E0 00 08 EC 3F 74 52 0A 44 2C 00 +0A 4A 1C 4B AC 44 50 4D B8 47 6A 52 4C 52 A0 56 +0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C +59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E +AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E FE 55 08 52 +52 43 4D 00 85 12 8A 56 50 00 CE 56 08 52 52 41 +4D 00 85 12 8A 56 50 01 DC 56 08 52 4C 41 4D 00 +85 12 8A 56 50 02 EA 56 08 52 52 55 4D 00 85 12 +8A 56 50 03 FC 54 0A 50 55 53 48 4D 85 12 8A 56 +00 15 06 57 08 50 4F 50 4D 00 85 12 8A 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +C2 46 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 08 46 +q diff --git a/binaries/MSP_EXP430FR5969_8MHz_I2C.txt b/binaries/MSP_EXP430FR5969_8MHz_I2C.txt index 67e6d97..6af88b3 100644 --- a/binaries/MSP_EXP430FR5969_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5969_8MHz_I2C.txt @@ -1,335 +1,322 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF E2 57 F2 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 84 46 E2 57 -F2 4F 72 46 82 47 00 47 DC 46 3C 1D 50 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +BC 46 56 45 56 45 58 45 44 45 FC 56 B4 4F 6E 4F +6E 4F AA 46 2E 47 06 47 3C 1D E0 1C 62 49 B6 44 +C4 44 7E 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 FC 56 B4 4F 6E 4F 6E 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 70 46 B2 49 80 47 B2 49 FE 46 B2 49 DA 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D D0 47 18 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 98 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4C 47 90 48 4C 47 -14 44 04 1B 5B 30 6D 00 4C 47 18 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 -B0 12 8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 -07 0D 0A 1B 5B 37 6D 40 4C 47 0A 44 02 18 D0 47 -C6 48 0A 44 23 00 FC 46 C6 48 14 44 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 4C 47 0A 44 40 FF 28 44 C4 47 -90 48 14 44 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 44 7E 45 00 00 06 41 43 43 45 50 54 00 30 40 -72 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 -B7 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 46 2F 83 8F 4E -00 00 58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 -4C 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 47 -08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D -F6 46 04 45 43 48 4F 00 B2 40 C2 48 0A 47 82 43 -DE 1D 38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 47 92 43 DE 1D -28 42 F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 68 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 FE 46 6A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 -82 47 0D 12 84 12 14 44 02 0D 0A 00 4C 47 50 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 66 46 01 40 -2E 4E 30 4D CE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 7A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 0A 48 02 23 53 00 0D 12 -84 12 0C 48 46 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 3A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 46 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 FD 3C 0E 93 3E 4F +7F 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 A8 46 B2 49 +2C 47 B2 49 04 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 28 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 88 48 AC 44 +42 45 46 47 1E 44 05 1B 5B 37 6D 40 72 47 0A 44 +02 18 AA 48 D6 49 72 47 1E 44 04 1B 5B 30 6D 00 +72 47 BE 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 46 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 72 47 0A 44 02 18 AA 48 D6 49 0A 44 23 00 +2A 47 D6 49 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +72 47 0A 44 40 FF 32 44 9E 48 A2 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +20 00 21 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 40 FE FF 02 02 +B2 D3 06 02 B2 D3 26 02 B2 40 FF BF 22 02 F2 43 +22 03 F2 D3 26 03 F2 40 A5 00 61 01 82 43 66 01 +B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 +10 00 2A 03 F2 C0 40 00 A1 04 39 40 00 08 29 83 +89 43 00 1C FC 23 1E 42 08 18 82 43 08 18 3E F3 +02 20 1E 42 9E 01 B0 12 D0 44 80 45 00 00 0C 41 +43 43 45 50 54 00 30 40 AA 46 0A 4E 2E 4F 0A 5E +3B 40 0A 00 3C 40 20 00 3D 15 A2 3E 21 52 A2 C2 +6C 06 B2 B0 10 00 40 06 9B 22 3A 17 92 B3 6C 06 +FD 27 58 42 4C 06 48 9B 0E 24 48 9C 06 2C 78 92 +F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B +45 59 30 40 06 47 58 43 B0 12 46 45 2F 83 8F 4E +00 00 92 B3 6C 06 FD 27 1E 42 4C 06 B0 12 44 45 +30 4D 00 00 08 45 4D 49 54 00 30 40 2E 47 08 4E +3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D 24 47 +08 45 43 48 4F 00 B2 40 C2 48 38 47 38 40 05 00 +B0 12 46 45 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 38 47 28 42 F3 3F 00 00 08 54 59 50 +45 00 0D 12 3D 40 82 47 29 4F 8F 4E 00 00 7E 49 +D4 3F 84 47 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 87 22 F9 98 00 00 84 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 7B 22 9B 24 FE 46 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 44 00 00 +A2 48 94 47 E6 49 A0 4C B0 44 10 48 14 44 06 5B +54 48 45 4E 5D 00 98 47 EE 47 B4 47 D2 47 14 44 +06 5B 45 4C 53 45 5D 00 98 47 00 48 B4 47 D0 47 +1E 44 04 5B 49 46 5D 00 98 47 D2 47 B2 44 D0 47 +1E 44 05 0D 6B 6F 20 0A 72 47 9A 44 84 44 B2 44 +D2 47 C0 47 0D 5B 54 48 45 4E 5D 00 30 4D 24 48 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 30 48 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 94 47 +E6 49 4E 4A F2 4B 62 49 40 48 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 94 47 E6 49 4E 4A +72 48 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D 9E 46 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D E0 45 05 53 22 00 +82 43 C0 1D 0D 12 84 12 0A 44 1E 44 50 4C 0A 44 +22 00 E6 49 E6 48 B2 40 20 00 C0 1D 1A 53 1A B3 +82 6A C8 1D 3E 4F 3D 41 30 4D 58 47 05 2E 22 00 +0D 12 84 12 D0 48 0A 44 72 47 50 4C 62 49 00 00 +04 3C 23 00 B2 40 B2 1D B2 1D 30 4D CC 48 02 23 +1B 42 BE 1D 2C 4F 2F 83 B0 12 46 44 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 1E 49 04 23 +53 00 0D 12 84 12 20 49 5A 49 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 4E 49 04 23 3E 00 9F 42 B2 1D +00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F 68 49 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 40 47 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -00 48 3E 48 EE 44 7E 48 5A 48 4C 47 04 4C FC 46 -50 48 2E 47 01 2E 0E 93 E3 37 38 43 E2 3F 78 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -4A 4B 0A 44 22 00 1C 49 EA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -C4 48 82 2E 22 00 0D 12 84 12 D4 48 0A 44 4C 47 -4A 4B 50 48 FA 45 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9E 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F A0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 +14 49 94 47 82 49 52 49 7E 48 90 49 6C 49 72 47 +62 49 FC 48 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D D4 49 +0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F +29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 +7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C +82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 +09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 +02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E +06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 +3D 40 58 4B 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F +2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 +5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C +01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 +FC 9C 00 00 E0 23 AE 27 5A 4B 2F 24 2D 83 6A 4C +7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 +7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 +02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +00 00 0E 4B 2C 15 B0 12 3E 44 2A 17 E8 3F 9F 4F +04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 48 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 56 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 6A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 04 4C 1C 49 C0 4B -9C 26 3D 40 C8 4B DE 3E CA 4B 0A 4E 3E 4F 3D 40 -E4 4B 36 27 3D 40 BA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 E6 4B 3E 4F 3D 40 BA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 86 4D -CC 3F EE 4B 86 12 20 00 D6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7E 47 -BC 44 B4 4B B4 47 E6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -EE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 2E 4C 0A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 D4 48 0A 44 2A 45 4A 4B 50 48 7E 49 -01 27 0D 12 84 12 04 4C 1C 49 84 49 34 44 02 4C -50 48 00 00 83 5B 27 5D 0D 12 84 12 82 4C 0A 44 -0A 44 4A 4B 4A 4B 50 48 94 4C 81 5B 82 43 BE 1D -30 4D FC 47 01 5D B2 43 BE 1D 30 4D B4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 04 4C 1C 49 84 49 98 47 -34 44 02 4C E6 47 34 44 F6 4C 0A 44 0A 44 4A 4B -4A 4B 0A 44 4A 4B 4A 4B 50 48 AA 4C 01 3A 30 12 -46 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 04 4C -1C 49 14 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 FC 4C 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 50 48 4A 4B 58 4D AC 4C -50 48 AA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 94 4B 06 43 52 45 -41 54 45 00 B0 12 02 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F BC 4D 04 43 4F 44 45 00 B0 12 02 4D -A2 82 C6 1D 0D 12 84 12 F4 4F CE 4F 50 48 A4 4D -07 48 44 4E 43 4F 44 45 B2 40 D2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 58 4D -0E 50 2C 50 50 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 0E 50 2C 50 50 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F F0 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 -9C 4F 4A 4B AC 4C E4 4D 50 48 8A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 6C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 C8 47 04 4C 1C 49 -9A 4B 90 47 34 44 04 4F 9E 47 14 44 06 5B 54 48 -45 4E 5D 00 76 4E DE 4E 9A 4E BC 4E 50 48 9E 47 -14 44 06 5B 45 4C 53 45 5D 00 76 4E F4 4E 9A 4E -BA 4E 50 48 14 44 04 5B 49 46 5D 00 76 4E BC 4E -3A 44 BA 4E 72 47 14 44 05 0D 0A 6B 6F 20 4C 47 -BC 44 AC 44 3A 44 BC 4E AA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 1A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 04 4C 1C 49 -84 49 28 4F 50 48 2E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 38 4F E0 47 50 48 60 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5C 4B -06 4D 41 52 4B 45 52 00 B0 12 02 4D BA 40 85 12 -FC FF BA 40 5E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D D8 47 50 48 85 12 A0 4F 68 4C D6 4D -12 47 80 4C 54 4E D4 46 70 4F 02 49 98 50 AC 50 -8C 48 16 49 00 00 48 4F BE 4C E4 49 00 00 85 12 -A0 4F 58 56 BE 56 00 56 0E 57 C6 55 00 00 92 53 -00 00 D6 57 BA 57 2A 56 68 56 A2 54 00 00 00 00 -2A 57 CC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D A8 4F 26 50 2C 50 3C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -CA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 34 50 -E2 57 D0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 80 50 F3 3F 72 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 80 50 30 4D 84 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 0A 51 FE FF 29 83 -B9 40 E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 E4 45 B2 49 FA 44 B2 49 02 44 B2 49 02 46 -B2 49 EE FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 B2 40 -FF BF 22 02 F2 43 22 03 F2 D3 26 03 F2 40 A5 00 -61 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -B2 D2 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A1 04 -1E 42 08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 44 -00 46 38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 -1C 49 84 49 E0 47 34 44 D2 51 40 4A 34 44 EC 51 -E6 51 D4 51 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 EE 51 B2 41 -C4 1D 3E 41 84 12 0A 44 2B 00 1C 49 84 49 E0 47 -34 44 0A 52 40 4A 34 44 02 4C AA 47 1C 49 40 4A -34 44 02 4C 16 52 3E 5F E7 3F 3E 40 28 00 B0 12 -B6 51 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 -29 00 92 92 C0 1D C4 1D 02 20 30 40 70 4D 1C 15 -12 12 C4 1D 92 53 C4 1D 84 12 1C 49 40 4A 34 44 -5E 52 54 52 21 53 3E 90 10 00 C6 2B 7F 2D 60 52 -B2 41 C4 1D C1 3F 0D 12 84 12 04 4C 92 51 70 52 -0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 1D B0 12 B6 51 3C 40 00 03 +01 20 2F 53 30 4D 10 49 03 5C 92 42 C2 1D C6 1D +30 4D 0D 12 84 12 84 44 94 47 E6 49 B0 44 2A 4D +4E 4A 14 4C 0A 4E 3E 4F 3D 40 2E 4C 6D 27 3D 40 +08 4C 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 30 4C +3E 4F 3D 40 08 4C 19 20 DE 53 00 00 68 4E 08 5E +F8 40 3F 00 00 00 3D 40 06 4E 2A 3C F8 4B 02 2C +A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D +4E 4C 0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 +09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A 44 00 00 +8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +8A 4E 02 00 EE 3F 30 4D 8A 49 0A 43 4F 55 4E 54 +2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D B0 48 +0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 +80 1C 0E 43 84 12 1E 44 02 0D 0A 00 72 47 94 44 +02 4C 90 48 BA 48 1E 44 0B 73 74 61 63 6B 20 65 +6D 70 74 79 08 45 32 44 0A 44 40 FF C2 48 1E 44 +09 46 52 41 4D 20 66 75 6C 6C 08 45 B2 44 C6 4C +B0 4C 0D 41 42 4F 52 54 22 00 0D 12 84 12 D0 48 +0A 44 08 45 50 4C 62 49 E0 49 02 27 0D 12 84 12 +94 47 E6 49 4E 4A B0 44 2C 4D F4 48 38 4C 5A 48 +07 5B 27 5D 0D 12 84 12 1C 4D 0A 44 0A 44 50 4C +50 4C 62 49 30 4D 03 5B 82 43 BC 1D 30 4D 00 00 +02 5D B2 43 BC 1D 30 4D A8 48 11 50 4F 53 54 50 +4F 4E 45 00 0D 12 84 12 94 47 E6 49 4E 4A B0 44 +2C 4D BA 48 AC 44 84 4D 0A 44 0A 44 50 4C 50 4C +0A 44 50 4C 50 4C 62 49 00 00 02 3A 30 12 DA 4D +92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 94 47 E6 49 +A2 4D 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E +5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F +BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF +BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D +66 25 84 12 1E 44 0F 73 74 61 63 6B 20 6D 69 73 +6D 61 74 63 68 21 12 45 46 4D 03 3B 82 93 BC 1D +F4 26 0D 12 84 12 0A 44 62 49 50 4C EC 4D 48 4D +62 49 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +B4 1D D8 D3 00 00 30 4D 9A 4C 0C 43 52 45 41 54 +45 00 B0 12 90 4D BA 40 86 12 FC FF 8A 4A FE FF +3A 3D 6C 47 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 +85 12 00 00 8A 4D 02 00 3D 41 30 4D 8A 4D 0E 3A +4E 4F 4E 41 4D 45 30 12 DA 4D 2F 83 8F 4E 00 00 +1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +98 3F 24 4E 05 49 53 00 0D 12 82 93 BC 1D 08 20 +84 12 1C 4D A6 4E 3D 41 BE 4F 02 00 3E 4F 30 4D +84 12 34 4D 0A 44 A8 4E 50 4C 62 49 3A 4E 08 43 +4F 44 45 00 B0 12 90 4D A2 82 C8 1D 61 3C 7C 49 +0E 48 44 4E 43 4F 44 45 B2 40 94 4F CC 1D F2 3F +00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 EC 4D +F2 4E 3D 41 92 42 D0 1D CC 1D 5D 3C BE 4E 0E 43 +4F 44 45 4E 4E 4D 30 12 C8 4E B7 3F 00 00 0A 43 +4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 +84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 +0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F +D0 4E 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D +8A 4A FE FF 82 43 BC 1D B9 3F 5C 4F B2 40 6E 4F +D0 1D 82 4E CE 1D 30 40 F4 48 85 12 5A 4F 5A 4D +02 4D EC 4F FE 4E 54 4E 9E 49 48 4A 1A 4D 42 4F +94 4E 6E 4E 0A 4E 62 4C 76 50 A0 4A 00 00 00 00 +85 12 5A 4F F0 56 74 55 D4 56 9C 54 F8 54 46 55 +22 56 2E 56 BE 53 E2 54 00 00 00 00 30 4F AE 52 +00 00 4A 56 8E 4F B2 40 6E 4F CE 1D 82 43 D0 1D +30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 +30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D +3A 40 42 18 B0 12 C2 4F 30 4D D4 4F 0E 52 53 54 +5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 +C2 4F 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 +18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 +2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 +29 83 B9 43 80 FF FC 23 B9 40 10 46 FE FF 29 83 +B9 40 FA 45 FE FF 39 90 AE FF F9 23 39 40 10 18 +B2 49 EE FF 3B 40 10 00 3A 40 3A 18 B0 12 C6 4F +82 43 4A 18 C7 3F 68 50 B2 4E 42 18 BE 12 3E 4F +3D 41 C0 3F 50 4D 0C 4D 41 52 4B 45 52 00 12 12 +C6 1D 0D 12 84 12 94 47 E6 49 4E 4A AC 44 94 50 +88 48 28 4C 96 50 3E 4F 3D 41 B2 41 C6 1D B0 12 +90 4D BA 40 85 12 FC FF BA 40 66 50 FE FF 28 83 +8A 48 00 00 BA 40 82 44 02 00 A2 52 C8 1D 18 42 +B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D +12 12 C6 1D 84 12 E6 49 4E 4A AC 44 00 51 E0 50 +3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C +BE 90 66 50 00 00 01 20 3E 52 2E 83 21 53 30 41 +F8 4A AC 44 08 51 FC 50 0A 51 B2 41 C6 1D 30 41 +92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 D0 50 +15 20 3E 40 2B 00 B0 12 D0 50 06 20 3E 40 2D 00 +B0 12 D0 50 92 83 C6 1D 0E 12 1E 41 02 00 84 12 +E6 49 F8 4A AC 44 2C 4D 4A 51 3E 51 3A 17 30 41 +B0 12 10 51 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D +3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 +E6 49 F8 4A AC 44 82 51 7A 51 3E 90 10 00 E6 2B +7C 2D 84 51 A2 41 C6 1D E1 3F 03 20 B0 12 68 51 +43 3C 7A 90 23 00 24 20 B0 12 18 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D -B0 12 B6 51 ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 1D B0 12 3E 52 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 3E 52 92 92 C0 1D C4 1D 02 24 92 53 -C4 1D 8E 10 0C 5E DA 3F B0 12 3E 52 FA 23 3C 50 -10 00 B0 12 1A 52 EF 3F 0C 43 1B 42 C6 1D A2 53 -C6 1D 0D 12 84 12 04 4C 92 51 3C 53 FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -3E 52 E0 23 3C 50 80 00 B0 12 1A 52 DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 44 00 13 4A 4B -50 48 0A 44 2C 00 66 52 32 53 7C 53 09 4B 2E 4E -0E DC A2 3F 42 4E 03 4D 4F 56 85 12 72 53 00 40 -86 53 05 4D 4F 56 2E 42 85 12 72 53 40 40 00 00 -03 41 44 44 85 12 72 53 00 50 A0 53 05 41 44 44 -2E 42 85 12 72 53 40 50 AC 53 04 41 44 44 43 00 -85 12 72 53 00 60 BA 53 06 41 44 44 43 2E 42 00 -85 12 72 53 40 60 60 53 04 53 55 42 43 00 85 12 -72 53 00 70 D8 53 06 53 55 42 43 2E 42 00 85 12 -72 53 40 70 E6 53 03 53 55 42 85 12 72 53 00 80 -F6 53 05 53 55 42 2E 42 85 12 72 53 40 80 18 4E -03 43 4D 50 85 12 72 53 00 90 10 54 05 43 4D 50 -2E 42 85 12 72 53 40 90 02 4E 04 44 41 44 44 00 -85 12 72 53 00 A0 2A 54 06 44 41 44 44 2E 42 00 -85 12 72 53 40 A0 1C 54 03 42 49 54 85 12 72 53 -00 B0 48 54 05 42 49 54 2E 42 85 12 72 53 40 B0 -54 54 03 42 49 43 85 12 72 53 00 C0 62 54 05 42 -49 43 2E 42 85 12 72 53 40 C0 6E 54 03 42 49 53 -85 12 72 53 00 D0 7C 54 05 42 49 53 2E 42 85 12 -72 53 40 D0 00 00 03 58 4F 52 85 12 72 53 00 E0 -96 54 05 58 4F 52 2E 42 85 12 72 53 40 E0 C8 53 -03 41 4E 44 85 12 72 53 00 F0 B0 54 05 41 4E 44 -2E 42 85 12 72 53 40 F0 04 4C 66 52 CE 54 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 02 54 -03 52 52 43 85 12 C8 54 00 10 E0 54 05 52 52 43 -2E 42 85 12 C8 54 40 10 EC 54 04 53 57 50 42 00 -85 12 C8 54 80 10 FA 54 03 52 52 41 85 12 C8 54 -00 11 08 55 05 52 52 41 2E 42 85 12 C8 54 40 11 -14 55 03 53 58 54 85 12 C8 54 80 11 00 00 04 50 -55 53 48 00 85 12 C8 54 00 12 2E 55 06 50 55 53 -48 2E 42 00 85 12 C8 54 40 12 88 54 04 43 41 4C -4C 00 85 12 C8 54 80 12 1A 53 0E 4A 0D 12 84 12 -C6 48 14 44 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 45 22 55 03 53 3E 3D 86 12 00 38 76 55 -02 53 3C 00 86 12 00 34 3C 55 03 30 3E 3D 86 12 -00 30 8A 55 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C 9E 55 03 55 3E 3D 86 12 00 28 -94 55 03 30 3C 3E 86 12 00 24 B2 55 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 0E 4A 30 4D A8 55 04 54 48 45 -4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 38 54 -04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 -A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 4C 55 05 42 -45 47 49 4E 30 40 28 44 DC 55 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 1D 30 4D BC 54 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 CA 55 AA 47 50 48 80 55 06 52 45 50 45 41 -54 00 0D 12 84 12 5E 56 E2 55 50 48 8E 56 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D -00 00 30 4D 1E 56 03 42 57 31 85 12 8C 56 00 00 -A6 56 03 42 57 32 85 12 8C 56 00 00 B2 56 03 42 -57 33 85 12 8C 56 00 00 CA 56 3D 41 1A 42 C6 1D -28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -C8 56 00 00 EA 56 03 46 57 32 85 12 C8 56 00 00 -F6 56 03 46 57 33 85 12 C8 56 00 00 02 57 04 47 +19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D +7A 90 26 00 05 20 3C 40 10 02 B0 12 18 51 F0 3F +7A 90 40 00 14 20 3C 40 20 00 B0 12 64 51 0C 20 +3C D0 10 00 3E 40 2B 00 B0 12 68 51 92 92 C2 1D +C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 +10 00 B0 12 50 51 F2 3F 03 20 B0 12 68 51 F5 3F +7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 +B0 12 50 51 EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D +3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 +5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 +30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 0A 44 +00 13 50 4C 62 49 0A 44 2C 00 46 52 8A 51 94 47 +50 52 28 52 96 52 3D 41 2C DE 8B 4C 00 00 9E 3F +00 00 06 4D 4F 56 85 12 86 52 00 40 A2 52 0A 4D +4F 56 2E 42 85 12 86 52 40 40 00 00 06 41 44 44 +85 12 86 52 00 50 BC 52 0A 41 44 44 2E 42 85 12 +86 52 40 50 C8 52 08 41 44 44 43 00 85 12 86 52 +00 60 D6 52 0C 41 44 44 43 2E 42 00 85 12 86 52 +40 60 0E 4F 08 53 55 42 43 00 85 12 86 52 00 70 +F4 52 0C 53 55 42 43 2E 42 00 85 12 86 52 40 70 +02 53 06 53 55 42 85 12 86 52 00 80 12 53 0A 53 +55 42 2E 42 85 12 86 52 40 80 1E 53 06 43 4D 50 +85 12 86 52 00 90 2C 53 0A 43 4D 50 2E 42 85 12 +86 52 40 90 00 00 08 44 41 44 44 00 85 12 86 52 +00 A0 46 53 0C 44 41 44 44 2E 42 00 85 12 86 52 +40 A0 74 52 06 42 49 54 85 12 86 52 00 B0 64 53 +0A 42 49 54 2E 42 85 12 86 52 40 B0 70 53 06 42 +49 43 85 12 86 52 00 C0 7E 53 0A 42 49 43 2E 42 +85 12 86 52 40 C0 8A 53 06 42 49 53 85 12 86 52 +00 D0 98 53 0A 42 49 53 2E 42 85 12 86 52 40 D0 +00 00 06 58 4F 52 85 12 86 52 00 E0 B2 53 0A 58 +4F 52 2E 42 85 12 86 52 40 E0 E4 52 06 41 4E 44 +85 12 86 52 00 F0 CC 53 0A 41 4E 44 2E 42 85 12 +86 52 40 F0 94 47 46 52 8A 51 EC 53 0A 4C 3C F0 +70 00 8A 10 3A F0 0F 00 0C DA 4D 3F A4 53 06 52 +52 43 85 12 E4 53 00 10 FE 53 0A 52 52 43 2E 42 +85 12 E4 53 40 10 38 53 08 53 57 50 42 00 85 12 +E4 53 80 10 0A 54 06 52 52 41 85 12 E4 53 00 11 +26 54 0A 52 52 41 2E 42 85 12 E4 53 40 11 18 54 +06 53 58 54 85 12 E4 53 80 11 00 00 08 50 55 53 +48 00 85 12 E4 53 00 12 4C 54 0C 50 55 53 48 2E +42 00 85 12 E4 53 40 12 40 54 08 43 41 4C 4C 00 +85 12 E4 53 80 12 1A 53 0E 4A 84 12 D6 49 1E 44 +0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 12 45 +6A 54 06 53 3E 3D 86 12 00 38 92 54 04 53 3C 00 +86 12 00 34 5A 54 06 30 3E 3D 86 12 00 30 A6 54 +04 30 3C 00 86 12 00 30 E2 4E 04 55 3C 00 86 12 +00 2C BA 54 06 55 3E 3D 86 12 00 28 B0 54 06 30 +3C 3E 86 12 00 24 CE 54 04 30 3D 00 86 12 00 20 +00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 +C8 1D 0E 4A 30 4D 54 53 08 54 48 45 4E 00 1A 42 +C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 +00 02 B2 2F 88 DA 00 00 30 4D C4 54 08 45 4C 53 +45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D +2F 83 8F 4A 00 00 E3 3F 32 54 0A 42 45 47 49 4E +30 40 32 44 1C 55 0A 55 4E 54 49 4C 3A 4F 08 4E +3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE +8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D +30 4D D8 53 0A 41 47 41 49 4E 0A 4E 38 40 00 3C +E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 E6 54 +7C 48 62 49 3A 55 0C 52 45 50 45 41 54 00 0D 12 +84 12 7A 55 FE 54 62 49 AA 55 3D 41 08 4E 3E 4F +2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D +96 55 06 42 57 31 85 12 A8 55 00 00 C2 55 06 42 +57 32 85 12 A8 55 00 00 CE 55 06 42 57 33 85 12 +A8 55 00 00 E6 55 3D 41 1A 42 C8 1D 28 4E 8E 43 +00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D +8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 +E4 55 00 00 0A 56 06 46 57 32 85 12 E4 55 00 00 +16 56 06 46 57 33 85 12 E4 55 00 00 84 55 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 82 4C DE 4B 50 48 00 00 05 3F 47 4F 54 4F +84 12 1C 4D 28 4C 62 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 04 4C 92 51 4C 57 92 53 C4 1D -3E 40 2C 00 84 12 1C 49 40 4A 34 44 02 4C 28 53 -62 57 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 7A 56 -04 52 52 43 4D 00 85 12 46 57 50 00 90 57 04 52 -52 41 4D 00 85 12 46 57 50 01 9E 57 04 52 4C 41 -4D 00 85 12 46 57 50 02 AC 57 04 52 52 55 4D 00 -85 12 46 57 50 03 BC 55 05 50 55 53 48 4D 85 12 -46 57 00 15 C8 57 04 50 4F 50 4D 00 85 12 46 57 -00 17 +3E E0 00 08 EC 3F 50 52 0A 44 2C 00 E6 49 F8 4A +AC 44 2C 4D 94 47 46 52 28 52 7C 56 0A 4E 3E 4F +1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 +0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 +EA 2E 8A 10 5A 06 A8 3E DA 55 08 52 52 43 4D 00 +85 12 66 56 50 00 AA 56 08 52 52 41 4D 00 85 12 +66 56 50 01 B8 56 08 52 4C 41 4D 00 85 12 66 56 +50 02 C6 56 08 52 52 55 4D 00 85 12 66 56 50 03 +D8 54 0A 50 55 53 48 4D 85 12 66 56 00 15 E2 56 +08 50 4F 50 4D 00 85 12 66 56 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 84 46 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 0A 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 BC 46 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 10 46 q diff --git a/binaries/MSP_EXP430FR5969_8MHz_UART.txt b/binaries/MSP_EXP430FR5969_8MHz_UART.txt deleted file mode 100644 index fba5a5c..0000000 --- a/binaries/MSP_EXP430FR5969_8MHz_UART.txt +++ /dev/null @@ -1,336 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF F8 57 04 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 96 46 F8 57 -04 50 7C 46 94 47 26 47 00 47 3C 1D 62 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 7A 46 B2 49 92 47 B2 49 24 47 B2 49 FE 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 D0 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E2 47 34 47 -14 44 04 1B 5B 37 6D 00 5E 47 AA 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5E 47 A2 48 5E 47 14 44 04 1B 5B 30 6D 00 -5E 47 2A 4C 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D3 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C3 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 F2 B0 20 00 21 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 -B0 12 9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 -5E 47 D8 48 14 44 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -5E 47 0A 44 40 FF 28 44 D6 47 A2 48 14 44 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 44 86 45 00 00 -06 41 43 43 45 50 54 00 30 40 7C 46 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 46 3C 40 -D4 46 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 46 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 47 -2F 83 8F 4E 00 00 B0 12 DA 45 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 47 08 4E 3E 4F C8 3F 1C 47 04 45 -43 48 4F 00 B2 40 C2 48 C2 46 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 46 -92 43 DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 -11 24 0D 12 3D 40 7A 47 28 4F 2F 83 8F 4E 00 00 -7E 48 8F 48 02 00 10 42 24 47 7C 47 2D 83 1E 83 -F3 23 3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 -30 40 94 47 0D 12 84 12 14 44 02 0D 0A 00 5E 47 -62 48 2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D -8F 4E FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E -00 00 0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F -0E 11 2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 46 -01 40 2E 4E 30 4D E0 47 01 21 BE 4F 00 00 3E 4F -30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D -3E 8F 03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C -23 00 B2 40 B2 1D B2 1D 30 4D 8C 47 01 23 1B 42 -DC 1D 2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 -0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D -18 42 B2 1D C8 4A 00 00 30 4D 1C 48 02 23 53 00 -0D 12 84 12 1E 48 58 48 2D 83 09 93 E2 23 0E 93 -E0 23 3D 41 30 4D 4C 48 02 23 3E 00 9F 42 B2 1D -00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C -44 00 4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 -0E 93 3E 4F 7A 40 2D 00 D1 33 30 4D 58 47 02 55 -2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 -3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 -84 12 12 48 50 48 EE 44 90 48 6C 48 5E 47 16 4C -22 47 62 48 42 47 01 2E 0E 93 E3 37 38 43 E2 3F -8A 48 82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 -14 44 5C 4B 0A 44 22 00 2E 49 FC 48 B2 40 20 00 -B4 1D 6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 -30 4D D6 48 82 2E 22 00 0D 12 84 12 E6 48 0A 44 -5E 47 5C 4B 62 48 1A 46 04 57 4F 52 44 00 3C 40 -C0 1D 39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 -7E 9A FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 -27 00 00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 -7C 4A 4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 -F3 2F 4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A -C4 1D 1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 -04 46 49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 -3B 40 CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 -1E 00 0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E -78 49 48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 -1A 53 58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 -1E 43 01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 -D4 44 30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F -38 4F 29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 -7A 90 0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 -0A 9B 22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B -C8 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 -1E 83 E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 -30 4D 32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 -B0 4A 09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C -FC 90 27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 -7E 90 03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 -B1 43 02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 -04 24 3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F -B2 4A 31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 -2A 20 32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 -22 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C -69 49 79 80 30 00 79 90 0A 00 05 28 79 80 07 00 -79 90 0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B -2C 15 B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 -AF 4F 04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 -32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F -02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 -02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 -00 02 01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D -8A 4E 00 00 A2 53 C6 1D 3E 4F 30 4D 5A 4B 87 4C -49 54 45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 -C6 1D A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 -3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 -EE 3F 30 4D 68 48 05 43 4F 55 4E 54 2F 83 1E 53 -8F 4E 00 00 5E 4E FF FF 30 4D 7C 48 09 49 4E 54 -45 52 50 52 45 54 0D 12 84 12 AC 44 16 4C 2E 49 -D2 4B 9C 26 3D 40 DA 4B DE 3E DC 4B 0A 4E 3E 4F -3D 40 F6 4B 36 27 3D 40 CC 4B 1A E2 BE 1D B6 27 -0E 12 3E 4F 30 41 F8 4B 3E 4F 3D 40 CC 4B BB 23 -DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 -98 4D CC 3F 00 4C 86 12 20 00 E8 47 05 41 4C 4C -4F 54 82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 -31 40 E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 -90 47 BC 44 C6 4B C6 47 F8 47 14 44 0C 73 74 61 -63 6B 20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF -28 44 00 48 14 44 0A 46 52 41 4D 20 66 75 6C 6C -21 00 2A 45 3A 44 40 4C 1C 4C 86 41 42 4F 52 54 -22 00 0D 12 84 12 E6 48 0A 44 2A 45 5C 4B 62 48 -90 49 01 27 0D 12 84 12 16 4C 2E 49 96 49 34 44 -14 4C 62 48 00 00 83 5B 27 5D 0D 12 84 12 94 4C -0A 44 0A 44 5C 4B 5C 4B 62 48 A6 4C 81 5B 82 43 -BE 1D 30 4D 0E 48 01 5D B2 43 BE 1D 30 4D C6 4C -81 5C 92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 -54 50 4F 4E 45 00 0D 12 84 12 16 4C 2E 49 96 49 -AA 47 34 44 14 4C F8 47 34 44 08 4D 0A 44 0A 44 -5C 4B 5C 4B 0A 44 5C 4B 5C 4B 62 48 BC 4C 01 3A -30 12 58 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 -16 4C 2E 49 26 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 -0A 58 19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F -82 48 B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D -2A 52 82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 -84 12 FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 -18 42 B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 -30 4D 0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D -69 73 6D 61 74 63 68 21 36 45 0E 4D 81 3B 82 93 -BE 1D 97 27 0D 12 84 12 0A 44 62 48 5C 4B 6A 4D -BE 4C 62 48 BC 4B 09 49 4D 4D 45 44 49 41 54 45 -18 42 B6 1D F8 D0 80 00 00 00 30 4D A6 4B 06 43 -52 45 41 54 45 00 B0 12 14 4D BA 40 86 12 FC FF -8A 4A FE FF C9 3F CE 4D 04 43 4F 44 45 00 B0 12 -14 4D A2 82 C6 1D 0D 12 84 12 06 50 E0 4F 62 48 -B6 4D 07 48 44 4E 43 4F 44 45 B2 40 E4 4F DA 1D -EE 3F 00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 -6A 4D 20 50 3E 50 62 48 00 00 05 43 4F 4C 4F 4E -1A 42 C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 -A2 52 C6 1D B2 43 BE 1D 0D 12 84 12 20 50 3E 50 -62 48 00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 -C6 1D EB 3F 02 4E 85 48 49 32 4C 4F 0D 12 84 12 -28 44 AE 4F 5C 4B BE 4C F6 4D 62 48 9C 4D 86 5B -54 48 45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F -0E 4B 0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 -F9 98 FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 -00 00 F9 23 2F 53 2D 53 F7 3F 7E 4E 86 5B 45 4C -53 45 5D 00 0D 12 84 12 0A 44 00 00 DA 47 16 4C -2E 49 AC 4B A2 47 34 44 16 4F B0 47 14 44 06 5B -54 48 45 4E 5D 00 88 4E F0 4E AC 4E CE 4E 62 48 -B0 47 14 44 06 5B 45 4C 53 45 5D 00 88 4E 06 4F -AC 4E CC 4E 62 48 14 44 04 5B 49 46 5D 00 88 4E -CE 4E 3A 44 CC 4E 84 47 14 44 05 0D 0A 6B 6F 20 -5E 47 BC 44 AC 44 3A 44 CE 4E BC 4E 84 5B 49 46 -5D 00 0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2C 4F -89 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 16 4C -2E 49 96 49 3A 4F 62 48 40 4F 8B 5B 55 4E 44 45 -46 49 4E 45 44 5D 0D 12 84 12 4A 4F F2 47 62 48 -72 4F B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C -6E 4B 06 4D 41 52 4B 45 52 00 B0 12 14 4D BA 40 -85 12 FC FF BA 40 70 4F FE FF 28 83 8A 48 00 00 -BA 40 AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 -30 4D 0A 44 CA 1D EA 47 62 48 85 12 B2 4F 7A 4C -E8 4D 2E 47 92 4C 66 4E F8 46 82 4F 14 49 AA 50 -BE 50 9E 48 28 49 00 00 5A 4F D0 4C F6 49 00 00 -85 12 B2 4F 6E 56 D4 56 16 56 24 57 DC 55 00 00 -A8 53 00 00 EC 57 D0 57 40 56 7E 56 B8 54 00 00 -00 00 40 57 DE 4F 3A 40 0C 00 39 40 D6 1D 08 49 -28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 -CA 1D DA 1D 30 4D BA 4F 38 50 3E 50 4E 50 1A 42 -20 18 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 -09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 -00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 -30 4D DC 4C 09 50 57 52 5F 53 54 41 54 45 85 12 -46 50 F8 57 E2 48 09 52 53 54 5F 53 54 41 54 45 -92 42 0A 18 92 50 F3 3F 84 50 08 50 57 52 5F 48 -45 52 45 00 92 42 C6 1D 92 50 30 4D 96 50 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F -3E 90 0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 -10 00 29 83 B9 43 80 FF FC 23 B9 40 1C 51 FE FF -29 83 B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 -14 18 B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 -22 46 B2 49 F0 FF B2 49 0A 18 C2 3F B2 D0 03 00 -04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 -E0 1C 3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C -FC 23 B2 40 FE FF 02 02 B2 D3 06 02 B2 D3 26 02 -B2 40 FF BF 22 02 E2 D3 25 02 F2 43 22 03 F2 D3 -26 03 F2 40 A5 00 61 01 82 43 66 01 B2 40 33 00 -64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 B2 D2 B0 01 F2 D0 10 00 2A 03 -F2 C0 40 00 A1 04 1E 42 08 18 82 43 08 18 1E D2 -9E 01 B0 12 F8 44 20 46 38 40 C0 1D 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 -12 12 C4 1D 84 12 2E 49 96 49 F2 47 34 44 E8 51 -52 4A 34 44 02 52 FC 51 EA 51 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 04 52 B2 41 C4 1D 3E 41 84 12 0A 44 2B 00 -2E 49 96 49 F2 47 34 44 20 52 52 4A 34 44 14 4C -BC 47 2E 49 52 4A 34 44 14 4C 2C 52 3E 5F E7 3F -3E 40 28 00 B0 12 CC 51 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 -30 40 82 4D 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 -2E 49 52 4A 34 44 74 52 6A 52 21 53 3E 90 10 00 -C6 2B 7F 2D 76 52 B2 41 C4 1D C1 3F 0D 12 84 12 -16 4C A8 51 86 52 0C 43 1B 42 C6 1D A2 53 C6 1D -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 -CC 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 -18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 -10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 1D B0 12 CC 51 ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 1D B0 12 54 52 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 54 52 92 92 C0 1D -C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 -54 52 FA 23 3C 50 10 00 B0 12 30 52 EF 3F 0C 43 -1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 16 4C A8 51 -52 53 FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 54 52 E0 23 3C 50 80 00 B0 12 -30 52 DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 44 00 13 5C 4B 62 48 0A 44 2C 00 7C 52 48 53 -92 53 09 4B 2E 4E 0E DC A2 3F 54 4E 03 4D 4F 56 -85 12 88 53 00 40 9C 53 05 4D 4F 56 2E 42 85 12 -88 53 40 40 00 00 03 41 44 44 85 12 88 53 00 50 -B6 53 05 41 44 44 2E 42 85 12 88 53 40 50 C2 53 -04 41 44 44 43 00 85 12 88 53 00 60 D0 53 06 41 -44 44 43 2E 42 00 85 12 88 53 40 60 76 53 04 53 -55 42 43 00 85 12 88 53 00 70 EE 53 06 53 55 42 -43 2E 42 00 85 12 88 53 40 70 FC 53 03 53 55 42 -85 12 88 53 00 80 0C 54 05 53 55 42 2E 42 85 12 -88 53 40 80 2A 4E 03 43 4D 50 85 12 88 53 00 90 -26 54 05 43 4D 50 2E 42 85 12 88 53 40 90 14 4E -04 44 41 44 44 00 85 12 88 53 00 A0 40 54 06 44 -41 44 44 2E 42 00 85 12 88 53 40 A0 32 54 03 42 -49 54 85 12 88 53 00 B0 5E 54 05 42 49 54 2E 42 -85 12 88 53 40 B0 6A 54 03 42 49 43 85 12 88 53 -00 C0 78 54 05 42 49 43 2E 42 85 12 88 53 40 C0 -84 54 03 42 49 53 85 12 88 53 00 D0 92 54 05 42 -49 53 2E 42 85 12 88 53 40 D0 00 00 03 58 4F 52 -85 12 88 53 00 E0 AC 54 05 58 4F 52 2E 42 85 12 -88 53 40 E0 DE 53 03 41 4E 44 85 12 88 53 00 F0 -C6 54 05 41 4E 44 2E 42 85 12 88 53 40 F0 16 4C -7C 52 E4 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 18 54 03 52 52 43 85 12 DE 54 00 10 -F6 54 05 52 52 43 2E 42 85 12 DE 54 40 10 02 55 -04 53 57 50 42 00 85 12 DE 54 80 10 10 55 03 52 -52 41 85 12 DE 54 00 11 1E 55 05 52 52 41 2E 42 -85 12 DE 54 40 11 2A 55 03 53 58 54 85 12 DE 54 -80 11 00 00 04 50 55 53 48 00 85 12 DE 54 00 12 -44 55 06 50 55 53 48 2E 42 00 85 12 DE 54 40 12 -9E 54 04 43 41 4C 4C 00 85 12 DE 54 80 12 1A 53 -0E 4A 0D 12 84 12 D8 48 14 44 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 45 38 55 03 53 3E 3D -86 12 00 38 8C 55 02 53 3C 00 86 12 00 34 52 55 -03 30 3E 3D 86 12 00 30 A0 55 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C B4 55 03 55 -3E 3D 86 12 00 28 AA 55 03 30 3C 3E 86 12 00 24 -C8 55 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D -BE 55 04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 4E 54 04 45 4C 53 45 00 1A 42 C6 1D -BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 -E3 3F 62 55 05 42 45 47 49 4E 30 40 28 44 F2 55 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 1D 30 4D D2 54 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 E0 55 BC 47 62 48 96 55 -06 52 45 50 45 41 54 00 0D 12 84 12 74 56 F8 55 -62 48 A4 56 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D -CB 2F 98 42 C6 1D 00 00 30 4D 34 56 03 42 57 31 -85 12 A2 56 00 00 BC 56 03 42 57 32 85 12 A2 56 -00 00 C8 56 03 42 57 33 85 12 A2 56 00 00 E0 56 -3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F -00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 DE 56 00 00 00 57 03 46 57 32 -85 12 DE 56 00 00 0C 57 03 46 57 33 85 12 DE 56 -00 00 18 57 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 94 4C F0 4B 62 48 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 16 4C A8 51 -62 57 92 53 C4 1D 3E 40 2C 00 84 12 2E 49 52 4A -34 44 14 4C 3E 53 78 57 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 90 56 04 52 52 43 4D 00 85 12 5C 57 -50 00 A6 57 04 52 52 41 4D 00 85 12 5C 57 50 01 -B4 57 04 52 4C 41 4D 00 85 12 5C 57 50 02 C2 57 -04 52 52 55 4D 00 85 12 5C 57 50 03 D2 55 05 50 -55 53 48 4D 85 12 5C 57 00 15 DE 57 04 50 4F 50 -4D 00 85 12 5C 57 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -96 46 02 46 02 46 02 46 02 46 02 46 02 46 1C 51 -q diff --git a/binaries/MSP_EXP430FR5994_16MHz_115200.txt b/binaries/MSP_EXP430FR5994_16MHz_115200.txt new file mode 100644 index 0000000..c6f34d8 --- /dev/null +++ b/binaries/MSP_EXP430FR5994_16MHz_115200.txt @@ -0,0 +1,506 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 59 +EC 42 7E 41 1C 56 FC 54 5C 43 74 5E 60 4C 1A 4C +1A 4C D2 42 90 43 58 43 3C 1D E0 1C 0E 46 B6 40 +C4 40 2A 45 20 00 0A 00 00 1C 7E 41 1C 56 FC 54 +5C 43 74 5E 60 4C 1A 4C 1A 4C 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 11 3D 0E 93 3E 4F +D5 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D0 42 B2 49 +8E 43 B2 49 56 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 D4 4C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 5C 43 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 40 34 45 AC 40 52 41 9E 43 1E 40 04 1B +5B 37 6D 00 1E 44 1E 44 1E 40 04 1B 5B 30 6D 00 +1E 44 6A 49 B0 12 7E 41 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 9E 43 1E 40 +07 0D 0A 1B 5B 37 6D 23 1E 44 82 46 1E 40 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 1E 44 0A 40 40 FF 32 40 +4A 45 4E 46 1E 40 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 40 46 41 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 41 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 40 00 40 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 D3 06 02 B2 40 FC FF 02 02 B2 43 26 02 +B2 D3 22 02 E2 D2 25 02 B2 43 42 02 B2 D3 46 02 +B2 43 62 02 B2 D3 66 02 F2 43 26 03 F2 D3 22 03 +F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 41 01 +F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 66 01 +B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 F2 D0 10 00 2A 03 +F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 +39 40 00 10 29 83 89 43 00 1C FC 23 19 42 9E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 40 86 41 00 00 0C 41 43 43 45 50 54 00 30 40 +D2 42 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 30 43 3C 40 3C 43 5D 15 8A 3E 21 52 3A 17 +58 42 CC 05 48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 +13 00 CE 05 E2 D2 23 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D +32 43 2D 83 92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 DC 05 FD 27 58 42 CC 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 58 43 30 12 6E 43 A2 B3 DC 05 +FD 27 B2 40 11 00 CE 05 E2 C2 23 02 30 41 2F 83 +8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 F8 42 1E 42 +CC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 90 43 +08 4E 3E 4F C7 3F 86 43 08 45 43 48 4F 00 B2 40 +C2 48 2A 43 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 2A 43 30 4D 0D 12 3D 40 D8 43 1B 42 +32 20 9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 +1E 20 1B 42 20 20 02 3C DA 43 2D 83 0C 9B 16 2C +58 4C 00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 +F5 23 82 4C 1E 20 3D 41 3C 40 20 00 A6 3F 0E 99 +91 27 CA 48 00 00 1A 53 1E 53 8C 3F 1A 15 B0 12 +6A 57 19 17 DC 3F 00 00 08 54 59 50 45 00 0D 12 +3D 40 2E 44 29 4F 8F 4E 00 00 7E 49 AF 3F 30 44 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 31 22 +F9 98 00 00 2E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 25 22 9B 24 50 43 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 40 00 00 4E 45 40 44 +92 46 4C 49 B0 40 BC 44 14 40 06 5B 54 48 45 4E +5D 00 44 44 9A 44 60 44 7E 44 14 40 06 5B 45 4C +53 45 5D 00 44 44 AC 44 60 44 7C 44 1E 40 04 5B +49 46 5D 00 44 44 7E 44 B2 40 7C 44 1E 40 05 0D +6B 6F 20 0A 1E 44 9A 40 84 40 B2 40 7E 44 6C 44 +0D 5B 54 48 45 4E 5D 00 30 4D D0 44 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D DC 44 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 40 44 92 46 FA 46 +9E 48 0E 46 EC 44 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 40 44 92 46 FA 46 1E 45 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D C6 42 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 41 05 53 22 00 82 43 C0 1D +0D 12 84 12 0A 40 1E 40 FC 48 0A 40 22 00 92 46 +92 45 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D +3E 4F 3D 41 30 4D A8 43 05 2E 22 00 0D 12 84 12 +7C 45 0A 40 1E 44 FC 48 0E 46 00 00 04 3C 23 00 +B2 40 B2 1D B2 1D 30 4D 78 45 02 23 1B 42 BE 1D +2C 4F 2F 83 B0 12 46 40 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 +B2 1D C8 4A 00 00 30 4D CA 45 04 23 53 00 0D 12 +84 12 CC 45 06 46 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D FA 45 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 +B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 14 46 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 98 43 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 C0 45 40 44 +2E 46 FE 45 2A 45 3C 46 18 46 1E 44 0E 46 A8 45 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 80 46 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 04 48 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 06 48 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 40 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D BC 45 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 +84 12 84 40 40 44 92 46 B0 40 D6 49 FA 46 C0 48 +0A 4E 3E 4F 3D 40 DA 48 6D 27 3D 40 B4 48 1A E2 +BC 1D 14 24 0E 12 3E 4F 30 41 DC 48 3E 4F 3D 40 +B4 48 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 B2 4A 2A 3C A4 48 02 2C A2 53 C8 1D +1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D FA 48 0F 4C +49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 +C8 1D A2 52 C8 1D BA 40 0A 40 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D 36 46 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D 5C 45 0A 41 4C 4C +4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 +84 12 1E 40 02 0D 0A 00 1E 44 94 40 AE 48 3C 45 +66 45 1E 40 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 41 32 40 0A 40 40 FF 6E 45 1E 40 09 46 52 41 +4D 20 66 75 6C 6C 08 41 B2 40 72 49 5C 49 0D 41 +42 4F 52 54 22 00 0D 12 84 12 7C 45 0A 40 08 41 +FC 48 0E 46 8C 46 02 27 0D 12 84 12 40 44 92 46 +FA 46 B0 40 D8 49 A0 45 E4 48 06 45 07 5B 27 5D +0D 12 84 12 C8 49 0A 40 0A 40 FC 48 FC 48 0E 46 +DC 49 03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 +BC 1D 30 4D 54 45 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 40 44 92 46 FA 46 B0 40 D8 49 66 45 +AC 40 30 4A 0A 40 0A 40 FC 48 FC 48 0A 40 FC 48 +FC 48 0E 46 00 00 02 3A 30 12 86 4A 92 B3 C8 1D +A2 63 C8 1D 0D 12 84 12 40 44 92 46 4E 4A 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 +82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 +1E 40 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 41 F2 49 03 3B 82 93 BC 1D F4 26 0D 12 +84 12 0A 40 0E 46 FC 48 98 4A F4 49 0E 46 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 +00 00 30 4D 46 49 0C 43 52 45 41 54 45 00 B0 12 +3C 4A BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 18 44 +0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D 36 4A 0E 3A 4E 4F 4E 41 +4D 45 30 12 86 4A 2F 83 8F 4E 00 00 1A 42 C8 1D +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F D0 4A +05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 C8 49 +52 4B 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 E0 49 +0A 40 54 4B FC 48 0E 46 E6 4A 08 43 4F 44 45 00 +B0 12 3C 4A A2 82 C8 1D 61 3C 28 46 0E 48 44 4E +43 4F 44 45 B2 40 40 4C CC 1D F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 98 4A 9E 4B 3D 41 +92 42 D0 1D CC 1D 5D 3C 6A 4B 0E 43 4F 44 45 4E +4E 4D 30 12 74 4B B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F 7C 4B 0B 48 +49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF +82 43 BC 1D B9 3F 08 4C B2 40 1A 4C D0 1D 82 4E +CE 1D 30 40 A0 45 85 12 06 4C 06 4A 7A 58 76 5A +88 58 10 5E 4A 46 F4 46 F0 5C EE 4B 40 4B 1A 4B +B6 4A 96 58 22 4D 5A 5A 00 00 00 00 85 12 06 4C +9C 53 20 52 42 54 48 51 A4 51 F2 51 CE 52 88 54 +6A 50 8E 51 00 00 00 00 DC 4B 5A 4F 00 00 F6 52 +3A 4C B2 40 1A 4C CE 1D 82 43 D0 1D 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 +B0 12 6E 4C 30 4D 80 4C 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 1D B0 12 6E 4C 1A 42 +CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 08 42 FE FF 29 83 B9 40 F2 41 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF +3B 40 10 00 3A 40 3A 18 B0 12 72 4C 82 43 4A 18 +C7 3F 14 4D B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +FC 49 0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 +84 12 40 44 92 46 FA 46 AC 40 40 4D 34 45 D4 48 +42 4D 3E 4F 3D 41 B2 41 C6 1D B0 12 3C 4A BA 40 +85 12 FC FF BA 40 12 4D FE FF 28 83 8A 48 00 00 +BA 40 82 40 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 +B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D +84 12 92 46 FA 46 AC 40 AC 4D 8C 4D 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 12 4D +00 00 01 20 3E 52 2E 83 21 53 30 41 A4 47 AC 40 +B4 4D A8 4D B6 4D B2 41 C6 1D 30 41 92 83 C6 1D +3E 40 28 00 0A 4E 3D 15 B0 12 7C 4D 15 20 3E 40 +2B 00 B0 12 7C 4D 06 20 3E 40 2D 00 B0 12 7C 4D +92 83 C6 1D 0E 12 1E 41 02 00 84 12 92 46 A4 47 +AC 40 D8 49 F6 4D 3E 51 3A 17 30 41 B0 12 BC 4D +19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 +92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 92 46 A4 47 +AC 40 2E 4E 26 4E 3E 90 10 00 E6 2B 7C 2D 30 4E +A2 41 C6 1D E1 3F 03 20 B0 12 14 4E 43 3C 7A 90 +23 00 24 20 B0 12 C4 4D 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D +A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 C4 4D F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 10 4E 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 14 4E 92 92 C2 1D C6 1D 02 24 +92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +FC 4D F2 3F 03 20 B0 12 14 4E F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 FC 4D +EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 +19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF +19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 40 00 13 FC 48 +0E 46 0A 40 2C 00 F2 4E 36 4E 40 44 FC 4E D4 4E +42 4F 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 32 4F 00 40 4E 4F 0A 4D 4F 56 2E 42 +85 12 32 4F 40 40 00 00 06 41 44 44 85 12 32 4F +00 50 68 4F 0A 41 44 44 2E 42 85 12 32 4F 40 50 +74 4F 08 41 44 44 43 00 85 12 32 4F 00 60 82 4F +0C 41 44 44 43 2E 42 00 85 12 32 4F 40 60 BA 4B +08 53 55 42 43 00 85 12 32 4F 00 70 A0 4F 0C 53 +55 42 43 2E 42 00 85 12 32 4F 40 70 AE 4F 06 53 +55 42 85 12 32 4F 00 80 BE 4F 0A 53 55 42 2E 42 +85 12 32 4F 40 80 CA 4F 06 43 4D 50 85 12 32 4F +00 90 D8 4F 0A 43 4D 50 2E 42 85 12 32 4F 40 90 +00 00 08 44 41 44 44 00 85 12 32 4F 00 A0 F2 4F +0C 44 41 44 44 2E 42 00 85 12 32 4F 40 A0 20 4F +06 42 49 54 85 12 32 4F 00 B0 10 50 0A 42 49 54 +2E 42 85 12 32 4F 40 B0 1C 50 06 42 49 43 85 12 +32 4F 00 C0 2A 50 0A 42 49 43 2E 42 85 12 32 4F +40 C0 36 50 06 42 49 53 85 12 32 4F 00 D0 44 50 +0A 42 49 53 2E 42 85 12 32 4F 40 D0 00 00 06 58 +4F 52 85 12 32 4F 00 E0 5E 50 0A 58 4F 52 2E 42 +85 12 32 4F 40 E0 90 4F 06 41 4E 44 85 12 32 4F +00 F0 78 50 0A 41 4E 44 2E 42 85 12 32 4F 40 F0 +40 44 F2 4E 36 4E 98 50 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F 50 50 06 52 52 43 85 12 +90 50 00 10 AA 50 0A 52 52 43 2E 42 85 12 90 50 +40 10 E4 4F 08 53 57 50 42 00 85 12 90 50 80 10 +B6 50 06 52 52 41 85 12 90 50 00 11 D2 50 0A 52 +52 41 2E 42 85 12 90 50 40 11 C4 50 06 53 58 54 +85 12 90 50 80 11 00 00 08 50 55 53 48 00 85 12 +90 50 00 12 F8 50 0C 50 55 53 48 2E 42 00 85 12 +90 50 40 12 EC 50 08 43 41 4C 4C 00 85 12 90 50 +80 12 1A 53 0E 4A 84 12 82 46 1E 40 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 41 16 51 06 53 +3E 3D 86 12 00 38 3E 51 04 53 3C 00 86 12 00 34 +06 51 06 30 3E 3D 86 12 00 30 52 51 04 30 3C 00 +86 12 00 30 8E 4B 04 55 3C 00 86 12 00 2C 66 51 +06 55 3E 3D 86 12 00 28 5C 51 06 30 3C 3E 86 12 +00 24 7A 51 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A +30 4D 00 50 08 54 48 45 4E 00 1A 42 C8 1D 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D 70 51 08 45 4C 53 45 00 1A 42 +C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A +00 00 E3 3F DE 50 0A 42 45 47 49 4E 30 40 32 40 +C8 51 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D 84 50 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 92 51 28 45 0E 46 +E6 51 0C 52 45 50 45 41 54 00 0D 12 84 12 26 52 +AA 51 0E 46 56 52 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 1D CB 2F 98 42 C8 1D 00 00 30 4D 42 52 06 42 +57 31 85 12 54 52 00 00 6E 52 06 42 57 32 85 12 +54 52 00 00 7A 52 06 42 57 33 85 12 54 52 00 00 +92 52 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 +C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 90 52 00 00 +B6 52 06 46 57 32 85 12 90 52 00 00 C2 52 06 46 +57 33 85 12 90 52 00 00 30 52 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 C8 49 +D4 48 0E 46 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F FC 4E 0A 40 2C 00 92 46 A4 47 AC 40 D8 49 +40 44 F2 4E D4 4E 28 53 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 86 52 08 52 52 43 4D 00 85 12 12 53 +50 00 56 53 08 52 52 41 4D 00 85 12 12 53 50 01 +64 53 08 52 4C 41 4D 00 85 12 12 53 50 02 72 53 +08 52 52 55 4D 00 85 12 12 53 50 03 84 51 0A 50 +55 53 48 4D 85 12 12 53 00 15 8E 53 08 50 4F 50 +4D 00 85 12 12 53 00 17 D2 C3 23 02 E2 B2 60 02 +02 24 30 40 F2 41 1A 52 04 20 19 62 06 20 92 43 +14 20 C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 17 20 +89 10 C2 49 18 20 B0 12 1C 54 5A 53 FC 23 39 40 +05 00 D2 49 14 20 4E 06 82 93 46 06 05 24 92 B3 +6C 06 FD 27 C2 93 4C 06 59 83 F3 2F 19 83 0B 30 +F2 43 4E 06 82 93 46 06 03 24 92 B3 6C 06 FD 27 +5A 92 4C 06 F3 23 30 41 1A 43 E1 3F 19 43 3A 43 +8A 10 C2 4A 4E 06 82 93 46 06 05 24 92 B3 6C 06 +FD 27 C2 93 4C 06 19 83 F3 23 5A 42 4C 06 30 41 +80 53 12 52 5F 53 45 43 54 5F 57 58 1C D3 F2 40 +51 00 19 20 B0 12 A8 53 38 20 B0 12 1C 54 6A 53 +04 24 FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 03 43 +19 53 39 90 01 02 F6 23 F2 43 4E 06 3C C0 03 00 +D2 D3 23 02 30 41 DA 52 12 57 5F 53 45 43 54 5F +57 58 2C D3 F0 40 58 00 81 CB B0 12 A8 53 15 20 +3A 40 FE FF 29 43 B0 12 20 54 D2 49 00 1E 4E 06 +03 43 19 53 39 90 00 02 F8 23 39 40 03 00 B0 12 +1E 54 7A C0 E1 00 6A 82 D9 27 8C 10 1C 52 4C 06 +D2 D3 23 02 84 12 9E 43 1E 40 0B 3C 20 53 44 20 +45 72 72 6F 72 21 E8 54 2F 83 8F 4E 00 00 B2 40 +10 00 BE 1D 0E 4C 84 12 4E 46 12 41 B0 12 54 41 +E2 B2 60 02 8A 20 B2 40 81 A9 40 06 B2 40 30 00 +46 06 D2 D3 25 02 B2 D0 C0 04 0C 02 92 C3 40 06 +39 40 6E 01 29 83 89 43 02 20 FC 23 39 42 B0 12 +1E 54 D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 +00 40 18 20 B0 12 18 54 02 24 30 40 CA 54 B0 12 +1C 54 7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 +B2 40 00 48 18 20 B0 12 18 54 29 42 B0 12 1E 54 +92 43 14 20 82 43 16 20 78 43 3C 42 B2 40 00 77 +18 20 B0 12 18 54 B2 40 40 69 18 20 B0 12 D6 53 +03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 +00 50 18 20 B0 12 D6 53 D0 23 92 D3 40 06 82 43 +46 06 92 C3 40 06 0A 43 09 43 B0 12 4C 54 38 40 +00 1E 92 48 C6 01 04 20 92 48 C8 01 06 20 5C 48 +C2 01 7C 80 0C 00 08 24 5C 53 06 24 6C 52 04 24 +3C 50 07 20 30 40 D0 54 09 43 B0 12 4C 54 A2 43 +2C 20 19 48 0E 00 82 49 08 20 1A 48 24 00 82 4A +0A 20 09 5A 82 49 0C 20 09 5A 58 48 0D 00 82 48 +12 20 09 88 09 88 82 49 10 20 30 41 82 43 32 20 +30 40 84 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 +5A 42 23 20 58 42 22 20 59 42 24 20 89 10 0A D9 +88 10 08 58 0A 6A 88 10 08 58 30 41 1A 52 08 20 +09 43 FC 3E 92 42 22 20 D0 04 92 42 24 20 D2 04 +92 42 12 20 C8 04 92 42 E4 04 1A 20 92 42 E6 04 +1C 20 92 52 10 20 1A 20 82 63 1C 20 30 41 92 4B +0E 00 22 20 92 4B 10 00 24 20 B0 12 54 56 5A 4B +03 00 82 5A 1A 20 82 63 1C 20 30 41 3C 42 3B 40 +38 20 09 43 CB 93 02 00 10 24 9B 92 24 20 0C 00 +04 20 9B 92 22 20 0A 00 A3 25 09 4B 3B 50 1C 00 +3B 90 18 21 EF 23 0C 5C 9B 3D 0C 43 82 4B 32 20 +8B 49 00 00 09 93 0A 24 99 52 C6 1D 16 00 4A 93 +05 34 C9 93 02 00 02 34 5A 59 02 00 CB 4A 02 00 +CB 43 03 00 9B 42 1A 20 04 00 9B 42 1C 20 06 00 +18 42 30 20 8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 +14 1E 0C 00 9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 +9B 48 1C 1E 12 00 9B 48 1E 1E 14 00 82 43 1E 20 +6A 93 1A 24 A4 37 8B 43 16 00 7A 93 02 24 07 38 +35 3C B2 40 1C 21 A0 40 B2 40 B8 43 D0 42 9B 42 +C2 1D 18 00 9B 82 C6 1D 18 00 9B 42 C4 1D 1A 00 +9B 52 C6 1D 1A 00 22 3C 30 41 1B 42 32 20 82 43 +1E 20 B2 90 00 02 20 20 3F 20 BB 80 00 02 12 00 +8B 73 14 00 DB 53 03 00 DB 92 12 20 03 00 0E 28 +CB 43 03 00 B0 12 24 56 B0 12 4C 56 8B 43 10 00 +9B 48 00 1E 0E 00 9B 48 02 1E 10 00 B2 40 00 02 +20 20 8B 93 14 00 0B 20 92 9B 12 00 1E 20 1C 2C +BB 90 00 02 12 00 03 2C 92 4B 12 00 20 20 B0 12 +7E 56 1A 42 1A 20 19 42 1C 20 38 3E CB 43 02 00 +2B 4B 82 4B 32 20 0B 93 06 24 92 4B 16 00 1E 20 +B0 12 AC 57 22 C3 30 41 1B 42 32 20 0B 93 FB 27 +EB 92 02 00 04 20 B0 12 6A 5B B0 12 5A 5C CB 93 +02 00 E4 37 1E 4B 18 00 9F 4B 1A 00 00 00 31 50 +06 00 3D 41 B0 12 DC 57 02 24 30 40 B0 43 B2 40 +3C 1D A0 40 B2 40 D2 42 D0 42 30 40 9E 43 09 93 +07 24 F8 90 20 00 00 1E 03 20 18 53 19 83 F9 23 +30 41 98 4C 0B 52 45 41 44 22 5A 43 20 3C 00 4B +09 44 45 4C 22 00 6A 43 1A 3C C6 49 0D 57 52 49 +54 45 22 00 6A 42 13 3C AE 49 0F 41 50 50 45 4E +44 22 7A 42 0C 3C AA 4B 0A 43 4C 4F 53 45 B0 12 +F8 57 30 4D 0E 49 0B 4C 4F 41 44 22 7A 43 2F 83 +8F 4E 00 00 0E 4A 82 93 BC 1D 0B 24 0D 12 84 12 +0A 40 0A 40 FC 48 FC 48 7C 45 0A 40 D2 58 FC 48 +0E 46 0D 12 84 12 0A 40 22 00 92 46 4C 49 D0 58 +3D 41 36 4F 0E 56 82 4E 36 20 A2 43 22 20 82 43 +24 20 1C 43 0E 96 8C 24 F6 90 3A 00 01 00 01 20 +26 53 F6 90 5C 00 00 00 03 20 16 53 0E 96 66 24 +82 46 34 20 B0 12 54 56 15 42 12 20 B0 12 D2 57 +2C 43 0A 43 08 4A 58 0E 08 58 82 48 30 20 C8 93 +00 1E 60 24 39 42 F8 96 00 1E 04 20 18 53 19 83 +FA 23 16 53 F6 90 2E 00 FF FF 19 24 39 50 03 00 +B0 12 3E 58 06 20 F6 90 5C 00 FF FF 29 24 0E 96 +27 28 16 42 34 20 1A 53 3A 90 10 00 DB 23 92 53 +1A 20 82 63 1C 20 15 83 D1 23 2C 42 49 3C F6 90 +2E 00 FE FF EE 27 B0 12 3E 58 EB 23 39 40 03 00 +F8 96 00 1E 04 20 18 53 19 83 FA 23 09 3C 0E 96 +E0 2F F6 90 5C 00 FF FF DC 23 B0 12 3E 58 D9 23 +18 42 30 20 92 48 1A 1E 22 20 92 48 14 1E 24 20 +F8 B0 10 00 0B 1E 13 24 82 93 24 20 05 20 82 93 +22 20 02 20 A2 43 22 20 0E 96 9A 23 92 42 22 20 +2C 20 92 42 24 20 2E 20 8F 43 00 00 03 3C 2A 4F +B0 12 9C 56 35 40 B6 40 36 40 C4 40 3A 4F 3E 4F +0A 93 04 24 7A 93 39 20 0C 93 02 20 30 40 B0 43 +0D 12 84 12 9E 43 1E 40 0B 3C 20 4F 70 65 6E 45 +72 72 6F 72 B2 40 E6 54 E2 B2 60 02 02 24 30 40 +86 41 92 12 3E 18 3F 40 7E 1C 8F 43 00 00 0D 12 +84 12 1E 40 0F 4C 4F 41 44 22 20 42 4F 4F 54 2E +34 54 48 22 B2 40 7C 49 54 58 08 42 4F 4F 54 00 +B2 40 18 5A C2 42 30 4D 4C 47 0C 4E 4F 42 4F 4F +54 00 B2 40 86 41 C2 42 30 4D 1A 93 89 20 0C 93 +C7 23 30 4D 4A 5A 08 52 45 41 44 00 2F 83 8F 4E +00 00 1E 42 32 20 B0 12 6A 57 1E 82 32 20 30 4D +08 4A 1A 52 08 20 B0 12 A0 5A 0A 48 1A 52 0C 20 +09 43 30 40 92 54 3C 42 0A 12 2A 41 82 9A 0A 20 +2B 25 B0 12 4C 56 88 93 02 1E 03 20 88 93 00 1E +08 24 28 52 38 90 00 02 F6 2B 91 53 00 00 08 43 +EC 3F A2 41 26 20 82 48 28 20 0C 43 B8 43 00 1E +6A 41 B8 40 FF 0F 02 1E 08 11 8A 10 08 5A 5A 41 +01 00 0A 11 08 10 82 4A 24 20 82 48 22 20 2A 41 +B0 12 90 5A 3A 41 30 41 90 4B 0A 00 16 C5 90 4B +0C 00 12 C5 B0 12 30 56 82 4A 26 20 82 48 28 20 +0A 12 B0 12 4C 56 1A 48 00 1E 88 43 00 1E 19 48 +02 1E 88 43 02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 +3A 93 10 24 82 4A 22 20 82 49 24 20 B0 12 30 56 +2A 91 E9 27 09 4A 2A 41 81 49 00 00 B0 12 90 5A +2A 41 DF 3F 3A 41 30 40 90 5A 9B 52 1E 20 12 00 +8B 63 14 00 1A 42 1A 20 19 42 1C 20 30 40 92 54 +2A 93 BC 20 0C 93 09 20 F8 40 E5 00 00 1E B0 12 +74 5B B0 12 08 5B B0 12 F8 57 30 4D F2 B0 40 00 +A2 04 29 20 F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 +4A 11 59 42 B4 04 F2 40 20 00 C0 04 D2 42 B1 04 +C8 04 1A 52 E4 04 D2 42 B5 04 C8 04 19 52 E4 04 +D2 42 B2 04 C0 04 B2 40 00 08 C8 04 1A 52 E4 04 +92 42 B6 04 C0 04 B2 80 BC 07 C0 04 B2 40 00 02 +C8 04 19 52 E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C +3D 3E 3F 5B 5C 5D 7C 2E 29 92 06 28 39 80 03 00 +B0 12 48 5C 39 40 03 00 7A 4B C8 4A 00 1E 82 9B +36 20 12 28 0D 12 3D 40 0F 00 3C 40 F8 5B 7A 9C +F3 27 1D 83 FC 23 3D 41 6A 9C E6 27 3A 80 21 00 +EB 3B 18 53 19 83 E8 23 09 93 06 24 F8 40 20 00 +00 1E 18 53 19 83 FA 23 30 41 1A 4B 04 00 19 4B +06 00 B0 12 4C 54 18 4B 08 00 B0 12 9C 5B 88 49 +12 1E 88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E +98 4B 14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 +92 54 B2 40 00 02 1E 20 1B 42 32 20 B0 12 6A 5B +82 43 1E 20 DB 53 03 00 DB 92 12 20 03 00 1D 28 +B0 12 24 56 08 12 0A 12 B0 12 A6 5A 2A 91 03 24 +2A 41 B0 12 4C 56 3A 41 38 41 98 42 22 20 00 1E +98 42 24 20 02 1E B0 12 90 5A AB 42 02 00 9B 42 +22 20 0E 00 9B 42 24 20 10 00 30 40 8A 56 6C 58 +0A 57 52 49 54 45 B0 12 92 5C 30 4D 2A 92 54 20 +2C 93 0E 24 0C 93 3D 24 0D 12 84 12 1E 40 0C 3C +20 57 72 69 74 65 45 72 72 6F 72 00 B2 40 E6 54 +0A 43 08 43 B0 12 A6 5A B0 12 D2 57 18 42 30 20 +F8 40 20 00 0B 1E B0 12 9C 5B 88 43 0C 1E 88 4A +0E 1E 88 49 10 1E 98 42 24 20 14 1E 98 42 22 20 +1A 1E 88 43 1C 1E 88 43 1E 1E 2C 42 1B 42 34 20 +82 9B 36 20 D1 27 FB 90 2E 00 00 00 CD 27 39 40 +0B 00 B0 12 18 5C B0 12 74 5B 2A 42 B0 12 9C 56 +30 4D B0 12 08 5B 8B 43 12 00 8B 43 14 00 90 4B +0A 00 90 C2 90 4B 0C 00 8C C2 B0 12 30 56 B0 12 +A6 5A B0 12 DA 5C 30 4D 2C 93 BA 27 0C 93 AC 23 +EB 42 02 00 58 4B 13 00 59 4B 14 00 89 10 09 58 +58 4B 15 00 5B 42 12 20 0A 43 3C 42 08 11 09 10 +4A 10 1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 +32 20 19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 +10 00 CB 4A 03 00 B0 12 CE 57 1A 4B 12 00 BB C0 +FF 01 12 00 3A F0 FF 01 82 4A 1E 20 30 4D 60 58 +10 54 45 52 4D 32 53 44 22 00 0D 12 84 12 74 58 +22 5E 0A 43 B0 12 5C 43 92 B3 DC 05 FD 27 59 42 +CC 05 C2 49 CE 05 69 92 0D 24 CA 49 00 1E 1A 53 +3A 90 FF 01 04 24 F0 2B B0 12 92 5C EA 3F B0 12 +F8 42 EA 3F F2 90 0D 00 CC 05 FC 27 B0 12 F8 42 +F2 90 0A 00 CC 05 FC 27 82 4A 1E 20 B0 12 F8 57 +3D 41 30 4D +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +EC 42 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 08 42 +q diff --git a/binaries/MSP_EXP430FR5994_16MHz_4MBds.txt b/binaries/MSP_EXP430FR5994_16MHz_4MBds.txt new file mode 100644 index 0000000..4c94bcd --- /dev/null +++ b/binaries/MSP_EXP430FR5994_16MHz_4MBds.txt @@ -0,0 +1,506 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +EC 42 7E 41 1C 56 FC 54 5C 43 74 5E 60 4C 1A 4C +1A 4C D2 42 90 43 58 43 3C 1D E0 1C 0E 46 B6 40 +C4 40 2A 45 20 00 0A 00 00 1C 7E 41 1C 56 FC 54 +5C 43 74 5E 60 4C 1A 4C 1A 4C 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 11 3D 0E 93 3E 4F +D5 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D0 42 B2 49 +8E 43 B2 49 56 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 D4 4C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 5C 43 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 40 34 45 AC 40 52 41 9E 43 1E 40 04 1B +5B 37 6D 00 1E 44 1E 44 1E 40 04 1B 5B 30 6D 00 +1E 44 6A 49 B0 12 7E 41 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 9E 43 1E 40 +07 0D 0A 1B 5B 37 6D 23 1E 44 82 46 1E 40 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 1E 44 0A 40 40 FF 32 40 +4A 45 4E 46 1E 40 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 40 46 41 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 41 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 40 00 40 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 D3 06 02 B2 40 FC FF 02 02 B2 43 26 02 +B2 D3 22 02 E2 D2 25 02 B2 43 42 02 B2 D3 46 02 +B2 43 62 02 B2 D3 66 02 F2 43 26 03 F2 D3 22 03 +F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 41 01 +F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 66 01 +B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 +00 18 18 83 FE 23 19 83 FA 23 F2 D0 10 00 2A 03 +F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 +39 40 00 10 29 83 89 43 00 1C FC 23 19 42 9E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 40 86 41 00 00 0C 41 43 43 45 50 54 00 30 40 +D2 42 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 30 43 3C 40 3C 43 5D 15 8A 3E 21 52 3A 17 +58 42 CC 05 48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 +13 00 CE 05 E2 D2 23 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D +32 43 2D 83 92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 DC 05 FD 27 58 42 CC 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 58 43 30 12 6E 43 A2 B3 DC 05 +FD 27 B2 40 11 00 CE 05 E2 C2 23 02 30 41 2F 83 +8F 4E 00 00 92 B3 DC 05 FD 27 B0 12 F8 42 1E 42 +CC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 90 43 +08 4E 3E 4F C7 3F 86 43 08 45 43 48 4F 00 B2 40 +C2 48 2A 43 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 2A 43 30 4D 0D 12 3D 40 D8 43 1B 42 +32 20 9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 +1E 20 1B 42 20 20 02 3C DA 43 2D 83 0C 9B 16 2C +58 4C 00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 +F5 23 82 4C 1E 20 3D 41 3C 40 20 00 A6 3F 0E 99 +91 27 CA 48 00 00 1A 53 1E 53 8C 3F 1A 15 B0 12 +6A 57 19 17 DC 3F 00 00 08 54 59 50 45 00 0D 12 +3D 40 2E 44 29 4F 8F 4E 00 00 7E 49 AF 3F 30 44 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 31 22 +F9 98 00 00 2E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 25 22 9B 24 50 43 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 40 00 00 4E 45 40 44 +92 46 4C 49 B0 40 BC 44 14 40 06 5B 54 48 45 4E +5D 00 44 44 9A 44 60 44 7E 44 14 40 06 5B 45 4C +53 45 5D 00 44 44 AC 44 60 44 7C 44 1E 40 04 5B +49 46 5D 00 44 44 7E 44 B2 40 7C 44 1E 40 05 0D +6B 6F 20 0A 1E 44 9A 40 84 40 B2 40 7E 44 6C 44 +0D 5B 54 48 45 4E 5D 00 30 4D D0 44 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D DC 44 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 40 44 92 46 FA 46 +9E 48 0E 46 EC 44 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 40 44 92 46 FA 46 1E 45 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D C6 42 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D D8 41 05 53 22 00 82 43 C0 1D +0D 12 84 12 0A 40 1E 40 FC 48 0A 40 22 00 92 46 +92 45 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D +3E 4F 3D 41 30 4D A8 43 05 2E 22 00 0D 12 84 12 +7C 45 0A 40 1E 44 FC 48 0E 46 00 00 04 3C 23 00 +B2 40 B2 1D B2 1D 30 4D 78 45 02 23 1B 42 BE 1D +2C 4F 2F 83 B0 12 46 40 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 +B2 1D C8 4A 00 00 30 4D CA 45 04 23 53 00 0D 12 +84 12 CC 45 06 46 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D FA 45 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 +B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 14 46 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 98 43 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 C0 45 40 44 +2E 46 FE 45 2A 45 3C 46 18 46 1E 44 0E 46 A8 45 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 80 46 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 04 48 +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 06 48 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 40 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D BC 45 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 +84 12 84 40 40 44 92 46 B0 40 D6 49 FA 46 C0 48 +0A 4E 3E 4F 3D 40 DA 48 6D 27 3D 40 B4 48 1A E2 +BC 1D 14 24 0E 12 3E 4F 30 41 DC 48 3E 4F 3D 40 +B4 48 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 B2 4A 2A 3C A4 48 02 2C A2 53 C8 1D +1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D FA 48 0F 4C +49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 +C8 1D A2 52 C8 1D BA 40 0A 40 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D 36 46 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D 5C 45 0A 41 4C 4C +4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 +84 12 1E 40 02 0D 0A 00 1E 44 94 40 AE 48 3C 45 +66 45 1E 40 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 41 32 40 0A 40 40 FF 6E 45 1E 40 09 46 52 41 +4D 20 66 75 6C 6C 08 41 B2 40 72 49 5C 49 0D 41 +42 4F 52 54 22 00 0D 12 84 12 7C 45 0A 40 08 41 +FC 48 0E 46 8C 46 02 27 0D 12 84 12 40 44 92 46 +FA 46 B0 40 D8 49 A0 45 E4 48 06 45 07 5B 27 5D +0D 12 84 12 C8 49 0A 40 0A 40 FC 48 FC 48 0E 46 +DC 49 03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 +BC 1D 30 4D 54 45 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 40 44 92 46 FA 46 B0 40 D8 49 66 45 +AC 40 30 4A 0A 40 0A 40 FC 48 FC 48 0A 40 FC 48 +FC 48 0E 46 00 00 02 3A 30 12 86 4A 92 B3 C8 1D +A2 63 C8 1D 0D 12 84 12 40 44 92 46 4E 4A 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 +82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 +1E 40 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 41 F2 49 03 3B 82 93 BC 1D F4 26 0D 12 +84 12 0A 40 0E 46 FC 48 98 4A F4 49 0E 46 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 +00 00 30 4D 46 49 0C 43 52 45 41 54 45 00 B0 12 +3C 4A BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 18 44 +0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D 36 4A 0E 3A 4E 4F 4E 41 +4D 45 30 12 86 4A 2F 83 8F 4E 00 00 1A 42 C8 1D +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F D0 4A +05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 C8 49 +52 4B 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 E0 49 +0A 40 54 4B FC 48 0E 46 E6 4A 08 43 4F 44 45 00 +B0 12 3C 4A A2 82 C8 1D 61 3C 28 46 0E 48 44 4E +43 4F 44 45 B2 40 40 4C CC 1D F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 98 4A 9E 4B 3D 41 +92 42 D0 1D CC 1D 5D 3C 6A 4B 0E 43 4F 44 45 4E +4E 4D 30 12 74 4B B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F 7C 4B 0B 48 +49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF +82 43 BC 1D B9 3F 08 4C B2 40 1A 4C D0 1D 82 4E +CE 1D 30 40 A0 45 85 12 06 4C 06 4A 7A 58 76 5A +88 58 10 5E 4A 46 F4 46 F0 5C EE 4B 40 4B 1A 4B +B6 4A 96 58 22 4D 5A 5A 00 00 00 00 85 12 06 4C +9C 53 20 52 42 54 48 51 A4 51 F2 51 CE 52 88 54 +6A 50 8E 51 00 00 00 00 DC 4B 5A 4F 00 00 F6 52 +3A 4C B2 40 1A 4C CE 1D 82 43 D0 1D 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 +B0 12 6E 4C 30 4D 80 4C 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 1D B0 12 6E 4C 1A 42 +CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 08 42 FE FF 29 83 B9 40 F2 41 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF +3B 40 10 00 3A 40 3A 18 B0 12 72 4C 82 43 4A 18 +C7 3F 14 4D B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +FC 49 0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 +84 12 40 44 92 46 FA 46 AC 40 40 4D 34 45 D4 48 +42 4D 3E 4F 3D 41 B2 41 C6 1D B0 12 3C 4A BA 40 +85 12 FC FF BA 40 12 4D FE FF 28 83 8A 48 00 00 +BA 40 82 40 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 +B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D +84 12 92 46 FA 46 AC 40 AC 4D 8C 4D 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 12 4D +00 00 01 20 3E 52 2E 83 21 53 30 41 A4 47 AC 40 +B4 4D A8 4D B6 4D B2 41 C6 1D 30 41 92 83 C6 1D +3E 40 28 00 0A 4E 3D 15 B0 12 7C 4D 15 20 3E 40 +2B 00 B0 12 7C 4D 06 20 3E 40 2D 00 B0 12 7C 4D +92 83 C6 1D 0E 12 1E 41 02 00 84 12 92 46 A4 47 +AC 40 D8 49 F6 4D 3E 51 3A 17 30 41 B0 12 BC 4D +19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 +92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 92 46 A4 47 +AC 40 2E 4E 26 4E 3E 90 10 00 E6 2B 7C 2D 30 4E +A2 41 C6 1D E1 3F 03 20 B0 12 14 4E 43 3C 7A 90 +23 00 24 20 B0 12 C4 4D 3C 40 00 03 0E 93 1C 24 +3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D +A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 C4 4D F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 10 4E 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 14 4E 92 92 C2 1D C6 1D 02 24 +92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +FC 4D F2 3F 03 20 B0 12 14 4E F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 FC 4D +EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 +19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF +19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 40 00 13 FC 48 +0E 46 0A 40 2C 00 F2 4E 36 4E 40 44 FC 4E D4 4E +42 4F 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 32 4F 00 40 4E 4F 0A 4D 4F 56 2E 42 +85 12 32 4F 40 40 00 00 06 41 44 44 85 12 32 4F +00 50 68 4F 0A 41 44 44 2E 42 85 12 32 4F 40 50 +74 4F 08 41 44 44 43 00 85 12 32 4F 00 60 82 4F +0C 41 44 44 43 2E 42 00 85 12 32 4F 40 60 BA 4B +08 53 55 42 43 00 85 12 32 4F 00 70 A0 4F 0C 53 +55 42 43 2E 42 00 85 12 32 4F 40 70 AE 4F 06 53 +55 42 85 12 32 4F 00 80 BE 4F 0A 53 55 42 2E 42 +85 12 32 4F 40 80 CA 4F 06 43 4D 50 85 12 32 4F +00 90 D8 4F 0A 43 4D 50 2E 42 85 12 32 4F 40 90 +00 00 08 44 41 44 44 00 85 12 32 4F 00 A0 F2 4F +0C 44 41 44 44 2E 42 00 85 12 32 4F 40 A0 20 4F +06 42 49 54 85 12 32 4F 00 B0 10 50 0A 42 49 54 +2E 42 85 12 32 4F 40 B0 1C 50 06 42 49 43 85 12 +32 4F 00 C0 2A 50 0A 42 49 43 2E 42 85 12 32 4F +40 C0 36 50 06 42 49 53 85 12 32 4F 00 D0 44 50 +0A 42 49 53 2E 42 85 12 32 4F 40 D0 00 00 06 58 +4F 52 85 12 32 4F 00 E0 5E 50 0A 58 4F 52 2E 42 +85 12 32 4F 40 E0 90 4F 06 41 4E 44 85 12 32 4F +00 F0 78 50 0A 41 4E 44 2E 42 85 12 32 4F 40 F0 +40 44 F2 4E 36 4E 98 50 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F 50 50 06 52 52 43 85 12 +90 50 00 10 AA 50 0A 52 52 43 2E 42 85 12 90 50 +40 10 E4 4F 08 53 57 50 42 00 85 12 90 50 80 10 +B6 50 06 52 52 41 85 12 90 50 00 11 D2 50 0A 52 +52 41 2E 42 85 12 90 50 40 11 C4 50 06 53 58 54 +85 12 90 50 80 11 00 00 08 50 55 53 48 00 85 12 +90 50 00 12 F8 50 0C 50 55 53 48 2E 42 00 85 12 +90 50 40 12 EC 50 08 43 41 4C 4C 00 85 12 90 50 +80 12 1A 53 0E 4A 84 12 82 46 1E 40 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 41 16 51 06 53 +3E 3D 86 12 00 38 3E 51 04 53 3C 00 86 12 00 34 +06 51 06 30 3E 3D 86 12 00 30 52 51 04 30 3C 00 +86 12 00 30 8E 4B 04 55 3C 00 86 12 00 2C 66 51 +06 55 3E 3D 86 12 00 28 5C 51 06 30 3C 3E 86 12 +00 24 7A 51 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A +30 4D 00 50 08 54 48 45 4E 00 1A 42 C8 1D 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D 70 51 08 45 4C 53 45 00 1A 42 +C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A +00 00 E3 3F DE 50 0A 42 45 47 49 4E 30 40 32 40 +C8 51 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D 84 50 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 92 51 28 45 0E 46 +E6 51 0C 52 45 50 45 41 54 00 0D 12 84 12 26 52 +AA 51 0E 46 56 52 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 1D CB 2F 98 42 C8 1D 00 00 30 4D 42 52 06 42 +57 31 85 12 54 52 00 00 6E 52 06 42 57 32 85 12 +54 52 00 00 7A 52 06 42 57 33 85 12 54 52 00 00 +92 52 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 +C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 90 52 00 00 +B6 52 06 46 57 32 85 12 90 52 00 00 C2 52 06 46 +57 33 85 12 90 52 00 00 30 52 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 C8 49 +D4 48 0E 46 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +EC 3F FC 4E 0A 40 2C 00 92 46 A4 47 AC 40 D8 49 +40 44 F2 4E D4 4E 28 53 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 86 52 08 52 52 43 4D 00 85 12 12 53 +50 00 56 53 08 52 52 41 4D 00 85 12 12 53 50 01 +64 53 08 52 4C 41 4D 00 85 12 12 53 50 02 72 53 +08 52 52 55 4D 00 85 12 12 53 50 03 84 51 0A 50 +55 53 48 4D 85 12 12 53 00 15 8E 53 08 50 4F 50 +4D 00 85 12 12 53 00 17 D2 C3 23 02 E2 B2 60 02 +02 24 30 40 F2 41 1A 52 04 20 19 62 06 20 92 43 +14 20 C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 17 20 +89 10 C2 49 18 20 B0 12 1C 54 5A 53 FC 23 39 40 +05 00 D2 49 14 20 4E 06 82 93 46 06 05 24 92 B3 +6C 06 FD 27 C2 93 4C 06 59 83 F3 2F 19 83 0B 30 +F2 43 4E 06 82 93 46 06 03 24 92 B3 6C 06 FD 27 +5A 92 4C 06 F3 23 30 41 1A 43 E1 3F 19 43 3A 43 +8A 10 C2 4A 4E 06 82 93 46 06 05 24 92 B3 6C 06 +FD 27 C2 93 4C 06 19 83 F3 23 5A 42 4C 06 30 41 +80 53 12 52 5F 53 45 43 54 5F 57 58 1C D3 F2 40 +51 00 19 20 B0 12 A8 53 38 20 B0 12 1C 54 6A 53 +04 24 FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 03 43 +19 53 39 90 01 02 F6 23 F2 43 4E 06 3C C0 03 00 +D2 D3 23 02 30 41 DA 52 12 57 5F 53 45 43 54 5F +57 58 2C D3 F0 40 58 00 81 CB B0 12 A8 53 15 20 +3A 40 FE FF 29 43 B0 12 20 54 D2 49 00 1E 4E 06 +03 43 19 53 39 90 00 02 F8 23 39 40 03 00 B0 12 +1E 54 7A C0 E1 00 6A 82 D9 27 8C 10 1C 52 4C 06 +D2 D3 23 02 84 12 9E 43 1E 40 0B 3C 20 53 44 20 +45 72 72 6F 72 21 E8 54 2F 83 8F 4E 00 00 B2 40 +10 00 BE 1D 0E 4C 84 12 4E 46 12 41 B0 12 54 41 +E2 B2 60 02 8A 20 B2 40 81 A9 40 06 B2 40 30 00 +46 06 D2 D3 25 02 B2 D0 C0 04 0C 02 92 C3 40 06 +39 40 6E 01 29 83 89 43 02 20 FC 23 39 42 B0 12 +1E 54 D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 +00 40 18 20 B0 12 18 54 02 24 30 40 CA 54 B0 12 +1C 54 7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 +B2 40 00 48 18 20 B0 12 18 54 29 42 B0 12 1E 54 +92 43 14 20 82 43 16 20 78 43 3C 42 B2 40 00 77 +18 20 B0 12 18 54 B2 40 40 69 18 20 B0 12 D6 53 +03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 +00 50 18 20 B0 12 D6 53 D0 23 92 D3 40 06 82 43 +46 06 92 C3 40 06 0A 43 09 43 B0 12 4C 54 38 40 +00 1E 92 48 C6 01 04 20 92 48 C8 01 06 20 5C 48 +C2 01 7C 80 0C 00 08 24 5C 53 06 24 6C 52 04 24 +3C 50 07 20 30 40 D0 54 09 43 B0 12 4C 54 A2 43 +2C 20 19 48 0E 00 82 49 08 20 1A 48 24 00 82 4A +0A 20 09 5A 82 49 0C 20 09 5A 58 48 0D 00 82 48 +12 20 09 88 09 88 82 49 10 20 30 41 82 43 32 20 +30 40 84 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 +5A 42 23 20 58 42 22 20 59 42 24 20 89 10 0A D9 +88 10 08 58 0A 6A 88 10 08 58 30 41 1A 52 08 20 +09 43 FC 3E 92 42 22 20 D0 04 92 42 24 20 D2 04 +92 42 12 20 C8 04 92 42 E4 04 1A 20 92 42 E6 04 +1C 20 92 52 10 20 1A 20 82 63 1C 20 30 41 92 4B +0E 00 22 20 92 4B 10 00 24 20 B0 12 54 56 5A 4B +03 00 82 5A 1A 20 82 63 1C 20 30 41 3C 42 3B 40 +38 20 09 43 CB 93 02 00 10 24 9B 92 24 20 0C 00 +04 20 9B 92 22 20 0A 00 A3 25 09 4B 3B 50 1C 00 +3B 90 18 21 EF 23 0C 5C 9B 3D 0C 43 82 4B 32 20 +8B 49 00 00 09 93 0A 24 99 52 C6 1D 16 00 4A 93 +05 34 C9 93 02 00 02 34 5A 59 02 00 CB 4A 02 00 +CB 43 03 00 9B 42 1A 20 04 00 9B 42 1C 20 06 00 +18 42 30 20 8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 +14 1E 0C 00 9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 +9B 48 1C 1E 12 00 9B 48 1E 1E 14 00 82 43 1E 20 +6A 93 1A 24 A4 37 8B 43 16 00 7A 93 02 24 07 38 +35 3C B2 40 1C 21 A0 40 B2 40 B8 43 D0 42 9B 42 +C2 1D 18 00 9B 82 C6 1D 18 00 9B 42 C4 1D 1A 00 +9B 52 C6 1D 1A 00 22 3C 30 41 1B 42 32 20 82 43 +1E 20 B2 90 00 02 20 20 3F 20 BB 80 00 02 12 00 +8B 73 14 00 DB 53 03 00 DB 92 12 20 03 00 0E 28 +CB 43 03 00 B0 12 24 56 B0 12 4C 56 8B 43 10 00 +9B 48 00 1E 0E 00 9B 48 02 1E 10 00 B2 40 00 02 +20 20 8B 93 14 00 0B 20 92 9B 12 00 1E 20 1C 2C +BB 90 00 02 12 00 03 2C 92 4B 12 00 20 20 B0 12 +7E 56 1A 42 1A 20 19 42 1C 20 38 3E CB 43 02 00 +2B 4B 82 4B 32 20 0B 93 06 24 92 4B 16 00 1E 20 +B0 12 AC 57 22 C3 30 41 1B 42 32 20 0B 93 FB 27 +EB 92 02 00 04 20 B0 12 6A 5B B0 12 5A 5C CB 93 +02 00 E4 37 1E 4B 18 00 9F 4B 1A 00 00 00 31 50 +06 00 3D 41 B0 12 DC 57 02 24 30 40 B0 43 B2 40 +3C 1D A0 40 B2 40 D2 42 D0 42 30 40 9E 43 09 93 +07 24 F8 90 20 00 00 1E 03 20 18 53 19 83 F9 23 +30 41 98 4C 0B 52 45 41 44 22 5A 43 20 3C 00 4B +09 44 45 4C 22 00 6A 43 1A 3C C6 49 0D 57 52 49 +54 45 22 00 6A 42 13 3C AE 49 0F 41 50 50 45 4E +44 22 7A 42 0C 3C AA 4B 0A 43 4C 4F 53 45 B0 12 +F8 57 30 4D 0E 49 0B 4C 4F 41 44 22 7A 43 2F 83 +8F 4E 00 00 0E 4A 82 93 BC 1D 0B 24 0D 12 84 12 +0A 40 0A 40 FC 48 FC 48 7C 45 0A 40 D2 58 FC 48 +0E 46 0D 12 84 12 0A 40 22 00 92 46 4C 49 D0 58 +3D 41 36 4F 0E 56 82 4E 36 20 A2 43 22 20 82 43 +24 20 1C 43 0E 96 8C 24 F6 90 3A 00 01 00 01 20 +26 53 F6 90 5C 00 00 00 03 20 16 53 0E 96 66 24 +82 46 34 20 B0 12 54 56 15 42 12 20 B0 12 D2 57 +2C 43 0A 43 08 4A 58 0E 08 58 82 48 30 20 C8 93 +00 1E 60 24 39 42 F8 96 00 1E 04 20 18 53 19 83 +FA 23 16 53 F6 90 2E 00 FF FF 19 24 39 50 03 00 +B0 12 3E 58 06 20 F6 90 5C 00 FF FF 29 24 0E 96 +27 28 16 42 34 20 1A 53 3A 90 10 00 DB 23 92 53 +1A 20 82 63 1C 20 15 83 D1 23 2C 42 49 3C F6 90 +2E 00 FE FF EE 27 B0 12 3E 58 EB 23 39 40 03 00 +F8 96 00 1E 04 20 18 53 19 83 FA 23 09 3C 0E 96 +E0 2F F6 90 5C 00 FF FF DC 23 B0 12 3E 58 D9 23 +18 42 30 20 92 48 1A 1E 22 20 92 48 14 1E 24 20 +F8 B0 10 00 0B 1E 13 24 82 93 24 20 05 20 82 93 +22 20 02 20 A2 43 22 20 0E 96 9A 23 92 42 22 20 +2C 20 92 42 24 20 2E 20 8F 43 00 00 03 3C 2A 4F +B0 12 9C 56 35 40 B6 40 36 40 C4 40 3A 4F 3E 4F +0A 93 04 24 7A 93 39 20 0C 93 02 20 30 40 B0 43 +0D 12 84 12 9E 43 1E 40 0B 3C 20 4F 70 65 6E 45 +72 72 6F 72 B2 40 E6 54 E2 B2 60 02 02 24 30 40 +86 41 92 12 3E 18 3F 40 7E 1C 8F 43 00 00 0D 12 +84 12 1E 40 0F 4C 4F 41 44 22 20 42 4F 4F 54 2E +34 54 48 22 B2 40 7C 49 54 58 08 42 4F 4F 54 00 +B2 40 18 5A C2 42 30 4D 4C 47 0C 4E 4F 42 4F 4F +54 00 B2 40 86 41 C2 42 30 4D 1A 93 89 20 0C 93 +C7 23 30 4D 4A 5A 08 52 45 41 44 00 2F 83 8F 4E +00 00 1E 42 32 20 B0 12 6A 57 1E 82 32 20 30 4D +08 4A 1A 52 08 20 B0 12 A0 5A 0A 48 1A 52 0C 20 +09 43 30 40 92 54 3C 42 0A 12 2A 41 82 9A 0A 20 +2B 25 B0 12 4C 56 88 93 02 1E 03 20 88 93 00 1E +08 24 28 52 38 90 00 02 F6 2B 91 53 00 00 08 43 +EC 3F A2 41 26 20 82 48 28 20 0C 43 B8 43 00 1E +6A 41 B8 40 FF 0F 02 1E 08 11 8A 10 08 5A 5A 41 +01 00 0A 11 08 10 82 4A 24 20 82 48 22 20 2A 41 +B0 12 90 5A 3A 41 30 41 90 4B 0A 00 16 C5 90 4B +0C 00 12 C5 B0 12 30 56 82 4A 26 20 82 48 28 20 +0A 12 B0 12 4C 56 1A 48 00 1E 88 43 00 1E 19 48 +02 1E 88 43 02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 +3A 93 10 24 82 4A 22 20 82 49 24 20 B0 12 30 56 +2A 91 E9 27 09 4A 2A 41 81 49 00 00 B0 12 90 5A +2A 41 DF 3F 3A 41 30 40 90 5A 9B 52 1E 20 12 00 +8B 63 14 00 1A 42 1A 20 19 42 1C 20 30 40 92 54 +2A 93 BC 20 0C 93 09 20 F8 40 E5 00 00 1E B0 12 +74 5B B0 12 08 5B B0 12 F8 57 30 4D F2 B0 40 00 +A2 04 29 20 F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 +4A 11 59 42 B4 04 F2 40 20 00 C0 04 D2 42 B1 04 +C8 04 1A 52 E4 04 D2 42 B5 04 C8 04 19 52 E4 04 +D2 42 B2 04 C0 04 B2 40 00 08 C8 04 1A 52 E4 04 +92 42 B6 04 C0 04 B2 80 BC 07 C0 04 B2 40 00 02 +C8 04 19 52 E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C +3D 3E 3F 5B 5C 5D 7C 2E 29 92 06 28 39 80 03 00 +B0 12 48 5C 39 40 03 00 7A 4B C8 4A 00 1E 82 9B +36 20 12 28 0D 12 3D 40 0F 00 3C 40 F8 5B 7A 9C +F3 27 1D 83 FC 23 3D 41 6A 9C E6 27 3A 80 21 00 +EB 3B 18 53 19 83 E8 23 09 93 06 24 F8 40 20 00 +00 1E 18 53 19 83 FA 23 30 41 1A 4B 04 00 19 4B +06 00 B0 12 4C 54 18 4B 08 00 B0 12 9C 5B 88 49 +12 1E 88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E +98 4B 14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 +92 54 B2 40 00 02 1E 20 1B 42 32 20 B0 12 6A 5B +82 43 1E 20 DB 53 03 00 DB 92 12 20 03 00 1D 28 +B0 12 24 56 08 12 0A 12 B0 12 A6 5A 2A 91 03 24 +2A 41 B0 12 4C 56 3A 41 38 41 98 42 22 20 00 1E +98 42 24 20 02 1E B0 12 90 5A AB 42 02 00 9B 42 +22 20 0E 00 9B 42 24 20 10 00 30 40 8A 56 6C 58 +0A 57 52 49 54 45 B0 12 92 5C 30 4D 2A 92 54 20 +2C 93 0E 24 0C 93 3D 24 0D 12 84 12 1E 40 0C 3C +20 57 72 69 74 65 45 72 72 6F 72 00 B2 40 E6 54 +0A 43 08 43 B0 12 A6 5A B0 12 D2 57 18 42 30 20 +F8 40 20 00 0B 1E B0 12 9C 5B 88 43 0C 1E 88 4A +0E 1E 88 49 10 1E 98 42 24 20 14 1E 98 42 22 20 +1A 1E 88 43 1C 1E 88 43 1E 1E 2C 42 1B 42 34 20 +82 9B 36 20 D1 27 FB 90 2E 00 00 00 CD 27 39 40 +0B 00 B0 12 18 5C B0 12 74 5B 2A 42 B0 12 9C 56 +30 4D B0 12 08 5B 8B 43 12 00 8B 43 14 00 90 4B +0A 00 90 C2 90 4B 0C 00 8C C2 B0 12 30 56 B0 12 +A6 5A B0 12 DA 5C 30 4D 2C 93 BA 27 0C 93 AC 23 +EB 42 02 00 58 4B 13 00 59 4B 14 00 89 10 09 58 +58 4B 15 00 5B 42 12 20 0A 43 3C 42 08 11 09 10 +4A 10 1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 +32 20 19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 +10 00 CB 4A 03 00 B0 12 CE 57 1A 4B 12 00 BB C0 +FF 01 12 00 3A F0 FF 01 82 4A 1E 20 30 4D 60 58 +10 54 45 52 4D 32 53 44 22 00 0D 12 84 12 74 58 +22 5E 0A 43 B0 12 5C 43 92 B3 DC 05 FD 27 59 42 +CC 05 C2 49 CE 05 69 92 0D 24 CA 49 00 1E 1A 53 +3A 90 FF 01 04 24 F0 2B B0 12 92 5C EA 3F B0 12 +F8 42 EA 3F F2 90 0D 00 CC 05 FC 27 B0 12 F8 42 +F2 90 0A 00 CC 05 FC 27 82 4A 1E 20 B0 12 F8 57 +3D 41 30 4D +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +EC 42 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 08 42 +q diff --git a/binaries/MSP_EXP430FR5994_16MHz_I2C.txt b/binaries/MSP_EXP430FR5994_16MHz_I2C.txt index fc3e728..b7c3a10 100644 --- a/binaries/MSP_EXP430FR5994_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5994_16MHz_I2C.txt @@ -1,658 +1,504 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF 16 68 3E 4D 34 01 -10 00 C1 87 B6 41 62 5F B8 41 20 5E 84 42 16 68 -3E 4D 72 42 E0 43 00 43 DC 42 3C 1D AE 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +E6 42 56 41 F8 55 D8 54 44 41 56 5E 3C 4C F6 4B +F6 4B D4 42 58 43 30 43 3C 1D E0 1C EA 45 B6 40 +C4 40 06 45 20 00 0A 00 00 1C 56 41 F8 55 D8 54 +44 41 56 5E 3C 4C F6 4B F6 4B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4000 -B0 12 B8 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 62 5F 39 40 22 18 -B2 49 70 42 B2 49 DE 43 B2 49 FE 42 B2 49 DA 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 46 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 41 0E 12 B0 12 -F8 40 0A 40 DE 1D 2E 44 18 43 EE 40 34 40 8A 41 -14 40 05 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 F6 43 34 40 7E 41 14 40 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 AA 43 EE 44 AA 43 -14 40 04 1B 5B 30 6D 00 AA 43 76 48 2E 93 13 28 -B2 D0 C0 07 C0 06 18 42 02 18 08 11 38 D0 00 04 -82 48 D4 06 F2 D0 03 00 6A 02 92 C3 C0 06 A2 D2 -EA 06 92 C3 30 01 30 41 48 43 A2 B3 EC 06 FD 27 -C2 48 CE 06 A2 B2 EC 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 41 04 57 41 52 4D 00 -B0 12 20 5E 78 40 03 00 B0 12 BA 41 84 12 14 40 -07 0D 0A 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 0A 40 23 00 FC 42 24 45 14 40 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 AA 43 0A 40 40 FF 28 40 22 44 -EE 44 14 40 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 40 7E 41 00 00 06 41 43 43 45 50 54 00 30 40 -72 42 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 EC 06 B2 B0 10 00 C0 06 -B7 22 3A 17 92 B3 EC 06 FD 27 58 42 CC 06 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 41 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 42 2F 83 8F 4E -00 00 58 43 B0 12 BA 41 92 B3 EC 06 FD 27 1E 42 -CC 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 43 -08 4E 3E 4F A2 B3 EC 06 FD 27 C2 48 CE 06 30 4D -F6 42 04 45 43 48 4F 00 B2 40 C2 48 0A 43 82 43 -DE 1D 38 40 05 00 B0 12 BA 41 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 43 92 43 DE 1D -28 42 F1 3F 0D 12 3D 40 64 43 1B 42 32 20 9B 42 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 12 3D 0E 93 3E 4F +C3 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D2 42 B2 49 +56 43 B2 49 2E 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 B0 4C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 41 B0 12 D0 40 10 45 AC 40 +42 41 70 43 1E 40 05 1B 5B 37 6D 40 FA 43 0A 40 +02 18 32 45 5E 46 FA 43 1E 40 04 1B 5B 30 6D 00 +FA 43 46 49 48 43 A2 B3 EC 06 FD 27 C2 48 CE 06 +A2 B2 EC 06 FD 27 30 41 B2 D0 C0 07 C0 06 18 42 +02 18 08 11 38 D0 00 04 82 48 D4 06 F2 D0 03 00 +6A 02 92 C3 C0 06 A2 D2 EA 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 70 43 1E 40 07 0D 0A 1B 5B 37 +6D 40 FA 43 0A 40 02 18 32 45 5E 46 0A 40 23 00 +54 43 5E 46 1E 40 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +FA 43 0A 40 40 FF 32 40 26 45 2A 46 1E 40 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 40 36 41 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 41 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +40 00 40 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 +FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 42 02 +B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 26 03 +F2 D3 22 03 F2 40 A5 00 41 01 F2 40 10 00 40 01 +D2 43 41 01 F2 40 A5 00 61 01 B2 40 48 00 62 01 +82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 +40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 F2 D0 +10 00 2A 03 F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 +B2 42 B0 01 39 40 00 10 29 83 89 43 00 1C FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 9E 01 +B0 12 D0 40 80 41 00 00 0C 41 43 43 45 50 54 00 +30 40 D4 42 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 8D 3E 21 52 A2 C2 EC 06 B2 B0 10 00 +C0 06 86 22 3A 17 92 B3 EC 06 FD 27 58 42 CC 06 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 30 43 +58 43 B0 12 46 41 2F 83 8F 4E 00 00 92 B3 EC 06 +FD 27 1E 42 CC 06 B0 12 44 41 30 4D 00 00 08 45 +4D 49 54 00 30 40 58 43 08 4E 3E 4F A2 B3 EC 06 +FD 27 C2 48 CE 06 30 4D 4E 43 08 45 43 48 4F 00 +B2 40 C2 48 62 43 38 40 05 00 B0 12 46 41 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 62 43 +28 42 F3 3F 0D 12 3D 40 B4 43 1B 42 32 20 9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 1B 42 -20 20 02 3C 66 43 2D 83 0C 9B 16 2C 58 4C 00 1E -1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 3D 41 -82 4C 1E 20 3C 40 20 00 9D 3F 0E 99 BB 27 CA 48 -00 00 1A 53 1E 53 B6 3F 1A 15 B0 12 18 60 19 17 -DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 C6 43 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FE 42 C8 43 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 41 02 43 52 00 30 40 E0 43 -0D 12 84 12 14 40 02 0D 0A 00 AA 43 AE 44 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 66 42 01 40 2E 4E -30 4D 2C 44 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D D8 43 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 68 44 02 23 53 00 0D 12 84 12 -6A 44 A4 44 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 98 44 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D A4 43 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 5E 44 -9C 44 EE 40 DC 44 B8 44 AA 43 62 48 FC 42 AE 44 -2E 43 01 2E 0E 93 E3 37 38 43 E2 3F D6 44 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 A8 47 -0A 40 22 00 7A 45 48 45 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D 22 45 -82 2E 22 00 0D 12 84 12 32 45 0A 40 AA 43 A8 47 -AE 44 FA 41 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 FC 46 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F FE 46 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D A6 47 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 +20 20 02 3C B6 43 2D 83 0C 9B 16 2C 58 4C 00 1E +1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 82 4C +1E 20 3D 41 3C 40 20 00 A4 3F 0E 99 BF 27 CA 48 +00 00 1A 53 1E 53 BA 3F 1A 15 B0 12 46 57 19 17 +DC 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 0A 44 +29 4F 8F 4E 00 00 7E 49 A5 3F 0C 44 2D 83 2F 83 +5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 +0C 4E 38 4F 3C 9F 39 4F 3E 4F 43 22 F9 98 00 00 +40 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F +1E 83 37 22 9B 24 28 43 0D 5B 45 4C 53 45 5D 00 +0D 12 84 12 0A 40 00 00 2A 45 1C 44 6E 46 28 49 +B0 40 98 44 14 40 06 5B 54 48 45 4E 5D 00 20 44 +76 44 3C 44 5A 44 14 40 06 5B 45 4C 53 45 5D 00 +20 44 88 44 3C 44 58 44 1E 40 04 5B 49 46 5D 00 +20 44 5A 44 B2 40 58 44 1E 40 05 0D 6B 6F 20 0A +FA 43 9A 40 84 40 B2 40 5A 44 48 44 0D 5B 54 48 +45 4E 5D 00 30 4D AC 44 09 5B 49 46 5D 00 0E 93 +3E 4F C6 27 30 4D B8 44 13 5B 44 45 46 49 4E 45 +44 5D 0D 12 84 12 1C 44 6E 46 D6 46 7A 48 EA 45 +C8 44 17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 +84 12 1C 44 6E 46 D6 46 FA 44 3D 41 2F 53 1E 83 +0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D +8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C +0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 +02 40 2E 4E 30 4D C8 42 02 21 BE 4F 00 00 3E 4F +30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 +30 4D E0 41 05 53 22 00 82 43 C0 1D 0D 12 84 12 +0A 40 1E 40 D8 48 0A 40 22 00 6E 46 6E 45 B2 40 +20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 +30 4D 82 43 05 2E 22 00 0D 12 84 12 58 45 0A 40 +FA 43 D8 48 EA 45 00 00 04 3C 23 00 B2 40 B2 1D +B2 1D 30 4D 54 45 02 23 1B 42 BE 1D 2C 4F 2F 83 +B0 12 46 40 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 +07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A +00 00 30 4D A6 45 04 23 53 00 0D 12 84 12 A8 45 +E2 45 2D 83 09 DE 09 93 E1 23 3D 41 30 4D D6 45 +04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F +30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F +F0 45 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 +D2 33 30 4D 6A 43 04 55 2E 00 0C 43 2F 83 8F 4E +00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 +9F 53 00 00 0E 63 84 12 9C 45 1C 44 0A 46 DA 45 +06 45 18 46 F4 45 FA 43 EA 45 84 45 02 2E 0E 93 +E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 +C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 +7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 +04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 +0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B +7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 +C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 +08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B +0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 +2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 +68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 +FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 +8F 4C 00 00 30 4D 5C 46 0E 3E 4E 55 4D 42 45 52 +1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 +6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 +0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 +19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 +E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D +32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 +BE 1D 0C 4E 0E 43 1E 15 3D 40 E0 47 7E 4C 6A 4C +7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 +6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 +3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 +38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 +E2 47 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 +00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 +20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C +69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 +0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 +3E 40 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 +4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 +30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 +09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 +8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D 98 45 +03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 40 +1C 44 6E 46 B0 40 B2 49 D6 46 9C 48 0A 4E 3E 4F +3D 40 B6 48 6D 27 3D 40 90 48 1A E2 BC 1D 14 24 +0E 12 3E 4F 30 41 B8 48 3E 4F 3D 40 90 48 19 20 +DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 +8E 4A 2A 3C 80 48 02 2C A2 53 C8 1D 1A 42 C8 1D +8A 4E FE FF 3E 4F 30 4D D6 48 0F 4C 49 54 45 52 +41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 +C8 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -B4 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D C8 44 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 40 62 48 7A 45 1E 48 9C 26 -3D 40 26 48 DE 3E 28 48 0A 4E 3E 4F 3D 40 42 48 -36 27 3D 40 18 48 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 44 48 3E 4F 3D 40 18 48 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 E4 49 CC 3F -4C 48 86 12 20 00 34 44 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 DC 43 BC 40 -12 48 12 44 44 44 14 40 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 4C 44 -14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 41 -3A 40 8C 48 68 48 86 41 42 4F 52 54 22 00 0D 12 -84 12 32 45 0A 40 2A 41 A8 47 AE 44 DC 45 01 27 -0D 12 84 12 62 48 7A 45 E2 45 34 40 60 48 AE 44 -00 00 83 5B 27 5D 0D 12 84 12 E0 48 0A 40 0A 40 -A8 47 A8 47 AE 44 F2 48 81 5B 82 43 BE 1D 30 4D -5A 44 01 5D B2 43 BE 1D 30 4D 12 49 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 62 48 7A 45 E2 45 F6 43 34 40 -60 48 44 44 34 40 54 49 0A 40 0A 40 A8 47 A8 47 -0A 40 A8 47 A8 47 AE 44 08 49 01 3A 30 12 A4 49 -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 62 48 7A 45 -72 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 41 5A 49 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 40 AE 44 A8 47 B6 49 0A 49 AE 44 -08 48 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D F2 47 06 43 52 45 41 54 -45 00 B0 12 60 49 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F E8 49 07 3A 4E 4F 4E 41 4D 45 30 12 A4 49 -2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 0E 4A -39 40 10 02 08 49 28 53 99 3F 12 43 05 44 45 46 -45 52 B0 12 60 49 BA 40 30 40 FC FF BA 40 E2 4D -FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 02 4A 82 49 -53 00 0D 12 82 93 BE 1D 06 24 84 12 F6 48 0A 40 -74 4A A8 47 AE 44 84 12 E0 48 74 4A AE 44 1A 4A -04 43 4F 44 45 00 B0 12 60 49 A2 82 C6 1D 82 43 -78 5C 0D 12 84 12 48 4D 1A 4D AE 44 7E 4A 07 48 -44 4E 43 4F 44 45 B2 40 1E 4D DA 1D EC 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 B6 49 6E 4D -A2 4D AE 44 A0 4A 07 43 4F 44 45 4E 4E 4D 30 12 -AA 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 6E 4D A2 4D AE 44 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -BE 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 82 4C -A8 47 0A 49 AE 4A AE 44 34 4A 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 4A 4B 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 40 00 00 26 44 62 48 7A 45 F8 47 -EE 43 34 40 E2 4B FC 43 14 40 06 5B 54 48 45 4E -5D 00 54 4B BC 4B 78 4B 9A 4B AE 44 FC 43 14 40 -06 5B 45 4C 53 45 5D 00 54 4B D2 4B 78 4B 98 4B -AE 44 14 40 04 5B 49 46 5D 00 54 4B 9A 4B 3A 40 -98 4B D0 43 14 40 05 0D 0A 6B 6F 20 AA 43 BC 40 -AC 40 3A 40 9A 4B 88 4B 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D F8 4B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 62 48 7A 45 E2 45 -06 4C AE 44 0C 4C 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 16 4C 3E 44 AE 44 3E 4C B2 4E -0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C BA 47 -06 4D 41 52 4B 45 52 00 B0 12 60 49 BA 40 85 12 -FC FF BA 40 3C 4C FE FF 28 83 8A 48 00 00 9A 42 -C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 C6 1D -9D 3E 2E 53 30 4D 5C 4A 05 44 4F 45 53 3E 1A 42 -BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D -74 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 0D 12 -84 12 22 4A 0A 40 10 00 0A 40 00 00 3E 40 0A 40 -00 00 A8 47 60 40 BE 4C 28 40 0A 40 C8 1D EE 43 -2E 44 A8 47 36 44 8E 4C 0A 40 CA 1D 36 44 AE 44 -DE 48 05 46 4F 52 54 48 85 12 D8 4C 42 4D AC 63 -E0 61 E2 4C 32 4B D4 42 FA 61 88 4D 14 4E 02 64 -AA 67 C6 66 00 00 9E 63 1C 49 42 46 00 00 C6 48 -09 41 53 53 45 4D 42 4C 45 52 85 12 D8 4C 44 5B -DC 5A 40 5A 00 55 92 53 00 00 08 59 00 00 68 5C -64 5D F6 53 AA 5D 10 5B 00 00 00 00 DA 54 0C 4D -10 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 D6 1D -08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 -30 4D 28 49 08 50 52 45 56 49 4F 55 53 00 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 60 45 04 4F 4E 4C 59 00 82 43 -CC 1D 30 4D 88 4C 0B 44 45 46 49 4E 49 54 49 4F -4E 53 92 42 CA 1D DA 1D 30 4D E8 4C 8E 4D A2 4D -B2 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 -10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B -89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F -3D 41 30 4D 64 4D 09 50 57 52 5F 53 54 41 54 45 -85 12 AA 4D 3E 4D 16 68 2E 45 09 52 53 54 5F 53 -54 41 54 45 92 42 0A 18 F6 4D 92 42 0C 18 F4 4D -EF 3F E6 4D 08 50 57 52 5F 48 45 52 45 00 92 42 -C6 1D F6 4D 92 42 C8 1D F4 4D 30 4D FA 4D 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 92 42 -C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 DA 37 -0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 96 4E FE FF 29 83 B9 40 E2 41 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 41 B2 49 FA 40 -B2 49 02 40 B2 49 02 42 B2 49 BC FF B2 49 0A 18 -B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 10 00 -00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 80 1C -39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 06 02 -B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 -42 02 B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 -26 03 F2 D3 22 03 F2 40 A5 00 41 01 F2 40 10 00 -40 01 D2 43 41 01 F2 40 A5 00 61 01 B2 40 48 00 -62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -F2 D0 10 00 2A 03 F2 40 A5 00 A1 04 F2 C0 40 00 -A2 04 B2 42 B0 01 1E 42 08 18 82 43 08 18 1E D2 -9E 01 B0 12 F8 40 00 42 38 40 C0 1D 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 -12 12 C4 1D 84 12 7A 45 E2 45 3E 44 34 40 88 4F -9E 46 34 40 A2 4F 9C 4F 8A 4F 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 A4 4F B2 41 C4 1D 3E 41 84 12 0A 40 2B 00 -7A 45 E2 45 3E 44 34 40 C0 4F 9E 46 34 40 60 48 -08 44 7A 45 9E 46 34 40 60 48 CC 4F 3E 5F E7 3F -32 B0 00 02 01 24 3E 4F 30 41 3E 40 28 00 B0 12 -6C 4F B0 12 D0 4F 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 40 29 00 1C 15 92 92 C0 1D C4 1D 02 20 -30 40 CE 49 12 12 C4 1D 92 53 C4 1D 84 12 7A 45 -9E 46 34 40 22 50 18 50 21 53 3E 90 10 00 84 2D -BE 2B 24 50 B2 41 C4 1D BA 3F 0D 12 84 12 62 48 -48 4F 34 50 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E -3E 4F 7A 90 23 00 29 20 92 53 C4 1D B0 12 6C 4F -B0 12 D0 4F 3C 40 00 03 0E 93 1C 24 3C 40 10 03 +12 46 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 +0E 4A 3E F3 30 4D 38 45 0A 41 4C 4C 4F 54 82 5E +C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 40 +02 0D 0A 00 FA 43 94 40 8A 48 18 45 42 45 1E 40 +0B 73 74 61 63 6B 20 65 6D 70 74 79 08 41 32 40 +0A 40 40 FF 4A 45 1E 40 09 46 52 41 4D 20 66 75 +6C 6C 08 41 B2 40 4E 49 38 49 0D 41 42 4F 52 54 +22 00 0D 12 84 12 58 45 0A 40 08 41 D8 48 EA 45 +68 46 02 27 0D 12 84 12 1C 44 6E 46 D6 46 B0 40 +B4 49 7C 45 C0 48 E2 44 07 5B 27 5D 0D 12 84 12 +A4 49 0A 40 0A 40 D8 48 D8 48 EA 45 B8 49 03 5B +82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D +30 45 11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 +1C 44 6E 46 D6 46 B0 40 B4 49 42 45 AC 40 0C 4A +0A 40 0A 40 D8 48 D8 48 0A 40 D8 48 D8 48 EA 45 +00 00 02 3A 30 12 62 4A 92 B3 C8 1D A2 63 C8 1D +0D 12 84 12 1C 44 6E 46 2A 4A 3D 41 5A D3 5A 53 +0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 +0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 +B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D +30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 +BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 40 0F 73 +74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 12 41 +CE 49 03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 40 +EA 45 D8 48 74 4A D0 49 EA 45 00 00 12 49 4D 4D +45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D +22 49 0C 43 52 45 41 54 45 00 B0 12 18 4A BA 40 +86 12 FC FF 8A 4A FE FF 3A 3D F4 43 0A 44 4F 45 +53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 +3D 41 30 4D 12 4A 0E 3A 4E 4F 4E 41 4D 45 30 12 +62 4A 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 +0E 4A 39 40 12 02 08 49 98 3F AC 4A 05 49 53 00 +0D 12 82 93 BC 1D 08 20 84 12 A4 49 2E 4B 3D 41 +BE 4F 02 00 3E 4F 30 4D 84 12 BC 49 0A 40 30 4B +D8 48 EA 45 C2 4A 08 43 4F 44 45 00 B0 12 18 4A +A2 82 C8 1D 61 3C 04 46 0E 48 44 4E 43 4F 44 45 +B2 40 1C 4C CC 1D F2 3F 00 00 0E 45 4E 44 43 4F +44 45 0D 12 84 12 74 4A 7A 4B 3D 41 92 42 D0 1D +CC 1D 5D 3C 46 4B 0E 43 4F 44 45 4E 4E 4D 30 12 +50 4B B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D +BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D +B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 +C8 1D 1A 42 C8 1D EF 3F 58 4B 0B 48 49 32 4C 4F +A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D +B9 3F E4 4B B2 40 F6 4B D0 1D 82 4E CE 1D 30 40 +7C 45 85 12 E2 4B E2 49 56 58 52 5A 64 58 EC 5D +26 46 D0 46 CC 5C CA 4B 1C 4B F6 4A 92 4A 72 58 +FE 4C 36 5A 00 00 00 00 85 12 E2 4B 78 53 FC 51 +1E 54 24 51 80 51 CE 51 AA 52 64 54 46 50 6A 51 +00 00 00 00 B8 4B 36 4F 00 00 D2 52 16 4C B2 40 +F6 4B CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 +00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 +5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 4A 4C +30 4D 5C 4C 0E 52 53 54 5F 52 45 54 39 40 42 18 +2C 49 3A 40 C8 1D B0 12 4A 4C 1A 42 CA 1D 3B 40 +10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B +89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D +0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 +B9 40 10 42 FE FF 29 83 B9 40 FA 41 FE FF 39 90 +AE FF F9 23 39 40 10 18 B2 49 BC FF 3B 40 10 00 +3A 40 3A 18 B0 12 4E 4C 82 43 4A 18 C7 3F F0 4C +B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F D8 49 0C 4D +41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 1C 44 +6E 46 D6 46 AC 40 1C 4D 10 45 B0 48 1E 4D 3E 4F +3D 41 B2 41 C6 1D B0 12 18 4A BA 40 85 12 FC FF +BA 40 EE 4C FE FF 28 83 8A 48 00 00 BA 40 82 40 +02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 +FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 6E 46 +D6 46 AC 40 88 4D 68 4D 3C 4E 3C 80 87 12 0A 24 +1C 53 02 20 2E 4E 06 3C BE 90 EE 4C 00 00 01 20 +3E 52 2E 83 21 53 30 41 80 47 AC 40 90 4D 84 4D +92 4D B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 +0A 4E 3D 15 B0 12 58 4D 15 20 3E 40 2B 00 B0 12 +58 4D 06 20 3E 40 2D 00 B0 12 58 4D 92 83 C6 1D +0E 12 1E 41 02 00 84 12 6E 46 80 47 AC 40 B4 49 +D2 4D 3E 51 3A 17 30 41 B0 12 98 4D 19 42 C8 1D +89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D +1A 42 C6 1D 3D 15 84 12 6E 46 80 47 AC 40 0A 4E +02 4E 3E 90 10 00 E6 2B 7C 2D 0C 4E A2 41 C6 1D +E1 3F 03 20 B0 12 F0 4D 43 3C 7A 90 23 00 24 20 +B0 12 A0 4D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 09 20 -3C 40 10 02 92 53 C4 1D B0 12 6C 4F B0 12 D0 4F -EB 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D -B0 12 F6 4F 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -F6 4F 92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 -0C 5E D8 3F B0 12 F6 4F FA 23 3C 50 10 00 B0 12 -DA 4F EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 -84 12 62 48 48 4F 08 51 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C5 3F B0 12 F6 4F E0 23 -3C 50 80 00 B0 12 DA 4F DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 40 00 13 A8 47 AE 44 0A 40 -2C 00 2A 50 FE 50 48 51 09 4B 2E 4E 0E DC A0 3F -20 4B 03 4D 4F 56 85 12 3E 51 00 40 52 51 05 4D -4F 56 2E 42 85 12 3E 51 40 40 00 00 03 41 44 44 -85 12 3E 51 00 50 6C 51 05 41 44 44 2E 42 85 12 -3E 51 40 50 78 51 04 41 44 44 43 00 85 12 3E 51 -00 60 86 51 06 41 44 44 43 2E 42 00 85 12 3E 51 -40 60 2C 51 04 53 55 42 43 00 85 12 3E 51 00 70 -A4 51 06 53 55 42 43 2E 42 00 85 12 3E 51 40 70 -B2 51 03 53 55 42 85 12 3E 51 00 80 C2 51 05 53 -55 42 2E 42 85 12 3E 51 40 80 F6 4A 03 43 4D 50 -85 12 3E 51 00 90 DC 51 05 43 4D 50 2E 42 85 12 -3E 51 40 90 D0 4A 04 44 41 44 44 00 85 12 3E 51 -00 A0 F6 51 06 44 41 44 44 2E 42 00 85 12 3E 51 -40 A0 E8 51 03 42 49 54 85 12 3E 51 00 B0 14 52 -05 42 49 54 2E 42 85 12 3E 51 40 B0 20 52 03 42 -49 43 85 12 3E 51 00 C0 2E 52 05 42 49 43 2E 42 -85 12 3E 51 40 C0 3A 52 03 42 49 53 85 12 3E 51 -00 D0 48 52 05 42 49 53 2E 42 85 12 3E 51 40 D0 -00 00 03 58 4F 52 85 12 3E 51 00 E0 62 52 05 58 -4F 52 2E 42 85 12 3E 51 40 E0 94 51 03 41 4E 44 -85 12 3E 51 00 F0 7C 52 05 41 4E 44 2E 42 85 12 -3E 51 40 F0 62 48 2A 50 9A 52 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F CE 51 03 52 52 43 -85 12 94 52 00 10 AC 52 05 52 52 43 2E 42 85 12 -94 52 40 10 B8 52 04 53 57 50 42 00 85 12 94 52 -80 10 C6 52 03 52 52 41 85 12 94 52 00 11 D4 52 -05 52 52 41 2E 42 85 12 94 52 40 11 E0 52 03 53 -58 54 85 12 94 52 80 11 00 00 04 50 55 53 48 00 -85 12 94 52 00 12 FA 52 06 50 55 53 48 2E 42 00 -85 12 94 52 40 12 54 52 04 43 41 4C 4C 00 85 12 -94 52 80 12 1A 53 0E 4A 0D 12 84 12 24 45 14 40 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 41 -EE 52 03 53 3E 3D 86 12 00 38 42 53 02 53 3C 00 -86 12 00 34 08 53 03 30 3E 3D 86 12 00 30 56 53 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C 6A 53 03 55 3E 3D 86 12 00 28 60 53 03 30 -3C 3E 86 12 00 24 7E 53 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 -C6 1D 0E 4A 30 4D 74 53 04 54 48 45 4E 00 1A 42 -C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 04 52 04 45 4C 53 -45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D -2F 83 8F 4A 00 00 E3 3F 18 53 05 42 45 47 49 4E -30 40 28 40 A8 53 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D -30 4D 88 52 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 96 53 -08 44 AE 44 4C 53 06 52 45 50 45 41 54 00 0D 12 -84 12 2A 54 AE 53 AE 44 5A 54 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D -EA 53 03 42 57 31 85 12 58 54 00 00 72 54 03 42 -57 32 85 12 58 54 00 00 7E 54 03 42 57 33 85 12 -58 54 00 00 96 54 3D 41 1A 42 C6 1D 28 4E B2 92 -C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 94 54 00 00 -B6 54 03 46 57 32 85 12 94 54 00 00 C2 54 03 46 -57 33 85 12 94 54 00 00 00 00 05 3F 47 4F 54 4F -3E 90 00 30 07 24 3E E0 00 04 3E B0 00 10 02 24 -3E E0 00 08 0D 12 84 12 E0 48 3C 48 AE 44 CE 54 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -F1 3F 62 48 48 4F 18 55 92 53 C4 1D 3E 40 2C 00 -84 12 7A 45 9E 46 34 40 60 48 F4 50 2E 55 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 46 54 04 52 52 43 -4D 00 85 12 12 55 50 00 5C 55 04 52 52 41 4D 00 -85 12 12 55 50 01 6A 55 04 52 4C 41 4D 00 85 12 -12 55 50 02 78 55 04 52 52 55 4D 00 85 12 12 55 -50 03 88 53 05 50 55 53 48 4D 85 12 12 55 00 15 -94 55 04 50 4F 50 4D 00 85 12 12 55 00 17 86 55 -06 52 52 43 4D 2E 41 00 85 12 12 55 40 00 B0 55 -06 52 52 41 4D 2E 41 00 85 12 12 55 40 01 C0 55 -06 52 4C 41 4D 2E 41 00 85 12 12 55 40 02 D0 55 -06 52 52 55 4D 2E 41 00 85 12 12 55 40 03 A2 55 -07 50 55 53 48 4D 2E 41 85 12 12 55 00 14 F0 55 -06 50 4F 50 4D 2E 41 00 85 12 12 55 00 16 8A 54 -05 43 41 4C 4C 41 0D 12 84 12 62 48 48 4F 20 56 -1B 42 C6 1D A2 53 C6 1D 6E 4E 3C 40 34 01 7E 90 -52 00 0B 20 7E 40 20 00 B0 12 F6 4F 5C 0E 0C DE -8B 4C 00 00 3E 4F 3D 41 30 4D 2C 53 7E 90 40 00 -0B 20 92 53 C4 1D 7E 40 20 00 B0 12 F6 4F EE 23 -1C 53 3E 40 2B 00 E8 3F A2 53 C6 1D 7E 90 23 00 -09 20 3C 40 3B 01 92 53 C4 1D B0 12 6C 4F BB 4F -02 00 DC 3F 7E 90 26 00 02 20 2C 53 F4 3F 7E 40 -28 00 1C 83 B0 12 6C 4F BB 4F 02 00 3E 40 29 00 -CB 3F 0D 12 84 12 62 48 48 4F AC 56 69 4E 3E 4F -3C 4F 2C 4C 1B 42 C6 1D A2 53 C6 1D 79 90 52 00 -0A 20 B0 12 F6 4F 5E 0E 5E 0E 0E DC 8B 4E 00 00 -0E 4B 3D 41 30 4D 79 90 23 00 0D 20 3C C0 40 00 -92 53 C4 1D A2 53 C6 1D B0 12 6C 4F BB 4F 02 00 -3E F0 0F 00 E8 3F 79 90 26 00 03 20 3C E0 E0 00 -EF 3F 3C C0 F0 00 79 90 40 00 12 20 92 53 C4 1D -B0 12 F6 4F D8 23 3C D0 10 00 3E 40 2B 00 B0 12 -F6 4F 92 92 C0 1D C4 1D CE 27 92 53 C4 1D CB 3F -3C D0 30 00 A2 53 C6 1D 3E 40 28 00 B0 12 6C 4F -BB 4F 02 00 3E 40 29 00 EA 3F 0D 12 84 12 62 48 -48 4F 54 57 3B 4F 2C 4B 69 4E 7E 40 20 00 79 90 -52 00 03 20 B0 12 F6 4F B0 3F 3C C0 F0 00 A2 53 -C6 1D 79 90 26 00 09 20 3C D0 60 00 92 53 C4 1D -B0 12 6C 4F BB 4F 02 00 A0 3F 3C D0 70 00 3E 40 -28 00 B0 12 6C 4F BB 4F 02 00 3E 40 29 00 E2 3F -0A 40 2C 00 A2 56 4A 57 D2 43 AE 44 5E 51 04 4D -4F 56 41 00 85 12 A0 57 C0 00 10 56 04 43 4D 50 -41 00 85 12 A0 57 D0 00 24 54 04 41 44 44 41 00 -85 12 A0 57 E0 00 E0 55 04 53 55 42 41 00 85 12 -A0 57 F0 00 0D 12 84 12 62 48 48 4F EE 57 69 4E -3E 4F 3C 40 00 18 79 90 52 00 05 20 B0 12 F6 4F -0E 4C 3D 41 30 4D 82 43 78 5C 79 90 23 00 0B 20 -92 53 C4 1D B0 12 6C 4F 2F 53 3E F0 0F 00 5E 0A -5E 0E 0C DE ED 3F 79 90 26 00 F2 27 79 90 40 00 -12 20 92 53 C4 1D B0 12 F6 4F E2 23 3E 40 2B 00 -92 53 C4 1D B0 12 F6 4F 92 92 C0 1D C4 1D D8 27 -92 53 C4 1D D5 3F 3E 40 28 00 B0 12 6C 4F 8F 4E -00 00 3E 40 29 00 B0 12 F6 4F 3E 4F 3E F0 0F 00 -0C DE EA 3F 0D 12 84 12 62 48 48 4F 7E 58 3C 4F -69 4E 3E 40 20 00 79 90 52 00 BA 27 82 43 78 5C -79 90 26 00 08 20 92 53 C4 1D B0 12 6C 4F 2F 53 -3E F0 0F 00 BE 3F 3E 40 28 00 B0 12 6C 4F F7 3F -B2 4F C4 1D 1B 42 C6 1D A2 53 C6 1D 0C 4E 3E 4F -1C D2 78 5C 82 43 78 5C 3C DE 8B 4C 00 00 30 4D -0A 40 C4 1D 2E 44 0A 40 2C 00 E4 57 74 58 B0 58 -3A 40 3E 51 AE 57 04 4D 4F 56 58 00 85 12 D0 58 -40 00 00 40 E6 58 06 4D 4F 56 58 2E 41 00 85 12 -D0 58 00 00 40 40 F6 58 06 4D 4F 56 58 2E 42 00 -85 12 D0 58 40 00 40 40 CA 57 04 41 44 44 58 00 -85 12 D0 58 40 00 00 50 1A 59 06 41 44 44 58 2E -41 00 85 12 D0 58 00 00 40 50 2A 59 06 41 44 44 -58 2E 42 00 85 12 D0 58 40 00 40 50 3C 59 05 41 -44 44 43 58 85 12 D0 58 40 00 00 60 4E 59 07 41 -44 44 43 58 2E 41 85 12 D0 58 00 00 40 60 5E 59 -07 41 44 44 43 58 2E 42 85 12 D0 58 40 00 40 60 -D8 57 05 53 55 42 43 58 85 12 D0 58 40 00 00 70 -82 59 07 53 55 42 43 58 2E 41 85 12 D0 58 00 00 -40 70 92 59 07 53 55 42 43 58 2E 42 85 12 D0 58 -40 00 40 70 A4 59 04 53 55 42 58 00 85 12 D0 58 -40 00 00 80 B6 59 06 53 55 42 58 2E 41 00 85 12 -D0 58 00 00 40 80 C6 59 06 53 55 42 58 2E 42 00 -85 12 D0 58 40 00 40 80 BC 57 04 43 4D 50 58 00 -85 12 D0 58 40 00 00 90 EA 59 06 43 4D 50 58 2E -41 00 85 12 D0 58 00 00 40 90 FA 59 06 43 4D 50 -58 2E 42 00 85 12 D0 58 40 00 40 90 CC 53 05 44 -41 44 44 58 85 12 D0 58 40 00 00 A0 1E 5A 07 44 -41 44 44 58 2E 41 85 12 D0 58 00 00 40 A0 2E 5A -07 44 41 44 44 58 2E 42 85 12 D0 58 40 00 40 A0 -0C 5A 04 42 49 54 58 00 85 12 D0 58 40 00 00 B0 -52 5A 06 42 49 54 58 2E 41 00 85 12 D0 58 00 00 -40 B0 62 5A 06 42 49 54 58 2E 42 00 85 12 D0 58 -40 00 40 B0 74 5A 04 42 49 43 58 00 85 12 D0 58 -40 00 00 C0 86 5A 06 42 49 43 58 2E 41 00 85 12 -D0 58 00 00 40 C0 96 5A 06 42 49 43 58 2E 42 00 -85 12 D0 58 40 00 40 C0 A8 5A 04 42 49 53 58 00 -85 12 D0 58 40 00 00 D0 BA 5A 06 42 49 53 58 2E -41 00 85 12 D0 58 00 00 40 D0 CA 5A 06 42 49 53 -58 2E 42 00 85 12 D0 58 40 00 40 D0 6E 52 04 58 -4F 52 58 00 85 12 D0 58 40 00 00 E0 EE 5A 06 58 -4F 52 58 2E 41 00 85 12 D0 58 00 00 40 E0 FE 5A -06 58 4F 52 58 2E 42 00 85 12 D0 58 40 00 40 E0 -70 59 04 41 4E 44 58 00 85 12 D0 58 40 00 00 F0 -22 5B 06 41 4E 44 58 2E 41 00 85 12 D0 58 00 00 -40 F0 32 5B 06 41 4E 44 58 2E 42 00 85 12 D0 58 -40 00 40 F0 0A 40 C4 1D 2E 44 62 48 E4 57 B0 58 -3A 40 94 52 D8 59 04 52 52 43 58 00 85 12 54 5B -40 00 00 10 66 5B 06 52 52 43 58 2E 41 00 85 12 -54 5B 00 00 40 10 76 5B 06 52 52 43 58 2E 42 00 -85 12 54 5B 40 00 40 10 88 5B 04 52 52 55 58 00 -85 12 54 5B 40 01 00 10 9A 5B 06 52 52 55 58 2E -41 00 85 12 54 5B 00 01 40 10 AA 5B 06 52 52 55 -58 2E 42 00 85 12 54 5B 40 01 40 10 BC 5B 05 53 -57 50 42 58 85 12 54 5B 40 00 80 10 CE 5B 07 53 -57 50 42 58 2E 41 85 12 54 5B 00 00 80 10 DE 5B -04 52 52 41 58 00 85 12 54 5B 40 00 00 11 F0 5B -06 52 52 41 58 2E 41 00 85 12 54 5B 00 00 40 11 -00 5C 06 52 52 41 58 2E 42 00 85 12 54 5B 40 00 -40 11 12 5C 04 53 58 54 58 00 85 12 54 5B 40 00 -80 11 24 5C 06 53 58 54 58 2E 41 00 85 12 54 5B -00 00 80 11 00 56 05 50 55 53 48 58 85 12 54 5B -40 00 00 12 46 5C 07 50 55 53 48 58 2E 41 85 12 -54 5B 00 00 40 12 56 5C 07 50 55 53 48 58 2E 42 -85 12 54 5B 40 00 40 12 00 00 34 5C 03 52 50 54 -0D 12 84 12 62 48 48 4F 8A 5C 29 4E 7E 40 20 00 -79 90 52 00 06 20 B0 12 F6 4F 03 24 3E D0 80 00 -05 3C B0 12 6C 4F 1E 83 3E F0 0F 00 82 4E 78 5C -3E 4F 3D 41 30 4D D2 C3 23 02 E2 B2 60 02 02 24 -30 40 E2 41 1A 52 04 20 19 62 06 20 92 43 14 20 -A2 93 02 20 07 24 0A 5A 49 69 82 4A 16 20 C2 49 -18 20 0A 3C C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 -17 20 89 10 C2 49 18 20 B0 12 3E 5D 5A 53 FC 23 -39 40 05 00 D2 49 14 20 4E 06 82 93 46 06 05 24 -92 B3 6C 06 FD 27 C2 93 4C 06 59 83 F3 2F 19 83 -0B 30 F2 43 4E 06 82 93 46 06 03 24 92 B3 6C 06 -FD 27 5A 92 4C 06 F3 23 30 41 1A 43 E1 3F 19 43 -3A 43 8A 10 C2 4A 4E 06 82 93 46 06 05 24 92 B3 -6C 06 FD 27 C2 93 4C 06 19 83 F3 23 5A 42 4C 06 -30 41 7C 5C 08 52 45 41 44 5F 53 57 58 00 1C D3 -F2 40 51 00 19 20 B0 12 B6 5C 38 20 B0 12 3E 5D -6A 53 04 24 FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 -03 43 19 53 39 90 01 02 F6 23 F2 43 4E 06 3C C0 -03 00 D2 D3 23 02 30 41 34 54 09 57 52 49 54 45 -5F 53 57 58 2C D3 F0 40 58 00 5F C2 B0 12 B6 5C -15 20 3A 40 FE FF 29 43 B0 12 42 5D D2 49 00 1E -4E 06 03 43 19 53 39 90 00 02 F8 23 39 40 03 00 -B0 12 40 5D 7A C0 E1 00 6A 92 D9 27 8C 10 1C 52 -4C 06 D2 D3 23 02 0D 12 84 12 18 43 14 40 0B 3C -20 53 44 20 45 72 72 6F 72 21 0C 5E 2F 83 8F 4E -00 00 B2 40 10 00 DC 1D 0E 4C 84 12 EE 44 36 41 -B0 12 8C 41 0E 93 9C 24 E2 B2 60 02 99 20 B2 40 -81 A9 40 06 B2 40 30 00 46 06 D2 D3 25 02 B2 D0 -C0 04 0C 02 92 C3 40 06 39 42 B0 12 40 5D D2 C3 +3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D +89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 +10 02 B0 12 A0 4D F0 3F 7A 90 40 00 14 20 3C 40 +20 00 B0 12 EC 4D 0C 20 3C D0 10 00 3E 40 2B 00 +B0 12 F0 4D 92 92 C2 1D C6 1D 02 24 92 53 C6 1D +8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 D8 4D F2 3F +03 20 B0 12 F0 4D F5 3F 7A 90 26 00 03 20 3C D0 +82 00 D7 3F 3C D0 80 00 B0 12 D8 4D EA 3F 0C 43 +1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D +19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D +82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 +49 00 0D 12 84 12 0A 40 00 13 D8 48 EA 45 0A 40 +2C 00 CE 4E 12 4E 1C 44 D8 4E B0 4E 1E 4F 3D 41 +2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 +0E 4F 00 40 2A 4F 0A 4D 4F 56 2E 42 85 12 0E 4F +40 40 00 00 06 41 44 44 85 12 0E 4F 00 50 44 4F +0A 41 44 44 2E 42 85 12 0E 4F 40 50 50 4F 08 41 +44 44 43 00 85 12 0E 4F 00 60 5E 4F 0C 41 44 44 +43 2E 42 00 85 12 0E 4F 40 60 96 4B 08 53 55 42 +43 00 85 12 0E 4F 00 70 7C 4F 0C 53 55 42 43 2E +42 00 85 12 0E 4F 40 70 8A 4F 06 53 55 42 85 12 +0E 4F 00 80 9A 4F 0A 53 55 42 2E 42 85 12 0E 4F +40 80 A6 4F 06 43 4D 50 85 12 0E 4F 00 90 B4 4F +0A 43 4D 50 2E 42 85 12 0E 4F 40 90 00 00 08 44 +41 44 44 00 85 12 0E 4F 00 A0 CE 4F 0C 44 41 44 +44 2E 42 00 85 12 0E 4F 40 A0 FC 4E 06 42 49 54 +85 12 0E 4F 00 B0 EC 4F 0A 42 49 54 2E 42 85 12 +0E 4F 40 B0 F8 4F 06 42 49 43 85 12 0E 4F 00 C0 +06 50 0A 42 49 43 2E 42 85 12 0E 4F 40 C0 12 50 +06 42 49 53 85 12 0E 4F 00 D0 20 50 0A 42 49 53 +2E 42 85 12 0E 4F 40 D0 00 00 06 58 4F 52 85 12 +0E 4F 00 E0 3A 50 0A 58 4F 52 2E 42 85 12 0E 4F +40 E0 6C 4F 06 41 4E 44 85 12 0E 4F 00 F0 54 50 +0A 41 4E 44 2E 42 85 12 0E 4F 40 F0 1C 44 CE 4E +12 4E 74 50 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 +0C DA 4D 3F 2C 50 06 52 52 43 85 12 6C 50 00 10 +86 50 0A 52 52 43 2E 42 85 12 6C 50 40 10 C0 4F +08 53 57 50 42 00 85 12 6C 50 80 10 92 50 06 52 +52 41 85 12 6C 50 00 11 AE 50 0A 52 52 41 2E 42 +85 12 6C 50 40 11 A0 50 06 53 58 54 85 12 6C 50 +80 11 00 00 08 50 55 53 48 00 85 12 6C 50 00 12 +D4 50 0C 50 55 53 48 2E 42 00 85 12 6C 50 40 12 +C8 50 08 43 41 4C 4C 00 85 12 6C 50 80 12 1A 53 +0E 4A 84 12 5E 46 1E 40 0D 6F 75 74 20 6F 66 20 +62 6F 75 6E 64 73 12 41 F2 50 06 53 3E 3D 86 12 +00 38 1A 51 04 53 3C 00 86 12 00 34 E2 50 06 30 +3E 3D 86 12 00 30 2E 51 04 30 3C 00 86 12 00 30 +6A 4B 04 55 3C 00 86 12 00 2C 42 51 06 55 3E 3D +86 12 00 28 38 51 06 30 3C 3E 86 12 00 24 56 51 +04 30 3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 +C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D DC 4F +08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 +29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 +30 4D 4C 51 08 45 4C 53 45 00 1A 42 C8 1D BA 40 +00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F +BA 50 0A 42 45 47 49 4E 30 40 32 40 A4 51 0A 55 +4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 +0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA +89 48 00 00 A2 53 C8 1D 30 4D 60 50 0A 41 47 41 +49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 +4C 45 0D 12 84 12 6E 51 04 45 EA 45 C2 51 0C 52 +45 50 45 41 54 00 0D 12 84 12 02 52 86 51 EA 45 +32 52 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F +98 42 C8 1D 00 00 30 4D 1E 52 06 42 57 31 85 12 +30 52 00 00 4A 52 06 42 57 32 85 12 30 52 00 00 +56 52 06 42 57 33 85 12 30 52 00 00 6E 52 3D 41 +1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B +BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D +00 00 06 46 57 31 85 12 6C 52 00 00 92 52 06 46 +57 32 85 12 6C 52 00 00 9E 52 06 46 57 33 85 12 +6C 52 00 00 0C 52 08 47 4F 54 4F 00 2F 83 8F 4E +00 00 3E 40 00 3C 0D 12 84 12 A4 49 B0 48 EA 45 +00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 +00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F D8 4E +0A 40 2C 00 6E 46 80 47 AC 40 B4 49 1C 44 CE 4E +B0 4E 04 53 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E +0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 +EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E +62 52 08 52 52 43 4D 00 85 12 EE 52 50 00 32 53 +08 52 52 41 4D 00 85 12 EE 52 50 01 40 53 08 52 +4C 41 4D 00 85 12 EE 52 50 02 4E 53 08 52 52 55 +4D 00 85 12 EE 52 50 03 60 51 0A 50 55 53 48 4D +85 12 EE 52 00 15 6A 53 08 50 4F 50 4D 00 85 12 +EE 52 00 17 D2 C3 23 02 E2 B2 60 02 02 24 30 40 +FA 41 1A 52 04 20 19 62 06 20 92 43 14 20 C2 4A +15 20 8A 10 C2 4A 16 20 C2 49 17 20 89 10 C2 49 +18 20 B0 12 F8 53 5A 53 FC 23 39 40 05 00 D2 49 +14 20 4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 +C2 93 4C 06 59 83 F3 2F 19 83 0B 30 F2 43 4E 06 +82 93 46 06 03 24 92 B3 6C 06 FD 27 5A 92 4C 06 +F3 23 30 41 1A 43 E1 3F 19 43 3A 43 8A 10 C2 4A +4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 +4C 06 19 83 F3 23 5A 42 4C 06 30 41 5C 53 12 52 +5F 53 45 43 54 5F 57 58 1C D3 F2 40 51 00 19 20 +B0 12 84 53 38 20 B0 12 F8 53 6A 53 04 24 FB 23 +D9 42 4C 06 FF 1D F2 43 4E 06 03 43 19 53 39 90 +01 02 F6 23 F2 43 4E 06 3C C0 03 00 D2 D3 23 02 +30 41 B6 52 12 57 5F 53 45 43 54 5F 57 58 2C D3 +F0 40 58 00 A5 CB B0 12 84 53 15 20 3A 40 FE FF +29 43 B0 12 FC 53 D2 49 00 1E 4E 06 03 43 19 53 +39 90 00 02 F8 23 39 40 03 00 B0 12 FA 53 7A C0 +E1 00 6A 82 D9 27 8C 10 1C 52 4C 06 D2 D3 23 02 +84 12 70 43 1E 40 0B 3C 20 53 44 20 45 72 72 6F +72 21 C4 54 2F 83 8F 4E 00 00 B2 40 10 00 BE 1D +0E 4C 84 12 2A 46 12 41 B0 12 58 41 E2 B2 60 02 +8A 20 B2 40 81 A9 40 06 B2 40 30 00 46 06 D2 D3 +25 02 B2 D0 C0 04 0C 02 92 C3 40 06 39 40 6E 01 +29 83 89 43 02 20 FC 23 39 42 B0 12 FA 53 D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 00 40 18 20 -B0 12 3A 5D 02 24 30 40 EC 5D B0 12 3E 5D 7A 93 +B0 12 F4 53 02 24 30 40 A6 54 B0 12 F8 53 7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 B2 40 00 48 -18 20 B0 12 3A 5D 29 42 B0 12 40 5D 92 43 14 20 +18 20 B0 12 F4 53 29 42 B0 12 FA 53 92 43 14 20 82 43 16 20 78 43 3C 42 B2 40 00 77 18 20 B0 12 -3A 5D B2 40 40 69 18 20 B0 12 F8 5C 03 24 58 83 +F4 53 B2 40 40 69 18 20 B0 12 B2 53 03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 00 50 18 20 -B0 12 F8 5C D0 23 92 D3 40 06 82 43 46 06 92 C3 -40 06 09 43 B0 12 6E 5D 38 40 00 1E 92 48 C6 01 -04 20 92 48 C8 01 06 20 5A 48 C2 01 92 43 02 20 -7A 80 06 00 0F 24 7A 82 0D 24 A2 43 02 20 6A 53 -09 24 5A 53 07 24 6A 52 05 24 3A 50 0B 20 0C 4A -30 40 F2 5D 09 43 B0 12 6E 5D D2 48 0D 00 12 20 -19 48 0E 00 82 49 08 20 1A 48 16 00 0A 93 02 20 -1A 48 24 00 82 4A 0A 20 09 5A 82 49 0C 20 09 5A -A2 93 02 20 04 24 82 49 0E 20 39 50 20 00 19 82 -12 20 19 82 12 20 82 49 10 20 92 42 02 20 2C 20 -30 41 B0 12 AA 40 39 40 E0 00 29 83 89 43 38 20 -FC 23 82 43 32 20 30 41 92 4B 0E 00 22 20 92 4B -10 00 24 20 5A 42 23 20 58 42 22 20 92 93 02 20 -08 24 59 42 24 20 89 10 0A 59 88 10 08 58 0A 6A -88 10 08 58 30 41 82 43 1C 20 92 42 0E 20 1A 20 -C2 93 24 20 03 20 92 93 22 20 14 24 92 42 22 20 -D0 04 92 42 24 20 D2 04 92 42 12 20 C8 04 92 42 -E4 04 1A 20 92 42 E6 04 1C 20 92 52 10 20 1A 20 -82 63 1C 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 -24 20 B0 12 A6 5F 5A 4B 03 00 82 5A 1A 20 82 63 -1C 20 30 41 09 93 07 24 F8 90 20 00 00 1E 03 20 -18 53 19 83 F9 23 30 41 1B 42 32 20 82 43 1E 20 -B2 90 00 02 20 20 AB 20 BB 80 00 02 12 00 8B 73 -14 00 DB 53 03 00 DB 92 12 20 03 00 14 28 CB 43 -03 00 B0 12 78 5F 1A 52 08 20 09 43 B0 12 6E 5D -8B 43 10 00 9B 48 00 1E 0E 00 92 93 02 20 03 24 -9B 48 02 1E 10 00 B2 40 00 02 20 20 8B 93 14 00 -0B 20 92 9B 12 00 1E 20 82 2C BB 90 00 02 12 00 -03 2C 92 4B 12 00 20 20 B0 12 E6 5F 1A 42 1A 20 -19 42 1C 20 6C 3E 3C 42 3B 40 38 20 09 43 CB 93 -02 00 10 24 9B 92 24 20 0C 00 04 20 9B 92 22 20 -0A 00 07 24 09 4B 3B 50 1C 00 3B 90 18 21 EF 23 -0C 5C 30 41 0C 43 82 4B 32 20 8B 49 00 00 09 93 -0A 24 99 52 C4 1D 16 00 4A 93 05 34 C9 93 02 00 -02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00 9B 42 -1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20 8B 48 -08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 -1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E 12 00 -9B 48 1E 1E 14 00 82 43 1E 20 6A 93 5C 27 C9 37 -8B 43 16 00 7A 93 02 24 07 38 95 3F B2 40 1C 21 -CA 40 B2 40 44 43 70 42 9B 42 C0 1D 18 00 9B 82 -C4 1D 18 00 9B 42 C2 1D 1A 00 9B 52 C4 1D 1A 00 -82 3F CB 43 02 00 2B 4B 82 4B 32 20 0B 93 06 24 -92 4B 16 00 1E 20 B0 12 66 60 22 C3 30 41 1B 42 -32 20 0B 93 FB 27 EB 93 02 00 04 20 B0 12 42 66 -B0 12 0A 66 CB 93 02 00 E4 37 1E 4B 18 00 9F 4B -1A 00 00 00 31 50 06 00 3D 41 B0 12 62 61 02 24 -30 40 36 43 B2 40 3C 1D CA 40 B2 40 72 42 70 42 -30 40 18 43 2E 4E 85 52 45 41 44 22 5A 43 19 3C -A2 4C 86 57 52 49 54 45 22 00 6A 43 12 3C 96 4D -84 44 45 4C 22 00 6A 42 0C 3C E6 4A 05 43 4C 4F -53 45 B0 12 7E 61 30 4D 50 4C 85 4C 4F 41 44 22 -7A 43 2F 83 8F 4E 00 00 0E 4A 82 93 BE 1D 0B 24 -0D 12 84 12 0A 40 0A 40 A8 47 A8 47 32 45 0A 40 -36 62 A8 47 AE 44 0D 12 84 12 0A 40 22 00 7A 45 -F8 47 34 62 3D 41 36 4F 0E 56 82 4E 36 20 1C 43 -92 42 2C 20 22 20 92 42 2E 20 24 20 0E 96 8D 24 -F6 90 3A 00 01 00 01 20 26 53 F6 90 5C 00 00 00 -08 20 16 53 92 42 02 20 22 20 82 43 24 20 0E 96 -70 24 82 46 34 20 B0 12 A6 5F 35 40 20 00 A2 93 -02 20 04 24 92 92 22 20 02 20 02 24 15 42 12 20 -B0 12 8C 60 2C 43 0A 43 08 4A 58 0E 08 58 82 48 -30 20 C8 93 00 1E 61 24 39 42 F8 96 00 1E 04 20 -18 53 19 83 FA 23 16 53 F6 90 2E 00 FF FF 19 24 -39 50 03 00 B0 12 04 60 06 20 F6 90 5C 00 FF FF -29 24 0E 96 27 28 16 42 34 20 1A 53 3A 90 10 00 -DB 23 92 53 1A 20 82 63 1C 20 15 83 D1 23 2C 42 -3C 3C F6 90 2E 00 FE FF EE 27 B0 12 04 60 EB 23 -39 40 03 00 F8 96 00 1E 04 20 18 53 19 83 FA 23 -09 3C 0E 96 E0 2F F6 90 5C 00 FF FF DC 23 B0 12 -04 60 D9 23 18 42 30 20 92 48 1A 1E 22 20 92 48 -14 1E 24 20 F8 B0 10 00 0B 1E 14 24 82 93 24 20 -06 20 82 93 22 20 03 20 92 42 02 20 22 20 0E 96 -8E 2F 92 42 22 20 2C 20 92 42 24 20 2E 20 8F 43 -00 00 03 3C 2A 4F B0 12 96 60 35 40 D4 40 36 40 -E2 40 3A 4F 3E 4F 0A 93 04 24 7A 93 3C 20 0C 93 -01 20 30 4D 0D 12 84 12 18 43 14 40 0B 3C 20 4F -70 65 6E 45 72 72 6F 72 3A 40 0A 5E 26 4C 05 5B -50 46 41 5D 2E 53 2E 4E 30 4D EC 61 04 42 4F 4F -54 00 39 40 20 5E 2E 93 01 2C 30 41 E2 B2 60 02 -02 24 10 49 02 00 89 12 3F 40 7E 1C 8F 43 00 00 -82 43 BE 1D B2 40 00 1C 00 1C 31 40 E0 1C 84 12 -14 40 0F 4C 4F 41 44 22 20 42 4F 4F 54 2E 34 54 -48 22 3A 40 90 48 1A 93 BB 20 0C 93 C3 23 30 4D -C6 61 04 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 -32 20 B0 12 18 60 1E 82 32 20 30 4D 2C 43 12 12 -2A 20 18 42 02 20 08 58 2A 41 82 9A 0A 20 A6 24 -1A 52 08 20 09 43 B0 12 6E 5D 09 43 28 93 03 24 -89 93 02 1E 03 20 89 93 00 1E 07 24 09 58 39 90 -00 02 F4 23 91 53 00 00 E7 3F 0C 43 6A 41 B9 43 -00 1E 28 93 0F 24 B9 40 FF 0F 02 1E 09 11 8A 10 -09 5A 5A 41 01 00 0A 11 09 10 82 4A 28 20 82 49 -26 20 07 3C 09 11 C2 49 26 20 C2 4A 27 20 82 43 -28 20 3A 41 82 4A 2A 20 30 41 0A 12 1A 52 08 20 -09 43 B0 12 B4 5D 3A 41 1A 52 0C 20 09 43 B0 12 -B4 5D F2 B0 40 00 A2 04 29 20 F2 B0 10 00 A2 04 -FC 27 5A 42 B0 04 4A 11 59 42 B4 04 F2 40 20 00 -C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 D2 42 B5 04 -C8 04 19 52 E4 04 D2 42 B2 04 C0 04 B2 40 00 08 -C8 04 1A 52 E4 04 92 42 B6 04 C0 04 B2 80 BC 07 -C0 04 B2 40 00 02 C8 04 19 52 E4 04 30 41 22 2A -2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D 7C 2E 29 92 -06 38 39 80 03 00 B0 12 5E 65 39 40 03 00 7A 4B -C8 4A 00 1E 82 9B 36 20 12 28 0D 12 3D 40 0F 00 -3C 40 0E 65 7A 9C F3 27 1D 83 FC 23 3D 41 6A 9C -E6 27 3A 80 21 00 EB 3B 18 53 19 83 E8 23 09 93 -06 24 F8 40 20 00 00 1E 18 53 19 83 FA 23 30 41 -2A 93 DC 20 2C 93 0E 24 0C 93 AB 24 0D 12 84 12 -14 40 0C 3C 20 57 72 69 74 65 45 72 72 6F 72 00 -3A 40 0A 5E B0 12 1C 64 92 42 26 20 22 20 92 42 -28 20 24 20 B0 12 9A 64 B0 12 8C 60 18 42 30 20 -F8 40 20 00 0B 1E B0 12 B2 64 88 43 0C 1E 88 4A -0E 1E 88 49 10 1E 88 49 12 1E 98 42 24 20 14 1E -98 42 22 20 1A 1E 88 43 1C 1E 88 43 1E 1E 1C 43 -1B 42 34 20 82 9B 36 20 C9 27 FB 90 2E 00 00 00 -C5 27 39 40 0B 00 B0 12 2E 65 B0 12 4C 66 2A 43 -B0 12 96 60 0C 93 BA 23 30 4D 1A 4B 04 00 19 4B -06 00 B0 12 6E 5D B0 12 B2 64 18 4B 08 00 88 49 -12 1E 88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E -98 4B 14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 -B4 5D 9B 52 1E 20 12 00 8B 63 14 00 1A 42 1A 20 -19 42 1C 20 30 40 B4 5D B2 40 00 02 1E 20 1B 42 -32 20 B0 12 42 66 82 43 1E 20 DB 53 03 00 DB 92 -12 20 03 00 25 20 CB 43 03 00 B0 12 78 5F 08 12 -0A 12 B0 12 1C 64 2A 91 08 24 B0 12 9A 64 2A 41 -1A 52 08 20 09 43 B0 12 6E 5D 3A 41 38 41 98 42 -26 20 00 1E 92 93 02 20 03 24 98 42 28 20 02 1E -B0 12 9A 64 9B 42 26 20 0E 00 9B 42 28 20 10 00 -30 40 E6 5F D2 61 05 57 52 49 54 45 B0 12 58 66 -30 4D 58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B -15 00 5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 -1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 -19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 -CB 4A 03 00 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 -FF 01 82 4A 1E 20 B0 12 88 60 30 4D 0C 93 3B 20 -38 90 E0 01 03 2C C8 93 20 1E 02 24 7C 40 E5 00 -C8 4C 00 1E B0 12 4C 66 B0 12 84 5F 82 4A 2A 20 -0B 4A 1A 52 08 20 09 43 B0 12 6E 5D 1A 48 00 1E -88 43 00 1E 92 93 02 20 09 24 19 48 02 1E 88 43 -02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 0E 24 -82 4A 22 20 82 49 24 20 B0 12 84 5F 0B 9A E6 27 -0A 12 0A 4B B0 12 9A 64 3A 41 DA 3F 0A 4B B0 12 -9A 64 B0 12 7E 61 30 4D EA 44 08 54 45 52 4D 32 -53 44 22 00 0D 12 84 12 E6 61 0A 40 02 00 28 40 -F8 47 36 62 C6 67 B0 12 B8 41 0A 43 92 B3 EC 06 -FD 27 59 42 CC 06 69 92 11 24 CA 49 00 1E 1A 53 -79 90 0A 00 05 20 84 12 DC 43 EC 67 B0 12 B8 41 -3A 90 00 02 EB 2B B0 12 58 66 E7 3F 92 B3 EC 06 -FD 27 F2 90 0A 00 CC 06 F9 23 82 4A 1E 20 B0 12 -7E 61 3D 41 30 4D +B0 12 B2 53 D0 23 92 D3 40 06 82 43 46 06 92 C3 +40 06 0A 43 09 43 B0 12 28 54 38 40 00 1E 92 48 +C6 01 04 20 92 48 C8 01 06 20 5C 48 C2 01 7C 80 +0C 00 08 24 5C 53 06 24 6C 52 04 24 3C 50 07 20 +30 40 AC 54 09 43 B0 12 28 54 A2 43 2C 20 19 48 +0E 00 82 49 08 20 1A 48 24 00 82 4A 0A 20 09 5A +82 49 0C 20 09 5A 58 48 0D 00 82 48 12 20 09 88 +09 88 82 49 10 20 30 41 82 43 32 20 30 40 56 41 +92 4B 0E 00 22 20 92 4B 10 00 24 20 5A 42 23 20 +58 42 22 20 59 42 24 20 89 10 0A D9 88 10 08 58 +0A 6A 88 10 08 58 30 41 1A 52 08 20 09 43 FC 3E +92 42 22 20 D0 04 92 42 24 20 D2 04 92 42 12 20 +C8 04 92 42 E4 04 1A 20 92 42 E6 04 1C 20 92 52 +10 20 1A 20 82 63 1C 20 30 41 92 4B 0E 00 22 20 +92 4B 10 00 24 20 B0 12 30 56 5A 4B 03 00 82 5A +1A 20 82 63 1C 20 30 41 3C 42 3B 40 38 20 09 43 +CB 93 02 00 10 24 9B 92 24 20 0C 00 04 20 9B 92 +22 20 0A 00 A3 25 09 4B 3B 50 1C 00 3B 90 18 21 +EF 23 0C 5C 9B 3D 0C 43 82 4B 32 20 8B 49 00 00 +09 93 0A 24 99 52 C6 1D 16 00 4A 93 05 34 C9 93 +02 00 02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00 +9B 42 1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20 +8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 +9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E +12 00 9B 48 1E 1E 14 00 82 43 1E 20 6A 93 1A 24 +A4 37 8B 43 16 00 7A 93 02 24 07 38 35 3C B2 40 +1C 21 A0 40 B2 40 94 43 D2 42 9B 42 C2 1D 18 00 +9B 82 C6 1D 18 00 9B 42 C4 1D 1A 00 9B 52 C6 1D +1A 00 22 3C 30 41 1B 42 32 20 82 43 1E 20 B2 90 +00 02 20 20 3F 20 BB 80 00 02 12 00 8B 73 14 00 +DB 53 03 00 DB 92 12 20 03 00 0E 28 CB 43 03 00 +B0 12 00 56 B0 12 28 56 8B 43 10 00 9B 48 00 1E +0E 00 9B 48 02 1E 10 00 B2 40 00 02 20 20 8B 93 +14 00 0B 20 92 9B 12 00 1E 20 1C 2C BB 90 00 02 +12 00 03 2C 92 4B 12 00 20 20 B0 12 5A 56 1A 42 +1A 20 19 42 1C 20 38 3E CB 43 02 00 2B 4B 82 4B +32 20 0B 93 06 24 92 4B 16 00 1E 20 B0 12 88 57 +22 C3 30 41 1B 42 32 20 0B 93 FB 27 EB 92 02 00 +04 20 B0 12 46 5B B0 12 36 5C CB 93 02 00 E4 37 +1E 4B 18 00 9F 4B 1A 00 00 00 31 50 06 00 3D 41 +B0 12 B8 57 02 24 30 40 8A 43 B2 40 3C 1D A0 40 +B2 40 D4 42 D2 42 30 40 70 43 09 93 07 24 F8 90 +20 00 00 1E 03 20 18 53 19 83 F9 23 30 41 74 4C +0B 52 45 41 44 22 5A 43 20 3C DC 4A 09 44 45 4C +22 00 6A 43 1A 3C A2 49 0D 57 52 49 54 45 22 00 +6A 42 13 3C 8A 49 0F 41 50 50 45 4E 44 22 7A 42 +0C 3C 86 4B 0A 43 4C 4F 53 45 B0 12 D4 57 30 4D +EA 48 0B 4C 4F 41 44 22 7A 43 2F 83 8F 4E 00 00 +0E 4A 82 93 BC 1D 0B 24 0D 12 84 12 0A 40 0A 40 +D8 48 D8 48 58 45 0A 40 AE 58 D8 48 EA 45 0D 12 +84 12 0A 40 22 00 6E 46 28 49 AC 58 3D 41 36 4F +0E 56 82 4E 36 20 A2 43 22 20 82 43 24 20 1C 43 +0E 96 8C 24 F6 90 3A 00 01 00 01 20 26 53 F6 90 +5C 00 00 00 03 20 16 53 0E 96 66 24 82 46 34 20 +B0 12 30 56 15 42 12 20 B0 12 AE 57 2C 43 0A 43 +08 4A 58 0E 08 58 82 48 30 20 C8 93 00 1E 60 24 +39 42 F8 96 00 1E 04 20 18 53 19 83 FA 23 16 53 +F6 90 2E 00 FF FF 19 24 39 50 03 00 B0 12 1A 58 +06 20 F6 90 5C 00 FF FF 29 24 0E 96 27 28 16 42 +34 20 1A 53 3A 90 10 00 DB 23 92 53 1A 20 82 63 +1C 20 15 83 D1 23 2C 42 49 3C F6 90 2E 00 FE FF +EE 27 B0 12 1A 58 EB 23 39 40 03 00 F8 96 00 1E +04 20 18 53 19 83 FA 23 09 3C 0E 96 E0 2F F6 90 +5C 00 FF FF DC 23 B0 12 1A 58 D9 23 18 42 30 20 +92 48 1A 1E 22 20 92 48 14 1E 24 20 F8 B0 10 00 +0B 1E 13 24 82 93 24 20 05 20 82 93 22 20 02 20 +A2 43 22 20 0E 96 9A 23 92 42 22 20 2C 20 92 42 +24 20 2E 20 8F 43 00 00 03 3C 2A 4F B0 12 78 56 +35 40 B6 40 36 40 C4 40 3A 4F 3E 4F 0A 93 04 24 +7A 93 39 20 0C 93 02 20 30 40 8A 43 0D 12 84 12 +70 43 1E 40 0B 3C 20 4F 70 65 6E 45 72 72 6F 72 +B2 40 C2 54 E2 B2 60 02 02 24 30 40 80 41 92 12 +3E 18 3F 40 7E 1C 8F 43 00 00 0D 12 84 12 1E 40 +0F 4C 4F 41 44 22 20 42 4F 4F 54 2E 34 54 48 22 +B2 40 58 49 30 58 08 42 4F 4F 54 00 B2 40 F4 59 +C4 42 30 4D 28 47 0C 4E 4F 42 4F 4F 54 00 B2 40 +80 41 C4 42 30 4D 1A 93 89 20 0C 93 C7 23 30 4D +26 5A 08 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 +32 20 B0 12 46 57 1E 82 32 20 30 4D 08 4A 1A 52 +08 20 B0 12 7C 5A 0A 48 1A 52 0C 20 09 43 30 40 +6E 54 3C 42 0A 12 2A 41 82 9A 0A 20 2B 25 B0 12 +28 56 88 93 02 1E 03 20 88 93 00 1E 08 24 28 52 +38 90 00 02 F6 2B 91 53 00 00 08 43 EC 3F A2 41 +26 20 82 48 28 20 0C 43 B8 43 00 1E 6A 41 B8 40 +FF 0F 02 1E 08 11 8A 10 08 5A 5A 41 01 00 0A 11 +08 10 82 4A 24 20 82 48 22 20 2A 41 B0 12 6C 5A +3A 41 30 41 90 4B 0A 00 3A C5 90 4B 0C 00 36 C5 +B0 12 0C 56 82 4A 26 20 82 48 28 20 0A 12 B0 12 +28 56 1A 48 00 1E 88 43 00 1E 19 48 02 1E 88 43 +02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 10 24 +82 4A 22 20 82 49 24 20 B0 12 0C 56 2A 91 E9 27 +09 4A 2A 41 81 49 00 00 B0 12 6C 5A 2A 41 DF 3F +3A 41 30 40 6C 5A 9B 52 1E 20 12 00 8B 63 14 00 +1A 42 1A 20 19 42 1C 20 30 40 6E 54 2A 93 BC 20 +0C 93 09 20 F8 40 E5 00 00 1E B0 12 50 5B B0 12 +E4 5A B0 12 D4 57 30 4D F2 B0 40 00 A2 04 29 20 +F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 4A 11 59 42 +B4 04 F2 40 20 00 C0 04 D2 42 B1 04 C8 04 1A 52 +E4 04 D2 42 B5 04 C8 04 19 52 E4 04 D2 42 B2 04 +C0 04 B2 40 00 08 C8 04 1A 52 E4 04 92 42 B6 04 +C0 04 B2 80 BC 07 C0 04 B2 40 00 02 C8 04 19 52 +E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B +5C 5D 7C 2E 29 92 06 28 39 80 03 00 B0 12 24 5C +39 40 03 00 7A 4B C8 4A 00 1E 82 9B 36 20 12 28 +0D 12 3D 40 0F 00 3C 40 D4 5B 7A 9C F3 27 1D 83 +FC 23 3D 41 6A 9C E6 27 3A 80 21 00 EB 3B 18 53 +19 83 E8 23 09 93 06 24 F8 40 20 00 00 1E 18 53 +19 83 FA 23 30 41 1A 4B 04 00 19 4B 06 00 B0 12 +28 54 18 4B 08 00 B0 12 78 5B 88 49 12 1E 88 4A +16 1E 88 49 18 1E 98 4B 12 00 1C 1E 98 4B 14 00 +1E 1E 1A 4B 04 00 19 4B 06 00 30 40 6E 54 B2 40 +00 02 1E 20 1B 42 32 20 B0 12 46 5B 82 43 1E 20 +DB 53 03 00 DB 92 12 20 03 00 1D 28 B0 12 00 56 +08 12 0A 12 B0 12 82 5A 2A 91 03 24 2A 41 B0 12 +28 56 3A 41 38 41 98 42 22 20 00 1E 98 42 24 20 +02 1E B0 12 6C 5A AB 42 02 00 9B 42 22 20 0E 00 +9B 42 24 20 10 00 30 40 66 56 48 58 0A 57 52 49 +54 45 B0 12 6E 5C 30 4D 2A 92 54 20 2C 93 0E 24 +0C 93 3D 24 0D 12 84 12 1E 40 0C 3C 20 57 72 69 +74 65 45 72 72 6F 72 00 B2 40 C2 54 0A 43 08 43 +B0 12 82 5A B0 12 AE 57 18 42 30 20 F8 40 20 00 +0B 1E B0 12 78 5B 88 43 0C 1E 88 4A 0E 1E 88 49 +10 1E 98 42 24 20 14 1E 98 42 22 20 1A 1E 88 43 +1C 1E 88 43 1E 1E 2C 42 1B 42 34 20 82 9B 36 20 +D1 27 FB 90 2E 00 00 00 CD 27 39 40 0B 00 B0 12 +F4 5B B0 12 50 5B 2A 42 B0 12 78 56 30 4D B0 12 +E4 5A 8B 43 12 00 8B 43 14 00 90 4B 0A 00 B4 C2 +90 4B 0C 00 B0 C2 B0 12 0C 56 B0 12 82 5A B0 12 +B6 5C 30 4D 2C 93 BA 27 0C 93 AC 23 EB 42 02 00 +58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B 15 00 +5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 1C 83 +0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 19 5B +0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 CB 4A +03 00 B0 12 AA 57 1A 4B 12 00 BB C0 FF 01 12 00 +3A F0 FF 01 82 4A 1E 20 30 4D 3C 58 10 54 45 52 +4D 32 53 44 22 00 0D 12 84 12 50 58 FE 5D 0A 43 +7D 40 0A 00 B0 12 44 41 3A 90 00 02 03 28 B0 12 +6E 5C 0A 43 92 B3 EC 06 FD 27 59 42 CC 06 69 92 +11 24 CA 49 00 1E 1A 53 49 9D EE 23 A2 B3 EC 06 +FD 27 F2 40 0D 00 CE 06 A2 B3 EC 06 FD 27 C2 4D +CE 06 E0 3F C2 9D CC 06 FD 23 82 4A 1E 20 B0 12 +D4 57 3D 41 30 4D @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 84 42 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 96 4E +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 E6 42 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 10 42 q diff --git a/binaries/MSP_EXP430FR5994_16MHz_UART.txt b/binaries/MSP_EXP430FR5994_16MHz_UART.txt deleted file mode 100644 index 937328d..0000000 --- a/binaries/MSP_EXP430FR5994_16MHz_UART.txt +++ /dev/null @@ -1,658 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 1E 68 50 4D 34 01 -10 00 C1 B3 94 41 78 5F DA 41 36 5E 96 42 1E 68 -50 4D 7C 42 F2 43 26 43 00 43 3C 1D C0 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 -@4000 -B0 12 DA 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 78 5F 39 40 22 18 -B2 49 7A 42 B2 49 F0 43 B2 49 24 43 B2 49 FE 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 58 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 41 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 40 0A 40 DE 1D 40 44 34 43 -14 40 04 1B 5B 37 6D 00 BC 43 08 44 34 40 86 41 -14 40 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 BC 43 00 45 BC 43 14 40 04 1B 5B 30 6D 00 -BC 43 88 48 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 41 04 57 41 52 4D 00 -B0 12 36 5E 84 12 14 40 07 0D 0A 1B 5B 37 6D 23 -BC 43 36 45 14 40 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -BC 43 0A 40 40 FF 28 40 34 44 00 45 14 40 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 40 86 41 00 00 -06 41 43 43 45 50 54 00 30 40 7C 42 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 42 3C 40 -D4 42 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 42 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 43 -2F 83 8F 4E 00 00 B0 12 DA 41 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 41 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 43 08 4E 3E 4F C8 3F 1C 43 04 45 -43 48 4F 00 B2 40 C2 48 C2 42 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 42 -92 43 DE 1D 30 4D 0D 12 3D 40 76 43 1B 42 32 20 -9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 -1B 42 20 20 02 3C 78 43 2D 83 0C 9B 16 2C 58 4C -00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 -3D 41 82 4C 1E 20 3C 40 20 00 A6 3F 0E 99 8E 27 -CA 48 00 00 1A 53 1E 53 89 3F 1A 15 B0 12 2E 60 -19 17 DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 D8 43 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 24 43 DA 43 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 41 02 43 52 00 30 40 -F2 43 0D 12 84 12 14 40 02 0D 0A 00 BC 43 C0 44 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 42 01 40 -2E 4E 30 4D 3E 44 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D EA 43 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 7A 44 02 23 53 00 0D 12 -84 12 7C 44 B6 44 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D AA 44 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D B6 43 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -70 44 AE 44 EE 40 EE 44 CA 44 BC 43 74 48 22 43 -C0 44 42 43 01 2E 0E 93 E3 37 38 43 E2 3F E8 44 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 -BA 47 0A 40 22 00 8C 45 5A 45 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -34 45 82 2E 22 00 0D 12 84 12 44 45 0A 40 BC 43 -BA 47 C0 44 1A 42 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 0E 47 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F 10 47 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D B8 47 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D C6 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D DA 44 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 40 74 48 8C 45 30 48 -9C 26 3D 40 38 48 DE 3E 3A 48 0A 4E 3E 4F 3D 40 -54 48 36 27 3D 40 2A 48 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 56 48 3E 4F 3D 40 2A 48 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 F6 49 -CC 3F 5E 48 86 12 20 00 46 44 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 EE 43 -BC 40 24 48 24 44 56 44 14 40 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 -5E 44 14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 41 3A 40 9E 48 7A 48 86 41 42 4F 52 54 22 00 -0D 12 84 12 44 45 0A 40 2A 41 BA 47 C0 44 EE 45 -01 27 0D 12 84 12 74 48 8C 45 F4 45 34 40 72 48 -C0 44 00 00 83 5B 27 5D 0D 12 84 12 F2 48 0A 40 -0A 40 BA 47 BA 47 C0 44 04 49 81 5B 82 43 BE 1D -30 4D 6C 44 01 5D B2 43 BE 1D 30 4D 24 49 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 74 48 8C 45 F4 45 08 44 -34 40 72 48 56 44 34 40 66 49 0A 40 0A 40 BA 47 -BA 47 0A 40 BA 47 BA 47 C0 44 1A 49 01 3A 30 12 -B6 49 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 74 48 -8C 45 84 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 41 6C 49 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 40 C0 44 BA 47 C8 49 1C 49 -C0 44 1A 48 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 04 48 06 43 52 45 -41 54 45 00 B0 12 72 49 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F FA 49 07 3A 4E 4F 4E 41 4D 45 30 12 -B6 49 2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 -0E 4A 39 40 10 02 08 49 28 53 99 3F 2E 43 05 44 -45 46 45 52 B0 12 72 49 BA 40 30 40 FC FF BA 40 -F4 4D FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 14 4A -82 49 53 00 0D 12 82 93 BE 1D 06 24 84 12 08 49 -0A 40 86 4A BA 47 C0 44 84 12 F2 48 86 4A C0 44 -2C 4A 04 43 4F 44 45 00 B0 12 72 49 A2 82 C6 1D -82 43 8E 5C 0D 12 84 12 5A 4D 2C 4D C0 44 90 4A -07 48 44 4E 43 4F 44 45 B2 40 30 4D DA 1D EC 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 C8 49 -80 4D B4 4D C0 44 B2 4A 07 43 4F 44 45 4E 4E 4D -30 12 BC 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 80 4D B4 4D C0 44 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F D0 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 -94 4C BA 47 1C 49 C0 4A C0 44 46 4A 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 5C 4B 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 40 00 00 38 44 74 48 8C 45 -0A 48 00 44 34 40 F4 4B 0E 44 14 40 06 5B 54 48 -45 4E 5D 00 66 4B CE 4B 8A 4B AC 4B C0 44 0E 44 -14 40 06 5B 45 4C 53 45 5D 00 66 4B E4 4B 8A 4B -AA 4B C0 44 14 40 04 5B 49 46 5D 00 66 4B AC 4B -3A 40 AA 4B E2 43 14 40 05 0D 0A 6B 6F 20 BC 43 -BC 40 AC 40 3A 40 AC 4B 9A 4B 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 0A 4C 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 74 48 8C 45 -F4 45 18 4C C0 44 1E 4C 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 28 4C 50 44 C0 44 50 4C -B2 4E 0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C -CC 47 06 4D 41 52 4B 45 52 00 B0 12 72 49 BA 40 -85 12 FC FF BA 40 4E 4C FE FF 28 83 8A 48 00 00 -9A 42 C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 -C6 1D 9D 3E 2E 53 30 4D 6E 4A 05 44 4F 45 53 3E -1A 42 BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 -30 4D 86 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 -0D 12 84 12 34 4A 0A 40 10 00 0A 40 00 00 3E 40 -0A 40 00 00 BA 47 60 40 D0 4C 28 40 0A 40 C8 1D -00 44 40 44 BA 47 48 44 A0 4C 0A 40 CA 1D 48 44 -C0 44 F0 48 05 46 4F 52 54 48 85 12 EA 4C 54 4D -C2 63 F6 61 F4 4C 44 4B F8 42 10 62 9A 4D 26 4E -18 64 C0 67 DC 66 00 00 B4 63 2E 49 54 46 00 00 -D8 48 09 41 53 53 45 4D 42 4C 45 52 85 12 EA 4C -5A 5B F2 5A 56 5A 16 55 A8 53 00 00 1E 59 00 00 -7E 5C 7A 5D 0C 54 C0 5D 26 5B 00 00 00 00 F0 54 -1E 4D 22 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 -D6 1D 08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 -FA 23 30 4D 3A 49 08 50 52 45 56 49 4F 55 53 00 -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 72 45 04 4F 4E 4C 59 00 -82 43 CC 1D 30 4D 9A 4C 0B 44 45 46 49 4E 49 54 -49 4F 4E 53 92 42 CA 1D DA 1D 30 4D FA 4C A0 4D -B4 4D C4 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D -3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 -FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 -3E 4F 3D 41 30 4D 76 4D 09 50 57 52 5F 53 54 41 -54 45 85 12 BC 4D 50 4D 1E 68 40 45 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 08 4E 92 42 0C 18 -06 4E EF 3F F8 4D 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 08 4E 92 42 C8 1D 06 4E 30 4D 0C 4E -08 52 53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 -92 42 C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 -DA 37 0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 A8 4E FE FF 29 83 B9 40 02 42 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 42 B2 49 -FA 40 B2 49 02 40 B2 49 22 42 B2 49 F0 FF B2 49 -0A 18 B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 -E2 D2 25 02 B2 43 42 02 B2 D3 46 02 B2 43 62 02 -B2 D3 66 02 F2 43 26 03 F2 D3 22 03 F2 40 A5 00 -41 01 F2 40 10 00 40 01 D2 43 41 01 F2 40 A5 00 -61 01 B2 40 48 00 62 01 82 43 66 01 B2 40 33 00 -64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 F2 D0 10 00 2A 03 F2 40 A5 00 -A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 1E 42 08 18 -82 43 08 18 1E D2 9E 01 B0 12 F8 40 20 42 38 40 -C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D -30 4D 1C 15 0E 12 12 12 C4 1D 84 12 8C 45 F4 45 -50 44 34 40 9E 4F B0 46 34 40 B8 4F B2 4F A0 4F -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 BA 4F B2 41 C4 1D 3E 41 -84 12 0A 40 2B 00 8C 45 F4 45 50 44 34 40 D6 4F -B0 46 34 40 72 48 1A 44 8C 45 B0 46 34 40 72 48 -E2 4F 3E 5F E7 3F 32 B0 00 02 01 24 3E 4F 30 41 -3E 40 28 00 B0 12 82 4F B0 12 E6 4F 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 40 29 00 1C 15 92 92 -C0 1D C4 1D 02 20 30 40 E0 49 12 12 C4 1D 92 53 -C4 1D 84 12 8C 45 B0 46 34 40 38 50 2E 50 21 53 -3E 90 10 00 84 2D BE 2B 3A 50 B2 41 C4 1D BA 3F -0D 12 84 12 74 48 5E 4F 4A 50 0C 43 1B 42 C6 1D -A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 29 20 92 53 -C4 1D B0 12 82 4F B0 12 E6 4F 3C 40 00 03 0E 93 -1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 -14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 -0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D -7A 90 26 00 09 20 3C 40 10 02 92 53 C4 1D B0 12 -82 4F B0 12 E6 4F EB 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 1D B0 12 0C 50 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 0C 50 92 92 C0 1D C4 1D 02 24 -92 53 C4 1D 8E 10 0C 5E D8 3F B0 12 0C 50 FA 23 -3C 50 10 00 B0 12 F0 4F EF 3F 0C 43 1B 42 C6 1D -A2 53 C6 1D 0D 12 84 12 74 48 5E 4F 1E 51 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C5 3F -B0 12 0C 50 E0 23 3C 50 80 00 B0 12 F0 4F DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 40 00 13 -BA 47 C0 44 0A 40 2C 00 40 50 14 51 5E 51 09 4B -2E 4E 0E DC A0 3F 32 4B 03 4D 4F 56 85 12 54 51 -00 40 68 51 05 4D 4F 56 2E 42 85 12 54 51 40 40 -00 00 03 41 44 44 85 12 54 51 00 50 82 51 05 41 -44 44 2E 42 85 12 54 51 40 50 8E 51 04 41 44 44 -43 00 85 12 54 51 00 60 9C 51 06 41 44 44 43 2E -42 00 85 12 54 51 40 60 42 51 04 53 55 42 43 00 -85 12 54 51 00 70 BA 51 06 53 55 42 43 2E 42 00 -85 12 54 51 40 70 C8 51 03 53 55 42 85 12 54 51 -00 80 D8 51 05 53 55 42 2E 42 85 12 54 51 40 80 -08 4B 03 43 4D 50 85 12 54 51 00 90 F2 51 05 43 -4D 50 2E 42 85 12 54 51 40 90 E2 4A 04 44 41 44 -44 00 85 12 54 51 00 A0 0C 52 06 44 41 44 44 2E -42 00 85 12 54 51 40 A0 FE 51 03 42 49 54 85 12 -54 51 00 B0 2A 52 05 42 49 54 2E 42 85 12 54 51 -40 B0 36 52 03 42 49 43 85 12 54 51 00 C0 44 52 -05 42 49 43 2E 42 85 12 54 51 40 C0 50 52 03 42 -49 53 85 12 54 51 00 D0 5E 52 05 42 49 53 2E 42 -85 12 54 51 40 D0 00 00 03 58 4F 52 85 12 54 51 -00 E0 78 52 05 58 4F 52 2E 42 85 12 54 51 40 E0 -AA 51 03 41 4E 44 85 12 54 51 00 F0 92 52 05 41 -4E 44 2E 42 85 12 54 51 40 F0 74 48 40 50 B0 52 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -E4 51 03 52 52 43 85 12 AA 52 00 10 C2 52 05 52 -52 43 2E 42 85 12 AA 52 40 10 CE 52 04 53 57 50 -42 00 85 12 AA 52 80 10 DC 52 03 52 52 41 85 12 -AA 52 00 11 EA 52 05 52 52 41 2E 42 85 12 AA 52 -40 11 F6 52 03 53 58 54 85 12 AA 52 80 11 00 00 -04 50 55 53 48 00 85 12 AA 52 00 12 10 53 06 50 -55 53 48 2E 42 00 85 12 AA 52 40 12 6A 52 04 43 -41 4C 4C 00 85 12 AA 52 80 12 1A 53 0E 4A 0D 12 -84 12 36 45 14 40 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 41 04 53 03 53 3E 3D 86 12 00 38 -58 53 02 53 3C 00 86 12 00 34 1E 53 03 30 3E 3D -86 12 00 30 6C 53 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C 80 53 03 55 3E 3D 86 12 -00 28 76 53 03 30 3C 3E 86 12 00 24 94 53 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D -8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D 8A 53 04 54 -48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -1A 52 04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C -00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 2E 53 -05 42 45 47 49 4E 30 40 28 40 BE 53 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 1D 30 4D 9E 52 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 AC 53 1A 44 C0 44 62 53 06 52 45 50 -45 41 54 00 0D 12 84 12 40 54 C4 53 C0 44 70 54 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 -C6 1D 00 00 30 4D 00 54 03 42 57 31 85 12 6E 54 -00 00 88 54 03 42 57 32 85 12 6E 54 00 00 94 54 -03 42 57 33 85 12 6E 54 00 00 AC 54 3D 41 1A 42 -C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 -C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 AA 54 00 00 CC 54 03 46 57 32 85 12 AA 54 -00 00 D8 54 03 46 57 33 85 12 AA 54 00 00 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 07 24 3E E0 00 04 -3E B0 00 10 02 24 3E E0 00 08 0D 12 84 12 F2 48 -4E 48 C0 44 E4 54 04 47 4F 54 4F 00 2F 83 8F 4E -00 00 3E 40 00 3C F1 3F 74 48 5E 4F 2E 55 92 53 -C4 1D 3E 40 2C 00 84 12 8C 45 B0 46 34 40 72 48 -0A 51 44 55 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -5C 54 04 52 52 43 4D 00 85 12 28 55 50 00 72 55 -04 52 52 41 4D 00 85 12 28 55 50 01 80 55 04 52 -4C 41 4D 00 85 12 28 55 50 02 8E 55 04 52 52 55 -4D 00 85 12 28 55 50 03 9E 53 05 50 55 53 48 4D -85 12 28 55 00 15 AA 55 04 50 4F 50 4D 00 85 12 -28 55 00 17 9C 55 06 52 52 43 4D 2E 41 00 85 12 -28 55 40 00 C6 55 06 52 52 41 4D 2E 41 00 85 12 -28 55 40 01 D6 55 06 52 4C 41 4D 2E 41 00 85 12 -28 55 40 02 E6 55 06 52 52 55 4D 2E 41 00 85 12 -28 55 40 03 B8 55 07 50 55 53 48 4D 2E 41 85 12 -28 55 00 14 06 56 06 50 4F 50 4D 2E 41 00 85 12 -28 55 00 16 A0 54 05 43 41 4C 4C 41 0D 12 84 12 -74 48 5E 4F 36 56 1B 42 C6 1D A2 53 C6 1D 6E 4E -3C 40 34 01 7E 90 52 00 0B 20 7E 40 20 00 B0 12 -0C 50 5C 0E 0C DE 8B 4C 00 00 3E 4F 3D 41 30 4D -2C 53 7E 90 40 00 0B 20 92 53 C4 1D 7E 40 20 00 -B0 12 0C 50 EE 23 1C 53 3E 40 2B 00 E8 3F A2 53 -C6 1D 7E 90 23 00 09 20 3C 40 3B 01 92 53 C4 1D -B0 12 82 4F BB 4F 02 00 DC 3F 7E 90 26 00 02 20 -2C 53 F4 3F 7E 40 28 00 1C 83 B0 12 82 4F BB 4F -02 00 3E 40 29 00 CB 3F 0D 12 84 12 74 48 5E 4F -C2 56 69 4E 3E 4F 3C 4F 2C 4C 1B 42 C6 1D A2 53 -C6 1D 79 90 52 00 0A 20 B0 12 0C 50 5E 0E 5E 0E -0E DC 8B 4E 00 00 0E 4B 3D 41 30 4D 79 90 23 00 -0D 20 3C C0 40 00 92 53 C4 1D A2 53 C6 1D B0 12 -82 4F BB 4F 02 00 3E F0 0F 00 E8 3F 79 90 26 00 -03 20 3C E0 E0 00 EF 3F 3C C0 F0 00 79 90 40 00 -12 20 92 53 C4 1D B0 12 0C 50 D8 23 3C D0 10 00 -3E 40 2B 00 B0 12 0C 50 92 92 C0 1D C4 1D CE 27 -92 53 C4 1D CB 3F 3C D0 30 00 A2 53 C6 1D 3E 40 -28 00 B0 12 82 4F BB 4F 02 00 3E 40 29 00 EA 3F -0D 12 84 12 74 48 5E 4F 6A 57 3B 4F 2C 4B 69 4E -7E 40 20 00 79 90 52 00 03 20 B0 12 0C 50 B0 3F -3C C0 F0 00 A2 53 C6 1D 79 90 26 00 09 20 3C D0 -60 00 92 53 C4 1D B0 12 82 4F BB 4F 02 00 A0 3F -3C D0 70 00 3E 40 28 00 B0 12 82 4F BB 4F 02 00 -3E 40 29 00 E2 3F 0A 40 2C 00 B8 56 60 57 E4 43 -C0 44 74 51 04 4D 4F 56 41 00 85 12 B6 57 C0 00 -26 56 04 43 4D 50 41 00 85 12 B6 57 D0 00 3A 54 -04 41 44 44 41 00 85 12 B6 57 E0 00 F6 55 04 53 -55 42 41 00 85 12 B6 57 F0 00 0D 12 84 12 74 48 -5E 4F 04 58 69 4E 3E 4F 3C 40 00 18 79 90 52 00 -05 20 B0 12 0C 50 0E 4C 3D 41 30 4D 82 43 8E 5C -79 90 23 00 0B 20 92 53 C4 1D B0 12 82 4F 2F 53 -3E F0 0F 00 5E 0A 5E 0E 0C DE ED 3F 79 90 26 00 -F2 27 79 90 40 00 12 20 92 53 C4 1D B0 12 0C 50 -E2 23 3E 40 2B 00 92 53 C4 1D B0 12 0C 50 92 92 -C0 1D C4 1D D8 27 92 53 C4 1D D5 3F 3E 40 28 00 -B0 12 82 4F 8F 4E 00 00 3E 40 29 00 B0 12 0C 50 -3E 4F 3E F0 0F 00 0C DE EA 3F 0D 12 84 12 74 48 -5E 4F 94 58 3C 4F 69 4E 3E 40 20 00 79 90 52 00 -BA 27 82 43 8E 5C 79 90 26 00 08 20 92 53 C4 1D -B0 12 82 4F 2F 53 3E F0 0F 00 BE 3F 3E 40 28 00 -B0 12 82 4F F7 3F B2 4F C4 1D 1B 42 C6 1D A2 53 -C6 1D 0C 4E 3E 4F 1C D2 8E 5C 82 43 8E 5C 3C DE -8B 4C 00 00 30 4D 0A 40 C4 1D 40 44 0A 40 2C 00 -FA 57 8A 58 C6 58 3A 40 54 51 C4 57 04 4D 4F 56 -58 00 85 12 E6 58 40 00 00 40 FC 58 06 4D 4F 56 -58 2E 41 00 85 12 E6 58 00 00 40 40 0C 59 06 4D -4F 56 58 2E 42 00 85 12 E6 58 40 00 40 40 E0 57 -04 41 44 44 58 00 85 12 E6 58 40 00 00 50 30 59 -06 41 44 44 58 2E 41 00 85 12 E6 58 00 00 40 50 -40 59 06 41 44 44 58 2E 42 00 85 12 E6 58 40 00 -40 50 52 59 05 41 44 44 43 58 85 12 E6 58 40 00 -00 60 64 59 07 41 44 44 43 58 2E 41 85 12 E6 58 -00 00 40 60 74 59 07 41 44 44 43 58 2E 42 85 12 -E6 58 40 00 40 60 EE 57 05 53 55 42 43 58 85 12 -E6 58 40 00 00 70 98 59 07 53 55 42 43 58 2E 41 -85 12 E6 58 00 00 40 70 A8 59 07 53 55 42 43 58 -2E 42 85 12 E6 58 40 00 40 70 BA 59 04 53 55 42 -58 00 85 12 E6 58 40 00 00 80 CC 59 06 53 55 42 -58 2E 41 00 85 12 E6 58 00 00 40 80 DC 59 06 53 -55 42 58 2E 42 00 85 12 E6 58 40 00 40 80 D2 57 -04 43 4D 50 58 00 85 12 E6 58 40 00 00 90 00 5A -06 43 4D 50 58 2E 41 00 85 12 E6 58 00 00 40 90 -10 5A 06 43 4D 50 58 2E 42 00 85 12 E6 58 40 00 -40 90 E2 53 05 44 41 44 44 58 85 12 E6 58 40 00 -00 A0 34 5A 07 44 41 44 44 58 2E 41 85 12 E6 58 -00 00 40 A0 44 5A 07 44 41 44 44 58 2E 42 85 12 -E6 58 40 00 40 A0 22 5A 04 42 49 54 58 00 85 12 -E6 58 40 00 00 B0 68 5A 06 42 49 54 58 2E 41 00 -85 12 E6 58 00 00 40 B0 78 5A 06 42 49 54 58 2E -42 00 85 12 E6 58 40 00 40 B0 8A 5A 04 42 49 43 -58 00 85 12 E6 58 40 00 00 C0 9C 5A 06 42 49 43 -58 2E 41 00 85 12 E6 58 00 00 40 C0 AC 5A 06 42 -49 43 58 2E 42 00 85 12 E6 58 40 00 40 C0 BE 5A -04 42 49 53 58 00 85 12 E6 58 40 00 00 D0 D0 5A -06 42 49 53 58 2E 41 00 85 12 E6 58 00 00 40 D0 -E0 5A 06 42 49 53 58 2E 42 00 85 12 E6 58 40 00 -40 D0 84 52 04 58 4F 52 58 00 85 12 E6 58 40 00 -00 E0 04 5B 06 58 4F 52 58 2E 41 00 85 12 E6 58 -00 00 40 E0 14 5B 06 58 4F 52 58 2E 42 00 85 12 -E6 58 40 00 40 E0 86 59 04 41 4E 44 58 00 85 12 -E6 58 40 00 00 F0 38 5B 06 41 4E 44 58 2E 41 00 -85 12 E6 58 00 00 40 F0 48 5B 06 41 4E 44 58 2E -42 00 85 12 E6 58 40 00 40 F0 0A 40 C4 1D 40 44 -74 48 FA 57 C6 58 3A 40 AA 52 EE 59 04 52 52 43 -58 00 85 12 6A 5B 40 00 00 10 7C 5B 06 52 52 43 -58 2E 41 00 85 12 6A 5B 00 00 40 10 8C 5B 06 52 -52 43 58 2E 42 00 85 12 6A 5B 40 00 40 10 9E 5B -04 52 52 55 58 00 85 12 6A 5B 40 01 00 10 B0 5B -06 52 52 55 58 2E 41 00 85 12 6A 5B 00 01 40 10 -C0 5B 06 52 52 55 58 2E 42 00 85 12 6A 5B 40 01 -40 10 D2 5B 05 53 57 50 42 58 85 12 6A 5B 40 00 -80 10 E4 5B 07 53 57 50 42 58 2E 41 85 12 6A 5B -00 00 80 10 F4 5B 04 52 52 41 58 00 85 12 6A 5B -40 00 00 11 06 5C 06 52 52 41 58 2E 41 00 85 12 -6A 5B 00 00 40 11 16 5C 06 52 52 41 58 2E 42 00 -85 12 6A 5B 40 00 40 11 28 5C 04 53 58 54 58 00 -85 12 6A 5B 40 00 80 11 3A 5C 06 53 58 54 58 2E -41 00 85 12 6A 5B 00 00 80 11 16 56 05 50 55 53 -48 58 85 12 6A 5B 40 00 00 12 5C 5C 07 50 55 53 -48 58 2E 41 85 12 6A 5B 00 00 40 12 6C 5C 07 50 -55 53 48 58 2E 42 85 12 6A 5B 40 00 40 12 00 00 -4A 5C 03 52 50 54 0D 12 84 12 74 48 5E 4F A0 5C -29 4E 7E 40 20 00 79 90 52 00 06 20 B0 12 0C 50 -03 24 3E D0 80 00 05 3C B0 12 82 4F 1E 83 3E F0 -0F 00 82 4E 8E 5C 3E 4F 3D 41 30 4D D2 C3 23 02 -E2 B2 60 02 02 24 30 40 02 42 1A 52 04 20 19 62 -06 20 92 43 14 20 A2 93 02 20 07 24 0A 5A 49 69 -82 4A 16 20 C2 49 18 20 0A 3C C2 4A 15 20 8A 10 -C2 4A 16 20 C2 49 17 20 89 10 C2 49 18 20 B0 12 -54 5D 5A 53 FC 23 39 40 05 00 D2 49 14 20 4E 06 -82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 -59 83 F3 2F 19 83 0B 30 F2 43 4E 06 82 93 46 06 -03 24 92 B3 6C 06 FD 27 5A 92 4C 06 F3 23 30 41 -1A 43 E1 3F 19 43 3A 43 8A 10 C2 4A 4E 06 82 93 -46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 19 83 -F3 23 5A 42 4C 06 30 41 92 5C 08 52 45 41 44 5F -53 57 58 00 1C D3 F2 40 51 00 19 20 B0 12 CC 5C -38 20 B0 12 54 5D 6A 53 04 24 FB 23 D9 42 4C 06 -FF 1D F2 43 4E 06 03 43 19 53 39 90 01 02 F6 23 -F2 43 4E 06 3C C0 03 00 D2 D3 23 02 30 41 4A 54 -09 57 52 49 54 45 5F 53 57 58 2C D3 F0 40 58 00 -49 C2 B0 12 CC 5C 15 20 3A 40 FE FF 29 43 B0 12 -58 5D D2 49 00 1E 4E 06 03 43 19 53 39 90 00 02 -F8 23 39 40 03 00 B0 12 56 5D 7A C0 E1 00 6A 92 -D9 27 8C 10 1C 52 4C 06 D2 D3 23 02 0D 12 84 12 -34 43 14 40 0B 3C 20 53 44 20 45 72 72 6F 72 21 -22 5E 2F 83 8F 4E 00 00 B2 40 10 00 DC 1D 0E 4C -84 12 00 45 36 41 B0 12 9C 41 0E 93 9C 24 E2 B2 -60 02 99 20 B2 40 81 A9 40 06 B2 40 30 00 46 06 -D2 D3 25 02 B2 D0 C0 04 0C 02 92 C3 40 06 39 42 -B0 12 56 5D D2 C3 23 02 2C 42 B2 40 95 00 14 20 -B2 40 00 40 18 20 B0 12 50 5D 02 24 30 40 02 5E -B0 12 54 5D 7A 93 FC 23 B2 40 87 AA 14 20 92 43 -16 20 B2 40 00 48 18 20 B0 12 50 5D 29 42 B0 12 -56 5D 92 43 14 20 82 43 16 20 78 43 3C 42 B2 40 -00 77 18 20 B0 12 50 5D B2 40 40 69 18 20 B0 12 -0E 5D 03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 -B2 40 00 50 18 20 B0 12 0E 5D D0 23 92 D3 40 06 -82 43 46 06 92 C3 40 06 09 43 B0 12 84 5D 38 40 -00 1E 92 48 C6 01 04 20 92 48 C8 01 06 20 5A 48 -C2 01 92 43 02 20 7A 80 06 00 0F 24 7A 82 0D 24 -A2 43 02 20 6A 53 09 24 5A 53 07 24 6A 52 05 24 -3A 50 0B 20 0C 4A 30 40 08 5E 09 43 B0 12 84 5D -D2 48 0D 00 12 20 19 48 0E 00 82 49 08 20 1A 48 -16 00 0A 93 02 20 1A 48 24 00 82 4A 0A 20 09 5A -82 49 0C 20 09 5A A2 93 02 20 04 24 82 49 0E 20 -39 50 20 00 19 82 12 20 19 82 12 20 82 49 10 20 -92 42 02 20 2C 20 30 41 B0 12 AA 40 39 40 E0 00 -29 83 89 43 38 20 FC 23 82 43 32 20 30 41 92 4B -0E 00 22 20 92 4B 10 00 24 20 5A 42 23 20 58 42 -22 20 92 93 02 20 08 24 59 42 24 20 89 10 0A 59 -88 10 08 58 0A 6A 88 10 08 58 30 41 82 43 1C 20 -92 42 0E 20 1A 20 C2 93 24 20 03 20 92 93 22 20 -14 24 92 42 22 20 D0 04 92 42 24 20 D2 04 92 42 -12 20 C8 04 92 42 E4 04 1A 20 92 42 E6 04 1C 20 -92 52 10 20 1A 20 82 63 1C 20 30 41 92 4B 0E 00 -22 20 92 4B 10 00 24 20 B0 12 BC 5F 5A 4B 03 00 -82 5A 1A 20 82 63 1C 20 30 41 09 93 07 24 F8 90 -20 00 00 1E 03 20 18 53 19 83 F9 23 30 41 1B 42 -32 20 82 43 1E 20 B2 90 00 02 20 20 AB 20 BB 80 -00 02 12 00 8B 73 14 00 DB 53 03 00 DB 92 12 20 -03 00 14 28 CB 43 03 00 B0 12 8E 5F 1A 52 08 20 -09 43 B0 12 84 5D 8B 43 10 00 9B 48 00 1E 0E 00 -92 93 02 20 03 24 9B 48 02 1E 10 00 B2 40 00 02 -20 20 8B 93 14 00 0B 20 92 9B 12 00 1E 20 82 2C -BB 90 00 02 12 00 03 2C 92 4B 12 00 20 20 B0 12 -FC 5F 1A 42 1A 20 19 42 1C 20 6C 3E 3C 42 3B 40 -38 20 09 43 CB 93 02 00 10 24 9B 92 24 20 0C 00 -04 20 9B 92 22 20 0A 00 07 24 09 4B 3B 50 1C 00 -3B 90 18 21 EF 23 0C 5C 30 41 0C 43 82 4B 32 20 -8B 49 00 00 09 93 0A 24 99 52 C4 1D 16 00 4A 93 -05 34 C9 93 02 00 02 34 5A 59 02 00 CB 4A 02 00 -CB 43 03 00 9B 42 1A 20 04 00 9B 42 1C 20 06 00 -18 42 30 20 8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 -14 1E 0C 00 9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 -9B 48 1C 1E 12 00 9B 48 1E 1E 14 00 82 43 1E 20 -6A 93 5C 27 C9 37 8B 43 16 00 7A 93 02 24 07 38 -95 3F B2 40 1C 21 CA 40 B2 40 56 43 7A 42 9B 42 -C0 1D 18 00 9B 82 C4 1D 18 00 9B 42 C2 1D 1A 00 -9B 52 C4 1D 1A 00 82 3F CB 43 02 00 2B 4B 82 4B -32 20 0B 93 06 24 92 4B 16 00 1E 20 B0 12 7C 60 -22 C3 30 41 1B 42 32 20 0B 93 FB 27 EB 93 02 00 -04 20 B0 12 58 66 B0 12 20 66 CB 93 02 00 E4 37 -1E 4B 18 00 9F 4B 1A 00 00 00 31 50 06 00 3D 41 -B0 12 78 61 02 24 30 40 4A 43 B2 40 3C 1D CA 40 -B2 40 7C 42 7A 42 30 40 34 43 40 4E 85 52 45 41 -44 22 5A 43 19 3C B4 4C 86 57 52 49 54 45 22 00 -6A 43 12 3C A8 4D 84 44 45 4C 22 00 6A 42 0C 3C -F8 4A 05 43 4C 4F 53 45 B0 12 94 61 30 4D 62 4C -85 4C 4F 41 44 22 7A 43 2F 83 8F 4E 00 00 0E 4A -82 93 BE 1D 0B 24 0D 12 84 12 0A 40 0A 40 BA 47 -BA 47 44 45 0A 40 4C 62 BA 47 C0 44 0D 12 84 12 -0A 40 22 00 8C 45 0A 48 4A 62 3D 41 36 4F 0E 56 -82 4E 36 20 1C 43 92 42 2C 20 22 20 92 42 2E 20 -24 20 0E 96 8D 24 F6 90 3A 00 01 00 01 20 26 53 -F6 90 5C 00 00 00 08 20 16 53 92 42 02 20 22 20 -82 43 24 20 0E 96 70 24 82 46 34 20 B0 12 BC 5F -35 40 20 00 A2 93 02 20 04 24 92 92 22 20 02 20 -02 24 15 42 12 20 B0 12 A2 60 2C 43 0A 43 08 4A -58 0E 08 58 82 48 30 20 C8 93 00 1E 61 24 39 42 -F8 96 00 1E 04 20 18 53 19 83 FA 23 16 53 F6 90 -2E 00 FF FF 19 24 39 50 03 00 B0 12 1A 60 06 20 -F6 90 5C 00 FF FF 29 24 0E 96 27 28 16 42 34 20 -1A 53 3A 90 10 00 DB 23 92 53 1A 20 82 63 1C 20 -15 83 D1 23 2C 42 3C 3C F6 90 2E 00 FE FF EE 27 -B0 12 1A 60 EB 23 39 40 03 00 F8 96 00 1E 04 20 -18 53 19 83 FA 23 09 3C 0E 96 E0 2F F6 90 5C 00 -FF FF DC 23 B0 12 1A 60 D9 23 18 42 30 20 92 48 -1A 1E 22 20 92 48 14 1E 24 20 F8 B0 10 00 0B 1E -14 24 82 93 24 20 06 20 82 93 22 20 03 20 92 42 -02 20 22 20 0E 96 8E 2F 92 42 22 20 2C 20 92 42 -24 20 2E 20 8F 43 00 00 03 3C 2A 4F B0 12 AC 60 -35 40 D4 40 36 40 E2 40 3A 4F 3E 4F 0A 93 04 24 -7A 93 3C 20 0C 93 01 20 30 4D 0D 12 84 12 34 43 -14 40 0B 3C 20 4F 70 65 6E 45 72 72 6F 72 3A 40 -20 5E 38 4C 05 5B 50 46 41 5D 2E 53 2E 4E 30 4D -02 62 04 42 4F 4F 54 00 39 40 36 5E 2E 93 01 2C -30 41 E2 B2 60 02 02 24 10 49 02 00 89 12 3F 40 -7E 1C 8F 43 00 00 82 43 BE 1D B2 40 00 1C 00 1C -31 40 E0 1C 84 12 14 40 0F 4C 4F 41 44 22 20 42 -4F 4F 54 2E 34 54 48 22 3A 40 A2 48 1A 93 BB 20 -0C 93 C3 23 30 4D DC 61 04 52 45 41 44 00 2F 83 -8F 4E 00 00 1E 42 32 20 B0 12 2E 60 1E 82 32 20 -30 4D 2C 43 12 12 2A 20 18 42 02 20 08 58 2A 41 -82 9A 0A 20 A6 24 1A 52 08 20 09 43 B0 12 84 5D -09 43 28 93 03 24 89 93 02 1E 03 20 89 93 00 1E -07 24 09 58 39 90 00 02 F4 23 91 53 00 00 E7 3F -0C 43 6A 41 B9 43 00 1E 28 93 0F 24 B9 40 FF 0F -02 1E 09 11 8A 10 09 5A 5A 41 01 00 0A 11 09 10 -82 4A 28 20 82 49 26 20 07 3C 09 11 C2 49 26 20 -C2 4A 27 20 82 43 28 20 3A 41 82 4A 2A 20 30 41 -0A 12 1A 52 08 20 09 43 B0 12 CA 5D 3A 41 1A 52 -0C 20 09 43 B0 12 CA 5D F2 B0 40 00 A2 04 29 20 -F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 4A 11 59 42 -B4 04 F2 40 20 00 C0 04 D2 42 B1 04 C8 04 1A 52 -E4 04 D2 42 B5 04 C8 04 19 52 E4 04 D2 42 B2 04 -C0 04 B2 40 00 08 C8 04 1A 52 E4 04 92 42 B6 04 -C0 04 B2 80 BC 07 C0 04 B2 40 00 02 C8 04 19 52 -E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B -5C 5D 7C 2E 29 92 06 38 39 80 03 00 B0 12 74 65 -39 40 03 00 7A 4B C8 4A 00 1E 82 9B 36 20 12 28 -0D 12 3D 40 0F 00 3C 40 24 65 7A 9C F3 27 1D 83 -FC 23 3D 41 6A 9C E6 27 3A 80 21 00 EB 3B 18 53 -19 83 E8 23 09 93 06 24 F8 40 20 00 00 1E 18 53 -19 83 FA 23 30 41 2A 93 DC 20 2C 93 0E 24 0C 93 -AB 24 0D 12 84 12 14 40 0C 3C 20 57 72 69 74 65 -45 72 72 6F 72 00 3A 40 20 5E B0 12 32 64 92 42 -26 20 22 20 92 42 28 20 24 20 B0 12 B0 64 B0 12 -A2 60 18 42 30 20 F8 40 20 00 0B 1E B0 12 C8 64 -88 43 0C 1E 88 4A 0E 1E 88 49 10 1E 88 49 12 1E -98 42 24 20 14 1E 98 42 22 20 1A 1E 88 43 1C 1E -88 43 1E 1E 1C 43 1B 42 34 20 82 9B 36 20 C9 27 -FB 90 2E 00 00 00 C5 27 39 40 0B 00 B0 12 44 65 -B0 12 62 66 2A 43 B0 12 AC 60 0C 93 BA 23 30 4D -1A 4B 04 00 19 4B 06 00 B0 12 84 5D B0 12 C8 64 -18 4B 08 00 88 49 12 1E 88 4A 16 1E 88 49 18 1E -98 4B 12 00 1C 1E 98 4B 14 00 1E 1E 1A 4B 04 00 -19 4B 06 00 30 40 CA 5D 9B 52 1E 20 12 00 8B 63 -14 00 1A 42 1A 20 19 42 1C 20 30 40 CA 5D B2 40 -00 02 1E 20 1B 42 32 20 B0 12 58 66 82 43 1E 20 -DB 53 03 00 DB 92 12 20 03 00 25 20 CB 43 03 00 -B0 12 8E 5F 08 12 0A 12 B0 12 32 64 2A 91 08 24 -B0 12 B0 64 2A 41 1A 52 08 20 09 43 B0 12 84 5D -3A 41 38 41 98 42 26 20 00 1E 92 93 02 20 03 24 -98 42 28 20 02 1E B0 12 B0 64 9B 42 26 20 0E 00 -9B 42 28 20 10 00 30 40 FC 5F E8 61 05 57 52 49 -54 45 B0 12 6E 66 30 4D 58 4B 13 00 59 4B 14 00 -89 10 09 58 58 4B 15 00 5B 42 12 20 0A 43 3C 42 -08 11 09 10 4A 10 1C 83 0B 11 FA 2B 0A 11 1C 83 -FD 37 1B 42 32 20 19 5B 0A 00 18 6B 0C 00 8B 49 -0E 00 8B 48 10 00 CB 4A 03 00 1A 4B 12 00 BB C0 -FF 01 12 00 3A F0 FF 01 82 4A 1E 20 B0 12 9E 60 -30 4D 0C 93 3B 20 38 90 E0 01 03 2C C8 93 20 1E -02 24 7C 40 E5 00 C8 4C 00 1E B0 12 62 66 B0 12 -9A 5F 82 4A 2A 20 0B 4A 1A 52 08 20 09 43 B0 12 -84 5D 1A 48 00 1E 88 43 00 1E 92 93 02 20 09 24 -19 48 02 1E 88 43 02 1E 39 F0 FF 0F 39 90 FF 0F -02 20 3A 93 0E 24 82 4A 22 20 82 49 24 20 B0 12 -9A 5F 0B 9A E6 27 0A 12 0A 4B B0 12 B0 64 3A 41 -DA 3F 0A 4B B0 12 B0 64 B0 12 94 61 30 4D FC 44 -08 54 45 52 4D 32 53 44 22 00 0D 12 84 12 FC 61 -0A 40 02 00 28 40 0A 48 4C 62 DC 67 3D 41 0A 43 -B0 12 DA 41 92 B3 DC 05 FD 27 59 42 CC 05 C2 49 -CE 05 69 92 0D 24 CA 49 00 1E 1A 53 3A 90 FF 01 -F1 2B 03 24 B0 12 6E 66 EA 3F B0 12 C8 41 EA 3F -B0 12 C8 41 82 4A 1E 20 B0 12 94 61 30 4D -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -96 42 02 42 02 42 02 42 02 42 02 42 02 42 A8 4E -q diff --git a/binaries/MSP_EXP430FR5994_1MHz_115200.txt b/binaries/MSP_EXP430FR5994_1MHz_115200.txt new file mode 100644 index 0000000..f789d59 --- /dev/null +++ b/binaries/MSP_EXP430FR5994_1MHz_115200.txt @@ -0,0 +1,505 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 59 +DA 42 7E 41 0A 56 EA 54 4A 43 62 5E 4E 4C 08 4C +08 4C C0 42 7E 43 46 43 3C 1D E0 1C FC 45 B6 40 +C4 40 18 45 20 00 0A 00 00 1C 7E 41 0A 56 EA 54 +4A 43 62 5E 4E 4C 08 4C 08 4C 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 08 3D 0E 93 3E 4F +CC 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BE 42 B2 49 +7C 43 B2 49 44 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 C2 4C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 4A 43 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 40 22 45 AC 40 52 41 8C 43 1E 40 04 1B +5B 37 6D 00 0C 44 0C 44 1E 40 04 1B 5B 30 6D 00 +0C 44 58 49 B0 12 7E 41 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 8C 43 1E 40 +07 0D 0A 1B 5B 37 6D 23 0C 44 70 46 1E 40 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 0C 44 0A 40 40 FF 32 40 +38 45 3C 46 1E 40 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 40 46 41 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 41 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 40 00 40 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 D3 06 02 B2 40 FC FF 02 02 B2 43 26 02 +B2 D3 22 02 E2 D2 25 02 B2 43 42 02 B2 D3 46 02 +B2 43 62 02 B2 D3 66 02 F2 43 26 03 F2 D3 22 03 +F2 40 A5 00 61 01 82 43 62 01 82 43 66 01 B2 40 +33 00 64 01 D2 43 61 01 39 40 40 00 18 42 00 18 +18 83 FE 23 19 83 FA 23 F2 D0 10 00 2A 03 F2 40 +A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 39 40 +00 10 29 83 89 43 00 1C FC 23 19 42 9E 01 1E 42 +08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 40 +86 41 00 00 0C 41 43 43 45 50 54 00 30 40 C0 42 +08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 +1E 43 3C 40 2A 43 5D 15 93 3E 21 52 3A 17 58 42 +CC 05 48 9B 09 20 A2 B3 DC 05 FD 27 B2 40 13 00 +CE 05 E2 D2 23 02 30 41 48 9C 06 2C 78 92 11 20 +2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 +1E 53 A2 B3 DC 05 FD 27 C2 48 CE 05 30 4D 20 43 +2D 83 92 B3 DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 +DC 05 FD 27 58 42 CC 05 08 4C EB 3F 00 00 06 4B +45 59 30 40 46 43 30 12 5C 43 A2 B3 DC 05 FD 27 +B2 40 11 00 CE 05 E2 C2 23 02 30 41 2F 83 8F 4E +00 00 92 B3 DC 05 FD 27 B0 12 E6 42 1E 42 CC 05 +30 4D 00 00 08 45 4D 49 54 00 30 40 7E 43 08 4E +3E 4F C7 3F 74 43 08 45 43 48 4F 00 B2 40 C2 48 +18 43 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 +30 4D 18 43 30 4D 0D 12 3D 40 C6 43 1B 42 32 20 +9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 +1B 42 20 20 02 3C C8 43 2D 83 0C 9B 16 2C 58 4C +00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 +82 4C 1E 20 3D 41 3C 40 20 00 A6 3F 0E 99 91 27 +CA 48 00 00 1A 53 1E 53 8C 3F 1A 15 B0 12 58 57 +19 17 DC 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +1C 44 29 4F 8F 4E 00 00 7E 49 AF 3F 1E 44 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 3A 22 F9 98 +00 00 37 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 2E 22 9B 24 3E 43 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 40 00 00 3C 45 2E 44 80 46 +3A 49 B0 40 AA 44 14 40 06 5B 54 48 45 4E 5D 00 +32 44 88 44 4E 44 6C 44 14 40 06 5B 45 4C 53 45 +5D 00 32 44 9A 44 4E 44 6A 44 1E 40 04 5B 49 46 +5D 00 32 44 6C 44 B2 40 6A 44 1E 40 05 0D 6B 6F +20 0A 0C 44 9A 40 84 40 B2 40 6C 44 5A 44 0D 5B +54 48 45 4E 5D 00 30 4D BE 44 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D CA 44 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 2E 44 80 46 E8 46 8C 48 +FC 45 DA 44 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 2E 44 80 46 E8 46 0C 45 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D B4 42 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D D8 41 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A 40 1E 40 EA 48 0A 40 22 00 80 46 80 45 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 96 43 05 2E 22 00 0D 12 84 12 6A 45 +0A 40 0C 44 EA 48 FC 45 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D 66 45 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 40 BF 4F 00 00 7A 90 0A 00 02 28 +7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D +C8 4A 00 00 30 4D B8 45 04 23 53 00 0D 12 84 12 +BA 45 F4 45 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +E8 45 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 02 46 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 86 43 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 AE 45 2E 44 1C 46 +EC 45 18 45 2A 46 06 46 0C 44 FC 45 96 45 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D 6E 46 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 F2 47 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 F4 47 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 40 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +AA 45 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 40 2E 44 80 46 B0 40 C4 49 E8 46 AE 48 0A 4E +3E 4F 3D 40 C8 48 6D 27 3D 40 A2 48 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 CA 48 3E 4F 3D 40 A2 48 +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 A0 4A 2A 3C 92 48 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D E8 48 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D 24 46 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D 4A 45 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E 40 02 0D 0A 00 0C 44 94 40 9C 48 2A 45 54 45 +1E 40 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 41 +32 40 0A 40 40 FF 5C 45 1E 40 09 46 52 41 4D 20 +66 75 6C 6C 08 41 B2 40 60 49 4A 49 0D 41 42 4F +52 54 22 00 0D 12 84 12 6A 45 0A 40 08 41 EA 48 +FC 45 7A 46 02 27 0D 12 84 12 2E 44 80 46 E8 46 +B0 40 C6 49 8E 45 D2 48 F4 44 07 5B 27 5D 0D 12 +84 12 B6 49 0A 40 0A 40 EA 48 EA 48 FC 45 CA 49 +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D 42 45 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 2E 44 80 46 E8 46 B0 40 C6 49 54 45 AC 40 +1E 4A 0A 40 0A 40 EA 48 EA 48 0A 40 EA 48 EA 48 +FC 45 00 00 02 3A 30 12 74 4A 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 2E 44 80 46 3C 4A 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 40 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 41 E0 49 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A 40 FC 45 EA 48 86 4A E2 49 FC 45 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D 34 49 0C 43 52 45 41 54 45 00 B0 12 2A 4A +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 06 44 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D 24 4A 0E 3A 4E 4F 4E 41 4D 45 +30 12 74 4A 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F BE 4A 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 B6 49 40 4B +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 CE 49 0A 40 +42 4B EA 48 FC 45 D4 4A 08 43 4F 44 45 00 B0 12 +2A 4A A2 82 C8 1D 61 3C 16 46 0E 48 44 4E 43 4F +44 45 B2 40 2E 4C CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 86 4A 8C 4B 3D 41 92 42 +D0 1D CC 1D 5D 3C 58 4B 0E 43 4F 44 45 4E 4E 4D +30 12 62 4B B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F 6A 4B 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F F6 4B B2 40 08 4C D0 1D 82 4E CE 1D +30 40 8E 45 85 12 F4 4B F4 49 68 58 64 5A 76 58 +FE 5D 38 46 E2 46 DE 5C DC 4B 2E 4B 08 4B A4 4A +84 58 10 4D 48 5A 00 00 00 00 85 12 F4 4B 8A 53 +0E 52 30 54 36 51 92 51 E0 51 BC 52 76 54 58 50 +7C 51 00 00 00 00 CA 4B 48 4F 00 00 E4 52 28 4C +B2 40 08 4C CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +5C 4C 30 4D 6E 4C 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 5C 4C 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 08 42 FE FF 29 83 B9 40 F2 41 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 F0 FF 3B 40 +10 00 3A 40 3A 18 B0 12 60 4C 82 43 4A 18 C7 3F +02 4D B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F EA 49 +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +2E 44 80 46 E8 46 AC 40 2E 4D 22 45 C2 48 30 4D +3E 4F 3D 41 B2 41 C6 1D B0 12 2A 4A BA 40 85 12 +FC FF BA 40 00 4D FE FF 28 83 8A 48 00 00 BA 40 +82 40 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +80 46 E8 46 AC 40 9A 4D 7A 4D 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 00 4D 00 00 +01 20 3E 52 2E 83 21 53 30 41 92 47 AC 40 A2 4D +96 4D A4 4D B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 6A 4D 15 20 3E 40 2B 00 +B0 12 6A 4D 06 20 3E 40 2D 00 B0 12 6A 4D 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 80 46 92 47 AC 40 +C6 49 E4 4D 3E 51 3A 17 30 41 B0 12 AA 4D 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 80 46 92 47 AC 40 +1C 4E 14 4E 3E 90 10 00 E6 2B 7C 2D 1E 4E A2 41 +C6 1D E1 3F 03 20 B0 12 02 4E 43 3C 7A 90 23 00 +24 20 B0 12 B2 4D 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 B2 4D F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 FE 4D 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 02 4E 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 EA 4D +F2 3F 03 20 B0 12 02 4E F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 EA 4D EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 40 00 13 EA 48 FC 45 +0A 40 2C 00 E0 4E 24 4E 2E 44 EA 4E C2 4E 30 4F +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 20 4F 00 40 3C 4F 0A 4D 4F 56 2E 42 85 12 +20 4F 40 40 00 00 06 41 44 44 85 12 20 4F 00 50 +56 4F 0A 41 44 44 2E 42 85 12 20 4F 40 50 62 4F +08 41 44 44 43 00 85 12 20 4F 00 60 70 4F 0C 41 +44 44 43 2E 42 00 85 12 20 4F 40 60 A8 4B 08 53 +55 42 43 00 85 12 20 4F 00 70 8E 4F 0C 53 55 42 +43 2E 42 00 85 12 20 4F 40 70 9C 4F 06 53 55 42 +85 12 20 4F 00 80 AC 4F 0A 53 55 42 2E 42 85 12 +20 4F 40 80 B8 4F 06 43 4D 50 85 12 20 4F 00 90 +C6 4F 0A 43 4D 50 2E 42 85 12 20 4F 40 90 00 00 +08 44 41 44 44 00 85 12 20 4F 00 A0 E0 4F 0C 44 +41 44 44 2E 42 00 85 12 20 4F 40 A0 0E 4F 06 42 +49 54 85 12 20 4F 00 B0 FE 4F 0A 42 49 54 2E 42 +85 12 20 4F 40 B0 0A 50 06 42 49 43 85 12 20 4F +00 C0 18 50 0A 42 49 43 2E 42 85 12 20 4F 40 C0 +24 50 06 42 49 53 85 12 20 4F 00 D0 32 50 0A 42 +49 53 2E 42 85 12 20 4F 40 D0 00 00 06 58 4F 52 +85 12 20 4F 00 E0 4C 50 0A 58 4F 52 2E 42 85 12 +20 4F 40 E0 7E 4F 06 41 4E 44 85 12 20 4F 00 F0 +66 50 0A 41 4E 44 2E 42 85 12 20 4F 40 F0 2E 44 +E0 4E 24 4E 86 50 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F 3E 50 06 52 52 43 85 12 7E 50 +00 10 98 50 0A 52 52 43 2E 42 85 12 7E 50 40 10 +D2 4F 08 53 57 50 42 00 85 12 7E 50 80 10 A4 50 +06 52 52 41 85 12 7E 50 00 11 C0 50 0A 52 52 41 +2E 42 85 12 7E 50 40 11 B2 50 06 53 58 54 85 12 +7E 50 80 11 00 00 08 50 55 53 48 00 85 12 7E 50 +00 12 E6 50 0C 50 55 53 48 2E 42 00 85 12 7E 50 +40 12 DA 50 08 43 41 4C 4C 00 85 12 7E 50 80 12 +1A 53 0E 4A 84 12 70 46 1E 40 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 41 04 51 06 53 3E 3D +86 12 00 38 2C 51 04 53 3C 00 86 12 00 34 F4 50 +06 30 3E 3D 86 12 00 30 40 51 04 30 3C 00 86 12 +00 30 7C 4B 04 55 3C 00 86 12 00 2C 54 51 06 55 +3E 3D 86 12 00 28 4A 51 06 30 3C 3E 86 12 00 24 +68 51 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +EE 4F 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D 5E 51 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F CC 50 0A 42 45 47 49 4E 30 40 32 40 B6 51 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D 72 50 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 80 51 16 45 FC 45 D4 51 +0C 52 45 50 45 41 54 00 0D 12 84 12 14 52 98 51 +FC 45 44 52 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D 30 52 06 42 57 31 +85 12 42 52 00 00 5C 52 06 42 57 32 85 12 42 52 +00 00 68 52 06 42 57 33 85 12 42 52 00 00 80 52 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 7E 52 00 00 A4 52 +06 46 57 32 85 12 7E 52 00 00 B0 52 06 46 57 33 +85 12 7E 52 00 00 1E 52 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 B6 49 C2 48 +FC 45 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +EA 4E 0A 40 2C 00 80 46 92 47 AC 40 C6 49 2E 44 +E0 4E C2 4E 16 53 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 74 52 08 52 52 43 4D 00 85 12 00 53 50 00 +44 53 08 52 52 41 4D 00 85 12 00 53 50 01 52 53 +08 52 4C 41 4D 00 85 12 00 53 50 02 60 53 08 52 +52 55 4D 00 85 12 00 53 50 03 72 51 0A 50 55 53 +48 4D 85 12 00 53 00 15 7C 53 08 50 4F 50 4D 00 +85 12 00 53 00 17 D2 C3 23 02 E2 B2 60 02 02 24 +30 40 F2 41 1A 52 04 20 19 62 06 20 92 43 14 20 +C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 17 20 89 10 +C2 49 18 20 B0 12 0A 54 5A 53 FC 23 39 40 05 00 +D2 49 14 20 4E 06 82 93 46 06 05 24 92 B3 6C 06 +FD 27 C2 93 4C 06 59 83 F3 2F 19 83 0B 30 F2 43 +4E 06 82 93 46 06 03 24 92 B3 6C 06 FD 27 5A 92 +4C 06 F3 23 30 41 1A 43 E1 3F 19 43 3A 43 8A 10 +C2 4A 4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 +C2 93 4C 06 19 83 F3 23 5A 42 4C 06 30 41 6E 53 +12 52 5F 53 45 43 54 5F 57 58 1C D3 F2 40 51 00 +19 20 B0 12 96 53 38 20 B0 12 0A 54 6A 53 04 24 +FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 03 43 19 53 +39 90 01 02 F6 23 F2 43 4E 06 3C C0 03 00 D2 D3 +23 02 30 41 C8 52 12 57 5F 53 45 43 54 5F 57 58 +2C D3 F0 40 58 00 93 CB B0 12 96 53 15 20 3A 40 +FE FF 29 43 B0 12 0E 54 D2 49 00 1E 4E 06 03 43 +19 53 39 90 00 02 F8 23 39 40 03 00 B0 12 0C 54 +7A C0 E1 00 6A 82 D9 27 8C 10 1C 52 4C 06 D2 D3 +23 02 84 12 8C 43 1E 40 0B 3C 20 53 44 20 45 72 +72 6F 72 21 D6 54 2F 83 8F 4E 00 00 B2 40 10 00 +BE 1D 0E 4C 84 12 3C 46 12 41 B0 12 54 41 E2 B2 +60 02 8A 20 B2 40 81 A9 40 06 B2 40 03 00 46 06 +D2 D3 25 02 B2 D0 C0 04 0C 02 92 C3 40 06 39 40 +6E 01 29 83 89 43 02 20 FC 23 39 42 B0 12 0C 54 +D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 00 40 +18 20 B0 12 06 54 02 24 30 40 B8 54 B0 12 0A 54 +7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 B2 40 +00 48 18 20 B0 12 06 54 29 42 B0 12 0C 54 92 43 +14 20 82 43 16 20 78 43 3C 42 B2 40 00 77 18 20 +B0 12 06 54 B2 40 40 69 18 20 B0 12 C4 53 03 24 +58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 00 50 +18 20 B0 12 C4 53 D0 23 92 D3 40 06 82 43 46 06 +92 C3 40 06 0A 43 09 43 B0 12 3A 54 38 40 00 1E +92 48 C6 01 04 20 92 48 C8 01 06 20 5C 48 C2 01 +7C 80 0C 00 08 24 5C 53 06 24 6C 52 04 24 3C 50 +07 20 30 40 BE 54 09 43 B0 12 3A 54 A2 43 2C 20 +19 48 0E 00 82 49 08 20 1A 48 24 00 82 4A 0A 20 +09 5A 82 49 0C 20 09 5A 58 48 0D 00 82 48 12 20 +09 88 09 88 82 49 10 20 30 41 82 43 32 20 30 40 +84 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 5A 42 +23 20 58 42 22 20 59 42 24 20 89 10 0A D9 88 10 +08 58 0A 6A 88 10 08 58 30 41 1A 52 08 20 09 43 +FC 3E 92 42 22 20 D0 04 92 42 24 20 D2 04 92 42 +12 20 C8 04 92 42 E4 04 1A 20 92 42 E6 04 1C 20 +92 52 10 20 1A 20 82 63 1C 20 30 41 92 4B 0E 00 +22 20 92 4B 10 00 24 20 B0 12 42 56 5A 4B 03 00 +82 5A 1A 20 82 63 1C 20 30 41 3C 42 3B 40 38 20 +09 43 CB 93 02 00 10 24 9B 92 24 20 0C 00 04 20 +9B 92 22 20 0A 00 A3 25 09 4B 3B 50 1C 00 3B 90 +18 21 EF 23 0C 5C 9B 3D 0C 43 82 4B 32 20 8B 49 +00 00 09 93 0A 24 99 52 C6 1D 16 00 4A 93 05 34 +C9 93 02 00 02 34 5A 59 02 00 CB 4A 02 00 CB 43 +03 00 9B 42 1A 20 04 00 9B 42 1C 20 06 00 18 42 +30 20 8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 14 1E +0C 00 9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 +1C 1E 12 00 9B 48 1E 1E 14 00 82 43 1E 20 6A 93 +1A 24 A4 37 8B 43 16 00 7A 93 02 24 07 38 35 3C +B2 40 1C 21 A0 40 B2 40 A6 43 BE 42 9B 42 C2 1D +18 00 9B 82 C6 1D 18 00 9B 42 C4 1D 1A 00 9B 52 +C6 1D 1A 00 22 3C 30 41 1B 42 32 20 82 43 1E 20 +B2 90 00 02 20 20 3F 20 BB 80 00 02 12 00 8B 73 +14 00 DB 53 03 00 DB 92 12 20 03 00 0E 28 CB 43 +03 00 B0 12 12 56 B0 12 3A 56 8B 43 10 00 9B 48 +00 1E 0E 00 9B 48 02 1E 10 00 B2 40 00 02 20 20 +8B 93 14 00 0B 20 92 9B 12 00 1E 20 1C 2C BB 90 +00 02 12 00 03 2C 92 4B 12 00 20 20 B0 12 6C 56 +1A 42 1A 20 19 42 1C 20 38 3E CB 43 02 00 2B 4B +82 4B 32 20 0B 93 06 24 92 4B 16 00 1E 20 B0 12 +9A 57 22 C3 30 41 1B 42 32 20 0B 93 FB 27 EB 92 +02 00 04 20 B0 12 58 5B B0 12 48 5C CB 93 02 00 +E4 37 1E 4B 18 00 9F 4B 1A 00 00 00 31 50 06 00 +3D 41 B0 12 CA 57 02 24 30 40 9E 43 B2 40 3C 1D +A0 40 B2 40 C0 42 BE 42 30 40 8C 43 09 93 07 24 +F8 90 20 00 00 1E 03 20 18 53 19 83 F9 23 30 41 +86 4C 0B 52 45 41 44 22 5A 43 20 3C EE 4A 09 44 +45 4C 22 00 6A 43 1A 3C B4 49 0D 57 52 49 54 45 +22 00 6A 42 13 3C 9C 49 0F 41 50 50 45 4E 44 22 +7A 42 0C 3C 98 4B 0A 43 4C 4F 53 45 B0 12 E6 57 +30 4D FC 48 0B 4C 4F 41 44 22 7A 43 2F 83 8F 4E +00 00 0E 4A 82 93 BC 1D 0B 24 0D 12 84 12 0A 40 +0A 40 EA 48 EA 48 6A 45 0A 40 C0 58 EA 48 FC 45 +0D 12 84 12 0A 40 22 00 80 46 3A 49 BE 58 3D 41 +36 4F 0E 56 82 4E 36 20 A2 43 22 20 82 43 24 20 +1C 43 0E 96 8C 24 F6 90 3A 00 01 00 01 20 26 53 +F6 90 5C 00 00 00 03 20 16 53 0E 96 66 24 82 46 +34 20 B0 12 42 56 15 42 12 20 B0 12 C0 57 2C 43 +0A 43 08 4A 58 0E 08 58 82 48 30 20 C8 93 00 1E +60 24 39 42 F8 96 00 1E 04 20 18 53 19 83 FA 23 +16 53 F6 90 2E 00 FF FF 19 24 39 50 03 00 B0 12 +2C 58 06 20 F6 90 5C 00 FF FF 29 24 0E 96 27 28 +16 42 34 20 1A 53 3A 90 10 00 DB 23 92 53 1A 20 +82 63 1C 20 15 83 D1 23 2C 42 49 3C F6 90 2E 00 +FE FF EE 27 B0 12 2C 58 EB 23 39 40 03 00 F8 96 +00 1E 04 20 18 53 19 83 FA 23 09 3C 0E 96 E0 2F +F6 90 5C 00 FF FF DC 23 B0 12 2C 58 D9 23 18 42 +30 20 92 48 1A 1E 22 20 92 48 14 1E 24 20 F8 B0 +10 00 0B 1E 13 24 82 93 24 20 05 20 82 93 22 20 +02 20 A2 43 22 20 0E 96 9A 23 92 42 22 20 2C 20 +92 42 24 20 2E 20 8F 43 00 00 03 3C 2A 4F B0 12 +8A 56 35 40 B6 40 36 40 C4 40 3A 4F 3E 4F 0A 93 +04 24 7A 93 39 20 0C 93 02 20 30 40 9E 43 0D 12 +84 12 8C 43 1E 40 0B 3C 20 4F 70 65 6E 45 72 72 +6F 72 B2 40 D4 54 E2 B2 60 02 02 24 30 40 86 41 +92 12 3E 18 3F 40 7E 1C 8F 43 00 00 0D 12 84 12 +1E 40 0F 4C 4F 41 44 22 20 42 4F 4F 54 2E 34 54 +48 22 B2 40 6A 49 42 58 08 42 4F 4F 54 00 B2 40 +06 5A B0 42 30 4D 3A 47 0C 4E 4F 42 4F 4F 54 00 +B2 40 86 41 B0 42 30 4D 1A 93 89 20 0C 93 C7 23 +30 4D 38 5A 08 52 45 41 44 00 2F 83 8F 4E 00 00 +1E 42 32 20 B0 12 58 57 1E 82 32 20 30 4D 08 4A +1A 52 08 20 B0 12 8E 5A 0A 48 1A 52 0C 20 09 43 +30 40 80 54 3C 42 0A 12 2A 41 82 9A 0A 20 2B 25 +B0 12 3A 56 88 93 02 1E 03 20 88 93 00 1E 08 24 +28 52 38 90 00 02 F6 2B 91 53 00 00 08 43 EC 3F +A2 41 26 20 82 48 28 20 0C 43 B8 43 00 1E 6A 41 +B8 40 FF 0F 02 1E 08 11 8A 10 08 5A 5A 41 01 00 +0A 11 08 10 82 4A 24 20 82 48 22 20 2A 41 B0 12 +7E 5A 3A 41 30 41 90 4B 0A 00 28 C5 90 4B 0C 00 +24 C5 B0 12 1E 56 82 4A 26 20 82 48 28 20 0A 12 +B0 12 3A 56 1A 48 00 1E 88 43 00 1E 19 48 02 1E +88 43 02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 +10 24 82 4A 22 20 82 49 24 20 B0 12 1E 56 2A 91 +E9 27 09 4A 2A 41 81 49 00 00 B0 12 7E 5A 2A 41 +DF 3F 3A 41 30 40 7E 5A 9B 52 1E 20 12 00 8B 63 +14 00 1A 42 1A 20 19 42 1C 20 30 40 80 54 2A 93 +BC 20 0C 93 09 20 F8 40 E5 00 00 1E B0 12 62 5B +B0 12 F6 5A B0 12 E6 57 30 4D F2 B0 40 00 A2 04 +29 20 F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 4A 11 +59 42 B4 04 F2 40 20 00 C0 04 D2 42 B1 04 C8 04 +1A 52 E4 04 D2 42 B5 04 C8 04 19 52 E4 04 D2 42 +B2 04 C0 04 B2 40 00 08 C8 04 1A 52 E4 04 92 42 +B6 04 C0 04 B2 80 BC 07 C0 04 B2 40 00 02 C8 04 +19 52 E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E +3F 5B 5C 5D 7C 2E 29 92 06 28 39 80 03 00 B0 12 +36 5C 39 40 03 00 7A 4B C8 4A 00 1E 82 9B 36 20 +12 28 0D 12 3D 40 0F 00 3C 40 E6 5B 7A 9C F3 27 +1D 83 FC 23 3D 41 6A 9C E6 27 3A 80 21 00 EB 3B +18 53 19 83 E8 23 09 93 06 24 F8 40 20 00 00 1E +18 53 19 83 FA 23 30 41 1A 4B 04 00 19 4B 06 00 +B0 12 3A 54 18 4B 08 00 B0 12 8A 5B 88 49 12 1E +88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E 98 4B +14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 80 54 +B2 40 00 02 1E 20 1B 42 32 20 B0 12 58 5B 82 43 +1E 20 DB 53 03 00 DB 92 12 20 03 00 1D 28 B0 12 +12 56 08 12 0A 12 B0 12 94 5A 2A 91 03 24 2A 41 +B0 12 3A 56 3A 41 38 41 98 42 22 20 00 1E 98 42 +24 20 02 1E B0 12 7E 5A AB 42 02 00 9B 42 22 20 +0E 00 9B 42 24 20 10 00 30 40 78 56 5A 58 0A 57 +52 49 54 45 B0 12 80 5C 30 4D 2A 92 54 20 2C 93 +0E 24 0C 93 3D 24 0D 12 84 12 1E 40 0C 3C 20 57 +72 69 74 65 45 72 72 6F 72 00 B2 40 D4 54 0A 43 +08 43 B0 12 94 5A B0 12 C0 57 18 42 30 20 F8 40 +20 00 0B 1E B0 12 8A 5B 88 43 0C 1E 88 4A 0E 1E +88 49 10 1E 98 42 24 20 14 1E 98 42 22 20 1A 1E +88 43 1C 1E 88 43 1E 1E 2C 42 1B 42 34 20 82 9B +36 20 D1 27 FB 90 2E 00 00 00 CD 27 39 40 0B 00 +B0 12 06 5C B0 12 62 5B 2A 42 B0 12 8A 56 30 4D +B0 12 F6 5A 8B 43 12 00 8B 43 14 00 90 4B 0A 00 +A2 C2 90 4B 0C 00 9E C2 B0 12 1E 56 B0 12 94 5A +B0 12 C8 5C 30 4D 2C 93 BA 27 0C 93 AC 23 EB 42 +02 00 58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B +15 00 5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 +1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 +19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 +CB 4A 03 00 B0 12 BC 57 1A 4B 12 00 BB C0 FF 01 +12 00 3A F0 FF 01 82 4A 1E 20 30 4D 4E 58 10 54 +45 52 4D 32 53 44 22 00 0D 12 84 12 62 58 10 5E +0A 43 B0 12 4A 43 92 B3 DC 05 FD 27 59 42 CC 05 +C2 49 CE 05 69 92 0D 24 CA 49 00 1E 1A 53 3A 90 +FF 01 04 24 F0 2B B0 12 80 5C EA 3F B0 12 E6 42 +EA 3F F2 90 0D 00 CC 05 FC 27 B0 12 E6 42 F2 90 +0A 00 CC 05 FC 27 82 4A 1E 20 B0 12 E6 57 3D 41 +30 4D +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +DA 42 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 08 42 +q diff --git a/binaries/MSP_EXP430FR5994_1MHz_I2C.txt b/binaries/MSP_EXP430FR5994_1MHz_I2C.txt index 070a11c..34ced74 100644 --- a/binaries/MSP_EXP430FR5994_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5994_1MHz_I2C.txt @@ -1,657 +1,503 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF 04 68 3E 4D 34 01 -10 00 C1 87 B6 41 50 5F B8 41 0E 5E 84 42 04 68 -3E 4D 72 42 E0 43 00 43 DC 42 3C 1D AE 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +D4 42 56 41 E6 55 C6 54 44 41 44 5E 2A 4C E4 4B +E4 4B C2 42 46 43 1E 43 3C 1D E0 1C D8 45 B6 40 +C4 40 F4 44 20 00 0A 00 00 1C 56 41 E6 55 C6 54 +44 41 44 5E 2A 4C E4 4B E4 4B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4000 -B0 12 B8 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 50 5F 39 40 22 18 -B2 49 70 42 B2 49 DE 43 B2 49 FE 42 B2 49 DA 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 46 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 41 0E 12 B0 12 -F8 40 0A 40 DE 1D 2E 44 18 43 EE 40 34 40 8A 41 -14 40 05 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 F6 43 34 40 7E 41 14 40 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 AA 43 EE 44 AA 43 -14 40 04 1B 5B 30 6D 00 AA 43 76 48 2E 93 13 28 -B2 D0 C0 07 C0 06 18 42 02 18 08 11 38 D0 00 04 -82 48 D4 06 F2 D0 03 00 6A 02 92 C3 C0 06 A2 D2 -EA 06 92 C3 30 01 30 41 48 43 A2 B3 EC 06 FD 27 -C2 48 CE 06 A2 B2 EC 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 41 04 57 41 52 4D 00 -B0 12 0E 5E 78 40 03 00 B0 12 BA 41 84 12 14 40 -07 0D 0A 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 0A 40 23 00 FC 42 24 45 14 40 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 AA 43 0A 40 40 FF 28 40 22 44 -EE 44 14 40 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 40 7E 41 00 00 06 41 43 43 45 50 54 00 30 40 -72 42 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 EC 06 B2 B0 10 00 C0 06 -B7 22 3A 17 92 B3 EC 06 FD 27 58 42 CC 06 48 9B +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 09 3D 0E 93 3E 4F +BA 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 C0 42 B2 49 +44 43 B2 49 1C 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 9E 4C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 41 B0 12 D0 40 FE 44 AC 40 +42 41 5E 43 1E 40 05 1B 5B 37 6D 40 E8 43 0A 40 +02 18 20 45 4C 46 E8 43 1E 40 04 1B 5B 30 6D 00 +E8 43 34 49 48 43 A2 B3 EC 06 FD 27 C2 48 CE 06 +A2 B2 EC 06 FD 27 30 41 B2 D0 C0 07 C0 06 18 42 +02 18 08 11 38 D0 00 04 82 48 D4 06 F2 D0 03 00 +6A 02 92 C3 C0 06 A2 D2 EA 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 5E 43 1E 40 07 0D 0A 1B 5B 37 +6D 40 E8 43 0A 40 02 18 20 45 4C 46 0A 40 23 00 +42 43 4C 46 1E 40 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +E8 43 0A 40 40 FF 32 40 14 45 18 46 1E 40 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 40 36 41 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 41 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +40 00 40 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 +FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 42 02 +B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 26 03 +F2 D3 22 03 F2 40 A5 00 61 01 82 43 62 01 82 43 +66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 F2 D0 10 00 +2A 03 F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 +B0 01 39 40 00 10 29 83 89 43 00 1C FC 23 1E 42 +08 18 82 43 08 18 3E F3 02 20 1E 42 9E 01 B0 12 +D0 40 80 41 00 00 0C 41 43 43 45 50 54 00 30 40 +C2 42 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 +3D 15 96 3E 21 52 A2 C2 EC 06 B2 B0 10 00 C0 06 +8F 22 3A 17 92 B3 EC 06 FD 27 58 42 CC 06 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 41 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 42 2F 83 8F 4E -00 00 58 43 B0 12 BA 41 92 B3 EC 06 FD 27 1E 42 -CC 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 43 -08 4E 3E 4F A2 B3 EC 06 FD 27 C2 48 CE 06 30 4D -F6 42 04 45 43 48 4F 00 B2 40 C2 48 0A 43 82 43 -DE 1D 38 40 05 00 B0 12 BA 41 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 43 92 43 DE 1D -28 42 F1 3F 0D 12 3D 40 64 43 1B 42 32 20 9B 42 -1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 1B 42 -20 20 02 3C 66 43 2D 83 0C 9B 16 2C 58 4C 00 1E -1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 3D 41 -82 4C 1E 20 3C 40 20 00 9D 3F 0E 99 BB 27 CA 48 -00 00 1A 53 1E 53 B6 3F 1A 15 B0 12 06 60 19 17 -DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 C6 43 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FE 42 C8 43 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 41 02 43 52 00 30 40 E0 43 -0D 12 84 12 14 40 02 0D 0A 00 AA 43 AE 44 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 66 42 01 40 2E 4E -30 4D 2C 44 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D D8 43 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 68 44 02 23 53 00 0D 12 84 12 -6A 44 A4 44 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 98 44 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D A4 43 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 5E 44 -9C 44 EE 40 DC 44 B8 44 AA 43 62 48 FC 42 AE 44 -2E 43 01 2E 0E 93 E3 37 38 43 E2 3F D6 44 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 A8 47 -0A 40 22 00 7A 45 48 45 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D 22 45 -82 2E 22 00 0D 12 84 12 32 45 0A 40 AA 43 A8 47 -AE 44 FA 41 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 +F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F +08 4C 1B 3C 00 00 06 4B 45 59 30 40 1E 43 58 43 +B0 12 46 41 2F 83 8F 4E 00 00 92 B3 EC 06 FD 27 +1E 42 CC 06 B0 12 44 41 30 4D 00 00 08 45 4D 49 +54 00 30 40 46 43 08 4E 3E 4F A2 B3 EC 06 FD 27 +C2 48 CE 06 30 4D 3C 43 08 45 43 48 4F 00 B2 40 +C2 48 50 43 38 40 05 00 B0 12 46 41 30 4D 00 00 +0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 50 43 28 42 +F3 3F 0D 12 3D 40 A2 43 1B 42 32 20 9B 42 1E 20 +16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 1B 42 20 20 +02 3C A4 43 2D 83 0C 9B 16 2C 58 4C 00 1E 1C 53 +78 90 20 00 09 2C 78 90 0A 00 F5 23 82 4C 1E 20 +3D 41 3C 40 20 00 A4 3F 0E 99 BF 27 CA 48 00 00 +1A 53 1E 53 BA 3F 1A 15 B0 12 34 57 19 17 DC 3F +00 00 08 54 59 50 45 00 0D 12 3D 40 F8 43 29 4F +8F 4E 00 00 7E 49 A5 3F FA 43 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 4C 22 F9 98 00 00 49 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +40 22 9B 24 16 43 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A 40 00 00 18 45 0A 44 5C 46 16 49 B0 40 +86 44 14 40 06 5B 54 48 45 4E 5D 00 0E 44 64 44 +2A 44 48 44 14 40 06 5B 45 4C 53 45 5D 00 0E 44 +76 44 2A 44 46 44 1E 40 04 5B 49 46 5D 00 0E 44 +48 44 B2 40 46 44 1E 40 05 0D 6B 6F 20 0A E8 43 +9A 40 84 40 B2 40 48 44 36 44 0D 5B 54 48 45 4E +5D 00 30 4D 9A 44 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D A6 44 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 0A 44 5C 46 C4 46 68 48 D8 45 B6 44 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +0A 44 5C 46 C4 46 E8 44 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D B6 42 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +E0 41 05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 40 +1E 40 C6 48 0A 40 22 00 5C 46 5C 45 B2 40 20 00 +C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D +70 43 05 2E 22 00 0D 12 84 12 46 45 0A 40 E8 43 +C6 48 D8 45 00 00 04 3C 23 00 B2 40 B2 1D B2 1D +30 4D 42 45 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 +46 40 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 +30 4D 94 45 04 23 53 00 0D 12 84 12 96 45 D0 45 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D C4 45 04 23 +3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F DE 45 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 58 43 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 8A 45 0A 44 F8 45 C8 45 F4 44 +06 46 E2 45 E8 43 D8 45 72 45 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D +1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D 4A 46 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 FC 46 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F FE 46 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D A6 47 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -B4 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D C8 44 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 40 62 48 7A 45 1E 48 9C 26 -3D 40 26 48 DE 3E 28 48 0A 4E 3E 4F 3D 40 42 48 -36 27 3D 40 18 48 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 44 48 3E 4F 3D 40 18 48 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 E4 49 CC 3F -4C 48 86 12 20 00 34 44 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 DC 43 BC 40 -12 48 12 44 44 44 14 40 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 4C 44 -14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 41 -3A 40 8C 48 68 48 86 41 42 4F 52 54 22 00 0D 12 -84 12 32 45 0A 40 2A 41 A8 47 AE 44 DC 45 01 27 -0D 12 84 12 62 48 7A 45 E2 45 34 40 60 48 AE 44 -00 00 83 5B 27 5D 0D 12 84 12 E0 48 0A 40 0A 40 -A8 47 A8 47 AE 44 F2 48 81 5B 82 43 BE 1D 30 4D -5A 44 01 5D B2 43 BE 1D 30 4D 12 49 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 62 48 7A 45 E2 45 F6 43 34 40 -60 48 44 44 34 40 54 49 0A 40 0A 40 A8 47 A8 47 -0A 40 A8 47 A8 47 AE 44 08 49 01 3A 30 12 A4 49 -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 62 48 7A 45 -72 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 41 5A 49 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 40 AE 44 A8 47 B6 49 0A 49 AE 44 -08 48 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D F2 47 06 43 52 45 41 54 -45 00 B0 12 60 49 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F E8 49 07 3A 4E 4F 4E 41 4D 45 30 12 A4 49 -2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 0E 4A -39 40 10 02 08 49 28 53 99 3F 12 43 05 44 45 46 -45 52 B0 12 60 49 BA 40 30 40 FC FF BA 40 E2 4D -FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 02 4A 82 49 -53 00 0D 12 82 93 BE 1D 06 24 84 12 F6 48 0A 40 -74 4A A8 47 AE 44 84 12 E0 48 74 4A AE 44 1A 4A -04 43 4F 44 45 00 B0 12 60 49 A2 82 C6 1D 82 43 -66 5C 0D 12 84 12 48 4D 1A 4D AE 44 7E 4A 07 48 -44 4E 43 4F 44 45 B2 40 1E 4D DA 1D EC 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 B6 49 6E 4D -A2 4D AE 44 A0 4A 07 43 4F 44 45 4E 4E 4D 30 12 -AA 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 6E 4D A2 4D AE 44 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -BE 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 82 4C -A8 47 0A 49 AE 4A AE 44 34 4A 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 4A 4B 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 40 00 00 26 44 62 48 7A 45 F8 47 -EE 43 34 40 E2 4B FC 43 14 40 06 5B 54 48 45 4E -5D 00 54 4B BC 4B 78 4B 9A 4B AE 44 FC 43 14 40 -06 5B 45 4C 53 45 5D 00 54 4B D2 4B 78 4B 98 4B -AE 44 14 40 04 5B 49 46 5D 00 54 4B 9A 4B 3A 40 -98 4B D0 43 14 40 05 0D 0A 6B 6F 20 AA 43 BC 40 -AC 40 3A 40 9A 4B 88 4B 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D F8 4B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 62 48 7A 45 E2 45 -06 4C AE 44 0C 4C 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 16 4C 3E 44 AE 44 3E 4C B2 4E -0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C BA 47 -06 4D 41 52 4B 45 52 00 B0 12 60 49 BA 40 85 12 -FC FF BA 40 3C 4C FE FF 28 83 8A 48 00 00 9A 42 -C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 C6 1D -9D 3E 2E 53 30 4D 5C 4A 05 44 4F 45 53 3E 1A 42 -BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D -74 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 0D 12 -84 12 22 4A 0A 40 10 00 0A 40 00 00 3E 40 0A 40 -00 00 A8 47 60 40 BE 4C 28 40 0A 40 C8 1D EE 43 -2E 44 A8 47 36 44 8E 4C 0A 40 CA 1D 36 44 AE 44 -DE 48 05 46 4F 52 54 48 85 12 D8 4C 42 4D 9A 63 -CE 61 E2 4C 32 4B D4 42 E8 61 88 4D 14 4E F0 63 -98 67 B4 66 00 00 8C 63 1C 49 42 46 00 00 C6 48 -09 41 53 53 45 4D 42 4C 45 52 85 12 D8 4C 32 5B -CA 5A 2E 5A EE 54 80 53 00 00 F6 58 00 00 56 5C -52 5D E4 53 98 5D FE 5A 00 00 00 00 C8 54 0C 4D -10 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 D6 1D -08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 -30 4D 28 49 08 50 52 45 56 49 4F 55 53 00 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 60 45 04 4F 4E 4C 59 00 82 43 -CC 1D 30 4D 88 4C 0B 44 45 46 49 4E 49 54 49 4F -4E 53 92 42 CA 1D DA 1D 30 4D E8 4C 8E 4D A2 4D -B2 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 -10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B -89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F -3D 41 30 4D 64 4D 09 50 57 52 5F 53 54 41 54 45 -85 12 AA 4D 3E 4D 04 68 2E 45 09 52 53 54 5F 53 -54 41 54 45 92 42 0A 18 F6 4D 92 42 0C 18 F4 4D -EF 3F E6 4D 08 50 57 52 5F 48 45 52 45 00 92 42 -C6 1D F6 4D 92 42 C8 1D F4 4D 30 4D FA 4D 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 92 42 -C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 DA 37 -0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 96 4E FE FF 29 83 B9 40 E2 41 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 41 B2 49 FA 40 -B2 49 02 40 B2 49 02 42 B2 49 BC FF B2 49 0A 18 -B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 10 00 -00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 80 1C -39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 06 02 -B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 -42 02 B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 -26 03 F2 D3 22 03 F2 40 A5 00 61 01 82 43 62 01 -82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 -40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 F2 D0 -10 00 2A 03 F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 -B2 42 B0 01 1E 42 08 18 82 43 08 18 1E D2 9E 01 -B0 12 F8 40 00 42 38 40 C0 1D 0A 4E 39 48 2E 48 -09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 -0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 12 12 -C4 1D 84 12 7A 45 E2 45 3E 44 34 40 76 4F 9E 46 -34 40 90 4F 8A 4F 78 4F 3C 4E 3C 80 87 12 05 24 -1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 -92 4F B2 41 C4 1D 3E 41 84 12 0A 40 2B 00 7A 45 -E2 45 3E 44 34 40 AE 4F 9E 46 34 40 60 48 08 44 -7A 45 9E 46 34 40 60 48 BA 4F 3E 5F E7 3F 32 B0 -00 02 01 24 3E 4F 30 41 3E 40 28 00 B0 12 5A 4F -B0 12 BE 4F 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 -3E 40 29 00 1C 15 92 92 C0 1D C4 1D 02 20 30 40 -CE 49 12 12 C4 1D 92 53 C4 1D 84 12 7A 45 9E 46 -34 40 10 50 06 50 21 53 3E 90 10 00 84 2D BE 2B -12 50 B2 41 C4 1D BA 3F 0D 12 84 12 62 48 36 4F -22 50 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F -7A 90 23 00 29 20 92 53 C4 1D B0 12 5A 4F B0 12 -BE 4F 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D +0C 4E 0E 43 1E 15 3D 40 CE 47 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 D0 47 +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 +0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 40 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D 86 45 03 5C +92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 40 0A 44 +5C 46 B0 40 A0 49 C4 46 8A 48 0A 4E 3E 4F 3D 40 +A4 48 6D 27 3D 40 7E 48 1A E2 BC 1D 14 24 0E 12 +3E 4F 30 41 A6 48 3E 4F 3D 40 7E 48 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 7C 4A +2A 3C 6E 48 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E +FE FF 3E 4F 30 4D C4 48 0F 4C 49 54 45 52 41 4C +82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D +BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D 00 46 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D 26 45 0A 41 4C 4C 4F 54 82 5E C8 1D +3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 40 02 0D +0A 00 E8 43 94 40 78 48 06 45 30 45 1E 40 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 41 32 40 0A 40 +40 FF 38 45 1E 40 09 46 52 41 4D 20 66 75 6C 6C +08 41 B2 40 3C 49 26 49 0D 41 42 4F 52 54 22 00 +0D 12 84 12 46 45 0A 40 08 41 C6 48 D8 45 56 46 +02 27 0D 12 84 12 0A 44 5C 46 C4 46 B0 40 A2 49 +6A 45 AE 48 D0 44 07 5B 27 5D 0D 12 84 12 92 49 +0A 40 0A 40 C6 48 C6 48 D8 45 A6 49 03 5B 82 43 +BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D 1E 45 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 0A 44 +5C 46 C4 46 B0 40 A2 49 30 45 AC 40 FA 49 0A 40 +0A 40 C6 48 C6 48 0A 40 C6 48 C6 48 D8 45 00 00 +02 3A 30 12 50 4A 92 B3 C8 1D A2 63 C8 1D 0D 12 +84 12 0A 44 5C 46 18 4A 3D 41 5A D3 5A 53 0A 5E +19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D +82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D +30 4D 82 9F BA 1D 66 25 84 12 1E 40 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 41 BC 49 +03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 40 D8 45 +C6 48 62 4A BE 49 D8 45 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D 10 49 +0C 43 52 45 41 54 45 00 B0 12 06 4A BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D E2 43 0A 44 4F 45 53 3E +1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D 00 4A 0E 3A 4E 4F 4E 41 4D 45 30 12 50 4A +2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F 9A 4A 05 49 53 00 0D 12 +82 93 BC 1D 08 20 84 12 92 49 1C 4B 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 AA 49 0A 40 1E 4B C6 48 +D8 45 B0 4A 08 43 4F 44 45 00 B0 12 06 4A A2 82 +C8 1D 61 3C F2 45 0E 48 44 4E 43 4F 44 45 B2 40 +0A 4C CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 62 4A 68 4B 3D 41 92 42 D0 1D CC 1D +5D 3C 34 4B 0E 43 4F 44 45 4E 4E 4D 30 12 3E 4B +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 +BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D +1A 42 C8 1D EF 3F 46 4B 0B 48 49 32 4C 4F A2 53 +C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F +D2 4B B2 40 E4 4B D0 1D 82 4E CE 1D 30 40 6A 45 +85 12 D0 4B D0 49 44 58 40 5A 52 58 DA 5D 14 46 +BE 46 BA 5C B8 4B 0A 4B E4 4A 80 4A 60 58 EC 4C +24 5A 00 00 00 00 85 12 D0 4B 66 53 EA 51 0C 54 +12 51 6E 51 BC 51 98 52 52 54 34 50 58 51 00 00 +00 00 A6 4B 24 4F 00 00 C0 52 04 4C B2 40 E4 4B +CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 1D 3A 40 42 18 B0 12 38 4C 30 4D +4A 4C 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 1D B0 12 38 4C 1A 42 CA 1D 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +10 42 FE FF 29 83 B9 40 FA 41 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 BC FF 3B 40 10 00 3A 40 +3A 18 B0 12 3C 4C 82 43 4A 18 C7 3F DE 4C B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F C6 49 0C 4D 41 52 +4B 45 52 00 12 12 C6 1D 0D 12 84 12 0A 44 5C 46 +C4 46 AC 40 0A 4D FE 44 9E 48 0C 4D 3E 4F 3D 41 +B2 41 C6 1D B0 12 06 4A BA 40 85 12 FC FF BA 40 +DC 4C FE FF 28 83 8A 48 00 00 BA 40 82 40 02 00 +A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 1D 84 12 5C 46 C4 46 +AC 40 76 4D 56 4D 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 DC 4C 00 00 01 20 3E 52 +2E 83 21 53 30 41 6E 47 AC 40 7E 4D 72 4D 80 4D +B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E +3D 15 B0 12 46 4D 15 20 3E 40 2B 00 B0 12 46 4D +06 20 3E 40 2D 00 B0 12 46 4D 92 83 C6 1D 0E 12 +1E 41 02 00 84 12 5C 46 6E 47 AC 40 A2 49 C0 4D +3E 51 3A 17 30 41 B0 12 86 4D 19 42 C8 1D 89 4E +00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 +C6 1D 3D 15 84 12 5C 46 6E 47 AC 40 F8 4D F0 4D +3E 90 10 00 E6 2B 7C 2D FA 4D A2 41 C6 1D E1 3F +03 20 B0 12 DE 4D 43 3C 7A 90 23 00 24 20 B0 12 +8E 4D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 09 20 3C 40 -10 02 92 53 C4 1D B0 12 5A 4F B0 12 BE 4F EB 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D B0 12 -E4 4F 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 E4 4F -92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E -D8 3F B0 12 E4 4F FA 23 3C 50 10 00 B0 12 C8 4F -EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 -62 48 36 4F F6 50 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C5 3F B0 12 E4 4F E0 23 3C 50 -80 00 B0 12 C8 4F DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A 40 00 13 A8 47 AE 44 0A 40 2C 00 -18 50 EC 50 36 51 09 4B 2E 4E 0E DC A0 3F 20 4B -03 4D 4F 56 85 12 2C 51 00 40 40 51 05 4D 4F 56 -2E 42 85 12 2C 51 40 40 00 00 03 41 44 44 85 12 -2C 51 00 50 5A 51 05 41 44 44 2E 42 85 12 2C 51 -40 50 66 51 04 41 44 44 43 00 85 12 2C 51 00 60 -74 51 06 41 44 44 43 2E 42 00 85 12 2C 51 40 60 -1A 51 04 53 55 42 43 00 85 12 2C 51 00 70 92 51 -06 53 55 42 43 2E 42 00 85 12 2C 51 40 70 A0 51 -03 53 55 42 85 12 2C 51 00 80 B0 51 05 53 55 42 -2E 42 85 12 2C 51 40 80 F6 4A 03 43 4D 50 85 12 -2C 51 00 90 CA 51 05 43 4D 50 2E 42 85 12 2C 51 -40 90 D0 4A 04 44 41 44 44 00 85 12 2C 51 00 A0 -E4 51 06 44 41 44 44 2E 42 00 85 12 2C 51 40 A0 -D6 51 03 42 49 54 85 12 2C 51 00 B0 02 52 05 42 -49 54 2E 42 85 12 2C 51 40 B0 0E 52 03 42 49 43 -85 12 2C 51 00 C0 1C 52 05 42 49 43 2E 42 85 12 -2C 51 40 C0 28 52 03 42 49 53 85 12 2C 51 00 D0 -36 52 05 42 49 53 2E 42 85 12 2C 51 40 D0 00 00 -03 58 4F 52 85 12 2C 51 00 E0 50 52 05 58 4F 52 -2E 42 85 12 2C 51 40 E0 82 51 03 41 4E 44 85 12 -2C 51 00 F0 6A 52 05 41 4E 44 2E 42 85 12 2C 51 -40 F0 62 48 18 50 88 52 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F BC 51 03 52 52 43 85 12 -82 52 00 10 9A 52 05 52 52 43 2E 42 85 12 82 52 -40 10 A6 52 04 53 57 50 42 00 85 12 82 52 80 10 -B4 52 03 52 52 41 85 12 82 52 00 11 C2 52 05 52 -52 41 2E 42 85 12 82 52 40 11 CE 52 03 53 58 54 -85 12 82 52 80 11 00 00 04 50 55 53 48 00 85 12 -82 52 00 12 E8 52 06 50 55 53 48 2E 42 00 85 12 -82 52 40 12 42 52 04 43 41 4C 4C 00 85 12 82 52 -80 12 1A 53 0E 4A 0D 12 84 12 24 45 14 40 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 41 DC 52 -03 53 3E 3D 86 12 00 38 30 53 02 53 3C 00 86 12 -00 34 F6 52 03 30 3E 3D 86 12 00 30 44 53 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -58 53 03 55 3E 3D 86 12 00 28 4E 53 03 30 3C 3E -86 12 00 24 6C 53 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D -0E 4A 30 4D 62 53 04 54 48 45 4E 00 1A 42 C6 1D -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D F2 51 04 45 4C 53 45 00 -1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 -8F 4A 00 00 E3 3F 06 53 05 42 45 47 49 4E 30 40 -28 40 96 53 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D 30 4D -76 52 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 84 53 08 44 -AE 44 3A 53 06 52 45 50 45 41 54 00 0D 12 84 12 -18 54 9C 53 AE 44 48 54 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D D8 53 -03 42 57 31 85 12 46 54 00 00 60 54 03 42 57 32 -85 12 46 54 00 00 6C 54 03 42 57 33 85 12 46 54 -00 00 84 54 3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D -88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 82 54 00 00 A4 54 -03 46 57 32 85 12 82 54 00 00 B0 54 03 46 57 33 -85 12 82 54 00 00 00 00 05 3F 47 4F 54 4F 3E 90 -00 30 07 24 3E E0 00 04 3E B0 00 10 02 24 3E E0 -00 08 0D 12 84 12 E0 48 3C 48 AE 44 BC 54 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C F1 3F -62 48 36 4F 06 55 92 53 C4 1D 3E 40 2C 00 84 12 -7A 45 9E 46 34 40 60 48 E2 50 1C 55 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 34 54 04 52 52 43 4D 00 -85 12 00 55 50 00 4A 55 04 52 52 41 4D 00 85 12 -00 55 50 01 58 55 04 52 4C 41 4D 00 85 12 00 55 -50 02 66 55 04 52 52 55 4D 00 85 12 00 55 50 03 -76 53 05 50 55 53 48 4D 85 12 00 55 00 15 82 55 -04 50 4F 50 4D 00 85 12 00 55 00 17 74 55 06 52 -52 43 4D 2E 41 00 85 12 00 55 40 00 9E 55 06 52 -52 41 4D 2E 41 00 85 12 00 55 40 01 AE 55 06 52 -4C 41 4D 2E 41 00 85 12 00 55 40 02 BE 55 06 52 -52 55 4D 2E 41 00 85 12 00 55 40 03 90 55 07 50 -55 53 48 4D 2E 41 85 12 00 55 00 14 DE 55 06 50 -4F 50 4D 2E 41 00 85 12 00 55 00 16 78 54 05 43 -41 4C 4C 41 0D 12 84 12 62 48 36 4F 0E 56 1B 42 -C6 1D A2 53 C6 1D 6E 4E 3C 40 34 01 7E 90 52 00 -0B 20 7E 40 20 00 B0 12 E4 4F 5C 0E 0C DE 8B 4C -00 00 3E 4F 3D 41 30 4D 2C 53 7E 90 40 00 0B 20 -92 53 C4 1D 7E 40 20 00 B0 12 E4 4F EE 23 1C 53 -3E 40 2B 00 E8 3F A2 53 C6 1D 7E 90 23 00 09 20 -3C 40 3B 01 92 53 C4 1D B0 12 5A 4F BB 4F 02 00 -DC 3F 7E 90 26 00 02 20 2C 53 F4 3F 7E 40 28 00 -1C 83 B0 12 5A 4F BB 4F 02 00 3E 40 29 00 CB 3F -0D 12 84 12 62 48 36 4F 9A 56 69 4E 3E 4F 3C 4F -2C 4C 1B 42 C6 1D A2 53 C6 1D 79 90 52 00 0A 20 -B0 12 E4 4F 5E 0E 5E 0E 0E DC 8B 4E 00 00 0E 4B -3D 41 30 4D 79 90 23 00 0D 20 3C C0 40 00 92 53 -C4 1D A2 53 C6 1D B0 12 5A 4F BB 4F 02 00 3E F0 -0F 00 E8 3F 79 90 26 00 03 20 3C E0 E0 00 EF 3F -3C C0 F0 00 79 90 40 00 12 20 92 53 C4 1D B0 12 -E4 4F D8 23 3C D0 10 00 3E 40 2B 00 B0 12 E4 4F -92 92 C0 1D C4 1D CE 27 92 53 C4 1D CB 3F 3C D0 -30 00 A2 53 C6 1D 3E 40 28 00 B0 12 5A 4F BB 4F -02 00 3E 40 29 00 EA 3F 0D 12 84 12 62 48 36 4F -42 57 3B 4F 2C 4B 69 4E 7E 40 20 00 79 90 52 00 -03 20 B0 12 E4 4F B0 3F 3C C0 F0 00 A2 53 C6 1D -79 90 26 00 09 20 3C D0 60 00 92 53 C4 1D B0 12 -5A 4F BB 4F 02 00 A0 3F 3C D0 70 00 3E 40 28 00 -B0 12 5A 4F BB 4F 02 00 3E 40 29 00 E2 3F 0A 40 -2C 00 90 56 38 57 D2 43 AE 44 4C 51 04 4D 4F 56 -41 00 85 12 8E 57 C0 00 FE 55 04 43 4D 50 41 00 -85 12 8E 57 D0 00 12 54 04 41 44 44 41 00 85 12 -8E 57 E0 00 CE 55 04 53 55 42 41 00 85 12 8E 57 -F0 00 0D 12 84 12 62 48 36 4F DC 57 69 4E 3E 4F -3C 40 00 18 79 90 52 00 05 20 B0 12 E4 4F 0E 4C -3D 41 30 4D 82 43 66 5C 79 90 23 00 0B 20 92 53 -C4 1D B0 12 5A 4F 2F 53 3E F0 0F 00 5E 0A 5E 0E -0C DE ED 3F 79 90 26 00 F2 27 79 90 40 00 12 20 -92 53 C4 1D B0 12 E4 4F E2 23 3E 40 2B 00 92 53 -C4 1D B0 12 E4 4F 92 92 C0 1D C4 1D D8 27 92 53 -C4 1D D5 3F 3E 40 28 00 B0 12 5A 4F 8F 4E 00 00 -3E 40 29 00 B0 12 E4 4F 3E 4F 3E F0 0F 00 0C DE -EA 3F 0D 12 84 12 62 48 36 4F 6C 58 3C 4F 69 4E -3E 40 20 00 79 90 52 00 BA 27 82 43 66 5C 79 90 -26 00 08 20 92 53 C4 1D B0 12 5A 4F 2F 53 3E F0 -0F 00 BE 3F 3E 40 28 00 B0 12 5A 4F F7 3F B2 4F -C4 1D 1B 42 C6 1D A2 53 C6 1D 0C 4E 3E 4F 1C D2 -66 5C 82 43 66 5C 3C DE 8B 4C 00 00 30 4D 0A 40 -C4 1D 2E 44 0A 40 2C 00 D2 57 62 58 9E 58 3A 40 -2C 51 9C 57 04 4D 4F 56 58 00 85 12 BE 58 40 00 -00 40 D4 58 06 4D 4F 56 58 2E 41 00 85 12 BE 58 -00 00 40 40 E4 58 06 4D 4F 56 58 2E 42 00 85 12 -BE 58 40 00 40 40 B8 57 04 41 44 44 58 00 85 12 -BE 58 40 00 00 50 08 59 06 41 44 44 58 2E 41 00 -85 12 BE 58 00 00 40 50 18 59 06 41 44 44 58 2E -42 00 85 12 BE 58 40 00 40 50 2A 59 05 41 44 44 -43 58 85 12 BE 58 40 00 00 60 3C 59 07 41 44 44 -43 58 2E 41 85 12 BE 58 00 00 40 60 4C 59 07 41 -44 44 43 58 2E 42 85 12 BE 58 40 00 40 60 C6 57 -05 53 55 42 43 58 85 12 BE 58 40 00 00 70 70 59 -07 53 55 42 43 58 2E 41 85 12 BE 58 00 00 40 70 -80 59 07 53 55 42 43 58 2E 42 85 12 BE 58 40 00 -40 70 92 59 04 53 55 42 58 00 85 12 BE 58 40 00 -00 80 A4 59 06 53 55 42 58 2E 41 00 85 12 BE 58 -00 00 40 80 B4 59 06 53 55 42 58 2E 42 00 85 12 -BE 58 40 00 40 80 AA 57 04 43 4D 50 58 00 85 12 -BE 58 40 00 00 90 D8 59 06 43 4D 50 58 2E 41 00 -85 12 BE 58 00 00 40 90 E8 59 06 43 4D 50 58 2E -42 00 85 12 BE 58 40 00 40 90 BA 53 05 44 41 44 -44 58 85 12 BE 58 40 00 00 A0 0C 5A 07 44 41 44 -44 58 2E 41 85 12 BE 58 00 00 40 A0 1C 5A 07 44 -41 44 44 58 2E 42 85 12 BE 58 40 00 40 A0 FA 59 -04 42 49 54 58 00 85 12 BE 58 40 00 00 B0 40 5A -06 42 49 54 58 2E 41 00 85 12 BE 58 00 00 40 B0 -50 5A 06 42 49 54 58 2E 42 00 85 12 BE 58 40 00 -40 B0 62 5A 04 42 49 43 58 00 85 12 BE 58 40 00 -00 C0 74 5A 06 42 49 43 58 2E 41 00 85 12 BE 58 -00 00 40 C0 84 5A 06 42 49 43 58 2E 42 00 85 12 -BE 58 40 00 40 C0 96 5A 04 42 49 53 58 00 85 12 -BE 58 40 00 00 D0 A8 5A 06 42 49 53 58 2E 41 00 -85 12 BE 58 00 00 40 D0 B8 5A 06 42 49 53 58 2E -42 00 85 12 BE 58 40 00 40 D0 5C 52 04 58 4F 52 -58 00 85 12 BE 58 40 00 00 E0 DC 5A 06 58 4F 52 -58 2E 41 00 85 12 BE 58 00 00 40 E0 EC 5A 06 58 -4F 52 58 2E 42 00 85 12 BE 58 40 00 40 E0 5E 59 -04 41 4E 44 58 00 85 12 BE 58 40 00 00 F0 10 5B -06 41 4E 44 58 2E 41 00 85 12 BE 58 00 00 40 F0 -20 5B 06 41 4E 44 58 2E 42 00 85 12 BE 58 40 00 -40 F0 0A 40 C4 1D 2E 44 62 48 D2 57 9E 58 3A 40 -82 52 C6 59 04 52 52 43 58 00 85 12 42 5B 40 00 -00 10 54 5B 06 52 52 43 58 2E 41 00 85 12 42 5B -00 00 40 10 64 5B 06 52 52 43 58 2E 42 00 85 12 -42 5B 40 00 40 10 76 5B 04 52 52 55 58 00 85 12 -42 5B 40 01 00 10 88 5B 06 52 52 55 58 2E 41 00 -85 12 42 5B 00 01 40 10 98 5B 06 52 52 55 58 2E -42 00 85 12 42 5B 40 01 40 10 AA 5B 05 53 57 50 -42 58 85 12 42 5B 40 00 80 10 BC 5B 07 53 57 50 -42 58 2E 41 85 12 42 5B 00 00 80 10 CC 5B 04 52 -52 41 58 00 85 12 42 5B 40 00 00 11 DE 5B 06 52 -52 41 58 2E 41 00 85 12 42 5B 00 00 40 11 EE 5B -06 52 52 41 58 2E 42 00 85 12 42 5B 40 00 40 11 -00 5C 04 53 58 54 58 00 85 12 42 5B 40 00 80 11 -12 5C 06 53 58 54 58 2E 41 00 85 12 42 5B 00 00 -80 11 EE 55 05 50 55 53 48 58 85 12 42 5B 40 00 -00 12 34 5C 07 50 55 53 48 58 2E 41 85 12 42 5B -00 00 40 12 44 5C 07 50 55 53 48 58 2E 42 85 12 -42 5B 40 00 40 12 00 00 22 5C 03 52 50 54 0D 12 -84 12 62 48 36 4F 78 5C 29 4E 7E 40 20 00 79 90 -52 00 06 20 B0 12 E4 4F 03 24 3E D0 80 00 05 3C -B0 12 5A 4F 1E 83 3E F0 0F 00 82 4E 66 5C 3E 4F -3D 41 30 4D D2 C3 23 02 E2 B2 60 02 02 24 30 40 -E2 41 1A 52 04 20 19 62 06 20 92 43 14 20 A2 93 -02 20 07 24 0A 5A 49 69 82 4A 16 20 C2 49 18 20 -0A 3C C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 17 20 -89 10 C2 49 18 20 B0 12 2C 5D 5A 53 FC 23 39 40 -05 00 D2 49 14 20 4E 06 82 93 46 06 05 24 92 B3 -6C 06 FD 27 C2 93 4C 06 59 83 F3 2F 19 83 0B 30 -F2 43 4E 06 82 93 46 06 03 24 92 B3 6C 06 FD 27 -5A 92 4C 06 F3 23 30 41 1A 43 E1 3F 19 43 3A 43 -8A 10 C2 4A 4E 06 82 93 46 06 05 24 92 B3 6C 06 -FD 27 C2 93 4C 06 19 83 F3 23 5A 42 4C 06 30 41 -6A 5C 08 52 45 41 44 5F 53 57 58 00 1C D3 F2 40 -51 00 19 20 B0 12 A4 5C 38 20 B0 12 2C 5D 6A 53 -04 24 FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 03 43 -19 53 39 90 01 02 F6 23 F2 43 4E 06 3C C0 03 00 -D2 D3 23 02 30 41 22 54 09 57 52 49 54 45 5F 53 -57 58 2C D3 F0 40 58 00 71 C2 B0 12 A4 5C 15 20 -3A 40 FE FF 29 43 B0 12 30 5D D2 49 00 1E 4E 06 -03 43 19 53 39 90 00 02 F8 23 39 40 03 00 B0 12 -2E 5D 7A C0 E1 00 6A 92 D9 27 8C 10 1C 52 4C 06 -D2 D3 23 02 0D 12 84 12 18 43 14 40 0B 3C 20 53 -44 20 45 72 72 6F 72 21 FA 5D 2F 83 8F 4E 00 00 -B2 40 10 00 DC 1D 0E 4C 84 12 EE 44 36 41 B0 12 -8C 41 0E 93 9C 24 E2 B2 60 02 99 20 B2 40 81 A9 -40 06 B2 40 03 00 46 06 D2 D3 25 02 B2 D0 C0 04 -0C 02 92 C3 40 06 39 42 B0 12 2E 5D D2 C3 23 02 +08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 8E 4D F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 DA 4D 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +DE 4D 92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 C6 4D F2 3F 03 20 +B0 12 DE 4D F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 C6 4D EA 3F 0C 43 1B 42 +C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 +C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 +C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A 40 00 13 C6 48 D8 45 0A 40 2C 00 +BC 4E 00 4E 0A 44 C6 4E 9E 4E 0C 4F 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 FC 4E +00 40 18 4F 0A 4D 4F 56 2E 42 85 12 FC 4E 40 40 +00 00 06 41 44 44 85 12 FC 4E 00 50 32 4F 0A 41 +44 44 2E 42 85 12 FC 4E 40 50 3E 4F 08 41 44 44 +43 00 85 12 FC 4E 00 60 4C 4F 0C 41 44 44 43 2E +42 00 85 12 FC 4E 40 60 84 4B 08 53 55 42 43 00 +85 12 FC 4E 00 70 6A 4F 0C 53 55 42 43 2E 42 00 +85 12 FC 4E 40 70 78 4F 06 53 55 42 85 12 FC 4E +00 80 88 4F 0A 53 55 42 2E 42 85 12 FC 4E 40 80 +94 4F 06 43 4D 50 85 12 FC 4E 00 90 A2 4F 0A 43 +4D 50 2E 42 85 12 FC 4E 40 90 00 00 08 44 41 44 +44 00 85 12 FC 4E 00 A0 BC 4F 0C 44 41 44 44 2E +42 00 85 12 FC 4E 40 A0 EA 4E 06 42 49 54 85 12 +FC 4E 00 B0 DA 4F 0A 42 49 54 2E 42 85 12 FC 4E +40 B0 E6 4F 06 42 49 43 85 12 FC 4E 00 C0 F4 4F +0A 42 49 43 2E 42 85 12 FC 4E 40 C0 00 50 06 42 +49 53 85 12 FC 4E 00 D0 0E 50 0A 42 49 53 2E 42 +85 12 FC 4E 40 D0 00 00 06 58 4F 52 85 12 FC 4E +00 E0 28 50 0A 58 4F 52 2E 42 85 12 FC 4E 40 E0 +5A 4F 06 41 4E 44 85 12 FC 4E 00 F0 42 50 0A 41 +4E 44 2E 42 85 12 FC 4E 40 F0 0A 44 BC 4E 00 4E +62 50 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F 1A 50 06 52 52 43 85 12 5A 50 00 10 74 50 +0A 52 52 43 2E 42 85 12 5A 50 40 10 AE 4F 08 53 +57 50 42 00 85 12 5A 50 80 10 80 50 06 52 52 41 +85 12 5A 50 00 11 9C 50 0A 52 52 41 2E 42 85 12 +5A 50 40 11 8E 50 06 53 58 54 85 12 5A 50 80 11 +00 00 08 50 55 53 48 00 85 12 5A 50 00 12 C2 50 +0C 50 55 53 48 2E 42 00 85 12 5A 50 40 12 B6 50 +08 43 41 4C 4C 00 85 12 5A 50 80 12 1A 53 0E 4A +84 12 4C 46 1E 40 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 41 E0 50 06 53 3E 3D 86 12 00 38 +08 51 04 53 3C 00 86 12 00 34 D0 50 06 30 3E 3D +86 12 00 30 1C 51 04 30 3C 00 86 12 00 30 58 4B +04 55 3C 00 86 12 00 2C 30 51 06 55 3E 3D 86 12 +00 28 26 51 06 30 3C 3E 86 12 00 24 44 51 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D +8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D CA 4F 08 54 +48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +3A 51 08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C +00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F A8 50 +0A 42 45 47 49 4E 30 40 32 40 92 51 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 1D 30 4D 4E 50 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 5C 51 F2 44 D8 45 B0 51 0C 52 45 50 +45 41 54 00 0D 12 84 12 F0 51 74 51 D8 45 20 52 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 +C8 1D 00 00 30 4D 0C 52 06 42 57 31 85 12 1E 52 +00 00 38 52 06 42 57 32 85 12 1E 52 00 00 44 52 +06 42 57 33 85 12 1E 52 00 00 5C 52 3D 41 1A 42 +C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F +00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 5A 52 00 00 80 52 06 46 57 32 +85 12 5A 52 00 00 8C 52 06 46 57 33 85 12 5A 52 +00 00 FA 51 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 92 49 9E 48 D8 45 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F C6 4E 0A 40 +2C 00 5C 46 6E 47 AC 40 A2 49 0A 44 BC 4E 9E 4E +F2 52 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E 50 52 +08 52 52 43 4D 00 85 12 DC 52 50 00 20 53 08 52 +52 41 4D 00 85 12 DC 52 50 01 2E 53 08 52 4C 41 +4D 00 85 12 DC 52 50 02 3C 53 08 52 52 55 4D 00 +85 12 DC 52 50 03 4E 51 0A 50 55 53 48 4D 85 12 +DC 52 00 15 58 53 08 50 4F 50 4D 00 85 12 DC 52 +00 17 D2 C3 23 02 E2 B2 60 02 02 24 30 40 FA 41 +1A 52 04 20 19 62 06 20 92 43 14 20 C2 4A 15 20 +8A 10 C2 4A 16 20 C2 49 17 20 89 10 C2 49 18 20 +B0 12 E6 53 5A 53 FC 23 39 40 05 00 D2 49 14 20 +4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 +4C 06 59 83 F3 2F 19 83 0B 30 F2 43 4E 06 82 93 +46 06 03 24 92 B3 6C 06 FD 27 5A 92 4C 06 F3 23 +30 41 1A 43 E1 3F 19 43 3A 43 8A 10 C2 4A 4E 06 +82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 +19 83 F3 23 5A 42 4C 06 30 41 4A 53 12 52 5F 53 +45 43 54 5F 57 58 1C D3 F2 40 51 00 19 20 B0 12 +72 53 38 20 B0 12 E6 53 6A 53 04 24 FB 23 D9 42 +4C 06 FF 1D F2 43 4E 06 03 43 19 53 39 90 01 02 +F6 23 F2 43 4E 06 3C C0 03 00 D2 D3 23 02 30 41 +A4 52 12 57 5F 53 45 43 54 5F 57 58 2C D3 F0 40 +58 00 B7 CB B0 12 72 53 15 20 3A 40 FE FF 29 43 +B0 12 EA 53 D2 49 00 1E 4E 06 03 43 19 53 39 90 +00 02 F8 23 39 40 03 00 B0 12 E8 53 7A C0 E1 00 +6A 82 D9 27 8C 10 1C 52 4C 06 D2 D3 23 02 84 12 +5E 43 1E 40 0B 3C 20 53 44 20 45 72 72 6F 72 21 +B2 54 2F 83 8F 4E 00 00 B2 40 10 00 BE 1D 0E 4C +84 12 18 46 12 41 B0 12 58 41 E2 B2 60 02 8A 20 +B2 40 81 A9 40 06 B2 40 03 00 46 06 D2 D3 25 02 +B2 D0 C0 04 0C 02 92 C3 40 06 39 40 6E 01 29 83 +89 43 02 20 FC 23 39 42 B0 12 E8 53 D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 00 40 18 20 B0 12 -28 5D 02 24 30 40 DA 5D B0 12 2C 5D 7A 93 FC 23 +E2 53 02 24 30 40 94 54 B0 12 E6 53 7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 B2 40 00 48 18 20 -B0 12 28 5D 29 42 B0 12 2E 5D 92 43 14 20 82 43 -16 20 78 43 3C 42 B2 40 00 77 18 20 B0 12 28 5D -B2 40 40 69 18 20 B0 12 E6 5C 03 24 58 83 F3 23 +B0 12 E2 53 29 42 B0 12 E8 53 92 43 14 20 82 43 +16 20 78 43 3C 42 B2 40 00 77 18 20 B0 12 E2 53 +B2 40 40 69 18 20 B0 12 A0 53 03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 00 50 18 20 B0 12 -E6 5C D0 23 92 D3 40 06 82 43 46 06 92 C3 40 06 -09 43 B0 12 5C 5D 38 40 00 1E 92 48 C6 01 04 20 -92 48 C8 01 06 20 5A 48 C2 01 92 43 02 20 7A 80 -06 00 0F 24 7A 82 0D 24 A2 43 02 20 6A 53 09 24 -5A 53 07 24 6A 52 05 24 3A 50 0B 20 0C 4A 30 40 -E0 5D 09 43 B0 12 5C 5D D2 48 0D 00 12 20 19 48 -0E 00 82 49 08 20 1A 48 16 00 0A 93 02 20 1A 48 -24 00 82 4A 0A 20 09 5A 82 49 0C 20 09 5A A2 93 -02 20 04 24 82 49 0E 20 39 50 20 00 19 82 12 20 -19 82 12 20 82 49 10 20 92 42 02 20 2C 20 30 41 -B0 12 AA 40 39 40 E0 00 29 83 89 43 38 20 FC 23 -82 43 32 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 -24 20 5A 42 23 20 58 42 22 20 92 93 02 20 08 24 -59 42 24 20 89 10 0A 59 88 10 08 58 0A 6A 88 10 -08 58 30 41 82 43 1C 20 92 42 0E 20 1A 20 C2 93 -24 20 03 20 92 93 22 20 14 24 92 42 22 20 D0 04 -92 42 24 20 D2 04 92 42 12 20 C8 04 92 42 E4 04 -1A 20 92 42 E6 04 1C 20 92 52 10 20 1A 20 82 63 -1C 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 -B0 12 94 5F 5A 4B 03 00 82 5A 1A 20 82 63 1C 20 -30 41 09 93 07 24 F8 90 20 00 00 1E 03 20 18 53 -19 83 F9 23 30 41 1B 42 32 20 82 43 1E 20 B2 90 -00 02 20 20 AB 20 BB 80 00 02 12 00 8B 73 14 00 -DB 53 03 00 DB 92 12 20 03 00 14 28 CB 43 03 00 -B0 12 66 5F 1A 52 08 20 09 43 B0 12 5C 5D 8B 43 -10 00 9B 48 00 1E 0E 00 92 93 02 20 03 24 9B 48 -02 1E 10 00 B2 40 00 02 20 20 8B 93 14 00 0B 20 -92 9B 12 00 1E 20 82 2C BB 90 00 02 12 00 03 2C -92 4B 12 00 20 20 B0 12 D4 5F 1A 42 1A 20 19 42 -1C 20 6C 3E 3C 42 3B 40 38 20 09 43 CB 93 02 00 -10 24 9B 92 24 20 0C 00 04 20 9B 92 22 20 0A 00 -07 24 09 4B 3B 50 1C 00 3B 90 18 21 EF 23 0C 5C -30 41 0C 43 82 4B 32 20 8B 49 00 00 09 93 0A 24 -99 52 C4 1D 16 00 4A 93 05 34 C9 93 02 00 02 34 -5A 59 02 00 CB 4A 02 00 CB 43 03 00 9B 42 1A 20 -04 00 9B 42 1C 20 06 00 18 42 30 20 8B 48 08 00 -9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 1A 1E -0E 00 9B 48 14 1E 10 00 9B 48 1C 1E 12 00 9B 48 -1E 1E 14 00 82 43 1E 20 6A 93 5C 27 C9 37 8B 43 -16 00 7A 93 02 24 07 38 95 3F B2 40 1C 21 CA 40 -B2 40 44 43 70 42 9B 42 C0 1D 18 00 9B 82 C4 1D -18 00 9B 42 C2 1D 1A 00 9B 52 C4 1D 1A 00 82 3F -CB 43 02 00 2B 4B 82 4B 32 20 0B 93 06 24 92 4B -16 00 1E 20 B0 12 54 60 22 C3 30 41 1B 42 32 20 -0B 93 FB 27 EB 93 02 00 04 20 B0 12 30 66 B0 12 -F8 65 CB 93 02 00 E4 37 1E 4B 18 00 9F 4B 1A 00 -00 00 31 50 06 00 3D 41 B0 12 50 61 02 24 30 40 -36 43 B2 40 3C 1D CA 40 B2 40 72 42 70 42 30 40 -18 43 2E 4E 85 52 45 41 44 22 5A 43 19 3C A2 4C -86 57 52 49 54 45 22 00 6A 43 12 3C 96 4D 84 44 -45 4C 22 00 6A 42 0C 3C E6 4A 05 43 4C 4F 53 45 -B0 12 6C 61 30 4D 50 4C 85 4C 4F 41 44 22 7A 43 -2F 83 8F 4E 00 00 0E 4A 82 93 BE 1D 0B 24 0D 12 -84 12 0A 40 0A 40 A8 47 A8 47 32 45 0A 40 24 62 -A8 47 AE 44 0D 12 84 12 0A 40 22 00 7A 45 F8 47 -22 62 3D 41 36 4F 0E 56 82 4E 36 20 1C 43 92 42 -2C 20 22 20 92 42 2E 20 24 20 0E 96 8D 24 F6 90 -3A 00 01 00 01 20 26 53 F6 90 5C 00 00 00 08 20 -16 53 92 42 02 20 22 20 82 43 24 20 0E 96 70 24 -82 46 34 20 B0 12 94 5F 35 40 20 00 A2 93 02 20 -04 24 92 92 22 20 02 20 02 24 15 42 12 20 B0 12 -7A 60 2C 43 0A 43 08 4A 58 0E 08 58 82 48 30 20 -C8 93 00 1E 61 24 39 42 F8 96 00 1E 04 20 18 53 -19 83 FA 23 16 53 F6 90 2E 00 FF FF 19 24 39 50 -03 00 B0 12 F2 5F 06 20 F6 90 5C 00 FF FF 29 24 -0E 96 27 28 16 42 34 20 1A 53 3A 90 10 00 DB 23 -92 53 1A 20 82 63 1C 20 15 83 D1 23 2C 42 3C 3C -F6 90 2E 00 FE FF EE 27 B0 12 F2 5F EB 23 39 40 -03 00 F8 96 00 1E 04 20 18 53 19 83 FA 23 09 3C -0E 96 E0 2F F6 90 5C 00 FF FF DC 23 B0 12 F2 5F -D9 23 18 42 30 20 92 48 1A 1E 22 20 92 48 14 1E -24 20 F8 B0 10 00 0B 1E 14 24 82 93 24 20 06 20 -82 93 22 20 03 20 92 42 02 20 22 20 0E 96 8E 2F -92 42 22 20 2C 20 92 42 24 20 2E 20 8F 43 00 00 -03 3C 2A 4F B0 12 84 60 35 40 D4 40 36 40 E2 40 -3A 4F 3E 4F 0A 93 04 24 7A 93 3C 20 0C 93 01 20 -30 4D 0D 12 84 12 18 43 14 40 0B 3C 20 4F 70 65 -6E 45 72 72 6F 72 3A 40 F8 5D 26 4C 05 5B 50 46 -41 5D 2E 53 2E 4E 30 4D DA 61 04 42 4F 4F 54 00 -39 40 0E 5E 2E 93 01 2C 30 41 E2 B2 60 02 02 24 -10 49 02 00 89 12 3F 40 7E 1C 8F 43 00 00 82 43 -BE 1D B2 40 00 1C 00 1C 31 40 E0 1C 84 12 14 40 -0F 4C 4F 41 44 22 20 42 4F 4F 54 2E 34 54 48 22 -3A 40 90 48 1A 93 BB 20 0C 93 C3 23 30 4D B4 61 -04 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 32 20 -B0 12 06 60 1E 82 32 20 30 4D 2C 43 12 12 2A 20 -18 42 02 20 08 58 2A 41 82 9A 0A 20 A6 24 1A 52 -08 20 09 43 B0 12 5C 5D 09 43 28 93 03 24 89 93 -02 1E 03 20 89 93 00 1E 07 24 09 58 39 90 00 02 -F4 23 91 53 00 00 E7 3F 0C 43 6A 41 B9 43 00 1E -28 93 0F 24 B9 40 FF 0F 02 1E 09 11 8A 10 09 5A -5A 41 01 00 0A 11 09 10 82 4A 28 20 82 49 26 20 -07 3C 09 11 C2 49 26 20 C2 4A 27 20 82 43 28 20 -3A 41 82 4A 2A 20 30 41 0A 12 1A 52 08 20 09 43 -B0 12 A2 5D 3A 41 1A 52 0C 20 09 43 B0 12 A2 5D -F2 B0 40 00 A2 04 29 20 F2 B0 10 00 A2 04 FC 27 -5A 42 B0 04 4A 11 59 42 B4 04 F2 40 20 00 C0 04 -D2 42 B1 04 C8 04 1A 52 E4 04 D2 42 B5 04 C8 04 -19 52 E4 04 D2 42 B2 04 C0 04 B2 40 00 08 C8 04 -1A 52 E4 04 92 42 B6 04 C0 04 B2 80 BC 07 C0 04 -B2 40 00 02 C8 04 19 52 E4 04 30 41 22 2A 2B 2C -2F 3A 3B 3C 3D 3E 3F 5B 5C 5D 7C 2E 29 92 06 38 -39 80 03 00 B0 12 4C 65 39 40 03 00 7A 4B C8 4A -00 1E 82 9B 36 20 12 28 0D 12 3D 40 0F 00 3C 40 -FC 64 7A 9C F3 27 1D 83 FC 23 3D 41 6A 9C E6 27 -3A 80 21 00 EB 3B 18 53 19 83 E8 23 09 93 06 24 -F8 40 20 00 00 1E 18 53 19 83 FA 23 30 41 2A 93 -DC 20 2C 93 0E 24 0C 93 AB 24 0D 12 84 12 14 40 -0C 3C 20 57 72 69 74 65 45 72 72 6F 72 00 3A 40 -F8 5D B0 12 0A 64 92 42 26 20 22 20 92 42 28 20 -24 20 B0 12 88 64 B0 12 7A 60 18 42 30 20 F8 40 -20 00 0B 1E B0 12 A0 64 88 43 0C 1E 88 4A 0E 1E -88 49 10 1E 88 49 12 1E 98 42 24 20 14 1E 98 42 -22 20 1A 1E 88 43 1C 1E 88 43 1E 1E 1C 43 1B 42 -34 20 82 9B 36 20 C9 27 FB 90 2E 00 00 00 C5 27 -39 40 0B 00 B0 12 1C 65 B0 12 3A 66 2A 43 B0 12 -84 60 0C 93 BA 23 30 4D 1A 4B 04 00 19 4B 06 00 -B0 12 5C 5D B0 12 A0 64 18 4B 08 00 88 49 12 1E -88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E 98 4B -14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 A2 5D -9B 52 1E 20 12 00 8B 63 14 00 1A 42 1A 20 19 42 -1C 20 30 40 A2 5D B2 40 00 02 1E 20 1B 42 32 20 -B0 12 30 66 82 43 1E 20 DB 53 03 00 DB 92 12 20 -03 00 25 20 CB 43 03 00 B0 12 66 5F 08 12 0A 12 -B0 12 0A 64 2A 91 08 24 B0 12 88 64 2A 41 1A 52 -08 20 09 43 B0 12 5C 5D 3A 41 38 41 98 42 26 20 -00 1E 92 93 02 20 03 24 98 42 28 20 02 1E B0 12 -88 64 9B 42 26 20 0E 00 9B 42 28 20 10 00 30 40 -D4 5F C0 61 05 57 52 49 54 45 B0 12 46 66 30 4D -58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B 15 00 -5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 1C 83 -0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 19 5B -0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 CB 4A -03 00 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 FF 01 -82 4A 1E 20 B0 12 76 60 30 4D 0C 93 3B 20 38 90 -E0 01 03 2C C8 93 20 1E 02 24 7C 40 E5 00 C8 4C -00 1E B0 12 3A 66 B0 12 72 5F 82 4A 2A 20 0B 4A -1A 52 08 20 09 43 B0 12 5C 5D 1A 48 00 1E 88 43 -00 1E 92 93 02 20 09 24 19 48 02 1E 88 43 02 1E -39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 0E 24 82 4A -22 20 82 49 24 20 B0 12 72 5F 0B 9A E6 27 0A 12 -0A 4B B0 12 88 64 3A 41 DA 3F 0A 4B B0 12 88 64 -B0 12 6C 61 30 4D EA 44 08 54 45 52 4D 32 53 44 -22 00 0D 12 84 12 D4 61 0A 40 02 00 28 40 F8 47 -24 62 B4 67 B0 12 B8 41 0A 43 92 B3 EC 06 FD 27 -59 42 CC 06 69 92 11 24 CA 49 00 1E 1A 53 79 90 -0A 00 05 20 84 12 DC 43 DA 67 B0 12 B8 41 3A 90 -00 02 EB 2B B0 12 46 66 E7 3F 92 B3 EC 06 FD 27 -F2 90 0A 00 CC 06 F9 23 82 4A 1E 20 B0 12 6C 61 +A0 53 D0 23 92 D3 40 06 82 43 46 06 92 C3 40 06 +0A 43 09 43 B0 12 16 54 38 40 00 1E 92 48 C6 01 +04 20 92 48 C8 01 06 20 5C 48 C2 01 7C 80 0C 00 +08 24 5C 53 06 24 6C 52 04 24 3C 50 07 20 30 40 +9A 54 09 43 B0 12 16 54 A2 43 2C 20 19 48 0E 00 +82 49 08 20 1A 48 24 00 82 4A 0A 20 09 5A 82 49 +0C 20 09 5A 58 48 0D 00 82 48 12 20 09 88 09 88 +82 49 10 20 30 41 82 43 32 20 30 40 56 41 92 4B +0E 00 22 20 92 4B 10 00 24 20 5A 42 23 20 58 42 +22 20 59 42 24 20 89 10 0A D9 88 10 08 58 0A 6A +88 10 08 58 30 41 1A 52 08 20 09 43 FC 3E 92 42 +22 20 D0 04 92 42 24 20 D2 04 92 42 12 20 C8 04 +92 42 E4 04 1A 20 92 42 E6 04 1C 20 92 52 10 20 +1A 20 82 63 1C 20 30 41 92 4B 0E 00 22 20 92 4B +10 00 24 20 B0 12 1E 56 5A 4B 03 00 82 5A 1A 20 +82 63 1C 20 30 41 3C 42 3B 40 38 20 09 43 CB 93 +02 00 10 24 9B 92 24 20 0C 00 04 20 9B 92 22 20 +0A 00 A3 25 09 4B 3B 50 1C 00 3B 90 18 21 EF 23 +0C 5C 9B 3D 0C 43 82 4B 32 20 8B 49 00 00 09 93 +0A 24 99 52 C6 1D 16 00 4A 93 05 34 C9 93 02 00 +02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00 9B 42 +1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20 8B 48 +08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 +1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E 12 00 +9B 48 1E 1E 14 00 82 43 1E 20 6A 93 1A 24 A4 37 +8B 43 16 00 7A 93 02 24 07 38 35 3C B2 40 1C 21 +A0 40 B2 40 82 43 C0 42 9B 42 C2 1D 18 00 9B 82 +C6 1D 18 00 9B 42 C4 1D 1A 00 9B 52 C6 1D 1A 00 +22 3C 30 41 1B 42 32 20 82 43 1E 20 B2 90 00 02 +20 20 3F 20 BB 80 00 02 12 00 8B 73 14 00 DB 53 +03 00 DB 92 12 20 03 00 0E 28 CB 43 03 00 B0 12 +EE 55 B0 12 16 56 8B 43 10 00 9B 48 00 1E 0E 00 +9B 48 02 1E 10 00 B2 40 00 02 20 20 8B 93 14 00 +0B 20 92 9B 12 00 1E 20 1C 2C BB 90 00 02 12 00 +03 2C 92 4B 12 00 20 20 B0 12 48 56 1A 42 1A 20 +19 42 1C 20 38 3E CB 43 02 00 2B 4B 82 4B 32 20 +0B 93 06 24 92 4B 16 00 1E 20 B0 12 76 57 22 C3 +30 41 1B 42 32 20 0B 93 FB 27 EB 92 02 00 04 20 +B0 12 34 5B B0 12 24 5C CB 93 02 00 E4 37 1E 4B +18 00 9F 4B 1A 00 00 00 31 50 06 00 3D 41 B0 12 +A6 57 02 24 30 40 78 43 B2 40 3C 1D A0 40 B2 40 +C2 42 C0 42 30 40 5E 43 09 93 07 24 F8 90 20 00 +00 1E 03 20 18 53 19 83 F9 23 30 41 62 4C 0B 52 +45 41 44 22 5A 43 20 3C CA 4A 09 44 45 4C 22 00 +6A 43 1A 3C 90 49 0D 57 52 49 54 45 22 00 6A 42 +13 3C 78 49 0F 41 50 50 45 4E 44 22 7A 42 0C 3C +74 4B 0A 43 4C 4F 53 45 B0 12 C2 57 30 4D D8 48 +0B 4C 4F 41 44 22 7A 43 2F 83 8F 4E 00 00 0E 4A +82 93 BC 1D 0B 24 0D 12 84 12 0A 40 0A 40 C6 48 +C6 48 46 45 0A 40 9C 58 C6 48 D8 45 0D 12 84 12 +0A 40 22 00 5C 46 16 49 9A 58 3D 41 36 4F 0E 56 +82 4E 36 20 A2 43 22 20 82 43 24 20 1C 43 0E 96 +8C 24 F6 90 3A 00 01 00 01 20 26 53 F6 90 5C 00 +00 00 03 20 16 53 0E 96 66 24 82 46 34 20 B0 12 +1E 56 15 42 12 20 B0 12 9C 57 2C 43 0A 43 08 4A +58 0E 08 58 82 48 30 20 C8 93 00 1E 60 24 39 42 +F8 96 00 1E 04 20 18 53 19 83 FA 23 16 53 F6 90 +2E 00 FF FF 19 24 39 50 03 00 B0 12 08 58 06 20 +F6 90 5C 00 FF FF 29 24 0E 96 27 28 16 42 34 20 +1A 53 3A 90 10 00 DB 23 92 53 1A 20 82 63 1C 20 +15 83 D1 23 2C 42 49 3C F6 90 2E 00 FE FF EE 27 +B0 12 08 58 EB 23 39 40 03 00 F8 96 00 1E 04 20 +18 53 19 83 FA 23 09 3C 0E 96 E0 2F F6 90 5C 00 +FF FF DC 23 B0 12 08 58 D9 23 18 42 30 20 92 48 +1A 1E 22 20 92 48 14 1E 24 20 F8 B0 10 00 0B 1E +13 24 82 93 24 20 05 20 82 93 22 20 02 20 A2 43 +22 20 0E 96 9A 23 92 42 22 20 2C 20 92 42 24 20 +2E 20 8F 43 00 00 03 3C 2A 4F B0 12 66 56 35 40 +B6 40 36 40 C4 40 3A 4F 3E 4F 0A 93 04 24 7A 93 +39 20 0C 93 02 20 30 40 78 43 0D 12 84 12 5E 43 +1E 40 0B 3C 20 4F 70 65 6E 45 72 72 6F 72 B2 40 +B0 54 E2 B2 60 02 02 24 30 40 80 41 92 12 3E 18 +3F 40 7E 1C 8F 43 00 00 0D 12 84 12 1E 40 0F 4C +4F 41 44 22 20 42 4F 4F 54 2E 34 54 48 22 B2 40 +46 49 1E 58 08 42 4F 4F 54 00 B2 40 E2 59 B2 42 +30 4D 16 47 0C 4E 4F 42 4F 4F 54 00 B2 40 80 41 +B2 42 30 4D 1A 93 89 20 0C 93 C7 23 30 4D 14 5A +08 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 32 20 +B0 12 34 57 1E 82 32 20 30 4D 08 4A 1A 52 08 20 +B0 12 6A 5A 0A 48 1A 52 0C 20 09 43 30 40 5C 54 +3C 42 0A 12 2A 41 82 9A 0A 20 2B 25 B0 12 16 56 +88 93 02 1E 03 20 88 93 00 1E 08 24 28 52 38 90 +00 02 F6 2B 91 53 00 00 08 43 EC 3F A2 41 26 20 +82 48 28 20 0C 43 B8 43 00 1E 6A 41 B8 40 FF 0F +02 1E 08 11 8A 10 08 5A 5A 41 01 00 0A 11 08 10 +82 4A 24 20 82 48 22 20 2A 41 B0 12 5A 5A 3A 41 +30 41 90 4B 0A 00 4C C5 90 4B 0C 00 48 C5 B0 12 +FA 55 82 4A 26 20 82 48 28 20 0A 12 B0 12 16 56 +1A 48 00 1E 88 43 00 1E 19 48 02 1E 88 43 02 1E +39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 10 24 82 4A +22 20 82 49 24 20 B0 12 FA 55 2A 91 E9 27 09 4A +2A 41 81 49 00 00 B0 12 5A 5A 2A 41 DF 3F 3A 41 +30 40 5A 5A 9B 52 1E 20 12 00 8B 63 14 00 1A 42 +1A 20 19 42 1C 20 30 40 5C 54 2A 93 BC 20 0C 93 +09 20 F8 40 E5 00 00 1E B0 12 3E 5B B0 12 D2 5A +B0 12 C2 57 30 4D F2 B0 40 00 A2 04 29 20 F2 B0 +10 00 A2 04 FC 27 5A 42 B0 04 4A 11 59 42 B4 04 +F2 40 20 00 C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 +D2 42 B5 04 C8 04 19 52 E4 04 D2 42 B2 04 C0 04 +B2 40 00 08 C8 04 1A 52 E4 04 92 42 B6 04 C0 04 +B2 80 BC 07 C0 04 B2 40 00 02 C8 04 19 52 E4 04 +30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D +7C 2E 29 92 06 28 39 80 03 00 B0 12 12 5C 39 40 +03 00 7A 4B C8 4A 00 1E 82 9B 36 20 12 28 0D 12 +3D 40 0F 00 3C 40 C2 5B 7A 9C F3 27 1D 83 FC 23 +3D 41 6A 9C E6 27 3A 80 21 00 EB 3B 18 53 19 83 +E8 23 09 93 06 24 F8 40 20 00 00 1E 18 53 19 83 +FA 23 30 41 1A 4B 04 00 19 4B 06 00 B0 12 16 54 +18 4B 08 00 B0 12 66 5B 88 49 12 1E 88 4A 16 1E +88 49 18 1E 98 4B 12 00 1C 1E 98 4B 14 00 1E 1E +1A 4B 04 00 19 4B 06 00 30 40 5C 54 B2 40 00 02 +1E 20 1B 42 32 20 B0 12 34 5B 82 43 1E 20 DB 53 +03 00 DB 92 12 20 03 00 1D 28 B0 12 EE 55 08 12 +0A 12 B0 12 70 5A 2A 91 03 24 2A 41 B0 12 16 56 +3A 41 38 41 98 42 22 20 00 1E 98 42 24 20 02 1E +B0 12 5A 5A AB 42 02 00 9B 42 22 20 0E 00 9B 42 +24 20 10 00 30 40 54 56 36 58 0A 57 52 49 54 45 +B0 12 5C 5C 30 4D 2A 92 54 20 2C 93 0E 24 0C 93 +3D 24 0D 12 84 12 1E 40 0C 3C 20 57 72 69 74 65 +45 72 72 6F 72 00 B2 40 B0 54 0A 43 08 43 B0 12 +70 5A B0 12 9C 57 18 42 30 20 F8 40 20 00 0B 1E +B0 12 66 5B 88 43 0C 1E 88 4A 0E 1E 88 49 10 1E +98 42 24 20 14 1E 98 42 22 20 1A 1E 88 43 1C 1E +88 43 1E 1E 2C 42 1B 42 34 20 82 9B 36 20 D1 27 +FB 90 2E 00 00 00 CD 27 39 40 0B 00 B0 12 E2 5B +B0 12 3E 5B 2A 42 B0 12 66 56 30 4D B0 12 D2 5A +8B 43 12 00 8B 43 14 00 90 4B 0A 00 C6 C2 90 4B +0C 00 C2 C2 B0 12 FA 55 B0 12 70 5A B0 12 A4 5C +30 4D 2C 93 BA 27 0C 93 AC 23 EB 42 02 00 58 4B +13 00 59 4B 14 00 89 10 09 58 58 4B 15 00 5B 42 +12 20 0A 43 3C 42 08 11 09 10 4A 10 1C 83 0B 11 +FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 19 5B 0A 00 +18 6B 0C 00 8B 49 0E 00 8B 48 10 00 CB 4A 03 00 +B0 12 98 57 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 +FF 01 82 4A 1E 20 30 4D 2A 58 10 54 45 52 4D 32 +53 44 22 00 0D 12 84 12 3E 58 EC 5D 0A 43 7D 40 +0A 00 B0 12 44 41 3A 90 00 02 03 28 B0 12 5C 5C +0A 43 92 B3 EC 06 FD 27 59 42 CC 06 69 92 11 24 +CA 49 00 1E 1A 53 49 9D EE 23 A2 B3 EC 06 FD 27 +F2 40 0D 00 CE 06 A2 B3 EC 06 FD 27 C2 4D CE 06 +E0 3F C2 9D CC 06 FD 23 82 4A 1E 20 B0 12 C2 57 3D 41 30 4D @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 84 42 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 96 4E +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 D4 42 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 10 42 q diff --git a/binaries/MSP_EXP430FR5994_1MHz_UART.txt b/binaries/MSP_EXP430FR5994_1MHz_UART.txt deleted file mode 100644 index 782000a..0000000 --- a/binaries/MSP_EXP430FR5994_1MHz_UART.txt +++ /dev/null @@ -1,657 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF 0C 68 50 4D 34 01 -10 00 C1 B3 94 41 66 5F DA 41 24 5E 96 42 0C 68 -50 4D 7C 42 F2 43 26 43 00 43 3C 1D C0 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 -@4000 -B0 12 DA 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 66 5F 39 40 22 18 -B2 49 7A 42 B2 49 F0 43 B2 49 24 43 B2 49 FE 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 58 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 41 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 40 0A 40 DE 1D 40 44 34 43 -14 40 04 1B 5B 37 6D 00 BC 43 08 44 34 40 86 41 -14 40 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 BC 43 00 45 BC 43 14 40 04 1B 5B 30 6D 00 -BC 43 88 48 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 41 04 57 41 52 4D 00 -B0 12 24 5E 84 12 14 40 07 0D 0A 1B 5B 37 6D 23 -BC 43 36 45 14 40 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -BC 43 0A 40 40 FF 28 40 34 44 00 45 14 40 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 40 86 41 00 00 -06 41 43 43 45 50 54 00 30 40 7C 42 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 42 3C 40 -D4 42 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 42 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 43 -2F 83 8F 4E 00 00 B0 12 DA 41 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 41 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 43 08 4E 3E 4F C8 3F 1C 43 04 45 -43 48 4F 00 B2 40 C2 48 C2 42 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 42 -92 43 DE 1D 30 4D 0D 12 3D 40 76 43 1B 42 32 20 -9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 -1B 42 20 20 02 3C 78 43 2D 83 0C 9B 16 2C 58 4C -00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 -3D 41 82 4C 1E 20 3C 40 20 00 A6 3F 0E 99 8E 27 -CA 48 00 00 1A 53 1E 53 89 3F 1A 15 B0 12 1C 60 -19 17 DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 D8 43 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 24 43 DA 43 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 41 02 43 52 00 30 40 -F2 43 0D 12 84 12 14 40 02 0D 0A 00 BC 43 C0 44 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 42 01 40 -2E 4E 30 4D 3E 44 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D EA 43 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 7A 44 02 23 53 00 0D 12 -84 12 7C 44 B6 44 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D AA 44 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D B6 43 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -70 44 AE 44 EE 40 EE 44 CA 44 BC 43 74 48 22 43 -C0 44 42 43 01 2E 0E 93 E3 37 38 43 E2 3F E8 44 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 -BA 47 0A 40 22 00 8C 45 5A 45 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -34 45 82 2E 22 00 0D 12 84 12 44 45 0A 40 BC 43 -BA 47 C0 44 1A 42 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 0E 47 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F 10 47 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D B8 47 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D C6 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D DA 44 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 40 74 48 8C 45 30 48 -9C 26 3D 40 38 48 DE 3E 3A 48 0A 4E 3E 4F 3D 40 -54 48 36 27 3D 40 2A 48 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 56 48 3E 4F 3D 40 2A 48 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 F6 49 -CC 3F 5E 48 86 12 20 00 46 44 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 EE 43 -BC 40 24 48 24 44 56 44 14 40 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 -5E 44 14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 41 3A 40 9E 48 7A 48 86 41 42 4F 52 54 22 00 -0D 12 84 12 44 45 0A 40 2A 41 BA 47 C0 44 EE 45 -01 27 0D 12 84 12 74 48 8C 45 F4 45 34 40 72 48 -C0 44 00 00 83 5B 27 5D 0D 12 84 12 F2 48 0A 40 -0A 40 BA 47 BA 47 C0 44 04 49 81 5B 82 43 BE 1D -30 4D 6C 44 01 5D B2 43 BE 1D 30 4D 24 49 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 74 48 8C 45 F4 45 08 44 -34 40 72 48 56 44 34 40 66 49 0A 40 0A 40 BA 47 -BA 47 0A 40 BA 47 BA 47 C0 44 1A 49 01 3A 30 12 -B6 49 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 74 48 -8C 45 84 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 41 6C 49 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 40 C0 44 BA 47 C8 49 1C 49 -C0 44 1A 48 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 04 48 06 43 52 45 -41 54 45 00 B0 12 72 49 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F FA 49 07 3A 4E 4F 4E 41 4D 45 30 12 -B6 49 2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 -0E 4A 39 40 10 02 08 49 28 53 99 3F 2E 43 05 44 -45 46 45 52 B0 12 72 49 BA 40 30 40 FC FF BA 40 -F4 4D FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 14 4A -82 49 53 00 0D 12 82 93 BE 1D 06 24 84 12 08 49 -0A 40 86 4A BA 47 C0 44 84 12 F2 48 86 4A C0 44 -2C 4A 04 43 4F 44 45 00 B0 12 72 49 A2 82 C6 1D -82 43 7C 5C 0D 12 84 12 5A 4D 2C 4D C0 44 90 4A -07 48 44 4E 43 4F 44 45 B2 40 30 4D DA 1D EC 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 C8 49 -80 4D B4 4D C0 44 B2 4A 07 43 4F 44 45 4E 4E 4D -30 12 BC 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 80 4D B4 4D C0 44 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F D0 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 -94 4C BA 47 1C 49 C0 4A C0 44 46 4A 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 5C 4B 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 40 00 00 38 44 74 48 8C 45 -0A 48 00 44 34 40 F4 4B 0E 44 14 40 06 5B 54 48 -45 4E 5D 00 66 4B CE 4B 8A 4B AC 4B C0 44 0E 44 -14 40 06 5B 45 4C 53 45 5D 00 66 4B E4 4B 8A 4B -AA 4B C0 44 14 40 04 5B 49 46 5D 00 66 4B AC 4B -3A 40 AA 4B E2 43 14 40 05 0D 0A 6B 6F 20 BC 43 -BC 40 AC 40 3A 40 AC 4B 9A 4B 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 0A 4C 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 74 48 8C 45 -F4 45 18 4C C0 44 1E 4C 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 28 4C 50 44 C0 44 50 4C -B2 4E 0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C -CC 47 06 4D 41 52 4B 45 52 00 B0 12 72 49 BA 40 -85 12 FC FF BA 40 4E 4C FE FF 28 83 8A 48 00 00 -9A 42 C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 -C6 1D 9D 3E 2E 53 30 4D 6E 4A 05 44 4F 45 53 3E -1A 42 BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 -30 4D 86 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 -0D 12 84 12 34 4A 0A 40 10 00 0A 40 00 00 3E 40 -0A 40 00 00 BA 47 60 40 D0 4C 28 40 0A 40 C8 1D -00 44 40 44 BA 47 48 44 A0 4C 0A 40 CA 1D 48 44 -C0 44 F0 48 05 46 4F 52 54 48 85 12 EA 4C 54 4D -B0 63 E4 61 F4 4C 44 4B F8 42 FE 61 9A 4D 26 4E -06 64 AE 67 CA 66 00 00 A2 63 2E 49 54 46 00 00 -D8 48 09 41 53 53 45 4D 42 4C 45 52 85 12 EA 4C -48 5B E0 5A 44 5A 04 55 96 53 00 00 0C 59 00 00 -6C 5C 68 5D FA 53 AE 5D 14 5B 00 00 00 00 DE 54 -1E 4D 22 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 -D6 1D 08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 -FA 23 30 4D 3A 49 08 50 52 45 56 49 4F 55 53 00 -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 72 45 04 4F 4E 4C 59 00 -82 43 CC 1D 30 4D 9A 4C 0B 44 45 46 49 4E 49 54 -49 4F 4E 53 92 42 CA 1D DA 1D 30 4D FA 4C A0 4D -B4 4D C4 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D -3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 -FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 -3E 4F 3D 41 30 4D 76 4D 09 50 57 52 5F 53 54 41 -54 45 85 12 BC 4D 50 4D 0C 68 40 45 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 08 4E 92 42 0C 18 -06 4E EF 3F F8 4D 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 08 4E 92 42 C8 1D 06 4E 30 4D 0C 4E -08 52 53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 -92 42 C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 -DA 37 0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 A8 4E FE FF 29 83 B9 40 02 42 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 42 B2 49 -FA 40 B2 49 02 40 B2 49 22 42 B2 49 F0 FF B2 49 -0A 18 B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 -E2 D2 25 02 B2 43 42 02 B2 D3 46 02 B2 43 62 02 -B2 D3 66 02 F2 43 26 03 F2 D3 22 03 F2 40 A5 00 -61 01 82 43 62 01 82 43 66 01 B2 40 33 00 64 01 -D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 -19 83 FA 23 F2 D0 10 00 2A 03 F2 40 A5 00 A1 04 -F2 C0 40 00 A2 04 B2 42 B0 01 1E 42 08 18 82 43 -08 18 1E D2 9E 01 B0 12 F8 40 20 42 38 40 C0 1D -0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D -1C 15 0E 12 12 12 C4 1D 84 12 8C 45 F4 45 50 44 -34 40 8C 4F B0 46 34 40 A6 4F A0 4F 8E 4F 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 A8 4F B2 41 C4 1D 3E 41 84 12 -0A 40 2B 00 8C 45 F4 45 50 44 34 40 C4 4F B0 46 -34 40 72 48 1A 44 8C 45 B0 46 34 40 72 48 D0 4F -3E 5F E7 3F 32 B0 00 02 01 24 3E 4F 30 41 3E 40 -28 00 B0 12 70 4F B0 12 D4 4F 19 42 C6 1D A2 53 -C6 1D 89 4E 00 00 3E 40 29 00 1C 15 92 92 C0 1D -C4 1D 02 20 30 40 E0 49 12 12 C4 1D 92 53 C4 1D -84 12 8C 45 B0 46 34 40 26 50 1C 50 21 53 3E 90 -10 00 84 2D BE 2B 28 50 B2 41 C4 1D BA 3F 0D 12 -84 12 74 48 4C 4F 38 50 0C 43 1B 42 C6 1D A2 53 -C6 1D 6A 4E 3E 4F 7A 90 23 00 29 20 92 53 C4 1D -B0 12 70 4F B0 12 D4 4F 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 09 20 3C 40 10 02 92 53 C4 1D B0 12 70 4F -B0 12 D4 4F EB 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 1D B0 12 FA 4F 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 FA 4F 92 92 C0 1D C4 1D 02 24 92 53 -C4 1D 8E 10 0C 5E D8 3F B0 12 FA 4F FA 23 3C 50 -10 00 B0 12 DE 4F EF 3F 0C 43 1B 42 C6 1D A2 53 -C6 1D 0D 12 84 12 74 48 4C 4F 0C 51 FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C5 3F B0 12 -FA 4F E0 23 3C 50 80 00 B0 12 DE 4F DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 40 00 13 BA 47 -C0 44 0A 40 2C 00 2E 50 02 51 4C 51 09 4B 2E 4E -0E DC A0 3F 32 4B 03 4D 4F 56 85 12 42 51 00 40 -56 51 05 4D 4F 56 2E 42 85 12 42 51 40 40 00 00 -03 41 44 44 85 12 42 51 00 50 70 51 05 41 44 44 -2E 42 85 12 42 51 40 50 7C 51 04 41 44 44 43 00 -85 12 42 51 00 60 8A 51 06 41 44 44 43 2E 42 00 -85 12 42 51 40 60 30 51 04 53 55 42 43 00 85 12 -42 51 00 70 A8 51 06 53 55 42 43 2E 42 00 85 12 -42 51 40 70 B6 51 03 53 55 42 85 12 42 51 00 80 -C6 51 05 53 55 42 2E 42 85 12 42 51 40 80 08 4B -03 43 4D 50 85 12 42 51 00 90 E0 51 05 43 4D 50 -2E 42 85 12 42 51 40 90 E2 4A 04 44 41 44 44 00 -85 12 42 51 00 A0 FA 51 06 44 41 44 44 2E 42 00 -85 12 42 51 40 A0 EC 51 03 42 49 54 85 12 42 51 -00 B0 18 52 05 42 49 54 2E 42 85 12 42 51 40 B0 -24 52 03 42 49 43 85 12 42 51 00 C0 32 52 05 42 -49 43 2E 42 85 12 42 51 40 C0 3E 52 03 42 49 53 -85 12 42 51 00 D0 4C 52 05 42 49 53 2E 42 85 12 -42 51 40 D0 00 00 03 58 4F 52 85 12 42 51 00 E0 -66 52 05 58 4F 52 2E 42 85 12 42 51 40 E0 98 51 -03 41 4E 44 85 12 42 51 00 F0 80 52 05 41 4E 44 -2E 42 85 12 42 51 40 F0 74 48 2E 50 9E 52 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F D2 51 -03 52 52 43 85 12 98 52 00 10 B0 52 05 52 52 43 -2E 42 85 12 98 52 40 10 BC 52 04 53 57 50 42 00 -85 12 98 52 80 10 CA 52 03 52 52 41 85 12 98 52 -00 11 D8 52 05 52 52 41 2E 42 85 12 98 52 40 11 -E4 52 03 53 58 54 85 12 98 52 80 11 00 00 04 50 -55 53 48 00 85 12 98 52 00 12 FE 52 06 50 55 53 -48 2E 42 00 85 12 98 52 40 12 58 52 04 43 41 4C -4C 00 85 12 98 52 80 12 1A 53 0E 4A 0D 12 84 12 -36 45 14 40 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 41 F2 52 03 53 3E 3D 86 12 00 38 46 53 -02 53 3C 00 86 12 00 34 0C 53 03 30 3E 3D 86 12 -00 30 5A 53 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C 6E 53 03 55 3E 3D 86 12 00 28 -64 53 03 30 3C 3E 86 12 00 24 82 53 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 0E 4A 30 4D 78 53 04 54 48 45 -4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 08 52 -04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 -A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 1C 53 05 42 -45 47 49 4E 30 40 28 40 AC 53 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 1D 30 4D 8C 52 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 9A 53 1A 44 C0 44 50 53 06 52 45 50 45 41 -54 00 0D 12 84 12 2E 54 B2 53 C0 44 5E 54 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D -00 00 30 4D EE 53 03 42 57 31 85 12 5C 54 00 00 -76 54 03 42 57 32 85 12 5C 54 00 00 82 54 03 42 -57 33 85 12 5C 54 00 00 9A 54 3D 41 1A 42 C6 1D -28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -98 54 00 00 BA 54 03 46 57 32 85 12 98 54 00 00 -C6 54 03 46 57 33 85 12 98 54 00 00 00 00 05 3F -47 4F 54 4F 3E 90 00 30 07 24 3E E0 00 04 3E B0 -00 10 02 24 3E E0 00 08 0D 12 84 12 F2 48 4E 48 -C0 44 D2 54 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C F1 3F 74 48 4C 4F 1C 55 92 53 C4 1D -3E 40 2C 00 84 12 8C 45 B0 46 34 40 72 48 F8 50 -32 55 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E 4A 54 -04 52 52 43 4D 00 85 12 16 55 50 00 60 55 04 52 -52 41 4D 00 85 12 16 55 50 01 6E 55 04 52 4C 41 -4D 00 85 12 16 55 50 02 7C 55 04 52 52 55 4D 00 -85 12 16 55 50 03 8C 53 05 50 55 53 48 4D 85 12 -16 55 00 15 98 55 04 50 4F 50 4D 00 85 12 16 55 -00 17 8A 55 06 52 52 43 4D 2E 41 00 85 12 16 55 -40 00 B4 55 06 52 52 41 4D 2E 41 00 85 12 16 55 -40 01 C4 55 06 52 4C 41 4D 2E 41 00 85 12 16 55 -40 02 D4 55 06 52 52 55 4D 2E 41 00 85 12 16 55 -40 03 A6 55 07 50 55 53 48 4D 2E 41 85 12 16 55 -00 14 F4 55 06 50 4F 50 4D 2E 41 00 85 12 16 55 -00 16 8E 54 05 43 41 4C 4C 41 0D 12 84 12 74 48 -4C 4F 24 56 1B 42 C6 1D A2 53 C6 1D 6E 4E 3C 40 -34 01 7E 90 52 00 0B 20 7E 40 20 00 B0 12 FA 4F -5C 0E 0C DE 8B 4C 00 00 3E 4F 3D 41 30 4D 2C 53 -7E 90 40 00 0B 20 92 53 C4 1D 7E 40 20 00 B0 12 -FA 4F EE 23 1C 53 3E 40 2B 00 E8 3F A2 53 C6 1D -7E 90 23 00 09 20 3C 40 3B 01 92 53 C4 1D B0 12 -70 4F BB 4F 02 00 DC 3F 7E 90 26 00 02 20 2C 53 -F4 3F 7E 40 28 00 1C 83 B0 12 70 4F BB 4F 02 00 -3E 40 29 00 CB 3F 0D 12 84 12 74 48 4C 4F B0 56 -69 4E 3E 4F 3C 4F 2C 4C 1B 42 C6 1D A2 53 C6 1D -79 90 52 00 0A 20 B0 12 FA 4F 5E 0E 5E 0E 0E DC -8B 4E 00 00 0E 4B 3D 41 30 4D 79 90 23 00 0D 20 -3C C0 40 00 92 53 C4 1D A2 53 C6 1D B0 12 70 4F -BB 4F 02 00 3E F0 0F 00 E8 3F 79 90 26 00 03 20 -3C E0 E0 00 EF 3F 3C C0 F0 00 79 90 40 00 12 20 -92 53 C4 1D B0 12 FA 4F D8 23 3C D0 10 00 3E 40 -2B 00 B0 12 FA 4F 92 92 C0 1D C4 1D CE 27 92 53 -C4 1D CB 3F 3C D0 30 00 A2 53 C6 1D 3E 40 28 00 -B0 12 70 4F BB 4F 02 00 3E 40 29 00 EA 3F 0D 12 -84 12 74 48 4C 4F 58 57 3B 4F 2C 4B 69 4E 7E 40 -20 00 79 90 52 00 03 20 B0 12 FA 4F B0 3F 3C C0 -F0 00 A2 53 C6 1D 79 90 26 00 09 20 3C D0 60 00 -92 53 C4 1D B0 12 70 4F BB 4F 02 00 A0 3F 3C D0 -70 00 3E 40 28 00 B0 12 70 4F BB 4F 02 00 3E 40 -29 00 E2 3F 0A 40 2C 00 A6 56 4E 57 E4 43 C0 44 -62 51 04 4D 4F 56 41 00 85 12 A4 57 C0 00 14 56 -04 43 4D 50 41 00 85 12 A4 57 D0 00 28 54 04 41 -44 44 41 00 85 12 A4 57 E0 00 E4 55 04 53 55 42 -41 00 85 12 A4 57 F0 00 0D 12 84 12 74 48 4C 4F -F2 57 69 4E 3E 4F 3C 40 00 18 79 90 52 00 05 20 -B0 12 FA 4F 0E 4C 3D 41 30 4D 82 43 7C 5C 79 90 -23 00 0B 20 92 53 C4 1D B0 12 70 4F 2F 53 3E F0 -0F 00 5E 0A 5E 0E 0C DE ED 3F 79 90 26 00 F2 27 -79 90 40 00 12 20 92 53 C4 1D B0 12 FA 4F E2 23 -3E 40 2B 00 92 53 C4 1D B0 12 FA 4F 92 92 C0 1D -C4 1D D8 27 92 53 C4 1D D5 3F 3E 40 28 00 B0 12 -70 4F 8F 4E 00 00 3E 40 29 00 B0 12 FA 4F 3E 4F -3E F0 0F 00 0C DE EA 3F 0D 12 84 12 74 48 4C 4F -82 58 3C 4F 69 4E 3E 40 20 00 79 90 52 00 BA 27 -82 43 7C 5C 79 90 26 00 08 20 92 53 C4 1D B0 12 -70 4F 2F 53 3E F0 0F 00 BE 3F 3E 40 28 00 B0 12 -70 4F F7 3F B2 4F C4 1D 1B 42 C6 1D A2 53 C6 1D -0C 4E 3E 4F 1C D2 7C 5C 82 43 7C 5C 3C DE 8B 4C -00 00 30 4D 0A 40 C4 1D 40 44 0A 40 2C 00 E8 57 -78 58 B4 58 3A 40 42 51 B2 57 04 4D 4F 56 58 00 -85 12 D4 58 40 00 00 40 EA 58 06 4D 4F 56 58 2E -41 00 85 12 D4 58 00 00 40 40 FA 58 06 4D 4F 56 -58 2E 42 00 85 12 D4 58 40 00 40 40 CE 57 04 41 -44 44 58 00 85 12 D4 58 40 00 00 50 1E 59 06 41 -44 44 58 2E 41 00 85 12 D4 58 00 00 40 50 2E 59 -06 41 44 44 58 2E 42 00 85 12 D4 58 40 00 40 50 -40 59 05 41 44 44 43 58 85 12 D4 58 40 00 00 60 -52 59 07 41 44 44 43 58 2E 41 85 12 D4 58 00 00 -40 60 62 59 07 41 44 44 43 58 2E 42 85 12 D4 58 -40 00 40 60 DC 57 05 53 55 42 43 58 85 12 D4 58 -40 00 00 70 86 59 07 53 55 42 43 58 2E 41 85 12 -D4 58 00 00 40 70 96 59 07 53 55 42 43 58 2E 42 -85 12 D4 58 40 00 40 70 A8 59 04 53 55 42 58 00 -85 12 D4 58 40 00 00 80 BA 59 06 53 55 42 58 2E -41 00 85 12 D4 58 00 00 40 80 CA 59 06 53 55 42 -58 2E 42 00 85 12 D4 58 40 00 40 80 C0 57 04 43 -4D 50 58 00 85 12 D4 58 40 00 00 90 EE 59 06 43 -4D 50 58 2E 41 00 85 12 D4 58 00 00 40 90 FE 59 -06 43 4D 50 58 2E 42 00 85 12 D4 58 40 00 40 90 -D0 53 05 44 41 44 44 58 85 12 D4 58 40 00 00 A0 -22 5A 07 44 41 44 44 58 2E 41 85 12 D4 58 00 00 -40 A0 32 5A 07 44 41 44 44 58 2E 42 85 12 D4 58 -40 00 40 A0 10 5A 04 42 49 54 58 00 85 12 D4 58 -40 00 00 B0 56 5A 06 42 49 54 58 2E 41 00 85 12 -D4 58 00 00 40 B0 66 5A 06 42 49 54 58 2E 42 00 -85 12 D4 58 40 00 40 B0 78 5A 04 42 49 43 58 00 -85 12 D4 58 40 00 00 C0 8A 5A 06 42 49 43 58 2E -41 00 85 12 D4 58 00 00 40 C0 9A 5A 06 42 49 43 -58 2E 42 00 85 12 D4 58 40 00 40 C0 AC 5A 04 42 -49 53 58 00 85 12 D4 58 40 00 00 D0 BE 5A 06 42 -49 53 58 2E 41 00 85 12 D4 58 00 00 40 D0 CE 5A -06 42 49 53 58 2E 42 00 85 12 D4 58 40 00 40 D0 -72 52 04 58 4F 52 58 00 85 12 D4 58 40 00 00 E0 -F2 5A 06 58 4F 52 58 2E 41 00 85 12 D4 58 00 00 -40 E0 02 5B 06 58 4F 52 58 2E 42 00 85 12 D4 58 -40 00 40 E0 74 59 04 41 4E 44 58 00 85 12 D4 58 -40 00 00 F0 26 5B 06 41 4E 44 58 2E 41 00 85 12 -D4 58 00 00 40 F0 36 5B 06 41 4E 44 58 2E 42 00 -85 12 D4 58 40 00 40 F0 0A 40 C4 1D 40 44 74 48 -E8 57 B4 58 3A 40 98 52 DC 59 04 52 52 43 58 00 -85 12 58 5B 40 00 00 10 6A 5B 06 52 52 43 58 2E -41 00 85 12 58 5B 00 00 40 10 7A 5B 06 52 52 43 -58 2E 42 00 85 12 58 5B 40 00 40 10 8C 5B 04 52 -52 55 58 00 85 12 58 5B 40 01 00 10 9E 5B 06 52 -52 55 58 2E 41 00 85 12 58 5B 00 01 40 10 AE 5B -06 52 52 55 58 2E 42 00 85 12 58 5B 40 01 40 10 -C0 5B 05 53 57 50 42 58 85 12 58 5B 40 00 80 10 -D2 5B 07 53 57 50 42 58 2E 41 85 12 58 5B 00 00 -80 10 E2 5B 04 52 52 41 58 00 85 12 58 5B 40 00 -00 11 F4 5B 06 52 52 41 58 2E 41 00 85 12 58 5B -00 00 40 11 04 5C 06 52 52 41 58 2E 42 00 85 12 -58 5B 40 00 40 11 16 5C 04 53 58 54 58 00 85 12 -58 5B 40 00 80 11 28 5C 06 53 58 54 58 2E 41 00 -85 12 58 5B 00 00 80 11 04 56 05 50 55 53 48 58 -85 12 58 5B 40 00 00 12 4A 5C 07 50 55 53 48 58 -2E 41 85 12 58 5B 00 00 40 12 5A 5C 07 50 55 53 -48 58 2E 42 85 12 58 5B 40 00 40 12 00 00 38 5C -03 52 50 54 0D 12 84 12 74 48 4C 4F 8E 5C 29 4E -7E 40 20 00 79 90 52 00 06 20 B0 12 FA 4F 03 24 -3E D0 80 00 05 3C B0 12 70 4F 1E 83 3E F0 0F 00 -82 4E 7C 5C 3E 4F 3D 41 30 4D D2 C3 23 02 E2 B2 -60 02 02 24 30 40 02 42 1A 52 04 20 19 62 06 20 -92 43 14 20 A2 93 02 20 07 24 0A 5A 49 69 82 4A -16 20 C2 49 18 20 0A 3C C2 4A 15 20 8A 10 C2 4A -16 20 C2 49 17 20 89 10 C2 49 18 20 B0 12 42 5D -5A 53 FC 23 39 40 05 00 D2 49 14 20 4E 06 82 93 -46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 59 83 -F3 2F 19 83 0B 30 F2 43 4E 06 82 93 46 06 03 24 -92 B3 6C 06 FD 27 5A 92 4C 06 F3 23 30 41 1A 43 -E1 3F 19 43 3A 43 8A 10 C2 4A 4E 06 82 93 46 06 -05 24 92 B3 6C 06 FD 27 C2 93 4C 06 19 83 F3 23 -5A 42 4C 06 30 41 80 5C 08 52 45 41 44 5F 53 57 -58 00 1C D3 F2 40 51 00 19 20 B0 12 BA 5C 38 20 -B0 12 42 5D 6A 53 04 24 FB 23 D9 42 4C 06 FF 1D -F2 43 4E 06 03 43 19 53 39 90 01 02 F6 23 F2 43 -4E 06 3C C0 03 00 D2 D3 23 02 30 41 38 54 09 57 -52 49 54 45 5F 53 57 58 2C D3 F0 40 58 00 5B C2 -B0 12 BA 5C 15 20 3A 40 FE FF 29 43 B0 12 46 5D -D2 49 00 1E 4E 06 03 43 19 53 39 90 00 02 F8 23 -39 40 03 00 B0 12 44 5D 7A C0 E1 00 6A 92 D9 27 -8C 10 1C 52 4C 06 D2 D3 23 02 0D 12 84 12 34 43 -14 40 0B 3C 20 53 44 20 45 72 72 6F 72 21 10 5E -2F 83 8F 4E 00 00 B2 40 10 00 DC 1D 0E 4C 84 12 -00 45 36 41 B0 12 9C 41 0E 93 9C 24 E2 B2 60 02 -99 20 B2 40 81 A9 40 06 B2 40 03 00 46 06 D2 D3 -25 02 B2 D0 C0 04 0C 02 92 C3 40 06 39 42 B0 12 -44 5D D2 C3 23 02 2C 42 B2 40 95 00 14 20 B2 40 -00 40 18 20 B0 12 3E 5D 02 24 30 40 F0 5D B0 12 -42 5D 7A 93 FC 23 B2 40 87 AA 14 20 92 43 16 20 -B2 40 00 48 18 20 B0 12 3E 5D 29 42 B0 12 44 5D -92 43 14 20 82 43 16 20 78 43 3C 42 B2 40 00 77 -18 20 B0 12 3E 5D B2 40 40 69 18 20 B0 12 FC 5C -03 24 58 83 F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 -00 50 18 20 B0 12 FC 5C D0 23 92 D3 40 06 82 43 -46 06 92 C3 40 06 09 43 B0 12 72 5D 38 40 00 1E -92 48 C6 01 04 20 92 48 C8 01 06 20 5A 48 C2 01 -92 43 02 20 7A 80 06 00 0F 24 7A 82 0D 24 A2 43 -02 20 6A 53 09 24 5A 53 07 24 6A 52 05 24 3A 50 -0B 20 0C 4A 30 40 F6 5D 09 43 B0 12 72 5D D2 48 -0D 00 12 20 19 48 0E 00 82 49 08 20 1A 48 16 00 -0A 93 02 20 1A 48 24 00 82 4A 0A 20 09 5A 82 49 -0C 20 09 5A A2 93 02 20 04 24 82 49 0E 20 39 50 -20 00 19 82 12 20 19 82 12 20 82 49 10 20 92 42 -02 20 2C 20 30 41 B0 12 AA 40 39 40 E0 00 29 83 -89 43 38 20 FC 23 82 43 32 20 30 41 92 4B 0E 00 -22 20 92 4B 10 00 24 20 5A 42 23 20 58 42 22 20 -92 93 02 20 08 24 59 42 24 20 89 10 0A 59 88 10 -08 58 0A 6A 88 10 08 58 30 41 82 43 1C 20 92 42 -0E 20 1A 20 C2 93 24 20 03 20 92 93 22 20 14 24 -92 42 22 20 D0 04 92 42 24 20 D2 04 92 42 12 20 -C8 04 92 42 E4 04 1A 20 92 42 E6 04 1C 20 92 52 -10 20 1A 20 82 63 1C 20 30 41 92 4B 0E 00 22 20 -92 4B 10 00 24 20 B0 12 AA 5F 5A 4B 03 00 82 5A -1A 20 82 63 1C 20 30 41 09 93 07 24 F8 90 20 00 -00 1E 03 20 18 53 19 83 F9 23 30 41 1B 42 32 20 -82 43 1E 20 B2 90 00 02 20 20 AB 20 BB 80 00 02 -12 00 8B 73 14 00 DB 53 03 00 DB 92 12 20 03 00 -14 28 CB 43 03 00 B0 12 7C 5F 1A 52 08 20 09 43 -B0 12 72 5D 8B 43 10 00 9B 48 00 1E 0E 00 92 93 -02 20 03 24 9B 48 02 1E 10 00 B2 40 00 02 20 20 -8B 93 14 00 0B 20 92 9B 12 00 1E 20 82 2C BB 90 -00 02 12 00 03 2C 92 4B 12 00 20 20 B0 12 EA 5F -1A 42 1A 20 19 42 1C 20 6C 3E 3C 42 3B 40 38 20 -09 43 CB 93 02 00 10 24 9B 92 24 20 0C 00 04 20 -9B 92 22 20 0A 00 07 24 09 4B 3B 50 1C 00 3B 90 -18 21 EF 23 0C 5C 30 41 0C 43 82 4B 32 20 8B 49 -00 00 09 93 0A 24 99 52 C4 1D 16 00 4A 93 05 34 -C9 93 02 00 02 34 5A 59 02 00 CB 4A 02 00 CB 43 -03 00 9B 42 1A 20 04 00 9B 42 1C 20 06 00 18 42 -30 20 8B 48 08 00 9B 48 1A 1E 0A 00 9B 48 14 1E -0C 00 9B 48 1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 -1C 1E 12 00 9B 48 1E 1E 14 00 82 43 1E 20 6A 93 -5C 27 C9 37 8B 43 16 00 7A 93 02 24 07 38 95 3F -B2 40 1C 21 CA 40 B2 40 56 43 7A 42 9B 42 C0 1D -18 00 9B 82 C4 1D 18 00 9B 42 C2 1D 1A 00 9B 52 -C4 1D 1A 00 82 3F CB 43 02 00 2B 4B 82 4B 32 20 -0B 93 06 24 92 4B 16 00 1E 20 B0 12 6A 60 22 C3 -30 41 1B 42 32 20 0B 93 FB 27 EB 93 02 00 04 20 -B0 12 46 66 B0 12 0E 66 CB 93 02 00 E4 37 1E 4B -18 00 9F 4B 1A 00 00 00 31 50 06 00 3D 41 B0 12 -66 61 02 24 30 40 4A 43 B2 40 3C 1D CA 40 B2 40 -7C 42 7A 42 30 40 34 43 40 4E 85 52 45 41 44 22 -5A 43 19 3C B4 4C 86 57 52 49 54 45 22 00 6A 43 -12 3C A8 4D 84 44 45 4C 22 00 6A 42 0C 3C F8 4A -05 43 4C 4F 53 45 B0 12 82 61 30 4D 62 4C 85 4C -4F 41 44 22 7A 43 2F 83 8F 4E 00 00 0E 4A 82 93 -BE 1D 0B 24 0D 12 84 12 0A 40 0A 40 BA 47 BA 47 -44 45 0A 40 3A 62 BA 47 C0 44 0D 12 84 12 0A 40 -22 00 8C 45 0A 48 38 62 3D 41 36 4F 0E 56 82 4E -36 20 1C 43 92 42 2C 20 22 20 92 42 2E 20 24 20 -0E 96 8D 24 F6 90 3A 00 01 00 01 20 26 53 F6 90 -5C 00 00 00 08 20 16 53 92 42 02 20 22 20 82 43 -24 20 0E 96 70 24 82 46 34 20 B0 12 AA 5F 35 40 -20 00 A2 93 02 20 04 24 92 92 22 20 02 20 02 24 -15 42 12 20 B0 12 90 60 2C 43 0A 43 08 4A 58 0E -08 58 82 48 30 20 C8 93 00 1E 61 24 39 42 F8 96 -00 1E 04 20 18 53 19 83 FA 23 16 53 F6 90 2E 00 -FF FF 19 24 39 50 03 00 B0 12 08 60 06 20 F6 90 -5C 00 FF FF 29 24 0E 96 27 28 16 42 34 20 1A 53 -3A 90 10 00 DB 23 92 53 1A 20 82 63 1C 20 15 83 -D1 23 2C 42 3C 3C F6 90 2E 00 FE FF EE 27 B0 12 -08 60 EB 23 39 40 03 00 F8 96 00 1E 04 20 18 53 -19 83 FA 23 09 3C 0E 96 E0 2F F6 90 5C 00 FF FF -DC 23 B0 12 08 60 D9 23 18 42 30 20 92 48 1A 1E -22 20 92 48 14 1E 24 20 F8 B0 10 00 0B 1E 14 24 -82 93 24 20 06 20 82 93 22 20 03 20 92 42 02 20 -22 20 0E 96 8E 2F 92 42 22 20 2C 20 92 42 24 20 -2E 20 8F 43 00 00 03 3C 2A 4F B0 12 9A 60 35 40 -D4 40 36 40 E2 40 3A 4F 3E 4F 0A 93 04 24 7A 93 -3C 20 0C 93 01 20 30 4D 0D 12 84 12 34 43 14 40 -0B 3C 20 4F 70 65 6E 45 72 72 6F 72 3A 40 0E 5E -38 4C 05 5B 50 46 41 5D 2E 53 2E 4E 30 4D F0 61 -04 42 4F 4F 54 00 39 40 24 5E 2E 93 01 2C 30 41 -E2 B2 60 02 02 24 10 49 02 00 89 12 3F 40 7E 1C -8F 43 00 00 82 43 BE 1D B2 40 00 1C 00 1C 31 40 -E0 1C 84 12 14 40 0F 4C 4F 41 44 22 20 42 4F 4F -54 2E 34 54 48 22 3A 40 A2 48 1A 93 BB 20 0C 93 -C3 23 30 4D CA 61 04 52 45 41 44 00 2F 83 8F 4E -00 00 1E 42 32 20 B0 12 1C 60 1E 82 32 20 30 4D -2C 43 12 12 2A 20 18 42 02 20 08 58 2A 41 82 9A -0A 20 A6 24 1A 52 08 20 09 43 B0 12 72 5D 09 43 -28 93 03 24 89 93 02 1E 03 20 89 93 00 1E 07 24 -09 58 39 90 00 02 F4 23 91 53 00 00 E7 3F 0C 43 -6A 41 B9 43 00 1E 28 93 0F 24 B9 40 FF 0F 02 1E -09 11 8A 10 09 5A 5A 41 01 00 0A 11 09 10 82 4A -28 20 82 49 26 20 07 3C 09 11 C2 49 26 20 C2 4A -27 20 82 43 28 20 3A 41 82 4A 2A 20 30 41 0A 12 -1A 52 08 20 09 43 B0 12 B8 5D 3A 41 1A 52 0C 20 -09 43 B0 12 B8 5D F2 B0 40 00 A2 04 29 20 F2 B0 -10 00 A2 04 FC 27 5A 42 B0 04 4A 11 59 42 B4 04 -F2 40 20 00 C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 -D2 42 B5 04 C8 04 19 52 E4 04 D2 42 B2 04 C0 04 -B2 40 00 08 C8 04 1A 52 E4 04 92 42 B6 04 C0 04 -B2 80 BC 07 C0 04 B2 40 00 02 C8 04 19 52 E4 04 -30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D -7C 2E 29 92 06 38 39 80 03 00 B0 12 62 65 39 40 -03 00 7A 4B C8 4A 00 1E 82 9B 36 20 12 28 0D 12 -3D 40 0F 00 3C 40 12 65 7A 9C F3 27 1D 83 FC 23 -3D 41 6A 9C E6 27 3A 80 21 00 EB 3B 18 53 19 83 -E8 23 09 93 06 24 F8 40 20 00 00 1E 18 53 19 83 -FA 23 30 41 2A 93 DC 20 2C 93 0E 24 0C 93 AB 24 -0D 12 84 12 14 40 0C 3C 20 57 72 69 74 65 45 72 -72 6F 72 00 3A 40 0E 5E B0 12 20 64 92 42 26 20 -22 20 92 42 28 20 24 20 B0 12 9E 64 B0 12 90 60 -18 42 30 20 F8 40 20 00 0B 1E B0 12 B6 64 88 43 -0C 1E 88 4A 0E 1E 88 49 10 1E 88 49 12 1E 98 42 -24 20 14 1E 98 42 22 20 1A 1E 88 43 1C 1E 88 43 -1E 1E 1C 43 1B 42 34 20 82 9B 36 20 C9 27 FB 90 -2E 00 00 00 C5 27 39 40 0B 00 B0 12 32 65 B0 12 -50 66 2A 43 B0 12 9A 60 0C 93 BA 23 30 4D 1A 4B -04 00 19 4B 06 00 B0 12 72 5D B0 12 B6 64 18 4B -08 00 88 49 12 1E 88 4A 16 1E 88 49 18 1E 98 4B -12 00 1C 1E 98 4B 14 00 1E 1E 1A 4B 04 00 19 4B -06 00 30 40 B8 5D 9B 52 1E 20 12 00 8B 63 14 00 -1A 42 1A 20 19 42 1C 20 30 40 B8 5D B2 40 00 02 -1E 20 1B 42 32 20 B0 12 46 66 82 43 1E 20 DB 53 -03 00 DB 92 12 20 03 00 25 20 CB 43 03 00 B0 12 -7C 5F 08 12 0A 12 B0 12 20 64 2A 91 08 24 B0 12 -9E 64 2A 41 1A 52 08 20 09 43 B0 12 72 5D 3A 41 -38 41 98 42 26 20 00 1E 92 93 02 20 03 24 98 42 -28 20 02 1E B0 12 9E 64 9B 42 26 20 0E 00 9B 42 -28 20 10 00 30 40 EA 5F D6 61 05 57 52 49 54 45 -B0 12 5C 66 30 4D 58 4B 13 00 59 4B 14 00 89 10 -09 58 58 4B 15 00 5B 42 12 20 0A 43 3C 42 08 11 -09 10 4A 10 1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 -1B 42 32 20 19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 -8B 48 10 00 CB 4A 03 00 1A 4B 12 00 BB C0 FF 01 -12 00 3A F0 FF 01 82 4A 1E 20 B0 12 8C 60 30 4D -0C 93 3B 20 38 90 E0 01 03 2C C8 93 20 1E 02 24 -7C 40 E5 00 C8 4C 00 1E B0 12 50 66 B0 12 88 5F -82 4A 2A 20 0B 4A 1A 52 08 20 09 43 B0 12 72 5D -1A 48 00 1E 88 43 00 1E 92 93 02 20 09 24 19 48 -02 1E 88 43 02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 -3A 93 0E 24 82 4A 22 20 82 49 24 20 B0 12 88 5F -0B 9A E6 27 0A 12 0A 4B B0 12 9E 64 3A 41 DA 3F -0A 4B B0 12 9E 64 B0 12 82 61 30 4D FC 44 08 54 -45 52 4D 32 53 44 22 00 0D 12 84 12 EA 61 0A 40 -02 00 28 40 0A 48 3A 62 CA 67 3D 41 0A 43 B0 12 -DA 41 92 B3 DC 05 FD 27 59 42 CC 05 C2 49 CE 05 -69 92 0D 24 CA 49 00 1E 1A 53 3A 90 FF 01 F1 2B -03 24 B0 12 5C 66 EA 3F B0 12 C8 41 EA 3F B0 12 -C8 41 82 4A 1E 20 B0 12 82 61 30 4D -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -96 42 02 42 02 42 02 42 02 42 02 42 02 42 A8 4E -q diff --git a/binaries/MSP_EXP430FR5994_8MHz_115200.txt b/binaries/MSP_EXP430FR5994_8MHz_115200.txt new file mode 100644 index 0000000..579c6fc --- /dev/null +++ b/binaries/MSP_EXP430FR5994_8MHz_115200.txt @@ -0,0 +1,504 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 59 +D6 42 7E 41 06 56 E6 54 46 43 5E 5E 4A 4C 04 4C +04 4C BC 42 7A 43 42 43 3C 1D E0 1C F8 45 B6 40 +C4 40 14 45 20 00 0A 00 00 1C 7E 41 06 56 E6 54 +46 43 5E 5E 4A 4C 04 4C 04 4C 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4000 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 06 3D 0E 93 3E 4F +CA 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BA 42 B2 49 +78 43 B2 49 40 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 BE 4C 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 46 43 92 C3 DC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 DC 05 F3 23 +B0 12 D0 40 1E 45 AC 40 52 41 88 43 1E 40 04 1B +5B 37 6D 00 08 44 08 44 1E 40 04 1B 5B 30 6D 00 +08 44 54 49 B0 12 7E 41 B2 40 81 00 C0 05 92 42 +02 18 C6 05 92 42 04 18 C8 05 F2 D0 03 00 0D 02 +92 C3 C0 05 92 D3 DA 05 92 C3 30 01 30 41 92 B3 +CA 05 FD 23 30 41 92 12 3E 18 84 12 88 43 1E 40 +07 0D 0A 1B 5B 37 6D 23 08 44 6C 46 1E 40 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 08 44 0A 40 40 FF 32 40 +34 45 38 46 1E 40 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 40 46 41 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 41 01 12 71 3F 82 4E +08 18 92 12 3A 18 F2 B0 40 00 40 02 02 20 B2 43 +08 18 B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 +10 00 00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 +E0 1C B2 D3 06 02 B2 40 FC FF 02 02 B2 43 26 02 +B2 D3 22 02 E2 D2 25 02 B2 43 42 02 B2 D3 46 02 +B2 43 62 02 B2 D3 66 02 F2 43 26 03 F2 D3 22 03 +F2 40 A5 00 61 01 82 43 66 01 B2 40 33 00 64 01 +D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 F2 D0 10 00 2A 03 F2 40 A5 00 A1 04 +F2 C0 40 00 A2 04 B2 42 B0 01 39 40 00 10 29 83 +89 43 00 1C FC 23 19 42 9E 01 1E 42 08 18 82 43 +08 18 3E F3 01 20 0E 49 B0 12 D0 40 86 41 00 00 +0C 41 43 43 45 50 54 00 30 40 BC 42 08 4E 2E 4F +08 5E 39 40 0D 00 3A 40 20 00 3B 40 1A 43 3C 40 +26 43 5D 15 95 3E 21 52 3A 17 58 42 CC 05 48 9B +09 20 A2 B3 DC 05 FD 27 B2 40 13 00 CE 05 E2 D2 +23 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 +1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 A2 B3 +DC 05 FD 27 C2 48 CE 05 30 4D 1C 43 2D 83 92 B3 +DC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 DC 05 FD 27 +58 42 CC 05 08 4C EB 3F 00 00 06 4B 45 59 30 40 +42 43 30 12 58 43 A2 B3 DC 05 FD 27 B2 40 11 00 +CE 05 E2 C2 23 02 30 41 2F 83 8F 4E 00 00 92 B3 +DC 05 FD 27 B0 12 E2 42 1E 42 CC 05 30 4D 00 00 +08 45 4D 49 54 00 30 40 7A 43 08 4E 3E 4F C7 3F +70 43 08 45 43 48 4F 00 B2 40 C2 48 14 43 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 14 43 +30 4D 0D 12 3D 40 C2 43 1B 42 32 20 9B 42 1E 20 +16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 1B 42 20 20 +02 3C C4 43 2D 83 0C 9B 16 2C 58 4C 00 1E 1C 53 +78 90 20 00 09 2C 78 90 0A 00 F5 23 82 4C 1E 20 +3D 41 3C 40 20 00 A6 3F 0E 99 91 27 CA 48 00 00 +1A 53 1E 53 8C 3F 1A 15 B0 12 54 57 19 17 DC 3F +00 00 08 54 59 50 45 00 0D 12 3D 40 18 44 29 4F +8F 4E 00 00 7E 49 AF 3F 1A 44 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 3C 22 F9 98 00 00 39 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +30 22 9B 24 3A 43 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A 40 00 00 38 45 2A 44 7C 46 36 49 B0 40 +A6 44 14 40 06 5B 54 48 45 4E 5D 00 2E 44 84 44 +4A 44 68 44 14 40 06 5B 45 4C 53 45 5D 00 2E 44 +96 44 4A 44 66 44 1E 40 04 5B 49 46 5D 00 2E 44 +68 44 B2 40 66 44 1E 40 05 0D 6B 6F 20 0A 08 44 +9A 40 84 40 B2 40 68 44 56 44 0D 5B 54 48 45 4E +5D 00 30 4D BA 44 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D C6 44 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 2A 44 7C 46 E4 46 88 48 F8 45 D6 44 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +2A 44 7C 46 E4 46 08 45 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D B0 42 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +D8 41 05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 40 +1E 40 E6 48 0A 40 22 00 7C 46 7C 45 B2 40 20 00 +C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D +92 43 05 2E 22 00 0D 12 84 12 66 45 0A 40 08 44 +E6 48 F8 45 00 00 04 3C 23 00 B2 40 B2 1D B2 1D +30 4D 62 45 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 +46 40 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 +30 4D B4 45 04 23 53 00 0D 12 84 12 B6 45 F0 45 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D E4 45 04 23 +3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F FE 45 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 82 43 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 AA 45 2A 44 18 46 E8 45 14 45 +26 46 02 46 08 44 F8 45 92 45 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D +1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D 6A 46 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 +8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D +0C 4E 0E 43 1E 15 3D 40 EE 47 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 F0 47 +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 +0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 40 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D A6 45 03 5C +92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 40 2A 44 +7C 46 B0 40 C0 49 E4 46 AA 48 0A 4E 3E 4F 3D 40 +C4 48 6D 27 3D 40 9E 48 1A E2 BC 1D 14 24 0E 12 +3E 4F 30 41 C6 48 3E 4F 3D 40 9E 48 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 9C 4A +2A 3C 8E 48 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E +FE FF 3E 4F 30 4D E4 48 0F 4C 49 54 45 52 41 4C +82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D +BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D 20 46 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D 46 45 0A 41 4C 4C 4F 54 82 5E C8 1D +3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 40 02 0D +0A 00 08 44 94 40 98 48 26 45 50 45 1E 40 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 41 32 40 0A 40 +40 FF 58 45 1E 40 09 46 52 41 4D 20 66 75 6C 6C +08 41 B2 40 5C 49 46 49 0D 41 42 4F 52 54 22 00 +0D 12 84 12 66 45 0A 40 08 41 E6 48 F8 45 76 46 +02 27 0D 12 84 12 2A 44 7C 46 E4 46 B0 40 C2 49 +8A 45 CE 48 F0 44 07 5B 27 5D 0D 12 84 12 B2 49 +0A 40 0A 40 E6 48 E6 48 F8 45 C6 49 03 5B 82 43 +BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D 3E 45 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 2A 44 +7C 46 E4 46 B0 40 C2 49 50 45 AC 40 1A 4A 0A 40 +0A 40 E6 48 E6 48 0A 40 E6 48 E6 48 F8 45 00 00 +02 3A 30 12 70 4A 92 B3 C8 1D A2 63 C8 1D 0D 12 +84 12 2A 44 7C 46 38 4A 3D 41 5A D3 5A 53 0A 5E +19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D +82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D +30 4D 82 9F BA 1D 66 25 84 12 1E 40 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 41 DC 49 +03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 40 F8 45 +E6 48 82 4A DE 49 F8 45 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D 30 49 +0C 43 52 45 41 54 45 00 B0 12 26 4A BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D 02 44 0A 44 4F 45 53 3E +1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D 20 4A 0E 3A 4E 4F 4E 41 4D 45 30 12 70 4A +2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F BA 4A 05 49 53 00 0D 12 +82 93 BC 1D 08 20 84 12 B2 49 3C 4B 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 CA 49 0A 40 3E 4B E6 48 +F8 45 D0 4A 08 43 4F 44 45 00 B0 12 26 4A A2 82 +C8 1D 61 3C 12 46 0E 48 44 4E 43 4F 44 45 B2 40 +2A 4C CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 82 4A 88 4B 3D 41 92 42 D0 1D CC 1D +5D 3C 54 4B 0E 43 4F 44 45 4E 4E 4D 30 12 5E 4B +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 +BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D +1A 42 C8 1D EF 3F 66 4B 0B 48 49 32 4C 4F A2 53 +C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F +F2 4B B2 40 04 4C D0 1D 82 4E CE 1D 30 40 8A 45 +85 12 F0 4B F0 49 64 58 60 5A 72 58 FA 5D 34 46 +DE 46 DA 5C D8 4B 2A 4B 04 4B A0 4A 80 58 0C 4D +44 5A 00 00 00 00 85 12 F0 4B 86 53 0A 52 2C 54 +32 51 8E 51 DC 51 B8 52 72 54 54 50 78 51 00 00 +00 00 C6 4B 44 4F 00 00 E0 52 24 4C B2 40 04 4C +CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 1D 3A 40 42 18 B0 12 58 4C 30 4D +6A 4C 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 1D B0 12 58 4C 1A 42 CA 1D 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +08 42 FE FF 29 83 B9 40 F2 41 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 F0 FF 3B 40 10 00 3A 40 +3A 18 B0 12 5C 4C 82 43 4A 18 C7 3F FE 4C B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F E6 49 0C 4D 41 52 +4B 45 52 00 12 12 C6 1D 0D 12 84 12 2A 44 7C 46 +E4 46 AC 40 2A 4D 1E 45 BE 48 2C 4D 3E 4F 3D 41 +B2 41 C6 1D B0 12 26 4A BA 40 85 12 FC FF BA 40 +FC 4C FE FF 28 83 8A 48 00 00 BA 40 82 40 02 00 +A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 1D 84 12 7C 46 E4 46 +AC 40 96 4D 76 4D 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 FC 4C 00 00 01 20 3E 52 +2E 83 21 53 30 41 8E 47 AC 40 9E 4D 92 4D A0 4D +B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E +3D 15 B0 12 66 4D 15 20 3E 40 2B 00 B0 12 66 4D +06 20 3E 40 2D 00 B0 12 66 4D 92 83 C6 1D 0E 12 +1E 41 02 00 84 12 7C 46 8E 47 AC 40 C2 49 E0 4D +3E 51 3A 17 30 41 B0 12 A6 4D 19 42 C8 1D 89 4E +00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 +C6 1D 3D 15 84 12 7C 46 8E 47 AC 40 18 4E 10 4E +3E 90 10 00 E6 2B 7C 2D 1A 4E A2 41 C6 1D E1 3F +03 20 B0 12 FE 4D 43 3C 7A 90 23 00 24 20 B0 12 +AE 4D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 +10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 +08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 AE 4D F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 FA 4D 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +FE 4D 92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 E6 4D F2 3F 03 20 +B0 12 FE 4D F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 E6 4D EA 3F 0C 43 1B 42 +C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 +C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 +C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A 40 00 13 E6 48 F8 45 0A 40 2C 00 +DC 4E 20 4E 2A 44 E6 4E BE 4E 2C 4F 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 1C 4F +00 40 38 4F 0A 4D 4F 56 2E 42 85 12 1C 4F 40 40 +00 00 06 41 44 44 85 12 1C 4F 00 50 52 4F 0A 41 +44 44 2E 42 85 12 1C 4F 40 50 5E 4F 08 41 44 44 +43 00 85 12 1C 4F 00 60 6C 4F 0C 41 44 44 43 2E +42 00 85 12 1C 4F 40 60 A4 4B 08 53 55 42 43 00 +85 12 1C 4F 00 70 8A 4F 0C 53 55 42 43 2E 42 00 +85 12 1C 4F 40 70 98 4F 06 53 55 42 85 12 1C 4F +00 80 A8 4F 0A 53 55 42 2E 42 85 12 1C 4F 40 80 +B4 4F 06 43 4D 50 85 12 1C 4F 00 90 C2 4F 0A 43 +4D 50 2E 42 85 12 1C 4F 40 90 00 00 08 44 41 44 +44 00 85 12 1C 4F 00 A0 DC 4F 0C 44 41 44 44 2E +42 00 85 12 1C 4F 40 A0 0A 4F 06 42 49 54 85 12 +1C 4F 00 B0 FA 4F 0A 42 49 54 2E 42 85 12 1C 4F +40 B0 06 50 06 42 49 43 85 12 1C 4F 00 C0 14 50 +0A 42 49 43 2E 42 85 12 1C 4F 40 C0 20 50 06 42 +49 53 85 12 1C 4F 00 D0 2E 50 0A 42 49 53 2E 42 +85 12 1C 4F 40 D0 00 00 06 58 4F 52 85 12 1C 4F +00 E0 48 50 0A 58 4F 52 2E 42 85 12 1C 4F 40 E0 +7A 4F 06 41 4E 44 85 12 1C 4F 00 F0 62 50 0A 41 +4E 44 2E 42 85 12 1C 4F 40 F0 2A 44 DC 4E 20 4E +82 50 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F 3A 50 06 52 52 43 85 12 7A 50 00 10 94 50 +0A 52 52 43 2E 42 85 12 7A 50 40 10 CE 4F 08 53 +57 50 42 00 85 12 7A 50 80 10 A0 50 06 52 52 41 +85 12 7A 50 00 11 BC 50 0A 52 52 41 2E 42 85 12 +7A 50 40 11 AE 50 06 53 58 54 85 12 7A 50 80 11 +00 00 08 50 55 53 48 00 85 12 7A 50 00 12 E2 50 +0C 50 55 53 48 2E 42 00 85 12 7A 50 40 12 D6 50 +08 43 41 4C 4C 00 85 12 7A 50 80 12 1A 53 0E 4A +84 12 6C 46 1E 40 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 41 00 51 06 53 3E 3D 86 12 00 38 +28 51 04 53 3C 00 86 12 00 34 F0 50 06 30 3E 3D +86 12 00 30 3C 51 04 30 3C 00 86 12 00 30 78 4B +04 55 3C 00 86 12 00 2C 50 51 06 55 3E 3D 86 12 +00 28 46 51 06 30 3C 3E 86 12 00 24 64 51 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D +8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D EA 4F 08 54 +48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +5A 51 08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C +00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F C8 50 +0A 42 45 47 49 4E 30 40 32 40 B2 51 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 1D 30 4D 6E 50 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 7C 51 12 45 F8 45 D0 51 0C 52 45 50 +45 41 54 00 0D 12 84 12 10 52 94 51 F8 45 40 52 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 +C8 1D 00 00 30 4D 2C 52 06 42 57 31 85 12 3E 52 +00 00 58 52 06 42 57 32 85 12 3E 52 00 00 64 52 +06 42 57 33 85 12 3E 52 00 00 7C 52 3D 41 1A 42 +C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F +00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 7A 52 00 00 A0 52 06 46 57 32 +85 12 7A 52 00 00 AC 52 06 46 57 33 85 12 7A 52 +00 00 1A 52 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 B2 49 BE 48 F8 45 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F E6 4E 0A 40 +2C 00 7C 46 8E 47 AC 40 C2 49 2A 44 DC 4E BE 4E +12 53 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E 70 52 +08 52 52 43 4D 00 85 12 FC 52 50 00 40 53 08 52 +52 41 4D 00 85 12 FC 52 50 01 4E 53 08 52 4C 41 +4D 00 85 12 FC 52 50 02 5C 53 08 52 52 55 4D 00 +85 12 FC 52 50 03 6E 51 0A 50 55 53 48 4D 85 12 +FC 52 00 15 78 53 08 50 4F 50 4D 00 85 12 FC 52 +00 17 D2 C3 23 02 E2 B2 60 02 02 24 30 40 F2 41 +1A 52 04 20 19 62 06 20 92 43 14 20 C2 4A 15 20 +8A 10 C2 4A 16 20 C2 49 17 20 89 10 C2 49 18 20 +B0 12 06 54 5A 53 FC 23 39 40 05 00 D2 49 14 20 +4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 +4C 06 59 83 F3 2F 19 83 0B 30 F2 43 4E 06 82 93 +46 06 03 24 92 B3 6C 06 FD 27 5A 92 4C 06 F3 23 +30 41 1A 43 E1 3F 19 43 3A 43 8A 10 C2 4A 4E 06 +82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 +19 83 F3 23 5A 42 4C 06 30 41 6A 53 12 52 5F 53 +45 43 54 5F 57 58 1C D3 F2 40 51 00 19 20 B0 12 +92 53 38 20 B0 12 06 54 6A 53 04 24 FB 23 D9 42 +4C 06 FF 1D F2 43 4E 06 03 43 19 53 39 90 01 02 +F6 23 F2 43 4E 06 3C C0 03 00 D2 D3 23 02 30 41 +C4 52 12 57 5F 53 45 43 54 5F 57 58 2C D3 F0 40 +58 00 97 CB B0 12 92 53 15 20 3A 40 FE FF 29 43 +B0 12 0A 54 D2 49 00 1E 4E 06 03 43 19 53 39 90 +00 02 F8 23 39 40 03 00 B0 12 08 54 7A C0 E1 00 +6A 82 D9 27 8C 10 1C 52 4C 06 D2 D3 23 02 84 12 +88 43 1E 40 0B 3C 20 53 44 20 45 72 72 6F 72 21 +D2 54 2F 83 8F 4E 00 00 B2 40 10 00 BE 1D 0E 4C +84 12 38 46 12 41 B0 12 54 41 E2 B2 60 02 8A 20 +B2 40 81 A9 40 06 B2 40 18 00 46 06 D2 D3 25 02 +B2 D0 C0 04 0C 02 92 C3 40 06 39 40 6E 01 29 83 +89 43 02 20 FC 23 39 42 B0 12 08 54 D2 C3 23 02 +2C 42 B2 40 95 00 14 20 B2 40 00 40 18 20 B0 12 +02 54 02 24 30 40 B4 54 B0 12 06 54 7A 93 FC 23 +B2 40 87 AA 14 20 92 43 16 20 B2 40 00 48 18 20 +B0 12 02 54 29 42 B0 12 08 54 92 43 14 20 82 43 +16 20 78 43 3C 42 B2 40 00 77 18 20 B0 12 02 54 +B2 40 40 69 18 20 B0 12 C0 53 03 24 58 83 F3 23 +D9 3F 0C 5C A2 43 16 20 B2 40 00 50 18 20 B0 12 +C0 53 D0 23 92 D3 40 06 82 43 46 06 92 C3 40 06 +0A 43 09 43 B0 12 36 54 38 40 00 1E 92 48 C6 01 +04 20 92 48 C8 01 06 20 5C 48 C2 01 7C 80 0C 00 +08 24 5C 53 06 24 6C 52 04 24 3C 50 07 20 30 40 +BA 54 09 43 B0 12 36 54 A2 43 2C 20 19 48 0E 00 +82 49 08 20 1A 48 24 00 82 4A 0A 20 09 5A 82 49 +0C 20 09 5A 58 48 0D 00 82 48 12 20 09 88 09 88 +82 49 10 20 30 41 82 43 32 20 30 40 84 41 92 4B +0E 00 22 20 92 4B 10 00 24 20 5A 42 23 20 58 42 +22 20 59 42 24 20 89 10 0A D9 88 10 08 58 0A 6A +88 10 08 58 30 41 1A 52 08 20 09 43 FC 3E 92 42 +22 20 D0 04 92 42 24 20 D2 04 92 42 12 20 C8 04 +92 42 E4 04 1A 20 92 42 E6 04 1C 20 92 52 10 20 +1A 20 82 63 1C 20 30 41 92 4B 0E 00 22 20 92 4B +10 00 24 20 B0 12 3E 56 5A 4B 03 00 82 5A 1A 20 +82 63 1C 20 30 41 3C 42 3B 40 38 20 09 43 CB 93 +02 00 10 24 9B 92 24 20 0C 00 04 20 9B 92 22 20 +0A 00 A3 25 09 4B 3B 50 1C 00 3B 90 18 21 EF 23 +0C 5C 9B 3D 0C 43 82 4B 32 20 8B 49 00 00 09 93 +0A 24 99 52 C6 1D 16 00 4A 93 05 34 C9 93 02 00 +02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00 9B 42 +1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20 8B 48 +08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 +1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E 12 00 +9B 48 1E 1E 14 00 82 43 1E 20 6A 93 1A 24 A4 37 +8B 43 16 00 7A 93 02 24 07 38 35 3C B2 40 1C 21 +A0 40 B2 40 A2 43 BA 42 9B 42 C2 1D 18 00 9B 82 +C6 1D 18 00 9B 42 C4 1D 1A 00 9B 52 C6 1D 1A 00 +22 3C 30 41 1B 42 32 20 82 43 1E 20 B2 90 00 02 +20 20 3F 20 BB 80 00 02 12 00 8B 73 14 00 DB 53 +03 00 DB 92 12 20 03 00 0E 28 CB 43 03 00 B0 12 +0E 56 B0 12 36 56 8B 43 10 00 9B 48 00 1E 0E 00 +9B 48 02 1E 10 00 B2 40 00 02 20 20 8B 93 14 00 +0B 20 92 9B 12 00 1E 20 1C 2C BB 90 00 02 12 00 +03 2C 92 4B 12 00 20 20 B0 12 68 56 1A 42 1A 20 +19 42 1C 20 38 3E CB 43 02 00 2B 4B 82 4B 32 20 +0B 93 06 24 92 4B 16 00 1E 20 B0 12 96 57 22 C3 +30 41 1B 42 32 20 0B 93 FB 27 EB 92 02 00 04 20 +B0 12 54 5B B0 12 44 5C CB 93 02 00 E4 37 1E 4B +18 00 9F 4B 1A 00 00 00 31 50 06 00 3D 41 B0 12 +C6 57 02 24 30 40 9A 43 B2 40 3C 1D A0 40 B2 40 +BC 42 BA 42 30 40 88 43 09 93 07 24 F8 90 20 00 +00 1E 03 20 18 53 19 83 F9 23 30 41 82 4C 0B 52 +45 41 44 22 5A 43 20 3C EA 4A 09 44 45 4C 22 00 +6A 43 1A 3C B0 49 0D 57 52 49 54 45 22 00 6A 42 +13 3C 98 49 0F 41 50 50 45 4E 44 22 7A 42 0C 3C +94 4B 0A 43 4C 4F 53 45 B0 12 E2 57 30 4D F8 48 +0B 4C 4F 41 44 22 7A 43 2F 83 8F 4E 00 00 0E 4A +82 93 BC 1D 0B 24 0D 12 84 12 0A 40 0A 40 E6 48 +E6 48 66 45 0A 40 BC 58 E6 48 F8 45 0D 12 84 12 +0A 40 22 00 7C 46 36 49 BA 58 3D 41 36 4F 0E 56 +82 4E 36 20 A2 43 22 20 82 43 24 20 1C 43 0E 96 +8C 24 F6 90 3A 00 01 00 01 20 26 53 F6 90 5C 00 +00 00 03 20 16 53 0E 96 66 24 82 46 34 20 B0 12 +3E 56 15 42 12 20 B0 12 BC 57 2C 43 0A 43 08 4A +58 0E 08 58 82 48 30 20 C8 93 00 1E 60 24 39 42 +F8 96 00 1E 04 20 18 53 19 83 FA 23 16 53 F6 90 +2E 00 FF FF 19 24 39 50 03 00 B0 12 28 58 06 20 +F6 90 5C 00 FF FF 29 24 0E 96 27 28 16 42 34 20 +1A 53 3A 90 10 00 DB 23 92 53 1A 20 82 63 1C 20 +15 83 D1 23 2C 42 49 3C F6 90 2E 00 FE FF EE 27 +B0 12 28 58 EB 23 39 40 03 00 F8 96 00 1E 04 20 +18 53 19 83 FA 23 09 3C 0E 96 E0 2F F6 90 5C 00 +FF FF DC 23 B0 12 28 58 D9 23 18 42 30 20 92 48 +1A 1E 22 20 92 48 14 1E 24 20 F8 B0 10 00 0B 1E +13 24 82 93 24 20 05 20 82 93 22 20 02 20 A2 43 +22 20 0E 96 9A 23 92 42 22 20 2C 20 92 42 24 20 +2E 20 8F 43 00 00 03 3C 2A 4F B0 12 86 56 35 40 +B6 40 36 40 C4 40 3A 4F 3E 4F 0A 93 04 24 7A 93 +39 20 0C 93 02 20 30 40 9A 43 0D 12 84 12 88 43 +1E 40 0B 3C 20 4F 70 65 6E 45 72 72 6F 72 B2 40 +D0 54 E2 B2 60 02 02 24 30 40 86 41 92 12 3E 18 +3F 40 7E 1C 8F 43 00 00 0D 12 84 12 1E 40 0F 4C +4F 41 44 22 20 42 4F 4F 54 2E 34 54 48 22 B2 40 +66 49 3E 58 08 42 4F 4F 54 00 B2 40 02 5A AC 42 +30 4D 36 47 0C 4E 4F 42 4F 4F 54 00 B2 40 86 41 +AC 42 30 4D 1A 93 89 20 0C 93 C7 23 30 4D 34 5A +08 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 32 20 +B0 12 54 57 1E 82 32 20 30 4D 08 4A 1A 52 08 20 +B0 12 8A 5A 0A 48 1A 52 0C 20 09 43 30 40 7C 54 +3C 42 0A 12 2A 41 82 9A 0A 20 2B 25 B0 12 36 56 +88 93 02 1E 03 20 88 93 00 1E 08 24 28 52 38 90 +00 02 F6 2B 91 53 00 00 08 43 EC 3F A2 41 26 20 +82 48 28 20 0C 43 B8 43 00 1E 6A 41 B8 40 FF 0F +02 1E 08 11 8A 10 08 5A 5A 41 01 00 0A 11 08 10 +82 4A 24 20 82 48 22 20 2A 41 B0 12 7A 5A 3A 41 +30 41 90 4B 0A 00 2C C5 90 4B 0C 00 28 C5 B0 12 +1A 56 82 4A 26 20 82 48 28 20 0A 12 B0 12 36 56 +1A 48 00 1E 88 43 00 1E 19 48 02 1E 88 43 02 1E +39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 10 24 82 4A +22 20 82 49 24 20 B0 12 1A 56 2A 91 E9 27 09 4A +2A 41 81 49 00 00 B0 12 7A 5A 2A 41 DF 3F 3A 41 +30 40 7A 5A 9B 52 1E 20 12 00 8B 63 14 00 1A 42 +1A 20 19 42 1C 20 30 40 7C 54 2A 93 BC 20 0C 93 +09 20 F8 40 E5 00 00 1E B0 12 5E 5B B0 12 F2 5A +B0 12 E2 57 30 4D F2 B0 40 00 A2 04 29 20 F2 B0 +10 00 A2 04 FC 27 5A 42 B0 04 4A 11 59 42 B4 04 +F2 40 20 00 C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 +D2 42 B5 04 C8 04 19 52 E4 04 D2 42 B2 04 C0 04 +B2 40 00 08 C8 04 1A 52 E4 04 92 42 B6 04 C0 04 +B2 80 BC 07 C0 04 B2 40 00 02 C8 04 19 52 E4 04 +30 41 22 2A 2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D +7C 2E 29 92 06 28 39 80 03 00 B0 12 32 5C 39 40 +03 00 7A 4B C8 4A 00 1E 82 9B 36 20 12 28 0D 12 +3D 40 0F 00 3C 40 E2 5B 7A 9C F3 27 1D 83 FC 23 +3D 41 6A 9C E6 27 3A 80 21 00 EB 3B 18 53 19 83 +E8 23 09 93 06 24 F8 40 20 00 00 1E 18 53 19 83 +FA 23 30 41 1A 4B 04 00 19 4B 06 00 B0 12 36 54 +18 4B 08 00 B0 12 86 5B 88 49 12 1E 88 4A 16 1E +88 49 18 1E 98 4B 12 00 1C 1E 98 4B 14 00 1E 1E +1A 4B 04 00 19 4B 06 00 30 40 7C 54 B2 40 00 02 +1E 20 1B 42 32 20 B0 12 54 5B 82 43 1E 20 DB 53 +03 00 DB 92 12 20 03 00 1D 28 B0 12 0E 56 08 12 +0A 12 B0 12 90 5A 2A 91 03 24 2A 41 B0 12 36 56 +3A 41 38 41 98 42 22 20 00 1E 98 42 24 20 02 1E +B0 12 7A 5A AB 42 02 00 9B 42 22 20 0E 00 9B 42 +24 20 10 00 30 40 74 56 56 58 0A 57 52 49 54 45 +B0 12 7C 5C 30 4D 2A 92 54 20 2C 93 0E 24 0C 93 +3D 24 0D 12 84 12 1E 40 0C 3C 20 57 72 69 74 65 +45 72 72 6F 72 00 B2 40 D0 54 0A 43 08 43 B0 12 +90 5A B0 12 BC 57 18 42 30 20 F8 40 20 00 0B 1E +B0 12 86 5B 88 43 0C 1E 88 4A 0E 1E 88 49 10 1E +98 42 24 20 14 1E 98 42 22 20 1A 1E 88 43 1C 1E +88 43 1E 1E 2C 42 1B 42 34 20 82 9B 36 20 D1 27 +FB 90 2E 00 00 00 CD 27 39 40 0B 00 B0 12 02 5C +B0 12 5E 5B 2A 42 B0 12 86 56 30 4D B0 12 F2 5A +8B 43 12 00 8B 43 14 00 90 4B 0A 00 A6 C2 90 4B +0C 00 A2 C2 B0 12 1A 56 B0 12 90 5A B0 12 C4 5C +30 4D 2C 93 BA 27 0C 93 AC 23 EB 42 02 00 58 4B +13 00 59 4B 14 00 89 10 09 58 58 4B 15 00 5B 42 +12 20 0A 43 3C 42 08 11 09 10 4A 10 1C 83 0B 11 +FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 19 5B 0A 00 +18 6B 0C 00 8B 49 0E 00 8B 48 10 00 CB 4A 03 00 +B0 12 B8 57 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 +FF 01 82 4A 1E 20 30 4D 4A 58 10 54 45 52 4D 32 +53 44 22 00 0D 12 84 12 5E 58 0C 5E 0A 43 B0 12 +46 43 92 B3 DC 05 FD 27 59 42 CC 05 C2 49 CE 05 +69 92 0D 24 CA 49 00 1E 1A 53 3A 90 FF 01 04 24 +F0 2B B0 12 7C 5C EA 3F B0 12 E2 42 EA 3F F2 90 +0D 00 CC 05 FC 27 B0 12 E2 42 F2 90 0A 00 CC 05 +FC 27 82 4A 1E 20 B0 12 E2 57 3D 41 30 4D +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 +D6 42 F2 41 F2 41 F2 41 F2 41 F2 41 F2 41 08 42 +q diff --git a/binaries/MSP_EXP430FR5994_8MHz_I2C.txt b/binaries/MSP_EXP430FR5994_8MHz_I2C.txt index e362bd2..0380c4c 100644 --- a/binaries/MSP_EXP430FR5994_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR5994_8MHz_I2C.txt @@ -1,656 +1,502 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF 00 68 3E 4D 34 01 -10 00 C1 87 B6 41 4C 5F B8 41 0A 5E 84 42 00 68 -3E 4D 72 42 E0 43 00 43 DC 42 3C 1D AE 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +D0 42 56 41 E2 55 C2 54 44 41 40 5E 26 4C E0 4B +E0 4B BE 42 42 43 1A 43 3C 1D E0 1C D4 45 B6 40 +C4 40 F0 44 20 00 0A 00 00 1C 56 41 E2 55 C2 54 +44 41 40 5E 26 4C E0 4B E0 4B 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4000 -B0 12 B8 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CD 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 4C 5F 39 40 22 18 -B2 49 70 42 B2 49 DE 43 B2 49 FE 42 B2 49 DA 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 46 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 41 0E 12 B0 12 -F8 40 0A 40 DE 1D 2E 44 18 43 EE 40 34 40 8A 41 -14 40 05 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 F6 43 34 40 7E 41 14 40 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 AA 43 EE 44 AA 43 -14 40 04 1B 5B 30 6D 00 AA 43 76 48 2E 93 13 28 -B2 D0 C0 07 C0 06 18 42 02 18 08 11 38 D0 00 04 -82 48 D4 06 F2 D0 03 00 6A 02 92 C3 C0 06 A2 D2 -EA 06 92 C3 30 01 30 41 48 43 A2 B3 EC 06 FD 27 -C2 48 CE 06 A2 B2 EC 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 CE 41 04 57 41 52 4D 00 -B0 12 0A 5E 78 40 03 00 B0 12 BA 41 84 12 14 40 -07 0D 0A 1B 5B 37 6D 40 AA 43 0A 40 02 18 2E 44 -24 45 0A 40 23 00 FC 42 24 45 14 40 19 46 61 73 -74 46 6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F -6F 72 65 6E 73 20 AA 43 0A 40 40 FF 28 40 22 44 -EE 44 14 40 0A 62 79 74 65 73 20 66 72 65 65 00 -3A 40 7E 41 00 00 06 41 43 43 45 50 54 00 30 40 -72 42 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 -3D 15 BE 3E 21 52 A2 C2 EC 06 B2 B0 10 00 C0 06 -B7 22 3A 17 92 B3 EC 06 FD 27 58 42 CC 06 48 9B -0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 -F1 3F 0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F -B0 12 C4 41 82 93 DE 1D 02 24 92 53 DE 1D 08 4C -19 3C 00 00 03 4B 45 59 30 40 DC 42 2F 83 8F 4E -00 00 58 43 B0 12 BA 41 92 B3 EC 06 FD 27 1E 42 -CC 06 30 4D 00 00 04 45 4D 49 54 00 30 40 00 43 -08 4E 3E 4F A2 B3 EC 06 FD 27 C2 48 CE 06 30 4D -F6 42 04 45 43 48 4F 00 B2 40 C2 48 0A 43 82 43 -DE 1D 38 40 05 00 B0 12 BA 41 30 4D 00 00 06 4E -4F 45 43 48 4F 00 B2 40 30 4D 0A 43 92 43 DE 1D -28 42 F1 3F 0D 12 3D 40 64 43 1B 42 32 20 9B 42 -1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 1B 42 -20 20 02 3C 66 43 2D 83 0C 9B 16 2C 58 4C 00 1E -1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 3D 41 -82 4C 1E 20 3C 40 20 00 9D 3F 0E 99 BB 27 CA 48 -00 00 1A 53 1E 53 B6 3F 1A 15 B0 12 02 60 19 17 -DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 C6 43 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FE 42 C8 43 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 41 02 43 52 00 30 40 E0 43 -0D 12 84 12 14 40 02 0D 0A 00 AA 43 AE 44 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 66 42 01 40 2E 4E -30 4D 2C 44 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D D8 43 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 68 44 02 23 53 00 0D 12 84 12 -6A 44 A4 44 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 98 44 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D A4 43 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 5E 44 -9C 44 EE 40 DC 44 B8 44 AA 43 62 48 FC 42 AE 44 -2E 43 01 2E 0E 93 E3 37 38 43 E2 3F D6 44 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 A8 47 -0A 40 22 00 7A 45 48 45 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D 22 45 -82 2E 22 00 0D 12 84 12 32 45 0A 40 AA 43 A8 47 -AE 44 FA 41 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 FC 46 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F FE 46 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D A6 47 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -B4 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D C8 44 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 40 62 48 7A 45 1E 48 9C 26 -3D 40 26 48 DE 3E 28 48 0A 4E 3E 4F 3D 40 42 48 -36 27 3D 40 18 48 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 44 48 3E 4F 3D 40 18 48 BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 E4 49 CC 3F -4C 48 86 12 20 00 34 44 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 DC 43 BC 40 -12 48 12 44 44 44 14 40 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 4C 44 -14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 41 -3A 40 8C 48 68 48 86 41 42 4F 52 54 22 00 0D 12 -84 12 32 45 0A 40 2A 41 A8 47 AE 44 DC 45 01 27 -0D 12 84 12 62 48 7A 45 E2 45 34 40 60 48 AE 44 -00 00 83 5B 27 5D 0D 12 84 12 E0 48 0A 40 0A 40 -A8 47 A8 47 AE 44 F2 48 81 5B 82 43 BE 1D 30 4D -5A 44 01 5D B2 43 BE 1D 30 4D 12 49 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 62 48 7A 45 E2 45 F6 43 34 40 -60 48 44 44 34 40 54 49 0A 40 0A 40 A8 47 A8 47 -0A 40 A8 47 A8 47 AE 44 08 49 01 3A 30 12 A4 49 -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 62 48 7A 45 -72 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 41 5A 49 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 40 AE 44 A8 47 B6 49 0A 49 AE 44 -08 48 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D F2 47 06 43 52 45 41 54 -45 00 B0 12 60 49 BA 40 86 12 FC FF 8A 4A FE FF -C9 3F E8 49 07 3A 4E 4F 4E 41 4D 45 30 12 A4 49 -2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 0E 4A -39 40 10 02 08 49 28 53 99 3F 12 43 05 44 45 46 -45 52 B0 12 60 49 BA 40 30 40 FC FF BA 40 E2 4D -FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 02 4A 82 49 -53 00 0D 12 82 93 BE 1D 06 24 84 12 F6 48 0A 40 -74 4A A8 47 AE 44 84 12 E0 48 74 4A AE 44 1A 4A -04 43 4F 44 45 00 B0 12 60 49 A2 82 C6 1D 82 43 -62 5C 0D 12 84 12 48 4D 1A 4D AE 44 7E 4A 07 48 -44 4E 43 4F 44 45 B2 40 1E 4D DA 1D EC 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 B6 49 6E 4D -A2 4D AE 44 A0 4A 07 43 4F 44 45 4E 4E 4D 30 12 -AA 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 6E 4D A2 4D AE 44 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -BE 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 82 4C -A8 47 0A 49 AE 4A AE 44 34 4A 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 4A 4B 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 40 00 00 26 44 62 48 7A 45 F8 47 -EE 43 34 40 E2 4B FC 43 14 40 06 5B 54 48 45 4E -5D 00 54 4B BC 4B 78 4B 9A 4B AE 44 FC 43 14 40 -06 5B 45 4C 53 45 5D 00 54 4B D2 4B 78 4B 98 4B -AE 44 14 40 04 5B 49 46 5D 00 54 4B 9A 4B 3A 40 -98 4B D0 43 14 40 05 0D 0A 6B 6F 20 AA 43 BC 40 -AC 40 3A 40 9A 4B 88 4B 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D F8 4B 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 62 48 7A 45 E2 45 -06 4C AE 44 0C 4C 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 16 4C 3E 44 AE 44 3E 4C B2 4E -0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C BA 47 -06 4D 41 52 4B 45 52 00 B0 12 60 49 BA 40 85 12 -FC FF BA 40 3C 4C FE FF 28 83 8A 48 00 00 9A 42 -C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 C6 1D -9D 3E 2E 53 30 4D 5C 4A 05 44 4F 45 53 3E 1A 42 -BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D -74 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 0D 12 -84 12 22 4A 0A 40 10 00 0A 40 00 00 3E 40 0A 40 -00 00 A8 47 60 40 BE 4C 28 40 0A 40 C8 1D EE 43 -2E 44 A8 47 36 44 8E 4C 0A 40 CA 1D 36 44 AE 44 -DE 48 05 46 4F 52 54 48 85 12 D8 4C 42 4D 96 63 -CA 61 E2 4C 32 4B D4 42 E4 61 88 4D 14 4E EC 63 -94 67 B0 66 00 00 88 63 1C 49 42 46 00 00 C6 48 -09 41 53 53 45 4D 42 4C 45 52 85 12 D8 4C 2E 5B -C6 5A 2A 5A EA 54 7C 53 00 00 F2 58 00 00 52 5C -4E 5D E0 53 94 5D FA 5A 00 00 00 00 C4 54 0C 4D -10 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 D6 1D -08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 FA 23 -30 4D 28 49 08 50 52 45 56 49 4F 55 53 00 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 60 45 04 4F 4E 4C 59 00 82 43 -CC 1D 30 4D 88 4C 0B 44 45 46 49 4E 49 54 49 4F -4E 53 92 42 CA 1D DA 1D 30 4D E8 4C 8E 4D A2 4D -B2 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 -10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 FC 2B -89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F -3D 41 30 4D 64 4D 09 50 57 52 5F 53 54 41 54 45 -85 12 AA 4D 3E 4D 00 68 2E 45 09 52 53 54 5F 53 -54 41 54 45 92 42 0A 18 F6 4D 92 42 0C 18 F4 4D -EF 3F E6 4D 08 50 57 52 5F 48 45 52 45 00 92 42 -C6 1D F6 4D 92 42 C8 1D F4 4D 30 4D FA 4D 08 52 -53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 92 42 -C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 DA 37 -0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF FC 23 -B9 40 96 4E FE FF 29 83 B9 40 E2 41 FE FF 39 90 -AE FF F9 23 39 40 14 18 B2 49 E4 41 B2 49 FA 40 -B2 49 02 40 B2 49 02 42 B2 49 BC FF B2 49 0A 18 -B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 10 00 -00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 80 1C -39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 06 02 -B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 -42 02 B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 -26 03 F2 D3 22 03 F2 40 A5 00 61 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 F2 D0 10 00 2A 03 -F2 40 A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 -1E 42 08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 40 -00 42 38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 -7A 45 E2 45 3E 44 34 40 72 4F 9E 46 34 40 8C 4F -86 4F 74 4F 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 8E 4F B2 41 -C4 1D 3E 41 84 12 0A 40 2B 00 7A 45 E2 45 3E 44 -34 40 AA 4F 9E 46 34 40 60 48 08 44 7A 45 9E 46 -34 40 60 48 B6 4F 3E 5F E7 3F 32 B0 00 02 01 24 -3E 4F 30 41 3E 40 28 00 B0 12 56 4F B0 12 BA 4F -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 -1C 15 92 92 C0 1D C4 1D 02 20 30 40 CE 49 12 12 -C4 1D 92 53 C4 1D 84 12 7A 45 9E 46 34 40 0C 50 -02 50 21 53 3E 90 10 00 84 2D BE 2B 0E 50 B2 41 -C4 1D BA 3F 0D 12 84 12 62 48 32 4F 1E 50 0C 43 -1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 -29 20 92 53 C4 1D B0 12 56 4F B0 12 BA 4F 3C 40 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 07 3D 0E 93 3E 4F +B8 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BC 42 B2 49 +40 43 B2 49 18 43 B2 49 A0 40 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 9A 4C 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 41 B0 12 D0 40 FA 44 AC 40 +42 41 5A 43 1E 40 05 1B 5B 37 6D 40 E4 43 0A 40 +02 18 1C 45 48 46 E4 43 1E 40 04 1B 5B 30 6D 00 +E4 43 30 49 48 43 A2 B3 EC 06 FD 27 C2 48 CE 06 +A2 B2 EC 06 FD 27 30 41 B2 D0 C0 07 C0 06 18 42 +02 18 08 11 38 D0 00 04 82 48 D4 06 F2 D0 03 00 +6A 02 92 C3 C0 06 A2 D2 EA 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 5A 43 1E 40 07 0D 0A 1B 5B 37 +6D 40 E4 43 0A 40 02 18 1C 45 48 46 0A 40 23 00 +3E 43 48 46 1E 40 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +E4 43 0A 40 40 FF 32 40 10 45 14 46 1E 40 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 40 36 41 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 41 01 12 6D 3F 82 4E 08 18 92 12 3A 18 F2 B0 +40 00 40 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 +B2 D0 03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A +5C 01 31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 +FC FF 02 02 B2 43 26 02 B2 D3 22 02 B2 43 42 02 +B2 D3 46 02 B2 43 62 02 B2 D3 66 02 F2 43 26 03 +F2 D3 22 03 F2 40 A5 00 61 01 82 43 66 01 B2 40 +33 00 64 01 D2 43 61 01 39 40 40 00 18 42 00 18 +18 83 FE 23 19 83 FA 23 F2 D0 10 00 2A 03 F2 40 +A5 00 A1 04 F2 C0 40 00 A2 04 B2 42 B0 01 39 40 +00 10 29 83 89 43 00 1C FC 23 1E 42 08 18 82 43 +08 18 3E F3 02 20 1E 42 9E 01 B0 12 D0 40 80 41 +00 00 0C 41 43 43 45 50 54 00 30 40 BE 42 0A 4E +2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 98 3E +21 52 A2 C2 EC 06 B2 B0 10 00 C0 06 91 22 3A 17 +92 B3 EC 06 FD 27 58 42 CC 06 48 9B 0E 24 48 9C +06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A +EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C 1B 3C +00 00 06 4B 45 59 30 40 1A 43 58 43 B0 12 46 41 +2F 83 8F 4E 00 00 92 B3 EC 06 FD 27 1E 42 CC 06 +B0 12 44 41 30 4D 00 00 08 45 4D 49 54 00 30 40 +42 43 08 4E 3E 4F A2 B3 EC 06 FD 27 C2 48 CE 06 +30 4D 38 43 08 45 43 48 4F 00 B2 40 C2 48 4C 43 +38 40 05 00 B0 12 46 41 30 4D 00 00 0C 4E 4F 45 +43 48 4F 00 B2 40 30 4D 4C 43 28 42 F3 3F 0D 12 +3D 40 9E 43 1B 42 32 20 9B 42 1E 20 16 00 3A 4F +09 4E 0E 43 1C 42 1E 20 1B 42 20 20 02 3C A0 43 +2D 83 0C 9B 16 2C 58 4C 00 1E 1C 53 78 90 20 00 +09 2C 78 90 0A 00 F5 23 82 4C 1E 20 3D 41 3C 40 +20 00 A4 3F 0E 99 BF 27 CA 48 00 00 1A 53 1E 53 +BA 3F 1A 15 B0 12 30 57 19 17 DC 3F 00 00 08 54 +59 50 45 00 0D 12 3D 40 F4 43 29 4F 8F 4E 00 00 +7E 49 A5 3F F6 43 2D 83 2F 83 5E 83 F7 23 3D 41 +2F 53 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F +39 4F 3E 4F 4E 22 F9 98 00 00 4B 22 19 53 1C 83 +FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 42 22 9B 24 +12 43 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 40 +00 00 14 45 06 44 58 46 12 49 B0 40 82 44 14 40 +06 5B 54 48 45 4E 5D 00 0A 44 60 44 26 44 44 44 +14 40 06 5B 45 4C 53 45 5D 00 0A 44 72 44 26 44 +42 44 1E 40 04 5B 49 46 5D 00 0A 44 44 44 B2 40 +42 44 1E 40 05 0D 6B 6F 20 0A E4 43 9A 40 84 40 +B2 40 44 44 32 44 0D 5B 54 48 45 4E 5D 00 30 4D +96 44 09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D +A2 44 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +06 44 58 46 C0 46 64 48 D4 45 B2 44 17 5B 55 4E +44 45 46 49 4E 45 44 5D 0D 12 84 12 06 44 58 46 +C0 46 E4 44 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 +2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 +30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F +3E 8F 3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D +B2 42 02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E +3E E3 30 4D 3E 8F 01 28 0E F3 30 4D E0 41 05 53 +22 00 82 43 C0 1D 0D 12 84 12 0A 40 1E 40 C2 48 +0A 40 22 00 58 46 58 45 B2 40 20 00 C0 1D 1A 53 +1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 6C 43 05 2E +22 00 0D 12 84 12 42 45 0A 40 E4 43 C2 48 D4 45 +00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D 3E 45 +02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 40 BF 4F +00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 90 45 +04 23 53 00 0D 12 84 12 92 45 CC 45 2D 83 09 DE +09 93 E1 23 3D 41 30 4D C0 45 04 23 3E 00 9F 42 +B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +4F 4C 44 00 4A 4E 3E 4F DB 3F DA 45 08 53 49 47 +4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 54 43 +04 55 2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 +3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 +84 12 86 45 06 44 F4 45 C4 45 F0 44 02 46 DE 45 +E4 43 D4 45 6E 45 02 2E 0E 93 E4 37 3C 43 E3 3F +00 00 08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C +09 58 38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 +1B 42 C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 +01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C +09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F +4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D +0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 +2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C +01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF +0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C +FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 +0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D +46 46 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F +38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 +03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 +0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 +E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 +8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 +8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 +1E 15 3D 40 CA 47 7E 4C 6A 4C 7A 80 2D 00 16 24 +CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 +10 00 5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 +FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 +1E 83 FC 9C 00 00 E0 23 AE 27 CC 47 2F 24 2D 83 +6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 +00 02 7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 +8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 +03 28 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C +8F 49 00 00 0E 4B 2C 15 B0 12 3E 40 2A 17 E8 3F +9F 4F 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 +32 C0 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F +02 00 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 +02 00 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 +00 02 01 20 2F 53 30 4D 82 45 03 5C 92 42 C2 1D +C6 1D 30 4D 0D 12 84 12 84 40 06 44 58 46 B0 40 +9C 49 C0 46 86 48 0A 4E 3E 4F 3D 40 A0 48 6D 27 +3D 40 7A 48 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 +A2 48 3E 4F 3D 40 7A 48 19 20 DE 53 00 00 68 4E +08 5E F8 40 3F 00 00 00 3D 40 78 4A 2A 3C 6A 48 +02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F +30 4D C0 48 0F 4C 49 54 45 52 41 4C 82 93 BC 1D +0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A 40 +00 00 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 +03 24 8A 4E 02 00 EE 3F 30 4D FC 45 0A 43 4F 55 +4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D +22 45 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D +3F 40 80 1C 0E 43 84 12 1E 40 02 0D 0A 00 E4 43 +94 40 74 48 02 45 2C 45 1E 40 0B 73 74 61 63 6B +20 65 6D 70 74 79 08 41 32 40 0A 40 40 FF 34 45 +1E 40 09 46 52 41 4D 20 66 75 6C 6C 08 41 B2 40 +38 49 22 49 0D 41 42 4F 52 54 22 00 0D 12 84 12 +42 45 0A 40 08 41 C2 48 D4 45 52 46 02 27 0D 12 +84 12 06 44 58 46 C0 46 B0 40 9E 49 66 45 AA 48 +CC 44 07 5B 27 5D 0D 12 84 12 8E 49 0A 40 0A 40 +C2 48 C2 48 D4 45 A2 49 03 5B 82 43 BC 1D 30 4D +00 00 02 5D B2 43 BC 1D 30 4D 1A 45 11 50 4F 53 +54 50 4F 4E 45 00 0D 12 84 12 06 44 58 46 C0 46 +B0 40 9E 49 2C 45 AC 40 F6 49 0A 40 0A 40 C2 48 +C2 48 0A 40 C2 48 C2 48 D4 45 00 00 02 3A 30 12 +4C 4A 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 06 44 +58 46 14 4A 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D +08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F +E8 58 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D +82 4F BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 +FC FF BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F +BA 1D 66 25 84 12 1E 40 0F 73 74 61 63 6B 20 6D +69 73 6D 61 74 63 68 21 12 41 B8 49 03 3B 82 93 +BC 1D F4 26 0D 12 84 12 0A 40 D4 45 C2 48 5E 4A +BA 49 D4 45 00 00 12 49 4D 4D 45 44 49 41 54 45 +18 42 B4 1D D8 D3 00 00 30 4D 0C 49 0C 43 52 45 +41 54 45 00 B0 12 02 4A BA 40 86 12 FC FF 8A 4A +FE FF 3A 3D DE 43 0A 44 4F 45 53 3E 1A 42 B8 1D +BA 40 85 12 00 00 8A 4D 02 00 3D 41 30 4D FC 49 +0E 3A 4E 4F 4E 41 4D 45 30 12 4C 4A 2F 83 8F 4E +00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 +08 49 98 3F 96 4A 05 49 53 00 0D 12 82 93 BC 1D +08 20 84 12 8E 49 18 4B 3D 41 BE 4F 02 00 3E 4F +30 4D 84 12 A6 49 0A 40 1A 4B C2 48 D4 45 AC 4A +08 43 4F 44 45 00 B0 12 02 4A A2 82 C8 1D 61 3C +EE 45 0E 48 44 4E 43 4F 44 45 B2 40 06 4C CC 1D +F2 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +5E 4A 64 4B 3D 41 92 42 D0 1D CC 1D 5D 3C 30 4B +0E 43 4F 44 45 4E 4E 4D 30 12 3A 4B B7 3F 00 00 +0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 +BA 40 84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F +00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +EF 3F 42 4B 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F CE 4B B2 40 +E0 4B D0 1D 82 4E CE 1D 30 40 66 45 85 12 CC 4B +CC 49 40 58 3C 5A 4E 58 D6 5D 10 46 BA 46 B6 5C +B4 4B 06 4B E0 4A 7C 4A 5C 58 E8 4C 20 5A 00 00 +00 00 85 12 CC 4B 62 53 E6 51 08 54 0E 51 6A 51 +B8 51 94 52 4E 54 30 50 54 51 00 00 00 00 A2 4B +20 4F 00 00 BC 52 00 4C B2 40 E0 4B CE 1D 82 43 +D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 +FB 23 30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 +C8 1D 3A 40 42 18 B0 12 34 4C 30 4D 46 4C 0E 52 +53 54 5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D +B0 12 34 4C 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 +29 83 18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 +F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 +10 00 29 83 B9 43 80 FF FC 23 B9 40 10 42 FE FF +29 83 B9 40 FA 41 FE FF 39 90 AE FF F9 23 39 40 +10 18 B2 49 BC FF 3B 40 10 00 3A 40 3A 18 B0 12 +38 4C 82 43 4A 18 C7 3F DA 4C B2 4E 42 18 BE 12 +3E 4F 3D 41 C0 3F C2 49 0C 4D 41 52 4B 45 52 00 +12 12 C6 1D 0D 12 84 12 06 44 58 46 C0 46 AC 40 +06 4D FA 44 9A 48 08 4D 3E 4F 3D 41 B2 41 C6 1D +B0 12 02 4A BA 40 85 12 FC FF BA 40 D8 4C FE FF +28 83 8A 48 00 00 BA 40 82 40 02 00 A2 52 C8 1D +18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +30 4D 12 12 C6 1D 84 12 58 46 C0 46 AC 40 72 4D +52 4D 3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E +06 3C BE 90 D8 4C 00 00 01 20 3E 52 2E 83 21 53 +30 41 6A 47 AC 40 7A 4D 6E 4D 7C 4D B2 41 C6 1D +30 41 92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 +42 4D 15 20 3E 40 2B 00 B0 12 42 4D 06 20 3E 40 +2D 00 B0 12 42 4D 92 83 C6 1D 0E 12 1E 41 02 00 +84 12 58 46 6A 47 AC 40 9E 49 BC 4D 3E 51 3A 17 +30 41 B0 12 82 4D 19 42 C8 1D 89 4E 00 00 A2 53 +C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 +84 12 58 46 6A 47 AC 40 F4 4D EC 4D 3E 90 10 00 +E6 2B 7C 2D F6 4D A2 41 C6 1D E1 3F 03 20 B0 12 +DA 4D 43 3C 7A 90 23 00 24 20 B0 12 8A 4D 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 09 20 3C 40 10 02 92 53 -C4 1D B0 12 56 4F B0 12 BA 4F EB 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 1D B0 12 E0 4F 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 E0 4F 92 92 C0 1D -C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E D8 3F B0 12 -E0 4F FA 23 3C 50 10 00 B0 12 C4 4F EF 3F 0C 43 -1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 62 48 32 4F -F2 50 FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C5 3F B0 12 E0 4F E0 23 3C 50 80 00 B0 12 -C4 4F DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 40 00 13 A8 47 AE 44 0A 40 2C 00 14 50 E8 50 -32 51 09 4B 2E 4E 0E DC A0 3F 20 4B 03 4D 4F 56 -85 12 28 51 00 40 3C 51 05 4D 4F 56 2E 42 85 12 -28 51 40 40 00 00 03 41 44 44 85 12 28 51 00 50 -56 51 05 41 44 44 2E 42 85 12 28 51 40 50 62 51 -04 41 44 44 43 00 85 12 28 51 00 60 70 51 06 41 -44 44 43 2E 42 00 85 12 28 51 40 60 16 51 04 53 -55 42 43 00 85 12 28 51 00 70 8E 51 06 53 55 42 -43 2E 42 00 85 12 28 51 40 70 9C 51 03 53 55 42 -85 12 28 51 00 80 AC 51 05 53 55 42 2E 42 85 12 -28 51 40 80 F6 4A 03 43 4D 50 85 12 28 51 00 90 -C6 51 05 43 4D 50 2E 42 85 12 28 51 40 90 D0 4A -04 44 41 44 44 00 85 12 28 51 00 A0 E0 51 06 44 -41 44 44 2E 42 00 85 12 28 51 40 A0 D2 51 03 42 -49 54 85 12 28 51 00 B0 FE 51 05 42 49 54 2E 42 -85 12 28 51 40 B0 0A 52 03 42 49 43 85 12 28 51 -00 C0 18 52 05 42 49 43 2E 42 85 12 28 51 40 C0 -24 52 03 42 49 53 85 12 28 51 00 D0 32 52 05 42 -49 53 2E 42 85 12 28 51 40 D0 00 00 03 58 4F 52 -85 12 28 51 00 E0 4C 52 05 58 4F 52 2E 42 85 12 -28 51 40 E0 7E 51 03 41 4E 44 85 12 28 51 00 F0 -66 52 05 41 4E 44 2E 42 85 12 28 51 40 F0 62 48 -14 50 84 52 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F B8 51 03 52 52 43 85 12 7E 52 00 10 -96 52 05 52 52 43 2E 42 85 12 7E 52 40 10 A2 52 -04 53 57 50 42 00 85 12 7E 52 80 10 B0 52 03 52 -52 41 85 12 7E 52 00 11 BE 52 05 52 52 41 2E 42 -85 12 7E 52 40 11 CA 52 03 53 58 54 85 12 7E 52 -80 11 00 00 04 50 55 53 48 00 85 12 7E 52 00 12 -E4 52 06 50 55 53 48 2E 42 00 85 12 7E 52 40 12 -3E 52 04 43 41 4C 4C 00 85 12 7E 52 80 12 1A 53 -0E 4A 0D 12 84 12 24 45 14 40 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 41 D8 52 03 53 3E 3D -86 12 00 38 2C 53 02 53 3C 00 86 12 00 34 F2 52 -03 30 3E 3D 86 12 00 30 40 53 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C 54 53 03 55 -3E 3D 86 12 00 28 4A 53 03 30 3C 3E 86 12 00 24 -68 53 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D -5E 53 04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D EE 51 04 45 4C 53 45 00 1A 42 C6 1D -BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 -E3 3F 02 53 05 42 45 47 49 4E 30 40 28 40 92 53 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 1D 30 4D 72 52 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 80 53 08 44 AE 44 36 53 -06 52 45 50 45 41 54 00 0D 12 84 12 14 54 98 53 -AE 44 44 54 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D -CB 2F 98 42 C6 1D 00 00 30 4D D4 53 03 42 57 31 -85 12 42 54 00 00 5C 54 03 42 57 32 85 12 42 54 -00 00 68 54 03 42 57 33 85 12 42 54 00 00 80 54 -3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F -00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 7E 54 00 00 A0 54 03 46 57 32 -85 12 7E 54 00 00 AC 54 03 46 57 33 85 12 7E 54 -00 00 00 00 05 3F 47 4F 54 4F 3E 90 00 30 07 24 -3E E0 00 04 3E B0 00 10 02 24 3E E0 00 08 0D 12 -84 12 E0 48 3C 48 AE 44 B8 54 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C F1 3F 62 48 32 4F -02 55 92 53 C4 1D 3E 40 2C 00 84 12 7A 45 9E 46 -34 40 60 48 DE 50 18 55 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 30 54 04 52 52 43 4D 00 85 12 FC 54 -50 00 46 55 04 52 52 41 4D 00 85 12 FC 54 50 01 -54 55 04 52 4C 41 4D 00 85 12 FC 54 50 02 62 55 -04 52 52 55 4D 00 85 12 FC 54 50 03 72 53 05 50 -55 53 48 4D 85 12 FC 54 00 15 7E 55 04 50 4F 50 -4D 00 85 12 FC 54 00 17 70 55 06 52 52 43 4D 2E -41 00 85 12 FC 54 40 00 9A 55 06 52 52 41 4D 2E -41 00 85 12 FC 54 40 01 AA 55 06 52 4C 41 4D 2E -41 00 85 12 FC 54 40 02 BA 55 06 52 52 55 4D 2E -41 00 85 12 FC 54 40 03 8C 55 07 50 55 53 48 4D -2E 41 85 12 FC 54 00 14 DA 55 06 50 4F 50 4D 2E -41 00 85 12 FC 54 00 16 74 54 05 43 41 4C 4C 41 -0D 12 84 12 62 48 32 4F 0A 56 1B 42 C6 1D A2 53 -C6 1D 6E 4E 3C 40 34 01 7E 90 52 00 0B 20 7E 40 -20 00 B0 12 E0 4F 5C 0E 0C DE 8B 4C 00 00 3E 4F -3D 41 30 4D 2C 53 7E 90 40 00 0B 20 92 53 C4 1D -7E 40 20 00 B0 12 E0 4F EE 23 1C 53 3E 40 2B 00 -E8 3F A2 53 C6 1D 7E 90 23 00 09 20 3C 40 3B 01 -92 53 C4 1D B0 12 56 4F BB 4F 02 00 DC 3F 7E 90 -26 00 02 20 2C 53 F4 3F 7E 40 28 00 1C 83 B0 12 -56 4F BB 4F 02 00 3E 40 29 00 CB 3F 0D 12 84 12 -62 48 32 4F 96 56 69 4E 3E 4F 3C 4F 2C 4C 1B 42 -C6 1D A2 53 C6 1D 79 90 52 00 0A 20 B0 12 E0 4F -5E 0E 5E 0E 0E DC 8B 4E 00 00 0E 4B 3D 41 30 4D -79 90 23 00 0D 20 3C C0 40 00 92 53 C4 1D A2 53 -C6 1D B0 12 56 4F BB 4F 02 00 3E F0 0F 00 E8 3F -79 90 26 00 03 20 3C E0 E0 00 EF 3F 3C C0 F0 00 -79 90 40 00 12 20 92 53 C4 1D B0 12 E0 4F D8 23 -3C D0 10 00 3E 40 2B 00 B0 12 E0 4F 92 92 C0 1D -C4 1D CE 27 92 53 C4 1D CB 3F 3C D0 30 00 A2 53 -C6 1D 3E 40 28 00 B0 12 56 4F BB 4F 02 00 3E 40 -29 00 EA 3F 0D 12 84 12 62 48 32 4F 3E 57 3B 4F -2C 4B 69 4E 7E 40 20 00 79 90 52 00 03 20 B0 12 -E0 4F B0 3F 3C C0 F0 00 A2 53 C6 1D 79 90 26 00 -09 20 3C D0 60 00 92 53 C4 1D B0 12 56 4F BB 4F -02 00 A0 3F 3C D0 70 00 3E 40 28 00 B0 12 56 4F -BB 4F 02 00 3E 40 29 00 E2 3F 0A 40 2C 00 8C 56 -34 57 D2 43 AE 44 48 51 04 4D 4F 56 41 00 85 12 -8A 57 C0 00 FA 55 04 43 4D 50 41 00 85 12 8A 57 -D0 00 0E 54 04 41 44 44 41 00 85 12 8A 57 E0 00 -CA 55 04 53 55 42 41 00 85 12 8A 57 F0 00 0D 12 -84 12 62 48 32 4F D8 57 69 4E 3E 4F 3C 40 00 18 -79 90 52 00 05 20 B0 12 E0 4F 0E 4C 3D 41 30 4D -82 43 62 5C 79 90 23 00 0B 20 92 53 C4 1D B0 12 -56 4F 2F 53 3E F0 0F 00 5E 0A 5E 0E 0C DE ED 3F -79 90 26 00 F2 27 79 90 40 00 12 20 92 53 C4 1D -B0 12 E0 4F E2 23 3E 40 2B 00 92 53 C4 1D B0 12 -E0 4F 92 92 C0 1D C4 1D D8 27 92 53 C4 1D D5 3F -3E 40 28 00 B0 12 56 4F 8F 4E 00 00 3E 40 29 00 -B0 12 E0 4F 3E 4F 3E F0 0F 00 0C DE EA 3F 0D 12 -84 12 62 48 32 4F 68 58 3C 4F 69 4E 3E 40 20 00 -79 90 52 00 BA 27 82 43 62 5C 79 90 26 00 08 20 -92 53 C4 1D B0 12 56 4F 2F 53 3E F0 0F 00 BE 3F -3E 40 28 00 B0 12 56 4F F7 3F B2 4F C4 1D 1B 42 -C6 1D A2 53 C6 1D 0C 4E 3E 4F 1C D2 62 5C 82 43 -62 5C 3C DE 8B 4C 00 00 30 4D 0A 40 C4 1D 2E 44 -0A 40 2C 00 CE 57 5E 58 9A 58 3A 40 28 51 98 57 -04 4D 4F 56 58 00 85 12 BA 58 40 00 00 40 D0 58 -06 4D 4F 56 58 2E 41 00 85 12 BA 58 00 00 40 40 -E0 58 06 4D 4F 56 58 2E 42 00 85 12 BA 58 40 00 -40 40 B4 57 04 41 44 44 58 00 85 12 BA 58 40 00 -00 50 04 59 06 41 44 44 58 2E 41 00 85 12 BA 58 -00 00 40 50 14 59 06 41 44 44 58 2E 42 00 85 12 -BA 58 40 00 40 50 26 59 05 41 44 44 43 58 85 12 -BA 58 40 00 00 60 38 59 07 41 44 44 43 58 2E 41 -85 12 BA 58 00 00 40 60 48 59 07 41 44 44 43 58 -2E 42 85 12 BA 58 40 00 40 60 C2 57 05 53 55 42 -43 58 85 12 BA 58 40 00 00 70 6C 59 07 53 55 42 -43 58 2E 41 85 12 BA 58 00 00 40 70 7C 59 07 53 -55 42 43 58 2E 42 85 12 BA 58 40 00 40 70 8E 59 -04 53 55 42 58 00 85 12 BA 58 40 00 00 80 A0 59 -06 53 55 42 58 2E 41 00 85 12 BA 58 00 00 40 80 -B0 59 06 53 55 42 58 2E 42 00 85 12 BA 58 40 00 -40 80 A6 57 04 43 4D 50 58 00 85 12 BA 58 40 00 -00 90 D4 59 06 43 4D 50 58 2E 41 00 85 12 BA 58 -00 00 40 90 E4 59 06 43 4D 50 58 2E 42 00 85 12 -BA 58 40 00 40 90 B6 53 05 44 41 44 44 58 85 12 -BA 58 40 00 00 A0 08 5A 07 44 41 44 44 58 2E 41 -85 12 BA 58 00 00 40 A0 18 5A 07 44 41 44 44 58 -2E 42 85 12 BA 58 40 00 40 A0 F6 59 04 42 49 54 -58 00 85 12 BA 58 40 00 00 B0 3C 5A 06 42 49 54 -58 2E 41 00 85 12 BA 58 00 00 40 B0 4C 5A 06 42 -49 54 58 2E 42 00 85 12 BA 58 40 00 40 B0 5E 5A -04 42 49 43 58 00 85 12 BA 58 40 00 00 C0 70 5A -06 42 49 43 58 2E 41 00 85 12 BA 58 00 00 40 C0 -80 5A 06 42 49 43 58 2E 42 00 85 12 BA 58 40 00 -40 C0 92 5A 04 42 49 53 58 00 85 12 BA 58 40 00 -00 D0 A4 5A 06 42 49 53 58 2E 41 00 85 12 BA 58 -00 00 40 D0 B4 5A 06 42 49 53 58 2E 42 00 85 12 -BA 58 40 00 40 D0 58 52 04 58 4F 52 58 00 85 12 -BA 58 40 00 00 E0 D8 5A 06 58 4F 52 58 2E 41 00 -85 12 BA 58 00 00 40 E0 E8 5A 06 58 4F 52 58 2E -42 00 85 12 BA 58 40 00 40 E0 5A 59 04 41 4E 44 -58 00 85 12 BA 58 40 00 00 F0 0C 5B 06 41 4E 44 -58 2E 41 00 85 12 BA 58 00 00 40 F0 1C 5B 06 41 -4E 44 58 2E 42 00 85 12 BA 58 40 00 40 F0 0A 40 -C4 1D 2E 44 62 48 CE 57 9A 58 3A 40 7E 52 C2 59 -04 52 52 43 58 00 85 12 3E 5B 40 00 00 10 50 5B -06 52 52 43 58 2E 41 00 85 12 3E 5B 00 00 40 10 -60 5B 06 52 52 43 58 2E 42 00 85 12 3E 5B 40 00 -40 10 72 5B 04 52 52 55 58 00 85 12 3E 5B 40 01 -00 10 84 5B 06 52 52 55 58 2E 41 00 85 12 3E 5B -00 01 40 10 94 5B 06 52 52 55 58 2E 42 00 85 12 -3E 5B 40 01 40 10 A6 5B 05 53 57 50 42 58 85 12 -3E 5B 40 00 80 10 B8 5B 07 53 57 50 42 58 2E 41 -85 12 3E 5B 00 00 80 10 C8 5B 04 52 52 41 58 00 -85 12 3E 5B 40 00 00 11 DA 5B 06 52 52 41 58 2E -41 00 85 12 3E 5B 00 00 40 11 EA 5B 06 52 52 41 -58 2E 42 00 85 12 3E 5B 40 00 40 11 FC 5B 04 53 -58 54 58 00 85 12 3E 5B 40 00 80 11 0E 5C 06 53 -58 54 58 2E 41 00 85 12 3E 5B 00 00 80 11 EA 55 -05 50 55 53 48 58 85 12 3E 5B 40 00 00 12 30 5C -07 50 55 53 48 58 2E 41 85 12 3E 5B 00 00 40 12 -40 5C 07 50 55 53 48 58 2E 42 85 12 3E 5B 40 00 -40 12 00 00 1E 5C 03 52 50 54 0D 12 84 12 62 48 -32 4F 74 5C 29 4E 7E 40 20 00 79 90 52 00 06 20 -B0 12 E0 4F 03 24 3E D0 80 00 05 3C B0 12 56 4F -1E 83 3E F0 0F 00 82 4E 62 5C 3E 4F 3D 41 30 4D -D2 C3 23 02 E2 B2 60 02 02 24 30 40 E2 41 1A 52 -04 20 19 62 06 20 92 43 14 20 A2 93 02 20 07 24 -0A 5A 49 69 82 4A 16 20 C2 49 18 20 0A 3C C2 4A -15 20 8A 10 C2 4A 16 20 C2 49 17 20 89 10 C2 49 -18 20 B0 12 28 5D 5A 53 FC 23 39 40 05 00 D2 49 -14 20 4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 -C2 93 4C 06 59 83 F3 2F 19 83 0B 30 F2 43 4E 06 -82 93 46 06 03 24 92 B3 6C 06 FD 27 5A 92 4C 06 -F3 23 30 41 1A 43 E1 3F 19 43 3A 43 8A 10 C2 4A -4E 06 82 93 46 06 05 24 92 B3 6C 06 FD 27 C2 93 -4C 06 19 83 F3 23 5A 42 4C 06 30 41 66 5C 08 52 -45 41 44 5F 53 57 58 00 1C D3 F2 40 51 00 19 20 -B0 12 A0 5C 38 20 B0 12 28 5D 6A 53 04 24 FB 23 -D9 42 4C 06 FF 1D F2 43 4E 06 03 43 19 53 39 90 -01 02 F6 23 F2 43 4E 06 3C C0 03 00 D2 D3 23 02 -30 41 1E 54 09 57 52 49 54 45 5F 53 57 58 2C D3 -F0 40 58 00 75 C2 B0 12 A0 5C 15 20 3A 40 FE FF -29 43 B0 12 2C 5D D2 49 00 1E 4E 06 03 43 19 53 -39 90 00 02 F8 23 39 40 03 00 B0 12 2A 5D 7A C0 -E1 00 6A 92 D9 27 8C 10 1C 52 4C 06 D2 D3 23 02 -0D 12 84 12 18 43 14 40 0B 3C 20 53 44 20 45 72 -72 6F 72 21 F6 5D 2F 83 8F 4E 00 00 B2 40 10 00 -DC 1D 0E 4C 84 12 EE 44 36 41 B0 12 8C 41 0E 93 -9C 24 E2 B2 60 02 99 20 B2 40 81 A9 40 06 B2 40 -18 00 46 06 D2 D3 25 02 B2 D0 C0 04 0C 02 92 C3 -40 06 39 42 B0 12 2A 5D D2 C3 23 02 2C 42 B2 40 -95 00 14 20 B2 40 00 40 18 20 B0 12 24 5D 02 24 -30 40 D6 5D B0 12 28 5D 7A 93 FC 23 B2 40 87 AA -14 20 92 43 16 20 B2 40 00 48 18 20 B0 12 24 5D -29 42 B0 12 2A 5D 92 43 14 20 82 43 16 20 78 43 -3C 42 B2 40 00 77 18 20 B0 12 24 5D B2 40 40 69 -18 20 B0 12 E2 5C 03 24 58 83 F3 23 D9 3F 0C 5C -A2 43 16 20 B2 40 00 50 18 20 B0 12 E2 5C D0 23 -92 D3 40 06 82 43 46 06 92 C3 40 06 09 43 B0 12 -58 5D 38 40 00 1E 92 48 C6 01 04 20 92 48 C8 01 -06 20 5A 48 C2 01 92 43 02 20 7A 80 06 00 0F 24 -7A 82 0D 24 A2 43 02 20 6A 53 09 24 5A 53 07 24 -6A 52 05 24 3A 50 0B 20 0C 4A 30 40 DC 5D 09 43 -B0 12 58 5D D2 48 0D 00 12 20 19 48 0E 00 82 49 -08 20 1A 48 16 00 0A 93 02 20 1A 48 24 00 82 4A -0A 20 09 5A 82 49 0C 20 09 5A A2 93 02 20 04 24 -82 49 0E 20 39 50 20 00 19 82 12 20 19 82 12 20 -82 49 10 20 92 42 02 20 2C 20 30 41 B0 12 AA 40 -39 40 E0 00 29 83 89 43 38 20 FC 23 82 43 32 20 -30 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 5A 42 -23 20 58 42 22 20 92 93 02 20 08 24 59 42 24 20 -89 10 0A 59 88 10 08 58 0A 6A 88 10 08 58 30 41 -82 43 1C 20 92 42 0E 20 1A 20 C2 93 24 20 03 20 -92 93 22 20 14 24 92 42 22 20 D0 04 92 42 24 20 -D2 04 92 42 12 20 C8 04 92 42 E4 04 1A 20 92 42 -E6 04 1C 20 92 52 10 20 1A 20 82 63 1C 20 30 41 -92 4B 0E 00 22 20 92 4B 10 00 24 20 B0 12 90 5F -5A 4B 03 00 82 5A 1A 20 82 63 1C 20 30 41 09 93 -07 24 F8 90 20 00 00 1E 03 20 18 53 19 83 F9 23 -30 41 1B 42 32 20 82 43 1E 20 B2 90 00 02 20 20 -AB 20 BB 80 00 02 12 00 8B 73 14 00 DB 53 03 00 -DB 92 12 20 03 00 14 28 CB 43 03 00 B0 12 62 5F -1A 52 08 20 09 43 B0 12 58 5D 8B 43 10 00 9B 48 -00 1E 0E 00 92 93 02 20 03 24 9B 48 02 1E 10 00 -B2 40 00 02 20 20 8B 93 14 00 0B 20 92 9B 12 00 -1E 20 82 2C BB 90 00 02 12 00 03 2C 92 4B 12 00 -20 20 B0 12 D0 5F 1A 42 1A 20 19 42 1C 20 6C 3E -3C 42 3B 40 38 20 09 43 CB 93 02 00 10 24 9B 92 -24 20 0C 00 04 20 9B 92 22 20 0A 00 07 24 09 4B -3B 50 1C 00 3B 90 18 21 EF 23 0C 5C 30 41 0C 43 -82 4B 32 20 8B 49 00 00 09 93 0A 24 99 52 C4 1D -16 00 4A 93 05 34 C9 93 02 00 02 34 5A 59 02 00 -CB 4A 02 00 CB 43 03 00 9B 42 1A 20 04 00 9B 42 -1C 20 06 00 18 42 30 20 8B 48 08 00 9B 48 1A 1E -0A 00 9B 48 14 1E 0C 00 9B 48 1A 1E 0E 00 9B 48 -14 1E 10 00 9B 48 1C 1E 12 00 9B 48 1E 1E 14 00 -82 43 1E 20 6A 93 5C 27 C9 37 8B 43 16 00 7A 93 -02 24 07 38 95 3F B2 40 1C 21 CA 40 B2 40 44 43 -70 42 9B 42 C0 1D 18 00 9B 82 C4 1D 18 00 9B 42 -C2 1D 1A 00 9B 52 C4 1D 1A 00 82 3F CB 43 02 00 -2B 4B 82 4B 32 20 0B 93 06 24 92 4B 16 00 1E 20 -B0 12 50 60 22 C3 30 41 1B 42 32 20 0B 93 FB 27 -EB 93 02 00 04 20 B0 12 2C 66 B0 12 F4 65 CB 93 -02 00 E4 37 1E 4B 18 00 9F 4B 1A 00 00 00 31 50 -06 00 3D 41 B0 12 4C 61 02 24 30 40 36 43 B2 40 -3C 1D CA 40 B2 40 72 42 70 42 30 40 18 43 2E 4E -85 52 45 41 44 22 5A 43 19 3C A2 4C 86 57 52 49 -54 45 22 00 6A 43 12 3C 96 4D 84 44 45 4C 22 00 -6A 42 0C 3C E6 4A 05 43 4C 4F 53 45 B0 12 68 61 -30 4D 50 4C 85 4C 4F 41 44 22 7A 43 2F 83 8F 4E -00 00 0E 4A 82 93 BE 1D 0B 24 0D 12 84 12 0A 40 -0A 40 A8 47 A8 47 32 45 0A 40 20 62 A8 47 AE 44 -0D 12 84 12 0A 40 22 00 7A 45 F8 47 1E 62 3D 41 -36 4F 0E 56 82 4E 36 20 1C 43 92 42 2C 20 22 20 -92 42 2E 20 24 20 0E 96 8D 24 F6 90 3A 00 01 00 -01 20 26 53 F6 90 5C 00 00 00 08 20 16 53 92 42 -02 20 22 20 82 43 24 20 0E 96 70 24 82 46 34 20 -B0 12 90 5F 35 40 20 00 A2 93 02 20 04 24 92 92 -22 20 02 20 02 24 15 42 12 20 B0 12 76 60 2C 43 -0A 43 08 4A 58 0E 08 58 82 48 30 20 C8 93 00 1E -61 24 39 42 F8 96 00 1E 04 20 18 53 19 83 FA 23 -16 53 F6 90 2E 00 FF FF 19 24 39 50 03 00 B0 12 -EE 5F 06 20 F6 90 5C 00 FF FF 29 24 0E 96 27 28 -16 42 34 20 1A 53 3A 90 10 00 DB 23 92 53 1A 20 -82 63 1C 20 15 83 D1 23 2C 42 3C 3C F6 90 2E 00 -FE FF EE 27 B0 12 EE 5F EB 23 39 40 03 00 F8 96 -00 1E 04 20 18 53 19 83 FA 23 09 3C 0E 96 E0 2F -F6 90 5C 00 FF FF DC 23 B0 12 EE 5F D9 23 18 42 -30 20 92 48 1A 1E 22 20 92 48 14 1E 24 20 F8 B0 -10 00 0B 1E 14 24 82 93 24 20 06 20 82 93 22 20 -03 20 92 42 02 20 22 20 0E 96 8E 2F 92 42 22 20 -2C 20 92 42 24 20 2E 20 8F 43 00 00 03 3C 2A 4F -B0 12 80 60 35 40 D4 40 36 40 E2 40 3A 4F 3E 4F -0A 93 04 24 7A 93 3C 20 0C 93 01 20 30 4D 0D 12 -84 12 18 43 14 40 0B 3C 20 4F 70 65 6E 45 72 72 -6F 72 3A 40 F4 5D 26 4C 05 5B 50 46 41 5D 2E 53 -2E 4E 30 4D D6 61 04 42 4F 4F 54 00 39 40 0A 5E -2E 93 01 2C 30 41 E2 B2 60 02 02 24 10 49 02 00 -89 12 3F 40 7E 1C 8F 43 00 00 82 43 BE 1D B2 40 -00 1C 00 1C 31 40 E0 1C 84 12 14 40 0F 4C 4F 41 -44 22 20 42 4F 4F 54 2E 34 54 48 22 3A 40 90 48 -1A 93 BB 20 0C 93 C3 23 30 4D B0 61 04 52 45 41 -44 00 2F 83 8F 4E 00 00 1E 42 32 20 B0 12 02 60 -1E 82 32 20 30 4D 2C 43 12 12 2A 20 18 42 02 20 -08 58 2A 41 82 9A 0A 20 A6 24 1A 52 08 20 09 43 -B0 12 58 5D 09 43 28 93 03 24 89 93 02 1E 03 20 -89 93 00 1E 07 24 09 58 39 90 00 02 F4 23 91 53 -00 00 E7 3F 0C 43 6A 41 B9 43 00 1E 28 93 0F 24 -B9 40 FF 0F 02 1E 09 11 8A 10 09 5A 5A 41 01 00 -0A 11 09 10 82 4A 28 20 82 49 26 20 07 3C 09 11 -C2 49 26 20 C2 4A 27 20 82 43 28 20 3A 41 82 4A -2A 20 30 41 0A 12 1A 52 08 20 09 43 B0 12 9E 5D -3A 41 1A 52 0C 20 09 43 B0 12 9E 5D F2 B0 40 00 -A2 04 29 20 F2 B0 10 00 A2 04 FC 27 5A 42 B0 04 -4A 11 59 42 B4 04 F2 40 20 00 C0 04 D2 42 B1 04 -C8 04 1A 52 E4 04 D2 42 B5 04 C8 04 19 52 E4 04 -D2 42 B2 04 C0 04 B2 40 00 08 C8 04 1A 52 E4 04 -92 42 B6 04 C0 04 B2 80 BC 07 C0 04 B2 40 00 02 -C8 04 19 52 E4 04 30 41 22 2A 2B 2C 2F 3A 3B 3C -3D 3E 3F 5B 5C 5D 7C 2E 29 92 06 38 39 80 03 00 -B0 12 48 65 39 40 03 00 7A 4B C8 4A 00 1E 82 9B -36 20 12 28 0D 12 3D 40 0F 00 3C 40 F8 64 7A 9C -F3 27 1D 83 FC 23 3D 41 6A 9C E6 27 3A 80 21 00 -EB 3B 18 53 19 83 E8 23 09 93 06 24 F8 40 20 00 -00 1E 18 53 19 83 FA 23 30 41 2A 93 DC 20 2C 93 -0E 24 0C 93 AB 24 0D 12 84 12 14 40 0C 3C 20 57 -72 69 74 65 45 72 72 6F 72 00 3A 40 F4 5D B0 12 -06 64 92 42 26 20 22 20 92 42 28 20 24 20 B0 12 -84 64 B0 12 76 60 18 42 30 20 F8 40 20 00 0B 1E -B0 12 9C 64 88 43 0C 1E 88 4A 0E 1E 88 49 10 1E -88 49 12 1E 98 42 24 20 14 1E 98 42 22 20 1A 1E -88 43 1C 1E 88 43 1E 1E 1C 43 1B 42 34 20 82 9B -36 20 C9 27 FB 90 2E 00 00 00 C5 27 39 40 0B 00 -B0 12 18 65 B0 12 36 66 2A 43 B0 12 80 60 0C 93 -BA 23 30 4D 1A 4B 04 00 19 4B 06 00 B0 12 58 5D -B0 12 9C 64 18 4B 08 00 88 49 12 1E 88 4A 16 1E -88 49 18 1E 98 4B 12 00 1C 1E 98 4B 14 00 1E 1E -1A 4B 04 00 19 4B 06 00 30 40 9E 5D 9B 52 1E 20 -12 00 8B 63 14 00 1A 42 1A 20 19 42 1C 20 30 40 -9E 5D B2 40 00 02 1E 20 1B 42 32 20 B0 12 2C 66 -82 43 1E 20 DB 53 03 00 DB 92 12 20 03 00 25 20 -CB 43 03 00 B0 12 62 5F 08 12 0A 12 B0 12 06 64 -2A 91 08 24 B0 12 84 64 2A 41 1A 52 08 20 09 43 -B0 12 58 5D 3A 41 38 41 98 42 26 20 00 1E 92 93 -02 20 03 24 98 42 28 20 02 1E B0 12 84 64 9B 42 -26 20 0E 00 9B 42 28 20 10 00 30 40 D0 5F BC 61 -05 57 52 49 54 45 B0 12 42 66 30 4D 58 4B 13 00 -59 4B 14 00 89 10 09 58 58 4B 15 00 5B 42 12 20 -0A 43 3C 42 08 11 09 10 4A 10 1C 83 0B 11 FA 2B -0A 11 1C 83 FD 37 1B 42 32 20 19 5B 0A 00 18 6B -0C 00 8B 49 0E 00 8B 48 10 00 CB 4A 03 00 1A 4B -12 00 BB C0 FF 01 12 00 3A F0 FF 01 82 4A 1E 20 -B0 12 72 60 30 4D 0C 93 3B 20 38 90 E0 01 03 2C -C8 93 20 1E 02 24 7C 40 E5 00 C8 4C 00 1E B0 12 -36 66 B0 12 6E 5F 82 4A 2A 20 0B 4A 1A 52 08 20 -09 43 B0 12 58 5D 1A 48 00 1E 88 43 00 1E 92 93 -02 20 09 24 19 48 02 1E 88 43 02 1E 39 F0 FF 0F -39 90 FF 0F 02 20 3A 93 0E 24 82 4A 22 20 82 49 -24 20 B0 12 6E 5F 0B 9A E6 27 0A 12 0A 4B B0 12 -84 64 3A 41 DA 3F 0A 4B B0 12 84 64 B0 12 68 61 -30 4D EA 44 08 54 45 52 4D 32 53 44 22 00 0D 12 -84 12 D0 61 0A 40 02 00 28 40 F8 47 20 62 B0 67 -B0 12 B8 41 0A 43 92 B3 EC 06 FD 27 59 42 CC 06 -69 92 11 24 CA 49 00 1E 1A 53 79 90 0A 00 05 20 -84 12 DC 43 D6 67 B0 12 B8 41 3A 90 00 02 EB 2B -B0 12 42 66 E7 3F 92 B3 EC 06 FD 27 F2 90 0A 00 -CC 06 F9 23 82 4A 1E 20 B0 12 68 61 3D 41 30 4D +30 00 19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F +30 4D 7A 90 26 00 05 20 3C 40 10 02 B0 12 8A 4D +F0 3F 7A 90 40 00 14 20 3C 40 20 00 B0 12 D6 4D +0C 20 3C D0 10 00 3E 40 2B 00 B0 12 DA 4D 92 92 +C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F +3C D0 10 00 B0 12 C2 4D F2 3F 03 20 B0 12 DA 4D +F5 3F 7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 +80 00 B0 12 C2 4D EA 3F 0C 43 1B 42 C8 1D A2 53 +C8 1D 3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 +FE 27 5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 +52 00 30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 +0A 40 00 13 C2 48 D4 45 0A 40 2C 00 B8 4E FC 4D +06 44 C2 4E 9A 4E 08 4F 3D 41 2C DE 8B 4C 00 00 +9E 3F 00 00 06 4D 4F 56 85 12 F8 4E 00 40 14 4F +0A 4D 4F 56 2E 42 85 12 F8 4E 40 40 00 00 06 41 +44 44 85 12 F8 4E 00 50 2E 4F 0A 41 44 44 2E 42 +85 12 F8 4E 40 50 3A 4F 08 41 44 44 43 00 85 12 +F8 4E 00 60 48 4F 0C 41 44 44 43 2E 42 00 85 12 +F8 4E 40 60 80 4B 08 53 55 42 43 00 85 12 F8 4E +00 70 66 4F 0C 53 55 42 43 2E 42 00 85 12 F8 4E +40 70 74 4F 06 53 55 42 85 12 F8 4E 00 80 84 4F +0A 53 55 42 2E 42 85 12 F8 4E 40 80 90 4F 06 43 +4D 50 85 12 F8 4E 00 90 9E 4F 0A 43 4D 50 2E 42 +85 12 F8 4E 40 90 00 00 08 44 41 44 44 00 85 12 +F8 4E 00 A0 B8 4F 0C 44 41 44 44 2E 42 00 85 12 +F8 4E 40 A0 E6 4E 06 42 49 54 85 12 F8 4E 00 B0 +D6 4F 0A 42 49 54 2E 42 85 12 F8 4E 40 B0 E2 4F +06 42 49 43 85 12 F8 4E 00 C0 F0 4F 0A 42 49 43 +2E 42 85 12 F8 4E 40 C0 FC 4F 06 42 49 53 85 12 +F8 4E 00 D0 0A 50 0A 42 49 53 2E 42 85 12 F8 4E +40 D0 00 00 06 58 4F 52 85 12 F8 4E 00 E0 24 50 +0A 58 4F 52 2E 42 85 12 F8 4E 40 E0 56 4F 06 41 +4E 44 85 12 F8 4E 00 F0 3E 50 0A 41 4E 44 2E 42 +85 12 F8 4E 40 F0 06 44 B8 4E FC 4D 5E 50 0A 4C +3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4D 3F 16 50 +06 52 52 43 85 12 56 50 00 10 70 50 0A 52 52 43 +2E 42 85 12 56 50 40 10 AA 4F 08 53 57 50 42 00 +85 12 56 50 80 10 7C 50 06 52 52 41 85 12 56 50 +00 11 98 50 0A 52 52 41 2E 42 85 12 56 50 40 11 +8A 50 06 53 58 54 85 12 56 50 80 11 00 00 08 50 +55 53 48 00 85 12 56 50 00 12 BE 50 0C 50 55 53 +48 2E 42 00 85 12 56 50 40 12 B2 50 08 43 41 4C +4C 00 85 12 56 50 80 12 1A 53 0E 4A 84 12 48 46 +1E 40 0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 +12 41 DC 50 06 53 3E 3D 86 12 00 38 04 51 04 53 +3C 00 86 12 00 34 CC 50 06 30 3E 3D 86 12 00 30 +18 51 04 30 3C 00 86 12 00 30 54 4B 04 55 3C 00 +86 12 00 2C 2C 51 06 55 3E 3D 86 12 00 28 22 51 +06 30 3C 3E 86 12 00 24 40 51 04 30 3D 00 86 12 +00 20 00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 +A2 53 C8 1D 0E 4A 30 4D C6 4F 08 54 48 45 4E 00 +1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 +3A 90 00 02 B2 2F 88 DA 00 00 30 4D 36 51 08 45 +4C 53 45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 +C8 1D 2F 83 8F 4A 00 00 E3 3F A4 50 0A 42 45 47 +49 4E 30 40 32 40 8E 51 0A 55 4E 54 49 4C 3A 4F +08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 +00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 +C8 1D 30 4D 4A 50 0A 41 47 41 49 4E 0A 4E 38 40 +00 3C E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 +58 51 EE 44 D4 45 AC 51 0C 52 45 50 45 41 54 00 +0D 12 84 12 EC 51 70 51 D4 45 1C 52 3D 41 08 4E +3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 +30 4D 08 52 06 42 57 31 85 12 1A 52 00 00 34 52 +06 42 57 32 85 12 1A 52 00 00 40 52 06 42 57 33 +85 12 1A 52 00 00 58 52 3D 41 1A 42 C8 1D 28 4E +8E 43 00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 +C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 +85 12 56 52 00 00 7C 52 06 46 57 32 85 12 56 52 +00 00 88 52 06 46 57 33 85 12 56 52 00 00 F6 51 +08 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C +0D 12 84 12 8E 49 9A 48 D4 45 00 00 0A 3F 47 4F +54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 +EF 27 3E E0 00 08 EC 3F C2 4E 0A 40 2C 00 58 46 +6A 47 AC 40 9E 49 06 44 B8 4E 9A 4E EE 52 0A 4E +3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A +01 28 0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E +2A 92 EA 2E 8A 10 5A 06 A8 3E 4C 52 08 52 52 43 +4D 00 85 12 D8 52 50 00 1C 53 08 52 52 41 4D 00 +85 12 D8 52 50 01 2A 53 08 52 4C 41 4D 00 85 12 +D8 52 50 02 38 53 08 52 52 55 4D 00 85 12 D8 52 +50 03 4A 51 0A 50 55 53 48 4D 85 12 D8 52 00 15 +54 53 08 50 4F 50 4D 00 85 12 D8 52 00 17 D2 C3 +23 02 E2 B2 60 02 02 24 30 40 FA 41 1A 52 04 20 +19 62 06 20 92 43 14 20 C2 4A 15 20 8A 10 C2 4A +16 20 C2 49 17 20 89 10 C2 49 18 20 B0 12 E2 53 +5A 53 FC 23 39 40 05 00 D2 49 14 20 4E 06 82 93 +46 06 05 24 92 B3 6C 06 FD 27 C2 93 4C 06 59 83 +F3 2F 19 83 0B 30 F2 43 4E 06 82 93 46 06 03 24 +92 B3 6C 06 FD 27 5A 92 4C 06 F3 23 30 41 1A 43 +E1 3F 19 43 3A 43 8A 10 C2 4A 4E 06 82 93 46 06 +05 24 92 B3 6C 06 FD 27 C2 93 4C 06 19 83 F3 23 +5A 42 4C 06 30 41 46 53 12 52 5F 53 45 43 54 5F +57 58 1C D3 F2 40 51 00 19 20 B0 12 6E 53 38 20 +B0 12 E2 53 6A 53 04 24 FB 23 D9 42 4C 06 FF 1D +F2 43 4E 06 03 43 19 53 39 90 01 02 F6 23 F2 43 +4E 06 3C C0 03 00 D2 D3 23 02 30 41 A0 52 12 57 +5F 53 45 43 54 5F 57 58 2C D3 F0 40 58 00 BB CB +B0 12 6E 53 15 20 3A 40 FE FF 29 43 B0 12 E6 53 +D2 49 00 1E 4E 06 03 43 19 53 39 90 00 02 F8 23 +39 40 03 00 B0 12 E4 53 7A C0 E1 00 6A 82 D9 27 +8C 10 1C 52 4C 06 D2 D3 23 02 84 12 5A 43 1E 40 +0B 3C 20 53 44 20 45 72 72 6F 72 21 AE 54 2F 83 +8F 4E 00 00 B2 40 10 00 BE 1D 0E 4C 84 12 14 46 +12 41 B0 12 58 41 E2 B2 60 02 8A 20 B2 40 81 A9 +40 06 B2 40 18 00 46 06 D2 D3 25 02 B2 D0 C0 04 +0C 02 92 C3 40 06 39 40 6E 01 29 83 89 43 02 20 +FC 23 39 42 B0 12 E4 53 D2 C3 23 02 2C 42 B2 40 +95 00 14 20 B2 40 00 40 18 20 B0 12 DE 53 02 24 +30 40 90 54 B0 12 E2 53 7A 93 FC 23 B2 40 87 AA +14 20 92 43 16 20 B2 40 00 48 18 20 B0 12 DE 53 +29 42 B0 12 E4 53 92 43 14 20 82 43 16 20 78 43 +3C 42 B2 40 00 77 18 20 B0 12 DE 53 B2 40 40 69 +18 20 B0 12 9C 53 03 24 58 83 F3 23 D9 3F 0C 5C +A2 43 16 20 B2 40 00 50 18 20 B0 12 9C 53 D0 23 +92 D3 40 06 82 43 46 06 92 C3 40 06 0A 43 09 43 +B0 12 12 54 38 40 00 1E 92 48 C6 01 04 20 92 48 +C8 01 06 20 5C 48 C2 01 7C 80 0C 00 08 24 5C 53 +06 24 6C 52 04 24 3C 50 07 20 30 40 96 54 09 43 +B0 12 12 54 A2 43 2C 20 19 48 0E 00 82 49 08 20 +1A 48 24 00 82 4A 0A 20 09 5A 82 49 0C 20 09 5A +58 48 0D 00 82 48 12 20 09 88 09 88 82 49 10 20 +30 41 82 43 32 20 30 40 56 41 92 4B 0E 00 22 20 +92 4B 10 00 24 20 5A 42 23 20 58 42 22 20 59 42 +24 20 89 10 0A D9 88 10 08 58 0A 6A 88 10 08 58 +30 41 1A 52 08 20 09 43 FC 3E 92 42 22 20 D0 04 +92 42 24 20 D2 04 92 42 12 20 C8 04 92 42 E4 04 +1A 20 92 42 E6 04 1C 20 92 52 10 20 1A 20 82 63 +1C 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 24 20 +B0 12 1A 56 5A 4B 03 00 82 5A 1A 20 82 63 1C 20 +30 41 3C 42 3B 40 38 20 09 43 CB 93 02 00 10 24 +9B 92 24 20 0C 00 04 20 9B 92 22 20 0A 00 A3 25 +09 4B 3B 50 1C 00 3B 90 18 21 EF 23 0C 5C 9B 3D +0C 43 82 4B 32 20 8B 49 00 00 09 93 0A 24 99 52 +C6 1D 16 00 4A 93 05 34 C9 93 02 00 02 34 5A 59 +02 00 CB 4A 02 00 CB 43 03 00 9B 42 1A 20 04 00 +9B 42 1C 20 06 00 18 42 30 20 8B 48 08 00 9B 48 +1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 1A 1E 0E 00 +9B 48 14 1E 10 00 9B 48 1C 1E 12 00 9B 48 1E 1E +14 00 82 43 1E 20 6A 93 1A 24 A4 37 8B 43 16 00 +7A 93 02 24 07 38 35 3C B2 40 1C 21 A0 40 B2 40 +7E 43 BC 42 9B 42 C2 1D 18 00 9B 82 C6 1D 18 00 +9B 42 C4 1D 1A 00 9B 52 C6 1D 1A 00 22 3C 30 41 +1B 42 32 20 82 43 1E 20 B2 90 00 02 20 20 3F 20 +BB 80 00 02 12 00 8B 73 14 00 DB 53 03 00 DB 92 +12 20 03 00 0E 28 CB 43 03 00 B0 12 EA 55 B0 12 +12 56 8B 43 10 00 9B 48 00 1E 0E 00 9B 48 02 1E +10 00 B2 40 00 02 20 20 8B 93 14 00 0B 20 92 9B +12 00 1E 20 1C 2C BB 90 00 02 12 00 03 2C 92 4B +12 00 20 20 B0 12 44 56 1A 42 1A 20 19 42 1C 20 +38 3E CB 43 02 00 2B 4B 82 4B 32 20 0B 93 06 24 +92 4B 16 00 1E 20 B0 12 72 57 22 C3 30 41 1B 42 +32 20 0B 93 FB 27 EB 92 02 00 04 20 B0 12 30 5B +B0 12 20 5C CB 93 02 00 E4 37 1E 4B 18 00 9F 4B +1A 00 00 00 31 50 06 00 3D 41 B0 12 A2 57 02 24 +30 40 74 43 B2 40 3C 1D A0 40 B2 40 BE 42 BC 42 +30 40 5A 43 09 93 07 24 F8 90 20 00 00 1E 03 20 +18 53 19 83 F9 23 30 41 5E 4C 0B 52 45 41 44 22 +5A 43 20 3C C6 4A 09 44 45 4C 22 00 6A 43 1A 3C +8C 49 0D 57 52 49 54 45 22 00 6A 42 13 3C 74 49 +0F 41 50 50 45 4E 44 22 7A 42 0C 3C 70 4B 0A 43 +4C 4F 53 45 B0 12 BE 57 30 4D D4 48 0B 4C 4F 41 +44 22 7A 43 2F 83 8F 4E 00 00 0E 4A 82 93 BC 1D +0B 24 0D 12 84 12 0A 40 0A 40 C2 48 C2 48 42 45 +0A 40 98 58 C2 48 D4 45 0D 12 84 12 0A 40 22 00 +58 46 12 49 96 58 3D 41 36 4F 0E 56 82 4E 36 20 +A2 43 22 20 82 43 24 20 1C 43 0E 96 8C 24 F6 90 +3A 00 01 00 01 20 26 53 F6 90 5C 00 00 00 03 20 +16 53 0E 96 66 24 82 46 34 20 B0 12 1A 56 15 42 +12 20 B0 12 98 57 2C 43 0A 43 08 4A 58 0E 08 58 +82 48 30 20 C8 93 00 1E 60 24 39 42 F8 96 00 1E +04 20 18 53 19 83 FA 23 16 53 F6 90 2E 00 FF FF +19 24 39 50 03 00 B0 12 04 58 06 20 F6 90 5C 00 +FF FF 29 24 0E 96 27 28 16 42 34 20 1A 53 3A 90 +10 00 DB 23 92 53 1A 20 82 63 1C 20 15 83 D1 23 +2C 42 49 3C F6 90 2E 00 FE FF EE 27 B0 12 04 58 +EB 23 39 40 03 00 F8 96 00 1E 04 20 18 53 19 83 +FA 23 09 3C 0E 96 E0 2F F6 90 5C 00 FF FF DC 23 +B0 12 04 58 D9 23 18 42 30 20 92 48 1A 1E 22 20 +92 48 14 1E 24 20 F8 B0 10 00 0B 1E 13 24 82 93 +24 20 05 20 82 93 22 20 02 20 A2 43 22 20 0E 96 +9A 23 92 42 22 20 2C 20 92 42 24 20 2E 20 8F 43 +00 00 03 3C 2A 4F B0 12 62 56 35 40 B6 40 36 40 +C4 40 3A 4F 3E 4F 0A 93 04 24 7A 93 39 20 0C 93 +02 20 30 40 74 43 0D 12 84 12 5A 43 1E 40 0B 3C +20 4F 70 65 6E 45 72 72 6F 72 B2 40 AC 54 E2 B2 +60 02 02 24 30 40 80 41 92 12 3E 18 3F 40 7E 1C +8F 43 00 00 0D 12 84 12 1E 40 0F 4C 4F 41 44 22 +20 42 4F 4F 54 2E 34 54 48 22 B2 40 42 49 1A 58 +08 42 4F 4F 54 00 B2 40 DE 59 AE 42 30 4D 12 47 +0C 4E 4F 42 4F 4F 54 00 B2 40 80 41 AE 42 30 4D +1A 93 89 20 0C 93 C7 23 30 4D 10 5A 08 52 45 41 +44 00 2F 83 8F 4E 00 00 1E 42 32 20 B0 12 30 57 +1E 82 32 20 30 4D 08 4A 1A 52 08 20 B0 12 66 5A +0A 48 1A 52 0C 20 09 43 30 40 58 54 3C 42 0A 12 +2A 41 82 9A 0A 20 2B 25 B0 12 12 56 88 93 02 1E +03 20 88 93 00 1E 08 24 28 52 38 90 00 02 F6 2B +91 53 00 00 08 43 EC 3F A2 41 26 20 82 48 28 20 +0C 43 B8 43 00 1E 6A 41 B8 40 FF 0F 02 1E 08 11 +8A 10 08 5A 5A 41 01 00 0A 11 08 10 82 4A 24 20 +82 48 22 20 2A 41 B0 12 56 5A 3A 41 30 41 90 4B +0A 00 50 C5 90 4B 0C 00 4C C5 B0 12 F6 55 82 4A +26 20 82 48 28 20 0A 12 B0 12 12 56 1A 48 00 1E +88 43 00 1E 19 48 02 1E 88 43 02 1E 39 F0 FF 0F +39 90 FF 0F 02 20 3A 93 10 24 82 4A 22 20 82 49 +24 20 B0 12 F6 55 2A 91 E9 27 09 4A 2A 41 81 49 +00 00 B0 12 56 5A 2A 41 DF 3F 3A 41 30 40 56 5A +9B 52 1E 20 12 00 8B 63 14 00 1A 42 1A 20 19 42 +1C 20 30 40 58 54 2A 93 BC 20 0C 93 09 20 F8 40 +E5 00 00 1E B0 12 3A 5B B0 12 CE 5A B0 12 BE 57 +30 4D F2 B0 40 00 A2 04 29 20 F2 B0 10 00 A2 04 +FC 27 5A 42 B0 04 4A 11 59 42 B4 04 F2 40 20 00 +C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 D2 42 B5 04 +C8 04 19 52 E4 04 D2 42 B2 04 C0 04 B2 40 00 08 +C8 04 1A 52 E4 04 92 42 B6 04 C0 04 B2 80 BC 07 +C0 04 B2 40 00 02 C8 04 19 52 E4 04 30 41 22 2A +2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D 7C 2E 29 92 +06 28 39 80 03 00 B0 12 0E 5C 39 40 03 00 7A 4B +C8 4A 00 1E 82 9B 36 20 12 28 0D 12 3D 40 0F 00 +3C 40 BE 5B 7A 9C F3 27 1D 83 FC 23 3D 41 6A 9C +E6 27 3A 80 21 00 EB 3B 18 53 19 83 E8 23 09 93 +06 24 F8 40 20 00 00 1E 18 53 19 83 FA 23 30 41 +1A 4B 04 00 19 4B 06 00 B0 12 12 54 18 4B 08 00 +B0 12 62 5B 88 49 12 1E 88 4A 16 1E 88 49 18 1E +98 4B 12 00 1C 1E 98 4B 14 00 1E 1E 1A 4B 04 00 +19 4B 06 00 30 40 58 54 B2 40 00 02 1E 20 1B 42 +32 20 B0 12 30 5B 82 43 1E 20 DB 53 03 00 DB 92 +12 20 03 00 1D 28 B0 12 EA 55 08 12 0A 12 B0 12 +6C 5A 2A 91 03 24 2A 41 B0 12 12 56 3A 41 38 41 +98 42 22 20 00 1E 98 42 24 20 02 1E B0 12 56 5A +AB 42 02 00 9B 42 22 20 0E 00 9B 42 24 20 10 00 +30 40 50 56 32 58 0A 57 52 49 54 45 B0 12 58 5C +30 4D 2A 92 54 20 2C 93 0E 24 0C 93 3D 24 0D 12 +84 12 1E 40 0C 3C 20 57 72 69 74 65 45 72 72 6F +72 00 B2 40 AC 54 0A 43 08 43 B0 12 6C 5A B0 12 +98 57 18 42 30 20 F8 40 20 00 0B 1E B0 12 62 5B +88 43 0C 1E 88 4A 0E 1E 88 49 10 1E 98 42 24 20 +14 1E 98 42 22 20 1A 1E 88 43 1C 1E 88 43 1E 1E +2C 42 1B 42 34 20 82 9B 36 20 D1 27 FB 90 2E 00 +00 00 CD 27 39 40 0B 00 B0 12 DE 5B B0 12 3A 5B +2A 42 B0 12 62 56 30 4D B0 12 CE 5A 8B 43 12 00 +8B 43 14 00 90 4B 0A 00 CA C2 90 4B 0C 00 C6 C2 +B0 12 F6 55 B0 12 6C 5A B0 12 A0 5C 30 4D 2C 93 +BA 27 0C 93 AC 23 EB 42 02 00 58 4B 13 00 59 4B +14 00 89 10 09 58 58 4B 15 00 5B 42 12 20 0A 43 +3C 42 08 11 09 10 4A 10 1C 83 0B 11 FA 2B 0A 11 +1C 83 FD 37 1B 42 32 20 19 5B 0A 00 18 6B 0C 00 +8B 49 0E 00 8B 48 10 00 CB 4A 03 00 B0 12 94 57 +1A 4B 12 00 BB C0 FF 01 12 00 3A F0 FF 01 82 4A +1E 20 30 4D 26 58 10 54 45 52 4D 32 53 44 22 00 +0D 12 84 12 3A 58 E8 5D 0A 43 7D 40 0A 00 B0 12 +44 41 3A 90 00 02 03 28 B0 12 58 5C 0A 43 92 B3 +EC 06 FD 27 59 42 CC 06 69 92 11 24 CA 49 00 1E +1A 53 49 9D EE 23 A2 B3 EC 06 FD 27 F2 40 0D 00 +CE 06 A2 B3 EC 06 FD 27 C2 4D CE 06 E0 3F C2 9D +CC 06 FD 23 82 4A 1E 20 B0 12 BE 57 3D 41 30 4D @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 84 42 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 -E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 E2 41 96 4E +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 D0 42 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 +FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 FA 41 10 42 q diff --git a/binaries/MSP_EXP430FR5994_8MHz_UART.txt b/binaries/MSP_EXP430FR5994_8MHz_UART.txt deleted file mode 100644 index 24cd7dd..0000000 --- a/binaries/MSP_EXP430FR5994_8MHz_UART.txt +++ /dev/null @@ -1,657 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF 08 68 50 4D 34 01 -10 00 C1 B3 94 41 62 5F DA 41 20 5E 96 42 08 68 -50 4D 7C 42 F2 43 26 43 00 43 3C 1D C0 44 D4 40 -E2 40 EE 40 20 00 0A 00 00 00 00 00 00 00 00 00 -@4000 -B0 12 DA 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 40 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D2 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 62 5F 39 40 22 18 -B2 49 7A 42 B2 49 F0 43 B2 49 24 43 B2 49 FE 42 -B2 49 CA 40 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 58 4E 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 41 92 C3 DC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -DC 05 F3 23 B0 12 F8 40 0A 40 DE 1D 40 44 34 43 -14 40 04 1B 5B 37 6D 00 BC 43 08 44 34 40 86 41 -14 40 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 BC 43 00 45 BC 43 14 40 04 1B 5B 30 6D 00 -BC 43 88 48 92 B3 CA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 C0 05 92 42 02 18 C6 05 92 42 04 18 -C8 05 F2 D0 03 00 0D 02 92 C3 C0 05 92 D3 DA 05 -92 C3 30 01 30 41 09 3C A2 B3 DC 05 FD 27 B2 40 -13 00 CE 05 E2 D2 23 02 30 41 A2 B3 DC 05 FD 27 -B2 40 11 00 CE 05 E2 C2 23 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 41 F2 B0 40 00 40 02 02 20 B2 43 -08 18 B2 40 04 A5 20 01 EE 41 04 57 41 52 4D 00 -B0 12 20 5E 84 12 14 40 07 0D 0A 1B 5B 37 6D 23 -BC 43 36 45 14 40 19 46 61 73 74 46 6F 72 74 68 -20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 -BC 43 0A 40 40 FF 28 40 34 44 00 45 14 40 0A 62 -79 74 65 73 20 66 72 65 65 00 3A 40 86 41 00 00 -06 41 43 43 45 50 54 00 30 40 7C 42 08 4E 2E 4F -08 5E 39 40 0D 00 3A 40 20 00 3B 40 C8 42 3C 40 -D4 42 5D 15 B5 3E 21 52 3A 17 58 42 CC 05 48 9B -93 27 48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 -05 3C 0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 DC 05 -FD 27 C2 48 CE 05 30 4D CA 42 2D 83 92 B3 DC 05 -E4 23 FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 -DC 05 FD 27 58 42 CC 05 82 93 DE 1D 02 24 92 53 -DE 1D 08 4C E3 3F 00 00 03 4B 45 59 30 40 00 43 -2F 83 8F 4E 00 00 B0 12 DA 41 92 B3 DC 05 FD 27 -1E 42 CC 05 B0 12 C8 41 30 4D 00 00 04 45 4D 49 -54 00 30 40 26 43 08 4E 3E 4F C8 3F 1C 43 04 45 -43 48 4F 00 B2 40 C2 48 C2 42 82 43 DE 1D 30 4D -00 00 06 4E 4F 45 43 48 4F 00 B2 40 30 4D C2 42 -92 43 DE 1D 30 4D 0D 12 3D 40 76 43 1B 42 32 20 -9B 42 1E 20 16 00 3A 4F 09 4E 0E 43 1C 42 1E 20 -1B 42 20 20 02 3C 78 43 2D 83 0C 9B 16 2C 58 4C -00 1E 1C 53 78 90 20 00 09 2C 78 90 0A 00 F5 23 -3D 41 82 4C 1E 20 3C 40 20 00 A6 3F 0E 99 8E 27 -CA 48 00 00 1A 53 1E 53 89 3F 1A 15 B0 12 18 60 -19 17 DC 3F 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 D8 43 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 24 43 DA 43 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 41 02 43 52 00 30 40 -F2 43 0D 12 84 12 14 40 02 0D 0A 00 BC 43 C0 44 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 70 42 01 40 -2E 4E 30 4D 3E 44 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D EA 43 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 40 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 7A 44 02 23 53 00 0D 12 -84 12 7C 44 B6 44 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D AA 44 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D B6 43 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -70 44 AE 44 EE 40 EE 44 CA 44 BC 43 74 48 22 43 -C0 44 42 43 01 2E 0E 93 E3 37 38 43 E2 3F E8 44 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 40 14 40 -BA 47 0A 40 22 00 8C 45 5A 45 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -34 45 82 2E 22 00 0D 12 84 12 44 45 0A 40 BC 43 -BA 47 C0 44 1A 42 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 40 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 40 35 40 D4 40 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 0E 47 -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F 10 47 -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 40 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D B8 47 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 40 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D C6 44 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D DA 44 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 40 74 48 8C 45 30 48 -9C 26 3D 40 38 48 DE 3E 3A 48 0A 4E 3E 4F 3D 40 -54 48 36 27 3D 40 2A 48 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 56 48 3E 4F 3D 40 2A 48 BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 F6 49 -CC 3F 5E 48 86 12 20 00 46 44 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 EE 43 -BC 40 24 48 24 44 56 44 14 40 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 41 0A 40 40 FF 28 40 -5E 44 14 40 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 41 3A 40 9E 48 7A 48 86 41 42 4F 52 54 22 00 -0D 12 84 12 44 45 0A 40 2A 41 BA 47 C0 44 EE 45 -01 27 0D 12 84 12 74 48 8C 45 F4 45 34 40 72 48 -C0 44 00 00 83 5B 27 5D 0D 12 84 12 F2 48 0A 40 -0A 40 BA 47 BA 47 C0 44 04 49 81 5B 82 43 BE 1D -30 4D 6C 44 01 5D B2 43 BE 1D 30 4D 24 49 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 74 48 8C 45 F4 45 08 44 -34 40 72 48 56 44 34 40 66 49 0A 40 0A 40 BA 47 -BA 47 0A 40 BA 47 BA 47 C0 44 1A 49 01 3A 30 12 -B6 49 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 74 48 -8C 45 84 49 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 40 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 41 6C 49 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 40 C0 44 BA 47 C8 49 1C 49 -C0 44 1A 48 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D 04 48 06 43 52 45 -41 54 45 00 B0 12 72 49 BA 40 86 12 FC FF 8A 4A -FE FF C9 3F FA 49 07 3A 4E 4F 4E 41 4D 45 30 12 -B6 49 2F 83 8F 4E 00 00 1A 42 C6 1D 1A B3 0A 63 -0E 4A 39 40 10 02 08 49 28 53 99 3F 2E 43 05 44 -45 46 45 52 B0 12 72 49 BA 40 30 40 FC FF BA 40 -F4 4D FE FF A8 3F BE 4F 02 00 3E 4F 30 4D 14 4A -82 49 53 00 0D 12 82 93 BE 1D 06 24 84 12 08 49 -0A 40 86 4A BA 47 C0 44 84 12 F2 48 86 4A C0 44 -2C 4A 04 43 4F 44 45 00 B0 12 72 49 A2 82 C6 1D -82 43 78 5C 0D 12 84 12 5A 4D 2C 4D C0 44 90 4A -07 48 44 4E 43 4F 44 45 B2 40 30 4D DA 1D EC 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 C8 49 -80 4D B4 4D C0 44 B2 4A 07 43 4F 44 45 4E 4E 4D -30 12 BC 4A A6 3F 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 80 4D B4 4D C0 44 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F D0 4A 85 48 49 32 4C 4F 0D 12 84 12 28 40 -94 4C BA 47 1C 49 C0 4A C0 44 46 4A 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 5C 4B 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 40 00 00 38 44 74 48 8C 45 -0A 48 00 44 34 40 F4 4B 0E 44 14 40 06 5B 54 48 -45 4E 5D 00 66 4B CE 4B 8A 4B AC 4B C0 44 0E 44 -14 40 06 5B 45 4C 53 45 5D 00 66 4B E4 4B 8A 4B -AA 4B C0 44 14 40 04 5B 49 46 5D 00 66 4B AC 4B -3A 40 AA 4B E2 43 14 40 05 0D 0A 6B 6F 20 BC 43 -BC 40 AC 40 3A 40 AC 4B 9A 4B 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 0A 4C 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 74 48 8C 45 -F4 45 18 4C C0 44 1E 4C 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 28 4C 50 44 C0 44 50 4C -B2 4E 0A 18 B2 4E 0C 18 BE 12 3E 4F 3D 41 DB 3C -CC 47 06 4D 41 52 4B 45 52 00 B0 12 72 49 BA 40 -85 12 FC FF BA 40 4E 4C FE FF 28 83 8A 48 00 00 -9A 42 C8 1D 02 00 BA 40 AA 40 04 00 B2 50 06 00 -C6 1D 9D 3E 2E 53 30 4D 6E 4A 05 44 4F 45 53 3E -1A 42 BA 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 -30 4D 86 45 0A 56 4F 43 41 42 55 4C 41 52 59 00 -0D 12 84 12 34 4A 0A 40 10 00 0A 40 00 00 3E 40 -0A 40 00 00 BA 47 60 40 D0 4C 28 40 0A 40 C8 1D -00 44 40 44 BA 47 48 44 A0 4C 0A 40 CA 1D 48 44 -C0 44 F0 48 05 46 4F 52 54 48 85 12 EA 4C 54 4D -AC 63 E0 61 F4 4C 44 4B F8 42 FA 61 9A 4D 26 4E -02 64 AA 67 C6 66 00 00 9E 63 2E 49 54 46 00 00 -D8 48 09 41 53 53 45 4D 42 4C 45 52 85 12 EA 4C -44 5B DC 5A 40 5A 00 55 92 53 00 00 08 59 00 00 -68 5C 64 5D F6 53 AA 5D 10 5B 00 00 00 00 DA 54 -1E 4D 22 4D 04 41 4C 53 4F 00 3A 40 0C 00 39 40 -D6 1D 08 49 28 53 19 83 18 83 E8 49 00 00 1A 83 -FA 23 30 4D 3A 49 08 50 52 45 56 49 4F 55 53 00 -3A 40 0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 -18 53 1A 83 FB 23 30 4D 72 45 04 4F 4E 4C 59 00 -82 43 CC 1D 30 4D 9A 4C 0B 44 45 46 49 4E 49 54 -49 4F 4E 53 92 42 CA 1D DA 1D 30 4D FA 4C A0 4D -B4 4D C4 4D 3A 4E 82 4A C8 1D 2E 4E 82 4E C6 1D -3D 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0E 98 -FC 2B 89 48 00 00 1D 83 F6 23 2A 4A 0A 93 F0 23 -3E 4F 3D 41 30 4D 76 4D 09 50 57 52 5F 53 54 41 -54 45 85 12 BC 4D 50 4D 08 68 40 45 09 52 53 54 -5F 53 54 41 54 45 92 42 0A 18 08 4E 92 42 0C 18 -06 4E EF 3F F8 4D 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 08 4E 92 42 C8 1D 06 4E 30 4D 0C 4E -08 52 53 54 5F 48 45 52 45 00 92 42 C6 1D 0A 18 -92 42 C8 1D 0C 18 EC 3F 3E 90 0E 00 D2 27 2E 92 -DA 37 0E 93 CE 37 39 40 10 00 29 83 B9 43 80 FF -FC 23 B9 40 A8 4E FE FF 29 83 B9 40 02 42 FE FF -39 90 AE FF F9 23 39 40 14 18 B2 49 04 42 B2 49 -FA 40 B2 49 02 40 B2 49 22 42 B2 49 F0 FF B2 49 -0A 18 B2 49 0C 18 B7 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 10 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FC FF 02 02 B2 43 26 02 B2 D3 22 02 -E2 D2 25 02 B2 43 42 02 B2 D3 46 02 B2 43 62 02 -B2 D3 66 02 F2 43 26 03 F2 D3 22 03 F2 40 A5 00 -61 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -F2 D0 10 00 2A 03 F2 40 A5 00 A1 04 F2 C0 40 00 -A2 04 B2 42 B0 01 1E 42 08 18 82 43 08 18 1E D2 -9E 01 B0 12 F8 40 20 42 38 40 C0 1D 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 -12 12 C4 1D 84 12 8C 45 F4 45 50 44 34 40 88 4F -B0 46 34 40 A2 4F 9C 4F 8A 4F 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 A4 4F B2 41 C4 1D 3E 41 84 12 0A 40 2B 00 -8C 45 F4 45 50 44 34 40 C0 4F B0 46 34 40 72 48 -1A 44 8C 45 B0 46 34 40 72 48 CC 4F 3E 5F E7 3F -32 B0 00 02 01 24 3E 4F 30 41 3E 40 28 00 B0 12 -6C 4F B0 12 D0 4F 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 40 29 00 1C 15 92 92 C0 1D C4 1D 02 20 -30 40 E0 49 12 12 C4 1D 92 53 C4 1D 84 12 8C 45 -B0 46 34 40 22 50 18 50 21 53 3E 90 10 00 84 2D -BE 2B 24 50 B2 41 C4 1D BA 3F 0D 12 84 12 74 48 -48 4F 34 50 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E -3E 4F 7A 90 23 00 29 20 92 53 C4 1D B0 12 6C 4F -B0 12 D0 4F 3C 40 00 03 0E 93 1C 24 3C 40 10 03 -1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 -2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 -3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 09 20 -3C 40 10 02 92 53 C4 1D B0 12 6C 4F B0 12 D0 4F -EB 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D -B0 12 F6 4F 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -F6 4F 92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 -0C 5E D8 3F B0 12 F6 4F FA 23 3C 50 10 00 B0 12 -DA 4F EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 -84 12 74 48 48 4F 08 51 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C5 3F B0 12 F6 4F E0 23 -3C 50 80 00 B0 12 DA 4F DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 40 00 13 BA 47 C0 44 0A 40 -2C 00 2A 50 FE 50 48 51 09 4B 2E 4E 0E DC A0 3F -32 4B 03 4D 4F 56 85 12 3E 51 00 40 52 51 05 4D -4F 56 2E 42 85 12 3E 51 40 40 00 00 03 41 44 44 -85 12 3E 51 00 50 6C 51 05 41 44 44 2E 42 85 12 -3E 51 40 50 78 51 04 41 44 44 43 00 85 12 3E 51 -00 60 86 51 06 41 44 44 43 2E 42 00 85 12 3E 51 -40 60 2C 51 04 53 55 42 43 00 85 12 3E 51 00 70 -A4 51 06 53 55 42 43 2E 42 00 85 12 3E 51 40 70 -B2 51 03 53 55 42 85 12 3E 51 00 80 C2 51 05 53 -55 42 2E 42 85 12 3E 51 40 80 08 4B 03 43 4D 50 -85 12 3E 51 00 90 DC 51 05 43 4D 50 2E 42 85 12 -3E 51 40 90 E2 4A 04 44 41 44 44 00 85 12 3E 51 -00 A0 F6 51 06 44 41 44 44 2E 42 00 85 12 3E 51 -40 A0 E8 51 03 42 49 54 85 12 3E 51 00 B0 14 52 -05 42 49 54 2E 42 85 12 3E 51 40 B0 20 52 03 42 -49 43 85 12 3E 51 00 C0 2E 52 05 42 49 43 2E 42 -85 12 3E 51 40 C0 3A 52 03 42 49 53 85 12 3E 51 -00 D0 48 52 05 42 49 53 2E 42 85 12 3E 51 40 D0 -00 00 03 58 4F 52 85 12 3E 51 00 E0 62 52 05 58 -4F 52 2E 42 85 12 3E 51 40 E0 94 51 03 41 4E 44 -85 12 3E 51 00 F0 7C 52 05 41 4E 44 2E 42 85 12 -3E 51 40 F0 74 48 2A 50 9A 52 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F CE 51 03 52 52 43 -85 12 94 52 00 10 AC 52 05 52 52 43 2E 42 85 12 -94 52 40 10 B8 52 04 53 57 50 42 00 85 12 94 52 -80 10 C6 52 03 52 52 41 85 12 94 52 00 11 D4 52 -05 52 52 41 2E 42 85 12 94 52 40 11 E0 52 03 53 -58 54 85 12 94 52 80 11 00 00 04 50 55 53 48 00 -85 12 94 52 00 12 FA 52 06 50 55 53 48 2E 42 00 -85 12 94 52 40 12 54 52 04 43 41 4C 4C 00 85 12 -94 52 80 12 1A 53 0E 4A 0D 12 84 12 36 45 14 40 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 41 -EE 52 03 53 3E 3D 86 12 00 38 42 53 02 53 3C 00 -86 12 00 34 08 53 03 30 3E 3D 86 12 00 30 56 53 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C 6A 53 03 55 3E 3D 86 12 00 28 60 53 03 30 -3C 3E 86 12 00 24 7E 53 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 -C6 1D 0E 4A 30 4D 74 53 04 54 48 45 4E 00 1A 42 -C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 04 52 04 45 4C 53 -45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D -2F 83 8F 4A 00 00 E3 3F 18 53 05 42 45 47 49 4E -30 40 28 40 A8 53 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D -30 4D 88 52 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 96 53 -1A 44 C0 44 4C 53 06 52 45 50 45 41 54 00 0D 12 -84 12 2A 54 AE 53 C0 44 5A 54 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D -EA 53 03 42 57 31 85 12 58 54 00 00 72 54 03 42 -57 32 85 12 58 54 00 00 7E 54 03 42 57 33 85 12 -58 54 00 00 96 54 3D 41 1A 42 C6 1D 28 4E B2 92 -C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 94 54 00 00 -B6 54 03 46 57 32 85 12 94 54 00 00 C2 54 03 46 -57 33 85 12 94 54 00 00 00 00 05 3F 47 4F 54 4F -3E 90 00 30 07 24 3E E0 00 04 3E B0 00 10 02 24 -3E E0 00 08 0D 12 84 12 F2 48 4E 48 C0 44 CE 54 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -F1 3F 74 48 48 4F 18 55 92 53 C4 1D 3E 40 2C 00 -84 12 8C 45 B0 46 34 40 72 48 F4 50 2E 55 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E 46 54 04 52 52 43 -4D 00 85 12 12 55 50 00 5C 55 04 52 52 41 4D 00 -85 12 12 55 50 01 6A 55 04 52 4C 41 4D 00 85 12 -12 55 50 02 78 55 04 52 52 55 4D 00 85 12 12 55 -50 03 88 53 05 50 55 53 48 4D 85 12 12 55 00 15 -94 55 04 50 4F 50 4D 00 85 12 12 55 00 17 86 55 -06 52 52 43 4D 2E 41 00 85 12 12 55 40 00 B0 55 -06 52 52 41 4D 2E 41 00 85 12 12 55 40 01 C0 55 -06 52 4C 41 4D 2E 41 00 85 12 12 55 40 02 D0 55 -06 52 52 55 4D 2E 41 00 85 12 12 55 40 03 A2 55 -07 50 55 53 48 4D 2E 41 85 12 12 55 00 14 F0 55 -06 50 4F 50 4D 2E 41 00 85 12 12 55 00 16 8A 54 -05 43 41 4C 4C 41 0D 12 84 12 74 48 48 4F 20 56 -1B 42 C6 1D A2 53 C6 1D 6E 4E 3C 40 34 01 7E 90 -52 00 0B 20 7E 40 20 00 B0 12 F6 4F 5C 0E 0C DE -8B 4C 00 00 3E 4F 3D 41 30 4D 2C 53 7E 90 40 00 -0B 20 92 53 C4 1D 7E 40 20 00 B0 12 F6 4F EE 23 -1C 53 3E 40 2B 00 E8 3F A2 53 C6 1D 7E 90 23 00 -09 20 3C 40 3B 01 92 53 C4 1D B0 12 6C 4F BB 4F -02 00 DC 3F 7E 90 26 00 02 20 2C 53 F4 3F 7E 40 -28 00 1C 83 B0 12 6C 4F BB 4F 02 00 3E 40 29 00 -CB 3F 0D 12 84 12 74 48 48 4F AC 56 69 4E 3E 4F -3C 4F 2C 4C 1B 42 C6 1D A2 53 C6 1D 79 90 52 00 -0A 20 B0 12 F6 4F 5E 0E 5E 0E 0E DC 8B 4E 00 00 -0E 4B 3D 41 30 4D 79 90 23 00 0D 20 3C C0 40 00 -92 53 C4 1D A2 53 C6 1D B0 12 6C 4F BB 4F 02 00 -3E F0 0F 00 E8 3F 79 90 26 00 03 20 3C E0 E0 00 -EF 3F 3C C0 F0 00 79 90 40 00 12 20 92 53 C4 1D -B0 12 F6 4F D8 23 3C D0 10 00 3E 40 2B 00 B0 12 -F6 4F 92 92 C0 1D C4 1D CE 27 92 53 C4 1D CB 3F -3C D0 30 00 A2 53 C6 1D 3E 40 28 00 B0 12 6C 4F -BB 4F 02 00 3E 40 29 00 EA 3F 0D 12 84 12 74 48 -48 4F 54 57 3B 4F 2C 4B 69 4E 7E 40 20 00 79 90 -52 00 03 20 B0 12 F6 4F B0 3F 3C C0 F0 00 A2 53 -C6 1D 79 90 26 00 09 20 3C D0 60 00 92 53 C4 1D -B0 12 6C 4F BB 4F 02 00 A0 3F 3C D0 70 00 3E 40 -28 00 B0 12 6C 4F BB 4F 02 00 3E 40 29 00 E2 3F -0A 40 2C 00 A2 56 4A 57 E4 43 C0 44 5E 51 04 4D -4F 56 41 00 85 12 A0 57 C0 00 10 56 04 43 4D 50 -41 00 85 12 A0 57 D0 00 24 54 04 41 44 44 41 00 -85 12 A0 57 E0 00 E0 55 04 53 55 42 41 00 85 12 -A0 57 F0 00 0D 12 84 12 74 48 48 4F EE 57 69 4E -3E 4F 3C 40 00 18 79 90 52 00 05 20 B0 12 F6 4F -0E 4C 3D 41 30 4D 82 43 78 5C 79 90 23 00 0B 20 -92 53 C4 1D B0 12 6C 4F 2F 53 3E F0 0F 00 5E 0A -5E 0E 0C DE ED 3F 79 90 26 00 F2 27 79 90 40 00 -12 20 92 53 C4 1D B0 12 F6 4F E2 23 3E 40 2B 00 -92 53 C4 1D B0 12 F6 4F 92 92 C0 1D C4 1D D8 27 -92 53 C4 1D D5 3F 3E 40 28 00 B0 12 6C 4F 8F 4E -00 00 3E 40 29 00 B0 12 F6 4F 3E 4F 3E F0 0F 00 -0C DE EA 3F 0D 12 84 12 74 48 48 4F 7E 58 3C 4F -69 4E 3E 40 20 00 79 90 52 00 BA 27 82 43 78 5C -79 90 26 00 08 20 92 53 C4 1D B0 12 6C 4F 2F 53 -3E F0 0F 00 BE 3F 3E 40 28 00 B0 12 6C 4F F7 3F -B2 4F C4 1D 1B 42 C6 1D A2 53 C6 1D 0C 4E 3E 4F -1C D2 78 5C 82 43 78 5C 3C DE 8B 4C 00 00 30 4D -0A 40 C4 1D 40 44 0A 40 2C 00 E4 57 74 58 B0 58 -3A 40 3E 51 AE 57 04 4D 4F 56 58 00 85 12 D0 58 -40 00 00 40 E6 58 06 4D 4F 56 58 2E 41 00 85 12 -D0 58 00 00 40 40 F6 58 06 4D 4F 56 58 2E 42 00 -85 12 D0 58 40 00 40 40 CA 57 04 41 44 44 58 00 -85 12 D0 58 40 00 00 50 1A 59 06 41 44 44 58 2E -41 00 85 12 D0 58 00 00 40 50 2A 59 06 41 44 44 -58 2E 42 00 85 12 D0 58 40 00 40 50 3C 59 05 41 -44 44 43 58 85 12 D0 58 40 00 00 60 4E 59 07 41 -44 44 43 58 2E 41 85 12 D0 58 00 00 40 60 5E 59 -07 41 44 44 43 58 2E 42 85 12 D0 58 40 00 40 60 -D8 57 05 53 55 42 43 58 85 12 D0 58 40 00 00 70 -82 59 07 53 55 42 43 58 2E 41 85 12 D0 58 00 00 -40 70 92 59 07 53 55 42 43 58 2E 42 85 12 D0 58 -40 00 40 70 A4 59 04 53 55 42 58 00 85 12 D0 58 -40 00 00 80 B6 59 06 53 55 42 58 2E 41 00 85 12 -D0 58 00 00 40 80 C6 59 06 53 55 42 58 2E 42 00 -85 12 D0 58 40 00 40 80 BC 57 04 43 4D 50 58 00 -85 12 D0 58 40 00 00 90 EA 59 06 43 4D 50 58 2E -41 00 85 12 D0 58 00 00 40 90 FA 59 06 43 4D 50 -58 2E 42 00 85 12 D0 58 40 00 40 90 CC 53 05 44 -41 44 44 58 85 12 D0 58 40 00 00 A0 1E 5A 07 44 -41 44 44 58 2E 41 85 12 D0 58 00 00 40 A0 2E 5A -07 44 41 44 44 58 2E 42 85 12 D0 58 40 00 40 A0 -0C 5A 04 42 49 54 58 00 85 12 D0 58 40 00 00 B0 -52 5A 06 42 49 54 58 2E 41 00 85 12 D0 58 00 00 -40 B0 62 5A 06 42 49 54 58 2E 42 00 85 12 D0 58 -40 00 40 B0 74 5A 04 42 49 43 58 00 85 12 D0 58 -40 00 00 C0 86 5A 06 42 49 43 58 2E 41 00 85 12 -D0 58 00 00 40 C0 96 5A 06 42 49 43 58 2E 42 00 -85 12 D0 58 40 00 40 C0 A8 5A 04 42 49 53 58 00 -85 12 D0 58 40 00 00 D0 BA 5A 06 42 49 53 58 2E -41 00 85 12 D0 58 00 00 40 D0 CA 5A 06 42 49 53 -58 2E 42 00 85 12 D0 58 40 00 40 D0 6E 52 04 58 -4F 52 58 00 85 12 D0 58 40 00 00 E0 EE 5A 06 58 -4F 52 58 2E 41 00 85 12 D0 58 00 00 40 E0 FE 5A -06 58 4F 52 58 2E 42 00 85 12 D0 58 40 00 40 E0 -70 59 04 41 4E 44 58 00 85 12 D0 58 40 00 00 F0 -22 5B 06 41 4E 44 58 2E 41 00 85 12 D0 58 00 00 -40 F0 32 5B 06 41 4E 44 58 2E 42 00 85 12 D0 58 -40 00 40 F0 0A 40 C4 1D 40 44 74 48 E4 57 B0 58 -3A 40 94 52 D8 59 04 52 52 43 58 00 85 12 54 5B -40 00 00 10 66 5B 06 52 52 43 58 2E 41 00 85 12 -54 5B 00 00 40 10 76 5B 06 52 52 43 58 2E 42 00 -85 12 54 5B 40 00 40 10 88 5B 04 52 52 55 58 00 -85 12 54 5B 40 01 00 10 9A 5B 06 52 52 55 58 2E -41 00 85 12 54 5B 00 01 40 10 AA 5B 06 52 52 55 -58 2E 42 00 85 12 54 5B 40 01 40 10 BC 5B 05 53 -57 50 42 58 85 12 54 5B 40 00 80 10 CE 5B 07 53 -57 50 42 58 2E 41 85 12 54 5B 00 00 80 10 DE 5B -04 52 52 41 58 00 85 12 54 5B 40 00 00 11 F0 5B -06 52 52 41 58 2E 41 00 85 12 54 5B 00 00 40 11 -00 5C 06 52 52 41 58 2E 42 00 85 12 54 5B 40 00 -40 11 12 5C 04 53 58 54 58 00 85 12 54 5B 40 00 -80 11 24 5C 06 53 58 54 58 2E 41 00 85 12 54 5B -00 00 80 11 00 56 05 50 55 53 48 58 85 12 54 5B -40 00 00 12 46 5C 07 50 55 53 48 58 2E 41 85 12 -54 5B 00 00 40 12 56 5C 07 50 55 53 48 58 2E 42 -85 12 54 5B 40 00 40 12 00 00 34 5C 03 52 50 54 -0D 12 84 12 74 48 48 4F 8A 5C 29 4E 7E 40 20 00 -79 90 52 00 06 20 B0 12 F6 4F 03 24 3E D0 80 00 -05 3C B0 12 6C 4F 1E 83 3E F0 0F 00 82 4E 78 5C -3E 4F 3D 41 30 4D D2 C3 23 02 E2 B2 60 02 02 24 -30 40 02 42 1A 52 04 20 19 62 06 20 92 43 14 20 -A2 93 02 20 07 24 0A 5A 49 69 82 4A 16 20 C2 49 -18 20 0A 3C C2 4A 15 20 8A 10 C2 4A 16 20 C2 49 -17 20 89 10 C2 49 18 20 B0 12 3E 5D 5A 53 FC 23 -39 40 05 00 D2 49 14 20 4E 06 82 93 46 06 05 24 -92 B3 6C 06 FD 27 C2 93 4C 06 59 83 F3 2F 19 83 -0B 30 F2 43 4E 06 82 93 46 06 03 24 92 B3 6C 06 -FD 27 5A 92 4C 06 F3 23 30 41 1A 43 E1 3F 19 43 -3A 43 8A 10 C2 4A 4E 06 82 93 46 06 05 24 92 B3 -6C 06 FD 27 C2 93 4C 06 19 83 F3 23 5A 42 4C 06 -30 41 7C 5C 08 52 45 41 44 5F 53 57 58 00 1C D3 -F2 40 51 00 19 20 B0 12 B6 5C 38 20 B0 12 3E 5D -6A 53 04 24 FB 23 D9 42 4C 06 FF 1D F2 43 4E 06 -03 43 19 53 39 90 01 02 F6 23 F2 43 4E 06 3C C0 -03 00 D2 D3 23 02 30 41 34 54 09 57 52 49 54 45 -5F 53 57 58 2C D3 F0 40 58 00 5F C2 B0 12 B6 5C -15 20 3A 40 FE FF 29 43 B0 12 42 5D D2 49 00 1E -4E 06 03 43 19 53 39 90 00 02 F8 23 39 40 03 00 -B0 12 40 5D 7A C0 E1 00 6A 92 D9 27 8C 10 1C 52 -4C 06 D2 D3 23 02 0D 12 84 12 34 43 14 40 0B 3C -20 53 44 20 45 72 72 6F 72 21 0C 5E 2F 83 8F 4E -00 00 B2 40 10 00 DC 1D 0E 4C 84 12 00 45 36 41 -B0 12 9C 41 0E 93 9C 24 E2 B2 60 02 99 20 B2 40 -81 A9 40 06 B2 40 18 00 46 06 D2 D3 25 02 B2 D0 -C0 04 0C 02 92 C3 40 06 39 42 B0 12 40 5D D2 C3 -23 02 2C 42 B2 40 95 00 14 20 B2 40 00 40 18 20 -B0 12 3A 5D 02 24 30 40 EC 5D B0 12 3E 5D 7A 93 -FC 23 B2 40 87 AA 14 20 92 43 16 20 B2 40 00 48 -18 20 B0 12 3A 5D 29 42 B0 12 40 5D 92 43 14 20 -82 43 16 20 78 43 3C 42 B2 40 00 77 18 20 B0 12 -3A 5D B2 40 40 69 18 20 B0 12 F8 5C 03 24 58 83 -F3 23 D9 3F 0C 5C A2 43 16 20 B2 40 00 50 18 20 -B0 12 F8 5C D0 23 92 D3 40 06 82 43 46 06 92 C3 -40 06 09 43 B0 12 6E 5D 38 40 00 1E 92 48 C6 01 -04 20 92 48 C8 01 06 20 5A 48 C2 01 92 43 02 20 -7A 80 06 00 0F 24 7A 82 0D 24 A2 43 02 20 6A 53 -09 24 5A 53 07 24 6A 52 05 24 3A 50 0B 20 0C 4A -30 40 F2 5D 09 43 B0 12 6E 5D D2 48 0D 00 12 20 -19 48 0E 00 82 49 08 20 1A 48 16 00 0A 93 02 20 -1A 48 24 00 82 4A 0A 20 09 5A 82 49 0C 20 09 5A -A2 93 02 20 04 24 82 49 0E 20 39 50 20 00 19 82 -12 20 19 82 12 20 82 49 10 20 92 42 02 20 2C 20 -30 41 B0 12 AA 40 39 40 E0 00 29 83 89 43 38 20 -FC 23 82 43 32 20 30 41 92 4B 0E 00 22 20 92 4B -10 00 24 20 5A 42 23 20 58 42 22 20 92 93 02 20 -08 24 59 42 24 20 89 10 0A 59 88 10 08 58 0A 6A -88 10 08 58 30 41 82 43 1C 20 92 42 0E 20 1A 20 -C2 93 24 20 03 20 92 93 22 20 14 24 92 42 22 20 -D0 04 92 42 24 20 D2 04 92 42 12 20 C8 04 92 42 -E4 04 1A 20 92 42 E6 04 1C 20 92 52 10 20 1A 20 -82 63 1C 20 30 41 92 4B 0E 00 22 20 92 4B 10 00 -24 20 B0 12 A6 5F 5A 4B 03 00 82 5A 1A 20 82 63 -1C 20 30 41 09 93 07 24 F8 90 20 00 00 1E 03 20 -18 53 19 83 F9 23 30 41 1B 42 32 20 82 43 1E 20 -B2 90 00 02 20 20 AB 20 BB 80 00 02 12 00 8B 73 -14 00 DB 53 03 00 DB 92 12 20 03 00 14 28 CB 43 -03 00 B0 12 78 5F 1A 52 08 20 09 43 B0 12 6E 5D -8B 43 10 00 9B 48 00 1E 0E 00 92 93 02 20 03 24 -9B 48 02 1E 10 00 B2 40 00 02 20 20 8B 93 14 00 -0B 20 92 9B 12 00 1E 20 82 2C BB 90 00 02 12 00 -03 2C 92 4B 12 00 20 20 B0 12 E6 5F 1A 42 1A 20 -19 42 1C 20 6C 3E 3C 42 3B 40 38 20 09 43 CB 93 -02 00 10 24 9B 92 24 20 0C 00 04 20 9B 92 22 20 -0A 00 07 24 09 4B 3B 50 1C 00 3B 90 18 21 EF 23 -0C 5C 30 41 0C 43 82 4B 32 20 8B 49 00 00 09 93 -0A 24 99 52 C4 1D 16 00 4A 93 05 34 C9 93 02 00 -02 34 5A 59 02 00 CB 4A 02 00 CB 43 03 00 9B 42 -1A 20 04 00 9B 42 1C 20 06 00 18 42 30 20 8B 48 -08 00 9B 48 1A 1E 0A 00 9B 48 14 1E 0C 00 9B 48 -1A 1E 0E 00 9B 48 14 1E 10 00 9B 48 1C 1E 12 00 -9B 48 1E 1E 14 00 82 43 1E 20 6A 93 5C 27 C9 37 -8B 43 16 00 7A 93 02 24 07 38 95 3F B2 40 1C 21 -CA 40 B2 40 56 43 7A 42 9B 42 C0 1D 18 00 9B 82 -C4 1D 18 00 9B 42 C2 1D 1A 00 9B 52 C4 1D 1A 00 -82 3F CB 43 02 00 2B 4B 82 4B 32 20 0B 93 06 24 -92 4B 16 00 1E 20 B0 12 66 60 22 C3 30 41 1B 42 -32 20 0B 93 FB 27 EB 93 02 00 04 20 B0 12 42 66 -B0 12 0A 66 CB 93 02 00 E4 37 1E 4B 18 00 9F 4B -1A 00 00 00 31 50 06 00 3D 41 B0 12 62 61 02 24 -30 40 4A 43 B2 40 3C 1D CA 40 B2 40 7C 42 7A 42 -30 40 34 43 40 4E 85 52 45 41 44 22 5A 43 19 3C -B4 4C 86 57 52 49 54 45 22 00 6A 43 12 3C A8 4D -84 44 45 4C 22 00 6A 42 0C 3C F8 4A 05 43 4C 4F -53 45 B0 12 7E 61 30 4D 62 4C 85 4C 4F 41 44 22 -7A 43 2F 83 8F 4E 00 00 0E 4A 82 93 BE 1D 0B 24 -0D 12 84 12 0A 40 0A 40 BA 47 BA 47 44 45 0A 40 -36 62 BA 47 C0 44 0D 12 84 12 0A 40 22 00 8C 45 -0A 48 34 62 3D 41 36 4F 0E 56 82 4E 36 20 1C 43 -92 42 2C 20 22 20 92 42 2E 20 24 20 0E 96 8D 24 -F6 90 3A 00 01 00 01 20 26 53 F6 90 5C 00 00 00 -08 20 16 53 92 42 02 20 22 20 82 43 24 20 0E 96 -70 24 82 46 34 20 B0 12 A6 5F 35 40 20 00 A2 93 -02 20 04 24 92 92 22 20 02 20 02 24 15 42 12 20 -B0 12 8C 60 2C 43 0A 43 08 4A 58 0E 08 58 82 48 -30 20 C8 93 00 1E 61 24 39 42 F8 96 00 1E 04 20 -18 53 19 83 FA 23 16 53 F6 90 2E 00 FF FF 19 24 -39 50 03 00 B0 12 04 60 06 20 F6 90 5C 00 FF FF -29 24 0E 96 27 28 16 42 34 20 1A 53 3A 90 10 00 -DB 23 92 53 1A 20 82 63 1C 20 15 83 D1 23 2C 42 -3C 3C F6 90 2E 00 FE FF EE 27 B0 12 04 60 EB 23 -39 40 03 00 F8 96 00 1E 04 20 18 53 19 83 FA 23 -09 3C 0E 96 E0 2F F6 90 5C 00 FF FF DC 23 B0 12 -04 60 D9 23 18 42 30 20 92 48 1A 1E 22 20 92 48 -14 1E 24 20 F8 B0 10 00 0B 1E 14 24 82 93 24 20 -06 20 82 93 22 20 03 20 92 42 02 20 22 20 0E 96 -8E 2F 92 42 22 20 2C 20 92 42 24 20 2E 20 8F 43 -00 00 03 3C 2A 4F B0 12 96 60 35 40 D4 40 36 40 -E2 40 3A 4F 3E 4F 0A 93 04 24 7A 93 3C 20 0C 93 -01 20 30 4D 0D 12 84 12 34 43 14 40 0B 3C 20 4F -70 65 6E 45 72 72 6F 72 3A 40 0A 5E 38 4C 05 5B -50 46 41 5D 2E 53 2E 4E 30 4D EC 61 04 42 4F 4F -54 00 39 40 20 5E 2E 93 01 2C 30 41 E2 B2 60 02 -02 24 10 49 02 00 89 12 3F 40 7E 1C 8F 43 00 00 -82 43 BE 1D B2 40 00 1C 00 1C 31 40 E0 1C 84 12 -14 40 0F 4C 4F 41 44 22 20 42 4F 4F 54 2E 34 54 -48 22 3A 40 A2 48 1A 93 BB 20 0C 93 C3 23 30 4D -C6 61 04 52 45 41 44 00 2F 83 8F 4E 00 00 1E 42 -32 20 B0 12 18 60 1E 82 32 20 30 4D 2C 43 12 12 -2A 20 18 42 02 20 08 58 2A 41 82 9A 0A 20 A6 24 -1A 52 08 20 09 43 B0 12 6E 5D 09 43 28 93 03 24 -89 93 02 1E 03 20 89 93 00 1E 07 24 09 58 39 90 -00 02 F4 23 91 53 00 00 E7 3F 0C 43 6A 41 B9 43 -00 1E 28 93 0F 24 B9 40 FF 0F 02 1E 09 11 8A 10 -09 5A 5A 41 01 00 0A 11 09 10 82 4A 28 20 82 49 -26 20 07 3C 09 11 C2 49 26 20 C2 4A 27 20 82 43 -28 20 3A 41 82 4A 2A 20 30 41 0A 12 1A 52 08 20 -09 43 B0 12 B4 5D 3A 41 1A 52 0C 20 09 43 B0 12 -B4 5D F2 B0 40 00 A2 04 29 20 F2 B0 10 00 A2 04 -FC 27 5A 42 B0 04 4A 11 59 42 B4 04 F2 40 20 00 -C0 04 D2 42 B1 04 C8 04 1A 52 E4 04 D2 42 B5 04 -C8 04 19 52 E4 04 D2 42 B2 04 C0 04 B2 40 00 08 -C8 04 1A 52 E4 04 92 42 B6 04 C0 04 B2 80 BC 07 -C0 04 B2 40 00 02 C8 04 19 52 E4 04 30 41 22 2A -2B 2C 2F 3A 3B 3C 3D 3E 3F 5B 5C 5D 7C 2E 29 92 -06 38 39 80 03 00 B0 12 5E 65 39 40 03 00 7A 4B -C8 4A 00 1E 82 9B 36 20 12 28 0D 12 3D 40 0F 00 -3C 40 0E 65 7A 9C F3 27 1D 83 FC 23 3D 41 6A 9C -E6 27 3A 80 21 00 EB 3B 18 53 19 83 E8 23 09 93 -06 24 F8 40 20 00 00 1E 18 53 19 83 FA 23 30 41 -2A 93 DC 20 2C 93 0E 24 0C 93 AB 24 0D 12 84 12 -14 40 0C 3C 20 57 72 69 74 65 45 72 72 6F 72 00 -3A 40 0A 5E B0 12 1C 64 92 42 26 20 22 20 92 42 -28 20 24 20 B0 12 9A 64 B0 12 8C 60 18 42 30 20 -F8 40 20 00 0B 1E B0 12 B2 64 88 43 0C 1E 88 4A -0E 1E 88 49 10 1E 88 49 12 1E 98 42 24 20 14 1E -98 42 22 20 1A 1E 88 43 1C 1E 88 43 1E 1E 1C 43 -1B 42 34 20 82 9B 36 20 C9 27 FB 90 2E 00 00 00 -C5 27 39 40 0B 00 B0 12 2E 65 B0 12 4C 66 2A 43 -B0 12 96 60 0C 93 BA 23 30 4D 1A 4B 04 00 19 4B -06 00 B0 12 6E 5D B0 12 B2 64 18 4B 08 00 88 49 -12 1E 88 4A 16 1E 88 49 18 1E 98 4B 12 00 1C 1E -98 4B 14 00 1E 1E 1A 4B 04 00 19 4B 06 00 30 40 -B4 5D 9B 52 1E 20 12 00 8B 63 14 00 1A 42 1A 20 -19 42 1C 20 30 40 B4 5D B2 40 00 02 1E 20 1B 42 -32 20 B0 12 42 66 82 43 1E 20 DB 53 03 00 DB 92 -12 20 03 00 25 20 CB 43 03 00 B0 12 78 5F 08 12 -0A 12 B0 12 1C 64 2A 91 08 24 B0 12 9A 64 2A 41 -1A 52 08 20 09 43 B0 12 6E 5D 3A 41 38 41 98 42 -26 20 00 1E 92 93 02 20 03 24 98 42 28 20 02 1E -B0 12 9A 64 9B 42 26 20 0E 00 9B 42 28 20 10 00 -30 40 E6 5F D2 61 05 57 52 49 54 45 B0 12 58 66 -30 4D 58 4B 13 00 59 4B 14 00 89 10 09 58 58 4B -15 00 5B 42 12 20 0A 43 3C 42 08 11 09 10 4A 10 -1C 83 0B 11 FA 2B 0A 11 1C 83 FD 37 1B 42 32 20 -19 5B 0A 00 18 6B 0C 00 8B 49 0E 00 8B 48 10 00 -CB 4A 03 00 1A 4B 12 00 BB C0 FF 01 12 00 3A F0 -FF 01 82 4A 1E 20 B0 12 88 60 30 4D 0C 93 3B 20 -38 90 E0 01 03 2C C8 93 20 1E 02 24 7C 40 E5 00 -C8 4C 00 1E B0 12 4C 66 B0 12 84 5F 82 4A 2A 20 -0B 4A 1A 52 08 20 09 43 B0 12 6E 5D 1A 48 00 1E -88 43 00 1E 92 93 02 20 09 24 19 48 02 1E 88 43 -02 1E 39 F0 FF 0F 39 90 FF 0F 02 20 3A 93 0E 24 -82 4A 22 20 82 49 24 20 B0 12 84 5F 0B 9A E6 27 -0A 12 0A 4B B0 12 9A 64 3A 41 DA 3F 0A 4B B0 12 -9A 64 B0 12 7E 61 30 4D FC 44 08 54 45 52 4D 32 -53 44 22 00 0D 12 84 12 E6 61 0A 40 02 00 28 40 -0A 48 36 62 C6 67 3D 41 0A 43 B0 12 DA 41 92 B3 -DC 05 FD 27 59 42 CC 05 C2 49 CE 05 69 92 0D 24 -CA 49 00 1E 1A 53 3A 90 FF 01 F1 2B 03 24 B0 12 -58 66 EA 3F B0 12 C8 41 EA 3F B0 12 C8 41 82 4A -1E 20 B0 12 7E 61 30 4D -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -02 42 02 42 02 42 02 42 02 42 02 42 02 42 02 42 -96 42 02 42 02 42 02 42 02 42 02 42 02 42 A8 4E -q diff --git a/binaries/MSP_EXP430FR6989_16MHz_115200.txt b/binaries/MSP_EXP430FR6989_16MHz_115200.txt new file mode 100644 index 0000000..5843d58 --- /dev/null +++ b/binaries/MSP_EXP430FR6989_16MHz_115200.txt @@ -0,0 +1,327 @@ +@1800 +80 3E 08 00 A1 F7 18 00 FD FF 35 01 10 00 A1 59 +EE 46 7E 45 84 45 54 45 5E 47 4C 57 04 50 BE 4F +BE 4F D4 46 92 47 5A 47 3C 1D E0 1C B2 49 B6 44 +C4 44 CE 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +5E 47 4C 57 04 50 BE 4F BE 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 12 3D 0E 93 3E 4F +A7 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D2 46 B2 49 +90 47 B2 49 58 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 78 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 5E 47 92 C3 FC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 FC 05 F3 23 +B0 12 D0 44 D8 48 AC 44 52 45 A0 47 1E 44 04 1B +5B 37 6D 00 C2 47 C2 47 1E 44 04 1B 5B 30 6D 00 +C2 47 0E 4D B0 12 7E 45 B2 40 81 00 E0 05 92 42 +02 18 E6 05 92 42 04 18 E8 05 F2 D0 30 00 2A 02 +92 C3 E0 05 92 D3 FA 05 92 C3 30 01 30 41 92 B3 +EA 05 FD 23 30 41 92 12 3E 18 84 12 A0 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 C2 47 26 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 C2 47 0A 44 40 FF 32 44 +EE 48 F2 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 +22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 +66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 +F2 43 26 03 F2 43 22 03 F2 40 A5 00 41 01 F2 40 +10 00 40 01 D2 43 41 01 F2 40 A5 00 61 01 B2 40 +48 00 62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 +61 01 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 +A2 04 39 40 00 08 29 83 89 43 00 1C FC 23 19 42 +9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 +B0 12 D0 44 86 45 00 00 0C 41 43 43 45 50 54 00 +30 40 D4 46 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 +20 00 3B 40 32 47 3C 40 3E 47 5D 15 89 3E 21 52 +3A 17 58 42 EC 05 48 9B 09 20 A2 B3 FC 05 FD 27 +B2 40 13 00 EE 05 D2 D3 22 02 30 41 48 9C 06 2C +78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C +CE 48 00 00 1E 53 A2 B3 FC 05 FD 27 C2 48 EE 05 +30 4D 34 47 2D 83 92 B3 FC 05 DB 23 FC 3F 3E 8F +3D 41 92 B3 FC 05 FD 27 58 42 EC 05 08 4C EB 3F +00 00 06 4B 45 59 30 40 5A 47 30 12 70 47 A2 B3 +FC 05 FD 27 B2 40 11 00 EE 05 D2 C3 22 02 30 41 +2F 83 8F 4E 00 00 92 B3 FC 05 FD 27 B0 12 FA 46 +1E 42 EC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 +92 47 08 4E 3E 4F C7 3F 88 47 08 45 43 48 4F 00 +B2 40 C2 48 2C 47 30 4D 00 00 0C 4E 4F 45 43 48 +4F 00 B2 40 30 4D 2C 47 30 4D 00 00 08 54 59 50 +45 00 0D 12 3D 40 D2 47 29 4F 8F 4E 00 00 7E 49 +DE 3F D4 47 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 5F 22 F9 98 00 00 5C 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 53 22 9B 24 52 47 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 44 00 00 +F2 48 E4 47 36 4A F0 4C B0 44 60 48 14 44 06 5B +54 48 45 4E 5D 00 E8 47 3E 48 04 48 22 48 14 44 +06 5B 45 4C 53 45 5D 00 E8 47 50 48 04 48 20 48 +1E 44 04 5B 49 46 5D 00 E8 47 22 48 B2 44 20 48 +1E 44 05 0D 6B 6F 20 0A C2 47 9A 44 84 44 B2 44 +22 48 10 48 0D 5B 54 48 45 4E 5D 00 30 4D 74 48 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 80 48 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 E4 47 +36 4A 9E 4A 42 4C B2 49 90 48 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 E4 47 36 4A 9E 4A +C2 48 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D C8 46 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D D8 45 05 53 22 00 +82 43 C0 1D 0D 12 84 12 0A 44 1E 44 A0 4C 0A 44 +22 00 36 4A 36 49 B2 40 20 00 C0 1D 1A 53 1A B3 +82 6A C8 1D 3E 4F 3D 41 30 4D AA 47 05 2E 22 00 +0D 12 84 12 20 49 0A 44 C2 47 A0 4C B2 49 00 00 +04 3C 23 00 B2 40 B2 1D B2 1D 30 4D 1C 49 02 23 +1B 42 BE 1D 2C 4F 2F 83 B0 12 46 44 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 6E 49 04 23 +53 00 0D 12 84 12 70 49 AA 49 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 9E 49 04 23 3E 00 9F 42 B2 1D +00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F B8 49 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 9A 47 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +64 49 E4 47 D2 49 A2 49 CE 48 E0 49 BC 49 C2 47 +B2 49 4C 49 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D 24 4A +0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F +29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 +7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C +82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 +09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 +02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E +06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 +3D 40 A8 4B 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F +2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 +5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C +01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 +FC 9C 00 00 E0 23 AE 27 AA 4B 2F 24 2D 83 6A 4C +7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 +7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 +02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +00 00 0E 4B 2C 15 B0 12 3E 44 2A 17 E8 3F 9F 4F +04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 +00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 +04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 +BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 +01 20 2F 53 30 4D 60 49 03 5C 92 42 C2 1D C6 1D +30 4D 0D 12 84 12 84 44 E4 47 36 4A B0 44 7A 4D +9E 4A 64 4C 0A 4E 3E 4F 3D 40 7E 4C 6D 27 3D 40 +58 4C 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 80 4C +3E 4F 3D 40 58 4C 19 20 DE 53 00 00 68 4E 08 5E +F8 40 3F 00 00 00 3D 40 56 4E 2A 3C 48 4C 02 2C +A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D +9E 4C 0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 +09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A 44 00 00 +8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +8A 4E 02 00 EE 3F 30 4D DA 49 0A 43 4F 55 4E 54 +2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D 00 49 +0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 +80 1C 0E 43 84 12 1E 44 02 0D 0A 00 C2 47 94 44 +52 4C E0 48 0A 49 1E 44 0B 73 74 61 63 6B 20 65 +6D 70 74 79 08 45 32 44 0A 44 40 FF 12 49 1E 44 +09 46 52 41 4D 20 66 75 6C 6C 08 45 B2 44 16 4D +00 4D 0D 41 42 4F 52 54 22 00 0D 12 84 12 20 49 +0A 44 08 45 A0 4C B2 49 30 4A 02 27 0D 12 84 12 +E4 47 36 4A 9E 4A B0 44 7C 4D 44 49 88 4C AA 48 +07 5B 27 5D 0D 12 84 12 6C 4D 0A 44 0A 44 A0 4C +A0 4C B2 49 80 4D 03 5B 82 43 BC 1D 30 4D 00 00 +02 5D B2 43 BC 1D 30 4D F8 48 11 50 4F 53 54 50 +4F 4E 45 00 0D 12 84 12 E4 47 36 4A 9E 4A B0 44 +7C 4D 0A 49 AC 44 D4 4D 0A 44 0A 44 A0 4C A0 4C +0A 44 A0 4C A0 4C B2 49 00 00 02 3A 30 12 2A 4E +92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 E4 47 36 4A +F2 4D 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E +5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F +BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF +BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D +66 25 84 12 1E 44 0F 73 74 61 63 6B 20 6D 69 73 +6D 61 74 63 68 21 12 45 96 4D 03 3B 82 93 BC 1D +F4 26 0D 12 84 12 0A 44 B2 49 A0 4C 3C 4E 98 4D +B2 49 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +B4 1D D8 D3 00 00 30 4D EA 4C 0C 43 52 45 41 54 +45 00 B0 12 E0 4D BA 40 86 12 FC FF 8A 4A FE FF +3A 3D BC 47 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 +85 12 00 00 8A 4D 02 00 3D 41 30 4D DA 4D 0E 3A +4E 4F 4E 41 4D 45 30 12 2A 4E 2F 83 8F 4E 00 00 +1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +98 3F 74 4E 05 49 53 00 0D 12 82 93 BC 1D 08 20 +84 12 6C 4D F6 4E 3D 41 BE 4F 02 00 3E 4F 30 4D +84 12 84 4D 0A 44 F8 4E A0 4C B2 49 8A 4E 08 43 +4F 44 45 00 B0 12 E0 4D A2 82 C8 1D 61 3C CC 49 +0E 48 44 4E 43 4F 44 45 B2 40 E4 4F CC 1D F2 3F +00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 3C 4E +42 4F 3D 41 92 42 D0 1D CC 1D 5D 3C 0E 4F 0E 43 +4F 44 45 4E 4E 4D 30 12 18 4F B7 3F 00 00 0A 43 +4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 +84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 +0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F +20 4F 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D +8A 4A FE FF 82 43 BC 1D B9 3F AC 4F B2 40 BE 4F +D0 1D 82 4E CE 1D 30 40 44 49 85 12 AA 4F AA 4D +52 4D 3C 50 4E 4F A4 4E EE 49 98 4A 6A 4D 92 4F +E4 4E BE 4E 5A 4E B2 4C C6 50 F0 4A 00 00 00 00 +85 12 AA 4F 40 57 C4 55 24 57 EC 54 48 55 96 55 +72 56 7E 56 0E 54 32 55 00 00 00 00 80 4F FE 52 +00 00 9A 56 DE 4F B2 40 BE 4F CE 1D 82 43 D0 1D +30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 +30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D +3A 40 42 18 B0 12 12 50 30 4D 24 50 0E 52 53 54 +5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 +12 50 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 +18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 +2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 +29 83 B9 43 80 FF FC 23 B9 40 06 46 FE FF 29 83 +B9 40 F2 45 FE FF 39 90 AE FF F9 23 39 40 10 18 +B2 49 E4 FF 3B 40 10 00 3A 40 3A 18 B0 12 16 50 +82 43 4A 18 C7 3F B8 50 B2 4E 42 18 BE 12 3E 4F +3D 41 C0 3F A0 4D 0C 4D 41 52 4B 45 52 00 12 12 +C6 1D 0D 12 84 12 E4 47 36 4A 9E 4A AC 44 E4 50 +D8 48 78 4C E6 50 3E 4F 3D 41 B2 41 C6 1D B0 12 +E0 4D BA 40 85 12 FC FF BA 40 B6 50 FE FF 28 83 +8A 48 00 00 BA 40 82 44 02 00 A2 52 C8 1D 18 42 +B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D +12 12 C6 1D 84 12 36 4A 9E 4A AC 44 50 51 30 51 +3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C +BE 90 B6 50 00 00 01 20 3E 52 2E 83 21 53 30 41 +48 4B AC 44 58 51 4C 51 5A 51 B2 41 C6 1D 30 41 +92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 20 51 +15 20 3E 40 2B 00 B0 12 20 51 06 20 3E 40 2D 00 +B0 12 20 51 92 83 C6 1D 0E 12 1E 41 02 00 84 12 +36 4A 48 4B AC 44 7C 4D 9A 51 3E 51 3A 17 30 41 +B0 12 60 51 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D +3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 +36 4A 48 4B AC 44 D2 51 CA 51 3E 90 10 00 E6 2B +7C 2D D4 51 A2 41 C6 1D E1 3F 03 20 B0 12 B8 51 +43 3C 7A 90 23 00 24 20 B0 12 68 51 3C 40 00 03 +0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 +2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 +3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 +19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D +7A 90 26 00 05 20 3C 40 10 02 B0 12 68 51 F0 3F +7A 90 40 00 14 20 3C 40 20 00 B0 12 B4 51 0C 20 +3C D0 10 00 3E 40 2B 00 B0 12 B8 51 92 92 C2 1D +C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 +10 00 B0 12 A0 51 F2 3F 03 20 B0 12 B8 51 F5 3F +7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 +B0 12 A0 51 EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D +3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 +5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 +30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 0A 44 +00 13 A0 4C B2 49 0A 44 2C 00 96 52 DA 51 E4 47 +A0 52 78 52 E6 52 3D 41 2C DE 8B 4C 00 00 9E 3F +00 00 06 4D 4F 56 85 12 D6 52 00 40 F2 52 0A 4D +4F 56 2E 42 85 12 D6 52 40 40 00 00 06 41 44 44 +85 12 D6 52 00 50 0C 53 0A 41 44 44 2E 42 85 12 +D6 52 40 50 18 53 08 41 44 44 43 00 85 12 D6 52 +00 60 26 53 0C 41 44 44 43 2E 42 00 85 12 D6 52 +40 60 5E 4F 08 53 55 42 43 00 85 12 D6 52 00 70 +44 53 0C 53 55 42 43 2E 42 00 85 12 D6 52 40 70 +52 53 06 53 55 42 85 12 D6 52 00 80 62 53 0A 53 +55 42 2E 42 85 12 D6 52 40 80 6E 53 06 43 4D 50 +85 12 D6 52 00 90 7C 53 0A 43 4D 50 2E 42 85 12 +D6 52 40 90 00 00 08 44 41 44 44 00 85 12 D6 52 +00 A0 96 53 0C 44 41 44 44 2E 42 00 85 12 D6 52 +40 A0 C4 52 06 42 49 54 85 12 D6 52 00 B0 B4 53 +0A 42 49 54 2E 42 85 12 D6 52 40 B0 C0 53 06 42 +49 43 85 12 D6 52 00 C0 CE 53 0A 42 49 43 2E 42 +85 12 D6 52 40 C0 DA 53 06 42 49 53 85 12 D6 52 +00 D0 E8 53 0A 42 49 53 2E 42 85 12 D6 52 40 D0 +00 00 06 58 4F 52 85 12 D6 52 00 E0 02 54 0A 58 +4F 52 2E 42 85 12 D6 52 40 E0 34 53 06 41 4E 44 +85 12 D6 52 00 F0 1C 54 0A 41 4E 44 2E 42 85 12 +D6 52 40 F0 E4 47 96 52 DA 51 3C 54 0A 4C 3C F0 +70 00 8A 10 3A F0 0F 00 0C DA 4D 3F F4 53 06 52 +52 43 85 12 34 54 00 10 4E 54 0A 52 52 43 2E 42 +85 12 34 54 40 10 88 53 08 53 57 50 42 00 85 12 +34 54 80 10 5A 54 06 52 52 41 85 12 34 54 00 11 +76 54 0A 52 52 41 2E 42 85 12 34 54 40 11 68 54 +06 53 58 54 85 12 34 54 80 11 00 00 08 50 55 53 +48 00 85 12 34 54 00 12 9C 54 0C 50 55 53 48 2E +42 00 85 12 34 54 40 12 90 54 08 43 41 4C 4C 00 +85 12 34 54 80 12 1A 53 0E 4A 84 12 26 4A 1E 44 +0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 12 45 +BA 54 06 53 3E 3D 86 12 00 38 E2 54 04 53 3C 00 +86 12 00 34 AA 54 06 30 3E 3D 86 12 00 30 F6 54 +04 30 3C 00 86 12 00 30 32 4F 04 55 3C 00 86 12 +00 2C 0A 55 06 55 3E 3D 86 12 00 28 00 55 06 30 +3C 3E 86 12 00 24 1E 55 04 30 3D 00 86 12 00 20 +00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 +C8 1D 0E 4A 30 4D A4 53 08 54 48 45 4E 00 1A 42 +C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 +00 02 B2 2F 88 DA 00 00 30 4D 14 55 08 45 4C 53 +45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D +2F 83 8F 4A 00 00 E3 3F 82 54 0A 42 45 47 49 4E +30 40 32 44 6C 55 0A 55 4E 54 49 4C 3A 4F 08 4E +3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE +8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D +30 4D 28 54 0A 41 47 41 49 4E 0A 4E 38 40 00 3C +E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 36 55 +CC 48 B2 49 8A 55 0C 52 45 50 45 41 54 00 0D 12 +84 12 CA 55 4E 55 B2 49 FA 55 3D 41 08 4E 3E 4F +2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D +E6 55 06 42 57 31 85 12 F8 55 00 00 12 56 06 42 +57 32 85 12 F8 55 00 00 1E 56 06 42 57 33 85 12 +F8 55 00 00 36 56 3D 41 1A 42 C8 1D 28 4E 8E 43 +00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D +8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 +34 56 00 00 5A 56 06 46 57 32 85 12 34 56 00 00 +66 56 06 46 57 33 85 12 34 56 00 00 D4 55 08 47 +4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 +84 12 6C 4D 78 4C B2 49 00 00 0A 3F 47 4F 54 4F +3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 +3E E0 00 08 EC 3F A0 52 0A 44 2C 00 36 4A 48 4B +AC 44 7C 4D E4 47 96 52 78 52 CC 56 0A 4E 3E 4F +1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 +0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 +EA 2E 8A 10 5A 06 A8 3E 2A 56 08 52 52 43 4D 00 +85 12 B6 56 50 00 FA 56 08 52 52 41 4D 00 85 12 +B6 56 50 01 08 57 08 52 4C 41 4D 00 85 12 B6 56 +50 02 16 57 08 52 52 55 4D 00 85 12 B6 56 50 03 +28 55 0A 50 55 53 48 4D 85 12 B6 56 00 15 32 57 +08 50 4F 50 4D 00 85 12 B6 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 EE 46 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 06 46 +q diff --git a/binaries/MSP_EXP430FR6989_16MHz_4MBds.txt b/binaries/MSP_EXP430FR6989_16MHz_4MBds.txt new file mode 100644 index 0000000..5ba8482 --- /dev/null +++ b/binaries/MSP_EXP430FR6989_16MHz_4MBds.txt @@ -0,0 +1,327 @@ +@1800 +80 3E 04 00 00 00 18 00 FD FF 35 01 10 00 A1 59 +EE 46 7E 45 84 45 54 45 5E 47 4C 57 04 50 BE 4F +BE 4F D4 46 92 47 5A 47 3C 1D E0 1C B2 49 B6 44 +C4 44 CE 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +5E 47 4C 57 04 50 BE 4F BE 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 12 3D 0E 93 3E 4F +A7 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D2 46 B2 49 +90 47 B2 49 58 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 78 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 5E 47 92 C3 FC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 FC 05 F3 23 +B0 12 D0 44 D8 48 AC 44 52 45 A0 47 1E 44 04 1B +5B 37 6D 00 C2 47 C2 47 1E 44 04 1B 5B 30 6D 00 +C2 47 0E 4D B0 12 7E 45 B2 40 81 00 E0 05 92 42 +02 18 E6 05 92 42 04 18 E8 05 F2 D0 30 00 2A 02 +92 C3 E0 05 92 D3 FA 05 92 C3 30 01 30 41 92 B3 +EA 05 FD 23 30 41 92 12 3E 18 84 12 A0 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 C2 47 26 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 C2 47 0A 44 40 FF 32 44 +EE 48 F2 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 +22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 +66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 +F2 43 26 03 F2 43 22 03 F2 40 A5 00 41 01 F2 40 +10 00 40 01 D2 43 41 01 F2 40 A5 00 61 01 B2 40 +48 00 62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 +61 01 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 +FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 +A2 04 39 40 00 08 29 83 89 43 00 1C FC 23 19 42 +9E 01 1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 +B0 12 D0 44 86 45 00 00 0C 41 43 43 45 50 54 00 +30 40 D4 46 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 +20 00 3B 40 32 47 3C 40 3E 47 5D 15 89 3E 21 52 +3A 17 58 42 EC 05 48 9B 09 20 A2 B3 FC 05 FD 27 +B2 40 13 00 EE 05 D2 D3 22 02 30 41 48 9C 06 2C +78 92 11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C +CE 48 00 00 1E 53 A2 B3 FC 05 FD 27 C2 48 EE 05 +30 4D 34 47 2D 83 92 B3 FC 05 DB 23 FC 3F 3E 8F +3D 41 92 B3 FC 05 FD 27 58 42 EC 05 08 4C EB 3F +00 00 06 4B 45 59 30 40 5A 47 30 12 70 47 A2 B3 +FC 05 FD 27 B2 40 11 00 EE 05 D2 C3 22 02 30 41 +2F 83 8F 4E 00 00 92 B3 FC 05 FD 27 B0 12 FA 46 +1E 42 EC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 +92 47 08 4E 3E 4F C7 3F 88 47 08 45 43 48 4F 00 +B2 40 C2 48 2C 47 30 4D 00 00 0C 4E 4F 45 43 48 +4F 00 B2 40 30 4D 2C 47 30 4D 00 00 08 54 59 50 +45 00 0D 12 3D 40 D2 47 29 4F 8F 4E 00 00 7E 49 +DE 3F D4 47 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +3E 4F 5F 22 F9 98 00 00 5C 22 19 53 1C 83 FA 23 +2D 53 30 4D 2F 53 3E 4F 1E 83 53 22 9B 24 52 47 +0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 44 00 00 +F2 48 E4 47 36 4A F0 4C B0 44 60 48 14 44 06 5B +54 48 45 4E 5D 00 E8 47 3E 48 04 48 22 48 14 44 +06 5B 45 4C 53 45 5D 00 E8 47 50 48 04 48 20 48 +1E 44 04 5B 49 46 5D 00 E8 47 22 48 B2 44 20 48 +1E 44 05 0D 6B 6F 20 0A C2 47 9A 44 84 44 B2 44 +22 48 10 48 0D 5B 54 48 45 4E 5D 00 30 4D 74 48 +09 5B 49 46 5D 00 0E 93 3E 4F C6 27 30 4D 80 48 +13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 E4 47 +36 4A 9E 4A 42 4C B2 49 90 48 17 5B 55 4E 44 45 +46 49 4E 45 44 5D 0D 12 84 12 E4 47 36 4A 9E 4A +C2 48 3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 +8F 4E 00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D +8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F +3E E3 1E 53 30 4D 00 00 02 40 2E 4E 30 4D C8 46 +02 21 BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 +30 4D 3E 8F 01 28 0E F3 30 4D D8 45 05 53 22 00 +82 43 C0 1D 0D 12 84 12 0A 44 1E 44 A0 4C 0A 44 +22 00 36 4A 36 49 B2 40 20 00 C0 1D 1A 53 1A B3 +82 6A C8 1D 3E 4F 3D 41 30 4D AA 47 05 2E 22 00 +0D 12 84 12 20 49 0A 44 C2 47 A0 4C B2 49 00 00 +04 3C 23 00 B2 40 B2 1D B2 1D 30 4D 1C 49 02 23 +1B 42 BE 1D 2C 4F 2F 83 B0 12 46 44 BF 4F 00 00 +7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 +B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 6E 49 04 23 +53 00 0D 12 84 12 70 49 AA 49 2D 83 09 DE 09 93 +E1 23 3D 41 30 4D 9E 49 04 23 3E 00 9F 42 B2 1D +00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C +44 00 4A 4E 3E 4F DB 3F B8 49 08 53 49 47 4E 00 +0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 9A 47 04 55 +2E 00 0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 +06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 +64 49 E4 47 D2 49 A2 49 CE 48 E0 49 BC 49 C2 47 +B2 49 4C 49 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 +08 57 4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 +38 5C 2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 +C0 1D F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 +0B 43 CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 +1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B +F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E +CE 4A 00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 +0C 4E 3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 +78 F0 0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 +F2 27 09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 +01 00 F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 +6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 30 4D 24 4A +0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F +29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 +7A 80 07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C +82 49 E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 +09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 +02 00 8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E +06 00 08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 +3D 40 A8 4B 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F +2B 43 7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 +5A 93 0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C +01 00 6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 +FC 9C 00 00 E0 23 AE 27 AA 4B 2F 24 2D 83 6A 4C +7A 90 5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 +7A 80 2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 +02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +00 00 0E 4B 2C 15 B0 12 3E 44 2A 17 E8 3F 9F 4F +04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 +00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 +04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 +BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 +01 20 2F 53 30 4D 60 49 03 5C 92 42 C2 1D C6 1D +30 4D 0D 12 84 12 84 44 E4 47 36 4A B0 44 7A 4D +9E 4A 64 4C 0A 4E 3E 4F 3D 40 7E 4C 6D 27 3D 40 +58 4C 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 80 4C +3E 4F 3D 40 58 4C 19 20 DE 53 00 00 68 4E 08 5E +F8 40 3F 00 00 00 3D 40 56 4E 2A 3C 48 4C 02 2C +A2 53 C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D +9E 4C 0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 +09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A 44 00 00 +8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +8A 4E 02 00 EE 3F 30 4D DA 49 0A 43 4F 55 4E 54 +2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D 00 49 +0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 +80 1C 0E 43 84 12 1E 44 02 0D 0A 00 C2 47 94 44 +52 4C E0 48 0A 49 1E 44 0B 73 74 61 63 6B 20 65 +6D 70 74 79 08 45 32 44 0A 44 40 FF 12 49 1E 44 +09 46 52 41 4D 20 66 75 6C 6C 08 45 B2 44 16 4D +00 4D 0D 41 42 4F 52 54 22 00 0D 12 84 12 20 49 +0A 44 08 45 A0 4C B2 49 30 4A 02 27 0D 12 84 12 +E4 47 36 4A 9E 4A B0 44 7C 4D 44 49 88 4C AA 48 +07 5B 27 5D 0D 12 84 12 6C 4D 0A 44 0A 44 A0 4C +A0 4C B2 49 80 4D 03 5B 82 43 BC 1D 30 4D 00 00 +02 5D B2 43 BC 1D 30 4D F8 48 11 50 4F 53 54 50 +4F 4E 45 00 0D 12 84 12 E4 47 36 4A 9E 4A B0 44 +7C 4D 0A 49 AC 44 D4 4D 0A 44 0A 44 A0 4C A0 4C +0A 44 A0 4C A0 4C B2 49 00 00 02 3A 30 12 2A 4E +92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 E4 47 36 4A +F2 4D 3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E +5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F +BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF +BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D +66 25 84 12 1E 44 0F 73 74 61 63 6B 20 6D 69 73 +6D 61 74 63 68 21 12 45 96 4D 03 3B 82 93 BC 1D +F4 26 0D 12 84 12 0A 44 B2 49 A0 4C 3C 4E 98 4D +B2 49 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +B4 1D D8 D3 00 00 30 4D EA 4C 0C 43 52 45 41 54 +45 00 B0 12 E0 4D BA 40 86 12 FC FF 8A 4A FE FF +3A 3D BC 47 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 +85 12 00 00 8A 4D 02 00 3D 41 30 4D DA 4D 0E 3A +4E 4F 4E 41 4D 45 30 12 2A 4E 2F 83 8F 4E 00 00 +1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +98 3F 74 4E 05 49 53 00 0D 12 82 93 BC 1D 08 20 +84 12 6C 4D F6 4E 3D 41 BE 4F 02 00 3E 4F 30 4D +84 12 84 4D 0A 44 F8 4E A0 4C B2 49 8A 4E 08 43 +4F 44 45 00 B0 12 E0 4D A2 82 C8 1D 61 3C CC 49 +0E 48 44 4E 43 4F 44 45 B2 40 E4 4F CC 1D F2 3F +00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 3C 4E +42 4F 3D 41 92 42 D0 1D CC 1D 5D 3C 0E 4F 0E 43 +4F 44 45 4E 4E 4D 30 12 18 4F B7 3F 00 00 0A 43 +4F 4C 4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 +84 12 02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 +0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F +20 4F 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D +8A 4A FE FF 82 43 BC 1D B9 3F AC 4F B2 40 BE 4F +D0 1D 82 4E CE 1D 30 40 44 49 85 12 AA 4F AA 4D +52 4D 3C 50 4E 4F A4 4E EE 49 98 4A 6A 4D 92 4F +E4 4E BE 4E 5A 4E B2 4C C6 50 F0 4A 00 00 00 00 +85 12 AA 4F 40 57 C4 55 24 57 EC 54 48 55 96 55 +72 56 7E 56 0E 54 32 55 00 00 00 00 80 4F FE 52 +00 00 9A 56 DE 4F B2 40 BE 4F CE 1D 82 43 D0 1D +30 4D 3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 +30 41 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D +3A 40 42 18 B0 12 12 50 30 4D 24 50 0E 52 53 54 +5F 52 45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 +12 50 1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 +18 48 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 +2A 4A 0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 +29 83 B9 43 80 FF FC 23 B9 40 06 46 FE FF 29 83 +B9 40 F2 45 FE FF 39 90 AE FF F9 23 39 40 10 18 +B2 49 E4 FF 3B 40 10 00 3A 40 3A 18 B0 12 16 50 +82 43 4A 18 C7 3F B8 50 B2 4E 42 18 BE 12 3E 4F +3D 41 C0 3F A0 4D 0C 4D 41 52 4B 45 52 00 12 12 +C6 1D 0D 12 84 12 E4 47 36 4A 9E 4A AC 44 E4 50 +D8 48 78 4C E6 50 3E 4F 3D 41 B2 41 C6 1D B0 12 +E0 4D BA 40 85 12 FC FF BA 40 B6 50 FE FF 28 83 +8A 48 00 00 BA 40 82 44 02 00 A2 52 C8 1D 18 42 +B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D +12 12 C6 1D 84 12 36 4A 9E 4A AC 44 50 51 30 51 +3C 4E 3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C +BE 90 B6 50 00 00 01 20 3E 52 2E 83 21 53 30 41 +48 4B AC 44 58 51 4C 51 5A 51 B2 41 C6 1D 30 41 +92 83 C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 20 51 +15 20 3E 40 2B 00 B0 12 20 51 06 20 3E 40 2D 00 +B0 12 20 51 92 83 C6 1D 0E 12 1E 41 02 00 84 12 +36 4A 48 4B AC 44 7C 4D 9A 51 3E 51 3A 17 30 41 +B0 12 60 51 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D +3E 40 29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 +36 4A 48 4B AC 44 D2 51 CA 51 3E 90 10 00 E6 2B +7C 2D D4 51 A2 41 C6 1D E1 3F 03 20 B0 12 B8 51 +43 3C 7A 90 23 00 24 20 B0 12 68 51 3C 40 00 03 +0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 +2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 +3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 +19 42 C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D +7A 90 26 00 05 20 3C 40 10 02 B0 12 68 51 F0 3F +7A 90 40 00 14 20 3C 40 20 00 B0 12 B4 51 0C 20 +3C D0 10 00 3E 40 2B 00 B0 12 B8 51 92 92 C2 1D +C6 1D 02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 +10 00 B0 12 A0 51 F2 3F 03 20 B0 12 B8 51 F5 3F +7A 90 26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 +B0 12 A0 51 EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D +3A 40 20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 +5A 49 FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 +30 4D 00 00 08 52 45 54 49 00 0D 12 84 12 0A 44 +00 13 A0 4C B2 49 0A 44 2C 00 96 52 DA 51 E4 47 +A0 52 78 52 E6 52 3D 41 2C DE 8B 4C 00 00 9E 3F +00 00 06 4D 4F 56 85 12 D6 52 00 40 F2 52 0A 4D +4F 56 2E 42 85 12 D6 52 40 40 00 00 06 41 44 44 +85 12 D6 52 00 50 0C 53 0A 41 44 44 2E 42 85 12 +D6 52 40 50 18 53 08 41 44 44 43 00 85 12 D6 52 +00 60 26 53 0C 41 44 44 43 2E 42 00 85 12 D6 52 +40 60 5E 4F 08 53 55 42 43 00 85 12 D6 52 00 70 +44 53 0C 53 55 42 43 2E 42 00 85 12 D6 52 40 70 +52 53 06 53 55 42 85 12 D6 52 00 80 62 53 0A 53 +55 42 2E 42 85 12 D6 52 40 80 6E 53 06 43 4D 50 +85 12 D6 52 00 90 7C 53 0A 43 4D 50 2E 42 85 12 +D6 52 40 90 00 00 08 44 41 44 44 00 85 12 D6 52 +00 A0 96 53 0C 44 41 44 44 2E 42 00 85 12 D6 52 +40 A0 C4 52 06 42 49 54 85 12 D6 52 00 B0 B4 53 +0A 42 49 54 2E 42 85 12 D6 52 40 B0 C0 53 06 42 +49 43 85 12 D6 52 00 C0 CE 53 0A 42 49 43 2E 42 +85 12 D6 52 40 C0 DA 53 06 42 49 53 85 12 D6 52 +00 D0 E8 53 0A 42 49 53 2E 42 85 12 D6 52 40 D0 +00 00 06 58 4F 52 85 12 D6 52 00 E0 02 54 0A 58 +4F 52 2E 42 85 12 D6 52 40 E0 34 53 06 41 4E 44 +85 12 D6 52 00 F0 1C 54 0A 41 4E 44 2E 42 85 12 +D6 52 40 F0 E4 47 96 52 DA 51 3C 54 0A 4C 3C F0 +70 00 8A 10 3A F0 0F 00 0C DA 4D 3F F4 53 06 52 +52 43 85 12 34 54 00 10 4E 54 0A 52 52 43 2E 42 +85 12 34 54 40 10 88 53 08 53 57 50 42 00 85 12 +34 54 80 10 5A 54 06 52 52 41 85 12 34 54 00 11 +76 54 0A 52 52 41 2E 42 85 12 34 54 40 11 68 54 +06 53 58 54 85 12 34 54 80 11 00 00 08 50 55 53 +48 00 85 12 34 54 00 12 9C 54 0C 50 55 53 48 2E +42 00 85 12 34 54 40 12 90 54 08 43 41 4C 4C 00 +85 12 34 54 80 12 1A 53 0E 4A 84 12 26 4A 1E 44 +0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 12 45 +BA 54 06 53 3E 3D 86 12 00 38 E2 54 04 53 3C 00 +86 12 00 34 AA 54 06 30 3E 3D 86 12 00 30 F6 54 +04 30 3C 00 86 12 00 30 32 4F 04 55 3C 00 86 12 +00 2C 0A 55 06 55 3E 3D 86 12 00 28 00 55 06 30 +3C 3E 86 12 00 24 1E 55 04 30 3D 00 86 12 00 20 +00 00 04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 +C8 1D 0E 4A 30 4D A4 53 08 54 48 45 4E 00 1A 42 +C8 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 +00 02 B2 2F 88 DA 00 00 30 4D 14 55 08 45 4C 53 +45 00 1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D +2F 83 8F 4A 00 00 E3 3F 82 54 0A 42 45 47 49 4E +30 40 32 44 6C 55 0A 55 4E 54 49 4C 3A 4F 08 4E +3E 4F 19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE +8B 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D +30 4D 28 54 0A 41 47 41 49 4E 0A 4E 38 40 00 3C +E7 3F 00 00 0A 57 48 49 4C 45 0D 12 84 12 36 55 +CC 48 B2 49 8A 55 0C 52 45 50 45 41 54 00 0D 12 +84 12 CA 55 4E 55 B2 49 FA 55 3D 41 08 4E 3E 4F +2A 48 B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D +E6 55 06 42 57 31 85 12 F8 55 00 00 12 56 06 42 +57 32 85 12 F8 55 00 00 1E 56 06 42 57 33 85 12 +F8 55 00 00 36 56 3D 41 1A 42 C8 1D 28 4E 8E 43 +00 00 B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D +8E 4A 00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 +34 56 00 00 5A 56 06 46 57 32 85 12 34 56 00 00 +66 56 06 46 57 33 85 12 34 56 00 00 D4 55 08 47 +4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 +84 12 6C 4D 78 4C B2 49 00 00 0A 3F 47 4F 54 4F +3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 +3E E0 00 08 EC 3F A0 52 0A 44 2C 00 36 4A 48 4B +AC 44 7C 4D E4 47 96 52 78 52 CC 56 0A 4E 3E 4F +1A 83 F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 +0C 8A 08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 +EA 2E 8A 10 5A 06 A8 3E 2A 56 08 52 52 43 4D 00 +85 12 B6 56 50 00 FA 56 08 52 52 41 4D 00 85 12 +B6 56 50 01 08 57 08 52 4C 41 4D 00 85 12 B6 56 +50 02 16 57 08 52 52 55 4D 00 85 12 B6 56 50 03 +28 55 0A 50 55 53 48 4D 85 12 B6 56 00 15 32 57 +08 50 4F 50 4D 00 85 12 B6 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 EE 46 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 06 46 +q diff --git a/binaries/MSP_EXP430FR6989_16MHz_I2C.txt b/binaries/MSP_EXP430FR6989_16MHz_I2C.txt index 37c93ab..d5ffa6b 100644 --- a/binaries/MSP_EXP430FR6989_16MHz_I2C.txt +++ b/binaries/MSP_EXP430FR6989_16MHz_I2C.txt @@ -1,337 +1,325 @@ @1800 -80 3E 12 00 00 00 F8 00 F9 FF 0E 58 F0 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 82 46 0E 58 -F0 4F 70 46 80 47 FE 46 DA 46 3C 1D 4E 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +80 3E 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +E8 46 56 45 56 45 58 45 44 45 28 57 E0 4F 9A 4F +9A 4F D6 46 5A 47 32 47 3C 1D E0 1C 8E 49 B6 44 +C4 44 AA 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 28 57 E0 4F 9A 4F 9A 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 6E 46 B2 49 7E 47 B2 49 FC 46 B2 49 D8 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D CE 47 16 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 -C4 48 96 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 47 8E 48 4A 47 -14 44 04 1B 5B 30 6D 00 4A 47 16 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 B0 12 -8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 07 0D -0A 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 C4 48 -0A 44 23 00 FA 46 C4 48 14 44 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 47 0A 44 40 FF 28 44 C2 47 8E 48 -14 44 0A 62 79 74 65 73 20 66 72 65 65 00 3A 44 -7E 45 00 00 06 41 43 43 45 50 54 00 30 40 70 46 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 46 2F 83 8F 4E 00 00 -58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 46 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 46 -04 45 43 48 4F 00 B2 40 C2 48 08 47 82 43 DE 1D -38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 47 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 47 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 46 68 47 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 80 47 -0D 12 84 12 14 44 02 0D 0A 00 4A 47 4E 48 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 46 01 40 2E 4E -30 4D CC 47 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 47 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 48 02 23 53 00 0D 12 84 12 -0A 48 44 48 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 48 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 47 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 47 -3C 48 EE 44 7C 48 58 48 4A 47 02 4C FA 46 4E 48 -2C 47 01 2E 0E 93 E3 37 38 43 E2 3F 76 48 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 48 4B -0A 44 22 00 1A 49 E8 48 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 48 -82 2E 22 00 0D 12 84 12 D2 48 0A 44 4A 47 48 4B -4E 48 F8 45 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C 4A 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 4A 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 4B 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 48 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 44 02 4C 1A 49 BE 4B 9C 26 -3D 40 C6 4B DE 3E C8 4B 0A 4E 3E 4F 3D 40 E2 4B -36 27 3D 40 B8 4B 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 4B 3E 4F 3D 40 B8 4B BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 4D CC 3F -EC 4B 86 12 20 00 D4 47 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C 47 BC 44 -B2 4B B2 47 E4 47 14 44 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 EC 47 -14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 45 -3A 44 2C 4C 08 4C 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 48 0A 44 2A 45 48 4B 4E 48 7C 49 01 27 -0D 12 84 12 02 4C 1A 49 82 49 34 44 00 4C 4E 48 -00 00 83 5B 27 5D 0D 12 84 12 80 4C 0A 44 0A 44 -48 4B 48 4B 4E 48 92 4C 81 5B 82 43 BE 1D 30 4D -FA 47 01 5D B2 43 BE 1D 30 4D B2 4C 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 4C 1A 49 82 49 96 47 34 44 -00 4C E4 47 34 44 F4 4C 0A 44 0A 44 48 4B 48 4B -0A 44 48 4B 48 4B 4E 48 A8 4C 01 3A 30 12 44 4D -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 4C 1A 49 -12 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 45 FA 4C 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 44 4E 48 48 4B 56 4D AA 4C 4E 48 -A8 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 4B 06 43 52 45 41 54 -45 00 B0 12 00 4D BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 4D 04 43 4F 44 45 00 B0 12 00 4D A2 82 -C6 1D 0D 12 84 12 F2 4F CC 4F 4E 48 A2 4D 07 48 -44 4E 43 4F 44 45 B2 40 D0 4F DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 4D 0C 50 -2A 50 4E 48 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C 50 2A 50 4E 48 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 9A 4F -48 4B AA 4C E2 4D 4E 48 88 4D 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 4E 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 44 00 00 C6 47 02 4C 1A 49 98 4B -8E 47 34 44 02 4F 9C 47 14 44 06 5B 54 48 45 4E -5D 00 74 4E DC 4E 98 4E BA 4E 4E 48 9C 47 14 44 -06 5B 45 4C 53 45 5D 00 74 4E F2 4E 98 4E B8 4E -4E 48 14 44 04 5B 49 46 5D 00 74 4E BA 4E 3A 44 -B8 4E 70 47 14 44 05 0D 0A 6B 6F 20 4A 47 BC 44 -AC 44 3A 44 BA 4E A8 4E 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 4F 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 4C 1A 49 82 49 -26 4F 4E 48 2C 4F 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 4F DE 47 4E 48 5E 4F B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 4B 06 4D -41 52 4B 45 52 00 B0 12 00 4D BA 40 85 12 FC FF -BA 40 5C 4F FE FF 28 83 8A 48 00 00 BA 40 AA 44 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A 44 -CA 1D D6 47 4E 48 85 12 9E 4F 66 4C D4 4D 10 47 -7E 4C 52 4E D2 46 6E 4F 00 49 96 50 AA 50 8A 48 -14 49 00 00 46 4F BC 4C E2 49 00 00 85 12 9E 4F -84 56 EA 56 2C 56 3A 57 F2 55 00 00 BE 53 00 00 -02 58 E6 57 56 56 94 56 CE 54 00 00 00 00 56 57 -CA 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 4F 24 50 2A 50 3A 50 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 4C -09 50 57 52 5F 53 54 41 54 45 85 12 32 50 0E 58 -CE 48 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 50 F3 3F 70 50 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E 50 30 4D 82 50 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 51 FE FF 29 83 B9 40 -E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 45 B2 49 FA 44 B2 49 02 44 B2 49 00 46 B2 49 -EC FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 22 02 -B2 43 46 02 B2 43 42 02 B2 43 66 02 B2 43 62 02 -B2 43 86 02 B2 40 7F FF 82 02 F2 43 26 03 F2 43 -22 03 F2 40 A5 00 41 01 F2 40 10 00 40 01 D2 43 -41 01 F2 40 A5 00 61 01 B2 40 48 00 62 01 82 43 -66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 B2 42 B0 01 -F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 1E 42 08 18 -82 43 08 18 1E D2 9E 01 B0 12 F8 44 FE 45 38 40 -C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D -30 4D 1C 15 0E 12 12 12 C4 1D 84 12 1A 49 82 49 -DE 47 34 44 FE 51 3E 4A 34 44 18 52 12 52 00 52 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 1A 52 B2 41 C4 1D 3E 41 -84 12 0A 44 2B 00 1A 49 82 49 DE 47 34 44 36 52 -3E 4A 34 44 00 4C A8 47 1A 49 3E 4A 34 44 00 4C -42 52 3E 5F E7 3F 3E 40 28 00 B0 12 E2 51 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 -C0 1D C4 1D 02 20 30 40 6E 4D 1C 15 12 12 C4 1D -92 53 C4 1D 84 12 1A 49 3E 4A 34 44 8A 52 80 52 -21 53 3E 90 10 00 C6 2B 7F 2D 8C 52 B2 41 C4 1D -C1 3F 0D 12 84 12 02 4C BE 51 9C 52 0C 43 1B 42 -C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 1D B0 12 E2 51 3C 40 00 03 0E 93 1C 24 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 13 3D 0E 93 3E 4F +95 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 D4 46 B2 49 +58 47 B2 49 30 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 54 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 B4 48 AC 44 +42 45 72 47 1E 44 05 1B 5B 37 6D 40 9E 47 0A 44 +02 18 D6 48 02 4A 9E 47 1E 44 04 1B 5B 30 6D 00 +9E 47 EA 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 72 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 9E 47 0A 44 02 18 D6 48 02 4A 0A 44 23 00 +56 47 02 4A 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +9E 47 0A 44 40 FF 32 44 CA 48 CE 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 FE FF +02 02 B2 43 26 02 B2 43 22 02 B2 43 46 02 B2 43 +42 02 B2 43 66 02 B2 43 62 02 B2 43 86 02 B2 40 +7F FF 82 02 F2 43 26 03 F2 43 22 03 F2 40 A5 00 +41 01 F2 40 10 00 40 01 D2 43 41 01 F2 40 A5 00 +61 01 B2 40 48 00 62 01 82 43 66 01 B2 40 33 00 +64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 +FE 23 19 83 FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 +F2 C0 40 00 A2 04 39 40 00 08 29 83 89 43 00 1C +FC 23 1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 +9E 01 B0 12 D0 44 80 45 00 00 0C 41 43 43 45 50 +54 00 30 40 D6 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 +3C 40 20 00 3D 15 8C 3E 21 52 A2 C2 6C 06 B2 B0 +10 00 40 06 85 22 3A 17 92 B3 6C 06 FD 27 58 42 +4C 06 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F +F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 +EB 3F 3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 +32 47 58 43 B0 12 46 45 2F 83 8F 4E 00 00 92 B3 +6C 06 FD 27 1E 42 4C 06 B0 12 44 45 30 4D 00 00 +08 45 4D 49 54 00 30 40 5A 47 08 4E 3E 4F A2 B3 +6C 06 FD 27 C2 48 4E 06 30 4D 50 47 08 45 43 48 +4F 00 B2 40 C2 48 64 47 38 40 05 00 B0 12 46 45 +30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D +64 47 28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 +3D 40 AE 47 29 4F 8F 4E 00 00 7E 49 D4 3F B0 47 +2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D +86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 71 22 +F9 98 00 00 6E 22 19 53 1C 83 FA 23 2D 53 30 4D +2F 53 3E 4F 1E 83 65 22 9B 24 2A 47 0D 5B 45 4C +53 45 5D 00 0D 12 84 12 0A 44 00 00 CE 48 C0 47 +12 4A CC 4C B0 44 3C 48 14 44 06 5B 54 48 45 4E +5D 00 C4 47 1A 48 E0 47 FE 47 14 44 06 5B 45 4C +53 45 5D 00 C4 47 2C 48 E0 47 FC 47 1E 44 04 5B +49 46 5D 00 C4 47 FE 47 B2 44 FC 47 1E 44 05 0D +6B 6F 20 0A 9E 47 9A 44 84 44 B2 44 FE 47 EC 47 +0D 5B 54 48 45 4E 5D 00 30 4D 50 48 09 5B 49 46 +5D 00 0E 93 3E 4F C6 27 30 4D 5C 48 13 5B 44 45 +46 49 4E 45 44 5D 0D 12 84 12 C0 47 12 4A 7A 4A +1E 4C 8E 49 6C 48 17 5B 55 4E 44 45 46 49 4E 45 +44 5D 0D 12 84 12 C0 47 12 4A 7A 4A 9E 48 3D 41 +2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 +3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +30 4D 00 00 02 40 2E 4E 30 4D CA 46 02 21 BE 4F +00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F +01 28 0E F3 30 4D E0 45 05 53 22 00 82 43 C0 1D +0D 12 84 12 0A 44 1E 44 7C 4C 0A 44 22 00 12 4A +12 49 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D +3E 4F 3D 41 30 4D 84 47 05 2E 22 00 0D 12 84 12 +FC 48 0A 44 9E 47 7C 4C 8E 49 00 00 04 3C 23 00 +B2 40 B2 1D B2 1D 30 4D F8 48 02 23 1B 42 BE 1D +2C 4F 2F 83 B0 12 46 44 BF 4F 00 00 7A 90 0A 00 +02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 +B2 1D C8 4A 00 00 30 4D 4A 49 04 23 53 00 0D 12 +84 12 4C 49 86 49 2D 83 09 DE 09 93 E1 23 3D 41 +30 4D 7A 49 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 +B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E +3E 4F DB 3F 94 49 08 53 49 47 4E 00 0E 93 3E 4F +7A 40 2D 00 D2 33 30 4D 6C 47 04 55 2E 00 0C 43 +2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 +00 00 3E E3 9F 53 00 00 0E 63 84 12 40 49 C0 47 +AE 49 7E 49 AA 48 BC 49 98 49 9E 47 8E 49 28 49 +02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 +44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C +09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 +27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C +00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 +61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 +C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 +30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 +CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 +08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E +78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 +1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 +01 20 1E 83 8F 4C 00 00 30 4D 00 4A 0E 3E 4E 55 +4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 +82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 +12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 +82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 +1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 +04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 +09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 84 4B +7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 +14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 +6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C +8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 +E0 23 AE 27 86 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 +BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 +B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 +09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 +0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B +2C 15 B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 +AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 +06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F +00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 +9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 +30 4D 3C 49 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 +84 12 84 44 C0 47 12 4A B0 44 56 4D 7A 4A 40 4C +0A 4E 3E 4F 3D 40 5A 4C 6D 27 3D 40 34 4C 1A E2 +BC 1D 14 24 0E 12 3E 4F 30 41 5C 4C 3E 4F 3D 40 +34 4C 19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 +00 00 3D 40 32 4E 2A 3C 24 4C 02 2C A2 53 C8 1D +1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 7A 4C 0F 4C +49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 +C8 1D A2 52 C8 1D BA 40 0A 44 00 00 8A 49 02 00 +3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 +EE 3F 30 4D B6 49 0A 43 4F 55 4E 54 2F 83 7A 4E +8F 4E 00 00 0E 4A 3E F3 30 4D DC 48 0A 41 4C 4C +4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 +84 12 1E 44 02 0D 0A 00 9E 47 94 44 2E 4C BC 48 +E6 48 1E 44 0B 73 74 61 63 6B 20 65 6D 70 74 79 +08 45 32 44 0A 44 40 FF EE 48 1E 44 09 46 52 41 +4D 20 66 75 6C 6C 08 45 B2 44 F2 4C DC 4C 0D 41 +42 4F 52 54 22 00 0D 12 84 12 FC 48 0A 44 08 45 +7C 4C 8E 49 0C 4A 02 27 0D 12 84 12 C0 47 12 4A +7A 4A B0 44 58 4D 20 49 64 4C 86 48 07 5B 27 5D +0D 12 84 12 48 4D 0A 44 0A 44 7C 4C 7C 4C 8E 49 +5C 4D 03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 +BC 1D 30 4D D4 48 11 50 4F 53 54 50 4F 4E 45 00 +0D 12 84 12 C0 47 12 4A 7A 4A B0 44 58 4D E6 48 +AC 44 B0 4D 0A 44 0A 44 7C 4C 7C 4C 0A 44 7C 4C +7C 4C 8E 49 00 00 02 3A 30 12 06 4E 92 B3 C8 1D +A2 63 C8 1D 0D 12 84 12 C0 47 12 4A CE 4D 3D 41 +5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 +3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 +B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 +82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 +FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 +1E 44 0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 +68 21 12 45 72 4D 03 3B 82 93 BC 1D F4 26 0D 12 +84 12 0A 44 8E 49 7C 4C 18 4E 74 4D 8E 49 00 00 +12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 +00 00 30 4D C6 4C 0C 43 52 45 41 54 45 00 B0 12 +BC 4D BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 98 47 +0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 +8A 4D 02 00 3D 41 30 4D B6 4D 0E 3A 4E 4F 4E 41 +4D 45 30 12 06 4E 2F 83 8F 4E 00 00 1A 42 C8 1D +1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F 50 4E +05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 48 4D +D2 4E 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 60 4D +0A 44 D4 4E 7C 4C 8E 49 66 4E 08 43 4F 44 45 00 +B0 12 BC 4D A2 82 C8 1D 61 3C A8 49 0E 48 44 4E +43 4F 44 45 B2 40 C0 4F CC 1D F2 3F 00 00 0E 45 +4E 44 43 4F 44 45 0D 12 84 12 18 4E 1E 4F 3D 41 +92 42 D0 1D CC 1D 5D 3C EA 4E 0E 43 4F 44 45 4E +4E 4D 30 12 F4 4E B7 3F 00 00 0A 43 4F 4C 4F 4E +1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 +A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 +48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F FC 4E 0B 48 +49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF +82 43 BC 1D B9 3F 88 4F B2 40 9A 4F D0 1D 82 4E +CE 1D 30 40 20 49 85 12 86 4F 86 4D 2E 4D 18 50 +2A 4F 80 4E CA 49 74 4A 46 4D 6E 4F C0 4E 9A 4E +36 4E 8E 4C A2 50 CC 4A 00 00 00 00 85 12 86 4F +1C 57 A0 55 00 57 C8 54 24 55 72 55 4E 56 5A 56 +EA 53 0E 55 00 00 00 00 5C 4F DA 52 00 00 76 56 +BA 4F B2 40 9A 4F CE 1D 82 43 D0 1D 30 4D 3B 40 +0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 +0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 +B0 12 EE 4F 30 4D 00 50 0E 52 53 54 5F 52 45 54 +39 40 42 18 2C 49 3A 40 C8 1D B0 12 EE 4F 1A 42 +CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF +0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 +F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 +80 FF FC 23 B9 40 0E 46 FE FF 29 83 B9 40 FA 45 +FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 EC FF +3B 40 10 00 3A 40 3A 18 B0 12 F2 4F 82 43 4A 18 +C7 3F 94 50 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F +7C 4D 0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 +84 12 C0 47 12 4A 7A 4A AC 44 C0 50 B4 48 54 4C +C2 50 3E 4F 3D 41 B2 41 C6 1D B0 12 BC 4D BA 40 +85 12 FC FF BA 40 92 50 FE FF 28 83 8A 48 00 00 +BA 40 82 44 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 +B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D +84 12 12 4A 7A 4A AC 44 2C 51 0C 51 3C 4E 3C 80 +87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 92 50 +00 00 01 20 3E 52 2E 83 21 53 30 41 24 4B AC 44 +34 51 28 51 36 51 B2 41 C6 1D 30 41 92 83 C6 1D +3E 40 28 00 0A 4E 3D 15 B0 12 FC 50 15 20 3E 40 +2B 00 B0 12 FC 50 06 20 3E 40 2D 00 B0 12 FC 50 +92 83 C6 1D 0E 12 1E 41 02 00 84 12 12 4A 24 4B +AC 44 58 4D 76 51 3E 51 3A 17 30 41 B0 12 3C 51 +19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 +92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 12 4A 24 4B +AC 44 AE 51 A6 51 3E 90 10 00 E6 2B 7C 2D B0 51 +A2 41 C6 1D E1 3F 03 20 B0 12 94 51 43 3C 7A 90 +23 00 24 20 B0 12 44 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 E2 51 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D -B0 12 6A 52 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -6A 52 92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 -0C 5E DA 3F B0 12 6A 52 FA 23 3C 50 10 00 B0 12 -46 52 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 -84 12 02 4C BE 51 68 53 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 6A 52 E0 23 -3C 50 80 00 B0 12 46 52 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 44 00 13 48 4B 4E 48 0A 44 -2C 00 92 52 5E 53 A8 53 09 4B 2E 4E 0E DC A2 3F -40 4E 03 4D 4F 56 85 12 9E 53 00 40 B2 53 05 4D -4F 56 2E 42 85 12 9E 53 40 40 00 00 03 41 44 44 -85 12 9E 53 00 50 CC 53 05 41 44 44 2E 42 85 12 -9E 53 40 50 D8 53 04 41 44 44 43 00 85 12 9E 53 -00 60 E6 53 06 41 44 44 43 2E 42 00 85 12 9E 53 -40 60 8C 53 04 53 55 42 43 00 85 12 9E 53 00 70 -04 54 06 53 55 42 43 2E 42 00 85 12 9E 53 40 70 -12 54 03 53 55 42 85 12 9E 53 00 80 22 54 05 53 -55 42 2E 42 85 12 9E 53 40 80 16 4E 03 43 4D 50 -85 12 9E 53 00 90 3C 54 05 43 4D 50 2E 42 85 12 -9E 53 40 90 00 4E 04 44 41 44 44 00 85 12 9E 53 -00 A0 56 54 06 44 41 44 44 2E 42 00 85 12 9E 53 -40 A0 48 54 03 42 49 54 85 12 9E 53 00 B0 74 54 -05 42 49 54 2E 42 85 12 9E 53 40 B0 80 54 03 42 -49 43 85 12 9E 53 00 C0 8E 54 05 42 49 43 2E 42 -85 12 9E 53 40 C0 9A 54 03 42 49 53 85 12 9E 53 -00 D0 A8 54 05 42 49 53 2E 42 85 12 9E 53 40 D0 -00 00 03 58 4F 52 85 12 9E 53 00 E0 C2 54 05 58 -4F 52 2E 42 85 12 9E 53 40 E0 F4 53 03 41 4E 44 -85 12 9E 53 00 F0 DC 54 05 41 4E 44 2E 42 85 12 -9E 53 40 F0 02 4C 92 52 FA 54 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 2E 54 03 52 52 43 -85 12 F4 54 00 10 0C 55 05 52 52 43 2E 42 85 12 -F4 54 40 10 18 55 04 53 57 50 42 00 85 12 F4 54 -80 10 26 55 03 52 52 41 85 12 F4 54 00 11 34 55 -05 52 52 41 2E 42 85 12 F4 54 40 11 40 55 03 53 -58 54 85 12 F4 54 80 11 00 00 04 50 55 53 48 00 -85 12 F4 54 00 12 5A 55 06 50 55 53 48 2E 42 00 -85 12 F4 54 40 12 B4 54 04 43 41 4C 4C 00 85 12 -F4 54 80 12 1A 53 0E 4A 0D 12 84 12 C4 48 14 44 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 45 -4E 55 03 53 3E 3D 86 12 00 38 A2 55 02 53 3C 00 -86 12 00 34 68 55 03 30 3E 3D 86 12 00 30 B6 55 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C CA 55 03 55 3E 3D 86 12 00 28 C0 55 03 30 -3C 3E 86 12 00 24 DE 55 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 -C6 1D 0E 4A 30 4D D4 55 04 54 48 45 4E 00 1A 42 -C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 64 54 04 45 4C 53 -45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D -2F 83 8F 4A 00 00 E3 3F 78 55 05 42 45 47 49 4E -30 40 28 44 08 56 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D -30 4D E8 54 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 F6 55 -A8 47 4E 48 AC 55 06 52 45 50 45 41 54 00 0D 12 -84 12 8A 56 0E 56 4E 48 BA 56 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D -4A 56 03 42 57 31 85 12 B8 56 00 00 D2 56 03 42 -57 32 85 12 B8 56 00 00 DE 56 03 42 57 33 85 12 -B8 56 00 00 F6 56 3D 41 1A 42 C6 1D 28 4E B2 92 -C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 F4 56 00 00 -16 57 03 46 57 32 85 12 F4 56 00 00 22 57 03 46 -57 33 85 12 F4 56 00 00 2E 57 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 4C -DC 4B 4E 48 00 00 05 3F 47 4F 54 4F 3E 90 00 30 +3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D +A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +05 20 3C 40 10 02 B0 12 44 51 F0 3F 7A 90 40 00 +14 20 3C 40 20 00 B0 12 90 51 0C 20 3C D0 10 00 +3E 40 2B 00 B0 12 94 51 92 92 C2 1D C6 1D 02 24 +92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +7C 51 F2 3F 03 20 B0 12 94 51 F5 3F 7A 90 26 00 +03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 7C 51 +EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 +19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF +19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 +08 52 45 54 49 00 0D 12 84 12 0A 44 00 13 7C 4C +8E 49 0A 44 2C 00 72 52 B6 51 C0 47 7C 52 54 52 +C2 52 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +4F 56 85 12 B2 52 00 40 CE 52 0A 4D 4F 56 2E 42 +85 12 B2 52 40 40 00 00 06 41 44 44 85 12 B2 52 +00 50 E8 52 0A 41 44 44 2E 42 85 12 B2 52 40 50 +F4 52 08 41 44 44 43 00 85 12 B2 52 00 60 02 53 +0C 41 44 44 43 2E 42 00 85 12 B2 52 40 60 3A 4F +08 53 55 42 43 00 85 12 B2 52 00 70 20 53 0C 53 +55 42 43 2E 42 00 85 12 B2 52 40 70 2E 53 06 53 +55 42 85 12 B2 52 00 80 3E 53 0A 53 55 42 2E 42 +85 12 B2 52 40 80 4A 53 06 43 4D 50 85 12 B2 52 +00 90 58 53 0A 43 4D 50 2E 42 85 12 B2 52 40 90 +00 00 08 44 41 44 44 00 85 12 B2 52 00 A0 72 53 +0C 44 41 44 44 2E 42 00 85 12 B2 52 40 A0 A0 52 +06 42 49 54 85 12 B2 52 00 B0 90 53 0A 42 49 54 +2E 42 85 12 B2 52 40 B0 9C 53 06 42 49 43 85 12 +B2 52 00 C0 AA 53 0A 42 49 43 2E 42 85 12 B2 52 +40 C0 B6 53 06 42 49 53 85 12 B2 52 00 D0 C4 53 +0A 42 49 53 2E 42 85 12 B2 52 40 D0 00 00 06 58 +4F 52 85 12 B2 52 00 E0 DE 53 0A 58 4F 52 2E 42 +85 12 B2 52 40 E0 10 53 06 41 4E 44 85 12 B2 52 +00 F0 F8 53 0A 41 4E 44 2E 42 85 12 B2 52 40 F0 +C0 47 72 52 B6 51 18 54 0A 4C 3C F0 70 00 8A 10 +3A F0 0F 00 0C DA 4D 3F D0 53 06 52 52 43 85 12 +10 54 00 10 2A 54 0A 52 52 43 2E 42 85 12 10 54 +40 10 64 53 08 53 57 50 42 00 85 12 10 54 80 10 +36 54 06 52 52 41 85 12 10 54 00 11 52 54 0A 52 +52 41 2E 42 85 12 10 54 40 11 44 54 06 53 58 54 +85 12 10 54 80 11 00 00 08 50 55 53 48 00 85 12 +10 54 00 12 78 54 0C 50 55 53 48 2E 42 00 85 12 +10 54 40 12 6C 54 08 43 41 4C 4C 00 85 12 10 54 +80 12 1A 53 0E 4A 84 12 02 4A 1E 44 0D 6F 75 74 +20 6F 66 20 62 6F 75 6E 64 73 12 45 96 54 06 53 +3E 3D 86 12 00 38 BE 54 04 53 3C 00 86 12 00 34 +86 54 06 30 3E 3D 86 12 00 30 D2 54 04 30 3C 00 +86 12 00 30 0E 4F 04 55 3C 00 86 12 00 2C E6 54 +06 55 3E 3D 86 12 00 28 DC 54 06 30 3C 3E 86 12 +00 24 FA 54 04 30 3D 00 86 12 00 20 00 00 04 49 +46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A +30 4D 80 53 08 54 48 45 4E 00 1A 42 C8 1D 08 4E +3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +88 DA 00 00 30 4D F0 54 08 45 4C 53 45 00 1A 42 +C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A +00 00 E3 3F 5E 54 0A 42 45 47 49 4E 30 40 32 44 +48 55 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D 04 54 +0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +0A 57 48 49 4C 45 0D 12 84 12 12 55 A8 48 8E 49 +66 55 0C 52 45 50 45 41 54 00 0D 12 84 12 A6 55 +2A 55 8E 49 D6 55 3D 41 08 4E 3E 4F 2A 48 B2 92 +C6 1D CB 2F 98 42 C8 1D 00 00 30 4D C2 55 06 42 +57 31 85 12 D4 55 00 00 EE 55 06 42 57 32 85 12 +D4 55 00 00 FA 55 06 42 57 33 85 12 D4 55 00 00 +12 56 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 +C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 +3E 4F 30 4D 00 00 06 46 57 31 85 12 10 56 00 00 +36 56 06 46 57 32 85 12 10 56 00 00 42 56 06 46 +57 33 85 12 10 56 00 00 B0 55 08 47 4F 54 4F 00 +2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 48 4D +54 4C 8E 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 02 4C BE 51 78 57 92 53 C4 1D 3E 40 2C 00 -84 12 1A 49 3E 4A 34 44 00 4C 54 53 8E 57 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E A6 56 04 52 52 43 -4D 00 85 12 72 57 50 00 BC 57 04 52 52 41 4D 00 -85 12 72 57 50 01 CA 57 04 52 4C 41 4D 00 85 12 -72 57 50 02 D8 57 04 52 52 55 4D 00 85 12 72 57 -50 03 E8 55 05 50 55 53 48 4D 85 12 72 57 00 15 -F4 57 04 50 4F 50 4D 00 85 12 72 57 00 17 +EC 3F 7C 52 0A 44 2C 00 12 4A 24 4B AC 44 58 4D +C0 47 72 52 54 52 A8 56 0A 4E 3E 4F 1A 83 F9 32 +29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +5A 06 A8 3E 06 56 08 52 52 43 4D 00 85 12 92 56 +50 00 D6 56 08 52 52 41 4D 00 85 12 92 56 50 01 +E4 56 08 52 4C 41 4D 00 85 12 92 56 50 02 F2 56 +08 52 52 55 4D 00 85 12 92 56 50 03 04 55 0A 50 +55 53 48 4D 85 12 92 56 00 15 0E 57 08 50 4F 50 +4D 00 85 12 92 56 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 82 46 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 08 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 E8 46 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 0E 46 q diff --git a/binaries/MSP_EXP430FR6989_16MHz_UART.txt b/binaries/MSP_EXP430FR6989_16MHz_UART.txt deleted file mode 100644 index 39ce9ca..0000000 --- a/binaries/MSP_EXP430FR6989_16MHz_UART.txt +++ /dev/null @@ -1,339 +0,0 @@ -@1800 -80 3E 08 00 A1 F7 18 00 F9 FF 24 58 02 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 94 46 24 58 -02 50 7A 46 92 47 24 47 FE 46 3C 1D 60 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 78 46 B2 49 90 47 B2 49 22 47 B2 49 FC 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 FC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -FC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E0 47 32 47 -14 44 04 1B 5B 37 6D 00 5C 47 A8 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 47 A0 48 5C 47 14 44 04 1B 5B 30 6D 00 -5C 47 28 4C 92 B3 EA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 E0 05 92 42 02 18 E6 05 92 42 04 18 -E8 05 F2 D0 30 00 2A 02 92 C3 E0 05 92 D3 FA 05 -92 C3 30 01 30 41 09 3C A2 B3 FC 05 FD 27 B2 40 -13 00 EE 05 D2 D3 22 02 30 41 A2 B3 FC 05 FD 27 -B2 40 11 00 EE 05 D2 C3 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 B0 12 -9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 5C 47 -D6 48 14 44 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 47 -0A 44 40 FF 28 44 D4 47 A0 48 14 44 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 44 86 45 00 00 06 41 -43 43 45 50 54 00 30 40 7A 46 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 46 3C 40 D2 46 -5D 15 B6 3E 21 52 3A 17 58 42 EC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 FC 05 FD 27 -C2 48 EE 05 30 4D C8 46 2D 83 92 B3 FC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 FC 05 -FD 27 58 42 EC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 46 2F 83 -8F 4E 00 00 B0 12 DA 45 92 B3 FC 05 FD 27 1E 42 -EC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 47 08 4E 3E 4F C8 3F 1A 47 04 45 43 48 -4F 00 B2 40 C2 48 C0 46 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 46 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 47 7A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 30 40 -92 47 0D 12 84 12 14 44 02 0D 0A 00 5C 47 60 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 46 01 40 -2E 4E 30 4D DE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A 48 02 23 53 00 0D 12 -84 12 1C 48 56 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 48 4E 48 EE 44 8E 48 6A 48 5C 47 14 4C 20 47 -60 48 40 47 01 2E 0E 93 E3 37 38 43 E2 3F 88 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -5A 4B 0A 44 22 00 2C 49 FA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 48 82 2E 22 00 0D 12 84 12 E4 48 0A 44 5C 47 -5A 4B 60 48 18 46 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 14 4C 2C 49 D0 4B -9C 26 3D 40 D8 4B DE 3E DA 4B 0A 4E 3E 4F 3D 40 -F4 4B 36 27 3D 40 CA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 4B 3E 4F 3D 40 CA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 4D -CC 3F FE 4B 86 12 20 00 E6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E 47 -BC 44 C4 4B C4 47 F6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -FE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 3E 4C 1A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 48 0A 44 2A 45 5A 4B 60 48 8E 49 -01 27 0D 12 84 12 14 4C 2C 49 94 49 34 44 12 4C -60 48 00 00 83 5B 27 5D 0D 12 84 12 92 4C 0A 44 -0A 44 5A 4B 5A 4B 60 48 A4 4C 81 5B 82 43 BE 1D -30 4D 0C 48 01 5D B2 43 BE 1D 30 4D C4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 4C 2C 49 94 49 A8 47 -34 44 12 4C F6 47 34 44 06 4D 0A 44 0A 44 5A 4B -5A 4B 0A 44 5A 4B 5A 4B 60 48 BA 4C 01 3A 30 12 -56 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 4C -2C 49 24 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 0C 4D 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 60 48 5A 4B 68 4D BC 4C -60 48 BA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 4B 06 43 52 45 -41 54 45 00 B0 12 12 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 4D 04 43 4F 44 45 00 B0 12 12 4D -A2 82 C6 1D 0D 12 84 12 04 50 DE 4F 60 48 B4 4D -07 48 44 4E 43 4F 44 45 B2 40 E2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 4D -1E 50 3C 50 60 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E 50 3C 50 60 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 4E 85 48 49 32 4C 4F 0D 12 84 12 28 44 -AC 4F 5A 4B BC 4C F4 4D 60 48 9A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 D8 47 14 4C 2C 49 -AA 4B A0 47 34 44 14 4F AE 47 14 44 06 5B 54 48 -45 4E 5D 00 86 4E EE 4E AA 4E CC 4E 60 48 AE 47 -14 44 06 5B 45 4C 53 45 5D 00 86 4E 04 4F AA 4E -CA 4E 60 48 14 44 04 5B 49 46 5D 00 86 4E CC 4E -3A 44 CA 4E 82 47 14 44 05 0D 0A 6B 6F 20 5C 47 -BC 44 AC 44 3A 44 CC 4E BA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 4C 2C 49 -94 49 38 4F 60 48 3E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 4F F0 47 60 48 70 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 4B -06 4D 41 52 4B 45 52 00 B0 12 12 4D BA 40 85 12 -FC FF BA 40 6E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D E8 47 60 48 85 12 B0 4F 78 4C E6 4D -2C 47 90 4C 64 4E F6 46 80 4F 12 49 A8 50 BC 50 -9C 48 26 49 00 00 58 4F CE 4C F4 49 00 00 85 12 -B0 4F 9A 56 00 57 42 56 50 57 08 56 00 00 D4 53 -00 00 18 58 FC 57 6C 56 AA 56 E4 54 00 00 00 00 -6C 57 DC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 4F 36 50 3C 50 4C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 44 50 -24 58 E0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 50 F3 3F 82 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 50 30 4D 94 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 51 FE FF 29 83 -B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 20 46 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 -22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 -66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 -F2 43 26 03 F2 43 22 03 F2 40 A5 00 41 01 F2 40 -10 00 40 01 D2 43 41 01 F2 40 A5 00 61 01 B2 40 -48 00 62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 -61 01 39 40 40 00 18 42 00 18 18 83 FE 23 19 83 -FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 -A2 04 1E 42 08 18 82 43 08 18 1E D2 9E 01 B0 12 -F8 44 1E 46 38 40 C0 1D 0A 4E 39 48 2E 48 09 5E -1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E -2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D -84 12 2C 49 94 49 F0 47 34 44 14 52 50 4A 34 44 -2E 52 28 52 16 52 3C 4E 3C 80 87 12 05 24 1C 53 -02 20 2E 4E 01 3C 2E 83 21 52 1B 17 30 41 30 52 -B2 41 C4 1D 3E 41 84 12 0A 44 2B 00 2C 49 94 49 -F0 47 34 44 4C 52 50 4A 34 44 12 4C BA 47 2C 49 -50 4A 34 44 12 4C 58 52 3E 5F E7 3F 3E 40 28 00 -B0 12 F8 51 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 -3E 40 29 00 92 92 C0 1D C4 1D 02 20 30 40 80 4D -1C 15 12 12 C4 1D 92 53 C4 1D 84 12 2C 49 50 4A -34 44 A0 52 96 52 21 53 3E 90 10 00 C6 2B 7F 2D -A2 52 B2 41 C4 1D C1 3F 0D 12 84 12 14 4C D4 51 -B2 52 0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F -7A 90 23 00 27 20 92 53 C4 1D B0 12 F8 51 3C 40 -00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 -20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 -30 02 3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 -30 00 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F -3D 41 30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 -C4 1D B0 12 F8 51 ED 3F 7A 90 40 00 16 20 3C 40 -20 00 92 53 C4 1D B0 12 80 52 0C 20 3C 50 10 00 -3E 40 2B 00 B0 12 80 52 92 92 C0 1D C4 1D 02 24 -92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 80 52 FA 23 -3C 50 10 00 B0 12 5C 52 EF 3F 0C 43 1B 42 C6 1D -A2 53 C6 1D 0D 12 84 12 14 4C D4 51 7E 53 FE 90 -26 00 00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F -B0 12 80 52 E0 23 3C 50 80 00 B0 12 5C 52 DB 3F -00 00 04 52 45 54 49 00 0D 12 84 12 0A 44 00 13 -5A 4B 60 48 0A 44 2C 00 A8 52 74 53 BE 53 09 4B -2E 4E 0E DC A2 3F 52 4E 03 4D 4F 56 85 12 B4 53 -00 40 C8 53 05 4D 4F 56 2E 42 85 12 B4 53 40 40 -00 00 03 41 44 44 85 12 B4 53 00 50 E2 53 05 41 -44 44 2E 42 85 12 B4 53 40 50 EE 53 04 41 44 44 -43 00 85 12 B4 53 00 60 FC 53 06 41 44 44 43 2E -42 00 85 12 B4 53 40 60 A2 53 04 53 55 42 43 00 -85 12 B4 53 00 70 1A 54 06 53 55 42 43 2E 42 00 -85 12 B4 53 40 70 28 54 03 53 55 42 85 12 B4 53 -00 80 38 54 05 53 55 42 2E 42 85 12 B4 53 40 80 -28 4E 03 43 4D 50 85 12 B4 53 00 90 52 54 05 43 -4D 50 2E 42 85 12 B4 53 40 90 12 4E 04 44 41 44 -44 00 85 12 B4 53 00 A0 6C 54 06 44 41 44 44 2E -42 00 85 12 B4 53 40 A0 5E 54 03 42 49 54 85 12 -B4 53 00 B0 8A 54 05 42 49 54 2E 42 85 12 B4 53 -40 B0 96 54 03 42 49 43 85 12 B4 53 00 C0 A4 54 -05 42 49 43 2E 42 85 12 B4 53 40 C0 B0 54 03 42 -49 53 85 12 B4 53 00 D0 BE 54 05 42 49 53 2E 42 -85 12 B4 53 40 D0 00 00 03 58 4F 52 85 12 B4 53 -00 E0 D8 54 05 58 4F 52 2E 42 85 12 B4 53 40 E0 -0A 54 03 41 4E 44 85 12 B4 53 00 F0 F2 54 05 41 -4E 44 2E 42 85 12 B4 53 40 F0 14 4C A8 52 10 55 -0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F -44 54 03 52 52 43 85 12 0A 55 00 10 22 55 05 52 -52 43 2E 42 85 12 0A 55 40 10 2E 55 04 53 57 50 -42 00 85 12 0A 55 80 10 3C 55 03 52 52 41 85 12 -0A 55 00 11 4A 55 05 52 52 41 2E 42 85 12 0A 55 -40 11 56 55 03 53 58 54 85 12 0A 55 80 11 00 00 -04 50 55 53 48 00 85 12 0A 55 00 12 70 55 06 50 -55 53 48 2E 42 00 85 12 0A 55 40 12 CA 54 04 43 -41 4C 4C 00 85 12 0A 55 80 12 1A 53 0E 4A 0D 12 -84 12 D6 48 14 44 0D 6F 75 74 20 6F 66 20 62 6F -75 6E 64 73 36 45 64 55 03 53 3E 3D 86 12 00 38 -B8 55 02 53 3C 00 86 12 00 34 7E 55 03 30 3E 3D -86 12 00 30 CC 55 02 30 3C 00 86 12 00 30 00 00 -02 55 3C 00 86 12 00 2C E0 55 03 55 3E 3D 86 12 -00 28 D6 55 03 30 3C 3E 86 12 00 24 F4 55 02 30 -3D 00 86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D -8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D EA 55 04 54 -48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 -0A 89 0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D -7A 54 04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C -00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 8E 55 -05 42 45 47 49 4E 30 40 28 44 1E 56 05 55 4E 54 -49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 -0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 -00 00 A2 53 C6 1D 30 4D FE 54 05 41 47 41 49 4E -0A 4E 38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 -0D 12 84 12 0C 56 BA 47 60 48 C2 55 06 52 45 50 -45 41 54 00 0D 12 84 12 A0 56 24 56 60 48 D0 56 -3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 -C6 1D 00 00 30 4D 60 56 03 42 57 31 85 12 CE 56 -00 00 E8 56 03 42 57 32 85 12 CE 56 00 00 F4 56 -03 42 57 33 85 12 CE 56 00 00 0C 57 3D 41 1A 42 -C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 -C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 -85 12 0A 57 00 00 2C 57 03 46 57 32 85 12 0A 57 -00 00 38 57 03 46 57 33 85 12 0A 57 00 00 44 57 -04 47 4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C -0D 12 84 12 92 4C EE 4B 60 48 00 00 05 3F 47 4F -54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 -EF 27 3E E0 00 08 EC 3F 14 4C D4 51 8E 57 92 53 -C4 1D 3E 40 2C 00 84 12 2C 49 50 4A 34 44 12 4C -6A 53 A4 57 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E -0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 -EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E -BC 56 04 52 52 43 4D 00 85 12 88 57 50 00 D2 57 -04 52 52 41 4D 00 85 12 88 57 50 01 E0 57 04 52 -4C 41 4D 00 85 12 88 57 50 02 EE 57 04 52 52 55 -4D 00 85 12 88 57 50 03 FE 55 05 50 55 53 48 4D -85 12 88 57 00 15 0A 58 04 50 4F 50 4D 00 85 12 -88 57 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 94 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 1A 51 -q diff --git a/binaries/MSP_EXP430FR6989_1MHz_115200.txt b/binaries/MSP_EXP430FR6989_1MHz_115200.txt new file mode 100644 index 0000000..83ef249 --- /dev/null +++ b/binaries/MSP_EXP430FR6989_1MHz_115200.txt @@ -0,0 +1,326 @@ +@1800 +E8 03 08 00 00 D6 18 00 FD FF 35 01 10 00 A1 59 +DC 46 7E 45 84 45 54 45 4C 47 3A 57 F2 4F AC 4F +AC 4F C2 46 80 47 48 47 3C 1D E0 1C A0 49 B6 44 +C4 44 BC 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +4C 47 3A 57 F2 4F AC 4F AC 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 09 3D 0E 93 3E 4F +9E 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 C0 46 B2 49 +7E 47 B2 49 46 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 66 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 4C 47 92 C3 FC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 FC 05 F3 23 +B0 12 D0 44 C6 48 AC 44 52 45 8E 47 1E 44 04 1B +5B 37 6D 00 B0 47 B0 47 1E 44 04 1B 5B 30 6D 00 +B0 47 FC 4C B0 12 7E 45 B2 40 81 00 E0 05 92 42 +02 18 E6 05 92 42 04 18 E8 05 F2 D0 30 00 2A 02 +92 C3 E0 05 92 D3 FA 05 92 C3 30 01 30 41 92 B3 +EA 05 FD 23 30 41 92 12 3E 18 84 12 8E 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 B0 47 14 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 B0 47 0A 44 40 FF 32 44 +DC 48 E0 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 +22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 +66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 +F2 43 26 03 F2 43 22 03 F2 40 A5 00 61 01 82 43 +62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 +39 40 00 08 29 83 89 43 00 1C FC 23 19 42 9E 01 +1E 42 08 18 82 43 08 18 3E F3 01 20 0E 49 B0 12 +D0 44 86 45 00 00 0C 41 43 43 45 50 54 00 30 40 +C2 46 08 4E 2E 4F 08 5E 39 40 0D 00 3A 40 20 00 +3B 40 20 47 3C 40 2C 47 5D 15 92 3E 21 52 3A 17 +58 42 EC 05 48 9B 09 20 A2 B3 FC 05 FD 27 B2 40 +13 00 EE 05 D2 D3 22 02 30 41 48 9C 06 2C 78 92 +11 20 2E 9F 0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 +00 00 1E 53 A2 B3 FC 05 FD 27 C2 48 EE 05 30 4D +22 47 2D 83 92 B3 FC 05 DB 23 FC 3F 3E 8F 3D 41 +92 B3 FC 05 FD 27 58 42 EC 05 08 4C EB 3F 00 00 +06 4B 45 59 30 40 48 47 30 12 5E 47 A2 B3 FC 05 +FD 27 B2 40 11 00 EE 05 D2 C3 22 02 30 41 2F 83 +8F 4E 00 00 92 B3 FC 05 FD 27 B0 12 E8 46 1E 42 +EC 05 30 4D 00 00 08 45 4D 49 54 00 30 40 80 47 +08 4E 3E 4F C7 3F 76 47 08 45 43 48 4F 00 B2 40 +C2 48 1A 47 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +B2 40 30 4D 1A 47 30 4D 00 00 08 54 59 50 45 00 +0D 12 3D 40 C0 47 29 4F 8F 4E 00 00 7E 49 DE 3F +C2 47 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F +30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F +68 22 F9 98 00 00 65 22 19 53 1C 83 FA 23 2D 53 +30 4D 2F 53 3E 4F 1E 83 5C 22 9B 24 40 47 0D 5B +45 4C 53 45 5D 00 0D 12 84 12 0A 44 00 00 E0 48 +D2 47 24 4A DE 4C B0 44 4E 48 14 44 06 5B 54 48 +45 4E 5D 00 D6 47 2C 48 F2 47 10 48 14 44 06 5B +45 4C 53 45 5D 00 D6 47 3E 48 F2 47 0E 48 1E 44 +04 5B 49 46 5D 00 D6 47 10 48 B2 44 0E 48 1E 44 +05 0D 6B 6F 20 0A B0 47 9A 44 84 44 B2 44 10 48 +FE 47 0D 5B 54 48 45 4E 5D 00 30 4D 62 48 09 5B +49 46 5D 00 0E 93 3E 4F C6 27 30 4D 6E 48 13 5B +44 45 46 49 4E 45 44 5D 0D 12 84 12 D2 47 24 4A +8C 4A 30 4C A0 49 7E 48 17 5B 55 4E 44 45 46 49 +4E 45 44 5D 0D 12 84 12 D2 47 24 4A 8C 4A B0 48 +3D 41 2F 53 1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E +00 00 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E +FE FF 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 +1E 53 30 4D 00 00 02 40 2E 4E 30 4D B6 46 02 21 +BE 4F 00 00 3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D +3E 8F 01 28 0E F3 30 4D D8 45 05 53 22 00 82 43 +C0 1D 0D 12 84 12 0A 44 1E 44 8E 4C 0A 44 22 00 +24 4A 24 49 B2 40 20 00 C0 1D 1A 53 1A B3 82 6A +C8 1D 3E 4F 3D 41 30 4D 98 47 05 2E 22 00 0D 12 +84 12 0E 49 0A 44 B0 47 8E 4C A0 49 00 00 04 3C +23 00 B2 40 B2 1D B2 1D 30 4D 0A 49 02 23 1B 42 +BE 1D 2C 4F 2F 83 B0 12 46 44 BF 4F 00 00 7A 90 +0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D +18 42 B2 1D C8 4A 00 00 30 4D 5C 49 04 23 53 00 +0D 12 84 12 5E 49 98 49 2D 83 09 DE 09 93 E1 23 +3D 41 30 4D 8C 49 04 23 3E 00 9F 42 B2 1D 00 00 +3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 4F 4C 44 00 +4A 4E 3E 4F DB 3F A6 49 08 53 49 47 4E 00 0E 93 +3E 4F 7A 40 2D 00 D2 33 30 4D 88 47 04 55 2E 00 +0C 43 2F 83 8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 +BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 52 49 +D2 47 C0 49 90 49 BC 48 CE 49 AA 49 B0 47 A0 49 +3A 49 02 2E 0E 93 E4 37 3C 43 E3 3F 00 00 08 57 +4F 52 44 00 3C 40 C2 1D 39 4C 38 4C 09 58 38 5C +2A 4C 09 98 1D 24 7E 98 FC 27 18 83 1B 42 C0 1D +F8 90 27 00 00 00 04 20 E8 98 02 00 01 20 0B 43 +CA 4C 00 00 09 98 0C 24 7C 48 4E 9C 09 24 1A 53 +7C 90 61 00 F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F +18 82 C4 1D 82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A +00 00 30 4D 00 00 08 46 49 4E 44 00 2F 83 0C 4E +3B 40 CE 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 +0F 00 08 58 0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 +09 4E 78 49 48 11 68 9C F7 23 0A 4C FA 99 01 00 +F3 23 1A 53 58 83 FA 23 19 B3 09 63 0C 49 6E 4E +1E F3 01 20 1E 83 8F 4C 00 00 30 4D 12 4A 0E 3E +4E 55 4D 42 45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F +2F 82 82 4B C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 +07 00 12 28 7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 +E0 04 82 48 E2 04 19 42 E4 04 18 42 E6 04 09 5A +08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 +8F 49 04 00 30 4D 32 C0 00 02 3F 82 8F 4E 06 00 +08 43 09 43 1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 +96 4B 7E 4C 6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 +7A 52 14 24 3B 52 6A 53 11 24 3B 40 10 00 5A 93 +0D 24 6A 92 41 20 3E 90 03 00 3E 20 FC 9C 01 00 +6C 4C 8F 4C 04 00 38 3C B1 43 02 00 1E 83 FC 9C +00 00 E0 23 AE 27 98 4B 2F 24 2D 83 6A 4C 7A 90 +5F 00 BF 27 32 B0 00 02 27 20 32 D0 00 02 7A 80 +2E 00 B7 27 6A 53 20 20 0A 4E 09 43 8F 49 02 00 +5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 79 80 +07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 00 00 +0E 4B 2C 15 B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 +02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 00 02 +3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 +BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 +00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 +2F 53 30 4D 4E 49 03 5C 92 42 C2 1D C6 1D 30 4D +0D 12 84 12 84 44 D2 47 24 4A B0 44 68 4D 8C 4A +52 4C 0A 4E 3E 4F 3D 40 6C 4C 6D 27 3D 40 46 4C +1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 6E 4C 3E 4F +3D 40 46 4C 19 20 DE 53 00 00 68 4E 08 5E F8 40 +3F 00 00 00 3D 40 44 4E 2A 3C 36 4C 02 2C A2 53 +C8 1D 1A 42 C8 1D 8A 4E FE FF 3E 4F 30 4D 8C 4C +0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 09 4E +1A 42 C8 1D A2 52 C8 1D BA 40 0A 44 00 00 8A 49 +02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 8A 4E +02 00 EE 3F 30 4D C8 49 0A 43 4F 55 4E 54 2F 83 +7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D EE 48 0A 41 +4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C +0E 43 84 12 1E 44 02 0D 0A 00 B0 47 94 44 40 4C +CE 48 F8 48 1E 44 0B 73 74 61 63 6B 20 65 6D 70 +74 79 08 45 32 44 0A 44 40 FF 00 49 1E 44 09 46 +52 41 4D 20 66 75 6C 6C 08 45 B2 44 04 4D EE 4C +0D 41 42 4F 52 54 22 00 0D 12 84 12 0E 49 0A 44 +08 45 8E 4C A0 49 1E 4A 02 27 0D 12 84 12 D2 47 +24 4A 8C 4A B0 44 6A 4D 32 49 76 4C 98 48 07 5B +27 5D 0D 12 84 12 5A 4D 0A 44 0A 44 8E 4C 8E 4C +A0 49 6E 4D 03 5B 82 43 BC 1D 30 4D 00 00 02 5D +B2 43 BC 1D 30 4D E6 48 11 50 4F 53 54 50 4F 4E +45 00 0D 12 84 12 D2 47 24 4A 8C 4A B0 44 6A 4D +F8 48 AC 44 C2 4D 0A 44 0A 44 8E 4C 8E 4C 0A 44 +8E 4C 8E 4C A0 49 00 00 02 3A 30 12 18 4E 92 B3 +C8 1D A2 63 C8 1D 0D 12 84 12 D2 47 24 4A E0 4D +3D 41 5A D3 5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E +01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 +82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F BA 1D +2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF BA 40 +84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 +84 12 1E 44 0F 73 74 61 63 6B 20 6D 69 73 6D 61 +74 63 68 21 12 45 84 4D 03 3B 82 93 BC 1D F4 26 +0D 12 84 12 0A 44 A0 49 8E 4C 2A 4E 86 4D A0 49 +00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 B4 1D +D8 D3 00 00 30 4D D8 4C 0C 43 52 45 41 54 45 00 +B0 12 CE 4D BA 40 86 12 FC FF 8A 4A FE FF 3A 3D +AA 47 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 85 12 +00 00 8A 4D 02 00 3D 41 30 4D C8 4D 0E 3A 4E 4F +4E 41 4D 45 30 12 18 4E 2F 83 8F 4E 00 00 1A 42 +C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 98 3F +62 4E 05 49 53 00 0D 12 82 93 BC 1D 08 20 84 12 +5A 4D E4 4E 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 +72 4D 0A 44 E6 4E 8E 4C A0 49 78 4E 08 43 4F 44 +45 00 B0 12 CE 4D A2 82 C8 1D 61 3C BA 49 0E 48 +44 4E 43 4F 44 45 B2 40 D2 4F CC 1D F2 3F 00 00 +0E 45 4E 44 43 4F 44 45 0D 12 84 12 2A 4E 30 4F +3D 41 92 42 D0 1D CC 1D 5D 3C FC 4E 0E 43 4F 44 +45 4E 4E 4D 30 12 06 4F B7 3F 00 00 0A 43 4F 4C +4F 4E 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 +02 00 A2 52 C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C +4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D EF 3F 0E 4F +0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A +FE FF 82 43 BC 1D B9 3F 9A 4F B2 40 AC 4F D0 1D +82 4E CE 1D 30 40 32 49 85 12 98 4F 98 4D 40 4D +2A 50 3C 4F 92 4E DC 49 86 4A 58 4D 80 4F D2 4E +AC 4E 48 4E A0 4C B4 50 DE 4A 00 00 00 00 85 12 +98 4F 2E 57 B2 55 12 57 DA 54 36 55 84 55 60 56 +6C 56 FC 53 20 55 00 00 00 00 6E 4F EC 52 00 00 +88 56 CC 4F B2 40 AC 4F CE 1D 82 43 D0 1D 30 4D +3B 40 0A 00 BA 49 00 00 2A 53 2B 83 FB 23 30 41 +00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 +42 18 B0 12 00 50 30 4D 12 50 0E 52 53 54 5F 52 +45 54 39 40 42 18 2C 49 3A 40 C8 1D B0 12 00 50 +1A 42 CA 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 +FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +0A 93 F0 23 30 4D 0E 93 E4 37 39 40 10 00 29 83 +B9 43 80 FF FC 23 B9 40 06 46 FE FF 29 83 B9 40 +F2 45 FE FF 39 90 AE FF F9 23 39 40 10 18 B2 49 +E4 FF 3B 40 10 00 3A 40 3A 18 B0 12 04 50 82 43 +4A 18 C7 3F A6 50 B2 4E 42 18 BE 12 3E 4F 3D 41 +C0 3F 8E 4D 0C 4D 41 52 4B 45 52 00 12 12 C6 1D +0D 12 84 12 D2 47 24 4A 8C 4A AC 44 D2 50 C6 48 +66 4C D4 50 3E 4F 3D 41 B2 41 C6 1D B0 12 CE 4D +BA 40 85 12 FC FF BA 40 A4 50 FE FF 28 83 8A 48 +00 00 BA 40 82 44 02 00 A2 52 C8 1D 18 42 B4 1D +19 42 B6 1D A8 49 FE FF 89 48 00 00 30 4D 12 12 +C6 1D 84 12 24 4A 8C 4A AC 44 3E 51 1E 51 3C 4E +3C 80 87 12 0A 24 1C 53 02 20 2E 4E 06 3C BE 90 +A4 50 00 00 01 20 3E 52 2E 83 21 53 30 41 36 4B +AC 44 46 51 3A 51 48 51 B2 41 C6 1D 30 41 92 83 +C6 1D 3E 40 28 00 0A 4E 3D 15 B0 12 0E 51 15 20 +3E 40 2B 00 B0 12 0E 51 06 20 3E 40 2D 00 B0 12 +0E 51 92 83 C6 1D 0E 12 1E 41 02 00 84 12 24 4A +36 4B AC 44 6A 4D 88 51 3E 51 3A 17 30 41 B0 12 +4E 51 19 42 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 +29 00 92 53 C6 1D 1A 42 C6 1D 3D 15 84 12 24 4A +36 4B AC 44 C0 51 B8 51 3E 90 10 00 E6 2B 7C 2D +C2 51 A2 41 C6 1D E1 3F 03 20 B0 12 A6 51 43 3C +7A 90 23 00 24 20 B0 12 56 51 3C 40 00 03 0E 93 +1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 +14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 +0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 +C8 1D A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 +26 00 05 20 3C 40 10 02 B0 12 56 51 F0 3F 7A 90 +40 00 14 20 3C 40 20 00 B0 12 A2 51 0C 20 3C D0 +10 00 3E 40 2B 00 B0 12 A6 51 92 92 C2 1D C6 1D +02 24 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 +B0 12 8E 51 F2 3F 03 20 B0 12 A6 51 F5 3F 7A 90 +26 00 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 +8E 51 EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 +20 00 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 +FF FF 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D +00 00 08 52 45 54 49 00 0D 12 84 12 0A 44 00 13 +8E 4C A0 49 0A 44 2C 00 84 52 C8 51 D2 47 8E 52 +66 52 D4 52 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 +06 4D 4F 56 85 12 C4 52 00 40 E0 52 0A 4D 4F 56 +2E 42 85 12 C4 52 40 40 00 00 06 41 44 44 85 12 +C4 52 00 50 FA 52 0A 41 44 44 2E 42 85 12 C4 52 +40 50 06 53 08 41 44 44 43 00 85 12 C4 52 00 60 +14 53 0C 41 44 44 43 2E 42 00 85 12 C4 52 40 60 +4C 4F 08 53 55 42 43 00 85 12 C4 52 00 70 32 53 +0C 53 55 42 43 2E 42 00 85 12 C4 52 40 70 40 53 +06 53 55 42 85 12 C4 52 00 80 50 53 0A 53 55 42 +2E 42 85 12 C4 52 40 80 5C 53 06 43 4D 50 85 12 +C4 52 00 90 6A 53 0A 43 4D 50 2E 42 85 12 C4 52 +40 90 00 00 08 44 41 44 44 00 85 12 C4 52 00 A0 +84 53 0C 44 41 44 44 2E 42 00 85 12 C4 52 40 A0 +B2 52 06 42 49 54 85 12 C4 52 00 B0 A2 53 0A 42 +49 54 2E 42 85 12 C4 52 40 B0 AE 53 06 42 49 43 +85 12 C4 52 00 C0 BC 53 0A 42 49 43 2E 42 85 12 +C4 52 40 C0 C8 53 06 42 49 53 85 12 C4 52 00 D0 +D6 53 0A 42 49 53 2E 42 85 12 C4 52 40 D0 00 00 +06 58 4F 52 85 12 C4 52 00 E0 F0 53 0A 58 4F 52 +2E 42 85 12 C4 52 40 E0 22 53 06 41 4E 44 85 12 +C4 52 00 F0 0A 54 0A 41 4E 44 2E 42 85 12 C4 52 +40 F0 D2 47 84 52 C8 51 2A 54 0A 4C 3C F0 70 00 +8A 10 3A F0 0F 00 0C DA 4D 3F E2 53 06 52 52 43 +85 12 22 54 00 10 3C 54 0A 52 52 43 2E 42 85 12 +22 54 40 10 76 53 08 53 57 50 42 00 85 12 22 54 +80 10 48 54 06 52 52 41 85 12 22 54 00 11 64 54 +0A 52 52 41 2E 42 85 12 22 54 40 11 56 54 06 53 +58 54 85 12 22 54 80 11 00 00 08 50 55 53 48 00 +85 12 22 54 00 12 8A 54 0C 50 55 53 48 2E 42 00 +85 12 22 54 40 12 7E 54 08 43 41 4C 4C 00 85 12 +22 54 80 12 1A 53 0E 4A 84 12 14 4A 1E 44 0D 6F +75 74 20 6F 66 20 62 6F 75 6E 64 73 12 45 A8 54 +06 53 3E 3D 86 12 00 38 D0 54 04 53 3C 00 86 12 +00 34 98 54 06 30 3E 3D 86 12 00 30 E4 54 04 30 +3C 00 86 12 00 30 20 4F 04 55 3C 00 86 12 00 2C +F8 54 06 55 3E 3D 86 12 00 28 EE 54 06 30 3C 3E +86 12 00 24 0C 55 04 30 3D 00 86 12 00 20 00 00 +04 49 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D +0E 4A 30 4D 92 53 08 54 48 45 4E 00 1A 42 C8 1D +08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 +B2 2F 88 DA 00 00 30 4D 02 55 08 45 4C 53 45 00 +1A 42 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 +8F 4A 00 00 E3 3F 70 54 0A 42 45 47 49 4E 30 40 +32 44 5A 55 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F +19 42 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B +3A F0 FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D +16 54 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F +00 00 0A 57 48 49 4C 45 0D 12 84 12 24 55 BA 48 +A0 49 78 55 0C 52 45 50 45 41 54 00 0D 12 84 12 +B8 55 3C 55 A0 49 E8 55 3D 41 08 4E 3E 4F 2A 48 +B2 92 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D D4 55 +06 42 57 31 85 12 E6 55 00 00 00 56 06 42 57 32 +85 12 E6 55 00 00 0C 56 06 42 57 33 85 12 E6 55 +00 00 24 56 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 +B2 92 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A +00 00 3E 4F 30 4D 00 00 06 46 57 31 85 12 22 56 +00 00 48 56 06 46 57 32 85 12 22 56 00 00 54 56 +06 46 57 33 85 12 22 56 00 00 C2 55 08 47 4F 54 +4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 +5A 4D 66 4C A0 49 00 00 0A 3F 47 4F 54 4F 3E 90 +00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 +00 08 EC 3F 8E 52 0A 44 2C 00 24 4A 36 4B AC 44 +6A 4D D2 47 84 52 66 52 BA 56 0A 4E 3E 4F 1A 83 +F9 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A +08 8A 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E +8A 10 5A 06 A8 3E 18 56 08 52 52 43 4D 00 85 12 +A4 56 50 00 E8 56 08 52 52 41 4D 00 85 12 A4 56 +50 01 F6 56 08 52 4C 41 4D 00 85 12 A4 56 50 02 +04 57 08 52 52 55 4D 00 85 12 A4 56 50 03 16 55 +0A 50 55 53 48 4D 85 12 A4 56 00 15 20 57 08 50 +4F 50 4D 00 85 12 A4 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 DC 46 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 06 46 +q diff --git a/binaries/MSP_EXP430FR6989_1MHz_I2C.txt b/binaries/MSP_EXP430FR6989_1MHz_I2C.txt index 3d509b8..5daea6e 100644 --- a/binaries/MSP_EXP430FR6989_1MHz_I2C.txt +++ b/binaries/MSP_EXP430FR6989_1MHz_I2C.txt @@ -1,336 +1,324 @@ @1800 -E8 03 12 00 00 00 F8 00 F9 FF FC 57 F0 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 82 46 FC 57 -F0 4F 70 46 80 47 FE 46 DA 46 3C 1D 4E 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +E8 03 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +D6 46 56 45 56 45 58 45 44 45 16 57 CE 4F 88 4F +88 4F C4 46 48 47 20 47 3C 1D E0 1C 7C 49 B6 44 +C4 44 98 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 16 57 CE 4F 88 4F 88 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 6E 46 B2 49 7E 47 B2 49 FC 46 B2 49 D8 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D CE 47 16 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 -C4 48 96 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 47 8E 48 4A 47 -14 44 04 1B 5B 30 6D 00 4A 47 16 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 B0 12 -8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 07 0D -0A 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 C4 48 -0A 44 23 00 FA 46 C4 48 14 44 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 47 0A 44 40 FF 28 44 C2 47 8E 48 -14 44 0A 62 79 74 65 73 20 66 72 65 65 00 3A 44 -7E 45 00 00 06 41 43 43 45 50 54 00 30 40 70 46 -0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 -3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 -48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 46 2F 83 8F 4E 00 00 -58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 46 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 46 -04 45 43 48 4F 00 B2 40 C2 48 08 47 82 43 DE 1D -38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 47 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 47 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 46 68 47 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 80 47 -0D 12 84 12 14 44 02 0D 0A 00 4A 47 4E 48 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 46 01 40 2E 4E -30 4D CC 47 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 47 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 02 28 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 0A 3D 0E 93 3E 4F +8C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 C2 46 B2 49 +46 47 B2 49 1E 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 42 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 A2 48 AC 44 +42 45 60 47 1E 44 05 1B 5B 37 6D 40 8C 47 0A 44 +02 18 C4 48 F0 49 8C 47 1E 44 04 1B 5B 30 6D 00 +8C 47 D8 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 60 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 8C 47 0A 44 02 18 C4 48 F0 49 0A 44 23 00 +44 47 F0 49 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +8C 47 0A 44 40 FF 32 44 B8 48 BC 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 FE FF +02 02 B2 43 26 02 B2 43 22 02 B2 43 46 02 B2 43 +42 02 B2 43 66 02 B2 43 62 02 B2 43 86 02 B2 40 +7F FF 82 02 F2 43 26 03 F2 43 22 03 F2 40 A5 00 +61 01 82 43 62 01 82 43 66 01 B2 40 33 00 64 01 +D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 +19 83 FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 +40 00 A2 04 39 40 00 08 29 83 89 43 00 1C FC 23 +1E 42 08 18 82 43 08 18 3E F3 02 20 1E 42 9E 01 +B0 12 D0 44 80 45 00 00 0C 41 43 43 45 50 54 00 +30 40 C4 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 +20 00 3D 15 95 3E 21 52 A2 C2 6C 06 B2 B0 10 00 +40 06 8E 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 +48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 +1E 83 F1 3F 0E 9A EF 2F CE 48 00 00 1E 53 EB 3F +3E 8F 08 4C 1B 3C 00 00 06 4B 45 59 30 40 20 47 +58 43 B0 12 46 45 2F 83 8F 4E 00 00 92 B3 6C 06 +FD 27 1E 42 4C 06 B0 12 44 45 30 4D 00 00 08 45 +4D 49 54 00 30 40 48 47 08 4E 3E 4F A2 B3 6C 06 +FD 27 C2 48 4E 06 30 4D 3E 47 08 45 43 48 4F 00 +B2 40 C2 48 52 47 38 40 05 00 B0 12 46 45 30 4D +00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D 52 47 +28 42 F3 3F 00 00 08 54 59 50 45 00 0D 12 3D 40 +9C 47 29 4F 8F 4E 00 00 7E 49 D4 3F 9E 47 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 7A 22 F9 98 +00 00 77 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 6E 22 9B 24 18 47 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 44 00 00 BC 48 AE 47 00 4A +BA 4C B0 44 2A 48 14 44 06 5B 54 48 45 4E 5D 00 +B2 47 08 48 CE 47 EC 47 14 44 06 5B 45 4C 53 45 +5D 00 B2 47 1A 48 CE 47 EA 47 1E 44 04 5B 49 46 +5D 00 B2 47 EC 47 B2 44 EA 47 1E 44 05 0D 6B 6F +20 0A 8C 47 9A 44 84 44 B2 44 EC 47 DA 47 0D 5B +54 48 45 4E 5D 00 30 4D 3E 48 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 4A 48 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 AE 47 00 4A 68 4A 0C 4C +7C 49 5A 48 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 AE 47 00 4A 68 4A 8C 48 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D B8 46 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D E0 45 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A 44 1E 44 6A 4C 0A 44 22 00 00 4A 00 49 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 72 47 05 2E 22 00 0D 12 84 12 EA 48 +0A 44 8C 47 6A 4C 7C 49 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D E6 48 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 44 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 48 02 23 53 00 0D 12 84 12 -0A 48 44 48 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 48 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 47 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 47 -3C 48 EE 44 7C 48 58 48 4A 47 02 4C FA 46 4E 48 -2C 47 01 2E 0E 93 E3 37 38 43 E2 3F 76 48 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 48 4B -0A 44 22 00 1A 49 E8 48 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 48 -82 2E 22 00 0D 12 84 12 D2 48 0A 44 4A 47 48 4B -4E 48 F8 45 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 -8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C 4A 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 4A 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 4B 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 48 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 44 02 4C 1A 49 BE 4B 9C 26 -3D 40 C6 4B DE 3E C8 4B 0A 4E 3E 4F 3D 40 E2 4B -36 27 3D 40 B8 4B 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 4B 3E 4F 3D 40 B8 4B BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 4D CC 3F -EC 4B 86 12 20 00 D4 47 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C 47 BC 44 -B2 4B B2 47 E4 47 14 44 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 EC 47 -14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 45 -3A 44 2C 4C 08 4C 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 48 0A 44 2A 45 48 4B 4E 48 7C 49 01 27 -0D 12 84 12 02 4C 1A 49 82 49 34 44 00 4C 4E 48 -00 00 83 5B 27 5D 0D 12 84 12 80 4C 0A 44 0A 44 -48 4B 48 4B 4E 48 92 4C 81 5B 82 43 BE 1D 30 4D -FA 47 01 5D B2 43 BE 1D 30 4D B2 4C 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 4C 1A 49 82 49 96 47 34 44 -00 4C E4 47 34 44 F4 4C 0A 44 0A 44 48 4B 48 4B -0A 44 48 4B 48 4B 4E 48 A8 4C 01 3A 30 12 44 4D -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 4C 1A 49 -12 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 45 FA 4C 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 44 4E 48 48 4B 56 4D AA 4C 4E 48 -A8 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 4B 06 43 52 45 41 54 -45 00 B0 12 00 4D BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 4D 04 43 4F 44 45 00 B0 12 00 4D A2 82 -C6 1D 0D 12 84 12 F2 4F CC 4F 4E 48 A2 4D 07 48 -44 4E 43 4F 44 45 B2 40 D0 4F DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 4D 0C 50 -2A 50 4E 48 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C 50 2A 50 4E 48 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 9A 4F -48 4B AA 4C E2 4D 4E 48 88 4D 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 4E 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 44 00 00 C6 47 02 4C 1A 49 98 4B -8E 47 34 44 02 4F 9C 47 14 44 06 5B 54 48 45 4E -5D 00 74 4E DC 4E 98 4E BA 4E 4E 48 9C 47 14 44 -06 5B 45 4C 53 45 5D 00 74 4E F2 4E 98 4E B8 4E -4E 48 14 44 04 5B 49 46 5D 00 74 4E BA 4E 3A 44 -B8 4E 70 47 14 44 05 0D 0A 6B 6F 20 4A 47 BC 44 -AC 44 3A 44 BA 4E A8 4E 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 4F 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 4C 1A 49 82 49 -26 4F 4E 48 2C 4F 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 4F DE 47 4E 48 5E 4F B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 4B 06 4D -41 52 4B 45 52 00 B0 12 00 4D BA 40 85 12 FC FF -BA 40 5C 4F FE FF 28 83 8A 48 00 00 BA 40 AA 44 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A 44 -CA 1D D6 47 4E 48 85 12 9E 4F 66 4C D4 4D 10 47 -7E 4C 52 4E D2 46 6E 4F 00 49 96 50 AA 50 8A 48 -14 49 00 00 46 4F BC 4C E2 49 00 00 85 12 9E 4F -72 56 D8 56 1A 56 28 57 E0 55 00 00 AC 53 00 00 -F0 57 D4 57 44 56 82 56 BC 54 00 00 00 00 44 57 -CA 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 4F 24 50 2A 50 3A 50 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 4C -09 50 57 52 5F 53 54 41 54 45 85 12 32 50 FC 57 -CE 48 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 50 F3 3F 70 50 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E 50 30 4D 82 50 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 51 FE FF 29 83 B9 40 -E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 45 B2 49 FA 44 B2 49 02 44 B2 49 00 46 B2 49 -EC FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 22 02 -B2 43 46 02 B2 43 42 02 B2 43 66 02 B2 43 62 02 -B2 43 86 02 B2 40 7F FF 82 02 F2 43 26 03 F2 43 -22 03 F2 40 A5 00 61 01 82 43 62 01 82 43 66 01 -B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 18 42 -00 18 18 83 FE 23 19 83 FA 23 B2 42 B0 01 F2 D0 -10 00 2A 03 F2 C0 40 00 A2 04 1E 42 08 18 82 43 -08 18 1E D2 9E 01 B0 12 F8 44 FE 45 38 40 C0 1D -0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 -7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D -1C 15 0E 12 12 12 C4 1D 84 12 1A 49 82 49 DE 47 -34 44 EC 51 3E 4A 34 44 06 52 00 52 EE 51 3C 4E -3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C 2E 83 -21 52 1B 17 30 41 08 52 B2 41 C4 1D 3E 41 84 12 -0A 44 2B 00 1A 49 82 49 DE 47 34 44 24 52 3E 4A -34 44 00 4C A8 47 1A 49 3E 4A 34 44 00 4C 30 52 -3E 5F E7 3F 3E 40 28 00 B0 12 D0 51 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 C0 1D -C4 1D 02 20 30 40 6E 4D 1C 15 12 12 C4 1D 92 53 -C4 1D 84 12 1A 49 3E 4A 34 44 78 52 6E 52 21 53 -3E 90 10 00 C6 2B 7F 2D 7A 52 B2 41 C4 1D C1 3F -0D 12 84 12 02 4C AC 51 8A 52 0C 43 1B 42 C6 1D -A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 92 53 -C4 1D B0 12 D0 51 3C 40 00 03 0E 93 1C 24 3C 40 +C8 4A 00 00 30 4D 38 49 04 23 53 00 0D 12 84 12 +3A 49 74 49 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +68 49 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F 82 49 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 5A 47 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 2E 49 AE 47 9C 49 +6C 49 98 48 AA 49 86 49 8C 47 7C 49 16 49 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D EE 49 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 72 4B 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 74 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +2A 49 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 44 AE 47 00 4A B0 44 44 4D 68 4A 2E 4C 0A 4E +3E 4F 3D 40 48 4C 6D 27 3D 40 22 4C 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 4A 4C 3E 4F 3D 40 22 4C +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 20 4E 2A 3C 12 4C 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D 68 4C 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D A4 49 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D CA 48 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E 44 02 0D 0A 00 8C 47 94 44 1C 4C AA 48 D4 48 +1E 44 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 45 +32 44 0A 44 40 FF DC 48 1E 44 09 46 52 41 4D 20 +66 75 6C 6C 08 45 B2 44 E0 4C CA 4C 0D 41 42 4F +52 54 22 00 0D 12 84 12 EA 48 0A 44 08 45 6A 4C +7C 49 FA 49 02 27 0D 12 84 12 AE 47 00 4A 68 4A +B0 44 46 4D 0E 49 52 4C 74 48 07 5B 27 5D 0D 12 +84 12 36 4D 0A 44 0A 44 6A 4C 6A 4C 7C 49 4A 4D +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D C2 48 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 AE 47 00 4A 68 4A B0 44 46 4D D4 48 AC 44 +9E 4D 0A 44 0A 44 6A 4C 6A 4C 0A 44 6A 4C 6A 4C +7C 49 00 00 02 3A 30 12 F4 4D 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 AE 47 00 4A BC 4D 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 44 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 45 60 4D 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A 44 7C 49 6A 4C 06 4E 62 4D 7C 49 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D B4 4C 0C 43 52 45 41 54 45 00 B0 12 AA 4D +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D 86 47 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D A4 4D 0E 3A 4E 4F 4E 41 4D 45 +30 12 F4 4D 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 3E 4E 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 36 4D C0 4E +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 4E 4D 0A 44 +C2 4E 6A 4C 7C 49 54 4E 08 43 4F 44 45 00 B0 12 +AA 4D A2 82 C8 1D 61 3C 96 49 0E 48 44 4E 43 4F +44 45 B2 40 AE 4F CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 06 4E 0C 4F 3D 41 92 42 +D0 1D CC 1D 5D 3C D8 4E 0E 43 4F 44 45 4E 4E 4D +30 12 E2 4E B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F EA 4E 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F 76 4F B2 40 88 4F D0 1D 82 4E CE 1D +30 40 0E 49 85 12 74 4F 74 4D 1C 4D 06 50 18 4F +6E 4E B8 49 62 4A 34 4D 5C 4F AE 4E 88 4E 24 4E +7C 4C 90 50 BA 4A 00 00 00 00 85 12 74 4F 0A 57 +8E 55 EE 56 B6 54 12 55 60 55 3C 56 48 56 D8 53 +FC 54 00 00 00 00 4A 4F C8 52 00 00 64 56 A8 4F +B2 40 88 4F CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +DC 4F 30 4D EE 4F 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 DC 4F 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 0E 46 FE FF 29 83 B9 40 FA 45 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 EC FF 3B 40 +10 00 3A 40 3A 18 B0 12 E0 4F 82 43 4A 18 C7 3F +82 50 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 6A 4D +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +AE 47 00 4A 68 4A AC 44 AE 50 A2 48 42 4C B0 50 +3E 4F 3D 41 B2 41 C6 1D B0 12 AA 4D BA 40 85 12 +FC FF BA 40 80 50 FE FF 28 83 8A 48 00 00 BA 40 +82 44 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +00 4A 68 4A AC 44 1A 51 FA 50 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 80 50 00 00 +01 20 3E 52 2E 83 21 53 30 41 12 4B AC 44 22 51 +16 51 24 51 B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 EA 50 15 20 3E 40 2B 00 +B0 12 EA 50 06 20 3E 40 2D 00 B0 12 EA 50 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 00 4A 12 4B AC 44 +46 4D 64 51 3E 51 3A 17 30 41 B0 12 2A 51 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 00 4A 12 4B AC 44 +9C 51 94 51 3E 90 10 00 E6 2B 7C 2D 9E 51 A2 41 +C6 1D E1 3F 03 20 B0 12 82 51 43 3C 7A 90 23 00 +24 20 B0 12 32 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 -30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D A2 53 -C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 26 00 -07 20 3C 40 10 02 92 53 C4 1D B0 12 D0 51 ED 3F -7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D B0 12 -58 52 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 58 52 -92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E -DA 3F B0 12 58 52 FA 23 3C 50 10 00 B0 12 34 52 -EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 -02 4C AC 51 56 53 FE 90 26 00 00 00 3E 40 20 00 -03 20 3C 50 82 00 C7 3F B0 12 58 52 E0 23 3C 50 -80 00 B0 12 34 52 DB 3F 00 00 04 52 45 54 49 00 -0D 12 84 12 0A 44 00 13 48 4B 4E 48 0A 44 2C 00 -80 52 4C 53 96 53 09 4B 2E 4E 0E DC A2 3F 40 4E -03 4D 4F 56 85 12 8C 53 00 40 A0 53 05 4D 4F 56 -2E 42 85 12 8C 53 40 40 00 00 03 41 44 44 85 12 -8C 53 00 50 BA 53 05 41 44 44 2E 42 85 12 8C 53 -40 50 C6 53 04 41 44 44 43 00 85 12 8C 53 00 60 -D4 53 06 41 44 44 43 2E 42 00 85 12 8C 53 40 60 -7A 53 04 53 55 42 43 00 85 12 8C 53 00 70 F2 53 -06 53 55 42 43 2E 42 00 85 12 8C 53 40 70 00 54 -03 53 55 42 85 12 8C 53 00 80 10 54 05 53 55 42 -2E 42 85 12 8C 53 40 80 16 4E 03 43 4D 50 85 12 -8C 53 00 90 2A 54 05 43 4D 50 2E 42 85 12 8C 53 -40 90 00 4E 04 44 41 44 44 00 85 12 8C 53 00 A0 -44 54 06 44 41 44 44 2E 42 00 85 12 8C 53 40 A0 -36 54 03 42 49 54 85 12 8C 53 00 B0 62 54 05 42 -49 54 2E 42 85 12 8C 53 40 B0 6E 54 03 42 49 43 -85 12 8C 53 00 C0 7C 54 05 42 49 43 2E 42 85 12 -8C 53 40 C0 88 54 03 42 49 53 85 12 8C 53 00 D0 -96 54 05 42 49 53 2E 42 85 12 8C 53 40 D0 00 00 -03 58 4F 52 85 12 8C 53 00 E0 B0 54 05 58 4F 52 -2E 42 85 12 8C 53 40 E0 E2 53 03 41 4E 44 85 12 -8C 53 00 F0 CA 54 05 41 4E 44 2E 42 85 12 8C 53 -40 F0 02 4C 80 52 E8 54 0A 4C 3C F0 70 00 8A 10 -3A F0 0F 00 0C DA 4F 3F 1C 54 03 52 52 43 85 12 -E2 54 00 10 FA 54 05 52 52 43 2E 42 85 12 E2 54 -40 10 06 55 04 53 57 50 42 00 85 12 E2 54 80 10 -14 55 03 52 52 41 85 12 E2 54 00 11 22 55 05 52 -52 41 2E 42 85 12 E2 54 40 11 2E 55 03 53 58 54 -85 12 E2 54 80 11 00 00 04 50 55 53 48 00 85 12 -E2 54 00 12 48 55 06 50 55 53 48 2E 42 00 85 12 -E2 54 40 12 A2 54 04 43 41 4C 4C 00 85 12 E2 54 -80 12 1A 53 0E 4A 0D 12 84 12 C4 48 14 44 0D 6F -75 74 20 6F 66 20 62 6F 75 6E 64 73 36 45 3C 55 -03 53 3E 3D 86 12 00 38 90 55 02 53 3C 00 86 12 -00 34 56 55 03 30 3E 3D 86 12 00 30 A4 55 02 30 -3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 00 2C -B8 55 03 55 3E 3D 86 12 00 28 AE 55 03 30 3C 3E -86 12 00 24 CC 55 02 30 3D 00 86 12 00 20 00 00 -02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D -0E 4A 30 4D C2 55 04 54 48 45 4E 00 1A 42 C6 1D -08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 -B1 2F 88 DA 00 00 30 4D 52 54 04 45 4C 53 45 00 -1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 -8F 4A 00 00 E3 3F 66 55 05 42 45 47 49 4E 30 40 -28 44 F6 55 05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F -19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B -3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D 30 4D -D6 54 05 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F -00 00 05 57 48 49 4C 45 0D 12 84 12 E4 55 A8 47 -4E 48 9A 55 06 52 45 50 45 41 54 00 0D 12 84 12 -78 56 FC 55 4E 48 A8 56 3D 41 08 4E 3E 4F 2A 48 -B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D 38 56 -03 42 57 31 85 12 A6 56 00 00 C0 56 03 42 57 32 -85 12 A6 56 00 00 CC 56 03 42 57 33 85 12 A6 56 -00 00 E4 56 3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D -88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F -30 4D 00 00 03 46 57 31 85 12 E2 56 00 00 04 57 -03 46 57 32 85 12 E2 56 00 00 10 57 03 46 57 33 -85 12 E2 56 00 00 1C 57 04 47 4F 54 4F 00 2F 83 -8F 4E 00 00 3E 40 00 3C 0D 12 84 12 80 4C DC 4B -4E 48 00 00 05 3F 47 4F 54 4F 3E 90 00 30 F4 27 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 32 51 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 7E 51 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 82 51 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 6A 51 +F2 3F 03 20 B0 12 82 51 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 6A 51 EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 44 00 13 6A 4C 7C 49 +0A 44 2C 00 60 52 A4 51 AE 47 6A 52 42 52 B0 52 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 A0 52 00 40 BC 52 0A 4D 4F 56 2E 42 85 12 +A0 52 40 40 00 00 06 41 44 44 85 12 A0 52 00 50 +D6 52 0A 41 44 44 2E 42 85 12 A0 52 40 50 E2 52 +08 41 44 44 43 00 85 12 A0 52 00 60 F0 52 0C 41 +44 44 43 2E 42 00 85 12 A0 52 40 60 28 4F 08 53 +55 42 43 00 85 12 A0 52 00 70 0E 53 0C 53 55 42 +43 2E 42 00 85 12 A0 52 40 70 1C 53 06 53 55 42 +85 12 A0 52 00 80 2C 53 0A 53 55 42 2E 42 85 12 +A0 52 40 80 38 53 06 43 4D 50 85 12 A0 52 00 90 +46 53 0A 43 4D 50 2E 42 85 12 A0 52 40 90 00 00 +08 44 41 44 44 00 85 12 A0 52 00 A0 60 53 0C 44 +41 44 44 2E 42 00 85 12 A0 52 40 A0 8E 52 06 42 +49 54 85 12 A0 52 00 B0 7E 53 0A 42 49 54 2E 42 +85 12 A0 52 40 B0 8A 53 06 42 49 43 85 12 A0 52 +00 C0 98 53 0A 42 49 43 2E 42 85 12 A0 52 40 C0 +A4 53 06 42 49 53 85 12 A0 52 00 D0 B2 53 0A 42 +49 53 2E 42 85 12 A0 52 40 D0 00 00 06 58 4F 52 +85 12 A0 52 00 E0 CC 53 0A 58 4F 52 2E 42 85 12 +A0 52 40 E0 FE 52 06 41 4E 44 85 12 A0 52 00 F0 +E6 53 0A 41 4E 44 2E 42 85 12 A0 52 40 F0 AE 47 +60 52 A4 51 06 54 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F BE 53 06 52 52 43 85 12 FE 53 +00 10 18 54 0A 52 52 43 2E 42 85 12 FE 53 40 10 +52 53 08 53 57 50 42 00 85 12 FE 53 80 10 24 54 +06 52 52 41 85 12 FE 53 00 11 40 54 0A 52 52 41 +2E 42 85 12 FE 53 40 11 32 54 06 53 58 54 85 12 +FE 53 80 11 00 00 08 50 55 53 48 00 85 12 FE 53 +00 12 66 54 0C 50 55 53 48 2E 42 00 85 12 FE 53 +40 12 5A 54 08 43 41 4C 4C 00 85 12 FE 53 80 12 +1A 53 0E 4A 84 12 F0 49 1E 44 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 45 84 54 06 53 3E 3D +86 12 00 38 AC 54 04 53 3C 00 86 12 00 34 74 54 +06 30 3E 3D 86 12 00 30 C0 54 04 30 3C 00 86 12 +00 30 FC 4E 04 55 3C 00 86 12 00 2C D4 54 06 55 +3E 3D 86 12 00 28 CA 54 06 30 3C 3E 86 12 00 24 +E8 54 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +6E 53 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D DE 54 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F 4C 54 0A 42 45 47 49 4E 30 40 32 44 36 55 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D F2 53 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 00 55 96 48 7C 49 54 55 +0C 52 45 50 45 41 54 00 0D 12 84 12 94 55 18 55 +7C 49 C4 55 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D B0 55 06 42 57 31 +85 12 C2 55 00 00 DC 55 06 42 57 32 85 12 C2 55 +00 00 E8 55 06 42 57 33 85 12 C2 55 00 00 00 56 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 FE 55 00 00 24 56 +06 46 57 32 85 12 FE 55 00 00 30 56 06 46 57 33 +85 12 FE 55 00 00 9E 55 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 36 4D 42 4C +7C 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F -02 4C AC 51 66 57 92 53 C4 1D 3E 40 2C 00 84 12 -1A 49 3E 4A 34 44 00 4C 42 53 7C 57 0A 4E 3E 4F -1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 -0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 -E8 2E 8A 10 5A 06 A6 3E 94 56 04 52 52 43 4D 00 -85 12 60 57 50 00 AA 57 04 52 52 41 4D 00 85 12 -60 57 50 01 B8 57 04 52 4C 41 4D 00 85 12 60 57 -50 02 C6 57 04 52 52 55 4D 00 85 12 60 57 50 03 -D6 55 05 50 55 53 48 4D 85 12 60 57 00 15 E2 57 -04 50 4F 50 4D 00 85 12 60 57 00 17 +6A 52 0A 44 2C 00 00 4A 12 4B AC 44 46 4D AE 47 +60 52 42 52 96 56 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E F4 55 08 52 52 43 4D 00 85 12 80 56 50 00 +C4 56 08 52 52 41 4D 00 85 12 80 56 50 01 D2 56 +08 52 4C 41 4D 00 85 12 80 56 50 02 E0 56 08 52 +52 55 4D 00 85 12 80 56 50 03 F2 54 0A 50 55 53 +48 4D 85 12 80 56 00 15 FC 56 08 50 4F 50 4D 00 +85 12 80 56 00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 82 46 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 08 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 D6 46 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 0E 46 q diff --git a/binaries/MSP_EXP430FR6989_1MHz_UART.txt b/binaries/MSP_EXP430FR6989_1MHz_UART.txt deleted file mode 100644 index bdae606..0000000 --- a/binaries/MSP_EXP430FR6989_1MHz_UART.txt +++ /dev/null @@ -1,338 +0,0 @@ -@1800 -E8 03 08 00 00 D6 18 00 F9 FF 12 58 02 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 94 46 12 58 -02 50 7A 46 92 47 24 47 FE 46 3C 1D 60 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 78 46 B2 49 90 47 B2 49 22 47 B2 49 FC 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 FC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -FC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E0 47 32 47 -14 44 04 1B 5B 37 6D 00 5C 47 A8 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 47 A0 48 5C 47 14 44 04 1B 5B 30 6D 00 -5C 47 28 4C 92 B3 EA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 E0 05 92 42 02 18 E6 05 92 42 04 18 -E8 05 F2 D0 30 00 2A 02 92 C3 E0 05 92 D3 FA 05 -92 C3 30 01 30 41 09 3C A2 B3 FC 05 FD 27 B2 40 -13 00 EE 05 D2 D3 22 02 30 41 A2 B3 FC 05 FD 27 -B2 40 11 00 EE 05 D2 C3 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 B0 12 -9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 5C 47 -D6 48 14 44 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 47 -0A 44 40 FF 28 44 D4 47 A0 48 14 44 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 44 86 45 00 00 06 41 -43 43 45 50 54 00 30 40 7A 46 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 46 3C 40 D2 46 -5D 15 B6 3E 21 52 3A 17 58 42 EC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 FC 05 FD 27 -C2 48 EE 05 30 4D C8 46 2D 83 92 B3 FC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 FC 05 -FD 27 58 42 EC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 46 2F 83 -8F 4E 00 00 B0 12 DA 45 92 B3 FC 05 FD 27 1E 42 -EC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 47 08 4E 3E 4F C8 3F 1A 47 04 45 43 48 -4F 00 B2 40 C2 48 C0 46 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 46 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 47 7A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 30 40 -92 47 0D 12 84 12 14 44 02 0D 0A 00 5C 47 60 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 46 01 40 -2E 4E 30 4D DE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A 48 02 23 53 00 0D 12 -84 12 1C 48 56 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 48 4E 48 EE 44 8E 48 6A 48 5C 47 14 4C 20 47 -60 48 40 47 01 2E 0E 93 E3 37 38 43 E2 3F 88 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -5A 4B 0A 44 22 00 2C 49 FA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 48 82 2E 22 00 0D 12 84 12 E4 48 0A 44 5C 47 -5A 4B 60 48 18 46 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 14 4C 2C 49 D0 4B -9C 26 3D 40 D8 4B DE 3E DA 4B 0A 4E 3E 4F 3D 40 -F4 4B 36 27 3D 40 CA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 4B 3E 4F 3D 40 CA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 4D -CC 3F FE 4B 86 12 20 00 E6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E 47 -BC 44 C4 4B C4 47 F6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -FE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 3E 4C 1A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 48 0A 44 2A 45 5A 4B 60 48 8E 49 -01 27 0D 12 84 12 14 4C 2C 49 94 49 34 44 12 4C -60 48 00 00 83 5B 27 5D 0D 12 84 12 92 4C 0A 44 -0A 44 5A 4B 5A 4B 60 48 A4 4C 81 5B 82 43 BE 1D -30 4D 0C 48 01 5D B2 43 BE 1D 30 4D C4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 4C 2C 49 94 49 A8 47 -34 44 12 4C F6 47 34 44 06 4D 0A 44 0A 44 5A 4B -5A 4B 0A 44 5A 4B 5A 4B 60 48 BA 4C 01 3A 30 12 -56 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 4C -2C 49 24 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 0C 4D 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 60 48 5A 4B 68 4D BC 4C -60 48 BA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 4B 06 43 52 45 -41 54 45 00 B0 12 12 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 4D 04 43 4F 44 45 00 B0 12 12 4D -A2 82 C6 1D 0D 12 84 12 04 50 DE 4F 60 48 B4 4D -07 48 44 4E 43 4F 44 45 B2 40 E2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 4D -1E 50 3C 50 60 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E 50 3C 50 60 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 4E 85 48 49 32 4C 4F 0D 12 84 12 28 44 -AC 4F 5A 4B BC 4C F4 4D 60 48 9A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 D8 47 14 4C 2C 49 -AA 4B A0 47 34 44 14 4F AE 47 14 44 06 5B 54 48 -45 4E 5D 00 86 4E EE 4E AA 4E CC 4E 60 48 AE 47 -14 44 06 5B 45 4C 53 45 5D 00 86 4E 04 4F AA 4E -CA 4E 60 48 14 44 04 5B 49 46 5D 00 86 4E CC 4E -3A 44 CA 4E 82 47 14 44 05 0D 0A 6B 6F 20 5C 47 -BC 44 AC 44 3A 44 CC 4E BA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 4C 2C 49 -94 49 38 4F 60 48 3E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 4F F0 47 60 48 70 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 4B -06 4D 41 52 4B 45 52 00 B0 12 12 4D BA 40 85 12 -FC FF BA 40 6E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D E8 47 60 48 85 12 B0 4F 78 4C E6 4D -2C 47 90 4C 64 4E F6 46 80 4F 12 49 A8 50 BC 50 -9C 48 26 49 00 00 58 4F CE 4C F4 49 00 00 85 12 -B0 4F 88 56 EE 56 30 56 3E 57 F6 55 00 00 C2 53 -00 00 06 58 EA 57 5A 56 98 56 D2 54 00 00 00 00 -5A 57 DC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 4F 36 50 3C 50 4C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 44 50 -12 58 E0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 50 F3 3F 82 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 50 30 4D 94 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 51 FE FF 29 83 -B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 20 46 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 -22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 -66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 -F2 43 26 03 F2 43 22 03 F2 40 A5 00 61 01 82 43 -62 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 -39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 -B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 -1E 42 08 18 82 43 08 18 1E D2 9E 01 B0 12 F8 44 -1E 46 38 40 C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 -C4 1D 09 9E 03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 -82 4A C4 1D 30 4D 1C 15 0E 12 12 12 C4 1D 84 12 -2C 49 94 49 F0 47 34 44 02 52 50 4A 34 44 1C 52 -16 52 04 52 3C 4E 3C 80 87 12 05 24 1C 53 02 20 -2E 4E 01 3C 2E 83 21 52 1B 17 30 41 1E 52 B2 41 -C4 1D 3E 41 84 12 0A 44 2B 00 2C 49 94 49 F0 47 -34 44 3A 52 50 4A 34 44 12 4C BA 47 2C 49 50 4A -34 44 12 4C 46 52 3E 5F E7 3F 3E 40 28 00 B0 12 -E6 51 19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 -29 00 92 92 C0 1D C4 1D 02 20 30 40 80 4D 1C 15 -12 12 C4 1D 92 53 C4 1D 84 12 2C 49 50 4A 34 44 -8E 52 84 52 21 53 3E 90 10 00 C6 2B 7F 2D 90 52 -B2 41 C4 1D C1 3F 0D 12 84 12 14 4C C2 51 A0 52 -0C 43 1B 42 C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 -23 00 27 20 92 53 C4 1D B0 12 E6 51 3C 40 00 03 -0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 -2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 -3E 92 0C 24 3C 40 30 03 3E 93 08 24 3C 40 30 00 -19 42 C6 1D A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 -30 4D 7A 90 26 00 07 20 3C 40 10 02 92 53 C4 1D -B0 12 E6 51 ED 3F 7A 90 40 00 16 20 3C 40 20 00 -92 53 C4 1D B0 12 6E 52 0C 20 3C 50 10 00 3E 40 -2B 00 B0 12 6E 52 92 92 C0 1D C4 1D 02 24 92 53 -C4 1D 8E 10 0C 5E DA 3F B0 12 6E 52 FA 23 3C 50 -10 00 B0 12 4A 52 EF 3F 0C 43 1B 42 C6 1D A2 53 -C6 1D 0D 12 84 12 14 4C C2 51 6C 53 FE 90 26 00 -00 00 3E 40 20 00 03 20 3C 50 82 00 C7 3F B0 12 -6E 52 E0 23 3C 50 80 00 B0 12 4A 52 DB 3F 00 00 -04 52 45 54 49 00 0D 12 84 12 0A 44 00 13 5A 4B -60 48 0A 44 2C 00 96 52 62 53 AC 53 09 4B 2E 4E -0E DC A2 3F 52 4E 03 4D 4F 56 85 12 A2 53 00 40 -B6 53 05 4D 4F 56 2E 42 85 12 A2 53 40 40 00 00 -03 41 44 44 85 12 A2 53 00 50 D0 53 05 41 44 44 -2E 42 85 12 A2 53 40 50 DC 53 04 41 44 44 43 00 -85 12 A2 53 00 60 EA 53 06 41 44 44 43 2E 42 00 -85 12 A2 53 40 60 90 53 04 53 55 42 43 00 85 12 -A2 53 00 70 08 54 06 53 55 42 43 2E 42 00 85 12 -A2 53 40 70 16 54 03 53 55 42 85 12 A2 53 00 80 -26 54 05 53 55 42 2E 42 85 12 A2 53 40 80 28 4E -03 43 4D 50 85 12 A2 53 00 90 40 54 05 43 4D 50 -2E 42 85 12 A2 53 40 90 12 4E 04 44 41 44 44 00 -85 12 A2 53 00 A0 5A 54 06 44 41 44 44 2E 42 00 -85 12 A2 53 40 A0 4C 54 03 42 49 54 85 12 A2 53 -00 B0 78 54 05 42 49 54 2E 42 85 12 A2 53 40 B0 -84 54 03 42 49 43 85 12 A2 53 00 C0 92 54 05 42 -49 43 2E 42 85 12 A2 53 40 C0 9E 54 03 42 49 53 -85 12 A2 53 00 D0 AC 54 05 42 49 53 2E 42 85 12 -A2 53 40 D0 00 00 03 58 4F 52 85 12 A2 53 00 E0 -C6 54 05 58 4F 52 2E 42 85 12 A2 53 40 E0 F8 53 -03 41 4E 44 85 12 A2 53 00 F0 E0 54 05 41 4E 44 -2E 42 85 12 A2 53 40 F0 14 4C 96 52 FE 54 0A 4C -3C F0 70 00 8A 10 3A F0 0F 00 0C DA 4F 3F 32 54 -03 52 52 43 85 12 F8 54 00 10 10 55 05 52 52 43 -2E 42 85 12 F8 54 40 10 1C 55 04 53 57 50 42 00 -85 12 F8 54 80 10 2A 55 03 52 52 41 85 12 F8 54 -00 11 38 55 05 52 52 41 2E 42 85 12 F8 54 40 11 -44 55 03 53 58 54 85 12 F8 54 80 11 00 00 04 50 -55 53 48 00 85 12 F8 54 00 12 5E 55 06 50 55 53 -48 2E 42 00 85 12 F8 54 40 12 B8 54 04 43 41 4C -4C 00 85 12 F8 54 80 12 1A 53 0E 4A 0D 12 84 12 -D6 48 14 44 0D 6F 75 74 20 6F 66 20 62 6F 75 6E -64 73 36 45 52 55 03 53 3E 3D 86 12 00 38 A6 55 -02 53 3C 00 86 12 00 34 6C 55 03 30 3E 3D 86 12 -00 30 BA 55 02 30 3C 00 86 12 00 30 00 00 02 55 -3C 00 86 12 00 2C CE 55 03 55 3E 3D 86 12 00 28 -C4 55 03 30 3C 3E 86 12 00 24 E2 55 02 30 3D 00 -86 12 00 20 00 00 02 49 46 00 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 0E 4A 30 4D D8 55 04 54 48 45 -4E 00 1A 42 C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 -0A 11 3A 90 00 02 B1 2F 88 DA 00 00 30 4D 68 54 -04 45 4C 53 45 00 1A 42 C6 1D BA 40 00 3C 00 00 -A2 53 C6 1D 2F 83 8F 4A 00 00 E3 3F 7C 55 05 42 -45 47 49 4E 30 40 28 44 0C 56 05 55 4E 54 49 4C -3A 4F 08 4E 3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 -3A 90 00 FE 8A 3B 3A F0 FF 03 08 DA 89 48 00 00 -A2 53 C6 1D 30 4D EC 54 05 41 47 41 49 4E 0A 4E -38 40 00 3C E7 3F 00 00 05 57 48 49 4C 45 0D 12 -84 12 FA 55 BA 47 60 48 B0 55 06 52 45 50 45 41 -54 00 0D 12 84 12 8E 56 12 56 60 48 BE 56 3D 41 -08 4E 3E 4F 2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D -00 00 30 4D 4E 56 03 42 57 31 85 12 BC 56 00 00 -D6 56 03 42 57 32 85 12 BC 56 00 00 E2 56 03 42 -57 33 85 12 BC 56 00 00 FA 56 3D 41 1A 42 C6 1D -28 4E B2 92 C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D -8E 4A 00 00 3E 4F 30 4D 00 00 03 46 57 31 85 12 -F8 56 00 00 1A 57 03 46 57 32 85 12 F8 56 00 00 -26 57 03 46 57 33 85 12 F8 56 00 00 32 57 04 47 -4F 54 4F 00 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 -84 12 92 4C EE 4B 60 48 00 00 05 3F 47 4F 54 4F -3E 90 00 30 F4 27 3E E0 00 04 3E B0 00 10 EF 27 -3E E0 00 08 EC 3F 14 4C C2 51 7C 57 92 53 C4 1D -3E 40 2C 00 84 12 2C 49 50 4A 34 44 12 4C 58 53 -92 57 0A 4E 3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 -08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EC 2E -5A 0E AB 3E 2A 92 E8 2E 8A 10 5A 06 A6 3E AA 56 -04 52 52 43 4D 00 85 12 76 57 50 00 C0 57 04 52 -52 41 4D 00 85 12 76 57 50 01 CE 57 04 52 4C 41 -4D 00 85 12 76 57 50 02 DC 57 04 52 52 55 4D 00 -85 12 76 57 50 03 EC 55 05 50 55 53 48 4D 85 12 -76 57 00 15 F8 57 04 50 4F 50 4D 00 85 12 76 57 -00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 94 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 1A 51 -q diff --git a/binaries/MSP_EXP430FR6989_8MHz_115200.txt b/binaries/MSP_EXP430FR6989_8MHz_115200.txt new file mode 100644 index 0000000..9dbbe93 --- /dev/null +++ b/binaries/MSP_EXP430FR6989_8MHz_115200.txt @@ -0,0 +1,326 @@ +@1800 +40 1F 04 00 51 55 18 00 FD FF 35 01 10 00 A1 59 +D8 46 7E 45 84 45 54 45 48 47 36 57 EE 4F A8 4F +A8 4F BE 46 7C 47 44 47 3C 1D E0 1C 9C 49 B6 44 +C4 44 B8 48 20 00 0A 00 00 1C 7E 45 84 45 54 45 +48 47 36 57 EE 4F A8 4F A8 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 +@4400 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 07 3D 0E 93 3E 4F +9C 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BC 46 B2 49 +7A 47 B2 49 42 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 62 50 8F 93 02 00 02 20 2F 52 +BF 3F B0 12 48 47 92 C3 FC 05 18 42 00 18 39 40 +41 00 19 83 FE 23 18 83 FA 23 92 B3 FC 05 F3 23 +B0 12 D0 44 C2 48 AC 44 52 45 8A 47 1E 44 04 1B +5B 37 6D 00 AC 47 AC 47 1E 44 04 1B 5B 30 6D 00 +AC 47 F8 4C B0 12 7E 45 B2 40 81 00 E0 05 92 42 +02 18 E6 05 92 42 04 18 E8 05 F2 D0 30 00 2A 02 +92 C3 E0 05 92 D3 FA 05 92 C3 30 01 30 41 92 B3 +EA 05 FD 23 30 41 92 12 3E 18 84 12 8A 47 1E 44 +07 0D 0A 1B 5B 37 6D 23 AC 47 10 4A 1E 44 19 46 +61 73 74 46 6F 72 74 68 20 A9 4A 2E 4D 2E 54 68 +6F 6F 72 65 6E 73 2C 20 AC 47 0A 44 40 FF 32 44 +D8 48 DC 49 1E 44 0A 62 79 74 65 73 20 66 72 65 +65 00 B2 44 46 45 00 00 06 53 59 53 0E 93 07 38 +02 24 1E B3 04 28 30 12 86 45 01 12 71 3F 82 4E +08 18 92 12 3A 18 E2 B3 00 02 02 20 B2 43 08 18 +B2 40 04 A5 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +00 01 B2 40 80 5A 5C 01 3F 40 80 1C 31 40 E0 1C +B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 +22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 +66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 +F2 43 26 03 F2 43 22 03 F2 40 A5 00 61 01 82 43 +66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 +18 42 00 18 18 83 FE 23 19 83 FA 23 B2 42 B0 01 +F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 39 40 00 08 +29 83 89 43 00 1C FC 23 19 42 9E 01 1E 42 08 18 +82 43 08 18 3E F3 01 20 0E 49 B0 12 D0 44 86 45 +00 00 0C 41 43 43 45 50 54 00 30 40 BE 46 08 4E +2E 4F 08 5E 39 40 0D 00 3A 40 20 00 3B 40 1C 47 +3C 40 28 47 5D 15 94 3E 21 52 3A 17 58 42 EC 05 +48 9B 09 20 A2 B3 FC 05 FD 27 B2 40 13 00 EE 05 +D2 D3 22 02 30 41 48 9C 06 2C 78 92 11 20 2E 9F +0F 24 1E 83 05 3C 0E 9A 03 2C CE 48 00 00 1E 53 +A2 B3 FC 05 FD 27 C2 48 EE 05 30 4D 1E 47 2D 83 +92 B3 FC 05 DB 23 FC 3F 3E 8F 3D 41 92 B3 FC 05 +FD 27 58 42 EC 05 08 4C EB 3F 00 00 06 4B 45 59 +30 40 44 47 30 12 5A 47 A2 B3 FC 05 FD 27 B2 40 +11 00 EE 05 D2 C3 22 02 30 41 2F 83 8F 4E 00 00 +92 B3 FC 05 FD 27 B0 12 E4 46 1E 42 EC 05 30 4D +00 00 08 45 4D 49 54 00 30 40 7C 47 08 4E 3E 4F +C7 3F 72 47 08 45 43 48 4F 00 B2 40 C2 48 16 47 +30 4D 00 00 0C 4E 4F 45 43 48 4F 00 B2 40 30 4D +16 47 30 4D 00 00 08 54 59 50 45 00 0D 12 3D 40 +BC 47 29 4F 8F 4E 00 00 7E 49 DE 3F BE 47 2D 83 +2F 83 5E 83 F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 +20 00 0C 4E 38 4F 3C 9F 39 4F 3E 4F 6A 22 F9 98 +00 00 67 22 19 53 1C 83 FA 23 2D 53 30 4D 2F 53 +3E 4F 1E 83 5E 22 9B 24 3C 47 0D 5B 45 4C 53 45 +5D 00 0D 12 84 12 0A 44 00 00 DC 48 CE 47 20 4A +DA 4C B0 44 4A 48 14 44 06 5B 54 48 45 4E 5D 00 +D2 47 28 48 EE 47 0C 48 14 44 06 5B 45 4C 53 45 +5D 00 D2 47 3A 48 EE 47 0A 48 1E 44 04 5B 49 46 +5D 00 D2 47 0C 48 B2 44 0A 48 1E 44 05 0D 6B 6F +20 0A AC 47 9A 44 84 44 B2 44 0C 48 FA 47 0D 5B +54 48 45 4E 5D 00 30 4D 5E 48 09 5B 49 46 5D 00 +0E 93 3E 4F C6 27 30 4D 6A 48 13 5B 44 45 46 49 +4E 45 44 5D 0D 12 84 12 CE 47 20 4A 88 4A 2C 4C +9C 49 7A 48 17 5B 55 4E 44 45 46 49 4E 45 44 5D +0D 12 84 12 CE 47 20 4A 88 4A AC 48 3D 41 2F 53 +1E 83 0E 7E 30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 +30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 +80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D +00 00 02 40 2E 4E 30 4D B2 46 02 21 BE 4F 00 00 +3E 4F 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 +0E F3 30 4D D8 45 05 53 22 00 82 43 C0 1D 0D 12 +84 12 0A 44 1E 44 8A 4C 0A 44 22 00 20 4A 20 49 +B2 40 20 00 C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F +3D 41 30 4D 94 47 05 2E 22 00 0D 12 84 12 0A 49 +0A 44 AC 47 8A 4C 9C 49 00 00 04 3C 23 00 B2 40 +B2 1D B2 1D 30 4D 06 49 02 23 1B 42 BE 1D 2C 4F +2F 83 B0 12 46 44 BF 4F 00 00 7A 90 0A 00 02 28 +7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D +C8 4A 00 00 30 4D 58 49 04 23 53 00 0D 12 84 12 +5A 49 94 49 2D 83 09 DE 09 93 E1 23 3D 41 30 4D +88 49 04 23 3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D +2E 8F 30 4D 00 00 08 48 4F 4C 44 00 4A 4E 3E 4F +DB 3F A2 49 08 53 49 47 4E 00 0E 93 3E 4F 7A 40 +2D 00 D2 33 30 4D 84 47 04 55 2E 00 0C 43 2F 83 +8F 4E 00 00 0E 4C 1D 15 3E F3 06 34 BF E3 00 00 +3E E3 9F 53 00 00 0E 63 84 12 4E 49 CE 47 BC 49 +8C 49 B8 48 CA 49 A6 49 AC 47 9C 49 36 49 02 2E +0E 93 E4 37 3C 43 E3 3F 00 00 08 57 4F 52 44 00 +3C 40 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 +1D 24 7E 98 FC 27 18 83 1B 42 C0 1D F8 90 27 00 +00 00 04 20 E8 98 02 00 01 20 0B 43 CA 4C 00 00 +09 98 0C 24 7C 48 4E 9C 09 24 1A 53 7C 90 61 00 +F5 2B 7C 90 7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D +82 48 C6 1D 1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D +00 00 08 46 49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D +3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 0F 00 08 58 +0E 58 2E 53 1E 4E FE FF 0E 93 F2 27 09 4E 78 49 +48 11 68 9C F7 23 0A 4C FA 99 01 00 F3 23 1A 53 +58 83 FA 23 19 B3 09 63 0C 49 6E 4E 1E F3 01 20 +1E 83 8F 4C 00 00 30 4D 0E 4A 0E 3E 4E 55 4D 42 +45 52 1B 42 BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B +C0 04 6A 4C 7A 80 3A 00 03 28 7A 80 07 00 12 28 +7A 50 0A 00 0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 +E2 04 19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 +1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 +30 4D 32 C0 00 02 3F 82 8F 4E 06 00 08 43 09 43 +1B 42 BE 1D 0C 4E 0E 43 1E 15 3D 40 92 4B 7E 4C +6A 4C 7A 80 2D 00 16 24 CA 2F 2B 43 7A 52 14 24 +3B 52 6A 53 11 24 3B 40 10 00 5A 93 0D 24 6A 92 +41 20 3E 90 03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C +04 00 38 3C B1 43 02 00 1E 83 FC 9C 00 00 E0 23 +AE 27 94 4B 2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 +32 B0 00 02 27 20 32 D0 00 02 7A 80 2E 00 B7 27 +6A 53 20 20 0A 4E 09 43 8F 49 02 00 5A 83 09 4A +09 5C 69 49 79 80 3A 00 03 28 79 80 07 00 0C 28 +79 50 0A 00 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 +B0 12 3E 44 2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F +04 00 4A 93 1D 17 06 24 32 C0 00 02 3F 50 06 00 +0E F3 30 4D 2F 53 9F 4F 02 00 04 00 BF 4F 00 00 +3E E3 09 20 3E E3 BF E3 02 00 BF E3 00 00 9F 53 +02 00 8F 63 00 00 32 B0 00 02 01 20 2F 53 30 4D +4A 49 03 5C 92 42 C2 1D C6 1D 30 4D 0D 12 84 12 +84 44 CE 47 20 4A B0 44 64 4D 88 4A 4E 4C 0A 4E +3E 4F 3D 40 68 4C 6D 27 3D 40 42 4C 1A E2 BC 1D +14 24 0E 12 3E 4F 30 41 6A 4C 3E 4F 3D 40 42 4C +19 20 DE 53 00 00 68 4E 08 5E F8 40 3F 00 00 00 +3D 40 40 4E 2A 3C 32 4C 02 2C A2 53 C8 1D 1A 42 +C8 1D 8A 4E FE FF 3E 4F 30 4D 88 4C 0F 4C 49 54 +45 52 41 4C 82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D +A2 52 C8 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F +32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F +30 4D C4 49 0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E +00 00 0E 4A 3E F3 30 4D EA 48 0A 41 4C 4C 4F 54 +82 5E C8 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 +1E 44 02 0D 0A 00 AC 47 94 44 3C 4C CA 48 F4 48 +1E 44 0B 73 74 61 63 6B 20 65 6D 70 74 79 08 45 +32 44 0A 44 40 FF FC 48 1E 44 09 46 52 41 4D 20 +66 75 6C 6C 08 45 B2 44 00 4D EA 4C 0D 41 42 4F +52 54 22 00 0D 12 84 12 0A 49 0A 44 08 45 8A 4C +9C 49 1A 4A 02 27 0D 12 84 12 CE 47 20 4A 88 4A +B0 44 66 4D 2E 49 72 4C 94 48 07 5B 27 5D 0D 12 +84 12 56 4D 0A 44 0A 44 8A 4C 8A 4C 9C 49 6A 4D +03 5B 82 43 BC 1D 30 4D 00 00 02 5D B2 43 BC 1D +30 4D E2 48 11 50 4F 53 54 50 4F 4E 45 00 0D 12 +84 12 CE 47 20 4A 88 4A B0 44 66 4D F4 48 AC 44 +BE 4D 0A 44 0A 44 8A 4C 8A 4C 0A 44 8A 4C 8A 4C +9C 49 00 00 02 3A 30 12 14 4E 92 B3 C8 1D A2 63 +C8 1D 0D 12 84 12 CE 47 20 4A DC 4D 3D 41 5A D3 +5A 53 0A 5E 19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 +0F 00 0E 5E 09 5E 3E 4F E8 58 00 00 82 48 B4 1D +82 49 B6 1D 82 4A B8 1D 82 4F BA 1D 2A 52 82 4A +C8 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF +B2 43 BC 1D 30 4D 82 9F BA 1D 66 25 84 12 1E 44 +0F 73 74 61 63 6B 20 6D 69 73 6D 61 74 63 68 21 +12 45 80 4D 03 3B 82 93 BC 1D F4 26 0D 12 84 12 +0A 44 9C 49 8A 4C 26 4E 82 4D 9C 49 00 00 12 49 +4D 4D 45 44 49 41 54 45 18 42 B4 1D D8 D3 00 00 +30 4D D4 4C 0C 43 52 45 41 54 45 00 B0 12 CA 4D +BA 40 86 12 FC FF 8A 4A FE FF 3A 3D A6 47 0A 44 +4F 45 53 3E 1A 42 B8 1D BA 40 85 12 00 00 8A 4D +02 00 3D 41 30 4D C4 4D 0E 3A 4E 4F 4E 41 4D 45 +30 12 14 4E 2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 +0A 63 0E 4A 39 40 12 02 08 49 98 3F 5E 4E 05 49 +53 00 0D 12 82 93 BC 1D 08 20 84 12 56 4D E0 4E +3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 6E 4D 0A 44 +E2 4E 8A 4C 9C 49 74 4E 08 43 4F 44 45 00 B0 12 +CA 4D A2 82 C8 1D 61 3C B6 49 0E 48 44 4E 43 4F +44 45 B2 40 CE 4F CC 1D F2 3F 00 00 0E 45 4E 44 +43 4F 44 45 0D 12 84 12 26 4E 2C 4F 3D 41 92 42 +D0 1D CC 1D 5D 3C F8 4E 0E 43 4F 44 45 4E 4E 4D +30 12 02 4F B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 +C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 +C8 1D B2 43 BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 +A2 83 C8 1D 1A 42 C8 1D EF 3F 0A 4F 0B 48 49 32 +4C 4F A2 53 C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 +BC 1D B9 3F 96 4F B2 40 A8 4F D0 1D 82 4E CE 1D +30 40 2E 49 85 12 94 4F 94 4D 3C 4D 26 50 38 4F +8E 4E D8 49 82 4A 54 4D 7C 4F CE 4E A8 4E 44 4E +9C 4C B0 50 DA 4A 00 00 00 00 85 12 94 4F 2A 57 +AE 55 0E 57 D6 54 32 55 80 55 5C 56 68 56 F8 53 +1C 55 00 00 00 00 6A 4F E8 52 00 00 84 56 C8 4F +B2 40 A8 4F CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 +BA 49 00 00 2A 53 2B 83 FB 23 30 41 00 00 0E 52 +53 54 5F 53 45 54 39 40 C8 1D 3A 40 42 18 B0 12 +FC 4F 30 4D 0E 50 0E 52 53 54 5F 52 45 54 39 40 +42 18 2C 49 3A 40 C8 1D B0 12 FC 4F 1A 42 CA 1D +3B 40 10 00 09 4A 08 49 29 83 18 48 FE FF 0C 98 +FC 2B 89 48 00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 +30 4D 0E 93 E4 37 39 40 10 00 29 83 B9 43 80 FF +FC 23 B9 40 06 46 FE FF 29 83 B9 40 F2 45 FE FF +39 90 AE FF F9 23 39 40 10 18 B2 49 E4 FF 3B 40 +10 00 3A 40 3A 18 B0 12 00 50 82 43 4A 18 C7 3F +A2 50 B2 4E 42 18 BE 12 3E 4F 3D 41 C0 3F 8A 4D +0C 4D 41 52 4B 45 52 00 12 12 C6 1D 0D 12 84 12 +CE 47 20 4A 88 4A AC 44 CE 50 C2 48 62 4C D0 50 +3E 4F 3D 41 B2 41 C6 1D B0 12 CA 4D BA 40 85 12 +FC FF BA 40 A0 50 FE FF 28 83 8A 48 00 00 BA 40 +82 44 02 00 A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D +A8 49 FE FF 89 48 00 00 30 4D 12 12 C6 1D 84 12 +20 4A 88 4A AC 44 3A 51 1A 51 3C 4E 3C 80 87 12 +0A 24 1C 53 02 20 2E 4E 06 3C BE 90 A0 50 00 00 +01 20 3E 52 2E 83 21 53 30 41 32 4B AC 44 42 51 +36 51 44 51 B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 +28 00 0A 4E 3D 15 B0 12 0A 51 15 20 3E 40 2B 00 +B0 12 0A 51 06 20 3E 40 2D 00 B0 12 0A 51 92 83 +C6 1D 0E 12 1E 41 02 00 84 12 20 4A 32 4B AC 44 +66 4D 84 51 3E 51 3A 17 30 41 B0 12 4A 51 19 42 +C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +C6 1D 1A 42 C6 1D 3D 15 84 12 20 4A 32 4B AC 44 +BC 51 B4 51 3E 90 10 00 E6 2B 7C 2D BE 51 A2 41 +C6 1D E1 3F 03 20 B0 12 A2 51 43 3C 7A 90 23 00 +24 20 B0 12 52 51 3C 40 00 03 0E 93 1C 24 3C 40 +10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 +20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 +30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D A2 53 +C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 05 20 +3C 40 10 02 B0 12 52 51 F0 3F 7A 90 40 00 14 20 +3C 40 20 00 B0 12 9E 51 0C 20 3C D0 10 00 3E 40 +2B 00 B0 12 A2 51 92 92 C2 1D C6 1D 02 24 92 53 +C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 8A 51 +F2 3F 03 20 B0 12 A2 51 F5 3F 7A 90 26 00 03 20 +3C D0 82 00 D7 3F 3C D0 80 00 B0 12 8A 51 EA 3F +0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 19 42 +C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 +C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 08 52 +45 54 49 00 0D 12 84 12 0A 44 00 13 8A 4C 9C 49 +0A 44 2C 00 80 52 C4 51 CE 47 8A 52 62 52 D0 52 +3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 +85 12 C0 52 00 40 DC 52 0A 4D 4F 56 2E 42 85 12 +C0 52 40 40 00 00 06 41 44 44 85 12 C0 52 00 50 +F6 52 0A 41 44 44 2E 42 85 12 C0 52 40 50 02 53 +08 41 44 44 43 00 85 12 C0 52 00 60 10 53 0C 41 +44 44 43 2E 42 00 85 12 C0 52 40 60 48 4F 08 53 +55 42 43 00 85 12 C0 52 00 70 2E 53 0C 53 55 42 +43 2E 42 00 85 12 C0 52 40 70 3C 53 06 53 55 42 +85 12 C0 52 00 80 4C 53 0A 53 55 42 2E 42 85 12 +C0 52 40 80 58 53 06 43 4D 50 85 12 C0 52 00 90 +66 53 0A 43 4D 50 2E 42 85 12 C0 52 40 90 00 00 +08 44 41 44 44 00 85 12 C0 52 00 A0 80 53 0C 44 +41 44 44 2E 42 00 85 12 C0 52 40 A0 AE 52 06 42 +49 54 85 12 C0 52 00 B0 9E 53 0A 42 49 54 2E 42 +85 12 C0 52 40 B0 AA 53 06 42 49 43 85 12 C0 52 +00 C0 B8 53 0A 42 49 43 2E 42 85 12 C0 52 40 C0 +C4 53 06 42 49 53 85 12 C0 52 00 D0 D2 53 0A 42 +49 53 2E 42 85 12 C0 52 40 D0 00 00 06 58 4F 52 +85 12 C0 52 00 E0 EC 53 0A 58 4F 52 2E 42 85 12 +C0 52 40 E0 1E 53 06 41 4E 44 85 12 C0 52 00 F0 +06 54 0A 41 4E 44 2E 42 85 12 C0 52 40 F0 CE 47 +80 52 C4 51 26 54 0A 4C 3C F0 70 00 8A 10 3A F0 +0F 00 0C DA 4D 3F DE 53 06 52 52 43 85 12 1E 54 +00 10 38 54 0A 52 52 43 2E 42 85 12 1E 54 40 10 +72 53 08 53 57 50 42 00 85 12 1E 54 80 10 44 54 +06 52 52 41 85 12 1E 54 00 11 60 54 0A 52 52 41 +2E 42 85 12 1E 54 40 11 52 54 06 53 58 54 85 12 +1E 54 80 11 00 00 08 50 55 53 48 00 85 12 1E 54 +00 12 86 54 0C 50 55 53 48 2E 42 00 85 12 1E 54 +40 12 7A 54 08 43 41 4C 4C 00 85 12 1E 54 80 12 +1A 53 0E 4A 84 12 10 4A 1E 44 0D 6F 75 74 20 6F +66 20 62 6F 75 6E 64 73 12 45 A4 54 06 53 3E 3D +86 12 00 38 CC 54 04 53 3C 00 86 12 00 34 94 54 +06 30 3E 3D 86 12 00 30 E0 54 04 30 3C 00 86 12 +00 30 1C 4F 04 55 3C 00 86 12 00 2C F4 54 06 55 +3E 3D 86 12 00 28 EA 54 06 30 3C 3E 86 12 00 24 +08 55 04 30 3D 00 86 12 00 20 00 00 04 49 46 00 +1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D +8E 53 08 54 48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F +09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F 88 DA +00 00 30 4D FE 54 08 45 4C 53 45 00 1A 42 C8 1D +BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 +E3 3F 6C 54 0A 42 45 47 49 4E 30 40 32 44 56 55 +0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D +2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 +08 DA 89 48 00 00 A2 53 C8 1D 30 4D 12 54 0A 41 +47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 0A 57 +48 49 4C 45 0D 12 84 12 20 55 B6 48 9C 49 74 55 +0C 52 45 50 45 41 54 00 0D 12 84 12 B4 55 38 55 +9C 49 E4 55 3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D +CB 2F 98 42 C8 1D 00 00 30 4D D0 55 06 42 57 31 +85 12 E2 55 00 00 FC 55 06 42 57 32 85 12 E2 55 +00 00 08 56 06 42 57 33 85 12 E2 55 00 00 20 56 +3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D +86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F +30 4D 00 00 06 46 57 31 85 12 1E 56 00 00 44 56 +06 46 57 32 85 12 1E 56 00 00 50 56 06 46 57 33 +85 12 1E 56 00 00 BE 55 08 47 4F 54 4F 00 2F 83 +8F 4E 00 00 3E 40 00 3C 0D 12 84 12 56 4D 62 4C +9C 49 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 +3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 EC 3F +8A 52 0A 44 2C 00 20 4A 32 4B AC 44 66 4D CE 47 +80 52 62 52 B6 56 0A 4E 3E 4F 1A 83 F9 32 29 4E +59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A 38 90 +10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 +A8 3E 14 56 08 52 52 43 4D 00 85 12 A0 56 50 00 +E4 56 08 52 52 41 4D 00 85 12 A0 56 50 01 F2 56 +08 52 4C 41 4D 00 85 12 A0 56 50 02 00 57 08 52 +52 55 4D 00 85 12 A0 56 50 03 12 55 0A 50 55 53 +48 4D 85 12 A0 56 00 15 1C 57 08 50 4F 50 4D 00 +85 12 A0 56 00 17 +@FF80 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 D8 46 F2 45 F2 45 F2 45 F2 45 F2 45 +F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 F2 45 06 46 +q diff --git a/binaries/MSP_EXP430FR6989_8MHz_I2C.txt b/binaries/MSP_EXP430FR6989_8MHz_I2C.txt index 166b30f..1dbf49a 100644 --- a/binaries/MSP_EXP430FR6989_8MHz_I2C.txt +++ b/binaries/MSP_EXP430FR6989_8MHz_I2C.txt @@ -1,336 +1,324 @@ @1800 -40 1F 12 00 00 00 F8 00 F9 FF F8 57 F0 4F 34 01 -10 00 41 87 B6 45 AA 44 B8 45 8C 45 82 46 F8 57 -F0 4F 70 46 80 47 FE 46 DA 46 3C 1D 4E 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 +40 1F 12 00 00 00 F8 00 FD FF 35 01 10 00 A1 43 +D2 46 56 45 56 45 58 45 44 45 12 57 CA 4F 84 4F +84 4F C0 46 44 47 1C 47 3C 1D E0 1C 78 49 B6 44 +C4 44 94 48 20 00 0A 00 00 1C 56 45 56 45 58 45 +44 45 12 57 CA 4F 84 4F 84 4F 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 @4400 -B0 12 B8 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 CC 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 6E 46 B2 49 7E 47 B2 49 FC 46 B2 49 D8 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 BC 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D 68 43 B0 12 BA 45 0E 12 B0 12 -F8 44 0A 44 DE 1D CE 47 16 47 EE 44 34 44 8A 45 -14 44 05 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 -C4 48 96 47 34 44 7E 45 14 44 0F 4C 41 53 54 2E -34 54 48 2C 20 6C 69 6E 65 20 4A 47 8E 48 4A 47 -14 44 04 1B 5B 30 6D 00 4A 47 16 4C 2E 93 13 28 -B2 D0 C0 07 40 06 18 42 02 18 08 11 38 D0 00 04 -82 48 54 06 F2 D0 C0 00 0C 02 92 C3 40 06 A2 D2 -6A 06 92 C3 30 01 30 41 48 43 A2 B3 6C 06 FD 27 -C2 48 4E 06 A2 B2 6C 06 FD 27 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 B6 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 CE 45 04 57 41 52 4D 00 B0 12 -8C 45 78 40 03 00 B0 12 BA 45 84 12 14 44 07 0D -0A 1B 5B 37 6D 40 4A 47 0A 44 02 18 CE 47 C4 48 -0A 44 23 00 FA 46 C4 48 14 44 19 46 61 73 74 46 -6F 72 74 68 20 C2 A9 4A 2E 4D 2E 54 68 6F 6F 72 -65 6E 73 20 4A 47 0A 44 40 FF 28 44 C2 47 8E 48 -14 44 0A 62 79 74 65 73 20 66 72 65 65 00 3A 44 -7E 45 00 00 06 41 43 43 45 50 54 00 30 40 70 46 +92 12 40 18 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +12 D3 F5 3F 35 40 B6 44 8F 4A 02 00 8F 49 00 00 +0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +3C 1D 00 00 AF 4F FE FF 2F 83 08 3D 0E 93 3E 4F +8A 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +92 12 3C 18 3D 41 39 40 22 18 B2 49 BE 46 B2 49 +42 47 B2 49 1A 47 B2 49 A0 44 31 49 34 49 35 49 +36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +82 43 BC 1D 30 40 3E 50 8F 93 02 00 02 20 2F 52 +BF 3F 28 43 B0 12 46 45 B0 12 D0 44 9E 48 AC 44 +42 45 5C 47 1E 44 05 1B 5B 37 6D 40 88 47 0A 44 +02 18 C0 48 EC 49 88 47 1E 44 04 1B 5B 30 6D 00 +88 47 D4 4C 48 43 A2 B3 6C 06 FD 27 C2 48 4E 06 +A2 B2 6C 06 FD 27 30 41 B2 D0 C0 07 40 06 18 42 +02 18 08 11 38 D0 00 04 82 48 54 06 F2 D0 C0 00 +0C 02 92 C3 40 06 A2 D2 6A 06 92 C3 30 01 30 41 +92 12 3E 18 84 12 5C 47 1E 44 07 0D 0A 1B 5B 37 +6D 40 88 47 0A 44 02 18 C0 48 EC 49 0A 44 23 00 +40 47 EC 49 1E 44 19 46 61 73 74 46 6F 72 74 68 +20 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 2C 20 +88 47 0A 44 40 FF 32 44 B4 48 B8 49 1E 44 0A 62 +79 74 65 73 20 66 72 65 65 00 B2 44 36 45 00 00 +06 53 59 53 0E 93 07 38 02 24 1E B3 04 28 30 12 +80 45 01 12 6D 3F 82 4E 08 18 92 12 3A 18 E2 B3 +00 02 02 20 B2 43 08 18 B2 40 04 A5 20 01 B2 D0 +03 00 04 01 B2 D0 10 00 00 01 B2 40 80 5A 5C 01 +31 40 E0 1C 3F 40 80 1C B2 D3 06 02 B2 40 FE FF +02 02 B2 43 26 02 B2 43 22 02 B2 43 46 02 B2 43 +42 02 B2 43 66 02 B2 43 62 02 B2 43 86 02 B2 40 +7F FF 82 02 F2 43 26 03 F2 43 22 03 F2 40 A5 00 +61 01 82 43 66 01 B2 40 33 00 64 01 D2 43 61 01 +39 40 40 00 18 42 00 18 18 83 FE 23 19 83 FA 23 +B2 42 B0 01 F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 +39 40 00 08 29 83 89 43 00 1C FC 23 1E 42 08 18 +82 43 08 18 3E F3 02 20 1E 42 9E 01 B0 12 D0 44 +80 45 00 00 0C 41 43 43 45 50 54 00 30 40 C0 46 0A 4E 2E 4F 0A 5E 3B 40 0A 00 3C 40 20 00 3D 15 -BF 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 B8 22 +97 3E 21 52 A2 C2 6C 06 B2 B0 10 00 40 06 90 22 3A 17 92 B3 6C 06 FD 27 58 42 4C 06 48 9B 0E 24 48 9C 06 2C 78 92 F5 23 2E 9F F3 27 1E 83 F1 3F -0E 9A EF 27 CE 48 00 00 1E 53 EB 3F 3E 8F B0 12 -C4 45 82 93 DE 1D 02 24 92 53 DE 1D 08 4C 19 3C -00 00 03 4B 45 59 30 40 DA 46 2F 83 8F 4E 00 00 -58 43 B0 12 BA 45 92 B3 6C 06 FD 27 1E 42 4C 06 -30 4D 00 00 04 45 4D 49 54 00 30 40 FE 46 08 4E -3E 4F A2 B3 6C 06 FD 27 C2 48 4E 06 30 4D F4 46 -04 45 43 48 4F 00 B2 40 C2 48 08 47 82 43 DE 1D -38 40 05 00 B0 12 BA 45 30 4D 00 00 06 4E 4F 45 -43 48 4F 00 B2 40 30 4D 08 47 92 43 DE 1D 28 42 -F1 3F 00 00 04 54 59 50 45 00 0E 93 11 24 0D 12 -3D 40 66 47 28 4F 2F 83 8F 4E 00 00 7E 48 8F 48 -02 00 10 42 FC 46 68 47 2D 83 1E 83 F3 23 3D 41 -2F 53 3E 4F 30 4D DC 45 02 43 52 00 30 40 80 47 -0D 12 84 12 14 44 02 0D 0A 00 4A 47 4E 48 2F 83 -8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E FE FF -AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 0E 4A -30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 2F 83 -30 4D 3E 8F 3E E3 1E 53 30 4D 64 46 01 40 2E 4E -30 4D CC 47 01 21 BE 4F 00 00 3E 4F 30 4D 1E 83 -0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F 03 24 -3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 B2 40 -B2 1D B2 1D 30 4D 78 47 01 23 1B 42 DC 1D 2C 4F -2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 02 28 -7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 B2 1D -C8 4A 00 00 30 4D 08 48 02 23 53 00 0D 12 84 12 -0A 48 44 48 2D 83 09 93 E2 23 0E 93 E0 23 3D 41 -30 4D 38 48 02 23 3E 00 9F 42 B2 1D 00 00 3E 40 -B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 4A 4E -3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 3E 4F -7A 40 2D 00 D1 33 30 4D 44 47 02 55 2E 00 08 43 -2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 06 34 -BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 FE 47 -3C 48 EE 44 7C 48 58 48 4A 47 02 4C FA 46 4E 48 -2C 47 01 2E 0E 93 E3 37 38 43 E2 3F 76 48 82 53 -22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 48 4B -0A 44 22 00 1A 49 E8 48 B2 40 20 00 B4 1D 6E 4E -1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D C2 48 -82 2E 22 00 0D 12 84 12 D2 48 0A 44 4A 47 48 4B -4E 48 F8 45 04 57 4F 52 44 00 3C 40 C0 1D 39 4C -3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A FC 27 -1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 00 00 -01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A 4E 9C -08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F 4C 85 -F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D 1E 42 -C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 49 4E -44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 CA 1D -3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 0E 58 -2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 48 C5 -48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 -FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 01 30 -2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 30 4D -00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F 29 4F -2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 0A 00 -05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B 22 C3 -0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 19 42 -E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E3 23 +0E 9A EF 2F CE 48 00 00 1E 53 EB 3F 3E 8F 08 4C +1B 3C 00 00 06 4B 45 59 30 40 1C 47 58 43 B0 12 +46 45 2F 83 8F 4E 00 00 92 B3 6C 06 FD 27 1E 42 +4C 06 B0 12 44 45 30 4D 00 00 08 45 4D 49 54 00 +30 40 44 47 08 4E 3E 4F A2 B3 6C 06 FD 27 C2 48 +4E 06 30 4D 3A 47 08 45 43 48 4F 00 B2 40 C2 48 +4E 47 38 40 05 00 B0 12 46 45 30 4D 00 00 0C 4E +4F 45 43 48 4F 00 B2 40 30 4D 4E 47 28 42 F3 3F +00 00 08 54 59 50 45 00 0D 12 3D 40 98 47 29 4F +8F 4E 00 00 7E 49 D4 3F 9A 47 2D 83 2F 83 5E 83 +F7 23 3D 41 2F 53 3E 4F 30 4D 86 12 20 00 0C 4E +38 4F 3C 9F 39 4F 3E 4F 7C 22 F9 98 00 00 79 22 +19 53 1C 83 FA 23 2D 53 30 4D 2F 53 3E 4F 1E 83 +70 22 9B 24 14 47 0D 5B 45 4C 53 45 5D 00 0D 12 +84 12 0A 44 00 00 B8 48 AA 47 FC 49 B6 4C B0 44 +26 48 14 44 06 5B 54 48 45 4E 5D 00 AE 47 04 48 +CA 47 E8 47 14 44 06 5B 45 4C 53 45 5D 00 AE 47 +16 48 CA 47 E6 47 1E 44 04 5B 49 46 5D 00 AE 47 +E8 47 B2 44 E6 47 1E 44 05 0D 6B 6F 20 0A 88 47 +9A 44 84 44 B2 44 E8 47 D6 47 0D 5B 54 48 45 4E +5D 00 30 4D 3A 48 09 5B 49 46 5D 00 0E 93 3E 4F +C6 27 30 4D 46 48 13 5B 44 45 46 49 4E 45 44 5D +0D 12 84 12 AA 47 FC 49 64 4A 08 4C 78 49 56 48 +17 5B 55 4E 44 45 46 49 4E 45 44 5D 0D 12 84 12 +AA 47 FC 49 64 4A 88 48 3D 41 2F 53 1E 83 0E 7E +30 4D 3F 12 2F 83 8F 4E 00 00 3E 41 30 4D 8F 4E +FE FF 2F 83 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F +0E 11 F7 3F 3E 8F 3E E3 1E 53 30 4D 00 00 02 40 +2E 4E 30 4D B4 46 02 21 BE 4F 00 00 3E 4F 30 4D +0E 5E 0E 7E 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D +E0 45 05 53 22 00 82 43 C0 1D 0D 12 84 12 0A 44 +1E 44 66 4C 0A 44 22 00 FC 49 FC 48 B2 40 20 00 +C0 1D 1A 53 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D +6E 47 05 2E 22 00 0D 12 84 12 E6 48 0A 44 88 47 +66 4C 78 49 00 00 04 3C 23 00 B2 40 B2 1D B2 1D +30 4D E2 48 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 +46 44 BF 4F 00 00 7A 90 0A 00 02 28 7A 50 07 00 +7A 50 30 00 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 +30 4D 34 49 04 23 53 00 0D 12 84 12 36 49 70 49 +2D 83 09 DE 09 93 E1 23 3D 41 30 4D 64 49 04 23 +3E 00 9F 42 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D +00 00 08 48 4F 4C 44 00 4A 4E 3E 4F DB 3F 7E 49 +08 53 49 47 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 +30 4D 56 47 04 55 2E 00 0C 43 2F 83 8F 4E 00 00 +0E 4C 1D 15 3E F3 06 34 BF E3 00 00 3E E3 9F 53 +00 00 0E 63 84 12 2A 49 AA 47 98 49 68 49 94 48 +A6 49 82 49 88 47 78 49 12 49 02 2E 0E 93 E4 37 +3C 43 E3 3F 00 00 08 57 4F 52 44 00 3C 40 C2 1D +39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1D 24 7E 98 +FC 27 18 83 1B 42 C0 1D F8 90 27 00 00 00 04 20 +E8 98 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 +7C 48 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 +7B 00 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D +1E 42 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 +49 4E 44 00 2F 83 0C 4E 3B 40 CE 1D 3E 4B 0E 93 +1E 24 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 +1E 4E FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C +F7 23 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 +19 B3 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C +00 00 30 4D EA 49 0E 3E 4E 55 4D 42 45 52 1B 42 +BE 1D 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C +7A 80 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 +0A 9B 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 +E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 -00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 9C 4A 09 43 -08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 27 00 -00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 03 00 -48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 02 00 -0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 3B 40 -10 00 7A 53 36 20 1C 53 1E 83 EB 3F 9E 4A 31 24 -2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 32 D0 -00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 0A 4E -09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 79 80 -30 00 79 90 0A 00 05 28 79 80 07 00 79 90 0A 00 -0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 -66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F 04 00 -4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 00 02 -3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 04 00 -BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 BF E3 -00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 01 20 -2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E 00 00 -A2 53 C6 1D 3E 4F 30 4D 46 4B 87 4C 49 54 45 52 -41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D A2 52 -C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 -00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D -54 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E 00 00 -5E 4E FF FF 30 4D 68 48 09 49 4E 54 45 52 50 52 -45 54 0D 12 84 12 AC 44 02 4C 1A 49 BE 4B 9C 26 -3D 40 C6 4B DE 3E C8 4B 0A 4E 3E 4F 3D 40 E2 4B -36 27 3D 40 B8 4B 1A E2 BE 1D B6 27 0E 12 3E 4F -30 41 E4 4B 3E 4F 3D 40 B8 4B BB 23 DE 53 00 00 -68 4E 08 5E F8 40 3F 00 00 00 3D 40 84 4D CC 3F -EC 4B 86 12 20 00 D4 47 05 41 4C 4C 4F 54 82 5E -C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 E0 1C -B2 40 00 1C 00 1C 82 43 BE 1D 84 12 7C 47 BC 44 -B2 4B B2 47 E4 47 14 44 0C 73 74 61 63 6B 20 65 -6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 EC 47 -14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 2A 45 -3A 44 2C 4C 08 4C 86 41 42 4F 52 54 22 00 0D 12 -84 12 D2 48 0A 44 2A 45 48 4B 4E 48 7C 49 01 27 -0D 12 84 12 02 4C 1A 49 82 49 34 44 00 4C 4E 48 -00 00 83 5B 27 5D 0D 12 84 12 80 4C 0A 44 0A 44 -48 4B 48 4B 4E 48 92 4C 81 5B 82 43 BE 1D 30 4D -FA 47 01 5D B2 43 BE 1D 30 4D B2 4C 81 5C 92 42 -C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 4F 4E -45 00 0D 12 84 12 02 4C 1A 49 82 49 96 47 34 44 -00 4C E4 47 34 44 F4 4C 0A 44 0A 44 48 4B 48 4B -0A 44 48 4B 48 4B 4E 48 A8 4C 01 3A 30 12 44 4D -92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 02 4C 1A 49 -12 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 19 42 -DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 B6 1D -82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 82 4A -C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 FE FF -B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 B6 1D -19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D 0D 12 -84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 6D 61 -74 63 68 21 36 45 FA 4C 81 3B 82 93 BE 1D 97 27 -0D 12 84 12 0A 44 4E 48 48 4B 56 4D AA 4C 4E 48 -A8 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 B6 1D -F8 D0 80 00 00 00 30 4D 92 4B 06 43 52 45 41 54 -45 00 B0 12 00 4D BA 40 86 12 FC FF 8A 4A FE FF -C9 3F BA 4D 04 43 4F 44 45 00 B0 12 00 4D A2 82 -C6 1D 0D 12 84 12 F2 4F CC 4F 4E 48 A2 4D 07 48 -44 4E 43 4F 44 45 B2 40 D0 4F DA 1D EE 3F 00 00 -07 45 4E 44 43 4F 44 45 0D 12 84 12 56 4D 0C 50 -2A 50 4E 48 00 00 05 43 4F 4C 4F 4E 1A 42 C6 1D -BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 C6 1D -B2 43 BE 1D 0D 12 84 12 0C 50 2A 50 4E 48 00 00 -05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D EB 3F -EE 4D 85 48 49 32 4C 4F 0D 12 84 12 28 44 9A 4F -48 4B AA 4C E2 4D 4E 48 88 4D 86 5B 54 48 45 4E -5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B 0E 5C -10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 FF FF -F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 F9 23 -2F 53 2D 53 F7 3F 6A 4E 86 5B 45 4C 53 45 5D 00 -0D 12 84 12 0A 44 00 00 C6 47 02 4C 1A 49 98 4B -8E 47 34 44 02 4F 9C 47 14 44 06 5B 54 48 45 4E -5D 00 74 4E DC 4E 98 4E BA 4E 4E 48 9C 47 14 44 -06 5B 45 4C 53 45 5D 00 74 4E F2 4E 98 4E B8 4E -4E 48 14 44 04 5B 49 46 5D 00 74 4E BA 4E 3A 44 -B8 4E 70 47 14 44 05 0D 0A 6B 6F 20 4A 47 BC 44 -AC 44 3A 44 BA 4E A8 4E 84 5B 49 46 5D 00 0E 93 -3E 4F C6 27 30 4D 2F 53 30 4D 18 4F 89 5B 44 45 -46 49 4E 45 44 5D 0D 12 84 12 02 4C 1A 49 82 49 -26 4F 4E 48 2C 4F 8B 5B 55 4E 44 45 46 49 4E 45 -44 5D 0D 12 84 12 36 4F DE 47 4E 48 5E 4F B2 4E -0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 5A 4B 06 4D -41 52 4B 45 52 00 B0 12 00 4D BA 40 85 12 FC FF -BA 40 5C 4F FE FF 28 83 8A 48 00 00 BA 40 AA 44 -04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D 0A 44 -CA 1D D6 47 4E 48 85 12 9E 4F 66 4C D4 4D 10 47 -7E 4C 52 4E D2 46 6E 4F 00 49 96 50 AA 50 8A 48 -14 49 00 00 46 4F BC 4C E2 49 00 00 85 12 9E 4F -6E 56 D4 56 16 56 24 57 DC 55 00 00 A8 53 00 00 -EC 57 D0 57 40 56 7E 56 B8 54 00 00 00 00 40 57 -CA 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 19 83 -18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 0E 00 -38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 1A 83 -FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D DA 1D -30 4D A6 4F 24 50 2A 50 3A 50 1A 42 20 18 82 4A -C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A 08 49 -29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 1D 83 -F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D C8 4C -09 50 57 52 5F 53 54 41 54 45 85 12 32 50 F8 57 -CE 48 09 52 53 54 5F 53 54 41 54 45 92 42 0A 18 -7E 50 F3 3F 70 50 08 50 57 52 5F 48 45 52 45 00 -92 42 C6 1D 7E 50 30 4D 82 50 08 52 53 54 5F 48 -45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 0E 00 -DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 29 83 -B9 43 80 FF FC 23 B9 40 08 51 FE FF 29 83 B9 40 -E2 45 FE FF 39 90 AE FF F9 23 39 40 14 18 B2 49 -E4 45 B2 49 FA 44 B2 49 02 44 B2 49 00 46 B2 49 -EC FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 B2 D0 -10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 -80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 B2 D3 -06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 22 02 -B2 43 46 02 B2 43 42 02 B2 43 66 02 B2 43 62 02 -B2 43 86 02 B2 40 7F FF 82 02 F2 43 26 03 F2 43 -22 03 F2 40 A5 00 61 01 82 43 66 01 B2 40 33 00 -64 01 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 -FE 23 19 83 FA 23 B2 42 B0 01 F2 D0 10 00 2A 03 -F2 C0 40 00 A2 04 1E 42 08 18 82 43 08 18 1E D2 -9E 01 B0 12 F8 44 FE 45 38 40 C0 1D 0A 4E 39 48 -2E 48 09 5E 1E 52 C4 1D 09 9E 03 24 7A 9E FC 27 -1E 83 0A 4E 2A 88 82 4A C4 1D 30 4D 1C 15 0E 12 -12 12 C4 1D 84 12 1A 49 82 49 DE 47 34 44 E8 51 -3E 4A 34 44 02 52 FC 51 EA 51 3C 4E 3C 80 87 12 -05 24 1C 53 02 20 2E 4E 01 3C 2E 83 21 52 1B 17 -30 41 04 52 B2 41 C4 1D 3E 41 84 12 0A 44 2B 00 -1A 49 82 49 DE 47 34 44 20 52 3E 4A 34 44 00 4C -A8 47 1A 49 3E 4A 34 44 00 4C 2C 52 3E 5F E7 3F -3E 40 28 00 B0 12 CC 51 19 42 C6 1D A2 53 C6 1D -89 4E 00 00 3E 40 29 00 92 92 C0 1D C4 1D 02 20 -30 40 6E 4D 1C 15 12 12 C4 1D 92 53 C4 1D 84 12 -1A 49 3E 4A 34 44 74 52 6A 52 21 53 3E 90 10 00 -C6 2B 7F 2D 76 52 B2 41 C4 1D C1 3F 0D 12 84 12 -02 4C A8 51 86 52 0C 43 1B 42 C6 1D A2 53 C6 1D -6A 4E 3E 4F 7A 90 23 00 27 20 92 53 C4 1D B0 12 -CC 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 +00 02 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D +0C 4E 0E 43 1E 15 3D 40 6E 4B 7E 4C 6A 4C 7A 80 +2D 00 16 24 CA 2F 2B 43 7A 52 14 24 3B 52 6A 53 +11 24 3B 40 10 00 5A 93 0D 24 6A 92 41 20 3E 90 +03 00 3E 20 FC 9C 01 00 6C 4C 8F 4C 04 00 38 3C +B1 43 02 00 1E 83 FC 9C 00 00 E0 23 AE 27 70 4B +2F 24 2D 83 6A 4C 7A 90 5F 00 BF 27 32 B0 00 02 +27 20 32 D0 00 02 7A 80 2E 00 B7 27 6A 53 20 20 +0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 +79 80 3A 00 03 28 79 80 07 00 0C 28 79 50 0A 00 +09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 B0 12 3E 44 +2A 17 E8 3F 9F 4F 04 00 02 00 AF 4F 04 00 4A 93 +1D 17 06 24 32 C0 00 02 3F 50 06 00 0E F3 30 4D +2F 53 9F 4F 02 00 04 00 BF 4F 00 00 3E E3 09 20 +3E E3 BF E3 02 00 BF E3 00 00 9F 53 02 00 8F 63 +00 00 32 B0 00 02 01 20 2F 53 30 4D 26 49 03 5C +92 42 C2 1D C6 1D 30 4D 0D 12 84 12 84 44 AA 47 +FC 49 B0 44 40 4D 64 4A 2A 4C 0A 4E 3E 4F 3D 40 +44 4C 6D 27 3D 40 1E 4C 1A E2 BC 1D 14 24 0E 12 +3E 4F 30 41 46 4C 3E 4F 3D 40 1E 4C 19 20 DE 53 +00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 1C 4E +2A 3C 0E 4C 02 2C A2 53 C8 1D 1A 42 C8 1D 8A 4E +FE FF 3E 4F 30 4D 64 4C 0F 4C 49 54 45 52 41 4C +82 93 BC 1D 0D 24 09 4E 1A 42 C8 1D A2 52 C8 1D +BA 40 0A 44 00 00 8A 49 02 00 3E 4F 32 B0 00 02 +32 C0 00 02 03 24 8A 4E 02 00 EE 3F 30 4D A0 49 +0A 43 4F 55 4E 54 2F 83 7A 4E 8F 4E 00 00 0E 4A +3E F3 30 4D C6 48 0A 41 4C 4C 4F 54 82 5E C8 1D +3E 4F 30 4D 3F 40 80 1C 0E 43 84 12 1E 44 02 0D +0A 00 88 47 94 44 18 4C A6 48 D0 48 1E 44 0B 73 +74 61 63 6B 20 65 6D 70 74 79 08 45 32 44 0A 44 +40 FF D8 48 1E 44 09 46 52 41 4D 20 66 75 6C 6C +08 45 B2 44 DC 4C C6 4C 0D 41 42 4F 52 54 22 00 +0D 12 84 12 E6 48 0A 44 08 45 66 4C 78 49 F6 49 +02 27 0D 12 84 12 AA 47 FC 49 64 4A B0 44 42 4D +0A 49 4E 4C 70 48 07 5B 27 5D 0D 12 84 12 32 4D +0A 44 0A 44 66 4C 66 4C 78 49 46 4D 03 5B 82 43 +BC 1D 30 4D 00 00 02 5D B2 43 BC 1D 30 4D BE 48 +11 50 4F 53 54 50 4F 4E 45 00 0D 12 84 12 AA 47 +FC 49 64 4A B0 44 42 4D D0 48 AC 44 9A 4D 0A 44 +0A 44 66 4C 66 4C 0A 44 66 4C 66 4C 78 49 00 00 +02 3A 30 12 F0 4D 92 B3 C8 1D A2 63 C8 1D 0D 12 +84 12 AA 47 FC 49 B8 4D 3D 41 5A D3 5A 53 0A 5E +19 42 CC 1D 08 4E 5E 4E 01 00 3E F0 0F 00 0E 5E +09 5E 3E 4F E8 58 00 00 82 48 B4 1D 82 49 B6 1D +82 4A B8 1D 82 4F BA 1D 2A 52 82 4A C8 1D 30 41 +BA 40 0D 12 FC FF BA 40 84 12 FE FF B2 43 BC 1D +30 4D 82 9F BA 1D 66 25 84 12 1E 44 0F 73 74 61 +63 6B 20 6D 69 73 6D 61 74 63 68 21 12 45 5C 4D +03 3B 82 93 BC 1D F4 26 0D 12 84 12 0A 44 78 49 +66 4C 02 4E 5E 4D 78 49 00 00 12 49 4D 4D 45 44 +49 41 54 45 18 42 B4 1D D8 D3 00 00 30 4D B0 4C +0C 43 52 45 41 54 45 00 B0 12 A6 4D BA 40 86 12 +FC FF 8A 4A FE FF 3A 3D 82 47 0A 44 4F 45 53 3E +1A 42 B8 1D BA 40 85 12 00 00 8A 4D 02 00 3D 41 +30 4D A0 4D 0E 3A 4E 4F 4E 41 4D 45 30 12 F0 4D +2F 83 8F 4E 00 00 1A 42 C8 1D 1A B3 0A 63 0E 4A +39 40 12 02 08 49 98 3F 3A 4E 05 49 53 00 0D 12 +82 93 BC 1D 08 20 84 12 32 4D BC 4E 3D 41 BE 4F +02 00 3E 4F 30 4D 84 12 4A 4D 0A 44 BE 4E 66 4C +78 49 50 4E 08 43 4F 44 45 00 B0 12 A6 4D A2 82 +C8 1D 61 3C 92 49 0E 48 44 4E 43 4F 44 45 B2 40 +AA 4F CC 1D F2 3F 00 00 0E 45 4E 44 43 4F 44 45 +0D 12 84 12 02 4E 08 4F 3D 41 92 42 D0 1D CC 1D +5D 3C D4 4E 0E 43 4F 44 45 4E 4E 4D 30 12 DE 4E +B7 3F 00 00 0A 43 4F 4C 4F 4E 1A 42 C8 1D BA 40 +0D 12 00 00 BA 40 84 12 02 00 A2 52 C8 1D B2 43 +BC 1D E3 3F 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D +1A 42 C8 1D EF 3F E6 4E 0B 48 49 32 4C 4F A2 53 +C8 1D 1A 42 C8 1D 8A 4A FE FF 82 43 BC 1D B9 3F +72 4F B2 40 84 4F D0 1D 82 4E CE 1D 30 40 0A 49 +85 12 70 4F 70 4D 18 4D 02 50 14 4F 6A 4E B4 49 +5E 4A 30 4D 58 4F AA 4E 84 4E 20 4E 78 4C 8C 50 +B6 4A 00 00 00 00 85 12 70 4F 06 57 8A 55 EA 56 +B2 54 0E 55 5C 55 38 56 44 56 D4 53 F8 54 00 00 +00 00 46 4F C4 52 00 00 60 56 A4 4F B2 40 84 4F +CE 1D 82 43 D0 1D 30 4D 3B 40 0A 00 BA 49 00 00 +2A 53 2B 83 FB 23 30 41 00 00 0E 52 53 54 5F 53 +45 54 39 40 C8 1D 3A 40 42 18 B0 12 D8 4F 30 4D +EA 4F 0E 52 53 54 5F 52 45 54 39 40 42 18 2C 49 +3A 40 C8 1D B0 12 D8 4F 1A 42 CA 1D 3B 40 10 00 +09 4A 08 49 29 83 18 48 FE FF 0C 98 FC 2B 89 48 +00 00 1B 83 F6 23 2A 4A 0A 93 F0 23 30 4D 0E 93 +E4 37 39 40 10 00 29 83 B9 43 80 FF FC 23 B9 40 +0E 46 FE FF 29 83 B9 40 FA 45 FE FF 39 90 AE FF +F9 23 39 40 10 18 B2 49 EC FF 3B 40 10 00 3A 40 +3A 18 B0 12 DC 4F 82 43 4A 18 C7 3F 7E 50 B2 4E +42 18 BE 12 3E 4F 3D 41 C0 3F 66 4D 0C 4D 41 52 +4B 45 52 00 12 12 C6 1D 0D 12 84 12 AA 47 FC 49 +64 4A AC 44 AA 50 9E 48 3E 4C AC 50 3E 4F 3D 41 +B2 41 C6 1D B0 12 A6 4D BA 40 85 12 FC FF BA 40 +7C 50 FE FF 28 83 8A 48 00 00 BA 40 82 44 02 00 +A2 52 C8 1D 18 42 B4 1D 19 42 B6 1D A8 49 FE FF +89 48 00 00 30 4D 12 12 C6 1D 84 12 FC 49 64 4A +AC 44 16 51 F6 50 3C 4E 3C 80 87 12 0A 24 1C 53 +02 20 2E 4E 06 3C BE 90 7C 50 00 00 01 20 3E 52 +2E 83 21 53 30 41 0E 4B AC 44 1E 51 12 51 20 51 +B2 41 C6 1D 30 41 92 83 C6 1D 3E 40 28 00 0A 4E +3D 15 B0 12 E6 50 15 20 3E 40 2B 00 B0 12 E6 50 +06 20 3E 40 2D 00 B0 12 E6 50 92 83 C6 1D 0E 12 +1E 41 02 00 84 12 FC 49 0E 4B AC 44 42 4D 60 51 +3E 51 3A 17 30 41 B0 12 26 51 19 42 C8 1D 89 4E +00 00 A2 53 C8 1D 3E 40 29 00 92 53 C6 1D 1A 42 +C6 1D 3D 15 84 12 FC 49 0E 4B AC 44 98 51 90 51 +3E 90 10 00 E6 2B 7C 2D 9A 51 A2 41 C6 1D E1 3F +03 20 B0 12 7E 51 43 3C 7A 90 23 00 24 20 B0 12 +2E 51 3C 40 00 03 0E 93 1C 24 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 3C 40 30 03 3E 93 -08 24 3C 40 30 00 19 42 C6 1D A2 53 C6 1D 89 4E -00 00 3E 4F 3D 41 30 4D 7A 90 26 00 07 20 3C 40 -10 02 92 53 C4 1D B0 12 CC 51 ED 3F 7A 90 40 00 -16 20 3C 40 20 00 92 53 C4 1D B0 12 54 52 0C 20 -3C 50 10 00 3E 40 2B 00 B0 12 54 52 92 92 C0 1D -C4 1D 02 24 92 53 C4 1D 8E 10 0C 5E DA 3F B0 12 -54 52 FA 23 3C 50 10 00 B0 12 30 52 EF 3F 0C 43 -1B 42 C6 1D A2 53 C6 1D 0D 12 84 12 02 4C A8 51 -52 53 FE 90 26 00 00 00 3E 40 20 00 03 20 3C 50 -82 00 C7 3F B0 12 54 52 E0 23 3C 50 80 00 B0 12 -30 52 DB 3F 00 00 04 52 45 54 49 00 0D 12 84 12 -0A 44 00 13 48 4B 4E 48 0A 44 2C 00 7C 52 48 53 -92 53 09 4B 2E 4E 0E DC A2 3F 40 4E 03 4D 4F 56 -85 12 88 53 00 40 9C 53 05 4D 4F 56 2E 42 85 12 -88 53 40 40 00 00 03 41 44 44 85 12 88 53 00 50 -B6 53 05 41 44 44 2E 42 85 12 88 53 40 50 C2 53 -04 41 44 44 43 00 85 12 88 53 00 60 D0 53 06 41 -44 44 43 2E 42 00 85 12 88 53 40 60 76 53 04 53 -55 42 43 00 85 12 88 53 00 70 EE 53 06 53 55 42 -43 2E 42 00 85 12 88 53 40 70 FC 53 03 53 55 42 -85 12 88 53 00 80 0C 54 05 53 55 42 2E 42 85 12 -88 53 40 80 16 4E 03 43 4D 50 85 12 88 53 00 90 -26 54 05 43 4D 50 2E 42 85 12 88 53 40 90 00 4E -04 44 41 44 44 00 85 12 88 53 00 A0 40 54 06 44 -41 44 44 2E 42 00 85 12 88 53 40 A0 32 54 03 42 -49 54 85 12 88 53 00 B0 5E 54 05 42 49 54 2E 42 -85 12 88 53 40 B0 6A 54 03 42 49 43 85 12 88 53 -00 C0 78 54 05 42 49 43 2E 42 85 12 88 53 40 C0 -84 54 03 42 49 53 85 12 88 53 00 D0 92 54 05 42 -49 53 2E 42 85 12 88 53 40 D0 00 00 03 58 4F 52 -85 12 88 53 00 E0 AC 54 05 58 4F 52 2E 42 85 12 -88 53 40 E0 DE 53 03 41 4E 44 85 12 88 53 00 F0 -C6 54 05 41 4E 44 2E 42 85 12 88 53 40 F0 02 4C -7C 52 E4 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 -0C DA 4F 3F 18 54 03 52 52 43 85 12 DE 54 00 10 -F6 54 05 52 52 43 2E 42 85 12 DE 54 40 10 02 55 -04 53 57 50 42 00 85 12 DE 54 80 10 10 55 03 52 -52 41 85 12 DE 54 00 11 1E 55 05 52 52 41 2E 42 -85 12 DE 54 40 11 2A 55 03 53 58 54 85 12 DE 54 -80 11 00 00 04 50 55 53 48 00 85 12 DE 54 00 12 -44 55 06 50 55 53 48 2E 42 00 85 12 DE 54 40 12 -9E 54 04 43 41 4C 4C 00 85 12 DE 54 80 12 1A 53 -0E 4A 0D 12 84 12 C4 48 14 44 0D 6F 75 74 20 6F -66 20 62 6F 75 6E 64 73 36 45 38 55 03 53 3E 3D -86 12 00 38 8C 55 02 53 3C 00 86 12 00 34 52 55 -03 30 3E 3D 86 12 00 30 A0 55 02 30 3C 00 86 12 -00 30 00 00 02 55 3C 00 86 12 00 2C B4 55 03 55 -3E 3D 86 12 00 28 AA 55 03 30 3C 3E 86 12 00 24 -C8 55 02 30 3D 00 86 12 00 20 00 00 02 49 46 00 -1A 42 C6 1D 8A 4E 00 00 A2 53 C6 1D 0E 4A 30 4D -BE 55 04 54 48 45 4E 00 1A 42 C6 1D 08 4E 3E 4F -09 48 29 53 0A 89 0A 11 3A 90 00 02 B1 2F 88 DA -00 00 30 4D 4E 54 04 45 4C 53 45 00 1A 42 C6 1D -BA 40 00 3C 00 00 A2 53 C6 1D 2F 83 8F 4A 00 00 -E3 3F 62 55 05 42 45 47 49 4E 30 40 28 44 F2 55 -05 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 C6 1D -2A 83 0A 89 0A 11 3A 90 00 FE 8A 3B 3A F0 FF 03 -08 DA 89 48 00 00 A2 53 C6 1D 30 4D D2 54 05 41 -47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 05 57 -48 49 4C 45 0D 12 84 12 E0 55 A8 47 4E 48 96 55 -06 52 45 50 45 41 54 00 0D 12 84 12 74 56 F8 55 -4E 48 A4 56 3D 41 08 4E 3E 4F 2A 48 B2 92 C4 1D -CB 2F 98 42 C6 1D 00 00 30 4D 34 56 03 42 57 31 -85 12 A2 56 00 00 BC 56 03 42 57 32 85 12 A2 56 -00 00 C8 56 03 42 57 33 85 12 A2 56 00 00 E0 56 -3D 41 1A 42 C6 1D 28 4E B2 92 C4 1D 88 2B BA 4F -00 00 A2 53 C6 1D 8E 4A 00 00 3E 4F 30 4D 00 00 -03 46 57 31 85 12 DE 56 00 00 00 57 03 46 57 32 -85 12 DE 56 00 00 0C 57 03 46 57 33 85 12 DE 56 -00 00 18 57 04 47 4F 54 4F 00 2F 83 8F 4E 00 00 -3E 40 00 3C 0D 12 84 12 80 4C DC 4B 4E 48 00 00 -05 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 -3E B0 00 10 EF 27 3E E0 00 08 EC 3F 02 4C A8 51 -62 57 92 53 C4 1D 3E 40 2C 00 84 12 1A 49 3E 4A -34 44 00 4C 3E 53 78 57 0A 4E 3E 4F 1A 83 F7 32 -29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A -38 90 10 00 EC 2E 5A 0E AB 3E 2A 92 E8 2E 8A 10 -5A 06 A6 3E 90 56 04 52 52 43 4D 00 85 12 5C 57 -50 00 A6 57 04 52 52 41 4D 00 85 12 5C 57 50 01 -B4 57 04 52 4C 41 4D 00 85 12 5C 57 50 02 C2 57 -04 52 52 55 4D 00 85 12 5C 57 50 03 D2 55 05 50 -55 53 48 4D 85 12 5C 57 00 15 DE 57 04 50 4F 50 -4D 00 85 12 5C 57 00 17 +08 24 3C 40 30 00 19 42 C8 1D A2 53 C8 1D 89 4E +00 00 3E 4F 30 4D 7A 90 26 00 05 20 3C 40 10 02 +B0 12 2E 51 F0 3F 7A 90 40 00 14 20 3C 40 20 00 +B0 12 7A 51 0C 20 3C D0 10 00 3E 40 2B 00 B0 12 +7E 51 92 92 C2 1D C6 1D 02 24 92 53 C6 1D 8E 10 +0C 5E DF 3F 3C D0 10 00 B0 12 66 51 F2 3F 03 20 +B0 12 7E 51 F5 3F 7A 90 26 00 03 20 3C D0 82 00 +D7 3F 3C D0 80 00 B0 12 66 51 EA 3F 0C 43 1B 42 +C8 1D A2 53 C8 1D 3A 40 20 00 19 42 C6 1D 19 52 +C4 1D 7A 99 FE 27 5A 49 FF FF 19 82 C4 1D 82 49 +C6 1D 7A 90 52 00 30 4D 00 00 08 52 45 54 49 00 +0D 12 84 12 0A 44 00 13 66 4C 78 49 0A 44 2C 00 +5C 52 A0 51 AA 47 66 52 3E 52 AC 52 3D 41 2C DE +8B 4C 00 00 9E 3F 00 00 06 4D 4F 56 85 12 9C 52 +00 40 B8 52 0A 4D 4F 56 2E 42 85 12 9C 52 40 40 +00 00 06 41 44 44 85 12 9C 52 00 50 D2 52 0A 41 +44 44 2E 42 85 12 9C 52 40 50 DE 52 08 41 44 44 +43 00 85 12 9C 52 00 60 EC 52 0C 41 44 44 43 2E +42 00 85 12 9C 52 40 60 24 4F 08 53 55 42 43 00 +85 12 9C 52 00 70 0A 53 0C 53 55 42 43 2E 42 00 +85 12 9C 52 40 70 18 53 06 53 55 42 85 12 9C 52 +00 80 28 53 0A 53 55 42 2E 42 85 12 9C 52 40 80 +34 53 06 43 4D 50 85 12 9C 52 00 90 42 53 0A 43 +4D 50 2E 42 85 12 9C 52 40 90 00 00 08 44 41 44 +44 00 85 12 9C 52 00 A0 5C 53 0C 44 41 44 44 2E +42 00 85 12 9C 52 40 A0 8A 52 06 42 49 54 85 12 +9C 52 00 B0 7A 53 0A 42 49 54 2E 42 85 12 9C 52 +40 B0 86 53 06 42 49 43 85 12 9C 52 00 C0 94 53 +0A 42 49 43 2E 42 85 12 9C 52 40 C0 A0 53 06 42 +49 53 85 12 9C 52 00 D0 AE 53 0A 42 49 53 2E 42 +85 12 9C 52 40 D0 00 00 06 58 4F 52 85 12 9C 52 +00 E0 C8 53 0A 58 4F 52 2E 42 85 12 9C 52 40 E0 +FA 52 06 41 4E 44 85 12 9C 52 00 F0 E2 53 0A 41 +4E 44 2E 42 85 12 9C 52 40 F0 AA 47 5C 52 A0 51 +02 54 0A 4C 3C F0 70 00 8A 10 3A F0 0F 00 0C DA +4D 3F BA 53 06 52 52 43 85 12 FA 53 00 10 14 54 +0A 52 52 43 2E 42 85 12 FA 53 40 10 4E 53 08 53 +57 50 42 00 85 12 FA 53 80 10 20 54 06 52 52 41 +85 12 FA 53 00 11 3C 54 0A 52 52 41 2E 42 85 12 +FA 53 40 11 2E 54 06 53 58 54 85 12 FA 53 80 11 +00 00 08 50 55 53 48 00 85 12 FA 53 00 12 62 54 +0C 50 55 53 48 2E 42 00 85 12 FA 53 40 12 56 54 +08 43 41 4C 4C 00 85 12 FA 53 80 12 1A 53 0E 4A +84 12 EC 49 1E 44 0D 6F 75 74 20 6F 66 20 62 6F +75 6E 64 73 12 45 80 54 06 53 3E 3D 86 12 00 38 +A8 54 04 53 3C 00 86 12 00 34 70 54 06 30 3E 3D +86 12 00 30 BC 54 04 30 3C 00 86 12 00 30 F8 4E +04 55 3C 00 86 12 00 2C D0 54 06 55 3E 3D 86 12 +00 28 C6 54 06 30 3C 3E 86 12 00 24 E4 54 04 30 +3D 00 86 12 00 20 00 00 04 49 46 00 1A 42 C8 1D +8A 4E 00 00 A2 53 C8 1D 0E 4A 30 4D 6A 53 08 54 +48 45 4E 00 1A 42 C8 1D 08 4E 3E 4F 09 48 29 53 +0A 89 0A 11 3A 90 00 02 B2 2F 88 DA 00 00 30 4D +DA 54 08 45 4C 53 45 00 1A 42 C8 1D BA 40 00 3C +00 00 A2 53 C8 1D 2F 83 8F 4A 00 00 E3 3F 48 54 +0A 42 45 47 49 4E 30 40 32 44 32 55 0A 55 4E 54 +49 4C 3A 4F 08 4E 3E 4F 19 42 C8 1D 2A 83 0A 89 +0A 11 3A 90 00 FE 8B 3B 3A F0 FF 03 08 DA 89 48 +00 00 A2 53 C8 1D 30 4D EE 53 0A 41 47 41 49 4E +0A 4E 38 40 00 3C E7 3F 00 00 0A 57 48 49 4C 45 +0D 12 84 12 FC 54 92 48 78 49 50 55 0C 52 45 50 +45 41 54 00 0D 12 84 12 90 55 14 55 78 49 C0 55 +3D 41 08 4E 3E 4F 2A 48 B2 92 C6 1D CB 2F 98 42 +C8 1D 00 00 30 4D AC 55 06 42 57 31 85 12 BE 55 +00 00 D8 55 06 42 57 32 85 12 BE 55 00 00 E4 55 +06 42 57 33 85 12 BE 55 00 00 FC 55 3D 41 1A 42 +C8 1D 28 4E 8E 43 00 00 B2 92 C6 1D 86 2B BA 4F +00 00 A2 53 C8 1D 8E 4A 00 00 3E 4F 30 4D 00 00 +06 46 57 31 85 12 FA 55 00 00 20 56 06 46 57 32 +85 12 FA 55 00 00 2C 56 06 46 57 33 85 12 FA 55 +00 00 9A 55 08 47 4F 54 4F 00 2F 83 8F 4E 00 00 +3E 40 00 3C 0D 12 84 12 32 4D 3E 4C 78 49 00 00 +0A 3F 47 4F 54 4F 3E 90 00 30 F4 27 3E E0 00 04 +3E B0 00 10 EF 27 3E E0 00 08 EC 3F 66 52 0A 44 +2C 00 FC 49 0E 4B AC 44 42 4D AA 47 5C 52 3E 52 +92 56 0A 4E 3E 4F 1A 83 F9 32 29 4E 59 0E 0A 28 +08 4C 59 0A 01 28 0C 8A 08 8A 38 90 10 00 EE 2E +5A 0E AD 3E 2A 92 EA 2E 8A 10 5A 06 A8 3E F0 55 +08 52 52 43 4D 00 85 12 7C 56 50 00 C0 56 08 52 +52 41 4D 00 85 12 7C 56 50 01 CE 56 08 52 4C 41 +4D 00 85 12 7C 56 50 02 DC 56 08 52 52 55 4D 00 +85 12 7C 56 50 03 EE 54 0A 50 55 53 48 4D 85 12 +7C 56 00 15 F8 56 08 50 4F 50 4D 00 85 12 7C 56 +00 17 @FF80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 82 46 E2 45 -E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 E2 45 08 51 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 D2 46 FA 45 +FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 FA 45 0E 46 q diff --git a/binaries/MSP_EXP430FR6989_8MHz_UART.txt b/binaries/MSP_EXP430FR6989_8MHz_UART.txt deleted file mode 100644 index 868f118..0000000 --- a/binaries/MSP_EXP430FR6989_8MHz_UART.txt +++ /dev/null @@ -1,337 +0,0 @@ -@1800 -40 1F 04 00 51 55 18 00 F9 FF 0E 58 02 50 34 01 -10 00 41 B3 94 45 AA 44 DA 45 9C 45 94 46 0E 58 -02 50 7A 46 92 47 24 47 FE 46 3C 1D 60 48 D4 44 -E2 44 EE 44 20 00 0A 00 00 00 00 00 00 00 00 00 -@4400 -B0 12 DA 45 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 -3E 4D 30 4D 2F 82 8F 4E 02 00 7E 4D 8F 4D 00 00 -0D 5E 1D B3 0D 63 30 4D 2F 83 8F 4E 00 00 1E 42 -C6 1D 30 4D 0E 93 3E 4F 11 20 2D 4D 30 4D 39 40 -00 80 39 8F 08 4E 3E 4F 08 59 19 15 30 4D 81 5E -00 00 3E 4F 32 B0 00 01 F0 27 21 52 2D 53 30 4D -91 53 00 00 F7 3F 0B 4E 1C 4F 02 00 2E 4F 0A 43 -35 40 20 00 0E 93 04 20 05 11 0E 4C 0C 43 09 43 -0A 9B 01 28 0A 8B 09 69 08 68 15 83 07 30 0C 5C -0E 6E 0A 6A F5 2B 0A 8B 12 D3 F5 3F 35 40 D4 44 -8F 4A 02 00 8F 49 00 00 0E 48 30 41 82 4E C0 1D -B2 4F C2 1D 82 43 C4 1D 3E 4F 30 4D 3F 80 06 00 -8F 4E 04 00 3E 40 54 00 BF 40 3C 1D 00 00 AF 4F -02 00 D1 3C 2F 83 8F 4E 00 00 3E 41 0D 12 3D 4E -30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D 2F 83 -8F 4E 00 00 3E 41 30 4D B0 12 AA 44 39 40 22 18 -B2 49 78 46 B2 49 90 47 B2 49 22 47 B2 49 FC 46 -B2 49 CA 44 34 49 35 49 36 49 37 49 B2 49 B4 1D -B2 49 DC 1D 3D 41 30 40 CE 50 8F 93 02 00 03 20 -2F 52 3E 4F 30 4D B0 12 DA 45 92 C3 FC 05 18 42 -00 18 39 40 41 00 19 83 FE 23 18 83 FA 23 92 B3 -FC 05 F3 23 B0 12 F8 44 0A 44 DE 1D E0 47 32 47 -14 44 04 1B 5B 37 6D 00 5C 47 A8 47 34 44 86 45 -14 44 0F 4C 41 53 54 2E 34 54 48 2C 20 6C 69 6E -65 20 5C 47 A0 48 5C 47 14 44 04 1B 5B 30 6D 00 -5C 47 28 4C 92 B3 EA 05 FD 23 30 41 2E 93 12 28 -B2 40 81 00 E0 05 92 42 02 18 E6 05 92 42 04 18 -E8 05 F2 D0 30 00 2A 02 92 C3 E0 05 92 D3 FA 05 -92 C3 30 01 30 41 09 3C A2 B3 FC 05 FD 27 B2 40 -13 00 EE 05 D2 D3 22 02 30 41 A2 B3 FC 05 FD 27 -B2 40 11 00 EE 05 D2 C3 22 02 30 41 00 00 04 57 -49 50 45 00 B2 43 08 18 04 3C 00 00 04 43 4F 4C -44 00 B0 12 94 45 E2 B3 00 02 02 20 B2 43 08 18 -B2 40 04 A5 20 01 EE 45 04 57 41 52 4D 00 B0 12 -9C 45 84 12 14 44 07 0D 0A 1B 5B 37 6D 23 5C 47 -D6 48 14 44 19 46 61 73 74 46 6F 72 74 68 20 C2 -A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 5C 47 -0A 44 40 FF 28 44 D4 47 A0 48 14 44 0A 62 79 74 -65 73 20 66 72 65 65 00 3A 44 86 45 00 00 06 41 -43 43 45 50 54 00 30 40 7A 46 08 4E 2E 4F 08 5E -39 40 0D 00 3A 40 20 00 3B 40 C6 46 3C 40 D2 46 -5D 15 B6 3E 21 52 3A 17 58 42 EC 05 48 9B 94 27 -48 9C 06 2C 78 92 11 20 2E 9F 0F 24 1E 83 05 3C -0E 9A 03 24 CE 48 00 00 1E 53 A2 B3 FC 05 FD 27 -C2 48 EE 05 30 4D C8 46 2D 83 92 B3 FC 05 E4 23 -FC 3F 3E 8F 3D 41 B2 40 18 00 06 18 92 B3 FC 05 -FD 27 58 42 EC 05 82 93 DE 1D 02 24 92 53 DE 1D -08 4C E3 3F 00 00 03 4B 45 59 30 40 FE 46 2F 83 -8F 4E 00 00 B0 12 DA 45 92 B3 FC 05 FD 27 1E 42 -EC 05 B0 12 C8 45 30 4D 00 00 04 45 4D 49 54 00 -30 40 24 47 08 4E 3E 4F C8 3F 1A 47 04 45 43 48 -4F 00 B2 40 C2 48 C0 46 82 43 DE 1D 30 4D 00 00 -06 4E 4F 45 43 48 4F 00 B2 40 30 4D C0 46 92 43 -DE 1D 30 4D 00 00 04 54 59 50 45 00 0E 93 11 24 -0D 12 3D 40 78 47 28 4F 2F 83 8F 4E 00 00 7E 48 -8F 48 02 00 10 42 22 47 7A 47 2D 83 1E 83 F3 23 -3D 41 2F 53 3E 4F 30 4D FC 45 02 43 52 00 30 40 -92 47 0D 12 84 12 14 44 02 0D 0A 00 5C 47 60 48 -2F 83 8F 4E 00 00 30 4D 0E 93 FA 23 30 4D 8F 4E -FE FF AF 4F FC FF 2F 82 30 4D 2A 4F 8F 4E 00 00 -0E 4A 30 4D 8F 4E FE FF 3E 40 80 1C 0E 8F 0E 11 -2F 83 30 4D 3E 8F 3E E3 1E 53 30 4D 6E 46 01 40 -2E 4E 30 4D DE 47 01 21 BE 4F 00 00 3E 4F 30 4D -1E 83 0E 7E 30 4D 0E 5E 0E 7E 3E E3 30 4D 3E 8F -03 24 3E 43 01 2C 0E F3 30 4D 00 00 02 3C 23 00 -B2 40 B2 1D B2 1D 30 4D 8A 47 01 23 1B 42 DC 1D -2C 4F 2F 83 B0 12 6E 44 BF 4F 00 00 7A 90 0A 00 -02 28 7A 50 07 00 7A 50 30 00 92 83 B2 1D 18 42 -B2 1D C8 4A 00 00 30 4D 1A 48 02 23 53 00 0D 12 -84 12 1C 48 56 48 2D 83 09 93 E2 23 0E 93 E0 23 -3D 41 30 4D 4A 48 02 23 3E 00 9F 42 B2 1D 00 00 -3E 40 B2 1D 2E 8F 30 4D 00 00 04 48 4F 4C 44 00 -4A 4E 3E 4F DA 3F 00 00 04 53 49 47 4E 00 0E 93 -3E 4F 7A 40 2D 00 D1 33 30 4D 56 47 02 55 2E 00 -08 43 2F 83 8F 4E 00 00 0E 48 0D 12 0E 12 3E F3 -06 34 BF E3 00 00 3E E3 9F 53 00 00 0E 63 84 12 -10 48 4E 48 EE 44 8E 48 6A 48 5C 47 14 4C 20 47 -60 48 40 47 01 2E 0E 93 E3 37 38 43 E2 3F 88 48 -82 53 22 00 82 43 B4 1D 0D 12 84 12 0A 44 14 44 -5A 4B 0A 44 22 00 2C 49 FA 48 B2 40 20 00 B4 1D -6E 4E 1E 53 1E B3 82 6E C6 1D 3E 4F 3D 41 30 4D -D4 48 82 2E 22 00 0D 12 84 12 E4 48 0A 44 5C 47 -5A 4B 60 48 18 46 04 57 4F 52 44 00 3C 40 C0 1D -39 4C 3A 4C 09 5A 3A 5C 28 4C 09 9A 1D 24 7E 9A -FC 27 1A 83 3B 40 60 00 15 42 B4 1D FA 90 27 00 -00 00 01 20 05 43 C8 4C 00 00 09 9A 0B 24 7C 4A -4E 9C 08 24 18 53 4B 9C F6 2F 7C 90 7B 00 F3 2F -4C 85 F1 3F 35 40 D4 44 1A 82 C2 1D 82 4A C4 1D -1E 42 C6 1D 08 8E CE 48 00 00 30 4D 00 00 04 46 -49 4E 44 00 2F 83 0C 4E 66 4C 75 40 80 00 3B 40 -CA 1D 3E 4B 0E 93 1E 24 58 4C 01 00 78 F0 1E 00 -0E 58 2E 53 1E 4E FE FF 0E 93 F3 27 09 4E 78 49 -48 C5 48 96 F7 23 0A 4C FA 99 01 00 F3 23 1A 53 -58 83 FA 23 19 B3 09 63 0C 49 CE 93 00 00 1E 43 -01 30 2E 83 8F 4C 00 00 36 40 E2 44 35 40 D4 44 -30 4D 00 00 07 3E 4E 55 4D 42 45 52 3C 4F 38 4F -29 4F 2F 82 1B 42 DC 1D 6A 4C 7A 80 30 00 7A 90 -0A 00 05 28 7A 80 07 00 7A 90 0A 00 12 28 0A 9B -22 C3 0F 2C 82 49 D0 04 82 48 D2 04 82 4B C8 04 -19 42 E4 04 18 42 E6 04 09 5A 08 63 1C 53 1E 83 -E3 23 8F 4C 00 00 8F 48 02 00 8F 49 04 00 30 4D -32 C0 00 02 1B 42 DC 1D 0C 43 2D 15 3D 40 AE 4A -09 43 08 43 3F 82 8F 4E 06 00 0C 4E 7E 4C FC 90 -27 00 00 00 07 20 5C 4C 01 00 8F 4C 04 00 7E 90 -03 00 48 3C 6A 4C 7A 80 2D 00 04 28 BD 23 B1 43 -02 00 0A 3C 2B 43 7A 52 07 24 3B 52 6A 53 04 24 -3B 40 10 00 7A 53 36 20 1C 53 1E 83 EB 3F B0 4A -31 24 2D 83 7A 90 28 00 C1 27 32 B0 00 02 2A 20 -32 D0 00 02 7A 90 F7 00 B9 27 7A 90 F5 00 22 20 -0A 4E 09 43 8F 49 02 00 5A 83 09 4A 09 5C 69 49 -79 80 30 00 79 90 0A 00 05 28 79 80 07 00 79 90 -0A 00 0A 28 09 9B 08 2C 8F 49 00 00 0E 4B 2C 15 -B0 12 66 44 2A 17 E6 3F 9F 4F 04 00 02 00 AF 4F -04 00 4A 93 2B 17 0E 4C 82 4B DC 1D 06 24 32 C0 -00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 -04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 -BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 -01 20 2F 53 30 4D 00 00 01 2C 1A 42 C6 1D 8A 4E -00 00 A2 53 C6 1D 3E 4F 30 4D 58 4B 87 4C 49 54 -45 52 41 4C 82 93 BE 1D 0D 24 09 4E 1A 42 C6 1D -A2 52 C6 1D BA 40 0A 44 00 00 8A 49 02 00 3E 4F -32 B0 00 02 32 C0 00 02 03 24 8A 4E 02 00 EE 3F -30 4D 66 48 05 43 4F 55 4E 54 2F 83 1E 53 8F 4E -00 00 5E 4E FF FF 30 4D 7A 48 09 49 4E 54 45 52 -50 52 45 54 0D 12 84 12 AC 44 14 4C 2C 49 D0 4B -9C 26 3D 40 D8 4B DE 3E DA 4B 0A 4E 3E 4F 3D 40 -F4 4B 36 27 3D 40 CA 4B 1A E2 BE 1D B6 27 0E 12 -3E 4F 30 41 F6 4B 3E 4F 3D 40 CA 4B BB 23 DE 53 -00 00 68 4E 08 5E F8 40 3F 00 00 00 3D 40 96 4D -CC 3F FE 4B 86 12 20 00 E6 47 05 41 4C 4C 4F 54 -82 5E C6 1D 3E 4F 30 4D 3F 40 80 1C 0E 43 31 40 -E0 1C B2 40 00 1C 00 1C 82 43 BE 1D 84 12 8E 47 -BC 44 C4 4B C4 47 F6 47 14 44 0C 73 74 61 63 6B -20 65 6D 70 74 79 21 00 2A 45 0A 44 40 FF 28 44 -FE 47 14 44 0A 46 52 41 4D 20 66 75 6C 6C 21 00 -2A 45 3A 44 3E 4C 1A 4C 86 41 42 4F 52 54 22 00 -0D 12 84 12 E4 48 0A 44 2A 45 5A 4B 60 48 8E 49 -01 27 0D 12 84 12 14 4C 2C 49 94 49 34 44 12 4C -60 48 00 00 83 5B 27 5D 0D 12 84 12 92 4C 0A 44 -0A 44 5A 4B 5A 4B 60 48 A4 4C 81 5B 82 43 BE 1D -30 4D 0C 48 01 5D B2 43 BE 1D 30 4D C4 4C 81 5C -92 42 C0 1D C4 1D 30 4D 00 00 88 50 4F 53 54 50 -4F 4E 45 00 0D 12 84 12 14 4C 2C 49 94 49 A8 47 -34 44 12 4C F6 47 34 44 06 4D 0A 44 0A 44 5A 4B -5A 4B 0A 44 5A 4B 5A 4B 60 48 BA 4C 01 3A 30 12 -56 4D 92 B3 C6 1D A2 63 C6 1D 0D 12 84 12 14 4C -2C 49 24 4D 3D 41 08 4E 7A 4E 5A D3 5A 53 0A 58 -19 42 DA 1D 6E 4E 3E F0 1E 00 09 5E 3E 4F 82 48 -B6 1D 82 49 B8 1D 82 4A BA 1D 82 4F BC 1D 2A 52 -82 4A C6 1D 30 41 BA 40 0D 12 FC FF BA 40 84 12 -FE FF B2 43 BE 1D 30 4D 82 9F BC 1D 09 20 18 42 -B6 1D 19 42 B8 1D A8 49 FE FF 89 48 00 00 30 4D -0D 12 84 12 14 44 0F 73 74 61 63 6B 20 6D 69 73 -6D 61 74 63 68 21 36 45 0C 4D 81 3B 82 93 BE 1D -97 27 0D 12 84 12 0A 44 60 48 5A 4B 68 4D BC 4C -60 48 BA 4B 09 49 4D 4D 45 44 49 41 54 45 18 42 -B6 1D F8 D0 80 00 00 00 30 4D A4 4B 06 43 52 45 -41 54 45 00 B0 12 12 4D BA 40 86 12 FC FF 8A 4A -FE FF C9 3F CC 4D 04 43 4F 44 45 00 B0 12 12 4D -A2 82 C6 1D 0D 12 84 12 04 50 DE 4F 60 48 B4 4D -07 48 44 4E 43 4F 44 45 B2 40 E2 4F DA 1D EE 3F -00 00 07 45 4E 44 43 4F 44 45 0D 12 84 12 68 4D -1E 50 3C 50 60 48 00 00 05 43 4F 4C 4F 4E 1A 42 -C6 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 A2 52 -C6 1D B2 43 BE 1D 0D 12 84 12 1E 50 3C 50 60 48 -00 00 05 4C 4F 32 48 49 A2 83 C6 1D 1A 42 C6 1D -EB 3F 00 4E 85 48 49 32 4C 4F 0D 12 84 12 28 44 -AC 4F 5A 4B BC 4C F4 4D 60 48 9A 4D 86 5B 54 48 -45 4E 5D 00 30 4D 0C 4E 38 4F 3B 4F 39 4F 0E 4B -0E 5C 10 24 1B 83 06 30 1C 83 04 30 19 53 F9 98 -FF FF F5 27 2D 4D 3E 4F 30 4D 2F 53 9F 83 00 00 -F9 23 2F 53 2D 53 F7 3F 7C 4E 86 5B 45 4C 53 45 -5D 00 0D 12 84 12 0A 44 00 00 D8 47 14 4C 2C 49 -AA 4B A0 47 34 44 14 4F AE 47 14 44 06 5B 54 48 -45 4E 5D 00 86 4E EE 4E AA 4E CC 4E 60 48 AE 47 -14 44 06 5B 45 4C 53 45 5D 00 86 4E 04 4F AA 4E -CA 4E 60 48 14 44 04 5B 49 46 5D 00 86 4E CC 4E -3A 44 CA 4E 82 47 14 44 05 0D 0A 6B 6F 20 5C 47 -BC 44 AC 44 3A 44 CC 4E BA 4E 84 5B 49 46 5D 00 -0E 93 3E 4F C6 27 30 4D 2F 53 30 4D 2A 4F 89 5B -44 45 46 49 4E 45 44 5D 0D 12 84 12 14 4C 2C 49 -94 49 38 4F 60 48 3E 4F 8B 5B 55 4E 44 45 46 49 -4E 45 44 5D 0D 12 84 12 48 4F F0 47 60 48 70 4F -B2 4E 0A 18 2E 53 BE 12 3E 4F 3D 41 90 3C 6C 4B -06 4D 41 52 4B 45 52 00 B0 12 12 4D BA 40 85 12 -FC FF BA 40 6E 4F FE FF 28 83 8A 48 00 00 BA 40 -AA 44 04 00 B2 50 06 00 C6 1D E1 3E 2E 53 30 4D -0A 44 CA 1D E8 47 60 48 85 12 B0 4F 78 4C E6 4D -2C 47 90 4C 64 4E F6 46 80 4F 12 49 A8 50 BC 50 -9C 48 26 49 00 00 58 4F CE 4C F4 49 00 00 85 12 -B0 4F 84 56 EA 56 2C 56 3A 57 F2 55 00 00 BE 53 -00 00 02 58 E6 57 56 56 94 56 CE 54 00 00 00 00 -56 57 DC 4F 3A 40 0C 00 39 40 D6 1D 08 49 28 53 -19 83 18 83 E8 49 00 00 1A 83 FA 23 30 4D 3A 40 -0E 00 38 40 CA 1D 09 48 29 53 F8 49 00 00 18 53 -1A 83 FB 23 30 4D 82 43 CC 1D 30 4D 92 42 CA 1D -DA 1D 30 4D B8 4F 36 50 3C 50 4C 50 1A 42 20 18 -82 4A C8 1D 2E 4E 82 4E C6 1D 3D 40 10 00 09 4A -08 49 29 83 18 48 FE FF 0E 98 FC 2B 89 48 00 00 -1D 83 F6 23 2A 4A 0A 93 F0 23 3E 4F 3D 41 30 4D -DA 4C 09 50 57 52 5F 53 54 41 54 45 85 12 44 50 -0E 58 E0 48 09 52 53 54 5F 53 54 41 54 45 92 42 -0A 18 90 50 F3 3F 82 50 08 50 57 52 5F 48 45 52 -45 00 92 42 C6 1D 90 50 30 4D 94 50 08 52 53 54 -5F 48 45 52 45 00 92 42 C6 1D 0A 18 F2 3F 3E 90 -0E 00 DC 27 2E 92 E3 37 0E 93 D8 37 39 40 10 00 -29 83 B9 43 80 FF FC 23 B9 40 1A 51 FE FF 29 83 -B9 40 02 46 FE FF 39 90 AE FF F9 23 39 40 14 18 -B2 49 04 46 B2 49 FA 44 B2 49 02 44 B2 49 20 46 -B2 49 E4 FF B2 49 0A 18 C2 3F B2 D0 03 00 04 01 -B2 D0 10 00 00 01 B2 40 80 5A 5C 01 31 40 E0 1C -3F 40 80 1C 39 40 00 08 29 83 89 43 00 1C FC 23 -B2 D3 06 02 B2 40 FE FF 02 02 B2 43 26 02 B2 43 -22 02 D2 D3 24 02 B2 43 46 02 B2 43 42 02 B2 43 -66 02 B2 43 62 02 B2 43 86 02 B2 40 7F FF 82 02 -F2 43 26 03 F2 43 22 03 F2 40 A5 00 61 01 82 43 -66 01 B2 40 33 00 64 01 D2 43 61 01 39 40 40 00 -18 42 00 18 18 83 FE 23 19 83 FA 23 B2 42 B0 01 -F2 D0 10 00 2A 03 F2 C0 40 00 A2 04 1E 42 08 18 -82 43 08 18 1E D2 9E 01 B0 12 F8 44 1E 46 38 40 -C0 1D 0A 4E 39 48 2E 48 09 5E 1E 52 C4 1D 09 9E -03 24 7A 9E FC 27 1E 83 0A 4E 2A 88 82 4A C4 1D -30 4D 1C 15 0E 12 12 12 C4 1D 84 12 2C 49 94 49 -F0 47 34 44 FE 51 50 4A 34 44 18 52 12 52 00 52 -3C 4E 3C 80 87 12 05 24 1C 53 02 20 2E 4E 01 3C -2E 83 21 52 1B 17 30 41 1A 52 B2 41 C4 1D 3E 41 -84 12 0A 44 2B 00 2C 49 94 49 F0 47 34 44 36 52 -50 4A 34 44 12 4C BA 47 2C 49 50 4A 34 44 12 4C -42 52 3E 5F E7 3F 3E 40 28 00 B0 12 E2 51 19 42 -C6 1D A2 53 C6 1D 89 4E 00 00 3E 40 29 00 92 92 -C0 1D C4 1D 02 20 30 40 80 4D 1C 15 12 12 C4 1D -92 53 C4 1D 84 12 2C 49 50 4A 34 44 8A 52 80 52 -21 53 3E 90 10 00 C6 2B 7F 2D 8C 52 B2 41 C4 1D -C1 3F 0D 12 84 12 14 4C BE 51 9C 52 0C 43 1B 42 -C6 1D A2 53 C6 1D 6A 4E 3E 4F 7A 90 23 00 27 20 -92 53 C4 1D B0 12 E2 51 3C 40 00 03 0E 93 1C 24 -3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 -3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 -3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C6 1D -A2 53 C6 1D 89 4E 00 00 3E 4F 3D 41 30 4D 7A 90 -26 00 07 20 3C 40 10 02 92 53 C4 1D B0 12 E2 51 -ED 3F 7A 90 40 00 16 20 3C 40 20 00 92 53 C4 1D -B0 12 6A 52 0C 20 3C 50 10 00 3E 40 2B 00 B0 12 -6A 52 92 92 C0 1D C4 1D 02 24 92 53 C4 1D 8E 10 -0C 5E DA 3F B0 12 6A 52 FA 23 3C 50 10 00 B0 12 -46 52 EF 3F 0C 43 1B 42 C6 1D A2 53 C6 1D 0D 12 -84 12 14 4C BE 51 68 53 FE 90 26 00 00 00 3E 40 -20 00 03 20 3C 50 82 00 C7 3F B0 12 6A 52 E0 23 -3C 50 80 00 B0 12 46 52 DB 3F 00 00 04 52 45 54 -49 00 0D 12 84 12 0A 44 00 13 5A 4B 60 48 0A 44 -2C 00 92 52 5E 53 A8 53 09 4B 2E 4E 0E DC A2 3F -52 4E 03 4D 4F 56 85 12 9E 53 00 40 B2 53 05 4D -4F 56 2E 42 85 12 9E 53 40 40 00 00 03 41 44 44 -85 12 9E 53 00 50 CC 53 05 41 44 44 2E 42 85 12 -9E 53 40 50 D8 53 04 41 44 44 43 00 85 12 9E 53 -00 60 E6 53 06 41 44 44 43 2E 42 00 85 12 9E 53 -40 60 8C 53 04 53 55 42 43 00 85 12 9E 53 00 70 -04 54 06 53 55 42 43 2E 42 00 85 12 9E 53 40 70 -12 54 03 53 55 42 85 12 9E 53 00 80 22 54 05 53 -55 42 2E 42 85 12 9E 53 40 80 28 4E 03 43 4D 50 -85 12 9E 53 00 90 3C 54 05 43 4D 50 2E 42 85 12 -9E 53 40 90 12 4E 04 44 41 44 44 00 85 12 9E 53 -00 A0 56 54 06 44 41 44 44 2E 42 00 85 12 9E 53 -40 A0 48 54 03 42 49 54 85 12 9E 53 00 B0 74 54 -05 42 49 54 2E 42 85 12 9E 53 40 B0 80 54 03 42 -49 43 85 12 9E 53 00 C0 8E 54 05 42 49 43 2E 42 -85 12 9E 53 40 C0 9A 54 03 42 49 53 85 12 9E 53 -00 D0 A8 54 05 42 49 53 2E 42 85 12 9E 53 40 D0 -00 00 03 58 4F 52 85 12 9E 53 00 E0 C2 54 05 58 -4F 52 2E 42 85 12 9E 53 40 E0 F4 53 03 41 4E 44 -85 12 9E 53 00 F0 DC 54 05 41 4E 44 2E 42 85 12 -9E 53 40 F0 14 4C 92 52 FA 54 0A 4C 3C F0 70 00 -8A 10 3A F0 0F 00 0C DA 4F 3F 2E 54 03 52 52 43 -85 12 F4 54 00 10 0C 55 05 52 52 43 2E 42 85 12 -F4 54 40 10 18 55 04 53 57 50 42 00 85 12 F4 54 -80 10 26 55 03 52 52 41 85 12 F4 54 00 11 34 55 -05 52 52 41 2E 42 85 12 F4 54 40 11 40 55 03 53 -58 54 85 12 F4 54 80 11 00 00 04 50 55 53 48 00 -85 12 F4 54 00 12 5A 55 06 50 55 53 48 2E 42 00 -85 12 F4 54 40 12 B4 54 04 43 41 4C 4C 00 85 12 -F4 54 80 12 1A 53 0E 4A 0D 12 84 12 D6 48 14 44 -0D 6F 75 74 20 6F 66 20 62 6F 75 6E 64 73 36 45 -4E 55 03 53 3E 3D 86 12 00 38 A2 55 02 53 3C 00 -86 12 00 34 68 55 03 30 3E 3D 86 12 00 30 B6 55 -02 30 3C 00 86 12 00 30 00 00 02 55 3C 00 86 12 -00 2C CA 55 03 55 3E 3D 86 12 00 28 C0 55 03 30 -3C 3E 86 12 00 24 DE 55 02 30 3D 00 86 12 00 20 -00 00 02 49 46 00 1A 42 C6 1D 8A 4E 00 00 A2 53 -C6 1D 0E 4A 30 4D D4 55 04 54 48 45 4E 00 1A 42 -C6 1D 08 4E 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 -00 02 B1 2F 88 DA 00 00 30 4D 64 54 04 45 4C 53 -45 00 1A 42 C6 1D BA 40 00 3C 00 00 A2 53 C6 1D -2F 83 8F 4A 00 00 E3 3F 78 55 05 42 45 47 49 4E -30 40 28 44 08 56 05 55 4E 54 49 4C 3A 4F 08 4E -3E 4F 19 42 C6 1D 2A 83 0A 89 0A 11 3A 90 00 FE -8A 3B 3A F0 FF 03 08 DA 89 48 00 00 A2 53 C6 1D -30 4D E8 54 05 41 47 41 49 4E 0A 4E 38 40 00 3C -E7 3F 00 00 05 57 48 49 4C 45 0D 12 84 12 F6 55 -BA 47 60 48 AC 55 06 52 45 50 45 41 54 00 0D 12 -84 12 8A 56 0E 56 60 48 BA 56 3D 41 08 4E 3E 4F -2A 48 B2 92 C4 1D CB 2F 98 42 C6 1D 00 00 30 4D -4A 56 03 42 57 31 85 12 B8 56 00 00 D2 56 03 42 -57 32 85 12 B8 56 00 00 DE 56 03 42 57 33 85 12 -B8 56 00 00 F6 56 3D 41 1A 42 C6 1D 28 4E B2 92 -C4 1D 88 2B BA 4F 00 00 A2 53 C6 1D 8E 4A 00 00 -3E 4F 30 4D 00 00 03 46 57 31 85 12 F4 56 00 00 -16 57 03 46 57 32 85 12 F4 56 00 00 22 57 03 46 -57 33 85 12 F4 56 00 00 2E 57 04 47 4F 54 4F 00 -2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 92 4C -EE 4B 60 48 00 00 05 3F 47 4F 54 4F 3E 90 00 30 -F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 -EC 3F 14 4C BE 51 78 57 92 53 C4 1D 3E 40 2C 00 -84 12 2C 49 50 4A 34 44 12 4C 54 53 8E 57 0A 4E -3E 4F 1A 83 F7 32 29 4E 59 0E 0A 28 08 4C 59 0A -01 28 0C 8A 08 8A 38 90 10 00 EC 2E 5A 0E AB 3E -2A 92 E8 2E 8A 10 5A 06 A6 3E A6 56 04 52 52 43 -4D 00 85 12 72 57 50 00 BC 57 04 52 52 41 4D 00 -85 12 72 57 50 01 CA 57 04 52 4C 41 4D 00 85 12 -72 57 50 02 D8 57 04 52 52 55 4D 00 85 12 72 57 -50 03 E8 55 05 50 55 53 48 4D 85 12 72 57 00 15 -F4 57 04 50 4F 50 4D 00 85 12 72 57 00 17 -@FF80 -FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -77 00 10 00 12 00 14 00 16 00 00 00 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 94 46 02 46 02 46 02 46 02 46 02 46 -02 46 02 46 02 46 02 46 02 46 02 46 02 46 1A 51 -q diff --git a/config/BSL_prog.bat b/config/BSL_prog.bat index 46ce45e..7050a23 100644 --- a/config/BSL_prog.bat +++ b/config/BSL_prog.bat @@ -30,12 +30,12 @@ :: %1 = target name without ext. of \binaries\target.txt file :: %2 = port COMx in use :: %~d1 = drive: of %1 -:: %~n1 = target name without ext. of %1 +:: %~nx1 = target name with ext. of %1 @set PortCOM=%2 @if 1%PortCOM% == 1 CALL %~d1\config\Select.bat SelectPortCOM @%~d1\prog\BSL-Scripter.exe --log --quiet --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --erase ERASE_ALL --exit [RESET] -@%~d1\prog\BSL-Scripter.exe --log --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --speed FAST --bslPwd %~d1\binaries\pass32_default.txt -w %~d1\binaries\%~n1.txt --exit [RESET] +@%~d1\prog\BSL-Scripter.exe --log --initComm [INVOKE,%PortCOM%,UART,9600,PARITY] --device FRxx --speed FAST --bslPwd %~dp1binaries\pass32_default.txt -w %~dp1binaries\%~nx1 --exit [RESET] @pause diff --git a/config/Command Prompt.lnk b/config/Command Prompt.lnk new file mode 100644 index 0000000000000000000000000000000000000000..2f5d6b817393a489470e12d70112794365f678f6 GIT binary patch literal 1098 zcmeZaU|?VrVFHp23<tm@gWC~i28aNJkCS9XlTl@GU{GZ!XUJs8V@Ls#ML=E*Loq`o z5SK8dGUPHCGZ=wIGJw1sAO!LCfNDW(9R^(>&xpYkC~CqWNt8*+Kr>T-CZsY{0C5`7 zJ)8^-3v_|BVQ@h3qpk?IJw6uByZ;DJR-2J~P7vl^VHg8Q!xV>V_{^`IZ|S|_!ow@N z53ha(DHZ~$11U!KsR%Qezd*G-GcP5xNHwOovbZEQ*Vrf~IX6WwwIUUyX@me`VjDG% LMo7SnKyLy7<5xfS literal 0 HcmV?d00001 diff --git a/config/CopySourceFileToTarget_SD_Card.bat b/config/CopySourceFileToTarget_SD_Card.bat index f97083b..d03c1cb 100644 --- a/config/CopySourceFileToTarget_SD_Card.bat +++ b/config/CopySourceFileToTarget_SD_Card.bat @@ -14,9 +14,9 @@ exit call %~d1\config\Select.bat SelectTemplate -@start %~d1\config\CopyTo_SD_Card.bat %1 %~d1\inc\%template% %2 +@start %~d1\config\CopyTo_SD_Card.bat %1 %~dp1inc\%template% %2 ::PAUSE > NUL exit :: %1 is file.f or file.4th to be send -:: optionnal %2 may be used by CopyTo_SD_Card.bat \ No newline at end of file +:: optionnal %2 may be used by CopyTo_SD_Card.bat diff --git a/config/CopyTo_SD_Card.bat b/config/CopyTo_SD_Card.bat index a8582d7..de5a028 100644 --- a/config/CopyTo_SD_Card.bat +++ b/config/CopyTo_SD_Card.bat @@ -2,7 +2,7 @@ ::used by CopySourceFileToTarget_SD_Card.bat or by scite editor Tools menu ::echo %2 -::echo %~d1\inc\%~n2.pat +::echo %~dp1..\inc\%~n2.pat @ECHO OFF @@ -33,8 +33,8 @@ echo %~dpn1.f not found! goto badend ) -IF NOT EXIST %~d1\inc\%~n2.pat ( -echo %~d1\inc\%~n2.pat not found! +IF NOT EXIST %~dp1..\inc\%~n2.pat ( +echo %~dp1..\inc\%~n2.pat not found! goto badend ) @@ -51,8 +51,8 @@ exit :preprocessF -@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~d1\inc\%~n2.pat %~dpn1.f %~dpn1.4TH -@call %~d1\config\Select.bat SelectDeviceId %~d1\inc\%~n2.pat +@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dpn1.4TH +@call %~d1\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat :DownloadF @taskkill /F /IM ttermpro.exe 1> NUL 2>&1 diff --git a/config/FET_prog.bat b/config/FET_prog.bat index f1c2af6..4b98053 100644 --- a/config/FET_prog.bat +++ b/config/FET_prog.bat @@ -1,14 +1,26 @@ ::@echo off -@call %~d1\config\Select.bat SelectDevice %1 -@echo %device% programmation -%~d1\prog\msp430flasher -s -m SBW2 -u -n %device% -v -w %~d1\binaries\%~n1.txt -z [RESET,VCC] +@if F%1==F ( + @echo no file to do that! +) else ( + @call %~d1\config\Select.bat SelectDevice %1 + @IF EXIST %~dp1binaries\%~n1.txt GOTO progtxt + @IF EXIST %~dp1binaries\%~n1.hex GOTO proghex +) +@exit + +:progtxt +%~d1\prog\msp430flasher -s -m SBW2 -u -n %device% -v -w %~dp1binaries\%~n1.txt -z [RESET,VCC] +@exit +:proghex +%~d1\prog\msp430flasher -s -m SBW2 -u -n %device% -v -w %~dp1binaries\%~n1.hex -z [RESET,VCC] @exit :: your git copy must be the root of a virtual drive -:: %n1 = file filename (= target) to flash +:: %n1 = filename of file to flash +:: %nx1 = filename.ext of file to flash :: -s : force update :: -m : select SBW2 mode :: -u : Unlocks locked flash memory (INFOA) for writing. diff --git a/config/INFO.txt b/config/INFO.txt new file mode 100644 index 0000000..c8251e2 --- /dev/null +++ b/config/INFO.txt @@ -0,0 +1,34 @@ +@1800 +80 3E 12 00 00 00 F8 00 00 00 35 01 10 00 E0 43 +56 41 B8 5C 44 41 76 5B DC 42 1A 4C 96 65 62 4C +CA 42 4E 43 2A 43 3C 1D E0 1C E2 45 B6 40 C4 40 +F8 44 20 00 0A 00 00 1C 1A 4C 1A 4C 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +q diff --git a/config/MSP430read.bat b/config/MSP430read.bat index cfc1d5f..4a6c849 100644 --- a/config/MSP430read.bat +++ b/config/MSP430read.bat @@ -6,7 +6,7 @@ set readfile=%2 if "%1" == "" set howtoread=MAIN if "%2" == "" set readfile=MAIN_DUMP -%~d1\prog\msp430flasher -m SBW2 -r [%readfile%_%howtoread%.txt,%howtoread%] -z [VCC=3000] +%~d1\prog\msp430flasher -m SBW2 -r [%readfile%.HEX,%howtoread%] -z [VCC=3000] ::%~d1\prog\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary ::%~d1\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin diff --git a/config/MSP430readINFO.bat b/config/MSP430readINFO.bat new file mode 100644 index 0000000..fbf5de6 --- /dev/null +++ b/config/MSP430readINFO.bat @@ -0,0 +1,13 @@ + +:: usage: MSP430Read RAM|INFO|MAIN|BSL output + +::set howtoread=%1 +::set readfile=%2 +::if "%1" == "" set howtoread=MAIN +::if "%2" == "" set readfile=MAIN_DUMP + +%~d1\prog\msp430flasher -m SBW2 -r [target_INFO.txt,INFO] -z [VCC=3000] +::%~d1\prog\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary +::%~d1\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin + +pause diff --git a/config/MSP430readMAIN.bat b/config/MSP430readMAIN.bat new file mode 100644 index 0000000..6e45532 --- /dev/null +++ b/config/MSP430readMAIN.bat @@ -0,0 +1,13 @@ + +:: usage: MSP430Read RAM|INFO|MAIN|BSL output + +::set howtoread=%1 +::set readfile=%2 +::if "%1" == "" set howtoread=MAIN +::if "%2" == "" set readfile=MAIN_DUMP + +%~d1\prog\msp430flasher -m SBW2 -r [target_MAIN.txt,MAIN] -z [VCC=3000] +::%~d1\prog\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary +::%~d1\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin + +pause diff --git a/config/MSP430readRAM.bat b/config/MSP430readRAM.bat new file mode 100644 index 0000000..f6e05c3 --- /dev/null +++ b/config/MSP430readRAM.bat @@ -0,0 +1,13 @@ + +:: usage: MSP430Read RAM|INFO|MAIN|BSL output + +::set howtoread=%1 +::set readfile=%2 +::if "%1" == "" set howtoread=MAIN +::if "%2" == "" set readfile=MAIN_DUMP + +%~d1\prog\msp430flasher -m SBW2 -r [target_RAM.txt,RAM] -z [VCC=3000] +::%~d1\prog\srec_cat %readfile%_%howtoread%.HEX -intel -output %readfile%_%howtoread%.bin -Binary +::%~d1\prog\HxD\HxD.exe" %readfile%_%howtoread%.bin + +pause diff --git a/config/Preprocess.bat b/config/Preprocess.bat index 49cc83e..0c7ae9c 100644 --- a/config/Preprocess.bat +++ b/config/Preprocess.bat @@ -4,7 +4,7 @@ @ECHO OFF ::echo %2 -::echo %~d1\inc\%~n2.pat +::echo %~dp1..\inc\%~n2.pat IF "%2" == "" ( echo no file to be preprocessed! @@ -16,8 +16,8 @@ echo %~dpn1.f not found! goto badend ) -IF NOT EXIST %~d1\inc\%~n2.pat ( -echo %~d1\inc\%~n2.pat not found! +IF NOT EXIST %~dp1..\inc\%~n2.pat ( +echo %~dp1..\inc\%~n2.pat not found! goto badend ) @@ -31,8 +31,11 @@ exit :preprocess -%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~d1\inc\%~n2.pat %~dpn1.f %~dp1LAST.4TH -XCOPY /D /Y %~dp1LAST.4TH %~dp1\%~n2\%~n1.4TH* > NUL +%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dp1LAST.4TH + +call %~d1\config\Select.bat SelectDevice %~dp1..\inc\%~n2.pat +if not exist %~dp1SD_%device:~3% MD %~dp1SD_%device:~3% > NUL +COPY /y %~dp1LAST.4TH %~dp1SD_%device:~3%\%~n1.4TH > NUL exit :: %~dpn1.f is the symbolic source file diff --git a/config/PreprocessSourceFile.bat b/config/PreprocessSourceFile.bat index ac0b22c..4304288 100644 --- a/config/PreprocessSourceFile.bat +++ b/config/PreprocessSourceFile.bat @@ -2,7 +2,7 @@ ::used as link in any folder to drag and drop file.f on it. ::@call SelectTarget.bat @call %~d1\config\Select.bat SelectTemplate -@start %~d1\config\Preprocess.bat %1 %~d1\inc\%template% %2 +@start %~d1\config\Preprocess.bat %1 %~dp1..\inc\%template% %2 exit :: %1 is file.f to be preprocessed -:: %2 is used by Preprocess.bat as an unexpected third parameter \ No newline at end of file +:: %2 is used by Preprocess.bat as an unexpected third parameter diff --git a/config/SciTEUser.properties b/config/SciTEUser.properties new file mode 100644 index 0000000..c2c4123 --- /dev/null +++ b/config/SciTEUser.properties @@ -0,0 +1,250 @@ +# SciTEUser.properties +# For Windows, place in your home directory +# Documentation at http://www.scintilla.org/SciTEDoc.html + +# Globals + +PLAT_WIN=1 +PLAT_GTK=0 +position.maximize=1 + +save.session=1 +save.recent=1 +save.session=1 +session.bookmarks=1 + +buffers.zorder.switching=1 +properties.directory.enable=1 +check.if.already.open=1 + +# # Scripting +# ext.lua.startup.script=$(SciteUserHome)/SciTEStartup.lua +# ext.lua.auto.reload=1 +# #ext.lua.reset=1 + + +# Window sizes and visibility +if PLAT_WIN + position.left=-1 + position.top=0 +if PLAT_GTK + position.left=5 + position.top=22 + +position.width=1000 +position.height=768 +position.maximize=1 +#position.tile=1 +#full.screen.hides.menu=1 +minimize.to.tray=0 +split.vertical=1 +output.horizontal.size=400 +output.vertical.size=600 +output.initial.hide=1 +#horizontal.scrollbar=0 +#horizontal.scroll.width=10000 +#horizontal.scroll.width.tracking=0 +#output.horizontal.scrollbar=0 +#output.horizontal.scroll.width=10000 +#output.horizontal.scroll.width.tracking=0 +#output.scroll=0 +error.select.line=1 +#end.at.last.line=0 +tabbar.visible=1 +#tabbar.hide.one=1 +tabbar.multiline=0 +toolbar.large=1 +toolbar.visible=1 +#toolbar.detachable=1 +#toolbar.usestockicons=1 +#menubar.detachable=1 +#undo.redo.lazy=1 +statusbar.visible=1 +#fileselector.width=800 +#fileselector.height=600 +#fileselector.show.hidden=1 +magnification=0 +output.magnification=-4 + +# Sizes and visibility in edit pane +line.margin.visible=1 +line.margin.width=4 +margin.width=16 +fold.margin.width=0 +#fold.margin.colour=#00FF00 +#fold.margin.highlight.colour=#0000FF +blank.margin.left=20 +#blank.margin.right=4 +buffered.draw=1 +#two.phase.draw=0 +use.palette=0 + +#Element styles + +#view.eol=1 +#control.char.symbol=. +caret.period=500 +view.whitespace=0 +view.indentation.whitespace=1 +view.indentation.guides=0 +view.indentation.examine=3 +highlight.indentation.guides=1 +caret.fore=#FF0000 +#caret.additional.blinks=0 +caret.width=3 +caret.line.back=#222222 +calltip.back=#FFF0FE + +# Internationalisation +# Japanese input code page 932 and ShiftJIS character set 128 +#code.page=932 +#character.set=128 +# Unicode +#code.page=65001 +code.page=0 +#character.set=204 +# Required for Unicode to work on GTK+: +#LC_CTYPE=en_US.UTF-8 +if PLAT_GTK + output.code.page=65001 +if PLAT_MAC + output.code.page=65001 + +# Export +#export.keep.ext=1 +export.html.wysiwyg=1 +#export.html.tabs=1 +#export.html.folding=1 +export.html.styleused=1 +export.html.title.fullpath=1 +#export.rtf.tabs=1 +#export.rtf.font.face=Arial +#export.rtf.font.size=9 +#export.rtf.tabsize=8 +#export.rtf.wysiwyg=0 +#export.tex.title.fullpath=1 +# Magnification (added to default screen font size) +export.pdf.magnification=0 +# Font: Courier, Helvetica or Times (Courier line-wraps) +export.pdf.font=Courier +# Page size (in points): width, height +# E.g. Letter 612,792; A4 595,842; maximum 14400,14400 +export.pdf.pagesize=595,842 +# Margins (in points): left, right, top, bottom +export.pdf.margins=56,28,28,28 +export.xml.collapse.spaces=1 +export.xml.collapse.lines=1 + +if PLAT_WIN + font.base=font:Lucida Console,size:10 + font.small=font:Lucida Console,size:10 + font.comment=font:Lucida Console,size:10 + font.code.comment.box=$(font.comment) + font.code.comment.line=$(font.comment) + font.code.comment.doc=$(font.comment) + font.code.comment.nested=$(font.comment) + font.text=font:Lucida Console,size:10 + font.text.comment=font:Lucida Console,size:10 + font.embedded.base=font:Lucida Console,size:10 + font.embedded.comment=font:Lucida Console,size:10 + font.monospace=font:Lucida Console,size:10 + font.vbs=font:Lucida Sans Unicode,size:10 +if PLAT_GTK + font.base=font:Bitstream Vera Sans Mono,size:10 + font.small=font:Bitstream Vera Sans Mono,size:10 + font.comment=font:Bitstream Vera Sans Mono,size:10 + font.code.comment.box=$(font.comment) + font.code.comment.line=$(font.comment) + font.code.comment.doc=$(font.comment) + font.code.comment.nested=$(font.comment) + font.text=font:Bitstream Vera Sans Mono,size:10 + font.text.comment=font:Bitstream Vera Sans Mono,size:10 + font.embedded.base=font:Bitstream Vera Sans Mono,size:10 + font.embedded.comment=font:Bitstream Vera Sans Mono,size:10 + font.monospace=font:Bitstream Vera Sans Mono,size:10 + font.vbs=font:Bitstream Vera Sans Mono,size:10 +if PLAT_MAC + font.base=font:Verdana,size:12 + font.small=font:Verdana,size:10 + font.comment=font:Georgia,size:13 + font.code.comment.box=$(font.comment) + font.code.comment.line=$(font.comment) + font.code.comment.doc=$(font.comment) + font.code.comment.nested=$(font.comment) + font.text=font:Times New Roman,size:13 + font.text.comment=font:Verdana,size:11 + font.embedded.base=font:Verdana,size:11 + font.embedded.comment=font:Comic Sans MS,size:10 + font.monospace=font:Courier New,size:12 + font.vbs=font:Lucida Sans Unicode,size:12 + +font.js=$(font.comment) + +# Give symbolic names to the set of colours used in the standard styles. +colour.code.comment.box=fore:#00FF00 +colour.code.comment.line=fore:#00FF00 +colour.code.comment.doc=fore:#3F703F +colour.code.comment.nested=fore:#A0C0A0 +colour.text.comment=fore:#0000FF,back:#FFFFFF +colour.other.comment=fore:#00FF00 +colour.embedded.comment=back:#E0EEFF +colour.embedded.js=back:#F0F0FF +colour.notused=back:#FF0000 +#couleur des nombres +colour.number=fore:#FF00FF +#couleur des instructions du langage +colour.keyword=fore:#FF0000 +#couleur chaînes entre guillemets +colour.string=fore:#00FFFF +colour.char=fore:#7F7F7F +colour.operator=fore:#00FF00 +colour.preproc=fore:#FF7F00 +colour.error=fore:#FFFF00,back:#FF0000 + +# Global default styles for all languages +# Default style, black background +style.*.32=back:#000000,fore:#FFFFFF,font:Lucida Console,size:10 +# Line number +style.*.33=back:#404040,$(font.base)) +# Brace highlight +style.*.34=back:#222222,fore:#8080FF,bold +# Brace incomplete highlight +style.*.35=back:#222222,fore:#FF0000,bold +# Control characters +style.*.36= +# Indentation guides +style.*.37=fore:#C0C0C0,back:#FFFFFF + + +# Error list styles + +style.errorlist.32=fore:#B0B000,$(font.small) +# Default +style.errorlist.0=fore:#FFFFFF +# Microsoft Error +style.errorlist.3=fore:#0080FF +# command or return status +style.errorlist.4=fore:#FF00FF + +# Text matched with find in files and message part of GCC errors +style.errorlist.21=fore:#FF0000 + +# Printing - only works on Windows +if PLAT_WIN + #print.colour.mode=1 + print.magnification=-1 + # Setup: left, right, top, bottom margins, in local units: + # hundredths of millimeters or thousandths of inches + print.margins=2000,1000,1000,1000 + # Header/footer: + # && = &; &p = current page + # &f = file name; &F = full path + # &d = file date; &D = current date + # &t = file time; &T = full time + print.header.format=$(FileNameExt) — Printed on $(CurrentDate), $(CurrentTime) — Page $(CurrentPage) + print.footer.format=$(FilePath) — File date: $(FileDate) — File time: $(FileTime) + # Header/footer style + print.header.style=font:Arial,size:12,bold + print.footer.style=font:Arial Narrow,size:10,italics + + diff --git a/config/Select.bat b/config/Select.bat index 1f5416f..e058f3e 100644 --- a/config/Select.bat +++ b/config/Select.bat @@ -19,6 +19,7 @@ @echo 7 CHIPSTICK_FR2433 @echo 8 MSP_EXP430FR2355 @echo 9 LP_MSP430FR2476 + @set /p choice=your choice: @if %choice% == 1 set template=MSP_EXP430FR5739 diff --git a/config/Send b/config/Send new file mode 100644 index 0000000..ebd4361 --- /dev/null +++ b/config/Send @@ -0,0 +1,14 @@ +#!/bin/bash + +echo $1 +echo $2 +echo $3 + +#gema -nobackup -line -t '\r\n=\n' -f ../inc/$2.pat $1.f $FF/MSP430-FORTH/$1.4th +gema -nobackup -line -t '\r\n=\n' -f ../inc/$2.pat $1.f $1.4th +gema -line -t '\n=\r\n' ../MSP430-FORTH/$1.4th ../MSP430-FORTH/LAST.4th +#rm ../MSP430-FORTH/$1.4th + + +cat LAST.4th > /dev/ttyUSB0 +#cp LAST.4th /dev/ttyUSB0 diff --git a/config/SendFile.ttl b/config/SendFile.ttl index eb4e62e..84cf92a 100644 --- a/config/SendFile.ttl +++ b/config/SendFile.ttl @@ -22,12 +22,13 @@ showtt 0 ; close teraterm windows ; DEVICE ID TEST ; ============== -sendln 'CODE ?ID'; CODE ?ID -sendln 'CMP #0,R14 0<> IF SUB &$1A04,R14 THEN'; CMP #0,TOS 0<> IF SUB &DEVICEID,TOS THEN -sendln 'COLON '; COLON -sendln '$1B EMIT $63 EMIT'; $1B EMIT $63 EMIT \ send 'ESC c' (clear screen) -sendln 'CR ABORT" Device'39's ID mismatch!" ' ; CR ABORT" Device's ID mismatch!" -sendln 'PWR_STATE ;' ; PWR_STATE ; +sendln 'CODE ?ID' ; CODE ?ID +sendln 'CMP #0,R14 0<> IF SUB &$1A04,R14 THEN' ; CMP #0,TOS 0<> IF SUB &DEVICEID,TOS THEN +sendln 'COLON ' ; COLON +sendln '$1B EMIT $63 EMIT' ; $1B EMIT $63 EMIT \ send 'ESC c' (clear screen) +;sendln '13 EMIT $10 EMIT' ; CR +sendln ' ABORT" Device'39's ID mismatch!" ' ; ABORT" Device's ID mismatch!" +sendln 'RST_RET ;' ; RST_RET ; sendln param5 ' ?ID NOECHO' ; send: %deviceID% ?ID NOECHO diff --git a/config/SendSource b/config/SendSource index 936d0a6..a5fd450 100644 --- a/config/SendSource +++ b/config/SendSource @@ -1,14 +1,13 @@ -#!/bin/bash - echo $1 echo $2 echo $3 -#gema -nobackup -line -t '\r\n=\n' -f $FF/inc/$2.pat $1.f $FF/MSP430-FORTH/$1.4th -gema -nobackup -line -t '\r\n=\n' -f $FF/inc/$2.pat $1.f $1.4th -gema -line -t '\n=\r\n' $FF/MSP430-FORTH/$1.4th $FF/MSP430-FORTH/LAST.4th -#rm $FF/MSP430-FORTH/$1.4th +#gema -nobackup -line -t '\r\n=\n' -f ../inc/$2.pat $1.f $FF/MSP430-FORTH/$1.4th +gema -nobackup -line -t '\r\n=\n' -f ../inc/$2.pat $1.f ./LAST.4th +gema -line -t '\n=\r\n' ./LAST.4th $1.4th +rm ./LAST.4th -cat LAST.4th > /dev/ttyUSB0 +wine "c:\Program Files (x86)\teraterm\ttermpro.exe /V ..\config\SendFile.ttl $1.4TH /C $3 " +#cat $1.4th > /dev/ttyUSB0 #cp LAST.4th /dev/ttyUSB0 diff --git a/config/SendSource.bat b/config/SendSource.bat index 6f711f6..9466caa 100644 --- a/config/SendSource.bat +++ b/config/SendSource.bat @@ -2,7 +2,7 @@ ::used by SendSourceFileToTarget.bat or by scite editor Tools menu ::echo %2 -::echo %~d1\inc\%~n2.pat +::echo %~dp1..\inc\%~n2.pat @ECHO OFF @@ -33,8 +33,8 @@ echo %~dpn1.f not found! goto badend ) -IF NOT EXIST %~d1\inc\%~n2.pat ( -echo %~d1\inc\%~n2.pat not found! +IF NOT EXIST %~dp1..\inc\%~n2.pat ( +echo %~dp1..\inc\%~n2.pat not found! goto badend ) @@ -51,8 +51,8 @@ exit :preprocessF -@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~d1\inc\%~n2.pat %~dpn1.f %~dpn1.4TH -@call %~d1\config\Select.bat SelectDeviceId %~d1\inc\%~n2.pat +@%~d1\prog\gema.exe -nobackup -line -t '-\r\n=\r\n' -f %~dp1..\inc\%~n2.pat %~dpn1.f %~dpn1.4TH +@call %~d1\config\Select.bat SelectDeviceId %~dp1..\inc\%~n2.pat :DownloadF @taskkill /F /IM ttermpro.exe 1> NUL 2>&1 @@ -65,7 +65,10 @@ exit @"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %3 %deviceid% :EndF -@MOVE "%~dpn1.4TH" "%~dp1\LAST.4TH" > NUL +@MOVE "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL +call %~d1\config\Select.bat SelectDevice %~dp1..\inc\%~n2.pat +if not exist %~dp1SD_%device:~3% MD %~dp1SD_%device:~3% > NUL +COPY /y %~dp1LAST.4TH %~dp1SD_%device:~3%\%~n1.4TH > NUL exit @@ -110,6 +113,6 @@ goto badend @"C:\Program Files (x86)\teraterm\ttpmacro.exe" /V %~d1\config\SendFile.ttl %~dpn1.4TH /C %2 0 :End4th -@COPY "%~dpn1.4TH" "%~dp1\LAST.4TH" > NUL +@COPY "%~dpn1.4TH" "%~dp1LAST.4TH" > NUL exit diff --git a/config/SendSourceFileToTarget.bat b/config/SendSourceFileToTarget.bat index a149d20..0f61f75 100644 --- a/config/SendSourceFileToTarget.bat +++ b/config/SendSourceFileToTarget.bat @@ -16,7 +16,7 @@ exit call %~d1\config\Select.bat SelectTemplate -start %~d1\config\SendSource.bat %1 %~d1\inc\%template% ECHO +start %~d1\config\SendSource.bat %1 %~dp1..\inc\%template% ECHO ::PAUSE > NUL exit diff --git a/config/SendToSD.ttl b/config/SendToSD.ttl index f270f93..9fbff3a 100644 --- a/config/SendToSD.ttl +++ b/config/SendToSD.ttl @@ -23,16 +23,18 @@ showtt 0 ; close teraterm windows ; DEVICE ID TEST ; ============== -sendln 'CODE ?ID'; CODE ?ID -sendln 'CMP #0,R14 0<> IF SUB &$1A04,R14 THEN'; CMP #0,TOS 0<> IF SUB &DEVICEID,TOS THEN -sendln 'COLON '; COLON -;sendln '$1B EMIT $63 EMIT'; $1B EMIT $63 EMIT \ send 'ESC c' (clear screen) -sendln 'CR ABORT" Device'39's ID mismatch!" ' ; CR ABORT" Device's ID mismatch!" -sendln 'PWR_STATE ;' ; PWR_STATE ; +sendln 'CODE ?ID' ; CODE ?ID +sendln 'CMP #0,R14 0<> IF SUB &$1A04,R14 THEN' ; CMP #0,TOS 0<> IF SUB &DEVICEID,TOS THEN +sendln 'COLON ' ; COLON +sendln '$1B EMIT $63 EMIT' ; $1B EMIT $63 EMIT \ send 'ESC c' (clear screen) +;sendln '13 EMIT $10 EMIT' ; CR +sendln ' ABORT" Device'39's ID mismatch!" ' ; ABORT" Device's ID mismatch!" +sendln 'RST_RET ;' ; RST_RET ; ;sendln param4 ' ?ID NOECHO' ; send: %deviceID% ?ID sendln param4 ' ?ID ECHO' ; send: %deviceID% ?ID +sendln 'NOBOOT' ; sendln 'TERM2SD" ' inputstr '"' ; send to FastForth the command TERM2SD" \file.4TH" ...with optionnal path added in inputbox uptime timestart ; starts chrono... diff --git a/config/UNIFLASH_prog.bat b/config/UNIFLASH_prog.bat new file mode 100644 index 0000000..59a4abf --- /dev/null +++ b/config/UNIFLASH_prog.bat @@ -0,0 +1,16 @@ +::@echo off + +@call %~d1\config\Select.bat SelectDevice %1 +@echo %device% programmation +C:\ti\uniflash_5.3.1\dslite.bat -c C:\ti\uniflash_5.3.1\deskdb\content\TICloudAgent\win\ccs_base\common\targetdb\devices\%device%.xml --flash --verify %~d1\binaries\%~n1.txt +@exit + +:: your git copy must be the root of a virtual drive + +:: %n1 = file filename (= target) to flash +:: -s : force update +:: -m : select SBW2 mode +:: -n %device% : device set from %n1 +:: -v : verify device +:: -w %~dpn1.txt : file to be flashed +:: -z [] : end of flasher behaviour diff --git a/config/asm.properties b/config/asm.properties index 9db7b78..45a4b61 100644 --- a/config/asm.properties +++ b/config/asm.properties @@ -105,39 +105,39 @@ style.asm.13=fore:#FFFFFF,back:#000000 # $(2) = extension, example : _8MHz if PLAT_WIN - command.name.0.*.asm=Assemble 1:[target] - command.0.*.asm=*\config\build.bat $(FileNameExt) $(1)$(2) + command.name.0.*.asm=Assemble 1:[target] + command.0.*.asm=*.\config\build.bat $(FileNameExt) $(1)$(2) - command.name.1.*.asm=FET Prog 1:[target] - command.1.*.asm=*\config\FET_prog.bat $(1)$(2) + command.name.1.*.asm=FET Prog 1:[target] + command.1.*.asm=*\config\FET_prog.bat $(1)$(2) # $(3) = "COMx" - command.name.2.*.asm=BSL Prog 1:[target] with 3:[COMx] - command.2.*.asm=*\config\BSL_prog.bat $(1)$(2) $(3) + command.name.2.*.asm=BSL Prog 1:[target] with 3:[COMx] + command.2.*.asm=*\config\BSL_prog.bat $(1)$(2) $(3) - command.name.3.*.asm=Assemble target CurrentSelection - command.3.*.asm=\config\build.bat $(FileNameExt) $(CurrentSelection) + command.name.3.*.asm=Assemble target CurrentSelection + command.3.*.asm=\config\build.bat $(FileNameExt) $(CurrentSelection) - command.name.4.*.asm=FET Prog target CurrentSelection - command.4.*.asm=\config\FET_prog.bat $(CurrentSelection) + command.name.4.*.asm=FET Prog target CurrentSelection + command.4.*.asm=\config\FET_prog.bat $(CurrentSelection) - command.name.5.*.asm=BSL Prog target CurrentSelection with 3:[COMx] - command.5.*.asm=*\config\BSL_prog.bat $(CurrentSelection) $(3) + command.name.5.*.asm=BSL Prog target CurrentSelection with 3:[COMx] + command.5.*.asm=*\config\BSL_prog.bat $(CurrentSelection) $(3) if PLAT_GTK # variable $FF = /home/thoorens/CloudStation/projets/msp430 is defined in my ~.profile # open first scite in a terminal to import $FF - command.name.0.*.asm=Assemble for 1:[target] - command.0.*.asm=*$FF/config/build $(FileNameExt) $(1)$(2) + command.name.0.*.asm=Assemble for 1:[target] + command.0.*.asm=*./config/build $(FileNameExt) $(1) - command.name.1.*.asm=FET Prog 1:[target] - command.1.*.asm=*$FF/config/prog $(1)$(2) + command.name.1.*.asm=FET Prog 1:[target] + command.1.*.asm=*./config/prog $(1)$(2) - command.name.2.*.asm=Assemble for target CurrentSelection - command.2.*.asm=$FF/config/build $(FileNameExt) $(CurrentSelection) + command.name.2.*.asm=Assemble for target CurrentSelection + command.2.*.asm=./config/build $(FileNameExt) $(CurrentSelection) - command.name.3.*.asm=FET Prog target CurrentSelection - command.3.*.asm=$FF/config/prog $(CurrentSelection) + command.name.3.*.asm=FET Prog target CurrentSelection + command.3.*.asm=./config/prog $(CurrentSelection) diff --git a/config/build b/config/build index d1a846e..84983f5 100644 --- a/config/build +++ b/config/build @@ -1,9 +1,6 @@ -#asl -i $FF/inc -L $(FilePath)$1 -o $FF/binaries/$2.p -asl -i $FF/inc -L $1 -o $FF/binaries/$2.p -#p2hex -F Intel $FF/binaries/$2.p -p2hex $FF/binaries/$2.p -#srec_cat $FF/binaries/$2.hex -output $FF/binaries/$2.txt -Texas_Instruments_TeXT -#srec_cat -contradictory-bytes=warning $FF/binaries/$2.hex -intel -output $FF/binaries/$2.txt -Texas_Instruments_TeXT -# rm $FF/binaries/$2.hex -rm $FF/binaries/$2.p - +asl -i ./inc -L $1 -o ./binaries/$2.p +p2hex ./binaries/$2.p ./binaries/$2.hex +#srec_cat -contradictory-bytes=warning ./binaries/$2.hex -Intel -output ./binaries/$2asm -HEX_Dump +srec_cat -contradictory-bytes=warning ./binaries/$2.hex -Intel -output ./binaries/$2.txt -Texas_Instruments_TeXT +rm ./binaries/$2.p +rm ./binaries/$2.hex diff --git a/config/build.bat b/config/build.bat index 34ae2ec..eb6c323 100644 --- a/config/build.bat +++ b/config/build.bat @@ -1,12 +1,12 @@ -@ECHO OFF -%~d1\prog\asw -q -L -i %~d1\inc %1 -o %~d1\binaries\%2.p -%~d1\prog\p2hex %~d1\binaries\%2.p -r 0x0000-0xffff -%~d1\prog\srec_cat -contradictory-bytes=warning %~d1\binaries\%2.hex -intel -output %~d1\binaries\%2.txt -ti-txt -del %~d1\binaries\%2.p -del %~d1\binaries\%2.hex +::@ECHO OFF +%~d1\prog\asw -x -q -L -i %~dp1inc %1 -o %~dp1binaries\%2.p +%~d1\prog\p2hex %~dp1binaries\%2.p -r 0x0000-0xffff +%~d1\prog\srec_cat -contradictory-bytes=warning %~dp1binaries\%2.hex -intel -output %~dp1binaries\%2.txt -ti-txt +del %~dp1binaries\%2.p +::del %~dp1binaries\%2.hex exit rem your git copy must be the root of a virtual drive rem %1 is the input file.asm -rem %2 is the target name, plus optional infos +rem %2 is the target name diff --git a/config/forth.properties b/config/forth.properties index e804e7e..bf6994c 100644 --- a/config/forth.properties +++ b/config/forth.properties @@ -26,8 +26,8 @@ comment.stream.end.forth= comment.box.start.forth= comment.box.middle.forth= comment.box.end.forth= -block.start.forth=\ -block.end.forth=\ +block.start.forth= +block.end.forth= # Forth styles # control keywords Forth @@ -39,22 +39,21 @@ again begin case do i j else endcase endof if loop +loop leave unloop of repeat keywords2.$(file.patterns.forth)=\ dup ?dup drop rot swap over @ ! 2@ 2! 2dup 2drop 2swap 2over nip r@ >r r> 2r@ 2>r 2r> \ sp@ sp! @ ! c@ c! s>d um/mod um* m* * fm/mod sm/rem rshift lshift invert 1+ 1- negate \ - (cr) (EMIT) (accept) (warm) is lit warm depth /mod mod \ - space spaces bl word char fill key? key abort */ 2* 2/ /mod cell+ cells char+ \ + is lit depth /mod mod \ + space spaces bl word char fill key? key abort */ 2* 2/ /mod cell+ cells char+ \ chars move abs hex decimal hold <# # #s #> sign or \ count type . u. dump (.") >number ' exit recurse here allot , \ c, branch 0branch ?branch align aligned create does> \ - variable constant defer definitions forth forget only also previous literal \ + variable constant defer definitions forth only also previous literal \ source evaluate word interpret quit >body execute find state base \ words accept emit cr type echo noecho min max true false \ - char [char] postpone ['] rst_here rst_state wipe pwr_here pwr_state \ - assembler close pad caps_on caps_off + char [char] postpone ['] rst_set rst_ret sys \ + assembler close pad # defwords keywords3.$(file.patterns.forth)=\ -code hdncode endcode : ; immediate ;noname codennm \ +code hdncode endcode : ; immediate :noname codennm \ lo2hi hi2lo colon \ -[if] [else] [then] [undefined] [defined] # MSP430 assembly words & MSP430_instructions keywords4.$(file.patterns.forth)=\ @@ -185,54 +184,54 @@ if PLAT_GTK # variable $FF = /media/jeanmi/DATA/CloudStation is defined in my ~.profile # open first scite in a terminal to import $FF command.name.0.*.f=preprocess file.f with 1:[target].pat then download file.4th without ECHO - command.0.*.f=*$FF/config/SendSource $(FileDir)/$(FileName) $(1) NOECHO + command.0.*.f=*../config/SendSource $(FileDir)/$(FileName) $(1) NOECHO command.name.1.*.f=preprocess file.f with 1:[target].pat then download file.4th with ECHO - command.1.*.f=*$FF/config/SendSource $(FileDir)/$(FileName) $(1) ECHO + command.1.*.f=*../config/SendSource $(FileDir)/$(FileName) $(1) ECHO command.name.2.*.f=preprocess file.f with 1:[target].pat then download file.4th HALFDUPLEX - command.2.*.f=*$FF/config/SendSource $(FileDir)/$(FileName) $(1) HALF + command.2.*.f=*../config/SendSource $(FileDir)/$(FileName) $(1) HALF command.name.3.*.f=preprocess file.f with 1:[target].pat then download file.4th to target SD_CARD - command.3.*.f=*$FF/config/CopyTo_SD_Card $(FileDir)/$(FileName) $(1) + command.3.*.f=*../config/CopyTo_SD_Card $(FileDir)/$(FileName) $(1) command.name.4.*.f=preprocess file.f with 1:[target].pat to LAST.4th (for debug) - command.4.*.f=*$FF/config/Preprocess $(FileDir)/$(FileName) $(1) + command.4.*.f=*../config/Preprocess $(FileDir)/$(FileName) $(1) command.name.5.*.f=preprocess file.f with for target CurrentSelection then download - command.5.*.f=$FF/config/SendSource $(FileDir)/$(FileName) $(CurrentSelection) + command.5.*.f=../config/SendSource $(FileDir)/$(FileName) $(CurrentSelection) command.name.6.*.f=preprocess file.f with for target CurrentSelection then download with ECHO - command.6.*.f=$FF/config/SendSource $(FileDir)/$(FileName) $(CurrentSelection) ECHO + command.6.*.f=../config/SendSource $(FileDir)/$(FileName) $(CurrentSelection) ECHO command.name.7.*.f=preprocess file.f with for target CurrentSelection then download file.4th to target SD_CARD - command.7.*.f=$FF/config/CopyTo_SD_Card $(FileDir)/$(FileName).f $(CurrentSelection) + command.7.*.f=../config/CopyTo_SD_Card $(FileDir)/$(FileName).f $(CurrentSelection) command.name.8.*.f=preprocess file.f with for target CurrentSelection to LAST.4th (for debug) - command.8.*.f=$FF/config/Preprocess $(FileDir)/$(FileName) $(CurrentSelection) + command.8.*.f=../config/Preprocess $(FileDir)/$(FileName) $(CurrentSelection) command.name.9.*.f=convert FORTH registers to TI's ones - command.9.*.f=gema -line -t -f $FF/inc/FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt) + command.9.*.f=gema -line -t -f ./inc/FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt) command.name.10.*.f=convert TI registers to FORTH's ones - command.10.*.f=gema -line -t -f $FF/inc/tiREGtoFastForth.pat $(FileNameExt) $(FileNameExt) + command.10.*.f=gema -line -t -f ./inc/tiREGtoFastForth.pat $(FileNameExt) $(FileNameExt) command.name.0.*.4th=send file.4th to target without ECHO - command.0.*.4th=$FF/config/msp430/SendSource $(FileDir)/$(FileName).4th NOECHO + command.0.*.4th=./config/msp430/SendSource $(FileDir)/$(FileName).4th NOECHO command.name.1.*.4th=send file.4th to target with ECHO - command.1.*.4th=$FF/config/msp430/SendSource $(FileDir)/$(FileName).4th ECHO + command.1.*.4th=./config/msp430/SendSource $(FileDir)/$(FileName).4th ECHO command.name.2.*.4th=send file.4th to target with HALFDUPLEX - command.2.*.4th=$FF/config/msp430/SendSource $(FileDir)/$(FileName).4th HALF + command.2.*.4th=./config/msp430/SendSource $(FileDir)/$(FileName).4th HALF command.name.3.*.4th=send file.4th to target SD_CARD - command.3.*.4th=$FF/config/CopyTo_SD_Card $(FileDir)/$(FileName).4th + command.3.*.4th=./config/CopyTo_SD_Card $(FileDir)/$(FileName).4th command.name.4.*.4th=convert TI registers to FORTH's ones - command.4.*.4th=gema -line -t -f $FF/inc/TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt) + command.4.*.4th=gema -line -t -f ./inc/TiREGtoFastForth.pat $(FileNameExt) $(FileNameExt) command.name.5.*.4th=convert FORTH registers to TI's ones - command.5.*.4th=gema -line -t -f $FF/inc/FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt) + command.5.*.4th=gema -line -t -f ./inc/FastForthREGtoTI.pat $(FileNameExt) $(FileNameExt) diff --git a/config/others.properties b/config/others.properties index abcfe9a..e7608ab 100644 --- a/config/others.properties +++ b/config/others.properties @@ -134,7 +134,7 @@ style.errorlist.2=fore:#800080 # Microsoft Error style.errorlist.3=fore:#808000 # command or return status -style.errorlist.4=fore:#0000FF +# style.errorlist.4=fore:#0000FF # Borland error and warning messages style.errorlist.5=fore:#B06000 # perl error and warning messages diff --git a/config/prog b/config/prog index b717595..edfb4b6 100644 --- a/config/prog +++ b/config/prog @@ -3,7 +3,8 @@ device=$1 if [ ${device:0:16} == "MSP_EXP430FR5739" ]; then device=MSP430FR5739 -elif [ ${device:0:16} == "MSP_EXP430FR5969" ]; then +#elif [ ${device:0:16} == "MSP_EXP430FR5969" ]; then +elif [ $device == "MSP_EXP430FR5969" ]; then device=MSP430FR5969 elif [ ${device:0:16} == "MSP_EXP430FR5994" ]; then device=MSP430FR5994 @@ -18,7 +19,8 @@ elif [ ${device:0:16} == "MSP_EXP430FR2433" ]; then elif [ ${device:0:16} == "MSP_EXP430FR2355" ]; then device=MSP430FR2355 fi -echo $device -echo $1 -/usr/local/MSPFlasher/MSP430Flasher -s -n $device -v -w "$FF/binaries/$1.hex" -z [RESET,VCC] +echo +echo target: $1, device: $device +echo +$HOME/ti/MSPFlasher_1.3.20/MSP430Flasher -s -n $device -v -w "./binaries/$1.txt" -z [RESET,VCC] diff --git a/config/target_MAIN.txt b/config/target_MAIN.txt new file mode 100644 index 0000000..c5f8093 --- /dev/null +++ b/config/target_MAIN.txt @@ -0,0 +1,16385 @@ +@4000 B0 12 44 41 12 D2 06 18 FB 3F 2F 83 8F 4E 00 00 +@4010 3E 4D 30 4D 8F 4E FE FF AF 4F FC FF 2F 82 2F 82 +@4020 8F 4E 02 00 7E 4D 8F 4D 00 00 0D 5E 1D B3 0D 63 +@4030 30 4D 2F 83 8F 4E 00 00 1E 42 C8 1D 30 4D 0B 4E +@4040 1C 4F 02 00 2E 4F 0A 43 35 40 20 00 0E 93 04 20 +@4050 05 11 0E 4C 0C 43 09 43 0A 9B 01 28 0A 8B 09 69 +@4060 08 68 15 83 07 30 0C 5C 0E 6E 0A 6A F5 2B 0A 8B +@4070 12 D3 F5 3F 35 40 B6 40 8F 4A 02 00 8F 49 00 00 +@4080 0E 48 30 41 82 4E C2 1D B2 4F C4 1D 82 43 C6 1D +@4090 3E 4F 30 4D 2F 82 8F 4E 02 00 3E 40 54 00 BF 40 +@40A0 3C 1D 00 00 AF 4F FE FF 2F 83 0D 3D 0E 93 3E 4F +@40B0 8F 21 2D 4D 30 4D 2F 83 8F 4E 00 00 3E 41 0D 12 +@40C0 3D 4E 30 4D 2F 83 8F 4E 00 00 3E 41 2E 4E 30 4D +@40D0 B0 12 56 41 3D 41 39 40 20 18 B2 49 C8 42 B2 49 +@40E0 4C 43 B2 49 28 43 B2 49 A0 40 31 49 34 49 35 49 +@40F0 36 49 37 49 B2 49 C0 1D B2 49 BE 1D B2 49 00 1C +@4100 82 43 BC 1D 30 40 62 4D 8F 93 02 00 02 20 2F 52 +@4110 BF 3F 28 43 B0 12 46 41 B0 12 D0 40 A4 44 AC 40 +@4120 42 41 66 43 1E 40 05 1B 5B 37 6D 40 92 43 0A 40 +@4130 02 18 C6 44 FA 45 92 43 1E 40 04 1B 5B 30 6D 00 +@4140 92 43 DE 48 48 43 A2 B3 EC 06 FD 27 C2 48 CE 06 +@4150 A2 B2 EC 06 FD 27 30 41 B2 D0 C0 07 C0 06 18 42 +@4160 02 18 08 11 38 D0 00 04 82 48 D4 06 F2 D0 03 00 +@4170 6A 02 92 C3 C0 06 A2 D2 EA 06 92 C3 30 01 30 41 +@4180 B0 12 58 41 84 12 1E 40 07 0D 0A 1B 5B 37 6D 40 +@4190 92 43 0A 40 02 18 C6 44 FA 45 0A 40 23 00 4A 43 +@41A0 FA 45 1E 40 19 46 61 73 74 46 6F 72 74 68 20 C2 +@41B0 A9 4A 2E 4D 2E 54 68 6F 6F 72 65 6E 73 20 92 43 +@41C0 0A 40 40 FF 32 40 BA 44 C4 45 1E 40 0A 62 79 74 +@41D0 65 73 20 66 72 65 65 00 B2 40 36 41 00 00 06 53 +@41E0 59 53 0E 93 CF 27 02 38 F0 41 CA 2F 82 4E 08 18 +@41F0 B0 12 56 41 F0 41 40 00 40 02 02 20 B2 43 08 18 +@4200 B2 40 F0 41 20 01 B2 D0 03 00 04 01 B2 D0 10 00 +@4210 00 01 B2 40 80 5A 5C 01 31 40 E0 1C 3F 40 80 1C +@4220 B2 D3 06 02 B2 40 FC FF 02 02 B2 43 26 02 B2 D3 +@4230 22 02 B2 43 42 02 B2 D3 46 02 B2 43 62 02 B2 D3 +@4240 66 02 F2 43 26 03 F2 D3 22 03 F2 40 A5 00 41 01 +@4250 F2 40 10 00 40 01 D2 43 41 01 F2 40 A5 00 61 01 +@4260 B2 40 48 00 62 01 82 43 66 01 B2 40 33 00 64 01 +@4270 D2 43 61 01 39 40 40 00 18 42 00 18 18 83 FE 23 +@4280 19 83 FA 23 F2 D0 10 00 2A 03 F2 40 A5 00 A1 04 +@4290 F2 C0 40 00 A2 04 B2 42 B0 01 39 40 00 10 29 83 +@42A0 89 43 00 1C FC 23 1E 42 9E 01 19 E2 08 18 03 24 +@42B0 0E 49 82 43 08 18 B0 12 D0 40 80 41 00 00 0C 41 +@42C0 43 43 45 50 54 00 30 40 CA 42 0A 4E 2E 4F 0A 5E +@42D0 3B 40 0A 00 3C 40 20 00 3D 15 92 3E 21 52 A2 C2 +@42E0 EC 06 B2 B0 10 00 C0 06 8B 22 3A 17 92 B3 EC 06 +@42F0 FD 27 58 42 CC 06 48 9B 0E 24 48 9C 06 2C 78 92 +@4300 F5 23 2E 9F F3 27 1E 83 F1 3F 0E 9A EF 2F CE 48 +@4310 00 00 1E 53 EB 3F 3E 8F B0 12 50 41 08 4C 19 3C +@4320 00 00 06 4B 45 59 30 40 2A 43 58 43 B0 12 46 41 +@4330 2F 83 8F 4E 00 00 92 B3 EC 06 FD 27 1E 42 CC 06 +@4340 30 4D 00 00 08 45 4D 49 54 00 30 40 4E 43 08 4E +@4350 3E 4F A2 B3 EC 06 FD 27 C2 48 CE 06 30 4D 44 43 +@4360 08 45 43 48 4F 00 B2 40 C2 48 58 43 38 40 05 00 +@4370 B0 12 46 41 30 4D 00 00 0C 4E 4F 45 43 48 4F 00 +@4380 B2 40 30 4D 58 43 28 42 F3 3F 00 00 08 54 59 50 +@4390 45 00 0D 12 3D 40 A2 43 29 4F 8F 4E 00 00 7E 49 +@43A0 D4 3F A4 43 2D 83 2F 83 5E 83 F7 23 3D 41 2F 53 +@43B0 3E 4F 30 4D 86 12 20 00 0C 4E 38 4F 3C 9F 39 4F +@43C0 3E 4F 77 22 F9 98 00 00 74 22 19 53 1C 83 FA 23 +@43D0 2D 53 30 4D 2F 53 3E 4F 1E 83 6B 22 9C 24 22 43 +@43E0 0D 5B 45 4C 53 45 5D 00 0D 12 84 12 0A 40 00 00 +@43F0 BE 44 B4 43 0A 46 C0 48 B0 40 30 44 14 40 06 5B +@4000 54 48 45 4E 5D 00 B8 43 0E 44 D4 43 F2 43 14 40 +@4000 06 5B 45 4C 53 45 5D 00 B8 43 20 44 D4 43 F0 43 +@4000 1E 40 04 5B 49 46 5D 00 B8 43 F2 43 B2 40 F0 43 +@4000 AE 43 1E 40 05 0D 6B 6F 20 0A 92 43 94 40 84 40 +@4000 B2 40 F2 43 E0 43 0D 5B 54 48 45 4E 5D 00 30 4D +@4000 46 44 09 5B 49 46 5D 00 0E 93 3E 4F C5 27 30 4D +@4000 52 44 13 5B 44 45 46 49 4E 45 44 5D 0D 12 84 12 +@4000 B4 43 0A 46 72 46 12 48 84 45 62 44 17 5B 55 4E +@4000 44 45 46 49 4E 45 44 5D 0D 12 84 12 B4 43 0A 46 +@4000 72 46 12 48 D6 44 84 45 3F 12 2F 83 8F 4E 00 00 +@4000 3E 41 30 4D 8F 4E FE FF 2F 83 30 4D 8F 4E FE FF +@4000 3E 40 80 1C 0E 8F 0E 11 F7 3F 3E 8F 3E E3 1E 53 +@4000 30 4D 00 00 02 40 2E 4E 30 4D BE 42 02 21 BE 4F +@4000 00 00 3E 4F 30 4D 1E 83 0E 7E 30 4D 0E 5E 0E 7E +@4000 3E E3 30 4D 3E 8F 01 28 0E F3 30 4D DE 41 05 53 +@4000 22 00 82 43 C0 1D 0D 12 84 12 0A 40 1E 40 70 48 +@4000 0A 40 22 00 0A 46 08 45 B2 40 20 00 C0 1D 1A 53 +@4000 1A B3 82 6A C8 1D 3E 4F 3D 41 30 4D 78 43 05 2E +@4000 22 00 0D 12 84 12 F2 44 0A 40 92 43 70 48 84 45 +@4000 00 00 04 3C 23 00 B2 40 B2 1D B2 1D 30 4D EE 44 +@4000 02 23 1B 42 BE 1D 2C 4F 2F 83 B0 12 46 40 BF 4F +@4000 00 00 7A 90 0A 00 02 28 7A 50 07 00 7A 50 30 00 +@4000 92 83 B2 1D 18 42 B2 1D C8 4A 00 00 30 4D 40 45 +@4000 04 23 53 00 0D 12 84 12 42 45 7C 45 2D 83 09 DE +@4000 09 93 E1 23 3D 41 30 4D 70 45 04 23 3E 00 9F 42 +@4000 B2 1D 00 00 3E 40 B2 1D 2E 8F 30 4D 00 00 08 48 +@4000 4F 4C 44 00 4A 4E 3E 4F DB 3F 8A 45 08 53 49 47 +@4000 4E 00 0E 93 3E 4F 7A 40 2D 00 D2 33 30 4D 60 43 +@4000 04 55 2E 00 08 43 2F 83 8F 4E 00 00 0E 48 0D 12 +@4000 0E 12 3E F3 06 34 BF E3 00 00 3E E3 9F 53 00 00 +@4000 0E 63 84 12 36 45 B4 43 A4 45 74 45 9A 44 B2 45 +@4000 8E 45 92 43 84 45 1E 45 02 2E 0E 93 E3 37 38 43 +@4000 E2 3F 00 00 08 57 4F 52 44 00 1B 42 C0 1D 3C 40 +@4000 C2 1D 39 4C 38 4C 09 58 38 5C 2A 4C 09 98 1B 24 +@4000 7E 98 FC 27 18 83 F8 90 27 00 00 00 04 20 E8 98 +@4000 02 00 01 20 0B 43 CA 4C 00 00 09 98 0C 24 7C 48 +@4000 4E 9C 09 24 1A 53 7C 90 61 00 F5 2B 7C 90 7B 00 +@4000 F2 2F 4C 8B F0 3F 18 82 C4 1D 82 48 C6 1D 1E 42 +@4000 C8 1D 0A 8E CE 4A 00 00 30 4D 00 00 08 46 49 4E +@4000 44 00 2F 83 0C 4E 3B 40 CC 1D 3E 4B 0E 93 1E 24 +@4000 58 4C 01 00 78 F0 0F 00 08 58 0E 58 2E 53 1E 4E +@4000 FE FF 0E 93 F2 27 09 4E 78 49 48 11 68 9C F7 23 +@4000 0A 4C FA 99 01 00 F3 23 1A 53 58 83 FA 23 19 B3 +@4000 09 63 0C 49 6E 4E 1E F3 01 20 1E 83 8F 4C 00 00 +@4000 30 4D F8 45 0E 3E 4E 55 4D 42 45 52 1B 42 BE 1D +@4000 3C 4F 38 4F 29 4F 2F 82 82 4B C0 04 6A 4C 7A 80 +@4000 3A 00 03 28 7A 80 07 00 12 28 7A 50 0A 00 0A 9B +@4000 22 C3 0D 2C 82 49 E0 04 82 48 E2 04 19 42 E4 04 +@4000 18 42 E6 04 09 5A 08 63 1C 53 1E 83 E7 23 8F 4C +@4000 00 00 8F 48 02 00 8F 49 04 00 30 4D 32 C0 00 02 +@4000 3F 82 8F 4E 06 00 08 43 09 43 1B 42 BE 1D 0C 4E +@4000 0E 43 1E 15 3D 40 78 47 7E 4C 6A 4C 7A 80 2D 00 +@4000 14 24 CA 2F 2B 43 7A 52 12 24 3B 52 6A 53 0F 24 +@4000 3B 40 10 00 5A 93 0B 24 6A 92 3F 20 5B 4C 01 00 +@4000 8F 4B 04 00 EC 9C 02 00 38 3C B1 43 02 00 1E 83 +@4000 FC 9C 00 00 E2 23 B0 27 7A 47 2F 24 2D 83 6A 4C +@4000 7A 90 5F 00 C1 27 32 B0 00 02 27 20 32 D0 00 02 +@4000 7A 80 2E 00 B9 27 6A 53 20 20 0A 4E 09 43 8F 49 +@4000 02 00 5A 83 09 4A 09 5C 69 49 79 80 3A 00 03 28 +@4000 79 80 07 00 0C 28 79 50 0A 00 09 9B 08 2C 8F 49 +@4000 00 00 0E 4B 2C 15 B0 12 3E 40 2A 17 E8 3F 9F 4F +@4000 04 00 02 00 AF 4F 04 00 4A 93 1D 17 06 24 32 C0 +@4000 00 02 3F 50 06 00 0E F3 30 4D 2F 53 9F 4F 02 00 +@4000 04 00 BF 4F 00 00 3E E3 09 20 3E E3 BF E3 02 00 +@4000 BF E3 00 00 9F 53 02 00 8F 63 00 00 32 B0 00 02 +@4000 01 20 2F 53 30 4D 32 45 03 5C 92 42 C2 1D C6 1D +@4000 30 4D 0D 12 84 12 84 40 B4 43 0A 46 B0 40 4A 49 +@4000 72 46 34 48 0A 4E 3E 4F 3D 40 4E 48 6F 27 3D 40 +@4000 28 48 1A E2 BC 1D 14 24 0E 12 3E 4F 30 41 50 48 +@4000 3E 4F 3D 40 28 48 19 20 DE 53 00 00 68 4E 08 5E +@4000 F8 40 3F 00 00 00 3D 40 26 4A 2A 3C 18 48 02 2C +@4000 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 3E 4F 30 4D +@4000 6E 48 0F 4C 49 54 45 52 41 4C 82 93 BC 1D 0D 24 +@4000 09 4E 1A 42 C8 1D A2 52 C8 1D BA 40 0A 40 00 00 +@4000 8A 49 02 00 3E 4F 32 B0 00 02 32 C0 00 02 03 24 +@4000 8A 4E 02 00 EE 3F 30 4D AC 45 0A 43 4F 55 4E 54 +@4000 2F 83 7A 4E 8F 4E 00 00 0E 4A 3E F3 30 4D CC 44 +@4000 0A 41 4C 4C 4F 54 82 5E C8 1D 3E 4F 30 4D 3F 40 +@4000 80 1C 0E 43 84 12 1E 40 02 0D 0A 00 92 43 94 40 +@4000 22 48 AC 44 DC 44 1E 40 0B 73 74 61 63 6B 20 65 +@4000 6D 70 74 79 08 41 32 40 0A 40 40 FF E4 44 1E 40 +@4000 09 46 52 41 4D 20 66 75 6C 6C 08 41 B2 40 E6 48 +@4000 D0 48 0D 41 42 4F 52 54 22 00 0D 12 84 12 F2 44 +@4000 0A 40 08 41 70 48 84 45 04 46 02 27 0D 12 84 12 +@4000 B4 43 0A 46 72 46 B0 40 4C 49 16 45 58 48 7C 44 +@4000 07 5B 27 5D 0D 12 84 12 3C 49 0A 40 0A 40 70 48 +@4000 70 48 84 45 50 49 03 5B 82 43 BC 1D 30 4D 00 00 +@4000 02 5D B2 43 BC 1D 30 4D C4 44 11 50 4F 53 54 50 +@4000 4F 4E 45 00 0D 12 84 12 B4 43 0A 46 72 46 B0 40 +@4000 4C 49 DC 44 AC 40 A4 49 0A 40 0A 40 70 48 70 48 +@4000 0A 40 70 48 70 48 84 45 00 00 02 3A 30 12 FA 49 +@4000 92 B3 C8 1D A2 63 C8 1D 0D 12 84 12 B4 43 0A 46 +@4000 C2 49 3D 41 5A D3 5A 53 0A 5E 19 42 CA 1D 08 4E +@4000 5E 4E 01 00 3E F0 0F 00 0E 5E 09 5E 3E 4F E8 58 +@4000 00 00 82 48 B4 1D 82 49 B6 1D 82 4A B8 1D 82 4F +@4000 BA 1D 2A 52 82 4A C8 1D 30 41 BA 40 0D 12 FC FF +@4000 BA 40 84 12 FE FF B2 43 BC 1D 30 4D 82 9F BA 1D +@4000 9F 25 84 12 1E 40 0F 73 74 61 63 6B 20 6D 69 73 +@4000 6D 61 74 63 68 21 12 41 66 49 03 3B 82 93 BC 1D +@4000 F4 26 0D 12 84 12 0A 40 84 45 70 48 0C 4A 68 49 +@4000 84 45 00 00 12 49 4D 4D 45 44 49 41 54 45 18 42 +@4000 B4 1D D8 D3 00 00 30 4D BA 48 0C 43 52 45 41 54 +@4000 45 00 B0 12 B0 49 BA 40 86 12 FC FF 8A 4A FE FF +@4000 73 3D 8C 43 0A 44 4F 45 53 3E 1A 42 B8 1D BA 40 +@4000 85 12 00 00 8A 4D 02 00 3D 41 30 4D AA 49 0E 3A +@4000 4E 4F 4E 41 4D 45 30 12 FA 49 2F 83 8F 4E 00 00 +@4000 1A 42 C8 1D 1A B3 0A 63 0E 4A 39 40 12 02 08 49 +@4000 98 3F 74 4A 0A 44 45 46 45 52 B0 12 B0 49 BA 40 +@4000 30 40 FC FF BA 40 56 4A FE FF 46 3D 44 4A 05 49 +@4000 53 00 0D 12 82 93 BC 1D 08 20 84 12 3C 49 E0 4A +@4000 3D 41 BE 4F 02 00 3E 4F 30 4D 84 12 54 49 0A 40 +@4000 E2 4A 70 48 84 45 5A 4A 08 43 4F 44 45 00 B0 12 +@4000 B0 49 A2 82 C8 1D 0D 12 84 12 4A 4C 1C 4C 84 45 +@4000 9E 45 0E 48 44 4E 43 4F 44 45 B2 40 20 4C CA 1D +@4000 EE 3F 00 00 0E 45 4E 44 43 4F 44 45 0D 12 84 12 +@4000 0C 4A 6A 4C 98 4C 84 45 F8 4A 0E 43 4F 44 45 4E +@4000 4E 4D 30 12 02 4B A9 3F 00 00 0A 43 4F 4C 4F 4E +@4000 1A 42 C8 1D BA 40 0D 12 00 00 BA 40 84 12 02 00 +@4000 A2 52 C8 1D B2 43 BC 1D 92 42 CE 1D CA 1D 7D 3C +@4000 00 00 0A 4C 4F 32 48 49 A2 83 C8 1D 1A 42 C8 1D +@4000 EC 3F 12 4B 0B 48 49 32 4C 4F A2 53 C8 1D 1A 42 +@4000 C8 1D 8A 4A FE FF 82 43 BC 1D B5 3F 6C 46 14 56 +@4000 4F 43 41 42 55 4C 41 52 59 00 0D 12 84 12 62 4A +@4000 B2 4B 39 40 10 00 0A 59 0A 59 82 4A C8 1D 2A 83 +@4000 8A 43 00 00 19 83 FB 23 84 12 32 40 0A 40 DC 1D +@4000 A4 44 C6 44 70 48 CE 44 7A 4A 0A 40 CC 1D CE 44 +@4000 84 45 9E 4B 0A 46 4F 52 54 48 85 12 DA 4B 60 4C +@4000 44 4C CA 4C 3A 4B 8C 4C C0 45 E4 4B 3A 49 84 4B +@4000 CE 4A 8E 4A 2A 4A 82 48 1E 4D C4 46 7E 4C 00 00 +@4000 22 49 12 41 53 53 45 4D 42 4C 45 52 85 12 DA 4B +@4000 CC 53 50 52 B0 53 78 51 D4 51 22 52 FE 52 0A 53 +@4000 9A 50 BE 51 00 00 00 00 72 4B 8A 4F 00 00 26 53 +@4000 0E 4C 12 4C 08 41 4C 53 4F 00 38 40 06 00 39 40 +@4000 D6 1D A9 49 02 00 29 83 18 83 FB 23 30 4D 7A 49 +@4000 10 50 52 45 56 49 4F 55 53 00 38 40 07 00 39 40 +@4000 CE 1D B9 49 FC FF 18 83 FC 23 30 4D 00 00 08 4F +@4000 4E 4C 59 00 82 43 CE 1D 30 4D B4 4A 16 44 45 46 +@4000 49 4E 49 54 49 4F 4E 53 92 42 CC 1D CA 1D 30 4D +@4000 3B 40 0C 00 BA 49 00 00 2A 53 1B 83 FB 23 30 41 +@4000 00 00 0E 52 53 54 5F 53 45 54 39 40 C8 1D 3A 40 +@4000 38 18 B0 12 A0 4C 30 4D B2 4C 0E 52 53 54 5F 52 +@4000 45 54 39 40 38 18 2C 49 3A 40 C8 1D B0 12 A0 4C +@4000 1A 42 DC 1D 3B 40 10 00 09 4A 08 49 29 83 18 48 +@4000 FE FF 0C 98 FC 2B 89 48 00 00 1B 83 F6 23 2A 4A +@4000 0A 93 F0 23 30 4D 08 4D 09 4E 3A 40 38 18 B0 12 +@4000 A0 4C 0E 49 BE 12 3E 4F 3D 41 DB 3F 70 49 0C 4D +@4000 41 52 4B 45 52 00 B0 12 B0 49 BA 40 85 12 FC FF +@4000 BA 40 06 4D FE FF 28 83 82 48 C8 1D 39 40 C8 1D +@4000 B0 12 A0 4C BA 40 82 40 00 00 2A 53 82 4A C8 1D +@4000 18 42 B4 1D 19 42 B6 1D A8 49 FE FF 89 48 00 00 +@4000 30 4D 0E 93 B6 37 39 40 10 00 29 83 B9 43 80 FF +@4000 FC 23 B9 40 06 42 FE FF 29 83 B9 40 F0 41 FE FF +@4000 39 90 AE FF F9 23 39 40 10 18 B2 49 F2 41 B2 49 +@4000 D2 40 B2 49 02 40 B2 49 82 41 B2 49 BC FF B2 49 +@4000 38 18 A2 49 3A 18 B2 49 3C 18 82 43 3E 18 A2 49 +@4000 4E 18 8F 3F 92 83 C6 1D 3E 40 28 00 2D 15 0E 12 +@4000 12 12 C6 1D 84 12 0A 46 72 46 D6 44 AC 40 D8 4D +@4000 1C 47 AC 40 FC 4D F6 4D DA 4D 3C 4E 3C 80 87 12 +@4000 0A 24 1C 53 02 20 2E 4E 06 3C 3E 90 06 4D 02 20 +@4000 3E 50 18 00 2E 83 21 52 2B 17 30 41 FE 4D B2 41 +@4000 C6 1D 3E 41 84 12 0A 40 2B 00 0A 46 72 46 D6 44 +@4000 AC 40 1A 4E 1C 47 AC 40 4C 49 98 44 0A 46 1C 47 +@4000 AC 40 4C 49 26 4E 3E 5F E7 3F B0 12 B4 4D 19 42 +@4000 C8 1D 89 4E 00 00 A2 53 C8 1D 3E 40 29 00 92 53 +@4000 C6 1D 2D 15 12 12 C6 1D 84 12 0A 46 1C 47 AC 40 +@4000 5E 4E 54 4E 21 53 3E 90 10 00 CE 2B 7C 2D 60 4E +@4000 B2 41 C6 1D C9 3F 03 20 B0 12 42 4E 43 3C 7A 90 +@4000 23 00 24 20 B0 12 BC 4D 3C 40 00 03 0E 93 1C 24 +@4000 3C 40 10 03 1E 93 18 24 3C 40 20 03 2E 93 14 24 +@4000 3C 40 20 02 2E 92 10 24 3C 40 30 02 3E 92 0C 24 +@4000 3C 40 30 03 3E 93 08 24 3C 40 30 00 19 42 C8 1D +@4000 A2 53 C8 1D 89 4E 00 00 3E 4F 30 4D 7A 90 26 00 +@4000 05 20 3C 40 10 02 B0 12 BC 4D F0 3F 7A 90 40 00 +@4000 14 20 3C 40 20 00 B0 12 3E 4E 0C 20 3C D0 10 00 +@4000 3E 40 2B 00 B0 12 42 4E 92 92 C2 1D C6 1D 02 24 +@4000 92 53 C6 1D 8E 10 0C 5E DF 3F 3C D0 10 00 B0 12 +@4000 2A 4E F2 3F 03 20 B0 12 42 4E F5 3F 7A 90 26 00 +@4000 03 20 3C D0 82 00 D7 3F 3C D0 80 00 B0 12 2A 4E +@4000 EA 3F 0C 43 1B 42 C8 1D A2 53 C8 1D 3A 40 20 00 +@4000 19 42 C6 1D 19 52 C4 1D 7A 99 FE 27 5A 49 FF FF +@4000 19 82 C4 1D 82 49 C6 1D 7A 90 52 00 30 4D 00 00 +@4000 08 52 45 54 49 00 0D 12 84 12 0A 40 00 13 70 48 +@4000 84 45 0A 40 2C 00 22 4F 66 4E B4 43 2C 4F 04 4F +@4000 72 4F 3D 41 2C DE 8B 4C 00 00 9E 3F 00 00 06 4D +@4000 4F 56 85 12 62 4F 00 40 7E 4F 0A 4D 4F 56 2E 42 +@4000 85 12 62 4F 40 40 00 00 06 41 44 44 85 12 62 4F +@4000 00 50 98 4F 0A 41 44 44 2E 42 85 12 62 4F 40 50 +@4000 A4 4F 08 41 44 44 43 00 85 12 62 4F 00 60 B2 4F +@4000 0C 41 44 44 43 2E 42 00 85 12 62 4F 40 60 4A 4B +@4000 08 53 55 42 43 00 85 12 62 4F 00 70 D0 4F 0C 53 +@4000 55 42 43 2E 42 00 85 12 62 4F 40 70 DE 4F 06 53 +@4000 55 42 85 12 62 4F 00 80 EE 4F 0A 53 55 42 2E 42 +@4000 85 12 62 4F 40 80 FA 4F 06 43 4D 50 85 12 62 4F +@4000 00 90 08 50 0A 43 4D 50 2E 42 85 12 62 4F 40 90 +@4000 00 00 08 44 41 44 44 00 85 12 62 4F 00 A0 22 50 +@4000 0C 44 41 44 44 2E 42 00 85 12 62 4F 40 A0 50 4F +@4000 06 42 49 54 85 12 62 4F 00 B0 40 50 0A 42 49 54 +@4000 2E 42 85 12 62 4F 40 B0 4C 50 06 42 49 43 85 12 +@4000 62 4F 00 C0 5A 50 0A 42 49 43 2E 42 85 12 62 4F +@4000 40 C0 66 50 06 42 49 53 85 12 62 4F 00 D0 74 50 +@4000 0A 42 49 53 2E 42 85 12 62 4F 40 D0 00 00 06 58 +@4000 4F 52 85 12 62 4F 00 E0 8E 50 0A 58 4F 52 2E 42 +@4000 85 12 62 4F 40 E0 C0 4F 06 41 4E 44 85 12 62 4F +@4000 00 F0 A8 50 0A 41 4E 44 2E 42 85 12 62 4F 40 F0 +@4000 B4 43 22 4F 66 4E C8 50 0A 4C 3C F0 70 00 8A 10 +@4000 3A F0 0F 00 0C DA 4D 3F 80 50 06 52 52 43 85 12 +@4000 C0 50 00 10 DA 50 0A 52 52 43 2E 42 85 12 C0 50 +@4000 40 10 14 50 08 53 57 50 42 00 85 12 C0 50 80 10 +@4000 E6 50 06 52 52 41 85 12 C0 50 00 11 02 51 0A 52 +@4000 52 41 2E 42 85 12 C0 50 40 11 F4 50 06 53 58 54 +@4000 85 12 C0 50 80 11 00 00 08 50 55 53 48 00 85 12 +@4000 C0 50 00 12 28 51 0C 50 55 53 48 2E 42 00 85 12 +@4000 C0 50 40 12 1C 51 08 43 41 4C 4C 00 85 12 C0 50 +@4000 80 12 1A 53 0E 4A 84 12 FA 45 1E 40 0D 6F 75 74 +@4000 20 6F 66 20 62 6F 75 6E 64 73 12 41 46 51 06 53 +@4000 3E 3D 86 12 00 38 6E 51 04 53 3C 00 86 12 00 34 +@4000 36 51 06 30 3E 3D 86 12 00 30 82 51 04 30 3C 00 +@4000 86 12 00 30 24 4B 04 55 3C 00 86 12 00 2C 96 51 +@4000 06 55 3E 3D 86 12 00 28 8C 51 06 30 3C 3E 86 12 +@4000 00 24 AA 51 04 30 3D 00 86 12 00 20 00 00 04 49 +@4000 46 00 1A 42 C8 1D 8A 4E 00 00 A2 53 C8 1D 0E 4A +@4000 30 4D 30 50 08 54 48 45 4E 00 1A 42 C8 1D 08 4E +@4000 3E 4F 09 48 29 53 0A 89 0A 11 3A 90 00 02 B2 2F +@4000 88 DA 00 00 30 4D A0 51 08 45 4C 53 45 00 1A 42 +@4000 C8 1D BA 40 00 3C 00 00 A2 53 C8 1D 2F 83 8F 4A +@4000 00 00 E3 3F 0E 51 0A 42 45 47 49 4E 30 40 32 40 +@4000 F8 51 0A 55 4E 54 49 4C 3A 4F 08 4E 3E 4F 19 42 +@4000 C8 1D 2A 83 0A 89 0A 11 3A 90 00 FE 8B 3B 3A F0 +@4000 FF 03 08 DA 89 48 00 00 A2 53 C8 1D 30 4D B4 50 +@4000 0A 41 47 41 49 4E 0A 4E 38 40 00 3C E7 3F 00 00 +@4000 0A 57 48 49 4C 45 0D 12 84 12 C2 51 98 44 84 45 +@4000 16 52 0C 52 45 50 45 41 54 00 0D 12 84 12 56 52 +@4000 DA 51 84 45 86 52 3D 41 08 4E 3E 4F 2A 48 B2 92 +@4000 C6 1D CB 2F 98 42 C8 1D 00 00 30 4D 72 52 06 42 +@4000 57 31 85 12 84 52 00 00 9E 52 06 42 57 32 85 12 +@4000 84 52 00 00 AA 52 06 42 57 33 85 12 84 52 00 00 +@4000 C2 52 3D 41 1A 42 C8 1D 28 4E 8E 43 00 00 B2 92 +@4000 C6 1D 86 2B BA 4F 00 00 A2 53 C8 1D 8E 4A 00 00 +@4000 3E 4F 30 4D 00 00 06 46 57 31 85 12 C0 52 00 00 +@4000 E6 52 06 46 57 32 85 12 C0 52 00 00 F2 52 06 46 +@4000 57 33 85 12 C0 52 00 00 60 52 08 47 4F 54 4F 00 +@4000 2F 83 8F 4E 00 00 3E 40 00 3C 0D 12 84 12 3C 49 +@4000 48 48 84 45 00 00 0A 3F 47 4F 54 4F 3E 90 00 30 +@4000 F4 27 3E E0 00 04 3E B0 00 10 EF 27 3E E0 00 08 +@4000 EC 3F 2C 4F 0A 40 2C 00 0A 46 1C 47 AC 40 4C 49 +@4000 B4 43 22 4F 04 4F 58 53 0A 4E 3E 4F 1A 83 F9 32 +@4000 29 4E 59 0E 0A 28 08 4C 59 0A 01 28 0C 8A 08 8A +@4000 38 90 10 00 EE 2E 5A 0E AD 3E 2A 92 EA 2E 8A 10 +@4000 5A 06 A8 3E B6 52 08 52 52 43 4D 00 85 12 42 53 +@4000 50 00 86 53 08 52 52 41 4D 00 85 12 42 53 50 01 +@4000 94 53 08 52 4C 41 4D 00 85 12 42 53 50 02 A2 53 +@4000 08 52 52 55 4D 00 85 12 42 53 50 03 B4 51 0A 50 +@4000 55 53 48 4D 85 12 42 53 00 15 BE 53 08 50 4F 50 +@4000 4D 00 85 12 42 53 00 17 FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@4000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +77 00 10 00 12 00 14 00 16 00 00 00 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 DC 42 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 +F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 F0 41 06 42 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +q diff --git a/forthMSP430FR.asm b/forthMSP430FR.asm index feb29b4..fd85791 100644 --- a/forthMSP430FR.asm +++ b/forthMSP430FR.asm @@ -1,9 +1,8 @@ -; -*- coding: utf-8 -*- ; ;------------------------------------------------------------------------------- -; Vingt fois sur le métier remettez votre ouvrage, +; Vingt fois sur le métier remettez votre ouvrage, ; Polissez-le sans cesse, et le repolissez, -; Ajoutez quelquefois, et souvent effacez. Boileau, L'Art poétique +; Ajoutez quelquefois, et souvent effacez. Boileau, L'Art poétique ;------------------------------------------------------------------------------- ;------------------------------------------------------------------------------- @@ -14,90 +13,68 @@ ;------------------------------------------------------------------------------- .listing purecode ; reduce listing to true conditionnal parts MACEXP_DFT noif ; reduce macros listing to true part - .PAGE 0 ; + .PAGE 0 ; listing without pagination ;------------------------------------------------------------------------------- -VER .equ "V308" ; FORTH version +VER .equ "V309" ; FORTH version ;=============================================================================== ; before assembling or programming you must set TARGET in scite param1 (SHIFT+F8) ; according to the selected (uncommented) TARGET below ;=============================================================================== - -;=============================================================================== -; FAST FORTH has a minimalistic footprint to enable its use from 8k FRAM devices -; kernel size below are for 8MHz, DTC=1, THREADS=1, 4WIRES (RTS) options -;=============================================================================== -; TARGET ; ;INFO+VECTORS+ MAIN bytes -;MSP_EXP430FR5739 ; compile for MSP-EXP430FR5739 launchpad ; 64 + 128 + 2768 bytes -;MSP_EXP430FR5969 ; compile for MSP-EXP430FR5969 launchpad ; 64 + 128 + 2760 bytes -;MSP_EXP430FR5994 ; compile for MSP-EXP430FR5994 launchpad ; 64 + 128 + 2780 bytes -;MSP_EXP430FR6989 ; compile for MSP-EXP430FR6989 launchpad ; 64 + 128 + 2782 bytes -;MSP_EXP430FR4133 ; compile for MSP-EXP430FR4133 launchpad ; 64 + 128 + 2822 bytes -;MSP_EXP430FR2355 ; compile for MSP-EXP430FR2355 launchpad ; 64 + 128 + 2756 bytes -;MSP_EXP430FR2433 ; compile for MSP-EXP430FR2433 launchpad ; 64 + 128 + 2746 bytes -;LP_MSP430FR2476 ; compile for LP_MSP430FR2476 launchpad ; 64 + 128 + 2760 bytes -CHIPSTICK_FR2433; ; compile for "CHIPSTICK" of M. Ken BOAK ; 64 + 128 + 2748 bytes +; TARGET ; +;MSP_EXP430FR5739 ; compile for MSP-EXP430FR5739 launchpad +;MSP_EXP430FR5969 ; compile for MSP-EXP430FR5969 launchpad +MSP_EXP430FR5994 ;; compile for MSP-EXP430FR5994 launchpad +;MSP_EXP430FR6989 ; compile for MSP-EXP430FR6989 launchpad +;MSP_EXP430FR4133 ; compile for MSP-EXP430FR4133 launchpad +;MSP_EXP430FR2355 ; compile for MSP-EXP430FR2355 launchpad +;MSP_EXP430FR2433 ; compile for MSP-EXP430FR2433 launchpad +;LP_MSP430FR2476 ; compile for LP_MSP430FR2476 launchpad +;CHIPSTICK_FR2433 ; compile for "CHIPSTICK" of M. Ken BOAK ; choose DTC model (Direct Threaded Code); if you don't know, choose 2, because DOCOL routine without using scratch register DTC .equ 2 ; DTC model 1 : DOCOL = CALL rDOCOL 14 cycles 1 word shortest DTC model ; DTC model 2 : DOCOL = PUSH IP, CALL rEXIT 13 cycles 2 words best compromize to mix FORTH/ASM code ; DTC model 3 : inlined DOCOL 9 cycles 4 words fastest -THREADS .equ 16 ; 1, 2 , 4 , 8 , 16, 32 search entries in dictionnary. +THREADS .equ 16 ; 1, 2 , 4 , 8 , 16, 32 search entries in word-set. ; +0, +28, +48, +56, +90, +154 bytes, usefull to speed up compilation; ; the FORTH interpreter is speed up by about a square root factor of THREADS. -FREQUENCY .equ 1 ; fully tested at 1,2,4,8,16,24 MHz (24 MHz for MSP430FR57xx,MSP430FR2355) +FREQUENCY .equ 1 ; fully tested at 1,2,4,8,16 MHz, plus 24 MHz for MSP430FR57xx,MSP430FR2355 -;=============================================================================== -TERMINAL_I2C ; uncomment to select I2C_Master TERMINAL instead of UART TERMINAL -;=============================================================================== +; ============================================================================ +;TERMINAL_I2C ; - 12 bytes; uncomment to select I2C_Master TERMINAL instead of UART TERMINAL +; ============================================================================ .IFDEF TERMINAL_I2C MYSLAVEADR .equ 18 -;=============================================================================== +; ============================================================================ .ELSE ; UART TERMINAL -;=============================================================================== -TERMINALBAUDRATE .equ 115200 ; choose value considering the frequency and the UART2USB bridge, see explanations below. -;------------------------------------------------------------------------------- -TERMINAL3WIRES ; + 18 bytes enable 3 wires (GND,TX,RX) with XON/XOFF software flow control (PL2303TA/HXD, CP2102) -TERMINAL4WIRES ; + 12 bytes enable 4 wires with hardware flow control on RX with RTS (PL2303TA/HXD, FT232RL) -;TERMINAL5WIRES ; + 10 bytes enable 5 wires with hardware flow control on RX/TX with RTS/CTS (PL2303TA/HXD, FT232RL)... -;------------------------------------------------------------------------------- +; ============================================================================ +TERMINALBAUDRATE .equ 115200 ; choose value considering the frequency, see explanations below. +; ---------------------------------------------------------------------------- +TERMINAL3WIRES ; ; + 18 bytes enable 3 wires XON/XOFF software flow control +TERMINAL4WIRES ; ; + 12 bytes enable 4 wires RTS hardware flow control +;TERMINAL5WIRES ; + 10 bytes enable 5 wires RTS/CTS hardware flow control +; ---------------------------------------------------------------------------- ;HALFDUPLEX ; switch to UART half duplex TERMINAL input -;=============================================================================== +; ============================================================================ .ENDIF + ;=============================================================================== -; MINIMAL ADDONS if you want a canonical FORTH: CORE_COMPLEMENT + CONDCOMP + PROMPT +; KERNEL ADDONs that can't be added later ;=============================================================================== -; MINIMAL ADDONS for FAST FORTH: MSP430ASSEMBLER + CONDCOMP +DOUBLE_INPUT ;; + 60 bytes : adds the interpretation engine for double numbers (numbers with dot) +FIXPOINT_INPUT ;; + 68 bytes : adds the interpretation engine for Q15.16 numbers (numbers with comma) +SD_CARD_LOADER ; + 1766 bytes : to load source files from SD_card +BOOTLOADER ; + 132 bytes : includes in WARM process the bootloader SD_CARD\BOOT.4TH. +SD_CARD_READ_WRITE ; + 1148 bytes : to read, create, write and del files + copy text files from PC to target SD_Card +;EXTENDED_MEM ; + 506 bytes : allows assembler to execute code up to 1MB (LARGE_CODE). +;EXTENDED_ASM ; + 1212 bytes : extended assembler to 20 bits datas (LARGE_DATA + LARGE_CODE). +;VOCABULARY_SET ; + 162 bytes : adds words: WORDSET FORTH hidden PREVIOUS ONLY DEFINITIONS +;PROMPT ; + 18 bytes : to display prompt "ok ", for FORTH addicts. ;=============================================================================== - -;------------------------------------------------------------------------------- -; KERNEL ADDONs that can't be added later -;------------------------------------------------------------------------------- -MSP430ASSEMBLER ; + 1812 bytes : adds embedded assembler with TI syntax; without, you can do all but bigger and slower... -CONDCOMP ; + 306 bytes : adds conditionnal compilation [IF] [ELSE] [THEN] [DEFINED] [UNDEFINED] -DOUBLE_INPUT ; + 56 bytes : adds the interpretation engine for double numbers (numbers with dot) -FIXPOINT_INPUT ; + 74 bytes : adds the interpretation engine for Q15.16 numbers (numbers with comma) -;DEFERRED ; + 124 bytes : adds DEFER IS :NONAME CODENNM (CODE_No_NaMe), useful for interrupts start and stop. -;EXTENDED_MEM ; + 740 bytes : allows assembler to execute code up to 1MB (LARGE_CODE). -;EXTENDED_ASM ; + 1260 bytes : extended assembler to 20 bits datas (LARGE_DATA + LARGE_CODE). -;SD_CARD_LOADER ; + 1766 bytes : to load source files from SD_card -;SD_CARD_READ_WRITE ; + 1148 bytes : to read, create, write and del files + copy text files from PC to target SD_Card -;BOOTLOADER ; + 132 bytes : includes in WARM process the bootloader SD_CARD\BOOT.4TH. -;VOCABULARY_SET ; + 174 bytes : adds words: VOCABULARY FORTH ASSEMBLER ALSO PREVIOUS ONLY DEFINITIONS (FORTH83) -;PROMPT ; + 22 bytes : to display prompt "ok " -;------------------------------------------------------------------------------- - -;------------------------------------------------------------------------------- -; OPTIONS that can be added later by downloading their source file >-----------------------+ -; however, added here, they are protected against WIPE and Deep Reset. | -;------------------------------------------------------------------------------- v -;CORE_COMPLEMENT ; + 1974 bytes : MINIMAL OPTIONS if you want a conventional FORTH CORECOMP.f -;FIXPOINT ; + 422/528 bytes add HOLDS F+ F- F/ F* F#S F. S>F FIXPOINT.f -;UTILITY ; + 434/524 bytes (1/16threads) : add .S .RS WORDS U.R DUMP ? UTILITY.f -;SD_TOOLS ; + 142 bytes for trivial DIR, FAT, CLUSTR. and SECTOR. view, (adds UTILITY) SD_TOOLS.f .save .listing off ;=============================================================================== @@ -136,9 +113,9 @@ FIXPOINT_INPUT ; + 74 bytes : adds the interpretation engine for Q15.16 n ; up to 460800 Bds (2MHz) ; up to 921600 Bds (4MHz) ; up to 1843200 Bds (8MHz) -; up to 3 MBds (12MHz,PL2303HXD with shortened cable < 20cm) -; up to 4 MBds (16MHz,PL2303HXD with shortened cable < 20cm) -; up to 5 MBds (20MHz,PL2303HXD with shortened cable < 20cm) +; up to 3 MBds (12MHz,PL2303HXD with shortened cable < 80cm) +; up to 4 MBds (16MHz,PL2303HXD with shortened cable < 60cm) +; up to 5 MBds (20MHz,PL2303HXD with shortened cable < 40cm) ; up to 6 MBds (24MHz,PL2303HXD with shortened cable < 20cm) ; UARTtoUSB module with Silabs CP2102 (supply current = 20 mA) @@ -223,7 +200,7 @@ FIXPOINT_INPUT ; + 74 bytes : adds the interpretation engine for Q15.16 n ; TERATERM config terminal : NewLine receive : LF, ; NewLine transmit : CR+LF -; Size : 128 chars x 49 lines (adjust lines to your display) +; Size : 80 chars x 44 lines (adjust lines to your display) ; TERATERM config serial port : TERMINALBAUDRATE value, ; 8bits, no parity, 1Stopbit, @@ -233,295 +210,10 @@ FIXPOINT_INPUT ; + 74 bytes : adds the interpretation engine for Q15.16 n ; don't forget : save new TERATERM configuration ! ; in fact, compared to using a UART USB bridge, only the COMx port is to be updated. -; ------------------------------------------------------------------------------ .restore - .include "ThingsInFirst.inc" ; macros, target definitions, init FORTH variables... -;------------------------------------------------------------------------------- -; DTCforthMSP430FR5xxx RAM memory map: -;------------------------------------------------------------------------------- - -;---------------------------;--------- -; name words ; comment -;---------------------------;--------- -;LSTACK = L0 = LEAVEPTR ; ----- RAM_ORG - ; | -LSTACK_LEN .equ 16 ; | grows up - ; V - ; ^ -PSTACK_LEN .equ 48 ; | grows down - ; | -;PSTACK=S0 ; ----- RAM_ORG + $80 - ; ^ -RSTACK_LEN .equ 48 ; | grows down - ; | -;RSTACK=R0 ; ----- RAM_ORG + $E0 - -;---------------------------;--------- -; names bytes ; comments -;---------------------------;--------- -; PAD_I2CADR ; ----- RAM_ORG + $E0 -; PAD_I2CCNT ; -; PAD < ----- RAM_ORG + $E4 - ; | -PAD_LEN .equ 84 ; | grows up (ans spec. : PAD >= 84 chars) - ; v -; TIB_I2CADR ; ----- RAM_ORG + $138 -; TIB_I2CCNT ; -; TIB < ----- RAM_ORG + $13C - ; | -TIB_LEN .equ 84 ; | grows up (ans spec. : TIB >= 80 chars) - ; v -; HOLDS_ORG < ------RAM_ORG + $190 - ; ^ -HOLD_LEN .equ 34 ; | grows down (ans spec. : HOLD_LEN >= (2*n) + 2 char, with n = 16 bits/cell - ; | -; HOLD_BASE < ----- RAM_ORG + $1B2 - ; - ; system variables - ; - ; ----- RAM_ORG + $1E0 - ; - ; 28 bytes free - ; -; SD_BUF_I2CADR < ----- RAM_ORG + $1FC -; SD_BUF_I2CCNT ; -; SD_BUF < ----- RAM_ORG + $200 - ; -SD_BUF_LEN .equ 200h ; 512 bytes buffer - ; -; SD_BUF_END < ----- RAM_ORG + $400 - -LSTACK .equ RAM_ORG -LEAVEPTR .equ LSTACK ; Leave-stack pointer -PSTACK .equ LSTACK+(LSTACK_LEN*2)+(PSTACK_LEN*2) -RSTACK .equ PSTACK+(RSTACK_LEN*2) -PAD_I2CADR .equ PAD_ORG-4 -PAD_I2CCNT .equ PAD_ORG-2 -PAD_ORG .equ RSTACK+4 -TIB_I2CADR .equ TIB_ORG-4 -TIB_I2CCNT .equ TIB_ORG-2 -TIB_ORG .equ PAD_ORG+PAD_LEN+4 -HOLDS_ORG .equ TIB_ORG+TIB_LEN - -HOLD_BASE .equ HOLDS_ORG+HOLD_LEN - -; ---------------------------------------------------- -; RAM_ORG + $1B2 : RAM VARIABLES -; ---------------------------------------------------- -HP .equ HOLD_BASE ; HOLD ptr -CAPS .equ HOLD_BASE+2 ; CAPS ON = 32, CAPS OFF = 0 -LAST_NFA .equ HOLD_BASE+4 ; NFA, VOC_PFA, CFA, PSP of last created word -LAST_THREAD .equ HOLD_BASE+6 ; used by QREVEAL -LAST_CFA .equ HOLD_BASE+8 -LAST_PSP .equ HOLD_BASE+10 -STATE .equ HOLD_BASE+12 ; Interpreter state -SOURCE .equ HOLD_BASE+14 ; len, org of input stream -SOURCE_LEN .equ HOLD_BASE+14 -SOURCE_ORG .equ HOLD_BASE+16 -TOIN .equ HOLD_BASE+18 ; CurrentInputBuffer pointer -DDP .equ HOLD_BASE+20 ; dictionnary pointer -LASTVOC .equ HOLD_BASE+22 ; keep VOC-LINK -CONTEXT .equ HOLD_BASE+24 ; CONTEXT dictionnary space (8 CELLS) -CURRENT .equ HOLD_BASE+40 ; CURRENT dictionnary ptr -BASE .equ HOLD_BASE+42 -LINE .equ HOLD_BASE+44 ; line in interpretation (see NOECHO, ECHO) - -; --------------------------; -; RAM_ORG + $1E0 : free use ; -; --------------------------; - .IFDEF SD_CARD_LOADER -; -------------------------------------------------- -; RAM_ORG + $1FC : RAM SD_CARD SD_BUF 4 + 512 bytes -; -------------------------------------------------- -SD_BUF_I2CADR .equ SD_BUF-4 -SD_BUF_I2CCNT .equ SD_BUF-2 -SD_BUF .equ HOLD_BASE+78 -SD_BUF_END .equ SD_BUF + 200h ; 512bytes - .ENDIF - - .org INFO_ORG -;------------------------------------------------------------------------------- -; INFO(DCBA) >= 256 bytes memory map (FRAM) : +; ------------------------------------------------------------------------------ + .include "ThingsInFirst.inc" ; macros, target definitions, RAM & INFO variables... ;------------------------------------------------------------------------------- -; FRAM INFO: KERNEL INIT CONSTANTS and VARIABLES -; ---------------------------------------------- -FREQ_KHZ .word FREQUENCY*1000 ; used to stabilize MCLK before start, see MSP430FRxxxx.asm - .IFDEF TERMINAL_I2C -I2CSLAVEADR .word MYSLAVEADR ; on MSP430FR2xxx devices with BSL I2C, Slave address is FFA0h -I2CSLAVEADR1 .word 0 -LPM_MODE .word GIE+LPM4 ; LPM4 is the default mode for I2C TERMINAL - .ELSE ; TERMINAL_UART -TERMBRW_RST .word TERMBRW_INI ; set by TERMINALBAUDRATE.inc -TERMMCTLW_RST .word TERMMCTLW_INI ; set by TERMINALBAUDRATE.inc -LPM_MODE .word GIE+LPM0 ; LPM0 is the default mode for UART TERMINAL - .ENDIF -RSTIV_MEM .word -7 ; to do RESET = -3 when compiling new kernel -RST_DP .word ROMDICT ; define RST_STATE -RST_VOC .word lastvoclink ; define RST_STATE -FORTHVERSION .word VAL(SUBSTR(VER,1,0)); used by WARM -INI_THREAD .word THREADS ; used by FF_SPECS.f, UTILITY.f -FORTHADDON .word FADDON ; used by FF_SPECS.f and to secure donwloading of any application.f files. -; --------------------------------------; -WIPE_INI ; MOV #WIPE_INI,X ; WIPE_INI constants are in FRAM INFO= DEEP_RESET init -; --------------------------------------; - .IFNDEF SD_CARD_LOADER -WIPE_COLD .word COLD_TERM ; MOV @X+,&PFACOLD ; COLD_TERM --> PFACOLD -WIPE_INI_FORTH .word RET_ADR ; MOV @X+,&PFA_INI_FORTH; RET_ADR --> PFA_INI_FORTH -WIPE_SLEEP .word RXON ; MOV @X+,&PFASLEEP ; RXON --> PFASLEEP -WIPE_WARM .word INIT_TERM ; MOV @X+,&PFAWARM ; INIT_TERM --> PFAWARM - .ELSE -WIPE_COLD .word COLD_TERM ; MOV @X+,&PFACOLD ; COLD_TERM --> PFACOLD -WIPE_INI_FORTH .word INI_SOFT_SD ; MOV @X+,&PFA_INI_FORTH; INI_SOFT_SD --> PFA_INI_FORTH -WIPE_SLEEP .word RXON ; MOV @X+,&PFASLEEP ; RXON --> PFASLEEP -WIPE_WARM .word INI_HARD_SD ; MOV @X+,&PFAWARM ; INI_HARD_SD --> PFAWARM - .ENDIF -WIPE_TERM_INT .word TERMINAL_INT ; MOV @X+,&TERM_VEC ; TERMINAL_INT --> TERM_VEC -WIPE_DP .word ROMDICT ; MOV @X+,&RST_DP ; ROMDICT --> RST_DP -WIPE_VOC .word lastvoclink ; MOV @X+,&RST_VOC ; lastvoclink --> RST_VOC -; --------------------------------------; -INI_FORTH_INI ; MOV #INI_FORTH_INI,X, to reset all kernel variables -; --------------------------------------; -INI_FORTH_ACCEPT .word BODYACCEPT ; MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT -INI_FORTH_CR .word BODYCR ; MOV @X+,&PFACR ; BODYCR --> PFACR -INI_FORTH_EMIT .word BODYEMIT ; MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT -INI_FORTH_KEY .word BODYKEY ; MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY -INI_FORTH_CIB .word TIB_ORG ; MOV @X+,&CIB_ADR ; TIB_ORG --> CIB_ADR -; --------------------------------------; -HALF_FORTH_INI ; MOV #HALF_FORTH_INI,X to preserve defered words -; --------------------------------------; - .SWITCH DTC - .CASE 1 -INI_FORTH_COL .word xDOCOL ; MOV @X+,rDOCOL ; init rDOCOL (R4) - .CASE 2 -INI_FORTH_COL .word EXIT ; MOV @X+,rDOCOL ; init rDOCOL (R4) - .CASE 3 - .word 0 ; MOV @X+,R4 ; rDOCOL doesn't exist - .ENDCASE -INI_FORTH_DOES .word xDODOES ; MOV @X+,rDODOES ; init rDODOES (R5) -INI_FORTH_CON .word xDOCON ; MOV @X+,rDOCON ; init rDOCON (R6) -INI_FORTH_VAR .word RFROM ; MOV @X+,rDOVAR ; init rDOVAR (R7) -INI_FORTH_CAPS .word 32 ; MOV @X+,&CAPS ; 32 --> CAPS -INI_FORTH_BASE .word 10 ; MOV @X+,&BASE ; 10 --> BASE -; --------------------------------------; -USER_END .word 0 - .word 0 - .word 0 - .word 0 - - - .IFDEF SD_CARD_LOADER -; --------------------------------------- -; VARIABLES that should be in RAM -; --------------------------------------- - .IF RAM_LEN < 2048 ; if RAM < 2K (FR57xx) the variables below are in INFO space (FRAM) -SD_ORG .equ INFO_ORG+5Ah ; - .ELSE ; if RAM >= 2k the variables below are in RAM -SD_ORG .equ SD_BUF_END+2 ; 1 word guard - .ENDIF - - .org SD_ORG -; --------------------------------------- -; FAT FileSystemInfos -; --------------------------------------- -FATtype .equ SD_ORG+0 -BS_FirstSectorL .equ SD_ORG+2 ; init by SD_Init, used by RW_Sector_CMD -BS_FirstSectorH .equ SD_ORG+4 ; init by SD_Init, used by RW_Sector_CMD -OrgFAT1 .equ SD_ORG+6 ; init by SD_Init, -FATSize .equ SD_ORG+8 ; init by SD_Init, -OrgFAT2 .equ SD_ORG+10 ; init by SD_Init, -OrgRootDIR .equ SD_ORG+12 ; init by SD_Init, (FAT16 specific) -OrgClusters .equ SD_ORG+14 ; init by SD_Init, Sector of Cluster 0 -SecPerClus .equ SD_ORG+16 ; init by SD_Init, byte size - -; --------------------------------------- -; SD command -; --------------------------------------- -SD_LOW_LEVEL .equ SD_ORG+18 -SD_CMD_FRM .equ SD_LOW_LEVEL ; SD_CMDx inverted frame ${CRC7,ll,LL,hh,HH,CMD} -SectorL .equ SD_LOW_LEVEL+6 -SectorH .equ SD_LOW_LEVEL+8 -; --------------------------------------- -; SD_BUF management -; --------------------------------------- -BufferPtr .equ SD_LOW_LEVEL+10 -BufferLen .equ SD_LOW_LEVEL+12 -; --------------------------------------- -; FAT entry -; --------------------------------------- -SD_FAT_LEVEL .equ SD_LOW_LEVEL+14 -ClusterL .equ SD_FAT_LEVEL ; -ClusterH .equ SD_FAT_LEVEL+2 ; -NewClusterL .equ SD_FAT_LEVEL+4 ; -NewClusterH .equ SD_FAT_LEVEL+6 ; -CurFATsector .equ SD_FAT_LEVEL+8 ; current FATSector of last free cluster -; --------------------------------------- -; DIR entry -; --------------------------------------- -DIRClusterL .equ SD_FAT_LEVEL+10 ; contains the Cluster of current directory ; = 1 as FAT16 root directory -DIRClusterH .equ SD_FAT_LEVEL+12 ; contains the Cluster of current directory ; = 1 as FAT16 root directory -EntryOfst .equ SD_FAT_LEVEL+14 -; --------------------------------------- -; Handle Pointer -; --------------------------------------- -CurrentHdl .equ SD_FAT_LEVEL+16 ; contains the address of the last opened file structure, or 0 -; --------------------------------------- -; Load file operation -; --------------------------------------- -pathname .equ SD_FAT_LEVEL+18 ; start address -EndOfPath .equ SD_FAT_LEVEL+20 ; end address -; --------------------------------------- -; Handle structure -; --------------------------------------- -FirstHandle .equ SD_FAT_LEVEL+22 -; three handle tokens : -; HDLB_Token= 0 : free handle -; = 1 : file to read -; = 2 : file updated (write) -; =-1 : LOAD"ed file (source file) - -; offset values -HDLW_PrevHDL .equ 0 ; previous handle -HDLB_Token .equ 2 ; token -HDLB_ClustOfst .equ 3 ; Current sector offset in current cluster (Byte) -HDLL_DIRsect .equ 4 ; Dir SectorL -HDLH_DIRsect .equ 6 ; Dir SectorH -HDLW_DIRofst .equ 8 ; SD_BUF offset of Dir entry -HDLL_FirstClus .equ 10 ; File First ClusterLo (identify the file) -HDLH_FirstClus .equ 12 ; File First ClusterHi (identify the file) -HDLL_CurClust .equ 14 ; Current ClusterLo -HDLH_CurClust .equ 16 ; Current ClusterHi -HDLL_CurSize .equ 18 ; written size / not yet read size (Long) -HDLH_CurSize .equ 20 ; written size / not yet read size (Long) -HDLW_BUFofst .equ 22 ; SD_BUF offset ; used by LOAD" -HDLW_PrevLEN .equ 24 ; previous LEN -HDLW_PrevORG .equ 26 ; previous ORG - - .IF RAM_LEN < 2048 ; due to the lack of RAM, only 4 handles and PAD replaces SDIB -HandleMax .equ 4 ; and not 8 to respect INFO size (FRAM) -HandleLenght .equ 28 -HandlesLen .equ handleMax*HandleLenght -HandleEnd .equ FirstHandle+handleMax*HandleLenght -SD_END .equ HandleEnd -SDIB_I2CADR .equ PAD_ORG-4 -SDIB_I2CCNT .equ PAD_ORG-2 -SDIB_ORG .equ PAD_ORG - .ELSE ; RAM_Size >= 2k all is in RAM -HandleMax .equ 8 -HandleLenght .equ 28 -HandlesLen .equ handleMax*HandleLenght -HandleEnd .equ FirstHandle+handleMax*HandleLenght -SDIB_I2CADR .equ SDIB_ORG-4 -SDIB_I2CCNT .equ SDIB_ORG-2 -SDIB_ORG .equ HandleEnd+4 -SDIB_LEN .equ 84 ; = TIB_LEN = PAD_LEN -SD_END .equ SDIB_ORG+SDIB_LEN - .ENDIF ; RAM_Size -SD_LEN .equ SD_END-SD_ORG - .ENDIF ; SD_CARD_LOADER -; --------------------------; -; INFO_ORG + $40 : free use ; -; --------------------------; - .org MAIN_ORG ;------------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx program (FRAM) memory @@ -530,125 +222,77 @@ SD_LEN .equ SD_END-SD_ORG ; Users can access them via declarations made in \inc\MSP430FRxxxx.pat ; ;############################################################################### -; ╦┌┐┌┌┬┐┌─┐┬─┐┬─┐┬ ┬┌─┐┌┬┐┌─┐ ┌─┐┌─┐┬ ┬ ┌┬┐┌─┐┬ ┬┌┐┌ ┬ ┬┌─┐┬─┐┌─┐ -; ║│││ │ ├┤ ├┬┘├┬┘│ │├─┘ │ └─┐ ├┤ ├─┤│ │ │││ │││││││ ├─┤├┤ ├┬┘├┤ -; ╩┘└┘ ┴ └─┘┴└─┴└─└─┘┴ ┴ └─┘ └ ┴ ┴┴─┘┴─┘ ─┴┘└─┘└┴┘┘└┘ ┴ ┴└─┘┴└─└─┘ -;############################################################################### -SLEEP ; here, FAST FORTH sleeps, waiting any interrupt. With LPM4, supply current is below 1uA. ; IP,S,T,W,X,Y registers (R13 to R8) are free... ; ...and so TOS, PSP and RSP stacks within their rules of use. ; +; ; remember: to force SLEEP execution, you must end any interrupt routine with : +; ; BIC #%0_1111_000,0(RSP) ; 4~ +; ; RETI ; 5~ 4 words +; ; ; remember: to force SLEEP execution, you must end any interrupt routine with : ; MOV @RSP+,SR ; 2~ -; BIC #%1111_1000,SR ; 2~ +; BIC #%0_1111_000,SR ; 2~ ; RET ; 3~ 4 words ; -; or faster (but return SR flags will be lost) with: +; or faster (but SR flags will be lost): ; ADD #2 RSP ; 1~ ; RET ; 3~ 2 words ; - CALL @PC+ ;4 SLEEP first calls BACKGND_APP -PFASLEEP .word RXON ; BACKGND_DEF = RXON as default BACKGND_APP; value set by WIPE. +SLEEP CALL &SLEEP_APP ; BACKGND_DEF = UART_RXON/I2C_ACCEPT as default BACKGND_APP; value set by DEEP. BIS &LPM_MODE,SR ;2 enter in LPMx mode with GIE=1 - JMP SLEEP ;2 instruction always executed before CPU asleeping. -; + JMP SLEEP ;2 return off any interrupts else TERMINAL_INT +; ;############################################################################### ; ------------------------------------------------------------------------------ ; COMPILING OPERATORS ; ------------------------------------------------------------------------------ -; Primitive LIT; compiled by LITERAL +; Primitive lit; compiled by LITERAL ; lit -- x fetch inline literal to stack ; This is the run-time code of LITERAL. -; FORTHWORD "LIT" -LIT SUB #2,PSP ; 2 push old TOS.. - MOV TOS,0(PSP) ; 3 ..onto stack - MOV @IP+,TOS ; 2 fetch new TOS value - MOV @IP+,PC ; 4 NEXT - +lit SUB #2,PSP ; 1 save old TOS.. + MOV TOS,0(PSP) ; 3 ..onto stack + MOV @IP+,TOS ; 2 fetch new TOS value + MOV @IP+,PC ; 4 NEXT + +TWODUP_XSQUOTE ; used by [ELSE] + MOV TOS,-2(PSP) ; 3 + MOV @PSP,-4(PSP) ; 4 + SUB #4,PSP ; 1 ; Primitive XSQUOTE; compiled by SQUOTE ; (S") -- addr u run-time code to get address and length of a compiled string. -XSQUOTE SUB #4,PSP ; 1 -- x x TOS ; push old TOS on stack - MOV TOS,2(PSP) ; 3 -- TOS x x ; and reserve one cell on stack - MOV.B @IP+,TOS ; 2 -- x u ; u = lenght of string - MOV IP,0(PSP) ; 3 -- addr u IP is odd... - ADD TOS,IP ; 1 -- addr u IP=addr+u=addr(end_of_string) - BIT #1,IP ; 1 -- addr u IP=addr+u Carry set/clear if odd/even - ADDC #0,IP ; 1 -- addr u IP=addr+u aligned - MOV @IP+,PC ; 4 16~ +XSQUOTE SUB #4,PSP ; 1 push old TOS on stack + MOV TOS,2(PSP) ; 3 and reserve one cell on stack + MOV.B @IP+,TOS ; 2 -- ? u u = lenght of string + MOV IP,0(PSP) ; 3 -- addr u IP is odd... + ADD TOS,IP ; 1 -- addr u IP=addr+u=addr(end_of_string) + BIT #1,IP ; 1 -- addr u IP=addr+u Carry set/clear if odd/even + ADDC #0,IP ; 1 -- addr u IP=addr+u aligned + MOV @IP+,PC ; 4 16~ ; https://forth-standard.org/standard/core/HERE -; HERE -- addr returns memory ptr -HERE SUB #2,PSP +; HERE -- addr returns memory program ptr +HEREXEC SUB #2,PSP MOV TOS,0(PSP) - MOV &DDP,TOS + MOV &DP,TOS MOV @IP+,PC -;------------------------------------------------------------------------------- -; BRANCH run-time -;------------------------------------------------------------------------------- -; Primitive QFBRAN; compiled by IF UNTIL -;Z ?FalseBranch x -- ; branch if TOS is FALSE (TOS = 0) -QFBRAN CMP #0,TOS ; 1 test TOS value - MOV @PSP+,TOS ; 2 pop new TOS value (doesn't change flags) - JNZ SKIPBRANCH ; 2 if TOS was <> 0, skip the branch; 10 cycles -; Primitive BRAN -;Z branch -- ; -BRAN MOV @IP,IP ; 2 take the branch destination - MOV @IP+,PC ; 4 ==> branch taken - -;------------------------------------------------------------------------------- -; LOOP run-time -;------------------------------------------------------------------------------- -; Primitive XDO; compiled by DO -;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2 run-time code for DO -; n1|u1=limit, n2|u2=index -XDO MOV #8000h,X ;2 compute 8000h-limit = "fudge factor" - SUB @PSP+,X ;2 - MOV TOS,Y ;1 loop ctr = index+fudge - MOV @PSP+,TOS ;2 - ADD X,Y ;1 Y = INDEX - PUSHM #2,X ;4 PUSHM X,Y, i.e. PUSHM LIMIT, INDEX - MOV @IP+,PC ;4 -; Primitive XPLOOP; compiled by +LOOP -;Z (+loop) n -- R: sys1 sys2 -- | sys1 sys2 -; run-time code for +LOOP -; Add n to the loop index. If loop terminates, clean up the -; return stack and skip the branch. Else take the inline branch. -XPLOOP ADD TOS,0(RSP) ;4 increment INDEX by TOS value - MOV @PSP+,TOS ;2 get new TOS, doesn't change flags -XLOOPNEXT BIT #100h,SR ;2 is overflow bit set? - JZ BRAN ;2 no overflow = loop - ADD #4,RSP ;1 empty RSP -SKIPBRANCH ADD #2,IP ;1 overflow = loop done, skip branch ofs - MOV @IP+,PC ;4 16~ taken or not taken xloop/loop - -; Primitive XLOOP; compiled by LOOP -;Z (loop) R: sys1 sys2 -- | sys1 sys2 -; run-time code for LOOP -; Add 1 to the loop index. If loop terminates, clean up the -; return stack and skip the branch. Else take the inline branch. -; Note that LOOP terminates when index=8000h. -XLOOP ADD #1,0(RSP) ;4 increment INDEX - JMP XLOOPNEXT ;2 - -; primitive MUSMOD; compiled by ?NUMBER UM/MOD -; MUSMOD UDVDlo UDVDhi UDIVlo -- UREMlo UQUOTlo UQUOThi +; primitive MU/MOD; used by ?NUMBER UM/MOD, and M*/ in DOUBLE word set +; MU/MOD UDVDlo UDVDhi UDIVlo -- UREMlo UQUOTlo UQUOThi ;------------------------------------------------------------------------------- -; unsigned 32-BIT DiViDend : 16-BIT DIVisor --> 32-BIT QUOTient, 16-BIT REMainder +; unsigned 32-BIT DiViDend : 16-BIT DIVisor --> 32-BIT QUOTient 16-BIT REMainder ;------------------------------------------------------------------------------- +; two times faster if 16 bits DiViDend (cases of U. and . among others) -; 2 times faster if DVDhi = 0 (it's the general case) - -; reg division MU/MOD NUM -; --------------------------------------------- -; S = DVD(15-0) = ud1lo = ud1lo -; TOS = DVD(31-16) = ud1hi = ud1hi -; W = DVD(47-32)/REM = rem = digit --> char --> -[HP] -; T = DIV(15-0) = BASE = BASE -; X = QUOTlo = ud2lo = ud2lo -; Y = QUOThi = ud2hi = ud2hi +; reg division MU/MOD NUM M*/ +; --------------------------------------------------------------------- +; S = DVD(15-0) = ud1lo = ud1lo ud1lo +; TOS = DVD(31-16) = ud1hi = ud1hi ud1mi +; W = DVD(47-32)/REM = rem = digit --> char --> -[HP] ud1hi +; T = DIV(15-0) = BASE = BASE ud2 +; X = QUOTlo = ud2lo = ud2lo QUOTlo +; Y = QUOThi = ud2hi = ud2hi QUOThi ; rDODOES = count MUSMOD MOV TOS,T ;1 T = DIVlo @@ -658,12 +302,12 @@ MUSMOD1 MOV #0,W ;1 W = REMlo = 0 MOV #32,rDODOES ;2 init loop count CMP #0,TOS ;1 DVDhi=0 ? JNZ MDIV1 ;2 no -; ----------------------------------------- +; ----------------------------------; MDIV1DIV2 RRA rDODOES ;1 yes:loop count / 2 MOV S,TOS ;1 DVDhi <-- DVDlo MOV #0,S ;1 DVDlo <-- 0 MOV #0,X ;1 QUOTlo <-- 0 (to do QUOThi = 0 at the end of division) -; ----------------------------------------- +; ----------------------------------; MDIV1 CMP T,W ;1 REMlo U>= DIVlo ? JNC MDIV2 ;2 no : carry is reset SUB T,W ;1 yes: REMlo - DIVlo ; carry is set @@ -682,77 +326,79 @@ ENDMDIV MOV #XDODOES,rDODOES ;2 restore rDODOES MOV W,2(PSP) ;3 REMlo in 2(PSP) MOV X,0(PSP) ;3 QUOTlo in 0(PSP) MOV Y,TOS ;1 QUOThi in TOS -RET_ADR MOV @RSP+,PC ;4 35 words, about 473 cycles, not FORTH executable ! +RET_ADR MOV @RSP+,PC ;4 35 words, about 466/246 cycles, not FORTH executable ! -; : SETIB SOURCE 2! 0 >IN ! ; +; : SETIB SOURCE 2! 0 >IN ! ; ; SETIB org len -- set Input Buffer, shared by INTERPRET and [ELSE] SETIB MOV TOS,&SOURCE_LEN ; -- org len MOV @PSP+,&SOURCE_ORG ; -- len MOV #0,&TOIN ; - MOV @PSP+,TOS ; -- +DROP MOV @PSP+,TOS ; -- MOV @IP+,PC ; ; REFILL accept one line to input buffer and leave org len' of the filled input buffer ; as it has no more host OS and as waiting command is done by ACCEPT, REFILL's flag is useless -; : REFILL TIB DUP TIB_LEN ACCEPT ; -- org len' shared by QUIT and [ELSE] -REFILL SUB #6,PSP ;2 - MOV TOS,4(PSP) ;3 - MOV #TIB_LEN,TOS ;2 -- x x len +; : REFILL TIB DUP CIB_LEN ACCEPT ; -- org len' shared by QUIT and [ELSE] +REFILL SUB #4,PSP ;1 + MOV TOS,2(PSP) ;3 save TOS +TWODROP_REFILL ; see [ELSE] + MOV #CIB_LEN,TOS ;2 -- x len Current Input Buffer LENght .word 40BFh ; MOV #imm,index(PSP) -CIB_ADR .word TIB_ORG ; imm=TIB_ORG - .word 0 ;4 -- x org len index=0 ==> MOV #TIB_ORG,0(PSP) - MOV @PSP,2(PSP) ;4 -- org org len +CIB_ORG .word TIB_ORG ; imm=TIB_ORG + .word 0 ;4 -- org len index=0 ==> MOV #TIB_ORG,0(PSP) + MOV @PSP,-2(PSP) ;4 -- org len + SUB #2,PSP ;1 -- org org len JMP ACCEPT ;2 org org len -- org len' -XDODOES ; -- addr ; 4 for CALL rDODOES S-- BODY PFA R-- +; Primitive QFBRAN; compiled by IF UNTIL +;Z ?FalseBranch x -- ; branch if TOS is FALSE (TOS = 0) +QFBRAN CMP #0,TOS ; 1 test TOS value + MOV @PSP+,TOS ; 2 pop new TOS value (doesn't change flags) +ZBRAN JNZ SKIPBRANCH ; 2 if TOS was <> 0, skip the branch; 10 cycles +BRAN MOV @IP,IP ; 2 take the branch destination + MOV @IP+,PC ; 4 ==> branch taken, 11 cycles + +XDODOES ; 4 for CALL rDODOES SUB #2,PSP ;+1 MOV TOS,0(PSP) ;+3 save TOS on parameters stack MOV @RSP+,TOS ;+2 TOS = PFA address of master word, i.e. address of its first cell after DOES> PUSH IP ;+3 save IP on return stack MOV @TOS+,IP ;+2 IP = CFA of Master word, TOS = BODY address of created word MOV @IP+,PC ;+4 = 19~ = ITC-2 - -XDOCON ; 4 for CALL rDOCON S-- CTE PFA R-- - SUB #2,PSP ;+1 + +XDOCON ; 4 for CALL rDOCON + SUB #2,PSP ;+1 MOV TOS,0(PSP) ;+3 save TOS on parameters stack MOV @RSP+,TOS ;+2 TOS = PFA address of master word CONSTANT MOV @TOS,TOS ;+2 TOS = CONSTANT value MOV @IP+,PC ;+4 = 16~ = ITC+4 -; https://forth-standard.org/standard/core/Rfrom -; R> -- x R: x -- pop from return stack -RFROM -XDOVAR ; 4 for CALL rDOVAR ADR -- VAR - SUB #2,PSP ;+1 - MOV TOS,0(PSP) ;+3 - MOV @RSP+,TOS ;+2 - MOV @IP+,PC ;+4 = 14~ = ITC+4 - -;-----------------------------------; -; PUC 6.1: init Forth engine ; common part of QABORT|WARM -;-----------------------------------; -INI_FORTH ; - CALL @PC+ ; -PFA_INI_FORTH - .IFNDEF SD_CARD_LOADER - .word RET_ADR ; INI_SOFT_APP default value - .ELSE - .word INI_SOFT_SD ; init software SD_Card : close all handles - .ENDIF - MOV #INI_FORTH_INI,X ; in FRAM INFO +;-----------------------------------; +INIT_FORTH ; common part of QABORT|WARM|PUC +;-----------------------------------; + CALL &SOFT_APP ; init SOFT_APP + MOV @RSP+,IP ; init IP with CALLER next address +; ; + MOV #PUC_ABORT_ORG,X ; FRAM INFO FRAM MAIN +; ; --------- --------- MOV @X+,&PFAACCEPT ; BODYACCEPT --> PFAACCEPT - MOV @X+,&PFACR ; BODYCR --> PFACR MOV @X+,&PFAEMIT ; BODYEMIT --> PFAEMIT MOV @X+,&PFAKEY ; BODYKEY --> PFAKEY - MOV @X+,&CIB_ADR ; TIB_ORG --> CIB_ADR - MOV @X+,rDOCOL ; --> rDOCOL - MOV @X+,rDODOES ; xDODOES --> rDODOES - MOV @X+,rDOCON ; xDOCON --> rDOCON - MOV @X+,rDOVAR ; RFROM --> rDOVAR - MOV @X+,&CAPS ; 32 --> CAPS init CAPS ON - MOV @X+,&BASE ; 10 --> BASE init decimal base - MOV @RSP+,IP ; init IP with RET_ADR = LIT|WARM from resp. QABORT|RESET - MOV #SEL_P_R_D,PC ; goto PUC 6.2 to select PWR_STATE|RST_STATE|DEEP_RESET + MOV @X+,&CIB_ORG ; TIB_ORG --> CIB_ORG +; ; +; ; FRAM INFO REG|RAM +; ; --------- ------- + MOV @X+,RSP ; INIT_RSTACK --> R1=RSP + MOV @X+,rDOCOL ; INIT_DTC --> R4=rDOCOL + MOV @X+,rDODOES ; INIT_DODOES --> R5=rDODOES + MOV @X+,rDOCON ; INIT_DOCON --> R6=rDOCON + MOV @X+,rDOVAR ; INIT_RFROM --> R7=rDOVAR + MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS init CAPS ON + MOV @X+,&BASEADR ; INIT_BASE --> RAM BASE init decimal base + MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR + MOV #0,&STATE ; 0 --> RAM STATE + MOV #SEL_RST_DEP,PC ; goto PUC 7 to select the user's choice from TOS value: RST_RET|DEEP_RESET +;-----------------------------------; .IFDEF TERMINAL_I2C .include "forthMSP430FR_TERM_I2C.asm" @@ -767,7 +413,7 @@ PFA_INI_FORTH .include "forthMSP430FR_SD_ACCEPT.asm" .ENDIF - .IF DTC = 1 ; DOCOL = CALL rDOCOL, [rDOCOL] = xdocol + .IF DTC = 1 ; DOCOL = CALL rDOCOL, [rDOCOL] = XDOCOL XDOCOL MOV @RSP+,W ; 2 PUSH IP ; 3 save old IP on return stack MOV W,IP ; 1 set new IP to PFA @@ -776,169 +422,189 @@ XDOCOL MOV @RSP+,W ; 2 FORTHWORD "TYPE" ;https://forth-standard.org/standard/core/TYPE -;C TYPE adr len -- type string to terminal -TYPE CMP #0,TOS ;1 - JZ TWODROP ;2 abort fonction - PUSH IP ;3 +;C TYPE adr u -- type string to terminal +TYPE PUSH IP ;3 MOV #TYPE_NEXT,IP ;2 -TYPELOOP MOV @PSP,Y ;2 -- adr len Y = adr - SUB #2,PSP ;1 -- adr x len - MOV TOS,0(PSP) ;3 -- adr len len - MOV.B @Y+,TOS ;2 -- adr len char - MOV Y,2(PSP) ;3 -- adr+1 len char - MOV &PFAEMIT,PC ;5+17 all scratch registers must be and are free -TYPE_NEXT .word $+2 ; -- adr+1 len +; PUSHM #2,X ;4 push X Y + MOV @PSP,X ;2 -- adr len X = adr +TYPELOOP MOV TOS,0(PSP) ;3 -- len len + MOV.B @X+,TOS ;2 -- len char + JMP EMIT ;2 ~17, S T W regs are free +TYPE_NEXT mNEXTADR ; -- len SUB #2,IP ;1 [IP] = TYPE_NEXT - SUB #1,TOS ;1 -- adr+1 len-1 - JNZ TYPELOOP ;2 37~ EMIT loop - MOV @RSP+,IP ;3 -- adr+len 0 + SUB #2,PSP ;1 -- x len + SUB.B #1,TOS ;1 -- x len-1 byte operation, according to the /COUNTED-STRING value + JNZ TYPELOOP ;2 29~ EMIT loop +; POPM #2,X ;4 pop Y X + MOV @RSP+,IP ;2 -- x 0 TWODROP ADD #2,PSP ;1 -- 0 -DROP MOV @PSP+,TOS ;2 -- + MOV @PSP+,TOS ;2 -- MOV @IP+,PC ;4 - FORTHWORD "CR" -; https://forth-standard.org/standard/core/CR -; CR -- send CR to the output device -CR MOV @PC+,PC ;3 Code Field Address (CFA) of CR -PFACR .word BODYCR ; Parameter Field Address (PFA) of CR, with its default value -BODYCR mDOCOL ; send CR+LF to the default output device - .word XSQUOTE - .byte 2,13,10 - .word TYPE,EXIT +BL CALL rDOCON + .word 20h + +; ------------------------------------------------------------------------------ +; forthMSP430FR : CONDITIONNAL COMPILATION, 114/109 words +; ------------------------------------------------------------------------------ +; BRanch if BAD strings COMParaison, [COMPARE ZEROEQUAL QFBRAN] replacement +BRBADCOMP ; -- addr1 u1 addr2 u2 + MOV TOS,S ;1 S = u2 + MOV @PSP+,Y ;2 Y = addr2 + CMP @PSP+,S ;2 u1 = u2 ? + MOV @PSP+,X ;2 X = addr1 + MOV @PSP+,TOS ;2 -- + JNZ BRAN ;2 -- branch if u1<>u2, 11+6 cycles +COMPLOOP CMP.B @Y+,0(X) ;4 + JNZ BRAN ;2 -- if char1<>char2; branch on first char <> in 17+6 cycles + ADD #1,X ;1 addr1+1 + SUB #1,S ;1 u2-1 + JNZ COMPLOOP ;2 10 cycles char comp loop +SKIPBRANCH ADD #2,IP ;1 + MOV @IP+,PC ;4 + +; [TWODROP ONEMINUS ?DUP ZEROEQUAL QFBRAN next_comp EXIT] replacement +BRNEXTCMP ; -- cnt addr u + ADD #2,PSP ;1 -- cnt addr TWODROP + MOV @PSP+,TOS ;2 -- cnt + SUB #1,TOS ;3 -- cnt-1 ONEMINUS + JNZ BRAN ;2 -- cnt-1 branch to next comparaison if <> 0 + JZ DROPEXIT ;19w else DROP EXIT + + FORTHWORDIMM "[ELSE]" +; https://forth-standard.org/standard/tools/BracketELSE +; [ELSE] a small and fast definition +;Compilation: +;Perform the execution semantics given below. +;Execution: +;( "<spaces>name ..." -- ) +;Skipping leading spaces, parse and discard space-delimited words from the parse area, +;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN], +;until the word [THEN] has been parsed and discarded. +;If the parse area becomes exhausted, it is refilled as with REFILL. +BRACKETELSE + mDOCOL + .word lit,0 ; -- 0 +BRACKETELSE0 + .word ONEPLUS ; -- cnt+1 +BRACKETELSE1 ; + .word BL,WORDD,COUNT ; -- cnt addr u Z=1 if U=0 + .word ZBRAN,BRACKETELSE5 ; u = 0 if end of line --> refill buffer then loop back + .word TWODUP_XSQUOTE ; oui je sais, c'est pas beau mais c'est efficace.... + .byte 6,"[THEN]" ; -- cnt addr u addr u addr2 u2 + .word BRBADCOMP,BRACKETELSE2 ; -- cnt addr u if bad string comparaison, jump for next comparaison + .word BRNEXTCMP,BRACKETELSE1 ; 2DROP, count-1, loop back if count <> 0, else DROP EXIT +BRACKETELSE2 ; + .word TWODUP_XSQUOTE ; + .byte 6,"[ELSE]" ; + .word BRBADCOMP,BRACKETELSE3 ; if bad string comparaison, jump for next comparaison + .word BRNEXTCMP,BRACKETELSE0 ; 2DROP, count-1, loop back with count+1 if count <> 0, else DROP EXIT +BRACKETELSE3 ; + .word XSQUOTE ; + .byte 4,"[IF]" ; + .word BRBADCOMP,BRACKETELSE1 ; if bad string comparaison, loop back + .word BRAN,BRACKETELSE0 ; else loop back with count+1 +BRACKETELSE5 ; +;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; +; OPTION ; +5 words option +;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv; + .word XSQUOTE ; + .byte 5,13,"ko ",10 ; + .word TYPE ; CR ." ko " LF to show false branch of conditionnal compilation +;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; + .word TWODROP_REFILL ; REFILL Input Buffer with next line + .word SETIB ; SET Input Buffer pointers SOURCE_LEN, SOURCE_ORG and clear >IN + .word BRAN,BRACKETELSE1 ; then loop back 45/40 words with/without option + + FORTHWORDIMM "[THEN]" ; do nothing +; https://forth-standard.org/standard/tools/BracketTHEN +; [THEN] +BRACKETTHEN MOV @IP+,PC + + FORTHWORDIMM "[IF]" ; flag -- +; https://forth-standard.org/standard/tools/BracketIF +; [IF] +;Compilation: +;Perform the execution semantics given below. +;Execution: ;( flag | flag "<spaces>name ..." -- ) +;If flag is true, do nothing. Otherwise, skipping leading spaces, +; parse and discard space-delimited words from the parse area, +; including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN], +; until either the word [ELSE] or the word [THEN] has been parsed and discarded. +;If the parse area becomes exhausted, it is refilled as with REFILL. [IF] is an immediate word. +;An ambiguous condition exists if [IF] is POSTPONEd, +; or if the end of the input buffer is reached and cannot be refilled before the terminating [ELSE] or [THEN] is parsed. +BRACKETIF CMP #0,TOS ; -- f + MOV @PSP+,TOS ; -- + JZ BRACKETELSE ; if false flag output + MOV @IP+,PC ; if true flag output + + FORTHWORDIMM "[DEFINED]" +; https://forth-standard.org/standard/tools/BracketDEFINED +; [DEFINED] +;Compilation: +;Perform the execution semantics given below. +;Execution: +;( "<spaces>name ..." -- flag ) +;Skip leading space delimiters. Parse name delimited by a space. +;Return a true flag if name is the name of a word that can be found, +;otherwise return a false flag. [DEFINED] is an immediate word. +DEFINED mDOCOL + .word BL,WORDD,FIND + .word NIP,EXIT + + + FORTHWORDIMM "[UNDEFINED]" +; https://forth-standard.org/standard/tools/BracketUNDEFINED +; [UNDEFINED] +;Compilation: +;Perform the execution semantics given below. +;Execution: ( "<spaces>name ..." -- flag ) +;Skip leading space delimiters. Parse name delimited by a space. +;Return a false flag if name is the name of a word that can be found, +;otherwise return a true flag. + mDOCOL + .word BL,WORDD,FIND + mNEXTADR + MOV @RSP+,IP + ADD #2,PSP ; NIP +; https://forth-standard.org/standard/core/ZeroEqual +; 0= n/u -- flag return true if TOS=0 +ZEROEQUAL SUB #1,TOS ;1 borrow (clear cy) if TOS was 0 + SUBC TOS,TOS ;1 TOS=-1 if borrow was set + MOV @IP+,PC ;4 ;------------------------------------------------------------------------------- ; STACK OPERATIONS ;------------------------------------------------------------------------------- - .IFDEF CORE_COMPLEMENT - FORTHWORD "DUP" - .ENDIF -; https://forth-standard.org/standard/core/DUP -; DUP x -- x x duplicate top of stack -DUP SUB #2,PSP ; 2 push old TOS.. - MOV TOS,0(PSP) ; 3 ..onto stack - MOV @IP+,PC ; 4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "?DUP" - .ENDIF -; https://forth-standard.org/standard/core/qDUP -; ?DUP x -- 0 | x x DUP if nonzero -QDUP CMP #0,TOS ; 2 test for TOS nonzero - JNZ DUP ; 2 - MOV @IP+,PC ; 4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "2DUP" - .ENDIF -; https://forth-standard.org/standard/core/TwoDUP -; 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2 cells -TWODUP MOV TOS,-2(PSP) ; 3 - MOV @PSP,-4(PSP); 4 - SUB #4,PSP ; 1 - MOV @IP+,PC ; 4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "SWAP" - .ENDIF ; https://forth-standard.org/standard/core/SWAP -; SWAP x1 x2 -- x2 x1 swap top two items -SWAP MOV @PSP,W ; 2 - MOV TOS,0(PSP) ; 3 - MOV W,TOS ; 1 - MOV @IP+,PC ; 4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "DROP" -; https://forth-standard.org/standard/core/DROP -; DROP x -- drop top of stack - MOV @PSP+,TOS ; 2 - MOV @IP+,PC ; 4 - - FORTHWORD "NIP" -; https://forth-standard.org/standard/core/NIP -; NIP x1 x2 -- x2 Drop the first item below the top of stack - ADD #2,PSP ; 1 - MOV @IP+,PC ; 4 +SWAP PUSH @PSP+ ; 3 - .IFNDEF OVER - FORTHWORD "OVER" -;https://forth-standard.org/standard/core/OVER -;C OVER x1 x2 -- x1 x2 x1 - MOV TOS,-2(PSP) ; 3 -- x1 (x2) x2 - MOV @PSP,TOS ; 2 -- x1 (x2) x1 - SUB #2,PSP ; 1 -- x1 x2 x1 +; https://forth-standard.org/standard/core/Rfrom +; R> -- x R: x -- pop from return stack +; VARIABLE run time called by CALL rDOVAR +RFROM SUB #2,PSP ; 1 + MOV TOS,0(PSP) ; 3 + MOV @RSP+,TOS ; 2 MOV @IP+,PC ; 4 - .ENDIF - FORTHWORD "ROT" -;https://forth-standard.org/standard/core/ROT -;C ROT x1 x2 x3 -- x2 x3 x1 - MOV @PSP,W ; 2 fetch x2 - MOV TOS,0(PSP) ; 3 store x3 - MOV 2(PSP),TOS ; 3 fetch x1 - MOV W,2(PSP) ; 3 store x2 +; https://forth-standard.org/standard/core/DUP +; DUP x -- x x duplicate top of stack +DUP MOV TOS,-2(PSP) ; 3 +POSTDECR SUB #2,PSP ; 1 post decrement stack... MOV @IP+,PC ; 4 - FORTHWORD "DEPTH" - .ENDIF ; https://forth-standard.org/standard/core/DEPTH ; DEPTH -- +n number of items on stack, must leave 0 if stack empty DEPTH MOV TOS,-2(PSP) MOV #PSTACK,TOS SUB PSP,TOS ; PSP-S0--> TOS RRA TOS ; TOS/2 --> TOS - SUB #2,PSP ; post decrement stack... - MOV @IP+,PC - - .IFDEF CORE_COMPLEMENT - FORTHWORD "R@" -;https://forth-standard.org/standard/core/RFetch -;C R@ -- x R: x -- x fetch from rtn stk - SUB #2,PSP - MOV TOS,0(PSP) - MOV @RSP,TOS - MOV @IP+,PC + JMP POSTDECR - FORTHWORD ">R" -; https://forth-standard.org/standard/core/toR -; >R x -- R: -- x push to return stack -TOR PUSH TOS - MOV @PSP+,TOS - MOV @IP+,PC - - FORTHWORD "R>" -; https://forth-standard.org/standard/core/Rfrom -; R> -- x R: x -- pop from return stack - SUB #2,PSP ; 1 - MOV TOS,0(PSP) ; 3 - MOV @RSP+,TOS ; 2 - MOV @IP+,PC ; 4 - - .ENDIF ;------------------------------------------------------------------------------- ; ARITHMETIC OPERATIONS ;------------------------------------------------------------------------------- - .IFDEF CORE_COMPLEMENT - FORTHWORD "1+" -; https://forth-standard.org/standard/core/OnePlus -; 1+ n1/u1 -- n2/u2 add 1 to TOS - ADD #1,TOS - MOV @IP+,PC - - FORTHWORD "1-" -; https://forth-standard.org/standard/core/OneMinus -; 1- n1/u1 -- n2/u2 subtract 1 from TOS - SUB #1,TOS - MOV @IP+,PC - - FORTHWORD "+" -;https://forth-standard.org/standard/core/Plus -;C + n1/u1 n2/u2 -- n3/u3 add n1+n2 - ADD @PSP+,TOS - MOV @IP+,PC - - FORTHWORD "-" - .ENDIF ; https://forth-standard.org/standard/core/Minus ; - n1/u1 n2/u2 -- n3/u3 n3 = n1-n2 MINUS SUB @PSP+,TOS ;2 -- n2-n1 @@ -965,18 +631,6 @@ STORE MOV @PSP+,0(TOS);4 ;------------------------------------------------------------------------------- ; COMPARAISON OPERATIONS ;------------------------------------------------------------------------------- - .IFDEF CORE_COMPLEMENT - FORTHWORD "0=" - .ENDIF -; https://forth-standard.org/standard/core/ZeroEqual -; 0= n/u -- flag return true if TOS=0 -ZEROEQUAL SUB #1,TOS ;1 borrow (clear cy) if TOS was 0 - SUBC TOS,TOS ;1 TOS=-1 if borrow was set - MOV @IP+,PC ;4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "0<" - .ENDIF ; https://forth-standard.org/standard/core/Zeroless ; 0< n -- flag true if TOS negative ZEROLESS ADD TOS,TOS ;1 set carry if TOS negative @@ -984,49 +638,40 @@ ZEROLESS ADD TOS,TOS ;1 set carry if TOS negative INVERT XOR #-1,TOS ;1 TOS=-1 if carry was set MOV @IP+,PC ; - .IFDEF CORE_COMPLEMENT - FORTHWORD "U<" - .ENDIF -; https://forth-standard.org/standard/core/Uless -; U< u1 u2 -- flag test u1<u2, unsigned -ULESS SUB @PSP+,TOS ;2 - JZ ULESSEND ;2 flag Z = 1 - MOV #-1,TOS ;1 flag Z = 0 - JC ULESSEND ;2 unsigned jump - AND #0,TOS ;1 flag Z = 1 -ULESSEND MOV @IP+,PC ;4 - - .IFDEF CORE_COMPLEMENT - FORTHWORD "=" -; https://forth-standard.org/standard/core/Equal -; = x1 x2 -- flag test x1=x2 -EQUAL SUB @PSP+,TOS ;2 - JZ INVERT ;2 flag Z will be = 0 - AND #0,TOS ;1 flag Z = 1 - MOV @IP+,PC ;4 +; FORTHWORD "U>" +; https://forth-standard.org/standard/core/Umore +; U> n1 n2 -- flag +UMORE SUB @PSP+,TOS ;2 + JNC UMOREEND ; 2 flag = true, Z = 0 + AND #0,TOS ; 1 flag = false,Z = 1 +UMOREEND MOV @IP+,PC ; 4 - FORTHWORD "<" -;https://forth-standard.org/standard/core/less -;C < n1 n2 -- flag test n1<n2, signed - SUB @PSP+,TOS ;1 TOS=n2-n1 - JZ LESSEND ;2 flag Z = 1 - JL TOSFALSE ;2 signed jump -TOSTRUE MOV #-1,TOS ;1 flag Z = 0 -LESSEND MOV @IP+,PC ;4 - - FORTHWORD ">" -;https://forth-standard.org/standard/core/more -;C > n1 n2 -- flag test n1>n2, signed - SUB @PSP+,TOS ;2 TOS=n2-n1 - JL TOSTRUE ;2 --> +5 -TOSFALSE AND #0,TOS ;1 flag Z = 1 - MOV @IP+,PC ;4 +; ------------------------------------------------------------------------------ +; STRINGS PROCESSING +; ------------------------------------------------------------------------------ + FORTHWORDIMM "S\34" ; immediate +; https://forth-standard.org/standard/core/Sq +; S" -- compile in-line string +SQUOTE MOV #0,&CAPS ; CAPS OFF + mDOCOL + .word lit,XSQUOTE,COMMA + .word lit,'"',WORDD ; -- c-addr = HERE W=Count_of_chars + mNEXTADR ; + MOV #20h,&CAPS ; restore CAPS ON + ADD #1,W ; + BIT #1,W ;1 C = /Z + ADDC W,&DP ; DP is aligned +DROPEXIT MOV @PSP+,TOS ; -- + MOV @RSP+,IP + MOV @IP+,PC -;------------------------------------------------------------------------------- -; CORE ANS94 complement OPTION -;------------------------------------------------------------------------------- - .include "ADDON/CORE_ANS.asm" - .ENDIF ; CORE_COMPLEMENT + FORTHWORDIMM ".\34" ; immediate +; https://forth-standard.org/standard/core/Dotq +; ." -- compile string to print +DOTQUOTE mDOCOL + .word SQUOTE + .word lit,TYPE,COMMA + .word EXIT ;------------------------------------------------------------------------------- ; NUMERIC OUTPUT @@ -1043,40 +688,39 @@ LESSNUM MOV #HOLD_BASE,&HP FORTHWORD "#" ; https://forth-standard.org/standard/core/num ; # ud1lo ud1hi -- ud2lo ud2hi convert 1 digit of output -NUM MOV &BASE,T ;3 T = Divisor -NUM1 MOV @PSP,S ;2 -- DVDlo DVDhi S = DVDlo - SUB #2,PSP ;1 -- x x DVDhi TOS = DVDhi - CALL #MUSMOD1 ;4 -- REMlo QUOTlo QUOThi T is unchanged - MOV @PSP+,0(PSP) ;4 -- QUOTlo QUOThi -TODIGIT CMP.B #10,W ;2 W = REMlo +NUM MOV &BASEADR,T ;3 +NUM1 MOV @PSP,S ;2 -- DVDlo DVDhi S = DVDlo + SUB #2,PSP ;1 -- x x DVDhi TOS = DVDhi + CALL #MUSMOD1 ;244/444 -- REMlo QUOTlo QUOThi T is unchanged W=REMlo X=QUOTlo Y=QUOThi + MOV @PSP+,0(PSP) ;4 -- QUOTlo QUOThi W = REMlo +TODIGIT CMP.B #10,W ;2 JNC TODIGIT1 ;2 jump if U< ADD.B #7,W ;2 TODIGIT1 ADD.B #30h,W ;2 -HOLDW SUB #1,&HP ;4 store W=char --> -[HP] +HOLDW SUB #1,&HP ;3 store W=char --> -[HP] MOV &HP,Y ;3 MOV.B W,0(Y) ;3 - MOV @IP+,PC ;4 23 words + MOV @IP+,PC ;4 22 words, about 276|476 cycles for u|ud one digit FORTHWORD "#S" ; https://forth-standard.org/standard/core/numS ; #S udlo udhi -- 0 0 convert remaining digits NUMS mDOCOL .word NUM ; X=QUOTlo -NUM_RETURN .word $+2 ; next adr + mNEXTADR ; next adr SUB #2,IP ;1 restore NUM return - CMP #0,X ;1 test ud2lo first (generally <>0) - JNZ NUM1 ;2 - CMP #0,TOS ;1 then test ud2hi (generally =0) + BIS TOS,X ;1 + CMP #0,X ;1 ud = 0 ? JNZ NUM1 ;2 -EXIT MOV @RSP+,IP - MOV @IP+,PC ;6 10 words, about 241/417 cycles/char +EXIT MOV @RSP+,IP ;2 when DTC=2 rDOCOL is loaded with this EXIT address + MOV @IP+,PC ;4 10 words, about 294|494 cycles for u|ud one digit FORTHWORD "#>" ; https://forth-standard.org/standard/core/num-end -; #> udlo:udhi -- c-addr u end conversion, get string -NUMGREATER MOV &HP,0(PSP) - MOV #HOLD_BASE,TOS - SUB @PSP,TOS +; #> udlo:udhi -- addr u end conversion, get string +NUMGREATER MOV &HP,0(PSP) ; -- addr 0 + MOV #HOLD_BASE,TOS ; + SUB @PSP,TOS ; -- addr u MOV @IP+,PC FORTHWORD "HOLD" @@ -1099,158 +743,130 @@ SIGN CMP #0,TOS ; https://forth-standard.org/standard/core/Ud ; U. u -- display u (unsigned) ; note: DDOT = UDOT + 10 -UDOT MOV #0,Y ; 1 +; use enhanced MUSMOD with 16 bits dividend instead of 32. +UDOT MOV #0,S ; 1 -- hi=0 DOTTODDOT SUB #2,PSP ; 1 convert n|u to d|ud with Y = -1|0 - MOV TOS,0(PSP) ; 3 - MOV Y,TOS ; 1 -DDOT PUSH IP ; paired with EXIT R-- IP - PUSH TOS ; paired with RFROM R-- IP sign + MOV TOS,0(PSP) ; 3 -- lo lo + MOV S,TOS ; 1 -- lo hi +DDOT PUSHM #2,IP ; 4 R-- IP sign AND #-1,TOS ; clear V, set N - JGE DDOTNEXT ; if positive (N=0) + JGE DDOTNEXT ; if hi positive (N=0) XOR #-1,0(PSP) ;4 XOR #-1,TOS ;1 ADD #1,0(PSP) ;4 ADDC #0,TOS ;1 -DDOTNEXT ASMTOFORTH ;10 - .word LESSNUM,NUMS - .word RFROM,SIGN,NUMGREATER,TYPE - .word FBLANK,EMIT,EXIT +DDOTNEXT mASM2FORTH ;10 + .word LESSNUM + .word BL,HOLD ; add a trailing space + .word NUMS ; R-- IP sign + .word RFROM,SIGN ; R-- IP + .word NUMGREATER,TYPE + .word EXIT FORTHWORD "." ; https://forth-standard.org/standard/core/d ; . n -- display n (signed) DOT CMP #0,TOS JGE UDOT - MOV #-1,Y + MOV #-1,S JMP DOTTODDOT -; ------------------------------------------------------------------------------ -; STRINGS PROCESSING -; ------------------------------------------------------------------------------ - FORTHWORDIMM "S\34" ; immediate -; https://forth-standard.org/standard/core/Sq -; S" -- compile in-line string -SQUOTE MOV #0,&CAPS ; CAPS OFF - mDOCOL - .word lit,XSQUOTE,COMMA -SQUOTE1 .word lit,'"' ; separator for WORD - .word WORDD ; -- c-addr (= HERE) - .word $+2 - MOV #32,&CAPS ; CAPS ON - MOV.B @TOS,TOS ; -- u - ADD #1,TOS ; -- u+1 - BIT #1,TOS ;1 C = ~Z - ADDC TOS,&DDP -DROPEXIT MOV @PSP+,TOS - MOV @RSP+,IP - MOV @IP+,PC - - FORTHWORDIMM ".\34" ; immediate -; https://forth-standard.org/standard/core/Dotq -; ." -- compile string to print -DOTQUOTE mDOCOL - .word SQUOTE - .word lit,TYPE,COMMA,EXIT - ;------------------------------------------------------------------------------- ; INTERPRETER ;------------------------------------------------------------------------------- FORTHWORD "WORD" ; https://forth-standard.org/standard/core/WORD ; WORD char -- addr Z=1 if len=0 -; parse a word delimited by char separator; by default (CAPS=$20), this word is capitalized. -; if first char is TICK, the entire word is not capitalized. -WORDD MOV #SOURCE_LEN,S ;2 -- separator - MOV @S+,X ;2 X = src_len - MOV @S+,W ;2 W = src_org - ADD W,X ;1 X = src_end - ADD @S+,W ;2 W = src_org + >IN = src_ptr - MOV @S,Y ;2 Y = HERE = dst_ptr -SKIPCHARLOO CMP W,X ;1 src_ptr = src_end ? - JZ SKIPCHAREND ;2 if yes : End Of Line ! - CMP.B @W+,TOS ;2 does char = separator ? - JZ SKIPCHARLOO ;2 if yes; 7~ loop - SUB #1,W ;1 move back one the (post incremented) pointer -SCANWORD MOV #96,T ;2 T = 96 = ascii(a)-1 (test value set in a register before SCANWORD loop) - MOV &CAPS,rDODOES ;3 CAPS OFF = 0, CAPS ON = $20. -QSCANTICK CMP.B #27h,0(W) ;4 first char = TICK ? - JNZ SCANWORDLOO ;2 no - MOV #0,rDODOES ;1 yes, don't change to upper case -SCANWORDLOO MOV.B S,0(Y) ;3 first time make room in dst for word length; next, put char @ dst. - CMP W,X ;1 src_ptr = src_end ? - JZ SCANWORDEND ;2 if yes - MOV.B @W+,S ;2 - CMP.B S,TOS ;1 does char = separator ? - JZ SCANWORDEND ;2 if yes - ADD #1,Y ;1 increment dst just before test loop - CMP.B S,T ;1 char U< 'a' ? ('a'-1 U>= char) this condition is tested at each loop - JC SCANWORDLOO ;2 15~ upper case char loop - CMP.B #123,S ;2 char U>= 'z'+1 ? - JC SCANWORDLOO ;2 loopback if yes - SUB.B rDODOES,S ;1 convert a...z to A...Z if CAPS ON (rDODOES=$20) - JMP SCANWORDLOO ;2 22~ lower case char loop -SCANWORDEND MOV #XDODOES,rDODOES ;2 -SKIPCHAREND SUB &SOURCE_ORG,W ;3 -- separator W=src_ptr - src_org = new >IN (first char separator next) - MOV W,&TOIN ;3 update >IN - MOV &DDP,TOS ;3 -- c-addr - SUB TOS,Y ;1 Y=Word_Length - MOV.B Y,0(TOS) ;3 - MOV @IP+,PC ;4 -- c-addr 48 words Z=1 <==> lenght=0 <==> EOL, Z is tested by INTERPRET - - FORTHWORD "FIND" ; +; parse a word delimited by char separator +; if CAPS is ON, this word is CAPITALIZED unless 'char' input. +; notice that the average lenght of all CORE definitions is about 4. +WORDD MOV #SOURCE_LEN,S ;2 -- sep + MOV @S+,X ;2 X = src_len + MOV @S+,Y ;2 Y = src_org + ADD Y,X ;1 X = src_len + src_org = src_end + ADD @S+,Y ;2 Y = >IN + src_org = src_ptr + MOV @S,W ;2 W = HERE = dst_ptr +SKIPCHARLOO CMP Y,X ;1 src_ptr = src_end ? + JZ SKIPCHAREND ;2 if yes : End Of Line ! + CMP.B @Y+,TOS ;2 does char = separator ? + JZ SKIPCHARLOO ;2 if yes; 7~ loop + SUB #1,Y ;1 decrement the post incremented src_ptr +QSCANTICK MOV &CAPS,T ;3 CAPS OFF = 0, CAPS ON = $20. + CMP.B #"'",0(Y) ;4 first char = TICK ? + JNZ SCANWORDLOO ;2 no + CMP.B @Y,2(Y) ;3 third char = TICK ? + JNZ SCANWORDLOO ;2 no + MOV #0,T ;1 don't change to upper case for 'char' input +SCANWORDLOO MOV.B S,0(W) ;3 first, S makes room in dst for word length; next, put char. + CMP Y,X ;1 src_ptr = src_end ? + JZ SCANWORDEND ;2 if yes + MOV.B @Y+,S ;2 S=char + CMP.B S,TOS ;1 -- sep does char = separator ? + JZ SCANWORDEND ;2 if yes + ADD #1,W ;1 increment dst just before test loop + CMP.B #'a',S ;2 char U< 'a' ? this condition is tested at each loop + JNC SCANWORDLOO ;2 16~ upper case char loop + CMP.B #'z'+1,S ;2 char U>= 'z'+1 ? + JC SCANWORDLOO ;2 U>= loopback if yes + SUB.B T,S ;1 convert a...z to A...Z if CAPS ON (T=$20) + JMP SCANWORDLOO ;2 23~ lower case char loop +SCANWORDEND +SKIPCHAREND SUB &SOURCE_ORG,Y ;3 -- sep Y=src_ptr - src_org = new >IN (first char separator next) + MOV Y,&TOIN ;3 update >IN + MOV &DP,TOS ;3 -- c-addr + SUB TOS,W ;1 W=Word_Length + MOV.B W,0(TOS) ;3 + MOV @IP+,PC ;4 -- c-addr 48 words Z=1 <==> lenght=0 <==> EOL, Z is tested by INTERPRET + + FORTHWORD "FIND" ; ; https://forth-standard.org/standard/core/FIND -; FIND c-addr -- c-addr 0 if not found ; flag Z=1 c-addr at transient RAM area (HERE) +; FIND c-addr -- c-addr 0 if not found ; flag Z=1 c-addr at transient RAM area (HERE) ; CFA -1 if found ; flag Z=0 ; CFA 1 if immediate ; flag Z=0 ; compare WORD at c-addr (HERE) with each of words in each of listed vocabularies in CONTEXT -; FIND to WORDLOOP : 14/20 cycles, -; mismatch word loop: 13 cycles on len, +7 cycles on first char, +; FIND to WORDLOOP : 10/17 cycles, +; mismatch word loop: 14 cycles on len, 21 cycles on first char, ; +10 cycles char loop, -; VOCLOOP : 12/18 cycles, -; WORDFOUND to end : 21 cycles. +; WORDFOUND to end : 16 cycles. ; note: with 16 threads vocabularies, FIND takes only! 75% of CORETEST.4th processing time -FIND SUB #2,PSP ;1 -- ???? c-addr reserve one cell, not at FINDEND because kill flag Z - MOV TOS,S ;1 S=c-addr - MOV.B @S,rDOCON ;2 rDOCON= string count - MOV.B #80h,rDODOES ;2 rDODOES= immediate mask - MOV #CONTEXT,T ;2 -VOCLOOP MOV @T+,TOS ;2 -- ???? VOC_PFA T=CTXT+2 - CMP #0,TOS ;1 no more vocabulary in CONTEXT ? - JZ FINDEND ;2 -- ???? 0 yes ==> exit; Z=1 +FIND SUB #2,PSP ;1 -- ???? c-addr reserve one cell, not at FINDEND which would kill the Z flag + MOV TOS,S ;1 S=c-addr + MOV #CONTEXT,T ;2 T = first cell addr of CONTEXT stack +VOCLOOP MOV @T+,TOS ;2 -- ???? VOC_PFA T=CTXT+2 + CMP #0,TOS ;1 no more vocabulary in CONTEXT ? + JZ FINDEND ;2 -- ???? 0 yes ==> exit; Z=1 .SWITCH THREADS - .CASE 1 - .ELSECASE ; search thread add 6cycles 5words - MOV.B 1(S),Y ;3 -- ???? VOC_PFA0 S=c-addr Y=first char of c-addr string - AND.B #(THREADS-1)*2,Y ;2 -- ???? VOC_PFA0 Y=thread offset - ADD Y,TOS ;1 -- ???? VOC_PFAx TOS = words set entry + .CASE 1 ; nothing to do + .ELSECASE ; searching thread adds 7 cycles & 6 words + MOV.B 1(S),Y ;3 -- ???? VOC_PFA0 S=c-addr Y=first char of c-addr string + AND.B #(THREADS-1),Y;2 -- ???? VOC_PFA0 Y=thread_x + ADD Y,Y ;1 -- ???? VOC_PFA0 Y=thread_offset_x + ADD Y,TOS ;1 -- ???? VOC_PFAx TOS = words set entry .ENDCASE - ADD #2,TOS ;1 -- ???? VOC_PFA+2 -WORDLOOP MOV -2(TOS),TOS ;3 -- ???? NFA [VOC_PFA] first, then [LFA] - CMP #0,TOS ;1 -- ???? NFA no more word in the thread ? - JZ VOCLOOP ;2 -- ???? NFA yes ==> search next voc in context - MOV TOS,X ;1 - MOV.B @X+,Y ;2 TOS=NFA,X=NFA+1,Y=NFA_char - BIC.B rDODOES,Y ;1 hide Immediate bit -LENCOMP CMP.B rDOCON,Y ;1 compare lenght - JNZ WORDLOOP ;2 -- ???? NFA 13~ word loop on lenght mismatch - MOV S,W ;1 W=c-addr -CHARCOMP CMP.B @X+,1(W) ;4 compare chars - JNZ WORDLOOP ;2 -- ???? NFA 20~ word loop on first char mismatch - ADD #1,W ;1 - SUB.B #1,Y ;1 decr count - JNZ CHARCOMP ;2 -- ???? NFA 10~ char loop - -WORDFOUND BIT #1,X ;1 - ADDC #0,X ;1 - MOV X,S ;1 S=aligned CFA - CMP.B #0,0(TOS) ;3 -- ???? NFA 0(TOS)=NFA_first_char - MOV #1,TOS ;1 -- ???? 1 preset immediate flag - JN FINDEND ;2 -- ???? 1 jump if negative: NFA have immediate bit set - SUB #2,TOS ;1 -- ???? -1 -FINDEND MOV S,0(PSP) ;3 not found: -- c-addr 0 flag Z=1 - MOV #xdocon,rDOCON ;2 found: -- xt -1|+1 (not immediate|immediate) flag Z=0 - MOV #xdodoes,rDODOES ;2 - MOV @IP+,PC ;4 42/47 words + ADD #2,TOS ;1 -- ???? VOC_PFAx+2 +WORDLOOP MOV -2(TOS),TOS ;3 -- ???? NFA -2(TOS) = [VOC_PFAx] first, then [LFA] + CMP #0,TOS ;1 -- ???? NFA no more word in the thread ? + JZ VOCLOOP ;2 -- ???? NFA yes ==> search next voc in context + MOV TOS,X ;1 + MOV.B @X+,Y ;2 TOS = NFA, X= NFA+1, Y = NFA_first_byte = cnt<<2+i (i= immediate flag) + RRA.B Y ;1 remove immediate flag, the remainder is the count of the definition name. +LENCOMP CMP.B @S,Y ;2 compare lenght + JNZ WORDLOOP ;2 -- ???? NFA 14~ word loop on lenght mismatch + MOV S,W ;1 S=W=c-addr +CHARCOMP CMP.B @X+,1(W) ;4 compare chars + JNZ WORDLOOP ;2 -- ???? NFA 21~ word loop on first char mismatch + ADD #1,W ;1 + SUB.B #1,Y ;1 decr count + JNZ CHARCOMP ;2 -- ???? NFA 10~ char loop +WORDFOUND BIT #1,X ;1 + ADDC #0,X ;1 + MOV X,S ;1 S=aligned CFA + MOV.B @TOS,TOS ;2 -- ???? NFA_1st_byte + AND #1,TOS ;1 -- ???? 0|1 test immediate flag + JNZ FINDEND ;2 -- ???? 1 jump if bit 1 is set, as immediate bit + SUB #1,TOS ;1 -- ???? -1 +FINDEND MOV S,0(PSP) ;3 not found: -- c-addr 0 flag Z=1 + MOV @IP+,PC ;4 34/40 words .IFDEF MPY_32 ; if 32 bits hardware multiplier @@ -1258,247 +874,243 @@ FINDEND MOV S,0(PSP) ;3 not found: -- c-addr 0 ; >NUMBER ud1lo ud1hi addr1 cnt1 -- ud2lo ud2hi addr2 cnt2 ; https://forth-standard.org/standard/core/toNUMBER ; ud2 is the unsigned result of converting the characters within the string specified by c-addr1 u1 into digits, -; using the number in BASE, and adding each into ud1 after multiplying ud1 by the number in BASE. +; using the number in BASE, and adding each into ud1 after multiplying ud1 by the number in BASE. ; Conversion continues left-to-right until a character that is not convertible (including '.' ',' '_') ; is encountered or the string is entirely converted. c-addr2 is the location of the first unconverted character ; or the first character past the end of the string if the string was entirely converted. -; u2 is the number of unconverted characters in the string. +; cnt2 is the number of unconverted characters in the string. ; An ambiguous condition exists if ud2 overflows during the conversion. -TONUMBER MOV @PSP+,S ;2 -- ud1lo ud1hi cnt1 S = addr1 - MOV @PSP+,Y ;2 -- ud1lo cnt1 Y = ud1hi - MOV @PSP,X ;2 -- x cnt1 X = ud1lo - SUB #4,PSP ;1 -- x x x cnt - MOV &BASE,T ;3 -TONUMLOOP MOV.B @S,W ;2 -- x x x cnt S=adr, T=base, W=char, X=udlo, Y=udhi -DDIGITQ SUB.B #30h,W ;2 skip all chars < '0' - CMP.B #10,W ;2 char was U< 58 (U< ':') ? - JNC DDIGITQNEXT ;2 no - SUB.B #7,W ;2 - CMP.B #10,W ;2 - JNC TONUMEND ;2 -- x x x cnt if '9' < char < 'A', then return to QNUMBER with Z=0 -DDIGITQNEXT CMP T,W ;1 digit-base - BIC #Z,SR ;1 reset Z before return to QNUMBER because - JC TONUMEND ;2 with Z=1, QNUMBER conversion would be true :-( -UDSTAR MOV X,&MPY32L ;3 Load 1st operand (ud1lo) - MOV Y,&MPY32H ;3 Load 1st operand (ud1hi) - MOV T,&OP2 ;3 Load 2nd operand with BASE - MOV &RES0,X ;3 lo result in X (ud2lo) - MOV &RES1,Y ;3 hi result in Y (ud2hi) -MPLUS ADD W,X ;1 ud2lo + digit - ADDC #0,Y ;1 ud2hi + carry -TONUMPLUS ADD #1,S ;1 adr+1 - SUB #1,TOS ;1 -- x x x cnt cnt-1 - JNZ TONUMLOOP ;2 if count <>0 -TONUMEND MOV S,0(PSP) ;3 -- x x addr2 cnt2 - MOV Y,2(PSP) ;3 -- x ud2hi addr2 cnt2 - MOV X,4(PSP) ;3 -- ud2lo ud2hi addr2 cnt2 - MOV @IP+,PC ;4 42 words +TONUMBER MOV &BASEADR,T ;3 T = base + MOV @PSP+,S ;2 -- ud1lo ud1hi cnt1 S = addr1 + MOV @PSP+,Y ;2 -- ud1lo cnt1 Y = ud1hi + MOV @PSP,X ;2 -- x cnt1 X = ud1lo + SUB #4,PSP ;1 -- x x x cnt1 +TONUMLD_OP1 MOV T,&MPY ;3 base = MPY OP1 loaded out of TONUMLOOP +TONUMLOOP MOV.B @S,W ;2 -- x x x cnt S=adr, T=base, W=char, X=udlo, Y=udhi +DDIGITQ SUB.B #3Ah,W ;2 all Ctrl_Chars < '0' and all chars '0' to '9' become negative + JNC DDIGITQNEXT ;2 accept all chars U< ':' (accept $0 up to $39) + SUB.B #7,W ;2 W = char - ($3A + $07 = 'A') + JNC TONUMEND ;2 -- x x x cnt reject all Ctrl_Chars U< 'A', (with Z flag = 0) +DDIGITQNEXT ADD.B #0Ah,W ;2 restore digit value: 0 to 15 (and beyond) + CMP T,W ;1 digit-base (U>= comparaison rejects all Ctrl_Chars) + BIC #Z,SR ;1 reset Z before return to QNUMBER because else + JC TONUMEND ;2 to avoid QNUMBER conversion true with digit=base :-( +UDSTAR MOV X,&OP2L ;3 Load 2nd operand (ud1lo) + MOV Y,&OP2H ;3 Load 2nd operand (ud1hi) + MOV &RES0,X ;3 lo result in X (ud2lo) + MOV &RES1,Y ;3 hi result in Y (ud2hi) +MPLUS ADD W,X ;1 ud2lo + digit + ADDC #0,Y ;1 ud2hi + carry +TONUMPLUS ADD #1,S ;1 adr+1 + SUB #1,TOS ;1 -- x x x cnt cnt-1 + JNZ TONUMLOOP ;2 if count <>0 33~ loop +TONUMEND MOV S,0(PSP) ;3 -- x x addr2 cnt2 + MOV Y,2(PSP) ;3 -- x ud2hi addr2 cnt2 + MOV X,4(PSP) ;3 -- ud2lo ud2hi addr2 cnt2 + MOV @IP+,PC ;4 40 words ; ?NUMBER makes the interface between INTERPRET and >NUMBER; it's a subset of INTERPRET. ; convert a string to a signed number; FORTH 2012 prefixes $ % # are recognized, ; FORTH 2012 'char' numbers also, digits separator '_' also. -; with DOUBLE_INPUT switched ON, 32 bits signed numbers (with decimal point) are recognized, -; with FIXPOINT_INPUT switched ON, Q15.16 signed numbers (with comma) are recognized. +; with DOUBLE_INPUT option, 32 bits signed numbers (with decimal point) are recognized, +; with FIXPOINT_INPUT option, Q15.16 signed numbers (with comma) are recognized. ; prefixes ' # % $ - are processed before calling >NUMBER ; chars . , _ are processed as >NUMBER exits. ;Z ?NUMBER addr -- n|d -1 if convert ok ; flag Z=0, UF9=1 if double ;Z addr -- addr 0 if convert ko ; flag Z=1 -QNUMBER - .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT - BIC #UF9,SR ;2 reset UF9 used as double number flag - .ENDIF ; - MOV &BASE,T ;3 T=BASE - MOV #0,S ;1 S=sign of result - PUSHM #3,IP ;5 R-- IP sign base PUSH IP,S,T - MOV #TONUMEXIT,IP ;2 set TONUMEXIT as return from >NUMBER - MOV #0,X ;1 X=ud1lo - MOV #0,Y ;1 Y=ud1hi - SUB #8,PSP ;1 -- x x x x addr make room for TOS and >NUMBER - MOV TOS,6(PSP) ;3 -- addr x x x addr - MOV TOS,S ;1 S=addr - MOV.B @S+,TOS ;2 -- addr x x x cnt TOS=count -QTICK CMP.B #027h,0(S) ;4 prefix = ' ? - JNZ QNUMLDCHAR ;2 no - MOV.B 1(S),S ;3 - MOV S,4(PSP) ;3 -- addr ud2lo x x cnt ud2lo = ASCII code of 'char' - CMP.B #3,TOS ;2 string must be 3 chars long - JMP QNUMNEXT ;2 -QNUMLDCHAR MOV.B @S,W ;2 W=char -QMINUS SUB.B #'-',W ;2 sign minus ? - JNC QBINARY ;2 jump if char < '-' - JNZ TONUMLOOP ;2 -- addr x x x cnt jump if char > '-' - MOV #-1,2(RSP) ;3 R-- IP sign base set sign flag - JMP PREFIXED ;2 -QBINARY MOV #2,T ;1 preset base 2 - ADD.B #8,W ;1 binary '%' prefix ? - JZ PREFIXED ;2 yes -QDECIMAL ADD #8,T ;1 preset base 10 - ADD.B #2,W ;1 decimal '#' prefix ? - JZ PREFIXED ;2 yes -QHEXA MOV #16,T ;2 preset base 16 - ADD.B #-1,W ;1 hex '$' prefix ? - JNZ QNUMNEXT ;2 -- addr x x x cnt abort if not recognized prefix -PREFIXED ADD #1,S ;1 - SUB #1,TOS ;1 -- addr x x x cnt-1 S=adr+1 TOS=count-1 - JMP QNUMLDCHAR ;2 -; ----------------------------------; - -TONUMEXIT .word $+2 ; -- addr ud2lo-hi addr2 cnt2 R-- IP sign BASE S=addr2 -; ----------------------------------; - JZ QNUMNEXT ;2 TOS=cnt2, Z=1 if conversion is ok -; ----------------------------------; - SUB #2,IP ; redefines TONUMEXIT as >NUMBER return, if loopback applicable - CMP.B #28h,W ; rejected char by >NUMBER is a underscore ? ('_'-30h-7 = 28h) - JZ TONUMPLUS ; yes: loopback to >NUMBER to skip char -; ----------------------------------; - .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT - BIT #UF9,SR ; UF9 already set ? ( when you have typed .. ) - JNZ QNUMNEXT ; yes, goto QNUMKO - BIS #UF9,SR ;2 set double number flag +QNUMBER ; -- addr + .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT + BIC #UF9,SR ;2 reset UserFlag_9 used as double number flag + .ENDIF ; + SUB #8,PSP ;1 -- x x x x addr make room for >NUMBER + MOV TOS,6(PSP) ;3 -- addr x x x addr save TOS + MOV #0,Y ;1 Y=ud1hi=0 + MOV #0,X ;1 X=ud1lo=0 + MOV &BASEADR,T ;3 T=BASE + MOV TOS,S ;1 S=addr + MOV #0,TOS ;1 TOS=sign of result + PUSHM #2,TOS ;4 R-- sign IP PUSH TOS,IP + MOV #TONUMEXIT,IP ;2 set TONUMEXIT as return from >NUMBER + MOV.B @S+,TOS ;2 -- addr x x x cnt TOS=count, S=addr+1 +QNUMLDCHAR MOV.B @S,W ;2 W=char + SUB.B #'-',W ;2 + JZ QNUMMINUS ;2 + JC TONUMLD_OP1 ;2 -- addr x x x cnt jump if char U> '-', case of numeric chars +QBINARY MOV #2,T ;1 preset base 2 + ADD.B #8,W ;1 binary '%' prefix ? '%' + 8 = '-' + JZ PREFIXNEXT ;2 yes +QDECIMAL ADD #8,T ;1 preset base 10 + ADD.B #2,W ;1 decimal '#' prefix ? '#' + 2 = '%' + JZ PREFIXNEXT ;2 yes +QHEXA MOV #16,T ;2 preset base 16 + CMP.B #1,W ;1 hex '$' prefix ? '#' + 1 = '$' + JZ PREFIXNEXT ;2 yes +QTICK CMP.B #4,W ;1 prefix = ' ? '#' + 4 = "'" + JNZ QNUMNEXT ;2 -- addr x x x cnt no, abort because prefix not recognized + CMP #3,TOS ;2 count = 3 ? + JNZ QNUMNEXT ;2 no, abort + CMP.B @S+,1(S) ;4 -- addr x x x 3 3rd char = 1st char = "'" ? + MOV.B @S,S ;2 does byte to word conversion + MOV S,4(PSP) ;3 -- addr ud2lo x x x ud2lo = ASCII code of 'char' + JMP QNUMNEXT ;2 -- addr ud2lo x x x with happy end if 3rd char = 1st char +QNUMMINUS MOV #-1,2(RSP) ;3 R-- sign IP set sign flag +PREFIXNEXT SUB #1,TOS ;1 -- addr x x x cnt-1 TOS=count-1 + CMP.B @S+,0(S) ;4 S=adr+1; same prefix ? + JNZ QNUMLDCHAR ;2 loopback if no + JZ TONUMLD_OP1 ;2 if yes, this 2nd prefix will be rejected by >NUMBER +; ------------------------------;46 +TONUMEXIT mNEXTADR ; -- addr ud2lo-hi addr2 cnt2 R-- IP sign BASE S=addr2 + JZ QNUMNEXT ;2 TOS=0 and Z=1 if conversion is ok + SUB #2,IP ;1 redefines TONUMEXIT as >NUMBER return, if loopback applicable + MOV.B @S,W ;2 reload rejected char + CMP.B #'_',W ;2 rejected char by >NUMBER is a underscore ? + JZ TONUMPLUS ;2 yes: return to >NUMBER to skip char then resume conversion, 30~ loopback + .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT + BIT #UF9,SR ;2 UF9 already set ? ( if you have typed .. ) + JNZ QNUMNEXT ;2 yes, goto QNUMKO + BIS #UF9,SR ;2 set double number flag .ENDIF -; ----------------------------------; - .IFDEF DOUBLE_INPUT ; - CMP.B #0F7h,W ;2 rejected char by >NUMBER is a decimal point ? ('.'-37h = -9) - JZ TONUMPLUS ;2 yes, loopback to >NUMBER to skip char - .ENDIF ; -; ----------------------------------; - .IFDEF FIXPOINT_INPUT ; - CMP.B #0F5h,W ;2 rejected char by >NUMBER is a comma ? (','-37h = -0Bh) - JNZ QNUMNEXT ;2 no: with Z=0 ==> goto QNUMKO -; ----------------------------------; -S15Q16 MOV TOS,W ;1 -- addr ud2lo x x x W=cnt2 - MOV #0,X ;1 -- addr ud2lo x 0 x init X = ud2lo' = 0 -S15Q16LOOP MOV X,2(PSP) ;3 -- addr ud2lo ud2lo' ud2lo' x 0(PSP) = ud2lo' - SUB.B #1,W ;1 decrement cnt2 - MOV W,X ;1 X = cnt2-1 - ADD S,X ;1 X = end_of_string-1,-2,-3... - MOV.B @X,X ;2 X = last char of string first (reverse conversion) - SUB.B #30h,X ;2 char --> digit conversion - CMP.B #10,X ;2 - JNC QS15Q16DIGI ;2 if 0 <= digit < 10 - SUB.B #7,X ;2 char - CMP.B #10,X ;2 to skip all chars between "9" and "A" - JNC S15Q16EOC ;2 -QS15Q16DIGI CMP T,X ;1 R-- IP sign BASE is X a digit ? - JC S15Q16EOC ;2 -- addr ud2lo ud2lo' x ud2lo' if X>=base - MOV X,0(PSP) ;3 -- addr ud2lo ud2lo' digit x - MOV T,TOS ;1 -- addr ud2lo ud2lo' digit base R-- IP sign base - PUSHM #3,S ;5 PUSH S,T,W: R-- IP sign base addr2 base cnt2 - CALL #MUSMOD ;4 -- addr ud2lo ur uqlo uqhi CALL MU/MOD - POPM #3,S ;5 restore W,T,S: R-- IP sign BASE - JMP S15Q16LOOP ;2 W=cnt -S15Q16EOC MOV 4(PSP),2(PSP) ;5 -- addr ud2lo ud2hi uqlo x ud2lo from >NUMBER becomes here ud2hi part of Q15.16 - MOV @PSP,4(PSP) ;4 -- addr ud2lo ud2hi x x uqlo becomes ud2lo part of Q15.16 - CMP.B #0,W ;1 count = 0 if end of conversion ok - .ENDIF ; FIXPOINT_INPUT ; -; ----------------------------------; -QNUMNEXT POPM #3,IP ;5 -- addr ud2lo-hi x x POPM T,S,IP S = sign flag = {-1;0} - MOV S,TOS ;1 -- addr ud2lo-hi x sign - MOV T,&BASE ;3 - JZ QNUMOK ;2 -- addr ud2lo-hi x sign conversion OK if Z=1 -QNUMKO - .IFDEF DOUBLE_NUMBERS ; - BIC #UF9,SR ;2 reset flag UF9, before next use as double number flag + .IFDEF DOUBLE_INPUT ; + SUB.B #'.',W ;2 rejected char by >NUMBER is a decimal point ? + JZ TONUMPLUS ;2 yes, loopback to >NUMBER to skip char, 45~ loopback + .ENDIF ; + .IFDEF FIXPOINT_INPUT ; + .IFDEF DOUBLE_INPUT + ADD.B #2,W ;1 rejected char by >NUMBER is a comma ? (',' - '.' + 2 = 0) + .ELSE ; + CMP.B #',',W ;2 rejected char by >NUMBER is a comma ? + .ENDIF ; + JNZ QNUMNEXT ;2 no: with Z=0 ==> goto QNUMKO +S15Q16 MOV TOS,W ;1 -- addr ud2lo x x x W=cnt2 + MOV #0,X ;1 -- addr ud2lo x 0 x init X = ud2lo' = 0 +S15Q16LOOP MOV X,2(PSP) ;3 -- addr ud2lo ud2lo' 0 x 2(PSP) = ud2lo' + SUB.B #1,W ;1 decrement cnt2 + MOV W,X ;1 X = cnt2-1 + ADD S,X ;1 X = end_of_string-1,-2,-3... + MOV.B @X,X ;2 X = last char of string first (reverse conversion) + SUB.B #':',X ;2 + JNC QS15Q16DIGI ;2 accept all chars U< ':' + SUB.B #7,X ;2 + JNC S15Q16EOC ;2 reject all chars U< 'A' +QS15Q16DIGI ADD.B #10,X ;2 restore digit value + CMP T,X ;1 T=Base, is X a digit ? + JC S15Q16EOC ;2 -- addr ud2lo ud2lo' ud2lo' x if not a digit + MOV X,0(PSP) ;3 -- addr ud2lo ud2lo' digit x + MOV T,TOS ;1 -- addr ud2lo ud2lo' digit base R-- IP sign + PUSHM #3,S ;5 PUSH S,T,W: R-- IP sign addr2 base cnt2 + CALL #MUSMOD ;4 -- addr ud2lo ur uqlo uqhi CALL MU/MOD + POPM #3,S ;5 restore W,T,S: R-- IP sign + JMP S15Q16LOOP ;2 W=cnt +S15Q16EOC MOV 4(PSP),2(PSP) ;5 -- addr ud2lo ud2hi uqlo x ud2lo from >NUMBER becomes here ud2hi part of Q15.16 + MOV @PSP,4(PSP) ;4 -- addr ud2lo ud2hi x x uqlo becomes ud2lo part of Q15.16 + CMP.B #0,W ;1 count = 0 if end of conversion ok + .ENDIF ; FIXPOINT_INPUT +; ------------------------------; +QNUMNEXT POPM #2,TOS ;4 -- addr ud2lo-hi x sign R: -- POPM IP,TOS TOS = sign flag = {-1;0} + JZ QNUMOK ;2 -- addr ud2lo-hi x sign conversion OK if Z=1 +QNUMKO + .IFDEF DOUBLE_NUMBERS ; + BIC #UF9,SR ;2 reset flag UF9, before next use as double number flag .ENDIF - ADD #6,PSP ;1 -- addr sign - AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko - MOV @IP+,PC ;4 -; ----------------------------------; - .IFDEF DOUBLE_NUMBERS ; -- addr ud2lo-hi x sign -QNUMOK ADD #2,PSP ;1 -- addr ud2lo-hi sign - MOV 2(PSP),4(PSP) ;5 -- udlo udlo udhi sign - MOV @PSP+,0(PSP) ;4 -- udlo udhi sign note : PSP is incremented before write back. - XOR #-1,TOS ;1 -- udlo udhi inv(sign) - JNZ QDOUBLE ;2 if jump : TOS=-1 and Z=0 ==> conversion ok - XOR #-1,TOS ;1 -- udlo udhi tf -QDNEGATE XOR #-1,2(PSP) ;3 - XOR #-1,0(PSP) ;3 -- (dlo dhi)-1 tf - ADD #1,2(PSP) ;3 - ADDC #0,0(PSP) ;3 -QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point or comma fixpoint ? - JNZ QNUMEND ;2 leave double - ADD #2,PSP ;1 -- n tf leave number -QNUMEND MOV @IP+,PC ;4 TOS<>0 and Z=0 ==> conversion ok + ADD #6,PSP ;2 -- addr sign + AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko + MOV @IP+,PC ;4 +; ------------------------------; + .IFDEF DOUBLE_NUMBERS ; -- addr ud2lo-hi x sign +QNUMOK ADD #2,PSP ;1 -- addr ud2lo-hi sign + MOV 2(PSP),4(PSP) ;5 -- udlo udlo udhi sign + MOV @PSP+,0(PSP) ;4 -- udlo udhi sign note : PSP is incremented before write back. + XOR #-1,TOS ;1 -- udlo udhi inv(sign) + JNZ QDOUBLE ;2 -- udlo udhi tf if jump : TOS=-1 and Z=0 ==> conversion ok + XOR #-1,TOS ;1 -- udlo udhi tf +QDNEGATE XOR #-1,2(PSP) ;3 -- udlo udhi -1 + XOR #-1,0(PSP) ;3 -- (dlo dhi)-1 tf + ADD #1,2(PSP) ;3 + ADDC #0,0(PSP) ;3 +QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point or comma fixpoint ? + JNZ QNUMEND ;2 leave double +NIP ADD #2,PSP ;1 -- n tf leave number +QNUMEND MOV @IP+,PC ;4 TOS<>0 and Z=0 ==> conversion ok .ELSE -QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign - MOV @PSP+,0(PSP) ;4 -- udlo sign note : PSP is incremented before write back !!! - XOR #-1,TOS ;1 -- udlo inv(sign) - JNZ QNUMEND ;2 if jump : TOS=-1 and Z=0 ==> conversion ok - XOR #-1,TOS ;1 -- udlo tf TOS=-1 and Z=0 -QNEGATE XOR #-1,0(PSP) ;3 - ADD #1,0(PSP) ;3 -- n tf -QNUMEND MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok - .ENDIF ; DOUBLE_NUMBERS ; - - .ELSE ; no hardware MPY - +QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign + MOV @PSP,2(PSP) ;4 -- u u sign note : PSP is incremented before write back !!! + XOR #-1,TOS ;1 -- udlo udhi inv(sign) + JNZ QNUMEND ;2 -- udlo udhi tf if jump : TOS=-1 and Z=0 ==> conversion ok + XOR #-1,TOS ;1 -- udlo udhi sign +QNEGATE XOR #-1,2(PSP) ;3 + ADD #1,2(PSP) ;3 -- n u tf +QNUMEND +NIP ADD #2,PSP ;1 -- n tf + MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok + .ENDIF ; DOUBLE_NUMBERS ; + + .ELSE ; if no hardware MPY FORTHWORD "UM*" ; T.I. UNSIGNED MULTIPLY SUBROUTINE: U1 x U2 -> Ud ; https://forth-standard.org/standard/core/UMTimes ; UM* u1 u2 -- ud unsigned 16x16->32 mult. -UMSTAR MOV @PSP,S ;2 MDlo -UMSTAR1 MOV #0,T ;1 MDhi=0 - MOV #0,X ;1 RES0=0 - MOV #0,Y ;1 RES1=0 - MOV #1,W ;1 BIT TEST REGISTER -UMSTARLOOP BIT W,TOS ;1 TEST ACTUAL BIT MRlo - JZ UMSTARNEXT ;2 IF 0: DO NOTHING - ADD S,X ;1 IF 1: ADD MDlo TO RES0 - ADDC T,Y ;1 ADDC MDhi TO RES1 -UMSTARNEXT ADD S,S ;1 (RLA LSBs) MDlo x 2 - ADDC T,T ;1 (RLC MSBs) MDhi x 2 - ADD W,W ;1 (RLA) NEXT BIT TO TEST - JNC UMSTARLOOP ;2 IF BIT IN CARRY: FINISHED 10~ loop - MOV X,0(PSP) ;3 low result on stack - MOV Y,TOS ;1 high result in TOS - MOV @IP+,PC ;4 17 words +UMSTAR MOV @PSP,S ;2 MDlo +UMSTAR1 MOV #0,T ;1 MDhi=0 + MOV #0,X ;1 RES0=0 + MOV #0,Y ;1 RES1=0 + MOV #1,W ;1 BIT TEST REGISTER +UMSTARLOOP BIT W,TOS ;1 TEST ACTUAL BIT MRlo + JZ UMSTARNEXT ;2 IF 0: DO NOTHING + ADD S,X ;1 IF 1: ADD MDlo TO RES0 + ADDC T,Y ;1 ADDC MDhi TO RES1 +UMSTARNEXT ADD S,S ;1 (RLA LSBs) MDlo x 2 + ADDC T,T ;1 (RLC MSBs) MDhi x 2 + ADD W,W ;1 (RLA) NEXT BIT TO TEST + JNC UMSTARLOOP ;2 IF BIT IN CARRY: FINISHED 10~ loop + MOV X,0(PSP) ;3 low result on stack + MOV Y,TOS ;1 high result in TOS + MOV @IP+,PC ;4 17 words FORTHWORD ">NUMBER" ; https://forth-standard.org/standard/core/toNUMBER ; ud2 is the unsigned result of converting the characters within the string specified by c-addr1 u1 into digits, -; using the number in BASE, and adding each into ud1 after multiplying ud1 by the number in BASE. +; using the number in BASE, and adding each into ud1 after multiplying ud1 by the number in BASE. ; Conversion continues left-to-right until a character that is not convertible, including '.', ',' or '_', ; is encountered or the string is entirely converted. c-addr2 is the location of the first unconverted character ; or the first character past the end of the string if the string was entirely converted. ; u2 is the number of unconverted characters in the string. ; An ambiguous condition exists if ud2 overflows during the conversion. ; >NUMBER ud1lo|ud1hi addr1 count1 -- ud2lo|ud2hi addr2 count2 -TONUMBER MOV @PSP,S ;2 S=adr - MOV TOS,T ;1 T=count - MOV &BASE,W ;3 -TONUMLOOP MOV.B @S,Y ;2 -- ud1lo ud1hi x x S=adr, T=count, W=BASE, Y=char -DDIGITQ SUB.B #30h,Y ;2 skip all chars < '0' - CMP.B #10,Y ;2 char was > "9" ? - JNC DDIGITQNEXT ;2 -- ud1lo ud1hi x x no: good end - SUB.B #07,Y ;2 skip all chars between "9" and "A" - CMP.B #10,Y ;2 char was < "A" ? - JNC TONUMEND ;2 yes: for bad end -DDIGITQNEXT CMP W,Y ;1 -- ud1lo ud1hi x x digit-base - BIC #Z,SR ;1 reset Z before jmp TONUMEND because... - JC TONUMEND ;2 ...QNUMBER conversion will be true if Z = 1 :-( -UDSTAR PUSHM #6,IP ;8 -- ud1lo ud1hi x x save IP S T W X Y used by UM* r-- IP adr count base x digit - MOV 2(PSP),S ;3 -- ud1lo ud1hi x x S=ud1hi - MOV W,TOS ;1 -- ud1lo ud1hi x base - MOV #UMSTARNEXT1,IP ;2 -UMSTARONE JMP UMSTAR1 ;2 ud1hi * base -- x ud3hi X=ud3lo -UMSTARNEXT1 .word $+2 ; -- ud1lo ud1hi x ud3hi - MOV X,2(RSP) ;3 r-- IP adr count base ud3lo digit - MOV 4(PSP),S ;3 -- ud1lo ud1hi x ud3hi S=ud1lo - MOV 4(RSP),TOS ;3 -- ud1lo ud1hi x base - MOV #UMSTARNEXT2,IP ;2 -UMSTARTWO JMP UMSTAR1 ;2 -- ud1lo ud1hi x ud4hi X=ud4lo -UMSTARNEXT2 .word $+2 ; -- ud1lo ud1hi x ud4hi -MPLUS ADD @RSP+,X ;2 -- ud1lo ud1hi x ud4hi X=ud4lo+digit=ud2lo r-- IP adr count base ud3lo - ADDC @RSP+,TOS ;2 -- ud1lo ud1hi x ud2hi TOS=ud4hi+ud3lo+carry=ud2hi r-- IP adr count base - MOV X,4(PSP) ;3 -- ud2lo ud1hi x ud2hi - MOV TOS,2(PSP) ;3 -- ud2lo ud2hi x x r-- IP adr count base - POPM #4,IP ;6 -- ud2lo ud2hi x x W=base, T=count, S=adr, IP=prevIP r-- -TONUMPLUS ADD #1,S ;1 - SUB #1,T ;1 - JNZ TONUMLOOP ;2 -- ud2lo ud2hi x x S=adr+1, T=count-1, W=base 68 cycles char loop -TONUMEND MOV S,0(PSP) ;3 -- ud2lo ud2hi adr2 count2 - MOV T,TOS ;1 -- ud2lo ud2hi adr2 count2 - MOV @IP+,PC ;4 50/82 words/cycles, W = BASE +TONUMBER MOV &BASEADR,W ;3 W = base + MOV @PSP,S ;2 S=adr + MOV TOS,T ;1 T=count +TONUMLOOP MOV.B @S,Y ;2 -- ud1lo ud1hi x x S=adr, T=count, W=BASE, Y=char +DDIGITQ SUB.B #':',Y ;2 + JNC DDIGITQNEXT ;2 accept all chars <= 9 + SUB.B #07,Y ;2 reject all chars between "9" and "A" + JNC TONUMEND ;2 yes: for bad end +DDIGITQNEXT ADD.B #10,Y ;2 restore number + CMP W,Y ;1 -- ud1lo ud1hi x x digit-base + BIC #Z,SR ;1 reset Z before jmp TONUMEND because... + JC TONUMEND ;2 ...QNUMBER conversion will be true if Z = 1 :-( +UDSTAR PUSHM #6,IP ;8 -- ud1lo ud1hi x x save IP S T W X Y used by UM* r-- IP adr count base x digit + MOV 2(PSP),S ;3 -- ud1lo ud1hi x x S=ud1hi + MOV W,TOS ;1 -- ud1lo ud1hi x base + MOV #UMSTARNEXT1,IP ;2 +UMSTARONE JMP UMSTAR1 ;2 ud1hi * base -- x ud3hi X=ud3lo +UMSTARNEXT1 mNEXTADR ; -- ud1lo ud1hi x ud3hi + MOV X,2(RSP) ;3 r-- IP adr count base ud3lo digit + MOV 4(PSP),S ;3 -- ud1lo ud1hi x ud3hi S=ud1lo + MOV 4(RSP),TOS ;3 -- ud1lo ud1hi x base + MOV #UMSTARNEXT2,IP ;2 +UMSTARTWO JMP UMSTAR1 ;2 -- ud1lo ud1hi x ud4hi X=ud4lo +UMSTARNEXT2 mNEXTADR ; -- ud1lo ud1hi x ud4hi +MPLUS ADD @RSP+,X ;2 -- ud1lo ud1hi x ud4hi X=ud4lo+digit=ud2lo r-- IP adr count base ud3lo + ADDC @RSP+,TOS ;2 -- ud1lo ud1hi x ud2hi TOS=ud4hi+ud3lo+carry=ud2hi r-- IP adr count base + MOV X,4(PSP) ;3 -- ud2lo ud1hi x ud2hi + MOV TOS,2(PSP) ;3 -- ud2lo ud2hi x x r-- IP adr count base + POPM #4,IP ;6 -- ud2lo ud2hi x x W=base, T=count, S=adr, IP=prevIP r-- +TONUMPLUS ADD #1,S ;1 + SUB #1,T ;1 + JNZ TONUMLOOP ;2 -- ud2lo ud2hi x x S=adr+1, T=count-1, W=base 68 cycles char loop +TONUMEND MOV S,0(PSP) ;3 -- ud2lo ud2hi adr2 count2 + MOV T,TOS ;1 -- ud2lo ud2hi adr2 count2 + MOV @IP+,PC ;4 48/82 words/cycles, W = BASE ; ?NUMBER makes the interface between >NUMBER and INTERPRET; it's a subset of INTERPRET. ; convert a string to a signed number; FORTH 2012 prefixes ' $, %, # are recognized @@ -1510,301 +1122,282 @@ TONUMEND MOV S,0(PSP) ;3 -- ud2lo ud2hi adr2 count2 ;Z ?NUMBER addr -- n|d -1 if convert ok ; flag Z=0, UF9=1 if double ;Z addr -- addr 0 if convert ko ; flag Z=1 QNUMBER - .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT - BIC #UF9,SR ;2 reset flag UF9, before use as double number flag - .ENDIF ; - MOV &BASE,T ;3 T=BASE - MOV #0,S ;1 - PUSHM #3,IP ;5 R-- IP sign base (push IP,S,T) - MOV #TONUMEXIT,IP ;2 define >NUMBER return - MOV T,W ;1 W=BASE - SUB #8,PSP ;1 -- x x x x addr - MOV TOS,6(PSP) ;3 -- addr x x x addr - MOV #0,4(PSP) ;3 - MOV #0,2(PSP) ;3 -- addr 0 0 x addr - MOV TOS,S ;1 -- addr ud=0 x x - MOV.B @S+,T ;2 S=addr, T=count -QTICK CMP.B #27h,0(S) ;4 prefix = ' ? - JNZ QNUMLDCHAR ;2 no - MOV.B 1(S),4(PSP) ;5 -- addr ud2lo 0 x x ud2lo = ASCII code of 'char' - CMP.B #3,TOS ;2 string must be 3 chars long - JMP QNUMNEXT ;2 -QNUMLDCHAR MOV.B @S,Y ;2 Y=char -QMINUS SUB.B #'-',Y ;2 -- addr ud=0 x x sign minus ? - JNC QBINARY ;2 if char U< '-' - JNZ TONUMLOOP ;2 if char U> '-' - MOV #-1,2(RSP) ;3 R-- IP sign base - JMP PREFIXED ;2 -QBINARY MOV #2,W ;1 preset base 2 - ADD.B #8,Y ;1 binary prefix ? - JZ PREFIXED ;2 yes -QDECIMAL ADD #8,W ;1 preset base 10 - ADD.B #2,Y ;1 decimal prefix ? - JZ PREFIXED ;2 yes -QHEXA MOV #16,W ;1 preset base 16 - ADD.B #-1,Y ;2 hex prefix ? - JNZ QNUMNEXT ;2 -- addr x x x cnt abort if not recognized prefix -PREFIXED ADD #1,S ;1 - SUB #1,T ;1 S=adr+1 T=count-1 - JMP QNUMLDCHAR ;2 -; ----------------------------------;42 - -TONUMEXIT .word $+2 ; -- addr ud2lo-hi addr2 cnt2 R-- IP sign BASE S=addr2,T=cnt2 -; ----------------------------------; - JZ QNUMNEXT ;2 if conversion is ok -; ----------------------------------; + .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT + BIC #UF9,SR ;2 reset flag UF9, before use as double number flag + .ENDIF ; + SUB #8,PSP ;1 -- x x x x addr + MOV TOS,6(PSP) ;3 -- addr x x x addr save TOS + MOV #0,4(PSP) ;3 ud1hi=0 + MOV #0,2(PSP) ;3 -- addr 0 0 x addr ud1lo=0 + MOV &BASEADR,W ;3 W=BASE + MOV TOS,S ;1 -- addr ud=0 x x S=addr + MOV #0,TOS ;1 + PUSHM #2,TOS ;4 R-- sign IP (push TOS,IP) + MOV #TONUMEXIT,IP ;2 define >NUMBER return + MOV.B @S+,T ;2 S=addr+1, T=count +QNUMLDCHAR MOV.B @S,Y ;2 Y=char + SUB.B #'-',Y ;2 -- addr ud=0 x x sign minus ? + JZ QNUMMINUS ;2 yes + JC TONUMLOOP ;2 if char U> '-' +QBINARY MOV #2,W ;1 preset base 2 + ADD.B #8,Y ;1 binary prefix ? '%' = '-' + 8 + JZ PREFIXNEXT ;2 yes +QDECIMAL ADD #8,W ;1 preset base 10 + ADD.B #2,Y ;1 decimal prefix ? '#' = '%' + 2 + JZ PREFIXNEXT ;2 yes +QHEXA MOV #16,W ;2 preset base 16 + CMP.B #1,Y ;1 hex prefix ? '$' = '#' + 1 + JZ PREFIXNEXT ;2 yes +QTICK CMP.B #4,Y ;1 prefix = ' ? "'" = '#' + 4 + JNZ QNUMNEXT ;2 -- addr x x x cnt abort if not recognized prefix + CMP #3,TOS ; + JNZ QNUMNEXT ; + CMP.B @S+,1(S) ;4 compare 3rd with first char ' + MOV.B @S,S ;2 does char to word conversion + MOV S,4(PSP) ;5 -- addr ud2lo 0 x x ud2lo = ASCII code of 'char' + JMP QNUMNEXT ;2 with happy end if flag Z = 1 +QNUMMINUS MOV #-1,2(RSP) ;3 R-- sign IP set sign flag +PREFIXNEXT SUB #1,T ;1 T=count-1 + CMP.B @S+,0(S) ;4 S=adr+1; same prefix ? + JNZ QNUMLDCHAR ;2 no + JZ TONUMLOOP ;2 yes, that will abort conversion +; ------------------------------;43 +TONUMEXIT mNEXTADR ; -- addr ud2lo-hi addr2 cnt2 R-- IP sign BASE S=addr2,T=cnt2 + JZ QNUMNEXT ;2 if conversion is ok SUB #2,IP - CMP.B #28h,Y ; rejected char by >NUMBER is a underscore ? - JZ TONUMPLUS ; yes: loopback to >NUMBER to skip char - .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT - BIT #UF9,SR ; UF9 already set ? (you have wrongly typed two points) - JNZ QNUMNEXT ; yes, goto QNUMKO - BIS #UF9,SR ;2 set double number flag + MOV.B @S,Y ; regenerate rejected char + CMP.B #'_',Y ;2 rejected char by >NUMBER is a underscore ? + JZ TONUMPLUS ; yes: loopback to >NUMBER to skip char + .IFDEF DOUBLE_NUMBERS ; DOUBLE_NUMBERS = DOUBLE_INPUT | FIXPOINT_INPUT + BIT #UF9,SR ; UF9 already set ? (you have wrongly typed two points) + JNZ QNUMNEXT ; yes, goto QNUMKO + BIS #UF9,SR ;2 set double number flag .ENDIF .IFDEF DOUBLE_INPUT - CMP.B #0F7h,Y ;2 rejected char by >NUMBER is a decimal point ? - JZ TONUMPLUS ;2 to terminate conversion + SUB.B #'.',Y ;1 rejected char by >NUMBER is a decimal point ? + JZ TONUMPLUS ;2 to terminate conversion .ENDIF - .IFDEF FIXPOINT_INPUT ; - CMP.B #0F5h,Y ;2 rejected char by >NUMBER is a comma ? - JNZ QNUMNEXT ;2 no, goto QNUMKO -; ----------------------------------; -S15Q16 MOV #0,X ;1 -- addr ud2lo x 0 x init ud2lo' = 0 -S15Q16LOOP MOV X,2(PSP) ;3 -- addr ud2lo ud2lo' ud2lo' x X = 0(PSP) = ud2lo' - SUB.B #1,T ;1 decrement cnt2 - MOV T,X ;1 X = cnt2-1 - ADD S,X ;1 X = end_of_string-1, first... - MOV.B @X,X ;2 X = last char of string, first... - SUB.B #30h,X ;2 char --> digit conversion - CMP.B #10,X ;2 - JNC QS15Q16DIGI ;2 - SUB.B #7,X ;2 - CMP.B #10,X ;2 - JNC S15Q16EOC ;2 -QS15Q16DIGI CMP W,X ;1 R-- IP sign BASE, W=BASE, is X a digit ? - JC S15Q16EOC ;2 -- addr ud2lo ud2lo' x ud2lo' if no - MOV X,0(PSP) ;3 -- addr ud2lo ud2lo' digit x - MOV W,TOS ;1 -- addr ud2lo ud2lo' digit base R-- IP sign base - PUSHM #3,S ;5 PUSH S,T,W: R-- IP sign base addr2 cnt2 base - CALL #MUSMOD ;4 -- addr ud2lo ur uqlo uqhi - POPM #3,S ;5 restore W,T,S: R-- IP sign BASE - JMP S15Q16LOOP ;2 W=cnt -S15Q16EOC MOV 4(PSP),2(PSP) ;5 -- addr ud2lo ud2lo uqlo x ud2lo from >NUMBER part1 becomes here ud2hi=S15 part2 - MOV @PSP,4(PSP) ;4 -- addr ud2lo ud2hi x x uqlo becomes ud2lo - CMP.B #0,T ;1 cnt2 = 0 if end of conversion ok - .ENDIF ; FIXPOINT_INPUT ; -; ----------------------------------;97 -QNUMNEXT POPM #3,IP ;4 -- addr ud2lo-hi x cnt2 POPM T,S,IP S = sign flag = {-1;0} - MOV S,TOS ;1 -- addr ud2lo-hi x sign - MOV T,&BASE ;3 - JZ QNUMOK ;2 -- addr ud2lo-hi x sign flag Z=1: conversion OK -QNUMKO ; flag Z=0 + .IFDEF FIXPOINT_INPUT ; + .IFDEF DOUBLE_INPUT + ADD.B #2,Y ;1 rejected char by >NUMBER is a comma ? + .ELSE + SUB.B #',',Y ;1 rejected char by >NUMBER is a comma ? + .ENDIF + JNZ QNUMNEXT ;2 no, goto QNUMKO +S15Q16 MOV #0,X ;1 -- addr ud2lo x 0 x init ud2lo' = 0 +S15Q16LOOP MOV X,2(PSP) ;3 -- addr ud2lo ud2lo' ud2lo' x X = 0(PSP) = ud2lo' + SUB.B #1,T ;1 decrement cnt2 + MOV T,X ;1 X = cnt2-1 + ADD S,X ;1 X = end_of_string-1, first... + MOV.B @X,X ;2 X = last char of string, first... + SUB.B #':',X ;2 + JNC QS15Q16DIGI ;2 accept all chars U< ':' + SUB.B #7,X ;2 + JNC S15Q16EOC ;2 reject all chars U< 'A' +QS15Q16DIGI ADD.B #10,X ;2 restore number + CMP W,X ;1 W=BASE, is X a digit ? + JC S15Q16EOC ;2 -- addr ud2lo ud2lo' x ud2lo' if not a digit + MOV X,0(PSP) ;3 -- addr ud2lo ud2lo' digit x + MOV W,TOS ;1 -- addr ud2lo ud2lo' digit base R-- IP sign + PUSHM #3,S ;5 PUSH S,T,W: R-- IP sign addr2 cnt2 base + CALL #MUSMOD ;4 -- addr ud2lo ur uqlo uqhi + POPM #3,S ;5 restore W,T,S: R-- IP sign + JMP S15Q16LOOP ;2 W=cnt +S15Q16EOC MOV 4(PSP),2(PSP) ;5 -- addr ud2lo ud2lo uqlo x ud2lo from >NUMBER part1 becomes here ud2hi=S15 part2 + MOV @PSP,4(PSP) ;4 -- addr ud2lo ud2hi x x uqlo becomes ud2lo + CMP.B #0,T ;1 cnt2 = 0 if end of conversion ok + .ENDIF ; FIXPOINT_INPUT ; +; ------------------------------;97 +QNUMNEXT POPM #2,TOS ;4 -- addr ud2lo-hi x sign R: -- POPM IP,TOS TOS = sign flag = {-1;0} + JZ QNUMOK ;2 -- addr ud2lo-hi x sign conversion OK if Z=1 +QNUMKO ; flag Z=0 .IFDEF DOUBLE_NUMBERS BIC #UF9,SR .ENDIF - ADD #6,PSP ;1 -- addr sign - AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko - MOV @IP+,PC ;4 -; ----------------------------------; + ADD #6,PSP ;1 -- addr sign + AND #0,TOS ;1 -- addr ff TOS=0 and Z=1 ==> conversion ko + MOV @IP+,PC ;4 +; ------------------------------; .IFDEF DOUBLE_NUMBERS -QNUMOK ADD #2,PSP ;1 -- addr ud2lo ud2hi sign - MOV 2(PSP),4(PSP) ; -- udlo udlo udhi sign - MOV @PSP+,0(PSP) ;4 -- udlo udhi sign note : PSP is incremented before write back !!! - XOR #-1,TOS ;1 -- udlo udhi inv(sign) - JNZ QDOUBLE ;2 if jump : TOS=-1 and Z=0 ==> conversion ok - XOR #-1,TOS ;1 -- udlo udhi tf -Q2NEGATE XOR #-1,2(PSP) ;3 - XOR #-1,0(PSP) ;3 - ADD #1,2(PSP) ;3 - ADDC #0,0(PSP) ;3 -- dlo dhi tf -QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point added ? - JNZ QNUMEND ;2 -- dlo dhi tf leave double - ADD #2,PSP ;1 -- dlo tf leave number, Z=0 -QNUMEND MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok +QNUMOK ADD #2,PSP ;1 -- addr ud2lo ud2hi sign + MOV 2(PSP),4(PSP) ; -- udlo udlo udhi sign + MOV @PSP+,0(PSP) ;4 -- udlo udhi sign note : PSP is incremented before write back !!! + XOR #-1,TOS ;1 -- udlo udhi inv(sign) + JNZ QDOUBLE ;2 if jump : TOS=-1 and Z=0 ==> conversion ok + XOR #-1,TOS ;1 -- udlo udhi tf +Q2NEGATE XOR #-1,2(PSP) ;3 + XOR #-1,0(PSP) ;3 + ADD #1,2(PSP) ;3 + ADDC #0,0(PSP) ;3 -- dlo dhi tf +QDOUBLE BIT #UF9,SR ;2 -- dlo dhi tf decimal point added ? + JNZ QNUMEND ;2 -- dlo dhi tf leave double +NIP ADD #2,PSP ;1 -- dlo tf leave number, Z=0 +QNUMEND MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok .ELSE -QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign - MOV @PSP+,0(PSP) ;4 -- udlo sign note : PSP is incremented before write back !!! - XOR #-1,TOS ;1 -- udlo inv(sign) - JNZ QNUMEND ;2 if jump : TOS=-1 and Z=0 ==> conversion ok - XOR #-1,TOS ;1 -- udlo tf TOS=-1 and Z=0 -QNEGATE XOR #-1,0(PSP) ;3 - ADD #1,0(PSP) ;3 -- n tf -QNUMEND MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok +QNUMOK ADD #4,PSP ;1 -- addr ud2lo sign + MOV @PSP,2(PSP) ;4 -- udlo udlo sign note : PSP is incremented before write back !!! + XOR #-1,TOS ;1 -- udlo udlo inv(sign) + JNZ QNUMEND ;2 if jump : TOS=-1 and Z=0 ==> conversion ok + XOR #-1,TOS ;1 -- udlo udlo tf TOS=-1 and Z=0 +QNEGATE XOR #-1,2(PSP) ;3 + ADD #1,2(PSP) ;3 -- n udlo tf +QNUMEND +NIP ADD #2,PSP ;1 + MOV @IP+,PC ;4 TOS=-1 and Z=0 ==> conversion ok .ENDIF ; DOUBLE_NUMBERS - .ENDIF ; of Hardware/Software MPY + FORTHWORDIMM "\\" ; immediate +; https://forth-standard.org/standard/block/bs +; \ -- backslash +; everything up to the end of the current line is a comment. +BACKSLASH MOV &SOURCE_LEN,&TOIN ; + MOV @IP+,PC + +; INTERPRET i*x addr u -- j*x interpret given buffer +; This is the common factor of EVALUATE and QUIT. +; set addr u as input buffer then parse it word by word +INTERPRET mDOCOL ; INTERPRET = BACKSLASH + 8 + .word SETIB ; -- set input buffer pointers +INTLOOP .word BL,WORDD ; -- c-addr fl flag Z = 1 <=> End Of Line + .word ZBRAN,FDROPEXIT; BRANch to DROPEXIT if Z = 1 + .word FIND + mNEXTADR ; -- xt|c-addr|xt -1|0|+1 Z=1 --> not found + MOV TOS,W ; W = flag = (-1|0|+1) as (not_immediate|not_found|immediate) + MOV @PSP+,TOS ; -- xt|c-addr|xt + MOV #INTQNUMNEXT,IP ;2 INTQNUMNEXT is the continuation of QNUMBER + JZ QNUMBER ;2 if Z=1 --> not found, search a number + MOV #INTLOOP,IP ;2 INTLOOP is the continuation of EXECUTE|COMMA + XOR &STATE,W ;3 + JZ COMMA ;2 -- xt if W xor STATE = 0 compile xt, then loop back to INTLOOP +EXECUTE PUSH TOS ;3 -- xt + MOV @PSP+,TOS ;2 -- + MOV @RSP+,PC ;4 xt --> PC, then loop back to INTLOOP +; ------------------------------; +INTQNUMNEXT mNEXTADR ; -- n|c-addr fl Z = 1 --> not a number, SR(UF9) double number request + MOV @PSP+,TOS ;2 -- n|c-addr + MOV #INTLOOP,IP ;2 INTLOOP is the continuation of LITERAL. + JNZ LITERAL ;2 n -- Z = 0 --> is a number, execute LITERAL then loop back to INTLOOP +NotFoundexe ADD.B #1,0(TOS) ;3 c-addr -- Z = 1 --> Not a Number : incr string count to add '?' + MOV.B @TOS,Y ;2 Y=count+1 + ADD TOS,Y ;1 Y=end of string addr + MOV.B #'?',0(Y) ;5 add '?' to end of string + MOV #FABORT_TERM,IP ;2 ABORT_TERM is the continuation of COUNT + JMP COUNT ;2 -- addr len 37 words + ;------------------------------------------------------------------------------- ; DICTIONARY MANAGEMENT ;------------------------------------------------------------------------------- FORTHWORD "," ; https://forth-standard.org/standard/core/Comma ; , x -- append cell to dict -COMMA MOV &DDP,W ;3 - MOV TOS,0(W) ;3 - ADD #2,&DDP ;3 - MOV @PSP+,TOS ;2 - MOV @IP+,PC ;4 15~ - - .IFDEF CORE_COMPLEMENT - FORTHWORD "EXECUTE" -; https://forth-standard.org/standard/core/EXECUTE -; EXECUTE i*x xt -- j*x execute Forth word at 'xt' - JMP EXECUTE - .ENDIF +COMMA ADD #2,&DP ;3 + MOV &DP,W ;3 + MOV TOS,-2(W) ;3 + MOV @PSP+,TOS ;2 + MOV @IP+,PC ;4 15~ W = DP FORTHWORDIMM "LITERAL" ; immediate ; https://forth-standard.org/standard/core/LITERAL ; LITERAL n -- append single numeric literal if compiling state ; d -- append two numeric literals if compiling state and UF9<>0 (not ANS) - .IFDEF DOUBLE_NUMBERS ; are recognized -LITERAL CMP #0,&STATE ;3 - JZ LITERAL2 ;2 if interpreting state, clear UF9 flag then NEXT - MOV TOS,X ;1 -LITERAL1 MOV &DDP,W ;3 X = n|HId - ADD #4,&DDP ;3 - MOV #LIT,0(W) ;4 - MOV X,2(W) ;3 - MOV @PSP+,TOS ;2 - BIT #UF9,SR ;2 double number ? -LITERAL2 BIC #UF9,SR ;2 in all case, clear UF9 - JZ LITERALEND ;2 no - MOV TOS,2(W) ;3 - JMP LITERAL1 ;2 -LITERALEND MOV @IP+,PC ;4 + .IFDEF DOUBLE_NUMBERS ; are recognized +LITERAL CMP #0,&STATE ;3 + JZ LITERALNEXT ;2 if interpreting state, does nothing else clear UF9 flag + MOV TOS,X ;1 X = n|dhi +LITERALLOOP MOV &DP,W ;3 + ADD #4,&DP ;3 + MOV #lit,0(W) ;4 + MOV X,2(W) ;3 pass 1: compile n|dhi, if pass 2: compile dhi + MOV @PSP+,TOS ;2 + BIT #UF9,SR ;2 double number ? +LITERALNEXT BIC #UF9,SR ;2 in all case, clear UF9 + JZ LITERALEND ;2 goto end if n|interpret_state + MOV TOS,2(W) ;3 compile dlo over dhi + JMP LITERALLOOP ;2 +LITERALEND MOV @IP+,PC ;4 .ELSE -LITERAL CMP #0,&STATE ;3 - JZ LITERALEND ;2 if interpreting state, do nothing -LITERAL1 MOV &DDP,W ;3 - ADD #4,&DDP ;3 - MOV #LIT,0(W) ;4 - MOV TOS,2(W) ;3 - MOV @PSP+,TOS ;2 -LITERALEND MOV @IP+,PC ;4 +LITERAL CMP #0,&STATE ;3 + JZ LITERALEND ;2 if interpreting state, does nothing + MOV &DP,W ;3 + ADD #4,&DP ;3 + MOV #lit,0(W) ;4 + MOV TOS,2(W) ;3 + MOV @PSP+,TOS ;2 +LITERALEND MOV @IP+,PC ;4 .ENDIF FORTHWORD "COUNT" ; https://forth-standard.org/standard/core/COUNT ; COUNT c-addr1 -- adr len counted->adr/len -COUNT SUB #2,PSP ;1 - ADD #1,TOS ;1 - MOV TOS,0(PSP) ;3 - MOV.B -1(TOS),TOS ;3 - MOV @IP+,PC ;4 15~ - - FORTHWORD "INTERPRET" -; INTERPRET i*x addr u -- j*x interpret given buffer -; This is the common factor of EVALUATE and QUIT. -; set addr u as input buffer then parse it word by word -INTERPRET mDOCOL ; - .word SETIB ; -INTLOOP .word FBLANK,WORDD ; -- c-addr Z = 1 --> End Of Line - .word $+2 ; - JZ DROPEXIT ;2 Z = 1 --> EOL reached - MOV #INTFINDNEXT,IP ;2 define INTFINDNEXT as FIND return - JMP FIND ;2 -INTFINDNEXT .word $+2 ; -- c-addr fl Z = 1 -->not found - MOV TOS,W ; W = flag =(-1|0|+1) as (normal|not_found|immediate) - MOV @PSP+,TOS ; -- c-addr - MOV #INTQNUMNEXT,IP ;2 define QNUMBER return - JZ QNUMBER ;2 Z = 1 --> not found, search a number - MOV #INTLOOP,IP ;2 define (EXECUTE | COMMA) return - XOR &STATE,W ;3 - JZ COMMA ;2 if W xor STATE = 0 compile xt then loop back to INTLOOP -EXECUTE PUSH TOS ;3 - MOV @PSP+,TOS ;2 -- - MOV @RSP+,PC ;4 xt --> PC - -INTQNUMNEXT .word $+2 ; -- n|c-addr fl Z = 1 --> not a number, SR(UF9) double number request - MOV @PSP+,TOS ;2 - MOV #INTLOOP,IP ;2 -- n|c-addr define LITERAL return - JNZ LITERAL ;2 n -- Z = 0 --> is a number, execute LITERAL then loop back to INTLOOP - -NotFoundexe ADD.B #1,0(TOS) ;3 c-addr -- Z = 1 --> Not a Number : incr string count to add '?' - MOV.B @TOS,Y ;2 Y=count+1 - ADD TOS,Y ;1 Y=end of string addr - MOV.B #'?',0(Y) ;5 add '?' to end of string - MOV #FABORT_TERM,IP ;2 define the return of COUNT - JMP COUNT ;2 -- addr len 35 words -NotFound .word NotFoundExe ; - - .IFDEF CORE_COMPLEMENT - FORTHWORD "EVALUATE" -; https://forth-standard.org/standard/core/EVALUATE -; EVALUATE \ i*x c-addr u -- j*x interpret string -EVALUATE MOV #SOURCE_LEN,X ;2 - MOV @X+,S ;2 S = SOURCE_LEN - MOV @X+,T ;2 T = SOURCE_ORG - MOV @X+,W ;2 W = TOIN - PUSHM #4,IP ;6 PUSHM IP,S,T,W - ASMtoFORTH - .word INTERPRET - .word $+2 - MOV @RSP+,&TOIN ;4 - MOV @RSP+,&SOURCE_ORG ;4 - MOV @RSP+,&SOURCE_LEN ;4 - MOV @RSP+,IP - MOV @IP+,PC - - FORTHWORD "BL" -; https://forth-standard.org/standard/core/BL -; BL -- char an ASCII space - .ENDIF ; CORE_COMPLEMENT -FBLANK CALL rDOCON - .word 20h +COUNT SUB #2,PSP ;1 + MOV.B @TOS+,W ;2 + MOV TOS,0(PSP) ;3 + MOV W,TOS ;1 + AND #-1,TOS ; Z is set if u=0 + MOV @IP+,PC ;4 14~ FORTHWORD "ALLOT" ; https://forth-standard.org/standard/core/ALLOT ; ALLOT n -- allocate n bytes -ALLOT ADD TOS,&DDP +ALLOT ADD TOS,&DP MOV @PSP+,TOS MOV @IP+,PC ; FORTHWORD "ABORT" ; https://forth-standard.org/standard/core/ABORT -; Empty the data stack and perform the function of QUIT, +; Empty the data stack and perform the function of QUIT, ; which includes emptying the return stack, without displaying a message. ; ABORT is the common next of WARM and ABORT" -ABORT MOV #PSTACK,PSP ; - MOV #0,TOS ; to reset first PSP cell (TOS), used next by WARM +ABORT MOV #PSTACK,PSP ; ABORT = ALLOT + 8 + MOV #0,TOS ; and set TOS for SYS use. ; https://forth-standard.org/standard/core/QUIT ; QUIT -- interpret line by line the input stream -QUIT MOV #RSTACK,RSP ; - MOV #LSTACK,&LEAVEPTR ; - MOV #0,&STATE ; - ASMtoFORTH +QUIT mASM2FORTH ; QUIT = ALLOT + 14 .IFDEF PROMPT -QUIT1 .word XSQUOTE ; background interpret loop - .byte 5,13,10,"ok " ; CR+LF + Forth prompt -QUIT2 .word TYPE ; display it +QUIT1 .word XSQUOTE ; lower interpret loop + .byte 5,13,10,"ok " ; CR + LF + Forth prompt +QUIT2 .ELSE -QUIT2 .word CR +QUIT2 .word XSQUOTE + .byte 2,13,10 ; CR+LF .ENDIF -QUIT3 .word REFILL ; -- org len refill input buffer from ACCEPT (one line) -QUIT4 .word INTERPRET ; interpret this line|string - .word DEPTH,ZEROLESS ; stack empty test + .word TYPE ; + .word REFILL ; -- org len refill input buffer from ACCEPT (one line) +QUIT4 .word INTERPRET ; interpret input buffer|string +QUIT5 .word DEPTH,ZEROLESS ; stack empty test .word XSQUOTE ; ABORT" stack empty! " - .byte 12,"stack empty!" ; + .byte 11,"stack empty"; .word QABORT ; see QABORT in forthMSP430FR_TERM_xxx.asm - .word lit,FRAM_FULL ; - .word HERE,ULESS ; FRAM full test + .word HEREXEC ; ) + .word lit,FRAM_FULL ; > FRAM full test + .word UMORE ; ) .word XSQUOTE ; ABORT" FRAM full! " - .byte 10,"FRAM full!" ; + .byte 9,"FRAM full" ; .word QABORT ; see QABORT in forthMSP430FR_TERM_xxx.asm .IFDEF PROMPT - .word LIT,STATE,FETCH ; STATE @ + .word lit,STATE,FETCH ; STATE @ .word QFBRAN,QUIT1 ; 0= case of interpretion state .word XSQUOTE ; 0<> case of compilation state .byte 5,13,10," " ; CR+LF + 3 spaces .ENDIF .word BRAN,QUIT2 - FORTHWORDIMM "ABORT\34" ; immediate + FORTHWORDIMM "ABORT\34" +; ; ABORT" is enabled in interpretation mode (+ 17 words) : +; CMP #0,&STATE +; JNZ CMPL_QABORT +; MOV #0,&CAPS ; CAPS OFF +; EXEC_QABORT mDOCOL +; .word LIT,'"',WORDD,COUNT,QABORT +; .word BL,LIT,CAPS,STORE +; .word EXIT + ; https://forth-standard.org/standard/core/ABORTq +; ABORT" " (empty string) displays nothing ; ABORT" i*x flag -- i*x R: j*x -- j*x flag=0 ; i*x flag -- R: j*x -- flag<>0 -; ABORT" " (empty string) displays nothing -ABORTQUOTE mDOCOL +CMPL_QABORT mDOCOL .word SQUOTE .word lit,QABORT,COMMA ; see QABORT in forthMSP430FR_TERM_xxx.asm .word EXIT @@ -1816,16 +1409,18 @@ ABORTQUOTE mDOCOL ; https://forth-standard.org/standard/core/Tick ; ' -- xt find word in dictionary and leave on stack its execution address TICK mDOCOL - .word FBLANK,WORDD,FIND - .word QFBRAN,NotFound ; see INTERPRET - .word EXIT + .word BL,WORDD,FIND + .word ZBRAN,NotFound ; BRANch to NotFound if Z = 1 +FDROPEXIT .word DROPEXIT +NotFound .word NotFoundExe ; see INTERPRET + FORTHWORDIMM "[']" ; immediate word, i.e. word executed during compilation ; https://forth-standard.org/standard/core/BracketTick ; ['] <name> -- find word & compile it as literal BRACTICK mDOCOL .word TICK ; get xt of <name> - .word lit,lit,COMMA ; append LIT action + .word lit,lit,COMMA ; append lit action .word COMMA,EXIT ; append xt literal FORTHWORDIMM "[" ; immediate @@ -1842,73 +1437,66 @@ RIGHTBRACKET MOV #-1,&STATE MOV @IP+,PC - FORTHWORDIMM "\\" ; immediate -; https://forth-standard.org/standard/block/bs -; \ -- backslash -; everything up to the end of the current line is a comment. -BACKSLASH MOV &SOURCE_LEN,&TOIN ; - MOV @IP+,PC - FORTHWORDIMM "POSTPONE" ; https://forth-standard.org/standard/core/POSTPONE POSTPONE mDOCOL - .word FBLANK,WORDD,FIND,QDUP - .word QFBRAN,NotFound ; see INTERPRET + .word BL,WORDD,FIND + .word ZBRAN,NotFound ; BRANch to NotFound if Z = 1 .word ZEROLESS ; immediate word ? .word QFBRAN,POST1 ; if immediate .word lit,lit,COMMA ; else compile lit .word COMMA ; compile xt .word lit,COMMA ; CFA of COMMA -POST1 .word COMMA,EXIT ; then compile: if immediate xt of word found else CFA of COMMA +POST1 .word COMMA,EXIT ; then compile xt of word found if immediate else CFA of COMMA FORTHWORD ":" ; https://forth-standard.org/standard/core/Colon ; : <name> -- begin a colon definition -; HEADER is CALLed by all compiling words -COLON PUSH #COLONNEXT ;3 define COLONNEXT as HEADER return +COLON PUSH #COLONNEXT ;3 define COLONNEXT as HEADER return ;-----------------------------------; -HEADER BIT #1,&DDP ;3 carry set if odd - ADDC #2,&DDP ;4 (DP+2|DP+3) bytes, make room for LFA +HEADER BIT #1,&DP ;3 carry set if odd + ADDC #2,&DP ;4 align and make room for LFA mDOCOL ; - .word FBLANK,WORDD ; - .word $+2 ; -- HERE HERE is the NFA of this new word + .word BL,WORDD ; W=Count_of_chars + mNEXTADR ; -- HERE HERE is the NFA of this new word MOV @RSP+,IP ; - MOV TOS,Y ; -- NFA Y=NFA - MOV.B @TOS+,W ; -- NFA+1 W=Count_of_chars BIS.B #1,W ; W=count is always odd ADD.B #1,W ; W=add one byte for length - ADD Y,W ; W=Aligned_CFA + ADD TOS,W ; W=Aligned_CFA MOV &CURRENT,X ; X=VOC_BODY of CURRENT + MOV TOS,Y ; Y=NFA .SWITCH THREADS ; .CASE 1 ; nothing to do .ELSECASE ; multithreading add 5~ 4words - MOV.B @TOS,TOS ; -- char TOS=first CHAR of new word - AND #(THREADS-1)*2,TOS ; -- offset TOS= Thread offset + MOV.B 1(TOS),TOS ; -- char TOS=first CHAR of new word + AND #(THREADS-1),TOS ; -- offset TOS= thread_offset + ADD TOS,TOS ; TOS= thread_offset * 2 ADD TOS,X ; X=VOC_PFAx = thread x of VOC_PFA of CURRENT .ENDCASE ; MOV @PSP+,TOS ; -- -HEADEREND MOV Y,&LAST_NFA ; NFA --> LAST_NFA used by QREVEAL, IMMEDIATE, MARKER + ADD.B @Y,0(Y) ; shift left once NFA_1st_byte (make room for immediate flag) +HEADEREND MOV Y,&LAST_NFA ; NFA --> LAST_NFA used by QREVEAL, IMMEDIATE MOV X,&LAST_THREAD ; VOC_PFAx --> LAST_THREAD used by QREVEAL MOV W,&LAST_CFA ; HERE=CFA --> LAST_CFA used by DOES>, RECURSE MOV PSP,&LAST_PSP ; save PSP for check compiling, used by QREVEAL ADD #4,W ; by default make room for two words... - MOV W,&DDP ; + MOV W,&DP ; MOV @RSP+,PC ; RET W is the new DP value ) ; X is LAST_THREAD > used by compiling words: CREATE, DEFER, :... COLONNEXT ; Y is NFA ) .SWITCH DTC ; Direct Threaded Code select .CASE 1 ; - MOV #1284h,-4(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL) - SUB #2,&DDP ; + MOV #DOCOL,-4(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL) + SUB #2,&DP ; .CASE 2 ; MOV #120Dh,-4(W) ; compile PUSH IP 3~ - MOV #1284h,-2(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = EXIT) + MOV #DOCOL,-2(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = EXIT) .CASE 3 ; MOV #120Dh,-4(W) ; compile PUSH IP 3~ MOV #400Dh,-2(W) ; compile MOV PC,IP 1~ MOV #522Dh,0(W) ; compile ADD #4,IP 1~ MOV #4D30h,+2(W) ; compile MOV @IP+,PC 4~ - ADD #4,&DDP ; + ADD #4,&DP ; .ENDCASE ; MOV #-1,&STATE ; enter compiling state MOV @IP+,PC ; @@ -1916,14 +1504,8 @@ COLONNEXT ; Y is NFA ) ;;Z ?REVEAL -- if no stack mismatch, link this new word in the CURRENT vocabulary QREVEAL CMP PSP,&LAST_PSP ; Check SP with its saved value by :, :NONAME, CODE... - JNZ BAD_CSP ; if stack mismatch. -GOOD_CSP MOV &LAST_NFA,Y ; - MOV &LAST_THREAD,X ; -REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA (for NONAME: [LAST_THREAD] --> unused PA reg) - MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD] (for NONAME: LAST_NFA --> unused PA reg) - MOV @IP+,PC - -BAD_CSP mDOCOL + JZ LINK_NFA ; see MARKER +BAD_CSP mASM2FORTH ; if stack mismatch. .word XSQUOTE .byte 15,"stack mismatch!" FABORT_TERM .word ABORT_TERM @@ -1940,49 +1522,29 @@ SEMICOLON CMP #0,&STATE ; if interpret mode, semicolon becomes a com FORTHWORD "IMMEDIATE" ; https://forth-standard.org/standard/core/IMMEDIATE ; IMMEDIATE -- make last definition immediate -IMMEDIATE MOV &LAST_NFA,Y ; Y = NFA|unused_PA_reg as lure for :NONAME - BIS.B #BIT7,0(Y) ; - MOV @IP+,PC +IMMEDIATE MOV &LAST_NFA,Y ; Y = NFA|unused_PA_reg (as lure for :NONAME) + BIS.B #1,0(Y) ;4 FIND process more easier with bit0 than bit7 +NEXTADR MOV @IP+,PC FORTHWORD "CREATE" ; https://forth-standard.org/standard/core/CREATE ; CREATE <name> -- define a CONSTANT with its next address ; Execution: ( -- a-addr ) ; a-addr is the address of name's data field ; ; the execution semantics of name may be extended by using DOES> -CREATE CALL #HEADER ; -- W = DDP - MOV #1286h,-4(W) ;4 -4(W) = CFA = CALL R6 = rDOCON +CREATE CALL #HEADER ; -- W = DP + MOV #DOCON,-4(W) ;4 -4(W) = CFA = CALL rDOCON MOV W,-2(W) ;3 -2(W) = PFA = W = next address JMP REVEAL ; to link the definition in vocabulary - .IFDEF CORE_COMPLEMENT FORTHWORD "DOES>" ; https://forth-standard.org/standard/core/DOES ; DOES> -- set action for the latest CREATEd definition DOES MOV &LAST_CFA,W ; W = CFA of CREATEd word - MOV #1285h,0(W) ; replace old CFA of CREATE by new CFA CALL R5 = rDODOES + MOV #DODOES,0(W) ; replace CALL rDOCON of CREATE by new CFA: CALL rDODOES MOV IP,2(W) ; replace PFA by the address after DOES> as execution address - MOV @RSP+,IP ; - MOV @IP+,PC ; exit of the new created word - - FORTHWORD "CONSTANT" -;https://forth-standard.org/standard/core/CONSTANT -;C CONSTANT <name> n -- define a Forth CONSTANT -CONSTANT CALL #HEADER ; W = DDP = CFA + 2 words - MOV #1286h,-4(W) ; CFA = CALL R6 = rDOCON - MOV TOS,-2(W) ; PFA = n - MOV @PSP+,TOS ; -- - JMP REVEAL ; to link the definition in vocabulary - - FORTHWORD "VARIABLE" -;https://forth-standard.org/standard/core/VARIABLE -;C VARIABLE <name> -- define a Forth VARIABLE -VARIABLE CALL #HEADER ; W = DDP = CFA + 2 words - MOV #1287h,-4(W) ; CFA = CALL R7 = rDOVAR, PFA is undefined - JMP REVEAL ; to link created VARIABLE in vocabulary + MOV @RSP+,IP ; which ends the.. + MOV @IP+,PC ; ..of a CREATE definition. - .ENDIF ; CORE_COMPLEMENT - - .IFDEF DEFERRED FORTHWORD ":NONAME" ; https://forth-standard.org/standard/core/ColonNONAME ; :NONAME -- xt @@ -1990,312 +1552,183 @@ VARIABLE CALL #HEADER ; W = DDP = CFA + 2 words ; X is the LAST_THREAD lure value for REVEAL ; Y is the LAST_NFA lure value for REVEAL and IMMEDIATE ; ...because we don't want to modify the word set ! - PUSH #COLONNEXT ; define COLONNEXT as HEADERLESS RET + PUSH #COLONNEXT ; define COLONNEXT as HEADEREND RET HEADERLESS SUB #2,PSP ; common part of :NONAME and CODENNM MOV TOS,0(PSP) ; - MOV &DDP,W ; + MOV &DP,W ; BIT #1,W ; ADDC #0,W ; W = aligned CFA MOV W,TOS ; -- xt aligned CFA of :NONAME | CODENNM - MOV #210h,X ; X = 210h = unused PA register address (lure for REVEAL) - MOV X,Y ;1 - ADD #2,Y ;1 Y = 212h = unused PA register address (lure for REVEAL and IMMEDIATE) + MOV #212h,X ; MOV @X,-2(Y) writes to 210h = unused PA register address (lure for REVEAL and IMMEDIATE) + MOV X,Y ; MOV Y,0(X) writes to 212h = unused PA register address (lure for REVEAL) JMP HEADEREND ; -; https://forth-standard.org/standard/core/DEFER -; Skip leading space delimiters. Parse name delimited by a space. -; Create a definition for name with the execution semantics defined below. -; -; name Execution: -- -; Execute the xt that name is set to execute, i.e. NEXT (nothing), -; until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name. - FORTHWORD "DEFER" - CALL #HEADER - MOV #4030h,-4(W) ;4 first CELL = MOV @PC+,PC = BR... - MOV #NEXT_ADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default - JMP REVEAL ; to link created word in vocabulary - -; DEFER! ( xt CFA_DEFERed_WORD -- ) -; FORTHWORD "DEFER!" -DEFERSTORE MOV @PSP+,2(TOS) ; -- CFA_DEFERed_WORD xt --> [PFA_DEFERed_WORD] - MOV @PSP+,TOS ; -- - MOV @IP+,PC ; +;; https://forth-standard.org/standard/core/DEFER +;; Skip leading space delimiters. Parse name delimited by a space. +;; Create a definition for name with the execution semantics defined below. +;; +;; name Execution: -- +;; Execute the xt that name is set to execute, i.e. NEXT (nothing), +;; until the phrase ' word IS name is executed, causing a new value of xt to be assigned to name. +; FORTHWORD "DEFER" +; CALL #HEADER +; MOV #4030h,-4(W) ;4 first CELL = MOV @PC+,PC = BR #addr +; MOV #NEXTADR,-2(W) ;3 second CELL = ...mNEXT : do nothing by default +; JMP REVEAL ; to link created word in vocabulary ; IS <name> xt -- -; used like this: -; DEFER DISPLAY create a "do nothing" definition (2 CELLS) + +; used like this (high level defn.): +; DEFER DISPLAY create a "do nothing" definition (2 CELLS) + +; or (low level defn.): +; CODE DISPLAY create a "do nothing" definition (2 CELLS) +; MOV #NEXT_ADR,PC NEXT_ADR is the address of NEXT code: MOV @IP+,PC +; ENDCODE + ; inline command : ' U. IS DISPLAY U. becomes the runtime of the word DISPLAY -; or in a definition : ... ['] U. IS DISPLAY ... -; KEY, EMIT, CR, ACCEPT and WARM are examples of DEFERred words +; or in a definition : ... ['] U. IS DISPLAY ... ; +; KEY, EMIT, ACCEPT are examples of DEFERred words FORTHWORDIMM "IS" ; immediate IS PUSH IP - CMP #0,&STATE - JZ IS_EXEC -IS_COMPILE ASMtoFORTH + CMP #0,&STATE + JNZ IS_COMPILE +IS_EXEC mASM2FORTH + .word TICK + mNEXTADR + MOV @RSP+,IP +DEFERSTORE MOV @PSP+,2(TOS) ; -- CFA_DEFERed_WORD xt --> [PFA_DEFERed_WORD] + MOV @PSP+,TOS ; -- + MOV @IP+,PC ; + +IS_COMPILE mASM2FORTH .word BRACTICK ; find the word, compile its CFA as literal .word lit,DEFERSTORE,COMMA ; compile DEFERSTORE .word EXIT -IS_EXEC ASMtoFORTH - .word TICK,DEFERSTORE ; find the word, leave its CFA on the stack and execute DEFERSTORE - .word EXIT - - .ENDIF ; DEFERRED - - .IFDEF MSP430ASSEMBLER FORTHWORD "CODE" ; a CODE word must be finished with ENDCODE ASMCODE CALL #HEADER ; (that sets CFA and PFA) -ASMCODE1 SUB #4,&DDP ; remove default CFA and PFA +ASMCODE1 SUB #4,&DP ; remove default CFA and PFA ASMCODE2 - .IFDEF EXTENDED_ASM + .IFDEF EXTENDED_ASM MOV #0,&RPT_WORD ; clear RPT instruction - .ENDIF - mDOCOL - .word ALSO,ASSEMBLER,EXIT + .ENDIF + JMP ASSEMBLER ; add ASSEMBLER in CONTEXT stack ; HDNCODE (hidden CODE) is used to define a CODE word which must not to be executed by FORTH interpreter ; i.e. typically an assembler word called by CALL and ended by RET, or an interrupt routine ended by RETI. -; ASM words are only usable in ASSEMBLER defined words +; HDNCODE words are only usable in ASSEMBLER definitions. FORTHWORD "HDNCODE" MOV #BODYASSEMBLER,&CURRENT ; select ASSEMBLER word set to link this HDNCODE definition JMP ASMCODE asmword "ENDCODE" ; test PSP balancing then restore previous CONTEXT -ENDCODE mDOCOL ; and set CURRENT = CONTEXT (to also end ASM definitions) +ENDCODE mDOCOL ; and set CURRENT = CONTEXT (to also terminate HDNCODE definitions) .word QREVEAL -ENDCODE1 .word PREVIOUS,DEFINITIONS,EXIT + mNEXTADR + MOV @RSP+,IP +ENDCODEND MOV &CONTEXT+2,&CURRENT ;5 to do DEFINITIONS (before previous) + JMP PREVIOUS ; - .IFDEF DEFERRED FORTHWORD "CODENNM" ; CODENoNaMe is the assembly counterpart of :NONAME CODENNM PUSH #ASMCODE1 ; define HEADERLESS return JMP HEADERLESS ; that makes room for CFA and PFA - .ENDIF ; here are 3 words used to switch FORTH <--> ASSEMBLER ; COLON -- compile DOCOL, remove ASSEMBLER from CONTEXT and CURRENT, switch to compilation state asmword "COLON" - MOV &DDP,W - .SWITCH DTC - .CASE 1 - MOV #1284h,0(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL) - ADD #2,&DDP - .CASE 2 + MOV &DP,W + .SWITCH DTC + .CASE 1 + MOV #DOCOL,0(W) ; compile CALL R4 = rDOCOL ([rDOCOL] = XDOCOL) + ADD #2,&DP + .CASE 2 MOV #120Dh,0(W) ; compile PUSH IP -COLON1 MOV #1284h,2(W) ; compile CALL R4 = rDOCOL - ADD #4,&DDP - .CASE 3 ; inlined DOCOL +COLON1 MOV #DOCOL,2(W) ; compile CALL R4 = rDOCOL + ADD #4,&DP + .CASE 3 ; inlined DOCOL MOV #120Dh,0(W) ; compile PUSH IP COLON1 MOV #400Dh,2(W) ; compile MOV PC,IP MOV #522Dh,4(W) ; compile ADD #4,IP MOV #4D30h,6(W) ; compile MOV @IP+,PC - ADD #8,&DDP ; - .ENDCASE ; DTC - -COLON2 MOV #-1,&STATE ; enter in compile state - mDOCOL - .word PREVIOUS,DEFINITIONS,EXIT ; restore previous CONTEXT and set CURRENT = CONTEXT + ADD #8,&DP ; + .ENDCASE ; DTC +COLON2 MOV #-1,&STATE ;3 enter in compile state + JMP ENDCODEND ;2 to do PREVIOUS DEFINITIONS ; LO2HI -- same as COLON but without saving IP asmword "LO2HI" - .SWITCH DTC - .CASE 1 ; compile 2 words - MOV &DDP,W + .SWITCH DTC + .CASE 1 ; compile 2 words + MOV &DP,W MOV #12B0h,0(W) ; compile CALL #EXIT, 2 words 4+6=10~ MOV #EXIT,2(W) - ADD #4,&DDP + ADD #4,&DP JMP COLON2 - .ELSECASE ; CASE 2 : compile 1 word, CASE 3 : compile 3 words - SUB #2,&DDP ; to skip PUSH IP - MOV &DDP,W + .ELSECASE ; CASE 2 : compile 1 word, CASE 3 : compile 3 words + SUB #2,&DP ; to skip PUSH IP + MOV &DP,W JMP COLON1 - .ENDCASE + .ENDCASE ; HI2LO -- immediate, switch to low level, set interpretation state, add ASSEMBLER to CONTEXT FORTHWORDIMM "HI2LO" ; - mDOCOL - .word HERE,CELLPLUS,COMMA ; compile HERE+2 - .word LEFTBRACKET ; switch to interpret state - .word ASMCODE2 ; add ASSEMBLER in context - .word EXIT - - .ENDIF ; MSP430ASSEMBLER - - .IFDEF CONDCOMP -; ------------------------------------------------------------------------------ -; forthMSP430FR : CONDITIONNAL COMPILATION -; ------------------------------------------------------------------------------ - .include "forthMSP430FR_CONDCOMP.asm" - .ENDIF - - .IFDEF CORE_COMPLEMENT -; ------------------------------------------------------------------------------ -; CONTROL STRUCTURES -; ------------------------------------------------------------------------------ -; THEN and BEGIN compile nothing -; DO compile one word -; IF, ELSE, AGAIN, UNTIL, WHILE, REPEAT, LOOP & +LOOP compile two words -; LEAVE compile three words - - FORTHWORDIMM "IF" ; immediate -; https://forth-standard.org/standard/core/IF -; IF -- IFadr initialize conditional forward branch -IFF SUB #2,PSP ; - MOV TOS,0(PSP) ; - MOV &DDP,TOS ; -- HERE - ADD #4,&DDP ; compile one word, reserve one word - MOV #QFBRAN,0(TOS) ; -- HERE compile QFBRAN - .ENDIF ; CORE_COMPLEMENT -CELLPLUS ADD #2,TOS ; -- HERE+2=IFadr - MOV @IP+,PC - - .IFDEF CORE_COMPLEMENT - FORTHWORDIMM "ELSE" ; immediate -; https://forth-standard.org/standard/core/ELSE -; ELSE IFadr -- ELSEadr resolve forward IF branch, leave ELSEadr on stack -ELSS ADD #4,&DDP ; make room to compile two words - MOV &DDP,W ; W=HERE+4 - MOV #BRAN,-4(W) - MOV W,0(TOS) ; HERE+4 ==> [IFadr] - SUB #2,W ; HERE+2 - MOV W,TOS ; -- ELSEadr - MOV @IP+,PC - - FORTHWORDIMM "THEN" ; immediate -; https://forth-standard.org/standard/core/THEN -; THEN IFadr -- resolve forward branch -THEN MOV &DDP,0(TOS) ; -- IFadr - MOV @PSP+,TOS ; -- - MOV @IP+,PC - - FORTHWORDIMM "BEGIN" ; immediate -; https://forth-standard.org/standard/core/BEGIN -; BEGIN -- BEGINadr initialize backward branch - MOV #HERE,PC ; -- HERE - - FORTHWORDIMM "UNTIL" ; immediate -; https://forth-standard.org/standard/core/UNTIL -; UNTIL BEGINadr -- resolve conditional backward branch -UNTIL MOV #QFBRAN,X -UNTIL1 ADD #4,&DDP ; compile two words - MOV &DDP,W ; W = HERE - MOV X,-4(W) ; compile Bran or QFBRAN at HERE - MOV TOS,-2(W) ; compile bakcward adr at HERE+2 - MOV @PSP+,TOS - MOV @IP+,PC - - FORTHWORDIMM "AGAIN" ; immediate -; https://forth-standard.org/standard/core/AGAIN -;X AGAIN BEGINadr -- resolve uncondionnal backward branch -AGAIN MOV #BRAN,X - JMP UNTIL1 - - FORTHWORDIMM "WHILE" ; immediate -; https://forth-standard.org/standard/core/WHILE -; WHILE BEGINadr -- WHILEadr BEGINadr -WHILE mDOCOL - .word IFF,SWAP,EXIT - - FORTHWORDIMM "REPEAT" ; immediate -; https://forth-standard.org/standard/core/REPEAT -; REPEAT WHILEadr BEGINadr -- resolve WHILE loop -REPEAT mDOCOL - .word AGAIN,THEN,EXIT - - FORTHWORDIMM "DO" ; immediate -; https://forth-standard.org/standard/core/DO -; DO -- DOadr L: -- 0 -DO SUB #2,PSP ; - MOV TOS,0(PSP) ; - ADD #2,&DDP ; make room to compile xdo - MOV &DDP,TOS ; -- HERE+2 - MOV #xdo,-2(TOS) ; compile xdo - ADD #2,&LEAVEPTR ; -- HERE+2 LEAVEPTR+2 - MOV &LEAVEPTR,W ; - MOV #0,0(W) ; -- HERE+2 L-- 0 - MOV @IP+,PC - - FORTHWORD "I" -; https://forth-standard.org/standard/core/I -; I -- n R: sys1 sys2 -- sys1 sys2 -; get the innermost loop index -II SUB #2,PSP ;1 make room in TOS - MOV TOS,0(PSP) ;3 - MOV @RSP,TOS ;2 index = loopctr - fudge - SUB 2(RSP),TOS ;3 - MOV @IP+,PC ;4 13~ - - FORTHWORDIMM "LOOP" ; immediate -; https://forth-standard.org/standard/core/LOOP -; LOOP DOadr -- L-- an an-1 .. a1 0 -LOO MOV #xloop,X -LOOPNEXT ADD #4,&DDP ; make room to compile two words - MOV &DDP,W - MOV X,-4(W) ; xloop --> HERE - MOV TOS,-2(W) ; DOadr --> HERE+2 -; resolve all "leave" adr -LEAVELOOP MOV &LEAVEPTR,TOS ; -- Adr of top LeaveStack cell - SUB #2,&LEAVEPTR ; -- - MOV @TOS,TOS ; -- first LeaveStack value - CMP #0,TOS ; -- = value left by DO ? - JZ LOOPEND - MOV W,0(TOS) ; move adr after loop as UNLOOP adr - JMP LEAVELOOP -LOOPEND MOV @PSP+,TOS - MOV @IP+,PC - - FORTHWORDIMM "+LOOP" ; immediate -; https://forth-standard.org/standard/core/PlusLOOP -; +LOOP adrs -- L-- an an-1 .. a1 0 -PLUSLOOP MOV #xploop,X - JMP LOOPNEXT - .ENDIF ; CORE_COMPLEMENT + ADD #2,&DP ; HERE+2 + MOV &DP,W ; W = HERE+2 + MOV W,-2(W) ; compile HERE+2 to HERE + MOV #0,&STATE ; LEFTBRACKET + JMP ASMCODE2 ; add ASSEMBLER in context - .IFDEF VOCABULARY_SET ;------------------------------------------------------------------------------- -; WORDS SET for VOCABULARY, not ANS compliant +; WORDS SET for VOCABULARY, not ANS compliant, ;------------------------------------------------------------------------------- - .IFNDEF DOES - FORTHWORD "DOES>" -; https://forth-standard.org/standard/core/DOES -; DOES> -- set action for the latest CREATEd definition -DOES MOV &LAST_CFA,W ; W = CFA of CREATEd word - MOV #1285h,0(W) ; replace CFA (DOCON) by new CFA (DODOES) - MOV IP,2(W) ; replace PFA by the address after DOES> as execution address - MOV @RSP+,IP ; - MOV @IP+,PC ; exit of the new created word - .ENDIF - - FORTHWORD "VOCABULARY" -;X VOCABULARY -- create a vocabulary, up to 7 vocabularies in CONTEXT + .IFDEF VOCABULARY_SET + FORTHWORD "WORDSET" +;X VOCABULARY -- create a new word_set VOCABULARY mDOCOL .word CREATE .SWITCH THREADS .CASE 1 - .word lit,0,COMMA ; will keep the NFA of the last word of the future created vocabularies + .word lit,0,COMMA ; W = DP + mNEXTADR ; .ELSECASE - .word lit,THREADS,lit,0,xdo -VOCABULOOP .word lit,0,COMMA - .word xloop,VOCABULOOP - .ENDCASE - .word HERE ; link via LASTVOC the future created vocabulary - .word LIT,LASTVOC,DUP - .word FETCH,COMMA ; compile [LASTVOC] to HERE+ - .word STORE ; store (HERE - 2) to LASTVOC - .word DOES ; compile CFA and PFA for the future defined vocabulary + mNEXTADR ; W = DP + MOV #THREADS,X ; count +VOCABULOOP MOV #0,0(W) ; DP = BODY first + ADD #2,W + SUB #1,X + JNZ VOCABULOOP + .ENDCASE ; W = DP + MOV &LASTVOC,0(W) + MOV W,&LASTVOC + ADD #2,W + MOV W,&DP ; update DP + mASM2FORTH + .word DOES .ENDIF ; VOCABULARY_SET -VOCDOES .word LIT,CONTEXT,STORE - .word EXIT +VOCDOES mNEXTADR ; adds WORD-SET first in context stack + .IFDEF VOCABULARY_SET +ALSO MOV #7,Y ;2 -- move up 7 words, first word in last + MOV #CONTEXT+12,X ;2 X=src +ALSOLOOP MOV @X,2(X) ; X=src < Y=dst copy W bytes beginning with the end + SUB #2,X + SUB #1,Y + JNZ ALSOLOOP + .ELSE ; VOCABULARY_SET off ; VOCDOES is used only by the assembler to switch from HIlevel to LOlevel environments + MOV #BODYFORTH,&CONTEXT+2;4 copy BODYFORTH --> 2th cell of CONTEXT + .ENDIF ; VOCABULARY_SET + MOV TOS,&CONTEXT ;3 copy word-set BODY --> first cell of CONTEXT + MOV #DROPEXIT,PC .IFDEF VOCABULARY_SET FORTHWORD "FORTH" - .ENDIF ; VOCABULARY_SET -;X FORTH -- ; set FORTH the first context vocabulary; FORTH must be the first vocabulary + .ENDIF +;X FORTH -- ; add FORTH as first context word-set FORTH ; leave BODYFORTH on the stack and run VOCDOES CALL rDODOES ; Code Field Address (CFA) of FORTH PFAFORTH .word VOCDOES ; Parameter Field Address (PFA) of FORTH -BODYFORTH ; BODY of FORTH - .word lastforthword +BODYFORTH .word lastforthword ; BODY of FORTH .SWITCH THREADS .CASE 2 .word lastforthword1 @@ -2364,15 +1797,14 @@ BODYFORTH ; BODY of FORTH .word voclink voclink .set $-2 - .IFDEF MSP430ASSEMBLER .IFDEF VOCABULARY_SET - FORTHWORD "ASSEMBLER" - .ENDIF ; VOCABULARY_SET -;X ASSEMBLER -- ; set ASSEMBLER the first context vocabulary +; FORTHWORD "ASSEMBLER" + FORTHWORD "hidden" ; cannot be found by FORTH interpreter because the string is not capitalized + .ENDIF +;X ASSEMBLER -- ; add ASSEMBLER as first context word-set ASSEMBLER CALL rDODOES ; leave BODYASSEMBLER on the stack and run VOCDOES - .word VOCDOES -BODYASSEMBLER - .word lastasmword + .word VOCDOES +BODYASSEMBLER .word lastasmword .SWITCH THREADS .CASE 2 .word lastasmword1 @@ -2440,256 +1872,203 @@ BODYASSEMBLER .ENDCASE .word voclink voclink .set $-2 - .ENDIF ; MSP430ASSEMBLER - - .IFDEF VOCABULARY_SET - FORTHWORD "ALSO" - .ENDIF ; VOCABULARY_SET -;X ALSO -- make room to put a vocabulary as first in context -ALSO MOV #12,W ; -- move up 6 words, 8th word of CONTEXT area must remain to 0 - MOV #CONTEXT+12,X ; X=src - MOV X,Y - ADD #2,Y ; Y=dst -MOVEUP SUB #1,X - SUB #1,Y - MOV.B @X,0(Y) ; if X=src < Y=dst copy W bytes beginning with the end - SUB #1,W - JNZ MOVEUP - MOV @IP+,PC .IFDEF VOCABULARY_SET FORTHWORD "PREVIOUS" +;X PREVIOUS -- pop first word-set out of context stack +PREVIOUS MOV #8,Y ;1 move down 8 words, first with CONTEXT+2 addr, end when NULL_WORD is moved + MOV #CONTEXT+2,X ;2 X = CONTEXT+2 = org, X-2 = CONTEXT = dst +PREVIOUSLOO CMP #0,0(X) ;3 [org] = 0 ? + JZ PREVIOUSEND ;2 to avoid scratch of the first CONTEXT cell by human mistake, then to skip useless loops + MOV @X+,-4(X) ;4 + SUB #1,Y ;1 + JNZ PREVIOUSLOO ;2 7~ loop * 8 = 56 ~ +PREVIOUSEND MOV @IP+,PC ;4 + .ELSE ; +PREVIOUS MOV #BODYFORTH,&CONTEXT +ONLY MOV #0,&CONTEXT+2 ; then execute ONLY + MOV @IP+,PC .ENDIF ; VOCABULARY_SET -;X PREVIOUS -- pop last vocabulary out of context -PREVIOUS MOV #14,W ; move down 7 words, first with the 8th word equal to 0 - MOV #CONTEXT,Y ; Y=dst - MOV Y,X - ADD #2,X ; X=src -MOVEDOWN MOV.B @X+,0(Y) ; if X=src > Y=dst copy W bytes - ADD #1,Y - SUB #1,W - JNZ MOVEDOWN -MOVEND MOV @IP+,PC .IFDEF VOCABULARY_SET FORTHWORD "ONLY" - .ENDIF ; VOCABULARY_SET -;X ONLY -- cut context list to access only first vocabulary, ex.: FORTH ONLY +;X ONLY -- cut the context stack to access only the first word-set, ex.: FORTH ONLY ONLY MOV #0,&CONTEXT+2 MOV @IP+,PC - .IFDEF VOCABULARY_SET FORTHWORD "DEFINITIONS" - .ENDIF ; VOCABULARY_SET ;X DEFINITIONS -- set last context vocabulary as entry for further defining words DEFINITIONS MOV &CONTEXT,&CURRENT MOV @IP+,PC - - .IFDEF USE_MOVE ; if UTILITY.asm|ANS_COMP.asm - FORTHWORD "MOVE" -; https://forth-standard.org/standard/core/MOVE -; MOVE addr1 addr2 u -- smart move -; VERSION FOR 1 ADDRESS UNIT = 1 CHAR -MOVE MOV TOS,W ; W = cnt - MOV @PSP+,Y ; Y = addr2 = dst - MOV @PSP+,X ; X = addr1 = src - MOV @PSP+,TOS ; pop new TOS - CMP #0,W ; count = 0 ? - JZ MOVEND ; already done ! - CMP X,Y ; Y=dst = X=src ? - JZ MOVEND ; already done ! - JNC MOVEDOWN ; if Y=dst < X=src ; see PREVIOUS - ADD W,Y ; move beginning with the end - ADD W,X ; - JMP MOVEUP ; if Y=dst > X=src ; see ALSO - .ENDIF + .ENDIF ; VOCABULARY_SET ;------------------------------------------------------------------------------- -; MEMORY MANAGEMENT +; FASTFORTH environment management: DP, LASTVOC, CURRENT, CONTEXT and THREADS ;------------------------------------------------------------------------------- -STATE_DOES ; execution part of PWR_STATE ; sorry, doesn't restore search order pointers - .word FORTH,ONLY,DEFINITIONS - .word $+2 ; -- BODY IP is free - .IFDEF VOCABULARY_SET - MOV @TOS+,W ; -- BODY+2 W = old VOCLINK = VLK +ENV_COPY + .IFDEF VOCABULARY_SET + MOV #24,T ; bytes count of extended RST environment: DP,LASTVOC,CURRENT,CONTEXT(8),null_word .ELSE - MOV &WIPE_VOC,W ; W = VOCLINK = VLK - .ENDIF - MOV W,&LASTVOC ; restore (or init) LASTVOC in RAM - MOV @TOS,TOS ; -- OLD_DP - MOV TOS,&DDP ; -- DP restore (or init) DP in RAM - ; then restore words link(s) with their value < old DP - .SWITCH THREADS - .CASE 1 ; mono thread vocabularies -MARKALLVOC MOV W,Y ; -- DP W=VLK Y=VLK -MRKWORDLOOP MOV -2(Y),Y ; -- DP W=VLK Y=NFA - CMP Y,TOS ; -- DP CMP = TOS-Y : OLD_DP-NFA - JNC MRKWORDLOOP ; loop back if TOS<Y : OLD_DP<NFA - MOV Y,-2(W) ; W=VLK X=THD Y=NFA refresh thread with good NFA - MOV @W,W ; -- DP W=[VLK] = next voclink - CMP #0,W ; -- DP W=[VLK] = next voclink end of vocs ? - JNZ MARKALLVOC ; -- DP W=VLK no : loopback - .ELSECASE ; multi threads vocabularies -MARKALLVOC MOV #THREADS,IP ; -- DP W=VLK - MOV W,X ; -- DP W=VLK X=VLK -MRKTHRDLOOP MOV X,Y ; -- DP W=VLK X=VLK Y=VLK - SUB #2,X ; -- DP W=VLK X=THD (thread ((case-2)to0)) -MRKWORDLOOP MOV -2(Y),Y ; -- DP W=VLK Y=NFA - CMP Y,TOS ; -- DP CMP = TOS-Y : DP-NFA - JNC MRKWORDLOOP ; loop back if TOS<Y : DP<NFA -MARKTHREAD MOV Y,0(X) ; W=VLK X=THD Y=NFA refresh thread with good NFA - SUB #1,IP ; -- DP W=VLK X=THD Y=NFA IP=CFT-1 - JNZ MRKTHRDLOOP ; loopback to compare NFA in next thread (thread-1) - MOV @W,W ; -- DP W=[VLK] = next voclink - CMP #0,W ; -- DP W=[VLK] = next voclink end of vocs ? - JNZ MARKALLVOC ; -- DP W=VLK no : loopback - .ENDCASE ; of THREADS ; -- DP - MOV @PSP+,TOS ; - MOV @RSP+,IP ; -NEXT_ADR MOV @IP+,PC ; - -;------------------------------------------------------------------------------- -; FASTFORTH START: set DP, VOCLINK, CURRENT and CONTEXT -;------------------------------------------------------------------------------- - FORTHWORD "PWR_STATE" ; executed by POWER_ON and ABORT_TERM; does PWR_HERE word set -PWR_STATE CALL rDODOES ; DOES part of MARKER : resets pointers DP, voclink - .word STATE_DOES ; execution vector of PWR_STATE - .IFDEF VOCABULARY_SET -MARKVOC .word lastvoclink ; initialised by forthMSP430FR.asm as voclink value - .ENDIF -MARKDP .word ROMDICT ; initialised by forthMSP430FR.asm as DP value - - FORTHWORD "RST_STATE" ; executed by <reset>, COLD, SYSRSTIV error; does RST_HERE word set -RST_STATE MOV &RST_DP,&MARKDP ; INIT value above (FRAM value) - .IFDEF VOCABULARY_SET - MOV &RST_VOC,&MARKVOC ; INIT value above (FRAM value) - .ENDIF - JMP PWR_STATE - - FORTHWORD "PWR_HERE" ; define word set bound for POWER_ON, ABORT_TERM. -PWR_HERE MOV &DDP,&MARKDP - .IFDEF VOCABULARY_SET - MOV &LASTVOC,&MARKVOC + MOV #10,T ; bytes count of RST environment: DP,LASTVOC,CURRENT,CONTEXT(2) .ENDIF +ENV_LOOP MOV @X+,0(W) + ADD #2,W + SUB #2,T ; words-1 + JNZ ENV_LOOP + MOV @RSP+,PC + + FORTHWORD "RST_SET" ; define actual environment as new RESET environment +RST_SET MOV #DP,X ; org = RAM value (DP first) + MOV #RST_DP,W ; dst = FRAM value (RST_DP first), see \inc\ThingsInFirst.inc + CALL #ENV_COPY ; copy environment RAM --> FRAM RST, use T,W,X MOV @IP+,PC - FORTHWORD "RST_HERE" ; define word set bound for <reset>, COLD, SYSRSTIV error. -RST_HERE MOV &DDP,&RST_DP - .IFDEF VOCABULARY_SET - MOV &LASTVOC,&RST_VOC - .ENDIF - JMP PWR_HERE ; and obviously the same for POWER_ON... + FORTHWORD "RST_RET" ; init / return_to_previous RESET or MARKER environment +RST_RET MOV #RST_DP,X ; org = FRAM value (first RST_DP), see \inc\ThingsInFirst.inc + MOV @X,S ; S = restored DP, used below for comparaison with NFAs + MOV #DP,W ; dst = RAM value (first DP) + CALL #ENV_COPY ; copy environment FRAM RST --> RAM, use T,W,X +;-----------------------------------; + MOV &LASTVOC,W ; W = init/restored LASTVOC + .SWITCH THREADS ; init/restore THREAD(s) with NFAs value < init/restored DP, for all word set + .CASE 1 ; mono thread word-set +MARKALLVOC MOV W,Y ; W=VLK Y = VLK +MRKWORDLOOP MOV -2(Y),Y ; W=VLK Y = [THD_n] then [LFA] = NFA + CMP Y,S ; Y=NFA S=DP CMP = S-Y : OLD_DP-NFA + JNC MRKWORDLOOP ; loop back if S<Y : OLD_DP<NFA + MOV Y,-2(W) ; W=VLK X=THD Y=NFA refresh thread with good NFA + .ELSECASE ; multi threads word-set +MARKALLVOC MOV #THREADS,T ; S=DP T=ThdCnt (Threads Count), VLK = THD_n+1 + MOV W,X ; W = VLK X = VLK then THD_n (VOCLINK first, then THREADn) +MRKTHRDLOOP MOV X,Y ; + SUB #2,X ; +MRKWORDLOOP MOV -2(Y),Y ; Y = NFA = [THD_n] then [LFA] + CMP Y,S ; Y = NFA S=DP CMP = S-Y : DP-NFA + JNC MRKWORDLOOP ; loop back if S<Y : DP<NFA (if not_carry = if borrow) +MARKTHREAD MOV Y,0(X) ; Y=NFA X=THD_n refresh thread with good NFA + SUB #1,T ; T=ThdCnt-1 + JNZ MRKTHRDLOOP ; loopback to process NFA of next thread (thread-1) + .ENDCASE ; of THREADS ; + MOV @W,W ; W=[VLK] = VLK-1 + CMP #0,W ; end of vocs ? + JNZ MARKALLVOC ; W=VLK-1 no : loopback + MOV @IP+,PC ; ;------------------------------------------------------------------------------- -; PUC 6.2: SELECT PWR_STATE|RST_STATE|DEEP_RESET <== INI_FORTH +; PUC 7 : SELECT RST_RET|DEEP_RESET <== INIT_FORTH <== (PUC,SYS,QABORT) ;------------------------------------------------------------------------------- -SEL_P_R_D CMP #0Eh,TOS ; - JZ PWR_STATE ; if RSTIV_MEM = 14 (SYSSVSH event) - CMP #4,TOS ; - JGE RST_STATE ; if RSTIV_MEM >= 4 (RESET,COLD,SYS_FAILURES) - CMP #0,TOS ; - JGE PWR_STATE ; if RSTIV_MEM >= 0 (POWER_ON,WARM,ABORT") +SEL_RST_DEP CMP #0,TOS ; + JGE RST_RET ; if TOS >= 0 ;-----------------------------------; -; DEEP RESET ; if RSTIV_MEM < 0 +; DEEP RESET ; if TOS < 0 ;-----------------------------------; -; INIT SIGNATURES AREA ; +; DEEP INIT SIGNATURES AREA ; ;-----------------------------------; MOV #16,X ; max known SIGNATURES length = 12 bytes SIGNATLOOP SUB #2,X ; - MOV #-1,SIGNATURES(X) ; reset signature; WARNING ! DON'T CHANGE IMMEDIATE VALUE ! + MOV #-1,SIGNATURES(X) ; reset signatures; WARNING ! DON'T CHANGE IMMEDIATE VALUE ! JNZ SIGNATLOOP ; -;-----------------------------------; X = 0 ;-) -; INIT VECTORS INT ; -;-----------------------------------; +;-----------------------------------; +; DEEP INIT VECTORS INT ; X = 0 ;-) +;-----------------------------------; MOV #RESET,-2(X) ; write RESET at addr X-2 = FFFEh INIVECLOOP SUB #2,X ; MOV #COLD,-2(X) ; -2(X) = FFFCh first - CMP #0FFAEh,X ; init 41 vectors, FFFCh down to 0FFACh + CMP #0FFACh+2,X ; init 41 vectors, FFFCh down to 0FFACh JNZ INIVECLOOP ; all vectors are initialised to execute COLD routine -;-----------------------------------; -; INIT all "CALL #xxx_APP" ; -;-----------------------------------; - MOV #WIPE_INI,X ; WIPE_INI constants are in FRAM INFO - MOV @X+,&PFACOLD ; COLD_TERM as default COLD_APP --> PFACOLD - MOV @X+,&PFA_INI_FORTH ; RET_ADR|INI_FORTH_SD as default INI_SOFT_APP --> PFA_INI_FORTH - MOV @X+,&PFASLEEP ; RXON as default BACKGND_APP --> PFASLEEP - MOV @X+,&PFAWARM ; INIT_TERM|INIT_SD as default INI_HARD_APP --> PFAWARM - MOV @X+,&TERM_VEC ; TERMINAL_INT as default vector --> TERM_VEC -;-----------------------------------; -; INIT DP VOC_link ; -;-----------------------------------; - MOV @X+,&RST_DP ; ROMDICT --> RST_DP - .IFDEF VOCABULARY_SET - MOV @X+,&RST_VOC ; lastvoclink --> RST_VOC +;-----------------------------------; +; DEEP INIT Terminal Int vector ; +;-----------------------------------; + MOV #DEEP_ORG,X ; DEEP_ORG values are in FRAM INFO, see \inc\ThingsInFirst.inc + MOV @X+,&TERM_VEC ; TERMINAL_INT as default vector --> FRAM TERM_VEC +;-----------------------------------; +; DEEP INIT FRAM RST values ; 8 word values +;-----------------------------------; + MOV #RST_LEN,T ; bytes count + MOV #RST_ORG,W ; W = dst, X = org + CALL #ENV_LOOP ; + MOV #0,&RST_CONTEXT+2 ; to do FORTH ONLY +;-----------------------------------; +; WARM INIT threads of all word set ; +;-----------------------------------; + JMP RST_RET ; then go to DUP|PUCNEXT, resp. in QABORT|RESET +;-----------------------------------; + +; https://forth-standard.org/standard/core/MARKER +; MARKER +;name Execution: ( -- ) +;Restore all dictionary allocation and search order pointers to the state they had just prior to the +;definition of name. Remove the definition of name and all subsequent definitions. Restoration +;of any structures still existing that could refer to deleted definitions or deallocated data space is +;not necessarily provided. No other contextual information such as numeric base is affected. + +; FastForth provides all that is necessary for a real time application with MARKER definition, +; by adding a call to a custom subroutine to restore all user environment. +; the FORTH environment is it automaticaly restored. +MARKER_DOES ; restores RST environment saved by MARKER defn., + ; executes user defined subroutine (RET_ADR by default), + ; then executes RST_RET. + mNEXTADR ; -- BODY + .IFDEF VOCABULARY_SET + MOV TOS,X ; X = org (first : BODY=MARKER_DP) + MOV #RST_DP,W ; W = dst (first : RST_DP), see \inc\ThingsInFirst.inc + CALL #ENV_COPY ; copy FORTH environment FRAM MARKER --> FRAM RST + MOV X,TOS ; -- RET_ADR by default + .ELSE + MOV @TOS+,&RST_DP ; .ENDIF -;-----------------------------------; - JMP RST_STATE ; then return to LIT|WARM from resp. QABORT|RESET -;-----------------------------------; - -;=============================================================================== -; ┌┐ ┌─┐┬─┐ ┌─┐┌─┐┬─┐ ┌─┐┬ ┬┌─┐ ┌─┐┌─┐┬┬ ┬ ┬┬─┐┌─┐┌─┐ ┌─┐┌─┐┬ ┬ ┬ ┬┌─┐┬─┐┌─┐ -; ├┴┐│ │├┬┘ ├─┘│ │├┬┘ ├─┘│ ││ ├┤ ├─┤││ │ │├┬┘├┤ └─┐ ├┤ ├─┤│ │ ├─┤├┤ ├┬┘├┤ -; └─┘└─┘┴└─ ┴ └─┘┴└─ ┴ └─┘└─┘ └ ┴ ┴┴┴─┘└─┘┴└─└─┘└─┘ └ ┴ ┴┴─┘┴─┘ ┴ ┴└─┘┴└─└─┘ -;=============================================================================== -RESET -;=============================================================================== -; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET -;------------------------------------------------------------------------------- - BIS #3,&SFRRPCR ; pin RST becomes pin NMI with falling edge, so SYSRSTIV = 4 - BIS #10h,&SFRIE1 ; enable NMI interrupt ==> hardware RESET is redirected to COLD. - MOV #5A80h,&WDTCTL ; disable WDT RESET -;------------------------------------------------------------------------------- -; PUC 2: INIT STACKS -;------------------------------------------------------------------------------- - MOV #RSTACK,RSP ; init return stack - MOV #PSTACK,PSP ; init parameter stack -;------------------------------------------------------------------------------- -; PUC 3: init RAM to 0 -;------------------------------------------------------------------------------- - MOV #RAM_LEN,X -INITRAMLOOP SUB #2,X ; 1 - MOV #0,RAM_ORG(X) ; 3 - JNZ INITRAMLOOP ; 2 6 cycles loop ! -;------------------------------------------------------------------------------- -; PUC 4: I/O, RAM, RTC, CS, SYS initialisation limited to FastForth usage. -; All unused I/O are set as input with pullup resistor. -;------------------------------------------------------------------------------- - .include "TargetInit.asm" ; include target specific init code -;------------------------------------------------------------------------------- -; PUC 5: GET SYSRSTIV -;------------------------------------------------------------------------------- - MOV &RSTIV_MEM,TOS ; get RSTIV_MEM = Soft_SYSRSTIV - MOV #0,&RSTIV_MEM ; clear RSTIV_MEM - BIS &SYSRSTIV,TOS ; hard_SYSRSTIV|soft_SYSRSTIV --> TOS; SYSRSTIV = 0 + CALL @TOS+ ; -- USER_BODY executes user defined asm subroutine (RET_ADR by default), IP and TOS are free + MOV @PSP+,TOS ; -- + MOV @RSP+,IP ; + JMP RST_RET ; then performs RST_RET + + FORTHWORD "MARKER" ; definition part +;( "<spaces>name" -- ) +;Skip leading space delimiters. Parse name delimited by a space. Create a definition for name +;with the execution semantics defined above. ;------------------------------------------------------------------------------- -; PUC 6: START FORTH engine +;before that, it execute DOES part of previous definition if already exists. + PUSH &TOIN + mDOCOL + .word BL,WORDD,FIND + .word QFBRAN,MARKER_NEXT + .word DUP,EXECUTE +MARKER_NEXT mNEXTADR + MOV @PSP+,TOS ; + MOV @RSP+,IP + MOV @RSP+,&TOIN ;------------------------------------------------------------------------------- - CALL #INI_FORTH ; common ?ABORT|PUC "hybrid" subroutine with return to FORTH interpreter - .word WARM ; goto WARM, without return. See forthMSP430FR_TERM_xxx.asm -;-----------------------------------; + CALL #HEADER ;4 W = DP, Y = NFA, + MOV #1285h,-4(W) ;4 CFA = CALL rDODOES + MOV #MARKER_DOES,-2(W) ;4 PFA = MARKER_DOES + SUB #2,Y ;1 Y = NFA-2 = LFA = DP to be restored, W = FRAM MARKER_DDP + .IFDEF VOCABULARY_SET + MOV Y,&DP ; Y = previous DP (just before MARKER definition) + MOV #DP,X ; X = org = RAM DP, W = dst = MARKER_BODY + CALL #ENV_COPY ; copy environment RAM --> FRAM MARKER + MOV #RET_ADR,0(W) ;4 user defined subroutine by default = RET_ADR + ADD #2,W ;1 + MOV W,&DP ;4 set new RAM DP (after the end of MARKER definition) + .ELSE + MOV Y,0(W) ; DP to be restored + MOV #RET_ADR,2(W) ; MARKER subroutine + ADD #4,&DP ; + .ENDIF +LINK_NFA MOV &LAST_NFA,Y ; if no error, link this definition in its thread + MOV &LAST_THREAD,X ; +REVEAL MOV @X,-2(Y) ; [LAST_THREAD] --> LFA (for NONAME: LFA --> 210h unused PA reg) + MOV Y,0(X) ; LAST_NFA --> [LAST_THREAD] (for NONAME: [LAST_THREAD] --> 212h unused PA reg) +REVEAL_END MOV @IP+,PC - .IFDEF MSP430ASSEMBLER ;=============================================================================== ; ASSEMBLER OPTION ;=============================================================================== - .IFDEF EXTENDED_ASM - .include "forthMSP430FR_EXTD_ASM.asm" - .ELSE - .include "forthMSP430FR_ASM.asm" - .ENDIF - .ENDIF - .IFDEF UTILITY -;------------------------------------------------------------------------------- -; UTILITY WORDS OPTION -;------------------------------------------------------------------------------- - .include "ADDON/UTILITY.asm" - .ENDIF - .IFDEF FIXPOINT -;------------------------------------------------------------------------------- -; FIXED POINT OPERATORS OPTION -;------------------------------------------------------------------------------- - .include "ADDON/FIXPOINT.asm" + .IFDEF EXTENDED_ASM + .include "forthMSP430FR_EXTD_ASM.asm" + .ELSE + .include "forthMSP430FR_ASM.asm" .ENDIF + .IFDEF SD_CARD_LOADER ;------------------------------------------------------------------------------- ; SD CARD OPTIONS @@ -2697,21 +2076,23 @@ INITRAMLOOP SUB #2,X ; 1 .include "forthMSP430FR_SD_LowLvl.asm" ; SD primitives .include "forthMSP430FR_SD_INIT.asm" ; return to INIT_TERM; without use of IP,TOS .include "forthMSP430FR_SD_LOAD.asm" ; SD LOAD driver +; .include "forthMSP430FR_SD_LOAD_next.asm" ; SD LOAD driver .IFDEF SD_CARD_READ_WRITE .include "forthMSP430FR_SD_RW.asm" ; SD Read/Write driver - .ENDIF - .IFDEF SD_TOOLS - .include "ADDON/SD_TOOLS.asm" +; .include "forthMSP430FR_SD_RW_next.asm" ; SD Read/Write driver .ENDIF .ENDIF ;------------------------------------------------------------------------------- -; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against WIPE) +; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against Deep_RST) ;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv ; -; .include "MY_CODE.asm" +; .include "\ADDON\CORE_ANS.asm" +; .include "\ADDON\UTILITY.asm" +; .include "\ADDON\FIXPOINT.asm" +; .include "YOUR_CODE.asm" ; ;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against WIPE) +; ADD HERE YOUR CODE TO BE INTEGRATED IN KERNEL (protected against Deep_RST) ;------------------------------------------------------------------------------- ;------------------------------------------------------------------------------- diff --git a/forthMSP430FR_ASM.asm b/forthMSP430FR_ASM.asm index aa1cec1..1455080 100644 --- a/forthMSP430FR_ASM.asm +++ b/forthMSP430FR_ASM.asm @@ -1,18 +1,20 @@ ; -*- coding: utf-8 -*- ; ---------------------------------------------------------------------- -;forthMSP430FR_asm.asm +;forthMSP430FR_asm.asm 1584 bytes ; ---------------------------------------------------------------------- ; ---------------------------------------------------------------------- -; MOV(.B) #0, dst is coded as follow : MOV(.B) R3, dst ; 1 cycle, one word As=00 register mode -; MOV(.B) #1, dst is coded as follow : MOV(.B) 0(R3), dst ; 2 cycles, one word AS=01 x(reg) mode -; MOV(.B) #2, dst is coded as follow : MOV(.B) @R3, dst ; 2 cycles, one word AS=10 @reg mode -; MOV(.B) #4, dst is coded as follow : MOV(.B) @R2, dst ; 2 cycles, one word AS=10 @reg mode -; MOV(.B) #8, dst is coded as follow : MOV(.B) @R2+, dst ; 2 cycles, one word AS=11 @reg+ mode -; MOV(.B) #-1,dst is coded as follow : MOV(.B) @R3+, dst ; 2 cycles, one word AS=11 -; MOV(.B) #xxxx,dst is coded a follow : MOV(.B) @PC+, dst ; 2 cycles, two words AS=11 @reg+ mode -; MOV(.B) &EDE,&TON is coded as follow: MOV(.B) EDE(R2),TON(R2) ; (R2=0), three words AS=01, AD=1 x(reg) mode +; MOV(.B) SR,dst is coded as follow : MOV(.B) R2,dst ; 1 cycle, one word AS=00 (register mode) +; MOV(.B) #0,dst is coded as follow : MOV(.B) R3,dst ; 1 cycle, one word AS=00 (register mode) +; MOV(.B) &EDE,dst is coded as follow : MOV(.B) EDE(R2),dst ; 3 cycles, two words AS=01 ( x(reg) mode) +; MOV(.B) #1,dst is coded as follow : MOV(.B) (R3),dst ; 1 cycle, one word AS=01 ( x(reg) mode) +; MOV(.B) #4,dst is coded as follow : MOV(.B) @R2,dst ; 1 cycle, one word AS=10 ( @reg mode) +; MOV(.B) #2,dst is coded as follow : MOV(.B) @R3,dst ; 1 cycle, one word AS=10 ( @reg mode) +; MOV(.B) #8,dst is coded as follow : MOV(.B) @R2+,dst ; 1 cycle, one word AS=11 ( @reg+ mode) +; MOV(.B) #-1,dst is coded as follow : MOV(.B) @R3+,dst ; 1 cycle, one word AS=11 ( @reg+ mode) +; ---------------------------------------------------------------------- +; MOV(.B) #xxxx,dst is coded as follow: MOV(.B) @PC+,dst ; 2 cycles, two words AS=11 ( @reg+ mode) ; ---------------------------------------------------------------------- ; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC @@ -25,138 +27,117 @@ ; example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack - -;;Z SKIP char -- addr ; skip all occurring character 'char' -; FORTHWORD "SKIP" ; used by assembler to parse input stream -SKIP MOV #SOURCE_LEN,Y ;2 - MOV TOS,W ; -- char W=char - MOV @Y+,X ;2 -- char W=char X=buf_length - MOV @Y,TOS ;2 -- Start_buf_adr W=char X=buf_length - ADD TOS,X ; -- Start_buf_adr W=char X=Start_buf_adr+buf_length=End_buf_addr - ADD &TOIN,TOS ; -- Parse_Adr W=char X=End_buf_addr -SKIPLOOP CMP TOS,X ; -- Parse_Adr W=char X=End_buf_addr - JZ SKIPEND ; -- Parse_Adr if end of buffer - CMP.B @TOS+,W ; -- Parse_Adr does character match? - JZ SKIPLOOP ; -- Parse_Adr+1 -SKIPNEXT SUB #1,TOS ; -- addr -SKIPEND MOV TOS,W ; - SUB @Y,W ; -- addr W=Parse_Addr-Start_buf_adr=Toin - MOV W,&TOIN ; - MOV @IP+,PC ; 4 - ; ---------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER : search argument "xxxx", IP is free +; DTCforthMSP430FR5xxx ASSEMBLER : search argument "xxxx" ; ---------------------------------------------------------------------- -SearchARG ; separator -- n|d or abort" not found" -; Search ARG of "#xxxx," ; <== PARAM10 -; Search ARG of "&xxxx," ; <== PARAM111 -; Search ARG of "xxxx(REG)," ; <== ComputeARGpREG <== PARAM130 -; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM20 -; Search ARG of ",xxxx(REG)" ; <== ComputeARGpREG <== PARAM210 - PUSHM #2,S ; PUSHM S,T as OPCODE,OPCODEADR - PUSH TOS ; push sep, for SrchARGPO - PUSH &TOIN ; push TOIN, for SrchARGPO -;-----------------------------------; - ASMtoFORTH ; -- sep sep = ','|'('|' ' - .word WORDD,FIND ; -- addr search word first - .word ZEROEQUAL - .word QFBRAN,ARGWORD ; -- addr if Word found - .word QNUMBER ; - .word QFBRAN,SrchARGPO; -- addr search ARG Plus Offset if not found - .word SrchNext ; -- value goto SrchNext if number found -ARGWORD .word $+2 ; -- CFA - MOV @TOS+,S ; -- PFA S=DOxxx -QDOVAR SUB #1287h,S ; DOxxx = 1287h = CALL R7 = rDOVAR -ISDOVAR JZ SrchNext ; -- addr PFA = adr of VARIABLE -QDOCON ADD #1,S ; DOxxx = 1286h = DOCON - JNZ ISOTHER ; -ISDOCON MOV @TOS,TOS ; - JMP SrchNext ; -- cte -ISOTHER SUB #2,TOS ; -- CFA -SrchNext ADD #4,RSP ; remove TOIN,sep -SearchEnd POPM #2,S ; POPM T,S - MOV @RSP+,PC ; RET -;-----------------------------------; -; search for ARGUMENT16+OFFSET ; up to $FFFF only (FORTH area) -;-----------------------------------; -SrchARGPO .word $+2 - MOV @RSP+,&TOIN ; TOIN back - MOV @RSP+,TOS ; -- sep - ASMtoFORTH ; - .word LIT,'+' ; -- sep '+' search argument - .word WORDD,FIND ; -- sep CFA - .word ZEROEQUAL ; - .word QFBRAN,SrchOffst; - .word QNUMBER ; -- sep number - .word QFBRAN,NotFound ; see INTERPRET -SrchOffst .word SWAP ; -- CFA|number sep - .word WORDD,QNUMBER ; Search 'Offset,'|'Offset('|'Offset' - .word QFBRAN,NotFound ; see INTERPRET - .word $+2 ; -- CFA|number offset - ADD @PSP+,TOS ; -- (CFA|number + offset) - JMP SearchEnd ; +; common code for maxi 3 successive SearchARG: SearchARG, SearchARG+Offset, SearchARG-offset +; leave PFA of VARIABLE, [PFA] of CONSTANT, User_Parameter_Field_Address of MARKER_DOES, CFA for all others. +; if the ARGument is not found after those three SearchARg, the 'not found' error is issued by SrchOfst. +SearchARGn PUSH &TOIN ; push TOIN, for next SearchARGn if any + mASM2FORTH ; -- sep sep = ','|'('|' ' + .word WORDD,FIND ; -- addr search string name first + .word QFBRAN,SrchArgNum ; -- addr if string name not found +COMPUTEARG mNEXTADR ; -- CFA of named definition + MOV @TOS+,S ; -- PFA S=DOxxx +QDOVAR SUB #1287h,S ; CFA = DOxxx = 1287h = CALL R7 = rDOVAR +ISDOVAR JZ ARGFOUND ; -- addr PFA = adr of VARIABLE +QDOCON ADD #1,S ; CFA = DOxxx = 1286h = DOCON + JNZ QMARKER ; +ISDOCON MOV @TOS,TOS ; -- cte + JMP ARGFOUND ; -- cte +QMARKER CMP #MARKER_DOES,0(TOS) ; -- PFA search if PFA = [MARKER_DOES] + JNZ ISOTHER ; -- PFA + .IFDEF VOCABULARY_SET ; -- PFA + ADD #30,TOS ; -- UPFA+2 skip room for DP, CURRENT, CONTEXT(8), null_word, LASTVOC, RET_ADR 2+(2+2+16+2+2+2) +2 bytes + .ELSE ; + ADD #8,TOS ; -- UPFA+2 skip room for DP, RET_ADR 2+(2+2) +2 bytes + .ENDIF ; +ISOTHER SUB #2,TOS ; -- CFA|UPFA UPFA = MARKER_DOES User_Parameter_Field_Address +ARGFOUND ADD #2,RSP ; remove TOIN +SEARCHRET MOV @RSP+,PC ;24 SR(Z)=0 if ARG found + +SrchArgNum .word QNUMBER ; + .word QFBRAN,ARGNOTFOUND; -- addr with SR(Z)=1 + .word ARGFOUND ; -- value no return +ARGNOTFOUND mNEXTADR ; -- x + MOV @RSP+,&TOIN ; restore TOIN + MOV @RSP+,PC ;32 SR(Z)=1 if ARG not found + +SearchIndex +; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM13 +; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM21 + SUB #1,&TOIN ; move >IN back one (unskip 'R') + MOV #'(',TOS ; addr -- "(" as WORD separator to find xxxx of "xxxx(REG)," +SearchARG ; sep -- n|d or abort" not found" +; Search ARG of "#xxxx," ; <== PARAM101 +; Search ARG of "&xxxx," ; <== PARAM111 +; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM201 + MOV TOS,W + PUSHM #4,IP ; -- sep PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,sep + CALL #SearchARGn ; first search argument without offset + JNZ SrchEnd ; -- ARG if ARG found +SearchArgPo MOV #'+',TOS ; -- '+' + CALL #SearchARGn ; 2th search argument with '+' as separator + JNZ ArgPlusOfst ; -- ARG if ARG of ARG+offset found +SearchArgMo MOV #'-',TOS ; -- '-' + CALL #SearchARGn ; 3th search argument with '-' as separator + SUB #1,&TOIN ; to handle offset with its minus sign +ArgPlusOfst PUSH TOS ; -- ARG save ARG on stack + MOV 2(RSP),TOS ; -- sep reload offset sep +SrchOfst mASM2FORTH ; + .word WORDD,QNUMBER ; -- Ofst|c-addr flag + .word QFBRAN,NotFound ; -- c-addr no return, see INTERPRET + mNEXTADR ; -- Ofst + ADD @RSP+,TOS ; -- Arg+Ofst +SrchEnd POPM #4,IP ; POPM W,T,S,IP common return for SearchARG and SearchRn + MOV @RSP+,PC ;66 ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : search REG ; ---------------------------------------------------------------------- - -; compute arg of "xxxx(REG)," ; <== PARAM130, sep=',' -; compute arg of ",xxxx(REG)" ; <== PARAM210, sep=' ' -ComputeARGpREG ; sep -- Rn - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- xxxx aborted if not found - MOV &DDP,X - ADD #2,&DDP - MOV TOS,0(X) ; -- xxxx compile xxxx +; compute index of "xxxx(REG)," ; <== PARAM13, sep=',' +; compute index of ",xxxx(REG)" ; <== PARAM210, sep=' ' +ComputeIDXpREG ; addr -- Rn|addr + CALL #SearchIndex ; -- xxxx aborted if not found + MOV &DP,X + MOV TOS,0(X) ; -- xxxx compile ARG xxxx + ADD #2,&DP MOV #')',TOS ; -- ")" prepare separator to search REG of "xxxx(REG)" - - CMP &SOURCE_LEN,&TOIN ; bad case of ,xxxx (without prefix &) - JNZ SearchREG ; - MOV #BAD_CSP,PC ; génère une erreur bidon - -; search REG of "xxxx(REG)," separator = ')' -; search REG of ",xxxx(REG)" separator = ')' +; search REG of "xxxx(REG)," separator = ')' +; search REG of ",xxxx(REG)" separator = ')' ; search REG of "@REG," separator = ',' <== PARAM120 ; search REG of "@REG+," separator = '+' <== PARAM121 +SkipRSearchRn + ADD #1,&TOIN ; skip "R" in input buffer ; search REG of "REG," separator = ',' <== PARAM13 ; search REG of ",REG" separator = BL <== PARAM21 - -SearchREG PUSHM #2,S ; PUSHM S,T as OPCODE, OPCODEADR - PUSH &TOIN ; -- sep save >IN - ADD #1,&TOIN ; skip "R" - ASMtoFORTH ; search xx of Rxx +SearchRn MOV &TOIN,W ; + PUSHM #4,IP ; PUSHM IP,S,T,W as IP_RET,OPCODE,OPCODEADR,TOIN + mASM2FORTH ; search xx of Rxx .word WORDD,QNUMBER ; - .word QFBRAN,NOTaREG ; -- xxxx if Not a Number - .word $+2 ; -- Rn number is found - ADD #2,RSP ; remove >IN - CMP #16,TOS ; -- Rn - JNC SearchEnd ; -- Rn + .word QFBRAN,REGNOTFOUND; -- xxxx SR(Z)=1 if Not a Number + mNEXTADR ; -- Rn number is found + CMP #16,TOS ; -- Rn + JNC SrchEnd ; -- Rn SR(Z)=0, Rn found, JC BOUNDERROR ; abort if Rn out of bounds -NOTaREG .word $+2 ; -- addr Z=1 - MOV @RSP+,&TOIN ; -- addr restore >IN - JMP SearchEnd ; -- addr Z=1 ==> not a register +REGNOTFOUND mNEXTADR ; -- addr SR(Z)=1, (case of @REG not found), + MOV @RSP,&TOIN ; -- addr restore TOIN, ready for next SearchRn + JMP SrchEnd ; -- addr SR(Z)=1 ==> not a register ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET FIRST OPERAND ; ---------------------------------------------------------------------- - -; PARAM1 separator -- ; parse input buffer until separator and compute first operand of opcode - ; sep is comma for src and space for dst . -PARAM1 mDOCOL ; -- sep OPCODES types I|V sep = ',' OPCODES types II|VI sep = ' ' - .word FBLANK,SKIP ; -- sep addr - .word $+2 ; -- sep addr - MOV #0,S ; -- sep addr reset OPCODE - MOV &DDP,T ; -- sep addr HERE --> OPCODEADR (opcode is preset to its address !) - ADD #2,&DDP ; -- sep addr cell allot for opcode - MOV.B @TOS,W ; -- sep addr W=first char of instruction code - MOV @PSP+,TOS ; -- sep W=c-addr - CMP.B #'#',W ; -- sep W=first char - JNE PARAM11 -; "#" found : case of "#xxxx," -PARAM10 ADD #1,&TOIN ; -- sep skip # prefix - CALL #SearchARG ; -- xxxx abort if not found +; PARAM1 separator -- ; parse input buffer until separator and compute first operand of opcode + ; sep is comma for src and space for dst . +PARAM1 JNZ PARAM10 ; -- sep if prefix <> 'R' + CALL #SearchRn ; case of "REG," + JMP PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0 +; ----------------------------------; +PARAM10 CMP.B #'#',W ; -- sep W=first char + JNE PARAM11 +PARAM101 CALL #SearchARG ; -- xxxx abort if not found MOV #0300h,S ; OPCODE = 0300h : MOV #0,dst is coded MOV R3,dst CMP #0,TOS ; -- xxxx #0 ? JZ PARAMENDOF @@ -169,104 +150,102 @@ PARAM10 ADD #1,&TOIN ; -- sep skip # prefix MOV #0220h,S ; OPCODE = 0220h : MOV #4,dst is coded MOV @R2,dst CMP #4,TOS ; -- xxxx #4 ? JZ PARAMENDOF - MOV #0230h,S ; OPCODE = 0230h : MOV #8,dst is coded MOV @R2+,dst + MOV #0230h,S ; OPCODE = 0230h : MOV #8,dst is coded MOV @R2+,dst CMP #8,TOS ; -- xxxx #8 ? JZ PARAMENDOF - MOV #0330h,S ; -- -1 OPCODE = 0330h : MOV #-1,dst is coded MOV @R3+,dst + MOV #0330h,S ; OPCODE = 0330h : MOV #-1,dst is coded MOV @R3+,dst CMP #-1,TOS ; -- xxxx #-1 ? JZ PARAMENDOF MOV #0030h,S ; -- xxxx for all other cases : MOV @PC+,dst -; case of "&xxxx," ; <== PARAM110 -; case of ",&xxxx" ; <== PARAM20 -StoreArg MOV &DDP,X ; - ADD #2,&DDP ; cell allot for arg -StoreTOS ; <== TYPE1DOES +; endcase of "&xxxx," ; <== PARAM111 +; endcase of ",&xxxx" ; <== PARAM111 <== PARAM201 +StoreArg MOV &DP,X ; + ADD #2,&DP ; cell allot for arg MOV TOS,0(X) ; compile arg +; endcase of all "#xxxx," ; ; endcase of all "&xxxx" ; -; endcase of all "#xxxx" ; <== PARAM101,102,104,108,10M1 -; endcase of all "REG"|"@REG"|"@REG+" <== PARAM124 +; endcase of all "xxxx(REG)"|"@REG"|"@REG+" <== PARAM124 PARAMENDOF MOV @PSP+,TOS ; -- - MOV @RSP+,IP ; MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR ; ----------------------------------; PARAM11 CMP.B #'&',W ; -- sep JNE PARAM12 ; case of "&xxxx," ; -- sep search for "&xxxx," -PARAM110 MOV #0210h,S ; -- sep set code type : xxxx(SR) with AS=0b01 ==> x210h (and SR=0 !) -; case of "&xxxx," -; case of ",&xxxx" ; <== PARAM20 -PARAM111 ADD #1,&TOIN ; -- sep skip "&" prefix - CALL #SearchARG ; -- arg abort if not found +PARAM110 MOV #0210h,S ; -- sep set code type : xxxx(R2) with AS=0b01 ==> x210h +; case of "&xxxx,"|",&xxxx" ; <== PARAM201 +PARAM111 CALL #SearchARG ; -- arg abort if not found JMP StoreArg ; -- then ret ; ----------------------------------; PARAM12 CMP.B #'@',W ; -- sep JNE PARAM13 ; case of "@REG,"|"@REG+," PARAM120 MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10 - ADD #1,&TOIN ; -- sep skip "@" prefix - CALL #SearchREG ; Z = not found - JNZ PARAM123 ; -- value REG of "@REG," found -; case of "@REG+," ; -- addr REG of "@REG" not found, search REG of "@REG+" -PARAM121 ADD #0010h,S ; change OPCODE from @REG to @REG+ type - MOV #'+',TOS ; -- "+" as WORD separator to find REG of "@REG+," - CALL #SearchREG ; -- value|addr X = flag -; case of "@REG+," ; -; case of "xxxx(REG)," ; <== PARAM130 - ; case of double separator: +, and ), -PARAM122 CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma, + CALL #SkipRSearchRn ; Z = not found + JNZ PARAM123 ; -- Rn REG of "@REG," found +; case of "@REG+," ; -- addr search REG of "@REG+" +PARAM121 BIS #0010h,S ; change OPCODE from @REG to @REG+ type + MOV #'+',TOS ; -- sep + CALL #SearchRn ; -- Rn +; case of "@REG+,"|"xxxx(REG)," ; <== PARAM13 +PARAM122 ; case of double separator: +, and ), + CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma, JZ PARAM123 ; i.e. >IN = SOURCE_LEN : don't skip char CR ! ADD #1,&TOIN ; -- 000R skip "," ready for the second operand search -; case of "@REG+," -; case of "xxxx(REG)," +; case of "@REG+,"|"xxxx(REG)," ; ; case of "@REG," ; -- 000R <== PARAM120 -; case of "REG," ; -- 000R <== PARAM13 +; case of "REG," ; -- 000R <== PARAM1 PARAM123 SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.) -; case of "@REG+," ; -- 0R00 (src REG typeI) -; case of "xxxx(REG)," ; -- 0R00 (src REG typeI or dst REG typeII) -; case of "@REG," ; -- 0R00 (src REG typeI) -; case of "REG," ; -- 0R00 (src REG typeI or dst REG typeII) -; case of ",REG" ; -- 000R <== PARAM21 (dst REG typeI) -; case of ",xxxx(REG)" ; -- 000R <== PARAM210 (dst REG typeI) +; case of ",REG" ; -- 000R <== PARAM2 (dst REG typeI) +; case of ",xxxx(REG)" ; -- 000R <== PARAM21 (dst REG typeI) PARAM124 ADD TOS,S ; -- 0R00|000R JMP PARAMENDOF ; ----------------------------------; -; case of "REG,"|"xxxx(REG)," ; first, searg REG of "REG," -PARAM13 CALL #SearchREG ; -- sep save >IN for second parsing (case of "xxxx(REG),") - JNZ PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0 -; case of "xxxx(REG)," ; -- c-addr "REG," not found -PARAM130 ADD #0010h,S ; AS=0b01 for indexing address - CALL #ComputeARGpREG ; compile xxxx and search REG of "(REG)" - JMP PARAM122 ; +; case of "xxxx(REG)," ; -- sep +PARAM13 BIS #0010h,S ; AS=0b01 for indexing address + CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)" + JMP PARAM122 ; -- Rn +; ----------------------------------; ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET 2th OPERAND ; ---------------------------------------------------------------------- - -PARAM3 ; for OPCODES TYPE III - MOV #0,S ; init OPCODE=0 - MOV &DDP,T ; T=OPCODEADR - ADD #2,&DDP ; make room for opcode +PARAM2 JNZ PARAM20 ; -- sep if prefix <> 'R' + CALL #SearchRn ; -- sep case of ",REG" + JMP PARAM124 ; -- 000R REG of ",REG" found ; ----------------------------------; -PARAM2 mDOCOL ; parse input buffer until BL and compute this 2th operand - .word FBLANK,SKIP ; skip space(s) between "arg1," and "arg2" if any; use not S,T. - .word $+2 ; -- c-addr search for '&' of "&xxxx - CMP.B #'&',0(TOS) ; - MOV #20h,TOS ; -- ' ' as WORD separator to find xxxx of ",&xxxx" - JNE PARAM21 ; '&' not found +PARAM20 CMP.B #'&',W ; + JNZ PARAM21 ; '&' not found ; case of ",&xxxx" ; -PARAM20 ADD #0082h,S ; change OPCODE : AD=1, dst = R2 +PARAM201 BIS #0082h,S ; change OPCODE : AD=1, dst = R2 JMP PARAM111 ; -- ' ' ; ----------------------------------; -; case of ",REG"|",xxxx(REG) ; -- ' ' first, search REG of ",REG" -PARAM21 CALL #SearchREG ; - JNZ PARAM124 ; -- 000R REG of ",REG" found -; case of ",xxxx(REG) ; -- addr REG not found -PARAM210 ADD #0080h,S ; set AD=1 - CALL #ComputeARGpREG ; compile argument xxxx and search REG of "(REG)" - JMP PARAM124 ; -- 000R REG of "(REG) found +; case of ",xxxx(REG) ; -- sep +PARAM21 BIS #0080h,S ; set AD=1 + CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)" + JMP PARAM124 ; -- 000R REG of ",xxxx(REG) found + +; ---------------------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER: reset OPCODE in S reg, set OPCODE addr in T reg, +; move Prefix in W reg, skip prefix in input buffer. Flag SR(Z)=1 if prefix = 'R'. +; ---------------------------------------------------------------------------------------- +InitAndSkipPrfx + MOV #0,S ; reset OPCODE + MOV &DP,T ; HERE --> OPCODEADR + ADD #2,&DP ; cell allot for opcode +; SkipPrfx ; -- skip all occurring char 'BL' plus one prefix +SkipPrfx MOV #20h,W ; -- W=BL + MOV &TOIN,X ; -- + ADD &SOURCE_ORG,X ; +SKIPLOOP CMP.B @X+,W ; -- W=BL does character match? + JZ SKIPLOOP ; -- + MOV.B -1(X),W ; W=prefix + SUB &SOURCE_ORG,X ; -- + MOV X,&TOIN ; -- >IN points after prefix + CMP.B #'R',W ; preset SR(Z)=1 if prefix = 'R' + MOV @IP+,PC ; 4 ; ---------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER: OPCODES TYPE 0 : zero operand :-) +; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE 0 : zero operand :-) ; ---------------------------------------------------------------------- asmword "RETI" mDOCOL @@ -275,7 +254,7 @@ PARAM210 ADD #0080h,S ; set AD=1 ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER: OPCODES TYPE I : double operand ; ---------------------------------------------------------------------- -; OPCODE(FEDC) +; OPCODE(FEDC) ; OPCODE(code) = 0bxxxx opcode ; OPCODE(BA98) ; = 0bxxxx src_register, @@ -293,13 +272,18 @@ PARAM210 ADD #0080h,S ; set AD=1 ; OPCODE(3210) ; OPCODE(dst) = 0bxxxx ,dst_register ; ---------------------------------------------------------------------- -TYPE1DOES .word lit,',',PARAM1 ; -- BODYDOES - .word PARAM2 ; -- BODYDOES char separator (BL) included in PARAM2 - .word $+2 ; -MAKEOPCODE MOV T,X ; -- opcode X= OPCODEADR to compile opcode - MOV @TOS,TOS ; -- opcode part of instruction - BIS S,TOS ; -- opcode opcode is complete - JMP StoreTOS ; -- then EXIT + +; TYPE1DOES -- BODYDOES search and compute PARAM1 & PARAM2 as src and dst operands then compile instruction +TYPE1DOES .word lit,',' + .word InitAndSkipPrfx ; init S=0, T=DP, DP=DP+2 then skip prefix, SR(Z)=1 if prefix = 'R' + .word PARAM1 ; -- BODYDOES + .word BL,SkipPrfx ; SR(Z)=1 if prefix = 'R' + .word PARAM2 ; -- BODYDOES + mNEXTADR ; +MAKEOPCODE MOV @RSP+,IP + BIS @TOS,S ; -- opcode generic opcode + customized S + MOV S,0(T) ; -- opcode store completed opcode + JMP PARAMENDOF ; -- then EXIT asmword "MOV" CALL rDODOES @@ -390,8 +374,12 @@ MAKEOPCODE MOV T,X ; -- opcode X= OPCODEADR to comp ; OPCODE(3210) ; OPCODE(dst) = 0bxxxx dst register ; ---------------------------------------------------------------------- -TYPE2DOES .word FBLANK,PARAM1 ; -- BODYDOES - .word $+2 ; + +TYPE2DOES ; -- BODYDOES + .word BL ; -- BODYDOES ' ' + .word InitAndSkipPrfx ; + .word PARAM1 ; -- BODYDOES + mNEXTADR ; MOV S,W ; AND #0070h,S ; keep B/W & AS infos in OPCODE SWPB W ; (REG org --> REG dst) @@ -430,7 +418,7 @@ BIS_ASMTYPE BIS W,S ; -- BODYDOES add it in OPCODE BOUNDERRWM1 ADD #1,W ; <== RRAM|RRUM|RRCM|RLAM error BOUNDERRORW MOV W,TOS ; <== PUSHM|POPM|ASM_branch error BOUNDERROR ; <== REG number error - mDOCOL ; -- n n = value out of bounds + mASM2FORTH ; -- n n = value out of bounds .word DOT,XSQUOTE .byte 13,"out of bounds" .word ABORT_TERM @@ -438,7 +426,7 @@ BOUNDERROR ; <== REG number error ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, CONDITIONAL BRANCHS ; ---------------------------------------------------------------------- -; ASSEMBLER FORTH OPCODE(FEDC) +; ASSEMBLER FORTH OPCODE(FEDC) ; OPCODE(code) for TYPE JNE,JNZ 0<>, <> = 0x20xx + (offset AND 3FF) ; branch if Z = 0 ; OPCODE(code) for TYPE JEQ,JZ 0=, = = 0x24xx + (offset AND 3FF) ; branch if Z = 1 ; OPCODE(code) for TYPE JNC,JLO U< = 0x28xx + (offset AND 3FF) ; branch if C = 0 @@ -482,15 +470,15 @@ BOUNDERROR ; <== REG number error ;ASM IF OPCODE -- @OPCODE1 asmword "IF" -ASM_IF MOV &DDP,W +ASM_IF MOV &DP,W MOV TOS,0(W) ; compile incomplete opcode - ADD #2,&DDP + ADD #2,&DP MOV W,TOS MOV @IP+,PC ;ASM THEN @OPCODE -- resolve forward branch asmword "THEN" -ASM_THEN MOV &DDP,W ; -- @OPCODE W=dst +ASM_THEN MOV &DP,W ; -- @OPCODE W=dst MOV TOS,Y ; Y=@OPCODE ASM_THEN1 MOV @PSP+,TOS ; -- MOV Y,X ; @@ -504,23 +492,23 @@ ASM_THEN1 MOV @PSP+,TOS ; -- ; ELSE @OPCODE1 -- @OPCODE2 branch for IF..ELSE asmword "ELSE" -ASM_ELSE MOV &DDP,W ; -- W=HERE +ASM_ELSE MOV &DP,W ; -- W=HERE MOV #3C00h,0(W) ; compile unconditionnal branch - ADD #2,&DDP ; -- DP+2 + ADD #2,&DP ; -- DP+2 SUB #2,PSP MOV W,0(PSP) ; -- @OPCODE2 @OPCODE1 JMP ASM_THEN ; -- @OPCODE2 ; BEGIN -- BEGINadr initialize backward branch asmword "BEGIN" - MOV #HERE,PC + MOV #HEREXEC,PC ; UNTIL @BEGIN OPCODE -- resolve conditional backward branch asmword "UNTIL" ASM_UNTIL MOV @PSP+,W ; -- OPCODE W=@BEGIN ASM_UNTIL1 MOV TOS,Y ; Y=OPCODE W=@BEGIN ASM_UNTIL2 MOV @PSP+,TOS ; -- - MOV &DDP,X ; -- Y=OPCODE X=HERE W=dst + MOV &DP,X ; -- Y=OPCODE X=HERE W=dst SUB #2,W ; -- Y=OPCODE X=HERE W=dst-2 SUB X,W ; -- Y=OPCODE X=src W=src-dst-2=displacement (bytes) RRA W ; -- Y=OPCODE X=HERE W=displacement (words) @@ -529,10 +517,10 @@ ASM_UNTIL2 MOV @PSP+,TOS ; -- AND #3FFh,W ; -- Y=OPCODE X=HERE W=troncated negative displacement (words) BIS W,Y ; -- Y=OPCODE (completed) MOV Y,0(X) - ADD #2,&DDP + ADD #2,&DP MOV @IP+,PC -; AGAIN @BEGIN -- uncond'l backward branch +; AGAIN @BEGIN -- uncond'l backward branch ; unconditional backward branch asmword "AGAIN" ASM_AGAIN MOV TOS,W ; W=@BEGIN @@ -560,12 +548,12 @@ ASM_REPEAT mDOCOL ; -- @WHILE @BEGIN ;BACKWDOES FORTHtoASM ; MOV @RSP+,IP ; MOV @TOS,TOS -; MOV TOS,Y ; Y = ASMBWx -; MOV @PSP+,TOS ; -; MOV @Y,W ; W = [ASMBWx] +; MOV @TOS,Y ; Y = ASMBWx +; MOV @PSP+,TOS ; +; MOV @Y,W ; W = [BWx] ; CMP #8,&TOIN ; are we colon 8 or more ? -;BACKWUSE JHS ASM_UNTIL1 ; yes, use this label -;BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP +;BACKWUSE JHS ASM_UNTIL1 ; yes, use this label +;BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP ; mNEXT ;; backward label 1 @@ -574,21 +562,21 @@ ASM_REPEAT mDOCOL ; -- @WHILE @BEGIN ; .word BACKWDOES ; .word ASMBW1 ; in RAM -BACKWDOES .word $+2 +BACKWDOES mNEXTADR MOV @RSP+,IP ; - MOV TOS,Y ; -- PFA Y = ASMBWx addr + MOV TOS,Y ; -- BODY Y = BWx addr MOV @PSP+,TOS ; -- MOV @Y,W ; W = LABEL CMP #8,&TOIN ; are we colon 8 or more ? -BACKWUSE JC ASM_UNTIL1 ; yes, use this label -BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP +BACKWUSE JC ASM_UNTIL1 ; yes, use this label +BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP MOV @IP+,PC ; backward label 1 asmword "BW1" - CALL rDODOES - .word BACKWDOES - .word 0 + CALL rDODOES ; CFA + .word BACKWDOES ; PFA + .word 0 ; BODY ; backward label 2 asmword "BW2" CALL rDODOES @@ -600,15 +588,16 @@ BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP .word BACKWDOES .word 0 -;FORWDOES .word $+2 +;FORWDOES mNEXTADR ; MOV @RSP+,IP -; MOV &DDP,W ; +; MOV &DP,W ; ; MOV @TOS,TOS -; MOV @TOS,Y ; -- PFA Y= ASMFWx +; MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx +; MOV #0,0(TOS) ; V3.9: clear @OPCODE of FWx to erratic 2th resolution ; CMP #8,&TOIN ; are we colon 8 or more ? -;FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DDP, Y=ASMFWx +;FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE ;FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode -; ADD #2,&DDP ; increment DDP +; ADD #2,&DP ; increment DP ; MOV W,0(TOS) ; store @OPCODE into ASMFWx ; MOV @PSP+,TOS ; -- ; MOV @IP+,PC @@ -616,26 +605,27 @@ BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP ;; forward label 1 ; asmword "FW1" ; CALL rDODOES ; CFA -; .word FORWDOES ; -; .word ASMFW1 ; in RAM +; .word FORWDOES ; +; .word ASMFW1 ; in RAM -FORWDOES .word $+2 +FORWDOES mNEXTADR MOV @RSP+,IP - MOV &DDP,W ; - MOV @TOS,Y ; -- PFA Y=[BODY]=ASMFWx + MOV &DP,W ; + MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx + MOV #0,0(TOS) ; V3.9: clear @OPCODE of FWx to avoid jmp resolution without label CMP #8,&TOIN ; are we colon 8 or more ? -FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DDP, Y=ASMFWx -FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode - ADD #2,&DDP ; increment DDP - MOV W,0(TOS) ; store @OPCODE into ASMFWx - MOV @PSP+,TOS ; -- +FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE +FORWSET MOV @PSP+,0(W) ; yes compile opcode (without displacement) + ADD #2,&DP ; increment DP + MOV W,0(TOS) ; store @OPCODE into BODY of FWx + MOV @PSP+,TOS ; -- MOV @IP+,PC ; forward label 1 asmword "FW1" CALL rDODOES ; CFA - .word FORWDOES ; - .word 0 ; BODY + .word FORWDOES ; PFA + .word 0 ; BODY ; forward label 2 asmword "FW2" CALL rDODOES @@ -669,8 +659,8 @@ INVJMP CMP #3000h,TOS ; invert code jump process ; -------------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES TYPE III : PUSHM|POPM|RLAM|RRAM|RRUM|RRCM ; -------------------------------------------------------------------------------- -; PUSHM, syntax: PUSHM #n,REG with 0 < n < 17 -; POPM syntax: POPM #n,REG with 0 < n < 17 +; PUSHM, syntax: PUSHM #n,REG with 0 < n < 17 +; POPM syntax: POPM #n,REG with 0 < n < 17 ; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC @@ -683,17 +673,17 @@ INVJMP CMP #3000h,TOS ; invert code jump process ; example : POPM #6,IP pulls Y,X,W,T,S,IP registers from return stack -; RxxM syntax: RxxM #n,REG with 0 < n < 5 +; RxxM syntax: RxxM #n,REG with 0 < n < 5 -TYPE3DOES .word FBLANK,SKIP ; skip spaces if any - .word $+2 ; -- BODYDOES c-addr - ADD #1,&TOIN ; skip "#" - MOV #',',TOS ; -- BODYDOES "," - ASMtoFORTH - .word WORDD,QNUMBER +TYPE3DOES ; -- BODYDOES + .word SkipPrfx ; + .word LIT,',' ; -- BODYDOES ',' + .word WORDD,QNUMBER ; .word QFBRAN,NotFound ; see INTERPRET - .word PARAM3 ; -- BODYDOES 0x000N S=OPCODE = 0x000R - .word $+2 + .word BL ; -- BODYDOES n ' ' + .word InitAndSkipPrfx ; -- BODYDOES n ' ' + .word PARAM2 ; -- BODYDOES n S=OPCODE = 0x000R + mNEXTADR MOV TOS,W ; -- BODYDOES n W = n MOV @PSP+,TOS ; -- BODYDOES SUB #1,W ; W = n floored to 0 @@ -702,17 +692,17 @@ TYPE3DOES .word FBLANK,SKIP ; skip spaces if any RLAM #4,X ; OPCODE bit 1000h --> C JNC RxxMINSTRU ; if bit 1000h = 0 PxxxINSTRU MOV S,Y ; S=REG, Y=REG to test - RLAM #3,X ; OPCODE bit 0200h --> C + RLAM #3,X ; OPCODE bit 0200h --> C JNC PUSHMINSTRU ; W=n-1 Y=REG POPMINSTRU SUB W,S ; to make POPM opcode, compute first REG to POP; TI is complicated.... PUSHMINSTRU SUB W,Y ; Y=REG-(n-1) CMP #16,Y JC BOUNDERRWM1 ; JC=JHS (U>=) - RLAM #4,W ; W = n << 4 - JMP BIS_ASMTYPE ; BODYDOES -- + RLAM #4,W ; W = n << 4 + JMP BIS_ASMTYPE ; BODYDOES -- RxxMINSTRU CMP #4,W ; JC BOUNDERRWM1 ; JC=JHS (U>=) - SWPB W ; -- BODYDOES W = n << 8 + SWPB W ; W = n << 8 RLAM #2,W ; W = N << 10 JMP BIS_ASMTYPE ; BODYDOES -- @@ -735,6 +725,7 @@ RxxMINSTRU CMP #4,W ; CALL rDODOES .word TYPE3DOES,1700h + .IFDEF EXTENDED_MEM asmword "RRCM.A" CALL rDODOES @@ -759,163 +750,132 @@ RxxMINSTRU CMP #4,W ; ; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE III bis: CALLA (without extended word) ; -------------------------------------------------------------------------------- ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers with dot) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers with dot) -; -------------------------------------------------------------------------------- -; may be usefull to access ROM libraries beyond $FFFF +; indexed instructions must be written as $xxxx(REG) ; -------------------------------------------------------------------------------- asmword "CALLA" mDOCOL - .word FBLANK,SKIP ; -- addr - .word $+2 - MOV &DDP,T ; T = DDP - ADD #2,&DDP ; make room for opcode - MOV.B @TOS,TOS ; -- char First char of opcode + .word BL ; -- sep + .word InitAndSkipPrfx ; -- sep SR(Z)=1 if prefix = 'R' + mNEXTADR + MOV @RSP+,IP CALLA0 MOV #134h,S ; 134h<<4 = 1340h = opcode for CALLA Rn - CMP.B #'R',TOS - JNZ CALLA1 -CALLA01 MOV.B #' ',TOS ; -CALLA02 CALL #SearchREG ; -- Rn -CALLA03 RLAM #4,S ; (opcode>>4)<<4 = opcode - BIS TOS,S ; update opcode + JNZ CALLA1 ; -- sep if prefix <> 'R' +CALLA01 CALL #SearchRn ; -- Rn +CALLA02 RLAM #4,S ; (opcode>>4)<<4 = opcode + BIS TOS,S ; update opcode with Rn|$x MOV S,0(T) ; store opcode - MOV @PSP+,TOS - MOV @RSP+,IP - MOV @IP+,PC + MOV @PSP+,TOS ; -- + MOV @IP+,PC ; ;-----------------------------------; -CALLA1 ADD #2,S ; 136h<<4 = opcode for CALLA @REG - CMP.B #'@',TOS ; -- char Search @REG +CALLA1 ADD #2,S ; -- sep 136h<<4 = opcode for CALLA @REG + CMP.B #'@',W ; Search @REG JNZ CALLA2 ; - ADD #1,&TOIN ; skip '@' - MOV.B #' ',TOS ; -- ' ' - CALL #SearchREG ; - JNZ CALLA03 ; if REG found, update opcode +CALLA11 CALL #SkipRSearchRn ; + JNZ CALLA02 ; if REG found, update opcode ;-----------------------------------; ADD #1,S ; 137h<<4 = opcode for CALLA @REG+ - MOV #'+',TOS ; -- '+' - JMP CALLA02 ; + MOV #'+',TOS ; -- sep + JMP CALLA01 ; ;-----------------------------------; -CALLA2 ADD #2,&DDP ; make room for xxxx of #$x.xxxx|&$x.xxxx|$0.xxxx(REG) - CMP.B #'#',TOS ; +CALLA2 ADD #2,&DP ; -- sep make room for xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG) + CMP.B #'#',W ; JNZ CALLA3 MOV #13Bh,S ; 13Bh<<4 = opcode for CALLA #$x.xxxx -CALLA21 ADD #1,&TOIN ; skip '#'|'&' -CALLA22 CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store #$xxxx|&$xxxx - JMP CALLA03 ; update opcode with $x. and store opcode +CALLA21 CALL #SearchARG ; -- Lo Hi + MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx + JMP CALLA02 ; update opcode with $x. and store opcode ;-----------------------------------; -CALLA3 CMP.B #'&',TOS +CALLA3 CMP.B #'&',W ; -- sep JNZ CALLA4 ; ADD #2,S ; 138h<<4 = opcode for CALLA &$x.xxxx JMP CALLA21 ;-----------------------------------; -CALLA4 MOV.B #'(',TOS ; -- "(" - SUB #1,S ; 135h<<4 = opcode for CALLA $0.xxxx(REG) -CALLA41 CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx - MOV #')',TOS ; -- ')' - JMP CALLA02 ; search Rn and update opcode - +CALLA4 SUB #1,S ; 135h<<4 = opcode for CALLA $xxxx(REG) +CALLA41 CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n store $xxxx of $xxxx(REG) + MOV #')',TOS ; -- sep + JMP CALLA11 ; search Rn and update opcode + ; =============================================================== ; to allow data access beyond $FFFF ; =============================================================== -; MOVA (#$x.xxxx|&$x.xxxx|$.xxxx(Rs)|Rs|@Rs|@Rs+ , &|Rd|$.xxxx(Rd)) -; ADDA (#$x.xxxx|Rs , Rd) -; CMPA (#$x.xxxx|Rs , Rd) -; SUBA (#$x.xxxx|Rs , Rd) +; MOVA #$x.xxxx|&$x.xxxx|$xxxx(Rs)|Rs|@Rs|@Rs+ , &$x.xxxx|$xxxx(Rd)|Rd +; ADDA (#$x.xxxx|Rs , Rd) +; CMPA (#$x.xxxx|Rs , Rd) +; SUBA (#$x.xxxx|Rs , Rd) ; first argument process ACMS1 ;-----------------------------------; -ACMS1 mDOCOL ; -- BODYDOES ',' - .word FBLANK,SKIP ; -- BODYDOES ',' addr - .word $+2 ; - MOV.B @TOS,X ; X=first char of opcode string - MOV @PSP+,TOS ; -- BODYDOES ',' - MOV @PSP+,S ; -- ',' S=BODYDOES - MOV @S,S ; S=opcode - MOV &DDP,T ; T=DDP - ADD #2,&DDP ; make room for opcode +ACMS1 MOV @PSP+,S ; -- sep S=BODYDOES + MOV @S,S ; S=opcode ;-----------------------------------; -ACMS10 CMP.B #'R',X ; -- ',' - JNZ ACMS11 ; -ACMS101 CALL #SearchREG ; -- Rn src +ACMS10 JNZ ACMS11 ; -- sep if prefix <> 'R' +ACMS101 CALL #SearchRn ; -- Rn ACMS102 RLAM #4,TOS ; 8<<src RLAM #4,TOS ; ACMS103 BIS S,TOS ; update opcode with src|dst MOV TOS,0(T) ; save opcode MOV T,TOS ; -- OPCODE_addr - MOV @RSP+,IP ; MOV @IP+,PC ; ;-----------------------------------; -ACMS11 CMP.B #'#',X ; -- ',' X=addr +ACMS11 CMP.B #'#',W ; -- sep X=addr JNE MOVA12 ; BIC #40h,S ; set #opcode -ACMS111 ADD #1,&TOIN ; skip '#'|'&' - ADD #2,&DDP ; make room for low #$xxxx|&$xxxx|$xxxx(REG) +ACMS111 ADD #2,&DP ; make room for low #$xxxx|&$xxxx|$xxxx(REG) CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx|$x.xxxx(REG) + MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG) AND #0Fh,TOS ; -- Hi sel Hi src JMP ACMS102 ; ;-----------------------------------; -MOVA12 CMP.B #'&',X ; -- ',' case of MOVA &$x.xxxx +MOVA12 CMP.B #'&',W ; -- sep case of MOVA &$x.xxxx JNZ MOVA13 ; - XOR #00E0h,S ; set MOVA &$x.xxxx, opcode + XOR #00E0h,S ; set MOVA &$x.xxxx, opcode JMP ACMS111 ; ;-----------------------------------; MOVA13 BIC #00F0h,S ; set MOVA @REG, opcode - CMP.B #'@',X ; -- ',' + CMP.B #'@',W ; -- sep JNZ MOVA14 ; - ADD #1,&TOIN ; skip '@' - CALL #SearchREG ; -- Rn + CALL #SkipRSearchRn ; -- Rn JNZ ACMS102 ; if @REG found -;-----------------------------------; BIS #0010h,S ; set @REG+ opcode MOV #'+',TOS ; -- '+' -MOVA131 CALL #SearchREG ; -- Rn case of MOVA @REG+,|MOVA $x.xxxx(REG), - CMP &SOURCE_LEN,&TOIN ; test TYPE II first parameter ending by @REG+ (REG) without comma, - JZ ACMS102 ; i.e. may be >IN = SOURCE_LEN: don't skip char CR ! - ADD #1,&TOIN ; skip "," ready for the second operand search +MOVA131 CALL #SearchRn ; -- Rn case of MOVA @REG+,|MOVA $x.xxxx(REG), +MOVA132 ADD #1,&TOIN ; skip "," ready for the second operand search JMP ACMS102 ; ;-----------------------------------; -MOVA14 BIS #0030h,S ; set xxxx(REG), opcode - ADD #2,&DDP ; -- ',' make room for first $xxxx of $0.xxxx(REG), - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx as 2th word +MOVA14 BIS #0030h,S ; -- sep set xxxx(REG), opcode + ADD #2,&DP ; make room for first $xxxx of $xxxx(REG), + CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n store $xxxx as 2th word MOV #')',TOS ; -- ')' - JMP MOVA131 ; + CALL #SkipRSearchRn ; -- Rn + JMP MOVA132 ; ; 2th argument process ACMS2 -;-----------------------------------; -ACMS2 mDOCOL ; -- OPCODE_addr - .word FBLANK,SKIP ; -- OPCODE_addr addr - .word $+2 ; - MOV @PSP+,T ; -- addr T=OPCODE_addr +;-----------------------------------; -- OPCODE_addr sep +ACMS2 MOV @PSP+,T ; -- sep T=OPCODE_addr MOV @T,S ; S=opcode - MOV.B @TOS,X ; -- addr X=first char of string instruction - MOV.B #' ',TOS ; -- ' ' ;-----------------------------------; -ACMS21 CMP.B #'R',X ; -- ' ' - JNZ MOVA22 ; -ACMS211 CALL #SearchREG ; -- Rn +ACMS21 JNZ MOVA22 ; -- sep if prefix <> 'R' +ACMS211 CALL #SearchRn ; -- Rn JMP ACMS103 ; ;-----------------------------------; -MOVA22 BIC #0F0h,S ; - ADD #2,&DDP ; -- ' ' make room for $xxxx - CMP.B #'&',X ; +MOVA22 BIC #0F0h,S ; -- sep + ADD #2,&DP ; make room for $xxxx + CMP.B #'&',W ; JNZ MOVA23 ; BIS #060h,S ; set ,&$x.xxxx opcode - ADD #1,&TOIN ; skip '&' CALL #SearchARG ; -- Lo Hi MOV @PSP+,2(T) ; -- Hi store $xxxx as 2th word JMP ACMS103 ; update opcode with dst $x and write opcode ;-----------------------------------; MOVA23 BIS #070h,S ; set ,xxxx(REG) opcode - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi write $xxxx of ,$0.xxxx(REG) as 2th word + CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n write $xxxx of ,$xxxx(REG) as 2th word MOV #')',TOS ; -- ")" as WORD separator to find REG of "xxxx(REG)," - JMP ACMS211 + CALL #SkipRSearchRn ; -- Rn + JMP ACMS103 ; -------------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV 2 operands: Adda|Cmpa|Mova|Suba (without extended word) @@ -924,9 +884,11 @@ MOVA23 BIS #070h,S ; set ,xxxx(REG) opcode ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) ; -------------------------------------------------------------------------------- TYPE4DOES .word lit,',' ; -- BODYDOES "," char separator for PARAM1 + .word InitAndSkipPRFX ; SR(Z)=1 if prefix = 'R' .word ACMS1 ; -- OPCODE_addr + .word BL,SkipPRFX ; SR(Z)=1 if prefix = 'R' .word ACMS2 ; -- OPCODE_addr - .word DROP,EXIT + .word DROPEXIT asmword "MOVA" CALL rDODOES diff --git a/forthMSP430FR_CONDCOMP.asm b/forthMSP430FR_CONDCOMP.asm deleted file mode 100644 index e7cb74d..0000000 --- a/forthMSP430FR_CONDCOMP.asm +++ /dev/null @@ -1,271 +0,0 @@ -; -*- coding: utf-8 -*- -; - FORTHWORDIMM "[THEN]" ; do nothing -; https://forth-standard.org/standard/tools/BracketTHEN -; [THEN] - MOV @IP+,PC - -; ; https://forth-standard.org/standard/string/COMPARE -; ; COMPARE ( c-addr1 u1 c-addr2 u2 -- n ) -; ;Compare the string specified by c-addr1 u1 to the string specified by c-addr2 u2. -; ;The strings are compared, beginning at the given addresses, character by character, -; ;up to the length of the shorter string or until a difference is found. -; ;If the two strings are identical, n is zero. -; ;If the two strings are identical up to the length of the shorter string, -; ; n is minus-one (-1) if u1 is less than u2 and one (1) otherwise. -; ;If the two strings are not identical up to the length of the shorter string, -; ; n is minus-one (-1) if the first non-matching character in the string specified by c-addr1 u1 -; ; has a lesser numeric value than the corresponding character in the string specified by c-addr2 u2 and one (1) otherwise. -; FORTHWORD "COMPARE" -; COMPARE -; MOV TOS,S ;1 S = u2 -; MOV @PSP+,Y ;2 Y = addr2 -; MOV @PSP+,T ;2 T = u1 -; MOV @PSP+,X ;2 X = addr1 -; COMPLOOP MOV T,TOS ;1 -; ADD S,TOS ;1 TOS = u1+u2 -; JZ COMPEQUAL ;2 u1=u2=0, Z=1, end of all successfull comparisons -; SUB #1,T ;1 -; JN COMPLESS ;2 u1<u2 if u1 < 0 -; SUB #1,S ;1 -; JN COMPGREATER ;2 u1>u2 if u2 < 0 -; ADD #1,X ;1 -; CMP.B @Y+,-1(X) ;4 char1-char2 -; JZ COMPLOOP ;2 char1=char2 17~ loop -; JC COMPGREATER ;2 char1>char2 -; COMPLESS ; char1<char2 -; MOV #-1,TOS ;1 Z=0 -; MOV @IP+,PC ;4 -; COMPGREATER -; MOV #1,TOS ;1 Z=0 -; COMPEQUAL -; MOV @IP+,PC ;4 20 + 5 words def'n - -; ; https://forth-standard.org/standard/tools/BracketELSE -; ; [ELSE] a few (smaller and faster) definition -; ;Compilation: -; ;Perform the execution semantics given below. -; ;Execution: -; ;( "<spaces>name ..." -- ) -; ;Skipping leading spaces, parse and discard space-delimited words from the parse area, -; ;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN], -; ;until the word [THEN] has been parsed and discarded. -; ;If the parse area becomes exhausted, it is refilled as with REFILL. -; FORTHWORDIMM "[ELSE]" ; or [IF] if isnogood... -; BRACKETELSE -; mDOCOL -; .word lit,0 ; -- cnt=0 -; BRACKETELSE0 -; .word ONEPLUS ; -- cnt+1 -; BRACKETELSE1 ; -; .word FBLANK,WORDD,COUNT ; -- cnt addr u -; .word DUP,QFBRAN,BRACKETELSE5 ; u = 0 if end of line --> refill buffer then loop back -; .word TWODUP ; -; .word XSQUOTE ; -; .byte 6,"[THEN]" ; -; .word COMPARE,ZEROEQUAL ; -; .word QFBRAN,BRACKETELSE2 ; -- cnt addr u if bad comparaison, jump for next comparaison -; .word TWODROP,ONEMINUS ; -- cnt-1 2DROP, decrement count -; .word QDUP,ZEROEQUAL ; -; .word QFBRAN,BRACKETELSE1 ; -- cnt-1 loop back if count <> 0 -; .word EXIT ; -- else exit -; BRACKETELSE2 ; -; .word TWODUP ; -- cnt addr u addr u -; .word XSQUOTE ; -; .byte 6,"[ELSE]" ; -; .word COMPARE,ZEROEQUAL ; -- cnt addr u ff -; .word QFBRAN,BRACKETELSE3 ; -- cnt addr u if bad comparaison, jump for next comparaison -; .word TWODROP,ONEMINUS ; -- cnt-1 2DROP, decrement count -; .word QDUP,ZEROEQUAL ; -; .word QFBRAN,BRACKETELSE0 ; -- cnt-1 if count <> 0 restore old count with loop back increment -; .word EXIT ; -- else exit -; BRACKETELSE3 ; -; .word XSQUOTE ; -; .byte 4,"[IF]" ; -; .word COMPARE,ZEROEQUAL ; -; .word QFBRAN,BRACKETELSE1 ; -- cnt if bad comparaison, loop back -; .word BRAN,BRACKETELSE0 ; -- cnt else increment loop back -; BRACKETELSE5 ; -; .word TWODROP ; -- cnt -; ;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; -; ; OPTION ; plus 5 words option -; ;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv; -; .word XSQUOTE ; -; .byte 5,13,10,"ko " ; -; .word TYPE ; CR+LF ." ko" to show false branch of conditionnal compilation -; ;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; -; .word REFILL ; REFILL Input Buffer with next line -; .word SETIB ; SET Input Buffer pointers SOURCE_LEN, SOURCE_ORG and clear >IN -; .word BRAN,BRACKETELSE1 ; -- cnt then loop back 54 words without options - -; BRanch if string BAD COMParaison, [COMPARE,ZEROEQUAL,QFBRAN] replacement -BRBADCOMP ; -- cnt addr1 u1 addr1 u1 addr2 u2 - MOV TOS,S ;1 S = u2 - MOV @PSP+,Y ;2 Y = addr2 - MOV @PSP+,T ;2 T = u1 - MOV @PSP+,X ;2 X = addr1 -COMPLOOP MOV T,TOS ;1 -- cnt addr1 u1 u1 - ADD S,TOS ;1 -- cnt addr1 u1 u1+u2 - JZ COMPEQU ;2 u1=u2=0, Z=1, end of all successfull comparisons - SUB #1,T ;1 - JN COMPDIF ;2 u1<u2 if u1 < 0 - SUB #1,S ;1 - JN COMPDIF ;2 u1>u2 if u2 < 0 - ADD #1,X ;1 - CMP.B @Y+,-1(X) ;4 char1-char2 - JZ COMPLOOP ;2 char1=char2 17~ loop -COMPDIF MOV @IP,IP ;1 take branch -CMPEND MOV @PSP+,TOS ; - MOV @IP+,PC ;4 - -; BRanch if string GOOD COMParaison, [TWODROP,ONEMINUS,?DUP,ZEROEQUAL,QFBRAN] replacement -BRGOODCMP ; -- cnt addr u - ADD #2,PSP ;1 -- cnt u - SUB #1,0(PSP) ;3 -- cnt-1 u - JNZ COMPDIF ;2 -- cnt-1 u take branch - ADD #2,PSP ;1 -- u -COMPEQU ADD #2,IP ; skip branch - JMP CMPEND ; 25 words - - FORTHWORDIMM "[ELSE]" ; or [IF] if isnogood... -; https://forth-standard.org/standard/tools/BracketELSE -; [ELSE] a few (smaller and faster) definition -;Compilation: -;Perform the execution semantics given below. -;Execution: -;( "<spaces>name ..." -- ) -;Skipping leading spaces, parse and discard space-delimited words from the parse area, -;including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN], -;until the word [THEN] has been parsed and discarded. -;If the parse area becomes exhausted, it is refilled as with REFILL. -BRACKETELSE - mDOCOL - .word lit,0 -BRACKETELSE0 - .word ONEPLUS ; -BRACKETELSE1 ; - .word FBLANK,WORDD,COUNT ; -- addr u - .word DUP,QFBRAN,BRACKETELSE5 ; u = 0 if end of line --> refill buffer then loop back - .word TWODUP ; - .word XSQUOTE ; - .byte 6,"[THEN]" ; - .word BRBADCOMP,BRACKETELSE2 ; if bad string comparaison, jump for next comparaison - .word BRGOODCMP,BRACKETELSE1 ; 2DROP, count-1, loop back if count <> 0, else DROP - .word EXIT ; then exit -BRACKETELSE2 ; - .word TWODUP ; - .word XSQUOTE ; - .byte 6,"[ELSE]" ; - .word BRBADCOMP,BRACKETELSE3 ; if bad string comparaison, jump for next comparaison - .word BRGOODCMP,BRACKETELSE0 ; 2DROP, count-1, loop back with count+1 if count <> 0, else DROP - .word EXIT ; then exit -BRACKETELSE3 ; - .word XSQUOTE ; - .byte 4,"[IF]" ; - .word BRBADCOMP,BRACKETELSE1 ; if bad string comparaison, loop back - .word BRAN,BRACKETELSE0 ; else loop back with count+1 -BRACKETELSE5 ; - .word TWODROP ; -;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; -; OPTION ; +5 words option -;vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv; - .word XSQUOTE ; - .byte 5,13,10,"ko " ; - .word TYPE ; CR+LF ." ko " to show false branch of conditionnal compilation -;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; -BRKTELSEND .word REFILL ; REFILL Input Buffer with next line - .word SETIB ; SET Input Buffer pointers SOURCE_LEN, SOURCE_ORG and clear >IN - .word BRAN,BRACKETELSE1 ; then loop back 44 words without options - - FORTHWORDIMM "[IF]" ; flag -- -; https://forth-standard.org/standard/tools/BracketIF -; [IF] -;Compilation: -;Perform the execution semantics given below. -;Execution: ;( flag | flag "<spaces>name ..." -- ) -;If flag is true, do nothing. Otherwise, skipping leading spaces, -; parse and discard space-delimited words from the parse area, -; including nested occurrences of [IF] ... [THEN] and [IF] ... [ELSE] ... [THEN], -; until either the word [ELSE] or the word [THEN] has been parsed and discarded. -;If the parse area becomes exhausted, it is refilled as with REFILL. [IF] is an immediate word. -;An ambiguous condition exists if [IF] is POSTPONEd, -; or if the end of the input buffer is reached and cannot be refilled before the terminating [ELSE] or [THEN] is parsed. -BRACKETIF CMP #0,TOS ; -- f - MOV @PSP+,TOS ; -- - JZ BRACKETELSE ; false flag output - MOV @IP+,PC ; true flag output - - .IFNDEF NIP -; https://forth-standard.org/standard/core/NIP -; NIP x1 x2 -- x2 Drop the first item below the top of stack -NIP ADD #2,PSP ; 1 - MOV @IP+,PC ; 4 - .ENDIF - - - FORTHWORDIMM "[DEFINED]" -; https://forth-standard.org/standard/tools/BracketDEFINED -; [DEFINED] -;Compilation: -;Perform the execution semantics given below. -;Execution: -;( "<spaces>name ..." -- flag ) -;Skip leading space delimiters. Parse name delimited by a space. -;Return a true flag if name is the name of a word that can be found, -;otherwise return a false flag. [DEFINED] is an immediate word. -DEFINED mDOCOL - .word FBLANK,WORDD,FIND,NIP,EXIT - - FORTHWORDIMM "[UNDEFINED]" -; https://forth-standard.org/standard/tools/BracketUNDEFINED -; [UNDEFINED] -;Compilation: -;Perform the execution semantics given below. -;Execution: ( "<spaces>name ..." -- flag ) -;Skip leading space delimiters. Parse name delimited by a space. -;Return a false flag if name is the name of a word that can be found, -;otherwise return a true flag. - mDOCOL - .word DEFINED,ZEROEQUAL,EXIT - - -; https://forth-standard.org/standard/core/MARKER -; MARKER -;name Execution: ( -- ) -;Restore all dictionary allocation and search order pointers to the state they had just prior to the -;definition of name. Remove the definition of name and all subsequent definitions. Restoration -;of any structures still existing that could refer to deleted definitions or deallocated data space is -;not necessarily provided. No other contextual information such as numeric base is affected. - - -; FastForth provides all that is necessary for a real time application next MARKER definition, -; by adding a call to a custom subroutine, with the default parameters to be restored saved next MARKER definition. -MARKER_DOES ; execution part of MARKER, same effect than RST_STATE, but to restore state before MARKER defn. - .word $+2 ; -- BODY - MOV @TOS+,&RST_DP ; -- BODY+2 thus RST_STATE will restore the word-set state before MARKER - .IFDEF VOCABULARY_SET - MOV @TOS+,&RST_VOC ; -- BODY+4 thus RST_STATE will restore the word-set state before MARKER - .ELSE - ADD #2,TOS ; -- BODY+4 - .ENDIF - CALL @TOS+ ; -- BODY+6 @TOS = RET_ADR|STOP_APP_ADR (default|custom) - MOV @PSP+,TOS ; -- - MOV @RSP+,IP ; - JMP RST_STATE ; then next - - FORTHWORD "MARKER" ; definition part -;( "<spaces>name" -- ) -;Skip leading space delimiters. Parse name delimited by a space. Create a definition for name -;with the execution semantics defined below. - - CALL #HEADER ;4 W = DP+4, Y = NFA, - MOV #1285h,-4(W) ;4 CFA = CALL R5 = rDODOES - MOV #MARKER_DOES,-2(W) ;4 PFA = MARKER_DOES - SUB #2,Y ;1 Y = NFA-2 = LFA - MOV Y,0(W) ;3 BODY = DP value before this MARKER definition - .IFDEF VOCABULARY_SET - MOV &LASTVOC,2(W) ;5 BODY+2 = current VOCLINK - .ENDIF - MOV #RET_ADR,4(W) ; BODY+4 = RET addr, to do nothing by default - ADD #6,&DDP ;4 - JMP GOOD_CSP ; diff --git a/forthMSP430FR_EXTD_ASM.asm b/forthMSP430FR_EXTD_ASM.asm index 4604adf..8ec39f2 100644 --- a/forthMSP430FR_EXTD_ASM.asm +++ b/forthMSP430FR_EXTD_ASM.asm @@ -5,14 +5,16 @@ ; ---------------------------------------------------------------------- ; ---------------------------------------------------------------------- -; MOV(.B) #0, dst is coded as follow : MOV(.B) R3, dst ; 1 cycle, one word As=00 register mode -; MOV(.B) #1, dst is coded as follow : MOV(.B) 0(R3), dst ; 2 cycles, one word AS=01 x(reg) mode -; MOV(.B) #2, dst is coded as follow : MOV(.B) @R3, dst ; 2 cycles, one word AS=10 @reg mode -; MOV(.B) #4, dst is coded as follow : MOV(.B) @R2, dst ; 2 cycles, one word AS=10 @reg mode -; MOV(.B) #8, dst is coded as follow : MOV(.B) @R2+, dst ; 2 cycles, one word AS=11 @reg+ mode -; MOV(.B) #-1,dst is coded as follow : MOV(.B) @R3+, dst ; 2 cycles, one word AS=11 -; MOV(.B) #xxxx,dst is coded a follow : MOV(.B) @PC+, dst ; 2 cycles, two words AS=11 @reg+ mode -; MOV(.B) &EDE,&TON is coded as follow: MOV(.B) EDE(R2),TON(R2) ; (R2=0), three words AS=01, AD=1 x(reg) mode +; MOV(.B) SR,dst is coded as follow : MOV(.B) R2,dst ; 1 cycle, one word AS=00 (register mode) +; MOV(.B) #0,dst is coded as follow : MOV(.B) R3,dst ; 1 cycle, one word AS=00 (register mode) +; MOV(.B) &EDE,dst is coded as follow : MOV(.B) EDE(R2),dst ; 3 cycles, two words AS=01 ( x(reg) mode) +; MOV(.B) #1,dst is coded as follow : MOV(.B) 0(R3),dst ; 1 cycle, one word AS=01 ( x(reg) mode) +; MOV(.B) #4,dst is coded as follow : MOV(.B) @R2,dst ; 1 cycle, one word AS=10 ( @reg mode) +; MOV(.B) #2,dst is coded as follow : MOV(.B) @R3,dst ; 1 cycle, one word AS=10 ( @reg mode) +; MOV(.B) #8,dst is coded as follow : MOV(.B) @R2+,dst ; 1 cycle, one word AS=11 ( @reg+ mode) +; MOV(.B) #-1,dst is coded as follow : MOV(.B) @R3+,dst ; 1 cycle, one word AS=11 ( @reg+ mode) +; ---------------------------------------------------------------------- +; MOV(.B) #xxxx,dst is coded as follow: MOV(.B) @PC+,dst ; 2 cycles, two words AS=11 ( @reg+ mode) ; ---------------------------------------------------------------------- ; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC @@ -25,104 +27,71 @@ ; example : POPM #6,IP pop Y,X,W,T,S,IP registers from return stack - -;;Z SKIP char -- addr ; skip all occurring character 'char' -; FORTHWORD "SKIP" ; used by assembler to parse input stream -SKIP MOV #SOURCE_LEN,Y ;2 - MOV TOS,W ; -- char W=char - MOV @Y+,X ;2 -- char W=char X=buf_length - MOV @Y,TOS ;2 -- Start_buf_adr W=char X=buf_length - ADD TOS,X ; -- Start_buf_adr W=char X=Start_buf_adr+buf_length=End_buf_addr - ADD &TOIN,TOS ; -- Parse_Adr W=char X=End_buf_addr -SKIPLOOP CMP TOS,X ; -- Parse_Adr W=char X=End_buf_addr - JZ SKIPEND ; -- Parse_Adr if end of buffer - CMP.B @TOS+,W ; -- Parse_Adr does character match? - JZ SKIPLOOP ; -- Parse_Adr+1 -SKIPNEXT SUB #1,TOS ; -- addr -SKIPEND MOV TOS,W ; - SUB @Y,W ; -- addr W=Parse_Addr-Start_buf_adr=Toin - MOV W,&TOIN ; - MOV @IP+,PC ; 4 - ; ---------------------------------------------------------------------- -; DTCforthMSP430FR5xxx ASSEMBLER : search argument "xxxx", IP is free +; DTCforthMSP430FR5xxx ASSEMBLER : search argument "xxxx" ; ---------------------------------------------------------------------- -; SearchARG ; separator -- n|d or abort" not found" -; ; Search ARG of "#xxxx," ; <== PARAM10 -; ; Search ARG of "&xxxx," ; <== PARAM111 -; ; Search ARG of "xxxx(REG)," ; <== PARAM130 -; ; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM20 -; ; Search ARG of ",xxxx(REG)" ; <== PARAM210 -; PUSHM #2,S ; PUSHM S,T as OPCODE, OPCODEADR -; ASMtoFORTH ; -- separator search word first -; .word WORDD,FIND ; -- addr -; .word ZEROEQUAL -; .word QFBRAN,ARGWORD ; -- addr if Word found -; .word QNUMBER ; -; .word QFBRAN,NotFound ; -- addr ABORT if not found -; FSearchEnd .word SearchEnd ; -- value goto SearchEnd if number found -; ARGWORD .word $+2 ; -- CFA -; MOV @TOS+,S ; -- PFA S=DOxxx -; QDOVAR SUB #DOVAR,S ; DOxxx = 1287h = DOVAR -; ISDOVAR JZ SearchEnd ; -- addr PFA = adr of VARIABLE -; QDOCON ADD #1,S ; DOxxx = 1286h = DOCON -; JNZ ISOTHER ; -; ISDOCON MOV @TOS,TOS ; -; JMP SearchEnd ; -- cte -; ISOTHER SUB #2,TOS ; -- CFA -; SearchEnd POPM #2,S ; POPM T,S -; MOV @RSP+,PC ; RET - -SearchARG ; separator -- n|d or abort" not found" -; Search ARG of "#xxxx," ; <== PARAM10 -; Search ARG of "&xxxx," ; <== PARAM111 -; Search ARG of "xxxx(REG)," ; <== ComputeARGpREG <== PARAM130 -; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM20 -; Search ARG of ",xxxx(REG)" ; <== ComputeARGpREG <== PARAM210 - PUSHM #2,S ; PUSHM S,T as OPCODE,OPCODEADR - PUSH TOS ; push sep, for SrchARGPO - PUSH &TOIN ; push TOIN, for SrchARGPO -;-----------------------------------; - ASMtoFORTH ; -- sep sep = ','|'('|' ' - .word WORDD,FIND ; -- addr search word first - .word ZEROEQUAL - .word QFBRAN,ARGWORD ; -- addr if Word found - .word QNUMBER ; - .word QFBRAN,SrchARGPO; -- addr search ARG Plus Offset if not found - .word SrchNext ; -- value goto SrchNext if number found -ARGWORD .word $+2 ; -- CFA +; common code for maxi three successive SearchARG: SearchARG, SearchARG+Offset, SearchARG-offset +; leave PFA of VARIABLE, [PFA] of CONSTANT, User_Parameter_Field_Address of MARKER_DOES, CFA for all others. +; if the ARGument is not found after those three SearchARg, the 'not found' error is issued by the last SrchOfst. +SearchARGn PUSH &TOIN ; push TOIN, for next SearchARGn if any + mASM2FORTH ; -- sep sep = ','|'('|' ' + .word WORDD,FIND ; -- addr search string name first + .word QFBRAN,SRCHARGNUM ; -- addr if string name not found + mNEXTADR ; -- CFA MOV @TOS+,S ; -- PFA S=DOxxx QDOVAR SUB #1287h,S ; DOxxx = 1287h = CALL R7 = rDOVAR -ISDOVAR JZ SrchNext ; -- addr PFA = adr of VARIABLE +ISDOVAR JZ ARGFOUND ; -- addr PFA = adr of VARIABLE QDOCON ADD #1,S ; DOxxx = 1286h = DOCON - JNZ ISOTHER ; -ISDOCON MOV @TOS,TOS ; - JMP SrchNext ; -- cte -ISOTHER SUB #2,TOS ; -- CFA -SrchNext ADD #4,RSP ; remove TOIN,sep -SearchEnd POPM #2,S ; POPM T,S - MOV @RSP+,PC ; RET - -;-----------------------------------; -; search for ARGUMENT16+OFFSET ; up to $FFFF only (FORTH area) -;-----------------------------------; -SrchARGPO .word $+2 - MOV @RSP+,&TOIN ; TOIN back - MOV @RSP+,TOS ; -- sep - ASMtoFORTH ; - .word LIT,'+' ; -- sep '+' search argument - .word WORDD,FIND ; -- sep CFA - .word ZEROEQUAL ; - .word QFBRAN,SrchOffst; - .word QNUMBER ; -- sep number - .word QFBRAN,NotFound ; see INTERPRET -SrchOffst .word SWAP ; -- CFA|number sep - .word WORDD,QNUMBER ; Search 'Offset,'|'Offset('|'Offset' - .word QFBRAN,NotFound ; see INTERPRET - .word $+2 ; -- CFA|number offset - ADD @PSP+,TOS ; -- (CFA|number + offset) - JMP SearchEnd ; + JNZ QMARKER ; if not DOCON +ISDOCON MOV @TOS,TOS ; -- + JMP ARGFOUND ; -- cte +QMARKER CMP #MARKER_DOES,0(TOS) ; -- PFA search if PFA = [MARKER_DOES] + JNZ ISOTHER ; -- PFA + .IFDEF VOCABULARY_SET ; -- PFA + ADD #30,TOS ; -- UPFA+2 skip room for DP, CURRENT, CONTEXT(8), null_word, LASTVOC, RET_ADR 2+(2+2+16+2+2+2) +2 bytes + .ELSE ; + ADD #8,TOS ; -- UPFA+2 skip room for DP, RET_ADR 2+(2+2) +2 bytes + .ENDIF ; +ISOTHER SUB #2,TOS ; -- CFA|UPFA UPFA = MARKER_DOES User_Parameter_Field_Address +ARGFOUND ADD #2,RSP ; remove TOIN +SEARCHRET MOV @RSP+,PC ;24 SR(Z)=0 ARG found + +SRCHARGNUM .word QNUMBER ; + .word QFBRAN,ARGNOTFOUND; -- addr if ARG not found SR(Z)=1 + .word ARGFOUND ; -- value +ARGNOTFOUND mNEXTADR ; -- x + MOV @RSP+,&TOIN ; restore TOIN + MOV @RSP+,PC ;32 SR(Z)=1 ARG not found + +SearchIndex +; Search index of "xxxx(REG)," ; <== ComputeIDXpREG <== PARAM13 +; Search index of ",xxxx(REG)" ; <== ComputeIDXpREG <== PARAM21 + SUB #1,&TOIN ; move >IN back one + MOV #'(',TOS ; addr -- "(" as WORD separator to find xxxx of "xxxx(REG)," +SearchARG ; sep -- n|d or abort" not found" +; Search ARG of "#xxxx," ; <== PARAM101 +; Search ARG of "&xxxx," ; <== PARAM111 +; Search ARG of ",&xxxx" ; <== PARAM111 <== PARAM201 + MOV TOS,W + PUSHM #4,IP ; -- sep PUSHM IP, S,T,W as IP_RET,OPCODE,OPCODEADR,sep + CALL #SearchARGn ; first search argument without offset + JNZ SrchEnd ; -- ARG if ARG found goto SrchPopEnd +SearchArgPo MOV #'+',TOS ; -- '+' + CALL #SearchARGn ; 2th search argument with '+' as separator + JNZ ArgPlusOfst ; -- ARG if ARG of ARG+offset found +SearchArgMo MOV #'-',TOS ; -- '-' + CALL #SearchARGn ; 3th search argument with '-' as separator + SUB #1,&TOIN ; to handle offset with its minus sign +ArgPlusOfst PUSH TOS ; -- ARG save ARG on stack + MOV 2(RSP),TOS ; -- sep reload offset sep +SrchOfst mASM2FORTH ; + .word WORDD,QNUMBER ; -- Ofst|c-addr flag + .word QFBRAN,NotFound ; -- c-addr no return, see INTERPRET + mNEXTADR ; -- Ofst + ADD @RSP+,TOS ; -- Arg+Ofst +SrchEnd POPM #4,IP ; POPM W,T,S,IP common return for SearchARG and SearchRn + MOV @RSP+,PC ;66 ; Arg_Double_to_single conversion needed only for OPCODE type V|VI, 2th pass. ARGD2S BIT #UF9,SR ; -- Lo Hi @@ -133,66 +102,49 @@ ARGD2SEND MOV @RSP+,PC ; ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : search REG ; ---------------------------------------------------------------------- - ; compute arg of "xxxx(REG)," ; <== PARAM130, sep=',' ; compute arg of ",xxxx(REG)" ; <== PARAM210, sep=' ' -ComputeARGParenREG ; sep -- Rn - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- xxxx aborted if not found +ComputeIDXpREG ; addr -- Rn|addr + CALL #SearchIndex ; -- xxxx aborted if not found CALL #ARGD2S ; skip arg_hi if DOUBLE - MOV &DDP,X - ADD #2,&DDP - MOV TOS,0(X) ; -- xxxx compile xxxx + MOV &DP,X + MOV TOS,0(X) ; -- xxxx compile ARG xxxx + ADD #2,&DP MOV #')',TOS ; -- ")" prepare separator to search REG of "xxxx(REG)" - -; search REG of "xxxx(REG)," separator = ')' -; search REG of ",xxxx(REG)" separator = ')' +; search REG of "xxxx(REG)," separator = ')' +; search REG of ",xxxx(REG)" separator = ')' ; search REG of "@REG," separator = ',' <== PARAM120 ; search REG of "@REG+," separator = '+' <== PARAM121 +SkipRSearchRn + ADD #1,&TOIN ; skip "R" in input buffer ; search REG of "REG," separator = ',' <== PARAM13 ; search REG of ",REG" separator = BL <== PARAM21 - -SearchREG PUSHM #2,S ; PUSHM S,T as OPCODE, OPCODEADR - CMP &SOURCE_LEN,&TOIN ; bad case of ,xxxx without prefix & - JNZ SearchREG1 ; - MOV #BAD_CSP,PC ; génère une erreur bidon -SearchREG1 PUSH &TOIN ; -- sep save >IN - ADD #1,&TOIN ; skip "R" - ASMtoFORTH ; search xx of Rxx +SearchRn MOV &TOIN,W ; + PUSHM #4,IP ; PUSHM IP, S,T,W as IP_RET,OPCODE,OPCODEADR,TOIN + mASM2FORTH ; search xx of Rxx .word WORDD,QNUMBER ; - .word QFBRAN,NOTaREG ; -- xxxx if Not a Number - .word $+2 ; -- Rn number is found - ADD #2,RSP ; remove >IN - CMP #16,TOS ; -- Rn + .word QFBRAN,REGNOTFOUND; -- xxxx if Not a Number, SR(Z)=1 + mNEXTADR ; -- Rn number is found + CMP #16,TOS ; -- Rn + JNC SrchEnd ; -- Rn Rn is valid, remove TOIN then SrchEnd JC BOUNDERROR ; abort if Rn out of bounds - JNC SearchEnd ; -- Rn Z=0 ==> found -NOTaREG .word $+2 ; -- addr Z=1 - MOV @RSP+,&TOIN ; -- addr restore >IN - JMP SearchEnd ; -- addr Z=1 ==> not a register +REGNOTFOUND mNEXTADR ; -- addr SR(Z)=1, case of @REG not found, + MOV @RSP,&TOIN ; -- addr restore TOIN (to point after prefix 'R') + JMP SrchEnd ; -- addr SR(Z)=1 ==> not a register ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET FIRST OPERAND ; ---------------------------------------------------------------------- - -; PARAM1 is used for OPCODES type I (double operand) and OPCODES type II (single operand) instructions -; PARAM1 is used for OPCODES type V (double operand) and OPCODES type VI (single operand) extended instructions - ; PARAM1 separator -- ; parse input buffer until separator and compute first operand of opcode ; sep is comma for src and space for dst . -PARAM1 mDOCOL ; -- sep OPCODES types I|V sep = ',' OPCODES types II|VI sep = ' ' - .word FBLANK,SKIP ; -- sep addr - .word $+2 ; -- sep addr - MOV #0,S ; -- sep addr reset OPCODE - MOV &DDP,T ; -- sep addr HERE --> OPCODEADR (opcode is preset to its address !) - ADD #2,&DDP ; -- sep addr cell allot for opcode - MOV.B @TOS,W ; -- sep addr W=first char of instruction code - MOV @PSP+,TOS ; -- sep W=c-addr - CMP.B #'#',W ; -- sep W=first char - JNE PARAM11 -; "#" found : case of "#xxxx," -PARAM10 ADD #1,&TOIN ; -- sep skip # prefix - CALL #SearchARG ; -- xxxx abort if not found +PARAM1 JNZ PARAM10 ; -- sep if prefix <> 'R' + CALL #SearchRn ; case of "REG," + JMP PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0 +; ----------------------------------; +PARAM10 CMP.B #'#',W ; -- sep W=first char + JNE PARAM11 +PARAM101 CALL #SearchARG ; -- xxxx abort if not found CALL #ARGD2S ; skip arg_hi of OPCODE type V MOV #0300h,S ; OPCODE = 0300h : MOV #0,dst is coded MOV R3,dst CMP #0,TOS ; -- xxxx #0 ? @@ -206,102 +158,99 @@ PARAM10 ADD #1,&TOIN ; -- sep skip # prefix MOV #0220h,S ; OPCODE = 0220h : MOV #4,dst is coded MOV @R2,dst CMP #4,TOS ; -- xxxx #4 ? JZ PARAMENDOF - MOV #0230h,S ; OPCODE = 0230h : MOV #8,dst is coded MOV @R2+,dst + MOV #0230h,S ; OPCODE = 0230h : MOV #8,dst is coded MOV @R2+,dst CMP #8,TOS ; -- xxxx #8 ? JZ PARAMENDOF - MOV #0330h,S ; -- -1 OPCODE = 0330h : MOV #-1,dst is coded MOV @R3+,dst + MOV #0330h,S ; OPCODE = 0330h : MOV #-1,dst is coded MOV @R3+,dst CMP #-1,TOS ; -- xxxx #-1 ? JZ PARAMENDOF MOV #0030h,S ; -- xxxx for all other cases : MOV @PC+,dst -; case of "&xxxx," ; <== PARAM110 -; case of ",&xxxx" ; <== PARAM20 -StoreArg MOV &DDP,X ; - ADD #2,&DDP ; cell allot for arg -StoreTOS ; <== TYPE1DOES +StoreArg MOV &DP,X ; + ADD #2,&DP ; cell allot for arg MOV TOS,0(X) ; compile arg +; case of "&xxxx," ; <== PARAM111 +; case of ",&xxxx" ; <== PARAM110 <== PARAM201 ; endcase of all "&xxxx" ; ; endcase of all "#xxxx" ; <== PARAM101,102,104,108,10M1 ; endcase of all "REG"|"@REG"|"@REG+" <== PARAM124 PARAMENDOF MOV @PSP+,TOS ; -- - MOV @RSP+,IP ; - MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR + MOV @IP+,PC ; -- S=OPCODE,T=OPCODEADR ; ----------------------------------; PARAM11 CMP.B #'&',W ; -- sep JNE PARAM12 ; case of "&xxxx," ; -- sep search for "&xxxx," PARAM110 MOV #0210h,S ; -- sep set code type : xxxx(SR) with AS=0b01 ==> x210h (and SR=0 !) -; case of "&xxxx," -; case of ",&xxxx" ; <== PARAM20 -PARAM111 ADD #1,&TOIN ; -- sep skip "&" prefix - CALL #SearchARG ; -- arg abort if not found - CALL #ARGD2S ; skip argD_hi of opcode type V +; case of ",&xxxx" ; <== PARAM201 +PARAM111 CALL #SearchARG ; -- arg abort if not found + CALL #ARGD2S ; skip arg_hi of OPCODE type V JMP StoreArg ; -- then ret ; ----------------------------------; PARAM12 CMP.B #'@',W ; -- sep JNE PARAM13 ; case of "@REG,"|"@REG+," PARAM120 MOV #0020h,S ; -- sep init OPCODE with indirect code type : AS=0b10 - ADD #1,&TOIN ; -- sep skip "@" prefix - CALL #SearchREG ; Z = not found - JNZ PARAM123 ; -- value REG of "@REG," found -; case of "@REG+," ; -- addr REG of "@REG" not found, search REG of "@REG+" -PARAM121 ADD #0010h,S ; change OPCODE from @REG to @REG+ type - MOV #'+',TOS ; -- "+" as WORD separator to find REG of "@REG+," - CALL #SearchREG ; -- value|addr X = flag -; case of "@REG+," ; -; case of "xxxx(REG)," ; <== PARAM130 - ; case of double separator: +, and ), -PARAM122 CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma, + CALL #SkipRSearchRn ; Z = not found + JNZ PARAM123 ; -- Rn REG of "@REG," found +; case of "@REG+," ; -- addr search REG of "@REG+" +PARAM121 BIS #0010h,S ; change OPCODE from @REG to @REG+ type + MOV #'+',TOS ; -- sep + CALL #SearchRn ; -- Rn +; case of "xxxx(REG)," ; <== PARAM13 +PARAM122 ; case of double separator: +, and ), + CMP &SOURCE_LEN,&TOIN ; test OPCODE II parameter ending by REG+ or (REG) without comma, JZ PARAM123 ; i.e. >IN = SOURCE_LEN : don't skip char CR ! ADD #1,&TOIN ; -- 000R skip "," ready for the second operand search -; case of "@REG+," -; case of "xxxx(REG)," ; case of "@REG," ; -- 000R <== PARAM120 -; case of "REG," ; -- 000R <== PARAM13 +; case of "REG," ; -- 000R <== PARAM1 PARAM123 SWPB TOS ; -- 0R00 swap bytes because it's not a dst REG typeI (not a 2 ops inst.) -; case of "@REG+," ; -- 0R00 (src REG typeI) -; case of "xxxx(REG)," ; -- 0R00 (src REG typeI or dst REG typeII) -; case of "@REG," ; -- 0R00 (src REG typeI) -; case of "REG," ; -- 0R00 (src REG typeI or dst REG typeII) -; case of ",REG" ; -- 000R <== PARAM21 (dst REG typeI) -; case of ",xxxx(REG)" ; -- 000R <== PARAM210 (dst REG typeI) +; case of ",REG" ; -- 000R <== PARAM2 (dst REG typeI) +; case of ",xxxx(REG)" ; -- 000R <== PARAM21 (dst REG typeI) PARAM124 ADD TOS,S ; -- 0R00|000R JMP PARAMENDOF ; ----------------------------------; -; case of "REG,"|"xxxx(REG)," ; first, searg REG of "REG," -PARAM13 CALL #SearchREG ; -- sep save >IN for second parsing (case of "xxxx(REG),") - JNZ PARAM123 ; -- 000R REG of "REG," found, S=OPCODE=0 -; case of "xxxx(REG)," ; -- c-addr "REG," not found -PARAM130 ADD #0010h,S ; AS=0b01 for indexing address - CALL #ComputeARGparenREG; compile xxxx and search REG of "(REG)" - JMP PARAM122 ; +; case of "xxxx(REG)," ; -- sep +PARAM13 BIS #0010h,S ; AS=0b01 for indexing address + CALL #ComputeIDXpREG ; compile index xxxx and search REG of "(REG)" + JMP PARAM122 ; -- Rn +; ----------------------------------; ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER : INTERPRET 2th OPERAND ; ---------------------------------------------------------------------- - -PARAM3 ; for OPCODES TYPE III - MOV #0,S ; init OPCODE=0 - MOV &DDP,T ; T=OPCODEADR - ADD #2,&DDP ; make room for opcode +PARAM2 JNZ PARAM20 ; -- sep if prefix <> 'R' + CALL #SearchRn ; -- sep case of ",REG" + JMP PARAM124 ; -- 000R REG of ",REG" found ; ----------------------------------; -PARAM2 mDOCOL ; parse input buffer until BL and compute this 2th operand - .word FBLANK,SKIP ; skip space(s) between "arg1," and "arg2" if any; use not S,T. - .word $+2 ; -- c-addr search for '&' of "&xxxx - CMP.B #'&',0(TOS) ; - MOV #20h,TOS ; -- ' ' as WORD separator to find xxxx of ",&xxxx" +PARAM20 CMP.B #'&',W ; JNE PARAM21 ; '&' not found ; case of ",&xxxx" ; -PARAM20 ADD #0082h,S ; change OPCODE : AD=1, dst = R2 +PARAM201 BIS #0082h,S ; change OPCODE : AD=1, dst = R2 JMP PARAM111 ; -- ' ' ; ----------------------------------; -; case of ",REG"|",xxxx(REG) ; -- ' ' first, search REG of ",REG" -PARAM21 CALL #SearchREG ; - JNZ PARAM124 ; -- 000R REG of ",REG" found -; case of ",xxxx(REG) ; -- addr REG not found -PARAM210 ADD #0080h,S ; set AD=1 - CALL #ComputeARGparenREG; compile argument xxxx and search REG of "(REG)" - JMP PARAM124 ; -- 000R REG of "(REG) found +; case of ",xxxx(REG) ; -- sep +PARAM21 BIS #0080h,S ; set AD=1 + CALL #ComputeIDXpREG ; compile index xxxx and search REG of ",xxxx(REG)" + JMP PARAM124 ; -- 000R REG of ",xxxx(REG) found + +; ---------------------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx ASSEMBLER: reset OPCODE in S reg, set OPCODE addr in T reg, +; move Prefix in W reg, skip prefix in input buffer. Flag SR(Z)=1 if prefix = 'R'. +; ---------------------------------------------------------------------------------------- +InitAndSkipPrfx + MOV #0,S ; reset OPCODE + MOV &DP,T ; HERE --> OPCODEADR + ADD #2,&DP ; cell allot for opcode +; SkipPrfx ; -- skip all occurring char 'BL' plus one prefix +SkipPrfx MOV #20h,W ; -- W=BL + MOV &TOIN,X ; -- + ADD &SOURCE_ORG,X ; +SKIPLOOP CMP.B @X+,W ; -- W=BL does character match? + JZ SKIPLOOP ; -- + MOV.B -1(X),W ; W=prefix + SUB &SOURCE_ORG,X ; -- + MOV X,&TOIN ; -- >IN points after prefix + CMP.B #'R',W ; preset SR(Z)=1 if prefix = 'R' + MOV @IP+,PC ; 4 ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE 0 : zero operand f:-) @@ -313,33 +262,36 @@ PARAM210 ADD #0080h,S ; set AD=1 ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER: OPCODES TYPE I : double operand ; ---------------------------------------------------------------------- -; OPCODE(FEDC) -; OPCODE(code) for TYPE I = 0bxxxx opcode I -; OPCODE(BA98) -; = 0bxxxx src register -; OPCODE(7) AD (dst addr type) -; = 0b0 register -; = 0b1 x(Rn),&adr -; OPCODE(6) size -; OPCODE(B) for TYPE I or TYPE II = 0b0 word -; = 0b1 byte -; OPCODE(54) AS (src addr type) -; OPCODE(AS) for TYPE I or OPCODE(AD) for TYPE II = 0b00 register -; = 0b01 x(Rn),&adr -; = 0b10 @Rn -; = 0b11 @Rn+ -; OPCODE(3210) -; OPCODE(dst) for TYPE I or TYPE II = 0bxxxx dst register +; OPCODE(FEDC) +; OPCODE(code) = 0bxxxx opcode +; OPCODE(BA98) +; = 0bxxxx src_register, +; OPCODE(7) AD (dst addr type) +; = 0b0 ,register +; = 0b1 ,x(Rn),&adr +; OPCODE(6) size +; OPCODE(B) = 0b0 word +; = 0b1 byte +; OPCODE(54) AS (src addr type) +; OPCODE(AS) = 0b00 register, +; = 0b01 x(Rn),&adr, +; = 0b10 @Rn, +; = 0b11 @Rn+, +; OPCODE(3210) +; OPCODE(dst) = 0bxxxx ,dst_register ; ---------------------------------------------------------------------- ; TYPE1DOES -- BODYDOES search and compute PARAM1 & PARAM2 as src and dst operands then compile instruction -TYPE1DOES .word lit,',',PARAM1 ; -- BODYDOES - .word PARAM2 ; -- BODYDOES char separator (BL) included in PARAM2 - .word $+2 ; -MAKEOPCODE MOV T,X ; -- opcode X= OPCODEADR to compile opcode - MOV @TOS,TOS ; -- opcode part of instruction - BIS S,TOS ; -- opcode opcode is complete - JMP StoreTOS ; -- then EXIT +TYPE1DOES .word lit,',' + .word InitAndSkipPrfx ; init S=0, T=DP, DP=DP+2 then skip prefix, SR(Z)=1 if prefix = 'R' + .word PARAM1 ; -- BODYDOES + .word BL,SkipPrfx ; SR(Z)=1 if prefix = 'R' + .word PARAM2 ; -- BODYDOES + mNEXTADR ; +MAKEOPCODE MOV @RSP+,IP + BIS @TOS,S ; -- opcode generic opcode + customized S + MOV S,0(T) ; -- opcode store completed opcode + JMP PARAMENDOF ; -- then EXIT asmword "MOV" CALL rDODOES @@ -417,22 +369,25 @@ MAKEOPCODE MOV T,X ; -- opcode X= OPCODEADR to comp ; ---------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES TYPE II : single operand ; ---------------------------------------------------------------------- -; OPCODE(FEDCBA987) opcodeII -; OPCODE(code) for TYPE II = 0bxxxxxxxxx -; OPCODE(6) size -; OPCODE(B) for TYPE I or TYPE II = 0b0 word -; = 0b1 byte -; OPCODE(54) (dst addr type) -; OPCODE(AS) for TYPE I or OPCODE(AD) for TYPE II = 0b00 register -; = 0b01 x(Rn),&adr -; = 0b10 @Rn -; = 0b11 @Rn+ -; OPCODE(3210) -; OPCODE(dst) for TYPE I or TYPE II = 0bxxxx dst register +; OPCODE(FEDCBA987) +; OPCODE(code) = 0bxxxxxxxxx +; OPCODE(6) size +; OPCODE(B) = 0b0 word +; = 0b1 byte +; OPCODE(54) (dst addr type) +; OPCODE(AS) = 0b00 register +; = 0b01 x(Rn),&adr +; = 0b10 @Rn +; = 0b11 @Rn+ +; OPCODE(3210) +; OPCODE(dst) = 0bxxxx dst register ; ---------------------------------------------------------------------- -TYPE2DOES .word FBLANK,PARAM1 ; -- BODYDOES - .word $+2 ; +TYPE2DOES ; -- BODYDOES + .word BL ; -- BODYDOES ' ' + .word InitAndSkipPrfx ; + .word PARAM1 ; -- BODYDOES + mNEXTADR ; MOV S,W ; AND #0070h,S ; keep B/W & AS infos in OPCODE SWPB W ; (REG org --> REG dst) @@ -471,7 +426,7 @@ BIS_ASMTYPE BIS W,S ; -- BODYDOES add it in OPCODE BOUNDERRWM1 ADD #1,W ; <== RRAM|RRUM|RRCM|RLAM error BOUNDERRORW MOV W,TOS ; <== PUSHM|POPM|ASM_branch error BOUNDERROR ; <== REG number error - mDOCOL ; -- n n = value out of bounds + mASM2FORTH ; -- n n = value out of bounds .word DOT,XSQUOTE .byte 13,"out of bounds" .word ABORT_TERM @@ -501,7 +456,7 @@ BOUNDERROR ; <== REG number error CALL rDOCON .word 3000h - asmword "0<" ; jump if 0< ; use only with ?JMP ?GOTO ! + asmword "0<" ; jump if 0< ; use only with ?GOTO ! CALL rDOCON .word 3000h @@ -523,15 +478,15 @@ BOUNDERROR ; <== REG number error ;ASM IF OPCODE -- @OPCODE1 asmword "IF" -ASM_IF MOV &DDP,W +ASM_IF MOV &DP,W MOV TOS,0(W) ; compile incomplete opcode - ADD #2,&DDP + ADD #2,&DP MOV W,TOS - MOV @IP+,PC + MOV @IP+,PC ;ASM THEN @OPCODE -- resolve forward branch asmword "THEN" -ASM_THEN MOV &DDP,W ; -- @OPCODE W=dst +ASM_THEN MOV &DP,W ; -- @OPCODE W=dst MOV TOS,Y ; Y=@OPCODE ASM_THEN1 MOV @PSP+,TOS ; -- MOV Y,X ; @@ -541,27 +496,27 @@ ASM_THEN1 MOV @PSP+,TOS ; -- CMP #512,W JC BOUNDERRORW ; (JHS) unsigned branch if u> 511 BIS W,0(Y) ; -- [@OPCODE]=OPCODE completed - MOV @IP+,PC + MOV @IP+,PC ;C ELSE @OPCODE1 -- @OPCODE2 branch for IF..ELSE asmword "ELSE" -ASM_ELSE MOV &DDP,W ; -- W=HERE +ASM_ELSE MOV &DP,W ; -- W=HERE MOV #3C00h,0(W) ; compile unconditionnal branch - ADD #2,&DDP ; -- DP+2 + ADD #2,&DP ; -- DP+2 SUB #2,PSP MOV W,0(PSP) ; -- @OPCODE2 @OPCODE1 JMP ASM_THEN ; -- @OPCODE2 ; BEGIN -- BEGINadr initialize backward branch asmword "BEGIN" - MOV #HERE,PC + MOV #HEREXEC,PC -;C UNTIL @BEGIN OPCODE -- resolve conditional backward branch +; UNTIL @BEGIN OPCODE -- resolve conditional backward branch asmword "UNTIL" ASM_UNTIL MOV @PSP+,W ; -- OPCODE W=@BEGIN ASM_UNTIL1 MOV TOS,Y ; Y=OPCODE W=@BEGIN ASM_UNTIL2 MOV @PSP+,TOS ; -- - MOV &DDP,X ; -- Y=OPCODE X=HERE W=dst + MOV &DP,X ; -- Y=OPCODE X=HERE W=dst SUB #2,W ; -- Y=OPCODE X=HERE W=dst-2 SUB X,W ; -- Y=OPCODE X=src W=src-dst-2=displacement (bytes) RRA W ; -- Y=OPCODE X=HERE W=displacement (words) @@ -570,22 +525,22 @@ ASM_UNTIL2 MOV @PSP+,TOS ; -- AND #3FFh,W ; -- Y=OPCODE X=HERE W=troncated negative displacement (words) BIS W,Y ; -- Y=OPCODE (completed) MOV Y,0(X) - ADD #2,&DDP - MOV @IP+,PC + ADD #2,&DP + MOV @IP+,PC -;X AGAIN @BEGIN -- uncond'l backward branch +; AGAIN @BEGIN -- uncond'l backward branch ; unconditional backward branch asmword "AGAIN" ASM_AGAIN MOV TOS,W ; W=@BEGIN MOV #3C00h,Y ; Y = asmcode JMP JMP ASM_UNTIL2 ; -;C WHILE @BEGIN OPCODE -- @WHILE @BEGIN +; WHILE @BEGIN OPCODE -- @WHILE @BEGIN asmword "WHILE" ASM_WHILE mDOCOL ; -- @BEGIN OPCODE .word ASM_IF,SWAP,EXIT -;C REPEAT @WHILE @BEGIN -- resolve WHILE loop +; REPEAT @WHILE @BEGIN -- resolve WHILE loop asmword "REPEAT" ASM_REPEAT mDOCOL ; -- @WHILE @BEGIN .word ASM_AGAIN,ASM_THEN,EXIT @@ -594,18 +549,35 @@ ASM_REPEAT mDOCOL ; -- @WHILE @BEGIN ; DTCforthMSP430FR5xxx ASSEMBLER : branch up to 3 backward labels and up to 3 forward labels ; ------------------------------------------------------------------------------------------ ; used for non canonical branchs, as BASIC language: "goto line x" -; labels BWx and FWx must be set at the beginning of line (>IN < 8). +; labels BWx and FWx must be respectively set and used at the beginning of line (>IN < 8). ; FWx at the beginning of a line can resolve only one previous GOTO|?GOTO FWx. ; BWx at the beginning of a line can be resolved by any subsequent GOTO|?GOTO BWx. -BACKWDOES .word $+2 +;BACKWDOES FORTHtoASM +; MOV @RSP+,IP +; MOV @TOS,TOS +; MOV TOS,Y ; Y = ASMBWx +; MOV @PSP+,TOS ; +; MOV @Y,W ; W = [BWx] +; CMP #8,&TOIN ; are we colon 8 or more ? +;BACKWUSE JHS ASM_UNTIL1 ; yes, use this label +;BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP +; mNEXT + +;; backward label 1 +; asmword "BW1" +; mdodoes +; .word BACKWDOES +; .word ASMBW1 ; in RAM + +BACKWDOES mNEXTADR MOV @RSP+,IP ; - MOV TOS,Y ; -- PFA Y = ASMBWx addr + MOV TOS,Y ; -- BODY Y = ASMBWx addr MOV @PSP+,TOS ; -- MOV @Y,W ; W = LABEL CMP #8,&TOIN ; are we colon 8 or more ? -BACKWUSE JC ASM_UNTIL1 ; yes, use this label -BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP +BACKWUSE JC ASM_UNTIL1 ; yes, use this label +BACKWSET MOV &DP,0(Y) ; no, set LABEL = DP MOV @IP+,PC ; backward label 1 @@ -624,16 +596,37 @@ BACKWSET MOV &DDP,0(Y) ; no, set LABEL = DP .word BACKWDOES .word 0 -FORWDOES .word $+2 +;FORWDOES mNEXTADR +; MOV @RSP+,IP +; MOV &DP,W ; +; MOV @TOS,TOS +; MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx +; MOV #0,0(TOS) ; clear @OPCODE of FWx to erratic 2th resolution +; CMP #8,&TOIN ; are we colon 8 or more ? +;FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE +;FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode +; ADD #2,&DP ; increment DP +; MOV W,0(TOS) ; store @OPCODE into ASMFWx +; MOV @PSP+,TOS ; -- +; MOV @IP+,PC +; +;; forward label 1 +; asmword "FW1" +; CALL rDODOES ; CFA +; .word FORWDOES ; +; .word ASMFW1 ; in RAM + +FORWDOES mNEXTADR MOV @RSP+,IP - MOV &DDP,W ; - MOV @TOS,Y ; -- PFA Y=[ASMFWx] + MOV &DP,W ; + MOV @TOS,Y ; -- BODY Y=@OPCODE of FWx + MOV #0,0(TOS) ; clear @OPCODE of FWx to avoid erratic 2th resolution CMP #8,&TOIN ; are we colon 8 or more ? -FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DDP, Y=ASMFWx -FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcode - ADD #2,&DDP ; increment DDP - MOV W,0(TOS) ; store @OPCODE into ASMFWx - MOV @PSP+,TOS ; -- +FORWUSE JNC ASM_THEN1 ; no: resolve FWx with W=DP, Y=@OPCODE +FORWSET MOV @PSP+,0(W) ; yes compile opcode (without displacement) + ADD #2,&DP ; increment DP + MOV W,0(TOS) ; store @OPCODE into BODY of FWx + MOV @PSP+,TOS ; -- MOV @IP+,PC ; forward label 1 @@ -652,6 +645,15 @@ FORWSET MOV @PSP+,0(W) ; yes compile incomplete opcod .word FORWDOES .word 0 +;ASM GOTO <label> -- unconditionnal branch to label + asmword "GOTO" + SUB #2,PSP + MOV TOS,0(PSP) + MOV #3C00h,TOS ; -- JMP_OPCODE +GOTONEXT mDOCOL + .word TICK ; -- OPCODE CFA<label> + .word EXECUTE,EXIT + ;ASM <cond> ?GOTO <label> OPCODE -- conditionnal branch to label asmword "?GOTO" INVJMP CMP #3000h,TOS ; invert code jump process @@ -660,22 +662,13 @@ INVJMP CMP #3000h,TOS ; invert code jump process BIT #1000h,TOS ; 3xxxh case ? JZ GOTONEXT ; no XOR #0800h,TOS ; complementary action for JL<-->JGE -GOTONEXT mDOCOL - .word TICK ; -- OPCODE CFA<label> - .word EXECUTE,EXIT - -;ASM GOTO <label> -- unconditionnal branch to label - asmword "GOTO" - SUB #2,PSP - MOV TOS,0(PSP) - MOV #3C00h,TOS ; asmcode JMP JMP GOTONEXT ; -------------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES TYPE III : PUSHM|POPM|RLAM|RRAM|RRUM|RRCM ; -------------------------------------------------------------------------------- -; PUSHM, syntax: PUSHM #n,REG with 0 < n < 17 -; POPM syntax: POPM #n,REG with 0 < n < 17 +; PUSHM, syntax: PUSHM #n,REG with 0 < n < 17 +; POPM syntax: POPM #n,REG with 0 < n < 17 ; PUSHM order : PSP,TOS, IP, S, T, W, X, Y, rEXIT,rDOVAR,rDOCON, rDODOES, R3, SR,RSP, PC @@ -688,17 +681,17 @@ GOTONEXT mDOCOL ; example : POPM #6,IP pulls Y,X,W,T,S,IP registers from return stack -; RxxM syntax: RxxM #n,REG with 0 < n < 5 - -TYPE3DOES .word FBLANK,SKIP ; skip spaces if any - .word $+2 ; -- BODYDOES c-addr - ADD #1,&TOIN ; skip "#" - MOV #',',TOS ; -- BODYDOES "," - ASMtoFORTH - .word WORDD,QNUMBER - .word QFBRAN,NotFound ; ABORT - .word PARAM3 ; -- BODYDOES 0x000N S=OPCODE = 0x000R - .word $+2 +; RxxM syntax: RxxM #n,REG with 0 < n < 5 + +TYPE3DOES ; -- BODYDOES + .word SkipPrfx ; + .word LIT,',' ; -- BODYDOES ',' + .word WORDD,QNUMBER ; + .word QFBRAN,NotFound ; see INTERPRET + .word BL ; -- BODYDOES n ' ' + .word InitAndSkipPrfx ; -- BODYDOES n ' ' + .word PARAM2 ; -- BODYDOES n S=OPCODE = 0x000R + mNEXTADR MOV TOS,W ; -- BODYDOES n W = n MOV @PSP+,TOS ; -- BODYDOES SUB #1,W ; W = n floored to 0 @@ -707,17 +700,17 @@ TYPE3DOES .word FBLANK,SKIP ; skip spaces if any RLAM #4,X ; OPCODE bit 1000h --> C JNC RxxMINSTRU ; if bit 1000h = 0 PxxxINSTRU MOV S,Y ; S=REG, Y=REG to test - RLAM #3,X ; OPCODE bit 0200h --> C + RLAM #3,X ; OPCODE bit 0200h --> C JNC PUSHMINSTRU ; W=n-1 Y=REG POPMINSTRU SUB W,S ; to make POPM opcode, compute first REG to POP; TI is complicated.... PUSHMINSTRU SUB W,Y ; Y=REG-(n-1) CMP #16,Y JC BOUNDERRWM1 ; JC=JHS (U>=) - RLAM #4,W ; W = n << 4 - JMP BIS_ASMTYPE ; BODYDOES -- + RLAM #4,W ; W = n << 4 + JMP BIS_ASMTYPE ; BODYDOES -- RxxMINSTRU CMP #4,W ; JC BOUNDERRWM1 ; JC=JHS (U>=) - SWPB W ; -- BODYDOES W = n << 8 + SWPB W ; W = n << 8 RLAM #2,W ; W = N << 10 JMP BIS_ASMTYPE ; BODYDOES -- @@ -739,7 +732,6 @@ RxxMINSTRU CMP #4,W ; asmword "POPM" CALL rDODOES .word TYPE3DOES,1700h - asmword "RRCM.A" CALL rDODOES .word TYPE3DOES,0040h @@ -763,163 +755,132 @@ RxxMINSTRU CMP #4,W ; ; DTCforthMSP430FR5xxx ASSEMBLER: OPCODE TYPE III bis: CALLA (without extended word) ; -------------------------------------------------------------------------------- ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) -; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) +; indexed instructions must be written as $xxxx(REG) ; -------------------------------------------------------------------------------- - asmword "CALLA" mDOCOL - .word FBLANK,SKIP ; -- addr - .word $+2 - MOV &DDP,T ; T = DDP - ADD #2,&DDP ; make room for opcode - MOV.B @TOS,TOS ; -- char First char of opcode + .word BL ; -- sep + .word InitAndSkipPrfx ; -- sep SR(Z)=1 if prefix = 'R' + mNEXTADR + MOV @RSP+,IP CALLA0 MOV #134h,S ; 134h<<4 = 1340h = opcode for CALLA Rn - CMP.B #'R',TOS - JNZ CALLA1 -CALLA01 MOV.B #' ',TOS ; -CALLA02 CALL #SearchREG ; -- Rn -CALLA03 RLAM #4,S ; (opcode>>4)<<4 = opcode - BIS TOS,S ; update opcode + JNZ CALLA1 ; -- sep if prefix <> 'R' +CALLA01 CALL #SearchRn ; -- Rn +CALLA02 RLAM #4,S ; (opcode>>4)<<4 = opcode + BIS TOS,S ; update opcode with Rn|$x MOV S,0(T) ; store opcode - MOV @PSP+,TOS - MOV @RSP+,IP - MOV @IP+,PC + MOV @PSP+,TOS ; -- + MOV @IP+,PC ; ;-----------------------------------; -CALLA1 ADD #2,S ; 136h<<4 = opcode for CALLA @REG - CMP.B #'@',TOS ; -- char Search @REG +CALLA1 ADD #2,S ; -- sep 136h<<4 = opcode for CALLA @REG + CMP.B #'@',W ; Search @REG JNZ CALLA2 ; - ADD #1,&TOIN ; skip '@' - MOV.B #' ',TOS ; -- ' ' - CALL #SearchREG ; - JNZ CALLA03 ; if REG found, update opcode +CALLA11 CALL #SkipRSearchRn ; + JNZ CALLA02 ; if REG found, update opcode ;-----------------------------------; ADD #1,S ; 137h<<4 = opcode for CALLA @REG+ - MOV #'+',TOS ; -- '+' - JMP CALLA02 ; + MOV #'+',TOS ; -- sep + JMP CALLA01 ; ;-----------------------------------; -CALLA2 ADD #2,&DDP ; make room for xxxx of #$x.xxxx|&$x.xxxx|$0.xxxx(REG) - CMP.B #'#',TOS ; +CALLA2 ADD #2,&DP ; -- sep make room for xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG) + CMP.B #'#',W ; JNZ CALLA3 MOV #13Bh,S ; 13Bh<<4 = opcode for CALLA #$x.xxxx -CALLA21 ADD #1,&TOIN ; skip '#'|'&' -CALLA22 CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store #$xxxx|&$xxxx - JMP CALLA03 ; update opcode with $x. and store opcode +CALLA21 CALL #SearchARG ; -- Lo Hi + MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx + JMP CALLA02 ; update opcode with $x. and store opcode ;-----------------------------------; -CALLA3 CMP.B #'&',TOS +CALLA3 CMP.B #'&',W ; -- sep JNZ CALLA4 ; ADD #2,S ; 138h<<4 = opcode for CALLA &$x.xxxx JMP CALLA21 ;-----------------------------------; -CALLA4 MOV.B #'(',TOS ; -- "(" - SUB #1,S ; 135h<<4 = opcode for CALLA $0.xxxx(REG) -CALLA41 CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx - MOV #')',TOS ; -- ')' - JMP CALLA02 ; search Rn and update opcode - +CALLA4 SUB #1,S ; 135h<<4 = opcode for CALLA $xxxx(REG) +CALLA41 CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n store $xxxx of $xxxx(REG) + MOV #')',TOS ; -- sep + JMP CALLA11 ; search Rn and update opcode ; =============================================================== ; to allow data access beyond $FFFF ; =============================================================== -; MOVA (#$x.xxxx|&$x.xxxx|$.xxxx(Rs)|Rs|@Rs|@Rs+ , &|Rd|$.xxxx(Rd)) -; ADDA (#$x.xxxx|Rs , Rd) -; CMPA (#$x.xxxx|Rs , Rd) -; SUBA (#$x.xxxx|Rs , Rd) +; MOVA (#$x.xxxx|&$x.xxxx|$xxxx(Rs)|Rs|@Rs|@Rs+ , &|Rd|$xxxx(Rd)) +; ADDA (#$x.xxxx|Rs , Rd) +; CMPA (#$x.xxxx|Rs , Rd) +; SUBA (#$x.xxxx|Rs , Rd) ; first argument process ACMS1 ;-----------------------------------; -ACMS1 mDOCOL ; -- BODYDOES ',' - .word FBLANK,SKIP ; -- BODYDOES ',' addr - .word $+2 ; - MOV.B @TOS,X ; X=first char of opcode string - MOV @PSP+,TOS ; -- BODYDOES ',' - MOV @PSP+,S ; -- ',' S=BODYDOES - MOV @S,S ; S=opcode - MOV &DDP,T ; T=DDP - ADD #2,&DDP ; make room for opcode +ACMS1 MOV @PSP+,S ; -- sep S=BODYDOES + MOV @S,S ; S=opcode ;-----------------------------------; -ACMS10 CMP.B #'R',X ; -- ',' - JNZ ACMS11 ; -ACMS101 CALL #SearchREG ; -- Rn src +ACMS10 JNZ ACMS11 ; -- sep if prefix <> 'R' +ACMS101 CALL #SearchRn ; -- Rn ACMS102 RLAM #4,TOS ; 8<<src RLAM #4,TOS ; ACMS103 BIS S,TOS ; update opcode with src|dst MOV TOS,0(T) ; save opcode MOV T,TOS ; -- OPCODE_addr - MOV @RSP+,IP MOV @IP+,PC ; ;-----------------------------------; -ACMS11 CMP.B #'#',X ; -- ',' X=addr +ACMS11 CMP.B #'#',W ; -- sep X=addr JNE MOVA12 ; BIC #40h,S ; set #opcode -ACMS111 ADD #1,&TOIN ; skip '#'|'&' - ADD #2,&DDP ; make room for low #$xxxx|&$xxxx|$xxxx(REG) +ACMS111 ADD #2,&DP ; make room for low #$xxxx|&$xxxx|$xxxx(REG) CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx|$x.xxxx(REG) + MOV @PSP+,2(T) ; -- Hi store $xxxx of #$x.xxxx|&$x.xxxx|$xxxx(REG) AND #0Fh,TOS ; -- Hi sel Hi src JMP ACMS102 ; ;-----------------------------------; -MOVA12 CMP.B #'&',X ; -- ',' case of MOVA &$x.xxxx +MOVA12 CMP.B #'&',W ; -- sep case of MOVA &$x.xxxx JNZ MOVA13 ; - XOR #00E0h,S ; set MOVA &$x.xxxx, opcode + XOR #00E0h,S ; set MOVA &$x.xxxx, opcode JMP ACMS111 ; ;-----------------------------------; MOVA13 BIC #00F0h,S ; set MOVA @REG, opcode - CMP.B #'@',X ; -- ',' + CMP.B #'@',W ; -- sep JNZ MOVA14 ; - ADD #1,&TOIN ; skip '@' - CALL #SearchREG ; -- Rn + CALL #SkipRSearchRn ; -- Rn JNZ ACMS102 ; if @REG found -;-----------------------------------; BIS #0010h,S ; set @REG+ opcode MOV #'+',TOS ; -- '+' -MOVA131 CALL #SearchREG ; -- Rn case of MOVA @REG+,|MOVA $x.xxxx(REG), - CMP &SOURCE_LEN,&TOIN ; test TYPE II first parameter ending by @REG+ (REG) without comma, - JZ ACMS102 ; i.e. may be >IN = SOURCE_LEN: don't skip char CR ! - ADD #1,&TOIN ; skip "," ready for the second operand search +MOVA131 CALL #SearchRn ; -- Rn case of MOVA @REG+,|MOVA $x.xxxx(REG), +MOVA132 ADD #1,&TOIN ; skip "," ready for the second operand search JMP ACMS102 ; ;-----------------------------------; -MOVA14 BIS #0030h,S ; set xxxx(REG), opcode - ADD #2,&DDP ; -- ',' make room for first $xxxx of $0.xxxx(REG), - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi store $xxxx as 2th word +MOVA14 BIS #0030h,S ; -- sep set xxxx(REG), opcode + ADD #2,&DP ; make room for first $xxxx of $xxxx(REG), + CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n store $xxxx as 2th word MOV #')',TOS ; -- ')' - JMP MOVA131 ; + CALL #SkipRSearchRn ; -- Rn + JMP MOVA132 ; ; 2th argument process ACMS2 -;-----------------------------------; -ACMS2 mDOCOL ; -- OPCODE_addr - .word FBLANK,SKIP ; -- OPCODE_addr addr - .word $+2 ; - MOV @PSP+,T ; -- addr T=OPCODE_addr +;-----------------------------------; -- OPCODE_addr sep +ACMS2 MOV @PSP+,T ; -- sep T=OPCODE_addr MOV @T,S ; S=opcode - MOV.B @TOS,X ; -- addr X=first char of string instruction - MOV.B #' ',TOS ; -- ' ' ;-----------------------------------; -ACMS21 CMP.B #'R',X ; -- ' ' - JNZ MOVA22 ; -ACMS211 CALL #SearchREG ; -- Rn +ACMS21 JNZ MOVA22 ; -- sep if prefix <> 'R' +ACMS211 CALL #SearchRn ; -- Rn JMP ACMS103 ; ;-----------------------------------; -MOVA22 BIC #0F0h,S ; - ADD #2,&DDP ; -- ' ' make room for $xxxx - CMP.B #'&',X ; +MOVA22 BIC #0F0h,S ; -- sep + ADD #2,&DP ; make room for $xxxx + CMP.B #'&',W ; JNZ MOVA23 ; BIS #060h,S ; set ,&$x.xxxx opcode - ADD #1,&TOIN ; skip '&' CALL #SearchARG ; -- Lo Hi MOV @PSP+,2(T) ; -- Hi store $xxxx as 2th word JMP ACMS103 ; update opcode with dst $x and write opcode ;-----------------------------------; MOVA23 BIS #070h,S ; set ,xxxx(REG) opcode - MOV #'(',TOS ; -- "(" as WORD separator to find xxxx of "xxxx(REG)," - CALL #SearchARG ; -- Lo Hi - MOV @PSP+,2(T) ; -- Hi write $xxxx of ,$0.xxxx(REG) as 2th word + CALL #SearchIndex ; -- n + MOV TOS,2(T) ; -- n write $xxxx of ,$xxxx(REG) as 2th word MOV #')',TOS ; -- ")" as WORD separator to find REG of "xxxx(REG)," - JMP ACMS211 + CALL #SkipRSearchRn ; -- Rn + JMP ACMS103 ; -------------------------------------------------------------------------------- ; DTCforthMSP430FR5xxx ASSEMBLER, OPCODES IV 2 operands: Adda|Cmpa|Mova|Suba (without extended word) @@ -927,11 +888,12 @@ MOVA23 BIS #070h,S ; set ,xxxx(REG) opcode ; absolute and immediate instructions must be written as $x.xxxx (DOUBLE numbers) ; indexed instructions must be written as $.xxxx(REG) (DOUBLE numbers) ; -------------------------------------------------------------------------------- - TYPE4DOES .word lit,',' ; -- BODYDOES "," char separator for PARAM1 + .word InitAndSkipPRFX ; SR(Z)=1 if prefix = 'R' .word ACMS1 ; -- OPCODE_addr + .word BL,SkipPRFX ; SR(Z)=1 if prefix = 'R' .word ACMS2 ; -- OPCODE_addr - .word DROP,EXIT + .word DROPEXIT asmword "MOVA" CALL rDODOES @@ -949,54 +911,43 @@ TYPE4DOES .word lit,',' ; -- BODYDOES "," char separator for ; PRMX1 is used for OPCODES type V (double operand) and OPCODES type VI (single operand) extended instructions -PRMX1 mDOCOL ; -- sep OPCODES type V|VI separator = ','|' ' - .word FBLANK,SKIP ; -- sep addr - .word $+2 ; - MOV.B @TOS,X ; -- sep addr X= first char of opcode string - MOV @PSP+,TOS ; -- sep - MOV #1800h,S ; init S=Extended word +PRMX1 MOV #1800h,S ; init S=Extended word ;-----------------------------------; -PRMX10 CMP.B #'R',X ; -- sep - JNZ PRMX11 ; -PRMX101 CALL #SearchREG ; -- Rn Rn of REG; call SearchREG only to update >IN -PRMX102 MOV S,TOS ; -- EW update Extended word -PRMX103 MOV @RSP+,IP - MOV @IP+,PC ; -- Ext_Word +PRMX10 JNZ PRMX11 ; -- sep if prefix <> 'R' +PRMX101 CALL #SearchRn ; -- Rn Rn of REG; call SearchRn only to update >IN +PRMX102 MOV S,TOS ; -- EW init|update Extended word +PRMX103 MOV @IP+,PC ; -- Ext_Word ;-----------------------------------; PRMX11 MOV #0,&RPT_WORD ; clear RPT - CMP.B #'#',X ; -- sep + CMP.B #'#',W ; -- sep JNZ PRMX12 -PRMX111 ADD #1,&TOIN ; -- sep skip '#' -PRMX112 CALL #SearchARG ; -- Lo Hi search $x.xxxx of #x.xxxx, +PRMX111 CALL #SearchARG ; -- Lo Hi search $x.xxxx of #x.xxxx, ADD #2,PSP ; -- Hi pop unused low word -PRMX113 AND #0Fh,TOS ; +PRMX113 AND #0Fh,TOS ; PRMX114 RLAM #3,TOS RLAM #4,TOS ; -- 7<<Hi PRMX115 BIS TOS,S ; update extended word with srcHi JMP PRMX102 ;-----------------------------------; -PRMX12 CMP.B #'&',X ; -- sep +PRMX12 CMP.B #'&',W ; -- sep JZ PRMX111 ;-----------------------------------; -PRMX13 CMP.B #'@',X ; -- sep +PRMX13 CMP.B #'@',W ; -- sep JNZ PRMX14 -PRMX131 ADD #1,&TOIN ; -- sep skip '@' -PRMX132 CALL #SearchREG ; -- Rn Rn of @REG, +PRMX131 CALL #SkipRSearchRn ; -- Rn Rn of @REG, JNZ PRMX102 ; if Rn found ;-----------------------------------; MOV #'+',TOS ; -- '+' -PRMX133 ADD #1,&TOIN ; skip '@' - CALL #SearchREG ; -- Rn Rn of @REG+, +PRMX133 CALL #SearchRn ; -- Rn Rn of @REG+, PRMX134 CMP &SOURCE_LEN,&TOIN ; test case of TYPE VI first parameter without ',' JZ PRMX102 ; don't take the risk of skipping CR ! ADD #1,&TOIN ; skip ',' ready to search 2th operand JMP PRMX102 ; ;-----------------------------------; -PRMX14 MOV #'(',TOS ; -- '(' to find $x.xxxx of "x.xxxx(REG)," - CALL #SearchARG ; -- Lo Hi +PRMX14 CALL #SearchIndex ; -- n MOV TOS,0(PSP) ; -- Hi Hi PRMX141 MOV #')',TOS ; -- Hi ')' - CALL #SearchREG ; -- Hi Rn + CALL #SkipRSearchRn ; -- Hi Rn MOV @PSP+,TOS ; -- Hi AND #0Fh,TOS BIS TOS,S @@ -1004,53 +955,30 @@ PRMX141 MOV #')',TOS ; -- Hi ')' ;-----------------------------------; ; PRMX2 is used for OPCODES type V (double operand) extended instructions - + ;-----------------------------------; -PRMX2 mDOCOL ; -- Extended_Word - .word FBLANK,SKIP ; -- Extended_Word addr - .word $+2 ; - MOV @PSP+,S ; -- addr S=Extended_Word - MOV.B @TOS,X ; -- addr X=first char of code instruction - MOV #' ',TOS ; -- ' ' +PRMX2 MOV @PSP+,S ; -- addr S=Extended_Word ;-----------------------------------; -PRMX20 CMP.B #'R',X ; -- ' ' - JZ PRMX102 ; extended word not to be updated +PRMX20 JZ PRMX102 ; -- sep if prefix <> 'R' ;-----------------------------------; PRMX21 MOV #0,&RPT_WORD ; - CMP.B #'&',X ; + CMP.B #'&',W ; JNZ PRMX22 ; -PRMX211 ADD #1,&TOIN ; -- ' ' skip '&' -PRMX212 CALL #SearchARG ; -- Lo Hi +PRMX211 CALL #SearchARG ; -- Lo Hi PRMX213 ADD #2,PSP ; -- hi pop low word AND #0Fh,TOS ; -- Hi JMP PRMX115 ; update Extended word with dst_Hi ;-----------------------------------; -PRMX22 MOV #'(',TOS ; -- '(' as WORD separator to find xxxx of "xxxx(REG)" - CALL #SearchARG ; -- Lo Hi search x.xxxx of x.xxxx(REG) +PRMX22 CALL #SearchIndex ; -- n JMP PRMX213 - -;; UPDATE_eXtendedWord -;;-----------------------------------; -;UPDATE_XW ; BODYDOES Extended_Word -- BODYDOES+2 >IN R-- -; MOV &DDP,T ; -; ADD #2,&DDP ; make room for extended word -; MOV TOS,S ; S = Extended_Word -; MOV @PSP+,TOS ; -- BODYDOES -; BIS &RPT_WORD,S ; update Extended_word with RPT_WORD -; MOV #0,&RPT_WORD ; clear RPT before next instruction -; BIS @TOS+,S ; -- BODYDOES+2 update Extended_word with [BODYDOES] = A/L bit -; MOV S,0(T) ; store extended word -; MOV @RSP+,&TOIN ; >IN R-- restore >IN at the start of instruction string -; MOV @IP+,PC ; -;;-----------------------------------; ;-----------------------------------; ; UPDATE_eXtendedWord ;-----------------------------------; UPDATE_XW ; BODYDOES >IN Extended_Word -- BODYDOES+2 MOV @PSP+,&TOIN ; -- BODYDOES EW restore >IN at the start of instruction string - MOV &DDP,T ; - ADD #2,&DDP ; make room for extended word + MOV &DP,T ; + ADD #2,&DP ; make room for extended word MOV TOS,S ; S = Extended_Word MOV @PSP+,TOS ; BIS &RPT_WORD,S ; update Extended_word with RPT_WORD @@ -1074,14 +1002,10 @@ UPDATE_XW ; BODYDOES >IN Extended_Word -- BODYDOES+2 ; all numeric arguments must be written as DOUBLE numbers (including a point) : $x.xxxx TYPE5DOES ; -- BODYDOES -; .word LIT,TOIN,FETCH,TOR ; R-- >IN save >IN for 2th pass -; .word lit,',' ; -- BODYDOES ',' char separator for PRMX1 -; .word PRMX1,PRMX2 ; -- BODYDOES Extended_Word -; .word UPDATE_XW ; -- BODYDOES+2 >IN is restored ready for 2th pass -; .word BRAN,TYPE1DOES ; -- BODYDOES+2 2th pass: completes instruction with opcode = [BODYDOES+2] .word LIT,TOIN,FETCH ; -- BODYDOES >IN - .word lit,',' ; -- BODYDOES >IN ',' char separator for PRMX1 - .word PRMX1,PRMX2 ; -- BODYDOES >IN Extended_Word + .word lit,',' + .word SkipPrfx,PRMX1 ; -- BODYDOES >IN ',' char separator for PRMX1 + .word BL,SkipPrfx,PRMX2 ; -- BODYDOES >IN Extended_Word .word UPDATE_XW ; -- BODYDOES+2 >IN is restored ready for 2th pass .word BRAN,TYPE1DOES ; -- BODYDOES+2 2th pass: completes instruction with opcode = [BODYDOES+2] @@ -1097,103 +1021,103 @@ TYPE5DOES ; -- BODYDOES CALL rDODOES .word TYPE5DOES,40h,4040h asmword "ADDX" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,40h,5000h asmword "ADDX.A" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,0,5040h asmword "ADDX.B" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,40h,5040h - asmword "ADDCX" - CALL rDODOES + asmword "ADDCX" + CALL rDODOES .word TYPE5DOES,40h,6000h asmword "ADDCX.A" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,0,6040h asmword "ADDCX.B" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,40h,6040h - asmword "SUBCX" - CALL rDODOES + asmword "SUBCX" + CALL rDODOES .word TYPE5DOES,40h,7000h asmword "SUBCX.A" CALL rDODOES .word TYPE5DOES,0,7040h asmword "SUBCX.B" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,40h,7040h - asmword "SUBX" - CALL rDODOES + asmword "SUBX" + CALL rDODOES .word TYPE5DOES,40h,8000h - asmword "SUBX.A" - CALL rDODOES + asmword "SUBX.A" + CALL rDODOES .word TYPE5DOES,0,8040h - asmword "SUBX.B" - CALL rDODOES + asmword "SUBX.B" + CALL rDODOES .word TYPE5DOES,40h,8040h - asmword "CMPX" - CALL rDODOES + asmword "CMPX" + CALL rDODOES .word TYPE5DOES,40h,9000h - asmword "CMPX.A" - CALL rDODOES + asmword "CMPX.A" + CALL rDODOES .word TYPE5DOES,0,9040h - asmword "CMPX.B" - CALL rDODOES + asmword "CMPX.B" + CALL rDODOES .word TYPE5DOES,40h,9040h asmword "DADDX" CALL rDODOES .word TYPE5DOES,40h,0A000h asmword "DADDX.A" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,0,0A040h asmword "DADDX.B" - CALL rDODOES + CALL rDODOES .word TYPE5DOES,40h,0A040h - asmword "BITX" - CALL rDODOES + asmword "BITX" + CALL rDODOES .word TYPE5DOES,40h,0B000h - asmword "BITX.A" - CALL rDODOES + asmword "BITX.A" + CALL rDODOES .word TYPE5DOES,0,0B040h - asmword "BITX.B" - CALL rDODOES + asmword "BITX.B" + CALL rDODOES .word TYPE5DOES,40h,0B040h - asmword "BICX" - CALL rDODOES + asmword "BICX" + CALL rDODOES .word TYPE5DOES,40h,0C000h - asmword "BICX.A" - CALL rDODOES + asmword "BICX.A" + CALL rDODOES .word TYPE5DOES,0,0C040h - asmword "BICX.B" - CALL rDODOES + asmword "BICX.B" + CALL rDODOES .word TYPE5DOES,40h,0C040h asmword "BISX" CALL rDODOES .word TYPE5DOES,40h,0D000h - asmword "BISX.A" - CALL rDODOES + asmword "BISX.A" + CALL rDODOES .word TYPE5DOES,0,0D040h - asmword "BISX.B" - CALL rDODOES + asmword "BISX.B" + CALL rDODOES .word TYPE5DOES,40h,0D040h - asmword "XORX" - CALL rDODOES + asmword "XORX" + CALL rDODOES .word TYPE5DOES,40h,0E000h - asmword "XORX.A" - CALL rDODOES + asmword "XORX.A" + CALL rDODOES .word TYPE5DOES,0,0E040h - asmword "XORX.B" - CALL rDODOES + asmword "XORX.B" + CALL rDODOES .word TYPE5DOES,40h,0E040h - asmword "ANDX" - CALL rDODOES + asmword "ANDX" + CALL rDODOES .word TYPE5DOES,40h,0F000h - asmword "ANDX.A" - CALL rDODOES + asmword "ANDX.A" + CALL rDODOES .word TYPE5DOES,0,0F040h - asmword "ANDX.B" - CALL rDODOES + asmword "ANDX.B" + CALL rDODOES .word TYPE5DOES,40h,0F040h ; -------------------------------------------------------------------------------- @@ -1209,64 +1133,58 @@ TYPE5DOES ; -- BODYDOES ; all numeric arguments must be written as DOUBLE numbers (including a point) : $x.xxxx TYPE6DOES ; -- BODYDOES -; .word LIT,TOIN,FETCH,TOR ; R-- >IN save >IN for 2th pass -; .word FBLANK ; -- BODYDOES ' ' -; .word PRMX1 ; -- BODYDOES Extended_Word -; .word UPDATE_XW ; -- BODYDOES+2 -; .word BRAN,TYPE2DOES ; -- BODYDOES+2 pass 2: completes instruction with opcode = [BODYDOES+2] .word LIT,TOIN,FETCH ; -- BODYDOES >IN - .word FBLANK ; -- BODYDOES >IN ' ' - .word PRMX1 ; -- BODYDOES >IN Extended_Word + .word BL,SkipPrfx,PRMX1 ; -- BODYDOES >IN Extended_Word .word UPDATE_XW ; -- BODYDOES+2 .word BRAN,TYPE2DOES ; -- BODYDOES+2 pass 2: completes instruction with opcode = [BODYDOES+2] asmword "RRCX" ; ZC=0; RRCX Rx,Rx may be repeated by prefix RPT #n|Rn CALL rDODOES .word TYPE6DOES,40h,1000h - asmword "RRCX.A" ; ZC=0; RRCX.A Rx may be repeated by prefix RPT #n|Rn - CALL rDODOES + asmword "RRCX.A" ; ZC=0; RRCX.A Rx may be repeated by prefix RPT #n|Rn + CALL rDODOES .word TYPE6DOES,0,1040h asmword "RRCX.B" ; ZC=0; RRCX.B Rx may be repeated by prefix RPT #n|Rn - CALL rDODOES + CALL rDODOES .word TYPE6DOES,40h,1040h asmword "RRUX" ; ZC=1; RRUX Rx may be repeated by prefix RPT #n|Rn - CALL rDODOES + CALL rDODOES .word TYPE6DOES,140h,1000h - asmword "RRUX.A" ; ZC=1; RRUX.A Rx may be repeated by prefix RPT #n|Rn - CALL rDODOES + asmword "RRUX.A" ; ZC=1; RRUX.A Rx may be repeated by prefix RPT #n|Rn + CALL rDODOES .word TYPE6DOES,100h,1040h - asmword "RRUX.B" ; ZC=1; RRUX.B Rx may be repeated by prefix RPT #n|Rn - CALL rDODOES + asmword "RRUX.B" ; ZC=1; RRUX.B Rx may be repeated by prefix RPT #n|Rn + CALL rDODOES .word TYPE6DOES,140h,1040h asmword "SWPBX" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,40h,1080h asmword "SWPBX.A" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,0,1080h asmword "RRAX" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,40h,1100h asmword "RRAX.A" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,0,1140h asmword "RRAX.B" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,40h,1140h asmword "SXTX" CALL rDODOES .word TYPE6DOES,40h,1180h - asmword "SXTX.A" - CALL rDODOES + asmword "SXTX.A" + CALL rDODOES .word TYPE6DOES,0,1180h - asmword "PUSHX" - CALL rDODOES + asmword "PUSHX" + CALL rDODOES .word TYPE6DOES,40h,1200h asmword "PUSHX.A" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,0,1240h asmword "PUSHX.B" - CALL rDODOES + CALL rDODOES .word TYPE6DOES,40h,1240h ; ---------------------------------------------------------------------- @@ -1277,16 +1195,12 @@ TYPE6DOES ; -- BODYDOES RPT_WORD .word 0 - asmword "RPT" ; RPT #n | RPT Rn repeat n | [Rn]+1 times modulo 16 - mdocol - .word FBLANK,SKIP - .word $+2 ; -- addr - MOV @TOS,X ; X=char - MOV.B #' ',TOS ; -- ' ' as separator - CMP.B #'R',X - JNZ RPT1 - CALL #SearchREG ; -- Rn - JZ RPT1 ; if not found + asmword "RPT" ; RPT #n | RPT Rn repeat n | [Rn] times modulo 16 + mDOCOL + .word BL,SkipPrfx ; -- sep + mNEXTADR ; + JNZ RPT1 ; -- sep if prefix <> 'R' + CALL #SearchRn ; -- Rn BIS #80h,TOS ; -- $008R R=Rn JMP RPT2 RPT1 CALL #SearchARG ; -- $xxxx @@ -1294,5 +1208,5 @@ RPT1 CALL #SearchARG ; -- $xxxx AND #0Fh,TOS ; -- $000x RPT2 MOV TOS,&RPT_WORD MOV @PSP+,TOS - MOV @RSP+,IP + MOV @RSP+,IP MOV @IP+,PC diff --git a/forthMSP430FR_SD_ACCEPT.asm b/forthMSP430FR_SD_ACCEPT.asm index 24091b7..03f01f8 100644 --- a/forthMSP430FR_SD_ACCEPT.asm +++ b/forthMSP430FR_SD_ACCEPT.asm @@ -5,72 +5,75 @@ ; defered word ACCEPT is redirected here by the word LOAD" ; "defered" word CIB is redirected to SDIB (PAD if RAM<2k) by the word LOAD" ; sequentially move an input line ended by CRLF from SD_BUF to PAD -; if end of SD_BUF is reached before CRLF, asks Read_HandledFile to refill buffer with next sector -; then load the end of the line to PAD ptr. +; if end of SD_BUF is reached before CRLF, asks Read_File to refill buffer with next sector +; then load the end of the line to SDIB_ptr. +; when the last buffer is loaded, the handle is automaticaly closed ; when all LOAD"ed files are read, redirects defered word ACCEPT to default ACCEPT and restore interpret pointers. -; see CloseHandleT. +; see CloseHandle. ; used variables : BufferPtr, BufferLen - -; ----------------------------------; -; FORTHWORD "SD_ACCEPT" ; CIB CIB CPL -- CIB len -; ----------------------------------; +; EMIT uses only IP TOS and Y registers +; ==================================; +; FORTHWORD "SD_ACCEPT" ; SDIB_org SDIB_org CPL -- SDIB len 94 bytes +; ==================================; SD_ACCEPT ; sequentially move from SD_BUF to SDIB (PAD if RAM=1k) a line of chars delimited by CRLF ; ----------------------------------; up to CPL = 80 chars - PUSH IP ; - MOV #SDA_YEMIT_RET,IP ; set YEMIT return + PUSH IP ; + MOV #SDA_YEMIT_RET,IP ; set YEMIT return ; ----------------------------------; -StartNewLine ; -- CIB CIB CPL +StartNewLine ; -- SDIB_org SDIB_org CPL ; ----------------------------------; - MOV &CurrentHdl,T ; prepare a link for the next LOADed file, if any... - MOV &BufferPtr,HDLW_BUFofst(T) ; ...see usage : GetFreeHandle(CheckCaseOfLoadFileToken) + MOV &CurrentHdl,T ; prepare a link for a next LOADed file, if any... + MOV &BufferPtr,HDLW_BUFofst(T) ; ...see usage : GetFreeHandle(CheckCaseOfLoadFileToken) ; ----------------------------------; - MOV @PSP+,W ; -- CIB CPL W=dst_ptr - MOV TOS,X ; X=dst_len - MOV #0,TOS ; -- CIB cnt +SDA_InitDstAddr ; ; ----------------------------------; -SDA_InitSrcAddr ; <== SDA_GetFileNextSector + MOV @PSP+,W ; -- SDIB_org CPL W=SDIB_ptr + MOV TOS,X ; X=SDIB_len + MOV #0,TOS ; -- SDIB_org len of moved bytes from SD_buf to SDIB ; ----------------------------------; - MOV &BufferPtr,S ; S=src_ptr - MOV &BufferLen,T ; T=src_len - JMP SDA_ComputeChar ; +SDA_InitSrcAddr ; <== SDA_GetFileNextSect +; ----------------------------------; + MOV &BufferPtr,S ; S=SD_buf_ptr + MOV &BufferLen,T ; T=SD_buf_len + JMP SDA_ComputeChar ; ; ----------------------------------; SDA_YEMIT_RET ; ; ----------------------------------; - .word $+2 ; - SUB #2,IP ; 1 restore YEMIT return + mNEXTADR ; + SUB #2,IP ; 1 restore YEMIT return ; ----------------------------------; -SDA_ComputeChar ; -- CIB cnt +SDA_ComputeChar ; -- SDIB_org len ; ----------------------------------; - CMP T,S ; 1 src_ptr >= src_len ? - JC SDA_GetFileNextSector ; 2 yes - MOV.B SD_BUF(S),Y ; 3 Y = char - ADD #1,S ; 1 increment input BufferPtr - CMP.B #32,Y ; 2 ascii printable char ? - JC SDA_MoveChar ; 2 yes - CMP.B #10,Y ; 2 control char = 'LF' ? - JNZ SDA_ComputeChar ; 2 no + CMP T,S ; 1 SD_buf_ptr >= SD_buf_len ? + JC SDA_GetFileNextSect ; 2 if yes + MOV.B SD_BUF(S),Y ; 3 Y = char + ADD #1,S ; 1 increment SD_buf_ptr + CMP.B #32,Y ; 2 ascii printable char ? + JC SDA_MoveChar ; 2 yes + CMP.B #10,Y ; 2 control char = 'LF' ? + JNZ SDA_ComputeChar ; 2 no, loop back ; ----------------------------------; -SDA_EndOfLine ; -- org cnt +SDA_EndOfLine ; -- SDIB_org len ; ----------------------------------; - MOV @RSP+,IP ; - MOV S,&BufferPtr ; yes save BufferPtr for next line - MOV #32,S ; S = BL - JMP ACCEPT_EOL ; ==> output + MOV S,&BufferPtr ; yes save SD_buf_ptr for next line + MOV @RSP+,IP ; + MOV #32,S ; S = BL + JMP ACCEPT_EOL ; -- SDIB_org len ==> output ; ----------------------------------; SDA_MoveChar ; ; ----------------------------------; - CMP X,TOS ; 1 cnt = dst_len ? - JZ YEMIT ; 2 yes, don't move char to dst - MOV.B Y,0(W) ; 3 move char to dst - ADD #1,W ; 1 increment dst addr - ADD #1,TOS ; 1 increment count of moved chars - JMP YEMIT ; 9/6~ send echo to terminal if ECHO, do nothing if NOECHO -; ----------------------------------; 29/26~ char loop, add 14~ for readsectorW ==> 43/40~ ==> 186/200 kbytes/s @ 8MHz -SDA_GetFileNextSector ; CIB cnt -- -; ----------------------------------; - PUSHM #2,W ; save dst_ptr, dst_len - CALL #Read_File ; that resets BufferPtr - POPM #2,W ; restore dst_ptr, dst_len - JMP SDA_InitSrcAddr ; loopback to end the line + CMP X,TOS ; 1 len = CPL ? + JZ YEMIT ; 2 yes, don't move char to dst + MOV.B Y,0(W) ; 3 move char to dst + ADD #1,W ; 1 increment SDIB_ptr + ADD #1,TOS ; 1 increment len of moved chars + JMP YEMIT ; 9/6~ send echo to terminal if ECHO, do nothing if NOECHO +; ----------------------------------; 29/26~ char loop, add 14~ for readsectorW one char ==> 43/40~ ==> 186/200 kbytes/s @ 8MHz +SDA_GetFileNextSect ; -- SDIB_org len +; ----------------------------------; + PUSHM #2,W ; save SD_buf_ptr, SD_buf_len + CALL #Read_File ; that resets BufferPtr + POPM #2,W ; restore SD_buf_ptr, SD_buf_len + JMP SDA_InitSrcAddr ; loopback to end the line ; ----------------------------------; \ No newline at end of file diff --git a/forthMSP430FR_SD_INIT.asm b/forthMSP430FR_SD_INIT.asm index ccde9da..6dae5fb 100644 --- a/forthMSP430FR_SD_INIT.asm +++ b/forthMSP430FR_SD_INIT.asm @@ -30,7 +30,7 @@ ; First sector of physical drive (sector 0) content : ; --------------------------------------------------- ; dec@| HEX@ -; 446 |0x1BE : partition table first record ==> logical drive 0 +; 446 |0x1BE : partition table first record ==> logical drive 0 ; 462 |0x1CE : partition table 2th record ==> logical drive 1 ; 478 |0x1DE : partition table 3th record ==> logical drive 2 ; 494 |0x1EE : partition table 4th record ==> logical drive 3 @@ -81,7 +81,7 @@ ; First sector of physical drive (sector 0) content : ; --------------------------------------------------- ; dec@| HEX@ -; 446 |0x1BE : partition table first record ==> logical drive 0 +; 446 |0x1BE : partition table first record ==> logical drive 0 ; 462 |0x1CE : partition table 2th record ==> logical drive 1 ; 478 |0x1DE : partition table 3th record ==> logical drive 2 ; 494 |0x1EE : partition table 4th record ==> logical drive 3 @@ -91,7 +91,7 @@ ; 450 |0x1C2 = 0x0C : type FAT32 using LBA addressing ; 454 |0x1C6 = 00 20 00 00 : FirstSector (of logical drive 0) = BS_FirstSector = 8192 -; +; ; FirstSector of logical block (sector 0) content : ; ------------------------------------------------- ; dec@| HEX@ = HEX decimal @@ -103,13 +103,13 @@ ; 32 | 0x20 = 00 C0 EC 00 : BPB_TotSec32 BPB_TotSec32 = 15515648 ; 36 | 0x24 = 30 3B 00 00 : BPB_FATSz32 BPB_FATSz32 = 15152 -; 40 | 0x28 = 00 00 : BPB_ExtFlags BPB_ExtFlags +; 40 | 0x28 = 00 00 : BPB_ExtFlags BPB_ExtFlags ; 44 | 0x2C = 02 00 00 00 : BPB_RootClus BPB_RootClus = 2 ; 48 | 0x30 = 01 00 : BPB_FSInfo BPB_FSInfo = 1 ; 50 | 0x33 = 06 00 : BPB_BkBootSec BPB_BkBootSec = 6 ; 82 | 0x52 = "FAT32" : BS_FilSysType BS_FilSysType (not used) -; +; ; all values below are evaluated in logical sectors ; FAT1 = BPB_RsvdSecCnt = 32 ; FAT2 = BPB_RsvdSecCnt + BPB_FATSz32 = 32 + 15152 = 15184 @@ -122,46 +122,49 @@ .restore ; =========================================================== +; WARNING! SD_INIT DRAW BIG CURRENT; IF THE SUPPLY IS TOO WEAK +; THE SD_CARD LOW VOLTAGE THRESHOLD MAY BE REACHED ==> SD_ERROR 8FF ! +; =========================================================== + +; =========================================================== ; Init hardware SD_Card, called by WARM ; =========================================================== + +; web search: "SDA simplified specifications" + ;-----------------------------------; -INI_HARD_SD CALL @PC+ ; link to previous INI_HARD_APP -I_H_S_PFA .word INIT_TERM ; which activates all previous I/O settings and set TOS = RSTIV_MEM. -;-----------------------------------; - CMP #0,TOS ; RSTIV_MEM = WARM ? - JZ INI_SD_END ; no init if RSTIV_MEM = WARM +INIT_HARD_SD CALL @PC+ ; link to previous INI_HARD_APP + .word INIT_TERM ; which activates all previous I/O settings and set TOS = RSTIV_MEM. ;-----------------------------------; BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card module ? - JNZ INI_SD_END ; no + JNZ INIT_HSD_END ; no ;-----------------------------------; MOV #0A981h,&SD_CTLW0 ; UCxxCTL1 = CKPH, MSB, MST, SPI_3, SMCLK + UCSWRST - MOV #FREQUENCY*3,&SD_BRW; UCxxBRW init SPI CLK = 333 kHz ( < 400 kHz) for SD_Card initialisation + MOV #FREQUENCY*3,&SD_BRW; UCxxBRW init SPI CLK = 333 kHz ( <= 400 kHz) for SD_Card initialisation BIS.B #CS_SD,&SD_CSDIR ; SD Chip Select as output high BIS #BUS_SD,&SD_SEL ; Configure pins as SIMO, SOMI & SCK (PxDIR.y are controlled by eUSCI module) BIC #1,&SD_CTLW0 ; release eUSCI from reset ;-----------------------------------; - .IF RAM_LEN < 2048 ; case of MSP430FR57xx : SD datas are in FRAM not initialized by RESET. - MOV #SD_LEN,X ; clear all SD datas + MOV #SD_LEN,X ; clear all SD datas ClearSDdata SUB #2,X ; 1 - MOV #0,SD_ORG(X) ; 3 + MOV #0,SD_ORG(X) ; 3 JNZ ClearSDdata ; 2 - .ENDIF ; ;-----------------------------------; SD_POWER_ON ; ----------------------------------; MOV #8,X ; send 8*8 = 64 clk on SPI CALL #SPI_X_GET ; - BIC.B #CS_SD,&SD_CSOUT ; preset Chip Select output low to switch in SPI one wire mode + BIC.B #CS_SD,&SD_CSOUT ; preset Chip Select output low to switch in SPI mode ; ----------------------------------; -INIT_CMD0 ; after PUC, all SD variables area is 0 filled +INIT_CMD0 ; SD_CMD_FRM+2 is already cleared... ; ----------------------------------; MOV #4,S ; preset error 4R1 for CMD0 - MOV #95h,&SD_CMD_FRM ; $(95 00 00 00 00 00) - MOV #4000h,&SD_CMD_FRM+4 ; $(95 00 00 00 00 40) = CMD0 + MOV #0095h,&SD_CMD_FRM ; $(95 00 00 00 00 00) + MOV #4000h,&SD_CMD_FRM+4 ; $(95 00 00 00 00 40) = CMD0 ; ----------------------------------; SEND_CMD0 ; GO_IDLE_STATE, expected SPI_R1 response = 1 = idle state ; ----------------------------------; - CALL #sendCommandIdleRet ;X send command, see forthMSP430FR_SD_lowLvl.asm + CALL #sendCommandIdleRet ;X send command (does little to big endian conversion), see forthMSP430FR_SD_lowLvl.asm JZ INIT_CMD8 ; if idle state SD_INIT_ERROR ; MOV #SD_CARD_ERROR,PC ; ReturnError = $04R1, case of defectuous card (or insufficient SD_POWER_ON clk) @@ -177,7 +180,7 @@ INIT_CMD8 ; mandatory if SD_Card >= V2.x [11:8]sup ; ----------------------------------; SEND_CMD8 ; SEND_IF_COND; expected R1 response (first byte of SPI R7) = 01h : idle state ; ----------------------------------; - CALL #sendCommandIdleRet ;X time out occurs with SD_Card V1.x (and all MMC_card) + CALL #sendCommandIdleRet ;X time out occurs with SD_Card V1.x (and all MMC_card) ; ----------------------------------; MOV #4,X ; skip end of SD_Card V2.x type R7 response (4 bytes), because useless CALL #SPI_X_GET ;WX @@ -186,7 +189,7 @@ INIT_ACMD41 ; no more CRC needed from here ; ----------------------------------; MOV #1,&SD_CMD_FRM ; $(01 00 ... set stop bit MOV #0,&SD_CMD_FRM+2 ; $(01 00 00 00 ... -; MOV.B #16,Y ; init 16 * ACMD41 repeats (power on fails with SanDisk ultra 8GB "HC I" and Transcend 2GB) +; MOV.B #16,Y ; init 16 * ACMD41 repeats (fails with SanDisk ultra 8GB "HC I" and Transcend 2GB) ; MOV.B #32,Y ; init 32 * ACMD41 repeats ==> ~400ms time out MOV.B #-1,Y ; init 255 * ACMD41 repeats ==> ~3 s time out MOV #8,S ; preset error 8R1 for ACMD41 @@ -210,7 +213,7 @@ setBLockLength ; set block = 512 bytes (buffer size), usefu ADD S,S ; preset error $10 for CMD16 SEND_CMD16 ; CMD16 = SET_BLOCKLEN MOV #02h,&SD_CMD_FRM+2 ; $(01 00 02 00 ...) - MOV #5000h,&SD_CMD_FRM+4 ; $(01 00 02 00 00 50) + MOV #5000h,&SD_CMD_FRM+4 ; $(01 00 02 00 00 50) CALL #WaitIdleBeforeSendCMD ; wait until idle then send CMD16 JNZ SD_INIT_ERROR ; if W = R1 <> 0, ReturnError = $20R1 ; send command ko ; ----------------------------------; W = R1 = 0 @@ -220,84 +223,70 @@ SwitchSPIhighSpeed ; end of SD init ==> SD_CLK = SMCLK MOV #0,&SD_BRW ; UCxxBRW = 0 ==> SPI_CLK = MCLK BIC #1,&SD_CTLW0 ; release from reset ; ----------------------------------; -Read_EBP_FirstSector ; W=0, BS_FirstSectorHL=0 +Read_EBP_FirstSector ; BS_FirstSectorHL=0 ; ----------------------------------; + MOV #0,W ; MOV #0,X ; - CALL #readSectorWX ; read physical first sector + CALL #readSectorWX ; read physical first sector, W=0 MOV #SD_BUF,Y ; - MOV 454(Y),&BS_FirstSectorL ; so, sectors become logical - MOV 456(Y),&BS_FirstSectorH ; - MOV.B 450(Y),W ; W = partition ID + MOV 454(Y),&BS_FirstSectorL ; so, from here, sectors become logical + MOV 456(Y),&BS_FirstSectorH ; + MOV.B 450(Y),S ; S = partition ID ; ----------------------------------; TestPartitionID ; ; ----------------------------------; - MOV #1,&FATtype ; preset FAT16 -FAT16_CHS_LBA_Test ; - SUB.B #6,W ; ID=06h Partition FAT16 > 32MB using CHS & LBA ? - JZ Read_MBR_FirstSector ; W = 0 -FAT16_LBA_Test ; - SUB.B #8,W ; ID=0Eh Partition FAT16 using LBA ? - JZ Read_MBR_FirstSector ; W = 0 + SUB.B #0Ch,S ; ID=0Ch Partition FAT32 using LBA ? + JZ Read_MBR_FirstSector ; + ADD.B #1,S ; ID=0Bh Partition FAT32 using CHS & LBA ? + JZ Read_MBR_FirstSector ; + ADD.B #4,S ; ID=07h assigned to FAT 32 by MiniTools Partition Wizard.... + JZ Read_MBR_FirstSector ; + ADD #02007h,S ; set ReturnError = $20 & restore ID value + MOV #SD_CARD_ID_ERROR,PC ; see: https://en.wikipedia.org/wiki/Partition_type ; ----------------------------------; - MOV #2,&FATtype ; set FAT32 -FAT32_LBA_Test ; - ADD.B #2,W ; ID=0Ch Partition FAT32 using LBA ? - JZ Read_MBR_FirstSector ; W = 0 -FAT32_CHS_LBA_Test ; - ADD.B #1,W ; ID=0Bh Partition FAT32 using CHS & LBA ? - JZ Read_MBR_FirstSector ; W = 0 - ADD.B #4,W ; ID=07h assigned to FAT 32 by MiniTools Partition Wizard.... - JZ Read_MBR_FirstSector ; W = 0 - ADD #0200Bh,W ; - MOV W,S ; - MOV #SD_CARD_ID_ERROR,PC ; S = ReturnError = $20xx with xx = partition ID -; ----------------------------------; see: https://en.wikipedia.org/wiki/Partition_type Read_MBR_FirstSector ; read first logical sector -; ----------------------------------; W = 0 - MOV #0,X ; +; ----------------------------------; + MOV #0,X ; W = 0 CALL #readSectorWX ; ...with the good CMD17 bytes/sectors frame ! (good switch FAT16/FAT32) ; ----------------------------------; FATxx_SetFileSystem ; ; ----------------------------------; - MOV.B 13(Y),&SecPerClus ; - MOV 14(Y),X ;3 X = BPB_RsvdSecCnt +; MOV 44(Y),&DIRClusterL ; init DIRcluster as FAT32 RootDIR + MOV #2,&DIRClusterL ; init DIRcluster as FAT32 RootDIR +; ----------------------------------; + MOV 14(Y),X ;3 X = BPB_RsvdSecCnt (05FEh=1534) MOV X,&OrgFAT1 ;3 set OrgFAT1 - MOV 22(Y),W ; W = BPB_FATsize - CMP #0,W ; BPB_FATsize <> 0 ? - JNZ Set_FATsize ; yes - MOV 36(Y),W ; W = BPB_FATSz32 -Set_FATsize ; - MOV W,&FATSize ; limited to 16384 sectors.... +; ----------------------------------; + MOV 36(Y),W ; no set W = BPB_FATSz32 (1D01h=7425) + MOV W,&FATSize ; limited to 32767 sectors.... +; ----------------------------------; ADD W,X ; - MOV X,&OrgFAT2 ; X = OrgFAT1 + FATsize = OrgFAT2 - ADD W,X ; X = OrgFAT2 + FATsize = FAT16 OrgRootDir | FAT32 OrgDatas - CMP #2,&FATtype ; FAT32? - JZ FATxx_SetFileSystemNext ; yes -FAT16_SetRootCluster ; - MOV X,&OrgRootDIR ; only FAT16 use, is a sector used by ComputeClusFrstSect - ADD #32,X ; OrgRootDir + RootDirSize = OrgDatas + MOV X,&OrgFAT2 ; X = OrgFAT1 + FATsize = OrgFAT2 (8959) +; ----------------------------------; + ADD W,X ; X = OrgFAT2 + FATsize = FAT32 OrgDatas = OrgRootDIR sector = 16384 +; MOV X,&OrgRootDIR ; FATxx_SetFileSystemNext ; - SUB &SecPerClus,X ; OrgDatas - SecPerClus*2 = OrgClusters - SUB &SecPerClus,X ; no borrow expected + MOV.B 13(Y),Y ; Logical sectors per cluster (8) + MOV Y,&SecPerClus ; + SUB Y,X ; OrgDatas - SecPerClus*2 = OrgClusters + SUB Y,X ; no borrow expected MOV X,&OrgClusters ; X = virtual cluster 0 address (clusters 0 and 1 don't exist) - MOV &FATtype,&DIRClusterL ; init DIRcluster as RootDIR -INI_SD_END ; - MOV @RSP+,PC ; RET +INIT_HSD_END ; + MOV @RSP+,PC ; RET ;-----------------------------------; ; =========================================================== -; Init SD_Card software, called by ?ABORT|RST +; Init SD_Card software, called by INIT_FORTH ; =========================================================== -;-----------------------------------; -INI_SOFT_SD ; called by INI_FORTH common part of ?ABORT|RST ;-----------------------------------; - CALL @PC+ ; link to previous INI_FORTH_APP -RSAB_SD_PFA .word RET_ADR ; which does nothing +INIT_SOFT_SD ; called by INI_FORTH common part of ?ABORT|RST ;-----------------------------------; - MOV #HandlesLen,X ; clear all handles -ClearHandle SUB #2,X ; 1 - MOV #0,FirstHandle(X) ; 3 - JNZ ClearHandle ; 2 +; CMP #0,TOS ; USERSYS = 0 ? +; JZ INIT_HSD_END ; no hardware init if USERSYS = 0 SYS +; MOV #HandlesLen,X ; clear all handles +;ClearHandle SUB #2,X ; 1 +; MOV #0,FirstHandle(X) ; 3 +; JNZ ClearHandle ; 2 MOV #0,&CurrentHdl ; - MOV @RSP+,PC ; RET + MOV #INIT_SOFT_TERM,PC ; link to previous INI_SOFT_APP then RET ;-----------------------------------; diff --git a/forthMSP430FR_SD_LOAD.asm b/forthMSP430FR_SD_LOAD.asm index 479cc98..2de23a0 100644 --- a/forthMSP430FR_SD_LOAD.asm +++ b/forthMSP430FR_SD_LOAD.asm @@ -1,15 +1,22 @@ ; -*- coding: utf-8 -*- ; forthMSP430FR_SD_LOAD.asm -;Z SD_ACCEPT addr addr len -- addr' len' get line to interpret from a SD Card file -; no interrupt allowed -; defered word ACCEPT is redirected here by the word LOAD" -; "defered" word CIB is redirected to SDIB (PAD if RAM<2k) by the word LOAD" -; sequentially move an input line ended by CRLF from SD_BUF to PAD -; if end of SD_BUF is reached before CRLF, asks Read_HandledFile to refill buffer with next sector -; then load the end of the line to PAD ptr. -; when all LOAD"ed files are read, redirects defered word ACCEPT to default ACCEPT and restore interpret pointers. -; see CloseHandleT. +; Tested with MSP-EXP430FR5994 launchpad +; Copyright (C) <2019> <J.M. THOORENS> +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see <http://www.gnu.org/licenses/>. + ; used variables : BufferPtr, BufferLen @@ -17,59 +24,52 @@ ; SD card OPEN, LOAD subroutines ;----------------------------------------------------------------------- -; used variables : BufferPtr, BufferLen - ; rules for registers use ; S = error ; T = CurrentHdl, pathname ; W = SectorL, (RTC) TIME ; X = SectorH, (RTC) DATE -; Y = BufferPtr, (DIR) EntryOfst, FAToffset +; Y = BufferPtr, (DIR) DIREntryOfst -; ----------------------------------; -HDLCurClusToFAT1sectWofstY ;WXY Input: T=currentHandle, Output: W=FATsector, Y=FAToffset, Cluster=HDL_CurCluster -; ----------------------------------; +; ==================================; +HDLcurClus2FATsecWofstY ;WXY Input: T=Handle, HDL_CurClustHL Output: ClusterHL, FATsector, W = FATsector, Y = FAToffset +; ==================================; MOV HDLL_CurClust(T),&ClusterL ; MOV HDLH_CurClust(T),&ClusterH ; -; ----------------------------------; -ClusterToFAT1sectWofstY ;WXY Input : Cluster ; Output: W = FATsector, Y = FAToffset -; ----------------------------------; +; ==================================; +ClusterHLtoFAT1sectWofstY ;WXY Input : ClusterHL Output: ClusterHL, FATsector, W = FATsector, Y = FAToffset +; ==================================; MOV.B &ClusterL+1,W ;3 W = ClusterLoHI - MOV.B &ClusterL,Y ;3 Y = ClusterLoLo - CMP #1,&FATtype ;3 FAT16? - JZ CTF1S_end ;2 yes - + MOV.B &ClusterL,Y ;3 Y = ClusterLOlo ; input : Cluster n, max = 7FFFFF (SDcard up to 256 GB) ; ClusterLoLo*4 = displacement in 512 bytes sector ==> FAToffset ; ClusterHiLo&ClusterLoHi +C << 1 = relative FATsector + orgFAT1 ==> FATsector ; ----------------------------------; - MOV.B &ClusterH,X ; X = 0:ClusterHiLo - SWPB X ; X = ClusterHiLo:0 - ADD X,W ; W = ClusterHiLo:ClusterLoHi + MOV.B &ClusterH,X ; X = 0:ClusterHIlo + SWPB X ; X = ClusterHIlo:0 + BIS X,W ; W = ClusterHIlo:ClusterLOhi ; ----------------------------------; - SWPB Y ; Y = ClusterLoLo:0 - ADD Y,Y ;1 Y = ClusterLoLo:0 << 1 + carry for FATsector - ADDC W,W ; W = ClusterHiLo:ClusterLoHi << 1 = ClusterHiLo:ClusterL / 128 - SWPB Y -CTF1S_end - ADD Y,Y ; Y = 0:ClusterLoLo << 1 + SWPB Y ; Y = ClusterLOlo:0 + ADD Y,Y ;1 Y = ClusterLOlo:0 << 1 (+ carry for FATsector) + ADDC W,W ; FATsector = W = ClusterHIlo:ClusterLOhi<<1 + Carry + SWPB Y ; Y = 0:ClusterLOlo + ADD Y,Y ; FAToffset = Y = 0:ClusterLOlo << 1 for FAT16 and 0:ClusterLOlo<<2 for FAT32 MOV @RSP+,PC ;4 ; ----------------------------------; +; ==================================; +ReadFAT1SectorW ;SWX (< 65536) +; ==================================; + ADD &OrgFAT1,W ; + MOV #0,X ; FAT1_SectorHI = 0 + JMP ReadSectorWX ;SWX read FAT1SectorW +; ----------------------------------; ; use no registers -; ----------------------------------; Input : Cluster, output: Sector = Cluster_first_sector -ComputeClusFrstSect ; If Cluster = 1 ==> RootDirectory ==> SectorL = OrgRootDir -; ----------------------------------; Output: SectorL of Cluster - MOV #0,&SectorH ; - MOV &OrgRootDir,&SectorL ; - CMP.B #0,&ClusterH ; clusterH <> 0 ? - JNE CCFS_AllOthers ; yes - CMP #1,&ClusterL ; clusterHL = 1 ? (FAT16 specificity) - JZ CCFS_RET ; yes, sectorL for FAT16 OrgRootDIR is done -CCFS_AllOthers ; -; ----------------------------------; +; ==================================; +ClusterHLtoFrstSectorHL ; Input : ClusterHL, output: first SectorHL of ClusterHL +; ==================================; .IFDEF MPY ; general case ; ----------------------------------; MOV &ClusterL,&MPY32L ;3 @@ -107,89 +107,20 @@ CCFS_RET ; ; ----------------------------------; -; ----------------------------------; -ComputeHDLcurrentSector ; input: currentHandle, output: Cluster, Sector -; ----------------------------------; - MOV HDLL_CurClust(T),&ClusterL ; - MOV HDLH_CurClust(T),&ClusterH ; - CALL #ComputeClusFrstSect ; - MOV.B HDLB_ClustOfst(T),W ; - ADD W,&SectorL ; - ADDC #0,&SectorH ; - MOV @RSP+,PC ; -; ----------------------------------; - -; ----------------------------------; input : X = countdown_of_spaces, Y = name pointer in buffer -ParseEntryNameSpaces ;XY -; ----------------------------------; output: Z flag, Y is set after the last space char - CMP #0,X ; - JZ PENSL_END ; -; ----------------------------------; -ParseEntryNameSpacesLoop ; -; ----------------------------------; - CMP.B #32,SD_BUF(Y) ; SPACE ? - JNZ PENSL_END ; no: RET - ADD #1,Y ; - SUB #1,X ; - JNZ ParseEntryNameSpacesLoop; -PENSL_END ; - MOV @RSP+,PC ; -; ----------------------------------; - - -; sequentially load in SD_BUF bytsPerSec bytes of a file opened as read or as load -; if new bufferLen have a size <= BufferPtr, closes the file then RET. -; if previous bufferLen had a size < bytsPerSec, closes the file and reloads previous LOADed file if exist. -; HDLL_CurSize leaves the not yet read size -; All used registers must be initialized. ; ==================================; -Read_File ; <== SD_ACCEPT, READ +HDLCurClusPlsOfst2sectorHL ;SWX input: HDL (CurClust, ClustOfst) output: SectorHL ; ==================================; - MOV &CurrentHdl,T ; - MOV #0,&BufferPtr ; reset BufferPtr (the buffer is already read) -; ----------------------------------; - CMP #bytsPerSec,&BufferLen ; - JNZ CloseHandleT ; because this last and incomplete sector is already read - SUB #bytsPerSec,HDLL_CurSize(T) ; HDLL_CurSize is decremented of one sector lenght - SUBC #0,HDLH_CurSize(T) ; - ADD.B #1,HDLB_ClustOfst(T) ; current cluster offset is incremented - CMP.B &SecPerClus,HDLB_ClustOfst(T) ; Cluster Bound reached ? - JNC SetBufLenAndLoadCurSector ; no -; ----------------------------------; -;SearchNextCluster ; yes -; ----------------------------------; - MOV.B #0,HDLB_ClustOfst(T) ; reset Current_Cluster sectors offset - CALL #HDLCurClusToFAT1sectWofstY;WXY Output: W=FATsector, Y=FAToffset, Cluster=HDL_CurCluster - ADD &OrgFAT1,W ; - MOV #0,X ; - CALL #ReadSectorWX ;SWX (< 65536) - MOV #0,HDLH_CurClust(T) ; - MOV SD_BUF(Y),HDLL_CurClust(T) ; - CMP #1,&FATtype ; FAT16? - JZ SetBufLenAndLoadCurSector ; - MOV SD_BUF+2(Y),HDLH_CurClust(T); -; ==================================; -SetBufLenAndLoadCurSector ;WXY <== previous handle reLOAD with BufferPtr<>0 -; ==================================; - MOV #bytsPerSec,&BufferLen ; preset BufferLen - CMP #0,HDLH_CurSize(T) ; CurSize > 65535 ? - JNZ LoadHDLcurrentSector ; yes - CMP HDLL_CurSize(T),&BufferPtr ; BufferPtr >= CurSize ? (BufferPtr = 0 or see RestorePreviousLoadedBuffer) - JC CloseHandleT ; yes - CMP #bytsPerSec,HDLL_CurSize(T) ; CurSize >= 512 ? - JC LoadHDLcurrentSector ; yes - MOV HDLL_CurSize(T),&BufferLen ; no: adjust BufferLen -; ==================================; -LoadHDLcurrentSector ; <=== OPEN_WRITE_APPEND -; ==================================; - CALL #ComputeHDLcurrentSector ; use no registers + MOV HDLL_CurClust(T),&ClusterL ; + MOV HDLH_CurClust(T),&ClusterH ; ; ==================================; -ReadSector ; +ClusterHL2sectorHL ;W input: ClusterHL, ClustOfst output: SectorHL ; ==================================; - MOV &SectorL,W ; Low - MOV &SectorH,X ; High - JMP ReadSectorWX ; SWX then RET + CALL #ClusterHLtoFrstSectorHL ; + MOV.B HDLB_ClustOfst(T),W ; byte to word conversion + ADD W,&SectorL ; + ADDC #0,&SectorH ; + MOV @RSP+,PC ; ; ----------------------------------; @@ -197,33 +128,32 @@ ReadSector ; ; if other open_load token, decrement token, save previous context ; OPEN subroutine -; Input : EntryOfst, Cluster = EntryOfst(HDLL_FirstClus()) +; Input : DIREntryOfst, Cluster = DIREntryOfst(HDLL_FirstClus()) ; init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus,HDLL_CurClust,HDLL_CurSize) ; Output: Cluster = first Cluster of file, X = CurrentHdl -; ----------------------------------; input : Cluster, EntryOfst +; ==================================; input : Cluster, DIREntryOfst GetFreeHandle ;STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize) -; ----------------------------------; output : T = new CurrentHdl +; ==================================; output : T = new CurrentHdl MOV #8,S ; prepare file already open error MOV #FirstHandle,T ; MOV #0,X ; X = init previous handle as 0 ; ----------------------------------; SearchHandleLoop ; ; ----------------------------------; - CMP.B #0,HDLB_Token(T) ; free handle ? - JZ FreeHandleFound ; yes + CMP.B #0,HDLB_Token(T) ; free handle ? + JZ FreeHandleFound ; yes AlreadyOpenTest ; no CMP &ClusterH,HDLH_FirstClus(T); JNE SearchNextHandle ; CMP &ClusterL,HDLL_FirstClus(T); - JZ InitHandleRET ; error 8: Already Open abort ===> + JZ OPEN_Error ; error 8: Already Open abort ===> SearchNextHandle ; MOV T,X ; handle is occupied, keep it in X as previous handle ADD #HandleLenght,T ; CMP #HandleEnd,T ; JNZ SearchHandleLoop ; - ADD S,S ; 16 = no more handle error, abort ===> -InitHandleRET ; - MOV @RSP+,PC ; + ADD S,S ; + JMP OPEN_Error ; error 16 = no more handle error, abort ===> ; ----------------------------------; FreeHandleFound ; T = new handle, X = previous handle ; ----------------------------------; @@ -247,45 +177,101 @@ CheckCaseOfLoadFileToken ; ; ----------------------------------; InitHandle ; ; ----------------------------------; - MOV.B W,HDLB_Token(T) ; marks handle as open type: <0=LOAD, 1=READ, 2=WRITE, 4=DEL + MOV.B W,HDLB_Token(T) ; marks handle as open type: <0=LOAD, 1=READ, 2=DEL, 4=WRITE, 8=APPEND MOV.B #0,HDLB_ClustOfst(T) ; clear ClustOfst MOV &SectorL,HDLL_DIRsect(T); init handle DIRsectorL - MOV &SectorH,HDLH_DIRsect(T); - MOV &EntryOfst,Y ; + MOV &SectorH,HDLH_DIRsect(T); + MOV &DIREntryOfst,Y ; MOV Y,HDLW_DIRofst(T) ; init handle SD_BUF offset of DIR entry MOV SD_BUF+26(Y),HDLL_FirstClus(T); init handle firstcluster of file (to identify file) - MOV SD_BUF+20(Y),HDLH_FirstClus(T) - MOV SD_BUF+26(Y),HDLL_CurClust(T) ; init handle CurrentCluster - MOV SD_BUF+20(Y),HDLH_CurClust(T) + MOV SD_BUF+20(Y),HDLH_FirstClus(T); = 0 if new DIRentry (create write file) + MOV SD_BUF+26(Y),HDLL_CurClust(T); init handle CurrentCluster + MOV SD_BUF+20(Y),HDLH_CurClust(T); = 0 if new DIRentry (create write file) MOV SD_BUF+28(Y),HDLL_CurSize(T); init handle LOW currentSizeL - MOV SD_BUF+30(Y),HDLH_CurSize(T); + MOV SD_BUF+30(Y),HDLH_CurSize(T); = 0 if new DIRentry (create write file) MOV #0,&BufferPtr ; reset BufferPtr all type of files - CMP.B #2,W ; is a WRITE file handle? - JZ ComputeHDLcurrentSector ; = 2, is a WRITE file - JGE InitHandleRET ; > 2, is a file to be deleted - MOV #0,HDLW_BUFofst(T) ; < 2, is a READ or a LOAD file + CMP.B #2,W ; del file request (2) ? + JZ InitHandleRET ; + JGE HDLCurClusPlsOfst2sectorHL ; set ClusterHL and SectorHL for all WRITE requests +; ----------------------------------; + MOV #0,HDLW_BUFofst(T) ; < 2, is a READ or a LOAD request CMP.B #-1,W ; JZ ReplaceInputBuffer ; case of first loaded file JL SaveBufferContext ; case of other loaded file - JMP SetBufLenAndLoadCurSector ; case of READ file + JMP SetBufLenLoadCurSector ; case of READ file ; ----------------------------------; ReplaceInputBuffer ; ; ----------------------------------; - MOV #SDIB_ORG,&CIB_ADR ; set SD Input Buffer as Current Input Buffer before return to QUIT + MOV #SDIB_ORG,&CIB_ORG ; set SD Input Buffer as Current Input Buffer before return to QUIT MOV #SD_ACCEPT,&PFAACCEPT ; redirect ACCEPT to SD_ACCEPT before return to QUIT ; ----------------------------------; -SaveBufferContext ; (see CloseHandleT) +SaveBufferContext ; (see CloseHandle) ; ----------------------------------; MOV &SOURCE_LEN,HDLW_PrevLEN(T) ; = CPL SUB &TOIN,HDLW_PrevLEN(T) ; PREVLEN = CPL - >IN MOV &SOURCE_ORG,HDLW_PrevORG(T) ; = CIB ADD &TOIN,HDLW_PrevORG(T) ; PrevORG = CIB + >IN - JMP SetBufLenAndLoadCurSector ; then RET + JMP SetBufLenLoadCurSector ; then RET +; ----------------------------------; +InitHandleRET ; +; ----------------------------------; + MOV @RSP+,PC ; ; ----------------------------------; +; sequentially load in SD_BUF bytsPerSec bytes of a file opened as read or as load +; if new bufferLen have a size <= BufferPtr, closes the file then RET. +; if previous bufferLen had a size < bytsPerSec, closes the file and reloads previous LOADed file if exist. +; HDLL_CurSize leaves the not yet read size +; All used registers must be initialized. +; ==================================; +Read_File ; <== SD_ACCEPT, READ +; ==================================; + MOV &CurrentHdl,T ; + MOV #0,&BufferPtr ; reset BufferPtr (the buffer is already read) ; ----------------------------------; -CloseHandleHere ; + CMP #bytsPerSec,&BufferLen ; + JNZ CloseHandle ; because this last and incomplete sector is already read + SUB #bytsPerSec,HDLL_CurSize(T) ; HDLL_CurSize is decremented of one sector lenght + SUBC #0,HDLH_CurSize(T) ; + ADD.B #1,HDLB_ClustOfst(T) ; current cluster offset is incremented + CMP.B &SecPerClus,HDLB_ClustOfst(T) ; Cluster Bound reached ? + JNC SetBufLenLoadCurSector ; no +; ----------------------------------; +;SearchNextClusterInFAT1 ; +; ----------------------------------; + MOV.B #0,HDLB_ClustOfst(T) ; reset Current_Cluster sectors offset + CALL #HDLcurClus2FATsecWofstY;WXY Output: FATsector W=FATsector, Y=FAToffset + CALL #ReadFAT1SectorW ;SWX (< 65536) + MOV #0,HDLH_CurClust(T) ; preset HDLH_CurClust(T)=0 for FAT16 + MOV SD_BUF(Y),HDLL_CurClust(T) ; + MOV SD_BUF+2(Y),HDLH_CurClust(T); set HDLH_CurClust(T)=0 for FAT32 +; ==================================; +SetBufLenLoadCurSector ;WXY <== previous handle reLOAD with BufferPtr<>0 +; ==================================; + MOV #bytsPerSec,&BufferLen ; preset BufferLen + CMP #0,HDLH_CurSize(T) ; CurSize > 65535 ? + JNZ LoadCurSectorHL ; yes + CMP HDLL_CurSize(T),&BufferPtr ; BufferPtr >= CurSize ? (BufferPtr = 0 or see RestorePreviousLoadedBuffer) + JC CloseHandle ; yes + CMP #bytsPerSec,HDLL_CurSize(T) ; CurSize >= 512 ? + JC LoadCurSectorHL ; yes + MOV HDLL_CurSize(T),&BufferLen ; no: adjust BufferLen +; ==================================; +LoadCurSectorHL ; +; ==================================; + CALL #HDLCurClusPlsOfst2sectorHL;SWX +; ==================================; +ReadSectorHL ; +; ==================================; + MOV &SectorL,W ; Low + MOV &SectorH,X ; High + JMP ReadSectorWX ; SWX then RET +; ----------------------------------; + + +; ----------------------------------; +CloseHandleT ; ; ----------------------------------; MOV.B #0,HDLB_Token(T) ; release the handle MOV @T,T ; T = previous handle @@ -296,8 +282,8 @@ CloseHandleHere ; RestorePreviousLoadedBuffer ; ; ----------------------------------; MOV HDLW_BUFofst(T),&BufferPtr ; restore previous BufferPtr - CALL #SetBufLenAndLoadCurSector ; then reload previous buffer - BIC #Z,SR ; + CALL #SetBufLenLoadCurSector ; then reload previous buffer + BIC #Z,SR ; ; ----------------------------------; CloseHandleRet ; MOV @RSP+,PC ; Z = 1 if no more handle @@ -305,17 +291,28 @@ CloseHandleRet ; ; ==================================; -CloseHandleT ; <== CLOSE, Read_File, TERM2SD", OPEN_DEL +CloseHandle ; <== CLOSE, Read_File, TERM2SD", OPEN_DEL ; ==================================; MOV &CurrentHdl,T ; CMP #0,T ; no handle? JZ CloseHandleRet ; RET ; ----------------------------------; .IFDEF SD_CARD_READ_WRITE - CMP.B #2,HDLB_Token(T) ; opened as write (updated) file ? - JNZ TestClosedToken ; no - CALL #WriteBuffer ;SWXY - CALL #OPWW_UpdateDirectory ;SWXY + CMP.B #4,HDLB_Token(T) ; WRITE file ? + JNZ TestClosedToken ; no, case of DEL READ LOAD file +;; ----------------------------------; optionnal +; MOV &BufferPtr,W ; +;FullFillZero ;the remainder of sector +; CMP #BytsPerSec,W ;2 buffer full ? +; JZ CloseWriteHandle ;2 remainding of buffer is full filled with 0 +; MOV.B #0,SD_BUF(W) ;3 +; ADD #1,W ;1 +; JMP FullFillZero ;2 +;; ----------------------------------; +WriteBeforeClose + CALL #WriteSD_Buf ;SWX +CloseWriteHandle + CALL #LoadUpdateSaveDirEntry ;SWXY .ENDIF ; ; ----------------------------------; TestClosedToken ; @@ -324,7 +321,7 @@ TestClosedToken ; ; ----------------------------------; CaseOfAnyReadWriteDelFileIsClosed ; token >= 0 ; ----------------------------------; - JGE CloseHandleHere ; then RET + JGE CloseHandleT ; then RET ; ----------------------------------; CaseOfAnyLoadedFileIsClosed ; -- org' len' R-- QUIT3 dst_ptr dst_len SD_ACCEPT ; ----------------------------------; @@ -335,10 +332,10 @@ RestoreSD_ACCEPTContext ; ; ----------------------------------; ReturnOfSD_ACCEPT ; ; ----------------------------------; - ADD #6,RSP ; R-- QUIT4 empties return stack + ADD #6,RSP ; R-- QUIT3 empties return stack MOV @RSP+,IP ; skip return to SD_ACCEPT ; ----------------------------------; - CALL #CloseHandleHere ; Z = 1 if no more handle + CALL #CloseHandleT ; Z = 1 if no more handle ; ----------------------------------; CheckFirstLoadedFileIsClosed ; ; ----------------------------------; @@ -347,12 +344,30 @@ CheckFirstLoadedFileIsClosed ; ; ----------------------------------; RestoreDefaultACCEPT ; if no more handle, first loaded file is closed... ; ----------------------------------; - MOV #TIB_ORG,&CIB_ADR ; restore TIB as Current Input Buffer for next line (next QUIT) + MOV #TIB_ORG,&CIB_ORG ; restore TIB as Current Input Buffer for next line (next QUIT) MOV #BODYACCEPT,&PFAACCEPT ; restore default ACCEPT for next line (next QUIT) MOV #ECHO,PC ; -- org len if return to Terminal ACCEPT ; ----------------------------------; +; ==================================; input : X = countdown_of_spaces, Y = DIRsector_buffer ptr +ParseEntryNameSpaces ;XY +; ==================================; output: Z flag, Y is set after the last space char + CMP #0,X ; + JZ PENSL_END ; +; ----------------------------------; +ParseEntryNameSpacesLoop ; +; ----------------------------------; + CMP.B #32,SD_BUF(Y) ; SPACE ? + JNZ PENSL_END ; no: RET + ADD #1,Y ; + SUB #1,X ; + JNZ ParseEntryNameSpacesLoop; +PENSL_END ; + MOV @RSP+,PC ; +; ----------------------------------; + + .IFDEF SD_CARD_READ_WRITE ;----------------------------------------------------------------------- @@ -375,56 +390,59 @@ RestoreDefaultACCEPT ; if no more handle, first loa ; if pathname is a directory, change current directory. ; if an error is encountered, no handle is set, error message is displayed. -; READ" acts also as CD dos command : +; READ" acts also as CD dos command : ; - READ" a:\misc\" set a:\misc as current directory ; - READ" a:\" reset current directory to root ; - READ" ..\" change to parent directory ; to close all files type : WARM (or COLD, RESET) -; ----------------------------------; +; ==================================; FORTHWORDIMM "READ\34" ; immediate -; ----------------------------------; +; ==================================; READDQ - MOV.B #1,W ; W = OpenType + MOV.B #1,W ; W = READ request JMP Open_File ; ; ----------------------------------; -;Z WRITE" pathame" -- immediate -; open or create the file designed by pathname. -; an error occurs if the file is already opened. -; the last sector of the file is loaded in buffer, and bufferPtr leave the address of the first free byte. -; compile state : compile WRITE" pathname" -; exec state : open or create entry selected by pathname +;Z DEL" pathame" -- immediate +; ==================================; + FORTHWORDIMM "DEL\34" ; immediate +; ==================================; +DELDQ + MOV.B #2,W ; W = DEL request + JMP Open_File ; ; ----------------------------------; + +;Z WRITE" pathame" -- immediate +; if file exist, free all clusters then switch handle to WRITE +; if "no such file", open a write handle +; ==================================; FORTHWORDIMM "WRITE\34" ; immediate -; ----------------------------------; +; ==================================; WRITEDQ - MOV.B #2,W ; W = OpenType + MOV.B #4,W ; W = WRITE request JMP Open_File ; ; ----------------------------------; - -;Z DEL" pathame" -- immediate -; compile state : compile DEL" pathname" -; exec state : DELETE entry selected by pathname - -; ----------------------------------; - FORTHWORDIMM "DEL\34" ; immediate -; ----------------------------------; -DELDQ - MOV.B #4,W ; W = OpenType +;Z APPEND" pathame" -- immediate +; open the file designed by pathname. +; the last sector of the file is loaded in buffer, and bufferPtr leave the address of the first free byte. +; ==================================; + FORTHWORDIMM "APPEND\34" ; immediate +; ==================================; +APPENDQ + MOV.B #8,W ; W = APPEND request JMP Open_File ; ; ----------------------------------; - -;Z CLOSE -- +;Z CLOSE -- ; close current handle -; ----------------------------------; +; ==================================; FORTHWORD "CLOSE" ; -; ----------------------------------; - CALL #CloseHandleT ; - MOV @IP+,PC ; +; ==================================; + CALL #CloseHandle ; + MOV @IP+,PC ; ; ----------------------------------; .ENDIF ; SD_CARD_READ_WRITE @@ -436,20 +454,19 @@ DELDQ ;Z LOAD" pathame" -- immediate ; compile state : compile LOAD" pathname" ; exec state : open a file from SD card via its pathname -; see Open_File primitive for pathname conventions +; see Open_File primitive for pathname conventions ; the opened file becomes the new input stream for INTERPRET ; this command is recursive, limited only by the count of free handles (up to 8) -; LOAD" acts also as dos command "CD" : +; LOAD" acts also as dos command "CD" : ; - LOAD" \misc\" set a:\misc as current directory ; - LOAD" \" reset current directory to root ; - LOAD" ..\" change to parent directory -; ----------------------------------; +; ==================================; FORTHWORDIMM "LOAD\34" ; immediate +; ==================================; + MOV.B #-1,W ; W = LOAD request ; ----------------------------------; - MOV.B #-1,W ; W = OpenType -; ----------------------------------; - ; ====================================================================== ; OPEN FILE primitive @@ -466,12 +483,12 @@ DELDQ ; ...open the file as read and return the handle in CurrentHdl. ; if the pathname is a directory, change current directory, no handle is set. ; if an error is encountered, no handle is set, an error message is displayed. -; ----------------------------------; +; ==================================; Open_File ; -- -; ----------------------------------; +; ==================================; SUB #2,PSP ; MOV TOS,0(PSP) ; - MOV W,TOS ; -- Open_type (0=LOAD", 1=READ", 2=WRITE", 4=DEL") + MOV W,TOS ; -- Open_type (-1=LOAD", 1=READ", 2=DEL", 4=WRITE", 8=APPEND") CMP #0,&STATE ; JZ OPEN_EXEC ; ; ----------------------------------; @@ -484,57 +501,49 @@ OPEN_COMP ; ; ----------------------------------; OPEN_EXEC ; mDOCOL ; if exec state - .word lit,'"',WORDD,COUNT ; -- open_type addr u + .word lit,'"',WORDD,COUNT ; -- open_type addr cnt .word $+2 ; MOV @RSP+,IP ; ; ----------------------------------; -ParenOpen ; -- open_type HERE HERE as pathname ptr +ParenOpen ; -- open_type addr cnt ; ----------------------------------; MOV @PSP+,rDOCON ; rDOCON = addr = pathname PTR ADD rDOCON,TOS ; TOS = EOS (End Of String) = pathname end .IFDEF SD_CARD_READ_WRITE ; - MOV TOS,&EndOfPath ; for WRITE CREATE part + MOV TOS,&PathName_END ; for WRITE CREATE part .ENDIF ; ----------------------------------; -OPN_PathName ; +;OPN_PathName ; ; ----------------------------------; + MOV #2,&ClusterL ; set root DIR cluster + MOV #0,&ClusterH ; MOV #1,S ; error 1 - MOV &DIRClusterL,&ClusterL ; - MOV &DIRclusterH,&ClusterH ; CMP rDOCON,TOS ; PTR = EOS ? (end of pathname ?) - JZ OPN_NoPathName ; yes: error 1 ===> + JZ OPEN_Error ; yes: error 1 ===> ; ----------------------------------; CMP.B #':',1(rDOCON) ; A: B: C: ... in pathname ? JNZ OPN_AntiSlashStartTest ; no ADD #2,rDOCON ; yes : skip drive because not used, only one SD_card ; ----------------------------------; OPN_AntiSlashStartTest ; - CMP.B #'\\',0(rDOCON) ; "\" as first char ? + CMP.B #'\\',0(rDOCON) ; "\" as first char ? JNZ OPN_SearchDirSector ; no ADD #1,rDOCON ; yes : skip '\' char - MOV &FATtype,&ClusterL ; FATtype = 1 as FAT16 RootDIR, FATtype = 2 = FAT32RootDIR - MOV #0,&ClusterH ; ; ----------------------------------; -OPN_EndOfStringTest ; <=== dir found in path +OPN_EndOfStringTest ; ; ----------------------------------; CMP rDOCON,TOS ; PTR = EOS ? (end of pathname ?) - JZ OPN_SetCurrentDIR ; yes + JZ OPN_SetCurrentDIR ; if pathname ptr = end of string ; ----------------------------------; -OPN_SearchDirSector ; +OPN_SearchDirSector ; <=== dir found in path ; ----------------------------------; - MOV rDOCON,&Pathname ; save Pathname ptr - CALL #ComputeClusFrstSect ; output: SectorHL - MOV #32,rDODOES ; preset countdown for FAT16 RootDIR sectors - CMP #2,&FATtype ; FAT32? - JZ OPN_SetDirSectors ; yes - CMP &ClusterL,&FATtype ; FAT16 AND RootDIR ? - JZ OPN_LoadDIRsector ; yes -OPN_SetDirSectors ; - MOV &SecPerClus,rDODOES ; + MOV rDOCON,&PathName_PTR ; save Pathname ptr + CALL #ClusterHLtoFrstSectorHL; output: SectorHL + MOV &SecPerClus,rDODOES ; DIR sectors = one cluster sectors ; ----------------------------------; OPN_LoadDIRsector ; <=== Dir Sector loopback ; ----------------------------------; - CALL #ReadSector ;SWX + CALL #ReadSectorHL ;SWX ; ----------------------------------; MOV #2,S ; prepare no such file error MOV #0,W ; init entries count @@ -544,7 +553,7 @@ OPN_SearchDIRentry ; <=== DIR Entry loopback MOV W,Y ; 1 RLAM #4,Y ; --> * 16 ADD Y,Y ; 1 --> * 2 - MOV Y,&EntryOfst ; EntryOfst points to first free entry + MOV Y,&DIREntryOfst ; DIREntryOfst CMP.B #0,SD_BUF(Y) ; free entry ? (end of entries in DIR) JZ OPN_NoSuchFile ; error 2 NoSuchFile, used by create ===> MOV #8,X ; count of chars in entry name @@ -559,14 +568,15 @@ OPN_CompareName8chars ; ADD #1,rDOCON ; 9th char of Pathname is always a dot ; ----------------------------------; OPN_FirstCharMismatch ; +; ----------------------------------; CMP.B #'.',-1(rDOCON) ; FirstNotEqualChar of Pathname = dot ? JZ OPN_DotFound ; ; ----------------------------------; -OPN_DotNotFound ; +OPN_DotNotFound ; ; ----------------------------------; - ADD #3,X ; for next cases not equal chars of entry until 11 must be spaces + ADD #3,X ; for next cases not equal chars of DIRentry until 11 must be spaces CALL #ParseEntryNameSpaces ; for X + 3 chars - JNZ OPN_DIRentryMismatch ; if a char entry <> space + JNZ OPN_DIRentryMismatch ; if a char entry <> space CMP.B #'\\',-1(rDOCON) ; FirstNotEqualChar of Pathname = "\" ? JZ OPN_EntryFound ; CMP rDOCON,TOS ; EOS exceeded ? @@ -574,9 +584,9 @@ OPN_DotNotFound ; ; ----------------------------------; OPN_DIRentryMismatch ; ; ----------------------------------; - MOV &pathname,rDOCON ; reload Pathname + MOV &PathName_PTR,rDOCON ; reload PathName_PTR as it was at last OPN_SearchDirSector ADD #1,W ; inc entry - CMP #16,W ; 16 entry in a sector + CMP #16,W ; 16 entries in a sector JNZ OPN_SearchDIRentry ; ===> loopback for search next DIR entry ; ----------------------------------; ADD #1,&SectorL ; @@ -585,14 +595,14 @@ OPN_DIRentryMismatch ; JNZ OPN_LoadDIRsector ; ===> loopback for search next DIR sector ; ----------------------------------; MOV #4,S ; - JMP OPN_EndOfDIR ; error 4 ===> + JMP OPEN_Error ; ENd of DIR error 4 ===> ; ----------------------------------; ; ----------------------------------; OPN_DotFound ; not equal chars of entry name until 8 must be spaces ; ----------------------------------; CMP.B #'.',-2(rDOCON) ; LastCharEqual = dot ? - JZ OPN_DIRentryMismatch ; case of first DIR entry = "." and Pathname = "..\" + JZ OPN_DIRentryMismatch ; case of first DIR entry = "." and Pathname = "..\" CALL #ParseEntryNameSpaces ; parse X spaces, X{0,...,7} JNZ OPN_DIRentryMismatch ; if a char entry <> space MOV #3,X ; @@ -607,7 +617,7 @@ OPN_CompareExt3chars ; JMP OPN_EntryFound ; OPN_ExtNotEqualChar ; CMP rDOCON,TOS ; EOS exceeded ? - JC OPN_DIRentryMismatch ; no, loop back + JC OPN_DIRentryMismatch ; no, loop back CMP.B #'\\',-1(rDOCON) ; FirstNotEqualChar = "\" ? JNZ OPN_DIRentryMismatch ; CALL #ParseEntryNameSpaces ; parse X spaces, X{0,...,3} @@ -615,12 +625,12 @@ OPN_ExtNotEqualChar ; ; ----------------------------------; OPN_EntryFound ; Y points on the file attribute (11th byte of entry) ; ----------------------------------; - MOV &EntryOfst,Y ; reload DIRentry + MOV &DIREntryOfst,Y ; reload DIRentry MOV SD_BUF+26(Y),&ClusterL ; first clusterL of file - MOV SD_BUF+20(Y),&ClusterH ; first clusterT of file, always 0 if FAT16 + MOV SD_BUF+20(Y),&ClusterH ; first clusterH of file OPN_EntryFoundNext BIT.B #10h,SD_BUF+11(Y) ; test if Directory or File - JZ OPN_FileFound ; + JZ OPN_FileFound ; is a file ; ----------------------------------; OPN_DIRfound ; entry is a DIRECTORY ; ----------------------------------; @@ -628,29 +638,25 @@ OPN_DIRfound ; entry is a DIRECTORY JNZ OPN_DIRfoundNext ; CMP #0,&ClusterL ; case of ".." entry, when parent directory is root JNZ OPN_DIRfoundNext ; - MOV &FATtype,&ClusterL ; set cluster as RootDIR cluster + MOV #2,&ClusterL ; set cluster as RootDIR cluster OPN_DIRfoundNext ; - CMP rDOCON,TOS ; EOS exceeded ? - JC OPN_EndOfStringTest ; no: (we presume that FirstNotEqualChar = "\") ==> loop back + CMP rDOCON,TOS ; EOS reached ? + JNZ OPN_SearchDirSector ; no: (we presume that FirstNotEqualChar = "\") ==> loop back ; ----------------------------------; -OPN_SetCurrentDIR ; -- open_type ptr +OPN_SetCurrentDIR ; -- open_type ptr PathName_PTR is set on name of this DIR ; ----------------------------------; MOV &ClusterL,&DIRClusterL ; MOV &ClusterH,&DIRclusterH ; - MOV #0,0(PSP) ; -- open_type ptr open_type = 0 + MOV #0,0(PSP) ; -- open_type ptr open_type = 0 JMP OPN_Dir ; ----------------------------------; -OPN_FileFound ; -- open_type ptr +OPN_FileFound ; -- open_type ptr PathName_PTR is set on name of file ; ----------------------------------; - MOV @PSP,W ; + MOV @PSP,W ; CALL #GetFreeHandle ;STWXY init handle(HDLL_DIRsect,HDLW_DIRofst,HDLL_FirstClus = HDLL_CurClust,HDLL_CurSize) ; ----------------------------------; output : T = CurrentHdl*, S = ReturnError, Y = DIRentry offset -OPN_NomoreHandle ; S = error 16 -OPN_alreadyOpen ; S = error 8 -OPN_EndOfDIR ; S = error 4 OPN_NoSuchFile ; S = error 2 -OPN_NoPathName ; S = error 1 -OPN_Dir +OPN_Dir ; MOV #xdodoes,rDODOES ; restore rDODOES MOV #xdocon,rDOCON ; restore rDODOES MOV @PSP+,W ; -- ptr W = open_type @@ -665,7 +671,7 @@ OPN_Dir ; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl ; output: nothing else abort on error ; ====================================================================== - + ; ----------------------------------; OPEN_QDIR ; ; ----------------------------------; @@ -676,15 +682,16 @@ OPEN_QLOAD ; ; ----------------------------------; .IFDEF SD_CARD_READ_WRITE ; CMP.B #-1,W ; open_type = LOAD" - JNZ OPEN_QREAD ; next step + JNZ OPEN_1W ; next step .ENDIF ; ; ----------------------------------; here W is free OPEN_LOAD ; ; ----------------------------------; CMP #0,S ; open file happy end ? JNZ OPEN_Error ; no -OPEN_LOAD_END - MOV @IP+,PC ; +OPEN_LOAD_END ; + MOV #NOECHO,PC ; +; MOV @IP+,PC ; ; ----------------------------------; ; ----------------------------------; @@ -703,43 +710,40 @@ OPEN_Error ; S= error .word BRAN,ABORT_SD ; to insert S error as flag, no return ; ----------------------------------; - .IFDEF BOOTLOADER +; to enable bootstrap: BOOT +; to disable bootstrap: NOBOOT + +; XBOOT [SYSRSTIV|USERSTIV] -- +; here we are after INIT_FORTH +; performs bootstrap from SD_CARD\BOOT.4th file, ready to test SYSRSTIV|USERSYS value +XBOOT ; BIT #1,TOS ; USERSYS request ? + ; JNZ AbortBoot ; + ; CMP #0,TOS ; WARM request ? + ; JZ AbortBoot ; if yes + BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card socket ? + JZ BOOT_YES ; if yes +AbortBoot MOV #WARM,PC ; goto WARM without return +; ----------------------------------; +BOOT_YES CALL &HARD_APP ; CALL HARD_APP (which includes INIT_HARD_SD) + MOV #PSTACK-2,PSP ; preserve SYSRSTIV|USERSYS in TOS for BOOT.4TH tests + MOV #0,0(PSP) ; set 0 for next SYS use + mDOCOL ; + .word XSQUOTE ; -- SYSRSTIV|USERSYS addr u + .byte 15,"LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file... +; .byte 22,"NOECHO LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file... + .word BRAN,QUIT4 ; to interpret this string, then loop back to QUIT +; ----------------------------------; - FORTHWORD "[PFA]" -; [PFA] CFA -- [PFA] ; add source indirection to DEFERSTORE - ADD #2,TOS - MOV @TOS,TOS +; ==================================; + FORTHWORD "BOOT" ; to enable BOOT +; ==================================; + MOV #XBOOT,&PUCNEXT ; inserts XBOOT in PUC chain. MOV @IP+,PC -; to enable bootstrap: ' BOOT IS WARM -; to disable bootstrap: ' BOOT [PFA] IS WARM - - FORTHWORD "BOOT" -; BOOT RSTIV_MEM -- -; performs bootstrap from SD_CARD\BOOT.4th file -BOOT MOV @PC+,X -PFA_BOOT .word INI_HARD_SD ; X = INI_HARD_SD addr, 2(X) = [PFA_X] = previous INI_HARD_APP (INIT_TERM) addr , see forthMSP430FR_SD_INIT.asm - CMP #2,TOS ; RSTIV_MEM <> WARM ? - JC QSD_MEM ; yes - MOV @RSP+,PC ; if RSTIV_MEM U< 2, return to BODYWARM -QSD_MEM BIT.B #CD_SD,&SD_CDIN ; SD_memory in SD_Card socket ? - JZ BOOT_YES ; -NO_BOOT MOV 2(X),PC ; if no, goto previous INIT: INIT TERMINAL then ret to PFAWARM -;--------------------------------------------------------------------------------- -; RESET 7: if RSTIV_MEM <> WARM, init TERM, init SD -;--------------------------------------------------------------------------------- -BOOT_YES CALL X ; init TERM UC first then init SD card, TOS = RSTIV_MEM -;--------------------------------------------------------------------------------- -; END OF RESET -;--------------------------------------------------------------------------------- - MOV #PSTACK-2,PSP ; - MOV #0,0(PSP) ; PUSH 0 on Stack - MOV #0,&STATE ; ) - MOV #LSTACK,&LEAVEPTR ; > same as QUIT - MOV #RSTACK,RSP ; ) - ASMtoFORTH ; - .word XSQUOTE ; -- RSTIV_MEM addr u - .byte 15,"LOAD\34 BOOT.4TH\34" ; LOAD" BOOT.4TH" issues error 2 if no such file... - .word BRAN,QUIT4 ; to interpret this string - .ENDIF +; ==================================; + FORTHWORD "NOBOOT" ; to disable BOOT +; ==================================; + MOV #WARM,&PUCNEXT ; removes XBOOT from PUC chain. + MOV @IP+,PC ; + .ENDIF diff --git a/forthMSP430FR_SD_LowLvl.asm b/forthMSP430FR_SD_LowLvl.asm index 400fd52..1711952 100644 --- a/forthMSP430FR_SD_LowLvl.asm +++ b/forthMSP430FR_SD_LowLvl.asm @@ -22,14 +22,14 @@ ComputePhysicalSector ; input = logical sector... ;Compute CMD ; ; ----------------------------------; MOV #1,&SD_CMD_FRM ;3 $(01 00 xx xx xx CMD) set stop bit in CMD frame - CMP #2,&FATtype ;3 FAT32 ? - JZ FAT32_CMD ;2 yes -FAT16_CMD ; FAT16 : CMD17/24 byte address = Sector * BPB_BytsPerSec - ADD W,W ;1 shift left one Sector - ADDC.B X,X ;1 - MOV W,&SD_CMD_FRM+2 ;3 $(01 00 ll LL xx CMD) - MOV.B X,&SD_CMD_FRM+4 ;3 $(01 00 ll LL hh CMD) - JMP WaitIdleBeforeSendCMD ; +; CMP #2,&FATtype ;3 FAT32 ? +; JZ FAT32_CMD ;2 yes +;FAT16_CMD ; FAT16 : CMD17/24 byte address = Sector * BPB_BytsPerSec +; ADD W,W ;1 shift left one Sector +; ADDC.B X,X ;1 +; MOV W,&SD_CMD_FRM+2 ;3 $(01 00 ll LL xx CMD) +; MOV.B X,&SD_CMD_FRM+4 ;3 $(01 00 ll LL hh CMD) +; JMP WaitIdleBeforeSendCMD ; FAT32_CMD ; FAT32 : CMD17/24 sector address MOV.B W,&SD_CMD_FRM+1 ;3 $(01 ll xx xx xx CMD) SWPB W ;1 @@ -44,9 +44,9 @@ WaitIdleBeforeSendCMD ; <=== CMD41, CMD1, CMD16 (forthMSP430FR_SD_ ADD.B #1,W ; expected value = FFh <==> MISO = 1 = SPI idle state JNZ WaitIdleBeforeSendCMD ; loop back if <> FFh ; ==================================; W = 0 = expected R1 response = ready, for CMD41,CMD16, CMD17, CMD24 -sendCommand ; +sendCommand ; ; ==================================; - ; input : SD_CMD_FRM : {CRC,byte_l,byte_L,byte_h,byte_H,CMD} + ; input : SD_CMD_FRM : {CRC,byte_l,byte_L,byte_h,byte_H,CMD} ; W = expected return value ; output W is unchanged, flag Z is positionned ; reverts CMD bytes before send : $(CMD hh LL ll 00 CRC) @@ -54,7 +54,7 @@ sendCommand ; ; ----------------------------------; Send_CMD_PUT ; performs little endian --> big endian conversion ; ----------------------------------; - MOV.B SD_CMD_FRM(X),&SD_TXBUF ;5 + MOV.B SD_CMD_FRM(X),&SD_TXBUF ;5 CMP #0,&SD_BRW ;3 full speed ? JZ FullSpeedSend ;2 yes Send_CMD_Loop ; case of low speed during memCardInit @@ -69,7 +69,7 @@ FullSpeedSend ; ; host must provide height clock cycles to complete operation ; here X=255, so wait for CMD return expected value with PUT FFh 256 times -; MOV #4,X ; to pass made in PRC SD_Card init +; MOV #4,X ; to pass made in PRC SD_Card init ; MOV #16,X ; to pass Transcend SD_Card init ; MOV #32,X ; to pass Panasonic SD_Card init ; MOV #64,X ; to pass SanDisk SD_Card init @@ -114,10 +114,10 @@ SPI_X_GET ; PUT(FFh) X times, output : W = last receiv ; ==================================; SPI_PUT ; PUT(W) X times, output : W = last received byte, X = 0 ; ==================================; - SWPB W ;1 + SWPB W ;1 MOV.B W,&SD_TXBUF ;3 put W high byte then W low byte and so forth, that performs little to big endian conversion CMP #0,&SD_BRW ;3 full speed ? - JZ FullSpeedPut ;2 + JZ FullSpeedPut ;2 SPI_PUTWAIT BIT #RX_SD,&SD_IFG ;3 JZ SPI_PUTWAIT ;2 CMP.B #0,&SD_RXBUF ;3 reset RX flag @@ -129,26 +129,26 @@ SPI_PUT_END MOV.B &SD_RXBUF,W ;3 MOV @RSP+,PC ;4 ; ----------------------------------; - ASMWORD "READ_SWX" + ASMWORD "R_SECT_WX" ; Read SECTor W=lo, X=Hi ; ==================================; ReadSectorWX ; SWX read a logical sector ; ==================================; BIS #1,S ; preset sd_read error MOV.B #51h,&SD_CMD_FRM+5 ; CMD17 = READ_SINGLE_BLOCK CALL #RW_Sector_CMD ; which performs logical sector to physical sector then little endian to big endian conversion - JNE SD_CARD_ERROR ; time out error if R1 <> 0 + JNE SD_CARD_ERROR ; time out error if R1 <> 0 ; ----------------------------------; -WaitFEhResponse ; wait SD_Card response FEh +WaitFEhResponse ; wait for SD_Card response = FEh ; ----------------------------------; CALL #SPI_GET ; - ADD.B #2,W ;1 FEh expected value - JZ ReadSectorFirstByte ; 2 + ADD.B #2,W ;1 W = 0 ? + JZ ReadSectorFirstByte ;2 yes JNZ WaitFEhResponse ;2 ; ----------------------------------; ReadSectorLoop ; get 512+1 bytes, write 512 bytes in SD_BUF ; ----------------------------------; MOV.B &SD_RXBUF,SD_BUF-1(X) ; 5 -ReadSectorFirstByte ; +ReadSectorFirstByte ; W=0 MOV.B #-1,&SD_TXBUF ; 3 put FF NOP ; 1 NOPx adjusted to avoid read SD_error ADD #1,X ; 1 @@ -161,12 +161,12 @@ ReadWriteHappyEnd ; <==== WriteSector ; ----------------------------------; BIC #3,S ; reset read and write errors BIS.B #CS_SD,&SD_CSOUT ; Chip Select high - MOV @RSP+,PC ; + MOV @RSP+,PC ; W = 0 ; ----------------------------------; .IFDEF SD_CARD_READ_WRITE - ASMWORD "WRITE_SWX" + ASMWORD "W_SECT_WX" ; Write SECTor W=lo, X=Hi ; ==================================; WriteSectorWX ; write a logical sector ; ==================================; @@ -194,7 +194,7 @@ WriteSkipCRC16 ; CRC16 not used in SPI mode CheckWriteState ; ; ----------------------------------; BIC.B #0E1h,W ; apply mask for Data response - CMP.B #4,W ; data accepted + SUB.B #4,W ; data accepted JZ ReadWriteHappyEnd ; ; ----------------------------------; @@ -203,7 +203,7 @@ CheckWriteState ; ; SD Error n° ; High byte ; 1 = CMD17 read error -; 2 = CMD24 write error +; 2 = CMD24 write error ; 4 = CMD0 time out (GO_IDLE_STATE) ; 8 = ACMD41 time out (APP_SEND_OP_COND) ; $10 = CMD16 time out (SET_BLOCKLEN) @@ -219,7 +219,7 @@ CheckWriteState ; ; 7th bit = parameter error ; Data Response Token -; Every data block written to the card will be acknowledged by a data response token. +; Every data block written to the card will be acknowledged by a data response token. ; It is one byte long and has the following format: ; %xxxx_sss0 with bits(3-1) = Status ;The meaning of the status bits is defined as follows: @@ -234,19 +234,22 @@ SD_CARD_ERROR ; <=== SD_INIT errors 4,8,$10 from forthMSP4 ADD &SD_RXBUF,S ; add SPI(GET) return value as low byte error SD_CARD_ID_ERROR ; <=== SD_INIT error $20 from forthMSP430FR_SD_INIT.asm BIS.B #CS_SD,&SD_CSOUT ; Chip Select high - mDOCOL ; +; mDOCOL ; + mASM2FORTH ; .word ECHO .word XSQUOTE ; don't use S register .byte 11,"< SD Error!" ; ; ----------------------------------; ABORT_SD ; <=== OPEN file errors from forthMSP430FR_SD_LOAD.asm ; ----------------------------------; - .word $+2 ; + mNEXTADR ; SUB #2,PSP ; MOV TOS,0(PSP) ; - MOV #10h,&BASE ; select hex + MOV #10h,&BASEADR ; select hex MOV S,TOS ; - ASMtoFORTH ; +; MOV #TIB_ORG,&CIB_ADR ; restore TIB as Current Input Buffer +; MOV #BODYACCEPT,&PFAACCEPT ; restore default ACCEPT + mASM2FORTH ; .word UDOT,ABORT_TERM ; no return... ; ----------------------------------; diff --git a/forthMSP430FR_SD_RW.asm b/forthMSP430FR_SD_RW.asm index 6637cb5..4dc59bf 100644 --- a/forthMSP430FR_SD_RW.asm +++ b/forthMSP430FR_SD_RW.asm @@ -1,6 +1,26 @@ ; -*- coding: utf-8 -*- ; DTCforthMSP430FR5xxxSD_RW.asm +; and only for FR5xxx and FR6xxx with RTC_B or RTC_C hardware if you want write file with date and time. + +; Tested with MSP-EXP430FR5969 launchpad +; Copyright (C) <2015> <J.M. THOORENS> +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see <http://www.gnu.org/licenses/>. + + + ; ====================================================================== ; READ" primitive as part of OpenPathName ; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL, @@ -10,15 +30,15 @@ ; ====================================================================== ; ----------------------------------; -OPEN_QREAD ; +OPEN_1W ; CMP #1,W ; open_type = READ" ? - JNZ OPEN_QWRITE ; no : goto next step + JNZ OPEN_2W ; no : goto next step ; ----------------------------------; OPEN_READ ; ; ----------------------------------; CMP #0,S ; open file happy end ? JNZ OPEN_Error ; no - MOV @IP+,PC ; + MOV @IP+,PC ; no more to do ; ----------------------------------; ;Z READ -- f @@ -26,120 +46,199 @@ OPEN_READ ; ; sectors are loaded in SD_BUF and BufferLen leave the count of loaded bytes. ; when the last sector of file is loaded in buffer, the handle is automatically closed and flag is true (<>0). -; ----------------------------------; +; ==================================; FORTHWORD "READ" ; -- fl closed flag -; ----------------------------------; +; ==================================; READ SUB #2,PSP ; MOV TOS,0(PSP) ; MOV &CurrentHdl,TOS ; CALL #Read_File ;SWX -READ_END - SUB &CurrentHdl,TOS ; -- fl if fl <>0 (if Z=0) handle is closed - MOV @IP+,PC ; + SUB &CurrentHdl,TOS ; -- fl if fl<>0 (if Z=0) handle is closed + MOV @IP+,PC ; ; ----------------------------------; -;----------------------------------------------------------------------- -; WRITE" (CREATE part) subroutines -;----------------------------------------------------------------------- - -; parse all FAT sectors until free cluster is found -; this NewCluster is marked as the end's one (-1) +; ==================================; +SaveSectorWtoFATs ;SWXY W = FATsector loaded in SD_buf +; ==================================; + MOV W,Y ; Y = W + ADD &OrgFAT1,W ; update FAT#1 + CALL #WriteFATsectorW ;SWX + MOV Y,W ; W = FATsector + ADD &OrgFAT2,W ; update FAT#2 +WriteFATsectorW ; + MOV #0,X ; + MOV #WriteSectorWX,PC ;SWX then RET +; ----------------------------------; +; parse all FAT sectors until free cluster is found +; this New Cluster is marked as the end's one (-1) -; input : CurFATsector +; input : W = FATSector, Y = FAToffset ; use SWX registers -; output: W = new FATsector, SD_BUF = [new FATsector], NewCluster -; SectorL is unchanged, FATS are not updated. +; output: updated (ClusterHL, FATsector, W = FATsector), SD_BUF = [new FATsector] +; SectorHL is unchanged, FATS are updated. ; S = 2 --> Disk FULL error +; ==================================; +SearchMarkNewClusterHL ;SWXY <== WRITE_FILE, OPEN_WRITE_CREATE, OPEN_OVERWRITE +; ==================================; + MOV #8,S ; preset disk full return error + PUSH W ;3 R-- FATsector ; ----------------------------------; -SearchNewCluster ; <== CREATE file, WRITE_File -; ----------------------------------; - MOV #2,S ; preset disk full return error - PUSH &CurFATsector ; last known free cluster sector - MOV &FATtype,Y ; - ADD Y,Y ; Y = bytes size of Cluster number (2 or 4) -; ----------------------------------; -LoadFATsectorInBUF ; <== IncrementFATsector +LoadFATsectorLoop ; ; ----------------------------------; - MOV @RSP,W ; W = FATsector - CMP W,&FATSize ; - JZ OPW_Error ; FATsector = FATSize ===> abort disk full - ADD &OrgFAT1,W ; - MOV #0,X ; - CALL #ReadSectorWX ;SWX (< 65536) - MOV #0,X ; init FAToffset + MOV @RSP,W ;2 + CMP W,&FATSize ;3 + JZ OPWC_DiskFull ;2 FATsector = FATSize ===> abort disk full + CALL #ReadFAT1SectorW ;SWX load FAT_buf with (new) FATsector ; ----------------------------------; -SearchFreeClustInBUF ; <== SearchNextCluster +SearchFreeClusterLoop ; ; ----------------------------------; - CMP #2,Y ; FAT16 Cluster size ? - JZ ClusterLowWordTest ; yes ClusterHighWordTest ; - CMP #0,SD_BUF+2(X) ; cluster address hi word = 0 ? - JNZ SearchNextNewCluster ; + CMP #0,SD_BUF+2(Y) ;3 cluster address hi word = 0 ? + JNZ SearchNextNewCluster ;2 ClusterLowWordTest ; - CMP #0,SD_BUF(X) ; Cluster address lo word = 0 ? - JZ GNC_FreeClusterFound ; + CMP #0,SD_BUF(Y) ;3 Cluster address lo word = 0 ? + JZ FreeClusterFound ;2 SearchNextNewCluster ; - ADD Y,X ; increment SD_BUF offset by size of Cluster address - CMP #BytsPerSec,X ; - JNE SearchFreeClustInBUF ; loopback while X < BytsPerSec -IncrementFATsector ; - ADD #1,0(RSP) ; increment FATsector - JMP LoadFATsectorInBUF ; loopback + ADD #4,Y ;1 increment SD_BUF offset by size of Cluster address + CMP #BytsPerSec,Y ;2 + JNC SearchFreeClusterLoop ;2 18/15~ loopback while X U< BytsPerSec +IncrementFATsector ;1 + ADD #1,0(RSP) ;3 increment FATsector + MOV #0,Y ; clear FAToffset + JMP LoadFATsectorLoop ;5 34/23~ loopback +; ----------------------------------; +FreeClusterFound ; X = cluster number low word in SD_BUF = FAToffset ; ----------------------------------; -GNC_FreeClusterFound ; Y = cluster number low word in SD_BUF = FATsector + MOV @RSP,&LastFATsector ; + MOV Y,&LastFAToffset ; ; ----------------------------------; MOV #0,S ; clear error + MOV #-1,SD_BUF(Y) ; mark New Cluster low word as end cluster (0xFFFF) in SD_BUF MOV.B @RSP,W ; W = 0:FATsectorLo - MOV #-1,SD_BUF(X) ; mark NewCluster low word as end cluster (0xFFFF) in SD_BUF - CMP #2,Y ; Y = FAT16 size of Cluster number ? - JZ FAT16EntryToClusterNum ; yes - MOV #0FFFh,SD_BUF+2(X) ; no: mark NewCluster high word as end cluster (0x0FFF) in SD_BUF + MOV #0FFFh,SD_BUF+2(Y) ; mark New Cluster high word as end cluster (0x0FFF) in SD_BUF ; ----------------------------------; -FAT32EntryToClusterNum ; convert FAT32 cluster address to cluster number +FAT32ClustAdrToClustNum ; convert FAT32 cluster address to cluster number (CluNum = CluAddr / 4) ; ----------------------------------; - RRA X ; X = FATOffset>>1, FAToffset is byte size + RRA Y ; Y = FATOffset>>1, (bytes to words conversion) SWPB W ; W = FATsectorLo:0 - ADD W,X ; X = FATsectorLo:FATOffset>>1 + ADD W,Y ; Y = FATsectorLo:FATOffset>>1 MOV.B 1(RSP),W ; W = FATsectorHi RRA W ; W = FATsectorHi>>1 - RRC X ; X = (FATsectorLo:FAToffset>>1)>>1 = FATsectorLo>>1:FAToffset>>2 - MOV W,&NewClusterH ; NewClusterH = FATsectorHi>>1 - MOV X,&NewClusterL ; NewClusterL = FATsectorLo>>1:FAToffset>>2 - JMP SearchNewClusterEnd ; max cluster = 7FFFFF ==> 1FFFFFFF sectors ==> 256 GB + RRC Y ; Y = (FATsectorLo:FAToffset>>1)>>1 = FATsectorLo>>1:FAToffset>>2 + MOV W,&ClusterH ; ClusterH = FATsectorHi>>1 + MOV Y,&ClusterL ; ClusterL = FATsectorLo>>1:FAToffset>>2 +; ----------------------------------; + MOV @RSP,W ; W = FATsector of new cluster + CALL #SaveSectorWtoFATs ;SWXY W = FATsector loaded in SD_buf + MOV @RSP+,W ; W = FATsector of New Cluster + MOV @RSP+,PC ; RET +; ----------------------------------; + + +; ==================================; +FreeAllClusters ;SWXY input: HDLL_FirstClus(T), output: +; ==================================;FATs are updated + MOV HDLL_FirstClus(T),ClusterL ; + MOV HDLH_FirstClus(T),ClusterH ; + CALL #ClusterHLtoFAT1sectWofstY ;WXY output: W = FATsector, Y=FAToffset + MOV W,&LastFATsector ; + MOV Y,&LastFAToffset ; + PUSH W ; R-- FATsector ptr +; ----------------------------------; +LoadFAT1sectorWloop ; +; ----------------------------------; + CALL #ReadFAT1SectorW ;SWX +; ----------------------------------; +GetAndFreeCluster ; +; ----------------------------------; + MOV SD_BUF(Y),W ; get [clusterLO] + MOV #0,SD_BUF(Y) ; free CLusterLO +GetAndFreeClusterHi ; + MOV SD_BUF+2(Y),X ; get [clusterHI] + MOV #0,SD_BUF+2(Y) ; free CLusterHI +ClusterHiTest + AND #00FFFh,X ; select 12 bits significant + CMP #00FFFh,X ; [ClusterHI] was = 0FFFh? + JNE SearchNextCluster2free ; no +ClusterLoTest ; + CMP #-1,W ; [ClusterLO] was = FFFFh? last cluster used for this file + JZ EndOfFileCluster ; yes ; ----------------------------------; -FAT16EntryToClusterNum ; convert FAT16 address of Cluster in cluster number +SearchNextCluster2free ; ; ----------------------------------; - RRA X ; X = Offset>>1, offset is word < 256 - MOV.B X,&NewClusterL ; X = NewCluster numberLO (byte) - MOV.B W,&NewClusterL+1 ; W = NewCluster numberHI (byte) - MOV #0,&NewClusterH ; + MOV W,&ClusterL ; + MOV X,&ClusterH ; + CALL #ClusterHLtoFAT1sectWofstY ;WXY W = new FATsector, new FAToffset + CMP @RSP,W ; new FATsector = FATsector ptr ? + JZ GetAndFreeCluster ; yes loop back + MOV W,X ; no: swap previous new FATsectors: + MOV @RSP,W ; W = previous FATsector + MOV X,0(RSP) ; R-- new FATsector + CALL #SaveSectorWtoFATs ;SWXY update FATs from SD_BUF to W = previous FATsector + MOV @RSP,W ; W = new FATsector + JMP LoadFAT1sectorWloop ; loop back with W = new FATsector, new FAToffset +; ----------------------------------; +EndOfFileCluster ; ; ----------------------------------; -SearchNewClusterEnd ; + MOV @RSP+,W ; + MOV #SaveSectorWtoFATs,PC ; update FATs ; ----------------------------------; - MOV @RSP+,W ; W = FATsector - MOV W,&CurFATsector ; refresh CurrentFATsector - MOV @RSP+,PC ; + +; this subroutine is called by Write_File (bufferPtr=512) and CloseHandle (0 =< BufferPtr =< 512) +; ==================================; +WriteSD_Buf ;SWX input: T = CurrentHDL +; ==================================; + ADD &BufferPtr,HDLL_CurSize(T) ; update handle CurrentSizeL + ADDC #0,HDLH_CurSize(T) ; +; ==================================; +WriteSectorHL ;SWX +; ==================================; + MOV &SectorL,W ; Low + MOV &SectorH,X ; High + MOV #WriteSectorWX,PC ; ...then RET ; ----------------------------------; -; update FATs with SD_BUF content. -; input : FATsector, FAToffset, SD_BUF = [FATsector] -; use : SWX registers -; ----------------------------------; else update FATsector of the old cluster -UpdateFATsSectorW ; +; ====================================================================== +; DEL" primitive as part of OpenPathName +; All "DEL"eted clusters are freed +; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL, +; Buffer = [DIRsector], ClusterHL = FirstClusterHL +; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl +; output: nothing (no message if open error) +; ====================================================================== +OPEN_2W ; + CMP #2,W ; open_type = DEL ? + JNZ OPEN_4W ; no : goto next step ; ----------------------------------; - PUSH W ; - ADD &OrgFAT1,W ; update FAT#1 - MOV #0,X ; - CALL #WriteSectorWX ; write a logical sector - MOV @RSP+,W ; - ADD &OrgFAT2,W ; update FAT#2 - MOV #0,X ; - CALL #WriteSectorWX ; write a logical sector +; 1- open file ; done +; ----------------------------------; + CMP #0,S ; open file happy end ? + JNE DEL_END ; no: don't send message, don't abort +; ----------------------------------; +; 2- Delete DIR entry ; +; ----------------------------------; + MOV.B #0E5h,SD_BUF(Y) ; + CALL #WriteSectorHL ;SWX write SectorHL=DIRsector +; ----------------------------------; +; 3- free all file clusters ; +; ----------------------------------; + CALL #FreeAllClusters ;SWXY input: HDLL_FirstClus(T), output: FATS are updated +; ----------------------------------; +; 4- Close Handle ; +; ----------------------------------; + CALL #CloseHandle ; ; ----------------------------------; +DEL_END ; + MOV @IP+,PC ;4 +; ----------------------------------; + +;----------------------------------------------------------------------- +; WRITE" (CREATE part) subroutines +;----------------------------------------------------------------------- @@ -150,9 +249,9 @@ UpdateFATsSectorW ; ; modified time : ofsset 16h = 0bhhhhhmmmmmmsssss, with : s=seconds*2, m=minutes, h=hours ; dates : offset 10, 12, 18 = 0byyyyyyymmmmddddd, with : y=year-1980, m=month, d=day -; ----------------------------------; input: -GetYMDHMSforDIR ;X=date, W=TIME -; ----------------------------------; +; ==================================; +GetYMDHMSforDIR ; output: X=date, W=TIME +; ==================================; .IFDEF LF_XTAL ; .IFNDEF RTC ; RTC_B or RTC_C select ; ----------------------------------; @@ -177,12 +276,12 @@ WaitRTC ; yes MOV #512,&OP2 ; ADD &RES0,X ; .ELSEIF - MOV #0,X ; X=DATE + MOV #0,X ; X=DATE MOV #0,W ; W=TIME .ENDIF .ENDIF SD_RW_RET ; - MOV @RSP+,PC ; + MOV @RSP+,PC ; ; ----------------------------------; @@ -190,24 +289,22 @@ SD_RW_RET ; ForbiddenChars ; 15 forbidden chars table + dot char .byte '"','*','+',',','/',':',';','<','=','>','?','[','\\',']','|','.' -; ----------------------------------; +; ==================================; OPWC_SkipDot ; -; ----------------------------------; +; ==================================; CMP #4,X ; - JL FillDIRentryName ; X < 4 : no need spaces to complete name entry + JNC FillDIRentryName ; X U< 4 : no need spaces to complete name entry SUB #3,X ; - CALL #OPWC_CompleteWithSpaces; complete name entry - MOV #3,X ; -; ----------------------------------; - -; ----------------------------------; + CALL #OPWC_CompleteWithSpaces; complete name entry + MOV #3,X ; +; ==================================; FillDIRentryName ;SWXY use -; ----------------------------------; +; ==================================; MOV.B @T+,W ; W = char of pathname MOV.B W,SD_BUF(Y) ; to DIRentry ; CMP #0,W ; end of stringZ ? ; JZ OPWC_CompleteWithSpaces ; - CMP T,&EndOfPath ; EOS < PTR ? + CMP T,&PathName_END ; EOS < PTR ? JNC OPWC_CompleteWithSpaces ; yes ; ----------------------------------; SkipForbiddenChars ; @@ -233,56 +330,131 @@ ForbiddenCharLoop ; ; ----------------------------------; OPWC_CompleteWithSpaces ; 0 to n spaces ! ; ----------------------------------; - CMP #0,X ; + CMP #0,X ; JZ OPWC_CWS_End ; ; ----------------------------------; OPWC_CompleteWithSpaceloop ; ; ----------------------------------; MOV.B #' ',SD_BUF(Y) ; remplace dot by char space - ADD #1,Y ; increment DIRentry ptr in buffer + ADD #1,Y ; increment DIRentry ptr in buffer SUB #1,X ; dec countdown of chars space JNZ OPWC_CompleteWithSpaceloop ; OPWC_CWS_End ; - MOV @RSP+,PC ; + MOV @RSP+,PC ; ; ----------------------------------; +; ==================================; +LoadUpdateSaveDirEntry ;SWXY +; ==================================; + MOV HDLL_DIRsect(T),W ; + MOV HDLH_DIRsect(T),X ; + CALL #readSectorWX ;SWX SD_buffer = DIRsector + MOV HDLW_DIRofst(T),Y ; Y = DirEntryOffset + CALL #GetYMDHMSforDIR ; X=DATE, W=TIME + MOV X,SD_BUF+18(Y) ; access date + MOV W,SD_BUF+22(Y) ; modified time + MOV X,SD_BUF+24(Y) ; modified date + MOV HDLL_CurSize(T),SD_BUF+28(Y); save new filesize + MOV HDLH_CurSize(T),SD_BUF+30(Y); + MOV HDLL_DIRsect(T),W ; + MOV HDLH_DIRsect(T),X ; + MOV #WriteSectorWX,PC ;SWX then RET +; ----------------------------------; +;----------------------------------------------------------------------- +; WRITE" subroutines +;----------------------------------------------------------------------- + + +; write sequentially the buffer in the post incremented SectorHL. +; The first time, SectorHL is initialized by WRITE". +; All used registers must be initialized. +; ==================================; +Write_File ;STWXY <== WRITE, SD_EMIT, TERM2SD" +; ==================================; + MOV #BytsPerSec,&BufferPtr ; write always all the buffer + MOV &CurrentHdl,T ; + CALL #WriteSD_Buf ;SWX write SD_BUF and update Handle informations only for DIRentry update + MOV #0,&BufferPtr ; reset buffer pointer +; ----------------------------------; +PostIncrementSector ; +; ----------------------------------; + ADD.B #1,HDLB_ClustOfst(T) ; increment current Cluster offset + CMP.B &SecPerClus,HDLB_ClustOfst(T) ; out of bound ? + JNC Write_File_End ; no, +; ----------------------------------; + CALL #HDLcurClus2FATsecWofstY;WXY Output: FATsector W=FATsector, Y=FAToffset + PUSH Y ; push previous FAToffset + PUSH W ; push previous FATsector +; ----------------------------------; +GetNewCluster ; input : T=CurrentHdl +; ----------------------------------; + CALL #SearchMarkNewClusterHL ;SWXY input: W = FATsector Y = FAToffset, output: ClusterHL, W = FATsector of New cluster + CMP @RSP,W ; previous and new clusters are in same FATsector? + JZ LinkClusters ; yes +; ----------------------------------; +UpdateNewClusterFATs ; +; ----------------------------------; +; CALL #SaveSectorWtoFATs ;SWXY no: already done by SearchMarkNewClusterHL + MOV @RSP,W ; W = previous FATsector + CALL #ReadFAT1SectorW ;SWX reload previous FATsector in buffer to link clusters +; ----------------------------------; +LinkClusters ; +; ----------------------------------; + MOV @RSP+,W ; W = previous FATsector + MOV @RSP+,Y ; Y = previous FAToffset + MOV &ClusterL,SD_BUF(Y) ; store new cluster to current cluster address in previous FATsector buffer + MOV &ClusterH,SD_BUF+2(Y) ; + CALL #SaveSectorWtoFATs ;SWXY update FATs from SD_BUF to W = previous FATsector +; ==================================; +HDLSetCurClustSetFrstSect ; +; ==================================; + MOV #4,HDLB_Token(T) ; and clear ClustOfst +; ==================================; +HDLSetCurClustSetCurSect ; +; ==================================; + MOV &ClusterL,HDLL_CurClust(T) ; update handle with new cluster + MOV &ClusterH,HDLH_CurClust(T) ; +Write_File_End + MOV #ClusterHL2sectorHL,PC ;W set current SectorHL to be written then RET +; ----------------------------------; + +;Z WRITE -- +; sequentially write the entire SD_BUF in a file opened by WRITE" +; ==================================; + FORTHWORD "WRITE" ; in assembly : CALL #WRITE,X CALL 2(X) +; ==================================; + CALL #Write_File ;STWXY + MOV @IP+,PC ; +; ----------------------------------; ; ====================================================================== ; WRITE" primitive as part of OpenPathName ; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL, ; Buffer = [DIRsector], ClusterHL = FirstClusterHL ; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl -; output: nothing else abort on error -; error 1 : PathNameNotFound -; error 2 : NoSuchFile -; error 4 : DirectoryFull -; error 8 : AlreadyOpen -; error 16 : NomoreHandle +; output: Current Sector is set else abort on WRITE error +; error 4 : InvalidPathname +; error 8 : DiskFull ; ====================================================================== - -; ----------------------------------; -OPEN_QWRITE ; - CMP #2,W ; open_type = WRITE" ? - JNZ OPEN_QDEL ; no : goto next step +OPEN_4W ; + CMP #4,W ; open_type = WRITE" ? + JNZ OPEN_8W ; no : goto next step ; ----------------------------------; ; 1 try to open ; done ; ----------------------------------; ; 2 select error "no such file" ; ; ----------------------------------; CMP #2,S ; "no such file" error ? - JZ OPEN_WRITE_CREATE ; yes - CMP #0,S ; no open file error ? - JZ OPEN_WRITE_APPEND ; yes + JZ OPEN_WRITE_CREATE ; yes, Handle is to be created ! + CMP #0,S ; well opened file ? + JZ OPEN_OVERWRITE ; yes ; ----------------------------------; -; Write errors ; +OPWC_Write_Errors ; ; ----------------------------------; -OPWC_InvalidPathname ; S = 1 -OPWC_DiskFull ; S = 2 -OPWC_DirectoryFull ; S = 4 -OPWC_AlreadyOpen ; S = 8 -OPWC_NomoreHandle ; S = 16 +OPWC_InvalidPathname ; S = 4 +OPWC_DiskFull ; S = 8 ; ----------------------------------; OPW_Error ; set ECHO, type Pathname, type #error, type "< WriteError"; no return mDOCOL ; @@ -291,195 +463,108 @@ OPW_Error ; set ECHO, type Pathname, type #error, type .word BRAN,ABORT_SD ; to insert S error as flag, no return ; ----------------------------------; - ; ====================================================================== -; WRITE" (CREATE part) primitive as part of OpenPathName -; input from open: S = NoSuchFile, W = open_type, SectorHL = DIRsectorHL, -; Buffer = [DIRsector], ClusterHL = FirstClusterHL -; output: nothing else abort on error: -; error 1 : InvalidPathname -; error 2 : DiskFull -; error 4 : DirectoryFull -; error 8 : AlreadyOpen -; error 16 : NomoreHandle +; WRITE" primitive as part of OpenPathName +; All "DEL"eted clusters are freed +; input from open: W = open_type, SectorHL = DIRsectorHL, +; Buffer = [DIRsector], ClusterHL = FirstCluster +; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl, +; output: nothing (no message if open error) ; ====================================================================== + +; ==================================; +OPEN_WRITE_CREATE ; a new Handle is to be created +; ==================================; +; 1- open file ; done ; ----------------------------------; -OPEN_WRITE_CREATE ; -; ----------------------------------; -; 3 get free cluster ; -; ----------------------------------; input: FATsector - CALL #SearchNewCluster ;SWXY output: W = new FATsector loaded in buffer,NewCluster - MOV &NewClusterL,&ClusterL ; - MOV &NewClusterH,&ClusterH ; - CALL #UpdateFATsSectorW ;SWX update FATs with buffer +; 2 get free cluster ; ; ----------------------------------; - CALL #ReadSector ; reload DIRsector - MOV &EntryOfst,Y ; reload entry offset (first free entry in DIR) + MOV #0,W ; init FATsector = 0, search new cluster + MOV #0,Y ; init FAToffset + CALL #SearchMarkNewClusterHL ;WXY output: updated (ClusterHL, FATsector, W = FATsector), SD_BUF = [new FATsector] ; ----------------------------------; -; 4 init DIRentryAttributes ; +; 3 init DIRentryAttributes ; ; ----------------------------------; -OPWC_SetEntryAttribute ; (cluster=DIRcluster!) + CALL #ReadSectorHL ; reload DIRsector + MOV &DIREntryOfst,Y ; Y = entry offset (first free entry in DIR) MOV.B #20h,SD_BUF+11(Y) ; file attribute = file CALL #GetYMDHMSforDIR ;WX X=DATE, W=TIME MOV #0,SD_BUF+12(Y) ; nt reserved = 0 and centiseconds are 0 MOV W,SD_BUF+14(Y) ; time of creation MOV X,SD_BUF+16(Y) ; date of creation 20/08/2001 - MOV X,SD_BUF+18(Y) ; date of access 20/08/2001 - MOV &ClusterH,SD_BUF+20(Y) ; as first Cluster Hi - MOV &ClusterL,SD_BUF+26(Y) ; as first cluster LO - MOV #0,SD_BUF+28(Y) ; file lenghtLO = 0 - MOV #0,SD_BUF+30(Y) ; file lenghtHI = 0 -; ----------------------------------; -; 5 create DIRentryName ; -; ----------------------------------; - MOV #1,S ; preset pathname error - MOV &Pathname,T ; here, pathname is "xxxxxxxx.yyy" format -; CMP.B #0,0(T) ; forbidden null string - CMP T,&EndOfPath ; - JZ OPWC_InvalidPathname ; write error 1 +; MOV X,SD_BUF+18(Y) ; date of access 20/08/2001 + MOV &ClusterH,SD_BUF+20(Y) ; as first Cluster Hi + MOV &ClusterL,SD_BUF+26(Y) ; as first cluster LO + MOV #0,SD_BUF+28(Y) ; set file_sizeLO = 0 + MOV #0,SD_BUF+30(Y) ; set file_sizeHI = 0 +; ----------------------------------; +; 4 create DIRentryName ; file name format "xxxxxxxx.yyy" +; ----------------------------------; + MOV #4,S ; preset pathname error + MOV &PathName_PTR,T ; here, PathName_PTR is set to file name + CMP T,&PathName_END ; end of string reached ? + JZ OPWC_InvalidPathname ; yes write error 1 CMP.B #'.',0(T) ; forbidden "." in first JZ OPWC_InvalidPathname ; write error 1 MOV #11,X ; X=countdown of chars entry CALL #FillDIRentryName ;STWXY ; ----------------------------------; -; 6 save DIRsector ; +; 5 update DIRsector ; ; ----------------------------------; - CALL #WriteSector ;SWX update DIRsector + CALL #WriteSectorHL ;SWX update DIRsector ; ----------------------------------; ; 7 Get free handle ; ; ----------------------------------; - MOV #2,W ; - CALL #GetFreeHandle ; output : S = handle error, CurCluster and CurSector are set -; ----------------------------------; - CMP #0,S ; no error ? - JNZ OPWC_NomoreHandle ; ==> abort with error 16 - MOV @IP+,PC ; -- -; ----------------------------------; - -;----------------------------------------------------------------------- -; WRITE" subroutines -;----------------------------------------------------------------------- - -; SectorL is unchanged -; ----------------------------------; -OPWW_UpdateDirectory ; <== CloseHandleT -; ----------------------------------; Input : current Handle - MOV HDLL_DIRsect(T),W ; - MOV HDLH_DIRsect(T),X ; - CALL #readSectorWX ;SWX buffer = DIRsector - CALL #GetYMDHMSforDIR ; X=DATE, W=TIME - MOV HDLW_DIRofst(T),Y ; Y = DirEntryOffset - MOV X,SD_BUF+18(Y) ; access date - MOV W,SD_BUF+22(Y) ; modified time - MOV X,SD_BUF+24(Y) ; modified date -OPWW_UpdateEntryFileSize ; - MOV HDLL_CurSize(T),SD_BUF+28(Y); save new filesize - MOV HDLH_CurSize(T),SD_BUF+30(Y); - MOV HDLL_DIRsect(T),W ; - MOV HDLH_DIRsect(T),X ; - MOV #WriteSectorWX,PC ;SWX then RET -; ----------------------------------; - -; this subroutine is called by Write_File (bufferPtr=512) and CloseHandleT (0 =< BufferPtr =< 512) -; ==================================; -WriteBuffer ;STWXY input: T = CurrentHDL -; ==================================; - ADD &BufferPtr,HDLL_CurSize(T) ; update handle CurrentSizeL - ADDC #0,HDLH_CurSize(T) ; -; ==================================; -WriteSector ;SWX -; ==================================; - MOV &SectorL,W ; Low - MOV &SectorH,X ; High - MOV #WriteSectorWX,PC ; ...then RET + MOV #4,W ; get handle for write + CALL #GetFreeHandle ; output : CurCluster and CurSector are set + MOV @IP+,PC ; -- ; ----------------------------------; - - -; write sequentially the buffer in the post incremented SectorHL. -; The first time, SectorHL is initialized by WRITE". -; All used registers must be initialized. ; ==================================; -Write_File ; <== WRITE, SD_EMIT, TERM2SD" +OPEN_OVERWRITE ; handle exists ; ==================================; - MOV #BytsPerSec,&BufferPtr ; write always all the buffer - MOV &CurrentHdl,T ; - CALL #WriteBuffer ; write SD_BUF and update Handle informations only for DIRentry update - MOV #0,&BufferPtr ; reset buffer pointer -; ----------------------------------; -PostIncrementSector ; -; ----------------------------------; - ADD.B #1,HDLB_ClustOfst(T) ; increment current Cluster offset - CMP.B &SecPerClus,HDLB_ClustOfst(T) ; out of bound ? - JNZ Write_File_End ; no, -; ----------------------------------; -GetNewCluster ; input : T=CurrentHdl -; ----------------------------------; - MOV.B #0,HDLB_ClustOfst(T) ; reset handle ClusterOffset - CALL #HDLCurClusToFAT1sectWofstY;WXY Output: W=FATsector, Y=FAToffset, Cluster=HDL_CurCluster - PUSH Y ; push current FAToffset - PUSH W ; push current FATsector - CALL #SearchNewCluster ;SWXY output: W = new FATsector loaded in buffer, NewCluster - CMP @RSP,W ; current and new clusters are in same FATsector? - JZ LinkClusters ; yes -UpdateNewClusterFATs ; - CALL #UpdateFATsSectorW ;SWX no: UpdateFATsSectorW with buffer of new FATsector - MOV @RSP,W ; W = current FATsector - ADD &OrgFAT1,W ; - MOV #0,X ; - CALL #ReadSectorWX ;SWX (< 65536) -LinkClusters ; - MOV @RSP+,W ; W = current FATsector - MOV @RSP+,Y ; pop current FAToffset - MOV &NewClusterL,SD_BUF(Y) ; store new cluster to current cluster address in current FATsector buffer - CMP #1,&FATtype ; FAT16? - JZ UpdatePreviousClusterFATs ; yes - MOV &NewClusterH,SD_BUF+2(Y); -UpdatePreviousClusterFATs ; - CALL #UpdateFATsSectorW ;SWX update FATS with current FATsector buffer -UpdateHandleCurCluster ; - MOV &NewClusterL,HDLL_CurClust(T) ; update handle with new cluster - MOV &NewClusterH,HDLH_CurClust(T) ; -; CALL #ComputeHDLcurrentSector ; set Cluster first Sector as next Sector to be written -; MOV #OPWW_UpdateDirectory,PC ; update DIRentry to avoid cluster lost, then RET -Write_File_End - MOV #ComputeHDLcurrentSector,PC ; set current Cluster Sector as next Sector to be written then RET -; ----------------------------------; - -;Z WRITE -- -; sequentially write the entire SD_BUF in a file opened by WRITE" +; free all file clusters ; ; ----------------------------------; - FORTHWORD "WRITE" ; in assembly : CALL &WRITE+2 -; ----------------------------------; - CALL #Write_File ; - MOV @IP+,PC ; + CALL #FreeAllClusters ;SWXY input: HDLL_FirstClus(T), output: FATS are updated + MOV #0,HDLL_CurSize(T) ; clear currentSize + MOV #0,HDLH_CurSize(T) ; + MOV HDLL_FirstClus(T),ClusterL ; Set ClusterHL + MOV HDLH_FirstClus(T),ClusterH ; + CALL #ClusterHLtoFAT1sectWofstY ;WXY output: W = FATsector, Y=FAToffset + CALL #SearchMarkNewClusterHL ;SWXY input: W = FATsector, Y = FAToffset output: ClusterHL, W = updated new FATsector loaded in SD_BUF + CALL #HDLSetCurClustSetFrstSect ; + MOV @IP+,PC ; -- ; ----------------------------------; ; ====================================================================== -; WRITE" (APPEND part) primitive as part of OpenPathName -; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL, +; APPEND" primitive as part of OpenPathName +; input from open: SectorHL = DIRsectorHL, ; Buffer = [DIRsector], ClusterHL = FirstClusterHL ; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl ; output: nothing else abort on error -; error 2 : DiskFull +; error 2 : DiskFull ; ====================================================================== - -; ----------------------------------; -OPEN_WRITE_APPEND ; -; ----------------------------------; +OPEN_8W ; + CMP #2,S ; "no such file" error ? + JZ OPEN_WRITE_CREATE ; yes + CMP #0,S ; well opened file ? + JNZ OPWC_Write_Errors ; no +; ==================================; +OPEN_WRITE_APPEND ; yes +; ==================================; ; 1- open file ; done ; ----------------------------------; -; 2- compute missing Handle infos ; + MOV.B #4,HDLB_Token(T) ; update HDLB_Token(T) ; ----------------------------------; ; 2.1- Compute Sectors count ; Sectors = HDLL_CurSize/512 ; ----------------------------------; - MOV.B HDLL_CurSize+1(T),Y ;Y = 0:CurSizeLOHi - MOV.B HDLH_CurSize(T),X ;X = 0:CurSizeHILo - SWPB X ;X = CurSizeHIlo:0 + MOV.B HDLL_CurSize+1(T),Y ;Y = 0:CurSizeLOHi (bytes) + MOV.B HDLH_CurSize(T),X ;X = 0:CurSizeHILo + SWPB X ;X = CurSizeHIlo:0 ADD Y,X ;X = CurSizeHIlo:CurSizeLOhi - MOV.B HDLH_CurSize+1(T),Y ;Y:X = CurSize / 256 + MOV.B HDLH_CurSize+1(T),Y ;Y:X = CurSize / 256 (bytes) ; ----------------------------------; ; 2.2 Compute Clusters Count ; ; ----------------------------------; @@ -499,153 +584,52 @@ DIVSECPERSPC2 ; SUB #1,S ;1 CNT-1 JGE DIVSECPERSPC2 ;2 4~ loopback Wlo = OFFSET, X = CLU_LO, Y = CLU_HI ; ----------------------------------; - MOV &CurrentHDL,T ;3 reload Handle ptr -; ----------------------------------; -; 2.3- Compute last Cluster ; X = Clusters numberLO, Y = Clusters numberHI +; 2.3- Compute Current Cluster ; X = ClusterCountLO, Y = ClusterCountHI ; ----------------------------------; + MOV &CurrentHDL,T ;3 reload Handle ptr ADD HDLL_FirstClus(T),X ; ADDC HDLH_FirstClus(T),Y ; MOV X,HDLL_CurClust(T) ; update handle MOV Y,HDLH_CurClust(T) ; ; ----------------------------------; -; 2.4- Compute Sectors offset ; +; 2.4- load current sectorHL ; ; ----------------------------------; - MOV.B W,HDLB_ClustOfst(T) ;3 update handle with W = REMlo = sectors offset in last cluster + MOV.B W,HDLB_ClustOfst(T) ;3 update handle with W = REM8 = sectors offset in last cluster + CALL #LoadCurSectorHL ;SWX in SD_buf ; ----------------------------------; -; 3- load last sector in SD_BUF ; +; 2.5- Compute SD_Buf ptr ; ; ----------------------------------; - MOV HDLL_CurSize(T),W ; example : W = 1013 - BIC #01FFh,HDLL_CurSize(T) ; substract 13 from HDLL_CurSize, because loaded in buffer - AND #01FFh,W ; W = 13 - MOV W,&BufferPtr ; init Buffer Pointer with 13 - CALL #LoadHDLcurrentSector ;SWX - MOV @IP+,PC ; BufferPtr = first free byte offset + MOV HDLL_CurSize(T),W ; example : W = $A313 bytes + BIC #01FFh,HDLL_CurSize(T) ; HDLL_CurSize = $A200 bytes + AND #01FFh,W ; remainder W = $0113 bytes + MOV W,&BufferPtr ; init Buffer Pointer with $0113 ; ----------------------------------; - - -; ====================================================================== -; DEL" primitive as part of OpenPathName -; All "DEL"eted clusters are freed -; If next DIRentry in same sector is free, DIRentry is freed, else hidden. -; input from open: S = OpenError, W = open_type, SectorHL = DIRsectorHL, -; Buffer = [DIRsector], ClusterHL = FirstClusterHL -; from open(GetFreeHandle): Y = DIRentry, T = CurrentHdl -; output: nothing (no message if open error) -; ====================================================================== - - -OPEN_QDEL ; -; CMP #4,W ; open_type = DEL" -; JNZ OPEN_8W ; -; ----------------------------------; -OPEN_DEL ; -; ----------------------------------; -; 1- open file ; done -; ----------------------------------; - CMP #0,S ; open file happy end ? - JNE DEL_END ; no: don't send message -; ----------------------------------; -; 2- Delete DIR entry ; "delete" entry with 00h if next entry in same DIRsector is free, else "hide" entry with 05Eh -; ----------------------------------; -SelectFreeEntry ; nothing to do: S = 0 ready for free entry! -; ----------------------------------; - CMP #BytsPerSec-32,Y ; Entry >= last entry in DIRsector ? - JC SelectHideEntry ; yes: next DIR entry is out of sector - CMP.B #0,SD_BUF+32(Y) ; no: next DIR entry in DIRsector is free? - JZ WriteDelEntry ; yes -; ----------------------------------; -SelectHideEntry ; no -; ----------------------------------; - MOV.B #0E5h,S ; -; ----------------------------------; -WriteDelEntry -; ----------------------------------; - MOV.B S,SD_BUF(Y) ; - CALL #WriteSector ;SWX write SectorHL=DIRsector -; ----------------------------------; -; 3- free all file clusters ; Cluster = FirstCluster -; ----------------------------------; -ComputeClusterSectWofstY ; - CALL #ClusterToFAT1sectWofstY;WXY W = FATsector, Y=FAToffset - MOV W,&CurFATsector ; update CurrentFATsector -; ----------------------------------; -LoadFAT1sector -; ----------------------------------; - MOV W,T ; T = W = current FATsector memory - ADD &OrgFAT1,W ; - MOV #0,X ; - CALL #ReadSectorWX ;SWX (< 65536) -; ----------------------------------; -GetAndFreeClusterLo ; -; ----------------------------------; - MOV SD_BUF(Y),W ; get [clusterLO] - MOV #0,SD_BUF(Y) ; free CLusterLO -ClusterTestSelect ; - CMP #1,&FATtype ; FAT16 ? - JZ ClusterLoTest ; yes -GetAndFreeClusterHi ; - MOV SD_BUF+2(Y),X ; get [clusterHI] - MOV #0,SD_BUF+2(Y) ; free CLusterHI -ClusterHiTest - AND #00FFFh,X ; select 12 bits significant - CMP #00FFFh,X ; [ClusterHI] was = 0FFFh? - JNE SearchNextCluster2free ; no -ClusterLoTest - CMP #-1,W ; [ClusterLO] was = FFFFh? - JZ EndOfFileClusters ; yes -; ----------------------------------; -SearchNextCluster2free -; ----------------------------------; - MOV W,&ClusterL ; - MOV X,&ClusterH ; - CALL #ClusterToFAT1sectWofstY;WXY - CMP W,T ; new FATsector = current FATsector memory ? - JZ GetAndFreeClusterLo ; yes loop back - PUSH W ; no: save new FATsector... - MOV T,W ; ...before update current FATsector - CALL #UpdateFATsSectorW ;SWX - MOV @RSP+,W ; restore new current FATsector - JMP LoadFAT1sector ; loop back with Y = FAToffset -; ----------------------------------; -EndOfFileClusters ; -; ----------------------------------; - MOV T,W ; T = W = current FATsector - CALL #UpdateFATsSectorW ;SWX -; ----------------------------------; -; 3- Close Handle ; -; ----------------------------------; - CALL #CloseHandleT ; -; ----------------------------------; -DEL_END ; - MOV @IP+,PC ;4 + MOV @IP+,PC ; BufferPtr = first free byte offset ; ----------------------------------; - .IFNDEF TERMINAL_I2C ; if UART_TERMINAL ; first TERATERM sends the command TERM2SD" file.ext" to FastForth which returns XOFF at the end of the line. ; then when XON is sent below, TERATERM sends "file.ext" up to XOFF sent by TERM2SD" (slices of 512 bytes), ; then TERATERM sends char EOT that closes the file on SD_CARD. - FORTHWORD "TERM2SD\34" - mDOCOL - .word DELDQ ; DEL file if already exist - .word lit,2 ; -- open_type - .word HERE,COUNT ; -- open_type addr cnt - .word PARENOPEN ; reopen same filepath but as write - .word $+2 ; - MOV @RSP+,IP ; +; ==================================; + FORTHWORD "TERM2SD\34" ; +; ==================================; + mDOCOL ; + .word WRITEDQ ; if already exist FreeAllClusters else create it as WRITE file + mNEXTADR ; ; ----------------------------------; -T2S_GetSliceLoop ; tranfert by slices of 512 bytes terminal input to file on SD_CARD via SD_BUF +T2S_GetSliceLoop ; tranfert by slices of 512 bytes from terminal input to file on SD_CARD via SD_BUF ; ----------------------------------; MOV #0,W ;1 reset W = BufferPtr CALL #RXON ; use no registers ; ----------------------------------; -T2S_FillBufferLoop ; +T2S_Get_a_Char_Loop ; ; ----------------------------------; BIT #RX_TERM,&TERM_IFG ;3 new char in TERMRXBUF ? - JZ T2S_FillBufferLoop ;2 + JZ T2S_Get_a_Char_Loop ;2 MOV.B &TERM_RXBUF,X ;3 MOV.B X,&TERM_TXBUF CMP.B #4,X ;1 EOT sent by TERATERM ? @@ -653,25 +637,38 @@ T2S_FillBufferLoop ; MOV.B X,SD_BUF(W) ;3 ADD #1,W ;1 CMP #BytsPerSec-1,W ;2 - JNC T2S_FillBufferLoop ;2 W < BytsPerSec-1 21 cycles char loop JZ T2S_XOFF ;2 W = BytsPerSec-1 send XOFF after RX 511th char + JNC T2S_Get_a_Char_Loop ;2 W < BytsPerSec-1 21 cycles char loop (476 kBds/MHz) ; ----------------------------------; T2S_WriteFile ;2 W = BytsPerSec ; ----------------------------------; - CALL #Write_File ;TSWXY write all the buffer - JMP T2S_GetSliceLoop ;2 + CALL #Write_File ;STWXY write all the buffer + JMP T2S_GetSliceLoop ;2 ; ----------------------------------; T2S_XOFF ; 27 cycles between XON and XOFF ; ----------------------------------; CALL #RXOFF ;4 use no registers - JMP T2S_FillBufferLoop ;2 loop back once to get last char + JMP T2S_Get_a_Char_Loop ;2 loop back once to get char sent by TERMINAL during XOFF time ; ----------------------------------; -T2S_End_Of_File ; +T2S_End_Of_File ; wait CR before sending XOFF +; ----------------------------------; +T2S_Wait_CR ; warning! EOT must be followed by CR+LF (TERM2SD" used with I2C_FastForth) +; ----------------------------------; + CMP.B #0Dh,&TERM_RXBUF ; also clears RX_IFG ! + JZ T2S_Wait_CR ; wait CR ; ----------------------------------; CALL #RXOFF ;4 use no registers +; ----------------------------------; +T2S_Wait_LF ; warning! EOT must be followed by CR+LF (TERM2SD" used with I2C_FastForth) +; ----------------------------------; + CMP.B #0Ah,&TERM_RXBUF ; also clears RX_IFG ! + JZ T2S_Wait_LF ; wait LF +; ----------------------------------; MOV W,&BufferPtr ;3 - CALL #CloseHandleT ;4 - MOV @IP+,PC ;4 + CALL #CloseHandle ;4 +; ----------------------------------; + MOV @RSP+,IP ; + MOV @IP+,PC ;4 ; ----------------------------------; .ELSE ; if I2C_TERMINAL @@ -680,59 +677,75 @@ T2S_End_Of_File ; ; then when RXON is sent below, I2C_Master sends "file.ext" line by line ; then TERATERM sends char EOT that closes the file on SD_CARD. +; ==================================; FORTHWORD "TERM2SD\34" ; here, I2C_Master is reSTARTed in RX mode - mDOCOL - .word DELDQ ; DEL file if already exist - .word lit,2 ; -- open_type - .word HERE,COUNT ; -- open_type addr cnt - .word PARENOPEN ; reopen same filepath but as write - .word $+2 ; +; ==================================; + mDOCOL ; + .word WRITEDQ ; if already exist FreeAllClusters else create it as WRITE file + mNEXTADR ; ; ----------------------------------; - CALL #RXON ; send I2C Ctrl_Char $00 to I2C_Master + MOV #0,W ; reset W = SD_Buf_Ptr + MOV.B #0Ah,IP ; IP = char 'LF' ; ----------------------------------; -T2S_ClearBuffer ; +T2S_GetLineLoop ; tranfert line by line from terminal input to SD_BUF ; ----------------------------------; - MOV #0,W ;1 reset W = BufferPtr + CALL #RXON ; use Y reg; send I2C Ctrl_Char $00 to request I2C_Master to switch from RX to TX +; ----------------------------------; +T2S_Get_a_Char_Loop ; ; ----------------------------------; -T2S_FillBufferLoop ; move by slices of 512 bytes from TERMINAL input to file on SD_CARD via SD_BUF +T2S_Q_BufferFull ; test it before to take data in RX buffer and so to do SCL strech low during Write_File !!!! +; ----------------------------------; + CMP #BytsPerSec,W ;2 buffer full ? + JNC T2S_Get_a_Char ;2 no +; ----------------------------------; +T2S_WriteFile ; tranfert all 512 bytes of SD_BUF to the opened file in SD_CARD +; ----------------------------------; SCL is stretched low by Slave (it's my) + CALL #Write_File ;STWXY Write_File write always all the buffer + MOV #0,W ; reset SD_Buf_Ptr +; ----------------------------------; +T2S_Get_a_Char ; ; ----------------------------------; BIT #RX_TERM,&TERM_IFG ;3 new char in TERMRXBUF ? - JZ T2S_FillBufferLoop ;2 no - MOV.B &TERM_RXBUF,X ;3 - CMP.B #4,X ;1 EOT sent by TERMINAL (teraterm.exe) ? + JZ T2S_Get_a_Char ;2 no + MOV.B &TERM_RXBUF,X ;3 SCL is released here +; ----------------------------------; +T2S_Q_EOF ; +; ----------------------------------; + CMP.B #4,X ;1 EOF sent by TERMINAL (teraterm.exe) ? JZ T2S_End_Of_File ;2 yes MOV.B X,SD_BUF(W) ;3 ADD #1,W ;1 - CMP.B #0Ah,X ;2 Char LF ? - JNZ T2S_Q_BufferFull ;2 no ; ----------------------------------; -T2S_GetNewLine ; here I2C_Master automatically (re)START in RX mode, one char must be sent to -; ----------------------------------; clear I2C_Slave UCSTTIFG, so we must send LF a minima - ASMtoFORTH ; - .word CR ; (CR+LF instead of LF is sent to beautify TERMINAL display, if ECHO is ON obviously) - .word $+2 ; - CALL #RXON ; send I2C Ctrl_Char $00 to I2C_Master +T2S_Q_Char_LF ; when Master send the Ack on char 'LF', it reStarts automatically in RX mode ; ----------------------------------; -T2S_Q_BufferFull ; + CMP.B IP,X ;1 Char LF received ? + JNZ T2S_Get_a_Char_Loop ;2 no, 22 cycles loop back (< 1us @ 24 MHz) ; ----------------------------------; - CMP #BytsPerSec,W ;2 buffer full ? - JNC T2S_FillBufferLoop ;2 no 21 cycles char loop +T2S_Send_CR ; because I2C_Master doesn't echo it on TERMINAL +; ----------------------------------; + BIT #TX_TERM,&TERM_IFG ; + JZ T2S_Send_CR ; wait TX buffer empty + MOV.B #0Dh,&TERM_TXBUF ; send CR to beautify TERMINAL display (if ECHO is ON, obviously) +; ----------------------------------; +T2S_Send_LF ; because I2C_Master doesn't echo it on TERMINAL ; ----------------------------------; -T2S_WriteFile ;2 yes + BIT #TX_TERM,&TERM_IFG ; + JZ T2S_Send_LF ; wait TX buffer empty + MOV.B IP,&TERM_TXBUF ; send LF to beautify TERMINAL display (if ECHO is ON, obviously) ; ----------------------------------; - CALL #Write_File ;4 TSWXY write all the buffer - JMP T2S_ClearBuffer ;2 + JMP T2S_GetLineLoop ; ; ----------------------------------; T2S_End_Of_File ; ; ----------------------------------; - BIT #RX_TERM,&TERM_IFG ;3 new char in TERMRXBUF ? - JZ T2S_End_Of_File ;2 no - CMP.B #0Ah,&TERM_RXBUF ;4 Char LF ? - JNZ T2S_End_Of_File ; +T2S_Wait_LF ; warning! EOT is followed by CR+LF, because I2C_Master uses LF to switch from TX to RX ; ----------------------------------; - MOV W,&BufferPtr ;3 - CALL #CloseHandleT ;4 - MOV @RSP+,IP ; moved here because ASMtoFORTH use above + CMP.B IP,&TERM_RXBUF ; and also clears RX_IFG ! + JNZ T2S_Wait_LF ; +; ----------------------------------; here I2C_Master switches from TX to RX + MOV W,&BufferPtr ; to add it to HDLL_CurSize + CALL #CloseHandle ; tranfert SD_BUF to last sector of opened file in SD_CARD then close it +; ----------------------------------; + MOV @RSP+,IP ; MOV @IP+,PC ; ; ----------------------------------; diff --git a/forthMSP430FR_TERM_HALF.asm b/forthMSP430FR_TERM_HALF.asm index a28736b..e051b3e 100644 --- a/forthMSP430FR_TERM_HALF.asm +++ b/forthMSP430FR_TERM_HALF.asm @@ -1,40 +1,38 @@ ; -*- coding: utf-8 -*- - +; ; --------------------------------------- -; TERMINAL driver for FastForth target +; UART TERMINAL driver for FastForth target ; --------------------------------------- -; +---------------------------+ -; ------ | +-----------------+ | -; WIRING | | +--------+ | | -; ------ | | | | | | -; FastForth target TXD RXD RTS <--> CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL -; ----------------------------------------------------------------------------------------- -; MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE -; MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD -; MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 -; MSP_EXP430FR6989 P3.4 P3.5 P3.0 -; MSP_EXP430FR4133 P1.0 P1.1 P2.3 -; CHIPSTICK_FR2433 P1.4 P1.5 P3.2 -; MSP_EXP430FR2433 P1.4 P1.5 P1.0 +; +; +---------------------------------------+ +; | +-----------------------------+ | +; | | +------(option)-----+ | | +; | | | | | | +; FastForth target: TXD RXD RTS connected to : CTS TXD RXD of UARTtoUSB <--> COMx <--> TERMINAL +; ---------------- --- --- --- --- --- --- ------------------------------------- +; MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE +; MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD +; MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 +; MSP_EXP430FR6989 P3.4 P3.5 P3.0 +; MSP_EXP430FR4133 P1.0 P1.1 P2.3 +; CHIPSTICK_FR2433 P1.4 P1.5 P3.2 +; MSP_EXP430FR2433 P1.4 P1.5 P1.0 ; MSP_EXP430FR2355 P4.3 P4.2 P2.0 ; LP_MSP430FR2476 P1.4 P1.5 P6.1 - - +; ;------------------------------------------------------------------------------- -; UART TERMINAL: QABORT ABORT_TERM COLD_TERM INI_TERM RXON RXOFF +; UART TERMINAL: QABORT COLD_TERM INIT_TERM RXON RXOFF ;------------------------------------------------------------------------------- -; define run-time part of ABORT" -;Z ?ABORT xi f c-addr u -- abort & print msg. -; FORTHWORD "?ABORT" + +; define run-time part of ABORT" ; if f is true display msg. then abort current process QABORT CMP #0,2(PSP) ; -- f c-addr u test flag f - JNZ ABORT_TERM ; + JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below THREEDROP ADD #4,PSP ; -- u - MOV @PSP+,TOS ; -- - MOV @IP+,PC ; + JMP DROP ; ; ----------------------------------; -ABORT_TERM ; exit from downloading file then reinit some variables via INI_FORTH +UART_ABORT_TERM ; exit from downloading then reinit some variables via INIT_FORTH ; ----------------------------------; - CALL #RXON ; PFA resume downloading source file if any +ABORT_TERM CALL #RXON ; resume downloading source file if any A_UART_LOOP BIC #RX_TERM,&TERM_IFG ; clear RX_TERM MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 240000 A_USB_LOOPJ MOV #65,X ; 2~ <-------+ linux with minicom seems very very slow... @@ -44,49 +42,31 @@ A_USB_LOOPI SUB #1,X ; 1~ <---+ | ==> ((65*3)+5)*1000 = JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+ BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after A_USB_LOOPJ delay ? JNZ A_UART_LOOP ; 2 yes, the input stream is still active: loop back - CALL #INI_FORTH ; common ?ABORT|RST subroutine -; ----------------------------------; - .word lit,LINE,FETCH ; -- f c-addr u line fetch line number before set ECHO ! - .word ECHO ; + CALL #INIT_FORTH ; common ?ABORT|PUC subroutine to init DEFERed definitions + ; cnt is a byte, always positive. If cnt = 0 no RST_RET. + .word DUP ; + .word QFBRAN,ABORT_END; display nothing, don't force ECHO if ABORT" empty string + .word ECHO ; force ECHO .word XSQUOTE ; - .byte 4,27,"[7m" ; type ESC[7m (set reverse video) - .word TYPE ; -; ----------------------------------; - .word QDUP,QFBRAN ; do nothing if line = 0 - .word ABORT_TYPE ; + .byte 4,27,"[7m" ; + .word TYPE ; type ESC [7m (set reverse video) ; ----------------------------------; -; Display error "line:xxx" ; -- f c-addr u line +; Display QABORT|WARM message ; <== WARM jumps here ; ----------------------------------; - .word XSQUOTE ; -- f c-addr u line c-addr1 u1 displays the line where error occured - .byte 15,"LAST.4TH, line " ; - .word TYPE ; -- f c-addr u line - .word UDOT ; -- f c-addr u -; ----------------------------------; -; Display ABORT message ; <== WARM jumps here -; ----------------------------------; -ABORT_TYPE .word TYPE ; -- f type abort message +ABORT_TYPE .word TYPE ; -- f type QABORT|WARM message .word XSQUOTE ; -- f c-addr u .byte 4,27,"[0m" ; - .word TYPE ; -- f set normal video - .word ABORT ; no return - - -; ----------------------------------; -COLD_TERM ; default STOP_APP: wait TERMINAL idle -; ----------------------------------; -UART_COLD_TERM - BIT #1,&TERM_STATW ;3 - JNZ COLD_TERM ;2 loop back while TERM_UART is busy - MOV @RSP+,PC ; return to software_BOR + .word TYPE ; -- f set normal video +ABORT_END .word ABORT ; -- f no return ; ----------------------------------; +;------------------------------------------------------------------------------- +; INIT TERMinal then enable I/O ; +;------------------------------------------------------------------------------- +UART_INIT_TERM ; see MSP430FRxxxx.pat file ; ----------------------------------; -INIT_TERM ; TOS = RSTIV_MEM -; ----------------------------------; -UART_INIT_TERM ; - CMP #2,TOS ; - JNC UART_INIT_TERM_END ; no INIT_TERM if RSTIV_MEM U< 2 (WARM) -; ----------------------------------; +INIT_TERM ; TOS = USERSYS, don't change it + CALL #COLD_TERM ; wait while TERM_UART is busy MOV #0081h,&TERM_CTLW0 ; UC SWRST + UCLK = SMCLK MOV &TERMBRW_RST,&TERM_BRW ; init value in FRAM MOV &TERMMCTLW_RST,&TERM_MCTLW ; init value in FRAM @@ -94,118 +74,129 @@ UART_INIT_TERM ; BIC #1,&TERM_CTLW0 ; release UC_TERM from reset... BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on terminal input BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings. -UART_INIT_TERM_END MOV @RSP+,PC ; RET ; ----------------------------------; - -; ----------------------------------; -RXON ; default BACKGND_APP -; ----------------------------------; -UART_RXON JMP RXON_EXE ; Software and/or hardware flow control, to start Terminal UART for one line -; ----------------------------------; - ; ----------------------------------; -RXOFF ; Software and/or hardware flow control, to stop Terminal UART comunication +UART_COLD_TERM ; default STOP_APP: wait TERMINAL idle ; ----------------------------------; -UART_RXOFF ; - .IFDEF TERMINAL3WIRES ; first software flow control -RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char - JZ RXOFF_LOOP ;2 - MOV #19,&TERM_TXBUF ;4 move XOFF char into TX_buf - .ENDIF ; - .IFDEF TERMINAL4WIRES ; and hardware flow control after - BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high - .ENDIF ; - MOV @RSP+,PC ;4 to CR_NEXT, ...or user defined +WAIT_UART_IDLE +COLD_TERM BIT #1,&TERM_STATW ;3 uart busy ? + JNZ COLD_TERM ;2 loop back while TERM_UART is busy ; ----------------------------------; - +UART_INIT_SOFT ; ; ----------------------------------; -RXON_EXE +INIT_SOFT_TERM + MOV @RSP+,PC ; does nothing by default ; ----------------------------------; - .IFDEF TERMINAL3WIRES ; first software flow control -RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates - JZ RXON_LOOP ;2 - MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf - .ENDIF ; - .IFDEF TERMINAL4WIRES ; and hardware flow control after - BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low - .ENDIF ; - MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD... -; ----------------------------------; ... (get next line of file downloading), or user defined - -;=============================================================================== - FORTHWORD "WIPE" ; software DEEP_RESET -;=============================================================================== -WIPE MOV #-1,&RSTIV_MEM ; negative value ==> DEEP_RESET - JMP COLD - -;=============================================================================== - FORTHWORD "COLD" -;=============================================================================== -;Z COLD -- performs a software RESET -; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector -; that allows actions to be performed before executing software BOR. -COLD CALL @PC+ ; COLD first calls STOP_APP, in this instance: CALL #COLD_TERM by default -PFACOLD .word COLD_TERM ; INI_COLD_DEF: default value set by WIPE. see forthMSP430FR_TERM_xxxx.asm - BIT.B #IO_WIPE,&WIPE_IN ; hardware Deep_RESET request (low) ? - JNZ COLDEXE ; no - MOV #-1,&RSTIV_MEM ; yes, set negative value to force DEEP_RESET -COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR, see RESET in forthMSP430FR.asm -; ----------------------------------; - -;-----------------------------------; - FORTHWORD "WARM" ; -;-----------------------------------; -;Z WARM xi -- ; the end of RESET -;-----------------------------------; -WARM ; ;------------------------------------------------------------------------------- -; RESET 7: if RSTIV_MEM <> WARM, init TERM and enable I/O +; UART TERMINAL : WARM SYS COLD ;------------------------------------------------------------------------------- - CALL @PC+ ; init TERM, only if TOS U>= 2 (RSTIV_MEM <> WARM) - .IFNDEF SD_CARD_LOADER ; -PFAWARM .word INIT_TERM ; INI_HARD_APP default value, init TERM UC, unlock I/O's, TOS = RSTIV_MEM - .ELSE -PFAWARM .word INI_HARD_SD ; init SD Card + init TERM, see forthMSP430FR_SD_INIT.asm - .ENDIF ; TOS = RSTIV_MEM -;-----------------------------------; -WARM_DISPLAY ; TOS = RSTIV_MEM value - ASMtoFORTH +; ----------------------------------; thanks to INIT_FORTH, WARM implements the choice +UART_WARM ; made by the user with SYS|hardwareRST|DEEP_reset +;-----------------------------------; regarding the state of the software. +WARM CALL &HARD_APP ; + mASM2FORTH ; + .word ECHO ; .word XSQUOTE .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + # .word TYPE - .word DOT ; display TOS = RSTIV_MEM value + .word DOT ; display TOS = USERSYS value .word XSQUOTE - .byte 25,"FastForth ©J.M.Thoorens " + .byte 25,"FastForth ",169,"J.M.Thoorens, " .word TYPE - .word LIT,FRAM_FULL,HERE,MINUS,UDOT + .word LIT,FRAM_FULL + .word HEREXEC,MINUS,UDOT .word XSQUOTE .byte 10,"bytes free" - .word BRAN,ABORT_TYPE ; without return + .word BRAN,ABORT_TYPE ; without return! +;-----------------------------------; + +;-----------------------------------; + FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM +;-----------------------------------; + CMP #0,TOS ; + JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET + JZ NOPUC ; if [0] SYS + BIT #1,TOS ; + JNC SYSEND ; if +n SYS (+n even) +NOPUC PUSH #WARM ; + PUSH RSP ; Push address of WARM address + JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display +SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display +;=============================================================================== +COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET) +;=============================================================================== +; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector +; that allows actions to be performed before executing software BOR. + CALL &COLD_APP ; to stop APPlication before reset + BIT.B #SW1,&SW1_IN ; <SW1> pressed ? + JNZ COLDEXE ; no + MOV #-1,&USERSYS ; yes, set negative value to force DEEP_RESET +COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+ +;=============================================================================== | +RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+ +;=============================================================================== +; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET +;------------------------------------------------------------------------------- + BIS #3,&SFRRPCR ; pin RST becomes pin NMI with falling edge, so SYSRSTIV = 4 + BIS #10h,&SFRIE1 ; enable NMI interrupt ==> hardware RESET is redirected to COLD. + MOV #5A80h,&WDTCTL ; disable WDT RESET +;------------------------------------------------------------------------------- +; PUC 2: INIT STACK +;------------------------------------------------------------------------------- + MOV #RSTACK,RSP ; init return stack + MOV #PSTACK,PSP ; init parameter stack +;------------------------------------------------------------------------------- +; PUC 3: I/O, RAM, RTC, CS, SYS initialisation limited to FastForth usage. +; All unused I/O are set as input with pullup resistor. +;------------------------------------------------------------------------------- + .include "TargetInit.asm" ; include target specific init code +;------------------------------------------------------------------------------- +; PUC 4: init RAM to 0 +;------------------------------------------------------------------------------- + MOV #RAM_LEN,X ; 2 RAM_LEN must be even and > 1, obviously. +INITRAMLOOP SUB #2,X ; 1 + MOV #0,RAM_ORG(X) ; 3 + JNZ INITRAMLOOP ; 2 6 cycles loop ! +;------------------------------------------------------------------------------- +; PUC 5: GET SYSRSTIV and SYS_USER ; X = 0 +;------------------------------------------------------------------------------- + MOV &SYSRSTIV,X ; X <-- SYSRSTIV <-- 0 + MOV &USERSYS,TOS ; TOS = USERSYS + MOV #0,&USERSYS ; clear USERSYS + AND #-1,TOS ; + JNZ PUC6 ; if TOS <> 0, keep USERSYS value + MOV X,TOS ; TOS <-- SYSRSTIV +;------------------------------------------------------------------------------- +; PUC 6: START FORTH engine +;------------------------------------------------------------------------------- +PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC +PUCNEXT .WORD WARM ; no return. May be redirected by BOOT. +;-----------------------------------; ;------------------------------------------------------------------------------- -; INTERPRETER INPUT +; INTERPRETER INPUT: ACCEPT KEY EMIT ECHO NOECHO ;------------------------------------------------------------------------------- FORTHWORD "ACCEPT" +;-----------------------------------; ;https://forth-standard.org/standard/core/ACCEPT ;C ACCEPT addr addr len -- addr len' get line at addr to interpret len' chars ACCEPT MOV @PC+,PC ;3 Code Field Address (CFA) of ACCEPT PFAACCEPT .word BODYACCEPT ; Parameter Field Address (PFA) of ACCEPT -BODYACCEPT ; BODY of ACCEPT = default execution of ACCEPT ; ----------------------------------; ; ACCEPT part I prepare TERMINAL_INT; ; ----------------------------------; - MOV TOS,X ;1 -- addr len +BODYACCEPT MOV TOS,X ;1 -- addr len MOV @PSP,TOS ;2 -- org ptr ADD TOS,X ;1 -- org ptr X = buf_end MOV #0Dh,W ;2 W = 'CR' to speed up char loop in part II MOV #20h,T ;2 T = 'BL' to speed up char loop in part II MOV IP,S ; S = ACCEPT_ret - MOV #CR_NEXT,IP ;2 IP = XOFF_ret + MOV #CR_NEXT,IP ;2 IP = XOFF_ret PUSHM #5,IP ;5 PUSHM IP,S,T,W,X r-- XOFF_ret ACCEPT_ret BL CR buf_end - JMP SLEEP ;2 which calls RXON before falling down to LPMx mode + JMP SLEEP ;2 ; ----------------------------------; ; **********************************; @@ -214,18 +205,26 @@ TERMINAL_INT ; <--- TEMR RX interrupt vector, delayed by ; (ACCEPT) part II under interrupt ; Org Ptr -- len' ; ----------------------------------; ADD #4,RSP ;1 remove SR and PC from stack, SR flags are lost (unused by FORTH interpreter) - POPM #4,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=ACCEPT_RET r-- XOFF_ret -; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv; -; starts the 2th stopwatch ; -; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; + POPM #3,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=ACCEPT_RET r-- XOFF_ret +; ----------------------------------; AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared ; ----------------------------------; CMP.B T,Y ;1 CR ? - JZ RXOFF ;2 then RET to CR_NEXT -; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv;+ 12 to send RXOFF -; stops the first stopwatch ;= first bottleneck, best case result: 25~ + LPMx wake_up time.. -; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; - CMP.B S,Y ;1 printable char ? + JNZ AKEYRDNNEXT ;2 no +; ----------------------------------; +RXOFF ; Software|hardware flow control to stop RX UART r-- ACCEPT_ret CR_NEXT +; ----------------------------------; + .IFDEF TERMINAL3WIRES ; first software flow control +RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char + JZ RXOFF_LOOP ;2 + MOV #19,&TERM_TXBUF ;4 move XOFF char into TX_buf + .ENDIF ; + .IFDEF TERMINAL4WIRES ; and hardware flow control after + BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high + .ENDIF ; + MOV @RSP+,PC ;4 to CR_NEXT +; ----------------------------------; +AKEYRDNNEXT CMP.B S,Y ;1 printable char ? JC ASTORETEST ;2 yes ; ----------------------------------; CMP.B #8,Y ;1 char = BS ? @@ -241,37 +240,24 @@ AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleare ; end of backspace ; ; ----------------------------------; ASTORETEST CMP W,TOS ; 1 Bound is reached ? - JZ YEMIT ; 2 yes: send echo then loopback - MOV.B Y,0(TOS) ; 3 no: store char @ Ptr, send echo then loopback + JC YEMIT ; 2 yes: don't store char @ Ptr, don't increment TOS + MOV.B Y,0(TOS) ; 3 no: store char @ Ptr ADD #1,TOS ; 1 increment Ptr ; ----------------------------------; WAITaKEY BIT #RX_TERM,&TERM_IFG ; 3 new char in TERMRXBUF ? JNZ AKEYREAD ; 2 yes -; vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv; -; stops the 2th stopwatch ; best case result: 26~/22~ (with/without echo) ==> 385/455 kBds/MHz -; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^; JZ WAITaKEY ; 2 no ; ----------------------------------; - -; ----------------------------------; ; return of RXOFF ; ----------------------------------; CR_NEXT SUB @PSP+,TOS ; -- len' -; ----------------------------------; - MOV #LPM0+GIE,&LPM_MODE ; reset LPM_MODE to default mode LPM0 for next line of input stream -; ----------------------------------; WAITLF BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ? JZ WAITLF ; no MOV.B &TERM_RXBUF,Y ; yes, clear RX_int flag after LF received ; ----------------------------------; -ACCEPT_EOL CMP #0,&LINE ; if LINE <> 0 increment LINE - JZ ACCEPT_END ; - ADD #1,&LINE ; -ACCEPT_END -; ----------------------------------; - MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) - JMP YEMIT ; before interpret line -; **********************************; +ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) + JMP YEMIT ; before return to ABORT to interpret line +; **********************************; UF9 to UF11 are reset. ; ------------------------------------------------------------------------------ ; TERMINAL I/O, input part @@ -281,9 +267,22 @@ ACCEPT_END ; KEY -- c wait character from input device ; primary DEFERred word KEY MOV @PC+,PC ;4 Code Field Address (CFA) of KEY PFAKEY .word BODYKEY ; Parameter Field Address (PFA) of KEY, with default value -BODYKEY SUB #2,PSP ;1 push old TOS.. +BODYKEY PUSH #KEYNEXT ; +; ----------------------------------; +RXON ; default BACKGND_APP +; ----------------------------------; + .IFDEF TERMINAL3WIRES ; first software flow control +RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates + JZ RXON_LOOP ;2 + MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf + .ENDIF ; + .IFDEF TERMINAL4WIRES ; and hardware flow control after + BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low + .ENDIF ; + MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD... +; ----------------------------------; ... (get next line of file downloading), or user defined +KEYNEXT SUB #2,PSP ;1 push old TOS.. MOV TOS,0(PSP) ;3 ..onto stack - CALL #RXON KEYLOOP BIT #RX_TERM,&TERM_IFG ; loop if bit0 = 0 in interupt flag register JZ KEYLOOP ; MOV &TERM_RXBUF,TOS ; @@ -306,18 +305,16 @@ YEMIT BIT #TX_TERM,&TERM_IFG ; 3 wait the sending end of previous char, u YEMIT1 BIT.B #CTS,&HANDSHAKIN ; JNZ YEMIT1 .ENDIF -QYEMIT .word 48C2h ;3 48C2h = MOV.B Y,&<next_adr> - .word TERM_TXBUF ; 3 MOV Y,&TERMTXBUF +QYEMIT MOV.B Y,&TERM_TXBUF ; 3 may be replaced by MOV @IP+,PC with NOECHO MOV @IP+,PC ; FORTHWORD "ECHO" ;Z ECHO -- connect terminal output (default) ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr> - MOV #0,&LINE ; MOV @IP+,PC FORTHWORD "NOECHO" ;Z NOECHO -- disconnect terminal output NOECHO MOV #NEXT,&QYEMIT ; NEXT = 4030h = MOV @IP+,PC - MOV #1,&LINE ; MOV @IP+,PC + diff --git a/forthMSP430FR_TERM_I2C.asm b/forthMSP430FR_TERM_I2C.asm index 2bda341..3316ab5 100644 --- a/forthMSP430FR_TERM_I2C.asm +++ b/forthMSP430FR_TERM_I2C.asm @@ -1,177 +1,200 @@ ; -*- coding: utf-8 -*- - - +; ; --------------------------------------------------- ; TERMINAL driver for I2CFastForth target (I2C Slave) ; --------------------------------------------------- - -; hardware Software -; I2C Slave I2C Master -; -; I2CFastForth target SCL SDA connected to: SCL SDA of UART to I2C bridge -; ------------------ ---- ---- ---- ---- ------------------ -; MSP_EXP430FR5739 P1.7 P1.6 P4.1 P4.0 MSP_EXP430FR5739 -; MSP_EXP430FR5969 P1.7 P1.6 P1.3 P1.2 MSP_EXP430FR5969 -; MSP_EXP430FR5994 P7.1 P7.0 P8.1 P8.2 MSP_EXP430FR5994 -; MSP_EXP430FR6989 P1.7 P1.6 P1.5 P1.3 MSP_EXP430FR6989 -; MSP_EXP430FR4133 P5.3 P5.2 P8.3 P8.2 MSP_EXP430FR4133 -; CHIPSTICK_FR2433 P1.3 P1.2 P2.2 P2.0 CHIPSTICK_FR2433 -; MSP_EXP430FR2433 P1.3 P1.2 P3.1 P3.2 MSP_EXP430FR2433 -; MSP_EXP430FR2355 P1.3 P1.2 P3.3 P3.2 MSP_EXP430FR2355 -; LP_MSP430FR2476 P4.3 P4.4 P3.3 P3.2 LP_MSP430FR2476 +; | +; | GND------------------------------GND +; | Vcc-------------o---o------------Vcc +; | | | +; | 3 3 +; | k k +; v 3 3 +; I2C_FastForth | | UARTI2C +---------------------------------------+ +; hardware +--------------|---o-------------+ Software | +-----------------------------+ | +; I2C Slave | +-------o----------+ | I2C Master | | +------(option)-----+ | | +; | | | | | | | | | | +; I2CFastForth target SCL SDA connected to: SDA SCL of UART to I2C bridge TXD RXD RTS connected to : CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL +; ------------------ ---- ---- ---- ---- ------------------ --- --- --- --- --- --- ------------------------------------- +; MSP_EXP430FR5739 P1.7 P1.6 P4.0 P4.1 MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE +; MSP_EXP430FR5969 P1.7 P1.6 P1.2 P1.3 MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD +; MSP_EXP430FR5994 P7.1 P7.0 P8.2 P8.1 MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 +; MSP_EXP430FR6989 P1.7 P1.6 P1.3 P1.5 MSP_EXP430FR6989 P3.4 P3.5 P3.0 +; MSP_EXP430FR4133 P5.3 P5.2 P8.2 P8.3 MSP_EXP430FR4133 P1.0 P1.1 P2.3 +; CHIPSTICK_FR2433 P1.3 P1.2 P2.0 P2.2 CHIPSTICK_FR2433 P1.4 P1.5 P3.2 +; MSP_EXP430FR2433 P1.3 P1.2 P3.2 P3.1 MSP_EXP430FR2433 P1.4 P1.5 P1.0 +; MSP_EXP430FR2355 P1.3 P1.2 P3.2 P3.3 MSP_EXP430FR2355 P4.3 P4.2 P2.0 +; LP_MSP430FR2476 P4.3 P4.4 P3.2 P3.3 LP_MSP430FR2476 P1.4 P1.5 P6.1 ; ; don't forget to link 3V3 and GND on each side and to add 3k3 pullup resistors on SDA and SCL. - +; ;------------------------------------------------------------------------------- -; I2C TERMINAL: QABORT ABORT_TERM INI_TERM COLD_TERM RXON I2C_CTRL_CH +; I2C TERMINAL: QABORT ABORT_TERM INIT_TERM COLD_TERM RXON I2C_CTRL_CH ;------------------------------------------------------------------------------- -; define run-time part of ABORT" -;Z ?ABORT xi f c-addr u -- abort & print msg. -; FORTHWORD "?ABORT" -QABORT CMP #0,2(PSP) ; -- f c-addr u test flag f - JNZ ABORT_TERM ; -THREEDROP ADD #4,PSP ; -- u - MOV @PSP+,TOS ; -- - MOV @IP+,PC ; -; ----------------------------------; -ABORT_TERM ; exit from downloading then reinit some variables via INI_FORTH -; ----------------------------------; - MOV.B #2,Y ; -- f c-addr u ABORT request Ctrl_Char = $02 - CALL #I2C_CTRL_CH ; send it to I2C_Master which will run QABORT_TERM on its side -; ----------------------------------; - PUSH TOS ; - CALL #INI_FORTH ; -; ----------------------------------; -; display line of error if NOECHO ; -; ----------------------------------; - .word lit,LINE,FETCH ; -- f c-addr u line fetch line number before set ECHO ! - .word ECHO ; - .word RFROM ; -- f c-addr u line u - .word QFBRAN,ABORT_END; display nothing if ABORT" with empty string - .word XSQUOTE ; -- f c-addr u line + +; ?ABORT defines run-time part of ABORT" +QABORT CMP #0,2(PSP) ; -- f addr cnt if f is true abort current process then display ABORT" msg. + JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below +THREEDROP ADD #4,PSP ; -- cnt + JMP DROP ; +; ----------------------------------; +I2C_ABORT_TERM ; exit from downloading then reinit FORTH variables via INIT_FORTH +; ----------------------------------; +ABORT_TERM MOV #2,Y ; send $02 as Ctrl_Char ?ABORT + CALL #I2C_CTRL_CH ; + CALL #INIT_FORTH ; common ?ABORT|PUC subroutine to init DEFERed definitions + INIT_FORTH + .word DUP ; -- f addr cnt cnt + .word QFBRAN,ABORT_END; -- f addr 0 if cnt = 0 display nothing + .word ECHO ; force ECHO + .word XSQUOTE ; .byte 5,27,"[7m",'@' ; .word TYPE ; cmd "reverse video" + displays "@" .word LIT,I2CSLAVEADR ; - .word FETCH,DOT ; displays <I2C_Slave_Address> - .word QDUP,QFBRAN ; don't display line if line = 0 (ECHO was ON) - .word ABORT_TYPE ; - .word XSQUOTE ; -- f c-addr u line c-addr1 u1 displays the line where error occured - .byte 15,"LAST.4TH, line " ; - .word TYPE ; -- f c-addr u line - .word UDOT ; -- f c-addr u -; ----------------------------------; -; Display ABORT|WARM message ; <== WARM jumps here -; ----------------------------------; -ABORT_TYPE .word TYPE ; -- f display abort|warm message - .word XSQUOTE ; -- f c-addr u + .word FETCH,DOT ; displays I2C_Slave_Address<<1 +; ----------------------------------; +; Display ABORT|WARM message ; -- f addr cnt <== WARM jumps here +; ----------------------------------; +ABORT_TYPE .word TYPE ; -- f display QABORT|WARM message + .word XSQUOTE ; .byte 4,27,"[0m" ; - .word TYPE ; -- f set normal video -ABORT_END .word ABORT ; -- f no return + .word TYPE ; set normal video +ABORT_END .word ABORT ; -- f|f addr 0 no return ; ----------------------------------; +RXON ; called by SLEEP before CPU sleeping down. ; ----------------------------------; -INIT_TERM ; TOS = RSTIV_MEM -; ----------------------------------; -I2C_INIT_TERM - CMP #2,TOS ; - JNC I2C_INIT_TERM_END ; no INIT_TERM if RSTIV_MEM U< 2 (WARM) +I2C_ACCEPT MOV.B #0,Y ; ACCEPT request Ctrl_Char = $00 ; ----------------------------------; - BIS #07C0h,&TERM_CTLW0 ; set I2C_Slave in RX mode to receive I2C_address - MOV &I2CSLAVEADR,Y ; init value found in FRAM INFO - RRA Y ; I2C Slave address without R/W bit - BIS #400h,Y ; enable I2COA0 Slave address - MOV Y,&TERM_I2COA0 ; - BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_I2C - BIC #1,&TERM_CTLW0 ; release UC_TERM from reset... - BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on terminal input - BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings. -I2C_INIT_TERM_END +I2C_CTRL_CH BIT #TX_TERM,&TERM_IFG ; send it to I2C_Master_RX to restart it in TX mode + JZ I2C_CTRL_CH ; wait TX buffer empty + MOV.B Y,&TERM_TXBUF ; send Ctrl_Char +WAITCHAREND BIT #4,&TERM_IFG ; I2C_Master (re)STARTed ? + JZ WAITCHAREND ; loop back if no ; ----------------------------------; -COLD_TERM ; nothing to do +I2C_COLD_TERM ; ----------------------------------; - MOV @RSP+,PC ; +COLD_TERM ; does nothing by default ; ----------------------------------; - - +I2C_INIT_SOFT ; ; ----------------------------------; -RXON ; send ctrl_char $00 as ACCEPT request +INIT_SOFT_TERM + MOV @RSP+,PC ; does nothing by default ; ----------------------------------; -I2C_RXON MOV.B #0,Y ; ACCEPT request Ctrl_Char = $00 +;------------------------------------------------------------------------------- +; INIT TERMinal then enable I/O +;------------------------------------------------------------------------------- ; ----------------------------------; -I2C_CTRL_CH ; send it to I2C_Master_RX to restart it in TX mode +I2C_INIT_TERM ; ; ----------------------------------; - BIT #TX_TERM,&TERM_IFG ;3 - JZ I2C_CTRL_CH ;2 wait TX buffer empty - MOV.B Y,&TERM_TXBUF ;3 send Ctrl_Char -WAITCHAREND - BIT #4,&TERM_IFG ; I2C_Master (re)STARTed ? - JZ WAITCHAREND ; no +INIT_TERM ; TOS = USERSYS, don't change + BIS #07C0h,&TERM_CTLW0 ; set I2C_Slave in RX mode to receive I2C_address + MOV &I2CSLAVEADR,Y ; init value found in FRAM INFO + RRA Y ; I2C Slave address without R/W bit + BIS #400h,Y ; enable I2COA0 Slave address + MOV Y,&TERM_I2COA0 ; + BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_I2C + BIC #1,&TERM_CTLW0 ; release UC_TERM from reset... + BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on START + BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings. MOV @RSP+,PC ; ; ----------------------------------; -; I2C_CTRL_CHAR sends a CTRL_Char that asks I2C_Master RX to (re)START in TX mode. -; As TI tells nothing about I2C_Slave UCSTTIFG ON --> OFF, -; it is assumed that the Slave clears itself UCSTTIFG after the first character has been exchanged. ;------------------------------------------------------------------------------- -; I2C TERMINAL : WIPE COLD WARM ACCEPT KEY EMIT ECHO NOECHO +; I2C TERMINAL : WARM SYS COLD ;------------------------------------------------------------------------------- ;-----------------------------------; - FORTHWORD "WIPE" ; software DEEP_RESET -;-----------------------------------; -WIPE MOV #-1,&RSTIV_MEM ; negative value forces DEEP_RESET - JMP COLD - -; ----------------------------------; - FORTHWORD "COLD" ; performs a software reset -; ----------------------------------; -; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector -; that allows specific actions before executing software BOR. -COLD CALL @PC+ ; COLD first calls STOP_APP, in this instance: CALL #COLD_TERM by default -PFACOLD .word COLD_TERM ; PFACOLD default value set by WIPE. -BODYCOLD BIT.B #IO_WIPE,&WIPE_IN ; hardware Deep_RESET request (low) ? - JNZ COLDEXE ; no - MOV #-1,&RSTIV_MEM ; yes, set negative value to force DEEP_RESET -COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR --> RST_vector --> RESET in forthMSP430FR.asm -; ----------------------------------; - -;-----------------------------------; - FORTHWORD "WARM" ; +; FORTHWORD "WARM" ; (n) -- ;-----------------------------------; -;Z WARM xi -- ; the end of RESET -;-----------------------------------; -WARM ; -;------------------------------------------------------------------------------- -; RESET 7: if RSTIV_MEM <> WARM, init TERM and enable I/O -;------------------------------------------------------------------------------- - CALL @PC+ ; init TERM, only if TOS U>= 2 (RSTIV_MEM <> WARM) - .IFNDEF SD_CARD_LOADER ; -PFAWARM .word INIT_TERM ; INI_HARD_APP default value, init TERM UC, unlock I/O's, TOS = RSTIV_MEM - .ELSE -PFAWARM .word INI_HARD_SD ; init SD Card + init TERM, see forthMSP430FR_SD_INIT.asm - .ENDIF ; TOS = RSTIV_MEM +I2C_WARM ; ;-----------------------------------; -WARM_DISPLAY ; TOS = RSTIV_MEM value - MOV.B #3,Y ; WARM request Ctrl_Char = $03 - CALL #I2C_CTRL_CH ; send it to I2C_Master to reSTART in RX mode - ASMtoFORTH +WARM CALL &HARD_APP ; init HARD_APP, i.e. UART_TERMinal then unlock IO's + mASM2FORTH ; display a message then goto QUIT (without return): + .word ECHO ; .word XSQUOTE .byte 7,13,10,27,"[7m@" ; CR+LF + cmd "reverse video" + @ .word TYPE - .word LIT,I2CSLAVEADR,FETCH,DOT + .word LIT,I2CSLAVEADR,FETCH + .word DOT ; display decimal I2C_address<<1 .word LIT,'#',EMIT - .word DOT ; display signed RSTIV_MEM + .word DOT ; display signed USERSYS .word XSQUOTE - .byte 25,"FastForth ©J.M.Thoorens " + .byte 25,"FastForth ",169,"J.M.Thoorens, " .word TYPE - .word LIT,FRAM_FULL,HERE,MINUS,UDOT + .word LIT,FRAM_FULL + .word HEREXEC,MINUS,UDOT ; number of... .word XSQUOTE - .byte 10,"bytes free" - .word BRAN,ABORT_TYPE ; without return! + .byte 10,"bytes free" ; bytes free + .word BRAN,ABORT_TYPE ; no return +;-----------------------------------; -; ----------------------------------; - FORTHWORD "ACCEPT" +;-----------------------------------; + FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM +;-----------------------------------; + CMP #0,TOS ; + JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET + JZ NOPUC ; if [0] SYS + BIT #1,TOS ; + JNC SYSEND ; if +n SYS (+n even) +NOPUC PUSH #WARM ; push WARM address + PUSH RSP ; Push address of WARM address + JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display +SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display +;=============================================================================== +COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET) +;=============================================================================== +; as pin RST is replaced by pin NMI by RESET below, hardware RESET is redirected here via USER NMI vector +; that allows specific actions before executing software BOR: + CALL &COLD_APP ; to stop APPlication before reset + BIT.B #SW1,&SW1_IN ; <SW1> pressed ? + JNZ COLDEXE ; no + MOV #-1,&USERSYS ; yes, force USERSYS negative value to do DEEP_RESET +COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+ +;=============================================================================== | +RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+ +;=============================================================================== +; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET +;------------------------------------------------------------------------------- + BIS #3,&SFRRPCR ; pin RST becomes pin NMI with falling edge, so SYSRSTIV = 4 + BIS #10h,&SFRIE1 ; enable NMI interrupt ==> hardware RESET is redirected to COLD. + MOV #5A80h,&WDTCTL ; disable WDT RESET +;------------------------------------------------------------------------------- +; PUC 2: INIT STACK +;------------------------------------------------------------------------------- + MOV #RSTACK,RSP ; init return stack + MOV #PSTACK,PSP ; init parameter stack +;------------------------------------------------------------------------------- +; PUC 3: I/O, RAM, RTC, CS, SYS initialisation limited to FastForth usage. +; All unused I/O are set as input with pullup resistor. +;------------------------------------------------------------------------------- + .include "TargetInit.asm" ; include target specific init code +;------------------------------------------------------------------------------- +; PUC 4: init RAM to 0 +;------------------------------------------------------------------------------- + MOV #RAM_LEN,X ; 2 RAM_LEN must be even and > 1, obviously. +INITRAMLOOP SUB #2,X ; 1 + MOV #0,RAM_ORG(X) ; 3 + JNZ INITRAMLOOP ; 2 6 cycles loop ! +;------------------------------------------------------------------------------- +; PUC 5: GET SYSRSTIV and SYS_USER +;------------------------------------------------------------------------------- + MOV &USERSYS,TOS ; TOS = USERSYS + MOV #0,&USERSYS ; clear USERSYS + AND #-1,TOS ; + JNZ PUC6 ; if TOS <> 0, keep USERSYS value + MOV &SYSRSTIV,TOS ; TOS <-- SYSRSTIV <-- 0 +;------------------------------------------------------------------------------- +; PUC 6: START FORTH engine +;------------------------------------------------------------------------------- +PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC +PUCNEXT .WORD WARM ; no return. May be replaced by XBOOT. +;-----------------------------------; + +;------------------------------------------------------------------------------- +; INTERPRETER INPUT: ACCEPT KEY EMIT ECHO NOECHO +;------------------------------------------------------------------------------- + FORTHWORD "ACCEPT" ; ; ----------------------------------; ;https://forth-standard.org/standard/core/ACCEPT ;C ACCEPT addr addr len -- addr len' get line at addr to interpret len' chars @@ -185,29 +208,23 @@ BODYACCEPT ; BODY of ACCEPT = default execution of ACC MOV @PSP,TOS ;2 -- org ptr ) ADD TOS,W ;1 -- org ptr W=buf_end ) MOV #0Ah,T ;2 T = 'LF' to speed up char loop in part II > prepare stack and registers for TERMINAL_INT use - MOV #20h,S ;2 S = 'BL' to speed up char loop in part II ) - PUSHM #4,IP ;6 PUSH IP,S,T,W r-- IP, 'BL', 'LF', buf_end ) -;vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvv; -; BIC.B #LED1,&LED1_DIR ; Red led OFF, -; BIC.B #LED1,&LED1_OUT ; end of Slave TX -;^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^; - JMP SLEEP ; which calls RXON before goto sleep + MOV #20h,S ;2 S = 'BL' to speed up char loop in part II ) + PUSHM #4,IP ;6 PUSH IP,S,T,W R-- IP, 'BL', 'LF', buf_end ) + JMP SLEEP ;2 ; ----------------------------------; +; As TI says nothing about the reset of the UCSTTIFG flag by the I2C_Slave, +; it is assumed that it clears it as soon as the first byte has been exchanged. ; **********************************; -TERMINAL_INT ; <--- START interrupt vector, bus is stalled, waiting ACK first char by I2C_Slave RX +TERMINAL_INT ; down to LPM4 <--- START interrupt vector, bus is stalled, waiting ACK first char by I2C_Slave RX ; **********************************; ; (ACCEPT) part II under interrupt ; Org Ptr -- ; ----------------------------------; ADD #4,RSP ;1 remove SR and PC from stack, SR flags are lost (unused by FORTH interpreter) - BIC #WAKE_UP,&TERM_IFG ; clear UCSTTIFG before return to SLEEP (because not cleared by RX_TERM reading) + BIC #WAKE_UP,&TERM_IFG ; clear UCSTTIFG before return to SLEEP (instead of RXBUF access to clear it) BIT #10h,&TERM_CTLW0 ;4 test UCTR JNZ SLEEP ; if I2C_Master RX, loop back to SLEEP POPM #4,IP ;6 POPM IP=ret_IP,W=src_end,T=0Ah,S=20h -;vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvv; -; BIS.B #LED2,&LED2_OUT ; green led ON, -; BIS.B #LED2,&LED2_DIR ; start of Slave RX -;^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^; QNEWCHAR BIT #RX_TERM,&TERM_IFG ;3 test RX BUF IFG JZ QNEWCHAR ;2 wait RX BUF full ; ----------------------------------; @@ -219,90 +236,74 @@ AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read char into Y, RX_IFG is cleared, JC ASTORETEST ;2 jump if char U>= BL ; ----------------------------------; CMP.B #8,Y ; char = BS ? - JNZ QNEWCHAR ; case of all other control chars + JNZ QNEWCHAR ; case of all other control chars: skip it ; ----------------------------------; -; start of backspace ; made only by an human +; case of backspace ; made only by an human ; ----------------------------------; CMP @PSP,TOS ; Ptr = Org ? JZ QNEWCHAR ; yes: do nothing else SUB #1,TOS ; no : dec Ptr - JMP QNEWCHAR + JMP QNEWCHAR ; ; ----------------------------------; ASTORETEST CMP W,TOS ; 1 end of buffer is reached ? - JZ QNEWCHAR ; 2 yes: loopback + JC QNEWCHAR ; 2 yes: don't store char @ dst_Ptr, don't increment TOS MOV.B Y,0(TOS) ; 3 no: store char @ dst_Ptr ADD #1,TOS ; 1 increment dst_Ptr - JMP QNEWCHAR -; ----------------------------------; -LF_NEXT ; -- Org Ptr -; ----------------------------------; - SUB @PSP+,TOS ; -- len' -; ----------------------------------; -; MOV #LPMx+GIE,&LPM_MODE ; no need to redefine LPM_MODE because I2C START works down to LPM4 mode -; ----------------------------------; after the sent of 'LF', I2C_Master automaticaly reSTARTs in RX mode: - CALL #WAITCHAREND ; wait I2C_Master (re)START RX -;vvvvvvvvvvvvv OPTION vvvvvvvvvvvvvv; -; BIC.B #LED2,&LED2_DIR ; green led OFF, -; BIC.B #LED2,&LED2_OUT ; end of Slave RX -; BIS.B #LED1,&LED1_DIR ; Red led ON, -; BIS.B #LED1,&LED1_OUT ; start of Slave TX -;^^^^^^^^^^^^^ OPTION ^^^^^^^^^^^^^^; -ACCEPT_EOL CMP #0,&LINE ; - JZ ACCEPT_END ; - ADD #1,&LINE ; if LINE <> 0 increment LINE -ACCEPT_END ; -; ----------------------------------; - MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) + JMP QNEWCHAR ; +; ----------------------------------; +LF_NEXT SUB @PSP+,TOS ; -- len' +ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) JMP YEMIT ; before line interpreting ; **********************************; ; ----------------------------------; - FORTHWORD "KEY" + FORTHWORD "KEY" ; ; ----------------------------------; ; https://forth-standard.org/standard/core/KEY ; KEY -- c wait character from input device ; primary DEFERred word KEY MOV @PC+,PC ; Code Field Address (CFA) of KEY PFAKEY .word BODYKEY ; Param Field Address (PFA) of KEY, with its default value -BODYKEY SUB #2,PSP ; push old TOS.. +BODYKEY MOV.B #1,Y ; KEY request Ctrl_Char = $01 + CALL #I2C_CTRL_CH ; send it to I2C_Master to restart its UART in RX mode + SUB #2,PSP ; push old TOS.. MOV TOS,0(PSP) ; ..onto stack - MOV.B #1,Y ; KEY request Ctrl_Char = $01 - CALL #I2C_CTRL_CH ; send it to I2C_Master to restart UART in RX mode BKEYLOOP BIT #RX_TERM,&TERM_IFG ; received char ? JZ BKEYLOOP ; wait char received MOV &TERM_RXBUF,TOS ; -- char + CALL #RXON ; send Ctrl_Char $00 to I2C_Master to restart its UART in TX mode BKEYEND MOV @IP+,PC ; -- char +; ----------------------------------; ; ----------------------------------; - FORTHWORD "EMIT" + FORTHWORD "EMIT" ; ; ----------------------------------; ; https://forth-standard.org/standard/core/EMIT ; EMIT c -- output character to an output device ; primary DEFERred word EMIT MOV @PC+,PC ;3 Code Field Address (CFA) of EMIT PFAEMIT .word BODYEMIT ; Parameter Field Address (PFA) of EMIT, with its default value -BODYEMIT MOV TOS,Y ;1 sends character to the default output TERMINAL +BODYEMIT + MOV TOS,Y ;1 sends character to the default output TERMINAL MOV @PSP+,TOS ;2 YEMIT BIT #TX_TERM,&TERM_IFG ;3 JZ YEMIT ;2 wait TX buffer empty -QYEMIT .word 48C2h ;3 48C2h = MOV.B Y,&<next_adr> - .word TERM_TXBUF ; +QYEMIT MOV.B Y,&TERM_TXBUF ;3 may be replaced by MOV @IP+,PC with NOECHO YEMITEND MOV @IP+,PC ;4 11 words +; ----------------------------------; ; ----------------------------------; - FORTHWORD "ECHO" + FORTHWORD "ECHO" ; connect EMIT to TERMINAL (default) ; ----------------------------------; -;Z ECHO -- connect EMIT to TERMINAL (default) ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr> - MOV #0,&LINE ; MOV #5,Y ; ECHO request Ctrl_Char = $05 -ECHOEND CALL #I2C_CTRL_CH ; send it to I2C_Master to do it echo char to TERMINAL - MOV @IP+,PC +ECHOEND CALL #I2C_CTRL_CH ; + MOV @IP+,PC ; +; ----------------------------------; ; ----------------------------------; - FORTHWORD "NOECHO" + FORTHWORD "NOECHO" ; disconnect EMIT to TERMINAL ; ----------------------------------; -;Z NOECHO -- disconnect EMIT to TERMINAL -NOECHO MOV #4D30h,&QYEMIT ; NEXT = 4D30h = MOV @IP+,PC - MOV #1,&LINE ; +NOECHO MOV #4D30h,&QYEMIT ; NEXT = 4D30h = MOV @IP+,PC MOV #4,Y ; NOECHO request Ctrl_Char = $04 - JMP ECHOEND ; send it to I2C_Master, to not do it echo to TERMINAL + JMP ECHOEND ; +; ----------------------------------; diff --git a/forthMSP430FR_TERM_UART.asm b/forthMSP430FR_TERM_UART.asm index b1d80fa..647a8dc 100644 --- a/forthMSP430FR_TERM_UART.asm +++ b/forthMSP430FR_TERM_UART.asm @@ -1,228 +1,236 @@ ; -*- coding: utf-8 -*- ; - ; --------------------------------------- -; TERMINAL driver for FastForth target +; UART TERMINAL driver for FastForth target ; --------------------------------------- -; +---------------------------+ -; ------ | +-----------------+ | -; WIRING | | +--------+ | | -; ------ | | | | | | -; FastForth target TXD RXD RTS <--> CTS TXD RXD UARTtoUSB <--> COMx <--> TERMINAL -; ----------------------------------------------------------------------------------------- -; MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE -; MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD -; MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 -; MSP_EXP430FR6989 P3.4 P3.5 P3.0 -; MSP_EXP430FR4133 P1.0 P1.1 P2.3 -; CHIPSTICK_FR2433 P1.4 P1.5 P3.2 -; MSP_EXP430FR2433 P1.4 P1.5 P1.0 +; +; +---------------------------------------+ +; | +-----------------------------+ | +; | | +------(option)-----+ | | +; | | | | | | +; FastForth target: TXD RXD RTS connected to : CTS TXD RXD of UARTtoUSB <--> COMx <--> TERMINAL +; ---------------- --- --- --- --- --- --- ------------------------------------- +; MSP_EXP430FR5739 P2.0 P2.1 P2.2 PL2303TA TERATERM.EXE +; MSP_EXP430FR5969 P2.0 P2.1 P4.1 PL2303HXD/GC +; MSP_EXP430FR5994 P2.0 P2.1 P4.2 CP2102 +; MSP_EXP430FR6989 P3.4 P3.5 P3.0 +; MSP_EXP430FR4133 P1.0 P1.1 P2.3 +; CHIPSTICK_FR2433 P1.4 P1.5 P3.2 +; MSP_EXP430FR2433 P1.4 P1.5 P1.0 ; MSP_EXP430FR2355 P4.3 P4.2 P2.0 ; LP_MSP430FR2476 P1.4 P1.5 P6.1 ; ;------------------------------------------------------------------------------- -; UART TERMINAL: QABORT ABORT_TERM COLD_TERM INI_TERM RXON RXOFF +; UART TERMINAL: QABORT INIT_TERM COLD_TERM ;------------------------------------------------------------------------------- -; define run-time part of ABORT" -;Z ?ABORT xi f c-addr u -- abort & print msg. -; FORTHWORD "?ABORT" -QABORT CMP #0,2(PSP) ; -- f c-addr u test flag f - JNZ ABORT_TERM ; -THREEDROP ADD #4,PSP ; -- u - MOV @PSP+,TOS ; -- - MOV @IP+,PC ; -; ----------------------------------; -ABORT_TERM ; exit from downloading file then reinit some variables via INI_FORTH -; ----------------------------------; - CALL #RXON ; PFA resume downloading source file if any + +; this define run-time part of ABORT" if f is true display msg. then abort current process +QABORT CMP #0,2(PSP) ; -- f addr cnt test flag f + JNZ ABORT_TERM ; see forthMSP430FR_TERM_xxxx.asm below +THREEDROP ADD #4,PSP ; -- cnt + JMP DROP ; +; ----------------------------------; +UART_ABORT_TERM ; exit from downloading, execute INIT_FORTH then display message if any +; ----------------------------------; +ABORT_TERM CALL #RXON ; resume downloading source file if any A_UART_LOOP BIC #RX_TERM,&TERM_IFG ; clear RX_TERM - MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 240000 -A_USB_LOOPJ MOV #65,X ; 2~ <-------+ linux with minicom seems very very slow... -A_USB_LOOPI SUB #1,X ; 1~ <---+ | ==> ((65*3)+5)*1000 = 200ms delay - JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ | to refill its USB buffer + MOV &FREQ_KHZ,Y ; 1000, 2000, 4000, 8000, 16000, 24000 +A_USB_LOOPJ MOV #65,X ; 2~ <----+ linux with minicom seems very very slow... +A_USB_LOOPI SUB #1,X ; 1~ <--+ | to refill its USB buffer + JNZ A_USB_LOOPI ; 2~ 3~ loop ---+ | SUB #1,Y ; 1~ | - JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+ - BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after A_USB_LOOPJ delay ? + JNZ A_USB_LOOPJ ; 2~ 200~ loop -----+ ((65*3)+5)*1000 = 200ms delay + BIT #RX_TERM,&TERM_IFG ; 4 new char in TERMRXBUF after 200ms delay ? JNZ A_UART_LOOP ; 2 yes, the input stream is still active: loop back - CALL #INI_FORTH ; common ?ABORT|RST, "hybrid" subroutine with return to FORTH interpreter + CALL #INIT_FORTH ; common ?ABORT|PUC subroutine + ; TOS = cnt (byte), always positive. No RST_RET if cnt = 0. + .word DUP ; -- f addr cnt cnt + .word QFBRAN,ABORT_END; -- f addr 0 don't force ECHO if ABORT" is an empty string + .word ECHO ; -- f addr cnt force ECHO + .word XSQUOTE ; + .byte 4,27,"[7m" ; + .word TYPE ; ESC [7m = set reverse video ; ----------------------------------; -; display line of error if NOECHO ; +; Display QABORT|WARM message ; <== WARM jumps here ; ----------------------------------; - .word lit,LINE,FETCH ; -- f c-addr u line fetch line number before set ECHO ! - .word ECHO ; +ABORT_TYPE .word TYPE ; -- f type QABORT|WARM message .word XSQUOTE ; - .byte 4,27,"[7m" ; type ESC[7m (set reverse video) - .word TYPE ; - .word QDUP,QFBRAN ; don't display line if line = 0 (ECHO was ON) - .word ABORT_TYPE ; - .word XSQUOTE ; -- f c-addr u line c-addr1 u1 displays the line where error occured - .byte 15,"LAST.4TH, line " ; - .word TYPE ; -- f c-addr u line - .word UDOT ; -- f c-addr u -; ----------------------------------; -; Display ABORT|WARM message ; <== WARM jumps here -; ----------------------------------; -ABORT_TYPE .word TYPE ; -- f type abort message - .word XSQUOTE ; -- f c-addr u .byte 4,27,"[0m" ; - .word TYPE ; -- f set normal video - .word ABORT ; without return + .word TYPE ; ESC [0m = set normal video +ABORT_END .word ABORT ; -- f no return ; ----------------------------------; -; ----------------------------------; -COLD_TERM ; default STOP_APP: wait TERMINAL idle -; ----------------------------------; -UART_COLD_TERM ; - BIT #1,&TERM_STATW ;3 uart busy ? - JNZ COLD_TERM ;2 loop back while TERM_UART is busy - MOV @RSP+,PC ; return to software_BOR -; ----------------------------------; +;------------------------------------------------------------------------------- +; INIT TERMinal then enable I/O +;------------------------------------------------------------------------------- ; ----------------------------------; -INIT_TERM ; TOS = RSTIV_MEM -; ----------------------------------; UART_INIT_TERM ; - CMP #2,TOS ; - JNC UART_INIT_TERM_END ; no INIT_TERM if RSTIV_MEM U< 2 (WARM|ABORT) ; ----------------------------------; - MOV #0081h,&TERM_CTLW0 ; UC SWRST + UCLK = SMCLK +INIT_TERM + CALL #WAIT_UART_IDLE ; wait while TERM_UART is busy + MOV #0081h,&TERM_CTLW0 ; 8 bits, UC SWRST + UCLK = SMCLK, max 6MBds +; MOV #1081h,&TERM_CTLW0 ; 7 bits, UC SWRST + UCLK = SMCLK, max 4MBds MOV &TERMBRW_RST,&TERM_BRW ; init value in FRAM INFO MOV &TERMMCTLW_RST,&TERM_MCTLW ; init value in FRAM INFO BIS.B #BUS_TERM,&TERM_SEL ; Configure pins TERM_UART|TERM_I2C BIC #1,&TERM_CTLW0 ; release UC_TERM from reset... BIS #WAKE_UP,&TERM_IE ; then enable interrupt for wake up on terminal input BIC #LOCKLPM5,&PM5CTL0 ; activate all previous I/O settings. -UART_INIT_TERM_END MOV @RSP+,PC ; RET ; ----------------------------------; - -; ----------------------------------; -UART_RXON JMP RXON_EXE ; Software and/or hardware flow control, to start Terminal UART for one line -; ----------------------------------; - ; ----------------------------------; -RXOFF ; Software and/or hardware flow control, to stop Terminal UART comunication -; ----------------------------------; -UART_RXOFF ; - .IFDEF TERMINAL3WIRES ; first software flow control -RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char - JZ RXOFF_LOOP ;2 - MOV #19,&TERM_TXBUF ;4 move XOFF char into TX_buf - .ENDIF ; - .IFDEF TERMINAL4WIRES ; and hardware flow control after - BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high - .ENDIF ; - MOV @RSP+,PC ;4 to CR_NEXT, ...or user defined +UART_COLD_TERM ; default STOP_APP: wait TERMINAL idle ; ----------------------------------; - +WAIT_UART_IDLE +COLD_TERM BIT #1,&TERM_STATW ;3 uart busy ? + JNZ COLD_TERM ;2 loop back while TERM_UART is busy ; ----------------------------------; -RXON ; default BACKGND_APP +UART_INIT_SOFT ; ; ----------------------------------; -RXON_EXE +INIT_SOFT_TERM + MOV @RSP+,PC ; does nothing ; ----------------------------------; - .IFDEF TERMINAL3WIRES ; first software flow control -RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates - JZ RXON_LOOP ;2 - MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf - .ENDIF ; - .IFDEF TERMINAL4WIRES ; and hardware flow control after - BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low - .ENDIF ; - MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD... -; ----------------------------------; ... (get next line of file downloading), or user defined - ;------------------------------------------------------------------------------- -; UART TERMINAL : WIPE COLD WARM ACCEPT KEY EMIT ECHO NOECHO +; UART TERMINAL : WARM SYS COLD RESET ;------------------------------------------------------------------------------- ;-----------------------------------; - FORTHWORD "WIPE" ; software DEEP_RESET +; FORTHWORD "WARM" ; (n) -- +;-----------------------------------; thanks to INIT_FORTH, WARM implements the choice +UART_WARM ; made by the user with SYS|hardwareRST|DEEP_reset +;-----------------------------------; regarding the state of the software. +WARM CALL &HARD_APP ; + mASM2FORTH ; + .word ECHO ; + .word XSQUOTE + .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + # + .word TYPE + .word DOT ; display TOS = USERSYS value + .word XSQUOTE + .byte 25,"FastForth ",169,"J.M.Thoorens, " + .word TYPE + .word LIT,FRAM_FULL + .word HEREXEC,MINUS,UDOT + .word XSQUOTE + .byte 10,"bytes free" + .word BRAN,ABORT_TYPE ; without return ;-----------------------------------; -WIPE MOV #-1,&RSTIV_MEM ; negative value ==> DEEP_RESET - JMP COLD ;-----------------------------------; - FORTHWORD "COLD" + FORTHWORD "SYS" ; n -- software RST, DEEP_RST, COLD, WARM ;-----------------------------------; -;Z COLD -- performs a software RESET + CMP #0,TOS ; + JL SYSEND ; if -n SYS ==> COLD + DEEP_RESET + JZ NOPUC ; if [0] SYS ==> INIT_FORTH --> WARM --> WARM display + BIT #1,TOS ; + JNC SYSEND ; if +n SYS (+n even) +NOPUC PUSH #WARM ; + PUSH RSP ; Push address of WARM address + JMP INIT_FORTH ; if +n SYS (+n odd) ==> INIT_FORTH --> WARM --> WARM display +SYSEND MOV TOS,&USERSYS ; ==> COLD --> PUC --> INIT_FORTH --> WARM --> WARM display +;=============================================================================== +COLD ; <--- USER_NMI vector <--- <RESET> and <RESET> + <SW1> (DEEP_RESET) +;=============================================================================== ; as pin RST is replaced by pin NMI, RESET by pin activation is redirected here via USER NMI vector ; that allows actions to be performed before executing software BOR. -COLD CALL @PC+ ; COLD first calls STOP_APP, in this instance: CALL #COLD_TERM by default -PFACOLD .word COLD_TERM ; INI_COLD_DEF: default value set by WIPE. see forthMSP430FR_TERM_xxxx.asm - BIT.B #IO_WIPE,&WIPE_IN ; hardware Deep_RESET request (low) ? + CALL &COLD_APP ; to stop APPlication before reset + BIT.B #SW1,&SW1_IN ; <SW1> pressed ? JNZ COLDEXE ; no - MOV #-1,&RSTIV_MEM ; yes, set negative value to force DEEP_RESET -COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR --> RST_vector --> RESET in forthMSP430FR.asm -; ----------------------------------; - -;-----------------------------------; - FORTHWORD "WARM" ; -;-----------------------------------; -;Z WARM xi -- ; common part of WARM|PUC -;-----------------------------------; -WARM ; + MOV #-1,&USERSYS ; yes, set negative value to force DEEP_RESET +COLDEXE MOV #0A504h,&PMMCTL0 ; performs software_BOR ------------------------+ +;=============================================================================== | +RESET ; <-- RST vect. <-- SYS_failures PUC POR BOR <--+ +;=============================================================================== +; PUC 1: replace pin RESET by pin NMI, stops WDT_RESET ;------------------------------------------------------------------------------- -; PUC 7: if RSTIV_MEM <> WARM, init TERM and enable I/O + BIS #3,&SFRRPCR ; pin NMI with falling edge replaces pin RST, so SYSRSTIV = 4 + BIS #10h,&SFRIE1 ; enable NMI pin interrupt ==> hardware RESET is redirected to COLD. + MOV #5A80h,&WDTCTL ; disable WDT RESET ;------------------------------------------------------------------------------- - CALL @PC+ ; init TERM, only if TOS U>= 2 (RSTIV_MEM <> WARM) - .IFNDEF SD_CARD_LOADER ; -PFAWARM .word INIT_TERM ; INI_HARD_APP default value, init TERM UC, unlock I/O's, TOS = RSTIV_MEM - .ELSE -PFAWARM .word INI_HARD_SD ; init SD Card + init TERM, see forthMSP430FR_SD_INIT.asm - .ENDIF ; TOS = RSTIV_MEM +; PUC 2: INIT STACK +;------------------------------------------------------------------------------- + MOV #PSTACK,PSP ; init parameter stack + MOV #RSTACK,RSP ; init return stack +;------------------------------------------------------------------------------- +; PUC 3: I/O, RAM, RTC, CS, SYS initialisation limited to FastForth usage. +; All unused I/O are set as input with pullup resistor. +;------------------------------------------------------------------------------- + .include "TargetInit.asm" ; include target specific init code +;------------------------------------------------------------------------------- +; PUC 4: init RAM to 0 +;------------------------------------------------------------------------------- + MOV #RAM_LEN,X ; 2 RAM_LEN must be even and > 1, obviously. +INITRAMLOOP SUB #2,X ; 1 + MOV #0,RAM_ORG(X) ; 3 + JNZ INITRAMLOOP ; 2 6 cycles loop ! +;------------------------------------------------------------------------------- +; PUC 5: GET SYSRSTIV and SYS_USER +;------------------------------------------------------------------------------- + MOV &SYSRSTIV,X ; X <-- SYSRSTIV <-- 0 + MOV &USERSYS,TOS ; TOS = USERSYS + MOV #0,&USERSYS ; clear USERSYS + AND #-1,TOS ; + JNZ PUC6 ; if TOS <> 0, keep USERSYS value + MOV X,TOS ; TOS <-- SYSRSTIV +;------------------------------------------------------------------------------- +; PUC 6: START FORTH engine +;------------------------------------------------------------------------------- +PUC6 CALL #INIT_FORTH ; common part of QABORT|PUC +PUCNEXT .WORD WARM ; no return. May be redirected by BOOT. ;-----------------------------------; -WARM_DISPLAY ; TOS = RSTIV_MEM value - ASMtoFORTH ; display a message then goto QUIT, without return - .word XSQUOTE - .byte 7,13,10,27,"[7m#" ; CR + cmd "reverse video" + # - .word TYPE - .word DOT ; display TOS = RSTIV_MEM value - .word XSQUOTE - .byte 25,"FastForth ©J.M.Thoorens " - .word TYPE - .word LIT,FRAM_FULL,HERE,MINUS,UDOT - .word XSQUOTE - .byte 10,"bytes free" - .word BRAN,ABORT_TYPE -; ----------------------------------; -;-----------------------------------; - FORTHWORD "ACCEPT" +;------------------------------------------------------------------------------- +; INTERPRETER INPUT: ACCEPT KEY EMIT ECHO NOECHO +;------------------------------------------------------------------------------- + FORTHWORD "ACCEPT" ; ;-----------------------------------; ;https://forth-standard.org/standard/core/ACCEPT -;C ACCEPT addr addr len -- addr len' from REFILL, get line at addr to interpret len' chars +;C ACCEPT addr addr len -- addr len' get line at addr to interpret len' chars ACCEPT MOV @PC+,PC ;3 Code Field Address (CFA) of ACCEPT PFAACCEPT .word BODYACCEPT ; Parameter Field Address (PFA) of ACCEPT -BODYACCEPT ; BODY of ACCEPT = default execution of ACCEPT ; ----------------------------------; -; ACCEPT part I prepare TERMINAL_INT; this version allows to RX one char (LF) after sending XOFF +; ACCEPT part I prepare TERMINAL_INT; this version allows to RX one char (LF) after sending XOFF ; ----------------------------------; - MOV TOS,Y ;1 -- addr len +BODYACCEPT MOV TOS,Y ;1 -- org len Y = len MOV @PSP,TOS ;2 -- org ptr - ADD TOS,Y ;1 -- org ptr Y = buf_end ) - MOV #0Dh,X ;2 X = 'CR' to speed up char loop in part II ) - MOV #20h,W ;2 W = 'BL' to speed up char loop in part II > - MOV #YEMIT_NEXT,T ;2 T = return for QYEMIT ) - MOV #CR_NEXT,S ;2 S = CR_NEXT ) + ADD TOS,Y ;1 -- org ptr Y = buf_end + MOV #0Dh,X ;2 X = 'CR' to speed up char loop in part II + MOV #20h,W ;2 W = 'BL' to speed up char loop in part II + MOV #YEMIT_NEXT,T ;2 T = return for QYEMIT + MOV #CR_NEXT,S ;2 S = CR_NEXT PUSHM #6,IP ;8 PUSHM IP,S,T,W,X,Y r-- ACCEPT_ret CR_NEXT YEMIT_NEXT BL CR buf_end - JMP SLEEP ;2 which calls RXON before falling down to LPMx mode + JMP SLEEP ;2 send RXON then shut down to LPM0 sleeping mode ; ----------------------------------; ; **********************************; -TERMINAL_INT ; <--- TEMR RX interrupt vector, delayed by the LPMx wake up time +TERMINAL_INT ; <--- TERM RX buffer full interrupt vector, delayed by the LPM0 wake up time ; **********************************; if wake up time increases, max bauds rate decreases... -; ACCEPT part II under interrupt ; Org Ptr -- len' +; ACCEPT part II under interrupt ; Org Ptr -- len' all SR flags are cleared ; ----------------------------------; - ADD #4,RSP ;1 remove SR and PC from stack, cleared flags: V SCG1 OSCOFF CPUOFF GIE N Z C - POPM #4,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=YEMIT_NEXT r-- ACCEPT_ret CR_NEXT + ADD #4,RSP ;1 remove SR and PC from stack + POPM #4,IP ;6 POPM W=buffer_bound, T=0Dh, S=20h, IP=YEMIT_NEXT r-- ACCEPT_ret CR_NEXT ; ----------------------------------; AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleared ; ----------------------------------; CMP.B T,Y ;1 CR ? - JZ RXOFF ;2 then RET to CR_NEXT - CMP.B S,Y ;1 printable char ? + JNZ AKEYRDNNEXT ;2 no +; ----------------------------------; +RXOFF ; Software|hardware flow control to stop RX UART r-- ACCEPT_ret CR_NEXT +; ----------------------------------; + .IFDEF TERMINAL3WIRES ; first software flow control +RXOFF_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char + JZ RXOFF_LOOP ;2 + MOV #19,&TERM_TXBUF ;4 move XOFF char into TX_buf + .ENDIF ; + .IFDEF TERMINAL4WIRES ; and hardware flow control after + BIS.B #RTS,&HANDSHAKOUT ;3 set RTS high + .ENDIF ; + MOV @RSP+,PC ;4 to CR_NEXT +; ----------------------------------; +AKEYRDNNEXT CMP.B S,Y ;1 printable char ? JC ASTORETEST ;2 yes ; ----------------------------------; CMP.B #8,Y ;1 char = BS ? @@ -233,10 +241,10 @@ AKEYREAD MOV.B &TERM_RXBUF,Y ;3 read character into Y, RX_TERM is cleare CMP @PSP,TOS ; Ptr = Org ? JZ WAITaKEY ; yes: do nothing SUB #1,TOS ; no : dec Ptr - JMP YEMIT ; don't store BS + JMP YEMIT ; don't store BS, return to YEMIT_NEXT ; ----------------------------------; ASTORETEST CMP W,TOS ; 1 Bound is reached ? - JZ YEMIT ; 2 yes: don't store char @ Ptr + JC YEMIT ; 2 yes: don't store char @ Ptr, don't increment TOS MOV.B Y,0(TOS) ; 3 no: store char @ Ptr ADD #1,TOS ; 1 increment Ptr ; ----------------------------------; @@ -246,8 +254,7 @@ YEMIT BIT #TX_TERM,&TERM_IFG ; 3 wait the sending end of previous char, u YEMIT1 BIT.B #CTS,&HANDSHAKIN ; 3 CTS is pulled low if unwired. JNZ YEMIT1 ; 2 .ENDIF ; -QYEMIT .word 48C2h ; 48C2h = MOV.B Y,&<next_adr> - .word TERM_TXBUF ; 3 +QYEMIT MOV.B Y,&TERM_TXBUF ; 3 may be replaced by MOV @IP+,PC with NOECHO MOV @IP+,PC ; 4 ; ----------------------------------; YEMIT_NEXT .word $+2 ; 0 YEMII NEXT address @@ -257,27 +264,17 @@ WAITaKEY BIT #RX_TERM,&TERM_IFG ; 3 new char in TERMRXBUF ? JNZ AKEYREAD ; 2 yes, loop = 34~/31~ by char (with/without echo) ==> 294/322 kBds/MHz JMP WAITaKEY ; 2 no ; ----------------------------------; - -; ----------------------------------; -; return of RXOFF ; --- Org Ptr r-- ACCEPT_NEXT +; return of RXOFF ; --- Org Ptr R-- ACCEPT_NEXT ; ----------------------------------; CR_NEXT SUB @PSP+,TOS ; -- len' - MOV @RSP+,IP ; -; ----------------------------------; - MOV #LPM0+GIE,&LPM_MODE ; reset LPM_MODE to default mode LPM0 for next line of input stream -; ----------------------------------; + MOV @RSP+,IP ; R-- WAITLF BIT #RX_TERM,&TERM_IFG ; char 'LF' is received ? JZ WAITLF ; no - MOV.B &TERM_RXBUF,Y ; yes, clear RX_int flag after LF received -; ----------------------------------; -ACCEPT_EOL CMP #0,&LINE ; if LINE <> 0 increment LINE - JZ ACCEPT_END ; - ADD #1,&LINE ; -ACCEPT_END + MOV.B &TERM_RXBUF,Y ; yes, clear RX_IFG flag after LF received ; ----------------------------------; - MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) - JMP YEMIT ; before return to ABORT to interpret line -; **********************************; UF9 to UF11 are reset. +ACCEPT_EOL MOV S,Y ; output a BL on TERMINAL (for the case of error occuring) + JMP YEMIT ; before return to QUIT to interpret line +; **********************************; UF9 to UF11 will be resetted. ;-----------------------------------; FORTHWORD "KEY" @@ -286,13 +283,26 @@ ACCEPT_END ; KEY -- c wait character from input device ; primary DEFERred word KEY MOV @PC+,PC ;4 Code Field Address (CFA) of KEY PFAKEY .word BODYKEY ; Parameter Field Address (PFA) of KEY, with default value -BODYKEY SUB #2,PSP ;1 push old TOS.. +BODYKEY PUSH #KEYNEXT ; +; ----------------------------------; +RXON ; default BACKGND_APP +; ----------------------------------; + .IFDEF TERMINAL3WIRES ; first software flow control +RXON_LOOP BIT #TX_TERM,&TERM_IFG ;3 wait the sending of last char, useless at high baudrates + JZ RXON_LOOP ;2 + MOV #17,&TERM_TXBUF ;4 move char XON into TX_buf + .ENDIF ; + .IFDEF TERMINAL4WIRES ; and hardware flow control after + BIC.B #RTS,&HANDSHAKOUT ;3 set RTS low + .ENDIF ; + MOV @RSP+,PC ;4 to BACKGND (End of file download or quiet input) or AKEYREAD... +; ----------------------------------; ... (get next line of file downloading), or user defined +KEYNEXT SUB #2,PSP ;1 push old TOS.. MOV TOS,0(PSP) ;3 ..onto stack - CALL #RXON KEYLOOP BIT #RX_TERM,&TERM_IFG ; loop if bit0 = 0 in interupt flag register JZ KEYLOOP ; - MOV &TERM_RXBUF,TOS ; CALL #RXOFF ; + MOV &TERM_RXBUF,TOS ; MOV @IP+,PC ;-----------------------------------; @@ -311,7 +321,6 @@ BODYEMIT MOV TOS,Y ;1 output character to the default output: T ;-----------------------------------; ;Z ECHO -- connect terminal output (default) ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr> - MOV #0,&LINE ; MOV @IP+,PC ;-----------------------------------; @@ -319,5 +328,5 @@ ECHO MOV #48C2h,&QYEMIT ; 48C2h = MOV.B Y,&<next_adr> ;-----------------------------------; ;Z NOECHO -- disconnect terminal output NOECHO MOV #4D30h,&QYEMIT ; NEXT = 4D30h = MOV @IP+,PC - MOV #1,&LINE ; MOV @IP+,PC + diff --git a/inc/CHIPSTICK_FR2433.asm b/inc/CHIPSTICK_FR2433.asm index da9ae18..677d1d2 100644 --- a/inc/CHIPSTICK_FR2433.asm +++ b/inc/CHIPSTICK_FR2433.asm @@ -18,7 +18,7 @@ ; PR2 - TEST ; PR3 - VCC ; PR4 - UART0 RX -; PR5 - UART0 TX +; PR5 - UART0 TX ; PR6 - /RST ; ChipStick Header PL1 @@ -27,8 +27,8 @@ ; P2 - 20 - P3.2 ; P3 - 4 - P1.5 UCA0 RX/SOMI ; P4 - 3 - P1.4 UCA0 TX/SIMO -; P5 - 5 - P1.6 UCA0 CLK -; P6 - 13 - P2.3 +; P5 - 5 - P1.6 UCA0 CLK +; P6 - 13 - P2.3 ; P7 - 12 - P3.0 ; P8 - 7 - P1.0 UCB0 STE ; P9 - 8 - P1.1 UCB0 CLK @@ -65,9 +65,9 @@ ; P3.1 - LED1 ; P2.1 - PL2.2 - SW1 -; P2.0 - PL2.3 - SW2 +; P2.0 - PL2.3 - SW2 -; +--4k7-< DeepRST <-- GND +; +--4k7-< DeepRST <-- GND ; | ; P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge ; P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge @@ -77,21 +77,21 @@ ; P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM ; P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM ; P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM - - + + ; P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK ; P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI ; P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO ; P2.3 - PL1.6 - <---- SD_CD (Card Detect) ; P2.2 - PL2.9 - ----> SD_CS (Card Select) - + ; P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave ; P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave - + ; P2.2 - PL2.9 - ----> SCL I2C SoftMaster ; P2.0 - PL2.3 - <---> SDA I2C SoftMaster - -; P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5) + +; P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5) ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : I/O @@ -107,7 +107,7 @@ MOV #-1,&PAOUT ; OUT1 for all pins BIS #-1,&PAREN ; all pins with pull resistors - + ; PORT1 usage .IFDEF UCB0_TERM ; @@ -127,13 +127,13 @@ BUS_SD .equ 000Eh ; pins P1.1 as UCB0CLK, P1.2 as UCB0SIMO & P1.3 as U TERM_IN .equ P1IN TERM_SEL .equ P1SEL0 TERM_REN .equ P1REN -TXD .equ 10h ; P1.4 = TXD + FORTH Deep_RST pin +TXD .equ 10h ; P1.4 RXD .equ 20h ; P1.5 BUS_TERM .equ 30h .ENDIF -WIPE_IN .equ P1IN -IO_WIPE .equ 10h ; P1.4 = FORTH Deep_RST pin +SW1_IN .equ P1IN +SW1 .equ 10h ; P1.4 = FORTH Deep_RST pin .IFDEF UCA0_SD BUS_SD .equ 0070h ; pins P1.4,P1.5,P1.6 @@ -145,7 +145,7 @@ SD_REN .equ PAREN CD_SD .equ 8 ; P2.3 as Card Detect SD_CDIN .equ P2IN -CS_SD .equ 4 ; P2.2 as Card Select +CS_SD .equ 4 ; P2.2 as Card Select SD_CSOUT .equ P2OUT SD_CSDIR .equ P2DIR @@ -163,7 +163,7 @@ HANDSHAKIN .equ P3IN CTS .equ 1 ; P3.0 RTS .equ 4 ; P3.2 -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; CTS is not used by FORTH terminal ; configure RTS as output high to disable RX TERM during start FORTH @@ -174,11 +174,11 @@ RTS .equ 4 ; P3.2 MOV.B #0FDh,&P3OUT ; all pins with pullup resistors and LED1 = output low .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P3DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P3OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -198,7 +198,7 @@ RTS .equ 4 ; P3.2 ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -; SYS code +; SYS code ; BIC #1,&SYSCFG0 ; enable write program in FRAM MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO @@ -208,161 +208,39 @@ RTS .equ 4 ; P3.2 ; CS code for EXP430FR2433 -; to measure REFO frequency, output ACLK on P2.2: +; to measure REFO frequency, output ACLK on P2.2: ; BIS.B #4,&P2SEL1 ; BIS.B #4,&P2DIR ; result : REFO = 32.69kHz -; =================================================================== -; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ? -; (no problem with MSP430FR5xxx families without FLL). -; =================================================================== - - .IF FREQUENCY = 0.25 - - MOV #0D6h,&CSCTL0 ; preset DCO = 0xD6 (measured value @ 0x180 ; to measure, type 0x180 @ U.) - - MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #200Dh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Dh - ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz -; MOV #200Eh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Eh - ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz - MOV #200Fh,&CSCTL2 ; Set FLLD=2 (DCOCLKCDIV=DCO/4),set FLLN=0Fh - ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz -; ===================================== - MOV #4,X - - .ELSEIF FREQUENCY = 0.5 - - MOV #0D6h,&CSCTL0 ; preset DCO = 0xD6 (measured value @ 0x180 ; to measure, type 0x180 @ U.) - - MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh - ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz -; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh - ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz - MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh - ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz -; ===================================== - MOV #8,X - - .ELSEIF FREQUENCY = 1 - - MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?) - - MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh - ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz - MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh - ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz -; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh - ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz -; ===================================== - MOV #16,X - + .IFDEF LF_XTAL +; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) + MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV + BIS.B #03,&P2SEL0 ; P2.0 as XOUT, P2.1 as XIN + .ELSE + BIS #0010h,&CSCTL3 ; FLL select REFCLOCK + MOV #0200h,&CSCTL4 ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value) + .ENDIF + BIC.B #-1,&CSCTL1 ; clear DCORSEL (Set 1MHZ DCORSEL), DCOFTRIM=0, ENable MODulation to reduce EMI + .IF FREQUENCY = 1 ; nothing else to do .ELSEIF FREQUENCY = 2 - - MOV #00B4h,&CSCTL0 ; preset DCO = 0xB4 (measured value @ 0x180 ; to measure, type HEX 0x180 ?) - - MOV #0003h,&CSCTL1 ; Set 2MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh - ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz -; MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch - ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz - MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh - ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz -; ===================================== - MOV #32,X - + BIS.B #2,&CSCTL1 ; Set 2MHZ DCORSEL .ELSEIF FREQUENCY = 4 - - MOV #00D2h,&CSCTL0 ; preset DCO = 0xD2 (measured value @ 0x180) - - MOV #0005h,&CSCTL1 ; Set 4MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h - ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz - - MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h - ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz - -; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah - ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz -; ===================================== - MOV #64,X - + BIS.B #4,&CSCTL1 ; Set 4MHZ DCORSEL .ELSEIF FREQUENCY = 8 - - - MOV #00F3h,&CSCTL0 ; preset DCO = 0xF2 (measured value @ 0x180) - - MOV #0007h,&CSCTL1 ; Set 8MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h - ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz -; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h - ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz -; MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h - ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz - -; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h - ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz - -; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value) -; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh -; =================================================================== -; CHIPSTICK_FR2433 : TLV area corrupted when welding ? -; =================================================================== - MOV #00FCh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FCh - ; fCOCLKDIV = 32768 x (252+1) = 8.290 MHz <============ why ? - -; ===================================== - MOV #128,X - + BIS.B #6,&CSCTL1 ; Set 8MHZ DCORSEL + .ELSEIF FREQUENCY = 12 + BIS.B #8,&CSCTL1 ; Set 12MHZ DCORSEL .ELSEIF FREQUENCY = 16 - - MOV #0129h,&CSCTL0 ; preset DCO = 0x129 (measured value @ 0x180) - - MOV #000Bh,&CSCTL1 ; Set 16MHZ DCORSEL,disable DCOFTRIM,Modulation -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz -; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz -; MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz - MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz -; ===================================== - MOV #256,X - + BIS.B #10,&CSCTL1 ; Set 16MHZ DCORSEL .ELSEIF - .error "bad frequency setting, only 0.5,1,2,4,8,16 MHz" - .ENDIF - - - .IFDEF LF_XTAL -; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) - MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV - - BIS.B #03,&P2SEL0 ; P2.0 as XOUT, P2.1 as XIN - - .ELSE - BIS #0010h,&CSCTL3 ; FLL select REFCLOCK -; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value) + .error "bad frequency setting, only 1,2,4,8,12,16 MHz" .ENDIF - -ClockWaitX MOV #4375,Y ; wait 0.42s before starting after POR - ; ...because FLL lock time = 280 ms +; MOV #INT(FREQUENCY*1000000/32768)-1,&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight lower + MOV #INT(FREQUENCY*1000000/32768),&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight upper + MOV #128,X ; 128* 3 ms = 384 ms delay, because FLL lock time = 280 ms +ClockWaitX MOV &FREQ_KHZ,Y ; ClockWaitY SUB #1,Y ;1 - JNZ ClockWaitY ;2 4375x3 = 13125 cycles delay = 13.125ms @ 1MHz - SUB #1,X ; x 32 @ 1 MHZ = 330ms + JNZ ClockWaitY ;2 FREQ_KHZ x 3 ==> 3ms + SUB #1,X ; JNZ ClockWaitX ; - -;WAITFLL BIT #300h,&CSCTL7 ; wait FLL lock -; JNZ WAITFLL - diff --git a/inc/CHIPSTICK_FR2433.pat b/inc/CHIPSTICK_FR2433.pat index 26bdd63..21a4dd2 100644 --- a/inc/CHIPSTICK_FR2433.pat +++ b/inc/CHIPSTICK_FR2433.pat @@ -4,7 +4,7 @@ \.f=\.4th for ChipStick_FR2433! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -20,9 +20,9 @@ ! P3.1 - LED1 ! ! P2.1 - PL2.2 - SW1 -! P2.0 - PL2.3 - SW2 +! P2.0 - PL2.3 - SW2 ! -! +--4k7-< DeepRST <-- GND +! +--4k7-< DeepRST <-- GND ! | ! P1.4 - UCA0 TXD PL1.4 - <-+-> RX UARTtoUSB bridge ! P1.5 - UCA0 RXD PL1.3 - <---- TX UARTtoUSB bridge @@ -32,27 +32,27 @@ ! P1.1 - UCB0 CLK PL1.9 - ----> CLK SPI_RAM ! P1.2 - UCB0 SIMO PL1.10 - ----> SI SPI_RAM ! P1.3 - UCB0 SOMI PL2.10 - <---- S0 SPI_RAM -! -! +! +! ! P1.1 - UCB0 CLK PL1.9 - ----> SD_CLK ! P1.2 - UCB0 SIMO PL1.10 - ----> SD_SDI ! P1.3 - UCB0 SOMI PL2.10 - <---- SD_SDO ! P2.3 - PL1.6 - <---- SD_CD (Card Detect) ! P2.2 - PL2.9 - ----> SD_CS (Card Select) -! +! ! P1.2 - UCB0 SDA PL1.10 - <---> SDA I2C Slave ! P1.3 - UCB0 SCL PL2.10 - ----> SCL I2C Slave -! +! ! P2.2 - PL2.9 - ----> SCL I2C SoftMaster ! P2.0 - PL2.3 - <---> SDA I2C SoftMaster -! -! P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5) +! +! P1.0 - UCB0 STE PL1.8 - <---- TSSOP32236 (IR RC5) ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX TERM_IN=\$200! @@ -62,21 +62,21 @@ TERM_SEL=\$20A! \SEL0 TERM_VEC=\$FFE4! \ UCA0 WAKE_UP=1! \ RX int -TERM_CTLW0=\$500! \ eUSCI_A control word 0 -TERM_CTLW1=\$502! \ eUSCI_A control word 1 -TERM_BRW=\$506! -TERM_BR0=\$506! \ eUSCI_A baud rate 0 -TERM_BR1=\$507! \ eUSCI_A baud rate 1 -TERM_MCTLW=\$508! \ eUSCI_A modulation control -TERM_STATW=\$50A! \ eUSCI_A status -TERM_RXBUF=\$50C! \ eUSCI_A receive buffer -TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer -TERM_ABCTL=\$510! \ eUSCI_A LIN control -TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control -TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control -TERM_IE=\$51A! \ eUSCI_A interrupt enable -TERM_IFG=\$51C! \ eUSCI_A interrupt flags -TERM_IV=\$51E! \ eUSCI_A interrupt vector word +TERM_CTLW0=\$500! \ eUSCI_A control word 0 +TERM_CTLW1=\$502! \ eUSCI_A control word 1 +TERM_BRW=\$506! +TERM_BR0=\$506! \ eUSCI_A baud rate 0 +TERM_BR1=\$507! \ eUSCI_A baud rate 1 +TERM_MCTLW=\$508! \ eUSCI_A modulation control +TERM_STATW=\$50A! \ eUSCI_A status +TERM_RXBUF=\$50C! \ eUSCI_A receive buffer +TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer +TERM_ABCTL=\$510! \ eUSCI_A LIN control +TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control +TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control +TERM_IE=\$51A! \ eUSCI_A interrupt enable +TERM_IFG=\$51C! \ eUSCI_A interrupt flags +TERM_IV=\$51E! \ eUSCI_A interrupt vector word RTS=4! ; P3.2 CTS=1! ; P3.0 @@ -90,19 +90,19 @@ LED1_OUT=\$222! LED1=\$02! P3.1 SW1_IN=\$201! -SW1=\$02! P2.1 +SW1=\$02! P2.1 WIPE_IN=\$201! -IO_WIPE=\$02! P2.1 +IO_WIPE=\$02! P2.1 SW2_IN=\$201! SW2=\$01! P2.0 -IR_IN=\$200! -IR_OUT=\$202! -IR_DIR=\$204! -IR_REN=\$208! +IR_IN=\$200! +IR_OUT=\$202! +IR_DIR=\$204! +IR_REN=\$208! IR_IES=\$218! IR_IE=\$21A! IR_IFG=\$21C! @@ -116,7 +116,7 @@ I2CSM_DIR=\$205! I2CSM_REN=\$207! SMSDA=\$01! P2.0 SMSCL=\$04! P2.2 -SM_BUS=\$05! +SM_BUS=\$05! I2CSMM_IN=\$201! I2CSMM_OUT=\$203! @@ -124,7 +124,7 @@ I2CSMM_DIR=\$205! I2CSMM_REN=\$207! SMMSDA=\$01! P2.0 SMMSCL=\$04! P2.2 -SMM_BUS=\$05! +SMM_BUS=\$05! I2CMM_IN=\$200! I2CMM_OUT=\$202! @@ -160,7 +160,7 @@ S_BUS=\$C0! CD_SD=8! ; P2.3 as Card Detect SD_CDIN=\$201! -CS_SD=4! ; P2.2 as Card Select +CS_SD=4! ; P2.2 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! diff --git a/inc/FastForthREGtoTI.pat b/inc/FastForthREGtoTI.pat index 94d81ca..64cced6 100644 --- a/inc/FastForthREGtoTI.pat +++ b/inc/FastForthREGtoTI.pat @@ -27,72 +27,91 @@ TOS=R14! PSP=R15! ! forth words filter -D\.R=D\.R - -M\*=M\* -M\+=M\+ - +\"\s*\"=\"\s*\"! ." xxxx" filter +S\"\s*\"=S\"\s*\"! S" xxxx" filter +s\"\s*\"=S\"\s*\"! s" xxxx" filter +\(\s*\)=\(\s*\)! ( xxxx) and .( xxxx) filter +abort\"\s*\"=ABORT\"\s*\"! abort" xxxx" filter +ABORT\"\s*\"=ABORT\"\s*\"! ABORT" xxxx" filter +! +D\.R=D\.R! +! +M\*=M\*! +M\+=M\+! +! R\>=R\>! R\@=R\@! \>R=\>R! - +! S\>=S\>! \>S=\>S! S\<=S\<! S\>\==S\>\=! \.S=\.S! -S\"=S\"! -S\_=S\_! - +\s\_=\S\_! s_ filter +\S\_=\S\_! S_ filter +! \<\#=\<\#! \#S=\#S! \#\>=\#\>! - +! T\{=T\{! \}T=\}T! - +! U\.R=U\.R! - +! ! ASCII numbers interpreter complement -\'NUL\'=\$00! -\'SOH\'=\$01! -\'STX\'=\$02! -\'ETX\'=\$03! -\'EOT\'=\$04! -\'ENQ\'=\$05! -\'ACK\'=\$06! -\'BEL\'=\$07! -\'BS\'=\$08! Backspace -\'HT\'=\$09! Horizontal Tabulation -\'LF\'=\$0A! -\'VT\'=\$0B! -\'FF\'=\$0C! -\'CR\'=\$0D! -\'SO\'=\$0E! -\'SI\'=\$0F! -\'DLE\'=\$10! -\'DC1\'=\$11! XON -\'DC2\'=\$12! -\'DC3\'=\$13! XOFF -\'DC4\'=\$14! -\'NAK\'=\$15! -\'SYN\'=\$16! -\'ETB\'=\$17! -\'CAN\'=\$18! -\'EM\'=\$19! -\'SUB\'=\$1A! -\'ESC\'=\$1B! -\'FS\'=\$1C! -\'GS\'=\$1D! -\'RS\'=\$1E! -\'US\'=\$1F! -\'SP\'=\$20! -\'\'\'=\$27!' QNUMBER can't interpret ''' ! -\'DEL\'=\$7F! - -\(RTS\)=\(RTS\)! -\(CTS\)=\(CTS\)! - +'NUL'=\$00! +'SOH'=\$01! +'STX'=\$02! +'ETX'=\$03! +'EOT'=\$04! +'ENQ'=\$05! +'ACK'=\$06! +'BEL'=\$07! +'BS'=\$08! Backspace +'HT'=\$09! Horizontal Tabulation +'LF'=\$0A! +'VT'=\$0B! +'FF'=\$0C! +'CR'=\$0D! +'SO'=\$0E! +'SI'=\$0F! +'DLE'=\$10! +'DC1'=\$11! +'XON'=\$11! +'DC2'=\$12! +'DC3'=\$13! +'XOFF'=\$13! +'DC4'=\$14! +'NAK'=\$15! +'SYN'=\$16! +'ETB'=\$17! +'CAN'=\$18! +'EM'=\$19! +'SUB'=\$1A! +'ESC'=\$1B! escape char +'FS'=\$1C! +'GS'=\$1D! +'RS'=\$1E! +'US'=\$1F! +'SP'=\$20! +'DEL'=\$7F! +'R'='R'! +'Q'='Q'! +'P'='P'! +'M'='M'! +'Y'='Y'! +'X'='X'! +'W'='W'! +'T'='T'! +'S'='S'! +(SW1)=(SW1)! +(SW2)=(SW2)! +(RST)=(RST)! +\/RTS=\/RTS! +\/CTS=\/CTS! +XON\/XOFF=XON\/XOFF! ! ============================================ ! SR bits : @@ -100,15 +119,15 @@ U\.R=U\.R! \#C=\#1! = SR(0) Carry flag \#Z=\#2! = SR(1) Zero flag \#N=\#4! = SR(2) Negative flag -\#GIE=\#8! = SR(3) Enable Int -\#CPUOFF=\#\$10!= SR(4) CPUOFF -\#OSCOFF=\#\$20!= SR(5) OSCOFF -\#SCG0=\#\$40! = SR(6) SCG0 -\#SCG1=\#\$80! = SR(7) SCG1 \#V=\#\$100! = SR(8) oVerflow flag -\#UF9=\#\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use. -\#UF10=\#\$400! = SR(10) User Flag 2 -\#UF11=\#\$800! = SR(11) User Flag 3 +GIE=8! = SR(3) Enable Int +CPUOFF=\$10! = SR(4) CPUOFF +OSCOFF=\$20! = SR(5) OSCOFF +SCG0=\$40! = SR(6) SCG0 +SCG1=\$80! = SR(7) SCG1 +UF9=\$200! = SR(9) User Flag 1 used by ?NUMBER --> INTERPRET --> LITERAL to process double numbers, else free for use. +UF10=\$400! = SR(10) User Flag 2 +UF11=\$800! = SR(11) User Flag 3 LPM4=\$F0! SR(LPM4) LPM3=\$D0! SR(LPM3) @@ -116,12 +135,6 @@ LPM2=\$90! SR(LPM2) LPM1=\$50! SR(LPM1) LPM0=\$10! SR(LPM0) -LPM4\+GIE=\$F8! SR(LPM4+GIE) -LPM3\+GIE=\$D8! SR(LPM3+GIE) -LPM2\+GIE=\$98! SR(LPM2+GIE) -LPM1\+GIE=\$58! SR(LPM1+GIE) -LPM0\+GIE=\$18! SR(LPM0+GIE) - ! ============================================ ! PORTx, Reg bits : ! ============================================ @@ -150,9 +163,15 @@ RETA=MOVA \@R1+,R0! \ MOVA @RSP+,PC NOP=MOV \#0,R3! \ one word one cycle NOP2=\$3C00 ,! \ compile JMP 0 one word two cycles NOP3=MOV R0,R0! \ MOV PC,PC one word three cycles -NEXT=MOV \@R13+,R0! \ MOV @IP+,PC - -ABORT=ALLOT\+8! Empty the data stack and perform the function of QUIT -QUIT=ALLOT\+\$0E! interpret line by line the input stream -ABORT\"=ABORT\"! +NEXT=MOV \@R13+,R0! \ MOV @IP+,PC +\'\ \\=\'\ \\! \ to compile INTERPRET in CORE_ANS.f +DODOES=\$1285! +DOCON=\$1286! +DOVAR=\$1287! +! ============================================ +! ADD-ON flags : +! ============================================ +FLOORED=\$8000! +LF_XTAL=\$4000! +HMPY=1! \ No newline at end of file diff --git a/inc/LP_MSP430FR2476.asm b/inc/LP_MSP430FR2476.asm index d6c9a0a..5b3e2a4 100644 --- a/inc/LP_MSP430FR2476.asm +++ b/inc/LP_MSP430FR2476.asm @@ -7,36 +7,36 @@ ; J101 Target J101 eZ-FET UARTtoUSB ; -; DVSS 14 o--o 13 GND +; DVSS 14 o--o 13 GND ; 5V0 12 o--o 11 5V0 ; DVCC 10 o--o 9 3V3 ; P1.5 UCA0_RX 8 o--o 7 <------------ TX UARTtoUSB ; P1.4 UCA0_TX 6 o--o 5 <---------+-> RX UARTtoUSB -; SBWTDIO/RST 4 o--o 3 | _ +; SBWTDIO/RST 4 o--o 3 | _ ; SBWTCK/TST 2 o--o 1 +--4k7---o o-- GND ; DeepRST ; SD_Card socket ; VCC - ----> VCC SD_CardAdapter ; GND - <---> GND SD_CardAdapter -; P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK) +; P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK) ; P2.6 - UCA1 TXD/SIMO J1 ----> SDI SD_CardAdapter (MOSI) ; P2.5 - UCA1 RXD/SOMI J1 <---- SDO SD_CardAdapter (MISO) ; P1.6 - J4 ----> CS SD_CardAdapter (Card Select) ; P1.7 - J4 <---- CD SD_CardAdapter (Card Detect) -; +; ; ====================================================================== ; LP_MSP430FR2476 board ; ====================================================================== ; J1 - left ext. ; 3v3 -; P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 +; P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 ; P2.5/UCA1RXD/UCA1SOMI/CAP1.2 ; P2.6/UCA1TXD/UCA1SIMO/CAP1.3 ; P2.2/SYNC/ACLK/COMP0.1 -; P5.4/UCB1STE/TA3CLK/A11 +; P5.4/UCB1STE/TA3CLK/A11 ; P3.5/UCB1CLK/TB0TRG/CAP3.1 -; P4.5/UCB0SOMI/UCB0SCL/TA3.2 +; P4.5/UCB0SOMI/UCB0SCL/TA3.2 ; P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 ; P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VEREF- ; @@ -47,14 +47,14 @@ ; P1.7/UCA0STE/SMCLK/TDO/A7 ; P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 ; P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 -; P5.3/UCB1CLK/TA3.0/A10 +; P5.3/UCB1CLK/TA3.0/A10 ; P1.0/UCB0STE/TA0CLK/A0/VEREF+ -<J7>- LED1 ; P1.1/UCB0CLK/TA0.1/COMP0.0/A1 --- TEMPERATURE SENSOR ---<J9>--- 3V3 -; P5.7/TA2.1/COMP0.2 +; P5.7/TA2.1/COMP0.2 ; P3.7/TA3.2/CAP2.0 ; ; J4 - right int. -; P5.2/UCA0TXD/UCA0SIMO/TB0.4 +; P5.2/UCA0TXD/UCA0SIMO/TB0.4 ; P5.1/UCA0RXD/UCA0SOMI/TB0.3 -<J8>- LED2Red ; P5.0/UCA0CLK/TB0.2 -<J8>- LED2Green ; P4.7/UCA0STE/TB0.1 -<J8>- LED2Blue @@ -78,8 +78,8 @@ ; P2.4/UCA1CLK/CAP1.1 ; ; switch-keys: -; P4.0/TA3.1/CAP2.1 - S1 -; P2.3/TA2.0/CAP0.2 - S2 +; P4.0/TA3.1/CAP2.1 - S1 +; P2.3/TA2.0/CAP0.2 - S2 ; /RST - S3 ; ; XTAL LF 32768 Hz @@ -114,8 +114,8 @@ LED2 .equ 1 MOV #0FFFEh,&PAOUT ; all pins with pull up resistors else P1.0 (LED2) .IFDEF UCA0_TERM -; P1.4 UCA0-TXD --> USB2UART RXD -; P1.5 UCA0-RXD <-- USB2UART TXD +; P1.4 UCA0-TXD --> USB2UART RXD +; P1.5 UCA0-RXD <-- USB2UART TXD TERM_IN .equ P1IN TERM_SEL .equ P1SEL0 TERM_REN .equ P1REN @@ -127,7 +127,7 @@ BUS_TERM .equ 30h CD_SD .equ 080h ; P1.7 as Card Detect SD_CDIN .equ P1IN -CS_SD .equ 040h ; P1.6 as Card Select +CS_SD .equ 040h ; P1.6 as Card Select SD_CSOUT .equ P1OUT SD_CSDIR .equ P1DIR @@ -137,7 +137,7 @@ SD_SEL .equ PASEL0 ; to configure UCA1 SD_REN .equ PAREN ; to configure pullup resistors .ENDIF -; P2.3/TA2.0/CAP0.2 - S2 +; P2.3/TA2.0/CAP0.2 - S2 SW2_IN .equ P2IN SW2 .equ 8 @@ -163,8 +163,6 @@ BUS_TERM .equ 0Ch ; P3.2=SDA P3.3=SCL ; S1 - P4.0 SW1_IN .equ P4IN SW1 .equ 1 ; P4.0 = S1 -WIPE_IN .equ P4IN -IO_WIPE .equ 1 ; P4.0 = S1 = FORTH Deep_RST pin ; LED2B - J8 - P4.7 @@ -198,11 +196,11 @@ CTS .equ 4 ; P6.2 MOV #0FFFCh,&PCOUT ; all pins with pull up resistors else P5.0 (LED2G) P5.1 (LED2R) .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P6DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P6OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -220,7 +218,7 @@ CTS .equ 4 ; P6.2 ; ---------------------------------------------------------------------- ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -; SYS code +; SYS code ; BIC #1,&SYSCFG0 ; enable write program in FRAM MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO @@ -229,125 +227,40 @@ CTS .equ 4 ; P6.2 ; ---------------------------------------------------------------------- ; CS code for MSP430FR2476 -; to measure REFO frequency, output ACLK on P2.2: +; to measure REFO frequency, output ACLK on P2.2: ; BIS.B #4,&P2SEL1 ; BIS.B #4,&P2DIR ; result : REFO = xx.xx kHz -; ===================================== - .IF FREQUENCY = 0.5 -; MOV #058h,&CSCTL0 ; preset DCO = measured value @ 0x180 (88) -; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation - MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209) - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh - ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz -; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh - ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz - MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh - ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz -; ===================================== - .ELSEIF FREQUENCY = 1 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B1h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh - ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz - MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh - ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz -; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh - ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz -; ===================================== - .ELSEIF FREQUENCY = 2 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B3h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh - ; fCOCLKDIV = 32768 x (59+1) = 1.966 MHz ; measured : MHz - MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch - ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz -; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh - ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz -; ===================================== - .ELSEIF FREQUENCY = 4 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B5h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h - ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz - MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h - ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz -; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah - ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz -; ===================================== - .ELSEIF FREQUENCY = 8 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B7h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h - ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz -; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h - ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz - MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h - ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz -; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h - ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz -; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value) -; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh - -; ===================================== - .ELSEIF FREQUENCY = 12 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B9h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #016Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 364+1) = 12.960 MHz ; measured : 11.xxxMHz -; MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz - MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz -; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz -; ===================================== - .ELSEIF FREQUENCY = 16 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00BBh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz -; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz - MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz -; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz -; ===================================== - .ELSEIF - .error "bad frequency setting, only 0.5,1,2,4,8,12,16 MHz" - .ENDIF - .IFDEF LF_XTAL ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV BIS.B #03,&P2SEL0 ; P2.0 as XOUT, P2.1 as XIN .ELSE BIS #0010h,&CSCTL3 ; FLL select REFCLOCK - MOV #0200h,&CSCTL4 ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value) +; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value) .ENDIF - + BIC.B #-1,&CSCTL1 ; clear DCORSEL (Set 1MHZ DCORSEL), DCOFTRIM=0, ENable MODulation to reduce EMI + .IF FREQUENCY = 1 ; nothing else to do + .ELSEIF FREQUENCY = 2 + BIS.B #2,&CSCTL1 ; Set 2MHZ DCORSEL + .ELSEIF FREQUENCY = 4 + BIS.B #4,&CSCTL1 ; Set 4MHZ DCORSEL + .ELSEIF FREQUENCY = 8 + BIS.B #6,&CSCTL1 ; Set 8MHZ DCORSEL + .ELSEIF FREQUENCY = 12 + BIS.B #8,&CSCTL1 ; Set 12MHZ DCORSEL + .ELSEIF FREQUENCY = 16 + BIS.B #10,&CSCTL1 ; Set 16MHZ DCORSEL + .ELSEIF FREQUENCY = 20 + BIS.B #12,&CSCTL1 ; Set 20MHZ DCORSEL + .ELSEIF FREQUENCY = 24 + BIS.B #14,&CSCTL1 ; Set 24MHZ DCORSEL + .ELSEIF + .error "bad frequency setting, only 1,2,4,8,12,16,20,24 MHz" + .ENDIF +; MOV #INT(FREQUENCY*1000000/32768)-1,&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight lower + MOV #INT(FREQUENCY*1000000/32768),&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight upper MOV #92,X ; 96* 3 ms = 288 ms delay, because FLL lock time = 200 ms ClockWaitX MOV &FREQ_KHZ,Y ; ClockWaitY SUB #1,Y ;1 diff --git a/inc/LP_MSP430FR2476.pat b/inc/LP_MSP430FR2476.pat index 36293a8..ccd03f0 100644 --- a/inc/LP_MSP430FR2476.pat +++ b/inc/LP_MSP430FR2476.pat @@ -4,7 +4,7 @@ \.f=\.4th for LP_MSP430FR2476! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -22,26 +22,26 @@ ! =================================================================================== ! in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE ! =================================================================================== -! +! ! J101 Target J101 eZ-FET UARTtoUSB ! -! DVSS 14 o--o 13 GND +! DVSS 14 o--o 13 GND ! 5V0 12 o--o 11 5V0 ! DVCC 10 o--o 9 3V3 ! P1.5 UCA0_RX 8 o--o 7 <------------ TX UARTtoUSB ! P1.4 UCA0_TX 6 o--o 5 <---------+-> RX UARTtoUSB -! SBWTDIO/RST 4 o--o 3 | _ +! SBWTDIO/RST 4 o--o 3 | _ ! SBWTCK/TST 2 o--o 1 +--4k7---o o-- GND ! DeepRST ! J1 - left ext. ! 3v3 -! P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 +! P1.6/UCA0CLK/TA1CLK/TDI/TCLK/A6 ! P2.5/UCA1RXD/UCA1SOMI/CAP1.2 ! P2.6/UCA1TXD/UCA1SIMO/CAP1.3 ! P2.2/SYNC/ACLK/COMP0.1 -! P5.4/UCB1STE/TA3CLK/A11 +! P5.4/UCB1STE/TA3CLK/A11 ! P3.5/UCB1CLK/TB0TRG/CAP3.1 -! P4.5/UCB0SOMI/UCB0SCL/TA3.2 +! P4.5/UCB0SOMI/UCB0SCL/TA3.2 ! P1.3/UCB0SOMI/UCB0SCL/MCLK/A3 ! P1.2/UCB0SIMO/UCB0SDA/TA0.2/A2/VEREF- ! @@ -52,15 +52,15 @@ ! P1.7/UCA0STE/SMCLK/TDO/A7 ! P4.3/UCB1SOMI/UCB1SCL/TB0.5/A8 ! P4.4/UCB1SIMO/UCB1SDA/TB0.6/A9 -! P5.3/UCB1CLK/TA3.0/A10 +! P5.3/UCB1CLK/TA3.0/A10 ! P1.0/UCB0STE/TA0CLK/A0/VEREF+ - J7 - LED1 ! P1.1/UCB0CLK/TA0.1/COMP0.0/A1 - TEMPERATURE SENSOR -! P5.7/TA2.1/COMP0.2 +! P5.7/TA2.1/COMP0.2 ! P3.7/TA3.2/CAP2.0 ! ! J4 - right int. -! P5.2/UCA0TXD/UCA0SIMO/TB0.4 -! P5.1/UCA0RXD/UCA0SOMI/TB0.3 - J8 - LED2R +! P5.2/UCA0TXD/UCA0SIMO/TB0.4 +! P5.1/UCA0RXD/UCA0SOMI/TB0.3 - J8 - LED2R ! P5.0/UCA0CLK/TB0.2 - J8 - LED2G ! P4.7/UCA0STE/TB0.1 - J8 - LED2B ! P6.0/TA2.2/COMP0.3 @@ -83,8 +83,8 @@ ! P2.4/UCA1CLK/CAP1.1 ! ! switch-keys: -! P4.0/TA3.1/CAP2.1 - S1 -! P2.3/TA2.0/CAP0.2 - S2 +! P4.0/TA3.1/CAP2.1 - S1 +! P2.3/TA2.0/CAP0.2 - S2 ! /RST - S3 ! ! XTAL LF 32768 Hz @@ -111,7 +111,7 @@ ! ! P4.0 - Switch S1 <--- LCD contrast + (finger :-) ! P2.3 - Switch S2 <--- LCD contrast - (finger ;-) -! +! ! GND - <-------+---0V0----------> 1 LCD_Vss ! VCC - >------ | --3V6-----+----> 2 LCD_Vdd ! | | @@ -128,8 +128,8 @@ ! P1.1 - J3 <---------red------------> 12 LCD_DB5 ! P1.2 - J1 <---------orange---------> 13 LCD_DB5 ! P1.3 - J1 <---------yellow---------> 14 LCD_DB7 -! -! +--4k7-< DeepRST <-- GND +! +! +--4k7-< DeepRST <-- GND ! | ! P1.4 - UCA0 TXD J101.8 <-+->white--> RX UARTtoUSB bridge ! P1.5 - UCA0 RXD J101.10 <----green--- TX UARTtoUSB bridge @@ -137,16 +137,16 @@ ! GND - J101.20 <---> GND ! P6.1 - RTS J4 ----blue----> CTS UARTtoUSB bridge (optional hardware control flow) ! P6.2 - CTS J4 ---yellow---> RTS UARTtoUSB bridge (optional hardware control flow) -! +! ! ! VCC - ----> VCC SD_CardAdapter ! GND - <---> GND SD_CardAdapter -! P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK) +! P2.4 - UCA1 CLK J2 ----> CLK SD_CardAdapter (SCK) ! P2.6 - UCA1 TXD/SIMO J1 ----> SDI SD_CardAdapter (MOSI) ! P2.5 - UCA1 RXD/SOMI J1 <---- SDO SD_CardAdapter (MISO) ! P1.6 - J4 ----> CS SD_CardAdapter (Card Select) ! P1.7 - J4 <---- CD SD_CardAdapter (Card Detect) -! +! ! ! P2.2 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ───┐ ! └┌───┐ @@ -165,7 +165,7 @@ ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX TERM_IN=\$200! @@ -175,21 +175,21 @@ TERM_SEL=\$20A! \SEL0 TERM_VEC=\$FFE4! \ UCA0 WAKE_UP=1! \ RX int -TERM_CTLW0=\$500! \ eUSCI_A control word 0 -TERM_CTLW1=\$502! \ eUSCI_A control word 1 -TERM_BRW=\$506! -TERM_BR0=\$506! \ eUSCI_A baud rate 0 -TERM_BR1=\$507! \ eUSCI_A baud rate 1 -TERM_MCTLW=\$508! \ eUSCI_A modulation control -TERM_STATW=\$50A! \ eUSCI_A status -TERM_RXBUF=\$50C! \ eUSCI_A receive buffer -TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer -TERM_ABCTL=\$510! \ eUSCI_A LIN control -TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control -TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control -TERM_IE=\$51A! \ eUSCI_A interrupt enable -TERM_IFG=\$51C! \ eUSCI_A interrupt flags -TERM_IV=\$51E! \ eUSCI_A interrupt vector word +TERM_CTLW0=\$500! \ eUSCI_A control word 0 +TERM_CTLW1=\$502! \ eUSCI_A control word 1 +TERM_BRW=\$506! +TERM_BR0=\$506! \ eUSCI_A baud rate 0 +TERM_BR1=\$507! \ eUSCI_A baud rate 1 +TERM_MCTLW=\$508! \ eUSCI_A modulation control +TERM_STATW=\$50A! \ eUSCI_A status +TERM_RXBUF=\$50C! \ eUSCI_A receive buffer +TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer +TERM_ABCTL=\$510! \ eUSCI_A LIN control +TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control +TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control +TERM_IE=\$51A! \ eUSCI_A interrupt enable +TERM_IFG=\$51C! \ eUSCI_A interrupt flags +TERM_IV=\$51E! \ eUSCI_A interrupt vector word RTS=2! P6.1 CTS=4! P6.2 @@ -199,7 +199,7 @@ HANDSHAKOUT=\$243! CD_SD=\$80! P1.7 as Card Detect SD_CDIN=\$200! -CS_SD=\$40! P1.6 as Card Select +CS_SD=\$40! P1.6 as Card Select SD_CSOUT=\$202! SD_CSDIR=\$204! @@ -219,7 +219,7 @@ LED1_DIR=\$244! LED1=2! P5.1 red led SW1_IN=\$221! -SW1=1! P4.0 = S1 +SW1=1! P4.0 = S1 WIPE_IN\$221! IO_WIPE=1! P4.0 = S1 = FORTH Deep_RST pin @@ -264,10 +264,10 @@ WDT_TIM_0_VEC=\$FFF8! TA0_0_VEC !IR_RC5 RC5_=RC5_! -IR_IN=\$201! -IR_OUT=\$203! -IR_DIR=\$205! -IR_REN=\$209! +IR_IN=\$201! +IR_OUT=\$203! +IR_DIR=\$205! +IR_REN=\$209! IR_IES=\$219! IR_IE=\$21B! IR_IFG=\$21D! @@ -285,7 +285,7 @@ I2CSM_DIR=\$224! I2CSM_REN=\$226! SMSDA=4! P3.2 SMSCL=8! P3.3 -SM_BUS=\$0C! +SM_BUS=\$0C! !Software I2C_Multi_Master I2CSMM_IN=\$220! @@ -294,7 +294,7 @@ I2CSMM_DIR=\$224! I2CSMM_REN=\$226! SMMSDA=4! P3.2 SMMSCL=8! P3.3 -SMM_BUS=\$0C! +SMM_BUS=\$0C! !hardware I2C_Multi_Master I2CMM_IN=\$221! @@ -342,12 +342,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$580! USCI_B1 Control Word Register 0 I2CM_CTLW1=\$582! USCI_B1 Control Word Register 1 I2CM_BRW=\$586! USCI_B1 Baud Word Rate 0 -I2CM_STATW=\$588! USCI_B1 status word -I2CM_TBCNT=\$58A! USCI_B1 byte counter threshold +I2CM_STATW=\$588! USCI_B1 status word +I2CM_TBCNT=\$58A! USCI_B1 byte counter threshold I2CM_RXBUF=\$58C! USCI_B1 Receive Buffer 8 I2CM_TXBUF=\$58E! USCI_B1 Transmit Buffer 8 I2CM_I2COA0=\$594! USCI_B1 I2C Own Address 0 -I2CM_ADDRX=\$59C! USCI_B1 Received Address Register +I2CM_ADDRX=\$59C! USCI_B1 Received Address Register I2CM_I2CSA=\$5A0! USCI_B1 I2C Slave Address I2CM_IE=\$5AA! USCI_B1 Interrupt Enable I2CM_IFG=\$5AC! USCI_B1 Interrupt Flags Register @@ -355,12 +355,12 @@ I2CM_IFG=\$5AC! USCI_B1 Interrupt Flags Register I2CS_CTLW0=\$580! USCI_B1 Control Word Register 0 I2CS_CTLW1=\$582! USCI_B1 Control Word Register 1 I2CS_BRW=\$586! USCI_B1 Baud Word Rate 0 -I2CS_STATW=\$588! USCI_B1 status word -I2CS_TBCNT=\$58A! USCI_B1 byte counter threshold +I2CS_STATW=\$588! USCI_B1 status word +I2CS_TBCNT=\$58A! USCI_B1 byte counter threshold I2CS_RXBUF=\$58C! USCI_B1 Receive Buffer 8 I2CS_TXBUF=\$58E! USCI_B1 Transmit Buffer 8 I2CS_I2COA0=\$594! USCI_B1 I2C Own Address 0 -I2CS_ADDRX=\$59C! USCI_B1 Received Address Register +I2CS_ADDRX=\$59C! USCI_B1 Received Address Register I2CS_I2CSA=\$5A0! USCI_B1 I2C Slave Address I2CS_IE=\$5AA! USCI_B1 Interrupt Enable I2CS_IFG=\$5AC! USCI_B1 Interrupt Flags Register diff --git a/inc/MSP430FR2355.pat b/inc/MSP430FR2355.pat index 708fb65..4e52a47 100644 --- a/inc/MSP430FR2355.pat +++ b/inc/MSP430FR2355.pat @@ -44,61 +44,89 @@ INFO_LEN=\$0200! ! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst ! those addresses are usable with the symbolic assembler ! ---------------------------------------------- -! FastForth INFO +! FastForth INFO addresses ! ---------------------------------------------- FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of default INI_SOFT_APP -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +! +INIT_DOXXX=\$182C! MOV #INIT_DOXXX,X \ te restore DOxxx registers +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +! +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ -TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value) +TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value) TLV_LEN=\$0032! DEVICEID=\$1A04! - +! ! ============================================ ! RAM ! ============================================ RAM_ORG=\$2000! RAM_LEN=\$1000! - +! ! ---------------------------------------------- ! FORTH RAM areas : ! ---------------------------------------------- @@ -106,55 +134,51 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes - +! ! ---------------------------------------------- ! FastForth RAM memory map (>= 1k): ! ---------------------------------------------- -LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT -LSATCK=\$2000! \ leave stack, grow up -PSTACK=\$2080! \ parameter stack, grow down -RSTACK=\$20E0! \ Return stack, grow down - -PAD_I2CADR=\$20E0! \ RX I2C address -PAD_I2CCNT=\$20E2! \ count max -PAD_ORG=\$20E4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$2138! \ TX I2C address -TIB_I2CCNT=\$213A! \ count of bytes -TIB_ORG=\$213C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$2190! \ a good address for HOLDS -HOLD_BASE=\$21B2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- +LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT +LSATCK=\$2000! leave stack, grow up +PSTACK=\$2080! parameter stack, grow down +RSTACK=\$20E0! Return stack, grow down +! +PAD_I2CADR=\$20E0! RX I2C address +PAD_I2CCNT=\$20E2! count max +PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$2138! TX I2C address +TIB_I2CCNT=\$213A! count of bytes +TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$2190! base address for HOLDS +HOLD_BASE=\$21B2! BASE HOLD area, grow down +! HP=\$21B2! HOLD ptr -CAPS=\$21B4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$21B6! -LAST_THREAD=\$21B8! -LAST_CFA=\$21BA! -LAST_PSP=\$21BC! - -STATEADR=\$21BE! Interpreter state - -SOURCE_LEN=\$21C0! len of input stream -SOURCE_ORG=\$21C2! adr of input stream -TOIN=\$21C4! >IN -DP=\$21C6! dictionary ptr - -LASTVOC=\$21C8! keep VOC-LINK -CONTEXT=\$21CA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$21DA! CURRENT dictionnary ptr - -BASEADR=\$21DC! numeric base, must be defined before first reset ! -LINE=\$21DE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$21B4! +LAST_THREAD=\$21B6! +LAST_CFA=\$21B8! +LAST_PSP=\$21BA! +! +STATEADR=\$21BC! Interpreter state +BASEADR=\$21BE! +CAPS=\$21C0 ! +! +SOURCE_LEN=\$21C2! len of input stream +SOURCE_ORG=\$21C4! adr of input stream +TOIN=\$21C6! >IN +DP=\$21C8! dictionary ptr +! +LASTVOC=\$21CA! keep VOC-LINK +CURRENT=\$21CC! CURRENT dictionnary ptr +CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- !21E0! 28 RAM bytes free ! --------------------------------------- - +! ! --------------------------------------- ! SD buffer ! --------------------------------------- @@ -162,7 +186,7 @@ SD_BUF_I2ADR=\$21FC! SD_BUF_I2CNT=\$21FE! SD_BUF=\$2200! \ SD_Card buffer SD_BUF_END=\$2400! - +! ! --------------------------------------- ! FAT16 FileSystemInfos ! --------------------------------------- @@ -175,7 +199,7 @@ OrgFAT2=\$240C! OrgRootDir=\$240E! OrgClusters=\$2410! Sector of Cluster 0 SecPerClus=\$2412! - +! ! --------------------------------------- ! SD command ! --------------------------------------- @@ -188,7 +212,7 @@ SD_CMD_FRM4=\$2418! HH:CMD word access SD_CMD_FRM5=\$2419! CMD byte access SectorL=\$241A! 2 words SectorH=\$241C! - +! ! --------------------------------------- ! BUFFER management ! --------------------------------------- @@ -244,12 +268,12 @@ HDLL_CurClust=14! Current ClusterLo HDLH_CurClust=16! Current ClusterHi (T as 3Th byte) HDLL_CurSize=18! written size / not yet read size (Long) HDLH_CurSize=20! written size / not yet read size (Long) -HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE" -HDLW_PrevLEN=24! previous LEN -HDLW_PrevORG=26! previous ORG +HDLW_BUFofst=22! SD BUFFER offset ; used by LOAD" and by WRITE" +HDLW_PrevLEN=24! CIB LEN of previous handle +HDLW_PrevORG=26! CIB ORG of previous handle -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2438! @@ -267,50 +291,59 @@ SD_LEN=\$16E! ! FRAM MAIN ! ============================================ MAIN_ORG=\$8000! Code space start - +! ---------------------------------------------- SLEEP=\$8000! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$800A! CODE compiled by LITERAL -XSQUOTE=\$8014! CODE compiled by S" and S_ -HEREXEC=\$8028! CODE HERE and BEGIN execute address -QFBRAN=\$8034! CODE compiled by IF UNTIL -BRAN=\$803A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$803C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$803E! CODE compiled by DO -XPLOOP=\$804E! CODE compiled by +LOOP -XLOOP=\$8060! CODE compiled by LOOP -MUSMOD=\$8066! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$8078! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$8080! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$80AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$80AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$80BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$80CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$80D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$80E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$80EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$801E! CODE compiled by S" and S_ +HEREXEC=\$8032! CODE HERE and BEGIN execute address +MUSMOD=\$803E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$8050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$8058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$8082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$8084! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$8094! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$80A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$80AC! CODE compiled by IF UNTIL +BRAN=\$80B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$80B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$80B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$80C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$80F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$812A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$8136! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$80D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$8108! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$8112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +!------------------------------------------------------------------------------- +! UART FASTFORTH +!------------------------------------------------------------------------------- +UART_INIT_TERM=\$8154! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$817E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$8184! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_WARM=\$8186! WARM address +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. !------------------------------------------------------------------------------- -UART_COLD_TERM=\$8194! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$819C! ASM CODE, content of WARM+2 by default -UART_RXON=\$81C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$81C8! ASM CODE, called by ACCEPT before RX char LF. +! I2C FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$81B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$818E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$81BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$81BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +I2C_ACCEPT=\$8144! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$8146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$8156! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$8156! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$8158! asm CODE, content of WARM+2 by default +I2C_WARM=\$8180! WARM address !------------------------------------------------------------------------------- +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR2355 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures -JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ! reset by wipe and by S1+<reset> +JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ! reset by -1 SYS and by S1+<reset> JTAG_SIG2=\$FF82! if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked BSL_SIG1=\$FF84! BSL_SIG2=\$FF86! @@ -325,7 +358,7 @@ JTAG_PASSWORD=\$FF88! 256 bits BSL_PASSWORD=\$FFE0! 256 bits VECT_ORG=\$FFCE! FFCE-FFFF : 24 vectors + reset VECT_LEN=\$32! - +! ---------------------------------------------- P4_VEC=\$FFCE! P3_VEC=\$FFD0! P2_VEC=\$FFD2! @@ -333,7 +366,7 @@ P1_VEC=\$FFD4! SAC1SAC3_VEC=\$FFD6! SAC0SAC2_VEC=\$FFD8! ECOMPX_VEC=\$FFDA! -ADC10_VEC=\$FFDC! +ADC12_VEC=\$FFDC! EUSCI_B1_VEC=\$FFDE! EUSCI_B0_VEC=\$FFE0! EUSCI_A1_VEC=\$FFE2! @@ -424,6 +457,7 @@ CSCTL8=\$190! \ CS control 8 FRCTLCTL0=\$1A0! \ FRAM control 0 +FRCTLCTL0_H=\$1A1! \ FRAM control 0_H: FRAM password byte = $A5 GCCTL0=\$1A4! \ General control 0 GCCTL1=\$1A6! \ General control 1 @@ -719,16 +753,16 @@ ICCILSR7=\$6C12! \ Interrupt Compare Controller Interrupt Level Setting Register -ADC10CTL0=\$700! \ ADC10_B Control register 0 -ADC10CTL1=\$702! \ ADC10_B Control register 1 -ADC10CTL2=\$704! \ ADC10_B Control register 2 -ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold -ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold -ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 -ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register -ADC10IE=\$71A! \ ADC10_B Interrupt Enable -ADC10IFG=\$71C! \ ADC10_B Interrupt Flags -ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word +ADC12CTL0=\$700! \ ADC12_B Control register 0 +ADC12CTL1=\$702! \ ADC12_B Control register 1 +ADC12CTL2=\$704! \ ADC12_B Control register 2 +ADC12LO=\$706! \ ADC12_B Window Comparator Low Threshold +ADC12HI=\$708! \ ADC12_B Window Comparator High Threshold +ADC12MCTL0=\$70A! \ ADC12_B Memory Control Register 0 +ADC12MEM0=\$712! \ ADC12_B Conversion Memory Register +ADC12IE=\$71A! \ ADC12_B Interrupt Enable +ADC12IFG=\$71C! \ ADC12_B Interrupt Flags +ADC12IV=\$71E! \ ADC12_B Interrupt Vector Word ADCON=\$10! ADCSTART=\$03! diff --git a/inc/MSP430FR2433.inc b/inc/MSP430FR2433.inc index d117a81..e7d4ddb 100644 --- a/inc/MSP430FR2433.inc +++ b/inc/MSP430FR2433.inc @@ -22,9 +22,9 @@ FR2_FAMILY ; ---------------------------------------------- PAGESIZE .equ 512 ; MPU unit ; ---------------------------------------------- -; BSL +; BSL ; ---------------------------------------------- -BSL1 .equ 01000h +BSL1 .equ 01000h BSL2 .equ 0FFC00h ; ---------------------------------------------- ; FRAM ; INFO B, TLV @@ -52,7 +52,7 @@ BSL_SIG1 .equ 0FF84h ; BSL_SIG2 .equ 0FF86h ; JTAG_PASSWORD .equ 0FF88h ; 256 bits BSL_PASSWORD .equ 0FFE0h ; 256 bits -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -72,25 +72,25 @@ VECT_LEN .equ 26h ; .org INTVECT ; FFDA-FFFF 18 vectors + reset ; -; .word reset ; FFDAh - P2 -; .word reset ; FFDCh - P1 -; .word reset ; FFDEh - ADC10 -; .word reset ; FFE0h - eUSCI_B0 -; .word reset ; FFE2h - eUSCI_A1 -; .word reset ; FFE4h - eUSCI_A0 -; .word reset ; FFE6h - WDT -; .word reset ; FFE8h - RTC -; .word reset ; FFEAh - TA3_x -; .word reset ; FFECh - TA3_0 -; .word reset ; FFEEh - TA2_x -; .word reset ; FFF0h - TA2_0 -; .word reset ; FFF2h - TA1_x -; .word reset ; FFF4h - TA1_0 -; .word reset ; FFF6h - TA0_x -; .word reset ; FFF8h - TA0_0 -; .word reset ; FFFAh - UserNMI -; .word reset ; FFFCh - SysNMI -; .word reset ; FFFEh - Reset +; .word reset ; FFDAh - P2 +; .word reset ; FFDCh - P1 +; .word reset ; FFDEh - ADC10 +; .word reset ; FFE0h - eUSCI_B0 +; .word reset ; FFE2h - eUSCI_A1 +; .word reset ; FFE4h - eUSCI_A0 +; .word reset ; FFE6h - WDT +; .word reset ; FFE8h - RTC +; .word reset ; FFEAh - TA3_x +; .word reset ; FFECh - TA3_0 +; .word reset ; FFEEh - TA2_x +; .word reset ; FFF0h - TA2_0 +; .word reset ; FFF2h - TA1_x +; .word reset ; FFF4h - TA1_0 +; .word reset ; FFF6h - TA0_x +; .word reset ; FFF8h - TA0_0 +; .word reset ; FFFAh - UserNMI +; .word reset ; FFFCh - SysNMI +; .word reset ; FFFEh - Reset ; ---------------------------------------------------------------------- ; MSP430FR2433 Peripheral File Map ; ---------------------------------------------------------------------- @@ -131,21 +131,21 @@ LOCKLPM5 .equ 1 ; bit position ; ---------------------------------------------------------------------- ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -SYSCTL .equ SYS_SFR + 00h ; System control -SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area -SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control -SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 -SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 -SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 -SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 -SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator -SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator -SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator -SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator -SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 -SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 -SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 - +SYSCTL .equ SYS_SFR + 00h ; System control +SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area +SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control +SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 +SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 +SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 +SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 +SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator +SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator +SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator +SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator +SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 +SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 +SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 + ; SYS Control Bits ; ... @@ -198,7 +198,7 @@ P1DIR .equ PA_SFR + 04h ; Port 1 Direction P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1 -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag @@ -212,7 +212,7 @@ P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3 @@ -227,10 +227,10 @@ P3SEL1 .equ PB_SFR + 0Ch ; Port 3 Selection 1 ; ---------------------------------------------------------------------- RTC ; ---------------------------------------------------------------------- -RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control -RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector -RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo -RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter +RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control +RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector +RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo +RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter ; ---------------------------------------------------------------------- MPY_32 @@ -313,7 +313,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR2433.pat b/inc/MSP430FR2433.pat index 61b51fd..abc9ad6 100644 --- a/inc/MSP430FR2433.pat +++ b/inc/MSP430FR2433.pat @@ -30,48 +30,73 @@ INFO_LEN=\$0200! ! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst ! those addresses are usable with the symbolic assembler ! ---------------------------------------------- -! FastForth INFO +! FastForth INFO addresses ! ---------------------------------------------- FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -79,7 +104,6 @@ TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value) TLV_LEN=\$0080! DEVICEID=\$1A04! - ! ============================================ ! RAM ! ============================================ @@ -93,53 +117,49 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! --------------------------------------- ! FastForth RAM memory map (>= 1k): ! --------------------------------------- -LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT -LSATCK=\$2000! \ leave stack, grow up -PSTACK=\$2080! \ parameter stack, grow down -RSTACK=\$20E0! \ Return stack, grow down - -PAD_I2CADR=\$20E0! \ RX I2C address -PAD_I2CCNT=\$20E2! \ count max -PAD_ORG=\$20E4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$2138! \ TX I2C address -TIB_I2CCNT=\$213A! \ count of bytes -TIB_ORG=\$213C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$2190! \ a good address for HOLDS -HOLD_BASE=\$21B2! \ BASE HOLD area, grow down - -! --------------------------------------- -! NOT SAVED VARIABLES -! --------------------------------------- +LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT +LSATCK=\$2000! leave stack, grow up +PSTACK=\$2080! parameter stack, grow down +RSTACK=\$20E0! Return stack, grow down +! +PAD_I2CADR=\$20E0! RX I2C address +PAD_I2CCNT=\$20E2! count max +PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$2138! TX I2C address +TIB_I2CCNT=\$213A! count of bytes +TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$2190! base address for HOLDS +HOLD_BASE=\$21B2! BASE HOLD area, grow down +! HP=\$21B2! HOLD ptr -CAPS=\$21B4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$21B6! -LAST_THREAD=\$21B8! -LAST_CFA=\$21BA! -LAST_PSP=\$21BC! - -STATEADR=\$21BE! Interpreter state - -SOURCE_LEN=\$21C0! len of input stream -SOURCE_ORG=\$21C2! adr of input stream -TOIN=\$21C4! >IN -DP=\$21C6! dictionary ptr - -LASTVOC=\$21C8! keep VOC-LINK -CONTEXT=\$21CA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$21DA! CURRENT dictionnary ptr - -BASEADR=\$21DC! numeric base, must be defined before first reset ! -LINE=\$21DE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$21B4! +LAST_THREAD=\$21B6! +LAST_CFA=\$21B8! +LAST_PSP=\$21BA! +! +STATEADR=\$21BC! Interpreter state +BASEADR=\$21BE! +CAPS=\$21C0 ! +! +SOURCE_LEN=\$21C2! len of input stream +SOURCE_ORG=\$21C4! adr of input stream +TOIN=\$21C6! >IN +DP=\$21C8! dictionary ptr +! +LASTVOC=\$21CA! keep VOC-LINK +CURRENT=\$21CC! CURRENT dictionnary ptr +CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!21E0! 28 RAM bytes free +!21E0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -151,7 +171,7 @@ SD_BUF=\$2200! \ SD_Card buffer BUFEND=\$2400! ! --------------------------------------- -! FAT16 FileSystemInfos +! FAT16 FileSystemInfos ! --------------------------------------- FATtype=\$2402! BS_FirstSectorL=\$2404! @@ -179,7 +199,7 @@ SectorH=\$241C! ! --------------------------------------- ! BUFFER management ! --------------------------------------- -BufferPtr=\$241E! +BufferPtr=\$241E! BufferLen=\$2420! ! --------------------------------------- @@ -187,8 +207,8 @@ BufferLen=\$2420! ! --------------------------------------- ClusterL=\$2422! 16 bits wide (FAT16) ClusterH=\$2424! 16 bits wide (FAT16) -NewClusterL=\$2426! 16 bits wide (FAT16) -NewClusterH=\$2428! 16 bits wide (FAT16) +NewClusterL=\$2426! 16 bits wide (FAT16) +NewClusterH=\$2428! 16 bits wide (FAT16) CurFATsector=\$242A! ! --------------------------------------- @@ -196,7 +216,7 @@ CurFATsector=\$242A! ! --------------------------------------- DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory -EntryOfst=\$2430! +EntryOfst=\$2430! ! --------------------------------------- ! Handle Pointer @@ -212,7 +232,7 @@ EndOfPath=\$2436! ! --------------------------------------- ! Handle structure ! --------------------------------------- -! three handle tokens : +! three handle tokens : ! token = 0 : free handle ! token = 1 : file to read ! token = 2 : file updated (write) @@ -236,7 +256,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2438! @@ -257,51 +277,59 @@ MAIN_ORG=\$C400! Code space start SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$C40A! CODE compiled by LITERAL -XSQUOTE=\$C414! CODE compiled by S" and S_ -HEREXEC=\$C428! CODE HERE and BEGIN execute address -QFBRAN=\$C434! CODE compiled by IF UNTIL -BRAN=\$C43A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$C43C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$C43E! CODE compiled by DO -XPLOOP=\$C44E! CODE compiled by +LOOP -XLOOP=\$C460! CODE compiled by LOOP -MUSMOD=\$C466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$C478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$C480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$C4AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$C4AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$C4BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$C4CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$C4D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$C4E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$C4EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$C41E! CODE compiled by S" and S_ +HEREXEC=\$C432! CODE HERE and BEGIN execute address +MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$C494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$C4AC! CODE compiled by IF UNTIL +BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$C4F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$C52A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$C536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$C594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$C59C! ASM CODE, content of WARM+2 by default -UART_RXON=\$C5C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$C5C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$C5B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$C58E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$C5BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$C5BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$C584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$C586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$C544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$C556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$C556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$C558! asm CODE, content of WARM+2 by default +I2C_WARM=\$C580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR2433 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset> JTAG_SIG2=\$FF82! if JTAG_SIG <> |\$FFFFFFFF, \$00000000|, SBW and JTAG are locked -BSL_SIG1=\$FF84! -BSL_SIG2=\$FF86! +BSL_SIG1=\$FF84! +BSL_SIG2=\$FF86! I2CSLA0=\$FFA2! UCBxI2COA0 default value address I2CSLA1=\$FFA4! UCBxI2COA1 default value address I2CSLA2=\$FFA6! UCBxI2COA2 default value address @@ -371,41 +399,41 @@ SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 PMMCTL1=\$122! \ PMM Control 0 PMMCTL2=\$124! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -SYSCTL=\$140! \ System control -SYSBSLC=\$142! \ Bootstrap loader configuration area -SYSJMBC=\$146! \ JTAG mailbox control -SYSJMBI0=\$148! \ JTAG mailbox input 0 -SYSJMBI1=\$14A! \ JTAG mailbox input 1 -SYSJMBO0=\$14C! \ JTAG mailbox output 0 -SYSJMBO1=\$14E! \ JTAG mailbox output 1 -SYSUNIV=\$15A! \ User NMI vector generator -SYSSNIV=\$15C! \ System NMI vector generator -SYSRSTIV=\$15E! \ Reset vector generator -SYSCFG0=\$160! \ System configuration 0 -SYSCFG1=\$162! \ System configuration 1 -SYSCFG2=\$164! \ System configuration 2 - -CSCTL0=\$180! \ CS control 0 -CSCTL1=\$182! \ CS control 1 -CSCTL2=\$184! \ CS control 2 -CSCTL3=\$186! \ CS control 3 -CSCTL4=\$188! \ CS control 4 -CSCTL5=\$18A! \ CS control 5 -CSCTL6=\$18C! \ CS control 6 -CSCTL7=\$18E! \ CS control 7 -CSCTL8=\$190! \ CS control 8 - -FRCTLCTL0=\$1A0! \ FRAM control 0 -GCCTL0=\$1A4! \ General control 0 -GCCTL1=\$1A6! \ General control 1 - -CRC16DI=\$1C0! \ CRC data input -CRCDIRB=\$1C2! \ CRC data input reverse byte -CRCINIRES=\$1C4! \ CRC initialization and result -CRCRESR=\$1C6! \ CRC result reverse byte +SYSCTL=\$140! \ System control +SYSBSLC=\$142! \ Bootstrap loader configuration area +SYSJMBC=\$146! \ JTAG mailbox control +SYSJMBI0=\$148! \ JTAG mailbox input 0 +SYSJMBI1=\$14A! \ JTAG mailbox input 1 +SYSJMBO0=\$14C! \ JTAG mailbox output 0 +SYSJMBO1=\$14E! \ JTAG mailbox output 1 +SYSUNIV=\$15A! \ User NMI vector generator +SYSSNIV=\$15C! \ System NMI vector generator +SYSRSTIV=\$15E! \ Reset vector generator +SYSCFG0=\$160! \ System configuration 0 +SYSCFG1=\$162! \ System configuration 1 +SYSCFG2=\$164! \ System configuration 2 + +CSCTL0=\$180! \ CS control 0 +CSCTL1=\$182! \ CS control 1 +CSCTL2=\$184! \ CS control 2 +CSCTL3=\$186! \ CS control 3 +CSCTL4=\$188! \ CS control 4 +CSCTL5=\$18A! \ CS control 5 +CSCTL6=\$18C! \ CS control 6 +CSCTL7=\$18E! \ CS control 7 +CSCTL8=\$190! \ CS control 8 + +FRCTLCTL0=\$1A0! \ FRAM control 0 +GCCTL0=\$1A4! \ General control 0 +GCCTL1=\$1A6! \ General control 1 + +CRC16DI=\$1C0! \ CRC data input +CRCDIRB=\$1C2! \ CRC data input reverse byte +CRCINIRES=\$1C4! \ CRC initialization and result +CRCRESR=\$1C6! \ CRC result reverse byte WDTCTL=\$1CC! \ WDT control register @@ -448,54 +476,54 @@ P3REN=\$226! P3SEL0=\$22A! P3SEL1=\$22C! -RTCCTL=\$300! \ RTC control -RTCIV=\$304! \ RTC interrupt vector word -RTCMOD=\$308! \ RTC modulo -RTCCNT=\$30C! \ RTC counter register +RTCCTL=\$300! \ RTC control +RTCIV=\$304! \ RTC interrupt vector word +RTCMOD=\$308! \ RTC modulo +RTCCNT=\$30C! \ RTC counter register TACLR=4! TAIFG=1! CCIFG=1! -TA0CTL=\$380! \ TA0 control -TA0CCTL0=\$382! \ Capture/compare control 0 -TA0CCTL1=\$384! \ Capture/compare control 1 -TA0CCTL2=\$386! \ Capture/compare control 2 -TA0R=\$390! \ TA0 counter register -TA0CCR0=\$392! \ Capture/compare register 0 -TA0CCR1=\$394! \ Capture/compare register 1 -TA0CCR2=\$396! \ Capture/compare register 2 -TA0EX0=\$3A0! \ TA0 expansion register 0 -TA0IV=\$3AE! \ TA0 interrupt vector - -TA1CTL=\$3C0! \ TA1 control -TA1CCTL0=\$3C2! \ Capture/compare control 0 -TA1CCTL1=\$3C4! \ Capture/compare control 1 -TA1CCTL2=\$3C6! \ Capture/compare control 2 -TA1R=\$3D0! \ TA1 counter register -TA1CCR0=\$3D2! \ Capture/compare register 0 -TA1CCR1=\$3D4! \ Capture/compare register 1 -TA1CCR2=\$3D6! \ Capture/compare register 2 -TA1EX0=\$3E0! \ TA1 expansion register 0 -TA1IV=\$3EE! \ TA1 interrupt vector - -TA2CTL=\$400! \ TA2 control -TA2CCTL0=\$402! \ Capture/compare control 0 -TA2CCTL1=\$404! \ Capture/compare control 1 -TA2R=\$410! \ TA2 counter register -TA2CCR0=\$412! \ Capture/compare register 0 -TA2CCR1=\$414! \ Capture/compare register 1 -TA2EX0=\$420! \ TA2 expansion register 0 -TA2IV=\$42E! \ TA2 interrupt vector - -TA3CTL=\$440! \ TA3 control -TA3CCTL0=\$442! \ Capture/compare control 0 -TA3CCTL1=\$444! \ Capture/compare control 1 -TA3R=\$450! \ TA3 counter register -TA3CCR0=\$452! \ Capture/compare register 0 -TA3CCR1=\$454! \ Capture/compare register 1 -TA3EX0=\$460! \ TA3 expansion register 0 -TA3IV=\$46E! \ TA3 interrupt vector +TA0CTL=\$380! \ TA0 control +TA0CCTL0=\$382! \ Capture/compare control 0 +TA0CCTL1=\$384! \ Capture/compare control 1 +TA0CCTL2=\$386! \ Capture/compare control 2 +TA0R=\$390! \ TA0 counter register +TA0CCR0=\$392! \ Capture/compare register 0 +TA0CCR1=\$394! \ Capture/compare register 1 +TA0CCR2=\$396! \ Capture/compare register 2 +TA0EX0=\$3A0! \ TA0 expansion register 0 +TA0IV=\$3AE! \ TA0 interrupt vector + +TA1CTL=\$3C0! \ TA1 control +TA1CCTL0=\$3C2! \ Capture/compare control 0 +TA1CCTL1=\$3C4! \ Capture/compare control 1 +TA1CCTL2=\$3C6! \ Capture/compare control 2 +TA1R=\$3D0! \ TA1 counter register +TA1CCR0=\$3D2! \ Capture/compare register 0 +TA1CCR1=\$3D4! \ Capture/compare register 1 +TA1CCR2=\$3D6! \ Capture/compare register 2 +TA1EX0=\$3E0! \ TA1 expansion register 0 +TA1IV=\$3EE! \ TA1 interrupt vector + +TA2CTL=\$400! \ TA2 control +TA2CCTL0=\$402! \ Capture/compare control 0 +TA2CCTL1=\$404! \ Capture/compare control 1 +TA2R=\$410! \ TA2 counter register +TA2CCR0=\$412! \ Capture/compare register 0 +TA2CCR1=\$414! \ Capture/compare register 1 +TA2EX0=\$420! \ TA2 expansion register 0 +TA2IV=\$42E! \ TA2 interrupt vector + +TA3CTL=\$440! \ TA3 control +TA3CCTL0=\$442! \ Capture/compare control 0 +TA3CCTL1=\$444! \ Capture/compare control 1 +TA3R=\$450! \ TA3 counter register +TA3CCR0=\$452! \ Capture/compare register 0 +TA3CCR1=\$454! \ Capture/compare register 1 +TA3EX0=\$460! \ TA3 expansion register 0 +TA3IV=\$46E! \ TA3 interrupt vector MPY=\$4C0! \ 16-bit operand 1 - multiply MPYS=\$4C2! \ 16-bit operand 1 - signed multiply @@ -522,89 +550,89 @@ RES3=\$4EA! \ 32 x 32 result 3 - most significant word MPY32CTL0=\$4EC! \ MPY32 control register 0 -UCA0CTLW0=\$500! \ eUSCI_A control word 0 -UCA0CTLW1=\$502! \ eUSCI_A control word 1 -UCA0BRW=\$506! -UCA0BR0=\$506! \ eUSCI_A baud rate 0 -UCA0BR1=\$507! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$508! \ eUSCI_A modulation control -UCA0STAT=\$50A! \ eUSCI_A status -UCA0RXBUF=\$50C! \ eUSCI_A receive buffer -UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer -UCA0ABCTL=\$510! \ eUSCI_A LIN control -UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control -UCA0IE=\$51A! \ eUSCI_A interrupt enable -UCA0IFG=\$51C! \ eUSCI_A interrupt flags -UCA0IV=\$51E! \ eUSCI_A interrupt vector word - -UCA1CTLW0=\$520! \ eUSCI_A control word 0 -UCA1CTLW1=\$522! \ eUSCI_A control word 1 -UCA1BRW=\$526! -UCA1BR0=\$526! \ eUSCI_A baud rate 0 -UCA1BR1=\$527! \ eUSCI_A baud rate 1 -UCA1MCTLW=\$528! \ eUSCI_A modulation control -UCA1STAT=\$52A! \ eUSCI_A status -UCA1RXBUF=\$52C! \ eUSCI_A receive buffer -UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer -UCA1ABCTL=\$530! \ eUSCI_A LIN control -UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control -UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control -UCA1IE=\$53A! \ eUSCI_A interrupt enable -UCA1IFG=\$53C! \ eUSCI_A interrupt flags -UCA1IV=\$53E! \ eUSCI_A interrupt vector word - -UCB0CTLW0=\$540! \ eUSCI_B control word 0 -UCB0CTLW1=\$542! \ eUSCI_B control word 1 -UCB0BRW=\$546! -UCB0BR0=\$546! \ eUSCI_B bit rate 0 -UCB0BR1=\$547! \ eUSCI_B bit rate 1 -UCB0STATW=\$548! \ eUSCI_B status word -UCBCNT0=\$549! \ eUSCI_B hardware count -UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$54C! \ eUSCI_B receive buffer -UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$55C! \ eUSCI_B received address -UCB0ADDMASK=\$55E! \ eUSCI_B address mask -UCB0I2CSA=\$560! \ eUSCI I2C slave address -UCB0IE=\$56A! \ eUSCI interrupt enable -UCB0IFG=\$56C! \ eUSCI interrupt flags -UCB0IV=\$56E! \ eUSCI interrupt vector word +UCA0CTLW0=\$500! \ eUSCI_A control word 0 +UCA0CTLW1=\$502! \ eUSCI_A control word 1 +UCA0BRW=\$506! +UCA0BR0=\$506! \ eUSCI_A baud rate 0 +UCA0BR1=\$507! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$508! \ eUSCI_A modulation control +UCA0STAT=\$50A! \ eUSCI_A status +UCA0RXBUF=\$50C! \ eUSCI_A receive buffer +UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer +UCA0ABCTL=\$510! \ eUSCI_A LIN control +UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control +UCA0IE=\$51A! \ eUSCI_A interrupt enable +UCA0IFG=\$51C! \ eUSCI_A interrupt flags +UCA0IV=\$51E! \ eUSCI_A interrupt vector word + +UCA1CTLW0=\$520! \ eUSCI_A control word 0 +UCA1CTLW1=\$522! \ eUSCI_A control word 1 +UCA1BRW=\$526! +UCA1BR0=\$526! \ eUSCI_A baud rate 0 +UCA1BR1=\$527! \ eUSCI_A baud rate 1 +UCA1MCTLW=\$528! \ eUSCI_A modulation control +UCA1STAT=\$52A! \ eUSCI_A status +UCA1RXBUF=\$52C! \ eUSCI_A receive buffer +UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer +UCA1ABCTL=\$530! \ eUSCI_A LIN control +UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control +UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control +UCA1IE=\$53A! \ eUSCI_A interrupt enable +UCA1IFG=\$53C! \ eUSCI_A interrupt flags +UCA1IV=\$53E! \ eUSCI_A interrupt vector word + +UCB0CTLW0=\$540! \ eUSCI_B control word 0 +UCB0CTLW1=\$542! \ eUSCI_B control word 1 +UCB0BRW=\$546! +UCB0BR0=\$546! \ eUSCI_B bit rate 0 +UCB0BR1=\$547! \ eUSCI_B bit rate 1 +UCB0STATW=\$548! \ eUSCI_B status word +UCBCNT0=\$549! \ eUSCI_B hardware count +UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$54C! \ eUSCI_B receive buffer +UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$55C! \ eUSCI_B received address +UCB0ADDMASK=\$55E! \ eUSCI_B address mask +UCB0I2CSA=\$560! \ eUSCI I2C slave address +UCB0IE=\$56A! \ eUSCI interrupt enable +UCB0IFG=\$56C! \ eUSCI interrupt flags +UCB0IV=\$56E! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -BAKMEM0=\$660! \ Backup Memory 0 -BAKMEM1=\$662! \ Backup Memory 1 -BAKMEM2=\$664! \ Backup Memory 2 -BAKMEM3=\$666! \ Backup Memory 3 -BAKMEM4=\$668! \ Backup Memory 4 -BAKMEM5=\$66A! \ Backup Memory 5 -BAKMEM6=\$66C! \ Backup Memory 6 -BAKMEM7=\$66E! \ Backup Memory 7 -BAKMEM8=\$670! \ Backup Memory 8 -BAKMEM9=\$672! \ Backup Memory 9 -BAKMEM10=\$674! \ Backup Memory 10 -BAKMEM11=\$676! \ Backup Memory 11 -BAKMEM12=\$678! \ Backup Memory 12 -BAKMEM13=\$67A! \ Backup Memory 13 -BAKMEM14=\$67C! \ Backup Memory 14 -BAKMEM15=\$67E! \ Backup Memory 15 - -ADC10CTL0=\$700! \ ADC10_B Control register 0 -ADC10CTL1=\$702! \ ADC10_B Control register 1 -ADC10CTL2=\$704! \ ADC10_B Control register 2 -ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold -ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold -ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 -ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register -ADC10IE=\$71A! \ ADC10_B Interrupt Enable -ADC10IFG=\$71C! \ ADC10_B Interrupt Flags -ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word +BAKMEM0=\$660! \ Backup Memory 0 +BAKMEM1=\$662! \ Backup Memory 1 +BAKMEM2=\$664! \ Backup Memory 2 +BAKMEM3=\$666! \ Backup Memory 3 +BAKMEM4=\$668! \ Backup Memory 4 +BAKMEM5=\$66A! \ Backup Memory 5 +BAKMEM6=\$66C! \ Backup Memory 6 +BAKMEM7=\$66E! \ Backup Memory 7 +BAKMEM8=\$670! \ Backup Memory 8 +BAKMEM9=\$672! \ Backup Memory 9 +BAKMEM10=\$674! \ Backup Memory 10 +BAKMEM11=\$676! \ Backup Memory 11 +BAKMEM12=\$678! \ Backup Memory 12 +BAKMEM13=\$67A! \ Backup Memory 13 +BAKMEM14=\$67C! \ Backup Memory 14 +BAKMEM15=\$67E! \ Backup Memory 15 + +ADC10CTL0=\$700! \ ADC10_B Control register 0 +ADC10CTL1=\$702! \ ADC10_B Control register 1 +ADC10CTL2=\$704! \ ADC10_B Control register 2 +ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold +ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold +ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 +ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register +ADC10IE=\$71A! \ ADC10_B Interrupt Enable +ADC10IFG=\$71C! \ ADC10_B Interrupt Flags +ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word ADCON=\$10! ADCSTART=\$03! diff --git a/inc/MSP430FR2476.inc b/inc/MSP430FR2476.inc index d506fb3..745bf42 100644 --- a/inc/MSP430FR2476.inc +++ b/inc/MSP430FR2476.inc @@ -25,7 +25,7 @@ FR2_FAMILY ; ---------------------------------------------- PAGESIZE .equ 512 ; MPU unit ; ---------------------------------------------- -; BSL +; BSL ; ---------------------------------------------- BSL1 .equ 01000h ; to 17FFh CapTivateLib .equ 0C0000h ; to 0C3FFFh @@ -42,7 +42,7 @@ TLV_LEN .equ 00080h ; ; RAM ; ---------------------------------------------- RAM_ORG .equ 02000h ; to 3FFFh -RAM_LEN .equ 02000h ; +RAM_LEN .equ 02000h ; ; ---------------------------------------------- ; FRAM ; ---------------------------------------------- @@ -58,7 +58,7 @@ BSL_SIG2 .equ 0FF86h ; JTAG_PASSWORD .equ 0FF88h ; 256 bits BSL_PASSWORD .equ 0FFE0h ; 256 bits BSL_I2C_ADRE .equ 0FFA0h ; -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -79,34 +79,34 @@ VECT_LEN .equ 38h ; .org INTVECT ; FFDA-FFFF 27 vectors + reset ; -; .word reset ; 0FFC8h - CapTivate -; .word reset ; 0FFCAh - eCOMP0 -; .word reset ; 0FFCCh - P6 -; .word reset ; 0FFCEh - P5 -; .word reset ; 0FFD0h - P4 -; .word reset ; 0FFD2h - P3 -; .word reset ; 0FFD4h - P2 -; .word reset ; 0FFD6h - P1 -; .word reset ; 0FFD8h - ADC10 -; .word reset ; 0FFDAh - eUSCI_B1 -; .word reset ; 0FFDCh - eUSCI_B0 -; .word reset ; 0FFDEh - eUSCI_A1 -; .word reset ; 0FFE0h - eUSCI_A0 -; .word reset ; 0FFE2h - WDT -; .word reset ; 0FFE4h - RTC -; .word reset ; 0FFE6h - TB0_x -; .word reset ; 0FFE8h - TB0_0 -; .word reset ; 0FFEAh - TA3_x -; .word reset ; 0FFECh - TA3_0 -; .word reset ; 0FFEEh - TA2_x -; .word reset ; 0FFF0h - TA2_0 -; .word reset ; 0FFF2h - TA1_x -; .word reset ; 0FFF4h - TA1_0 -; .word reset ; 0FFF6h - TA0_x -; .word reset ; 0FFF8h - TA0_0 -; .word reset ; 0FFFAh - UserNMI -; .word reset ; 0FFFCh - SysNMI -; .word reset ; 0FFFEh - Reset +; .word reset ; 0FFC8h - CapTivate +; .word reset ; 0FFCAh - eCOMP0 +; .word reset ; 0FFCCh - P6 +; .word reset ; 0FFCEh - P5 +; .word reset ; 0FFD0h - P4 +; .word reset ; 0FFD2h - P3 +; .word reset ; 0FFD4h - P2 +; .word reset ; 0FFD6h - P1 +; .word reset ; 0FFD8h - ADC10 +; .word reset ; 0FFDAh - eUSCI_B1 +; .word reset ; 0FFDCh - eUSCI_B0 +; .word reset ; 0FFDEh - eUSCI_A1 +; .word reset ; 0FFE0h - eUSCI_A0 +; .word reset ; 0FFE2h - WDT +; .word reset ; 0FFE4h - RTC +; .word reset ; 0FFE6h - TB0_x +; .word reset ; 0FFE8h - TB0_0 +; .word reset ; 0FFEAh - TA3_x +; .word reset ; 0FFECh - TA3_0 +; .word reset ; 0FFEEh - TA2_x +; .word reset ; 0FFF0h - TA2_0 +; .word reset ; 0FFF2h - TA1_x +; .word reset ; 0FFF4h - TA1_0 +; .word reset ; 0FFF6h - TA0_x +; .word reset ; 0FFF8h - TA0_0 +; .word reset ; 0FFFAh - UserNMI +; .word reset ; 0FFFCh - SysNMI +; .word reset ; 0FFFEh - Reset ; ---------------------------------------------------------------------- ; MSP430FR2476 Peripheral File Map @@ -134,7 +134,7 @@ eUSCI_B0_SFR .equ 0540h ; eUSCI_B0 eUSCI_B1_SFR .equ 0580h ; eUSCI_B1 BACK_MEM_SFR .equ 0660h ADC10_B_SFR .equ 0700h -eCOMP_SFR .equ 08F0h +eCOMP_SFR .equ 08F0h ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : LOCK PMM_LOCKLPM5 @@ -152,21 +152,21 @@ LOCKLPM5 .equ 1 ; bit position ; ---------------------------------------------------------------------- ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -SYSCTL .equ SYS_SFR + 00h ; System control -SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area -SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control -SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 -SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 -SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 -SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 -SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator -SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator -SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator -SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator -SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 -SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 -SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 - +SYSCTL .equ SYS_SFR + 00h ; System control +SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area +SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control +SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 +SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 +SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 +SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 +SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator +SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator +SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator +SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator +SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 +SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 +SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 + ; SYS Control Bits ; ... @@ -225,7 +225,7 @@ P1DIR .equ PA_SFR + 04h ; Port 1 Direction P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1 -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag @@ -239,7 +239,7 @@ P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3/4 @@ -266,7 +266,7 @@ P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag -P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word +P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word P4IN .equ PB_SFR + 01h ; Port 4 Input */ P4OUT .equ PB_SFR + 03h ; Port 4 Output @@ -278,7 +278,7 @@ P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag -P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word +P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT5/6 @@ -301,7 +301,7 @@ P5DIR .equ PC_SFR + 04h ; Port 5 Direction P5REN .equ PC_SFR + 06h ; Port 5 Resistor Enable P5SEL0 .equ PC_SFR + 0Ah ; Port 5 Selection 0 P5SEL1 .equ PC_SFR + 0Ch ; Port 5 Selection 1 -P5IV .equ PC_SFR + 0Eh ; Port 5 Interrupt Vector word +P5IV .equ PC_SFR + 0Eh ; Port 5 Interrupt Vector word P5SELC .set PC_SFR + 16h ; Port 5 Complement Selection P5IES .equ PC_SFR + 18h ; Port 5 Interrupt Edge Select P5IE .equ PC_SFR + 1Ah ; Port 5 Interrupt Enable @@ -317,15 +317,15 @@ P6SELC .set PC_SFR + 17h ; Port 6 Complement Selection P6IES .equ PC_SFR + 19h ; Port 6 Interrupt Edge Select P6IE .equ PC_SFR + 1Bh ; Port 6 Interrupt Enable P6IFG .equ PC_SFR + 1Dh ; Port 6 Interrupt Flag -P6IV .equ PC_SFR + 1Eh ; Port 6 Interrupt Vector word +P6IV .equ PC_SFR + 1Eh ; Port 6 Interrupt Vector word ; ---------------------------------------------------------------------- RTC ; ---------------------------------------------------------------------- -RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control -RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector -RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo -RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter +RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control +RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector +RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo +RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter ; ---------------------------------------------------------------------- MPY_32 @@ -402,7 +402,7 @@ TERM_STATW .equ eUSCI_B1_SFR + 08h ; USCI_B1 Status Word TERM_RXBUF .equ eUSCI_B1_SFR + 0Ch ; USCI_B1 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B1_SFR + 0Eh ; USCI_B1 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B1_SFR + 14h ; USCI_B1 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B1_SFR + 1Ch ; USCI_B1 Received Address Register +TERM_ADDRX .equ eUSCI_B1_SFR + 1Ch ; USCI_B1 Received Address Register TERM_I2CSA .equ eUSCI_B1_SFR + 20h ; USCI_B1 I2C Slave Address TERM_IE .equ eUSCI_B1_SFR + 2Ah ; USCI_B1 Interrupt Enable TERM_IFG .equ eUSCI_B1_SFR + 2Ch ; USCI_B1 Interrupt Flags Register diff --git a/inc/MSP430FR2476.pat b/inc/MSP430FR2476.pat index b3b4235..a671a15 100644 --- a/inc/MSP430FR2476.pat +++ b/inc/MSP430FR2476.pat @@ -47,42 +47,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -103,52 +128,47 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! ---------------------------------------------- ! FastForth RAM memory map (>= 1k): ! ---------------------------------------------- -LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT -LSATCK=\$2000! \ leave stack, grow up -PSTACK=\$2080! \ parameter stack, grow down -RSTACK=\$20E0! \ Return stack, grow down - -PAD_I2CADR=\$20E0! \ RX I2C address -PAD_I2CCNT=\$20E2! \ count max -PAD_ORG=\$20E4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$2138! \ TX I2C address -TIB_I2CCNT=\$213A! \ count of bytes -TIB_ORG=\$213C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$2190! \ a good address for HOLDS -HOLD_BASE=\$21B2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT +LSATCK=\$2000! leave stack, grow up +PSTACK=\$2080! parameter stack, grow down +RSTACK=\$20E0! Return stack, grow down +! +PAD_I2CADR=\$20E0! RX I2C address +PAD_I2CCNT=\$20E2! count max +PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$2138! TX I2C address +TIB_I2CCNT=\$213A! count of bytes +TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$2190! base address for HOLDS +HOLD_BASE=\$21B2! BASE HOLD area, grow down +! HP=\$21B2! HOLD ptr -CAPS=\$21B4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$21B6! -LAST_THREAD=\$21B8! -LAST_CFA=\$21BA! -LAST_PSP=\$21BC! - -STATEADR=\$21BE! Interpreter state - -SOURCE_LEN=\$21C0! len of input stream -SOURCE_ORG=\$21C2! adr of input stream -TOIN=\$21C4! >IN -DP=\$21C6! dictionary ptr - -LASTVOC=\$21C8! keep VOC-LINK -CONTEXT=\$21CA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$21DA! CURRENT dictionnary ptr - -BASEADR=\$21DC! numeric base, must be defined before first reset ! -LINE=\$21DE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$21B4! +LAST_THREAD=\$21B6! +LAST_CFA=\$21B8! +LAST_PSP=\$21BA! +! +STATEADR=\$21BC! Interpreter state +BASEADR=\$21BE! +CAPS=\$21C0 ! +! +SOURCE_LEN=\$21C2! len of input stream +SOURCE_ORG=\$21C4! adr of input stream +TOIN=\$21C6! >IN +DP=\$21C8! dictionary ptr +! +LASTVOC=\$21CA! keep VOC-LINK +CURRENT=\$21CC! CURRENT dictionnary ptr +CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- !21E0! 28 RAM bytes free ! --------------------------------------- @@ -162,7 +182,7 @@ SD_BUF=\$2200! \ SD_Card buffer BUFEND=\$2400! ! --------------------------------------- -! FAT16 FileSystemInfos +! FAT16 FileSystemInfos ! --------------------------------------- FATtype=\$2402! BS_FirstSectorL=\$2404! @@ -190,7 +210,7 @@ SectorH=\$241C! ! --------------------------------------- ! BUFFER management ! --------------------------------------- -BufferPtr=\$241E! +BufferPtr=\$241E! BufferLen=\$2420! ! --------------------------------------- @@ -198,8 +218,8 @@ BufferLen=\$2420! ! --------------------------------------- ClusterL=\$2422! 16 bits wide (FAT16) ClusterH=\$2424! 16 bits wide (FAT16) -NewClusterL=\$2426! 16 bits wide (FAT16) -NewClusterH=\$2428! 16 bits wide (FAT16) +NewClusterL=\$2426! 16 bits wide (FAT16) +NewClusterH=\$2428! 16 bits wide (FAT16) CurFATsector=\$242A! ! --------------------------------------- @@ -207,7 +227,7 @@ CurFATsector=\$242A! ! --------------------------------------- DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory -EntryOfst=\$2430! +EntryOfst=\$2430! ! --------------------------------------- ! Handle Pointer @@ -223,7 +243,7 @@ EndOfPath=\$2436! ! --------------------------------------- ! Handle structure ! --------------------------------------- -! three handle tokens : +! three handle tokens : ! token = 0 : free handle ! token = 1 : file to read ! token = 2 : file updated (write) @@ -247,7 +267,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2438! @@ -268,41 +288,49 @@ MAIN_ORG=\$8000! Code space start SLEEP=\$8000! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$800A! CODE compiled by LITERAL -XSQUOTE=\$8014! CODE compiled by S" and S_ -HEREXEC=\$8028! CODE HERE and BEGIN execute address -QFBRAN=\$8034! CODE compiled by IF UNTIL -BRAN=\$803A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$803C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$803E! CODE compiled by DO -XPLOOP=\$804E! CODE compiled by +LOOP -XLOOP=\$8060! CODE compiled by LOOP -MUSMOD=\$8066! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$8078! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$8080! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$80AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$80AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$80BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$80CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$80D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$80E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$80EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$801E! CODE compiled by S" and S_ +HEREXEC=\$8032! CODE HERE and BEGIN execute address +MUSMOD=\$803E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$8050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$8058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$8082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$8084! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$8094! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$80A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$80AC! CODE compiled by IF UNTIL +BRAN=\$80B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$80B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$80B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$80C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$80F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$812A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$8136! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$80D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$8108! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$8112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$8194! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$819C! ASM CODE, content of WARM+2 by default -UART_RXON=\$81C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$81C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$81B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$818E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$81BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$81BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$8154! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$817E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$8184! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$8186! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$8144! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$8146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$8156! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$8156! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$8158! asm CODE, content of WARM+2 by default +I2C_WARM=\$8180! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR2476 @@ -311,8 +339,8 @@ FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW ; reset by wipe and by S1+<reset> JTAG_SIG2=\$FF82! if JTAG_SIG <> |\$FFFFFFFF, \$00000000|, SBW and JTAG are locked -BSL_SIG1=\$FF84! -BSL_SIG2=\$FF86! +BSL_SIG1=\$FF84! +BSL_SIG2=\$FF86! BSL_I2C_ADRE=\$FFA0! I2CSLA0=\$FFA2! UCBxI2COA0 default value address I2CSLA1=\$FFA4! UCBxI2COA1 default value address @@ -323,38 +351,6 @@ BSL_PASSWORD=\$FFE0! 256 bits VECT_ORG=\$FFDA! FFDA-FFFF VECT_LEN=\$38! ! ---------------------------------------------- - - -; .org INTVECT ; FFDA-FFFF 26 vectors + reset -; -; .word reset ; FFCAh - eCOMP0 -; .word reset ; FFCCh - P6 -; .word reset ; FFCEh - P5 -; .word reset ; FFD0h - P4 -; .word reset ; FFD2h - P3 -; .word reset ; FFD4h - P2 -; .word reset ; FFD6h - P1 -; .word reset ; FFD8h - ADC10 -; .word reset ; FFDAh - eUSCI_B1 -; .word reset ; FFDCh - eUSCI_B0 -; .word reset ; FFDEh - eUSCI_A1 -; .word reset ; FFE0h - eUSCI_A0 -; .word reset ; FFE2h - WDT -; .word reset ; FFE4h - RTC -; .word reset ; FFE6h - TB0_x -; .word reset ; FFE8h - TB0_0 -; .word reset ; FFEAh - TA3_x -; .word reset ; FFECh - TA3_0 -; .word reset ; FFEEh - TA2_x -; .word reset ; FFF0h - TA2_0 -; .word reset ; FFF2h - TA1_x -; .word reset ; FFF4h - TA1_0 -; .word reset ; FFF6h - TA0_x -; .word reset ; FFF8h - TA0_0 -; .word reset ; FFFAh - UserNMI -; .word reset ; FFFCh - SysNMI - - ECOMP0_VEC=\$FFCA! P6_VEC=\$FFCC! P5_VEC=\$FFCE! @@ -383,10 +379,6 @@ U_NMI_VEC=\$FFFA! S_NMI_VEC=\$FFFC! RST_VEC=\$FFFE! - - - - ! ---------------------------------------------------------------------- ! MSP430FR2433 Peripheral File Map ! ---------------------------------------------------------------------- @@ -404,6 +396,7 @@ RST_VEC=\$FFFE! !TA1_SFR .equ 03C0h !TA2_SFR .equ 0400h !TA3_SFR .equ 0440h +!TB0_SFR .equ 0480h !MPY_SFR .equ 04C0h !eUSCI_A0_SFR .equ 0500h ; eUSCI_A0 !eUSCI_A1_SFR .equ 0520h ; eUSCI_A1 @@ -418,41 +411,41 @@ SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 PMMCTL1=\$122! \ PMM Control 0 PMMCTL2=\$124! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -SYSCTL=\$140! \ System control -SYSBSLC=\$142! \ Bootstrap loader configuration area -SYSJMBC=\$146! \ JTAG mailbox control -SYSJMBI0=\$148! \ JTAG mailbox input 0 -SYSJMBI1=\$14A! \ JTAG mailbox input 1 -SYSJMBO0=\$14C! \ JTAG mailbox output 0 -SYSJMBO1=\$14E! \ JTAG mailbox output 1 -SYSUNIV=\$15A! \ User NMI vector generator -SYSSNIV=\$15C! \ System NMI vector generator -SYSRSTIV=\$15E! \ Reset vector generator -SYSCFG0=\$160! \ System configuration 0 -SYSCFG1=\$162! \ System configuration 1 -SYSCFG2=\$164! \ System configuration 2 - -CSCTL0=\$180! \ CS control 0 -CSCTL1=\$182! \ CS control 1 -CSCTL2=\$184! \ CS control 2 -CSCTL3=\$186! \ CS control 3 -CSCTL4=\$188! \ CS control 4 -CSCTL5=\$18A! \ CS control 5 -CSCTL6=\$18C! \ CS control 6 -CSCTL7=\$18E! \ CS control 7 -CSCTL8=\$190! \ CS control 8 - -FRCTLCTL0=\$1A0! \ FRAM control 0 -GCCTL0=\$1A4! \ General control 0 -GCCTL1=\$1A6! \ General control 1 - -CRC16DI=\$1C0! \ CRC data input -CRCDIRB=\$1C2! \ CRC data input reverse byte -CRCINIRES=\$1C4! \ CRC initialization and result -CRCRESR=\$1C6! \ CRC result reverse byte +SYSCTL=\$140! \ System control +SYSBSLC=\$142! \ Bootstrap loader configuration area +SYSJMBC=\$146! \ JTAG mailbox control +SYSJMBI0=\$148! \ JTAG mailbox input 0 +SYSJMBI1=\$14A! \ JTAG mailbox input 1 +SYSJMBO0=\$14C! \ JTAG mailbox output 0 +SYSJMBO1=\$14E! \ JTAG mailbox output 1 +SYSUNIV=\$15A! \ User NMI vector generator +SYSSNIV=\$15C! \ System NMI vector generator +SYSRSTIV=\$15E! \ Reset vector generator +SYSCFG0=\$160! \ System configuration 0 +SYSCFG1=\$162! \ System configuration 1 +SYSCFG2=\$164! \ System configuration 2 + +CSCTL0=\$180! \ CS control 0 +CSCTL1=\$182! \ CS control 1 +CSCTL2=\$184! \ CS control 2 +CSCTL3=\$186! \ CS control 3 +CSCTL4=\$188! \ CS control 4 +CSCTL5=\$18A! \ CS control 5 +CSCTL6=\$18C! \ CS control 6 +CSCTL7=\$18E! \ CS control 7 +CSCTL8=\$190! \ CS control 8 + +FRCTLCTL0=\$1A0! \ FRAM control 0 +GCCTL0=\$1A4! \ General control 0 +GCCTL1=\$1A6! \ General control 1 + +CRC16DI=\$1C0! \ CRC data input +CRCDIRB=\$1C2! \ CRC data input reverse byte +CRCINIRES=\$1C4! \ CRC initialization and result +CRCRESR=\$1C6! \ CRC result reverse byte WDTCTL=\$1CC! \ WDT control register @@ -547,77 +540,77 @@ P6IE=\$25B! P6IFG=\$25D! P6IV=\$25E! -RTCCTL=\$300! \ RTC control -RTCIV=\$304! \ RTC interrupt vector word -RTCMOD=\$308! \ RTC modulo -RTCCNT=\$30C! \ RTC counter register +RTCCTL=\$300! \ RTC control +RTCIV=\$304! \ RTC interrupt vector word +RTCMOD=\$308! \ RTC modulo +RTCCNT=\$30C! \ RTC counter register TACLR=4! TAIFG=1! CCIFG=1! -TA0CTL=\$380! \ TA0 control -TA0CCTL0=\$382! \ Capture/compare control 0 -TA0CCTL1=\$384! \ Capture/compare control 1 -TA0CCTL2=\$386! \ Capture/compare control 2 -TA0R=\$390! \ TA0 counter register -TA0CCR0=\$392! \ Capture/compare register 0 -TA0CCR1=\$394! \ Capture/compare register 1 -TA0CCR2=\$396! \ Capture/compare register 2 -TA0EX0=\$3A0! \ TA0 expansion register 0 -TA0IV=\$3AE! \ TA0 interrupt vector - -TA1CTL=\$3C0! \ TA1 control -TA1CCTL0=\$3C2! \ Capture/compare control 0 -TA1CCTL1=\$3C4! \ Capture/compare control 1 -TA1CCTL2=\$3C6! \ Capture/compare control 2 -TA1R=\$3D0! \ TA1 counter register -TA1CCR0=\$3D2! \ Capture/compare register 0 -TA1CCR1=\$3D4! \ Capture/compare register 1 -TA1CCR2=\$3D6! \ Capture/compare register 2 -TA1EX0=\$3E0! \ TA1 expansion register 0 -TA1IV=\$3EE! \ TA1 interrupt vector - -TA2CTL=\$400! \ TA2 control -TA2CCTL0=\$402! \ Capture/compare control 0 -TA2CCTL1=\$404! \ Capture/compare control 1 -TA2CCTL2=\$406! \ Capture/compare control 2 -TA2R=\$410! \ TA2 counter register -TA2CCR0=\$412! \ Capture/compare register 0 -TA2CCR1=\$414! \ Capture/compare register 1 -TA2CCR1=\$416! \ Capture/compare register 2 -TA2EX0=\$420! \ TA2 expansion register 0 -TA2IV=\$42E! \ TA2 interrupt vector - -TA3CTL=\$440! \ TA3 control -TA3CCTL0=\$442! \ Capture/compare control 0 -TA3CCTL1=\$444! \ Capture/compare control 1 -TA3CCTL1=\$446! \ Capture/compare control 2 -TA3R=\$450! \ TA3 counter register -TA3CCR0=\$452! \ Capture/compare register 0 -TA3CCR1=\$454! \ Capture/compare register 1 -TA3CCR1=\$456! \ Capture/compare register 2 -TA3EX0=\$460! \ TA3 expansion register 0 -TA3IV=\$46E! \ TA3 interrupt vector - -TB0CTL=\$480! \ TB0 control -TB0CCTL0=\$482! \ Capture/compare control 0 -TB0CCTL1=\$484! \ Capture/compare control 1 -TB0CCTL2=\$486! \ Capture/compare control 2 -TB0CCTL3=\$488! \ Capture/compare control 3 -TB0CCTL4=\$48A! \ Capture/compare control 4 -TB0CCTL5=\$48C! \ Capture/compare control 5 -TB0CCTL6=\$48E! \ Capture/compare control 6 -TB0R=\$490! \ TB0 counter register -TB0CCR0=\$492! \ Capture/compare register 0 -TB0CCR1=\$494! \ Capture/compare register 1 -TB0CCR2=\$496! \ Capture/compare register 2 -TB0CCR3=\$498! \ Capture/compare register 3 -TB0CCR5=\$49A! \ Capture/compare register 4 -TB0CCR5=\$49C! \ Capture/compare register 5 -TB0CCR6=\$49E! \ Capture/compare register 6 -TB0EX0=\$4A0! \ TB0 expansion register 0 -TB0IV=\$4AE! \ TB0 interrupt vector +TA0CTL=\$380! \ TA0 control +TA0CCTL0=\$382! \ Capture/compare control 0 +TA0CCTL1=\$384! \ Capture/compare control 1 +TA0CCTL2=\$386! \ Capture/compare control 2 +TA0R=\$390! \ TA0 counter register +TA0CCR0=\$392! \ Capture/compare register 0 +TA0CCR1=\$394! \ Capture/compare register 1 +TA0CCR2=\$396! \ Capture/compare register 2 +TA0EX0=\$3A0! \ TA0 expansion register 0 +TA0IV=\$3AE! \ TA0 interrupt vector + +TA1CTL=\$3C0! \ TA1 control +TA1CCTL0=\$3C2! \ Capture/compare control 0 +TA1CCTL1=\$3C4! \ Capture/compare control 1 +TA1CCTL2=\$3C6! \ Capture/compare control 2 +TA1R=\$3D0! \ TA1 counter register +TA1CCR0=\$3D2! \ Capture/compare register 0 +TA1CCR1=\$3D4! \ Capture/compare register 1 +TA1CCR2=\$3D6! \ Capture/compare register 2 +TA1EX0=\$3E0! \ TA1 expansion register 0 +TA1IV=\$3EE! \ TA1 interrupt vector + +TA2CTL=\$400! \ TA2 control +TA2CCTL0=\$402! \ Capture/compare control 0 +TA2CCTL1=\$404! \ Capture/compare control 1 +TA2CCTL2=\$406! \ Capture/compare control 2 +TA2R=\$410! \ TA2 counter register +TA2CCR0=\$412! \ Capture/compare register 0 +TA2CCR1=\$414! \ Capture/compare register 1 +TA2CCR1=\$416! \ Capture/compare register 2 +TA2EX0=\$420! \ TA2 expansion register 0 +TA2IV=\$42E! \ TA2 interrupt vector + +TA3CTL=\$440! \ TA3 control +TA3CCTL0=\$442! \ Capture/compare control 0 +TA3CCTL1=\$444! \ Capture/compare control 1 +TA3CCTL1=\$446! \ Capture/compare control 2 +TA3R=\$450! \ TA3 counter register +TA3CCR0=\$452! \ Capture/compare register 0 +TA3CCR1=\$454! \ Capture/compare register 1 +TA3CCR1=\$456! \ Capture/compare register 2 +TA3EX0=\$460! \ TA3 expansion register 0 +TA3IV=\$46E! \ TA3 interrupt vector + +TB0CTL=\$480! \ TB0 control +TB0CCTL0=\$482! \ Capture/compare control 0 +TB0CCTL1=\$484! \ Capture/compare control 1 +TB0CCTL2=\$486! \ Capture/compare control 2 +TB0CCTL3=\$488! \ Capture/compare control 3 +TB0CCTL4=\$48A! \ Capture/compare control 4 +TB0CCTL5=\$48C! \ Capture/compare control 5 +TB0CCTL6=\$48E! \ Capture/compare control 6 +TB0R=\$490! \ TB0 counter register +TB0CCR0=\$492! \ Capture/compare register 0 +TB0CCR1=\$494! \ Capture/compare register 1 +TB0CCR2=\$496! \ Capture/compare register 2 +TB0CCR3=\$498! \ Capture/compare register 3 +TB0CCR5=\$49A! \ Capture/compare register 4 +TB0CCR5=\$49C! \ Capture/compare register 5 +TB0CCR6=\$49E! \ Capture/compare register 6 +TB0EX0=\$4A0! \ TB0 expansion register 0 +TB0IV=\$4AE! \ TB0 interrupt vector MPY=\$4C0! \ 16-bit operand 1 - multiply MPYS=\$4C2! \ 16-bit operand 1 - signed multiply @@ -644,110 +637,110 @@ RES3=\$4EA! \ 32 x 32 result 3 - most significant word MPY32CTL0=\$4EC! \ MPY32 control register 0 -UCA0CTLW0=\$500! \ eUSCI_A control word 0 -UCA0CTLW1=\$502! \ eUSCI_A control word 1 -UCA0BRW=\$506! -UCA0BR0=\$506! \ eUSCI_A baud rate 0 -UCA0BR1=\$507! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$508! \ eUSCI_A modulation control -UCA0STAT=\$50A! \ eUSCI_A status -UCA0RXBUF=\$50C! \ eUSCI_A receive buffer -UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer -UCA0ABCTL=\$510! \ eUSCI_A LIN control -UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control -UCA0IE=\$51A! \ eUSCI_A interrupt enable -UCA0IFG=\$51C! \ eUSCI_A interrupt flags -UCA0IV=\$51E! \ eUSCI_A interrupt vector word - -UCA1CTLW0=\$520! \ eUSCI_A control word 0 -UCA1CTLW1=\$522! \ eUSCI_A control word 1 -UCA1BRW=\$526! -UCA1BR0=\$526! \ eUSCI_A baud rate 0 -UCA1BR1=\$527! \ eUSCI_A baud rate 1 -UCA1MCTLW=\$528! \ eUSCI_A modulation control -UCA1STAT=\$52A! \ eUSCI_A status -UCA1RXBUF=\$52C! \ eUSCI_A receive buffer -UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer -UCA1ABCTL=\$530! \ eUSCI_A LIN control -UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control -UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control -UCA1IE=\$53A! \ eUSCI_A interrupt enable -UCA1IFG=\$53C! \ eUSCI_A interrupt flags -UCA1IV=\$53E! \ eUSCI_A interrupt vector word - -UCB0CTLW0=\$540! \ eUSCI_B control word 0 -UCB0CTLW1=\$542! \ eUSCI_B control word 1 -UCB0BRW=\$546! -UCB0BR0=\$546! \ eUSCI_B bit rate 0 -UCB0BR1=\$547! \ eUSCI_B bit rate 1 -UCB0STATW=\$548! \ eUSCI_B status word -UCBCNT0=\$549! \ eUSCI_B hardware count -UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$54C! \ eUSCI_B receive buffer -UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$55C! \ eUSCI_B received address -UCB0ADDMASK=\$55E! \ eUSCI_B address mask -UCB0I2CSA=\$560! \ eUSCI I2C slave address -UCB0IE=\$56A! \ eUSCI interrupt enable -UCB0IFG=\$56C! \ eUSCI interrupt flags -UCB0IV=\$56E! \ eUSCI interrupt vector word - -UCB1CTLW0=\$580! \ eUSCI_B control word 0 -UCB1CTLW1=\$582! \ eUSCI_B control word 1 -UCB1BRW=\$586! -UCB1BR0=\$586! \ eUSCI_B bit rate 0 -UCB1BR1=\$587! \ eUSCI_B bit rate 1 -UCB1STATW=\$588! \ eUSCI_B status word -UCB1NT0=\$589! \ eUSCI_B hardware count -UCB1TBCNT=\$58A! \ eUSCI_B byte counter threshold -UCB1RXBUF=\$58C! \ eUSCI_B receive buffer -UCB1TXBUF=\$58E! \ eUSCI_B transmit buffer -UCB1I2COA0=\$594! \ eUSCI_B I2C own address 0 -UCB1I2COA1=\$596! \ eUSCI_B I2C own address 1 -UCB1I2COA2=\$598! \ eUSCI_B I2C own address 2 -UCB1I2COA3=\$59A! \ eUSCI_B I2C own address 3 -UCB1ADDRX=\$59C! \ eUSCI_B received address -UCB1ADDMASK=\$59E! \ eUSCI_B address mask -UCB1I2CSA=\$5A0! \ eUSCI I2C slave address -UCB1IE=\$5AA! \ eUSCI interrupt enable -UCB1IFG=\$5AC! \ eUSCI interrupt flags -UCB1IV=\$5AE! \ eUSCI interrupt vector word +UCA0CTLW0=\$500! \ eUSCI_A control word 0 +UCA0CTLW1=\$502! \ eUSCI_A control word 1 +UCA0BRW=\$506! +UCA0BR0=\$506! \ eUSCI_A baud rate 0 +UCA0BR1=\$507! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$508! \ eUSCI_A modulation control +UCA0STAT=\$50A! \ eUSCI_A status +UCA0RXBUF=\$50C! \ eUSCI_A receive buffer +UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer +UCA0ABCTL=\$510! \ eUSCI_A LIN control +UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control +UCA0IE=\$51A! \ eUSCI_A interrupt enable +UCA0IFG=\$51C! \ eUSCI_A interrupt flags +UCA0IV=\$51E! \ eUSCI_A interrupt vector word + +UCA1CTLW0=\$520! \ eUSCI_A control word 0 +UCA1CTLW1=\$522! \ eUSCI_A control word 1 +UCA1BRW=\$526! +UCA1BR0=\$526! \ eUSCI_A baud rate 0 +UCA1BR1=\$527! \ eUSCI_A baud rate 1 +UCA1MCTLW=\$528! \ eUSCI_A modulation control +UCA1STAT=\$52A! \ eUSCI_A status +UCA1RXBUF=\$52C! \ eUSCI_A receive buffer +UCA1TXBUF=\$52E! \ eUSCI_A transmit buffer +UCA1ABCTL=\$530! \ eUSCI_A LIN control +UCA1IRTCTL=\$532! \ eUSCI_A IrDA transmit control +UCA1IRRCTL=\$533! \ eUSCI_A IrDA receive control +UCA1IE=\$53A! \ eUSCI_A interrupt enable +UCA1IFG=\$53C! \ eUSCI_A interrupt flags +UCA1IV=\$53E! \ eUSCI_A interrupt vector word + +UCB0CTLW0=\$540! \ eUSCI_B control word 0 +UCB0CTLW1=\$542! \ eUSCI_B control word 1 +UCB0BRW=\$546! +UCB0BR0=\$546! \ eUSCI_B bit rate 0 +UCB0BR1=\$547! \ eUSCI_B bit rate 1 +UCB0STATW=\$548! \ eUSCI_B status word +UCBCNT0=\$549! \ eUSCI_B hardware count +UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$54C! \ eUSCI_B receive buffer +UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$55C! \ eUSCI_B received address +UCB0ADDMASK=\$55E! \ eUSCI_B address mask +UCB0I2CSA=\$560! \ eUSCI I2C slave address +UCB0IE=\$56A! \ eUSCI interrupt enable +UCB0IFG=\$56C! \ eUSCI interrupt flags +UCB0IV=\$56E! \ eUSCI interrupt vector word + +UCB1CTLW0=\$580! \ eUSCI_B control word 0 +UCB1CTLW1=\$582! \ eUSCI_B control word 1 +UCB1BRW=\$586! +UCB1BR0=\$586! \ eUSCI_B bit rate 0 +UCB1BR1=\$587! \ eUSCI_B bit rate 1 +UCB1STATW=\$588! \ eUSCI_B status word +UCB1NT0=\$589! \ eUSCI_B hardware count +UCB1TBCNT=\$58A! \ eUSCI_B byte counter threshold +UCB1RXBUF=\$58C! \ eUSCI_B receive buffer +UCB1TXBUF=\$58E! \ eUSCI_B transmit buffer +UCB1I2COA0=\$594! \ eUSCI_B I2C own address 0 +UCB1I2COA1=\$596! \ eUSCI_B I2C own address 1 +UCB1I2COA2=\$598! \ eUSCI_B I2C own address 2 +UCB1I2COA3=\$59A! \ eUSCI_B I2C own address 3 +UCB1ADDRX=\$59C! \ eUSCI_B received address +UCB1ADDMASK=\$59E! \ eUSCI_B address mask +UCB1I2CSA=\$5A0! \ eUSCI I2C slave address +UCB1IE=\$5AA! \ eUSCI interrupt enable +UCB1IFG=\$5AC! \ eUSCI interrupt flags +UCB1IV=\$5AE! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -BAKMEM0=\$660! \ Backup Memory 0 -BAKMEM1=\$662! \ Backup Memory 1 -BAKMEM2=\$664! \ Backup Memory 2 -BAKMEM3=\$666! \ Backup Memory 3 -BAKMEM4=\$668! \ Backup Memory 4 -BAKMEM5=\$66A! \ Backup Memory 5 -BAKMEM6=\$66C! \ Backup Memory 6 -BAKMEM7=\$66E! \ Backup Memory 7 -BAKMEM8=\$670! \ Backup Memory 8 -BAKMEM9=\$672! \ Backup Memory 9 -BAKMEM10=\$674! \ Backup Memory 10 -BAKMEM11=\$676! \ Backup Memory 11 -BAKMEM12=\$678! \ Backup Memory 12 -BAKMEM13=\$67A! \ Backup Memory 13 -BAKMEM14=\$67C! \ Backup Memory 14 -BAKMEM15=\$67E! \ Backup Memory 15 - -ADC10CTL0=\$700! \ ADC10_B Control register 0 -ADC10CTL1=\$702! \ ADC10_B Control register 1 -ADC10CTL2=\$704! \ ADC10_B Control register 2 -ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold -ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold -ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 -ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register -ADC10IE=\$71A! \ ADC10_B Interrupt Enable -ADC10IFG=\$71C! \ ADC10_B Interrupt Flags -ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word +BAKMEM0=\$660! \ Backup Memory 0 +BAKMEM1=\$662! \ Backup Memory 1 +BAKMEM2=\$664! \ Backup Memory 2 +BAKMEM3=\$666! \ Backup Memory 3 +BAKMEM4=\$668! \ Backup Memory 4 +BAKMEM5=\$66A! \ Backup Memory 5 +BAKMEM6=\$66C! \ Backup Memory 6 +BAKMEM7=\$66E! \ Backup Memory 7 +BAKMEM8=\$670! \ Backup Memory 8 +BAKMEM9=\$672! \ Backup Memory 9 +BAKMEM10=\$674! \ Backup Memory 10 +BAKMEM11=\$676! \ Backup Memory 11 +BAKMEM12=\$678! \ Backup Memory 12 +BAKMEM13=\$67A! \ Backup Memory 13 +BAKMEM14=\$67C! \ Backup Memory 14 +BAKMEM15=\$67E! \ Backup Memory 15 + +ADC10CTL0=\$700! \ ADC10_B Control register 0 +ADC10CTL1=\$702! \ ADC10_B Control register 1 +ADC10CTL2=\$704! \ ADC10_B Control register 2 +ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold +ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold +ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 +ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register +ADC10IE=\$71A! \ ADC10_B Interrupt Enable +ADC10IFG=\$71C! \ ADC10_B Interrupt Flags +ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word ADCON=\$10! ADCSTART=\$03! diff --git a/inc/MSP430FR2633.pat b/inc/MSP430FR2633.pat index 09461ee..64b31d4 100644 --- a/inc/MSP430FR2633.pat +++ b/inc/MSP430FR2633.pat @@ -38,40 +38,65 @@ TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -92,51 +117,47 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! --------------------------------------- ! FastForth RAM memory map (>= 1k): ! --------------------------------------- -LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT -LSATCK=\$2000! \ leave stack, grow up -PSTACK=\$2080! \ parameter stack, grow down -RSTACK=\$20E0! \ Return stack, grow down - -PAD_I2CADR=\$20E0! \ RX I2C address -PAD_I2CCNT=\$20E2! \ count max -PAD_ORG=\$20E4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$2138! \ TX I2C address -TIB_I2CCNT=\$213A! \ count of bytes -TIB_ORG=\$213C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$2190! \ a good address for HOLDS -HOLD_BASE=\$21B2! \ BASE HOLD area, grow down - -! --------------------------------------- -! NOT SAVED VARIABLES -! --------------------------------------- +LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT +LSATCK=\$2000! leave stack, grow up +PSTACK=\$2080! parameter stack, grow down +RSTACK=\$20E0! Return stack, grow down +! +PAD_I2CADR=\$20E0! RX I2C address +PAD_I2CCNT=\$20E2! count max +PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$2138! TX I2C address +TIB_I2CCNT=\$213A! count of bytes +TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$2190! base address for HOLDS +HOLD_BASE=\$21B2! BASE HOLD area, grow down +! HP=\$21B2! HOLD ptr -CAPS=\$21B4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$21B6! -LAST_THREAD=\$21B8! -LAST_CFA=\$21BA! -LAST_PSP=\$21BC! - -STATEADR=\$21BE! Interpreter state - -SOURCE_LEN=\$21C0! len of input stream -SOURCE_ORG=\$21C2! adr of input stream -TOIN=\$21C4! >IN -DP=\$21C6! dictionary ptr - -LASTVOC=\$21C8! keep VOC-LINK -CONTEXT=\$21CA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$21DA! CURRENT dictionnary ptr - -BASEADR=\$21DC! numeric base, must be defined before first reset ! -LINE=\$21DE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$21B4! +LAST_THREAD=\$21B6! +LAST_CFA=\$21B8! +LAST_PSP=\$21BA! +! +STATEADR=\$21BC! Interpreter state +BASEADR=\$21BE! +CAPS=\$21C0 ! +! +SOURCE_LEN=\$21C2! len of input stream +SOURCE_ORG=\$21C4! adr of input stream +TOIN=\$21C6! >IN +DP=\$21C8! dictionary ptr +! +LASTVOC=\$21CA! keep VOC-LINK +CURRENT=\$21CC! CURRENT dictionnary ptr +CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- !21E0! 28 RAM bytes free ! --------------------------------------- @@ -256,46 +277,54 @@ MAIN_ORG=\$C400! Code space start SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$C40A! CODE compiled by LITERAL -XSQUOTE=\$C414! CODE compiled by S" and S_ -HEREXEC=\$C428! CODE HERE and BEGIN execute address -QFBRAN=\$C434! CODE compiled by IF UNTIL -BRAN=\$C43A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$C43C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$C43E! CODE compiled by DO -XPLOOP=\$C44E! CODE compiled by +LOOP -XLOOP=\$C460! CODE compiled by LOOP -MUSMOD=\$C466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$C478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$C480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$C4AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$C4AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$C4BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$C4CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$C4D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$C4E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$C4EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$C41E! CODE compiled by S" and S_ +HEREXEC=\$C432! CODE HERE and BEGIN execute address +MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$C494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$C4AC! CODE compiled by IF UNTIL +BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$C4F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$C52A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$C536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$C594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$C59C! ASM CODE, content of WARM+2 by default -UART_RXON=\$C5C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$C5C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$C5B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$C58E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$C5BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$C5BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$C584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$C586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$C544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$C556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$C556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$C558! asm CODE, content of WARM+2 by default +I2C_WARM=\$C580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR2633 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD diff --git a/inc/MSP430FR4133.inc b/inc/MSP430FR4133.inc index 8823ca4..e968bd7 100644 --- a/inc/MSP430FR4133.inc +++ b/inc/MSP430FR4133.inc @@ -41,7 +41,7 @@ JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW ; re JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG <> |0xFFFFFFFF, 0x00000000|, SBW and JTAG are locked BSL_SIG1 .equ 0FF84h ; BSL_SIG2 .equ 0FF86h ; -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -63,21 +63,21 @@ BSL_PASSWORD .equ 0FFE0h ; 256 bits ; ; .org INTVECT ; FFE2-FFFF 14 vectors + reset ; -; .word reset ; 0FFE2h - LCD -; .word reset ; 0FFE4h - P2 -; .word reset ; 0FFE6h - P1 -; .word reset ; 0FFE8h - ADC10 -; .word reset ; 0FFEAh - eUSCI_B0 -; .word reset ; 0FFECh - eUSCI_A0 -; .word reset ; 0FFEEh - WDT -; .word reset ; 0FFF0h - RTC -; .word reset ; 0FFF2h - TA1_x -; .word reset ; 0FFF4h - TA1_0 -; .word reset ; 0FFF6h - TA0_x -; .word reset ; 0FFF8h - TA0_0 -; .word reset ; 0FFFAh - UserNMI -; .word reset ; 0FFFCh - SysNMI -; .word reset ; 0FFFEh - Reset +; .word reset ; 0FFE2h - LCD +; .word reset ; 0FFE4h - P2 +; .word reset ; 0FFE6h - P1 +; .word reset ; 0FFE8h - ADC10 +; .word reset ; 0FFEAh - eUSCI_B0 +; .word reset ; 0FFECh - eUSCI_A0 +; .word reset ; 0FFEEh - WDT +; .word reset ; 0FFF0h - RTC +; .word reset ; 0FFF2h - TA1_x +; .word reset ; 0FFF4h - TA1_0 +; .word reset ; 0FFF6h - TA0_x +; .word reset ; 0FFF8h - TA0_0 +; .word reset ; 0FFFAh - UserNMI +; .word reset ; 0FFFCh - SysNMI +; .word reset ; 0FFFEh - Reset ; ---------------------------------------------------------------------- @@ -121,21 +121,21 @@ LOCKLPM5 .equ 1 ; bit position ; ---------------------------------------------------------------------- ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -SYSCTL .equ SYS_SFR + 00h ; System control -SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area -SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control -SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 -SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 -SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 -SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 -SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator -SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator -SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator -SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator -SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 -SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 -SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 - +SYSCTL .equ SYS_SFR + 00h ; System control +SYSBSLC .equ SYS_SFR + 02h ; Bootstrap loader configuration area +SYSJMBC .equ SYS_SFR + 06h ; JTAG mailbox control +SYSJMBI0 .equ SYS_SFR + 08h ; JTAG mailbox input 0 +SYSJMBI1 .equ SYS_SFR + 0Ah ; JTAG mailbox input 1 +SYSJMBO0 .equ SYS_SFR + 0Ch ; JTAG mailbox output 0 +SYSJMBO1 .equ SYS_SFR + 0Eh ; JTAG mailbox output 1 +SYSBERRIV .equ SYS_SFR + 18h ; Bus Error vector generator +SYSUNIV .equ SYS_SFR + 1Ah ; User NMI vector generator +SYSSNIV .equ SYS_SFR + 1Ch ; System NMI vector generator +SYSRSTIV .equ SYS_SFR + 1Eh ; Reset vector generator +SYSCFG0 .equ SYS_SFR + 20h ; System configuration 0 +SYSCFG1 .equ SYS_SFR + 22h ; System configuration 1 +SYSCFG2 .equ SYS_SFR + 24h ; System configuration 2 + ; SYS Control Bits ; ... ; ---------------------------------------------------------------------- @@ -170,7 +170,7 @@ P1DIR .equ PA_SFR + 04h ; Port 1 Direction P1REN .equ PA_SFR + 06h ; Port 1 Resistor Enable P1SEL0 .equ PA_SFR + 0Ah ; Port 1 Selection 0 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 Selection 1 -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt Flag @@ -184,7 +184,7 @@ P2SEL1 .equ PA_SFR + 0Dh ; Port 2 Selection 1 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3/4 @@ -291,10 +291,10 @@ CSCTL8 .equ CS_SFR + 10h ; Clock System Control Register 8 ; ---------------------------------------------------------------------- RTC ; ---------------------------------------------------------------------- -RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control -RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector -RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo -RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter +RTCCTL .equ RTC_SFR + 00h ; Real-Time Clock Control +RTCIV .equ RTC_SFR + 04h ; Real-Time Clock Interrupt Vector +RTCMOD .equ RTC_SFR + 08h ; Real-Timer Clock Modulo +RTCCNT .equ RTC_SFR + 0Ch ; Real-Time Clock Counter .IFDEF UCA0_TERM @@ -342,7 +342,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR4133.pat b/inc/MSP430FR4133.pat index afd11f3..0133a80 100644 --- a/inc/MSP430FR4133.pat +++ b/inc/MSP430FR4133.pat @@ -32,42 +32,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -88,53 +113,49 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! --------------------------------------- ! FastForth RAM memory map (>= 1k): ! --------------------------------------- -LEAVEPTR=\$2000! \ Leave-stack pointer, init by QUIT -LSATCK=\$2000! \ leave stack, grow up -PSTACK=\$2080! \ parameter stack, grow down -RSTACK=\$20E0! \ Return stack, grow down - -PAD_I2CADR=\$20E0! \ RX I2C address -PAD_I2CCNT=\$20E2! \ count max -PAD_ORG=\$20E4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$2138! \ TX I2C address -TIB_I2CCNT=\$213A! \ count of bytes -TIB_ORG=\$213C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$2190! \ a good address for HOLDS -HOLD_BASE=\$21B2! \ BASE HOLD area, grow down - -! --------------------------------------- -! NOT SAVED VARIABLES -! --------------------------------------- +LEAVEPTR=\$2000! Leave-stack pointer, init by QUIT +LSATCK=\$2000! leave stack, grow up +PSTACK=\$2080! parameter stack, grow down +RSTACK=\$20E0! Return stack, grow down +! +PAD_I2CADR=\$20E0! RX I2C address +PAD_I2CCNT=\$20E2! count max +PAD_ORG=\$20E4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$2138! TX I2C address +TIB_I2CCNT=\$213A! count of bytes +TIB_ORG=\$213C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$2190! base address for HOLDS +HOLD_BASE=\$21B2! BASE HOLD area, grow down +! HP=\$21B2! HOLD ptr -CAPS=\$21B4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$21B6! -LAST_THREAD=\$21B8! -LAST_CFA=\$21BA! -LAST_PSP=\$21BC! - -STATEADR=\$21BE! Interpreter state - -SOURCE_LEN=\$21C0! len of input stream -SOURCE_ORG=\$21C2! adr of input stream -TOIN=\$21C4! >IN -DP=\$21C6! dictionary ptr - -LASTVOC=\$21C8! keep VOC-LINK -CONTEXT=\$21CA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$21DA! CURRENT dictionnary ptr - -BASEADR=\$21DC! numeric base, must be defined before first reset ! -LINE=\$21DE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$21B4! +LAST_THREAD=\$21B6! +LAST_CFA=\$21B8! +LAST_PSP=\$21BA! +! +STATEADR=\$21BC! Interpreter state +BASEADR=\$21BE! +CAPS=\$21C0 ! +! +SOURCE_LEN=\$21C2! len of input stream +SOURCE_ORG=\$21C4! adr of input stream +TOIN=\$21C6! >IN +DP=\$21C8! dictionary ptr +! +LASTVOC=\$21CA! keep VOC-LINK +CURRENT=\$21CC! CURRENT dictionnary ptr +CONTEXT=\$21CE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!21E0! 28 RAM bytes free +!21E0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -146,7 +167,7 @@ SD_BUF=\$2200! \ SD_Card buffer BUFEND=\$2400! ! --------------------------------------- -! FAT16 FileSystemInfos +! FAT16 FileSystemInfos ! --------------------------------------- FATtype=\$2402! BS_FirstSectorL=\$2404! @@ -174,7 +195,7 @@ SectorH=\$241C! ! --------------------------------------- ! BUFFER management ! --------------------------------------- -BufferPtr=\$241E! +BufferPtr=\$241E! BufferLen=\$2420! ! --------------------------------------- @@ -182,8 +203,8 @@ BufferLen=\$2420! ! --------------------------------------- ClusterL=\$2422! 16 bits wide (FAT16) ClusterH=\$2424! 16 bits wide (FAT16) -NewClusterL=\$2426! 16 bits wide (FAT16) -NewClusterH=\$2428! 16 bits wide (FAT16) +NewClusterL=\$2426! 16 bits wide (FAT16) +NewClusterH=\$2428! 16 bits wide (FAT16) CurFATsector=\$242A! ! --------------------------------------- @@ -191,7 +212,7 @@ CurFATsector=\$242A! ! --------------------------------------- DIRclusterL=\$242C! contains the Cluster of current directory ; 1 if FAT16 root directory DIRclusterH=\$242E! contains the Cluster of current directory ; 1 if FAT16 root directory -EntryOfst=\$2430! +EntryOfst=\$2430! ! --------------------------------------- ! Handle Pointer @@ -207,7 +228,7 @@ EndOfPath=\$2436! ! --------------------------------------- ! Handle structure ! --------------------------------------- -! three handle tokens : +! three handle tokens : ! token = 0 : free handle ! token = 1 : file to read ! token = 2 : file updated (write) @@ -231,7 +252,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2438! @@ -252,51 +273,59 @@ MAIN_ORG=\$C400! Code space start SLEEP=\$C400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$C40A! CODE compiled by LITERAL -XSQUOTE=\$C414! CODE compiled by S" and S_ -HEREXEC=\$C428! CODE HERE and BEGIN execute address -QFBRAN=\$C434! CODE compiled by IF UNTIL -BRAN=\$C43A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$C43C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$C43E! CODE compiled by DO -XPLOOP=\$C44E! CODE compiled by +LOOP -XLOOP=\$C460! CODE compiled by LOOP -MUSMOD=\$C466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$C478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$C480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$C4AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$C4AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$C4BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$C4CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$C4D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$C4E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$C4EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$C41E! CODE compiled by S" and S_ +HEREXEC=\$C432! CODE HERE and BEGIN execute address +MUSMOD=\$C43E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$C450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$C458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$C482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$C484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$C494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$C4A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$C4AC! CODE compiled by IF UNTIL +BRAN=\$C4B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$C4B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$C4B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$C4C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$C4F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$C52A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$C536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$C4D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$C508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$C512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$C594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$C59C! ASM CODE, content of WARM+2 by default -UART_RXON=\$C5C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$C5C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$C5B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$C58E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$C5BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$C5BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$C554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$C57E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$C584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$C586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$C544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$C546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$C556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$C556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$C558! asm CODE, content of WARM+2 by default +I2C_WARM=\$C580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR4133 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD -BSL_SIG1=\$FF84! -BSL_SIG2=\$FF86! +BSL_SIG1=\$FF84! +BSL_SIG2=\$FF86! I2CSLA0=\$FFA2! UCBxI2COA0 default value address I2CSLA1=\$FFA4! UCBxI2COA1 default value address I2CSLA2=\$FFA6! UCBxI2COA2 default value address @@ -333,42 +362,42 @@ SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 PMMCTL1=\$122! \ PMM Control 0 PMMCTL2=\$124! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -SYSCTL=\$140! \ System control -SYSBSLC=\$142! \ Bootstrap loader configuration area -SYSJMBC=\$146! \ JTAG mailbox control -SYSJMBI0=\$148! \ JTAG mailbox input 0 -SYSJMBI1=\$14A! \ JTAG mailbox input 1 -SYSJMBO0=\$14C! \ JTAG mailbox output 0 -SYSJMBO1=\$14E! \ JTAG mailbox output 1 -SYSUNIV=\$15A! \ User NMI vector generator -SYSSNIV=\$15C! \ System NMI vector generator -SYSRSTIV=\$15E! \ Reset vector generator -SYSCFG0=\$160! \ System configuration 0 -SYSCFG1=\$162! \ System configuration 1 -SYSCFG2=\$164! \ System configuration 2 - -CSCTL0=\$180! \ CS control 0 -CSCTL1=\$182! \ CS control 1 -CSCTL2=\$184! \ CS control 2 -CSCTL3=\$186! \ CS control 3 -CSCTL4=\$188! \ CS control 4 -CSCTL5=\$18A! \ CS control 5 -CSCTL6=\$18C! \ CS control 6 -CSCTL7=\$18E! \ CS control 7 -CSCTL8=\$190! \ CS control 8 - - -FRCTLCTL0=\$1A0! \ FRAM control 0 -GCCTL0=\$1A4! \ General control 0 -GCCTL1=\$1A6! \ General control 1 - -CRC16DI=\$1C0! \ CRC data input -CRCDIRB=\$1C2! \ CRC data input reverse byte -CRCINIRES=\$1C4! \ CRC initialization and result -CRCRESR=\$1C6! \ CRC result reverse byte +SYSCTL=\$140! \ System control +SYSBSLC=\$142! \ Bootstrap loader configuration area +SYSJMBC=\$146! \ JTAG mailbox control +SYSJMBI0=\$148! \ JTAG mailbox input 0 +SYSJMBI1=\$14A! \ JTAG mailbox input 1 +SYSJMBO0=\$14C! \ JTAG mailbox output 0 +SYSJMBO1=\$14E! \ JTAG mailbox output 1 +SYSUNIV=\$15A! \ User NMI vector generator +SYSSNIV=\$15C! \ System NMI vector generator +SYSRSTIV=\$15E! \ Reset vector generator +SYSCFG0=\$160! \ System configuration 0 +SYSCFG1=\$162! \ System configuration 1 +SYSCFG2=\$164! \ System configuration 2 + +CSCTL0=\$180! \ CS control 0 +CSCTL1=\$182! \ CS control 1 +CSCTL2=\$184! \ CS control 2 +CSCTL3=\$186! \ CS control 3 +CSCTL4=\$188! \ CS control 4 +CSCTL5=\$18A! \ CS control 5 +CSCTL6=\$18C! \ CS control 6 +CSCTL7=\$18E! \ CS control 7 +CSCTL8=\$190! \ CS control 8 + + +FRCTLCTL0=\$1A0! \ FRAM control 0 +GCCTL0=\$1A4! \ General control 0 +GCCTL1=\$1A6! \ General control 1 + +CRC16DI=\$1C0! \ CRC data input +CRCDIRB=\$1C2! \ CRC data input reverse byte +CRCINIRES=\$1C4! \ CRC initialization and result +CRCRESR=\$1C6! \ CRC result reverse byte WDTCTL=\$1CC! \ WDT control register @@ -454,7 +483,7 @@ P8DIR=\$265! P8REN=\$267! P8SEL0=\$26B! -CAPTIO0CTL=\$2EE! \ Capacitive Touch IO 0 control +CAPTIO0CTL=\$2EE! \ Capacitive Touch IO 0 control @@ -462,178 +491,178 @@ TACLR=4! TAIFG=1! CCIFG=1! -TA0CTL=\$300! \ TA0 control -TA0CCTL0=\$302! \ Capture/compare control 0 -TA0CCTL1=\$304! \ Capture/compare control 1 -TA0CCTL2=\$306! \ Capture/compare control 2 -TA0R=\$310! \ TA0 counter register -TA0CCR0=\$312! \ Capture/compare register 0 -TA0CCR1=\$314! \ Capture/compare register 1 -TA0CCR2=\$316! \ Capture/compare register 2 -TA0EX0=\$320! \ TA0 expansion register 0 -TA0IV=\$32E! \ TA0 interrupt vector - -TA1CTL=\$340! \ TA1 control -TA1CCTL0=\$342! \ Capture/compare control 0 -TA1CCTL1=\$344! \ Capture/compare control 1 -TA1CCTL2=\$346! \ Capture/compare control 2 -TA1R=\$350! \ TA1 counter register -TA1CCR0=\$352! \ Capture/compare register 0 -TA1CCR1=\$354! \ Capture/compare register 1 -TA1CCR2=\$356! \ Capture/compare register 2 -TA1EX0=\$360! \ TA1 expansion register 0 -TA1IV=\$36E! \ TA1 interrupt vector - -RTCCTL=\$3C0! \ RTC control -RTCIV=\$3C4! \ RTC interrupt vector word -RTCMOD=\$3C8! \ RTC modulo -RTCCNT=\$3CC! \ RTC counter register - - -UCA0CTLW0=\$500! \ eUSCI_A control word 0 -UCA0CTLW1=\$502! \ eUSCI_A control word 1 -UCA0BRW=\$506! -UCA0BR0=\$506! \ eUSCI_A baud rate 0 -UCA0BR1=\$507! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$508! \ eUSCI_A modulation control -UCA0STAT=\$50A! \ eUSCI_A status -UCA0RXBUF=\$50C! \ eUSCI_A receive buffer -UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer -UCA0ABCTL=\$510! \ eUSCI_A LIN control -UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control -UCA0IE=\$51A! \ eUSCI_A interrupt enable -UCA0IFG=\$51C! \ eUSCI_A interrupt flags -UCA0IV=\$51E! \ eUSCI_A interrupt vector word - - -UCB0CTLW0=\$540! \ eUSCI_B control word 0 -UCB0CTLW1=\$542! \ eUSCI_B control word 1 -UCB0BRW=\$546! -UCB0BR0=\$546! \ eUSCI_B bit rate 0 -UCB0BR1=\$547! \ eUSCI_B bit rate 1 -UCB0STATW=\$548! \ eUSCI_B status word -UCBCNT0=\$549! \ eUSCI_B hardware count -UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$54C! \ eUSCI_B receive buffer -UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$55C! \ eUSCI_B received address -UCB0ADDMASK=\$55E! \ eUSCI_B address mask -UCB0I2CSA=\$560! \ eUSCI I2C slave address -UCB0IE=\$56A! \ eUSCI interrupt enable -UCB0IFG=\$56C! \ eUSCI interrupt flags -UCB0IV=\$56E! \ eUSCI interrupt vector word +TA0CTL=\$300! \ TA0 control +TA0CCTL0=\$302! \ Capture/compare control 0 +TA0CCTL1=\$304! \ Capture/compare control 1 +TA0CCTL2=\$306! \ Capture/compare control 2 +TA0R=\$310! \ TA0 counter register +TA0CCR0=\$312! \ Capture/compare register 0 +TA0CCR1=\$314! \ Capture/compare register 1 +TA0CCR2=\$316! \ Capture/compare register 2 +TA0EX0=\$320! \ TA0 expansion register 0 +TA0IV=\$32E! \ TA0 interrupt vector + +TA1CTL=\$340! \ TA1 control +TA1CCTL0=\$342! \ Capture/compare control 0 +TA1CCTL1=\$344! \ Capture/compare control 1 +TA1CCTL2=\$346! \ Capture/compare control 2 +TA1R=\$350! \ TA1 counter register +TA1CCR0=\$352! \ Capture/compare register 0 +TA1CCR1=\$354! \ Capture/compare register 1 +TA1CCR2=\$356! \ Capture/compare register 2 +TA1EX0=\$360! \ TA1 expansion register 0 +TA1IV=\$36E! \ TA1 interrupt vector + +RTCCTL=\$3C0! \ RTC control +RTCIV=\$3C4! \ RTC interrupt vector word +RTCMOD=\$3C8! \ RTC modulo +RTCCNT=\$3CC! \ RTC counter register + + +UCA0CTLW0=\$500! \ eUSCI_A control word 0 +UCA0CTLW1=\$502! \ eUSCI_A control word 1 +UCA0BRW=\$506! +UCA0BR0=\$506! \ eUSCI_A baud rate 0 +UCA0BR1=\$507! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$508! \ eUSCI_A modulation control +UCA0STAT=\$50A! \ eUSCI_A status +UCA0RXBUF=\$50C! \ eUSCI_A receive buffer +UCA0TXBUF=\$50E! \ eUSCI_A transmit buffer +UCA0ABCTL=\$510! \ eUSCI_A LIN control +UCA0IRTCTL=\$512! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$513! \ eUSCI_A IrDA receive control +UCA0IE=\$51A! \ eUSCI_A interrupt enable +UCA0IFG=\$51C! \ eUSCI_A interrupt flags +UCA0IV=\$51E! \ eUSCI_A interrupt vector word + + +UCB0CTLW0=\$540! \ eUSCI_B control word 0 +UCB0CTLW1=\$542! \ eUSCI_B control word 1 +UCB0BRW=\$546! +UCB0BR0=\$546! \ eUSCI_B bit rate 0 +UCB0BR1=\$547! \ eUSCI_B bit rate 1 +UCB0STATW=\$548! \ eUSCI_B status word +UCBCNT0=\$549! \ eUSCI_B hardware count +UCB0TBCNT=\$54A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$54C! \ eUSCI_B receive buffer +UCB0TXBUF=\$54E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$554! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$556! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$558! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$55A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$55C! \ eUSCI_B received address +UCB0ADDMASK=\$55E! \ eUSCI_B address mask +UCB0I2CSA=\$560! \ eUSCI I2C slave address +UCB0IE=\$56A! \ eUSCI interrupt enable +UCB0IFG=\$56C! \ eUSCI interrupt flags +UCB0IV=\$56E! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -LCDCTL0=\$600! \ LCD control register 0 -LCDCTL1=\$602! \ LCD control register 1 -LCDBLKCTL=\$604! \ LCD blink control register -LCDMEMCTL=\$606! \ LCD memory control register -LCDVCTL=\$608! \ LCD voltage control register -LCDPCTL0=\$60A! \ LCD port control 0 -LCDPCTL1=\$60C! \ LCD port control 1 -LCDPCTL2=\$60E! \ LCD port control 2 -LCDCSS0=\$614! \ LCD COM/SEG select register -LCDCSS1=\$616! \ LCD COM/SEG select register -LCDCSS2=\$618! \ LCD COM/SEG select register -LCDIV=\$61E! \ LCD interrupt vector -LCDM0=\$620! \ LCD memory 0 -LCDM1=\$621! \ LCD memory 1 -LCDM2=\$622! \ LCD memory 2 -LCDM3=\$623! \ LCD memory 3 -LCDM4=\$624! \ LCD memory 4 -LCDM5=\$625! \ LCD memory 5 -LCDM6=\$626! \ LCD memory 6 -LCDM7=\$627! \ LCD memory 7 -LCDM8=\$628! \ LCD memory 8 -LCDM9=\$629! \ LCD memory 9 -LCDM10=\$62A! \ LCD memory 10 -LCDM11=\$62B! \ LCD memory 11 -LCDM12=\$62C! \ LCD memory 12 -LCDM13=\$62D! \ LCD memory 13 -LCDM14=\$62E! \ LCD memory 14 -LCDM15=\$62F! \ LCD memory 15 -LCDM16=\$630! \ LCD memory 16 -LCDM17=\$631! \ LCD memory 17 -LCDM18=\$632! \ LCD memory 18 -LCDM19=\$633! \ LCD memory 19 -LCDM20=\$634! \ LCD memory 20 -LCDM21=\$635! \ LCD memory 21 -LCDM22=\$636! \ LCD memory 22 -LCDM23=\$637! \ LCD memory 23 -LCDM24=\$638! \ LCD memory 24 -LCDM25=\$639! \ LCD memory 25 -LCDM26=\$63A! \ LCD memory 26 -LCDM27=\$63B! \ LCD memory 27 -LCDM28=\$63C! \ LCD memory 28 -LCDM29=\$63D! \ LCD memory 29 -LCDM30=\$63E! \ LCD memory 30 -LCDM31=\$63F! \ LCD memory 31 -LCDM32=\$640! \ LCD memory 32 -LCDM33=\$641! \ LCD memory 33 -LCDM34=\$642! \ LCD memory 34 -LCDM35=\$643! \ LCD memory 35 -LCDM36=\$644! \ LCD memory 36 -LCDM37=\$645! \ LCD memory 37 -LCDM38=\$646! \ LCD memory 38 -LCDM39=\$647! \ LCD memory 39 -LCDBM0=\$640! \ LCD blinking memory 0 -LCDBM1=\$641! \ LCD blinking memory 1 -LCDBM2=\$642! \ LCD blinking memory 2 -LCDBM3=\$643! \ LCD blinking memory 3 -LCDBM4=\$644! \ LCD blinking memory 4 -LCDBM5=\$645! \ LCD blinking memory 5 -LCDBM6=\$646! \ LCD blinking memory 6 -LCDBM7=\$647! \ LCD blinking memory 7 -LCDBM8=\$648! \ LCD blinking memory 8 -LCDBM9=\$649! \ LCD blinking memory 9 -LCDBM10=\$64A! \ LCD blinking memory 10 -LCDBM11=\$64B! \ LCD blinking memory 11 -LCDBM12=\$64C! \ LCD blinking memory 12 -LCDBM13=\$64D! \ LCD blinking memory 13 -LCDBM14=\$64E! \ LCD blinking memory 14 -LCDBM15=\$64F! \ LCD blinking memory 15 -LCDBM16=\$650! \ LCD blinking memory 16 -LCDBM17=\$651! \ LCD blinking memory 17 -LCDBM18=\$652! \ LCD blinking memory 18 -LCDBM19=\$653! \ LCD blinking memory 19 - - -BAKMEM0=\$660! \ Backup Memory 0 -BAKMEM1=\$662! \ Backup Memory 1 -BAKMEM2=\$664! \ Backup Memory 2 -BAKMEM3=\$666! \ Backup Memory 3 -BAKMEM4=\$668! \ Backup Memory 4 -BAKMEM5=\$66A! \ Backup Memory 5 -BAKMEM6=\$66C! \ Backup Memory 6 -BAKMEM7=\$66E! \ Backup Memory 7 -BAKMEM8=\$670! \ Backup Memory 8 -BAKMEM9=\$672! \ Backup Memory 9 -BAKMEM10=\$674! \ Backup Memory 10 -BAKMEM11=\$676! \ Backup Memory 11 -BAKMEM12=\$678! \ Backup Memory 12 -BAKMEM13=\$67A! \ Backup Memory 13 -BAKMEM14=\$67C! \ Backup Memory 14 -BAKMEM15=\$67E! \ Backup Memory 15 - - - -ADC10CTL0=\$700! \ ADC10_B Control register 0 -ADC10CTL1=\$702! \ ADC10_B Control register 1 -ADC10CTL2=\$704! \ ADC10_B Control register 2 -ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold -ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold -ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 -ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register -ADC10IE=\$71A! \ ADC10_B Interrupt Enable -ADC10IFG=\$71C! \ ADC10_B Interrupt Flags -ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word +LCDCTL0=\$600! \ LCD control register 0 +LCDCTL1=\$602! \ LCD control register 1 +LCDBLKCTL=\$604! \ LCD blink control register +LCDMEMCTL=\$606! \ LCD memory control register +LCDVCTL=\$608! \ LCD voltage control register +LCDPCTL0=\$60A! \ LCD port control 0 +LCDPCTL1=\$60C! \ LCD port control 1 +LCDPCTL2=\$60E! \ LCD port control 2 +LCDCSS0=\$614! \ LCD COM/SEG select register +LCDCSS1=\$616! \ LCD COM/SEG select register +LCDCSS2=\$618! \ LCD COM/SEG select register +LCDIV=\$61E! \ LCD interrupt vector +LCDM0=\$620! \ LCD memory 0 +LCDM1=\$621! \ LCD memory 1 +LCDM2=\$622! \ LCD memory 2 +LCDM3=\$623! \ LCD memory 3 +LCDM4=\$624! \ LCD memory 4 +LCDM5=\$625! \ LCD memory 5 +LCDM6=\$626! \ LCD memory 6 +LCDM7=\$627! \ LCD memory 7 +LCDM8=\$628! \ LCD memory 8 +LCDM9=\$629! \ LCD memory 9 +LCDM10=\$62A! \ LCD memory 10 +LCDM11=\$62B! \ LCD memory 11 +LCDM12=\$62C! \ LCD memory 12 +LCDM13=\$62D! \ LCD memory 13 +LCDM14=\$62E! \ LCD memory 14 +LCDM15=\$62F! \ LCD memory 15 +LCDM16=\$630! \ LCD memory 16 +LCDM17=\$631! \ LCD memory 17 +LCDM18=\$632! \ LCD memory 18 +LCDM19=\$633! \ LCD memory 19 +LCDM20=\$634! \ LCD memory 20 +LCDM21=\$635! \ LCD memory 21 +LCDM22=\$636! \ LCD memory 22 +LCDM23=\$637! \ LCD memory 23 +LCDM24=\$638! \ LCD memory 24 +LCDM25=\$639! \ LCD memory 25 +LCDM26=\$63A! \ LCD memory 26 +LCDM27=\$63B! \ LCD memory 27 +LCDM28=\$63C! \ LCD memory 28 +LCDM29=\$63D! \ LCD memory 29 +LCDM30=\$63E! \ LCD memory 30 +LCDM31=\$63F! \ LCD memory 31 +LCDM32=\$640! \ LCD memory 32 +LCDM33=\$641! \ LCD memory 33 +LCDM34=\$642! \ LCD memory 34 +LCDM35=\$643! \ LCD memory 35 +LCDM36=\$644! \ LCD memory 36 +LCDM37=\$645! \ LCD memory 37 +LCDM38=\$646! \ LCD memory 38 +LCDM39=\$647! \ LCD memory 39 +LCDBM0=\$640! \ LCD blinking memory 0 +LCDBM1=\$641! \ LCD blinking memory 1 +LCDBM2=\$642! \ LCD blinking memory 2 +LCDBM3=\$643! \ LCD blinking memory 3 +LCDBM4=\$644! \ LCD blinking memory 4 +LCDBM5=\$645! \ LCD blinking memory 5 +LCDBM6=\$646! \ LCD blinking memory 6 +LCDBM7=\$647! \ LCD blinking memory 7 +LCDBM8=\$648! \ LCD blinking memory 8 +LCDBM9=\$649! \ LCD blinking memory 9 +LCDBM10=\$64A! \ LCD blinking memory 10 +LCDBM11=\$64B! \ LCD blinking memory 11 +LCDBM12=\$64C! \ LCD blinking memory 12 +LCDBM13=\$64D! \ LCD blinking memory 13 +LCDBM14=\$64E! \ LCD blinking memory 14 +LCDBM15=\$64F! \ LCD blinking memory 15 +LCDBM16=\$650! \ LCD blinking memory 16 +LCDBM17=\$651! \ LCD blinking memory 17 +LCDBM18=\$652! \ LCD blinking memory 18 +LCDBM19=\$653! \ LCD blinking memory 19 + + +BAKMEM0=\$660! \ Backup Memory 0 +BAKMEM1=\$662! \ Backup Memory 1 +BAKMEM2=\$664! \ Backup Memory 2 +BAKMEM3=\$666! \ Backup Memory 3 +BAKMEM4=\$668! \ Backup Memory 4 +BAKMEM5=\$66A! \ Backup Memory 5 +BAKMEM6=\$66C! \ Backup Memory 6 +BAKMEM7=\$66E! \ Backup Memory 7 +BAKMEM8=\$670! \ Backup Memory 8 +BAKMEM9=\$672! \ Backup Memory 9 +BAKMEM10=\$674! \ Backup Memory 10 +BAKMEM11=\$676! \ Backup Memory 11 +BAKMEM12=\$678! \ Backup Memory 12 +BAKMEM13=\$67A! \ Backup Memory 13 +BAKMEM14=\$67C! \ Backup Memory 14 +BAKMEM15=\$67E! \ Backup Memory 15 + + + +ADC10CTL0=\$700! \ ADC10_B Control register 0 +ADC10CTL1=\$702! \ ADC10_B Control register 1 +ADC10CTL2=\$704! \ ADC10_B Control register 2 +ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold +ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold +ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 +ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register +ADC10IE=\$71A! \ ADC10_B Interrupt Enable +ADC10IFG=\$71C! \ ADC10_B Interrupt Flags +ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word ADCON=\$10! ADCSTART=\$03! diff --git a/inc/MSP430FR5738.inc b/inc/MSP430FR5738.inc index 68e0263..69b9ee4 100644 --- a/inc/MSP430FR5738.inc +++ b/inc/MSP430FR5738.inc @@ -47,7 +47,7 @@ JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; mus JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD BSL_SIG1 .equ 0FF84h ; BSL_SIG2 .equ 0FF86h ; -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -104,10 +104,10 @@ BSL_PASSWORD .equ 0FFE0h ; 256 bits SFR_SFR .equ 0100h ; Special function PMM_SFR .equ 0120h ; PMM FRAM_SFR .equ 0140h ; FRAM control -CRC16_SFR .equ 0150h +CRC16_SFR .equ 0150h WDT_A_SFR .equ 015Ch ; Watchdog CS_SFR .equ 0160h -SYS_SFR .equ 0180h ; SYS +SYS_SFR .equ 0180h ; SYS REF_SFR .equ 01B0h ; REF PA_SFR .equ 0200h ; PORT1/2 PJ_SFR .equ 0320h ; PORTJ @@ -226,7 +226,7 @@ P1DIR .equ PA_SFR + 04h ; Port 1 DIRection P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1 -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable @@ -242,7 +242,7 @@ P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word .IFDEF UCB0_SD SD_SEL .equ PASEL1 ; word access, to configure UCB0 @@ -272,13 +272,13 @@ WIPE_IN .equ P2IN IO_WIPE .equ 1 ; P2.0 = TX + FORTH Deep_RST pin .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH HANDSHAKOUT .equ P2OUT HANDSHAKIN .equ P2IN RTS .equ 4 ; P2.2 .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired CTS .equ 8 ; P2.3 .ENDIF @@ -288,7 +288,7 @@ SD_CDIN .equ P2IN SD_CSOUT .equ P2OUT SD_CSDIR .equ P2DIR CD_SD .equ 8 ; P2.3 as SD Card Detect -CS_SD .equ 10h ; P2.4 as SD Chip Select +CS_SD .equ 10h ; P2.4 as SD Chip Select ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORTJ @@ -351,10 +351,10 @@ RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */ RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */ MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0 -MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 -MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 -MPUSEG .equ MPU_SFR + 04h ; MPU Segmentation Register -MPUSAM .equ MPU_SFR + 06h ; MPU access management +MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 +MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 +MPUSEG .equ MPU_SFR + 04h ; MPU Segmentation Register +MPUSAM .equ MPU_SFR + 06h ; MPU access management .IFDEF UCA0_TERM ; ---------------------------------------------------------------------- @@ -387,7 +387,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR5738.pat b/inc/MSP430FR5738.pat index 97bd663..a108d4d 100644 --- a/inc/MSP430FR5738.pat +++ b/inc/MSP430FR5738.pat @@ -33,42 +33,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! --------------------------------------- ! FAT16 FileSystemInfos ! --------------------------------------- @@ -154,7 +179,7 @@ HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE" HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=4! HandleLenght=28! FirstHandle=\$1890! @@ -183,7 +208,7 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes !SD_card Input Buffer = PAD @@ -195,46 +220,41 @@ SDIB_LEN=\$54! ! --------------------------------------- ! FastForth RAM memory map (= 1k) ! --------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ a good address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ORG=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO ! --------------------------------------- !1DE0! 28 RAM bytes free ! --------------------------------------- @@ -256,46 +276,54 @@ MAIN_LEN=\$3E00! 15.5 k FRAM SLEEP=\$C200! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$C20A! CODE compiled by LITERAL -XSQUOTE=\$C214! CODE compiled by S" and S_ -HEREXEC=\$C228! CODE HERE and BEGIN execute address -QFBRAN=\$C234! CODE compiled by IF UNTIL -BRAN=\$C23A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$C23C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$C23E! CODE compiled by DO -XPLOOP=\$C24E! CODE compiled by +LOOP -XLOOP=\$C260! CODE compiled by LOOP -MUSMOD=\$C266! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$C278! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$C280! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$C2AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$C2AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$C2BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$C2CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$C2D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$C2E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$C2EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$C21E! CODE compiled by S" and S_ +HEREXEC=\$C232! CODE HERE and BEGIN execute address +MUSMOD=\$C23E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$C250! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$C258! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$C282! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$C284! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$C294! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$C2A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$C2AC! CODE compiled by IF UNTIL +BRAN=\$C2B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$C2B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$C2B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$C2C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$C2F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$C32A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$C336! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$C2D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$C308! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$C312! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$C394! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$C39C! ASM CODE, content of WARM+2 by default -UART_RXON=\$C3C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$C3C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$C3B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$C38E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$C3BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$C3BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$C354! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$C37E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$C384! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$C386! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$C344! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$C346! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$C356! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$C356! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$C358! asm CODE, content of WARM+2 by default +I2C_WARM=\$C380! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR5738 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD @@ -467,27 +495,27 @@ TB0EX0=\$3E0! \ TB0 expansion register 0 TB0IV=\$3EE! \ TB0 interrupt vector -TB1CTL=\$400! \ TB1 control -TB1CCTL0=\$402! \ Capture/compare control 0 -TB1CCTL1=\$404! \ Capture/compare control 1 -TB1CCTL2=\$406! \ Capture/compare control 2 -TB1R=\$410! \ TB1 counter register -TB1CCR0=\$412! \ Capture/compare register 0 -TB1CCR1=\$414! \ Capture/compare register 1 -TB1CCR2=\$416! \ Capture/compare register 2 -TB1EX0=\$420! \ TB1 expansion register 0 -TB1IV=\$42E! \ TB1 interrupt vector - -TB2CTL=\$440! \ TB2 control -TB2CCTL0=\$442! \ Capture/compare control 0 -TB2CCTL1=\$444! \ Capture/compare control 1 -TB2CCTL2=\$446! \ Capture/compare control 2 -TB2R=\$450! \ TB2 counter register -TB2CCR0=\$452! \ Capture/compare register 0 -TB2CCR1=\$454! \ Capture/compare register 1 -TB2CCR2=\$456! \ Capture/compare register 2 -TB2EX0=\$460! \ TB2 expansion register 0 -TB2IV=\$46E! \ TB2 interrupt vector +TB1CTL=\$400! \ TB1 control +TB1CCTL0=\$402! \ Capture/compare control 0 +TB1CCTL1=\$404! \ Capture/compare control 1 +TB1CCTL2=\$406! \ Capture/compare control 2 +TB1R=\$410! \ TB1 counter register +TB1CCR0=\$412! \ Capture/compare register 0 +TB1CCR1=\$414! \ Capture/compare register 1 +TB1CCR2=\$416! \ Capture/compare register 2 +TB1EX0=\$420! \ TB1 expansion register 0 +TB1IV=\$42E! \ TB1 interrupt vector + +TB2CTL=\$440! \ TB2 control +TB2CCTL0=\$442! \ Capture/compare control 0 +TB2CCTL1=\$444! \ Capture/compare control 1 +TB2CCTL2=\$446! \ Capture/compare control 2 +TB2R=\$450! \ TB2 counter register +TB2CCR0=\$452! \ Capture/compare register 0 +TB2CCR1=\$454! \ Capture/compare register 1 +TB2CCR2=\$456! \ Capture/compare register 2 +TB2EX0=\$460! \ TB2 expansion register 0 +TB2IV=\$46E! \ TB2 interrupt vector ! RTC_B RTCCTL0=\$4A0! \ RTC control 0 diff --git a/inc/MSP430FR5739.inc b/inc/MSP430FR5739.inc index 03e50c1..a84076a 100644 --- a/inc/MSP430FR5739.inc +++ b/inc/MSP430FR5739.inc @@ -48,7 +48,7 @@ JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; mus JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD BSL_SIG1 .equ 0FF84h ; BSL_SIG2 .equ 0FF86h ; -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -109,10 +109,10 @@ BSL_PASSWORD .equ 0FFE0h ; 256 bits SFR_SFR .equ 0100h ; Special function PMM_SFR .equ 0120h ; PMM FRAM_SFR .equ 0140h ; FRAM control -CRC16_SFR .equ 0150h +CRC16_SFR .equ 0150h WDT_A_SFR .equ 015Ch ; Watchdog CS_SFR .equ 0160h -SYS_SFR .equ 0180h ; SYS +SYS_SFR .equ 0180h ; SYS REF_SFR .equ 01B0h ; REF PA_SFR .equ 0200h ; PORT1/2 PB_SFR .equ 0220h ; PORT3/4 @@ -239,7 +239,7 @@ P1DIR .equ PA_SFR + 04h ; Port 1 DIRection P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1 -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable @@ -255,7 +255,7 @@ P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3/4 @@ -360,10 +360,10 @@ RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */ MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0 -MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 -MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 -MPUSEG .equ MPU_SFR + 04h ; MPU Segmentation Register -MPUSAM .equ MPU_SFR + 06h ; MPU access management +MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 +MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 +MPUSEG .equ MPU_SFR + 04h ; MPU Segmentation Register +MPUSAM .equ MPU_SFR + 06h ; MPU access management .IFDEF UCA0_TERM @@ -410,7 +410,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR5739.pat b/inc/MSP430FR5739.pat index 057f04f..26ae408 100644 --- a/inc/MSP430FR5739.pat +++ b/inc/MSP430FR5739.pat @@ -37,42 +37,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! --------------------------------------- ! FAT16 FileSystemInfos ! --------------------------------------- @@ -158,7 +183,7 @@ HDLW_BUFofst=22! BUFFER offset ; used by LOAD" and by WRITE" HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=4! HandleLenght=28! FirstHandle=\$1890! @@ -187,7 +212,7 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes !SD_card Input Buffer = PAD @@ -199,48 +224,43 @@ SDIB_LEN=\$54! ! ---------------------------------------------- ! FastForth RAM memory map (= 1k): ! ---------------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ a good address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ORG=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!1DE0! 28 RAM bytes free +!1DE0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -260,46 +280,54 @@ MAIN_LEN=\$3E00! 15.5 k FRAM SLEEP=\$C200! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$C20A! CODE compiled by LITERAL -XSQUOTE=\$C214! CODE compiled by S" and S_ -HEREXEC=\$C228! CODE HERE and BEGIN execute address -QFBRAN=\$C234! CODE compiled by IF UNTIL -BRAN=\$C23A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$C23C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$C23E! CODE compiled by DO -XPLOOP=\$C24E! CODE compiled by +LOOP -XLOOP=\$C260! CODE compiled by LOOP -MUSMOD=\$C266! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$C278! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$C280! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$C2AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$C2AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$C2BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$C2CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$C2D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$C2E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$C2EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$C21E! CODE compiled by S" and S_ +HEREXEC=\$C232! CODE HERE and BEGIN execute address +MUSMOD=\$C23E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$C250! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$C258! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$C282! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$C284! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$C294! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$C2A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$C2AC! CODE compiled by IF UNTIL +BRAN=\$C2B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$C2B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$C2B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$C2C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$C2F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$C32A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$C336! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$C2D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$C308! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$C312! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$C394! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$C39C! ASM CODE, content of WARM+2 by default -UART_RXON=\$C3C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$C3C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$C3B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$C38E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$C3BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$C3BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$C354! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$C37E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$C384! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$C386! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$C344! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$C346! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$C356! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$C356! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$C358! asm CODE, content of WARM+2 by default +I2C_WARM=\$C380! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR5739 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD @@ -352,41 +380,41 @@ SFRIFG1=\$102! \ SFR flag register SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -FRCTLCTL0=\$140! \ FRAM control 0 -GCCTL0=\$144! \ General control 0 -GCCTL1=\$146! \ General control 1 +FRCTLCTL0=\$140! \ FRAM control 0 +GCCTL0=\$144! \ General control 0 +GCCTL1=\$146! \ General control 1 -CRC16DI=\$150! \ CRC data input -CRCDIRB=\$152! \ CRC data input reverse byte -CRCINIRES=\$154! \ CRC initialization and result -CRCRESR=\$156! \ CRC result reverse byte +CRC16DI=\$150! \ CRC data input +CRCDIRB=\$152! \ CRC data input reverse byte +CRCINIRES=\$154! \ CRC initialization and result +CRCRESR=\$156! \ CRC result reverse byte WDTCTL=\$15C! \ WDT control register CSCTL0=\$160! \ CS control 0 -CSCTL0_H=\$161! \ -CSCTL1=\$162! \ CS control 1 -CSCTL2=\$164! \ CS control 2 -CSCTL3=\$166! \ CS control 3 -CSCTL4=\$168! \ CS control 4 -CSCTL5=\$16A! \ CS control 5 -CSCTL6=\$16C! \ CS control 6 - -SYSCTL=\$180! \ System control -SYSJMBC=\$186! \ JTAG mailbox control -SYSJMBI0=\$188! \ JTAG mailbox input 0 -SYSJMBI1=\$18A! \ JTAG mailbox input 1 -SYSJMBO0=\$18C! \ JTAG mailbox output 0 -SYSJMBO1=\$18E! \ JTAG mailbox output 1 -SYSBERRIV=\$198! \ Bus Error vector generator -SYSUNIV=\$19A! \ User NMI vector generator -SYSSNIV=\$19C! \ System NMI vector generator -SYSRSTIV=\$19E! \ Reset vector generator - -REFCTL=\$1b0! \ Shared reference control +CSCTL0_H=\$161! \ +CSCTL1=\$162! \ CS control 1 +CSCTL2=\$164! \ CS control 2 +CSCTL3=\$166! \ CS control 3 +CSCTL4=\$168! \ CS control 4 +CSCTL5=\$16A! \ CS control 5 +CSCTL6=\$16C! \ CS control 6 + +SYSCTL=\$180! \ System control +SYSJMBC=\$186! \ JTAG mailbox control +SYSJMBI0=\$188! \ JTAG mailbox input 0 +SYSJMBI1=\$18A! \ JTAG mailbox input 1 +SYSJMBO0=\$18C! \ JTAG mailbox output 0 +SYSJMBO1=\$18E! \ JTAG mailbox output 1 +SYSBERRIV=\$198! \ Bus Error vector generator +SYSUNIV=\$19A! \ User NMI vector generator +SYSSNIV=\$19C! \ System NMI vector generator +SYSRSTIV=\$19E! \ Reset vector generator + +REFCTL=\$1b0! \ Shared reference control PAIN=\$200! PAOUT=\$202! @@ -473,86 +501,86 @@ TBCLR=4! TBIFG=1! CCIFG=1! -TA0CTL=\$340! \ TA0 control -TA0CCTL0=\$342! \ Capture/compare control 0 -TA0CCTL1=\$344! \ Capture/compare control 1 -TA0CCTL2=\$346! \ Capture/compare control 2 -TA0R=\$350! \ TA0 counter register -TA0CCR0=\$352! \ Capture/compare register 0 -TA0CCR1=\$354! \ Capture/compare register 1 -TA0CCR2=\$356! \ Capture/compare register 2 -TA0EX0=\$360! \ TA0 expansion register 0 -TA0IV=\$36E! \ TA0 interrupt vector - -TA1CTL=\$380! \ TA1 control -TA1CCTL0=\$382! \ Capture/compare control 0 -TA1CCTL1=\$384! \ Capture/compare control 1 -TA1CCTL2=\$386! \ Capture/compare control 2 -TA1R=\$390! \ TA1 counter register -TA1CCR0=\$392! \ Capture/compare register 0 -TA1CCR1=\$394! \ Capture/compare register 1 -TA1CCR2=\$396! \ Capture/compare register 2 -TA1EX0=\$3A0! \ TA1 expansion register 0 -TA1IV=\$3AE! \ TA1 interrupt vector - -TB0CTL=\$3C0! \ TB0 control -TB0CCTL0=\$3C2! \ Capture/compare control 0 -TB0CCTL1=\$3C4! \ Capture/compare control 1 -TB0CCTL2=\$3C6! \ Capture/compare control 2 -TB0R=\$3D0! \ TB0 counter register -TB0CCR0=\$3D2! \ Capture/compare register 0 -TB0CCR1=\$3D4! \ Capture/compare register 1 -TB0CCR2=\$3D6! \ Capture/compare register 2 -TB0EX0=\$3E0! \ TB0 expansion register 0 -TB0IV=\$3EE! \ TB0 interrupt vector - -TB1CTL=\$400! \ TB1 control -TB1CCTL0=\$402! \ Capture/compare control 0 -TB1CCTL1=\$404! \ Capture/compare control 1 -TB1CCTL2=\$406! \ Capture/compare control 2 -TB1R=\$410! \ TB1 counter register -TB1CCR0=\$412! \ Capture/compare register 0 -TB1CCR1=\$414! \ Capture/compare register 1 -TB1CCR2=\$416! \ Capture/compare register 2 -TB1EX0=\$420! \ TB1 expansion register 0 -TB1IV=\$42E! \ TB1 interrupt vector - -TB2CTL=\$440! \ TB2 control -TB2CCTL0=\$442! \ Capture/compare control 0 -TB2CCTL1=\$444! \ Capture/compare control 1 -TB2CCTL2=\$446! \ Capture/compare control 2 -TB2R=\$450! \ TB2 counter register -TB2CCR0=\$452! \ Capture/compare register 0 -TB2CCR1=\$454! \ Capture/compare register 1 -TB2CCR2=\$456! \ Capture/compare register 2 -TB2EX0=\$460! \ TB2 expansion register 0 -TB2IV=\$46E! \ TB2 interrupt vector +TA0CTL=\$340! \ TA0 control +TA0CCTL0=\$342! \ Capture/compare control 0 +TA0CCTL1=\$344! \ Capture/compare control 1 +TA0CCTL2=\$346! \ Capture/compare control 2 +TA0R=\$350! \ TA0 counter register +TA0CCR0=\$352! \ Capture/compare register 0 +TA0CCR1=\$354! \ Capture/compare register 1 +TA0CCR2=\$356! \ Capture/compare register 2 +TA0EX0=\$360! \ TA0 expansion register 0 +TA0IV=\$36E! \ TA0 interrupt vector + +TA1CTL=\$380! \ TA1 control +TA1CCTL0=\$382! \ Capture/compare control 0 +TA1CCTL1=\$384! \ Capture/compare control 1 +TA1CCTL2=\$386! \ Capture/compare control 2 +TA1R=\$390! \ TA1 counter register +TA1CCR0=\$392! \ Capture/compare register 0 +TA1CCR1=\$394! \ Capture/compare register 1 +TA1CCR2=\$396! \ Capture/compare register 2 +TA1EX0=\$3A0! \ TA1 expansion register 0 +TA1IV=\$3AE! \ TA1 interrupt vector + +TB0CTL=\$3C0! \ TB0 control +TB0CCTL0=\$3C2! \ Capture/compare control 0 +TB0CCTL1=\$3C4! \ Capture/compare control 1 +TB0CCTL2=\$3C6! \ Capture/compare control 2 +TB0R=\$3D0! \ TB0 counter register +TB0CCR0=\$3D2! \ Capture/compare register 0 +TB0CCR1=\$3D4! \ Capture/compare register 1 +TB0CCR2=\$3D6! \ Capture/compare register 2 +TB0EX0=\$3E0! \ TB0 expansion register 0 +TB0IV=\$3EE! \ TB0 interrupt vector + +TB1CTL=\$400! \ TB1 control +TB1CCTL0=\$402! \ Capture/compare control 0 +TB1CCTL1=\$404! \ Capture/compare control 1 +TB1CCTL2=\$406! \ Capture/compare control 2 +TB1R=\$410! \ TB1 counter register +TB1CCR0=\$412! \ Capture/compare register 0 +TB1CCR1=\$414! \ Capture/compare register 1 +TB1CCR2=\$416! \ Capture/compare register 2 +TB1EX0=\$420! \ TB1 expansion register 0 +TB1IV=\$42E! \ TB1 interrupt vector + +TB2CTL=\$440! \ TB2 control +TB2CCTL0=\$442! \ Capture/compare control 0 +TB2CCTL1=\$444! \ Capture/compare control 1 +TB2CCTL2=\$446! \ Capture/compare control 2 +TB2R=\$450! \ TB2 counter register +TB2CCR0=\$452! \ Capture/compare register 0 +TB2CCR1=\$454! \ Capture/compare register 1 +TB2CCR2=\$456! \ Capture/compare register 2 +TB2EX0=\$460! \ TB2 expansion register 0 +TB2IV=\$46E! \ TB2 interrupt vector ! RTC_B -RTCCTL0=\$4A0! \ RTC control 0 -RTCCTL1=\$4A1! \ RTC control 1 -RTCCTL2=\$4A2! \ RTC control 2 -RTCCTL3=\$4A3! \ RTC control 3 -RTCPS0CTL=\$4A8! \ RTC prescaler 0 control -RTCPS1CTL=\$4AA! \ RTC prescaler 1 control -RTCPS0=\$4AC! \ RTC prescaler 0 -RTCPS1=\$4AD! \ RTC prescaler 1 -RTCIV=\$4AE! \ RTC interrupt vector word -RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, -RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, -RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, -RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, -RTCDAY=\$4B4! \ RTC days +RTCCTL0=\$4A0! \ RTC control 0 +RTCCTL1=\$4A1! \ RTC control 1 +RTCCTL2=\$4A2! \ RTC control 2 +RTCCTL3=\$4A3! \ RTC control 3 +RTCPS0CTL=\$4A8! \ RTC prescaler 0 control +RTCPS1CTL=\$4AA! \ RTC prescaler 1 control +RTCPS0=\$4AC! \ RTC prescaler 0 +RTCPS1=\$4AD! \ RTC prescaler 1 +RTCIV=\$4AE! \ RTC interrupt vector word +RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, +RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, +RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, +RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, +RTCDAY=\$4B4! \ RTC days RTCMON=\$4B5! \ RTC month -RTCYEAR=\$4B6! -RTCYEARL=\$4B6! \ RTC year low -RTCYEARH=\$4B7! \ RTC year high -RTCAMIN=\$4B8! \ RTC alarm minutes -RTCAHOUR=\$4B9! \ RTC alarm hours -RTCADOW=\$4BA! \ RTC alarm day of week -RTCADAY=\$4BB! \ RTC alarm days -BIN2BCD=\$4BC! \ Binary-to-BCD conversion register -BCD2BIN=\$4BE! \ BCD-to-binary conversion register +RTCYEAR=\$4B6! +RTCYEARL=\$4B6! \ RTC year low +RTCYEARH=\$4B7! \ RTC year high +RTCAMIN=\$4B8! \ RTC alarm minutes +RTCAHOUR=\$4B9! \ RTC alarm hours +RTCADOW=\$4BA! \ RTC alarm day of week +RTCADAY=\$4BB! \ RTC alarm days +BIN2BCD=\$4BC! \ Binary-to-BCD conversion register +BCD2BIN=\$4BE! \ BCD-to-binary conversion register RTCHOLD=\$40! RTCRDY=\$10! @@ -582,102 +610,102 @@ MPY32CTL0=\$4EC! \ MPY32 control register 0 DMAIFG=8! -DMA0CTL=\$500! \ DMA channel 0 control -DMA0SAL=\$502! \ DMA channel 0 source address low -DMA0SAH=\$504! \ DMA channel 0 source address high -DMA0DAL=\$506! \ DMA channel 0 destination address low -DMA0DAH=\$508! \ DMA channel 0 destination address high -DMA0SZ=\$50A! \ DMA channel 0 transfer size -DMA1CTL=\$510! \ DMA channel 1 control -DMA1SAL=\$512! \ DMA channel 1 source address low -DMA1SAH=\$514! \ DMA channel 1 source address high -DMA1DAL=\$516! \ DMA channel 1 destination address low -DMA1DAH=\$518! \ DMA channel 1 destination address high -DMA1SZ=\$51A! \ DMA channel 1 transfer size -DMA2CTL=\$520! \ DMA channel 2 control -DMA2SAL=\$522! \ DMA channel 2 source address low -DMA2SAH=\$524! \ DMA channel 2 source address high -DMA2DAL=\$526! \ DMA channel 2 destination address low -DMA2DAH=\$528! \ DMA channel 2 destination address high -DMA2SZ=\$52A! \ DMA channel 2 transfer size -DMACTL0=\$530! \ DMA module control 0 -DMACTL1=\$532! \ DMA module control 1 -DMACTL2=\$534! \ DMA module control 2 -DMACTL3=\$536! \ DMA module control 3 -DMACTL4=\$538! \ DMA module control 4 -DMAIV=\$53A! \ DMA interrupt vector - -MPUCTL0=\$5A0! \ MPU control 0 -MPUCTL1=\$5A2! \ MPU control 1 -MPUSEG=\$5A4! \ MPU Segmentation Register -MPUSAM=\$5A6! \ MPU access management - -UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 -UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 -UCA0BRW=\$5C6! -UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 -UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$5C8! \ eUSCI_A modulation control -UCA0STAT=\$5CA! \ eUSCI_A status -UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer -UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer -UCA0ABCTL=\$5D0! \ eUSCI_A LIN control -UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control -UCA0IE=\$5DA! \ eUSCI_A interrupt enable -UCA0IFG=\$5DC! \ eUSCI_A interrupt flags -UCA0IV=\$5DE! \ eUSCI_A interrupt vector word - -UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 -UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 -UCA1BRW=\$5E6! -UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 -UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 -UCA1MCTLW=\$5E8! \ eUSCI_A modulation control -UCA1STAT=\$5EA! \ eUSCI_A status -UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer -UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer -UCA1ABCTL=\$5F0! \ eUSCI_A LIN control -UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control -UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control -UCA1IE=\$5FA! \ eUSCI_A interrupt enable -UCA1IFG=\$5FC! \ eUSCI_A interrupt flags -UCA1IV=\$5FE! \ eUSCI_A interrupt vector word - -UCB0CTLW0=\$640! \ eUSCI_B control word 0 -UCB0CTLW1=\$642! \ eUSCI_B control word 1 -UCB0BRW=\$646! -UCB0BR0=\$646! \ eUSCI_B bit rate 0 -UCB0BR1=\$647! \ eUSCI_B bit rate 1 -UCB0STATW=\$648! \ eUSCI_B status word -UCBCNT0=\$649! \ eUSCI_B hardware count -UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$64C! \ eUSCI_B receive buffer -UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$65C! \ eUSCI_B received address -UCB0ADDMASK=\$65E! \ eUSCI_B address mask -UCB0I2CSA=\$660! \ eUSCI I2C slave address -UCB0IE=\$66A! \ eUSCI interrupt enable -UCB0IFG=\$66C! \ eUSCI interrupt flags -UCB0IV=\$66E! \ eUSCI interrupt vector word +DMA0CTL=\$500! \ DMA channel 0 control +DMA0SAL=\$502! \ DMA channel 0 source address low +DMA0SAH=\$504! \ DMA channel 0 source address high +DMA0DAL=\$506! \ DMA channel 0 destination address low +DMA0DAH=\$508! \ DMA channel 0 destination address high +DMA0SZ=\$50A! \ DMA channel 0 transfer size +DMA1CTL=\$510! \ DMA channel 1 control +DMA1SAL=\$512! \ DMA channel 1 source address low +DMA1SAH=\$514! \ DMA channel 1 source address high +DMA1DAL=\$516! \ DMA channel 1 destination address low +DMA1DAH=\$518! \ DMA channel 1 destination address high +DMA1SZ=\$51A! \ DMA channel 1 transfer size +DMA2CTL=\$520! \ DMA channel 2 control +DMA2SAL=\$522! \ DMA channel 2 source address low +DMA2SAH=\$524! \ DMA channel 2 source address high +DMA2DAL=\$526! \ DMA channel 2 destination address low +DMA2DAH=\$528! \ DMA channel 2 destination address high +DMA2SZ=\$52A! \ DMA channel 2 transfer size +DMACTL0=\$530! \ DMA module control 0 +DMACTL1=\$532! \ DMA module control 1 +DMACTL2=\$534! \ DMA module control 2 +DMACTL3=\$536! \ DMA module control 3 +DMACTL4=\$538! \ DMA module control 4 +DMAIV=\$53A! \ DMA interrupt vector + +MPUCTL0=\$5A0! \ MPU control 0 +MPUCTL1=\$5A2! \ MPU control 1 +MPUSEG=\$5A4! \ MPU Segmentation Register +MPUSAM=\$5A6! \ MPU access management + +UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 +UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 +UCA0BRW=\$5C6! +UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 +UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$5C8! \ eUSCI_A modulation control +UCA0STAT=\$5CA! \ eUSCI_A status +UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer +UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer +UCA0ABCTL=\$5D0! \ eUSCI_A LIN control +UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control +UCA0IE=\$5DA! \ eUSCI_A interrupt enable +UCA0IFG=\$5DC! \ eUSCI_A interrupt flags +UCA0IV=\$5DE! \ eUSCI_A interrupt vector word + +UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 +UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 +UCA1BRW=\$5E6! +UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 +UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 +UCA1MCTLW=\$5E8! \ eUSCI_A modulation control +UCA1STAT=\$5EA! \ eUSCI_A status +UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer +UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer +UCA1ABCTL=\$5F0! \ eUSCI_A LIN control +UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control +UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control +UCA1IE=\$5FA! \ eUSCI_A interrupt enable +UCA1IFG=\$5FC! \ eUSCI_A interrupt flags +UCA1IV=\$5FE! \ eUSCI_A interrupt vector word + +UCB0CTLW0=\$640! \ eUSCI_B control word 0 +UCB0CTLW1=\$642! \ eUSCI_B control word 1 +UCB0BRW=\$646! +UCB0BR0=\$646! \ eUSCI_B bit rate 0 +UCB0BR1=\$647! \ eUSCI_B bit rate 1 +UCB0STATW=\$648! \ eUSCI_B status word +UCBCNT0=\$649! \ eUSCI_B hardware count +UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$64C! \ eUSCI_B receive buffer +UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$65C! \ eUSCI_B received address +UCB0ADDMASK=\$65E! \ eUSCI_B address mask +UCB0I2CSA=\$660! \ eUSCI I2C slave address +UCB0IE=\$66A! \ eUSCI interrupt enable +UCB0IFG=\$66C! \ eUSCI interrupt flags +UCB0IV=\$66E! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -ADC10CTL0=\$700! \ ADC10_B Control register 0 -ADC10CTL1=\$702! \ ADC10_B Control register 1 -ADC10CTL2=\$704! \ ADC10_B Control register 2 -ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold -ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold -ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 -ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register -ADC10IE=\$71A! \ ADC10_B Interrupt Enable -ADC10IFG=\$71C! \ ADC10_B Interrupt Flags -ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word +ADC10CTL0=\$700! \ ADC10_B Control register 0 +ADC10CTL1=\$702! \ ADC10_B Control register 1 +ADC10CTL2=\$704! \ ADC10_B Control register 2 +ADC10LO=\$706! \ ADC10_B Window Comparator Low Threshold +ADC10HI=\$708! \ ADC10_B Window Comparator High Threshold +ADC10MCTL0=\$70A! \ ADC10_B Memory Control Register 0 +ADC10MEM0=\$712! \ ADC10_B Conversion Memory Register +ADC10IE=\$71A! \ ADC10_B Interrupt Enable +ADC10IFG=\$71C! \ ADC10_B Interrupt Flags +ADC10IV=\$71E! \ ADC10_B Interrupt Vector Word ADCON=\$10! ADCSTART=\$03! @@ -685,9 +713,9 @@ ADCSTART=\$03! CDIFG=1! CDIIFG=2! -CDCTL0=\$8C0! \ Comparator_D control register 0 -CDCTL1=\$8C2! \ Comparator_D control register 1 -CDCTL2=\$8C4! \ Comparator_D control register 2 -CDCTL3=\$8C6! \ Comparator_D control register 3 -CDINT=\$8CC! \ Comparator_D interrupt register -CDIV=\$8CE! \ Comparator_D interrupt vector word +CDCTL0=\$8C0! \ Comparator_D control register 0 +CDCTL1=\$8C2! \ Comparator_D control register 1 +CDCTL2=\$8C4! \ Comparator_D control register 2 +CDCTL3=\$8C6! \ Comparator_D control register 3 +CDINT=\$8CC! \ Comparator_D interrupt register +CDIV=\$8CE! \ Comparator_D interrupt vector word diff --git a/inc/MSP430FR5948.inc b/inc/MSP430FR5948.inc index 90f331b..ce112e6 100644 --- a/inc/MSP430FR5948.inc +++ b/inc/MSP430FR5948.inc @@ -26,7 +26,7 @@ DEVICE = "MSP430FR5948" ; ---------------------------------------------- PAGESIZE .equ 512 ; MPU unit ; ---------------------------------------------- -; BSL +; BSL ; ---------------------------------------------- BSL .equ 1000h ; ---------------------------------------------- @@ -64,7 +64,7 @@ BSL_SIG2 .equ 0FF86h ; JTAG_PASSWORD .equ 0FF88h ; 256 bits max IPE_SIG_VALID .equ 0FF88h ; one word IPE_STR_PTR_SRC .equ 0FF8Ah ; one word -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -270,7 +270,7 @@ P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P2IN .equ PA_SFR + 01h ; Port 2 INput P2OUT .equ PA_SFR + 03h ; Port 2 OUTput @@ -282,15 +282,15 @@ P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word WIPE_IN .equ P2IN IO_WIPE .equ 1 ; P2.0 = FORTH Deep_RST pin .IFDEF UCA0_TERM -; P2.0 UCA0-TXD --> USB2UART RXD -; P2.1 UCA0-RXD <-- USB2UART TXD +; P2.0 UCA0-TXD --> USB2UART RXD +; P2.1 UCA0-RXD <-- USB2UART TXD TXD .equ 1 ; P2.0 = TX + FORTH Deep_RST pin RXD .equ 2 ; P2.1 = RX BUS_TERM .equ 3 @@ -307,13 +307,13 @@ BUS_SD .equ 04C0h ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0S .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH HANDSHAKOUT .equ P2OUT HANDSHAKIN .equ P2IN RTS .equ 4 ; P2.2 .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired CTS .equ 8 ; P2.3 .ENDIF ; TERMINAL5WIRES @@ -346,7 +346,7 @@ P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag -P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word +P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word P4IN .equ PB_SFR + 01h ; Port 4 Input */ P4OUT .equ PB_SFR + 03h ; Port 4 Output @@ -358,7 +358,7 @@ P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag -P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word +P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORTJ @@ -467,7 +467,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR5948.pat b/inc/MSP430FR5948.pat index fcb2420..32d54d2 100644 --- a/inc/MSP430FR5948.pat +++ b/inc/MSP430FR5948.pat @@ -32,42 +32,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -88,55 +113,49 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! --------------------------------------- ! FastForth RAM memory map (>= 1k) ! --------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ base address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ADR=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO - +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!1DE0! 28 RAM bytes free +!1DE0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -148,7 +167,7 @@ SD_BUF=\$1E00! \ SD_Card buffer BUFEND=\$2000! ! --------------------------------------- -! FAT16 FileSystemInfos +! FAT16 FileSystemInfos ! --------------------------------------- FATtype=\$2002! BS_FirstSectorL=\$2004! @@ -176,7 +195,7 @@ SectorH=\$201C! ! --------------------------------------- ! BUFFER management ! --------------------------------------- -BufferPtr=\$201E! +BufferPtr=\$201E! BufferLen=\$2020! ! --------------------------------------- @@ -184,16 +203,16 @@ BufferLen=\$2020! ! --------------------------------------- ClusterL=\$2022! 16 bits wide (FAT16) ClusterH=\$2024! 16 bits wide (FAT16) -NewClusterL=\$2026! 16 bits wide (FAT16) -NewClusterH=\$2028! 16 bits wide (FAT16) -CurFATsector=\$202A! +NewClusterL=\$2026! 16 bits wide (FAT16) +NewClusterH=\$2028! 16 bits wide (FAT16) +CurFATsector=\$202A! ! --------------------------------------- ! DIR entry ! --------------------------------------- DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory -EntryOfst=\$2030! +EntryOfst=\$2030! ! --------------------------------------- ! Handle Pointer @@ -209,7 +228,7 @@ EndOfPath=\$2036! ! --------------------------------------- ! Handle structure ! --------------------------------------- -! three handle tokens : +! three handle tokens : ! token = 0 : free handle ! token = 1 : file to read ! token = 2 : file updated (write) @@ -233,7 +252,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2038! @@ -257,51 +276,59 @@ MAIN_LEN=\$BC00! 47 k FRAM SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$440A! CODE compiled by LITERAL -XSQUOTE=\$4414! CODE compiled by S" and S_ -HEREXEC=\$4428! CODE HERE and BEGIN execute address -QFBRAN=\$4434! CODE compiled by IF UNTIL -BRAN=\$443A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$443C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$443E! CODE compiled by DO -XPLOOP=\$444E! CODE compiled by +LOOP -XLOOP=\$4460! CODE compiled by LOOP -MUSMOD=\$4466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$4478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$4480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$44AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$44AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$44BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$44CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$44D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$44E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$44EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$441E! CODE compiled by S" and S_ +HEREXEC=\$4432! CODE HERE and BEGIN execute address +MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$4494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$44AC! CODE compiled by IF UNTIL +BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$44F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$452A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$4536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$4594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$459C! ASM CODE, content of WARM+2 by default -UART_RXON=\$45C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$45C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$45B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$458E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$45BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$45BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$4584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$4586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$4544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$4556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$4556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$4558! asm CODE, content of WARM+2 by default +I2C_WARM=\$4580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR5948 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD -BSL_SIG1=\$FF84! -BSL_SIG2=\$FF86! +BSL_SIG1=\$FF84! +BSL_SIG2=\$FF86! I2CSLA0=\$FFA2! UCBxI2COA0 default value address I2CSLA1=\$FFA4! UCBxI2COA1 default value address I2CSLA2=\$FFA6! UCBxI2COA2 default value address @@ -348,39 +375,39 @@ SFRIFG1=\$102! \ SFR flag register SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -FRCTLCTL0=\$140! \ FRAM control 0 -GCCTL0=\$144! \ General control 0 -GCCTL1=\$146! \ General control 1 +FRCTLCTL0=\$140! \ FRAM control 0 +GCCTL0=\$144! \ General control 0 +GCCTL1=\$146! \ General control 1 -CRC16DI=\$150! \ CRC data input -CRCDIRB=\$152! \ CRC data input reverse byte -CRCINIRES=\$154! \ CRC initialization and result -CRCRESR=\$156! \ CRC result reverse byte +CRC16DI=\$150! \ CRC data input +CRCDIRB=\$152! \ CRC data input reverse byte +CRCINIRES=\$154! \ CRC initialization and result +CRCRESR=\$156! \ CRC result reverse byte WDTCTL=\$15C! \ WDT control register -CSCTL0=\$160! \ CS control 0 -CSCTL1=\$162! \ CS control 1 -CSCTL2=\$164! \ CS control 2 -CSCTL3=\$166! \ CS control 3 -CSCTL4=\$168! \ CS control 4 -CSCTL5=\$16A! \ CS control 5 -CSCTL6=\$16C! \ CS control 6 - -SYSCTL=\$180! \ System control -SYSJMBC=\$186! \ JTAG mailbox control -SYSJMBI0=\$188! \ JTAG mailbox input 0 -SYSJMBI1=\$18A! \ JTAG mailbox input 1 -SYSJMBO0=\$18C! \ JTAG mailbox output 0 -SYSJMBO1=\$18E! \ JTAG mailbox output 1 -SYSUNIV=\$19A! \ User NMI vector generator -SYSSNIV=\$19C! \ System NMI vector generator -SYSRSTIV=\$19E! \ Reset vector generator - -REFCTL=\$1B0! \ Shared reference control +CSCTL0=\$160! \ CS control 0 +CSCTL1=\$162! \ CS control 1 +CSCTL2=\$164! \ CS control 2 +CSCTL3=\$166! \ CS control 3 +CSCTL4=\$168! \ CS control 4 +CSCTL5=\$16A! \ CS control 5 +CSCTL6=\$16C! \ CS control 6 + +SYSCTL=\$180! \ System control +SYSJMBC=\$186! \ JTAG mailbox control +SYSJMBI0=\$188! \ JTAG mailbox input 0 +SYSJMBI1=\$18A! \ JTAG mailbox input 1 +SYSJMBO0=\$18C! \ JTAG mailbox output 0 +SYSJMBO1=\$18E! \ JTAG mailbox output 1 +SYSUNIV=\$19A! \ User NMI vector generator +SYSSNIV=\$19C! \ System NMI vector generator +SYSRSTIV=\$19E! \ Reset vector generator + +REFCTL=\$1B0! \ Shared reference control PAIN=\$200! PAOUT=\$202! @@ -467,90 +494,90 @@ TBCLR=2! TBIFG=1! CCIFG=1! -TA0CTL=\$340! \ TA0 control -TA0CCTL0=\$342! \ Capture/compare control 0 -TA0CCTL1=\$344! \ Capture/compare control 1 -TA0CCTL2=\$346! \ Capture/compare control 2 -TA0R=\$350! \ TA0 counter register -TA0CCR0=\$352! \ Capture/compare register 0 -TA0CCR1=\$354! \ Capture/compare register 1 -TA0CCR2=\$356! \ Capture/compare register 2 -TA0EX0=\$360! \ TA0 expansion register 0 -TA0IV=\$36E! \ TA0 interrupt vector - -TA1CTL=\$380! \ TA1 control -TA1CCTL0=\$382! \ Capture/compare control 0 -TA1CCTL1=\$384! \ Capture/compare control 1 -TA1CCTL2=\$386! \ Capture/compare control 2 -TA1R=\$390! \ TA1 counter register -TA1CCR0=\$392! \ Capture/compare register 0 -TA1CCR1=\$394! \ Capture/compare register 1 -TA1CCR2=\$396! \ Capture/compare register 2 -TA1EX0=\$3A0! \ TA1 expansion register 0 -TA1IV=\$3AE! \ TA1 interrupt vector - -TB0CTL=\$3C0! \ TB0 control -TB0CCTL0=\$3C2! \ Capture/compare control 0 -TB0CCTL1=\$3C4! \ Capture/compare control 1 -TB0CCTL2=\$3C6! \ Capture/compare control 2 -TB0CCTL3=\$3C8! \ Capture/compare control 3 -TB0CCTL4=\$3CA! \ Capture/compare control 4 -TB0CCTL5=\$3CC! \ Capture/compare control 5 -TB0CCTL6=\$3CE! \ Capture/compare control 6 -TB0R=\$3D0! \ TB0 counter register -TB0CCR0=\$3D2! \ Capture/compare register 0 -TB0CCR1=\$3D4! \ Capture/compare register 1 -TB0CCR2=\$3D6! \ Capture/compare register 2 -TB0CCR3=\$3D8! \ Capture/compare register 3 -TB0CCR5=\$3DA! \ Capture/compare register 4 -TB0CCR5=\$3DC! \ Capture/compare register 5 -TB0CCR6=\$3DE! \ Capture/compare register 6 -TB0EX0=\$3E0! \ TB0 expansion register 0 -TB0IV=\$3EE! \ TB0 interrupt vector - -TA2CTL=\$400! \ TA2 control -TA2CCTL0=\$402! \ Capture/compare control 0 -TA2CCTL1=\$404! \ Capture/compare control 1 -TA2R=\$410! \ TA2 counter register -TA2CCR0=\$412! \ Capture/compare register 0 -TA2CCR1=\$414! \ Capture/compare register 1 -TA2EX0=\$420! \ TA2 expansion register 0 -TA2IV=\$42E! \ TA2 interrupt vector - -TA3CTL=\$440! \ TA3 control -TA3CCTL0=\$442! \ Capture/compare control 0 -TA3CCTL1=\$444! \ Capture/compare control 1 -TA3R=\$450! \ TA3 counter register -TA3CCR0=\$452! \ Capture/compare register 0 -TA3CCR1=\$454! \ Capture/compare register 1 -TA3EX0=\$460! \ TA3 expansion register 0 -TA3IV=\$46E! \ TA3 interrupt vector +TA0CTL=\$340! \ TA0 control +TA0CCTL0=\$342! \ Capture/compare control 0 +TA0CCTL1=\$344! \ Capture/compare control 1 +TA0CCTL2=\$346! \ Capture/compare control 2 +TA0R=\$350! \ TA0 counter register +TA0CCR0=\$352! \ Capture/compare register 0 +TA0CCR1=\$354! \ Capture/compare register 1 +TA0CCR2=\$356! \ Capture/compare register 2 +TA0EX0=\$360! \ TA0 expansion register 0 +TA0IV=\$36E! \ TA0 interrupt vector + +TA1CTL=\$380! \ TA1 control +TA1CCTL0=\$382! \ Capture/compare control 0 +TA1CCTL1=\$384! \ Capture/compare control 1 +TA1CCTL2=\$386! \ Capture/compare control 2 +TA1R=\$390! \ TA1 counter register +TA1CCR0=\$392! \ Capture/compare register 0 +TA1CCR1=\$394! \ Capture/compare register 1 +TA1CCR2=\$396! \ Capture/compare register 2 +TA1EX0=\$3A0! \ TA1 expansion register 0 +TA1IV=\$3AE! \ TA1 interrupt vector + +TB0CTL=\$3C0! \ TB0 control +TB0CCTL0=\$3C2! \ Capture/compare control 0 +TB0CCTL1=\$3C4! \ Capture/compare control 1 +TB0CCTL2=\$3C6! \ Capture/compare control 2 +TB0CCTL3=\$3C8! \ Capture/compare control 3 +TB0CCTL4=\$3CA! \ Capture/compare control 4 +TB0CCTL5=\$3CC! \ Capture/compare control 5 +TB0CCTL6=\$3CE! \ Capture/compare control 6 +TB0R=\$3D0! \ TB0 counter register +TB0CCR0=\$3D2! \ Capture/compare register 0 +TB0CCR1=\$3D4! \ Capture/compare register 1 +TB0CCR2=\$3D6! \ Capture/compare register 2 +TB0CCR3=\$3D8! \ Capture/compare register 3 +TB0CCR5=\$3DA! \ Capture/compare register 4 +TB0CCR5=\$3DC! \ Capture/compare register 5 +TB0CCR6=\$3DE! \ Capture/compare register 6 +TB0EX0=\$3E0! \ TB0 expansion register 0 +TB0IV=\$3EE! \ TB0 interrupt vector + +TA2CTL=\$400! \ TA2 control +TA2CCTL0=\$402! \ Capture/compare control 0 +TA2CCTL1=\$404! \ Capture/compare control 1 +TA2R=\$410! \ TA2 counter register +TA2CCR0=\$412! \ Capture/compare register 0 +TA2CCR1=\$414! \ Capture/compare register 1 +TA2EX0=\$420! \ TA2 expansion register 0 +TA2IV=\$42E! \ TA2 interrupt vector + +TA3CTL=\$440! \ TA3 control +TA3CCTL0=\$442! \ Capture/compare control 0 +TA3CCTL1=\$444! \ Capture/compare control 1 +TA3R=\$450! \ TA3 counter register +TA3CCR0=\$452! \ Capture/compare register 0 +TA3CCR1=\$454! \ Capture/compare register 1 +TA3EX0=\$460! \ TA3 expansion register 0 +TA3IV=\$46E! \ TA3 interrupt vector ! \ RTC_B -RTCCTL0=\$4A0! \ RTC control 0 -RTCCTL1=\$4A1! \ RTC control 1 -RTCCTL2=\$4A2! \ RTC control 2 -RTCCTL3=\$4A3! \ RTC control 3 -RTCPS0CTL=\$4A8! \ RTC prescaler 0 control -RTCPS1CTL=\$4AA! \ RTC prescaler 1 control -RTCPS0=\$4AC! \ RTC prescaler 0 -RTCPS1=\$4AD! \ RTC prescaler 1 -RTCIV=\$4AE! \ RTC interrupt vector word -RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, -RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, -RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, -RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, -RTCDAY=\$4B4! \ RTC days -RTCMON=\$4B5! \ RTC month -RTCYEAR=\$4B6! -RTCYEARL=\$4B6! \ RTC year low -RTCYEARH=\$4B7! \ RTC year high -RTCAMIN=\$4B8! \ RTC alarm minutes -RTCAHOUR=\$4B9! \ RTC alarm hours -RTCADOW=\$4BA! \ RTC alarm day of week -RTCADAY=\$4BB! \ RTC alarm days -BIN2BCD=\$4BC! \ Binary-to-BCD conversion register -BCD2BIN=\$4BE! \ BCD-to-binary conversion register +RTCCTL0=\$4A0! \ RTC control 0 +RTCCTL1=\$4A1! \ RTC control 1 +RTCCTL2=\$4A2! \ RTC control 2 +RTCCTL3=\$4A3! \ RTC control 3 +RTCPS0CTL=\$4A8! \ RTC prescaler 0 control +RTCPS1CTL=\$4AA! \ RTC prescaler 1 control +RTCPS0=\$4AC! \ RTC prescaler 0 +RTCPS1=\$4AD! \ RTC prescaler 1 +RTCIV=\$4AE! \ RTC interrupt vector word +RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, +RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, +RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, +RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, +RTCDAY=\$4B4! \ RTC days +RTCMON=\$4B5! \ RTC month +RTCYEAR=\$4B6! +RTCYEARL=\$4B6! \ RTC year low +RTCYEARH=\$4B7! \ RTC year high +RTCAMIN=\$4B8! \ RTC alarm minutes +RTCAHOUR=\$4B9! \ RTC alarm hours +RTCADOW=\$4BA! \ RTC alarm day of week +RTCADAY=\$4BB! \ RTC alarm days +BIN2BCD=\$4BC! \ Binary-to-BCD conversion register +BCD2BIN=\$4BE! \ BCD-to-binary conversion register RTCHOLD=\$40! RTCRDY=\$10! @@ -580,178 +607,178 @@ MPY32CTL0=\$4EC! \ MPY32 control register 0 DMAIFG=8! -DMACTL0=\$500! \ DMA module control 0 -DMACTL1=\$502! \ DMA module control 1 -DMACTL2=\$504! \ DMA module control 2 -DMACTL3=\$506! \ DMA module control 3 -DMACTL4=\$508! \ DMA module control 4 -DMAIV=\$50A! \ DMA interrupt vector - -DMA0CTL=\$510! \ DMA channel 0 control -DMA0SAL=\$512! \ DMA channel 0 source address low -DMA0SAH=\$514! \ DMA channel 0 source address high -DMA0DAL=\$516! \ DMA channel 0 destination address low -DMA0DAH=\$518! \ DMA channel 0 destination address high -DMA0SZ=\$51A! \ DMA channel 0 transfer size - -DMA1CTL=\$520! \ DMA channel 1 control -DMA1SAL=\$522! \ DMA channel 1 source address low -DMA1SAH=\$524! \ DMA channel 1 source address high -DMA1DAL=\$526! \ DMA channel 1 destination address low -DMA1DAH=\$528! \ DMA channel 1 destination address high -DMA1SZ=\$52A! \ DMA channel 1 transfer size - -DMA2CTL=\$530! \ DMA channel 2 control -DMA2SAL=\$532! \ DMA channel 2 source address low -DMA2SAH=\$534! \ DMA channel 2 source address high -DMA2DAL=\$536! \ DMA channel 2 destination address low -DMA2DAH=\$538! \ DMA channel 2 destination address high -DMA2SZ=\$53A! \ DMA channel 2 transfer size - - -MPUCTL0=\$5A0! \ MPU control 0 -MPUCTL1=\$5A2! \ MPU control 1 -MPUSEGB2=\$5A4! \ MPU Segmentation Border2 -MPUSEGB1=\$5A6! \ MPU Segmentation Border1 -MPUSAM=\$5A8! \ MPU access management -MPUIPC0=\$5AA! \ MPU IP control 0 -MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 -MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 - -UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 -UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 -UCA0BRW=\$5C6! -UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 -UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$5C8! \ eUSCI_A modulation control -UCA0STAT=\$5CA! \ eUSCI_A status -UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer -UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer -UCA0ABCTL=\$5D0! \ eUSCI_A LIN control -UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control -UCA0IE=\$5DA! \ eUSCI_A interrupt enable -UCA0IFG=\$5DC! \ eUSCI_A interrupt flags -UCA0IV=\$5DE! \ eUSCI_A interrupt vector word - -UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 -UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 -UCA1BRW=\$5E6! -UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 -UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 -UCA1MCTLW=\$5E8! \ eUSCI_A modulation control -UCA1STAT=\$5EA! \ eUSCI_A status -UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer -UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer -UCA1ABCTL=\$5F0! \ eUSCI_A LIN control -UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control -UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control -UCA1IE=\$5FA! \ eUSCI_A interrupt enable -UCA1IFG=\$5FC! \ eUSCI_A interrupt flags -UCA1IV=\$5FE! \ eUSCI_A interrupt vector word - -UCB0CTLW0=\$640! \ eUSCI_B control word 0 -UCB0CTLW1=\$642! \ eUSCI_B control word 1 -UCB0BRW=\$646! -UCB0BR0=\$646! \ eUSCI_B bit rate 0 -UCB0BR1=\$647! \ eUSCI_B bit rate 1 -UCB0STATW=\$648! \ eUSCI_B status word -UCBCNT0=\$649! \ eUSCI_B hardware count -UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$64C! \ eUSCI_B receive buffer -UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$65C! \ eUSCI_B received address -UCB0ADDMASK=\$65E! \ eUSCI_B address mask -UCB0I2CSA=\$660! \ eUSCI I2C slave address -UCB0IE=\$66A! \ eUSCI interrupt enable -UCB0IFG=\$66C! \ eUSCI interrupt flags -UCB0IV=\$66E! \ eUSCI interrupt vector word +DMACTL0=\$500! \ DMA module control 0 +DMACTL1=\$502! \ DMA module control 1 +DMACTL2=\$504! \ DMA module control 2 +DMACTL3=\$506! \ DMA module control 3 +DMACTL4=\$508! \ DMA module control 4 +DMAIV=\$50A! \ DMA interrupt vector + +DMA0CTL=\$510! \ DMA channel 0 control +DMA0SAL=\$512! \ DMA channel 0 source address low +DMA0SAH=\$514! \ DMA channel 0 source address high +DMA0DAL=\$516! \ DMA channel 0 destination address low +DMA0DAH=\$518! \ DMA channel 0 destination address high +DMA0SZ=\$51A! \ DMA channel 0 transfer size + +DMA1CTL=\$520! \ DMA channel 1 control +DMA1SAL=\$522! \ DMA channel 1 source address low +DMA1SAH=\$524! \ DMA channel 1 source address high +DMA1DAL=\$526! \ DMA channel 1 destination address low +DMA1DAH=\$528! \ DMA channel 1 destination address high +DMA1SZ=\$52A! \ DMA channel 1 transfer size + +DMA2CTL=\$530! \ DMA channel 2 control +DMA2SAL=\$532! \ DMA channel 2 source address low +DMA2SAH=\$534! \ DMA channel 2 source address high +DMA2DAL=\$536! \ DMA channel 2 destination address low +DMA2DAH=\$538! \ DMA channel 2 destination address high +DMA2SZ=\$53A! \ DMA channel 2 transfer size + + +MPUCTL0=\$5A0! \ MPU control 0 +MPUCTL1=\$5A2! \ MPU control 1 +MPUSEGB2=\$5A4! \ MPU Segmentation Border2 +MPUSEGB1=\$5A6! \ MPU Segmentation Border1 +MPUSAM=\$5A8! \ MPU access management +MPUIPC0=\$5AA! \ MPU IP control 0 +MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 +MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 + +UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 +UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 +UCA0BRW=\$5C6! +UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 +UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$5C8! \ eUSCI_A modulation control +UCA0STAT=\$5CA! \ eUSCI_A status +UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer +UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer +UCA0ABCTL=\$5D0! \ eUSCI_A LIN control +UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control +UCA0IE=\$5DA! \ eUSCI_A interrupt enable +UCA0IFG=\$5DC! \ eUSCI_A interrupt flags +UCA0IV=\$5DE! \ eUSCI_A interrupt vector word + +UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 +UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 +UCA1BRW=\$5E6! +UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 +UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 +UCA1MCTLW=\$5E8! \ eUSCI_A modulation control +UCA1STAT=\$5EA! \ eUSCI_A status +UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer +UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer +UCA1ABCTL=\$5F0! \ eUSCI_A LIN control +UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control +UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control +UCA1IE=\$5FA! \ eUSCI_A interrupt enable +UCA1IFG=\$5FC! \ eUSCI_A interrupt flags +UCA1IV=\$5FE! \ eUSCI_A interrupt vector word + +UCB0CTLW0=\$640! \ eUSCI_B control word 0 +UCB0CTLW1=\$642! \ eUSCI_B control word 1 +UCB0BRW=\$646! +UCB0BR0=\$646! \ eUSCI_B bit rate 0 +UCB0BR1=\$647! \ eUSCI_B bit rate 1 +UCB0STATW=\$648! \ eUSCI_B status word +UCBCNT0=\$649! \ eUSCI_B hardware count +UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$64C! \ eUSCI_B receive buffer +UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$65C! \ eUSCI_B received address +UCB0ADDMASK=\$65E! \ eUSCI_B address mask +UCB0I2CSA=\$660! \ eUSCI I2C slave address +UCB0IE=\$66A! \ eUSCI interrupt enable +UCB0IFG=\$66C! \ eUSCI interrupt flags +UCB0IV=\$66E! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -ADC12CTL0=\$800! \ ADC12_B Control 0 -ADC12CTL1=\$802! \ ADC12_B Control 1 -ADC12CTL2=\$804! \ ADC12_B Control 2 -ADC12CTL3=\$806! \ ADC12_B Control 3 -ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register -ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register -ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0 -ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1 -ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2 -ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0 -ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1 -ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2 -ADC12IV=\$818! \ ADC12_B Interrupt Vector -ADC12MCTL0=\$820! \ ADC12_B Memory Control 0 -ADC12MCTL1=\$822! \ ADC12_B Memory Control 1 -ADC12MCTL2=\$824! \ ADC12_B Memory Control 2 -ADC12MCTL3=\$826! \ ADC12_B Memory Control 3 -ADC12MCTL4=\$828! \ ADC12_B Memory Control 4 -ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5 -ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6 -ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7 -ADC12MCTL8=\$830! \ ADC12_B Memory Control 8 -ADC12MCTL9=\$832! \ ADC12_B Memory Control 9 -ADC12MCTL10=\$834! \ ADC12_B Memory Control 10 -ADC12MCTL11=\$836! \ ADC12_B Memory Control 11 -ADC12MCTL12=\$838! \ ADC12_B Memory Control 12 -ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13 -ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14 -ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15 -ADC12MCTL16=\$840! \ ADC12_B Memory Control 16 -ADC12MCTL17=\$842! \ ADC12_B Memory Control 17 -ADC12MCTL18=\$844! \ ADC12_B Memory Control 18 -ADC12MCTL19=\$846! \ ADC12_B Memory Control 19 -ADC12MCTL20=\$848! \ ADC12_B Memory Control 20 -ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21 -ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22 -ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23 -ADC12MCTL24=\$850! \ ADC12_B Memory Control 24 -ADC12MCTL25=\$852! \ ADC12_B Memory Control 25 -ADC12MCTL26=\$854! \ ADC12_B Memory Control 26 -ADC12MCTL27=\$856! \ ADC12_B Memory Control 27 -ADC12MCTL28=\$858! \ ADC12_B Memory Control 28 -ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29 -ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30 -ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31 -ADC12MEM0=\$860! \ ADC12_B Memory 0 -ADC12MEM1=\$862! \ ADC12_B Memory 1 -ADC12MEM2=\$864! \ ADC12_B Memory 2 -ADC12MEM3=\$866! \ ADC12_B Memory 3 -ADC12MEM4=\$868! \ ADC12_B Memory 4 -ADC12MEM5=\$86A! \ ADC12_B Memory 5 -ADC12MEM6=\$86C! \ ADC12_B Memory 6 -ADC12MEM7=\$86E! \ ADC12_B Memory 7 -ADC12MEM8=\$870! \ ADC12_B Memory 8 -ADC12MEM9=\$872! \ ADC12_B Memory 9 -ADC12MEM10=\$874! \ ADC12_B Memory 10 -ADC12MEM11=\$876! \ ADC12_B Memory 11 -ADC12MEM12=\$878! \ ADC12_B Memory 12 -ADC12MEM13=\$87A! \ ADC12_B Memory 13 -ADC12MEM14=\$87C! \ ADC12_B Memory 14 -ADC12MEM15=\$87E! \ ADC12_B Memory 15 -ADC12MEM16=\$880! \ ADC12_B Memory 16 -ADC12MEM17=\$882! \ ADC12_B Memory 17 -ADC12MEM18=\$884! \ ADC12_B Memory 18 -ADC12MEM19=\$886! \ ADC12_B Memory 19 -ADC12MEM20=\$888! \ ADC12_B Memory 20 -ADC12MEM21=\$88A! \ ADC12_B Memory 21 -ADC12MEM22=\$88C! \ ADC12_B Memory 22 -ADC12MEM23=\$88E! \ ADC12_B Memory 23 -ADC12MEM24=\$890! \ ADC12_B Memory 24 -ADC12MEM25=\$892! \ ADC12_B Memory 25 -ADC12MEM26=\$894! \ ADC12_B Memory 26 -ADC12MEM27=\$896! \ ADC12_B Memory 27 -ADC12MEM28=\$898! \ ADC12_B Memory 28 -ADC12MEM29=\$89A! \ ADC12_B Memory 29 -ADC12MEM30=\$89C! \ ADC12_B Memory 30 -ADC12MEM31=\$89E! \ ADC12_B Memory 31 +ADC12CTL0=\$800! \ ADC12_B Control 0 +ADC12CTL1=\$802! \ ADC12_B Control 1 +ADC12CTL2=\$804! \ ADC12_B Control 2 +ADC12CTL3=\$806! \ ADC12_B Control 3 +ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register +ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register +ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0 +ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1 +ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2 +ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0 +ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1 +ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2 +ADC12IV=\$818! \ ADC12_B Interrupt Vector +ADC12MCTL0=\$820! \ ADC12_B Memory Control 0 +ADC12MCTL1=\$822! \ ADC12_B Memory Control 1 +ADC12MCTL2=\$824! \ ADC12_B Memory Control 2 +ADC12MCTL3=\$826! \ ADC12_B Memory Control 3 +ADC12MCTL4=\$828! \ ADC12_B Memory Control 4 +ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5 +ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6 +ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7 +ADC12MCTL8=\$830! \ ADC12_B Memory Control 8 +ADC12MCTL9=\$832! \ ADC12_B Memory Control 9 +ADC12MCTL10=\$834! \ ADC12_B Memory Control 10 +ADC12MCTL11=\$836! \ ADC12_B Memory Control 11 +ADC12MCTL12=\$838! \ ADC12_B Memory Control 12 +ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13 +ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14 +ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15 +ADC12MCTL16=\$840! \ ADC12_B Memory Control 16 +ADC12MCTL17=\$842! \ ADC12_B Memory Control 17 +ADC12MCTL18=\$844! \ ADC12_B Memory Control 18 +ADC12MCTL19=\$846! \ ADC12_B Memory Control 19 +ADC12MCTL20=\$848! \ ADC12_B Memory Control 20 +ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21 +ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22 +ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23 +ADC12MCTL24=\$850! \ ADC12_B Memory Control 24 +ADC12MCTL25=\$852! \ ADC12_B Memory Control 25 +ADC12MCTL26=\$854! \ ADC12_B Memory Control 26 +ADC12MCTL27=\$856! \ ADC12_B Memory Control 27 +ADC12MCTL28=\$858! \ ADC12_B Memory Control 28 +ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29 +ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30 +ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31 +ADC12MEM0=\$860! \ ADC12_B Memory 0 +ADC12MEM1=\$862! \ ADC12_B Memory 1 +ADC12MEM2=\$864! \ ADC12_B Memory 2 +ADC12MEM3=\$866! \ ADC12_B Memory 3 +ADC12MEM4=\$868! \ ADC12_B Memory 4 +ADC12MEM5=\$86A! \ ADC12_B Memory 5 +ADC12MEM6=\$86C! \ ADC12_B Memory 6 +ADC12MEM7=\$86E! \ ADC12_B Memory 7 +ADC12MEM8=\$870! \ ADC12_B Memory 8 +ADC12MEM9=\$872! \ ADC12_B Memory 9 +ADC12MEM10=\$874! \ ADC12_B Memory 10 +ADC12MEM11=\$876! \ ADC12_B Memory 11 +ADC12MEM12=\$878! \ ADC12_B Memory 12 +ADC12MEM13=\$87A! \ ADC12_B Memory 13 +ADC12MEM14=\$87C! \ ADC12_B Memory 14 +ADC12MEM15=\$87E! \ ADC12_B Memory 15 +ADC12MEM16=\$880! \ ADC12_B Memory 16 +ADC12MEM17=\$882! \ ADC12_B Memory 17 +ADC12MEM18=\$884! \ ADC12_B Memory 18 +ADC12MEM19=\$886! \ ADC12_B Memory 19 +ADC12MEM20=\$888! \ ADC12_B Memory 20 +ADC12MEM21=\$88A! \ ADC12_B Memory 21 +ADC12MEM22=\$88C! \ ADC12_B Memory 22 +ADC12MEM23=\$88E! \ ADC12_B Memory 23 +ADC12MEM24=\$890! \ ADC12_B Memory 24 +ADC12MEM25=\$892! \ ADC12_B Memory 25 +ADC12MEM26=\$894! \ ADC12_B Memory 26 +ADC12MEM27=\$896! \ ADC12_B Memory 27 +ADC12MEM28=\$898! \ ADC12_B Memory 28 +ADC12MEM29=\$89A! \ ADC12_B Memory 29 +ADC12MEM30=\$89C! \ ADC12_B Memory 30 +ADC12MEM31=\$89E! \ ADC12_B Memory 31 ADCON=\$10! ADCSTART=\$03! @@ -759,19 +786,19 @@ ADCSTART=\$03! CDIFG=1! CDIIFG=2! -CDCTL0=\$8C0! \ Comparator_E control register 0 -CDCTL1=\$8C2! \ Comparator_E control register 1 -CDCTL2=\$8C4! \ Comparator_E control register 2 -CDCTL3=\$8C6! \ Comparator_E control register 3 -CDINT=\$8CC! \ Comparator_E interrupt register -CDIV=\$8CE! \ Comparator_E interrupt vector word - - -AESACTL0=\$9C0! \ AES accelerator control register 0 -AESASTAT=\$9C4! \ AES accelerator status register -AESAKEY=\$9C6! \ AES accelerator key register -AESADIN=\$9C8! \ AES accelerator data in register -AESADOUT=\$9CA! \ AES accelerator data out register -AESAXDIN=\$9CC! \ AES accelerator XORed data in register -AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger) +CDCTL0=\$8C0! \ Comparator_E control register 0 +CDCTL1=\$8C2! \ Comparator_E control register 1 +CDCTL2=\$8C4! \ Comparator_E control register 2 +CDCTL3=\$8C6! \ Comparator_E control register 3 +CDINT=\$8CC! \ Comparator_E interrupt register +CDIV=\$8CE! \ Comparator_E interrupt vector word + + +AESACTL0=\$9C0! \ AES accelerator control register 0 +AESASTAT=\$9C4! \ AES accelerator status register +AESAKEY=\$9C6! \ AES accelerator key register +AESADIN=\$9C8! \ AES accelerator data in register +AESADOUT=\$9CA! \ AES accelerator data out register +AESAXDIN=\$9CC! \ AES accelerator XORed data in register +AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger) diff --git a/inc/MSP430FR5969.inc b/inc/MSP430FR5969.inc index fed66a4..1b7f55b 100644 --- a/inc/MSP430FR5969.inc +++ b/inc/MSP430FR5969.inc @@ -26,7 +26,7 @@ DEVICE = "MSP430FR5969" ; ---------------------------------------------- PAGESIZE .equ 512 ; MPU unit ; ---------------------------------------------- -; BSL +; BSL ; ---------------------------------------------- BSL .equ 1000h ; ---------------------------------------------- @@ -65,7 +65,7 @@ BSL_SIG2 .equ 0FF86h ; JTAG_PASSWORD .equ 0FF88h ; 256 bits max IPE_SIG_VALID .equ 0FF88h ; one word IPE_STR_PTR_SRC .equ 0FF8Ah ; one word -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -267,7 +267,7 @@ P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P2IN .equ PA_SFR + 01h ; Port 2 INput P2OUT .equ PA_SFR + 03h ; Port 2 OUTput @@ -279,7 +279,7 @@ P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3/4 @@ -306,7 +306,7 @@ P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag -P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word +P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word P4IN .equ PB_SFR + 01h ; Port 4 Input */ P4OUT .equ PB_SFR + 03h ; Port 4 Output @@ -318,7 +318,7 @@ P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag -P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word +P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORTJ @@ -383,14 +383,14 @@ RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */ MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0 -MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 -MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 -MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2 -MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1 -MPUSAM .equ MPU_SFR + 08h ; MPU access management -MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0 -MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2 -MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1 +MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 +MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 +MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2 +MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1 +MPUSAM .equ MPU_SFR + 08h ; MPU access management +MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0 +MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2 +MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1 .IFDEF UCA0_TERM @@ -437,7 +437,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR5969.pat b/inc/MSP430FR5969.pat index 4934d55..d51c85f 100644 --- a/inc/MSP430FR5969.pat +++ b/inc/MSP430FR5969.pat @@ -31,42 +31,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -87,55 +112,49 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! --------------------------------------- ! FastForth RAM memory map (>= 1k) ! --------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ base address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ADR=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO - +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!1DE0! 28 RAM bytes free +!1DE0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -147,7 +166,7 @@ SD_BUF=\$1E00! \ SD_Card buffer BUFEND=\$2000! ! --------------------------------------- -! FAT16 FileSystemInfos +! FAT16 FileSystemInfos ! --------------------------------------- FATtype=\$2002! BS_FirstSectorL=\$2004! @@ -175,7 +194,7 @@ SectorH=\$201C! ! --------------------------------------- ! BUFFER management ! --------------------------------------- -BufferPtr=\$201E! +BufferPtr=\$201E! BufferLen=\$2020! ! --------------------------------------- @@ -183,16 +202,16 @@ BufferLen=\$2020! ! --------------------------------------- ClusterL=\$2022! 16 bits wide (FAT16) ClusterH=\$2024! 16 bits wide (FAT16) -NewClusterL=\$2026! 16 bits wide (FAT16) -NewClusterH=\$2028! 16 bits wide (FAT16) -CurFATsector=\$202A! +NewClusterL=\$2026! 16 bits wide (FAT16) +NewClusterH=\$2028! 16 bits wide (FAT16) +CurFATsector=\$202A! ! --------------------------------------- ! DIR entry ! --------------------------------------- DIRclusterL=\$202C! contains the Cluster of current directory ; 1 if FAT16 root directory DIRclusterH=\$202E! contains the Cluster of current directory ; 1 if FAT16 root directory -EntryOfst=\$2030! +EntryOfst=\$2030! ! --------------------------------------- ! Handle Pointer @@ -208,7 +227,7 @@ EndOfPath=\$2036! ! --------------------------------------- ! Handle structure ! --------------------------------------- -! three handle tokens : +! three handle tokens : ! token = 0 : free handle ! token = 1 : file to read ! token = 2 : file updated (write) @@ -232,7 +251,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2038! @@ -256,52 +275,60 @@ MAIN_LEN=\$BC00! 47 k FRAM SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$440A! CODE compiled by LITERAL -XSQUOTE=\$4414! CODE compiled by S" and S_ -HEREXEC=\$4428! CODE HERE and BEGIN execute address -QFBRAN=\$4434! CODE compiled by IF UNTIL -BRAN=\$443A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$443C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$443E! CODE compiled by DO -XPLOOP=\$444E! CODE compiled by +LOOP -XLOOP=\$4460! CODE compiled by LOOP -MUSMOD=\$4466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$4478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$4480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$44AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$44AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$44BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$44CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$44D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$44E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$44EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$441E! CODE compiled by S" and S_ +HEREXEC=\$4432! CODE HERE and BEGIN execute address +MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$4494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$44AC! CODE compiled by IF UNTIL +BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$44F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$452A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$4536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$4594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$459C! ASM CODE, content of WARM+2 by default -UART_RXON=\$45C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$45C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$45B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$458E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$45BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$45BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$4584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$4586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$4544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$4556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$4556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$4558! asm CODE, content of WARM+2 by default +I2C_WARM=\$4580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR5969 ! ---------------------------------------------- MAIN_LEN=\$FC00! 63k FRAM -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD -BSL_SIG1=\$FF84! -BSL_SIG2=\$FF86! +BSL_SIG1=\$FF84! +BSL_SIG2=\$FF86! I2CSLA0=\$FFA2! UCBxI2COA0 default value address I2CSLA1=\$FFA4! UCBxI2COA1 default value address I2CSLA2=\$FFA6! UCBxI2COA2 default value address @@ -348,39 +375,39 @@ SFRIFG1=\$102! \ SFR flag register SFRRPCR=\$104! \ SFR reset pin control PMMCTL0=\$120! \ PMM Control 0 -PMMIFG=\$12A! \ PMM interrupt flags +PMMIFG=\$12A! \ PMM interrupt flags PM5CTL0=\$130! \ PM5 Control 0 -FRCTLCTL0=\$140! \ FRAM control 0 -GCCTL0=\$144! \ General control 0 -GCCTL1=\$146! \ General control 1 +FRCTLCTL0=\$140! \ FRAM control 0 +GCCTL0=\$144! \ General control 0 +GCCTL1=\$146! \ General control 1 -CRC16DI=\$150! \ CRC data input -CRCDIRB=\$152! \ CRC data input reverse byte -CRCINIRES=\$154! \ CRC initialization and result -CRCRESR=\$156! \ CRC result reverse byte +CRC16DI=\$150! \ CRC data input +CRCDIRB=\$152! \ CRC data input reverse byte +CRCINIRES=\$154! \ CRC initialization and result +CRCRESR=\$156! \ CRC result reverse byte WDTCTL=\$15C! \ WDT control register -CSCTL0=\$160! \ CS control 0 -CSCTL1=\$162! \ CS control 1 -CSCTL2=\$164! \ CS control 2 -CSCTL3=\$166! \ CS control 3 -CSCTL4=\$168! \ CS control 4 -CSCTL5=\$16A! \ CS control 5 -CSCTL6=\$16C! \ CS control 6 - -SYSCTL=\$180! \ System control -SYSJMBC=\$186! \ JTAG mailbox control -SYSJMBI0=\$188! \ JTAG mailbox input 0 -SYSJMBI1=\$18A! \ JTAG mailbox input 1 -SYSJMBO0=\$18C! \ JTAG mailbox output 0 -SYSJMBO1=\$18E! \ JTAG mailbox output 1 -SYSUNIV=\$19A! \ User NMI vector generator -SYSSNIV=\$19C! \ System NMI vector generator -SYSRSTIV=\$19E! \ Reset vector generator - -REFCTL=\$1B0! \ Shared reference control +CSCTL0=\$160! \ CS control 0 +CSCTL1=\$162! \ CS control 1 +CSCTL2=\$164! \ CS control 2 +CSCTL3=\$166! \ CS control 3 +CSCTL4=\$168! \ CS control 4 +CSCTL5=\$16A! \ CS control 5 +CSCTL6=\$16C! \ CS control 6 + +SYSCTL=\$180! \ System control +SYSJMBC=\$186! \ JTAG mailbox control +SYSJMBI0=\$188! \ JTAG mailbox input 0 +SYSJMBI1=\$18A! \ JTAG mailbox input 1 +SYSJMBO0=\$18C! \ JTAG mailbox output 0 +SYSJMBO1=\$18E! \ JTAG mailbox output 1 +SYSUNIV=\$19A! \ User NMI vector generator +SYSSNIV=\$19C! \ System NMI vector generator +SYSRSTIV=\$19E! \ Reset vector generator + +REFCTL=\$1B0! \ Shared reference control PAIN=\$200! PAOUT=\$202! @@ -467,90 +494,90 @@ TBCLR=2! TBIFG=1! CCIFG=1! -TA0CTL=\$340! \ TA0 control -TA0CCTL0=\$342! \ Capture/compare control 0 -TA0CCTL1=\$344! \ Capture/compare control 1 -TA0CCTL2=\$346! \ Capture/compare control 2 -TA0R=\$350! \ TA0 counter register -TA0CCR0=\$352! \ Capture/compare register 0 -TA0CCR1=\$354! \ Capture/compare register 1 -TA0CCR2=\$356! \ Capture/compare register 2 -TA0EX0=\$360! \ TA0 expansion register 0 -TA0IV=\$36E! \ TA0 interrupt vector - -TA1CTL=\$380! \ TA1 control -TA1CCTL0=\$382! \ Capture/compare control 0 -TA1CCTL1=\$384! \ Capture/compare control 1 -TA1CCTL2=\$386! \ Capture/compare control 2 -TA1R=\$390! \ TA1 counter register -TA1CCR0=\$392! \ Capture/compare register 0 -TA1CCR1=\$394! \ Capture/compare register 1 -TA1CCR2=\$396! \ Capture/compare register 2 -TA1EX0=\$3A0! \ TA1 expansion register 0 -TA1IV=\$3AE! \ TA1 interrupt vector - -TB0CTL=\$3C0! \ TB0 control -TB0CCTL0=\$3C2! \ Capture/compare control 0 -TB0CCTL1=\$3C4! \ Capture/compare control 1 -TB0CCTL2=\$3C6! \ Capture/compare control 2 -TB0CCTL3=\$3C8! \ Capture/compare control 3 -TB0CCTL4=\$3CA! \ Capture/compare control 4 -TB0CCTL5=\$3CC! \ Capture/compare control 5 -TB0CCTL6=\$3CE! \ Capture/compare control 6 -TB0R=\$3D0! \ TB0 counter register -TB0CCR0=\$3D2! \ Capture/compare register 0 -TB0CCR1=\$3D4! \ Capture/compare register 1 -TB0CCR2=\$3D6! \ Capture/compare register 2 -TB0CCR3=\$3D8! \ Capture/compare register 3 -TB0CCR5=\$3DA! \ Capture/compare register 4 -TB0CCR5=\$3DC! \ Capture/compare register 5 -TB0CCR6=\$3DE! \ Capture/compare register 6 -TB0EX0=\$3E0! \ TB0 expansion register 0 -TB0IV=\$3EE! \ TB0 interrupt vector - -TA2CTL=\$400! \ TA2 control -TA2CCTL0=\$402! \ Capture/compare control 0 -TA2CCTL1=\$404! \ Capture/compare control 1 -TA2R=\$410! \ TA2 counter register -TA2CCR0=\$412! \ Capture/compare register 0 -TA2CCR1=\$414! \ Capture/compare register 1 -TA2EX0=\$420! \ TA2 expansion register 0 -TA2IV=\$42E! \ TA2 interrupt vector - -TA3CTL=\$440! \ TA3 control -TA3CCTL0=\$442! \ Capture/compare control 0 -TA3CCTL1=\$444! \ Capture/compare control 1 -TA3R=\$450! \ TA3 counter register -TA3CCR0=\$452! \ Capture/compare register 0 -TA3CCR1=\$454! \ Capture/compare register 1 -TA3EX0=\$460! \ TA3 expansion register 0 -TA3IV=\$46E! \ TA3 interrupt vector +TA0CTL=\$340! \ TA0 control +TA0CCTL0=\$342! \ Capture/compare control 0 +TA0CCTL1=\$344! \ Capture/compare control 1 +TA0CCTL2=\$346! \ Capture/compare control 2 +TA0R=\$350! \ TA0 counter register +TA0CCR0=\$352! \ Capture/compare register 0 +TA0CCR1=\$354! \ Capture/compare register 1 +TA0CCR2=\$356! \ Capture/compare register 2 +TA0EX0=\$360! \ TA0 expansion register 0 +TA0IV=\$36E! \ TA0 interrupt vector + +TA1CTL=\$380! \ TA1 control +TA1CCTL0=\$382! \ Capture/compare control 0 +TA1CCTL1=\$384! \ Capture/compare control 1 +TA1CCTL2=\$386! \ Capture/compare control 2 +TA1R=\$390! \ TA1 counter register +TA1CCR0=\$392! \ Capture/compare register 0 +TA1CCR1=\$394! \ Capture/compare register 1 +TA1CCR2=\$396! \ Capture/compare register 2 +TA1EX0=\$3A0! \ TA1 expansion register 0 +TA1IV=\$3AE! \ TA1 interrupt vector + +TB0CTL=\$3C0! \ TB0 control +TB0CCTL0=\$3C2! \ Capture/compare control 0 +TB0CCTL1=\$3C4! \ Capture/compare control 1 +TB0CCTL2=\$3C6! \ Capture/compare control 2 +TB0CCTL3=\$3C8! \ Capture/compare control 3 +TB0CCTL4=\$3CA! \ Capture/compare control 4 +TB0CCTL5=\$3CC! \ Capture/compare control 5 +TB0CCTL6=\$3CE! \ Capture/compare control 6 +TB0R=\$3D0! \ TB0 counter register +TB0CCR0=\$3D2! \ Capture/compare register 0 +TB0CCR1=\$3D4! \ Capture/compare register 1 +TB0CCR2=\$3D6! \ Capture/compare register 2 +TB0CCR3=\$3D8! \ Capture/compare register 3 +TB0CCR5=\$3DA! \ Capture/compare register 4 +TB0CCR5=\$3DC! \ Capture/compare register 5 +TB0CCR6=\$3DE! \ Capture/compare register 6 +TB0EX0=\$3E0! \ TB0 expansion register 0 +TB0IV=\$3EE! \ TB0 interrupt vector + +TA2CTL=\$400! \ TA2 control +TA2CCTL0=\$402! \ Capture/compare control 0 +TA2CCTL1=\$404! \ Capture/compare control 1 +TA2R=\$410! \ TA2 counter register +TA2CCR0=\$412! \ Capture/compare register 0 +TA2CCR1=\$414! \ Capture/compare register 1 +TA2EX0=\$420! \ TA2 expansion register 0 +TA2IV=\$42E! \ TA2 interrupt vector + +TA3CTL=\$440! \ TA3 control +TA3CCTL0=\$442! \ Capture/compare control 0 +TA3CCTL1=\$444! \ Capture/compare control 1 +TA3R=\$450! \ TA3 counter register +TA3CCR0=\$452! \ Capture/compare register 0 +TA3CCR1=\$454! \ Capture/compare register 1 +TA3EX0=\$460! \ TA3 expansion register 0 +TA3IV=\$46E! \ TA3 interrupt vector ! \ RTC_B -RTCCTL0=\$4A0! \ RTC control 0 -RTCCTL1=\$4A1! \ RTC control 1 -RTCCTL2=\$4A2! \ RTC control 2 -RTCCTL3=\$4A3! \ RTC control 3 -RTCPS0CTL=\$4A8! \ RTC prescaler 0 control -RTCPS1CTL=\$4AA! \ RTC prescaler 1 control -RTCPS0=\$4AC! \ RTC prescaler 0 -RTCPS1=\$4AD! \ RTC prescaler 1 -RTCIV=\$4AE! \ RTC interrupt vector word -RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, -RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, -RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, -RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, -RTCDAY=\$4B4! \ RTC days -RTCMON=\$4B5! \ RTC month -RTCYEAR=\$4B6! -RTCYEARL=\$4B6! \ RTC year low -RTCYEARH=\$4B7! \ RTC year high -RTCAMIN=\$4B8! \ RTC alarm minutes -RTCAHOUR=\$4B9! \ RTC alarm hours -RTCADOW=\$4BA! \ RTC alarm day of week -RTCADAY=\$4BB! \ RTC alarm days -BIN2BCD=\$4BC! \ Binary-to-BCD conversion register -BCD2BIN=\$4BE! \ BCD-to-binary conversion register +RTCCTL0=\$4A0! \ RTC control 0 +RTCCTL1=\$4A1! \ RTC control 1 +RTCCTL2=\$4A2! \ RTC control 2 +RTCCTL3=\$4A3! \ RTC control 3 +RTCPS0CTL=\$4A8! \ RTC prescaler 0 control +RTCPS1CTL=\$4AA! \ RTC prescaler 1 control +RTCPS0=\$4AC! \ RTC prescaler 0 +RTCPS1=\$4AD! \ RTC prescaler 1 +RTCIV=\$4AE! \ RTC interrupt vector word +RTCSEC=\$4B0! \ RTC seconds, RTC counter register 1 RTCSEC, +RTCMIN=\$4B1! \ RTC minutes, RTC counter register 2 RTCMIN, +RTCHOUR=\$4B2! \ RTC hours, RTC counter register 3 RTCHOUR, +RTCDOW=\$4B3! \ RTC day of week, RTC counter register 4 RTCDOW, +RTCDAY=\$4B4! \ RTC days +RTCMON=\$4B5! \ RTC month +RTCYEAR=\$4B6! +RTCYEARL=\$4B6! \ RTC year low +RTCYEARH=\$4B7! \ RTC year high +RTCAMIN=\$4B8! \ RTC alarm minutes +RTCAHOUR=\$4B9! \ RTC alarm hours +RTCADOW=\$4BA! \ RTC alarm day of week +RTCADAY=\$4BB! \ RTC alarm days +BIN2BCD=\$4BC! \ Binary-to-BCD conversion register +BCD2BIN=\$4BE! \ BCD-to-binary conversion register RTCHOLD=\$40! RTCRDY=\$10! @@ -580,178 +607,178 @@ MPY32CTL0=\$4EC! \ MPY32 control register 0 DMAIFG=8! -DMACTL0=\$500! \ DMA module control 0 -DMACTL1=\$502! \ DMA module control 1 -DMACTL2=\$504! \ DMA module control 2 -DMACTL3=\$506! \ DMA module control 3 -DMACTL4=\$508! \ DMA module control 4 -DMAIV=\$50A! \ DMA interrupt vector - -DMA0CTL=\$510! \ DMA channel 0 control -DMA0SAL=\$512! \ DMA channel 0 source address low -DMA0SAH=\$514! \ DMA channel 0 source address high -DMA0DAL=\$516! \ DMA channel 0 destination address low -DMA0DAH=\$518! \ DMA channel 0 destination address high -DMA0SZ=\$51A! \ DMA channel 0 transfer size - -DMA1CTL=\$520! \ DMA channel 1 control -DMA1SAL=\$522! \ DMA channel 1 source address low -DMA1SAH=\$524! \ DMA channel 1 source address high -DMA1DAL=\$526! \ DMA channel 1 destination address low -DMA1DAH=\$528! \ DMA channel 1 destination address high -DMA1SZ=\$52A! \ DMA channel 1 transfer size - -DMA2CTL=\$530! \ DMA channel 2 control -DMA2SAL=\$532! \ DMA channel 2 source address low -DMA2SAH=\$534! \ DMA channel 2 source address high -DMA2DAL=\$536! \ DMA channel 2 destination address low -DMA2DAH=\$538! \ DMA channel 2 destination address high -DMA2SZ=\$53A! \ DMA channel 2 transfer size - - -MPUCTL0=\$5A0! \ MPU control 0 -MPUCTL1=\$5A2! \ MPU control 1 -MPUSEGB2=\$5A4! \ MPU Segmentation Border2 -MPUSEGB1=\$5A6! \ MPU Segmentation Border1 -MPUSAM=\$5A8! \ MPU access management -MPUIPC0=\$5AA! \ MPU IP control 0 -MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 -MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 - -UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 -UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 -UCA0BRW=\$5C6! -UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 -UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 -UCA0MCTLW=\$5C8! \ eUSCI_A modulation control -UCA0STAT=\$5CA! \ eUSCI_A status -UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer -UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer -UCA0ABCTL=\$5D0! \ eUSCI_A LIN control -UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control -UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control -UCA0IE=\$5DA! \ eUSCI_A interrupt enable -UCA0IFG=\$5DC! \ eUSCI_A interrupt flags -UCA0IV=\$5DE! \ eUSCI_A interrupt vector word - -UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 -UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 -UCA1BRW=\$5E6! -UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 -UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 -UCA1MCTLW=\$5E8! \ eUSCI_A modulation control -UCA1STAT=\$5EA! \ eUSCI_A status -UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer -UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer -UCA1ABCTL=\$5F0! \ eUSCI_A LIN control -UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control -UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control -UCA1IE=\$5FA! \ eUSCI_A interrupt enable -UCA1IFG=\$5FC! \ eUSCI_A interrupt flags -UCA1IV=\$5FE! \ eUSCI_A interrupt vector word - -UCB0CTLW0=\$640! \ eUSCI_B control word 0 -UCB0CTLW1=\$642! \ eUSCI_B control word 1 -UCB0BRW=\$646! -UCB0BR0=\$646! \ eUSCI_B bit rate 0 -UCB0BR1=\$647! \ eUSCI_B bit rate 1 -UCB0STATW=\$648! \ eUSCI_B status word -UCBCNT0=\$649! \ eUSCI_B hardware count -UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold -UCB0RXBUF=\$64C! \ eUSCI_B receive buffer -UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer -UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 -UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 -UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 -UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 -UCB0ADDRX=\$65C! \ eUSCI_B received address -UCB0ADDMASK=\$65E! \ eUSCI_B address mask -UCB0I2CSA=\$660! \ eUSCI I2C slave address -UCB0IE=\$66A! \ eUSCI interrupt enable -UCB0IFG=\$66C! \ eUSCI interrupt flags -UCB0IV=\$66E! \ eUSCI interrupt vector word +DMACTL0=\$500! \ DMA module control 0 +DMACTL1=\$502! \ DMA module control 1 +DMACTL2=\$504! \ DMA module control 2 +DMACTL3=\$506! \ DMA module control 3 +DMACTL4=\$508! \ DMA module control 4 +DMAIV=\$50A! \ DMA interrupt vector + +DMA0CTL=\$510! \ DMA channel 0 control +DMA0SAL=\$512! \ DMA channel 0 source address low +DMA0SAH=\$514! \ DMA channel 0 source address high +DMA0DAL=\$516! \ DMA channel 0 destination address low +DMA0DAH=\$518! \ DMA channel 0 destination address high +DMA0SZ=\$51A! \ DMA channel 0 transfer size + +DMA1CTL=\$520! \ DMA channel 1 control +DMA1SAL=\$522! \ DMA channel 1 source address low +DMA1SAH=\$524! \ DMA channel 1 source address high +DMA1DAL=\$526! \ DMA channel 1 destination address low +DMA1DAH=\$528! \ DMA channel 1 destination address high +DMA1SZ=\$52A! \ DMA channel 1 transfer size + +DMA2CTL=\$530! \ DMA channel 2 control +DMA2SAL=\$532! \ DMA channel 2 source address low +DMA2SAH=\$534! \ DMA channel 2 source address high +DMA2DAL=\$536! \ DMA channel 2 destination address low +DMA2DAH=\$538! \ DMA channel 2 destination address high +DMA2SZ=\$53A! \ DMA channel 2 transfer size + + +MPUCTL0=\$5A0! \ MPU control 0 +MPUCTL1=\$5A2! \ MPU control 1 +MPUSEGB2=\$5A4! \ MPU Segmentation Border2 +MPUSEGB1=\$5A6! \ MPU Segmentation Border1 +MPUSAM=\$5A8! \ MPU access management +MPUIPC0=\$5AA! \ MPU IP control 0 +MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 +MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 + +UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 +UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 +UCA0BRW=\$5C6! +UCA0BR0=\$5C6! \ eUSCI_A baud rate 0 +UCA0BR1=\$5C7! \ eUSCI_A baud rate 1 +UCA0MCTLW=\$5C8! \ eUSCI_A modulation control +UCA0STAT=\$5CA! \ eUSCI_A status +UCA0RXBUF=\$5CC! \ eUSCI_A receive buffer +UCA0TXBUF=\$5CE! \ eUSCI_A transmit buffer +UCA0ABCTL=\$5D0! \ eUSCI_A LIN control +UCA0IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control +UCA0IRRCTL=\$5D3! \ eUSCI_A IrDA receive control +UCA0IE=\$5DA! \ eUSCI_A interrupt enable +UCA0IFG=\$5DC! \ eUSCI_A interrupt flags +UCA0IV=\$5DE! \ eUSCI_A interrupt vector word + +UCA1CTLW0=\$5E0! \ eUSCI_A control word 0 +UCA1CTLW1=\$5E2! \ eUSCI_A control word 1 +UCA1BRW=\$5E6! +UCA1BR0=\$5E6! \ eUSCI_A baud rate 0 +UCA1BR1=\$5E7! \ eUSCI_A baud rate 1 +UCA1MCTLW=\$5E8! \ eUSCI_A modulation control +UCA1STAT=\$5EA! \ eUSCI_A status +UCA1RXBUF=\$5EC! \ eUSCI_A receive buffer +UCA1TXBUF=\$5EE! \ eUSCI_A transmit buffer +UCA1ABCTL=\$5F0! \ eUSCI_A LIN control +UCA1IRTCTL=\$5F2! \ eUSCI_A IrDA transmit control +UCA1IRRCTL=\$5F3! \ eUSCI_A IrDA receive control +UCA1IE=\$5FA! \ eUSCI_A interrupt enable +UCA1IFG=\$5FC! \ eUSCI_A interrupt flags +UCA1IV=\$5FE! \ eUSCI_A interrupt vector word + +UCB0CTLW0=\$640! \ eUSCI_B control word 0 +UCB0CTLW1=\$642! \ eUSCI_B control word 1 +UCB0BRW=\$646! +UCB0BR0=\$646! \ eUSCI_B bit rate 0 +UCB0BR1=\$647! \ eUSCI_B bit rate 1 +UCB0STATW=\$648! \ eUSCI_B status word +UCBCNT0=\$649! \ eUSCI_B hardware count +UCB0TBCNT=\$64A! \ eUSCI_B byte counter threshold +UCB0RXBUF=\$64C! \ eUSCI_B receive buffer +UCB0TXBUF=\$64E! \ eUSCI_B transmit buffer +UCB0I2COA0=\$654! \ eUSCI_B I2C own address 0 +UCB0I2COA1=\$656! \ eUSCI_B I2C own address 1 +UCB0I2COA2=\$658! \ eUSCI_B I2C own address 2 +UCB0I2COA3=\$65A! \ eUSCI_B I2C own address 3 +UCB0ADDRX=\$65C! \ eUSCI_B received address +UCB0ADDMASK=\$65E! \ eUSCI_B address mask +UCB0I2CSA=\$660! \ eUSCI I2C slave address +UCB0IE=\$66A! \ eUSCI interrupt enable +UCB0IFG=\$66C! \ eUSCI interrupt flags +UCB0IV=\$66E! \ eUSCI interrupt vector word UCTXACK=\$20! UCTR=\$10! -ADC12CTL0=\$800! \ ADC12_B Control 0 -ADC12CTL1=\$802! \ ADC12_B Control 1 -ADC12CTL2=\$804! \ ADC12_B Control 2 -ADC12CTL3=\$806! \ ADC12_B Control 3 -ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register -ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register -ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0 -ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1 -ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2 -ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0 -ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1 -ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2 -ADC12IV=\$818! \ ADC12_B Interrupt Vector -ADC12MCTL0=\$820! \ ADC12_B Memory Control 0 -ADC12MCTL1=\$822! \ ADC12_B Memory Control 1 -ADC12MCTL2=\$824! \ ADC12_B Memory Control 2 -ADC12MCTL3=\$826! \ ADC12_B Memory Control 3 -ADC12MCTL4=\$828! \ ADC12_B Memory Control 4 -ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5 -ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6 -ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7 -ADC12MCTL8=\$830! \ ADC12_B Memory Control 8 -ADC12MCTL9=\$832! \ ADC12_B Memory Control 9 -ADC12MCTL10=\$834! \ ADC12_B Memory Control 10 -ADC12MCTL11=\$836! \ ADC12_B Memory Control 11 -ADC12MCTL12=\$838! \ ADC12_B Memory Control 12 -ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13 -ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14 -ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15 -ADC12MCTL16=\$840! \ ADC12_B Memory Control 16 -ADC12MCTL17=\$842! \ ADC12_B Memory Control 17 -ADC12MCTL18=\$844! \ ADC12_B Memory Control 18 -ADC12MCTL19=\$846! \ ADC12_B Memory Control 19 -ADC12MCTL20=\$848! \ ADC12_B Memory Control 20 -ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21 -ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22 -ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23 -ADC12MCTL24=\$850! \ ADC12_B Memory Control 24 -ADC12MCTL25=\$852! \ ADC12_B Memory Control 25 -ADC12MCTL26=\$854! \ ADC12_B Memory Control 26 -ADC12MCTL27=\$856! \ ADC12_B Memory Control 27 -ADC12MCTL28=\$858! \ ADC12_B Memory Control 28 -ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29 -ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30 -ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31 -ADC12MEM0=\$860! \ ADC12_B Memory 0 -ADC12MEM1=\$862! \ ADC12_B Memory 1 -ADC12MEM2=\$864! \ ADC12_B Memory 2 -ADC12MEM3=\$866! \ ADC12_B Memory 3 -ADC12MEM4=\$868! \ ADC12_B Memory 4 -ADC12MEM5=\$86A! \ ADC12_B Memory 5 -ADC12MEM6=\$86C! \ ADC12_B Memory 6 -ADC12MEM7=\$86E! \ ADC12_B Memory 7 -ADC12MEM8=\$870! \ ADC12_B Memory 8 -ADC12MEM9=\$872! \ ADC12_B Memory 9 -ADC12MEM10=\$874! \ ADC12_B Memory 10 -ADC12MEM11=\$876! \ ADC12_B Memory 11 -ADC12MEM12=\$878! \ ADC12_B Memory 12 -ADC12MEM13=\$87A! \ ADC12_B Memory 13 -ADC12MEM14=\$87C! \ ADC12_B Memory 14 -ADC12MEM15=\$87E! \ ADC12_B Memory 15 -ADC12MEM16=\$880! \ ADC12_B Memory 16 -ADC12MEM17=\$882! \ ADC12_B Memory 17 -ADC12MEM18=\$884! \ ADC12_B Memory 18 -ADC12MEM19=\$886! \ ADC12_B Memory 19 -ADC12MEM20=\$888! \ ADC12_B Memory 20 -ADC12MEM21=\$88A! \ ADC12_B Memory 21 -ADC12MEM22=\$88C! \ ADC12_B Memory 22 -ADC12MEM23=\$88E! \ ADC12_B Memory 23 -ADC12MEM24=\$890! \ ADC12_B Memory 24 -ADC12MEM25=\$892! \ ADC12_B Memory 25 -ADC12MEM26=\$894! \ ADC12_B Memory 26 -ADC12MEM27=\$896! \ ADC12_B Memory 27 -ADC12MEM28=\$898! \ ADC12_B Memory 28 -ADC12MEM29=\$89A! \ ADC12_B Memory 29 -ADC12MEM30=\$89C! \ ADC12_B Memory 30 -ADC12MEM31=\$89E! \ ADC12_B Memory 31 +ADC12CTL0=\$800! \ ADC12_B Control 0 +ADC12CTL1=\$802! \ ADC12_B Control 1 +ADC12CTL2=\$804! \ ADC12_B Control 2 +ADC12CTL3=\$806! \ ADC12_B Control 3 +ADC12LO=\$808! \ ADC12_B Window Comparator Low Threshold Register +ADC12HI=\$80A! \ ADC12_B Window Comparator High Threshold Register +ADC12IFGR0=\$80C! \ ADC12_B Interrupt Flag Register 0 +ADC12IFGR1=\$80E! \ ADC12_B Interrupt Flag Register 1 +ADC12IFGR2=\$810! \ ADC12_B Interrupt Flag Register 2 +ADC12IER0=\$812! \ ADC12_B Interrupt Enable Register 0 +ADC12IER1=\$814! \ ADC12_B Interrupt Enable Register 1 +ADC12IER2=\$816! \ ADC12_B Interrupt Enable Register 2 +ADC12IV=\$818! \ ADC12_B Interrupt Vector +ADC12MCTL0=\$820! \ ADC12_B Memory Control 0 +ADC12MCTL1=\$822! \ ADC12_B Memory Control 1 +ADC12MCTL2=\$824! \ ADC12_B Memory Control 2 +ADC12MCTL3=\$826! \ ADC12_B Memory Control 3 +ADC12MCTL4=\$828! \ ADC12_B Memory Control 4 +ADC12MCTL5=\$82A! \ ADC12_B Memory Control 5 +ADC12MCTL6=\$82C! \ ADC12_B Memory Control 6 +ADC12MCTL7=\$82E! \ ADC12_B Memory Control 7 +ADC12MCTL8=\$830! \ ADC12_B Memory Control 8 +ADC12MCTL9=\$832! \ ADC12_B Memory Control 9 +ADC12MCTL10=\$834! \ ADC12_B Memory Control 10 +ADC12MCTL11=\$836! \ ADC12_B Memory Control 11 +ADC12MCTL12=\$838! \ ADC12_B Memory Control 12 +ADC12MCTL13=\$83A! \ ADC12_B Memory Control 13 +ADC12MCTL14=\$83C! \ ADC12_B Memory Control 14 +ADC12MCTL15=\$83E! \ ADC12_B Memory Control 15 +ADC12MCTL16=\$840! \ ADC12_B Memory Control 16 +ADC12MCTL17=\$842! \ ADC12_B Memory Control 17 +ADC12MCTL18=\$844! \ ADC12_B Memory Control 18 +ADC12MCTL19=\$846! \ ADC12_B Memory Control 19 +ADC12MCTL20=\$848! \ ADC12_B Memory Control 20 +ADC12MCTL21=\$84A! \ ADC12_B Memory Control 21 +ADC12MCTL22=\$84C! \ ADC12_B Memory Control 22 +ADC12MCTL23=\$84E! \ ADC12_B Memory Control 23 +ADC12MCTL24=\$850! \ ADC12_B Memory Control 24 +ADC12MCTL25=\$852! \ ADC12_B Memory Control 25 +ADC12MCTL26=\$854! \ ADC12_B Memory Control 26 +ADC12MCTL27=\$856! \ ADC12_B Memory Control 27 +ADC12MCTL28=\$858! \ ADC12_B Memory Control 28 +ADC12MCTL29=\$85A! \ ADC12_B Memory Control 29 +ADC12MCTL30=\$85C! \ ADC12_B Memory Control 30 +ADC12MCTL31=\$85E! \ ADC12_B Memory Control 31 +ADC12MEM0=\$860! \ ADC12_B Memory 0 +ADC12MEM1=\$862! \ ADC12_B Memory 1 +ADC12MEM2=\$864! \ ADC12_B Memory 2 +ADC12MEM3=\$866! \ ADC12_B Memory 3 +ADC12MEM4=\$868! \ ADC12_B Memory 4 +ADC12MEM5=\$86A! \ ADC12_B Memory 5 +ADC12MEM6=\$86C! \ ADC12_B Memory 6 +ADC12MEM7=\$86E! \ ADC12_B Memory 7 +ADC12MEM8=\$870! \ ADC12_B Memory 8 +ADC12MEM9=\$872! \ ADC12_B Memory 9 +ADC12MEM10=\$874! \ ADC12_B Memory 10 +ADC12MEM11=\$876! \ ADC12_B Memory 11 +ADC12MEM12=\$878! \ ADC12_B Memory 12 +ADC12MEM13=\$87A! \ ADC12_B Memory 13 +ADC12MEM14=\$87C! \ ADC12_B Memory 14 +ADC12MEM15=\$87E! \ ADC12_B Memory 15 +ADC12MEM16=\$880! \ ADC12_B Memory 16 +ADC12MEM17=\$882! \ ADC12_B Memory 17 +ADC12MEM18=\$884! \ ADC12_B Memory 18 +ADC12MEM19=\$886! \ ADC12_B Memory 19 +ADC12MEM20=\$888! \ ADC12_B Memory 20 +ADC12MEM21=\$88A! \ ADC12_B Memory 21 +ADC12MEM22=\$88C! \ ADC12_B Memory 22 +ADC12MEM23=\$88E! \ ADC12_B Memory 23 +ADC12MEM24=\$890! \ ADC12_B Memory 24 +ADC12MEM25=\$892! \ ADC12_B Memory 25 +ADC12MEM26=\$894! \ ADC12_B Memory 26 +ADC12MEM27=\$896! \ ADC12_B Memory 27 +ADC12MEM28=\$898! \ ADC12_B Memory 28 +ADC12MEM29=\$89A! \ ADC12_B Memory 29 +ADC12MEM30=\$89C! \ ADC12_B Memory 30 +ADC12MEM31=\$89E! \ ADC12_B Memory 31 ADCON=\$10! ADCSTART=\$03! @@ -759,19 +786,19 @@ ADCSTART=\$03! CDIFG=1! CDIIFG=2! -CDCTL0=\$8C0! \ Comparator_E control register 0 -CDCTL1=\$8C2! \ Comparator_E control register 1 -CDCTL2=\$8C4! \ Comparator_E control register 2 -CDCTL3=\$8C6! \ Comparator_E control register 3 -CDINT=\$8CC! \ Comparator_E interrupt register -CDIV=\$8CE! \ Comparator_E interrupt vector word - - -AESACTL0=\$9C0! \ AES accelerator control register 0 -AESASTAT=\$9C4! \ AES accelerator status register -AESAKEY=\$9C6! \ AES accelerator key register -AESADIN=\$9C8! \ AES accelerator data in register -AESADOUT=\$9CA! \ AES accelerator data out register -AESAXDIN=\$9CC! \ AES accelerator XORed data in register -AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger) +CDCTL0=\$8C0! \ Comparator_E control register 0 +CDCTL1=\$8C2! \ Comparator_E control register 1 +CDCTL2=\$8C4! \ Comparator_E control register 2 +CDCTL3=\$8C6! \ Comparator_E control register 3 +CDINT=\$8CC! \ Comparator_E interrupt register +CDIV=\$8CE! \ Comparator_E interrupt vector word + + +AESACTL0=\$9C0! \ AES accelerator control register 0 +AESASTAT=\$9C4! \ AES accelerator status register +AESAKEY=\$9C6! \ AES accelerator key register +AESADIN=\$9C8! \ AES accelerator data in register +AESADOUT=\$9CA! \ AES accelerator data out register +AESAXDIN=\$9CC! \ AES accelerator XORed data in register +AESAXIN =\$9CE! \ AES accelerator XORed data in register (no trigger) diff --git a/inc/MSP430FR5972.inc b/inc/MSP430FR5972.inc index d718445..279ec37 100644 --- a/inc/MSP430FR5972.inc +++ b/inc/MSP430FR5972.inc @@ -59,7 +59,7 @@ JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password strin BSL_SIG1 .equ 0FF84h ; BSL_SIG2 .equ 0FF86h ; JTAG_PASSWORD .equ 0FF86h ; up to 0FFC5h : 256 bits -I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address +I2CSLA0 .equ 0FFA2h ; UCBxI2COA0 default value address I2CSLA1 .equ 0FFA4h ; UCBxI2COA1 default value address I2CSLA2 .equ 0FFA6h ; UCBxI2COA2 default value address I2CSLA3 .equ 0FFA8h ; UCBxI2COA3 default value address @@ -233,7 +233,7 @@ P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG -P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word +P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word P2IN .equ PA_SFR + 01h ; Port 2 INput P2OUT .equ PA_SFR + 03h ; Port 2 OUTput @@ -245,7 +245,7 @@ P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt FlaG -P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word +P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT3/4 @@ -272,7 +272,7 @@ P3SELC .equ PB_SFR + 16h ; Port 3 Complement Selection P3IES .equ PB_SFR + 18h ; Port 3 Interrupt Edge Select P3IE .equ PB_SFR + 1Ah ; Port 3 Interrupt Enable P3IFG .equ PB_SFR + 1Ch ; Port 3 Interrupt Flag -P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word +P3IV .equ PB_SFR + 0Eh ; Port 3 Interrupt Vector word P4IN .equ PB_SFR + 01h ; Port 4 Input */ P4OUT .equ PB_SFR + 03h ; Port 4 Output @@ -284,7 +284,7 @@ P4SELC .equ PB_SFR + 17h ; Port 4 Complement Selection P4IES .equ PB_SFR + 19h ; Port 4 Interrupt Edge Select P4IE .equ PB_SFR + 1Bh ; Port 4 Interrupt Enable P4IFG .equ PB_SFR + 1Dh ; Port 4 Interrupt Flag -P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word +P4IV .equ PB_SFR + 1Eh ; Port 4 Interrupt Vector word ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : PORT5/6 @@ -364,7 +364,7 @@ RTCPS1CTL .set RTC_C_SFR + 0Ah RTCPS .set RTC_C_SFR + 0Ch ; = RT1PS:RT0PS RTCIV .set RTC_C_SFR + 0Eh RTCSEC .set RTC_C_SFR + 10h -RTCCNT1 .set RTC_C_SFR + 10h +RTCCNT1 .set RTC_C_SFR + 10h RTCMIN .set RTC_C_SFR + 11h RTCCNT2 .set RTC_C_SFR + 11h RTCHOUR .set RTC_C_SFR + 12h @@ -407,14 +407,14 @@ RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */ MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0 -MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 -MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 -MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2 -MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1 -MPUSAM .equ MPU_SFR + 08h ; MPU access management -MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0 -MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2 -MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1 +MPUCTL0 .equ MPU_SFR + 00h ; MPU control 0 +MPUCTL1 .equ MPU_SFR + 02h ; MPU control 1 +MPUSEGB2 .equ MPU_SFR + 04h ; MPU Segmentation Border 2 +MPUSEGB1 .equ MPU_SFR + 06h ; MPU Segmentation Border 1 +MPUSAM .equ MPU_SFR + 08h ; MPU access management +MPUIPC0 .equ MPU_SFR + 0Ah ; MPU IP control 0 +MPUIPSEGB2 .equ MPU_SFR + 0Ch ; MPU IP Encapsulation Segment Border 2 +MPUIPSEGB1 .equ MPU_SFR + 0Eh ; MPU IP Encapsulation Segment Border 1 ; ---------------------------------------------------------------------- ; eUSCI_A0 @@ -497,7 +497,7 @@ TERM_STATW .equ eUSCI_B0_SFR + 08h ; USCI_B0 Status Word TERM_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8 TERM_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8 TERM_I2COA0 .equ eUSCI_B0_SFR + 14h ; USCI_B0 I2C Own Address 0 -TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register +TERM_ADDRX .equ eUSCI_B0_SFR + 1Ch ; USCI_B0 Received Address Register TERM_I2CSA .equ eUSCI_B0_SFR + 20h ; USCI_B0 I2C Slave Address TERM_IE .equ eUSCI_B0_SFR + 2Ah ; USCI_B0 Interrupt Enable TERM_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register diff --git a/inc/MSP430FR5972.pat b/inc/MSP430FR5972.pat index f3e1a10..79e7d3d 100644 --- a/inc/MSP430FR5972.pat +++ b/inc/MSP430FR5972.pat @@ -44,40 +44,65 @@ TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -99,52 +124,47 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! ---------------------------------------------- ! FastForth RAM memory map (>= 1k): ! ---------------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ base address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ORG=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- !1DE0! 28 RAM bytes free ! --------------------------------------- @@ -267,47 +287,55 @@ MAIN_LEN=\$24000! 127 k FRAM SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$440A! CODE compiled by LITERAL -XSQUOTE=\$4414! CODE compiled by S" and S_ -HEREXEC=\$4428! CODE HERE and BEGIN execute address -QFBRAN=\$4434! CODE compiled by IF UNTIL -BRAN=\$443A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$443C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$443E! CODE compiled by DO -XPLOOP=\$444E! CODE compiled by +LOOP -XLOOP=\$4460! CODE compiled by LOOP -MUSMOD=\$4466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$4478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$4480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$44AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$44AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$44BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$44CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$44D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$44E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$44EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$441E! CODE compiled by S" and S_ +HEREXEC=\$4432! CODE HERE and BEGIN execute address +MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$4494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$44AC! CODE compiled by IF UNTIL +BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$44F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$452A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$4536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$4594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$459C! ASM CODE, content of WARM+2 by default -UART_RXON=\$45C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$45C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$45B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$458E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$45BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$45BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$4584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$4586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$4544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$4556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$4556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$4558! asm CODE, content of WARM+2 by default +I2C_WARM=\$4580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR6989 ! ---------------------------------------------- MAIN_LEN=\$1FC00! 127 k FRAM -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD diff --git a/inc/MSP430FR5994.pat b/inc/MSP430FR5994.pat index ac96d1b..eed89bc 100644 --- a/inc/MSP430FR5994.pat +++ b/inc/MSP430FR5994.pat @@ -38,7 +38,7 @@ INFO_LEN=\$0200! ! You can check the addresses below by comparing their values in DTCforthMSP430FRxxxx.lst ! those addresses are usable with the symbolic assembler ! ---------------------------------------------- -! FastForth INFO, system addresses (in EPROM) +! FastForth INFO addresses ! ---------------------------------------------- FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST @@ -46,45 +46,71 @@ TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X see WIPE -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC -! -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +! +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ -TLV_ORG=\$1A00! ; Device Descriptor Info (Tag-Lenght-Value) -TLV_LEN=\$0100! ; +TLV_ORG=\$1A00! Device Descriptor Info (Tag-Lenght-Value) +TLV_LEN=\$0100! DEVICEID=\$1A04! ! ============================================ @@ -102,52 +128,47 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! ---------------------------------------------- ! FastForth RAM memory map (>= 1k): ! ---------------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ base address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - -HP=\$1DB2! \ HOLD ptr -CAPS=\$1DB4! \ CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! \ Interpreter state - -SOURCE_LEN=\$1DC0! \ len of input stream -SOURCE_ORG=\$1DC2! \ adr of input stream -TOIN=\$1DC4! \ >IN -DP=\$1DC6! \ dictionary ptr - -LASTVOC=\$1DC8! \ keep VOC-LINK -CONTEXT=\$1DCA! \ CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! \ CURRENT dictionnary ptr - -BASEADR=\$1DDC! \ numeric base, must be defined before first reset ! -LINE=\$1DDE! \ line in interpretation, activated with NOECHO, desactivated with ECHO +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! +HP=\$1DB2! HOLD ptr +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- !1DE0! 28 RAM bytes free ! --------------------------------------- @@ -199,6 +220,8 @@ ClusterL=\$2022! 16 bits wide (FAT16) ClusterH=\$2024! 16 bits wide (FAT16) NewClusterL=\$2026! 16 bits wide (FAT16) NewClusterH=\$2028! 16 bits wide (FAT16) +LastFATsector=\$2026! 16 bits wide (FAT16) +LastFAToffset=\$2028! 16 bits wide (FAT16) CurFATsector=\$202A! ! --------------------------------------- @@ -273,49 +296,56 @@ WriteSectorWX=WRITE_SECT+8! MAIN_ORG=\$4000! Code space start MAIN_LEN=\$40000! 240 kb FRAM ! ---------------------------------------------- - SLEEP=\$4000! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$400A! CODE compiled by LITERAL -XSQUOTE=\$4014! CODE compiled by S" and S_ -HEREXEC=\$4028! CODE HERE and BEGIN execute address -QFBRAN=\$4034! CODE compiled by IF UNTIL -BRAN=\$403A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$403C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$403E! CODE compiled by DO -XPLOOP=\$404E! CODE compiled by +LOOP -XLOOP=\$4060! CODE compiled by LOOP -MUSMOD=\$4066! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$4078! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$4080! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$40AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$40AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$40BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$40CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$40D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$40E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$40EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$401E! CODE compiled by S" and S_ +HEREXEC=\$4032! CODE HERE and BEGIN execute address +MUSMOD=\$403E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$4050! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$4058! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$4082! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$4084! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$4094! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$40A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$40AC! CODE compiled by IF UNTIL +BRAN=\$40B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$40B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$40B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$40C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$40F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$412A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$4136! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$40D0! asm CODE common part of SYS and QABORT, starts FORTH engine +QABORT=\$4108! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$4112! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +!------------------------------------------------------------------------------- +! UART FASTFORTH !------------------------------------------------------------------------------- -UART_COLD_TERM=\$4194! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$419C! ASM CODE, content of WARM+2 by default -UART_RXON=\$41C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$41C8! ASM CODE, called by ACCEPT before RX char LF. +UART_INIT_TERM=\$4154! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP) +UART_COLD_TERM=\$417E! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP) +UART_INIT_SOFT=\$4184! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP) +UART_RXON=\$4186! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$41B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$418E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$41BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$41BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$4144! asm CODE, default content of SLEEP_APP (SLEEP starts with: CALL &SLEEP_APP) +I2C_CTRL_CH=\$4146! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$4156! asm CODE, default content of STOP_APP (COLD starts with: CALL &STOP_APP) +I2C_INIT_SOFT=\$4156! asm CODE, default content of SOFT_APP (INIT_FORTH starts with: CALL &SOFT_APP) +I2C_INIT_TERM=\$4158! asm CODE, default content of HARD_APP (WARM starts with: CALL &HARD_APP) +I2C_WARM=\$4180! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR5994 ! ---------------------------------------------- -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line, and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0, enable JTAG/SBW JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD diff --git a/inc/MSP430FR6989.pat b/inc/MSP430FR6989.pat index a8471cf..79fb218 100644 --- a/inc/MSP430FR6989.pat +++ b/inc/MSP430FR6989.pat @@ -42,42 +42,67 @@ FREQ_KHZ=\$1800! FREQUENCY (in kHz) TERMBRW_RST=\$1802! TERMBRW_RST TERMMCTLW_RST=\$1804! TERMMCTLW_RST I2CSLAVEADR=\$1802! I2C_SLAVE address -I2CSLAVEADR1=\$1804! +I2CSLAVEADR1=\$1804! LPM_MODE=\$1806! LPM_MODE value, LPM0+GIE is the default value -RSTIV_MEM=\$1808! SYSRSTIV memory, set to -1 to do Deep RESET -RST_DP=\$180A! RST value for DP -RST_VOC=\$180C! RST value for VOClink -VERSION=\$180E! -THREADS=\$1810! THREADS -KERNEL_ADDON=\$1812! - -WIPE_INI_=\$1814! MOV #WIPE_INI,X -WIPE_COLD=\$1814! WIPE value for PFA_COLD -WIPE_INI_FORTH=\$1816! WIPE value for PFA_INI_FORTH -WIPE_SLEEP=\$1818! WIPE value for PFA_SLEEP -WIPE_WARM=\$181A! WIPE value for PFA_WARM -WIPE_TERM_INT=\$181C! WIPE value for TERMINAL vector -WIPE_DP=\$182E! WIPE value for RST_DP -WIPE_VOC=\$1820! WIPE value for RST_VOC - -INI_FORTH_INI=\$1822! MOV #INI_FORTH_INI,X \ >BODY instruction of INI_FORTH subroutine -INIT_ACCEPT=\$1822! WIPE value for PFAACCEPT -INIT_CR=\$1824! WIPE value for PFACR -INIT_EMIT=\$1826! FORTH value for PFAEMIT -INIT_KEY=\$1828! WIPE value for PFAKEY -INIT_CIB=\$182A! WIPE value for CIB_ADR -HALF_FORTH_INI=\$182C! to preserve the state of DEFERed words, used by user INI_SOFT_APP as: -! ADD #4,0(RSP) \ skip INI_FORTH >BODY instruction "MOV #INI_FORTH_INI,X" -! MOV #HALF_FORTH_INI,X \ replace it by "MOV #HALF_FORTH_INI,X" -! MOV @RSP+,PC \ then RET -INIT_DOCOL=\$182C! FORTH value for rDOCOL (R4) -INIT_DODOES=\$182E! FORTH value for rDODOES (R5) -INIT_DOCON=\$1830! FORTH value for rDOCON (R6) -INIT_DOVAR=\$1832! FORTH value for rDOVAR (R7) -INIT_CAPS=\$1834! FORTH value for CAPS -INIT_BASE=\$1836! FORTH value for BASE -! free EPROM - +USERSTIV=\$1808! user SYS variable, defines software RESET, DEEP_RST, INIT_HARWARE, etc. +VERSION=\$180A! +THREADS=\$180C! THREADS +KERNEL_ADDON=\$180E! BIT15=FLOORED DIVISION +! BIT14=LF_XTAL +! BIT13=UART CTS +! BIT12=UART RTS +! BIT11=UART XON/XOFF +! BIT10=UART half duplex +! BIT9=I2C_TERMINAL +! BIT8=Q15.16 input +! BIT7=DOUBLE input +! BIT6=assembler 20 bits +! BIT5=assembler 16 bits +! BIT4=assembler 16 bits with 20 bits addr +! BIT3=vocabulary set +! BIT2= +! BIT1= +! BIT0= +! +DEEP_ORG=\$1810! MOV #DEEP_ORG,X +DEEP_TERM_VEC=\$1810! to DEEP_INIT TERMINAL vector +DEEP_COLD=\$1812! to DEEP_INIT COLD_APP +DEEP_SOFT=\$1814! to DEEP_INIT SOFT_APP +DEEP_HARD=\$1816! to DEEP_INIT HARD_APP +DEEP_SLEEP=\$1818! to DEEP_INIT SLEEP_APP +DEEP_DP=\$181A! to DEEP_INIT RST_DP +DEEP_LASTVOC=\$181C! to DEEP_INIT RST_LASTVOC +DEEP_CURRENT=\$181E! to DEEP_INIT RST_CURRENT +DEEP_CONTEXT=\$1820! to DEEP_INIT RST_CONTEXT +! +PUC_ABORT_ORG=\$1822! MOV #PUC_ABORT_ORG,X +INIT_ACCEPT=\$1822! to INIT PFA_ACCEPT +INIT_EMIT=\$1824! to INIT PFA_EMIT +INIT_KEY=\$1826! to INIT PFA_KEY +INIT_CIB=\$1828! to INIT CIB_ORG +FORTH_ORG=\$182A! MOV #FORTH_ORG,X \to preserve the state of DEFERed words +INIT_RSP=\$182A! to INIT RSP +INIT_DOCOL=\$182C! to INIT rDOCOL (R4) to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL +INIT_DODOES=\$182E! to INIT rDODOES (R5) +INIT_DOCON=\$1830! to INIT rDOCON (R6) +INIT_DOVAR=\$1832! to INIT rDOVAR (R7) +INIT_CAPS=\$1834! to INIT CAPS +INIT_BASE=\$1836! to INIT BASE +INIT_LEAVE=\$1838! to INIT LEAVEPTR +! +RST_ORG=\$183A! +RST_LEN=\$10! +COLD_APP=\$183A! COLD_APP +SOFT_APP=\$183C! SOFT_APP +HARD_APP=\$183E! HARD_APP +SLEEP_APP=\$1840! SLEEP_APP +RST_DP=\$1842! RST_RET value for (RAM) DDP +RST_LASTVOC=\$1844! RST_RET value for (RAM) LASTVOC +RST_CURRENT=\$1846! RST_RET value for (RAM) CURRENT +RST_CONTEXT=\$1848! RST_RET value for (RAM) CONTEXT (8 CELLS) +! +! $185A = free EPROM +! ! ============================================ ! FRAM TLV ! ============================================ @@ -99,54 +124,49 @@ LSTACK_SIZE=\#16! words PSTACK_SIZE=\#48! words RSTACK_SIZE=\#48! words PAD_LEN=\#84! bytes -TIB_LEN=\#84! bytes +CIB_LEN=\#84! bytes HOLD_SIZE=\#34! bytes ! ---------------------------------------------- ! FastForth RAM memory map (>= 1k): ! ---------------------------------------------- -LEAVEPTR=\$1C00! \ Leave-stack pointer, init by QUIT -LSATCK=\$1C00! \ leave stack, grow up -PSTACK=\$1C80! \ parameter stack, grow down -RSTACK=\$1CE0! \ Return stack, grow down - -PAD_I2CADR=\$1CE0! \ RX I2C address -PAD_I2CCNT=\$1CE2! \ count max -PAD_ORG=\$1CE4! \ user scratch pad buffer, 84 bytes, grow up - -TIB_I2CADR=\$1D38! \ TX I2C address -TIB_I2CCNT=\$1D3A! \ count of bytes -TIB_ORG=\$1D3C! \ Terminal input buffer, 84 bytes, grow up - -HOLDS_ORG=\$1D90! \ base address for HOLDS -HOLD_BASE=\$1DB2! \ BASE HOLD area, grow down - -! ---------------------- -! NOT SAVED VARIABLES -! ---------------------- - +LEAVEPTR=\$1C00! Leave-stack pointer, init by QUIT +LSATCK=\$1C00! leave stack, grow up +PSTACK=\$1C80! parameter stack, grow down +RSTACK=\$1CE0! Return stack, grow down +! +PAD_I2CADR=\$1CE0! RX I2C address +PAD_I2CCNT=\$1CE2! count max +PAD_ORG=\$1CE4! user scratch pad buffer, 84 bytes, grow up +! +TIB_I2CADR=\$1D38! TX I2C address +TIB_I2CCNT=\$1D3A! count of bytes +TIB_ORG=\$1D3C! Terminal input buffer, 84 bytes, grow up +! +HOLDS_ORG=\$1D90! base address for HOLDS +HOLD_BASE=\$1DB2! BASE HOLD area, grow down +! HP=\$1DB2! HOLD ptr -CAPS=\$1DB4! CAPS ON/OFF flag, must be set to -1 before first reset ! -LAST_NFA=\$1DB6! -LAST_THREAD=\$1DB8! -LAST_CFA=\$1DBA! -LAST_PSP=\$1DBC! - -STATEADR=\$1DBE! Interpreter state - -SOURCE_LEN=\$1DC0! len of input stream -SOURCE_ORG=\$1DC2! adr of input stream -TOIN=\$1DC4! >IN -DP=\$1DC6! dictionary ptr - -LASTVOC=\$1DC8! keep VOC-LINK -CONTEXT=\$1DCA! CONTEXT dictionnary space (8 CELLS) -CURRENT=\$1DDA! CURRENT dictionnary ptr - -BASEADR=\$1DDC! numeric base, must be defined before first reset ! -LINE=\$1DDE! line in interpretation, activated with NOECHO, desactivated with ECHO +LAST_NFA=\$1DB4! +LAST_THREAD=\$1DB6! +LAST_CFA=\$1DB8! +LAST_PSP=\$1DBA! +! +STATEADR=\$1DBC! Interpreter state +BASEADR=\$1DBE! base +CAPS=\$1DC0! CAPS ON/OFF +! +SOURCE_LEN=\$1DC2! len of input stream +SOURCE_ORG=\$1DC4! adr of input stream +TOIN=\$1DC6! >IN +DP=\$1DC8! dictionary ptr +! +LASTVOC=\$1DCA! keep VOC-LINK +CURRENT=\$1DCC! CURRENT dictionnary ptr +CONTEXT=\$1DCE! CONTEXT dictionnary space (8 CELLS) +! ! --------------------------------------- -!1DE0! 28 RAM bytes free +!1DE0! 28 RAM bytes free ! --------------------------------------- ! --------------------------------------- @@ -243,7 +263,7 @@ HDLW_PrevLEN=24! previous LEN HDLW_PrevORG=26! previous ORG -!OpenedFirstFile ; "openedFile" structure +!OpenedFirstFile ; "openedFile" structure HandleMax=8! HandleLenght=28! FirstHandle=\$2038! @@ -267,47 +287,55 @@ MAIN_LEN=\$24000! 127 k FRAM SLEEP=\$4400! CODE_WITHOUT_RETURN, CPU shutdown LIT=\$440A! CODE compiled by LITERAL -XSQUOTE=\$4414! CODE compiled by S" and S_ -HEREXEC=\$4428! CODE HERE and BEGIN execute address -QFBRAN=\$4434! CODE compiled by IF UNTIL -BRAN=\$443A! CODE compiled by ELSE REPEAT AGAIN -NEXT_ADR=\$443C! CODE NEXT instruction (MOV @IP+,PC) -XDO=\$443E! CODE compiled by DO -XPLOOP=\$444E! CODE compiled by +LOOP -XLOOP=\$4460! CODE compiled by LOOP -MUSMOD=\$4466! ASM CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD -MDIV1DIV2=\$4478! ASM CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ -MDIV1=\$4480! ASM CODE input for 48/16 unsigned division, see DOUBLE M*/ -RET_ADR=\$44AA! ASM CODE of INI_FORTH_PFA and MARKER+8 definitions, -SETIB=\$44AC! CODE Set Input Buffer with org & len values, reset >IN pointer -REFILL=\$44BC! CODE accept one line from input and leave org len of input buffer -CIB_ADR=\$44CA! [CIB_ADR] = TIB_ORG by default; may be redirected to SDIB_ORG -XDODOES=\$44D4! to restore rDODOES: MOV #XDODOES,rDODOES -XDOCON=\$44E2! to restore rDOCON: MOV #XDOCON,rDOCON -XDOVAR=\$44EE! to restore rDOVAR: MOV #XDOVAR,rDOVAR +XSQUOTE=\$441E! CODE compiled by S" and S_ +HEREXEC=\$4432! CODE HERE and BEGIN execute address +MUSMOD=\$443E! asm CODE 32/16 unsigned division, used by ?NUMBER, UM/MOD +MDIV1DIV2=\$4450! asm CODE input for 48/16 unsigned division with DVDhi=0, see DOUBLE M*/ +MDIV1=\$4458! asm CODE input for 48/16 unsigned division, see DOUBLE M*/ +RET_ADR=\$4482! asm CODE of INIT_SOFT_PFA and MARKER+8 definitions, +SETIB=\$4484! CODE Set Input Buffer with org & len values, reset >IN pointer +REFILL=\$4494! CODE accept one line from input and leave org len of input buffer +CIB_ORG=\$44A0! [CIB_ORG] = TIB_ORG by default; may be redirected to SDIB_ORG +QFBRAN=\$44AC! CODE compiled by IF UNTIL +BRAN=\$44B2! CODE compiled by ELSE REPEAT AGAIN +NEXT_ADR=\$44B4! CODE NEXT instruction (MOV @IP+,PC) +XDODOES=\$44B6! to restore rDODOES: MOV #XDODOES,rDODOES +XDOCON=\$44C4! to restore rDOCON: MOV #XDOCON,rDOCON +! to restore rDOVAR: MOV &INIT_DOVAR,rDOVAR ! to restore rDOCOL: MOV &INIT_DOCOL,rDOCOL -INI_FORTH=\$44F8! asm CODE common part of RST and QABORT, starts FORTH engine -QABORT=\$452A! CODE_WITHOUT_RETURN run-time part of ABORT" -ABORT_TERM=\$4536! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET +INIT_FORTH=\$44D0! asm CODE common part of RST and QABORT, starts FORTH engine +QABORT=\$4508! CODE_WITHOUT_RETURN run-time part of ABORT" +ABORT_TERM=\$4512! CODE_WITHOUT_RETURN, called by QREVEAL and INTERPRET !------------------------------------------------------------------------------- -UART_COLD_TERM=\$4594! ASM CODE, content of COLD+2 by default -UART_INIT_TERM=\$459C! ASM CODE, content of WARM+2 by default -UART_RXON=\$45C6! ASM CODE, content of SLEEP+2 by default -UART_RXOFF=\$45C8! ASM CODE, called by ACCEPT before RX char LF. +! UART FASTFORTH !------------------------------------------------------------------------------- -I2C_COLD_TERM=\$45B8! ASM CODE, content of COLD_PFA by default -I2C_INIT_TERM=\$458E! ASM CODE, content of WARM_PFA by default -I2C_RXON=\$45BA! ASM CODE, content of SLEEP_PFA by default -I2C_CTRL_CH=\$45BC! ASM CODE, used as is: MOV.B #CTRL_CHAR,Y +UART_INIT_TERM=\$4554! asm CODE, content of WARM+2 by default (WARM starts with: CALL #UART_INIT_TERM) +UART_COLD_TERM=\$457E! asm CODE, content of COLD+2 by default (COLD starts with: CALL #UART_COLD_TERM) +UART_INIT_SOFT=\$4584! asm CODE, content of INIT_FORTH+2 (by default, INIT_FORTH starts with: CALL #RET_ADR) +UART_RXON=\$4586! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXON=KEY\+\$8! asm CODE, content of SLEEP+2 (by default, SLEEP starts with: CALL #UART_RXON) +UART_RXOFF=ACCEPT\+\$2A! asm CODE, called by ACCEPT after 'CR' and before 'LF'. +!------------------------------------------------------------------------------- +! I2C FASTFORTH +!------------------------------------------------------------------------------- +I2C_ACCEPT=\$4544! asm CODE, content of SLEEP+2 by default +I2C_CTRL_CH=\$4546! asm CODE, used as is: MOV.B #CTRL_CHAR,Y ! CALL #I2C_CTRL_CH +I2C_COLD_TERM=\$4556! asm CODE, content of COLD+2, RET address by default +I2C_INIT_SOFT=\$4556! asm CODE, content of INIT_FORTH+2, RET address by default +I2C_INIT_TERM=\$4558! asm CODE, content of WARM+2 by default +I2C_WARM=\$4580! WARM address !------------------------------------------------------------------------------- - +NOPUC=SYS\+\$0A! NOPUC with FORTH: ' SYS 10 + +COLD=SYS\+\$16! COLD address ' SYS 22 + +ABORT=ALLOT\+\$8! CODE_WITHOUT_RETURN ' ALLOT 8 + +QUIT=ALLOT\+\$0E! CODE_WITHOUT_RETURN ' ALLOT 14 + ! ---------------------------------------------- ! Interrupt Vectors and signatures - MSP430FR6989 ! ---------------------------------------------- MAIN_LEN=\$1FC00! 127 k FRAM -FRAM_FULL=\$FF30! 80 bytes are sufficient considering what can be compiled in one line and WORD use. +FRAM_FULL=\$FF40! 64 bytes are sufficient considering what can be compiled in one line and WORD use. SIGNATURES=\$FF80! JTAG/BSL signatures JTAG_SIG1=\$FF80! if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe. JTAG_SIG2=\$FF82! if JTAG_SIG1=\$AAAA, length of password string @ JTAG_PASSWORD @@ -717,14 +745,14 @@ DMA2DAH=\$538! \ DMA channel 2 destination address high DMA2SZ=\$53A! \ DMA channel 2 transfer size -MPUCTL0=\$5A0! \ MPU control 0 -MPUCTL1=\$5A2! \ MPU control 1 -MPUSEGB2=\$5A4! \ MPU Segmentation Border2 -MPUSEGB1=\$5A6! \ MPU Segmentation Border1 -MPUSAM=\$5A8! \ MPU access management -MPUIPC0=\$5AA! \ MPU IP control 0 -MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 -MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 +MPUCTL0=\$5A0! \ MPU control 0 +MPUCTL1=\$5A2! \ MPU control 1 +MPUSEGB2=\$5A4! \ MPU Segmentation Border2 +MPUSEGB1=\$5A6! \ MPU Segmentation Border1 +MPUSAM=\$5A8! \ MPU access management +MPUIPC0=\$5AA! \ MPU IP control 0 +MPUIPSEGB2=\$5AC! \ MPU IP Encapsulation Segment Border 2 +MPUIPSEGB1=\$5AE! \ MPU IP Encapsulation Segment Border 1 UCA0CTLW0=\$5C0! \ eUSCI_A control word 0 UCA0CTLW1=\$5C2! \ eUSCI_A control word 1 diff --git a/inc/MSP_EXP430FR2355.asm b/inc/MSP_EXP430FR2355.asm index 5cbf7e9..034bd7d 100644 --- a/inc/MSP_EXP430FR2355.asm +++ b/inc/MSP_EXP430FR2355.asm @@ -76,7 +76,7 @@ ; MSP-EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD ; ====================================================================== -; +--4k7-< DeepRST switch <-- GND +; +--4k7-< DeepRST switch <-- GND ; | ; P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge ; P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge @@ -85,15 +85,15 @@ ; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave ; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave - -; P2.2 - J2.18 - <---- TSSOP32236 (IR RC5) + +; P2.2 - J2.18 - <---- TSSOP32236 (IR RC5) ; P2.5 - J2.13 - <---- SD_CD (Card Detect) ; P4.4 - J2.12 - ----> SD_CS (Card Select) ; P4.5 - UCB1 CLK J1.7 - ----> SD_CLK ; P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI ; P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO - + ; P6.0 - J4.39 - ----> SCL I2C Soft_Master ; P6.1 - J4.38 - <---> SDA I2C Soft_Master @@ -130,14 +130,14 @@ BUS_TERM .equ 0Ch ; P1.2=SDA, P1.3=SCL MOV #0FFFEh,&PAOUT ; all pins with pullup resistors else LED1 .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high (false) to disable RX TERM during start FORTH HANDSHAKOUT .equ P2OUT HANDSHAKIN .equ P2IN RTS .equ 1 ; P2.0 BIS.B #RTS,&P2DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired CTS .equ 2 ; P2.1 BIC.B #CTS,&P2OUT ; CTS input resistor is pulled down @@ -146,7 +146,7 @@ CTS .equ 2 ; P2.1 SW2_IN .equ P2IN -SW2 .equ 8 ; P2.3 = S2 +SW2 .equ 8 ; P2.3 = S2 SD_CDIN .equ P2IN CD_SD .equ 20h ; P2.5 @@ -171,10 +171,7 @@ CD_SD .equ 20h ; P2.5 MOV #-1,&PBOUT ; pullup resistors for all pins SW1_IN .equ P4IN -SW1 .equ 2 ; P4.1 = S1 - -WIPE_IN .equ P4IN -IO_WIPE .equ 2 ; P4.1 = S1 = FORTH Deep_RST pin +SW1 .equ 2 ; P4.1 = S1 .IFDEF UCA1_TERM ; UCA1 RXD P4.2 - J101.8 <---- TX UARTtoUSB bridge @@ -236,117 +233,44 @@ LED2 .equ 40h ; P6.6 LED2 green ; CS code for MSP430FR2355 -; to measure SMCLK frequency, wires SMCLK on P1.0: +; to measure SMCLK frequency, wires SMCLK on P1.0: ; BIS.B #1,&P1SEL1 ; BIS.B #1,&P1DIR -; to measure REFO frequency, wires ACLK on P1.1: +; to measure REFO frequency, wires ACLK on P1.1: ; BIS.B #2,&P1SEL1 ; BIS.B #2,&P1DIR -; ===================================== - .IF FREQUENCY = 1 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh - ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz - MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh - ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz -; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh - ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz -; ===================================== + .IFDEF LF_XTAL +; because LOCKLPM5 is ON, XT1 is replaced by REFO automaticaly until WARM clears LOCKLPM5 +; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) + MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV + BIS.B #0C0h,&P2SEL1 ; P2.6 as XOUT, P2.7 as XIN + .ELSE + BIS #0010h,&CSCTL3 ; FLL select REFCLOCK +; MOV #0100h,&CSCTL4 ; ACLOCK select REFOCLK, MCLK & SMCLK select DCOCLKDIV (default value) + .ENDIF + BIC.B #-1,&CSCTL1 ; clear DCORSEL (Set 1MHZ DCORSEL), DCOFTRIM=0, ENable MODulation to reduce EMI + .IF FREQUENCY = 1 ; nothing else to do .ELSEIF FREQUENCY = 2 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh - ; fCOCLKDIV = 32768 x (59+1) = 1.966 MHz ; measured : MHz - MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch - ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz -; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh - ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz -; ===================================== + BIS.B #2,&CSCTL1 ; Set 2MHZ DCORSEL .ELSEIF FREQUENCY = 4 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h - ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz - MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h - ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz -; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah - ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz -; ===================================== + BIS.B #4,&CSCTL1 ; Set 4MHZ DCORSEL .ELSEIF FREQUENCY = 8 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) - MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h - ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz -; MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h - ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz -; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h - ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz -; ===================================== + BIS.B #6,&CSCTL1 ; Set 8MHZ DCORSEL .ELSEIF FREQUENCY = 12 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) - MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz -; MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz -; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz -; ===================================== + BIS.B #8,&CSCTL1 ; Set 12MHZ DCORSEL .ELSEIF FREQUENCY = 16 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz - MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz -; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz -; ===================================== + BIS.B #10,&CSCTL1 ; Set 16MHZ DCORSEL .ELSEIF FREQUENCY = 20 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BCh,&CSCTL1 ; Set 20MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0261h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=261h - ; fCOCLKDIV = 32768 x 609+1) = 19.988 MHz ; measured : 19.xxxMHz - MOV #0262h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=262h - ; fCOCLKDIV = 32768 x 610+1) = 20.021 MHz ; measured : 20.xxxMHz -; MOV #0263h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=263h - ; fCOCLKDIV = 32768 x 611+1) = 20.054 MHz ; measured : 20.xxxMHz -; ===================================== + BIS.B #12,&CSCTL1 ; Set 20MHZ DCORSEL .ELSEIF FREQUENCY = 24 - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BEh,&CSCTL1 ; Set 24MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ------------------------------------- ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #02DBh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DBh - ; fCOCLKDIV = 32768 x 731+1) = 23.986 MHz ; measured : 23.xxxMHz - MOV #02DCh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DCh - ; fCOCLKDIV = 32768 x 732+1) = 24.019 MHz ; measured : 23.xxxMHz -; MOV #02DDh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=2DDh - ; fCOCLKDIV = 32768 x 733+1) = 24.051 MHz ; measured : 24.xxxMHz -; ===================================== + BIS.B #14,&CSCTL1 ; Set 24MHZ DCORSEL .ELSEIF - .error "bad frequency setting, only 0.5,1,2,4,8,12,16,20,24 MHz" + .error "bad frequency setting, only 1,2,4,8,12,16,20,24 MHz" .ENDIF - - .IFDEF LF_XTAL -; because LOCKLPM5 is ON, XT1 is replaced by REFO automaticaly until WARM clears LOCKLPM5 -; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) - MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV - BIS.B #0C0h,&P2SEL1 ; P2.6 as XOUT, P2.7 as XIN - .ELSE - BIS #0010h,&CSCTL3 ; FLL select REFCLOCK -; MOV #0100h,&CSCTL4 ; ACLOCK select REFOCLK, MCLK & SMCLK select DCOCLKDIV (default value) - .ENDIF - +; MOV #INT(FREQUENCY*1000000/32768)-1,&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight lower + MOV #INT(FREQUENCY*1000000/32768),&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight upper MOV #92,X ; 96* 3 ms = 288 ms delay, because FLL lock time = 200 ms ClockWaitX MOV &FREQ_KHZ,Y ; ClockWaitY SUB #1,Y ;1 diff --git a/inc/MSP_EXP430FR2355.pat b/inc/MSP_EXP430FR2355.pat index bb4f858..139e70b 100644 --- a/inc/MSP_EXP430FR2355.pat +++ b/inc/MSP_EXP430FR2355.pat @@ -4,10 +4,10 @@ \.f=\.4th for MSP_EXP430FR2355! to change file type ! !======================== -! remove comments +! remove comments !======================== -\\*\n= -\s\\*\n=\n +\\*\n=! entire comment lines +\s\\*\n=\n! comments at end of line ! ====================================================================== ! MSP430FR2355 Config ! ====================================================================== @@ -92,7 +92,7 @@ ! MSP_EXP430FR2355 LAUNCHPAD <--> OUTPUT WORLD ! ====================================================================== ! -! +--4k7-< DeepRST switch <-- GND +! +--4k7-< DeepRST switch <-- GND ! | ! P4.3 - UCA1 TXD J101.6 - <-+-> RX UARTtoUSB bridge ! P4.2 - UCA1 RXD J101.8 - <---- TX UARTtoUSB bridge @@ -101,15 +101,15 @@ ! ! P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave ! P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave -! -! P2.2 - J2.18 - <---- TSSOP32236 (IR RC5) +! +! P2.2 - J2.18 - <---- TSSOP32236 (IR RC5) ! ! P2.5 - J2.12 - ----> SD_CS (Card Select) ! P4.4 - J2.13 - <---- SD_CD (Card Detect) ! P4.5 - UCB1 CLK J1.7 - ----> SD_CLK ! P4.7 - UCB1 SOMI J2.14 - <---- SD_SDO ! P4.6 - UCB1 SIMO J2.15 - ----> SD_SDI -! +! ! P3.2 - J4.38 - <---> SDA I2C Soft_Master ! P3.3 - J4.39 - ----> SCL I2C Soft_Master @@ -129,7 +129,7 @@ ! P6.0 <------------------------> 11 LCD_DB4 ! P6.1 <------------------------> 12 LCD_DB5 ! P6.2 <------------------------> 13 LCD_DB5 -! P6.3 <------------------------> 14 LCD_DB7 +! P6.3 <------------------------> 14 LCD_DB7 ! P4.1 ---> S2 LCD contrast + ! P2.3 ---> S1 LCD contrast - @@ -138,7 +138,7 @@ ! ============================================ ! FORTH TERMINAL I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=\$0C! P4.2 = RX, P4.3 = TX TERM_IN=\$221! P4 @@ -196,10 +196,10 @@ LED2_DIR=\$245! LED2=\$40! P6.6 LED2 green SW1_IN=\$221! -SW1=2! P4.1 = S1 +SW1=2! P4.1 = S1 WIPE_IN=\$221! -WIPE=2! P4.1 = S1 = FORTH Deep_RST pin +WIPE=2! P4.1 = S1 = FORTH Deep_RST pin SW2_IN=\$201! SW2=8! P2.3 @@ -242,10 +242,10 @@ WDT_TIM_0_VEC=\$FFF4! TB1_0_VEC !IR_RC5 RC5_=RC5_! -IR_IN=\$201! -IR_OUT=\$203! -IR_DIR=\$205! -IR_REN=\$209! +IR_IN=\$201! +IR_OUT=\$203! +IR_DIR=\$205! +IR_REN=\$209! IR_IES=\$219! IR_IE=\$21B! IR_IFG=\$21D! @@ -261,18 +261,22 @@ I2CSM_IN=\$220! I2CSM_OUT=\$222! I2CSM_DIR=\$224! I2CSM_REN=\$226! +I2CSM_IES=\$238! +I2CSM_IFG=\$23C! SM_SDA=4! P3.2 SM_SCL=8! P3.3 -SM_BUS=\$0C! +SM_BUS=\$0C! !Software I2C_Multi_Master I2CSMM_IN=\$220! I2CSMM_OUT=\$222! I2CSMM_DIR=\$224! I2CSMM_REN=\$226! +I2CSMM_IES=\$238! +I2CSMM_IFG=\$23C! SMM_SDA=4! P3.2 SMM_SCL=8! P3.3 -SMM_BUS=\$0C! +SMM_BUS=\$0C! !hardware I2C_Multi_Master I2CMM_IN=\$200! @@ -321,12 +325,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$548! USCI_B0 status word -I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CM_STATW=\$548! USCI_B0 status word +I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$55C! USCI_B0 Received Address Register +I2CM_ADDRX=\$55C! USCI_B0 Received Address Register I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address I2CM_IE=\$56A! USCI_B0 Interrupt Enable I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register @@ -334,12 +338,12 @@ I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$548! USCI_B0 status word -I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CS_STATW=\$548! USCI_B0 status word +I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$55C! USCI_B0 Received Address Register +I2CS_ADDRX=\$55C! USCI_B0 Received Address Register I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address I2CS_IE=\$56A! USCI_B0 Interrupt Enable I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register @@ -347,7 +351,7 @@ I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register CD_SD=\$10! P4.4 as Card Detect SD_CDIN=\$221! -CS_SD=\$20! P2.5 as Card Select +CS_SD=\$20! P2.5 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! diff --git a/inc/MSP_EXP430FR2433.asm b/inc/MSP_EXP430FR2433.asm index 50facde..b875538 100644 --- a/inc/MSP_EXP430FR2433.asm +++ b/inc/MSP_EXP430FR2433.asm @@ -51,7 +51,7 @@ ; MSP-EXP430FR2433 LAUNCHPAD <--> OUTPUT WORLD ; ====================================================================== -; +--4k7-< DeepRST switch <-- GND +; +--4k7-< DeepRST switch <-- GND ; | ; P1.4 - UCA0 TXD J101.6 - <-+-> RX UARTtoUSB bridge ; P1.5 - UCA0 RXD J101.8 - <---- TX UARTtoUSB bridge @@ -60,18 +60,18 @@ ; P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Master_Slave ; P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Master_Slave - -; P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5) + +; P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5) ; P2.0 - J2.11 - ----> SD_CS (Card Select) ; P2.1 - J2.12 - <---- SD_CD (Card Detect) ; P2.4 - UCA1 CLK J1.7 - ----> SD_CLK ; P2.5 - UCA1 SOMI J2.14 - <---- SD_SDO ; P2.6 - UCA1 SIMO J2.15 - ----> SD_SDI - + ; P3.1 - J2.13 - ----> SCL I2C Soft_Master ; P3.2 - J2.17 - <---> SDA I2C Soft_Master - + ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : I/O @@ -89,8 +89,8 @@ ; LED2 - P1.1 ; P1.4 - TXD TERMINAL + DEEP_RST ; P1.5 - RXD TERMINAL -; P1.0 - RTS TERMINAL -; P1.1 - CTS TERMINAL +; P1.0 - RTS TERMINAL +; P1.1 - CTS TERMINAL LED1_OUT .equ P1OUT LED1_DIR .equ P1DIR @@ -151,18 +151,15 @@ BUS_TERM .equ 60h SW1_IN .equ P2IN SW1 .equ 8 ; P2.3 = S1 -WIPE_IN .equ P2IN -IO_WIPE .equ 8 ; P2.3 = S1 = FORTH Deep_RST pin - MOV #-1,&PAREN ; all inputs with pull up/down resistors MOV #0FFFCh,&PAOUT ; all pins with pullup resistors else LED1/LED2 .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P1DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P1OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -197,7 +194,7 @@ SW2 .equ 80h ; P2.7 = S2 ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -; SYS code +; SYS code ; BIC #1,&SYSCFG0 ; enable write program in FRAM MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO @@ -207,138 +204,36 @@ SW2 .equ 80h ; P2.7 = S2 ; CS code for EXP430FR2433 -; to measure REFO frequency, output ACLK on P2.2: +; to measure REFO frequency, output ACLK on P2.2: ; BIS.B #4,&P2SEL1 ; BIS.B #4,&P2DIR ; result : REFO = 32.69kHz -; =================================================================== -; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ? -; (no problem with MSP430FR5xxx families without FLL). -; =================================================================== - .IF FREQUENCY = 0.5 -; MOV #058h,&CSCTL0 ; preset DCO = measured value @ 0x180 (88) -; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation - MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209) - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh - ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz -; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh - ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz - MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh - ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz -; ===================================== - .ELSEIF FREQUENCY = 1 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B1h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh - ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz - MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh - ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz -; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh - ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz -; ===================================== + .IFDEF LF_XTAL +; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) + MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV + BIS.B #03,&P2SEL0 ; P2.0 as XOUT, P2.1 as XIN + .ELSE + BIS #0010h,&CSCTL3 ; FLL select REFCLOCK +; MOV #0200h,&CSCTL4 ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value) + .ENDIF + BIC.B #-1,&CSCTL1 ; clear DCORSEL (Set 1MHZ DCORSEL), DCOFTRIM=0, ENable MODulation to reduce EMI + .IF FREQUENCY = 1 ; nothing else to do .ELSEIF FREQUENCY = 2 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B3h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh - ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz - MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch - ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz -; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh - ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz -; ===================================== + BIS.B #2,&CSCTL1 ; Set 2MHZ DCORSEL .ELSEIF FREQUENCY = 4 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B5h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h - ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz - - MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h - ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz - -; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah - ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz -; ===================================== + BIS.B #4,&CSCTL1 ; Set 4MHZ DCORSEL .ELSEIF FREQUENCY = 8 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B7h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h - ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz -; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h - ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz - MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h - ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz - -; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h - ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz - -; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value) -; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh - -; ===================================== + BIS.B #6,&CSCTL1 ; Set 8MHZ DCORSEL .ELSEIF FREQUENCY = 12 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B9h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #016Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 364+1) = 12.960 MHz ; measured : 11.xxxMHz -; MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz - MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz -; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz -; ===================================== + BIS.B #8,&CSCTL1 ; Set 12MHZ DCORSEL .ELSEIF FREQUENCY = 16 - -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00BBh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz -; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz - MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz -; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz -; ===================================== + BIS.B #10,&CSCTL1 ; Set 16MHZ DCORSEL .ELSEIF - .error "bad frequency setting, only 0.5,1,2,4,8,12,16 MHz" + .error "bad frequency setting, only 1,2,4,8,12,16 MHz" .ENDIF - - .IFDEF LF_XTAL -; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) - MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV - BIS.B #03,&P2SEL0 ; P2.0 as XOUT, P2.1 as XIN - .ELSE - BIS #0010h,&CSCTL3 ; FLL select REFCLOCK - MOV #0200h,&CSCTL4 ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value) - .ENDIF - +; MOV #INT(FREQUENCY*1000000/32768)-1,&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight lower + MOV #INT(FREQUENCY*1000000/32768),&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight upper MOV #128,X ; 128* 3 ms = 384 ms delay, because FLL lock time = 280 ms ClockWaitX MOV &FREQ_KHZ,Y ; ClockWaitY SUB #1,Y ;1 diff --git a/inc/MSP_EXP430FR2433.pat b/inc/MSP_EXP430FR2433.pat index 4017a0f..5b862e9 100644 --- a/inc/MSP_EXP430FR2433.pat +++ b/inc/MSP_EXP430FR2433.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR2433! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -63,7 +63,7 @@ ! MSP-EXP430FR2433 LAUNCHPAD <--> OUTPUT WORLD ! ====================================================================== ! -! +--4k7-< DeepRST switch <-- GND +! +--4k7-< DeepRST switch <-- GND ! | ! P1.4 - UCA0 TXD J101.6 - <-+-> RX UARTtoUSB bridge ! P1.5 - UCA0 RXD J101.8 - <---- TX UARTtoUSB bridge @@ -76,21 +76,21 @@ ! P2.5 - UCA1 SOMI J2.14 - <---- SD_SDO ! P2.1 - J2.12 - <---- SD_CD (Card Detect) ! P2.0 - J2.11 - ----> SD_CS (Card Select) -! +! ! P1.3 - UCB0 SCL J1.9 - ----> SCL I2C Slave ! P1.2 - UCB0 SDA J1.10 - <---> SDA I2C Slave -! +! ! P3.1 - J2.13 - ----> SCL I2C SoftMaster ! P3.2 - J2.17 - <---> SDA I2C SoftMaster -! -! P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5) +! +! P2.2 - ACLK J2.18 - <---- TSSOP32236 (IR RC5) ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=\$30! ; P1.4 = TX, P1.5 = RX TERM_IN=\$200! @@ -100,21 +100,21 @@ TERM_SEL=\$20A! \SEL0 TERM_VEC=\$FFE4! \ UCA0 WAKE_UP=1! \ RX int -TERM_CTLW0=\$500! \ eUSCI_A control word 0 -TERM_CTLW1=\$502! \ eUSCI_A control word 1 -TERM_BRW=\$506! -TERM_BR0=\$506! \ eUSCI_A baud rate 0 -TERM_BR1=\$507! \ eUSCI_A baud rate 1 -TERM_MCTLW=\$508! \ eUSCI_A modulation control -TERM_STATW=\$50A! \ eUSCI_A status -TERM_RXBUF=\$50C! \ eUSCI_A receive buffer -TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer -TERM_ABCTL=\$510! \ eUSCI_A LIN control -TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control -TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control -TERM_IE=\$51A! \ eUSCI_A interrupt enable -TERM_IFG=\$51C! \ eUSCI_A interrupt flags -TERM_IV=\$51E! \ eUSCI_A interrupt vector word +TERM_CTLW0=\$500! \ eUSCI_A control word 0 +TERM_CTLW1=\$502! \ eUSCI_A control word 1 +TERM_BRW=\$506! +TERM_BR0=\$506! \ eUSCI_A baud rate 0 +TERM_BR1=\$507! \ eUSCI_A baud rate 1 +TERM_MCTLW=\$508! \ eUSCI_A modulation control +TERM_STATW=\$50A! \ eUSCI_A status +TERM_RXBUF=\$50C! \ eUSCI_A receive buffer +TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer +TERM_ABCTL=\$510! \ eUSCI_A LIN control +TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control +TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control +TERM_IE=\$51A! \ eUSCI_A interrupt enable +TERM_IFG=\$51C! \ eUSCI_A interrupt flags +TERM_IV=\$51E! \ eUSCI_A interrupt vector word RTS=1! P1.0 CTS=2! P1.1 @@ -133,20 +133,20 @@ LED2_DIR=\$204! LED2=2! P1.1 LED2 green SW1_IN=\$201! -SW1=8! P2.3 = S1 +SW1=8! P2.3 = S1 WIPE_IN=\$201! -IO_WIPE=8! P2.3 = S1 = FORTH Deep_RST pin +IO_WIPE=8! P2.3 = S1 = FORTH Deep_RST pin SW2_IN=\$201! SW2=\$80! P2.7 !IR_RC5 -IR_IN=\$201! -IR_OUT=\$203! -IR_DIR=\$205! -IR_REN=\$209! +IR_IN=\$201! +IR_OUT=\$203! +IR_DIR=\$205! +IR_REN=\$209! IR_IES=\$219! IR_IE=\$21B! IR_IFG=\$21D! @@ -161,7 +161,7 @@ I2CSM_DIR=\$224! I2CSM_REN=\$226! SM_SDA=4! P3.2 SM_SCL=2! P3.1 -SM_BUS=\$06! +SM_BUS=\$06! !I2C_Soft_Multi_Master I2CSMM_IN=\$220! @@ -170,14 +170,14 @@ I2CSMM_DIR=\$224! I2CSMM_REN=\$226! SMM_SDA=4! P3.2 SMM_SCL=2! P3.1 -SMM_BUS=\$06! +SMM_BUS=\$06! !I2C_Multi_Master I2CMM_IN=\$200! I2CMM_OUT=\$202! I2CMM_DIR=\$204! I2CMM_REN=\$206! -I2CMM_SEL=\$20A! SEL0 +I2CMM_SEL=\$20A! SEL0 I2CMM_VEC=\$FFE0! UCB0_VEC MM_SDA=\$04! P1.2 MM_SCL=\$08! P1.3 @@ -218,12 +218,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$548! USCI_B0 status word -I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CM_STATW=\$548! USCI_B0 status word +I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$55C! USCI_B0 Received Address Register +I2CM_ADDRX=\$55C! USCI_B0 Received Address Register I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address I2CM_IE=\$56A! USCI_B0 Interrupt Enable I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register @@ -231,12 +231,12 @@ I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$548! USCI_B0 status word -I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CS_STATW=\$548! USCI_B0 status word +I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$55C! USCI_B0 Received Address Register +I2CS_ADDRX=\$55C! USCI_B0 Received Address Register I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address I2CS_IE=\$56A! USCI_B0 Interrupt Enable I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register @@ -244,7 +244,7 @@ I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register CD_SD=2! ; P2.1 as Card Detect SD_CDIN=\$201! -CS_SD=1! ; P2.0 as Card Select +CS_SD=1! ; P2.0 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! diff --git a/inc/MSP_EXP430FR4133.asm b/inc/MSP_EXP430FR4133.asm index 4a2aff5..acbede8 100644 --- a/inc/MSP_EXP430FR4133.asm +++ b/inc/MSP_EXP430FR4133.asm @@ -30,7 +30,7 @@ ; P2 - P8.1 ACLK/A9 ; P3 - P1.1 UCA0 RXD ; P4 - P1.0 UCA0 TXD -; P5 - P2.7 +; P5 - P2.7 ; P6 - P8.0 SMCLK/A8 ; P7 - P5.1 UCB0 CLK ; P8 - P2.5 @@ -109,33 +109,33 @@ ; --------------------------------------------------- ; MSP - MSP-EXP430FR4133 LAUNCHPAD <--> OUTPUT WORLD ; --------------------------------------------------- -; P1.0 - LED1 red +; P1.0 - LED1 red ; P4.0 - LED2 green ; ; P1.2 - S1 -; P2.6 - S2 -; +-4k7-< DeepRST <-- GND +; P2.6 - S2 +; +-4k7-< DeepRST <-- GND ; | ; P1.0 - UCA0 TXD J101.8 --+-> RX UARTtoUSB bridge ; P1.1 - UCA0 RXD J101.10 <---- TX UARTtoUSB bridge ; P2.3 - RTS J101.14 ----> CTS UARTtoUSB bridge (if TERMINALCTSRTS option) ; VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ; GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge) -; +; ; P2.7 - J1.5 <---- OUT IR_Receiver (1 TSOP32236) -; -; P4.1 - LFXI 32768Hz quartz -; P4.2 - LFXO 32768Hz quartz +; +; P4.1 - LFXI 32768Hz quartz +; P4.2 - LFXO 32768Hz quartz ; ; P5.2 - UCB0 SDA/SIMO J2.6 <---> SDA I2C Slave ; P5.3 - UCB0 SCL/SOMI J2.7 <---- SCL I2C Slave -; +; ; P5.1 - UCB0 CLK J1.7 ----> orange SD_CLK ; P5.2 - UCB0 SDA/SIMO J2.6 ----> grey SD_SDI ; P5.3 - UCB0 SCL/SOMI J2.7 <---- purple SD_SDO ; P8.0 - J1.6 <---- violin SD_CD (Card Detect) ; P8.1 - J1.2 ----> brown SD_CS (Card Select) -; +; ; P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master ; P8.3 - Soft I2C_Master J1.10 <---> SCL software I2C Master @@ -179,7 +179,7 @@ RTS .set 8 ; P2.3 bit position CTS .set 10h ; P2.4 bit position .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P2DIR ; RTS as output high .IFDEF TERMINAL5WIRES @@ -203,9 +203,9 @@ SW2 .equ 40h ; P2.6 = S2 ; P4 configuration : ; P4.0 - LED2 green -; P4.1 - LFXI 32768Hz quartz -; P4.2 - LFXO 32768Hz quartz - +; P4.1 - LFXI 32768Hz quartz +; P4.2 - LFXO 32768Hz quartz + LED2_OUT .equ P4OUT LED2_DIR .equ P4IN LED2 .equ 1 ; P4.0 LED2 green @@ -249,7 +249,7 @@ SD_CDIN .equ P8IN SD_CSOUT .equ P8OUT SD_CSDIR .equ P8DIR CD_SD .equ 1 ; P8.0 -CS_SD .equ 2 ; P8.1 +CS_SD .equ 2 ; P8.1 ; reset state : Px{DIR,REN,SEL0,SEL1,SELC,IE,IFG,IV} = 0 ; Px{IN,OUT,IES} = ? @@ -268,7 +268,7 @@ CS_SD .equ 2 ; P8.1 ; ---------------------------------------------------------------------- ; POWER ON RESET SYS config ; ---------------------------------------------------------------------- -; SYS code +; SYS code ; BIC #1,&SYSCFG0 ; enable write program in FRAM MOV #0A500h,&SYSCFG0 ; enable write MAIN and INFO @@ -283,126 +283,31 @@ CS_SD .equ 2 ; P8.1 ; BIS.B #2,&P8DIR ; result : REFO = ? kHz - -; =================================================================== -; need to adjust FLLN (and DCO) for each device of MSP430fr2xxx family ? -; (no problem with MSP430FR5xxx families without FLL). -; =================================================================== - .IF FREQUENCY = 0.5 -; MOV #058h,&CSCTL0 ; preset DCO = measured value @ 0x180 (88) -; MOV #0001h,&CSCTL1 ; Set 1MHZ DCORSEL,disable DCOFTRIM,Modulation - MOV #1ED1h,&CSCTL0 ; preset MOD=31, DCO = measured value @ 0x180 (209) - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #100Dh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Dh - ; fCOCLKDIV = 32768 x (13+1) = 0.459 MHz ; measured : MHz -; MOV #100Eh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Eh - ; fCOCLKDIV = 32768 x (14+1) = 0.491 MHz ; measured : MHz - MOV #100Fh,&CSCTL2 ; Set FLLD=1 (DCOCLKCDIV=DCO/2),set FLLN=0Fh - ; fCOCLKDIV = 32768 x (15+1) = 0.524 MHz ; measured : MHz -; ===================================== - .ELSEIF FREQUENCY = 1 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B1h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B0h,&CSCTL1 ; Set 1MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #001Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Dh - ; fCOCLKDIV = 32768 x (29+1) = 0.983 MHz ; measured : 0.989MHz - MOV #001Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Eh - ; fCOCLKDIV = 32768 x (30+1) = 1.015 MHz ; measured : 1.013MHz -; MOV #001Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1Fh - ; fCOCLKDIV = 32768 x (31+1) = 1.049 MHz ; measured : 1.046MHz -; ===================================== - .ELSEIF FREQUENCY = 2 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B3h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B2h,&CSCTL1 ; Set 2MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #003Bh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Bh - ; fCOCLKDIV = 32768 x (59+1) = 1.996 MHz ; measured : MHz - MOV #003Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Ch - ; fCOCLKDIV = 32768 x (60+1) = 1.998 MHz ; measured : MHz -; MOV #003Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=3Dh - ; fCOCLKDIV = 32768 x (61+1) = 2.031 MHz ; measured : MHz -; ===================================== - .ELSEIF FREQUENCY = 4 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B5h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B4h,&CSCTL1 ; Set 4MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #0078h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=78h - ; fCOCLKDIV = 32768 x (120+1) = 3.965 MHz ; measured : 3.96MHz - - MOV #0079h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=79h - ; fCOCLKDIV = 32768 x (121+1) = 3.997 MHz ; measured : 3.99MHz - -; MOV #007Ah,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=7Ah - ; fCOCLKDIV = 32768 x (122+1) = 4.030 MHz ; measured : 4.020MHz -; ===================================== - .ELSEIF FREQUENCY = 8 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B7h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B6h,&CSCTL1 ; Set 8MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #00F2h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F2h - ; fCOCLKDIV = 32768 x (242+1) = 7.963 MHz ; measured : 7.943MHz -; MOV #00F3h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F3h - ; fCOCLKDIV = 32768 x (243+1) = 7.995 MHz ; measured : 7.976MHz - MOV #00F4h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F4h - ; fCOCLKDIV = 32768 x (244+1) = 8.028 MHz ; measured : 8.009MHz -; MOV #00F5h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=F5h - ; fCOCLKDIV = 32768 x (245+1) = 8.061 MHz ; measured : 8.042MHz - -; MOV #00F8h,&CSCTL2 ; don't work with cp2102 (by low value) -; MOV #00FAh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=FAh - -; ===================================== - .ELSEIF FREQUENCY = 12 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00B9h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00B8h,&CSCTL1 ; Set 12MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #016Ch,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 364+1) = 12.960 MHz ; measured : 11.xxxMHz -; MOV #016Dh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 365+1) = 11.993 MHz ; measured : 11.xxxMHz - MOV #016Eh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 366+1) = 12.025 MHz ; measured : 12.xxxMHz -; MOV #016Fh,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 367+1) = 12.058 MHz ; measured : 12.xxxMHz -; ===================================== - .ELSEIF FREQUENCY = 16 -; MOV #100h,&CSCTL0 ; preset DCO = 256 -; MOV #00BBh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,disable Modulation - MOV #1EFFh,&CSCTL0 ; preset MOD=31, DCO=255 - MOV #00BAh,&CSCTL1 ; Set 16MHZ DCORSEL,enable DCOFTRIM=3h ,enable Modulation to reduce EMI -; ===================================== ; fCOCLKDIV = REFO x (FLLN+1) -; MOV #01E6h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E6h - ; fCOCLKDIV = 32768 x 486+1) = 15.958 MHz ; measured : 15.92MHz -; MOV #01E7h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E7h - ; fCOCLKDIV = 32768 x 487+1) = 15.991 MHz ; measured : 15.95MHz - MOV #01E8h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E8h - ; fCOCLKDIV = 32768 x 488+1) = 16.023 MHz ; measured : 15.99MHz -; MOV #01E9h,&CSCTL2 ; Set FLLD=0 (DCOCLKCDIV=DCO),set FLLN=1E9h - ; fCOCLKDIV = 32768 x 489+1) = 16.056 MHz ; measured : 16.02MHz -; ===================================== - .ELSEIF - .error "bad frequency setting, only 0.5,1,2,4,8,12,16 MHz" - .ENDIF - .IFDEF LF_XTAL ; MOV #0000h,&CSCTL3 ; FLL select XT1, FLLREFDIV=0 (default value) MOV #0000h,&CSCTL4 ; ACLOCK select XT1, MCLK & SMCLK select DCOCLKDIV BIS.B #06,&P4SEL0 ; P4.2 as XOUT, P4.1 as XIN .ELSE BIS #0010h,&CSCTL3 ; FLL select REFCLOCK - MOV #0200h,&CSCTL4 ; ACLOCK select VLOCLK, MCLK & SMCLK select DCOCLKDIV (default value) +; MOV #0100h,&CSCTL4 ; ACLOCK select REFO, MCLK & SMCLK select DCOCLKDIV (default value) + .ENDIF + BIC.B #-1,&CSCTL1 ; clear DCORSEL (Set 1MHZ DCORSEL), DCOFTRIM=0, ENable MODulation to reduce EMI + .IF FREQUENCY = 1 ; nothing else to do + .ELSEIF FREQUENCY = 2 + BIS.B #2,&CSCTL1 ; Set 2MHZ DCORSEL + .ELSEIF FREQUENCY = 4 + BIS.B #4,&CSCTL1 ; Set 4MHZ DCORSEL + .ELSEIF FREQUENCY = 8 + BIS.B #6,&CSCTL1 ; Set 8MHZ DCORSEL + .ELSEIF FREQUENCY = 12 + BIS.B #8,&CSCTL1 ; Set 12MHZ DCORSEL + .ELSEIF FREQUENCY = 16 + BIS.B #10,&CSCTL1 ; Set 16MHZ DCORSEL + .ELSEIF + .error "bad frequency setting, only 1,2,4,8,12,16 MHz" .ENDIF +; MOV #INT(FREQUENCY*1000000/32768)-1,&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight lower + MOV #INT(FREQUENCY*1000000/32768),&CSCTL2; set FLLD=0 (DCOCLKCDIV=DCO),set FLLN for frequency slight upper MOV #64,X ; 64* 3 ms = 192 ms delay, because FLL lock time = 120 ms ClockWaitX MOV &FREQ_KHZ,Y ; ClockWaitY SUB #1,Y ;1 diff --git a/inc/MSP_EXP430FR4133.pat b/inc/MSP_EXP430FR4133.pat index 9335c25..db0a3c3 100644 --- a/inc/MSP_EXP430FR4133.pat +++ b/inc/MSP_EXP430FR4133.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR4133! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -37,7 +37,7 @@ ! P2 - P8.1 ACLK/A9 ! P3 - P1.1 UCA0 RXD ! P4 - P1.0 UCA0 TXD -! P5 - P2.7 +! P5 - P2.7 ! P6 - P8.0 SMCLK/A8 ! P7 - P5.1 UCB0 CLK ! P8 - P2.5 @@ -117,7 +117,7 @@ ! MSP - MSP-EXP430FR4133 LAUNCHPAD <--> OUTPUT WORLD ! --------------------------------------------------- ! -! +-4k7-< DeepRST <-- GND +! +-4k7-< DeepRST <-- GND ! | ! P1.0 - UCA0 TXD J101.8 --+-> RX UARTtoUSB bridge ! P1.1 - UCA0 RXD J101.10 <---- TX UARTtoUSB bridge @@ -125,15 +125,15 @@ ! VCC - J101.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ! GND - J101.20 <---> GND (optional supply from UARTtoUSB bridge) ! -! P1.0 - STRAP JP1 MUST BE REMOVED (LED red) +! P1.0 - STRAP JP1 MUST BE REMOVED (LED red) ! ========================= ! ! P4.0 - LED green ! ! P1.2 - Switch SW1 <--- LCD contrast + (finger :-) -! P2.6 - Switch SW2 <--- LCD contrast - (finger ;-) +! P2.6 - Switch SW2 <--- LCD contrast - (finger ;-) +! ! -! ! GND - J2.1 <-------+---0V0----------> 1 LCD_Vss ! VCC - J1.1 >------ | --3V6-----+----> 2 LCD_Vdd ! | | @@ -150,23 +150,23 @@ ! P5.1 - J1.7 <------------------------> 12 LCD_DB5 ! P5.2 - J2.15 <------------------------> 13 LCD_DB5 ! P5.3 - J2.14 <------------------------> 14 LCD_DB7 -! -! +! +! ! P1.7 - J2.19 <---- OUT IR_Receiver (1 TSOP32236) -! -! P4.1 - LFXIN 32768Hz quartz -! P4.2 - LFXOUT 32768Hz quartz -! +! +! P4.1 - LFXIN 32768Hz quartz +! P4.2 - LFXOUT 32768Hz quartz +! ! VCC - J1.1 ----> VCC SD_CardAdapter ! GND - J2.1 <---> GND SD_CardAdapter -! P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK) +! P5.1 - UCB0 CLK J1.7 ----> CLK SD_CardAdapter (SCK) ! P8.1 - J1.2 ----> CS SD_CardAdapter (Card Select) ! P5.2 - UCB0 TXD/SIMO J2.15 ----> SDI SD_CardAdapter (MOSI) ! P5.3 - UCB0 RXD/SOMI J2.14 <---- SDO SD_CardAdapter (MISO) ! P8.0 - J1.6 <---- CD SD_CardAdapter (Card Detect) ! ! -! +! ! P8.2 - Soft I2C_Master J1.9 ----> SDA software I2C Master ! P8.3 - Soft I2C_Master J1.10 <---> SCL software I2C Master @@ -174,7 +174,7 @@ ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=3! ; P1.0 = TX, P1.1 = RX TERM_IN=\$200! @@ -184,21 +184,21 @@ TERM_SEL=\$20A! \ SEL0 TERM_VEC=\$FFEC! \ UCA0 WAKE_UP=1! \ RX int -TERM_CTLW0=\$500! \ eUSCI_A control word 0 -TERM_CTLW1=\$502! \ eUSCI_A control word 1 -TERM_BRW=\$506! -TERM_BR0=\$506! \ eUSCI_A baud rate 0 -TERM_BR1=\$507! \ eUSCI_A baud rate 1 -TERM_MCTLW=\$508! \ eUSCI_A modulation control -TERM_STATW=\$50A! \ eUSCI_A status -TERM_RXBUF=\$50C! \ eUSCI_A receive buffer -TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer -TERM_ABCTL=\$510! \ eUSCI_A LIN control -TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control -TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control -TERM_IE=\$51A! \ eUSCI_A interrupt enable -TERM_IFG=\$51C! \ eUSCI_A interrupt flags -TERM_IV=\$51E! \ eUSCI_A interrupt vector word +TERM_CTLW0=\$500! \ eUSCI_A control word 0 +TERM_CTLW1=\$502! \ eUSCI_A control word 1 +TERM_BRW=\$506! +TERM_BR0=\$506! \ eUSCI_A baud rate 0 +TERM_BR1=\$507! \ eUSCI_A baud rate 1 +TERM_MCTLW=\$508! \ eUSCI_A modulation control +TERM_STATW=\$50A! \ eUSCI_A status +TERM_RXBUF=\$50C! \ eUSCI_A receive buffer +TERM_TXBUF=\$50E! \ eUSCI_A transmit buffer +TERM_ABCTL=\$510! \ eUSCI_A LIN control +TERM_IRTCTL=\$512! \ eUSCI_A IrDA transmit control +TERM_IRRCTL=\$513! \ eUSCI_A IrDA receive control +TERM_IE=\$51A! \ eUSCI_A interrupt enable +TERM_IFG=\$51C! \ eUSCI_A interrupt flags +TERM_IV=\$51E! \ eUSCI_A interrupt vector word RTS=8! ; P2.3 CTS=\$10! ; P2.4 @@ -262,10 +262,10 @@ LCD_DB=\$0F! P5.0-3 LCD_DATA_BUS !IR_RC5 input !------------ -IR_IN=\$200! -IR_OUT=\$202! -IR_DIR=\$204! -IR_REN=\$206! +IR_IN=\$200! +IR_OUT=\$202! +IR_DIR=\$204! +IR_REN=\$206! IR_IES=\$218! IR_IE=\$21A! IR_IFG=\$21C! @@ -340,12 +340,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CM_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$548! USCI_B0 status word -I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CM_STATW=\$548! USCI_B0 status word +I2CM_TBCNT=\$54A! USCI_B0 byte counter threshold I2CM_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$55C! USCI_B0 Received Address Register +I2CM_ADDRX=\$55C! USCI_B0 Received Address Register I2CM_I2CSA=\$560! USCI_B0 I2C Slave Address I2CM_IE=\$56A! USCI_B0 Interrupt Enable I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register @@ -353,18 +353,18 @@ I2CM_IFG=\$56C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$540! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$542! USCI_B0 Control Word Register 1 I2CS_BRW=\$546! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$548! USCI_B0 status word -I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold +I2CS_STATW=\$548! USCI_B0 status word +I2CS_TBCNT=\$54A! USCI_B0 byte counter threshold I2CS_RXBUF=\$54C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$54E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$554! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$55C! USCI_B0 Received Address Register +I2CS_ADDRX=\$55C! USCI_B0 Received Address Register I2CS_I2CSA=\$560! USCI_B0 I2C Slave Address I2CS_IE=\$56A! USCI_B0 Interrupt Enable I2CS_IFG=\$56C! USCI_B0 Interrupt Flags Register -CD_SD=2! ; P8.1 as Card Detect +CD_SD=2! ; P8.1 as Card Detect SD_CDIN=\$261! CS_SD=1! ; P8.0 as Card Select diff --git a/inc/MSP_EXP430FR5739.asm b/inc/MSP_EXP430FR5739.asm index 586e67a..475ea35 100644 --- a/inc/MSP_EXP430FR5739.asm +++ b/inc/MSP_EXP430FR5739.asm @@ -1,7 +1,7 @@ ; -*- coding: utf-8 -*- ; ---------------------------------------------------------------------- -; MSP_EXP430FR739.asm +; MSP_EXP430FR739.asm ; ---------------------------------------------------------------------- ; ---------------------------------------------------------------------- ; MSP430FR57xx BOOTSTRAP @@ -12,7 +12,7 @@ ; Buffer size for Core Commands : 260 bytes ; Notable Information ; 1. TX and RX pins are noted in the device data sheet -; 2. A mass erase command or incorrect password triggers a BSL reset. +; 2. A mass erase command or incorrect password triggers a BSL reset. ; This resets the BSL state to the default settings (9600 baud, password locked) ; Known Bugs ; 1. The baud rate of 115k cannot be ensured across all clock, voltage, and temperature variations @@ -105,7 +105,7 @@ ; ; P4.0 - Switch S1 <--- LCD contrast + (finger :-) ; P4.1 - Switch S2 <--- LCD contrast - (finger :-) -; +; ; GND <-------+---0V0----------> 1 LCD_Vss ; VCC >------ | --3V6-----+----> 2 LCD_Vdd ; | | @@ -123,25 +123,25 @@ ; P1.2 - SV1.3 <------------------------> 13 LCD_DB5 ; P1.3 - SV1.8 <------------------------> 14 LCD_DB7 ; -; PJ.4 - LFXI 32768Hz quartz -; PJ.5 - LFXO 32768Hz quartz -; PJ.6 - HFXI -; PJ.7 - HFXO -; +--4k7-< DeepRST <-- GND +; PJ.4 - LFXI 32768Hz quartz +; PJ.5 - LFXO 32768Hz quartz +; PJ.6 - HFXI +; PJ.7 - HFXO +; +--4k7-< DeepRST <-- GND ; | ; P2.0 - UCA0 TXD SV2.11 --+-> RX UARTtoUSB bridge ; P2.1 - UCA0 RXD SV2.8 <---- TX UARTtoUSB bridge ; VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ; GND - <---> GND (optional supply from UARTtoUSB bridge) -; +; ; --------------------------------------------------------------------------- ; SD_CardAdapter not compatible with HARDWARE flow control for FORTH TERMINAL ; --------------------------------------------------------------------------- -; VCC - RF.2 -; VSS - RF.1 +; VCC - RF.2 +; VSS - RF.1 ; P2.2 - RF.16 <---- CD SD_CardAdapter (Card Detect) / RTS ; P2.3 - RF.10 ----> CS SD_CardAdapter (Card Select) / CTS -; P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK) +; P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK) ; P2.5 - UCA1 TXD/SIMO RF.7 ----> SDI SD_CardAdapter (MOSI) ; P2.6 - UCA1 RXD/SOMI RF.5 <---- SDO SD_CardAdapter (MISO) ; @@ -199,14 +199,14 @@ SD_CDIN .equ P2IN SD_CSOUT .equ P2OUT SD_CSDIR .equ P2DIR CD_SD .equ 4 ; P2.2 -CS_SD .equ 8 ; P2.3 +CS_SD .equ 8 ; P2.3 HANDSHAKOUT .equ P2OUT HANDSHAKIN .equ P2IN RTS .equ 4 ; P2.2 CTS .equ 8 ; P2.3 -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH ; P2.7 is used to power the accelerometer and NTC voltage divider ==> output low = power OFF @@ -215,11 +215,11 @@ CTS .equ 8 ; P2.3 MOV #07FEFh,&PAOUT ; all input pins with pull up resistor else P2.7 and P1.4 .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P2DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P2OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -244,9 +244,6 @@ CTS .equ 8 ; P2.3 SW1_IN .equ P4IN SW1 .equ 1 ; P4.0 = S1 -WIPE_IN .equ P4IN -IO_WIPE .equ 1 ; P4.0 = S1 = FORTH Deep_RST pin - SW2_IN .equ P4IN SW2 .equ 2 ; P4.1 = S2 diff --git a/inc/MSP_EXP430FR5739.pat b/inc/MSP_EXP430FR5739.pat index d50a3a9..0a8992c 100644 --- a/inc/MSP_EXP430FR5739.pat +++ b/inc/MSP_EXP430FR5739.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR5739! to change file type !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -95,7 +95,7 @@ ! ! P4.0 - Switch S1 <--- LCD contrast + (finger :-) ! P4.1 - Switch S2 <--- LCD contrast - (finger :-) -! +! ! GND <-------+---0V0----------> 1 LCD_Vss ! VCC >------ | --3V6-----+----> 2 LCD_Vdd ! | | @@ -113,22 +113,22 @@ ! P1.2 - SV1.3 <------------------------> 13 LCD_DB5 ! P1.3 - SV1.8 <------------------------> 14 LCD_DB7 ! -! PJ.4 - LFXI 32768Hz quartz -! PJ.5 - LFXO 32768Hz quartz -! PJ.6 - HFXI -! PJ.7 - HFXO -! +--4k7-< DeepRST <-- GND +! PJ.4 - LFXI 32768Hz quartz +! PJ.5 - LFXO 32768Hz quartz +! PJ.6 - HFXI +! PJ.7 - HFXO +! +--4k7-< DeepRST <-- GND ! | ! P2.0 - UCA0 TXD SV2.11 --+-> RX UARTtoUSB bridge ! P2.1 - UCA0 RXD SV2.8 <---- TX UARTtoUSB bridge ! VCC - <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ! GND - <---> GND (optional supply from UARTtoUSB bridge) -! -! VCC - RF.2 -! VSS - RF.1 +! +! VCC - RF.2 +! VSS - RF.1 ! P2.2 - RF.16 <---- CD SD_CardAdapter (Card Detect) ! P2.3 - RF.10 ----> CS SD_CardAdapter (Card Select) -! P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK) +! P2.4 - UCA1 CLK RF.14 ----> CLK SD_CardAdapter (SCK) ! P2.5 - UCA1 TXD/SIMO RF.7 ----> SDI SD_CardAdapter (MOSI) ! P2.6 - UCA1 RXD/SOMI RF.5 <---- SDO SD_CardAdapter (MISO) ! @@ -140,7 +140,7 @@ ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=3! \ P2.0 = TX, P2.1 = RX TERM_IN=\$201! @@ -222,10 +222,10 @@ WDT_TIM_CCR0=\$352! TA0CCR0 WDT_TIM_EX0=\$360! TA0EX0 WDT_TIM_0_VEC=\$FFEA! TA0_0_VEC -IR_IN=\$201! -IR_OUT=\$203! -IR_DIR=\$205! -IR_REN=\$207! +IR_IN=\$201! +IR_OUT=\$203! +IR_DIR=\$205! +IR_REN=\$207! IR_IES=\$219! IR_IE=\$21B! IR_IFG=\$21D! @@ -307,12 +307,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$648! USCI_B0 status word -I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CM_STATW=\$648! USCI_B0 status word +I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$65C! USCI_B0 Received Address Register +I2CM_ADDRX=\$65C! USCI_B0 Received Address Register I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address I2CM_IE=\$66A! USCI_B0 Interrupt Enable I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register @@ -320,12 +320,12 @@ I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$648! USCI_B0 status word -I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CS_STATW=\$648! USCI_B0 status word +I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$65C! USCI_B0 Received Address Register +I2CS_ADDRX=\$65C! USCI_B0 Received Address Register I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address I2CS_IE=\$66A! USCI_B0 Interrupt Enable I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register @@ -334,7 +334,7 @@ I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register CD_SD=4! P2.2 as Card Detect SD_CDIN=\$201! -CS_SD=8! P2.3 as Card Select +CS_SD=8! P2.3 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! diff --git a/inc/MSP_EXP430FR5969.asm b/inc/MSP_EXP430FR5969.asm index 2d09033..98f39b3 100644 --- a/inc/MSP_EXP430FR5969.asm +++ b/inc/MSP_EXP430FR5969.asm @@ -108,7 +108,7 @@ ; P4.5 - Switch S1 <--- LCD contrast + (finger :-) ; P1.1 - Switch S2 <--- LCD contrast - (finger ;-) - + ; GND - J1.2 <-------+---0V0----------> 1 LCD_Vss ; VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd ; | | @@ -125,23 +125,23 @@ ; PJ.1 - J3.3 <---------red------------> 12 LCD_DB5 ; PJ.2 - J3.5 <---------orange---------> 13 LCD_DB5 ; PJ.3 - J3.7 <---------yellow---------> 14 LCD_DB7 - -; +--4k7-< DeepRST <-- GND + +; +--4k7-< DeepRST <-- GND ; | ; P2.0 - UCA0 TXD J13.8 <-+->white--> RX UARTtoUSB bridge ; P2.1 - UCA0 RXD J13.10 <----green--- TX UARTtoUSB bridge ; P4.1 - RTS J13.14 -----blue---> CTS UARTtoUSB bridge (optional hardware control flow) ; VCC - J13.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ; GND - J13.20 <---> GND (optional supply from UARTtoUSB bridge) - + ; VCC - J11.1 ----> VCC SD_CardAdapter ; GND - J12.3 <---> GND SD_CardAdapter -; P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK) +; P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK) ; P2.5 - UCA1 TXD/SIMO J4.4 ----> SDI SD_CardAdapter (MOSI) ; P2.6 - UCA1 RXD/SOMI J4.3 <---- SDO SD_CardAdapter (MISO) ; P4.3 - J4.5 ----> CS SD_CardAdapter (Card Select) ; P4.2 - J4.2 <---- CD SD_CardAdapter (Card Detect) -; +; ; P4.0 use is not compatible with core option "TERMINAL5WIRES" ; P4.0 - J3.10 <---- OUT IR_Receiver (1 TSOP32236) ───┐ ; └┌───┐ @@ -157,11 +157,11 @@ ; P1.6 - UCB0 SDA/SIMO J5.15 <---> SDA I2C MASTER/SLAVE ; P3.0 - J5.7 <---- free -; PJ.4 - LFXI 32768Hz quartz -; PJ.5 - LFXO 32768Hz quartz -; PJ.6 - HFXI -; PJ.7 - HFXO - +; PJ.4 - LFXI 32768Hz quartz +; PJ.5 - LFXO 32768Hz quartz +; PJ.6 - HFXI +; PJ.7 - HFXO + ; P2.3 - NC ; P2.7 - NC ; P3.1 - NC @@ -209,8 +209,8 @@ BUS_TERM .equ 0C0h .ENDIF .IFDEF UCA0_TERM -; P2.0 UCA0-TXD --> USB2UART RXD -; P2.1 UCA0-RXD <-- USB2UART TXD +; P2.0 UCA0-TXD --> USB2UART RXD +; P2.1 UCA0-RXD <-- USB2UART TXD TERM_IN .equ P2IN TERM_SEL .equ P2SEL1 TERM_REN .equ P2REN @@ -245,14 +245,11 @@ SD_CDIN .equ P4IN SD_CSOUT .equ P4OUT SD_CSDIR .equ P4DIR CD_SD .equ 4 ; P4.2 as Card Detect -CS_SD .equ 8 ; P4.3 as Chip Select +CS_SD .equ 8 ; P4.3 as Chip Select SW1_IN .equ P4IN SW1 .equ 20h ; P4.5 = S1 -WIPE_IN .equ P4IN -IO_WIPE .equ 20h ; P4.5 = S1 = FORTH Deep_RST pin - LED1_OUT .equ P4OUT LED1_DIR .equ P4DIR LED1 .equ 40h ; P4.6 LED1 red @@ -261,11 +258,11 @@ LED1 .equ 40h ; P4.6 LED1 red MOV #0BFFFh,&PBOUT ; all pins as input with pull up resistor else P4.6 .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P4DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P4OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES diff --git a/inc/MSP_EXP430FR5969.pat b/inc/MSP_EXP430FR5969.pat index b9a15e2..90f53ba 100644 --- a/inc/MSP_EXP430FR5969.pat +++ b/inc/MSP_EXP430FR5969.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR5969! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -41,7 +41,7 @@ ! P2 - P4.2 ! P3 - P2.6 UCA1 RX/SOMI ! P4 - P2.5 UCA1 TX/SIMO -! P5 - P4.3 +! P5 - P4.3 ! P6 - P2.4 UCA1 CLK ! P7 - P2.2 TB0.2 UCB0CLK ! P8 - P3.4 @@ -70,7 +70,7 @@ ! P9 P10 RX0 P2.1 (no strap) ! P11 P12 CTS P4.0 (no strap) ! P13 P14 RTS P4.1 (no strap) -! P15<->P16 V+ <-> VCC +! P15<->P16 V+ <-> VCC ! P17 P18 5V (no strap) ! P19---P20 GND-----VSS @@ -90,23 +90,23 @@ ! J13 jumpers : device <-> eZ-FET ! ------------------------------- -! P2 P1 NC NC +! P2 P1 NC NC ! P4<->P3 TEST <-> TEST -! P6<->P5 RST <-> RST +! P6<->P5 RST <-> RST ! P8 P7 P2.0 TX0 (no jumper) ! P10 P9 P2.1 RX0 (no jumper) ! P12 P11 P4.0 CTS (no jumper) ! P14 P13 P4.1 RTS (no jumper) -! P16<->P15 VCC <-> V+ +! P16<->P15 VCC <-> V+ ! P18 P17 5V 5V (no jumper) -! P20---P19 VSS-----GND +! P20---P19 VSS-----GND ! P4.6 - J6 - LED1 red ! P1.0 - LED2 green ! ! P4.5 - Switch S1 <--- LCD contrast + (finger :-) ! P1.1 - Switch S2 <--- LCD contrast - (finger ;-) -! +! ! GND - J1.2 <-------+---0V0----------> 1 LCD_Vss ! VCC - J1.3 >------ | --3V6-----+----> 2 LCD_Vdd ! | | @@ -123,18 +123,18 @@ ! PJ.1 - J3.3 <------------------------> 12 LCD_DB5 ! PJ.2 - J3.5 <------------------------> 13 LCD_DB6 ! PJ.3 - J3.7 <------------------------> 14 LCD_DB7 -! -! +--4k7-< DeepRST <-- GND +! +! +--4k7-< DeepRST <-- GND ! | ! P2.0 - UCA0 TXD J13.8 <-+-> RX UARTtoUSB bridge ! P2.1 - UCA0 RXD J13.10 <---- TX UARTtoUSB bridge ! P4.1 - RTS J13.14 ----> CTS UARTtoUSB bridge (optional hardware control flow) ! VCC - J13.16 <---- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !) ! GND - J13.20 <---> GND (optional supply from UARTtoUSB bridge) -! +! ! VCC - J11.1 ----> VCC SD_CardAdapter ! GND - J12.3 <---> GND SD_CardAdapter -! P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK) +! P2.4 - UCA1 CLK J4.6 ----> CLK SD_CardAdapter (SCK) ! P4.3 - J4.5 ----> CS SD_CardAdapter (Card Select) ! P2.5 - UCA1 TXD/SIMO J4.4 ----> SDI SD_CardAdapter (MOSI) ! P2.6 - UCA1 RXD/SOMI J4.3 <---- SDO SD_CardAdapter (MISO) @@ -152,11 +152,11 @@ ! P1.6 - UCB0 SDA/SIMO J5.15 <---> SDA I2C MASTER/SLAVE ! P3.0 - J5.7 <---- free ! -! PJ.4 - LFXI 32768Hz quartz -! PJ.5 - LFXO 32768Hz quartz -! PJ.6 - HFXI -! PJ.7 - HFXO -! +! PJ.4 - LFXI 32768Hz quartz +! PJ.5 - LFXO 32768Hz quartz +! PJ.6 - HFXI +! PJ.7 - HFXO +! ! P2.3 - NC ! P2.7 - NC ! P3.1 - NC @@ -179,7 +179,7 @@ ! ============================================ ! FORTH I/O : ! ============================================ -!TERMINAL +!TERMINAL BUS_TERM=3! \ P2.0 = TX, P2.1 = RX TERM_IN=\$201! @@ -189,21 +189,21 @@ TERM_SEL=\$20D! TERM_VEC=\$FFF0! \ UCA0 WAKE_UP=1! \ RX int -TERM_CTLW0=\$5C0! \ eUSCI_A control word 0 -TERM_CTLW1=\$5C2! \ eUSCI_A control word 1 -TERM_BRW=\$5C6! -TERM_BR0=\$5C6! \ eUSCI_A baud rate 0 -TERM_BR1=\$5C7! \ eUSCI_A baud rate 1 -TERM_MCTLW=\$5C8! \ eUSCI_A modulation control -TERM_STAT=\$5CA! \ eUSCI_A status -TERM_RXBUF=\$5CC! \ eUSCI_A receive buffer -TERM_TXBUF=\$5CE! \ eUSCI_A transmit buffer -TERM_ABCTL=\$5D0! \ eUSCI_A LIN control -TERM_IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control -TERM_IRRCTL=\$5D3! \ eUSCI_A IrDA receive control -TERM_IE=\$5DA! \ eUSCI_A interrupt enable -TERM_IFG=\$5DC! \ eUSCI_A interrupt flags -TERM_IV=\$5DE! \ eUSCI_A interrupt vector word +TERM_CTLW0=\$5C0! \ eUSCI_A control word 0 +TERM_CTLW1=\$5C2! \ eUSCI_A control word 1 +TERM_BRW=\$5C6! +TERM_BR0=\$5C6! \ eUSCI_A baud rate 0 +TERM_BR1=\$5C7! \ eUSCI_A baud rate 1 +TERM_MCTLW=\$5C8! \ eUSCI_A modulation control +TERM_STAT=\$5CA! \ eUSCI_A status +TERM_RXBUF=\$5CC! \ eUSCI_A receive buffer +TERM_TXBUF=\$5CE! \ eUSCI_A transmit buffer +TERM_ABCTL=\$5D0! \ eUSCI_A LIN control +TERM_IRTCTL=\$5D2! \ eUSCI_A IrDA transmit control +TERM_IRRCTL=\$5D3! \ eUSCI_A IrDA receive control +TERM_IE=\$5DA! \ eUSCI_A interrupt enable +TERM_IFG=\$5DC! \ eUSCI_A interrupt flags +TERM_IV=\$5DE! \ eUSCI_A interrupt vector word RTS=2! ; P4.1 CTS=1! ; P4.0 @@ -213,7 +213,7 @@ HANDSHAKOUT=\$223! CD_SD=4! P4.2 as Card Detect SD_CDIN=\$221! -CS_SD=8! P4.3 as Card Select +CS_SD=8! P4.3 as Card Select SD_CSOUT=\$223! SD_CSDIR=\$225! @@ -237,10 +237,10 @@ LED2=\$01! P1.0 ! init state : input with pullup resistor SW1_IN=\$221 -SW1=\$20! P4.5 = S1 +SW1=\$20! P4.5 = S1 WIPE_IN=\$221 -IO_WIPE=\$20! P4.5 = S1 = FORTH Deep_RST pin +IO_WIPE=\$20! P4.5 = S1 = FORTH Deep_RST pin ! init state : input with pullup resistor SW2_IN=\$200 @@ -353,12 +353,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$648! USCI_B0 status word -I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CM_STATW=\$648! USCI_B0 status word +I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$65C! USCI_B0 Received Address Register +I2CM_ADDRX=\$65C! USCI_B0 Received Address Register I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address I2CM_IE=\$66A! USCI_B0 Interrupt Enable I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register @@ -366,12 +366,12 @@ I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$648! USCI_B0 status word -I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CS_STATW=\$648! USCI_B0 status word +I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$65C! USCI_B0 Received Address Register +I2CS_ADDRX=\$65C! USCI_B0 Received Address Register I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address I2CS_IE=\$66A! USCI_B0 Interrupt Enable I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register diff --git a/inc/MSP_EXP430FR5972.asm b/inc/MSP_EXP430FR5972.asm index 8bdf083..c5e7f4e 100644 --- a/inc/MSP_EXP430FR5972.asm +++ b/inc/MSP_EXP430FR5972.asm @@ -30,7 +30,7 @@ ; P2 - P9.2 ESICH2 ; P3 - P4.3 UCA0 RXD ; P4 - P4.2 UCA0 TXD -; P5 - P3.2 UCB1 SCL +; P5 - P3.2 UCB1 SCL ; P6 - P9.3 ESICH3 ; P7 - P1.4 UCB0 CLK ; P8 - P2.0 TB0.6 @@ -106,7 +106,7 @@ ; P1.1 - Switch S1 <--- LCD contrast + (finger :-) ; P1.2 - Switch S2 <--- LCD contrast - (finger ;-) - + ; GND <-------+---0V0----------> 1 LCD_Vss ; VCC >------ | --3V3-----+----> 2 LCD_Vdd ; | | @@ -124,7 +124,7 @@ ; P9.5/A13/C13 -------------------------> 5 LCD_R/W ; P9.6/A14/C14 -------------------------> 6 LCD_EN -; +--4k7-< DeepRST <-- GND +; +--4k7-< DeepRST <-- GND ; | ; P3.4 - UCA1 TXD <-+-> RX UARTtoUSB bridge ; P3.5 - UCA1 RXD <---- TX UARTtoUSB bridge @@ -134,7 +134,7 @@ ; VCC - ----> VCC SD_CardAdapter ; GND - <---> GND SD_CardAdapter -; P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK) +; P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK) ; P2.6 - ----> CS SD_CardAdapter (Card Select) ; P2.0 - UCA0 TXD/SIMO ----> SDI SD_CardAdapter (MOSI) ; P2.1 - UCA0 RXD/SOMI <---- SDO SD_CardAdapter (MISO) @@ -157,11 +157,11 @@ ; P3.2 -UCB1 SCL/SOMI ----> free ; P3.3 - TA1.1 <---> free -; PJ.4 - LFXI 32768Hz quartz -; PJ.5 - LFXO 32768Hz quartz -; PJ.6 - HFXI -; PJ.7 - HFXO - +; PJ.4 - LFXI 32768Hz quartz +; PJ.5 - LFXO 32768Hz quartz +; PJ.6 - HFXI +; PJ.7 - HFXO + ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : I/O @@ -215,7 +215,7 @@ BUS_TERM .equ 0C0h SD_CDIN .equ P2IN SD_CSOUT .equ P2OUT SD_CSDIR .equ P2DIR -CS_SD .equ 40h ; P2.6 Chip Select +CS_SD .equ 40h ; P2.6 Chip Select CD_SD .equ 80h ; P2.7 Card Detect ; PORTx default wanted state : pins as input with pullup resistor @@ -256,11 +256,11 @@ BUS_TERM .equ 30h ; P3.5 = RX MOV #-1,&PBOUT ; all pins as input with resistor .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P3DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P3OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -313,7 +313,7 @@ LED2 .equ 80h ; P9.7 LED2 green ; PORT10 usage - + ; PORTx default wanted state : pins as input with pullup resistor MOV.B #-1,&P9REN ; all pins with pull resistors else P9.7 diff --git a/inc/MSP_EXP430FR5972.pat b/inc/MSP_EXP430FR5972.pat index 684fddd..b0e85bb 100644 --- a/inc/MSP_EXP430FR5972.pat +++ b/inc/MSP_EXP430FR5972.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR5972! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -26,7 +26,7 @@ ! ! P1.1 - Switch S1 <--- LCD contrast + (finger :-) ! P1.2 - Switch S2 <--- LCD contrast - (finger ;-) -! +! ! GND <-------+---0V0----------> 1 LCD_Vss ! VCC >------ | --3V3-----+----> 2 LCD_Vdd ! | | @@ -44,7 +44,7 @@ ! P9.5/A13/C13 -------------------------> 5 LCD_R/W ! P9.6/A14/C14 -------------------------> 6 LCD_EN ! -! +--4k7-< DeepRST <-- GND +! +--4k7-< DeepRST <-- GND ! | ! P3.4 - UCA1 TXD <-+-> RX UARTtoUSB bridge ! P3.5 - UCA1 RXD <---- TX UARTtoUSB bridge @@ -54,7 +54,7 @@ ! ! VCC - ----> VCC SD_CardAdapter ! GND - <---> GND SD_CardAdapter -! P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK) +! P2.2 - UCA0 CLK ----> CLK SD_CardAdapter (SCK) ! P2.6 - ----> CS SD_CardAdapter (Card Select) ! P2.0 - UCA0 TXD/SIMO ----> SDI SD_CardAdapter (MOSI) ! P2.1 - UCA0 RXD/SOMI <---- SDO SD_CardAdapter (MISO) @@ -77,11 +77,11 @@ ! P3.2 -UCB1 SCL/SOMI ----> free ! P3.3 - TA1.1 <---> free ! -! PJ.4 - LFXI 32768Hz quartz -! PJ.5 - LFXO 32768Hz quartz -! PJ.6 - HFXI -! PJ.7 - HFXO - +! PJ.4 - LFXI 32768Hz quartz +! PJ.5 - LFXO 32768Hz quartz +! PJ.6 - HFXI +! PJ.7 - HFXO + ! ============================================ ! FORTH I/O : @@ -120,7 +120,7 @@ HANDSHAKOUT=\$222! CD_SD=\$80! ; P2.7 as Card Detect SD_CDIN=\$201! -CS_SD=\$40! ; P2.6 as Card Select +CS_SD=\$40! ; P2.6 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! @@ -181,10 +181,10 @@ WDT_TIM_CCR0=\$352! TA0CCR0 WDT_TIM_EX0=\$360! TA0EX0 WDT_TIM_0_Vec=\$FFE8! TA0_0_Vec -IR_IN=\$221! -IR_OUT=\$223! -IR_DIR=\$225! -IR_REN=\$227! +IR_IN=\$221! +IR_OUT=\$223! +IR_DIR=\$225! +IR_REN=\$227! IR_IES=\$239! IR_IE=\$23B! IR_IFG=\$23D! @@ -198,7 +198,7 @@ I2CSM_DIR=\$204! I2CSM_REN=\$206! SM_SDA=8! P1.3 SM_SCL=\$20! P1.5 -SM_BUS=\$28! +SM_BUS=\$28! I2CSMM_IN=\$200! I2CSMM_OUT=\$202! @@ -206,7 +206,7 @@ I2CSMM_DIR=\$204! I2CSMM_REN=\$206! SMM_SDA=8! P1.3 SMM_SCL=\$20! P1.5 -SMM_BUS=\$28! +SMM_BUS=\$28! RC5_TIM_CTL=\$380! TA1CTL RC5_TIM_R=\$390! TA1R RC5_TIM_EX0=\$3A0! TA1EX0 @@ -220,7 +220,7 @@ I2CMM_SEL=\$20A! SEL0 I2CMM_Vec=\$FFEC! UCBO_Vec MM_SDA=\$40! P1.6 MM_SCL=\$80! P1.7 -MM_BUS=\$C0! +MM_BUS=\$C0! I2CM_IN=\$200! I2CM_OUT=\$202! @@ -230,7 +230,7 @@ I2CM_SEL=\$20A! SEL0 I2CM_Vec=\$FFEC! UCBO_Vec M_SDA=\$40! P1.6 M_SCL=\$80! P1.7 -M_BUS=\$C0! +M_BUS=\$C0! I2CS_IN=\$200! I2CS_OUT=\$202! @@ -255,12 +255,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$648! USCI_B0 status word -I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CM_STATW=\$648! USCI_B0 status word +I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$65C! USCI_B0 Received Address Register +I2CM_ADDRX=\$65C! USCI_B0 Received Address Register I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address I2CM_IE=\$66A! USCI_B0 Interrupt Enable I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register @@ -268,12 +268,12 @@ I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$648! USCI_B0 status word -I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CS_STATW=\$648! USCI_B0 status word +I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$65C! USCI_B0 Received Address Register +I2CS_ADDRX=\$65C! USCI_B0 Received Address Register I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address I2CS_IE=\$66A! USCI_B0 Interrupt Enable I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register diff --git a/inc/MSP_EXP430FR5994.asm b/inc/MSP_EXP430FR5994.asm index b2524c3..1760de3 100644 --- a/inc/MSP_EXP430FR5994.asm +++ b/inc/MSP_EXP430FR5994.asm @@ -11,7 +11,7 @@ ; 3V3 10-9 ; P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge ; +--4k7-< DeepRST <-- GND -; | +; | ; P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge ; /RST 4-3 ; TEST 2-1 @@ -19,18 +19,18 @@ ; ; P5.6 - sw1 <--- LCD contrast + (finger :-) ; P5.5 - sw2 <--- LCD contrast - (finger ;-) -; RST - sw3 +; RST - sw3 ; ; P1.0 - led1 red ; P1.1 - led2 green ; ; J1 - left ext. ; 3v3 -; P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236) +; P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236) ; P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS ; P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W ; P6.2/UCA3CLK -------------------------> 6 LCD_EN0 -; P1.3/TA1.2/UCB0STE/A3/C3 +; P1.3/TA1.2/UCB0STE/A3/C3 ; P5.2/UCB1CLK/TA4CLK ; P6.3/UCA3STE ; P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE @@ -39,23 +39,23 @@ ; J3 - left int. ; 5V ; GND -; P3.0/A12/C12 <------------------------> 11 LCD_DB4 +; P3.0/A12/C12 <------------------------> 11 LCD_DB4 ; P3.1/A13/C13 <------------------------> 12 LCD_DB5 ; P3.2/A14/C14 <------------------------> 13 LCD_DB6 ; P3.3/A15/C15 <------------------------> 14 LCD_DB7 ; P1.4/TB0.1/UCA0STE/A4/C4 -; P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation) +; P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation) ; P4.7 ; P8.0 ; ; J4 - right int. -; P3.7/TB0.6 -; P3.6/TB0.5 -; P3.5/TB0.4/COUT +; P3.7/TB0.6 +; P3.6/TB0.5 +; P3.5/TB0.4/COUT ; P3.4/TB0.3/SMCLK ; P7.3/UCB2STE/TA4.1 -; P2.6/TB0.1/UCA1RXD/UCA1SOMI -; P2.5/TB0.0/UCA1TXD/UCA1SIMO +; P2.6/TB0.1/UCA1RXD/UCA1SOMI +; P2.5/TB0.0/UCA1TXD/UCA1SIMO ; P4.3/A11 ; P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow) ; P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow) @@ -91,7 +91,7 @@ ; ----------------------------------------------- ; LCD config ; ----------------------------------------------- - + ; <-------+---0V0----------> 1 LCD_Vss ; >------ | --3V6-----+----> 2 LCD_Vdd ; | | @@ -144,8 +144,8 @@ BUS_SD .equ 04C0h ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0S .ENDIF .IFDEF UCA0_TERM ; see device.inc -; P2.0 UCA0-TXD --> USB2UART RXD -; P2.1 UCA0-RXD <-- USB2UART TXD +; P2.0 UCA0-TXD --> USB2UART RXD +; P2.1 UCA0-RXD <-- USB2UART TXD TERM_IN .equ P2IN TERM_SEL .equ P2SEL1 TERM_REN .equ P2REN @@ -163,7 +163,7 @@ BUS_TERM .equ 3 ; PORT4 FastForth usage SD_CSOUT .equ P4OUT SD_CSDIR .equ P4DIR -CS_SD .equ 1 ; P4.0 Chip Select +CS_SD .equ 1 ; P4.0 SD_card Chip Select HANDSHAKIN .equ P4IN HANDSHAKOUT .equ P4OUT @@ -174,11 +174,11 @@ CTS .equ 2 ; P4.1 BIS #-1,&PBOUT .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P4DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P4OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -193,12 +193,10 @@ CTS .equ 2 ; P4.1 ; P5.5 Switch S2 SW1_IN .set P5IN ; port SW1 .set 040h ; P5.6 bit position + SW2_IN .set P5IN ; port SW2 .set 020h ; P5.5 bit position -WIPE_IN .equ P5IN -IO_WIPE .equ 40h ; P5.6 = S1 = FORTH Deep_RST pin - ; PORT6 FastForth usage @@ -223,7 +221,7 @@ SCL .equ 2 ; P7.1 BUS_TERM .equ 3 .ENDIF -CD_SD .equ 4 ; P7.2 Card Detect +CD_SD .equ 4 ; P7.2 SD_Card Card Detect SD_CDIN .equ P7IN ; PORT8 FastForth usage diff --git a/inc/MSP_EXP430FR5994.pat b/inc/MSP_EXP430FR5994.pat index 45292be..04fe02d 100644 --- a/inc/MSP_EXP430FR5994.pat +++ b/inc/MSP_EXP430FR5994.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR5994! to change file type !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -24,7 +24,7 @@ ! 3V3 10-9 ! P2.1 UCA0_RX 8-7 <---- TX UARTtoUSB bridge ! +--4k7-< DeepRST <-- GND -! | +! | ! P2.0 UCA0_TX 6-5 <-+-> RX UARTtoUSB bridge ! /RST 4-3 ! TEST 2-1 @@ -32,18 +32,18 @@ ! P5.6 - sw1 <--- LCD contrast + (finger :-) ! P5.5 - sw2 <--- LCD contrast - (finger ;-) -! RST - sw3 +! RST - sw3 ! P1.0 - led1 red ! P1.1 - led2 green ! J1 - left ext. ! 3v3 -! P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236) +! P1.2/TA1.1/TA0CLK/COUT/A2/C2 <--- OUT IR_Receiver (1 TSOP32236) ! P6.1/UCA3RXD/UCA3SOMI -------------------------> 4 LCD_RS ! P6.0/UCA3TXD/UCA3SIMO -------------------------> 5 LCD_R/W ! P6.2/UCA3CLK -------------------------> 6 LCD_EN0 -! P1.3/TA1.2/UCB0STE/A3/C3 +! P1.3/TA1.2/UCB0STE/A3/C3 ! P5.2/UCB1CLK/TA4CLK ! P6.3/UCA3STE ! P7.1/UCB2SOMI/UCB2SCL ---> SCL I2C MASTER/SLAVE @@ -52,23 +52,23 @@ ! J3 - left int. ! 5V ! GND -! P3.0/A12/C12 <------------------------> 11 LCD_DB4 +! P3.0/A12/C12 <------------------------> 11 LCD_DB4 ! P3.1/A13/C13 <------------------------> 12 LCD_DB5 ! P3.2/A14/C14 <------------------------> 13 LCD_DB5 ! P3.3/A15/C15 <------------------------> 14 LCD_DB7 ! P1.4/TB0.1/UCA0STE/A4/C4 -! P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation) +! P1.5/TB0.2/UCA0CLK/A5/C5 >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation) ! P4.7 ! P8.0 ! J4 - right int. -! P3.7/TB0.6 -! P3.6/TB0.5 -! P3.5/TB0.4/COUT +! P3.7/TB0.6 +! P3.6/TB0.5 +! P3.5/TB0.4/COUT ! P3.4/TB0.3/SMCLK ! P7.3/UCB2STE/TA4.1 -! P2.6/TB0.1/UCA1RXD/UCA1SOMI -! P2.5/TB0.0/UCA1TXD/UCA1SIMO +! P2.6/TB0.1/UCA1RXD/UCA1SOMI +! P2.5/TB0.0/UCA1TXD/UCA1SIMO ! P4.3/A11 ! P4.2/A10 RTS ----> CTS UARTtoUSB bridge (optional hardware control flow) ! P4.1/A9 CTS <---- RTS UARTtoUSB bridge (optional hardware control flow) @@ -139,21 +139,21 @@ TERM_IN=\$201! TERM_REN=\$207! TERM_SEL=\$20D! ; SEL1 -TERM_CTLW0=\$5C0! \ eUSCI_A0 control word 0 -TERM_CTLW1=\$5C2! \ eUSCI_A0 control word 1 -TERM_BRW=\$5C6! -TERM_BR0=\$5C6! \ eUSCI_A0 baud rate 0 -TERM_BR1=\$5C7! \ eUSCI_A0 baud rate 1 -TERM_MCTLW=\$5C8! \ eUSCI_A0 modulation control -TERM_STATW=\$5CA! \ eUSCI_A0 status -TERM_RXBUF=\$5CC! \ eUSCI_A0 receive buffer -TERM_TXBUF=\$5CE! \ eUSCI_A0 transmit buffer -TERM_ABCTL=\$5D0! \ eUSCI_A0 LIN control -TERM_IRTCTL=\$5D2! \ eUSCI_A0 IrDA transmit control -TERM_IRRCTL=\$5D3! \ eUSCI_A0 IrDA receive control -TERM_IE=\$5DA! \ eUSCI_A0 interrupt enable -TERM_IFG=\$5DC! \ eUSCI_A0 interrupt flags -TERM_IV=\$5DE! \ eUSCI_A0 interrupt vector word +TERM_CTLW0=\$5C0! \ eUSCI_A0 control word 0 +TERM_CTLW1=\$5C2! \ eUSCI_A0 control word 1 +TERM_BRW=\$5C6! +TERM_BR0=\$5C6! \ eUSCI_A0 baud rate 0 +TERM_BR1=\$5C7! \ eUSCI_A0 baud rate 1 +TERM_MCTLW=\$5C8! \ eUSCI_A0 modulation control +TERM_STATW=\$5CA! \ eUSCI_A0 status +TERM_RXBUF=\$5CC! \ eUSCI_A0 receive buffer +TERM_TXBUF=\$5CE! \ eUSCI_A0 transmit buffer +TERM_ABCTL=\$5D0! \ eUSCI_A0 LIN control +TERM_IRTCTL=\$5D2! \ eUSCI_A0 IrDA transmit control +TERM_IRRCTL=\$5D3! \ eUSCI_A0 IrDA receive control +TERM_IE=\$5DA! \ eUSCI_A0 interrupt enable +TERM_IFG=\$5DC! \ eUSCI_A0 interrupt flags +TERM_IV=\$5DE! \ eUSCI_A0 interrupt vector word RTS=4! ; P4.2 CTS=2! ; P4.1 @@ -163,7 +163,7 @@ HANDSHAKOUT=\$223! CD_SD=4! ; P7.2 as Card Detect SD_CDIN=\$260! -CS_SD=1! ; P4.0 as Card Select +CS_SD=1! ; P4.0 as Card Select SD_CSOUT=\$223! SD_CSDIR=\$225! @@ -171,26 +171,26 @@ SD_SEL1=\$20C! ; word access, to configure UCB0 SD_REN=\$206! ; word access, to configure pullup resistors BUS_SD=\$04C0! ; pins P2.2 as UCB0CLK, P1.6 as UCB0SIMO & P1.7 as UCB0SOMI -SD_CTLW0=\$640! \ eUSCI_B0 control word 0 -SD_CTLW1=\$642! \ eUSCI_B0 control word 1 -SD_BRW=\$646! -SD_BR0=\$646! \ eUSCI_B0 bit rate 0 -SD_BR1=\$647! \ eUSCI_B0 bit rate 1 -SD_STATW=\$648! \ eUSCI_B0 status word -SD_NT0=\$649! \ eUSCI_B0 hardware count -SD_TBCNT=\$64A! \ eUSCI_B0 byte counter threshold -SD_RXBUF=\$64C! \ eUSCI_B0 receive buffer -SD_TXBUF=\$64E! \ eUSCI_B0 transmit buffer -SD_I2COA0=\$654! \ eUSCI_B0 I2C own address 0 -SD_I2COA1=\$656! \ eUSCI_B0 I2C own address 1 -SD_I2COA2=\$658! \ eUSCI_B0 I2C own address 2 -SD_I2COA3=\$65A! \ eUSCI_B0 I2C own address 3 -SD_ADDRX=\$65C! \ eUSCI_B0 received address -SD_ADDMASK=\$65E! \ eUSCI_B0 address mask -SD_I2CSA=\$660! \ eUSCI_B0 I2C slave address -SD_IE=\$66A! \ eUSCI_B0 interrupt enable -SD_IFG=\$66C! \ eUSCI_B0 interrupt flags -SD_IV=\$66E! \ eUSCI_B0 interrupt vector word +SD_CTLW0=\$640! \ eUSCI_B0 control word 0 +SD_CTLW1=\$642! \ eUSCI_B0 control word 1 +SD_BRW=\$646! +SD_BR0=\$646! \ eUSCI_B0 bit rate 0 +SD_BR1=\$647! \ eUSCI_B0 bit rate 1 +SD_STATW=\$648! \ eUSCI_B0 status word +SD_NT0=\$649! \ eUSCI_B0 hardware count +SD_TBCNT=\$64A! \ eUSCI_B0 byte counter threshold +SD_RXBUF=\$64C! \ eUSCI_B0 receive buffer +SD_TXBUF=\$64E! \ eUSCI_B0 transmit buffer +SD_I2COA0=\$654! \ eUSCI_B0 I2C own address 0 +SD_I2COA1=\$656! \ eUSCI_B0 I2C own address 1 +SD_I2COA2=\$658! \ eUSCI_B0 I2C own address 2 +SD_I2COA3=\$65A! \ eUSCI_B0 I2C own address 3 +SD_ADDRX=\$65C! \ eUSCI_B0 received address +SD_ADDMASK=\$65E! \ eUSCI_B0 address mask +SD_I2CSA=\$660! \ eUSCI_B0 I2C slave address +SD_IE=\$66A! \ eUSCI_B0 interrupt enable +SD_IFG=\$66C! \ eUSCI_B0 interrupt flags +SD_IV=\$66E! \ eUSCI_B0 interrupt vector word ! ============================================ @@ -247,10 +247,10 @@ WDT_TIM_CCR0=\$352! TA0CCR0 WDT_TIM_EX0=\$360! TA0EX0 WDT_TIM_0_VEC=\$FFEA! TA0_0_VEC -IR_IN=\$200! -IR_OUT=\$202! -IR_DIR=\$204! -IR_REN=\$206! +IR_IN=\$200! +IR_OUT=\$202! +IR_DIR=\$204! +IR_REN=\$206! IR_IES=\$208! IR_IE=\$20A! IR_IFG=\$20C! @@ -322,12 +322,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$6C0! USCI_B2 Control Word Register 0 I2CM_CTLW1=\$6C2! USCI_B2 Control Word Register 1 I2CM_BRW=\$6C6! USCI_B2 Baud Word Rate 0 -I2CM_STATW=\$6C8! USCI_B2 status word -I2CM_TBCNT=\$6CA! USCI_B2 byte counter threshold +I2CM_STATW=\$6C8! USCI_B2 status word +I2CM_TBCNT=\$6CA! USCI_B2 byte counter threshold I2CM_RXBUF=\$6CC! USCI_B2 Receive Buffer 8 I2CM_TXBUF=\$6CE! USCI_B2 Transmit Buffer 8 I2CM_I2COA0=\$6D4! USCI_B2 I2C Own Address 0 -I2CM_ADDRX=\$6DC! USCI_B2 Received Address Register +I2CM_ADDRX=\$6DC! USCI_B2 Received Address Register I2CM_I2CSA=\$6E0! USCI_B2 I2C Slave Address I2CM_IE=\$6EA! USCI_B2 Interrupt Enable I2CM_IFG=\$6EC! USCI_B2 Interrupt Flags Register @@ -335,12 +335,12 @@ I2CM_IFG=\$6EC! USCI_B2 Interrupt Flags Register I2CS_CTLW0=\$6C0! USCI_B2 Control Word Register 0 I2CS_CTLW1=\$6C2! USCI_B2 Control Word Register 1 I2CS_BRW=\$6C6! USCI_B2 Baud Word Rate 0 -I2CS_STATW=\$6C8! USCI_B2 status word -I2CS_TBCNT=\$6CA! USCI_B2 byte counter threshold +I2CS_STATW=\$6C8! USCI_B2 status word +I2CS_TBCNT=\$6CA! USCI_B2 byte counter threshold I2CS_RXBUF=\$6CC! USCI_B2 Receive Buffer 8 I2CS_TXBUF=\$6CE! USCI_B2 Transmit Buffer 8 I2CS_I2COA0=\$6D4! USCI_B2 I2C Own Address 0 -I2CS_ADDRX=\$6DC! USCI_B2 Received Address Register +I2CS_ADDRX=\$6DC! USCI_B2 Received Address Register I2CS_I2CSA=\$6E0! USCI_B2 I2C Slave Address I2CS_IE=\$6EA! USCI_B2 Interrupt Enable I2CS_IFG=\$6EC! USCI_B2 Interrupt Flags Register diff --git a/inc/MSP_EXP430FR6989.asm b/inc/MSP_EXP430FR6989.asm index f2db496..53cf5d1 100644 --- a/inc/MSP_EXP430FR6989.asm +++ b/inc/MSP_EXP430FR6989.asm @@ -30,7 +30,7 @@ ; P2 - P9.2 ESICH2 ; P3 - P4.3 UCA0 RXD ; P4 - P4.2 UCA0 TXD -; P5 - P3.2 UCB1 SCL +; P5 - P3.2 UCB1 SCL ; P6 - P9.3 ESICH3 ; P7 - P1.4 UCB0 CLK ; P8 - P2.0 TB0.6 @@ -149,7 +149,7 @@ ; P1.1 - Switch S1 <--- LCD contrast + (finger :-) ; P1.2 - Switch S2 <--- LCD contrast - (finger ;-) - + ; note : ESI1.1 = lowest left pin ; note : ESI1.2 is not connected to 3.3V ; GND/ESIVSS - ESI1.3 <-------+---0V0----------> 1 LCD_Vss @@ -169,7 +169,7 @@ ; P9.5/ESICI1 - ESI1.9 -------------------------> 5 LCD_R/W ; P9.6/ESICI2 - ESI1.8 -------------------------> 6 LCD_EN -; +--4k7-< DeepRST <-- GND +; +--4k7-< DeepRST <-- GND ; | ; P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge ; P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge @@ -179,7 +179,7 @@ ; VCC - J1.1 ----> VCC SD_CardAdapter ; GND - J2.20 <---> GND SD_CardAdapter -; P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK) +; P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK) ; P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select) ; P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI) ; P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO) @@ -202,11 +202,11 @@ ; P3.2 -UCB1 SCL/SOMI J1.5 ----> free ; P3.3 - TA1.1 J1.5 <---> free -; PJ.4 - LFXI 32768Hz quartz -; PJ.5 - LFXO 32768Hz quartz -; PJ.6 - HFXI -; PJ.7 - HFXO - +; PJ.4 - LFXI 32768Hz quartz +; PJ.5 - LFXO 32768Hz quartz +; PJ.6 - HFXI +; PJ.7 - HFXO + ; ---------------------------------------------------------------------- ; POWER ON RESET AND INITIALIZATION : I/O @@ -235,9 +235,6 @@ LED1 .equ 1 ; P1.0 LED1 red SW1_IN .set P1IN ; port SW1 .set 2 ; P1.1 = S1 -WIPE_IN .equ P1IN -IO_WIPE .equ 2 ; P1.1 = S1 = FORTH Deep_RST pin - ; P1.2 - Switch S2 SW2_IN .set P1IN ; port SW2 .set 4 ; P1.2 = S2 @@ -260,7 +257,7 @@ BUS_TERM .equ 0C0h SD_CDIN .equ P2IN SD_CSOUT .equ P2OUT SD_CSDIR .equ P2DIR -CS_SD .equ 40h ; P2.6 Chip Select +CS_SD .equ 40h ; P2.6 Chip Select CD_SD .equ 80h ; P2.7 Card Detect ; PORTx default wanted state : pins as input with pullup resistor @@ -301,11 +298,11 @@ BUS_TERM .equ 30h ; MOV #-1,&PBOUT ; all pins as input with resistor .IFDEF TERMINAL4WIRES -; RTS output is wired to the CTS input of UART2USB bridge +; RTS output is wired to the CTS input of UART2USB bridge ; configure RTS as output high to disable RX TERM during start FORTH BIS.B #RTS,&P3DIR ; RTS as output high .IFDEF TERMINAL5WIRES -; CTS input must be wired to the RTS output of UART2USB bridge +; CTS input must be wired to the RTS output of UART2USB bridge ; configure CTS as input low (true) to avoid lock when CTS is not wired BIC.B #CTS,&P3OUT ; CTS input pulled down .ENDIF ; TERMINAL5WIRES @@ -358,7 +355,7 @@ LED2 .equ 80h ; P9.7 LED2 green ; PORT10 usage - + ; PORTx default wanted state : pins as input with pullup resistor MOV #-1,&PEREN ; all pins with pull resistors else P9.7 diff --git a/inc/MSP_EXP430FR6989.pat b/inc/MSP_EXP430FR6989.pat index a3d6b83..1d81f21 100644 --- a/inc/MSP_EXP430FR6989.pat +++ b/inc/MSP_EXP430FR6989.pat @@ -4,7 +4,7 @@ \.f=\.4th for MSP_EXP430FR6989! to change file type ! !======================== -! remove comments +! remove comments !======================== \\*\n= \s\\*\n=\n @@ -26,7 +26,7 @@ ! ! P1.1 - Switch S1 <--- LCD contrast + (finger :-) ! P1.2 - Switch S2 <--- LCD contrast - (finger ;-) -! +! ! note : ESI1.1 = lowest left pin ! note : ESI1.2 is not connected to 3.3V ! GND J6.2 <-------+---0V0----------> 1 LCD_Vss @@ -46,7 +46,7 @@ ! P4.2 -------------------------> 5 LCD_R/W green ! P4.3 -------------------------> 6 LCD_EN blue ! -! +--4k7-< DeepRST <-- GND +! +--4k7-< DeepRST <-- GND ! | ! P3.4 - UCA1 TXD J101.8 <-+-> RX UARTtoUSB bridge ! P3.5 - UCA1 RXD J101.10 <---- TX UARTtoUSB bridge @@ -56,7 +56,7 @@ ! ! VCC - J1.1 ----> VCC SD_CardAdapter ! GND - J2.20 <---> GND SD_CardAdapter -! P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK) +! P2.2 - UCA0 CLK J4.35 ----> CLK SD_CardAdapter (SCK) ! P2.6 - J4.39 ----> CS SD_CardAdapter (Card Select) ! P2.0 - UCA0 TXD/SIMO J1.8 ----> SDI SD_CardAdapter (MOSI) ! P2.1 - UCA0 RXD/SOMI J2.19 <---- SDO SD_CardAdapter (MISO) @@ -79,10 +79,10 @@ ! P3.2 -UCB1 SCL/SOMI J1.5 ----> free ! P3.3 - TA1.1 J1.5 <---> free ! -! PJ.4 - LFXI 32768Hz quartz -! PJ.5 - LFXO 32768Hz quartz -! PJ.6 - HFXI -! PJ.7 - HFXO +! PJ.4 - LFXI 32768Hz quartz +! PJ.5 - LFXO 32768Hz quartz +! PJ.6 - HFXI +! PJ.7 - HFXO ! ============================================ @@ -122,7 +122,7 @@ HANDSHAKOUT=\$222! CD_SD=\$80! ; P2.7 as Card Detect SD_CDIN=\$201! -CS_SD=\$40! ; P2.6 as Card Select +CS_SD=\$40! ; P2.6 as Card Select SD_CSOUT=\$203! SD_CSDIR=\$205! @@ -183,10 +183,10 @@ WDT_TIM_CCR0=\$352! TA0CCR0 WDT_TIM_EX0=\$360! TA0EX0 WDT_TIM_0_Vec=\$FFE8! TA0_0_Vec -IR_IN=\$221! -IR_OUT=\$223! -IR_DIR=\$225! -IR_REN=\$227! +IR_IN=\$221! +IR_OUT=\$223! +IR_DIR=\$225! +IR_REN=\$227! IR_IES=\$239! IR_IE=\$23B! IR_IFG=\$23D! @@ -200,7 +200,7 @@ I2CSM_DIR=\$204! I2CSM_REN=\$206! SM_SDA=8! P1.3 SM_SCL=\$20! P1.5 -SM_BUS=\$28! +SM_BUS=\$28! I2CSMM_IN=\$200! I2CSMM_OUT=\$202! @@ -208,7 +208,7 @@ I2CSMM_DIR=\$204! I2CSMM_REN=\$206! SMM_SDA=8! P1.3 SMM_SCL=\$20! P1.5 -SMM_BUS=\$28! +SMM_BUS=\$28! RC5_TIM_CTL=\$380! TA1CTL RC5_TIM_R=\$390! TA1R RC5_TIM_EX0=\$3A0! TA1EX0 @@ -222,7 +222,7 @@ I2CMM_SEL=\$20A! SEL0 I2CMM_Vec=\$FFEC! UCBO_Vec MM_SDA=\$40! P1.6 MM_SCL=\$80! P1.7 -MM_BUS=\$C0! +MM_BUS=\$C0! I2CM_IN=\$200! I2CM_OUT=\$202! @@ -232,7 +232,7 @@ I2CM_SEL=\$20A! SEL0 I2CM_Vec=\$FFEC! UCBO_Vec M_SDA=\$40! P1.6 M_SCL=\$80! P1.7 -M_BUS=\$C0! +M_BUS=\$C0! I2CS_IN=\$200! I2CS_OUT=\$202! @@ -257,12 +257,12 @@ UCRXIFG0=1! eUSCI_B Receive Interrupt Flag I2CM_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CM_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CM_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CM_STATW=\$648! USCI_B0 status word -I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CM_STATW=\$648! USCI_B0 status word +I2CM_TBCNT=\$64A! USCI_B0 byte counter threshold I2CM_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CM_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CM_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CM_ADDRX=\$65C! USCI_B0 Received Address Register +I2CM_ADDRX=\$65C! USCI_B0 Received Address Register I2CM_I2CSA=\$660! USCI_B0 I2C Slave Address I2CM_IE=\$66A! USCI_B0 Interrupt Enable I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register @@ -270,12 +270,12 @@ I2CM_IFG=\$66C! USCI_B0 Interrupt Flags Register I2CS_CTLW0=\$640! USCI_B0 Control Word Register 0 I2CS_CTLW1=\$642! USCI_B0 Control Word Register 1 I2CS_BRW=\$646! USCI_B0 Baud Word Rate 0 -I2CS_STATW=\$648! USCI_B0 status word -I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold +I2CS_STATW=\$648! USCI_B0 status word +I2CS_TBCNT=\$64A! USCI_B0 byte counter threshold I2CS_RXBUF=\$64C! USCI_B0 Receive Buffer 8 I2CS_TXBUF=\$64E! USCI_B0 Transmit Buffer 8 I2CS_I2COA0=\$654! USCI_B0 I2C Own Address 0 -I2CS_ADDRX=\$65C! USCI_B0 Received Address Register +I2CS_ADDRX=\$65C! USCI_B0 Received Address Register I2CS_I2CSA=\$660! USCI_B0 I2C Slave Address I2CS_IE=\$66A! USCI_B0 Interrupt Enable I2CS_IFG=\$66C! USCI_B0 Interrupt Flags Register diff --git a/inc/TERMINALBAUDRATE.inc b/inc/TERMINALBAUDRATE.inc index 95f2c42..95e8eb1 100644 --- a/inc/TERMINALBAUDRATE.inc +++ b/inc/TERMINALBAUDRATE.inc @@ -305,7 +305,7 @@ TERMMCTLW_INI .equ 04900h ; ; TERMBRW=UCBR0, TERMMCTLW= (UCBRS0<<8)|(UCBRF0<<4)|UCOS16 ; TERMBRW_INI .equ 3 ; TERMMCTLW_INI .equ 04400h -; +; ; .CASE 806400 ; PL2303TA baudrate ; ; Configure UART_TERM @ 806400 bauds / 2MHz ; ; Configure UART_TERM @ 403200 bauds / 1MHz @@ -513,7 +513,7 @@ TERMMCTLW_INI .equ 0D600h ; Configure UART_TERM @ 1000000 bauds / 8MHz ; Configure UART_TERM @ 2000000 bauds / 16MHz ; N = 16000000/2000000 = 8 ==> {UCOS16=0, UCBR0=int(N)=8, UCBRF0=dont_care=0 UCBRS0=fn(frac(N))=fn(0.00000)=0x00 -TERMBRW_INI .equ 8 +TERMBRW_INI .equ 8 TERMMCTLW_INI .equ 00000h .CASE 1228800 ; PL2303TA baudrate @@ -542,7 +542,7 @@ TERMMCTLW_INI .equ 04900h ; ; TERMBRW=UCBR0, TERMMCTLW= (UCBRS0<<8)|(UCBRF0<<4)|UCOS16 ; TERMBRW_INI .equ 3 ; TERMMCTLW_INI .equ 04400h -; +; ; .CASE 3000000 ; PL2303TA baudrate ; ; Configure UART_TERM @ 3000000 bauds / 8MHz ; ; Configure UART_TERM @ 6000000 bauds / 16MHz @@ -966,7 +966,7 @@ TERMMCTLW_INI .equ 0D600h .CASE 2000000 ; Configure UART_TERM @ 2000000 bauds / 16MHz ; N = 16000000/2000000 = 8 ==> {UCOS16=0, UCBR0=int(N)=8, UCBRF0=dont_care=0 UCBRS0=fn(frac(N))=fn(0.00000)=0x00 -TERMBRW_INI .equ 8 +TERMBRW_INI .equ 8 TERMMCTLW_INI .equ 00000h .CASE 2457600 ; PL2303TA baudrate @@ -1002,7 +1002,7 @@ TERMMCTLW_INI .equ 0 ; ; TERMBRW=UCBR0, TERMMCTLW= (UCBRS0<<8)|(UCBRF0<<4)|UCOS16 ; TERMBRW_INI .equ 3 ; TERMMCTLW_INI .equ 02100h -; +; ; .CASE 6000000 ; PL2303TA baudrate ; ; Configure UART_TERM @ 6000000 bauds / 24MHz ; ; N = 16000000/6000000 = 2.6666.. ==> {UCOS16=0, UCBR0=int(N)=2, UCBRF0=dont_care=0 UCBRS0=fn(frac(N))=fn(0.6666)=0xB6 @@ -1303,15 +1303,9 @@ TERMMCTLW_INI .equ 0EE00h TERMBRW_INI .equ 4 TERMMCTLW_INI .equ 0 -; .CASE 7500000 ; PL2303TA baudrate -; ; Configure UART_TERM @ 7500000 bauds / 24MHz -; ; N = 24000000/7500000 = 3.2 ==> {UCOS16=0, UCBR0=int(N)=3, UCBRF0=dont_care=0 UCBRS0=fn(frac(N))=fn(0.2)=0x11 -; TERMBRW_INI .equ 3 -; TERMMCTLW_INI .equ 01100h - .ELSECASE .error "UART_TERM / 24 MHz : baudrate not implemented" .ENDCASE ; UART_TERM / 24MHz baudrates - .ELSEIF + .ELSEIF .error "UART_TERM frequency not implemented" .ENDIF ; frequency \ No newline at end of file diff --git a/inc/TargetInit.asm b/inc/TargetInit.asm index 18656d0..9a43ce2 100644 --- a/inc/TargetInit.asm +++ b/inc/TargetInit.asm @@ -1,31 +1,32 @@ -; Target.asm +; -*- coding: utf-8 -*- +; TargetInit.asm ; to Init I/O, Clock, FRAM, RTC, ... only for FastForth and SD_options use .IFDEF MSP_EXP430FR5739 - .include "MSP_EXP430FR5739.asm" + .include "MSP_EXP430FR5739.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR5969 - .include "MSP_EXP430FR5969.asm" + .include "MSP_EXP430FR5969.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR5994 - .include "MSP_EXP430FR5994.asm" + .include "MSP_EXP430FR5994.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR6989 - .INCLUDE "MSP_EXP430FR6989.asm" + .INCLUDE "MSP_EXP430FR6989.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR4133 - .INCLUDE "MSP_EXP430FR4133.asm" + .INCLUDE "MSP_EXP430FR4133.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR2433 - .include "MSP_EXP430FR2433.asm" + .include "MSP_EXP430FR2433.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF MSP_EXP430FR2355 - .include "MSP_EXP430FR2355.asm" + .include "MSP_EXP430FR2355.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF LP_MSP430FR2476 - .include "LP_MSP430FR2476.asm" + .include "LP_MSP430FR2476.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .IFDEF CHIPSTICK_FR2433 - .include "CHIPSTICK_FR2433.asm" + .include "CHIPSTICK_FR2433.asm" ; choose always Px0 to Px3 as RTS pin!!! .ENDIF .save .listing off @@ -33,3 +34,51 @@ ; add here your target.asm item: ;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .restore + .IFDEF MY_MSP430FR5734 + .include "MY_MSP430FR5734.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF MY_MSP430FR5738 + .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF MY_MSP430FR5738_1 + .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF MY_MSP430FR5738_2 + .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF MY_MSP430FR5948 + .include "MY_MSP430FR5948.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF MY_MSP430FR5948_1 + .include "MY_MSP430FR5948_1.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_2021_03_02 + .include "JMJ_BOX_2021_03_02.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_2021_05_04 + .include "JMJ_BOX_2021_05_04.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX + .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_2018_10_29 + .include "JMJ_BOX_2018_10_29.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_2018_08 + .include "MY_MSP430FR5738.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_GUILLAUME + .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF JMJ_BOX_FAVRE + .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF PA8_PA_MSP430 + .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF PA_PA_MSP430 + .include "MY_MSP430FR5738_2.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF + .IFDEF PA_Core_MSP430 + .include "MY_MSP430FR5948_1.asm" ; choose always Px0 to Px3 as RTS pin!!! + .ENDIF diff --git a/inc/ThingsInFirst.inc b/inc/ThingsInFirst.inc index a5e1a09..cf9e8db 100644 --- a/inc/ThingsInFirst.inc +++ b/inc/ThingsInFirst.inc @@ -22,8 +22,8 @@ BIT15 .equ 32768 ; ---------------------------------------------- ; MACROS FOR assembly instructions ; ---------------------------------------------- -NOP .macro ; 1 word, 1 cycle - .word 4303h ; mov #0, r3 +NOP .macro ; 1 word, 1 cycle + .word 4303h ; mov #0, r3 .endm NOP2 .macro ; 1 Word, 2 cycles @@ -46,7 +46,7 @@ SCG1 .equ 0080h ; System Clock Generator 1. 1=turn_off_SMCLK V .equ 0100h UF9 .equ 0200h ; = SR(9) User Flag 9 UF10 .equ 0400h ; = SR(10) User Flag 10 -UF11 .equ 0800h ; = SR(11) User Flag 11 +UF11 .equ 0800h ; = SR(11) User Flag 11 ;---------------------------------------------------------------------------- LPM0 .equ CPUOFF LPM1 .equ SCG0 + CPUOFF ; for devices with FLL: LPM1 = LPM0 + FLL disabled @@ -90,10 +90,17 @@ PSP .reg R15 ; PSP = Parameters Stack Pointer (stack data) ; "ASMtoFORTH" or "mDOCOL" switches anywhere in a word, i.e. not only at its ; beginning as ITC competitors. ;------------------------------------------------------------------------------- +DOCOL .equ 1284h ; 1284h = CALL rDOCOL instruction +DODOES .equ 1285h ; 1285h = CALL rDODOES instruction +DOCON .equ 1286h ; 1286h = CALL rDOCON instruction +DOVAR .equ 1287h ; 1287h = CALL rDOVAR instruction + + + .SWITCH DTC .CASE 1 ; DOCOL = CALL rDOCOL, [rDOCOL] = XDOCOL -ASMtoFORTH .MACRO ; compiled by LO2HI +mASM2FORTH .MACRO ; compiled by LO2HI CALL #EXIT ; 10 cycles .ENDM ; 2 words, 10 cycles ; LO2HI + HI2LO = 3 words, 10 cycles. @@ -103,9 +110,9 @@ mDOCOL .MACRO ; compiled by : and by colon .ENDM ; 1 word, 14 cycles (CALL included) (ITC+4) ; COLON + SEMI = 2 words, 20 cycles (ITC+2) .CASE 2 ; DOCOL = PUSH IP + CALL rDOCOL, [rDOCOL] = EXIT -ASMtoFORTH .MACRO ; compiled by LO2HI +mASM2FORTH .MACRO ; compiled by LO2HI CALL rDOCOL ; 10 [rDOCOL] = EXIT - .ENDM ; 1 word, 10 cycles. + .ENDM ; 1 word, 10 cycles. ; LO2HI + HI2LO = 2 words, 10 cycles. mDOCOL .MACRO ; compiled by : and by COLON @@ -114,7 +121,7 @@ mDOCOL .MACRO ; compiled by : and by COLON .ENDM ; 2 words, 13 cycles (ITC+3) ; COLON + SEMI = 3 words, 19 cycles (ITC+1) .CASE 3 ; inlined DOCOL -ASMtoFORTH .MACRO ; compiled by LO2HI +mASM2FORTH .MACRO ; compiled by LO2HI MOV PC,IP ; 1 ADD #4,IP ; 1 MOV @IP+,PC ; 4 NEXT @@ -130,6 +137,10 @@ mDOCOL .MACRO ; compiled by : and by COLON ; COLON + SEMI = 5 words, 15 cycles (ITC-3) .ENDCASE ; DTC +mNEXTADR .MACRO + .word $+2 + .ENDM + .save .listing off ; ---------------------------------------------- @@ -144,21 +155,21 @@ asmlink .set 0 FORTHWORD .MACRO name .word forthlink forthlink .set $ - .byte STRLEN(name),name + .byte STRLEN(name)*2,name ; .align 2 .ENDM FORTHWORDIMM .MACRO name .word forthlink forthlink .set $ - .byte STRLEN(name)+128,name + .byte STRLEN(name)*2+1,name ; bit 0 is the immediate flag ; .align 2 .ENDM asmword .MACRO name .word asmlink asmlink .set $ - .byte STRLEN(name),name + .byte STRLEN(name)*2,name ; .align 2 .ENDM @@ -231,7 +242,7 @@ asmlink31 .set 0 ; (THREADS-1)*2 = AND mask to define CURRENT offset in vocabulary ;------------------------------------------- FORTHWORD .MACRO name -CONTEXTofst .set charfromstr(name,0) & ((THREADS-1)*2) +CONTEXTofst .set (charfromstr(name,0) & (THREADS-1))*2 .SWITCH CONTEXTofst .case 0 .word forthlink @@ -330,14 +341,14 @@ forthlink30 .set $ .word forthlink31 forthlink31 .set $ .endcase - .byte STRLEN(name),name + .byte STRLEN(name)*2,name .ENDM ;------------------------------------------- ; (THREADS-1)*2 = AND mask to define CURRENT offset in vocabulary ;------------------------------------------- FORTHWORDIMM .MACRO name -CONTEXTofst .set charfromstr(name,0) & ((THREADS-1)*2) +CONTEXTofst .set (charfromstr(name,0) & (THREADS-1))*2 .SWITCH CONTEXTofst .case 0 .word forthlink @@ -436,14 +447,14 @@ forthlink30 .set $ .word forthlink31 forthlink31 .set $ .endcase - .byte 80h+STRLEN(name),name + .byte STRLEN(name)*2+1,name ; bit 0 is the immediate flag .ENDM ;------------------------------------------- ; (THREADS-1)*2 = AND mask to define CURRENT offset in vocabulary ;------------------------------------------- asmword .MACRO name -CONTEXTofst .set charfromstr(name,0) & ((THREADS-1)*2) +CONTEXTofst .set (charfromstr(name,0) & (THREADS-1))*2 .SWITCH CONTEXTofst .case 0 .word asmlink @@ -542,7 +553,7 @@ asmlink30 .set $ .word asmlink31 asmlink31 .set $ .endcase ; asmlink - .byte STRLEN(name),name + .byte STRLEN(name)*2,name .ENDM .endif ; thread case @@ -567,7 +578,7 @@ USE_MOVE USE_MOVE .ENDIF .ENDIF - .IFDEF SD_CARD_LOADER + .IFDEF SD_CARD_LOADER .IFNDEF DOUBLE_INPUT DOUBLE_INPUT .ENDIF @@ -575,9 +586,6 @@ DOUBLE_INPUT .IFNDEF CONDCOMP CONDCOMP ; mandatory for Bootstrap .ENDIF - .IFNDEF DEFERRED -DEFERRED ; mandatory for Bootstrap - .ENDIF .ENDIF .ENDIF .IFDEF EXTENDED_ASM @@ -619,7 +627,10 @@ DOUBLE_NUMBERS ; to process double numbers ;----------------------------------------------------------------------- ; DEVICE I/O, MEMORY, SFR, vectors and minimum FORTH I/O declarations ;----------------------------------------------------------------------- +FADDON .set 0 + .IFDEF MSP_EXP430FR5739 +FADDON .SET FADDON | BIT0 ; hardware MPY LF_XTAL .IFDEF TERMINAL_I2C UCB0_TERM @@ -630,6 +641,7 @@ UCA1_SD .include "MSP430FR5739.inc" .ENDIF .IFDEF MSP_EXP430FR5969 +FADDON .SET FADDON | BIT0 ; hardware MPY ;EXTENDED_MEM LF_XTAL .IFDEF TERMINAL_I2C @@ -641,6 +653,7 @@ UCA1_SD .include "MSP430FR5969.inc" .ENDIF .IFDEF MSP_EXP430FR5994 +FADDON .SET FADDON | BIT0 ; hardware MPY ;EXTENDED_MEM LF_XTAL .IFDEF TERMINAL_I2C @@ -652,6 +665,7 @@ UCB0_SD .include "MSP430FR5994.inc" .ENDIF .IFDEF MSP_EXP430FR6989 +FADDON .SET FADDON | BIT0 ; hardware MPY ;EXTENDED_MEM LF_XTAL .IFDEF TERMINAL_I2C @@ -663,6 +677,7 @@ UCA0_SD .INCLUDE "MSP430FR6989.inc" .ENDIF .IFDEF MSP_EXP430FR5972 +FADDON .SET FADDON | BIT0 ; hardware MPY ;EXTENDED_MEM LF_XTAL .IFDEF TERMINAL_I2C @@ -708,6 +723,7 @@ UCB0_SD .include "MSP430FR2433.inc" .ENDIF .IFDEF MSP_EXP430FR2355 +FADDON .SET FADDON | BIT0 ; hardware MPY FLL LF_XTAL .IFDEF TERMINAL_I2C @@ -719,6 +735,7 @@ UCB1_SD .include "MSP430FR2355.inc" .ENDIF .IFDEF LP_MSP430FR2476 +FADDON .SET FADDON | BIT0 ; hardware MPY FLL ;EXTENDED_MEM ; LF_XTAL ; connect resistors R2=0k, R3=0k before uncomment this line @@ -735,49 +752,381 @@ UCA1_SD ; add here your device.inc item: ;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .ENDIF - .restore ; --------------------------- ; compute value of FORTHADDON ; --------------------------- -FADDON .set 0 + .IFDEF FLOORED_DIVISION +FADDON .SET FADDON | BIT15 ; FLOORED_DIVISION + .ENDIF .IFDEF LF_XTAL -FADDON .SET FADDON | BIT15 ; LFXTAL = 32768 Hz +FADDON .SET FADDON | BIT14 ; LFXTAL = 32768 Hz .ENDIF .IFNDEF TERMINAL_I2C ; if TERMINAL UART... .IFDEF TERMINAL5WIRES -FADDON .SET FADDON | BIT14 ; UART CTS +FADDON .SET FADDON | BIT13 ; UART CTS .ENDIF .IFDEF TERMINAL4WIRES -FADDON .SET FADDON | BIT13 ; UART RTS +FADDON .SET FADDON | BIT12 ; UART RTS .ENDIF .IFDEF TERMINAL3WIRES -FADDON .SET FADDON | BIT12 ; UART XON/XOFF +FADDON .SET FADDON | BIT11 ; UART XON/XOFF .ENDIF .IFDEF HALFDUPLEX -FADDON .SET FADDON | BIT11 ; UART Half Duplex +FADDON .SET FADDON | BIT10 ; UART Half Duplex .ENDIF .ENDIF ; TERMINAL UART +; --------------------------- .IFDEF TERMINAL_I2C -FADDON .SET FADDON | BIT10 ;I2C TERMINAL +FADDON .SET FADDON | BIT9 ;I2C TERMINAL .ENDIF .IFDEF FIXPOINT_INPUT -FADDON .SET FADDON | BIT9 ; Q15.16 INPUT +FADDON .SET FADDON | BIT8 ; Q15.16 INPUT .ENDIF .IFDEF DOUBLE_INPUT -FADDON .SET FADDON | BIT8 ; DOUBLE INPUT +FADDON .SET FADDON | BIT7 ; DOUBLE INPUT .ENDIF +; --------------------------- .IFDEF EXTENDED_ASM ; Assembler 20 bits -FADDON .SET FADDON | BIT7 - .ENDIF - .IFDEF MSP430ASSEMBLER -FADDON .SET FADDON | BIT6 ; Assembler 16 bits +FADDON .SET FADDON | BIT6 .ENDIF +; .IFDEF MSP430ASSEMBLER +FADDON .SET FADDON | BIT5 ; Assembler 16 bits +; .ENDIF .IFDEF EXTENDED_MEM - .IFNDEF EXTENDED_ASM -FADDON .SET FADDON | BIT5 ; Assembler 16 bits with Address access beyond $FFFF + .IFNDEF EXTENDED_ASM +FADDON .SET FADDON | BIT4 ; Assembler 16 bits with Address access beyond $FFFF + .ENDIF + .ENDIF +; --------------------------- +; .IFDEF VOCABULARY_SET ; +;FADDON .SET FADDON | BIT3 ; vocabulary set +; .ENDIF ; BIT2 to BIT0 are free + + + +;------------------------------------------------------------------------------- +; DTCforthMSP430FR5xxx RAM memory map: +;------------------------------------------------------------------------------- + +;---------------------------;--------- +; name words ; comment +;---------------------------;--------- +;LSTACK = L0 = LEAVEPTR ; ----- RAM_ORG + ; | +LSTACK_LEN .equ 16 ; | grows up + ; V + ; ^ +PSTACK_LEN .equ 48 ; | grows down + ; | +;PSTACK=S0 ; ----- RAM_ORG + $80 + ; ^ +RSTACK_LEN .equ 48 ; | grows down + ; | +;RSTACK=R0 ; ----- RAM_ORG + $E0 + +;---------------------------;--------- +; names bytes ; comments +;---------------------------;--------- +; PAD_I2CADR ; ----- RAM_ORG + $E0 +; PAD_I2CCNT ; +; PAD < ----- RAM_ORG + $E4 + ; | +PAD_LEN .equ 84 ; | grows up (ans spec. : PAD >= 84 chars) + ; v +; TIB_I2CADR ; ----- RAM_ORG + $138 +; TIB_I2CCNT ; +; TIB < ----- RAM_ORG + $13C + ; | +CIB_LEN .equ 84 ; | grows up Current Input Buffer (ans spec. : TIB >= 80 chars) + ; v +; HOLDS_ORG < ------RAM_ORG + $190 + ; ^ +HOLD_LEN .equ 34 ; | grows down (ans spec. : HOLD_LEN >= (2*n) + 2 char, with n = 16 bits/cell + ; | +; HOLD_BASE < ----- RAM_ORG + $1B2 + ; + ; system variables + ; + ; ----- RAM_ORG + $1E0 + ; + ; 28 bytes free + ; +; SD_BUF_I2CADR < ----- RAM_ORG + $1FC +; SD_BUF_I2CCNT ; +; SD_BUF < ----- RAM_ORG + $200 + ; +SD_BUF_LEN .equ 200h ; 512 bytes buffer + ; +; SD_BUF_END < ----- RAM_ORG + $400 + +LSTACK .equ RAM_ORG +LEAVEPTR .equ LSTACK ; Leave-stack pointer +PSTACK .equ LSTACK+(LSTACK_LEN*2)+(PSTACK_LEN*2) +RSTACK .equ PSTACK+(RSTACK_LEN*2) +PAD_I2CADR .equ PAD_ORG-4 +PAD_I2CCNT .equ PAD_ORG-2 +PAD_ORG .equ RSTACK+4 +TIB_I2CADR .equ TIB_ORG-4 +TIB_I2CCNT .equ TIB_ORG-2 +TIB_ORG .equ PAD_ORG+PAD_LEN+4 +HOLDS_ORG .equ TIB_ORG+CIB_LEN + +HOLD_BASE .equ HOLDS_ORG+HOLD_LEN + +; ---------------------------------------------------- +; RAM_ORG + $1B2 : RAM VARIABLES +; ---------------------------------------------------- +HP .equ HOLD_BASE ; HOLD ptr +; ---------------------------------------------------- +; new definition pointers, generated by HEADER +; ---------------------------------------------------- +LAST_NFA .equ HOLD_BASE+2 ; used by REVEAL, IMMEDIATE +LAST_THREAD .equ HOLD_BASE+4 ; " REVEAL +LAST_CFA .equ HOLD_BASE+6 ; " DOES>, RECURSE +LAST_PSP .equ HOLD_BASE+8 ; " REVEAL +; ---------------------------------------------------- +; FORTH interpreter variables +; ---------------------------------------------------- +STATE .equ HOLD_BASE+10 ; Interpreter state +BASEADR .equ HOLD_BASE+12 ; BASE +CAPS .equ HOLD_BASE+14 ; CAPS +; ---------------------------------------------------- +SOURCE .equ HOLD_BASE+16 ; len, org of input stream +SOURCE_LEN .equ HOLD_BASE+16 ; +SOURCE_ORG .equ HOLD_BASE+18 ; +TOIN .equ HOLD_BASE+20 ; CurrentInputBuffer pointer +; ---------------------------------------------------- +; FORTH environment +; ---------------------------------------------------- +DP .equ HOLD_BASE+22 ; dictionnary pointer +LASTVOC .equ HOLD_BASE+24 ; +CURRENT .equ HOLD_BASE+26 ; +CONTEXT .equ HOLD_BASE+28 ; 8 words of depth ending +NULL_WORD .equ HOLD_BASE+44 ; with a null word in addition +; ----------------------------------; + + .IFDEF SD_CARD_LOADER +; -------------------------------------------------- +; RAM_ORG + $1FC : RAM SD_CARD SD_BUF 4 + 512 bytes +; -------------------------------------------------- +SD_BUF_I2CADR .equ SD_BUF-4 +SD_BUF_I2CCNT .equ SD_BUF-2 +SD_BUF .equ HOLD_BASE+78 +SD_BUF_END .equ SD_BUF+200h ; 512bytes +; -------------------------------------------------- +; RAM_ORG + $400 : free RAM +; -------------------------------------------------- .ENDIF + + .IFDEF SD_CARD_LOADER +; --------------------------------------- +; VARIABLES that should be in RAM +; --------------------------------------- + .IF RAM_LEN < 2048 ; if RAM < 2K (FR57xx) the variables below are in INFO space (FRAM) +SD_ORG .equ INFO_ORG+5Ah ; + .ELSE ; if RAM >= 2k the variables below are in RAM +SD_ORG .equ SD_BUF_END+2 ; 1 word guard + .ENDIF + + .org SD_ORG +; --------------------------------------- +; FAT FileSystemInfos +; --------------------------------------- +;FATtype .equ SD_ORG+0 +BS_FirstSectorL .equ SD_ORG+2 ; init by SD_Init, used by RW_Sector_CMD +BS_FirstSectorH .equ SD_ORG+4 ; init by SD_Init, used by RW_Sector_CMD +OrgFAT1 .equ SD_ORG+6 ; init by SD_Init, +FATSize .equ SD_ORG+8 ; init by SD_Init, +OrgFAT2 .equ SD_ORG+10 ; init by SD_Init, +;OrgRootDIR .equ SD_ORG+12 ; init by SD_Init, +OrgClusters .equ SD_ORG+14 ; init by SD_Init, Sector of Cluster 0 +SecPerClus .equ SD_ORG+16 ; init by SD_Init, byte size +; --------------------------------------- +; SD command +; --------------------------------------- +SD_LOW_LEVEL .equ SD_ORG+18 +SD_CMD_FRM .equ SD_LOW_LEVEL ; SD_CMDx inverted frame ${CRC7,ll,LL,hh,HH,CMD} +SectorL .equ SD_LOW_LEVEL+6 +SectorH .equ SD_LOW_LEVEL+8 +; --------------------------------------- +; SD_BUF management +; --------------------------------------- +BufferPtr .equ SD_LOW_LEVEL+10 +BufferLen .equ SD_LOW_LEVEL+12 +; --------------------------------------- +; FAT entry +; --------------------------------------- +SD_FAT_LEVEL .equ SD_LOW_LEVEL+14 +ClusterL .equ SD_FAT_LEVEL ; +ClusterH .equ SD_FAT_LEVEL+2 ; +LastFATsector .equ SD_FAT_LEVEL+4 ; +LastFAToffset .equ SD_FAT_LEVEL+6 ; +FATsector .equ SD_FAT_LEVEL+8 ; not used +; --------------------------------------- +; DIR entry +; --------------------------------------- +DIRClusterL .equ SD_FAT_LEVEL+10 ; contains the Cluster of current directory ; = 1 as FAT16 root directory +DIRClusterH .equ SD_FAT_LEVEL+12 ; contains the Cluster of current directory ; = 1 as FAT16 root directory +DIREntryOfst .equ SD_FAT_LEVEL+14 +; --------------------------------------- +; Handle Pointer +; --------------------------------------- +CurrentHdl .equ SD_FAT_LEVEL+16 ; contains the address of the last opened file structure, or 0 +; --------------------------------------- +; Load file operation +; --------------------------------------- +PathName_PTR .equ SD_FAT_LEVEL+18 ; +PathName_END .equ SD_FAT_LEVEL+20 ; +; --------------------------------------- +; Handle structure +; --------------------------------------- +FirstHandle .equ SD_FAT_LEVEL+22 +; three handle tokens : +; HDLB_Token= 0 : free handle +; = 1 : file to read +; = 2 : file updated (write) +; =-1 : LOAD"ed file (source file) + +; offset values +HDLW_PrevHDL .equ 0 ; previous handle +HDLB_Token .equ 2 ; token +HDLB_ClustOfst .equ 3 ; Current sector offset in current cluster (Byte) +HDLL_DIRsect .equ 4 ; Dir SectorL +HDLH_DIRsect .equ 6 ; Dir SectorH +HDLW_DIRofst .equ 8 ; SD_BUF offset of Dir entry +HDLL_FirstClus .equ 10 ; File First ClusterLo (identify the file) +HDLH_FirstClus .equ 12 ; File First ClusterHi (identify the file) +HDLL_CurClust .equ 14 ; Current ClusterLo +HDLH_CurClust .equ 16 ; Current ClusterHi +HDLL_CurSize .equ 18 ; written size / not yet read size (Long) +HDLH_CurSize .equ 20 ; written size / not yet read size (Long) +HDLW_BUFofst .equ 22 ; SD_BUF offset ; used by LOAD" +HDLW_PrevLEN .equ 24 ; previous LEN +HDLW_PrevORG .equ 26 ; previous ORG + + .IF RAM_LEN < 2048 ; due to the lack of RAM, only 4 handles and PAD replaces SDIB +HandleMax .equ 4 ; and not 8 to respect INFO size (FRAM) +HandleLenght .equ 28 +HandlesLen .equ handleMax*HandleLenght +HandleEnd .equ FirstHandle+handleMax*HandleLenght +SD_END .equ HandleEnd +SDIB_I2CADR .equ PAD_ORG-4 +SDIB_I2CCNT .equ PAD_ORG-2 +SDIB_ORG .equ PAD_ORG + .ELSE ; RAM_Size >= 2k all is in RAM +HandleMax .equ 8 +HandleLenght .equ 28 +HandlesLen .equ handleMax*HandleLenght +HandleEnd .equ FirstHandle+handleMax*HandleLenght +SDIB_I2CADR .equ SDIB_ORG-4 +SDIB_I2CCNT .equ SDIB_ORG-2 +SDIB_ORG .equ HandleEnd+4 +SD_END .equ SDIB_ORG+CIB_LEN + .ENDIF ; RAM_Size +SD_LEN .equ SD_END-SD_ORG + .ENDIF ; SD_CARD_LOADER + + .org INFO_ORG +;------------------------------------------------------------------------------- +; INFO(DCBA) >= 256 bytes memory map (FRAM) : +;------------------------------------------------------------------------------- +; FRAM INFO: KERNEL INIT CONSTANTS and VARIABLES +; ---------------------------------------------- +FREQ_KHZ .word FREQUENCY*1000 ; used to stabilize MCLK before start, see MSP430FRxxxx.asm + .IFDEF TERMINAL_I2C +I2CSLAVEADR .word MYSLAVEADR ; on MSP430FR2xxx devices with BSL I2C, Slave address is FFA0h +I2CSLAVEADR1 .word 0 +LPM_MODE .word GIE+LPM4 ; LPM4 is the default mode for I2C TERMINAL + .ELSE ; TERMINAL_UART +TERMBRW_RST .word TERMBRW_INI ; set by TERMINALBAUDRATE.inc +TERMMCTLW_RST .word TERMMCTLW_INI ; set by TERMINALBAUDRATE.inc +LPM_MODE .word GIE+LPM0 ; LPM0 is the default mode for UART TERMINAL .ENDIF - .IFDEF CONDCOMP -FADDON .SET FADDON | BIT0 ; Conditionnal Compilation +USERSYS .word -3 ; RESET use, value = -3 when compiling new kernel +FORTHVERSION .word VAL(SUBSTR(VER,1,0)); used by WARM +INI_THREAD .word THREADS ; used by WORDS definition +FORTHADDON .word FADDON ; used by FF_SPECS.f and to secure downloading of any source.f files. +; --------------------------------------; +DEEP_ORG ; MOV #DEEP_ORG,X see "PUC 7" in forthMSP430FR.ASM +; --------------------------------------; +DEEP_TERM_VEC .word TERMINAL_INT ; MOV @X+,&TERM_VEC ; TERMINAL_INT --> FRAM TERM_VEC + .IFNDEF SD_CARD_LOADER +DEEP_COLD .word COLD_TERM ; MOV @X+,&COLD_APP ; COLD_TERM --> FRAM COLD_APP +DEEP_SOFT .word INIT_SOFT_TERM ; MOV @X+,&SOFT_APP ; INIT_SOFT_TERM --> FRAM SOFT_APP +DEEP_HARD .word INIT_TERM ; MOV @X+,&HARD_APP ; INIT_TERM --> FRAM HARD_APP +DEEP_SLEEP .word RXON ; MOV @X+,&SLEEP_APP ; RXON --> FRAM SLEEP_APP + .ELSE +DEEP_COLD .word COLD_TERM ; MOV @X+,&COLD_APP ; COLD_TERM --> FRAM COLD_APP +DEEP_SOFT .word INIT_SOFT_SD ; MOV @X+,&SOFT_APP ; INIT_SOFT_SD --> FRAM SOFT_APP +DEEP_HARD .word INIT_HARD_SD ; MOV @X+,&HARD_APP ; INIT_HARD_SD --> FRAM HARD_APP +DEEP_SLEEP .word RXON ; MOV @X+,&SLEEP_APP ; RXON --> FRAM SLEEP_APP .ENDIF +DEEP_DP .word ROMDICT ; MOV @X+,&RST_DP ; DEEP_DP --> FRAM RST_DP +DEEP_LASTVOC .word lastvoclink ; MOV @X+,&RST_LASTVOC ; DEEP_LASTVOC --> FRAM RST_LASTVOC +DEEP_CURRENT .word BODYFORTH ; MOV @X+,&CURRENT ; DEEP_CONTEXT --> FRAM RST_CURRENT +DEEP_CONTEXT .word BODYFORTH ; MOV @X+,&CONTEXT ; DEEP_CONTEXT --> FRAM RST_CONTEXT +; --------------------------------------; +PUC_ABORT_ORG ; MOV #PUC_ABORT_ORG,X +; --------------------------------------; +INIT_ACCEPT .word ACCEPT+4 ; MOV @X+,&ACCEPT+2 ; INIT_ACCEPT --> FRAM PFA_ACCEPT +INIT_EMIT .word EMIT+4 ; MOV @X+,&EMIT+2 ; INIT_EMIT --> FRAM PFA_EMIT +INIT_KEY .word KEY+4 ; MOV @X+,&KEY+2 ; INIT_KEY --> FRAM PFA_KEY +INIT_CIB .word TIB_ORG ; MOV @X+,&CIB_ORG ; INIT_CIB --> FRAM CIB_ORG +; --------------------------------------; +FORTH_ORG ; MOV #FORTH_ORG,X +; --------------------------------------; +INIT_RSP .word RSTACK ; MOV @X+,RSP ; INIT_RSP --> RSP (R1) + .SWITCH DTC + .CASE 1 +INIT_DOCOL .word xDOCOL ; MOV @X+,rDOCOL ; INIT_DOCOL --> rDOCOL (R4) + .CASE 2 +INIT_DOCOL .word EXIT ; MOV @X+,rDOCOL ; INIT_DOCOL --> rDOCOL (R4) + .CASE 3 +INIT_DOCOL .word 0 ; MOV @X+,R4 ; useless rDOCOL + .ENDCASE +INIT_DODOES .word xDODOES ; MOV @X+,rDODOES ; INIT_DODOES --> rDODOES (R5) +INIT_DOCON .word xDOCON ; MOV @X+,rDOCON ; INIT_DOCON --> rDOCON (R6) +INIT_DOVAR .word RFROM ; MOV @X+,rDOVAR ; INIT_DOVAR --> rDOVAR (R7) +INIT_CAPS .word 32 ; MOV @X+,&CAPS ; INIT_CAPS --> RAM CAPS +INIT_BASE .word 10 ; MOV @X+,&BASE ; INIT_BASE --> RAM BASE +INIT_LEAVE .word LSTACK ; MOV @X+,&LEAVEPTR ; INIT_LEAVE --> RAM LEAVEPTR +; --------------------------------------; +; FRAM RST values initialised by -1 SYS ; +; --------------------------------------; +RST_ORG ; make room for RST values of: +RST_LEN .equ 16 ; 16 bytes +; --------------------------------------; + .IFNDEF SD_CARD_LOADER +COLD_APP .word COLD_TERM ; COLD_APP +SOFT_APP .word INIT_SOFT_TERM ; SOFT_APP +HARD_APP .word INIT_TERM ; HARD_APP +SLEEP_APP .word RXON ; SLEEP_APP + .ELSE +COLD_APP .word COLD_TERM ; COLD_APP +SOFT_APP .word INIT_SOFT_SD ; SOFT_APP +HARD_APP .word INIT_HARD_SD ; HARD_APP +SLEEP_APP .word RXON ; SLEEP_APP + .ENDIF +; --------------------------------------; +RST_DP .word ROMDICT ; program memory pointer +; --------------------------------------; +RST_LASTVOC .word lastvoclink ; last vocabulary link +; --------------------------------------; +RST_CURRENT .word BODYFORTH ; CURRENT word-set ptr +; --------------------------------------; +RST_CONTEXT .word BODYFORTH ; CONTEXT space (8 CELLS) + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 +; --------------------------------------; + .word 0 ; NULL_WORD, always 0 +; --------------------------------------; + +; --------------------------; +; INFO_ORG + $5A : free use ; +; --------------------------; \ No newline at end of file diff --git a/inc/ThingsInLast.inc b/inc/ThingsInLast.inc index 6282f4c..a3ee885 100644 --- a/inc/ThingsInLast.inc +++ b/inc/ThingsInLast.inc @@ -1,6 +1,6 @@ ; -*- coding: utf-8 -*- -ROMDICT ; init DDP with this current address +ROMDICT .equ $ ; init DDP with this current address lastvoclink .equ voclink lastforthword .equ forthlink lastasmword .equ asmlink @@ -81,32 +81,32 @@ lastasmword31 .equ asmlink31 ; 0FF80h = SIGNATURES AREA, Deep_RST erases only 8 words from 0FF80h to 0FF90h ;---------------- .org 0FF80h ; JTAG signature (2 words) - .word -1 + .word -1 .word -1 ; .org 0FF84h ; BSL signature (2 words) - .word -1 .word -1 -; .org 0FF88h ; MSP430FR5xxx|MSP430FR6xxx JTAG_PASSWORD, up to 0FFFFh -; .org 0FF88h ; MSP430FR5xxx|MSP430FR6xxx encapsulation signature (2 words) + .word -1 +; .org 0FF88h ; FR5xxx|FR6xxx JTAG_PASSWORD, up to 0FFFFh +; .org 0FF88h ; FR5xxx|FR6xxx encapsulation signature (2 words) +; .org 0FF88h ; FR215x|FR235x|FR247x|FR267x BLS config signature + BSL config (2 words) + .word -1 + .word -1 + .word -1 + .word -1 +; .org 0FF90h ; free (not erased by DEEP RESET) + .word -1 + .word -1 + .word -1 + .word -1 .word -1 .word -1 .word -1 .word -1 -; .org 0FF90h ; free for 8 x I2C addresses UCBx - .word 0 ; I2C address mini = 10h, maxi = 0EEh (I2C-bus specification and user manual V6) - .word 0 ; (112 x I2C addresses with R/W flag = 0) - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 ;---------------- -; FFA0h = MSP430FR2355/2476 BSL I2C Address, a good idea for I2C_SLAVE_ADR(s) area, isn't it? +; FFA0h = FR215x|FR235x|FR247x|FR267x BSL I2C Address, a good idea for I2C_SLAVE_ADR(s) area, isn't it? ;---------------- - .org 0FFA0h ; - .word 077h ; --> MSP430FR2355/2476 BSL I2C 7 bits address (without R/W flag) + .word 077h ; --> FR215x|FR235x|FR247x|FR267x BSL I2C 7 bits address (without R/W flag) .word 10h ; --> UCBxI2COA0 8 bits address (with R/W flag=0) .word 12h ; --> UCBxI2COA1 .word 14h ; --> UCBxI2COA2 @@ -116,7 +116,6 @@ lastasmword31 .equ asmlink31 ;---------------- ; FFACh = VECTORS AREA (lowest known vector interrupt) ;---------------- - .org 0FFACh .word COLD .word COLD .word COLD diff --git a/prog/SciTEUser.properties b/prog/SciTEUser.properties new file mode 100644 index 0000000..d6cd09c --- /dev/null +++ b/prog/SciTEUser.properties @@ -0,0 +1,11 @@ +PLAT_WIN=1 +PLAT_GTK=0 +position.maximize=1 + +properties.directory.enable=1 +check.if.already.open=1 + +save.session=1 +save.recent=1 +save.session=1 +session.bookmarks=1 diff --git a/prog/TERATERM.INI b/prog/TERATERM.INI new file mode 100644 index 0000000..9ea4ef4 --- /dev/null +++ b/prog/TERATERM.INI @@ -0,0 +1,972 @@ +[BG] +; Use Eterm look-feel Background extension (on/off) +BGEnable=on + +; Use AlphaBlend API (on/off) +BGUseAlphaBlendAPI=on + +; Susie plugin path +BGSPIPath=plugin + +; Fast window sizing/moving +BGFastSizeMove=on + +; Flickerless window moving +BGFlickerlessMove=on + +; If HideTitle=on and BGNoFrame=on, use window without frame +; you can resize window with Alt + Shift + LeftDrag +BGNoFrame=on + +; wildcard => random select +BGThemeFile=theme\*.INI + + +[Tera Term] +; Tera Term version number +Version=4.100 + +; Language (English/Japanese/Russian/Korean/UTF-8) +Language=English + +; User interface language file that includes message strings. +; Tera Term uses built-in English message when the file or message is not found. +UILanguageFile=lang\French.lng + +; Connecting timeout value(per seconds). No action if the value is zero. +; Connecting socket could be canceled after the value timeout if the value is greater than zero. +; The default value is zero(depends on Windows TCP/IP stack implementation). +ConnectingTimeout=0 + +; pasting string by clicking mouse right button disabled +DisablePasteMouseRButton=off + +; pasting string by clicking mouse middle button disabled +DisablePasteMouseMButton=on + +; confirm pasting string by clicking mouse right button +ConfirmPasteMouseRButton=off + +; confirm changing clipboard string by clicking mouse right button +ConfirmChangePaste=on +ConfirmChangePasteCR=on +PasteDialogSize=330,220 +ConfirmChangePasteStringFile= + +; Scroll out the current buffer when the clear screen does. +ScrollWindowClearScreen=on + +; Reset scrollback on display activity +AutoScrollOnlyInBottomLine=on + +; Starting the selection only by a left button. +SelectOnlyByLButton=on + +; New connection by Alt-N Accelerator key +AcceleratorNewConnection=on + +; Duplicate session by Alt-D Accelerator key disabled +DisableAcceleratorDuplicateSession=off + +; Cygwin connection by Alt-G Accelerator key +AcceleratorCygwinConnection=on + +; Send break by Alt-B Accelerator key disabled +DisableAcceleratorSendBreak=off + +; New connection Menu disabled +DisableMenuNewConnection=off + +; Duplicate session Menu disabled +DisableMenuDuplicateSession=off + +; Send break Menu disabled +DisableMenuSendBreak=off + +; ANSI color definition (in the case FullColor=on) +; * UseTextColor should be off, or the background and foreground color of +; VTColor are assigned to color-number 0 and 7 respectively, even if +; they are specified in ANSIColor. +; * ANSIColor is a set of 4 values that are color-number(0--15), +; red-value(0--255), green-value(0--255) and blue-value(0--255). +ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,128,128,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,64,64,64, 9,192,0,0, 10,0,192,0, 11,192,192,0, 12,64,64,192, 13,192,0,192, 14,0,192,192, 15,192,192,192 +; xterm +; ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,92,92,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,127,127,127, 9,205,0,0, 10,0,205,0, 11,205,205,0, 12,0,0,238, 13,205,0,205, 14,0,205,205, 15,229,229,229 +; PuTTY +;ANSIColor=0,0,0,0, 1,255,85,85, 2,85,255,85, 3,255,255,85, 4,85,85,255, 5,255,85,255, 6,85,255,255, 7,255,255,255, 8,85,85,85, 9,187,0,0, 10,0,187,0, 11,187,187,0, 12,0,0,187, 13,187,0,187, 14,0,187,187, 15,187,187,187 +; Tera Term Pro 2.3 +;ANSIColor=0,0,0,0, 1,255,0,0, 2,0,255,0, 3,255,255,0, 4,0,0,255, 5,255,0,255, 6,0,255,255, 7,255,255,255, 8,128,128,128, 9,128,0,0, 10,0,128,0, 11,128,128,0, 12,0,0,128, 13,128,0,128, 14,0,128,128, 15,192,192,192 +; Solarized (http://ethanschoonover.com/solarized) +;ANSIColor=0,7,54,66, 1,203,75,22, 2,88,110,117, 3,101,123,131, 4,131,148,150, 5,108,113,196, 6,147,161,161, 7,253,246,227, 8,0,43,54, 9,220,50,47, 10,133,153,0, 11,181,137,0, 12,38,139,210, 13,211,54,130, 14,42,161,152, 15,238,232,213 + +; Enable continued-line copy +EnableContinuedLineCopy=on + +; Mouse cursor type (arrow/ibeam/cross/hand) +MouseCursor=IBEAM + +; Translucent window (0 - 255: transparency value) +AlphaBlend=255 + +; Cygwin install path +CygwinDirectory=C:\cygwin64 + +; Viewlog Editor path +ViewlogEditor=C:\Windows\notepad.exe + +; Locale for Unicode +;Locale=chs +Locale=english + +; CodePage for Unicode +CodePage=1252 + +; Background color of text uses background color of screen (on/off) +UseNormalBGColor=on + +; Port type (serial/tcpip/namedpipe) +Port=serial + +; Window positions +VTPos=-2147483648,-2147483648 +TEKPos=-2147483648,-2147483648 + +; Terminal size +TerminalSize=128,42 +; Terminal size=window size (on/off) +TermIsWin=on +; Auto window resizing option (on/off) +AutoWinResize=off + +; Convert a received new-line (CR) char to CR/CRLF/LF/AUTO +CRReceive=AUTO +; New-line code to be transmitted (CR/CRLF/LF) +CRSend=CRLF + +; Terminal ID +TerminalID=VT100 + +; Local echo (on/off) +LocalEcho=off + +; Answerback +Answerback= + +; Auto window switching (VT<->TEK; on/off) +AutoWinSwitch=off + +; Kanji code to be received (SJIS/EUC/JIS) +KanjiReceive=UTF-8 +; JIS Katakana code to be received (7/8) +KatakanaReceive=8 + +; Kanji code to be transmitted (SJIS/EUC/JIS) +KanjiSend=UTF-8 +; JIS Katakana to be transmitted (7/8) +KatakanaSend=8 +; Kanji-in sequence to be transmitted (@/B) +KanjiIn=B +; Kanji-out sequence to be transmitted (J/B) +KanjiOut=B + +; Russian code set used in host +RussHost=Windows +; Russian code set used in PC +RussClient=Windows + +; Window title +Title=Tera Term + +; Cursor shape (block/vertical/horizontal) +CursorShape=block + +; Hide title & menu bars and enable popup menu (on/off) +HideTitle=off +; Hide menu bar and enable popup menu (on/off) +PopupMenu=off + +; Color mode (on/off) +EnableANSIColor=on +PcBoldColor=on +Aixterm16Color=on +Xterm256Color=on + +; Enable scroll buffer (on/off) +EnableScrollBuff=on +; Scroll buffer size +ScrollBuffSize=40000 + +; Text and background colors +; for Normal characters +VTColor=0,255,0,0,0,0 +; Solarized Dark +;VTColor=131,148,150,0,43,54 +; Solarized Light +;VTColor=101,123,131,253,246,227 +; +; for Bold characters +EnableBoldAttrColor=on +VTBoldColor=255,255,0,0,0,0 +; Solarized Dark +;VTBoldColor=147,161,161,7,54,66 +; Solarized Light +;VTBoldColor=88,110,117,238,232,213 +; +; for Blink characters +EnableBlinkAttrColor=on +VTBlinkColor=255,0,0,0,0,0 +; Solarized Dark +;VTBlinkColor=133,153,0,0,43,54 +; Solarized Light +;VTBlinkColor=133,153,0,253,246,227 +; +; for Reverse characters +EnableReverseAttrColor=on +VTReverseColor=0,0,0,255,255,255 +; Solarized Dark +;VTReverseColor=0,43,54,131,148,150 +;VTReverseColor=101,123,131,253,246,227 +; Solarized Light +;VTReverseColor=253,246,227,101,123,131 +;VTReverseColor=131,148,150,0,43,54 +; +; for URL(hyper link) text color +EnableURLColor=on +URLUnderline=on +URLColor=0,255,255,0,0,0 +; Solarized Dark +;URLColor=181,137,0,0,43,54 +; Solarized Light +;URLColor=181,137,0,253,246,227 +; + +; Enable clickable URL +EnableClickableUrl=off + +; Launched Browser +; Firefox example +; ClickableUrlBrowser=firefox +; ClickableUrlBrowserArg=-new-tab +; Opera example +; ClickableUrlBrowser=opera +; ClickableUrlBrowserArg=-newpage +; IE example +; ClickableUrlBrowser=iexplore +; ClickableUrlBrowserArg= +; Chrome example +; ClickableUrlBrowser=chrome +; ClickableUrlBrowserArg= +ClickableUrlBrowser= +ClickableUrlBrowserArg= + + +; for TEK window +TEKColor=0,0,0,255,255,255 + +; TEK color emulation (on/off) +TEKColorEmulation=off + +; Font +VTFont=Lucida Console,0,-13,0 +; Bold style font (on/off) +EnableBold=on +; Font for TEK window +TEKFont=Terminal,0,-8,255 +; Font quality(default/non-antialiased/antialiased/cleartype) +FontQuality=nonantialiased + +; Russian code set of the font +RussFont=Windows + +; Backspace key (BS/DEL) +BSKey=BS +; transmit DEL by Delete key (on/off) +DeleteKey=on + +; Russian code set used in the keyboard driver +RussKeyb=Windows + +; Meta key (on/off/left/right) +MetaKey=off + +; Meta key sets MSB (off/raw/text) +Meta8Bit=off + +; Application keypad mode disabled. +DisableAppKeypad=on + +; Application cursor mode disabled. +DisableAppCursor=on + +; Serial port parameters +; Port number +ComPort=4 +; Baud rate +BaudRate=4000000 +; Parity (even/odd/none/mark/space) +Parity=none +; Data (7/8) +DataBit=8 +; Stop (1/1.5/2) +StopBit=1 +; Flow control (x/hard/none) +FlowCtrl=x +; Transmit delay per character (in msec) +DelayPerChar=0 +; Transmit delay per line (in msec) +DelayPerLine=0 + +; TCP/IP parameters +; TCP port# +TCPPort=10001 +; Telnet flag (on/off) +Telnet=off +; Telnet terminal type +;TermType=vt100 +TermType=xterm + +; Auto window closing option (on/off) +AutoWinClose=on +; History list of hosts +HistoryList=on + +; Binary flag for Send File (on/off) +TransBin=off + +; without transfer dialog flag for Send File (on/off) +FTHideDialog=off + +; Binary flag for Log (on/off) +LogBinary=off +; Log append (on/off) +LogAppend=on +; plain text flag for Log (on/off) +LogTypePlainText=on +; timestamp flag for Log (on/off) +LogTimestamp=off +; without transfer dialog flag for Log (on/off) +LogHideDialog=off +; Current all buffer included in first (on/off) +LogIncludeScreenBuffer=off + +; Default Log file name. You can specify strftime format to here. +LogDefaultName=teraterm.log +; Default path to save the log file. +LogDefaultPath= +; Auto start logging with default log file name. +LogAutoStart=off + +; === Log Rotate === +; Mode: 0(none), 1(size) +LogRotate=0 +; Size +LogRotateSize=0 +; Size type: 0(byte), 1(KB), 2(MB) +LogRotateSizeType=0 +; Step: 0(none), >=1(count times) +LogRotateStep=0 + +; Deferred Log Write Mode (on/off) +DeferredLogWriteMode=on + + +; XMODEM option (checksum/crc/1k) +XmodemOpt=checksum +; Binary flag for XMODEM Receive and ZMODEM Send (on/off) +XmodemBin=on + +; XMODEM receive command +XmodemRcvCommand= + +; Default directory for file transfers +FileDir=A:\projets\msp430\MSP430-FORTH + +; Filter for send file +FileSendFilter= + +; SCP sending directory +ScpSendDir= + +; Save Broadcast Command History +BroadcastCommandHistory=on + +; Broadcast command enabling flag on the dialog window (on/off) +AcceptBroadcast=on + +; Number of broadcast command history +MaxBroadcatHistory=99 + +;------ special options (see Tera Term help) + +; C1 (8-bit) control characters +Accept8BitCtrl=on +Send8BitCtrl=off + +; Accept remote-controlled window title changing (off/overwrite/ahead/last) +AcceptTitleChangeRequest=overwrite + +; Wrong kanji-out ^[(H (Japanese only) +AllowWrongSequence=off + +; Alternate screen buffer support +AlternateScreenBuffer=on + +; Automatic serial reconnection when serial cable is inserted and extracted(Windows XP or later). +AutoComPortReconnect=on + +; When serial port is specified with with /C= option and the port does not exist, +; Tera Term will wait for port connection. +WaitCom=off + +; Auto file renaming for downloading +AutoFileRename=on + +; Auto text copying +AutoTextCopy=on + +; Back wrap +BackWrap=off + +; Beep by BEL (on/off/visual) +Beep=on + +; Beep over-used +BeepOverUsedTime=2 +BeepOverUsedCount=5 +BeepSuppressTime=5 + +; Beep on connection & disconnection +BeepOnConnect=off + +; B-Plus auto receive +BPAuto=off + +; Escape all control characters in B-Plus +BPEscCtl=off + +; B-Plus log +BPLog=off + +; Clear serial port buffer when port opening +ClearComBuffOnOpen=on + +; Clear screen when window is resized +ClearOnResize=on + +; Clear screen after the connection is closed +ClearScreenOnCloseConnection=off + +; Clipboard access from remote (on/off/read/write) +ClipboardAccessFromRemote=off + +; "Disconnect?" warning +ConfirmDisconnect=on + +; Control characters in kanji (Japanese only) +CtrlInKanji=on + +; Confirm send a file when drag and drop +ConfirmFileDragAndDrop=on + +; allow the sequences related to cursor control +CursorCtrlSequence=off + +; Display all characters (debug mode) +; Debug=off +Debug=on +; Debug mode type which can be selected by user. +; on|all = All types +; off|none = Disabled debug mode +; normal = usual teraterm debug mode +; hex = hex output +; noout = disable output completely +DebugModes=all + +; Delimters for word selection +; (compatible with earlier versions of Tera Term) +; DelimList=$20 +; DelimDBCS=off +DelimList=$20!"#$24%&'()*+,:;<=>?@[\]^`{|} +DelimDBCS=on + +; Disable mouse event tracking when Control-Key is pressed. +DisableMouseTrackingByCtrl=on + +; Disable wheel to cursor translation when Control-Key is pressed. +DisableWheelToCursorByCtrl=on + +; Line at a time mode +EnableLineMode=on + +; Popup menu +EnablePopupMenu=on + +; "Show menu bar" command +EnableShowMenu=on + +; Enable the status line +EnableStatusLine=on + +; High speed file transfer on serial connection. +FileSendHighSpeedMode=on + +; Display "New Connection" dialog on startup +HostDialogOnStartup=on + +; Enable IME / inline input (Japanese only) +IME=on +IMEInline=on + +IMERelatedCursor=off + +; Windows 7 jump list support +JumpList=on + +; Join Split URL +JoinSplitURL=off +JoinSplitURLIgnoreEOLChar=\ + +; Kermit log +KmtLog=off +; Kermit CAPAS: Ability to transmit and receive extended-length packets +KmtLongPacket=off +; Kermit CAPAS: Ability to accept "A" packets (file attributes) +KmtFileAttr=off + +; Language selection +LanguageSelection=on + +; Lock Terminal Unique ID +LockTUID=on + +; Exclusive lock for log file +LogLockExclusive=on + +; Max scroll buffer size +MaxBuffSize=500000 + +; Max serial port number +MaxComPort=256 + +; Max buffer size of OSC string +MaxOSCBufferSize=4096 + +; Mouse event tracking +MouseEventTracking=on + +; Maximized window bug tweak +MaximizedBugTweak=2 + +; Nonblinking cursor +NonblinkingCursor=off + +; Polygon cursor for KILLFOCUS +KillFocusCursor=on + +; Delay for pass-thru printing (in secs) +PassThruDelay=3 + +; Direct pass-thru printing +PassThruPort= + +; Delay for paste per each lines (in msec) +PasteDelayPerLine=10 + +; Allow the sequences related to printer control +PrinterCtrlSequence=on + +; Printer font +PrnFont= + +; Page margins for printing +; (left, right, top and bottom in 1/100 inches) +PrnMargin=50,50,50,50 + +; Quick-VAN log +QVLog=off + +; Quick-VAN window size +QVWinSize=8 + +; Russian code set of printer font +RussPrint=Windows + +; Save VT Window position +SaveVTWinPos=off + +; Max lines per one jump scroll +ScrollThreshold=12 + +; Scroll line count with mouse wheel button +MouseWheelScrollLine=3 + +; Text selection on window activation +SelectOnActivate=on + +; Break signal length (in msec) +SendBreakTime=1000 + +; Startup macro +StartupMacro= + +; Strict Key Mapping +StrictKeyMapping=off + +; Tab Stop Modify Sequence (on/off/combination of HTS,HTS7,HTS8,TBC,TBC0,TBC3) +TabStopModifySequence=on + +; TEK mouse code +TEKGINMouseCode=32 + +; Telnet Auto Detection +TelAutoDetect=on + +; Telnet binary option +TelBin=off + +; Telnet auto echo +TelEcho=off + +; Telnet log +TelLog=off + +; Standard telnet port +TelPort=23 + +; Keep-Alive packet sending interval on telnet connection (per second, 0=disabled) +TelKeepAliveInterval=300 + +; Auto setup for non-telnet +TCPLocalEcho=off +TCPCRSend= + +; Terminal Unique ID +TerminalUID=FFFFFFFF + +; Title format +; format ID: 5(000101) <title> - <host/port> VT/TEK +; format ID: 13(001101) <host/port> - <title> VT/TEK +; format ID: 29(011101) <host:tcpport/port> - <title> VT/TEK +; format ID: 45(101101) <host/port:baud> - <title> VT/TEK +; format ID: 61(111101) <host:tcpport/port:baud> - <title> VT/TEK +TitleFormat=45 + +; Allow the sequences related to title report (accept/ignore/empty) +TitleReportSequence=empty + +; Translate mouse wheel to cursor key when application cursor mode +TranslateWheelToCursor=on + +; Trim trailing new line character when pasting +TrimTrailingNLonPaste=off + +; Unknown Unicode character handling +UnknownUnicodeCharacterAsWide=off + +; Mapping of Unicode to DEC special character +; The sum of following values: +; 1 : Box drawings (U+2500-U+257F) +; 2 : Bullet (U+2022) +; Hyphenation point (U+2027) +; Light shade (25%) (U+2591) +; Medium shade (50%) (U+2592) +; Dark shade (75%) (U+2593) +; Black small square (U+25AA) +; Black vertical rectangle (U+25AE) +; Black verty small square (U+2B1D) +; 4 : Middle dot (U+00B7) +; One dot leader (U+2024) +; Bullet operator (U+2219) +UnicodeToDecSpMapping=3 + +; White & black color conversion +UseTextColor=off + +; VT Compatible Tab +VTCompatTab=off + +; Space between characters (lines) +VTFontSpace=0,0,0,0 + +; Window Icon +VTIcon=Default +TEKIcon=Default + +; Scaling factors for printing (in pixels per inch) +VTPPI=0,0 +TEKPPI=0,0 + +; `wait4all' macro command +Wait4allMacroCommand=off + +; allow the sequences related to window control +WindowCtrlSequence=on + +; allow the sequences related to window report +WindowReportSequence=on + +; [Window] menu +WindowMenu=on + +; XMODEM log +XmodemLog=off + +; XMODEM Timeout value(v1,v2,v3,v4,v5) by seconds +; v1=NAK mode: Timeout value for first packet +; v2=CRC mode: Timeout value for first packet +; v3=Timeout short time +; v4=Timeout long time +; v5=Timeout very long time +XmodemTimeouts=10,3,10,20,60 + +; YMODEM log +YmodemLog=off + +; YMODEM receive command +YmodemRcvCommand= + +; YMODEM Timeout value(v1,v2,v3,v4,v5) by seconds +; v1=NAK mode: Timeout value for first packet +; v2=CRC mode: Timeout value for first packet +; v3=Timeout short time +; v4=Timeout long time +; v5=Timeout very long time +YmodemTimeouts=10,3,10,20,60 + +; ZMODEM auto receive +ZmodemAuto=off + +; ZMODEM parameters for sending +ZmodemDataLen=1024 +ZmodemWinSize=32767 + +; Escape all control characters in ZMODEM +ZmodemEscCtl=off + +; ZMODEM log +ZmodemLog=off + +; ZMODEM receive command +ZmodemRcvCommand=rz + +; ZMODEM Timeout value(v1,v2,v3,v4) by seconds +; v1=Timeout value for serial port +; v2=Timeout value for TCP/IP port +; v3=Timeout value for initial packet +; v4=Timeout value for final packet +ZmodemTimeouts=10,0,10,3 +NormalizeLineBreakOnPaste=off +NotifyClipboardAccess=on +LogTimestampFormat=%Y-%m-%d %H:%M:%S.%N +LogTimestampUTC=off +PrnConvFF=off +ListHiddenFonts=on +ISO2022ShiftFunction=on +LogTimestampType=Local +TerminalSpeed=38400 + +;------ end of special options + +[TTSSH] +; SSH enabled flag (1=enabled 0=disabled) +Enabled=0 + +; default login username (setup to authentication dialog) +DefaultUserName= +DefaultForwarding= + +; Cipher algorithm order +; 2...DES(SSH1), 3...3DES(SSH1), 6...Blowfish(SSH1), 7...3DES-CBC, +; 8...AES128-CBC, 9...AES192-CBC, :...AES256-CBC, ;...Blowfish-CBC, +; <...AES128-CTR, =...AES192-CTR, >...AES256-CTR, ?...Arcfour, +; @...Arcfour128, A...Arcfour256, B...CAST128-CBC, C...3DES-CTR, +; D...Blowfish-CTR, E...CAST128-CTR, F...Camellia128-CBC, +; G...Camellia192-CBC, H...Camellia256-CBC, I...Camellia128-CTR, +; J...Camellia192-CTR, K...Camellia256-CTR +; 0...Ciphers below this line are disabled. +CipherOrder=K>H:J=G9I<F8C7D;EB3ML0A@?62 + +; KEX algorithm order(SSH2) +; 1...diffie-hellman-group1-sha1 +; 2...diffie-hellman-group14-sha1 +; 3...diffie-hellman-group-exchange-sha1 +; 4...diffie-hellman-group-exchange-sha256 +; 5...ecdh-sha2-nistp256 +; 6...ecdh-sha2-nistp384 +; 7...ecdh-sha2-nistp521 +; 8...diffie-hellman-group14-sha256 +; 9...diffie-hellman-group16-sha512 +; :...diffie-hellman-group18-sha512 +; 0...KEXs below this line are disabled. +KexOrder=567:9843210 + +; minimal size in bits of an acceptable group in SSH_MSG_KEY_DH_GEX_REQUEST packet +GexMinimalGroupSize=0 + +; Host Key algorithm order(SSH2) +; 2...ssh-rsa +; 3...ssh-dss +; 4...ecdh-sha2-nistp256 +; 5...ecdh-sha2-nistp384 +; 6...ecdh-sha2-nistp521 +; 7...ssh-ed25519 +; 0...below this line are disabled. +HostKeyOrder=4567230 + +; MAC algorithm order(SSH2) +; 1...hmac-sha1 +; 2...hmac-md5 +; 3...hmac-sha1-96 +; 4...hmac-md5-96 +; 5...hmac-ripemd160@openssh.com +; 6...hmac-sha2-256 +; 8...hmac-sha2-512 +; 0...below this line are disabled. +MacOrder=86152@?:>;034<= + +; Compression algorithm order(SSH2) +; 1...none +; 2...zlib +; 3...zlib@openssh.com(Delayed Compression) +; 0...below this line are disabled. +CompOrder=3210 +; packet compression level (0=none) +Compression=0 + + +KnownHostsFiles=ssh_known_hosts +DefaultRhostsLocalUserName= +DefaultRhostsHostPrivateKeyFile= +DefaultRSAPrivateKeyFile= +DefaultAuthMethod=3 +; Debug message logging level of `TTSSH.LOG'. +; The default value is disabled(0). +; LOG_LEVEL_FATAL 5 +; LOG_LEVEL_ERROR 10 +; LOG_LEVEL_URGENT 20 +; LOG_LEVEL_WARNING 30 +; LOG_LEVEL_NOTIFY 50 +; LOG_LEVEL_INFO 80 +; LOG_LEVEL_VERBOSE 100 +; LOG_LEVEL_SSHDUMP 200 +LogLevel=0 +WriteBufferSize=2097152 + +; SSH protocol version (1 or 2) +ProtocolVersion=2 + +; SSH heartbeat(keepalive): per second (0=disabled) +HeartBeat=60 + +; Remember password in memory (1=enabled 0=disabled) +RememberPassword=1 + +; Check supported auth methods with "none" method (1=enabled 0=disabled) +CheckAuthListFirst=0 + +; Enable connection to the server that has RSA key length less than 768 bit (1=enabled 0=disabled) +EnableRsaShortKeyServer=0 + +; SSH agent forwarding (pageant) (1=enabled 0=disabled) +ForwardAgent=0 + +; Confirm SSH agent forwarding (1=enabled 0=disabled) +ForwardAgentConfirm=1 + +; Verify host key by DNS (1=enabled 0=disabled) +VerifyHostKeyDNS=0 + +; SSH Icon +SSHIcon=Default + +; Disable error popup-message box +; 0 ... Default(not disabling) +; 1 ... Sending forwarded data to a local port +DisablePopupMessage=0 + +; X11 Forwarding +X11Display= + +; Host key rotation support (derived from OpenSSH 6.8) +; 0 ... Disabled +; 1 ... Enabled +; 2 ... Enabled with User's confirmation +UpdateHostkeys=0 +ForwardAgentNotify=1 +AuthBanner=1 + + +[TTProxy] +ConnectionTimeout="10" +SocksResolve="auto" +TelnetHostnamePrompt=">> Host name: " +TelnetUsernamePrompt="Username:" +TelnetPasswordPrompt="Password:" +TelnetConnectedMessage="-- Connected to " +TelnetErrorMessage="!!!!!!!!" + +[TTXKanjiMenu] +UseOneSetting=on + +[TTXttyrec] +RecordStartSize=on + +[TTXRecurringCommand] +Enable=off +Command= +Interval=300 +AddNewLine=off + +[Resize Menu] +; 80x62 +;ResizeMenu1= 80, 24 +; +; 120x52 +;ResizeMenu2=120, 52 +; +; Width: no-change, Height: 52 +;ResizeMenu3= 0, 52 +; +; Width: 80, Height: no-change +;ResizeMenu4= 80, 0 + +;------ Telnet host list +; Max number of hosts is 200. +; You can edit this list in the [Setup] TCP/IP dialog box. +;[Hosts] +; Host name +;Host1=myhost.example.com +; IPv4 address +;Host2=192.0.2.1 +; IPv6 address +;Host3=[2001:db8:1:2:8401:02ff:fe03:0405] +; IPv6 address with interface number +;Host4=[fe80::8401:02ff:fe03:0405%3] +; Host name with option +;Host5=myhost.example.com /F=myhost.ini +; Host name with user, port and option +;Host6=user@myhost.example.com:10022 /ssh +; URL +;Host7=ssh://user@myhost.example.com +; COM1 port +;Host8=/C=1 +; Replay a file +;Host9=/R=readme.txt + +[Hosts] +Host1=192.168.0.11 +Host2=192.168.0.1 +Host3=192.168.4.2 +Host4=192.168.0.8 +Host5=192.168.1.8 +Host6=192.168.1.8/ +Host7=myhost.example.com +Host8=192.0.2.1 +Host9=[2001:db8:1:2:8401:2ff:fe03:405] +Host10=[fe80::8401:2ff:fe03:405%3] +Host11=myhost.example.com /F=myhost.ini +Host12=user@myhost.example.com:10022 /ssh +Host13=ssh://user@myhost.example.com +Host14=/C=1 ;serial port +Host15=\\.\pipe\vmware-serial-port ;Named pipe +Host16=/R=readme.txt ;replay a file -- 2.11.0

4oTEF=FWjMj`^;ghmXgDz#o%qSYT05<7c~R*7Q52UnDO{RNaQzytu9| zKN>$S!HiImxxl?{U+eC7S;dGt{U2^&kS__mcP z(MV({wlp{PrC=1w!4fAJCFT>jw4;cH5^@~aFzDXs) z=`{Dz@bsxnmcKPn$y#RJoMW1ViPri9NW_Y+;eBpK3C4+HhvZYG@*hRZ9`KUu#=Y2r zvei8G-p@0ixYl{e8ozR_?c})q>(O%IA@TWwNxj3}jDY#v$qNf3KB{Uulef=wPiI(~ zUq-PuaT%fi4p;57^dZD3JDZuKW3IoK$g5|An*y-kg#6tJVXrCUm$8)b2*U_ z-YR=gpHI|52}T#dP*;r@D~lyqG;Pu&2uQ}ewehMFRJ)w!f=_zgVJ@$Reeb{orXK&pm9l;JL@jn) z%BQR6#Wq)=%4Gy_M}EASJB94(W;@!Csk0Muew1yN2Ur7kTeO^1A-O5d*hPf_ ztU0B4qR*H{@+1!{heM2C8dfb}ne#nN+e&ToDsiQz(MOJJ!pdIDn=JRx@S1?GyQBG! zM_>7##&I3;=a!X`kl|4_uh_n=)k%6B2Vi1p$#Qa2)lCH$O{puIz}{?x}OQ4j1_W$$!^3H@XnaQB^=kS*sK1cpeCNq;hO z+wbW=R1Np``ZZur69?}p80hko9!pn4Ybj5!I!(A7i{@;ef5ZyPw z+wXq`Z2j(SvnMh#GX6r9B_#ue^dn+G1L$87mfwbi*q26#!emLw{SQd-r`_L zCgQXZmKi{n{|3CM8>76}kU%X|ZhG`2Mw?pf)>-SHN_oukfVCZs7HsSV#y6tS*VHuQ zd+Q?Oa`rptPt@>3L_aeDnX>ZK-Myk5r?cP7V%A-+9GQ@CeJTyoozP~KX_zec{Q36w z#jpH!9Qu^_MV}b_U*u(Z@UyhbDIUQ+Eyq+ww)@L_-%n8k#`G@cLZYza9Z^wHc6Qm1 zsZE@^dNf?bf}9k3@-4`Q?oU&vWp5z>L17cg;zjTC>X+ij4gJx0MXPir4fZ z%+@$05gpRKTNbG|yuqYb65pW)N70pL#Z+^lg3K8fTBrbS)Us%ImSe2%M_Eom71W)! z?JqJvMJuHIJVl}6dJ7f_$<4{>WHr|^2_Wk}(OCB^+P?|yzahKIjV^;f_9 z=_wl9RKh@+`=pm;8CXq{*K-C?U1@qav*=w3$HL^~n}UK2Ck-PqvSGHHH*fOu^YiiX zv9o6u7QW#82det^6oJp}7byH8!dM)3!9C#o=UFuMa|L<^5MV}h3=H%0^OQ%dCyg^Q zvZ{an`R6*wM@(G&2)I0lKp?QOvH4#DGT(2bzbHuw*MUf8GsoA`?a%P^BYr*=NC!D< zKSf8g6W>4npUZouq@<*%DDHhwqJ3JI^V=I>VLefNy7qXt*=3D*A>sBV&}ci{mlT>d zarPp9er#+^qo4;k4!OJt*Z$$uetdYteoP3kZ{URR)vH%4Dk=c;1!iN#0$W=r>g?xh zWjF4i1E`wdl$1kt@=x}ZwLk8h5H84Gg}#3MIxQ{DxFrN|T0v~d9qsMiN#a&+|F8g7 zc%u~#l&=NHg1xqP*19{N98vvxCK*|w0-$IkqiLY)+TY)gL?S6ED8fL#LsFzM7y((k zkF+4^=~YWIfM8XEwEt0pTqivAx^Q?@)SY+`qr6?Yi2Of=j9U=Fc{I=t_a_RovH}`8 zdB{(dv9L(SfdGEfE!dg$SuBx|&^wb4Bh47pk-B}?t4Rx<$3FX@W1sJ{QR`@^~bV*TBc-VqAW1~zZ%sD_*o0;!L^D)QTrHy51nO6Pb`B$ z>tCbdZ4QUXeILTOhmXf?-!G6hgFgK^Bl%i94Aek2jU&1b&lpT@7VNPSZTj!1D%Tfg z#87TY!7kP9VxahStO$OH1-U+o+zJ`s8p^%Jv-VL`);xk~H-a6sKU5JK%4kh+l$3OF z>D)hD1deU(Y%6n~2wqQB+7Uas~u>=tM(B8y#r7+3+GIAQjTuW>yDT0-hC>~FTa%2*9>3lx9 zFehFhwdwQJ1rV{xMMV!pL_~&f#Ky+fzZoAN{}=i?^XP}3%J~4@#@m)WP3oudUYnS! z+aRn^%cH3H)-2A}C9}t6C=&V!u%k-^a4h{2|*{LkVmwpp%Fs@R+i;WItfze;xn*UhBkmP;GaEcgfMB=Qz z^5B+1#(zvwU&UidgH8x{u-&@80%qvv1bFPif_6uPfoZQe~!PCiWz? z%(OD9)|P~7a;;&93Dnr{c9)kWb!?HDpa%~_B55j3U;mo6bZgGH7?2gTspE)20uW=v z>uD5`fG?u9a!DAaeUK+=6yw6+yduW#yu)u*SA}mWs!Q7MU9UY__^Ux+r++eUAGg-X zCiuudk*DM`s(Zt+gyu5evB)g?%LI||J%+Ze;A6QctWPjE5D(WDvd!2q>T?_4ZIy0; zc_@y@>`8rb_10GTA_fzn^mnehZDDEKdLMdo?P0g^PH&ReK$fy4)jEaffo|aX$k}_I zRfPb)?V%;eslddT*+`7+-F#}FfgQz6>?9E@LPc9l%do=ll^d~wE~{5GOXs|Pt@3LOEx9o4MqT@cls=!T z8lS2gi`TuC%P+Mqi_u&j209YFlr_39A6VwTS!Ap%ke1?n=TTXLo{m2_6V<|^kFo@s zpWZ{3B)u1}26XR)3Mh;R{|%X2_jr>6EOx)VeP!oAtC=S1a4_)y;57oh_EUkQTk|`h zj|=D0OXxs^gQLmk2MeUq2pbN3T{%S5qD*ZFWr$#z#}!nSNNf?{y4 z%FD~?I5dSeq%#CzAZeo0A* zTBeeznOTyAx9;=w?gZf(ujbP~s%Er8?XiaJ#Y7!A3??3DZB9g_g>+=~B8Q=ISp;;UWF_a&DM_`}c&w+){nX241D*^(r%G&o$NY=Ya~`kK7$42y?Q>q{z12 z$syPd7QE-R)m($KJqN~p=_mnMJk)DXNSsSu@YI$p<Ux?Tbb7*=DWrs29&0Xbw1aKr4v_{^<0+;v= zlQ#u%uVJ6Xw-|tMgPs$xxtD&UZ$oX@CV2DA<|^ul%b-u7AV3GL50 zh57rWGsO__tOeCMx-OFVKu7P%<0jGL>civDP*An2_7ykPax^Kz6)Q8 zgzA<$UC`9TT4aL**w>kCsXn2=`sP?jA zamPVbej7a9GZOTq_f~x7Pz0hGn&RW1i=K-kVi#EaqilJ8lVD!^JbI6ZD5yBXWP4iS zDFznguSj0&l*esw_X?MLgWci<9=q=13faz6!eCI9r2!-${e z0@dP?mnQLk(%0sb@Qb;7=RLP!Hk9xhG1%J5N?uM*;QRN(mCja$4}t5Y*_9G{%pU=% z7X6{d?pY~pLU*(A#C}KE#eRLv5Kvy60w{&S1w#j0HprE}EZFjTdsnWzqKOq%9(5B9 zin+ji$~pr|$Eo4EugBdE_XIcUCJCNo*GJZcI5b8Y=M(%#k-K z;r_RC(FZlII|Et;#|H+W!?j38`s$tj)*`Lh1HGOHwlO_-Y_|vn63%<>)ZX8_H?SRe z;64)E+qZ9z4)0eYj%Vf3)kzv-Agot z0i=_K^IO!%$QN&i^NAJQY#66!^qSTk585+Lwf+J!1p~)=ll0Q9GpCE9QoYIBxQ+xw zK9rc05yn4hsubmtklynSDkSTeR|+#veivyy=raHr`S#1Ty0d`&Z*#1Yb;9e2L*f!V z2JFBK2R&k4E}R3SuP?>$KgZ7qFEOKONYHrUJWqiSwuwo0-&)C;h2}pUR|O)61Zt#cxj^gNr4{Jcv%@9p?}d@(?aJ`q3&Xj zAHnhc95Uv-yrS^c)C8FU*{@LNu^FvJ#My4YKTHx9y16wE@T-BF4c__tuZ@&)+`kXp zJvmxt%W&b|y?edpkGPLh$h#jCPkN6olBDxT@}gvTNGxtxD2$}THtf^JvExNIA}=i^DMP?>)HNF7s1iOV)4x>ask_k>%hk-6ag-? z8AYvbFZS>3>>O?RQeXG`!~R=&OT2mz>0$?<6{|c3ea6O%Md+PT?eQd)88Lwy>)miG zOUo@hURmh2xOh!M~`FOV=1!L6$FrfblwYF9l zPD7zkK&1*4yfB}wH@;yf72a$8upd6>ek**kSDGZ&`e!(@E7L#!GSUv8eBe*K`fqi6 z{@TyokHDeVTO~;!|Ez%Q4EZd&r=SD~ml2&ha{mBu$A7+bGiqzzdtgkGDRBTRqdz_{ zE`9pRhx>h&*)Jxa?3s$PUCJJDKBNMt*elmpt=>=NF$D`Oy9zM0ms}Poil{eh>o$vR zXkz)07Oe5%;rKNdd9Xmd-s`Ih(O;Q%RtNa`&Sw;^J5{>#eH8mN(j{6Xvru6h=4aN= z5lg>WeJ2%)xwiVb?xI$&ZY$ih-z=V{DpV8iIxRSm!BXkGHp(zAY*R7x>^t=K%CVy8uc z=Ns>B3lit^Ps0eC;ngEJ2(M@nJ-bv%)PYT9q&hDQxby=8rCXEzA9A}ciih-N)^;^> z1jYle`nUk1)Yu|8PO5x(`YD^`F)9`WwtN+SE}nVLgk*g)xRh$fB5D?W|EN@uvLGH% z15v8-Cbr#;a}F(quJ>7NlE*_*@!_ts=-t}6pD6f=+an|Up16XBH-%rg!_R!)-W-Wp zaAs*qdP+b_m`C2p>N}wJC&NA^>D|@huNP{+bM)2(`}fVhZmJzYlT-(VGzP2k=Kwr% zH~-T7`|=lYATYw4g)v1z2k@@S`sR9j(#Mt9w37ENcnJ0gGr9AF*aAQ#ze`K94J7~- z5~P1-q!4MbYHA^F0vth;9<#JKapOshfp0+qX^@l`npQ?HLxEw9&jS$=FmO zW!vR_c(?_TqYIH*UWOyi4}SC_=?xD-CzrORV!_6X14mL;1cL8{pH!Ov@x9)pLBzq@-D-nL>NXjInKXH2EgP8qBl#~>w161yVsU-f(*oLpE- zS$fh>rpDQ*Vh$mVSsTif7}l*AQ&FW+57Ck*TN&If+a4-^8<3J|R^f5kKMECO8^gIO zpzx8Y6RyZD$;}x3@M@uZ>!he>pKgy=eyv$6oV*Lz!6%BS?)UffRqpxlyqz>9v1v(QXh`750zt?-jP2WTI>0Q}uSBt79@UM<;`oS$yy7VO_1ESWUj zPgfR=Lxa1`o4RH`6=*?UhJggj1Q<-&)<72r*+m2-Sdcm8#j5(wxF_{f5wT5dmQc^K zbY_`EU8thz+G5E*t*{1H>8ja!*^osJI_>O{$z=xca?4z$)2R*x@f&odS`N-1?qPNA zBQn%bn~NpoGs2NvrCrX~24g=r&PHSgzI#v>`>~=*I`TH<3SBYvVrZ4;L$PBkNLZm#U;KL_p)Uv27?j$ z)oSHn=bSHm7Dckf9gONnLN}cuo;o%T(~@njlWXFhGyNS~dUl%Q8UvT%B3EfWAC_g5 z^qy{@+i`M6MZw#<eQ?3p=*i-s{C>i3rxX@R27*Qn8iPZgL}ScxW?XSG4AdS zu1L#gZvJ(y)%W^ObIm&h@U|rD28u1uRQTqR)Ba~IT}lA z=&M;}a)Z__2L;lS#;P1=`jWjNmVtvdRktWTDogdRDXQt{tbN*7?7*OxYg8u*Rt!-2 z=l87g_^3u#2eIQhmLfElR_ngUXX7)tf+px-g=xGJ1GfDrec6y9i}=J+q)W*N}G$5s_Sp0&5{PrBdiOaeH^)RrE>ML0|HgsF#BwZ+(xoHMW3;yiyEXJHdUGY3yJkV`!iQ) zg$Kx!5=t6er=qB;z9?zUMr)q!*3{4vL}i1)RU>grIaW)IgG=1dvL?%IDpVlWif8)i=$%VKn_;l=sWJ8OBmDy!^%tD#ZwrEM(HiQdZ@ z4Bp}Qe=>p;qE-$XFE%6neY~)J>S~RauF7XkhdZ0kT#Vnex6uydEQhuf#MQVf_B2aJ zW-44`jEfr`jbBnP6$7nRX9B*(-e#+Iqv_3NjRi7hk7Dl&s;IO-f}==ge09WsTh0EB z6|Q?HR3z4}-Ht~oGU)@zBSWI#$G~L*aQSWO2_(L!R|J}BF>IbzdTV`UYQs0Pc#r*t z*p=eVS2i+lY?{YnLCnD~OT6&yJ&Cb&5cz$Gf~l#qZw7YpaA0skGrR1MKPb9yjIG()VLVeT&X5X-RQ53jfw}i!AzDG zdjvAl)^tGgxgYS-AuYJ=q|{Q*QcjoNgK_ry(0M_vM6rvP%h?}JJwu?rEsYmBzKVp> zeGo0P))jydmSl2M`{lRJgDk2cU&y!v#ww+E}Po?)pWENT{+v1vZ=Hj;(pIg?xJtVyd>nlo+P z+$*JFY_DT4b3p26n|Avl{GgX5_uU$j$}JHJ9Rp5I&W`{`%H7Q&G}^13<*A~HShXI) z!G$kQfea0wIP_Wsyv2mX@#WCQ|6Lz`>q0cjsmxX5_Kgogaci!(Q`PsFpKm*rmg3fh zX;#Zju}mgup5)8l&2oYfA&bdkLU@p*Av3#`?~5u4+0eD&Wb1 zk>+E97vMU*({pMy(^UsGwFF&UMAQ%snxxK#ta-x(1Si7gIp{jg7c_jw*v8!2Cf7Dg z!iAUf)sAZrsu?cNou6xCy}Dq@pVQh~b*pl3#92#2Lw~fdHz!_MzwNC4jJ$@Lu|5caFfZs}2R+WDzpA)%-~J&-E+eCr)$)$ULy`1g zckhhy%#gipr=5lFmoU^`t(GP~>MVW~^CdqwD?jg|R+r`g>XD^xRn@h4s}T0};p&4? z0(dW->3&Y`w5MTK>$hdgCc0i{e-3f5j;TX>JtQwXB|l%uBV9kSJ6d7E#v0KfR%qih zjM+#e=tefHidN7Fl!2KHy`c&a*=ReS!21ryQV_0@LQC-eV*5(F*?5VaOvr&{WKV5Q zPJX@$tC!$8KF)-jqI}4bw6rf@lB;j!ChH+Ad)nvF-ZN8#{QNvia~q(p$qC#c>bUl4 zF3NE@v#(y1xLH3pfZ@js2%KBj)N0F%TeDfR5V|zv>usOM{-SxC|;11#ombP`vAP3yA{l+m;3`c6tvtrMKf9^lLM_hA<6n?`=7u)Hxh ze}Z`b5b#;{(?N!zUJhLg)K6<4?tXBsqY;?$+ek0$PrJGWnITqW$T>S4FL6Ea-huPS z9gIb!a0u`W45>~;6&4gCih}X;Z9%uF8~?E#E$$m~jVf5L@9Jf_w^Lf#U>Rqnw6;fk z&^rXfe8$YLQh_VXKjnv3)YgK_*i7gwM@LI!AmO`fG0SDfxp4R-E|SAIHzz?SAHo5A zL11=$93?OKQHK&&Ficy7;du-P4WR}yni1zdeh5?o0Cuavx9PNXS3xdgWf7T*I#*Ff zwl1d90$Q_Ymk_PJU>cDZ<-1rhK1X`Qut(ZMHLd+G(z#si!j~Bz!1Se@%wK)KX1_## z=E>>AEVWW0rY#HkYg@ZEu{A7ivJRH>^{-WXR*X zQY%3o?aFyOcYPO|t+tDkbd+v)kqrB1ZiI+OA}pTE4Hvo*(rlYy5^JODnMyi0icOSV zV)IvPH)Oyb91eCe3u=eHnu`TayKmXv1hgwH=BsPfvaYw*Zd6#!xCZ=l8nIf_7fb^V z8Pwnx_U6%bj=1;;HiPN$y$96|nqnPVXno%wY!@O_PY5cz&Z$^%Nme@?=2U0%PNn|r z(4y>>T7tQ=sj&~KXyg0hr1G(RIRh;_p&MRHc=g=F#R{K&iu6rX^T5wPU%#C9_T4+; z1y$1hc1!AGn7RIpF47da!Q@pWu8Z;+r-ZvEM+C^#)tphuw2^$d1?ezRKTfV-nSi)# zBo3oj8gaYN_sy=4&XM5>8(nTr$2HFVb?X#YZ*inJWwlM)@x5%T>a5u9itCSp+oi8R%l2wc%`$SN`f4Vl{_T>;{7b ztf{snJRu6xjoB(G3@#G=`&M!20T0C_oeQVdXgbE*b)7ola#)PU%dxJZbP2tjH-kc(LDUngV7u z4#I~v`T23h3OW+EWu!nw_s(T@F!IM%240V73cSt*?Q+L@p1LJqtGmctDlT^4avql` znX6^{@q>t-cAkyxa<^P4_WpTe!kMW`7g-tWPzvpGkHHKbQj4;NpeUFzH9c9vbML@! zv`iL$A7>Q>9heA*GgVm(;mF3%x>B%?UAj@yZab6IDm{JHQMu_1;?QGcYbWKeN}9Fz zBey^DzQXy>mgGzmiP8b}nmorgBV#%pnyX`V>_^s;iaL(at^5iODS>rmb!UF30nJ3Y zXBTvf3}<#oHy~+}kI0Zh7oj z$jMxA4ye2dnT%@f`ip~@irRU(C=WVb&?l!19AHA|SHvC?^p>Ue(&oa zvmx;b2$>Xa%l4oP+Qs5dTDqS!tqku~R!XbIAVItiLC1l?(`Qfl(d2K2hCFMZr@9a#t0o%`u7JSYf_a&1&wc zK9H}k5?}UCb{(7Kje9}d-H4=w5gpp4>b?d)XfaaO72?Sno`Jx`-6y zD$7W_c^reC`Y`3Es1eskWVIj7IBYWgj9cc`*8O z-kaS@e){jXdjTy>7Hj4&m_%bQirapx{ak7fy8=(nY-akLLQh;N5vR&$rKEedk)33-XR zVecIG1cUwVg^n@Rm_|%)>CE5)7PcUYTCzGm)A`=t0BA9mnlfm6vieASV$)KY9`mbD zU+@#7a!H;?!wAz;f-R9+3!2W(PEJ{aO9yAh`Qn^HEiBD1)?Rj@u#MDEr|5duEG-06 z8lDn$o_HrW3Do49rwX3EEWW>B?yMPn8>Z>}s4Noxf%06Upw(OwpRD{q_>IN`G%2@5 zaZ~3Coli-5ZB0?G-QI*EiO=la8c%la0s!vjU~s5@_SCl+?>eEoEcjgZVxostCTAiL|A(ow z4rr=<qJw0g;lH99^Ra%%TOPn+b?CNcTXHj?oPxH@Ze`EZ*bu zJiqsS|MCwHXXo5??(4e0*XO%=*bNl#s-?5K|9U8wvu#&gsxil~DDK=77oVw!gAmT^ z7;5Dz6T$upHcw$r(lg#-W@oQW$&?LVcU^oe)okT<=8GY8moDvw7dkj^bpb2NiugQu zBj__!J-?EzL%tmae$dp(S==!w?>Xvq0V9x}qD`60KoSYf%B%#Y-qo}UGOm@8n1 zrmXkb#@7bpMA4mB`c3I?-DzkpZ_1Q8(cZFdF3o*y2z&44TUDK{V8}$vy0$B9wK@N3 zquePn9K(yL)b~Rhdzg}p=H>@|AIXTh%&knlxT+GE-7u5FF#IWdd;m_EJGhmD!zOsp z`XxAMX!K2>PD-lzJ&Yqt&M8@wl4V{9Cth*7&EVx?VM_!rhYd#P@D*H?!VFB;ianGz zHOy`pK0tr+XQQCQUG3PCn$eudNUekQrnsUs3=`>-fv|7XCftJd^M#*&tn{&lIvXoZ zZ|Fo}*s~QKP72ub?_a`lS#~tl0`3ixAv(Cya}l zs-+;r0`%-#rB6wnwifwVfip@gyE&7Lo~?ULb9=CAJr zq1mWNW}j(0*}!@UeusT?a{o{nSjv8e0|$|-`nfY$a=G_{Zs3tD=icFOLaj%@(0YUL zMtW*w%J@(Ap>S(HCXnl}2x^^BVKv?um>L^4GN4;C&KhY{$=kAL(^@2V*>!VVK3BnN zrAmx7)I=J(7-b(2($!n4YrhFGe0x!Ez^K`G^LOQd`eN$7JE6MD6ggjyk$>x?pkS-n zKJ<-P)_~dJ<13PM1ax;=g@xCc8%c$ss&bK=Dt6bP^={?2t529sbd6j^w7tAv+kSNM z9!994E?a0hkEh4e z4wK%HcM~tMazE2yPb*TJ3E<}BcHg#a&eMwbQNOayclijMHIAHSxE&pnJ=Rl7H*rUF zMd2!;Ho!g!p{V4gWN)l&w>Fz+Oe5tsZ7))nYu-lS;=8x=-goz!u)1P!2`<3H5{O9(fW)RXI89meC zOm~U3OJl^?wxL=^n9q79MVW_Ps~3{SoA@30`p+>73Ou$s+jm&xnG!4J><@%i_s##} ze4GzVXfGwGg#!LKu%WFc*vd=05Ubwlj5_TneE-v^9WU5QW%gwqT7&a%FxOMj_Y8L+ z`B|Q{T7BHi%2JiGpZ2XR&f!ylUcfj^HdgK4VO9g_vCY`ztitA}Z4=<76YN9)T}-l8 zGJhgycUA)MjWjngaIA3>V$^z@-A@ItQS>^Ua>o+t3b`wG22rqWteBSZ5auNm|6zpimru)!Rv+BnH6~)Ed zJ3BV{&+gDS$+%1p%+9J*X_Abl^s}EO2RyJ_EJ_b9=Ps0T@6By65Efo))s0APUIr$m zhYu8&@huP`j39X~i7XoSPI%$t?#sqLDvF%)t(~1J`!`T{|8Jo10gcS=7_zWvPHs}6 zZ?3PXP?$XYSYhz;#6v4~PuE^gPpiQxGs`8!<$J3A3#bx+Rw7k!z)Bo!OQgLYa5!{- z-B!MP)Di!(ognEjGCCH$K33O{hH~J9Ph#)Xn+=F#iJz)3E3I?>Rf2p=9 z{~4E`Zr{${ucBiHHFe*wneT!V=sGrzFTFO&L@j@bEciLxMiZVG_@#Zl%}ki@G9@sx z&YY;GeHxv=^ovT;K+HXNul3vMRDNtlu=FK zvep*a8(X77-lEn^0Xa`x?s~F1rDpW|xt4B1%q-p|uKX6JGuSO{=5hKAK|J z?9~gpwAs4oI|a?;cNz%4kyOPgco-u1@@dA_8}StdzL1EUl(KW0V=-RO0&>YUst+UM z58BRqtfp{6ErI%i2D*}snQVTi?wKar@60pzB(d^%&tI;@OoSu$Zx!Y`dG# zV?EDNT^1>tI@@u*3cbshoJ9%eLdCUb1d(udLg(g*yO+&oWRARJ%27`DqS8rNaOx^@ zy2DRxyt?Y6tKkK&dtAlSw^9*O6=k`F#iB3`x22N0%+BM>r`t1kX_AKC4)MzJRv8u+ zKbE*%s}tj8_i2SKkG1y}Ms)Ilp4XX86)W;q^nWKxacK=stmS8NDl|{bs}_ z2BgQLp*Ab*OhV9JHlmiVVQF}P87!H{Bjc?c+cgd8cnu|>V^`YxcIRp1(_&4QUYGg* zllh{r{O7Ec>JK4#WLasRiR&f;QEo@>6~L6d8_FIN6Bo4|wVUg3Kku%pstT#t8{Zdb zmOhvQGw@Rq*HV{nrUUSu9=KyEOg8~^QUasWf5s>HsI-2vi1lO@Nkow9I7BT;J9%>r zH>NkI@xriiI|D}S+t29jNd~5GM(L&_nNMf`>_qOUSN$w*Xj1khLTv5UKCR_-g?u`m z)&&D>u}!$W!A9h^$uALi>^u=%b@URIepd}lTivgJ?{O-~%eHdtD)sKoR4K=^kLEg7 zUfDm7-Iu1v8ayQ`NItIamh#>KN)bOnSg@l#RMpIPEi3)wM@DL$)q?4qldRkdg^}^G zaZ6hwHfGIO$_wq4C!&r)0?apoIodJ{B@=K}hb0m6dSNyqwVH#)aou5S!`1Bu2QLO$ zoU^f%RE!n7;-D@uJUsQ@eVBm}SHZoyvhypDc3deZex*hk_F-+rng<8j#bX>P+=J;b z_n8MggsFC@3H&X2PKx#l_C7|F9eW>E?N6LdZ~0cPy$VFYvo*1aSFiRNG0@zLeOFk# zJ$Nz_9~)ok-1cKZZVJqkmeyLbag6^FVnuP!Ps%5yboc8#20>cbl=9zLnTl;TW^^s6 z{N6TygoMi7!=E|N!e@u|cY9|3tylR>`>(b#3530Pm4~~~P&DOBCo47Qw7T{$bA=k+ zLMOXndKVHefpy+?xxT_USDK|H;1=qBi_G(!ZUZ>j56 zW(#rx6dTi(L=&$$EkSaN6^+(<-*xiuQ+o-m-aepD6UGE zS)I5r;1YM#*PnA%`hNjf_Ydb((|Pdw%uQGs#aJ` zwBz_Q$J~HhWg-2BkXONVCRs2C&C&(JsR+qDuC?49~tsmIKqzW8BV7 zz4IzABDLJlP{j{X*%HA~1r_1(4eO@-`xGiF+oNKknob(I)%%uq=6zX`Pq}VrAE~RG z$sy3d9%hU!;P+J_9_}z6`PI93r?{4@0|(NW;=cJ;4g(XvyCHGFwCepx!OFBbP89#I zRKx$@+1^LMnZnh^A{wjsV8>e*<&}b{QEG9`-mcD<`U}59+b~E_)T3uAaqinyV0L!K z(faaB0x&U3T*ba&8fd~@+^b+SEb8aZTICSJ1j}c|LEs8wf`lm{BaP7sv*SWc>Y63f2uBC$&orLZ2CR}4O8ut z(>Lb6fhsfe`P&l&{laa#iE(QTYxv~-%3Qqzg0M^uAo2MC27t8`J>B#u+L9WR;PBDYEk7( z7>2$Rxlk_tm z`Sj~YQCm(>>wRWp#{z;(VGVzZsFUw|ZNAhOz#fxvE zy*c>pQc%%aoRsPbsKK}l-gz0Y)dFJSa}HmleCl;FcFZ6(*4-~V%Jg(7@9Rrt(yZ2q ziC%2Fw*#?gY!k@$bAOfJiJUL*cE%OCV&$mrT8h}!KU2Zd$~_b-Np9lh2%+%(PWrdV z`yEh200<_}p^^>{YaO(F30QBS&fsbQg`t=;W5%xDy7 zUNuh4;ax}7gcz&Tcsm^rQ<67_!kXpdRivm|LF}2Xb7ZJ&^xINE*)63IH0#u~=k8I&@NZ)`H- zq2oK)-n7wi@YJz5PX5tUpIvSrp6n$h+lwSxsN-#n$my z_?fkbSxZcDXN7iuy|6n4`)k#3(XTGQ37m%66*rfk49GAsmRZ{S=~fM8v@c~C04G8O z;6%uiS<-}y6rH6$8T(*PD{aoVT%(7WjWcirhj9pQ6?p3m-hmztAu7nuYN%yJ}SR^JYru z(wC0upX!U+-CS~hdi=NW*Y(S}8jAQ0y-u_E_LFr2`C5k@TjMjPSu0gwIoNxSQvlne z*DV|y`HJCWXG&n_i3{G=waI|TAnYW#)VO}qMc|%;Q7!JBqE+n9&3^n9OVs{Dp-% z=IJ1<`}@CxwEFaaNp6fzA*g_Ky}%@sz|K=gUO!MDt?zuSuGQ-8yLrx9aFyvh<>1a2 zX74E<@i+#?ie>b?{+8ihvWxz)R=MTrafLPBy;4`YVEz{%t;{`gu-Ern30n0ZX)xdX zl-Kw$z8b;E)ZLd3kz0OCy^>5yE~q+qtuTy_(Cm)ps*su%qP`rY=q&Zks8^?xF>G3> z^}@tjz-@wr{djpu$cMqMbclFII`5dr$ViT3pEM9XO;320c;ke@XHF`!9_4R6|K-&P z{s9V7fhvp-IIL*)JS|)}4_g2JGk>1V&1+rHb{j{-`KMLmq#)Mf0&J>)HL$;Y?tqN= zSrDTLmqxXHmD$=X^jK2URwr zBrB^tOGC#|F1@}`i(UzApIfi4Qw+sA06H8C3r9zPxp;3+ViKdlpQm2cVuhRB?v6Sh zfLf1v=}qCG-1hpoXZ~13)!0itznGqadd1i&L6L;1^={e{O_vn-#^6fpw0m3Q{^A z&DGWWRvJ6hhsQ3JQM7n&E(M)Z-+@Obs23x?JENX(w`*xL zz+XE0-N^0;%8=qSh6@?Xw6@r(U9tWyWn0*%Y}g+uw5gOdANeyVWdpHZTvF^{V^1d= z?`WrH99W<-I|2w3dh`sko8J=W%3Qp?w9Fvtr|AAO&#m74RZ!dBD`>q4Wk01yyl9YA zSK>s;_^93u&_%}4AP3{qoAKbS$wn{C&fceL?uZIF*Zv(3wG``$C~F}7qy$k@lT-a% zUzM9XW)o094Hapv`MQG#YQ+ub2H$8+d{4dP(LnM9qy`(>{=xvF$){WA-|g4o|HS{8 zXaU&#)RexSDQa+Xa(H-n^!phS&iMIrg+T4XC}-jpJNM~+XP<^_DEl)RKks=p@qA$+ z5d%kvzkj#^AJapo$4vb0Lhc8cw6wIx6klp)&)EChzfiXTr2&=#d~9r)Wi;e6AK1E` zeSsQfr0-BGG`Q`zW$j;l zu5S3Au5r3knY&i(-;9dO=?Lpaxp`LU<@(Vb@|@ESJW#w5_G(57mKxC8!T5{#WP%zb~vz z@2OLzk_g%q9UaZ9nnue&!(jN4n9UL%#6i!n)UGxdEPiq*GCq2ZlA%uD-@obad&KVg z3ja0ystk!*L2iwD< zY}bSB$BxqH)cE)kWG(6$*mQK{HcTofQzDL!J!hJplh@bBb!Ker^72NswY$mZ%6?SW zw-!AN)*7{|>W{raw!p+d{ylo?`bSC)l$-n=apTj|2E}j3#>Yg0tNwK6t~wPYT@X&fgJa_u%jL3vYw^2tWm`b=1_FHo&d7e!!*g-ow- z6_rArf(pQ2K~!{XY^=4ppaQ&EIh{hu*i(Y2UkT&U-kg~5^vFM?)aKT)($UfJ@Nl)A z3Z!l*Jq=35V&4AOTIbHS{|&gid)&C~8~VDm_1XMLT9O2l30^Z+CH|LzBrA=1%8ZVJ?^&n+$-oW2I`-xix1(i|8gejx6nxVE`V_G@YH~BTq?}m z*>Fg{^75(}74}hp!t;FX~Cj-l$ELRltb#@+IiPmJPsXHqy0>IFQ`d}_LrzXm^+ zjIAvDVTE#%GmLc#6t`JGBO589E3vL1-u1P$JahrWYEF)hvGG_yz$ylA`pnOJY-3Ev z(Xn+PYZ&OUf`I|`%rch{saWs{1_?kY@rD0u4MA^zz=9VjdQM-uL2-}Q1x6~0ibAR9 z?R1+s7MBgS7X5DNf%hjqr;u|0(={%TyIaNIC~C^bXS`EPkyKoiTm4I@arg0Dem~MG zM(iZ0t6aIp@?5!qm4MlE46=TE2+87)?IpBk9UmX#>+8AAq#!@t=IVPQ7z63Xs;WFZ zJX#H3Ud&8(TCJFA`%CkvnRV;^Z~X@lCEkFyu@}HenF3aSb=qfur^p21m?b>znWz}3 z8E|T-f96xx{zYqkLwF9{XJLtJs-M%@cTPr#G)_2H_nvOfXX|$Ac?c_;&UHX9IbSax zC<-X7aYQltM>MEi$%f^6t>ER(j$bwG+@o{dq;)e++l4>-U8*7O{wF*3nC#b4G|lvBIALcxnZuoClDL&~Yi7mWyAcd( zg}OWrtrUx@z`<0)U<-S91wb8LRQi?^_28yk&21SCk;pEk<_I?5uWL8zIudE-0o9~6V_dj{y)VD6Uz=QhqH9Gl3+I0JUxpm_&Pf;Bfh}O)faAYt_ z&0W~bYELVRCavEjA0?cYyL!*buQZ?`e9a&${Lr!F>5RodWB;n(aVjUqEw}j=ALp|d zacXhOaZ2tVY}kf~ZhEeC!N`}XHd!z%?-P!`c>$jdC${=GFvsyPj2&lL@JzKz=&2skaRzbPEXEsPe;|}v%0e_N%m`lv265%cX=Urnd z#}&R}$^L-$nv%}+izx}f_1M+Om;M7Z! zgRZWx;0n^D+2;Wak#55^B$UM^xzBjZiEUc3^3&QA3RTbIhUCXz*S_tgx1P`cO`l~U zf4))dojdc8Y3TTEP8zGV8u=`Z(109g?8hk<$nNIMY%U6WC(3lvyLg$`muaZ9pP^YX?)9i8jO53z`2dN%k|o7?hFV;M(hjM{$XpHWP#Fl|8(JoG zGhtd*|7*PGrQNYyHPzK&g^B6fIy$1}e+mnanXaF#ZxdFTlSP&2Zu6--I_VaUF+_Cy zx`99J5kJv$Ps*Dl|1^6aRFfm6c3dJocT%#$oc;6Qi*>FZ10u%rJt1&vqMmf5q+&u5 zaVT(hoN{a_^nt4Tn!9PnoHJYDPDG|!kH@PU`X~3kh*?$(;e?g%aT@B6@?NJ4KuO6ks_M=TwcfksfLfca6Y zl>G8h6~m)j#9+M(jOD1#LnWDRXaC;*4!5+&{lS3~NSB*D$5>e|_{*AX4o7}A-;gz# zI*4%z$nUx)rzVx=wIN<7u}CT0{U>f*n%vPrj{}!idAvP#u4UE9ugdQ;^<^lz%M5KY zDN#VH*E)rxY@+v=TOkiqUTG_cq_3SMAWw@C{j4GUk9@zaUCok_R%q4~v!1BWK=PCv z%0^in?}py^Lauwjz-Q}8GX%$7IH8HZq`Rt z$CDkav6I&7kCc7~9Lg{0K!YnEW~;qH?5d?g1O0=T>raGr0lVUDdB1Gu(h|*GJ?9-B z@tu}DuYG^wjDM*|>0tz3@x9-Vr?w!%5h?8WxG!GO5pU<~(nK{}By-DIyaUlECQbxE7b5w8W`~!n_ERzM8M9`4sP$<9Elm@Ejliq@A zCNccm70)}oQ2rCMv%Eh$)eG|S=$|gd-)*4Yo-AVr0@d%|zi+iTKszf4ap+OEK&VFp z=U2l$Xbu!52-=8f%EAAv4>;N3yBj6$$lLg2ij&Do;`5;giryD`dtOj>cx&tD#6b{0 z{$65WP0i*#_2xQq(K}AV_qx{%m6|V2yODSeW!n&hsgQT*wlx?3PY!w{-t~zh0c<%y z9JuNa;0AQ+&*4~^FhB=%ha0!!J3#T;OGL?`Y^E1v1=Djr3|xKT9GeNbw>%D>Z3wCh zk@GZoO#wbT(&f}I&ZYnXC)2dw7F9XG1WWi0EahQM<=G`yk1-4T#wA>S7lY@KE5?`>G&C?@w(g6*iAfm&H88vs75OBg-_Z!o^ zg*q$f-pT&y|B@`-8@u-{09j>}Zoz1};2ippsUI#JIu1d?mY+?6_70Bn(^_WYLF6ya zM46bEvnbkC>=RjxAuJMG@!w<+oP3=klAoWi{5mRKTUXcfWKKXJO1gF%s$m*W**hF& z!BnWSE&4;}d-{75F1Z(uHqd_`#34iNnOGFzmYSe|caM z!=2Jv7`-g{sxh&x1(YA`xSy>YvG%c%S1j5Jeg^cVYb~^ z;dawY_jn?!)l*pHN`<`J`CDd{hN1Ud4wzcV^R1BENF1hL7YcxNCm`+14@?GR0xcj7 zAv#j?@rAN%PON+I>r8nI{*vV6_m_wGBmJC5cgYlFzV~9eL~++!+wVw?!D|$erGcS% zW{p;J6Z+=g60q?-;afxw5B2H;QxSC6k>7PaUwsw#G@eSr0IBdlyeB=wBlWb&!NCW> z5aoXIr0#4dF>&YFt>g6E(w+pE65TyT^2|uKOV7;pF@ELmSMN;#Ml1h#-gFR>IVhsq zJ#v>NlOoV}G(`e8wNLlLtRNVdkE^yuf@U#4miCd7$iCPWBz%7fs4WzEVj@Bc7%2G@WVn=gEE`)J>`h`DXt4-*Jkl*fYyR*{T#rkMSp}n z#2d)~R4#<8*4|kY;7WD&O*JClHEPOv+WvS|7z~*pscH_YiDN% zAPwWiJ}oURHSBhfnW>1^aM;0qxbuR+RZYCZuQ=KX?{*wEkm)u*7dN_Uq-NtJ6@#R$ z`vsAy5n1`xx;`DMi)FvieuI&}8xD4T8Z3jqJ#wC4*+%MxGfJ$fqhHd7<3b}mX@nOI zImftOSDU&CNzZy}D4L+-yGcw=j8x5^!0+z~1Rzqqp2dO$7KA1mLWb*RdmaUR{q94W zZ3%~yi<{Fl37sL*bp%|g^ukM${9G%X|GzQ+Ya!Jc0gQRTWlpu)Y3`Xn{xB}?4v*ud zz`#JSIgi9#fooTUff7>@80lhX?(dlCYi5m+;<~ORKblgX=>rdClJw`qGxcTgqSe9eHO&|T?p{VLyY!Z+!M2(i$*AqxqI+wan7>@X3{!#S9W#6 z9CQM~v;*&O(S(huRmOB6JU|)suD<+4ou9zi-Ct5h&UOIywaahm!|MtgeBw)i4+tDY zk6b@oZd{vqL$pZR_uld)EkKx>Iu2qfJKeq&?j?un)mM@_RtaCbUJjg{YX#ky$=G0cW1kcG+lfS#}_S8TgGw=;1|>mry(?VtgX!e=Of2JyU-j z1A~;i6>-G@NszoxsMp~z`!DRKw?(H);-eCgncECB5BEJgLYZ1k_#N`VE5tNuJ z9$3J)>@Bc_zuNLu>|CxxUrBNEzIXrubsb@aR-(j6))@}tY!Gt|U&uob@l{JpV>N47 z4CD~&$A!$az+qV>{AAnLiHUx_TYO^wg-U{lUzw%E1Ox=w+1cm%rmO5hrwgBfmN+u? zb#5je1ANQn<>h`x3IK`=@Xe_-OmE%%Tayn4wzts&O5tVl5Xo;$$RX4=o{{XV?i*YC zs6(5dqVX&Hlt_u%KCeK3RR$=W)N}dqF@*A}9B3wVg9C?kOtalxQR)qJVPy4RP6Qat zC745rPpP3687*bit*jq|2vc7~V6sujgJ%MgkrH(|jFglbelglO0j+H1D ztrtpGM0I=vkv~EakzkLDbUG}~U^c2mdbv2HTv+s19Aj1@@94P8PZHLl0o_K)H=^uSvz`8GKzk|^k z@N9(zPMDdQb@lO;EX`^R+{1%VfH9evi^oA3vs~6oYGy~%sVkamC zCmurQ7d6`7nHV|RU?s?$=4k;)vVMt-P%y|l@i7ZMzXq_NlB>N*9( zq%^U&s0LuPNMONbSK0+Q+VAb4SN7f#BbvV@HqLiD&$S6SjqcWcZo@1RR*lo{8{}I{ zr)juToCq9aFA3a~wPw=H=;Tb#34HXYV?vc%us0I-s5_}x3QlKW$|K&|d%95)$5_!_ zcT@CnNpxY*(@z46D$0zpI2tG-y={-@Fur6?(X;Q-1ShBNN^NMcZ^lx^O-#W9w1V-# zvec2V@xHUY-s=eU+@2@PYVEBRm?UTAb@#xP!jqO z0-=6~GvLMpoJvjP--+CE|6iy@%TvJZaQGpNB?VUz1E%-{O#*ceruV_G18GLV!~eMZ z|2>!1msbb{QdBn zw4t!nPIlAM>Bgt9jF;NKSA|&CP}KC3$CR3)LpQTP-b-7p$gac?b=v-eKU2W;YP|UW z-{LP&<1?6YiQpqKBoONKsQwehUv-!_@Dcg@I}1qw3-fH%rmEmijqzCeKh3gN^db#J z{`&Zvjp&fD{EoliBVb$t;Ge(C_6G}KF`;E=#UWc_HvC5NB6VD zL%!^OjtZ4sy>fC8uQ`|9xz+Uvg^_j7KtkZ^}Dt z4TcXuED7HO0)eYXL}|7<{>-Ue4ov-5c(RR9#tE(s!l`i@>vv;O$??7>i{|4Y2Y=yA zOe)86-M2NQ-}Z38PGVZ`^V+a7d6X*#XheRXX5??g*)lhjI`H|3oQWW+Qkm}iH`Vo%cELg?qx1L2oewemUI_Zj8 z4~fr4xv-;eJFa$jFF?8cA7<{wZs{Ywu;V4~IN1vg(GPr7pbgQM2i+oSHiJc?d>C^# zvwD5n&lnIx=Aa?@^L}MP1e|@AuSsQNQk0CMwz_s-`Yi8#B+BPP&N7V&tVn9;8O89jg3(jl;{FA>pKfMz#(#J+aZi?n9c>`fo{W4^ptQD(E2z2ot*SV zUrdi9SwT(!IX6h+NmZf|iBQU%42CX)L&eQ|r+bc@@}W3uKPx?F!s|oNEER_5n_;Gt zc>!!9PnC;^Zl~9b^{(I_y|iCc+o^Ug^?vIQC9ZRHGDdYZUL?N4xy1L_{4o~~3IZ@V zp9Nq6No^R1tj8viXJ8Wrf?-y!5eUT0yP*jO~i$cTFq>-!7s80@#>8a7rN~n2#Lmuq=9$ z)xtj--cPY&>MztDZq7&y-^7%ZaQa4=mM*R~h+~sbXzWjH3OE|@ZAp_e!@ztpa@~9h zK|~yc2kw79xW0M$Fo0EQ-{R2m3*0j5cGGha6;LpWHhpCjf8C!Eh-pwE;}Dna!d(n| z#)|LX=%Zn}8}`-vn~hNJrZd26h`J?%%)ND%EFagi>=UCZV~V6byF_MQd~kxhCf<;` zd!~R70NiI}74Ez|6hc6N=1>=4CNi0aq#g-K zZ2JR&&soZv6pe-XK5^a?AM(y&5nO-4ke^1}{lRv1O|)&34bU|pSiol+YJu;>3|i3B zO~!%f@0l5Gcd{O-TQv{Y)TPl5us6QOdz2(S{d{q8mqRqmnH~Q@_&LZV!dHGV|l`GQ-L38lB`4w5hjY^=BE*zO~xm_7)s zuJ+fssigHM7qA(UIKinn`Avxi#5({@@-nVP^zonUKa&L6vrT7_eY?ez(`h6Zo_6T9 z$xUgcW{gl49P61w%B%6Ne_7iY^h%jTI3L_(7L!ft>W1XIl8Vrxi>SRSqt@tCD1MsZ zA$GqplNH&_ndm7Do_k6Nt=HX|Cg(Tr#@4<&#QAlUN*chO#_5m50b)NY34_$M;H_e& zU2P%jo5xEbbKdQ=UX2J^dSld`4hWci@}QJGI9zUoA$BnwuaHUV%1oP_abEX031`KJZ{JNqRi)HIAn^$DWMlm z$xLs;c*G68agpx;^E(j)`yFnpcbhnN(5Zcl`&>h#aIi7rRV%;eTk>dMKso;A?`u1L ziLR-M5i_&J&e$7?=C>+ViA+@F&ux8D5)N^|`IW1GkYnSwcSaggDW5lQtD6gOJnKBD zdezkS+g6a;@bKnDV#snJg3dLgF$lY-7t!f=6`Y~jNM>lqRZMntW3HrtV0(%zA2SYkey| z_5&eT78C!+gM0*BlVH}xY4GPnbimg28LRv?JrB3l`0egmn_5aw$m zlu3Sf1*iiOXa_DDeKQk>8{p?8qc^!nv0d%Hty7JUYtkn)qrPc7{Mvb8BAnL#qHs+{ z{RbE_1Y{92fOvX!p8@zrH-TV?AY`p72ylKCzIJCppcQX zEcqTxlGfcpP#9Oa9>qg_jzrI$drp=kZB4zXl>%51s)u3F+`;caR5bhr7=$%~Q7M3v zO;z;-sJU9Id2!`-#iJ{Q6>0^JkMo+@bQj*ZuJQ7Jx;J93tbB9%<$WUXM(XbkURVl_ zqv%CiDdEY2#A0jm(5f3D$MFG-gs$4gVa$d4#H)AMQZ;gqkxmfuu`Ljzad(8XT0z za}EHm8p7H*7y-zxYL@kS76yU2T5y~8hafQG1P)3;IIru zI`;CK#ie54L@W6Pt12+kQBtZX+x(q|hBD0;hMeHYY7Y^&85k>T# z{ZVGoDZBp%MLNulE^YMlGCEu}5Vd8@&rR{=R;H6pgq#}5%iu<1Rb{|ymZKU@xHBnC z1WO|h3zBfY--^Aoqj~X>6rN9MFlKO`mC7bsa-$#B#aF4)QPo9^g5#V zV)V*luv+-`jvzu^%$gGaCpO;%y1{!c?bqd&DZKlJx%*X&+Bcy9148=@vI>4mxbwMR z;Pk$qD#uY7xi7nTL1Eb(PrTkaROllJT67ml(|f{otU;PBGUed)4JUtc`Cwr(Br)*i zvyW(P5(f+!|Joeb_`oEOPnNF{Z?Isf{3EF3h!~B!mUb~jyE(|z?Eqy79FuU8FSC82 zO9&^v9*$B<0in9Y&8bb7k*j!IYQS}(u1T@K=iun zJOphrOB7iZ;!Z7kKa@|48NO<(i2J$6leNxb>wHfs8@X-CI4R7XZC@?TSbYE%(kN3C z){HITH0_s(anwh_9FTSazOmZOBf7OS}2oa}Ov^a3nm33QVj8(h-#SR&K zH|4q?6u&O&^X_{zd8)NCYIFYF`$34=X%TZP@DVYvH|(vdx+n%i5cV|?DI(i#)F3~= zwU7n66_v?0Q9VYzX`7kxY$Lxa0R-M|SemCZ0l^L@U!;Oi1Lv(J=)l*|3XQUjF`fyQ zO=SRws3>*+DivNAQc>d*zx6PZR{UTI9PNque^&H}ll-k0a8jb%0(S^~#t zHUB<4aV?Nk6+$O&=QqDdE00_NGwVXW%cKhLg>zB{AZa$acTAbEFNsOyd}k~#CTriQ z*_?rEqxCh*%Ht}~0p^PAP!xWcmc&#U@VkP`H`KZRJj<9iBDYtfLZ+Ld5so=K`Wnz@ z__dR%4Og)yK$2IyvzIKu@;h+yR`ng#=QsCv2aa4uvFN?Qzqf zskDd(qk7(C%WW~n#|x{V%9BB5kePL& z^KkAMNcJ7W=W?IwXE(!lr}1y}Nm3y>4T~#(yUV2w4?Y>88YK9P*20>}>tMM5F<^AL zUDM2b7qL8DGHzBMkL+*4Ra6I6j{PX+;F~}V-Y{gd#VV)DNnTF`0XCj=H5=1B* z(sh&Q8Pm(&nBTllUVXJkJ77&2FtGTm^oQ8NQR9H_WL;3(;$w9>xR6P#Lrz5P8eUcQ zNV)s{g}Q}~st$O2p~U-HUfYBo<@JeUY1rTb%!qzPLLflQi?4LzZfE1?PNtULAj%03 z@lu({RWl~E!!hHq%%p2H2NVWRya!Wpho@Tz@3UO3gS%pu0+k>|L<;59hA*gK9|p=1 zq41MGF3b0gY;pVq;a(?sEckO)NB!59fl$26QCob1&N zpO#*!ID#JUp%|Q2t?6iG2D&R2GguZulwT9vJtWC@-)H}bm|TTK3_*8A%q;ixQLJ$|JgI_&2+suKI-1Nb63g&O2{`4DlYd<~zNwh%faV>Gg0M~ompQ3{!0 zz|>5X^#u_P`dk{RiNeyUd&%4l#jPV_F3`r669 zL(>U4FD@0VaRTX;oWso}qh%?4^$C%P${-D*XRub8osvmckMQ`%4{0b3NAU@ZzupCL2s%QIRW9&NNkb zg#5|J$3Idvo~w!lO99&<90XPjtCnFY`fJD4pdXf!9`&8MAC3wu-Pkc359bmtsd5-D zDJ7L3QZ_RYTYgYqikss>y#NgYrJlfoAjJY*@6OHe#jkV4!~{%_ys%x@109WGSqYfo zi)BD$^P8&!7SO-e3D;kNZsR$EsY{2-OZ>BpdcWkbSQ{Jch^|NkRqLLF8kFZ?mN?k! z(4Fx-dfca*{|*1OH>9`%nVVj`FFhLwr;UDJer)z_UwwY|G~Rpb^XKDk+rVnMHW_}Y z@0gNXqM~gwTzf0>pEk0Ebk-fLaM|``C(807IIJ-{W&sUS!|r(uo>OFvi*qLo>YID* zr(+2x9haOM*Otq}L(Dx7%f%bz;YZR8=7BAeXo$z}%hD!(ZG{Z}M93qU&ge%C)y7@C zO6EJr6`^6*!nu1WT@yQBzTpoIef^n$^?mv3whO_YAW@qqO3x{rnNz>ZvU)m;HxXFc zcoCDOUosow2>vz3_>T9FHBKeKZC7fcS2&vW$^<)9+L|Y-nh1Necb70mx6q^4Ahq$! z{#z#u?ccrl1S(+GaNn=VeguLJ!@)k&*x4w&Fl7o@8$Y%7?{uhzlo_ z{zCkwG+^Jl>z(3R(JbX^G%xgY~tQSLPxU z_SuPKC?WWKsZLwkz)O7FKr~FN@lHN9$vw^f`1Y6lHmtBr;!D(wpvH>5$`ARy!Kp7e z6Tn()whuWyl(?0A@1diV{qU5?Eh>AqzD`IIm^%?6bccIOvO%G`rD z;`lV8-?MN>miO#+dOc-`JvT7BRg;Bk_v0CN*g}Qu+1^$UkqHw~B<$&%3MHsIzp$}4j)E8txq+kH4JuA&n@%oEP6CxptKEqV9B_#M3NfNmC; z^0it&OJFdscizE*iFl+%bLFG8-Z4^O8Qx?d8PD#^V%eMB8t`TC2T{vb7A2PYbwj@) zNZ0VxQ=qtpOsgKd(&ym>1;7Ff;}55dD|Qyq9)o4DD^}^K4Ep8#+_Af3GKMaulrUY0wp?AK@@EmGASo&?25AevCoU zg*9b~m?cxxv7({~CK4)4V}(8% zlL969L&E(x^&4Fq@oV3HPI|IA^sR6dG~UT>PM?rWAT9H0o+LE<2rr{Q6PiSGHcBn#d(bR4PK~-D+d7^;t~e`%tqHx8f~s7LV{P zoy9)^5pVYYyMQ^`wqdBs+0Qk8NjoubTD7;t72+SNPi1*!mkq7T2DSDGY{YNe20i~} z&Ek`iEX7tOn>d(It zu#9uwkUE?x_9rMjJ3{8557+QPjeEwT7M)ib8(nwcXx5X3cfCkGwOg1dQJ0lCf5G-sQvtLc9QS+<|9-tf{^QkqZ=mW1I@7#aX)@nf>6@02h+^% z$XQWvJzu*08_hazPO#_HOpxj?&Cs(Wb0l$aDq|E z59kpkCJ013)DaEy@ATXu80k73nWJ;mkLaxaqS@JQ@z5OCvnLuTq^reh(lEjz^hb5t zZaQ?|xy+BBthy{6Q5Dw=m5iB1gP5bZ^N_U0zumWbeS5MVD)nRCZ1nDjj_ z%?I+_Q z=It@7$f}T`QVdO%gTXYC>9H z!kC#g`G+?8r!1YfQVc!B@u56SBIk?iJdM0dlB}6@z69Y9PkE6gcUkGchf|AuLSF;k zl6sc(cEDw?7lXd5>{Qv*J=hu+i`2FQ%sXk`-tNe%qEjac6ql-mox9Spy4tHy9>AIDId=tyr-G=MnytPWkk(dG{U9TZ$%pL zETVNxcsbvP?D%EGo`X8M#R(e2EzheRz4AxFs@qGKl%u{X%No<4Ane}6X>4QBKBI?} zMb$2(5Rxs|lhYg<=S%-f#FJU^BE|T&wsvNPk+?0UT*+7pGi<|1x%xn2%Vu-v*-5neMuyAj_Z4(rERA&4R z=OWs!3g5yf^jje~{6+V?WXB4ajH-pQMfs!pp*~P~SrQ_vd7?p#rC4!HMz_2Q;E!n= zA{JND(c(ms=o!^NOI!yt6v2W)c(4PByrPf-=DvYAhmlTg8~gN&-@32r{FA)U-i~ovyCtAkSz+Qo;>U-a^#If>3ox}<4RT(!L!042`c98&wLIiJ42@(bU2H`R;F;a=YX zY0(d=X7qGwi(%2Wdb>F_o$L5X#B*#qi5!Qrzu-{NpSypI2m0FYN)T-~f+lq!d@qEfUQ&w~k6uHcBmnOD(OgJR^r-#)C zryFJTlk<+pdtp3-mBUCa*Sf9HZuy_laaZ*7BUA-EEv@rZ2nqw+FwAh>BQLgL1A4`7 zk6T|6+`P-*T7(v!?g^o^tCn5EGOyh558;hLQXe?Y?V@?Aua<4^q9L2Fv^W1+kM(nKX`VLhsIWl|c8G_+7`_WZ`G9=-G@e@4@}*@i&_b#fStPDY>+>BsJLE z68r~o@Pppx)KeQnvU(HGG`erM5dMnK1kPzwbXc6G(J#q#vJLxv1f#U$`d#=MZz$7z zReHtTdF&Wu=j=;jyl%8M&mPyW?NF7B{6M>(t1!9YxO98W!HKiq7jv44uu|84DT2nk zqi9KyAQrlEuWCv;ZIs((gul)^?vfrpj^X^Tg*!z|=`GbI9|^co`q5AZG*P0+Xh0a^^wC0;fNg>A(g)FOzQoJ*|bBR@i*7uMKeqsSH^q} z!9J$nF+0`i95k|;92kq9Zj6HJM{&%HM$_dXh(4p>OSAVweeW9{jI}-_R?G3IS#9(a zn$P{Lk&q2xP}&!Qb9bc7H(WIaJtF$vNLWZAQWv&i%4EUAs`Z^2KS&O7S3%AsgVG{& z2AaBaPV_B9?OQZM1*Y~LESEb_*Q5TB3@ub3jlruFy;d(=0 zol@6RA(hV7V0v4~XK!_B>iR4v@vs$}W@?A)DV;BIz2Q ztMh(aH;ONUSkg;E$iIdHR4)=!^2wB2C%KShY%2*CGFhwY?FFQS`u*7oZr4g5Ji zY+8h6v6THXX$kt!=#n=UoJ~n=a;fn)4SBn9relt1Uz0qyg6`QfSKGM;vQDtOev{IH zD3o^*N#Nw{<@cFvSZ`SbyTG+By27?i@ym@ri{XT{OG>%-jxNrI^$*L-QUS?-p#3K^ zC8BT_UA)%oBvakI?S%S2M{2U*D^7o=PWNcwurn;NlXu*OoxGe63N}UILhfuB$+U90 zhYn5ZA(hL;D~?fd!Vmoq4xyDDTr*8RPxd0A`pf$!nUI$H_ihuNEomXl>>igIJ+45s zH@O@7aDdfpTU#tsb#nC^`4<8ME)Ks6u<9Y`*oIk)Toj;l%d zHzBBfcyN0Q2}x@7*_1WhwZ&v7LimwbZ}Ubd3!=>jf|6)A?82Jar9ut z#6oLB8#Z_Dfq#Ab%D;x~KyurrsW@Kvd=4!gSMT1maK&VM`62FfV0Y&5@H26HvlNK= zJ@+e^OVAA(#k)JDf%v5A!9gfH)#1I0iy%Fxrm3{4uQq1M3T2OCS5!PTEkFNVDpg>l z0t?<@$|*tkTyA`h1ANr2am*KhXk{UgeYnJgGQWC~05XJLL3u*CsT8LZuB0)K-*Z|XK+tpoEo3QYYll|jGC;zk5i4bndYo+rXudjel=^lQ}&$< z+J^WmG-G(f$DG=Q`Sp6a$*)oJ|Lyx9NQxaf@6^D!8clk&3fe~qVQqnxyK-Py2}s4} z!!$vit_IxOxkCAvzv^C4?lu;rGu`kFvwO)K5n2d_lQ2fH1(NBI#{|p!yj~(VLo2+t z7SfSz+a=~Y9SZ7P+Au5>-l6(IwL_+Gp7hxdB=-@rp+_G|BZ~u>YKd-l3G^86``_Q~ zhpx|+0%&_0CjBqXjbc;sqdu*nFy;Z@oI~ z3iwvZCTd4oLRDMzG3=N-D8<%8H#&?v3Uc-GobQDV z_d*(0re#Pjb&G5Faa@*lsipou>et7vdw0VHAnUf-o5NU^`sQ7zXp zB=t79IHRYOzZ8n0ilpTRWne&cSdb;1Y|$cgID~U*5PBz#1d{13Sds)$bNLu?kF9S5 zQQ=yFmx^f&I${>D%JSsEsG?v#nDYPN=KTZFX3=txPL`GzXH7OdUiFIorFS*qw9LHf z+`rat(=H41kHTLMOt^cxjQrEbvT?P-cKv&Yvm14f`WESp9VjvuBcvm(As803i~gL6 z6*6sv64TamY0}hmF8Wva<<+~9!_J4{x+Z--6bwB{9oP5dK=Ms2gAtY{ox78B4CF*( zHV$fse*E*ePekvsA2pt06;;Fih&a6H9 z#B3%0-D$StEqGus=_KdTkCx!=7DC!o7@_DxDWAwd z9X(?$9kC>7rG_}f*(=#d@XYuf@}lR5%VVl>S#_N+_Z;^$O=G_jd1T5}Vb>p4#_PH*N4|^k**2{`97YRrfx= z8yFvM1HJERxzdb3BtxxKP2=vE{lZgWctP&{L*k)=BT-4MEw{?EEy&-4KeQ7(lWP9o z@E&WuEm+eRvVYfPb8=Y(0Q19A{Qa7>%0+#?{#5ppCFuSKgs`XA>(34_IEu*W9;qZN%cvgPV6*cATTldoXd}8BB$1fZdqWd4Zxyt3dxZ0E|5;9}5I`(iG zMmyXe$~AUZBA(r%DuTgs7*uiP^su|lSevgus|oC`4K?b8( zE=RsR*wZtN1C1HLFC?UaU*y*(2}x-JIz-Q`!8x9?|B;qtio-^#icz^MRub-s@xqanzxGsP2Xc4x5+;}x5>E=+NtpD30e$oJ% zkL8=(UcV~!74jSE3GVObBGsNxz6#9puTr;?uqa_xZhDmgfmt=6Y}oRh!zUI0K_p4H z2^7<}z);ip_;@-JS5S10D1;Y@8IjcAEX?K#NG^-~NO1Geit3!q zJwaUh;9=uRDeS*)N_g;IvLoPnMV0?(7MV@6J+*Y#0y>zIqBznwUNPwVOEglu9_4r~ ze`c*3Hp}j_RQ2UD`=n0`oo2L>yUB>s;RgMTV2P&tKQLGXqydAq*xG_3EHEY|;KFSS zBH;uSJb?ZI8HBfgkyK^apTJU5AA9&>Ki8WJD2+b8hO23rQYj3n{3^qtH6Zw6G5crW z5t#n-IhL#b2HaB$t`(q?$;9VqJNcFYQlGPq35iNwWvEy({pXsWezHDj`~3FpTMH7z zz`$bwWkd`{jfnWMb$oEFh5(VfM($VESn%s3W{Y!_bRoU7H>^bk6XKdhgyJw)4om0H z=FmaU8=pk>^O)%*MnBeHl8W4Ps$QQ$nwjn|A)_w|OW?B)?pj}E1%g&^kijfKD{(lo zQ&R)D-t*3M^XSv&DLPtfS+=1SG9#1*(`zJZef!k)COh)E`zn z%AK=4(TWTVpG1HatjVEx5S~;4Grwbiy1!&Q-9Kp5^A*^ZZyem_a7$~^OJ5={AK+zw z(|PpX)9k(Hv3GAKD8<~w?a2fuTt=ww=e?;;HpY6^!_vt$P;?&2vyE{Axc7m3zJ`*A z*|aOloGL(l=RBq!%HZd#a2~wj9>i(xWag@!S^{4ncaw96;-{@zNZyP9_wd*)36lj`o-&(Za*sm=p}t!l}Ckl-}v z3rSiK851v_OARpRzd zU2;K@g__+U=jh}(N^={yGp&i@g!b%V(b6O z|Lh&~T1h?cPpI3V+wF)UuUrE2T70FiPM|;g6i@TanrchD;Z3wYgULL>CyTpW#3)0x zsTA+JCx^@VzgzM{oj|i$xIq={)SbAySu-s&+M9TjZ~Vwp68P2@vA+_ZkQcOHFf=T3 zapuAiDQEz|YNoy;fg$cVG@KTz3v?ibu|fS#_d7p6;P8!JQc{u!hqD6#+Ft~6-kx8s z!pqhcfEG%ZrR+z}AL%()^j?ODQUJe0AaiqzKHoS$YHnYTxs65+7aD$bnYa=3i>Yy; z9Vy79;T~qq6;iZ*Gh*LVt11-Ywgrj{a5SbBCc&t9kF5qPXT!E&7;uRd45@z zJx;lMWoq8ll_;T<7VrtNM?9WFb%M^cG2k@G5;jw8vwT7(o$KJa_>b@Ym9OK%%` zL{TCrY-r%(lESGPEBD@b#S2Yk2G)7Gk| z?CSeo_9BTQo;{5`$Mreheobu~1nuD)@PvKVVtT@>rD&m(x1;WC437d4mcO2(Zlgq@ z!*XN4Jkn0q=ee32dBR*lWtd7?lr=X)XG4a$0C$Qit^IX)!^rh~brC#*YIwq#ql!DG)Xy(0m)=Q8!!o_hO2NHm6Mox|+V(cl zF;sqK&rfPOw|pIO)ROZgVWR?pJkDV%0@SjBH&cFOa_5Gxh84mmyY4Xh9mI7~J3Or% z54Mhv!AH8_720;8{D@`O_R@JTy;0*4L5+r){@UCvbo~f^W4b%C8&3lDTlmwAiu&vU zjAWL)|D-e|q)k*2q`9xJt+8g-3z;{tIJnSCzMh_*zQiE3#IEQGyFg)qARHdITu;0^ zH5s@^m^3Fgef##M%4LM;G0ArZF^5Ftq*3g?d^z;Anozy>bl>4u1rh=tCmo^ew>(!z zbnG79RdY@%htn@Sse0xu$#0Im7Wk6I07tLK&oM- z7gceOY9hH^X?c>xSqFKthCRS?70f!hWVyl2+^F|&3Wu*EiE2AZyzkn>d0#qNnxh{1 zn~KF)-rT&2i9v}L`Hk&SM;AEc%o#r%$0Oi?{isNQ2`hH7rrU@P?i5-YR2D3V}da8!M-=;!=+rDYJ={YqTE~I}tx^{8e#2DU|C7 zYpbz-pyfKEX8%Zp>1ywv1M84WATw7JG`L*6Lgjbg~Bc248lnf zyh?t1t8c5j(&V|V$wLf}vF3(-Mf3F5xk+Tg!!rTGyx&`F{kLxIRlXnN9>|l~Y&u|~ z?pfd=nVh}%?gvx~laA;H6uy}>gh$^$3ZC(UYy!=Vzbf3<{|+A5iWr5InmKk4jYZdf zV7`T5ajP1v7RMTC?3}py(rE;|995he8dfDKbh~H8Z?a#U& zYt@zTdxP%kRS{4=n<8mvWNh43U*rD!J->btN+q08Q1AxVg-%dRDX29$HYNv7|4?GSJ6YUgd0_2V zWuwbnYo=QC?A(&Y!lUdP1Y!{=It3l(B$O!62*g?cxt$q`ew_(|b}*QJnKh;-Rr+%( zy^u)~zrGMNbE;9fErQP9-@nWcF-7Q16c*mQ^(ZTJ^)~&vM*MboX=&+*RbSTqqwCC{ z;6;X|IR-zUItJ(FVnI{CTaWW@GZ9x;R*VacBtdheyFuiI=8a~88M1CUCSSm^N_M_< z&>g@iC?d|XZK7WU0fo1iNUYLI=TD;HZ;pDyEzH~3qiA>xBh%7XYQ8dXEVx+0>=Gpy zKKdFuA>(mq+szK;^+cj;3>-@KIDJ)i-nYkEGhw`P3Nw#jF6x8TuY82}@4~|SAR3)t zzBV)+4ldJN+;F~ikBTcM^O}wq>eniAA%eA$mCxtgR`!9S>lw%g=X1HIfQp2JP-0C? z6Ev;>x|crm z$^$c+l@j>)C(`oPwR=N^YD%wj=5tE(2F;GmvUC7$zZjK&W$MCKF`I)-k|fik?Snob zLfs=cWqjR?%MsCHk5Aml11X<+X56<-ffxNi-|%lwayw1P|>NxeSLfoQ(nzO?!WuMom5X}V7IB($1V1FcqU6Zq>K*~ z7>cKBeuC4FjEo4FH<%DZ$Cw-ltw5a_giP{uDgH+eH^0D@yd3-Q?H0%WaeOZWhkz3q zoeh>ff{ngDPC^!7KSkVOv0$m?h%$(cT5yx5?77zTktSZ#vqc9ddx)OfUA%mR6+zLg zrkVN(==~^5<&}IQqdg~rkwandSDOyg__rfYO3QlS&dxh$&7KLUd9L0Z(;Ns*tvS7U zSBW=8i2{t0wsCbeppri?Ry#wX8W?-4%SVi?wvpqsw6yMq(WbSYbbODX0vTKy2~R%j z<+ptQ{{1V5h=|Cf(-{#B)Fyhi)P3eh&>7P6S@&Xow6tU!S2`X^PEJk=8kM!D%kP8w zd9Gja3udHbloA!gz}kVU9xvr!lsxwF^61Z+g@JrsP-(7{in*>-#2{=26!41?(06-TJ zjuBr5#7(Xpd!91t*;p`NJ9G&Fl|-;;PV)0$=uu|Axa80V9wxPc+sTKT8|O2uCQMUF zKM&RiKCkyrVHfaDqA8Sj+rH19O{``hQ!*bcD2<`XHC5U;Wn@U6igmO>KwCp8V3w1D zff+Zea=ufWnV6{GpQG8518&c$ohE>n@(!=Tmk*Je&A5-c+3NAa=1QWv^}ZfDb)cCa)6b{wyE!&21rfG&E#?rC3c*xcFze-SyN z;XmIR#rnB1@xdCeaYaF9re*%4>sHPU zyux>T|Lk)Hnq3i55qK-A9yu|;n`3H1r>`uIsC(RmL(m{~q89X8bm7x4GJ&Y#MUs^Q zeA6SMR)&icd3Elt@=AHEj%%mV?AeSu|N}}>gDl45vzh);f%6k?hCJrZw zTF&1A)+YJ3^j}GgItMUqZS5`Nhy(ADv9Thv`Z4G)J|+EG{p+*PDA2Ez=`#>fSl<0q zskJaV{sEstc!GpYA9P}QZjMuFa;)%(AS)u`3=WHw)^@lkUCgSp#$#n!&Fv;l^JS`y zjkgzRfP7tl_i?2c&PHA}o){n3D>Pcz*eG6$3I0bD+tKW2V_w0vatMrIt0W}6r`L&8 zqQ+~((ZL~I(QglUh~M3yrG%bdZ;B*8tT!!RH`ft-7*q4dBiQ|;o!>3m8Q|Ck*?t%h zaNz85qQK8Z5&cNIsc<`JPft&=OyK01#4?rBx(O%8{EzcEv{W5$C=*7}=we{jtLf6x z(}9LbKKpUjAxiD*-SKzewtB3MJ@IEA{qpQh6%JT5J!w`*p#R?LD7b*MUS_p?X9eAv70`xb=J{{B+1WFaA;*_s3)(^E-VN|%X$?VFl{Hw9llcZnXf z1uW9Z45pa(P2ndSD95J1lwmQT{Bl0n=Lowz_<3WbB-5nYH7Y6!7>)5d zpVEUj538J?feFyIgP%GypSMHE$jG`BuHFZ%O5?$7`08ls{t~9C8K-S=_S`uiZ*Sn? zpYJSTK&KJ9soUUiZ%MPtxm$xxu*!RyH25DL;;^87uHbq`4JTe4;L5+Q9KcHdA~61a z5**2v7=j`GU>L}oiV2+S;_U1r@V~a^+BB~C1HcMgUid5!I8w&tZf(@aO$WCklWKtP z36JKGR;#T;g~q$lj@=N_rx}E5Z~V3yVr zj7kUfNo`TA;@*E;GcUdrm=@qz($muVvNfbVmLG31N-aqVo7M3ug@NzAv$b_`CYQd# z8gqBm%Frus3Q*S*LCG! z|E(5=WHGDdzU)hQH-Vq$UAkXTv^wT}gIGR&dUNw7T#A1hIfFbCdY=D=AIcx!4L!Zj zd=?mjtZ{{XSAw8?c8Js&QUc@6YdQzm4<9(TI#vfi>xa?uHS+){t8^qe>-H;0Gxdf_ zSe%flFF+H^W+;R8!CEh;bW;FaALTu~4lota7IqouZ>N|eYZvXB4sdgaM>FyWxP@po z#Ur2@o9L3;%*~jXm=b0SGv?Zle-R^Iy^8rpN*FD82@eKuOeQhvCp=>+1HvWf)12;5 zcHq-ju#go}A_a8>kmB?Ihw~2YmjbsryH`71?#cRKosV0(DOf4Dw4~k816b@3WTpEm znajOj1sh0GQc?y1gD>vCAElq0L6+y;VR2)8Q^I`fA6t3~whyq+myzN$C$|R@+n+Eh zhAvafwobtW@3dTStL}hOvfst#L1Nu%E!uvSyXYgg_yA+2oQC)y? zfNu-6^zrlieCY>dWe$tQ_FRjYc=+mXLwJU0ulL7`n56j`qG=APeW=b|HRUnVew?6~ zyYMI;kVj8?JkmK*dVNP#i>pLZCpl2{P{B|!=wu3V*yry2#|SrQETTc5Jh0#X{hSiU z4X{d$ypluEUZ_Xti>sy_H62#^p;9!G`nG*rze?T?C$5BcdO+zU#!LqM9r6~9Ic+Dd zX%&o@XTCd_c!bYmT`=1`?V<5rZWDc$NHH4<9tj7V_7gSb0J8z3WYrlLbDf!5T3R|e zYpY)y^82PuXgxGLkHHTS&_aHlWe8K@@Jqn(D?o4&jN*&HP{_6Q?V~Nyf%S<4;sh@W z@SNJ;+`J&Vj$~zFQBM#6W`f(}&H*goHSPc75&?YDtFl9*p}*y(XHyZrGSaMttuX7# zroga69YQ}*AG=`9r6Adw{!JBdq z%F^W%8W+A&D;Pra4}+~0F!u??CNN%N|2Nuo9eul2m!7xnlDd+TIX~~9laX9TMK;S) z7x3UE`!Y-G{r>4g7Jv&nh;)uNvH|=KPB_d>gLrQ~-Cv&&hxM8OGYHBAef|6z@d`x$ zgUy+k?jqCL*`>R$f~X4N^asbs+Nn~7z=#9qYCBXgdOPUv*X%GDSBycaoZnAT3aAasXI-!6o?WuJ&RaQa=y+ncO9DtjfZ zkHjpXFDh!Q4{HhzYE<1Ab_&`vqy#@t&p_1>cM%m#`{+4Mc}LszoOR{06w3!+Z{g^? zgWLqd21BnTx6gbSD0@~?_bM-0OgDrmJ1tY|e%~%Tr`k+Yy1)0K*t;c3;f11kZ+nZ2 zQ^|QBas*f#Ic-HjwMfOpy z)&!6r{{vvk3JMELt-7QM0n-o_D;r0`GZ?eBeTqe0Qw7lSH=@ zfTt68ETS=B$~k~_{0O?_w(^mt_F1Rd5imV~BN-|N1i{HdqB-CYP`w9-hbKoX#i)X( z-(QQxD9qdFHVkjF=nhk&-{<`p{fLvASl26WM5oDmS;U@RZQZP$+_uG#3hc$ z$w#TUSfLbH44%<>t$1ODrdptqag27TH2| z0>omPMoM<rv88wX5eY8xUKiJ=D8o!*-`M%fC}xIEHqk_W+(qXbAhdaWzgbkH z9_gkJE1;z{Uj(?%#KMcV(CIQZ&$;(4yHYl)w&XSDyFexyiNIMv2Aw`^!PNpgYl~(t zE^pJ}d?RyYdrjIgEn?zl@!$AbpZ4?GM6JFl3@9MV8~oGlE&xrM31ct0ENkHBJAj|d z64i4$blYq%v0zc~xDQ`BG(J;AlY=P4B@|Hl?|7k*4){n7vpbf#-PHPWep{}Me!^v` zLVm=`j{QkDkHDs=lkK53Szjp(8j?)$2e8Q=9>K_ZotM79@SxdW5_*bD=AGxVZTEDS z(ipyIF9Q*eX^Qz3%}{DPw6{QLXY(LedoVwHNqPy{IRD~>{(6rm=UBT=pNGUK(=DIS zl&=vEIhFa+7)7lPgO2K-mIwZxTZx)7i?d{?Cuvt78I>j~{+do@q3C-Tl6NJ-#Ij9N zI<#U7!Y-5Isa6_-u zZGm`On)<|k&dDC)tPmT1a4xAcKzHlY2J2c5E16cird8wNUYK^M9MO02_H27vkuv{+r}#ffVM?GTa9S=EI6qv+0jVnA5ry z;*U#8TW^}*UC>x>pXiNjvsLy`UoT(pc}2Z@NI5UIj(lQY&E~7Z9-pvm0^ui7o3%7-_xRx@T4hUDA7Sfx>EQ}`bQ2r zRz%({kyhR&bFK9wF%N{Bjp|gVeKeW=B%Ag(v3#JI0y>aTREER;5X(>V4c@``HaD%u ztG0$kpLNFZAp(Xt7{LpK;xA&F1lTCcCYoOKZ$LG_f-E%rwg~GPd3*ASjDPCd0%Uk* zX#A4;g)dC!>cWg|xym*3bX=z2&IjAO7rSt-dnXJ^`Nr$uO8Z`n8^t1GGV&BFx3%Uk zRZ8_ha;Jmmd!cPr{0FceZpIIy5nRr)$~>}fm*_B*X68ma?gby5TvNSl66PI!39>XW zLvI&ebvm}wFF1$2T}j=}#WJ^$QP)oo2425)e;}0kBk4g$aAZ6*Dmkqk6VHqMn%Dr> zLK8zDhR6?UyFxq81m?OXdolr4d71p|4&iWb?H6bWzD`2}+F_=Qz%IY1+C+cj*hJsA z%p+9mO$1*`D5_?aeNIX^%y1#rx%T(22aqAIlT)AIV>|wa;jv)SV+ptG_2sS`E}VY% z`uSQ_y)IOCeX``$rq{O(W6J;iA^*Cj3y;>!Nc&eWvD&3>(ff3s&#UFa<&nmvFujf+ zM#sDus$NA;tKsFQwV}@lqmlqg)l2JiQ(Y77w;ow*TZ!6<)MQEPh@|e-q;%AcSJtJ( zdzdB6eDrshJi`f5gP*hA}*hpMHY1D)x}uNnLYC5~F}R z9`7wQi)ny!TkU^>o*WdhO~Wk?(t}PzV^3{>0-XQW{R#wxz@wQ-c^Ca!Y=M6j;_{tm zC%HzFoXB#pIar+<2rD|wn+wyvw}f*ppMC+l&K8@BjC~wk$=^yL8=E8exo=F%r(}Mf z8*-Si*pMd{vK%aJ;G|Dl=6@{MrKfQcgjb3+5+;2%vnm2-wmn>ROQ^FwS!Axi5DK?c z^!r@28h}OgmNa)elx!E0^xQ#St4%YmWdCH9SpVkk4LyQaYuABUhueRk!`SYw;G@lz zMFD${BR?7n-JDk_?MLoRQJeMVZ|(6R(XcT4nyjmoTw~2 zknT5y|DtVwgu8-ta9AUUKk0VZRrRo=CHSB*rBix@hNWSy0nDcfr%5Io1@CzS*+%b$ z^ZjU8=!$psFp6#^Vvxck{exl=OJkYi2G#Qq%6=o(6SIdJ!+FM6GHP~A<83X(v?uX; zLsXisHvQTB1_%5O^@NB;rpJ}CIzZrlF^UF+Pf!W5VuY>wt2w>W1ionkr{6egge?e=Et ztX6h=Q#GTWs7Wq8%+X}Q+74D8Snn#LhKWCce7P%I0^#gpirh@)u$&D5;T~93-{pz*aXUb+2QLGWy zn<1``CcN2ag%s19Z<900bD?B3hU{4bqj??2XNTQ?+kYM|5N~q;(>EDVi$4lqe&=jM zXlfdjJ%BN9EfsVdmX>dfYnsYh^rJg-1Pp(95tO?hq{vQT*TqlpSS|R@dvVB6o}%-? zQpU;o@Y$TkGC(98Z{-@5G6?S1ADj5e>igeqwo3T?5X0q0?=pj`8h-iljcOE~xNADq z95>GqPjkVk*8*76CmqcrOKp0XGAN=(GzlXO3~@Q%A|v%KBvi{K1=?Wk6{Xu(;=kVd z+6zFX$5OIA2FRju9(l zn%N?yhuVTzcey9MM0sw86CIx&;tLtf`P zKbWFy4(O$i#ho(1-K2klqabi{^%M;~CZ>Jw80B(Hpyj(kKrVMe@VpMC4e*2#=F6#s zwANN`wcc@DVo}1%4x@yE#eN*$@fB8&7M}TDoU?4~Bk@eOvNb2u`8zxhke{{AD^c?w zOFM4arASDPx-E*0h}3y(P+=pIo1>;4dTB%`Owr@Ejp0qi4f>NxI= z4NV@sw8qN9`C{xO=kjf-CFFj36-U(j?;XEasI#S36`aL4UlB%`aOlLk*L%o1-qxOP z$F46%k`O-I3zc8L5;FCPy83l@GwP{g1NY5YWW5US#L}Od#>ZJpudRsZT$&5vgnB<@ zY@*^Dq$l9<-kF{502qWh1OucadGG@PqEb&#%(yY%$jfb z6?}*hgcZ->-Nbg$VorvsP|)ro>v!~FIDf%NK~3{52W56x4_$udRp|w$)%*kmi{b8H z5(Pfo$QLmRzOUGR8&tlC7AOKOLDC1SC3#}QYeUNowpiP9eT2U*D?a)emtyTA=I-W- zYx$J;qGkUUkJGIm6|&45Nyy#W?xps2oC>NA0tEeXfrLnL+vNHQ4zSQ@(hoBSTXO)u zJk2Bcbgl*gf4##l_X&6w*M$z|m@Jp&_YHu^{N32i0aJL*W}7&+gS}IoKkM}*D{->! z_-7(xvs1>7!vgz!w@UOk(byMpw~n3spGS`EVg(K9HaCS!Y`QXJ+%U;3|g zMg`+R2(~?0{)WR`^Eu1m!I^z{tWcX)a&~RL#y(tHGb3NCwGgfc8^BZ>J5}2Zyv>&r z=WNr)@BzuQS6?I;!v1qJrzPMdB zysvylq!}PZ>SG#PKro(Hqb11NRjgLy7B!N^W{Lbm`{;@a&!BL6e!aRZxhk1i_^T)g zan)<1Wu{brMcR>jzvsPVs_%~ZnEU2Wh3h)I=rJbQ0h*WaimJaUx~4ykVo7egO`jID zSigcx$?Tlq`pS)&BphP6HJR3?K7p`^aa3BP$J%K92FHo0$NKC`GO8FRn9~6zi&BmC z)_YmEh2N4-mk6;8*>D1(4f))vWR@!%ZdMuK)K$R>0%7|BgUh;$0^5y5u`oBYhG(h1 z0?D5RdU^bMO{fqoZRjqhK?qzwJLP*UttIw*>~hL~upb5v1^jsVobr^gA`t{42mzX8 z+4h~LMLq6oX{kO@Pm+r`I%3_wCxX;z{EAH}f+&=aVFI!73t7Fj|D zY$!q87uDB}A_p3u%r!$`hzmRIPF7agyXfEc4wv9h1m48P79jHBd$ni~TTJPim_f$w zokDei0mzg|oSe5TBa2_IRax<1ywgOPR+BYkzIlN~+@|&6@D}hV7yS>^)6Hu%`m-;q*(_A&A z!NIH{&=@MAR^tvCERr4$$d>wP+0=VtaZYsLOOzjC2C45bHoAk=tMK#$ct8@o=8?7N z=J_YccNhDy3B-!`0>OVDNu6h?^PNKl!BJL#`i4;Nax?X6T;^K7 z{rIk~rN-m%yxK+o<`lV&_k5CDZ>x&9p=Qunnm^q4OT)iTqgS^t;Y+_$1;HEICVHcO za|T8~IVokSC!^?@e=iGS52V4-N`4diQPqz8fU0fmo*t-bDK@(vUA|%sk}r@_d6a9G zWFAt#qrvrc9SaWV=(F--m(66W`7K-sf+ewnYQ3Z337=d1qSN`GC{#LCao)6i5_vE{n41J9yjK*dDDr! z0f%3M9l=B?GipqV?yC5ag%mdkH2_y!vfZgEuaS77+TCt(082l;uLgN=O6N@8)+v48 zKyo%BU;E&Q_e>)R;m|zn>hAR#oLf#C+#Mnv7*eeZ4a1r_dmzqaLMjxSd<}b$Qb3XFk8#b@Zg|FoOS&z4|Dwzbt8+ z&^uId4^up-98L$|adlvu(i%Axh6PqMdraan~DIBb<4N9NJ$Sfc0zo*sXBt))GX0YV#;C|N)=uTw{g&LhQL`nRc2 zYvZ>Gg6u_Sbu=rE-jhS;5L#4`y1g*o+9f_HgjaIPxd)K;B}}?Yc}sR4X=M696*Xu<}y!*Nj8@!M!48N`Qs=uH?^wt|#R%=J#yvwTWs_ zf3s=B1URKdk129HsPSZo3zs{=PAxj<%hDyJ(&)+RTah?S9PjGjbsV;IX= zNFGq$Fd7-Ym9aT{*moOx?fhzASY;r6@rS;rnN9@Uxt_az&L$ejlcN|z#h&5mUBB-^ zOiJ7DH2x+6;NdA0JPA#0k^+cTIk&3e1pLaYjLQ(1Zv(kTSx7~d^ET_~;7VTM<}Ngi z6Xv^up5IVl1exk5z8>{1>PV5e;ID;YDAVD1@KPkPXZ~D_!$MXK3?dPA+f!e?%#a9A zXNC<_6EU)QT8J;7frZbmA&dr<@U1BrrrpetIYh2_Ss7U*lh|?|+HdS_p^^Q~J!jjQ zTh7h_g%Fj2I(gOt@!$p49;kzL{}pn=Xh@Wdwo}daU5aSg_8X<5rMemOH>M?^rRBN$ zGI`>NSg0Sgz3hU)+aW`(`}s|Awr{Q`_w^wE3!BE!xIagryX@n4dIB}@flZLm<%;hg z`#WP2*2U)~&w0Co_hG;G&jIe1S;!>BSQ(L|v@NW0%WNhuKn@rJd{mPyU!uA7^k8&r zLc4ADeL2XNzOG6EXw+Jpc$XJEBCPb`g%zClP<`bXPx5oEK2UFJ6hvhU(1K;BhWL$m z3r>gK=TOk`qnNa$8-DLt9=b29q5YG~Op&=f%#*5ANNn<^ISUBos)zL1&<0}hX?v!| zFm5&(7F%>5&ZquiLiLKo?kru8b`8K93r>{@=ox553YzoPYK5m8Rf@vpk~Z$eVzb3x zLaX!C+ddjx75;-7!^;B}#OM~Y_Kn^Nf|q^4MgC{@7%WB3gfYy#mrzmW%Vs?~lTF6E zmMv!C-1;8hE@<0l>(M91)uZua^mszE@I%F&U`Ce_7PU?g$a)$>MPM*ZJa#roCE$2sJPKP{K$`zO$Mc z@_f3{Av=dX^iwBPMzCX^yx$?TK-E z>=Hso-)~-#8b7pSw~$SLB_pW01tR5SvV4icrltKe#s%lX(zxek)x@2)s{L@}6(cRF zx~7BT?KtjL0a*>R^2-OoW9`?dXtwSwi%%Y~_Ash57WQ2#o&4*43@%3o#yLf;d5Esn zH7R{?-cwS$TP!5DX!0oBAkr1*!c$}8C|h`4dUP9n-Br0Uoj}eb_L9=H^M>|ed?r`B zn>z)o9*Ww4$GHRWjPh{($HZaLS=X|2M_iB!Ct&4en4U}|Qa^clj1WnC?V4iCgYpj7 zO`j}8guc|E`4!zW%!}Ue8fTTZ8D*;`T{z$1z`#Ugkft4=4ItTOZ7Xzcl&p!lQGnCk>ix8PnMw;j;B&rJ`ckN7#ME)-- zESna_Od}L;^nCsU7v)It=GsT*Og6~mI)#Ez_OiJ1N)ta_RjytKBj*w>?8(;!SCJ^} zexYx+ZUEY1ho$Xlm(59ezi>ket^|$fCq@=&XQZZ&+ese$(#VSN#bE6!GGkF)myV zMJX}j&#rF!Aq9AtIlxi(dL%%sutet&QTvpz(sY7RbS3kY-gCm=E015Q<9tfF)I5GU;h1bw~G6O>61*etq|C?*T3qDqsJ*jA7sJ~Nuf1c%sgDp-w(0f5;H|3 zw4By$uc%#e5!lU?(tAZ0lJp?*$)nklpr250Y@<8WQ=F#$`s-!$AFo_LS$>p>v{*N! z>!FUP@{L)|D;&HKa~0gG;X;w2*;v%{vp5M$J;p^ZDAWGsK%^OuS=f4y zuxks4=ymJ_BdgV@GbM)!(mv@jN7!?dHG97_r{2ed!tkt7xkUuRsnn_ESvnJ-(QAnNF#?Wx3)pW09lx6I0JVf=9 z{BwVU1ci$`Ph0t&u6$N1iI@9CU$}47VM2kXh4mgrp03+<{aC9AsLyg-hK0FMY=xA`60S}tz)q*NMw=Y+z_>tjg6#&A2pI0t^3Un zr7>ZPqU7t%FYn?j?c?VT)!{o0!?p%Uo*3>Lg;pD64WS;21sQj~Td+ZbnUd0}vWcJ&$6I?|Lqq~^vk6}uF(qovCg-}(GS-<5HaPw{0 z6e%0;XIgdfe{m`hAXzoZP7Nn_sp|Wf9O1=>!@xh8_Ql5_M&oX=%9?AM-Jfl!ZYWe7 z>E^wVuXQKt#`}P@irtDN5raO>;6(4$vWH0;4ss&*J?73Qq&LQ!uSb>iH*;aZzFJ{NH-GZ>4f_!u6oV>Z~;W z%3yVosGRvd@|7k&cLS=0-iF08t#SYVo*Zw?G6x%f5acGilzW_qfJ_jC6L$=Wq(-}o z|DLDzZIobm%)#@#GUmB-W9=Zx%RAbIQpdM32o;al^EXI6gy|PE@|dT$*?Q}!*eyEV zLz_itjQkf#k_5!)!N;Vy3;*Jv?VDrqLpZ<_CqDiQ2|zl#V+gWQb)kk4iz@h9>xrcn ziEH01Uq#f!d|{e9H0d<27jgcsI)gXpw$4Eab=qd@-5i*GQNrnSA=a15^Dg=-9kcbY ze?Y30Z=H0+K|Ma38+rF(=P)R# zfbm*NN=i6pUQJhbFdL|YsysHg7k`pcvH~5eo&GJrx@dU&7TO1do;zwQ!bA+68c;QX zs>%$HUDhjAVD_0loE-}zor=7Z6?E-3W-NW~;5lvir<0!d{}rO~`#my!TS2wN92;^w;|&e=)Th=$z=dfPe7z)@n{dylOpG00R4O)S(V6Pg!wdO@&A-?WA<0F3F ztaCs4&l2pu5>IyB1LDCh`yIk-Kv+@TCXLLtJkMd%kz1fd;tlwJGQs-PzW1X=x3u{< z=#gw8UNjfbwrtA1FEd}IH-%@4YP!$OZ*zUth?d=wloSc@h%|*#BrqBv^&#pOz&C+nPrll8R(vAKrg5>DSZBR?$HO8xR4p=83xB&@uEWzN97X*Km_K7oSJ zjM4Oq>LpC1XiVVUj+J5b5+Y&~eYj8uZgOk+;PJ-K8V$^)krjy6k zZQV7*lA6db9PkUY64um8Yl=16eu%`hbyCIHhSWSo^D8Mll6DSb;0>wRs_yIO52@;s zlv@r?aEY|NZe^qTJw&b2?Gi`Z{b`yH|voT&GrF+(s4+P2Vp>Y=Ai;Nq9JD}ErKh`7z{7Vk|F4hO;N zAJyWZ>wpM6>-`vf`Y5GJD?r>vAVPPeaRk150Oem09~P`#g=w${42ahazb`SUM*y8hIo$Z7o{pu(PQqVS zjdXjCa)53j#>94IxGDU=pk|jEDl(+6a{Xc$ujKvP>g5vkLsvAe9E^LYIUqgf9*2gRn20**D<2nBZt($2Grp7TKTCZa8D(|c9# zCm1a8XH!10X+)nX4%WAqobquv(kP2mAK=(^WA$WioBY`qq>IW+B!m3;Uh75 zIVnkpa=|@)uf?>l*Szu_8`i+uR7ig|7>;w4XG-ny!_-y^*5cOJR<|u16s79iOZO&B zw{{NUOU_orlNRDR-+36}Dk8*aFM3pY*v3a#8~2*270%AXmp)mVl9j6FaHAwlG#~KE z&2>NqO4mG-MpoY z10ux{fGbgaKOz@wIhy|jfx1cX6d>Xu^0?EKcYs#P)6>(MQ{*o|{NCBzTkqNVE+F^>$Yn2Y&*NACRX&t?TFSml zX#+K1mm$7`3UTo2bOD-J<8OlG&)9NgG~4!ZC6{Max>Q*eZYR(_XQgN^c(ZELpCm4n zFt!E#nxDOc!{kFrhp6`^&k5FrO_b}&hK|*;E6d$}vmo0;Lf8A=6lZa>lsnY_(&z|3 zMM*LmvvtAlyAWe&Fyr;*w_IK=9Hk$M)HN-Vt#fLA7F~z8gzFgmL?mzAp3_Zd*Y*Gm z$79lBlchUFR%~!-+4I?)h$Ej+R%@IKRrtlB)_AU>dFs74V(e|yp`}DJdI1T47vyk% zKgYOQ(xk=*&=mpKv(g7!e(# zP=otZVgm&#A%#$a-TKnuPR>Xp%3u0rz2nvFC~dSsoSk zyC+!yEh)X&6=yS}s+2=l;U>2)s-vToQ5JT3$m-X)VqLJ`5``DnAd)Bl|Tn(ad2*JcC57Mo=K}hPMvR^b27kyB;@5P)m1nkNDJnJ zD@}HJSxB9kc9HwrtSMIKbK&ZZHolTQr|8;gV-gVJku%b@W4D%5&yDQUGXhv?;S9i{ z=aoC%NAbylM?_Z8yGuYE&R_ON{weD?UImm5y$%&#JD*3Rc{Nz$zfw_C7g_Znfj@Fb zipk0cFqW+9q;hbc4gXBrAntP}7gR9clw!f^BNnyrV$2!Ey>Oq5u2J z@7Scsv*RBN5iMHHiBXiv^DKvXu(uCd*eOUgUXPqnSkp+UqmvX9lUP1P*Fg8g$4t3Z z285uY?pk`#e{-*Kq;LuQO8;A`|Lch?32?)=!{j zYP8I01_8%YH7@ah*#UVf;Qse)k>MqV4q&w24xvV!MrBbFtV7RV zSt0LQUG}Oacb*LPDg$);rNQ5)LZm%AjhNRB->es_&N4Kytmh@vFGAo2WD{~u1XvNP zV7cb3lUeMh9=~kh& zg`boJpDoWVhryT48>rZO9v=IF=Yajva;e*@KFAJ|b0gRwvcTg2Og{Ly>or;UbvQvw z>^p!6-{1T-OGExg#mht8I)eAqDG92Cr1y_)bhN__L^Qq&2TG2L`rIWW*PijW7|H$g zl}zM1MN-q~JDQt$PQ_~;jnoQZM7e(<3ad9I57y80=sewb`SIf~cg@RxmH? zi8IYUdw9>q?4u6YcyPoTO1Y}=eTz^ijYNfWeK~Xjk^z%54yx?d*rHuUKacze_XB!% zqGn&*$uy9h_Lg}|H(;ZKL!=d3A4Cas7E-`U04PwLTwQl|cm1-^h`#&h=OOI{;RwHj z*6-gx-Vdcq6t#bk0on{$rQ7N)%MRVFhuk6tGxME^Y0CF;IZ>Pn;Xo+(Ido;bx{?=2 z_T(jmfvmtYhgHVQDnbOvz%)fo8_rTvM#L$v$af})tgfsih&k3gtv{nz4pbR{k6Kw) z7L4%jV-J^dUsDAls1;ct_5i}&My%SI!f)F+Sf8k%rkyaZ7z-#L-hgvY%cmXecoJlI zbQ7e;)n43UW3_O?V4+zQj~eyF9Uyhs0zZ|KO*T`Ci2VLDty?%u*SC!gF~{*&fq@~l z%QN2~Dt>b-)744Nc9M<3!!#GBV)b3m&$Uh~t7&qIu-q2;bZxES8Z(pLYYof%#GzNS zQ#nwK?nkz%Q8OL4T-j0O>IA{-wGW5l*a)TXX|t96`o~O*m@D<1Mx}f-01x_Pj{PaU zx9vCIOkl};e-2$SD7@{^AP>wQvWhVu8uaJ{M3!gKEpvBb`-&_%21?!-Vx&|Su|i}u z-CznZi{F;^c}NpK@f;-3S84P{M#=Rarq3XhhN`cZYJ@J!eCy$;uNoRcZF&pnU4fwQC+ixJ;c=_T#0)~~ z*b?0b+*SfbQcli&fK~-*lV3E{9(SWu>2U6l_dYJ$v(w^=Kczb+dhSqOM@} z5sG#YBB0d8pG)=_{70-WIv^_gGSvcU&<|E!}=I$XV8iT*}g=ulxB zJe=>k^KiYj!?%=gdE%6iD?M$qv^gQp8-bZrKOs~sGiSrc?ezLCowI&lU0$ry2~TP1 z?2x17G(uRNf}|FN7U>u?>Sz1m0c;u`fCo`_hwV5T4=Y!fu}IESRBjrD(quQpVEJ0F);aEJBfUEY3U8#G2WacDG~8<zS36oE;Pe1qJY`Xa@&CU(p~I4GvQG#UB=L&p1T`D;8Gm+ygYQqG^rd)ydgk*C30z z{`g^N-&=}S;EDkTFYcNakLLWs!eF@z?29uvfNbIcEAX+E?O%X$gi4W-`VL7HJ04k; zlDo`N48P=!pk8$z=TZVtC-oHkP)ed1FLmdn)x`Z3Yxe@dPU>1V38No{eJf45V^7eqpB-7Q$KUw`4Y7dxk3E$u*$f!m2Uyeo(_ z`?a=@{WKndh0t^RvMW;;7w!I_?FEJe+(XZcPczh$9fYdAcG{wNBf4nFK#?FfCkJe> z=&_5_yeN*67nbue|Xe{(7i(|UJ$h@@(2=VPXf`H@}2!#8T6%-Uax534i6#_^( z>hZVI3RB|*479yzzvb*R13RO!YAM0-T2F%0OsCEe@9Dv}8-*;3L=?mfpdfyG5d*32 zkg~wwqUW5xI)#sI2dSU9c z*o0S10R5#yx&&4auE{Th0{{?V8{?!?6&{5Rr3Ig!z^|Jf3hX7%`kNgctjwRTm+cVW zS@#dqCR9#}Mi7Yk`^G!?2i@-VRsf`M+_>3ylg(*L!x-+dHOy} z2J!V`-hJA?h>l%DK&<`6%?B&L4_*KTnEz}WUJb%Z-D2~hh&Ao<;E`lAhE$ymJNoUr zkm|_I)A46zBJGRKX4MvlNb)uFj`*1dq$6!_6&a7`_O6)8q{uj{(K&d?=IX&j#3*6? zz2XYSFo?<+bL4>2yw6IeEi%n)mRGtBqu1_Oa^OgQS)y+!426{pU1-JCu+7R_4G~5I zYO6l$!Dv(#J2aV@i0PEw`xkIGU?k8PYzw#~AWNDDu?DM9!{X13^@-a2HK5DRcF-?% zF#32eu;l?qGr+%42uQxR+v3(b!8#TkCqQx73Z>|S0G*T5c$Mdw2*0J?EbqOw#tDJb zhzNrq?uMorB$9TE8>{ zESHVVsP!m!0DTl*o)X4v7muJgI-adV*yiG?+3BA%F7J&^zx(;!G3Ax7xYMC)W8imJ z?N`PXhr0k+aq}h^SvtJq6#U>%|6B$)%VrGF7v8L(LsbZte`DxygW$VTsZb1n8|6@c zjWgArTL<-7e~ZP?2lndwp&u@c&^yYm?2z#Z3${3wAg&&o2D{^}Uvg5)VD~qpCZgO^ zDItZdOTs&|#V-IDHfI-LAw`=o>jX)C<>clIk$0&)IwfC9$%z5i+Wv57V(0Z zE%V0$(dU;q8XdeIgfMi;KOlftE#VW7^Y+TnPu(=pNKT+U2NA#DWedD;!C7G0lrSZm z{8d(bl74p=&Ngs*5GJa!efF8I2J#cQ%~Z^pfp^>qYfx1@Xfj=kRJr?M=iqZ4SRT>v(6#~Bmh z;6u2q!;Z%erovnDTx>kk?d5F@0Kfz%e5E`HW+;UzQ&s8Rl9sn4!?&_O%CdYNotVMw z5g}v%Ji87M4mMC3tE~Bcdij-4vdZrYYsg^W2WxF(r2)G#yB-W{I}2l{H)!C4 z*Wb_r@%HfO&D5;#=@9}W2K?u`&sa(O9`p_j>;Z2BfDPZeAqSTSktIWU(Go&VPR`<9 zu-n~S`&hhQ4yRu_EfIgffUDz6Be)-;njh9nZo}>%Q`Zq`R!5#=)syt=uCJTxH`eKc z7OV_}h@;%^Axj=t$aKItrZ@qR^3O3^F@qP5dY*T}&v`-obo$0N{BH%zJ zBM4*y0Vd_;hL75x3z?K!A&EqdGCSER0x9LQexEiRkYDM4KRS@c?^xiHD61VFEw;q8fjTh_pVN@=vlR`iD?Kg4-^K z)WF@`-39BdXe73eiaQn-ex!xIUH@>~`n~?j`uaqLtF5L`ODl762DAC;YWexsnsvUF>8e|NDB}AeN6F_>rN(c9aWp&0m*(6v)Fj zi|2GL*T<`!e}b&`n%Lt!L(iOhK$Y284bbgq@g#ultEdgX239a2r|NA30{y{}5fEql z%ru2L-xaZ!yOeD~yx(I53|ilFgH5wGHT5y&13x%Cd#(Y|t9J-BH*_=CpwxKl)CJ(? zpn}Vhd*%9ptO+Ol8gOL+uTqI*A8m!bl<_Ye$1$l2c<{r(DGcl`Y}_n?NymW!K=_C% z+mPJpAbIQu$STna$6SX27zF`{t+! z*^cNz7*UnU#j5m;=%>SGX>L$NaqFR+os8>JwEFF!3MHidz5XHd0{Q8gnN$;=aM$&5 z8T%n{F{l}Cq)|6~G~t&*xZ0?vNN2h5ztjES&!U@0xSy$pv$3+`K>$`zPyotY)qt@L zt{h;0a+Zv2sKi_vCmekFa>!?zRgR^^KMzDViwFn^pcl};Ey}YpQVQ%T7`Zr!s~eOL z&yy(DeS;{p^8)t>Aa)Ef9F*DRVN{=0z8#$@(=)KS=M)MDBqlD#Z*iOoyvR1FTS7ty zV9f6H^!_dlJv5CQhK{A?L=MvUHpU2qyrE7DtLlr*)Sh)^yy$xwliAgpmY0`zEWrFYgBUO&@HKxTId7H%c%RWT;q5zOnxiZ);J{Ulm2w1yZcxjk z?jz>~WQ0GrnzAXr+?n$FM2hkewNS&kO$*a@nD7qj20tQ##{Q}M!G-0v_oIOZSN$N) zn<|%)kl^8qk2$a3@BLuK-QFjg^EbCd`Eq4>x}}KbS>S=c9+U8g(rLK%%&kT1w#apX zAqIkd3uHN8_>mr(G;N+KPok9|qHRXbLhG9wUJPvy*-|K{Kdulz(FAo0VTESMDRxl1 z{e7-${n$W3w!a7f=g%~+U?te1lreeCnEa zfCWd8oR8n+HmFWTW~Lh}%dfO___mj0ujlML%ew?&_`}-20J)}It`j%8rIwLGmUa6* zk5igj7U?(kxY&4?kP?RaNJl+2Hozk;d5nUTYW7>Fcl2uZV>x+##o)h94t7RgdLpcDYQAfNj5zt)B3~+Zvd4~?&`A8rS&k_azr;9~|7_IQb;M7fpB3g`ns~d6 z@KP%~QZfy*JwNG{wQb)YB#LgJ2t5f4>=4&HCe0H_4rT2C8H0sa&?HAv2TImXa!JZa zVcV%Pq?G$fL7vY~t!&9_X7NdPZiRU#{=xLoirGd#8~59vIH;)COTA%=3D{YAge0@` z8nD6@8^XAH|a&Kv}N@p7&$o zquoqo6#7-QUn)7e+?&2XvH!vO&3m>V6;u;qYJ9W`fz8fe@PbE%t-fD_g7c`7rvz=E zL7v?+ZLIqWxS4#TJEQrDLTmkOs?Xy_s`wa&ZQAvivqOBurG~?Qz6bUI+~npgx#{v~ zE}Q$asI9LzQ812!5GztP!Zo*YU8xMJS~%zs@5YKR{r^@ON1BE70TPf{*d}Q-!c+(2yK#_(*Lr*M6-U@fIdK z4Hm8w`0eJu?r8oYNQU6V^PTx*V8i5#+uH1WLYb8ymOQ5KWpzzR6fwaAYe-iRWDUKg z$^7x}DMW~r^Ex#Pr~db8r`yXD$vJ;BHLNRi-SiA$+|ui`T$Fq%umIz67N2;XVrsv0Md>#J$~B1488qSDpc5cbkCW)fKAgMXKpEziXm>iTYxbelM=F$~tK;IS$uB z6lPVbxVPr_gYPBvJ%}8!U~@i|yBJSNkz;@Ee~FxTpGUh0)WF>qOuFe6wOZ8p69A1X1Bx zOX4Ee@37~8L!j_BD$T)Bkdao_lwJg^(12>Q4-G6A0H%=|DZ>{}#G@2rCb-Oo3|;=ryzSJ}$!; zHbY>h?yHR=w5kp#*&5cfm=FQt76wuUfGG0glKb?f@PAQ0rH(0{ zjk)FSV&pmE>lM7A{c59wc8v!*%zG3)`3Zke(>PNVc=W;lSC`~0Z@x(EI7 z|DdK8grTQB)v*de-F?y-_{6{F$qyGzS7Ve^0LevXp>_0BT^BVG;{Z#)0aBc?R@`&_L z3TCb%#HrhFR~>T6w%=u4Qq$FTv>@YOtUqw4gNduu%w@s^kyFgvGI0wf>B%E;z!^g2 z#)mH7-uL4<315~UJ^9Jk_Wyx2n|?!@P+y4&Ib&~4KL!huftJfsHDTIS{w4jG{U6#+ zd_+6*cbABFJ@Hpz{aajd zhTt^JQ|`?x>ulxqTYF6xOxnnN3b+@?Io5i$=Yi71j`2k9!CS}Y^4|i!jZmIy?B^9k zEI6{%q}2|Vn9fiXDi-ac;w2{CnS!_kr=OdM(WS_V?B05+*sNX5R5~9%wGr0F!^^tN z$$5*_lIvk+bJtDVkA;EX zUK7wyO8CuB0}_g#0p2Bdi1v9Cp2@rMq5%TGvyE>2;`$X|^Eqbl`O0>npfVvL=SaAa zXSJnEi$^i(ihfSWY4w{m<~{!wRF7g)i5$w;_9z zg84T6Lk$llUCyJ3(N6*MFP##}ot29ac?Zc-xZW58Zlk;$3^klqI zs65i$tQQrs88iQ*$lB|3Uyk(`b_kPxvTdp9OoCt=BW-+3WK2|)R+A44mH}$7*8icF zUj6kAX)(n61Ub{jy(@o2&$=(nl+2G2sbI@w>85(3<E;%f#MccAK`8BJ zR%z++gv_0gW`HvmQ9Qmg$`QU}4+Y%+Fdq)VksMigUGs6c`%@9-I*fH?- zv)0;clbk6)%L+C07Ysa=5&P0NRDrJ}mxf@$4Z*wNX zXKXmh11HYG#7Ul=)7MP+!ls~Pj>ug`q%OjNaCtcO^C7P*!O-;%UU>&k;q80avudLA z$hvSvYE^vti^lmOLe~ER$lX+t31%AC4q{>E9ewD;; zOrHq!=60(2hyl@LuGI&@Ip*oPbcSqsp zkDRcYZusEePYKLfr}gST z8ZQd=w!W;?2Z6WrbKKiU6D4YjSmpt|C#?H$Z)$1^@N3A{<&GphDPkCZwhj&`1J#w!_p zeMGQ#c`Ov0g1GV8M}TLnOWg~Sy#Id8!A^F z8?P;=+P9u+(vdNOZJ}1q{>&6$gl?+*b1L05A=ruPmcY}mAFZ~FUKVxgpLm)-QSI%H z*6ZF~&bCZqxV>~oL8u{gRZKfb_8e6r^n3TF@DJYCKH;|i;f~T_nT$fDIU)|B8X>#X zBB5xMq4d-Hv(V^(%)d0HkYAt!!SWYl`g%V-vU%gu$tWjs9UGEIEz>iKbm6zI)gk|U zu@lW`vRirr${S)?@U2u6_*NDIQLPSL`JIyR1tt!u>OTz9yN1I$kqTFkhWsO`z|VrX z#{cZG)1Y+8KLWuhKCV#@;11-v+Lg}NwyO05kfvd3Pp}NdpT^-iAa^rU+pofW~5z2jBzZF+A;DPzRqOQ zG(g%w(}IEjB>UDpd#I_h+Uc6YjNqngq312=Wdaxe3(eTUt4;CuIM=+p`s*2qQLj`A z1irSu4yPfJ8?A*y3LzhXvG^W`;=X=PL4!=*Z*f1X2E2F{_HU-UnQm|R*+n;lNER>iI7=9iAZjT%4`Z9D!YofG2cf<%700ny0=VdA?_WT2}5ju0+RVMi|Xw#Uk`l>63>6Qh{jxj)^XCoKkqfs z#OQ>N2QVd$h1l?k{8o_i>UZwl-9g}WBa%}=`b0PI zzxE`S`yLXP+WQ2!X#3MOyo6W=_nsxy5q4TEy=8QsC&wN|lS`D1BC72Sv1nfCKnMkm z+VuRh=Bt#F?-p2f{MxhHPlwE39GhpjAVMX{t9i^09F;ZlKTLCUX)jR^6CAkoRKcEH zpOEw>8T%Yb${))I6gf@DsF-+5MfpPvi>6U5sy{uM3_SA_ z>tlh2BEe_6A><;-ZNpkW7O+p=JpxcL-98#9T`^Q&o}3=O>L>e@=RI&2I2`$<`#eg5 zhNJdS)AIPPMVgtxFvnS+_mZP$b0bdmprE0__}O!y zHR?8sq;U>B;;LvB=~Gj$?w)rH4h2j)6Mkb2m#*KqL9r)A-#&T`H%Eb-2)4lZG*DZns^Z>63; zhxwG6&ZG1EHx(`Dlsfl8%2?Lo%g*4?_@qZ`P7}a%3h}z^Dg8Rn+sIQS;e{gU|?z2Y&(>~ z$$+)^kq%`BXyvszCtE`h){BUn(%#7VmFV9(PV|W$bwE{+Z&c~VK=K6Z;qA=}n)Ga% z&EoHW;qXhhD_BC-g1!RJtgIG5oq;Vmu?u3|RkO7<2TD?Pb# z7}yq{gY8-K#Nbv@UWCt&Nwj(sZ0x8c%IV7;)mRbV6Z9UkI5m`c&Qck~+}L&&z26a9re^VMsIncz8dbRhK;~ zdtb@FOIb1Sf*{a6BZM~}dt+$MWN$qCi9y8=8hJaZosLTUM(XtTH51~gl7kh!!XEm@ zLX$E_Gr#)mLfZv2wJ#wl<$@>6+C50?Cg))}nRJ|W2C+1y3*7qv7V>+DK(VYC6p#V+ z4hTPWd4R>{1TfJBl@01isWS(}SsywH^45QNP=J^KxX&S(oMPMR>}_--ln;c~l3D8n zzAXLU4lD*mVnr*-9XBLhI--JRx*;n17gy(cw1pS%Y@bsZbA{&WZG6@(lutQM(a9LF z63!CutYkIaSZT`BAI~OC=qaNjlr{oI33{y6r?O`fneE;uEZ7=v$kwh)#8iVinAg_h za$m0-JtxB7;*)7|fAepC<9)>bJ)k@V9ND>dlTVQ}P=ja}xY`3YKbg}qf@W+x0UfLb zPzo^r8yn5^%|1FqJ3dz6MiQxPu&`sXEl^N1w9|X_Mr%pFBq)_v7IXI%Sj!eq0s#*x zz?e`hBgVVVIgAV$>;5Q~J+GH^S|ID&-e{=Rr&~W&va+blo3ymdz?s2+t?@JDm5vrd zkwLjP4kI(`O3Qr^V61a+1t$2L|l70mC9 z`37^rvlp2V@80N5oJ45so6*<42~2MrL)U}1p2Y?}wxh@S5RwvnJuK%MpI7712}yj; zF~X`zVb84wIEU{%PvR8h%9ZFfrO9wpT)Hj-XUG>i?MuMPK&UrgHVN#pZ*dPdt&Rfg zxViCp9YzJCW9K-vcX;e&6Yu}lP=a#}IEJ1gp=S8yg&Kc=eh58P=3c5L4X;CTvlw(b z@Ow0GV1YH-rY<}=T)C#13N#y|NeYto&!iNi&EP)J)^Ztq5Y|9+NZSm2si0c@nr>rhbv2m?3kRtew4ELKC%@%9+i0T} zlfV`{zY&Xb(DlkNi5S?@l}yyiikny z9Jhug8vc&yqXof*62JA?^53ptzqFhG6e7O;2Yq4iEd(7e92TQaarY4FBYh($kt48p#ki}Q5uK82NSQ37u8 z`_-jcokra|^Q!%aX1#mawDiOT~H$h_)FiYvk= z3!6cU2861RpdYNTu(0*hJ3yuf-|fpcA%M;T(=N6T*gZg38UgZUkU0Ugq) z+?l&jA#yyNc_?(JVIxv#!s)TfPM~RfMtiF zoZi^oC3eaP4OIb7=_NWR_~Z6>QL?hK^t7PQ(kvRCApjn}#%bntg^~a(D2+>3?1w3J zjaInwD)6@i0^Q7uFvYgk!a$Vq1Lx5C1t$cvz?{K<<~$MbOtf!zA{*-6xl<$EbfOZ z8!dqo@ZH_rX)1A_8%>*ZH$g8c=w^{cd#|aG*$Q<-`C^j%rN(JS*Ee7uvrRw?)@ty? zsz2m#XFi(k_o6av*bc+oyn&ut&< zR%<-y$09CJ<_H5@C?s13u zMu$?T@@mQ;wE!g+S^tG$7hRc6H^c(4;EP5?~>uy{)Yoo_=!L(eY* zC-NwD-JtC3>?(=cqumh@O*BM&v~dD^$n}jv1gk)3V>&olbO0^OI;Eoam>tG)LcdcdBGzhNXv4kc@0*(hClmWls?S1@f0ZnTpEfgIh9qsfsQ&{uk{!vS#U}M?99)F}@B)uj{ z&jn-{bfSPSHrQ71ZprPfF9`OfdyjM-zt{029BEd$58_*tim$O~Zni7~H!LQsZjq(Z zY=Uc~Es$!8l(_|$UZdAsy1M6ooMWqUhG5Zv8bj>d0tot`Ey^|RoI%j3t4|GZq`<+{ z2GS(3o6ud!m0-bwa}e;WOkTShRyK4w*CB?RW^OsHTk=UEdz=C zExNzfA}nYd4(BE(H)bLr4j_94DB+pY{($(4_8csD3MM@cGad25 z!=;fN9J|v49G4qT5SS-|ArSzO2EwRAAY28keq`|upn(An8P&wahEkSIW3aLe#z0Sv zKVcQI_X!`h8kb}}OZgAjF6S`HrbH9xH#;4dlqBAhl*y=h4cP>>4fYSQbT%oOH9&4c ziRi+>xIy`Dy4Sg{=4QCkD+I&4j>%6~;xjJ#I#yX`KE%kW=4GeK$Fw`eT3yz}|9iS% zt(lssvwb^@KNY%|rQGbky*M##3Rbm*-QZ2o4@&4V1A{n_nh;kr8>jd70% zqE&&8)u<3KFh<@wG_vZc41GK9wVpj3_oUL{}^O4I1WaH?@s8YOj!^vF@r1s|S z|D)?Y;Hhr^|8Y$X%E$^KSy>@lgoBiklx$^YXJqFzRL9QVP8}f`;hpsW+>O4=>jc0F9dN3FZnzs*q2l9w`V^uhS{Ks!4w-;Z2Q-L8qFMzzK! zy{l|tt9s0h?Z!u7wD(x)Zh z6lRq6W1!-VPLV^(7wvV4)32Q8fJoY=1xs=#1YVq5`WJXYwIPmLcIr03_;S~W`{9l) z9FHu0g}_Z1dA~v<(JpY3@&fb7#@a)<6v)ETYirNDkqE4PuPthPmnYKX?tF~wEw%|= z-Gf9{a9W%GL!kJtJUj$7Lb=V(7MGg9f4KcM8+{Q5`1VUYcA}A1dZtPI08GgpCGzo1 zPwrxSFDC51jbD|#C9j9B{+)*sj&*c>)@A4+SSr{KP?Y|nO5;)N4qhdCa@T7Mt=?Q_ zG|MOd%yBM<6U8&v979e^cKSpe%QAy(oG&2ZBj8aq$C~Bd#b2=^CY`?2bE)OTkF9?4 zmfSZ)K6@@!LY8F!)DH`4 z#YhO9+qH=*Nu3|w%L8Q5c4ZubMoDtsq?&7tmmFNIk+HTN-$|;k!{;O@g>u~DQ&ZnO zD<}=k_C=4^MV4QbAVsJE&>#?OEjxfj1tHddP>n z;%jjLW~|25M|KT|c(^%?Qv)j%O3i#PFL>tp@4~; z07WCKXno~=`Ey}k-Z51SrfvGX#~qIoZX>aNt;xn5@#wwQW?fL%ogU5OA$sKXty&j@ zK?ov$IhK^~K8W=>`#OQy=+}U??zd}|Ma|y+H0_i+9S6pG!YO`}wtQ?fc%rOin8HTp zToBvi6uQ|_fBBeSJ}iL`ZW=%q2-Qp4sR?XVWu!3_?S>IY29G|-|cHs-ef#qAb)0W1 z`V@|tST5zTwMtE&Z?<;9iagt^JiTh?CT>&CUP-wR$YIBVQWoodu z2kbF-nEBPiE#6ApByY@*w15J811IcDMf4emYlorPgM)d%Xk*Hi8X!apoU2}&U`_iz z0a$LECYtu4Yt;e1iz_!aQ$-7bV$d1_|HyPsKXX$BnsE(iLIT|Jbg!@N8_?p)StX_2 z|IeW8bQ!r^o^>e4$p%2Wv3n;dq+&#Pvv)CBnaBrme94Y@u3%)EBjE5N>tWX8vxGF6 zM^@Z#_;qcW*eg6O1*@N$_m5Tu(?{}{mG}C~HHx<+tLJ%b$==R5`|U?YKcixr?j7Dn z&;B9uf`OA?z9F~n$#?Zc=d1K*4lRt_M=fKDfwbt$BrGYpW<*O_{8Q@Os!GbXP~>++ zaV;?UrUO|cXkY4q0cGx(Uw;(W8b#Z9&CPv%#+yNGkXqF9TN`TB1a4UyHo`L7xWUSUhoOwTd}t?-vmfg4K9=#d-~}#y z8$z67eB;=ylf4SGcsatl#BNttS2qrrqky4#;Kpxfy~n7C)!IaKx`bVXk0AI{etD++ z@X{g3IbVYk6G<% z_P(s{VJaSEobm9Vw;(jq*bsXc>)g|7FJTe0A?)bWnEf2`lfkDU@s9;`X zsg3wN5<5m(lppR7X1RvSJtQ~sK=}LL5_ofwAU1f->m0{%$8Ckws>x%mozqK2K~%OI z#)->pbaW>1nLw*_^Zf9oM-lVcnEor5zCiMA=_P~s+UWN)_StSn@Tb7fnbKX~Q_>|# zG2i~nZyv<-IYuta;}qtF^z^#XOc4*mYJ5mBZF2JYs^n%<331+Tke!b1nE9Y;=$5N{ z>e#$JM_}G_umcHD+Ovvr{}3VnDc@(GeLiV9Gk;8KM^>{uI(8Ee_U&;0cV=Gdh5`*n zSm3~_J8&wHWLD;61pShRUs5jptB@y)8WGFDyiOy64em~$ChOsaMujo#|M}T_pjmZUy7@6ALZ$bL0Cf+TV_$~a2s~Utvck92XKiU*jxhBJ>;${S?{2d( zGecKP+LO1Re>-EQp^qWZeR*o;k%r*Q&ECDD-|$RfKlr{2xGR; zBq$Z3n_(&}HGw5y6QG?QfBM?T=4Q<~#T&KvdY&3(ol$LZ#FZa*$s`< zHdVj}oR3^An62zoTvqng1@U*?{7?)?Rrt;c5-9ko1dD)m4K^Ss=!`>w^{eFwo6O}5 zb!ulL=o8tTC=FT7&4xaLWz5?iNF;)5#J*UHJv5kI-O(KN+!h)rUR^ZY?BX&%CSqzR zXSZnaBbC7G%w00RVW&<0Kw2ez@9(U*)XA{9NBXnkNM$JVxNze^hVuFKv+d@Ai|k4V z+l|CBvtl&qzeXiL`h7KiY8o>oC^=vxu-$CL7(M^iYHimyD}S9_kr%w!Mi=*e znYhqB$|rS#ly0ZVn%VuXd@=c}-wv@9J(NC63A9L)x#sTD@aysF??hLmYAiv;{#BtJ z`AWG`hmz80#Z|FCxTI6U;EpLTD+{ef$KnU8Jl&8iL39uTn$_33m2b;|`JLNxR5+U+6cqtCNyQ8mbzIhfBgKtop!Do7fI7H*# zLeD^s02!G!T!7#n3&{hw;FpqcDD-n|kT4D^97UFdhPaCrbF;I;bN6I;n3xivkI}F$ zOtBxTqkVyafxuR9eBB5vKOD^gOVPz$G&bVau$9@TA{=HOht$+;gH3M(@8Y*X*efL| zyLay%<896}!jGu9Qs_g^biY`;5(jLdfNdtUyW^KvaiDR(M!lI}5!fEc*Y2{u2BKME ztD#z(RnQ_-Uo_qvKS}OrUz^Yeui8Z>6qwVl%n!akF%5RHBlAZVyMtE0y#RJTE)RI2 z&=0ZPfF8)Y0pd8{E%SSHrCe*FPG!5$U zd+03p{@r))N${BZzIFS!crkF&TqQc9)lS+)_{1M+MYXTlr&7M(3{V@D>00M(XK`_D zd)*Z~{@|`qCOCxKGSoyb<9@Xh(eYydm19r7V^E~zO3b=$fwFf))|$??r61uN{tN|x3dnu9IVY{!;GsBPkAux|)iL1iT^nuKI1wk#9VdkEF5(1% zjA#iY61+kq8E&A=W3sBSRn&GrG`zyXR{ga}laM{cXaJF{Bz19N;kLIo(=>>YZ2j!i z1$sVh3_K}(G)#E7HWY>9^)xmwJ`j}yW}&(AcF2p%ZMmKzpygmY$cLWjABRk|OMG1Qc5E za&0R%FCg6iv~E3|I;Lql#Oxa*L1{GqmCccAu!rB_H-7a?PH=og6!tqm(U)3D^GxWK zm?-_Ufwgx9cue{y#cfV$l@>B7eRKR;t6YlVMb=8hJeITfMlgA8xc&)9?)2LoNb8}# z3--ZxyviXa7af<3QYEysT(XNHYaJu3rv<@^QFsRITd!|AI{t*zQ-Ye4XWFmMTe5F9ID_6id(H!6ib z42j#?+8X_>v->VG-UHRqVyw~B_^WHVBIcEbo7V%%EeXey@LUWfPEQ!)irI~iHJMLh z1fPIF5#v?rWd4S7`rk!<9fPDB1Z~0&icq69%AiwX3IF_y?swdJ->b z%3#e%Z@-CmctJ2oyNmG0K*tP(R2KapOG*+Cw!r6rPK2DXNkH3p7O>jEVU-Jo7*{_o zvdez}%32_deR&(2ls{m0AG}Te)olT701?x-g>Pwo;P|u>In6`2KN^r21ivkAit-;%ZRe@|BJx~}?Sa^5Lk)QugJ2AF_uhHh%kH7ukAynhPN)N`Z4u<| z^dW>ucBr+aQZE{JVSE=edrno~xxg;`P`&{Ob+Cp2od(mmh?8F2hj7|s6r2VBES)Cv zwh;LQh-&%4HtTYtPHNHv@}}=k!wowy8K>j9cuPWcjOzfX)$B;@wkx#+*)0y7&vJ$; z)&g?0a=A zf%E^ntgOtknw{Hrj28^E64&ima@yNykkobf%K|ZYA0omYOg1Vzi_lV`(R+;r(&MB; zE}HA7Oftq}C<)Urn7E`YjDLoF3AM9-Uz8I;j)1x>I7`{>{4D2hWpPiKC2Ygm9K@E8 z!5WmFPdS45m$1LU;Z5l8t{2}lQg?2;5xx^-;QokFWqKeZ}}!tR7154S305auPfq9P+B6Dz^48IC`J7WTcMd1w+KET93H zaUtp?j8G;AYqsHYbV=G28D16|pPgj~trQ<57K5l<=DB!Xx?|ha)YNgxY$K(sox*$& z<`r(%1(}5fPcdi?T?-X0v{Phul> z)k*^lOe)-G&jnA>XLcVO<8rug_PoIDYX*4fo9t=cwFu!ddB30JBFX^Ai~9brHwob{ zg9y(_K|u}o45TCL;FkoIZ9+IFPvI#>ayjVjKmr9G+{`k!pS692!Y4LmKNa&cTSu6c zWk9I}s{zwJfYsITn-p6I!*~dMyx}7g_>9cT!Mwg_c;b{#IHj}A~4 z??xg3YFkLMcs1r5%p;SggvennB&rZ?@c`9}6HwcLSejv=fc~?6?iQi5h%(B*{7w_x z71SKc4x`|c%4e+oQ`q1BQbR~nFh8Zobz<5}PydUInF{3-X=caURnip=IVWzgt} z;JWnY_U+)B6A@zrw?{vTpm!v9;ND}nxc<^3DX)o$gy1e-*QczQ&523KN1Nb2t@N-3Mqyw+t9=WqER5AWg%)!eT1tH znHzvo4`FU987BkdLr4$k31l*v3yv@4-{VWw`@s~Hu#ls=ETo@i^9}#z4ZxfmzudYN zS9hFFOEDz}U2x&-V-OAHAlOBme1|Ftsdy$#>o&lSVWe^9OV;)b#p zrlDq$J1W#Jj@$g7t3?2nQFvjI-8V2WNo^npB_G=Ks5=A2m{&Wbn6{;47+s(@7oQ}0 zg3{E|QilkS6r|(AQ`&M)eI-8tEdUiE(`$|J=>oLqjIJHOb;-he}t-y(GTcvo8{Lv#h29CvOu0GIqx zOVyxQT88r^mu925X{!1-bJ<>2Qw`JWOkbM>F(>H4CC9KPG_ymFuk$~3@$_BrG>eIu zsk_@%Ue4Mdf*mAXJl15pL7ACFEv@Ft>5ye)$KLLSEBN3z#V?6&7@OKpTQ!l{AIEld z(Kd~HO6%&sqXoUf|4B{d3!Y?v8-x=ic>y~PCInRXGLezGVF5ax_VX3V76ZH9ZK0Rh zoE9x()b`l~bJ|wo1M4}gKfT#-;6TSmEjLiWlu$_Lj@54K08-)n}XhDyKVhO=P zqIII%cE6cuat8B84~@$uDX-Z9j6!g~VI2Cs4R`Q~+v=WTt#W&MR=|F)#p)FH!+C9O zy-ZtUt-0lY+x*R>(Y87xOXBK{cg1>s`x_%&(n8*0BbY$=qhe&Pa7%jA5{JM2s>(9Y z>kMg%RDFJF;i;q&NdGrWw)E`JmYj9})4e~EQBAa5Gs&Fb!;J?V<>UVkl(VgWMDgK9 zkqt;amZc>%^_A>sKS!V30gHf^)1DhY{-({``=d%eI{4$A0^{$q0@_PHb36dGw4di? zfRz4rf7-b*UYzg#@D&54U&P2uG6<^&pFHzFd)XqGIh30!U(tMw(``diSP4Q-% z-&&S#P!qP+s|k5|0vq`P?>-6YO}+7SaHgi# z`i(on7Hw*1go>zB`0+BQnZYdlqVU&O(wGSM5W>pLb*m^!x<}{&!jI2PXNh|^({3GI zIk?@dV(x#q#yYby{FZQn&4{M_9Lx6?K>w6AA3grMGrn<0b5P@$WW`$1V-~H7RAm&0 zj3)O}E9r*h3YqWa#|Blwu_N_x$+_8eB8St(lF0d4t*@gts|Oz&?MQB%^4>`T5tc`7 z2Lk^P8c=G1s*#8DPFln#PyBk%{ax9{@qKt>OAu>-5#(VL)$wNxtLP81g_FMGR)7-}>*)^Xlw$ zUF+BmR&&;yeeR4BA=0#;ctSDz4_5P(-v53n4Jt71W9Vhdw^iKsFAe6xj=qN$AJu<^ z%!_^z8;+M9p%j0+G})MsUwJF>l`wX8XoqjfAKD}q%NHsrsTSVl`MK+9)?51Q+fHLa zAQdRDhHK@&hf&^!ez`Y~MX*(fg{rwZGFF~8$cy4z6sd8bJ9FqZ zt1l;*CIh9??Yr6~ZS6pV2Apl6)&tR!HR94FyCM7FST;)*h|%5JrGfGM++=-sJ1;%p z8jc)LMcGsDJ%MsW;#)a_aztFvBq-vK!1Wb%Y!h#LVK^_^@ILF}kH6X#`RNXC?3ZNye1hT5E}DOk;U6dsCkjju`B~G@o!d z^1sgIA0$#J;!=x7FX49#i;2$#1&x{zB2P1-GDSgQ44(pJ_P6f2S|k^bt|= z(Yq28H*>A5p-uhW>*+=O@kkFM{spzt$=fj#2k)&*=Kpd)$cx*xZfr+;lrFvLk7-KC zc$Fgf|Mttg5WkBqufJH$|2RqgJ?i(+I$7j$8oq-^M^5y)p+esd`miXah+YEFgQsTW z1fI3s6DP)2t=Btt)q3lW-07&}8kjna4o$h6v^$53Lj19zt9HNon3hUk51plxhp+QqHqH*YAASdEmD{6Pv z|HoSD&865ad`YWWaD3sgHv-foqK_&a6w8fL-C68EwqpM-_92*uPGLi7wv;`uE}ySm zLrKb{a@}8x<_@JqoA*6_*OuI*D;qm1XVP1C(dK4EmrS03VbjQf9^RNwbvo55YNIOa zQ_{mcZ^3;VhR;cu082T^4WrGeu0L4K7A6yo<@tRqvKJcCzBK_MXR)9i?{a+01*%`ING0;AUo#@4SC&prQk8k!jujW-?y~GO` zG0nwUqQEHJ$-OC_B9`o&1%Ob7gfUq7#64fPt@S(bP0p)4Alu>L8_1rWzj~k0RG1=!GL6_(0&WJQWSSBm2K^Ti>r?B& zle+(q%=s$IlK^QEvTV*xU8uwmd|o>07p6m_ zpy;GK*Lu`T>Gs>Vi!7)FS+B`4dUh1 zw}bHAWBLMpZcBAnVSjjb3txV`q2kMX?^Am~Os+$3Ibj&7RO`#Yadf$b& z=S$*W(nV!lvCj;m5ICJ_0A?ytq)I@`_* z4&*KDI-W_lB=z=W^3v-Gd=4Ii()kE@~HhOJDGQagq)qng2KlHYN zfDFPPZD9ZR!vVEp7ey_^-oK=jvnVwTFX-|3eS%V4TIN2YEHmH=xjQxMi+x~nxW*RB zm7`G-HTjO0Z_T8-XBnlBNDhr_CN&K|>nh=q(=1W$q%}*pg=Fg@AGKIBvy#lUyAxBF zZ{WHsV=JOZi-ITF^!RYQL16yt#E!r`7wSED-OZURvRx8K zi?WGJvYfF}#qi?Yb>9mQQU-guseA58$>FLxC?yAUJ)blUbNhfEj zyxrq5d4R@=L(n+ib>YD|ePN|{JZS!q4-k>XP}PhT-;(uiE5fcO zZNoR|e8#$6N&Hq$*IBiWT|BEkiuG{MC{}8xi|8&K{v}GEKVm+vI+IIuKd&K-`;_|5 z^yw`TJF??|!`qs3epG$E<8FfND7I?*BI5-2X~=E%??x(k0!? z#ftBW)zHrui8b^CLw8dIBnN4~42ND^E%Sm0uEjy@`?s<7N010;N=fT>{t=?zKWSGE zx_w(vcgYc^*(z96F~>dbf2oj?5y^KO93kjr-z_cgmBxRL4`@l=0$;sR-W@%29xERC z@1SRHR1+%7>hVd9;cGi0XfF5-1kGujhxMJCB*~8*T->zp#OOn=!wTH_;vfrx{RyME zHiR{I4=SKC>p}aUVfmZoV&YzwupG3fd^^-BavuF zvb0u-Pk%c#vf{ytTe92nBhL~Wla3DJ?@6*#>J;$jo$ddqm&nI1DOrxo)ypAF{o3EI zr&F|=&Yt(fh_Td=+u}wPVwu-|Vvhd1S{G(i@iFZq`nB8PGnj(f#&<+@X>Pr{@n7V? z84oX0K)==e=bUPmSV_-lMih87I#N9^Sorb%Qo;WP_Vt_OZu%eq6^# zb0q8j;5w=2a^IyXZmpbZr_YE1cv6rxOi$w&j!U})0LrjIk((v~g4GT=WJlE(03pr) zWrkM=NzAzq;8{@Er(OS^&}~#}5YkNfGGfI4+}Tk&`7ytX+K_W!Wixy%J+?Q@vHz#M zc~L{wP^|!Ci|j|$6Svq|`}|YmH>tn#&DTq2txK3(BWVSc zeMdQ#E5AGRMsS1m_1cHAiP`rkVmal8oq0Yj#{jnC8S80)eHcb=w}p@FB;R-a+1vDF z3G)*>u#Y}_*jyCN%s>i2I{PrO@f>AS43J4ba(8J=(-#APgjX>L0<+vbGtsotr>Ld| zeXJr9pnczegOK4b5UT{p>Y`^lr{3SD@1MQNSwn=BRNBQ-xbP7qEZcnl{3T?KcI z{2Rn2kMun|luo2u0?iuh`!%zgMnI1iOkVV}3LdY?J z2HB&>&+@kssZYuMKS#hM8U3B*C;6_=>S(A{b?%Ix;#o$rEDvj6HQTQtT3;X9eMKx~ zq~f54_(u-PI2X1AH_5W2CriEt-D!f{A0;7s%^<2~_zsDZ$@9$rNo)r8ZK6_}fjFKl1$*@=p znD&ALK^hQNpciFP;U)b4^S02#1P|hG^j~h+mp{ffX17`ww9I+#VUju3MAFSXNxGjp zAvJR_^)z=ShAqnk{Xeh+;UO3LEJ>^(0ny5=-+P>v0K9SG07d7O{G6pbN z^x=O*Q~0L!@9C#ex@|AW;2!mBR6WR$D(06=3U;7#9?sq?G7|8Euvz>5rVx(DSLTT| zY}1M*LxM}?IS!TlHAzTzn6-W;6G|(J+bje34qwFaUTi(;)N*urJj|A)fL+#1Uvjih z*&Z62JXl$0SncKJQXzX;?r(i^Pt%fYBn~q!-#d_IM@b;6if8M9RQiS8=HlbT*hTif zDo@)6bB7`sN?%17(tfMHTVb3hl8g47RptTF`LksQ4G#gS2-bI;vKVHIc5SI^KeDk6 zt|G8$-jtQO^uT30-3?T!l3ydsqo9K@HMLG)vVbvg4uSgk+0O!CW|M4cFU3f=N-|EDrBM<(}bPstnF5T3A*`!j|8WGjff#)&L=t{NmNa1tWR(E;w zuV8XG{&_N+m;x!nPnq9tt-qvAfqTVObeM5*I^cfHS_JzTKLe;DhyGDT9t_{Rk&Vda z)>>-vl6waRs)}iCiRt-slcS@ZzyJ~Jg*iG5hD6QYT@`lhE6MS)1;7r#D%j;bXFngRAAs^9ghthX5|kS-JG|!la|~XQ zjhyIec(jwxY94zH*dmyVwzaj5biahb$F1v(9DRVP=LU})02rNsfe62OslzoOPoaur ziU6bCc=01IcV%T|gUQT~ANF}eCo?1tLQcD*q8U2APNL$Dur^`KQz{mDmv%?_eEb?Y ziL_>$K02!KE96dRj?`?wxK7Qm!ff(#SFS~bViH1A6}-iy%0+b7*ZG>Br8GY;0Tso_ za>aEt27vYRqS;zV|J4O|5AYa zvVHFS1Id*jMBI3FH(ua+vS#z&3X@wxi*6?Wue9+zqO=RqUm(z+1dn(8{7jjW8aA7U zyZbBS(pMD~{^!r%>sf@I2NP5pdE2I^$}><6niX9KxU$;fy}1nVc32FVDT_V0ZRz5mVimSI1Ca-Mh5^O4`7{O%|*Q^0(^`P z#$2+|u~6LvW0F5ZU zDie*UzFiF*zKhg|M*>WF5PzRG10WOw`UBZy{i=(Mw<5X9t|5p6Kj?NsOCSzX>U zKYO;QVnmF;aFArIv7NDkIx(W5qA{gN!4AKoAa<+)iHeJhYtMeF3qYcJ_^`h4X1&Yz zN`XMXPXJ>A5FC&zGlZ+XW|K==VO%T+sFF+J0O9EAIVNhp2?NF{5ivjV5M(3`KY|%L zUTAXbtU@Vl+0ogFFt+SFvs$BhT7WLsRT2*I#O?;rIG9)7P@Ou^z78xxvXNaUpx(x^ zz~ikc33l(tB)Gz+kL9K$OFHt}UER)Wdx_DF?e8kF*H1%E8MENm!M#^EH#f^%2fxFu z5A;N5@W>KO+Oua5;Z4H6!;C*?zj=e&!AN9zqMmoqKcSrPU~75ghW_RJtJ$94`pKH$PYW^A65 zpJBh065s{kf!Gv$&H%J?fJdF|3ws05J9yZiT`!~FwIQ20noJ*b<1)a!N|dYL+KJL!H%; zdH0{7304k=>%MO<*Sm{W1j^UERO~6(Zu% zHV#;N^4(SGO^+@p9l#_iAJ7rN*SVsMwFQP2C%H1zTR(u}C&%c4f8xp|_XXkuN_35= z)VxDqTWQFi(5e%K%1qFCfSU-pBuTWsO6ZG?#TQ~eg;=$uNN#8p`vithdR z_GTWCZJw6WSCQWJ&VhgkZ*+U~reRq#Nxw8Tp>_$e%#qMj4t$lSohqC(bGz=`PMD$i zn^ZwIA#x5jR~EhnCZS`IQDEc*+RsU{9$EYz9v&?z(xQYKG%VmZ?j zhjU`X58%{U8`>Yad3$$94qQgY9Xsg+0kCQYo#{$1$DeL5Q)NULNhaTF{=e0Q8i+n{ zlhdHHU5&*RMYcSy<3>>fnCcKbPYinvZQ98x&8tF1MC734KQV$2h_1 zt{f{nyKX=YA7Ph!+0Ldnrqq~^7BR>(q~u17)O6+!o}m;XC~;elF6%v%$vU&&>c3VB z2^}`d=YiF7V|eZIH)a1JthVK`_PZyqOdHST|UKnV3H5f_8g&}Hm?6lB>4l_+`41mxIeIY+^z zC8m}vE7-1%BcMuyJNTMtp~TryOe3VAzeD~3wM$xBTJF`Hk%@_k`T5r_a**CpO?-Z? zDklLYeApuUt_fvWV4AsC4A`@a@;V^m4p)#opfnJC82{z-0YmbhlbnhY4mKd02w?vk z0E~dUst__d2+Di+>BWfKTwHWaFg(LcW=P!oZ)l01#+upsU&PKR%)W#B9>60l+vi-ArV=C2I?_HC9bf{9x)W?nSIV{i@Fk_5e1x0VWvSpK zUsNO}AXti4+mhHHIZ25V`uIfk7jf2?YPef9 z<)KiQJ89ohgm9nvRc_(-Hz>)q*cnBCNq?M5z!OS`f~q|l=W@F<*Ga!O8L6bMss{}zJUO?;ZL!oyKhmF0{FuYC|cgp>$*SyZz(8&`~O6`m|0aNa_S&iQv$j&{Z z6TLzNa@R2>>As#G0F;gbZm}|7c}6fWF*XG-s&@cf*Ry7aK*yFHz)S{j(^7VK!>gBS z?dK2uqGq_>pwkH;XQF$IH3V2dq7=S)!vVRMsWn2b8;5}2IFP^lU&X%J zFlPsV^tENdsmP8DJ6`cz+^&tyDrKTAO;Ebj`I~`VC&0}+riVvHilP0RSaFT!+`pX} zn7p^0T{f6m$95j+OKaF#PC&(B7-{plj8#fvCQr3<1s+OYWe3{z1zeSrKz*<|?Eu#j z@6u=gz9D`bAL?+=)p^c$b;ZVE9;Uqd@=m_30+p^5QB3XBieEWUYH@ee7vv86rp=-f zj2uHV-i-W=3_5krf2atRVWdpra_23Mm~}7;o}$g?e%ItpeCRrA1R$S%vB_L0;%Z$s zt@Gv6chWELw@tAYM9p^}39N}IG8cK?MRn4zExgquxQy1!lF0TcAtt6N_-IK=Q{*Id z)M^>i#j*NEIpIKwu+4d7GEDKAyLp2IyBn(Y7XY^a2oKPJ$>yq%!wvNJ!$&}jilC%# z1>+sB9q=U(x}5=`ZmN;j5BWOG4RTWY-nhPYiH35fvA5S3P6d#u<3gdYwJU6m1hCiw zEAaSacD~a7nwCSN{0B@8ih5qy0AOQend5NzAsjNE*pbRd;tWgnAO_AaOQB%!1}T0f zHGyX9bf7cm$HsW~bM3-&a%CV&g?*`bX=rptR#FsdkX-z7_2D&V6RyDV{Z4c^C63~| zo1r{jj_G}7aS6>Trq*ixJv0(JnC(NfoDIZO`i%YGhPd+*Hdrm?4ixEQ7!=~(DPUip z=*M37`CV+CM}v0bn7i@DB7r1@wR@tQGInf4?fZiMLyr@!HOg1VS^D}sK)siO!s9LY zxg9x@4g`hk7I!5f&I0G*TX8ewxi#W9L39H0Ed5-_ahZ-Emjk@;`U>FS3(Tt=j3W~g z5~$28yz<*m0|xNg@|(dxRvMZcUU4JfY7LoaNJuY;T?kp=ZNtr~c8gFc9q`@Nd$L!l#zyOki%F4}O%;B~Yn@2@WL=Ju$l%DN7pvv#?L z0u7$&MNS&(N2bDyD_>@;Mw6smhufmUMp-5*dOp-N%v0vI_UcUT-Lmcp5GR^=b&g>Q z8Z@OIJX#pDA6x5H+I~V(il2d-$ zic(Xv@$$d#2;-qo$b|c|*aFeO&1~CrL<7Asp+s8yaEVARHxerf(Z5+@#g*q1WB1|W zx6KF78(yKM?rskWs?5+@mcCayN_s)>Zi!Fb(~tQw$IfMYAnH11W(J!fGp=@g(8@3< z+vB>}%mtBahVK})wZm{Mx?ig6@KJUibJJ*+J|}M3-qSS>J?+vetHtD5n*(RyPp)}e zzvq!*3%*flm}B2uv6x6kPB|Ul>E1?s!=*y6z@}dTH;Ry;2QOqc`Ata_>@KWQ0D0at z^LuwU_}eEU=kuA>5H^409l3n<)3Vn(iT2yi5$u4@V0dJxjI7=?)}O&Y-D+(=G4hM8 zln&pv!u{n-4U1zANqc0UI#12#UCS+OyAz9cY1=sG*b`;ihHrAt3^uY6R@V#Ck0@cZ ztfonLE1l($;!HHqi{|s6mztRr`8F{swLyw}G}*A6soJaNNc`hS@bo@BV~Tb~6dlxQ zE&t~u_IN7&hzZp>r}uMXRINXvIhFMh?}^hgB>jyR(Q0b!PUoHY~8b)z0JFF*1bNW z%zY$^8%Dg23fC2`V$>dowL12EN5?C${*mw8d96K9qu@B<|NBVQEY#a0+vj+3d)yXY zca;NuiiePzvflp0CD2=Y%VWTjNU%M_7ZCX6cJg5mg*OqpkaE1zli~M=3c~UV1EaLG zjME}&h76Bxz89$Hf+dXlZdH|6NU^ltnj z*UGUGnoFbRj}zTg8V-qF#~h{Rxnt-_>G5Q2*mhG06-1*N^wJ3iBOy>-?MyuYR0m-cLklA4bjAQ?6|J0Ftw_e;O%aVqE70kf!Qu@<6Nt}>Q)U2+P zLfIgKkgv%}6&(s0qUJ3kUTGp_p|?oNW`|r(DNK`OGYcXngpQMHJSW zmQz{jk1(>;Z2Pu_7x^zm_Wn{JeRu<#$#0ycsI^In#QfF(j=NzIDa4&B+XAAOJLSP) zuArlrtelUGiRaz)#*3!4ru*j6I7{NQoEM2dYX-`fxE0F%cpK3~T*bqTW!D#Jn?hJh ze7H9gjzjmbsI{x}Y`LJ$fui(C7hd_X*3^rBJl=Q2eiL0UuY-%M92u;32kaYN*x)TG1Rz-5%YfdiEmAN| zg05HY+XA%6h}WlTV7jglACOMyGFpmd^Zur_6s?JSZNKE(_DFVZL8aAyU8e|@?|Oil zzd@|5^qQne9K#4xpss~}y%T9f<>yVx+^O;gdwzA+?@FtZ-4dsK&n49zPE}r)uPAm- zT-r~(srczhK+?8Y%q8nXN4&W{x&{8ASD_lkQdpB_r1LtiL~EBSSjevi}?Uu_+$8$&fE9HG>Y^c*R4D6em z^G_2)6)YHx=5y8K3-gcSmwg3NHdCupAIpA+XFUHEQA*VSdj=4`5utcC45A%Kysd&c z8AJCkB19*!Eo}eWM@T{7Y4ItOa$r?KtxVE_ zuXlC(;~?Uog6?Xn|LRxMdMSt!Vx%Ez+5Pz~Vz=|Xn!nzqg>8)dx(qR8h<{{c1hi6E z_urGXw6qlW586#}Z}iWC*)bt-8|42?Wr1}>e%;`J3+z4`@c77o{kiCo-)#VN0vO|) z_?DrC73Nn=2gof8uTVFnW!Jtud3{Jv4sU|gd@oM?&p*aX62dFFkwa5cGdMW-;K757 zi;He93tOKTFp{mgD#;rsy$uEz%!;~$<5csQ*f)ZoeWN=C=gPW$4)c0){> zO4!Glc;p#!fVcyvG=5=WVVZ)1=@dUdKV+^C=b8ULvKI^Qp~dr<9F;Ej%a7*W)4YQW zg;CU8hh$#%d7k9c6?WloIN(y2LPH-k*{U&26-$fDr|EvQD)2v^-B>40ZX9H*_D~F6 z0Xa!1G&se@#sB;ew>)&4XXkWksOlD;cYD7+P?7zNPHjJ~-@+emMYj=hR1}#kBWUa% z9iSOWrXj01(c?0lCC3FqZs;#1b&Lo?vO#l zGy#OYO!rZ|Jp%dmBea(eV#H*&|H+0O)5mSoi2-(XW8*d zX6b`&#s_p2t<_wA_e}SkxKwRfo^Pi0MjW}qDeeivd57)T0!!dL)R2aW<|k0Oubo|$Ly>XV5ZIGH2d za8xCAc#Y_~82E^bTSM=g!%O}KSuS#mM|R4hfv=C{vJlrv*&;7j)v;S#WbOtxu6ULR zM+x0`Cu-->SC0+(J!ZDN#T>wgdiz0%X=HUyC9M6YuEhyfsWJpC)x`fFq$R_Bv=^L! zUlZ8tjP$HQiSL)qN;g9fOBdD#7-1~)G7=UVy2n*k3tbgHc{s+Iq}SPYgb(Dr$f2oO zIMzS+IJ#LyVXW?v=^Qa-ugCfFE~Ql^;c8()&Cwz+=Jf%kb}}(Z2VMcTgCB-wh=3(OJ-)L}B2aZj?IqrN0SEY);Aj z{kh$l0awM9b&qS}CCzh{ewvX(^N#!+p|lo<-Apj26c2lS4*pgdqkGvVeR*@g;P}bZ z*6Y8C^MU`-=EzI%apOY5{&270c(`ffhWbT5O&SSs_h zkKDU(k?ZRuN0q!WTl7cSb6NOL+v#>PDZu+He{Jg_y4A47XPnt(+(uf8L5zJp#ZIIxND+`XMAy=_{PnAk|~wo!aHuJYsV zm_z4$j^9?}$|@>L<40+0YbklXs3|`E$qtXs3Y}rTWL*AbgV$HV>G|OlQcPvVtH;-O zO+YQDeU9GOqFU&Jjn>U{!rjLf_1)odODhTje#Kd>uNR7*94bGo|*MbF*3 zMO@)s6A4Ld2xA!GF({qCeI$f}i#O?N;)hMvdMYFFuZ7Im(+yYBk5s8kaC{T*P@1>1 zstLs>bXlj&zAp&8b7)Pve=W?_`qx0TUE8JgC0&MZYftt!Z{(HEJ8UlB;F?<`?%JZ- z(#MQ@xK#MTt5aOi{lCsjD1-mp{=2^Fj;vr!-0Wc!StKP?`|5K{oRdFeWyonE2Ja#x zVOu;p!di19{Q`ZxkHg%R?`jtl?{42vb6GHs|K92|vFsd=6ScQI?NJtf&eYsg-v!E` ziQk(a?_@P_a=Eyk6SLXIbz*d{rPqtP0jLL;EmRFY&Lqk>4A5I^F}n;mx1*8 zZNt=Cj+KMgI#M^Zr@>jhX37;sHb zr*@jKj2*m`evpfPYuU#jr_(4mE68TMKT;p#G&<8+8pDymPKHcxrMz+KMSr^3rd*8- z*Ga0i@IAh}7v>eZ*R|_~T%Met4JQ2*NTV(*ryw=H{iMWGnG|6D#^?o_oW!%>lK$c@ z1|7%j(x%i{yOe5bb;urb-$(nq_5_3o$`zO( zUybsAZP=Ly-UVlakM{GN&q4Ave}`}$bB=Stg<_gM2vH3J=v*6!+o5mTBz zAr^4|c5KV66lC9A=9fzKc(f`r&fG#SKdMVIZ^V10@G6POZ!TXbXjH}MUU4BFa3S)v zSq{es*jqKp4D&xO8qcbCdM=RH;QG^~CFbd2<6LDJN~pw+N%%+G=^q`D{gy>G8b`+q zXjG3RecF}xetCiQG?TmfWOb^wiRBdb(aq)ksR90q8zlUuW7BlR4}>IBtA|9P^I#x< z?C?EVNNdFXefl6Nq4;|yXB^-aHzSpzqb=LCw(Nip{#TW>(AQP$vyu2Wn#KOBft5X%AbWL zW?P*PvuRw1$$GF&?6xZvB$u&vi;u%)_&)5?ao!RQB^zCN828Ir=j-$D7knb~-LKVi z)er_wd?Fjg9~*ILZkD{@SalwQ_Gp_T&Q2i%2+je>*=zL_{C+kK4sP>9j(GGaafa4G z5F+$j;H>Bz-o)pwfwlwnVRHFi)&Vo2C!)pZIpU)SUu?|1!mj&Vbl6jW`DLS#{E0%G z&?l)odv%|fpKQohaDID~o~GPw76Y2bw;YWl?tD*TzL9=QmXIE+drQYrM5T4jy}Bbo7f?Ibl95vd;e_5g-B~w z4kE0;*&!Dp+eyYBSdQf%FI}(mA$$4@Qwx}?^B64zj3)1Q2tIY*VA{YqP7Q!!hV97ihsJ(iSvLS^+pQF5o}1>@yBdke2Z z{oX+rhLK~$lsj+Hfod3+{(Ib&2}Y@e5r6U%KWb$Mv=QQbG@wioz{gEnr5)38&CaV$qNJ@E-@QZ;Xy^#zx_zKPeeM}Jclyib#O zGEW0lSi*u$g&cApUyz1Kb^BO{(#HC_ZCMaS8v#%?$UyoB^`Co5cUve*Gfeb$y1Bmj zNDe-<_uP6RvuSJevYKjb%I1UeK^b3yfLGYyBJZ-K5vFD$jO}5sYj%`n-uZ6U@8jO# zgNELTlEu~(Eel+!Q_72?>2wMYOKR)u-yGGzJ!JGTjp#??n43FREpCz@Qw0W=g^=8B> zQ`%h$W;FR%YG052aeasO^qZ4r3dS285ri8Fp4LLPu2H_Ja-79^%f9U`b|vdikTtT+ zEK{Kioj?ZKgV-c(Tk{s5J0gE+KF{tI1K*T|9e-uywAYTuyPL^4FLAa$@Z< zRKvOKG8;431=1HwBCg!)W69L8yW5Ky@i=!QWp`NzGgZHshz|K^ydL4T8II9x+_Z_4 zE0rNAXFBr}my7oac#4N#0ae>}88+rEq_An*C^`|cSHE@q;{=OU1C(EX_h6?PTnI_n zR_6GhSAHPjvj8=@u=z}4(|a+V?zGj)FrV(+?iA05JpEtyMYLudWu}$e-_VJS^ewmC%>^W=zp9ua9{~`Q^D>0}0Fd>BNU= zc?<5JC#C!gEL~b#SR_8E-7FkEG2#*%J@Qb^vQXWolXlRvsGpKi!&N z*Gzy8>eki|5Lv*|?caG)4Nx=sis|-quKjo^sc9ReUQErY7|+TKtI1uV%1OlUGyF z>NeM?$`-D_`S2>Ug_h0CW)bu0n|`aUGyZp)3eBF`J9Q2KP&Hy5JEi$Cd{?xJ@>d)B z&2nbCCuOhuX6r0GpksSDaL-s`pGe)in#n9?w9O|2i+_#!9bu4AMa#I}0y+y6)&a9m zsSjd`ZverBR8Rq35~SAA@vLoZ80X#rxD$8*DWj_+NGgZ`O?5cDp8F>Z5BvN{!rbpJ z%ew^TmrwT;9`Ah`Wv^iEnZ*1kwqUhUnG+XlG%jAr!&&%b?^yG2ULNz9GFb*Q5Wwen z=72I3Cn}gty{_`xc=+VUnCkBd(}L7_=hm>hl8m3Nuq{Ti(q^prOB$PJ1=K@nHVaT9 z`u6R5i}<6*V5odQq(ENw&sho*bql83Yk}>0veCEpiOMAe_@?&b-(PE;sC>4Ls*+0vkh{pW|2=^Hz@jRne zIg@i9{uS?Z^QfhkMm+4PcccJ>1YIw7V4f&`mvrvG2St=9YvtRwN1;3{xCU<0#q6Ai z4xJ2$m$aw(Hh<}PZ!CaL;=dYmJNxst{g8gk9x*1npFdvCjZUAt#i&y4OP>19~W9kfxXamQunJ&|peIbZoJ z>9j=#3`Nt^GXn>deFZ=5J>J-IL~;q+|ByRm1kX}(5ro80TjF+2L$NJDH?rAmi1k`bFTDgZ@@0@lY zIB@9(KF?J9>6`hZz(*2pdBP#%@-3Np*U?kgA4->U`ofgj&G^$Nr3sBdnC{8)1z}=> zg)6*{toys~faXQ*Bant?WIg+EZm*PMw-XRuz}f?NX`0bh-+5#c5Xj;B`hYpPv}_O< zIcA{tbI0e$$TVsyQ=%dJPn{Vki?Q9!I2QTO!jgIUeAdbG+@3`#9~&8zjBJ=r`mlsT zYdIU4=yJSd4*-}pgc?^ii-UazI?dQXZ-1NTT)8BcHA|BRs7b88ilRh#4>8zJ@Djx# z!&bznzfYN*_MDW*Z1ChJno#Xz_y#%LIvdOPiIXz!H;bMXAe=06R{knA(;|tJJ&Nj5 z7#gu%EYx}yA2-CeXDnMTH&s~}-{UGs^?l3~F}*mh*e1@&e!mSVN#}oA0pZxc;xy6M zMjd;~j=B15ETM2i^SJlkMXsP$oI^2|pq3!u9#HP>G+)0>=`{~SWZ7MUZ8Gch3-nq_ z%lLX&eVV(>tx{)E$&(%q`^$rvrM#wIlT$9bLyp4hoowFa1Y(h`cN1~a3Ao(hHfQ&7 z>MgBdtR&^blbG~O+Yd=7YT;MIHpJkYNdq;1!B02$$A6Y;v||??zzBLNUWoG}v6YBB zVD(;+BJ`%kuDKQ_dY+4@ToRU<7eIM%WK7p&u*IMn`x#-jW0YgpJ>8e zTD(m>+o_^h6_{72Tin>-O__*t)#P@Mu%wJ?*zlRvM9OOWGO5HPM_Wva`$keu#)Wz! zMoxxUOl+F-&pQ^Io4sO}LlSPUO!)L?`?@DfhvKBQ#w$m5sH70EJ`WBxYlUPgd_7|? zM1JYx6rY6rS!nuMF|FVCxsDpoc<5pJ<(sBw+!Zg&nU{r*>5sQjvuDxigQ(fKl?Q~M zdSYt6vmF;&wdD9yy>rDxn@6M+r zdE}WH&0$>RAoucs^+WS)dW9@J+qBraAJJ9mK(-Y6uI*ZUeaVE_Bi|l3iNUi53m@jF zlJQzNnV=}V*{UkriO`tAt2f|ue}905#htvi2+Bjifv9AT00!i~!$LH__jBj^PdxyJ z7~#R?VAe3U5I;9qlW|g0#9MDfjJvZGfsxqnGyg#V+XnJwx+Eq9`BuZV>d&ZmkKHG~=z->4#rLOA zo>&cv?HKqcTvfue+0HfjDEVTy$G!iO0Xw z?^8p7!^Wqxe8qvx&V7GfVxLZG>^ds7+$r5j++}>!P)i~EVL@DTuIbudUFq}P5l!r` zs}Gmpp47YU(+=X%1(DpsA-SvLD`l8sR{o2o>kFg!Zp}DvZj3ftgM?Gp-Qt55(YUgo z1!=*|^peC3>>@AutpArNK5Ap=!pNden3ZB;FaM^-I6Biy0biOqhuG(yRVefg6t@6I{~$;i%FDjAx`DKS{Lwl{nWD)y?^G;#6anX}nz z@^bac`_|Tq=2L+c?^w|tYzoPFxk+khjAk(}%f}1H*NKH)R$WMv?H(q7#vhJ>17`p*L6{3*ea-xX2QRgWbYbb2O_zI&a9{#8KS z+f{^@4rS~^2@Rt5&ot`#;Pz@i*>L7JyRclYIO(N;uu8rkXx&Mtz_dc2YpbwPKj!=J zL*KCMw-dv-da{wb2(rmXE-SWW{mJGqYwL(+)#-~mE<{t0bc3}DyIK!}_@hsy6Fwdt zVxyFj6|E1fKA%A|tyLHBMGgS_{5DKRJo+>g=cHcTU$S=WRph5dw+JN*gz& z+?5{Z^<9Xw%)=tiaN>*;W@pPSb5W?~Uur)bJ;X{)xO^PB5swBX93QYa*j~7$8$UAM zVzP|Q^S$2jfVC+++gFRDS*j`A+E<0ORdM8%=fy}#y!lLR4P`CSRoskFkRe^u=A0W# z7PZr7g;EypNUPGA<}Lj33G=3kV_el0NqS=uUE!sAH3r^kCfKS@E7zN!S933zV6Wt+ zD~#~z+xfa4q;42cuH2Zluagm5mLFH7*s-RSyLL{l`NjD>I7mI8AMAQ83nj|1O#UpB zowwG0=98`d^4I{`aY|(1)lX3hV{U1=cNURLt&0UqMZF_Ac?XGlX;nvmiCI>*!ux#G zA}1TGLVvEgb1lqGn3ozBE}Q?X$q~*e1M&hZr9ixDfWO z^q3*v>%WhK6@Im{7h}sbYXN~EO*MFO0UNuYEOFz5Icq&8O(`35Dl>H@d&M4Ywl{S4hTA(`Q5y40oOFnG=S!4a zR*;rEbMBoD`HkN&v*k;qQr%xAyAYu*-ra>JLa~Dg`~+p{GsmsbQJWlNOU-`w?(0~m zC=pDVB64x2@;YjLjeldO)(XC-_pCyDOsykXmdcH$&!V2tN=t0gG>VT?^8Hv@S?80` zz}^kTqvos{f%!|<9-7trP+x2aDM|VG+I&ZhjIt~$X`J;k8CGzsw%Q?R`P1tJU1_@f z%WikyYaEL?m);|*tz#mDH@vv1{NjllMA26a<9i>?FO-~?TVqEj-qb{lSXt}FH+F63 zCdxC+E=qp-Dp8c4ouugAyD$S1D|HHI2T4BzF|8YM*0?>C`!)fsm=n&1-3u4WF_ICD z{*QtNRYF>QJ|=Glo8L1X50sh^yA!vmb%Mu$&7M{; z2-cBVY&ec`Zkd>}r!lCQMksZUzR1ak$R zXhjHzZDN8di)5ID3`5hCP$lGnMz-9>c;wpk<=%FJo{5&4rs7MIbfKEN^;3fN@I%X$ zML(y!B+w`q8=lb>ATYTTsy2uTM7lWQnP2vHH?(+iFE5W>8t&OpV14DT*JEfhu;yT( zhvgfN&S~s1QCw6ww7HgH9dAIGiccZwc`G7!2{+e#aKSnHvW-0Lc3j5`g%0ocy&S$g zGm74Q>-!r1PBoLvnD<1%Jig^U6P0y67%}>hgelvLJTE-fJX=_z%Oy{C-v{E5p0LV9 zjEYX_W-$BhO%bp#ycRkDCJ?|f?oCJgSAZvn^NIaE1S~WQ0cGzUeiII9=(RVDtOxnj zk_lwB|K>Txwmp?(B5=F?B^RLMeuG4^4}czzDWmJzx_6*+Z8AUUz$uNN>S~ogx0TS2 z>c>|zwIS^R{@?eYA>a~E1w#J=8faz3@FNHv(lBX{H8(L|Q?x;I5_sDs4qXnw>k|*( zXU)w79lSy@Lf?0b-pqds1X*C}JN6aw9lR^c@f)EWCcAH1V7r2Xa7?AGXIvBzME4_H zrG}aUg^YH!;dog@EkB`Sj#pFvMeB@SwY3JnMzvNFDp0t?w;W~d6clLJE^A`WXskbu z_QbriuVYHr>b2NK>91L!f-L-1DEOaLEKptdWh#o`9!w5gL=z1HL9ILS=G50YHDz(Xuivaip4)72r&ZJMsUWL zd8Jc5B$XZ~nlDdK3`LkoE<`y;2Tb{$9>Pe#(hqejpKu216+MaW0*_yxdtB9*Iq{aR ztw*1k+z$#`N+%mf?t5u@v?q9g{B5w>X$kAK7Fbo6FKS<7{o|he{%?eXSVqd5AjjbH zhlk1Wx;rQZ$3C5Hn=fRV|5RGYTGHrOj+mm z8G4@ZElzekM2HI`&l}(J$1A;Aj@gWy_N*_?5w~A+BL)&8Pib^x&{Qx$-H&Txj^O0l zU_{tunYm5|DQkuxm0D`pOUJZ&FIWA#LOJi+%=0Qs4Y|m~!b8Nr36Ya2g1-1K-;(bw zPv1ix%Bv!L0eQ9J>@!fZ6SxFYcC$c#g^G%2?0ogcHST$62C#ZAeYp{o_vgXu$zaFk zJRF2YQaTKZ9hrJrHki6JR+8;34wUva?9JRF_ksClp~4Fg$YbMrTJrIYgT7cAN$sJ^ z6$BM>Rtg|LG$C`!USG&&Gp(TOy1yt_m4pUGHQjtpX&`5Y^8pCs{_I!NWAMC@7Zwht z#NRkCYpDy}A)JrBXK#aQTrqO|ZQ_CV`!qL+kmu@!GtLJ8+~YpalM)WASz8T!7TVB= zJjP*gSpa3&$t*a%Q|HA3I=4}0py~_kfR6WNYzRSPf03~G@>Qll;?nnd1~3ZzB`8PI zZ_{6YYOT!UUlh2D>oO9q-&l=v$>*K_2|5H&L z=USg0?wh2T6Ia0!2y<*%53)|e`CM!}v?pd0% zGTt0@=WJ+KimvqdGsa~n{KSsUn+;i(BOj4{-!Hq*+}%&Ws)|u@Y$ZGdLwZf?ZqMwO zA{04v^9CIYDe&yK(Gb60+m*3~7D||VisRx}=RO1~!Ew?@GwqixdA#XV_1=^(2>e*Y zeZI*UQ(v9gdam4lOn_~tr$iC{$yk-v1kpbXF>@k9YjCKw+1DFGHCSF-2zi%{tFnzj z`lrPT`?bDSsM$e1pP4(jOqOA1k&}<=W2a2iMFnhJ4-t#)8`lXz4mZ|soTl`KZ=7r7 zx)Iu#bk1W9f3N;A^3{tM=fFk_xW}u|BLC#5+^_^xb&>{j{v(-*Z?`$xeE92iyY zSCtV)%;lal?B~>7}KU8b8_Z(pJ?sHaU+O)=inz zhs0p*;}GWV0jvqEXKA&z(;K#>9iHRkC$3$)ilCBTx8As{GS}#)P+l6*N+Ip>>2WpW z^>IX%!NOxe37EX#ova=n^_w(LKWcyC%MBygJVO~?8O&uX@Lakazez-scPd87TgBtb zW>&C5%@_x4OAh^wNi_ZrPt?`npu=TMH8!#KmONRX)yNn+AL(Q$R)lAX{`zqe{&9_A z&AqNAceaufnFK67<80>bcGPg-%2#)BD%mwE)%L-u67!*+7x?JmYur(_wpEp5WkPrM zg-Jt)SG z7j9HOzoG&LFY3^%568@o9SFR;hnnEBla4NwLuPKsb0if%2|*21gC$e1cyF7pyPmHw zTsrKn5d{qjstpMWUhS=|?*USWxfGf0(3x?8X$m%D3LurbdeGn+772}&3Hl*Ch+Dfl zO0Os1)_H?W8-mmpU}|HHBr-w1JJ_( z`hX~8Qam7z_1n6x7ukJxttP3aZp1)W@}Ms`r`Vs{er#7e76CqW5hZboJ|)5+@aY4s zjkmm~_|CNm9S90T>PH@}gT_!5|#kC2VhC;dC$P2tf z+V}f0Gq9e0d;Za1OBc@bobTtkprD|@F6~6?XN9f3qnPK=p+jS`RFfp-r=XU^`A-tSCq$3v3YqbOPEPY_84fb>lD>1j;jzla_DBJ#<@`Pb53cVz z@7kDWDZguaCURv|pj+#KP@FNrI`p_}pomsx8ik~Ey7f!W1uMnqzGESy2g_f&2-|hQ>p1io~T9!SDQ}k+h(4)JKpBzMm${r5T_Nii=jm2BR5wwwk zB;K3kQ&5s$m@K(QR4V*cHEpa(^=)RkP-#adBE2~MKa1Ite(DoH`x{xx8(>1HuVp|x zbk<|?>6K)pe*-}XMf^)-a#g`&qNDWO@;;;P@w`mD%1S~OYS{^em`Jj|H)AZ-$Q|uX z^+m19etL&|HHIcz*$}Qa*O+%9TyZ`&elAJcR43`8K8YQhL}?c-#p*uxV%vx`rb(}w zPku^a$WuA3RDC3=FcG2E+KmZA%v&k4;m|5&UY4YBW9eibtirq<21$uWt|YdIy_ED3 zTgJ+-_5LC>W_&Nmld+n302PqAtMSqys88+_O=4h{l%09@D-IcDF9Wf8w4#qkmIHL0 z75aiWeIX8Z#;kpjFpR3R8th#k4DGDg+m!iz`qGnE z1nkn{MVZ*gxVOf!Q%=a&&wr!txj3}nN9r1{pdfCrGgRpwvC?rG-FU>uCCaE^^hJl2 z>1#pWqIsU8X>|00iZzdPts8N6W^g^#jY9OyiR&S9LbCT&!$fTyEwiv=`3~wDiKpId zhP}8i%9?#+*pQv>V6EG{NSnejjVR3hnbwW)$^~i8=+fi3%PzwTQEteB!zSs?-;d)F zTDNVhqfCo(1cI4}#W3w62T^%t2G)v7fh%^K?yMUj*JhAEzII`rVmHnXD;#I^%NR;d zXIaC~3Ofh7VFg%Ueg0Vnb)#RsX)8bWP2zld!&Wrs(DRsH;9ujz%Dt=lIG83e5jT8r za{UPEz`~8D&Mc0;{EM18REtI>!)G6T3$L-BkXcL^M)~fW(BEL(#Axe`Q5Tn$ULlhg ztz?!}+`=kfhC1%)iFi8|fw)1Xe`X@Qfxp?tJs3W+W;5+ZmGqp^=^NaSzqe1iq%H%M z?&~q=g~Okvs9g!v=BOT3P>zq_*+4gkZte~8YvcWvqiNdAqMlCZU5m$7Gqu#`g>T@= z!l_s`^~X1Zd&ceS^EJ{a;8k@VM>|0eA=sibda_0eFni%)t9bQ&OvMV(YB2;Ix zMHoKH2lfb3ldsOeu6I~bhBLzXkEv{E=tqr=`t`AF|Ak% zMNl%_>>x^*1al3q$w-4Q(V}?=@1CMw4V{20RQqnwbc+#6x*Z!=@8k$;$d(N5LK#mu zib#;;-tw6(2ItoMbAu$+-NB35_}!&h4XadJGEHdK6ATU!GQiLTbx)|Qr+ zbINXAa6*1$*bKh}UvWmM*m}QsAb(fL5}Z<^GBz zP%D#2m3e6R8yqvBS%P!eY!a(2u;`sF1=K!BdfjkcJmh(Sz;rp|mbolc4;AVapE)5o`3BOIVCo z+sdA~Glp1Eg}RxR2?~iDQL}3C*}S_p!Qv7xW(FlurJ}CSY8yRy=OEQr^_iG*RjV>3 z=eWdIGvT^UvXwEJ_*Wah*clc1XS~;yX2}b6N<;N`vB>#&+r%zZyUS9bM37~ z!ZTX1suY@`dq2l1=ITZAr|Ty+-LOS!kX73#k5s5X;+m6(|IM*I&RM6Zu_-O$LTNGP-Yq`td zG*BRDEs4jj)R3|NB9gcs@tHfbn@~R$O_r1i<6*KTjIf{9n6U{!u2@(v%K4Pc8xHtm z*XJw)EQ3qo_>jX%2Hm$5&6=KSJa?)2wa?6hnh7h6SwYQxiJd%Gttlbl66FD*zv%sQC@3ErAuKETN#!q@;UR7RTGx6p9Yd%6v=8~tF2XiX{MvMDqs*H!r&!gQ)rgj)UX@L z>X@;RJ9ar0>*dtQr?tHBkZ!hT5TV%DRmmna7`dM$bFeILoe&!ttKvWE_1Qeoa>RPB zcVLmRv4L|BaiIK;| z-?&;RuCWd=MEAb>+ElanI&$i)i`MGI>>_SEGCnVCel7V+2#c{_i_GgIWYXGs9q0=) zZShvMpI&SSGF=3+i@ny?xooU@%reF_A?u|#V^2o{hpQ1*kaF9>zKKpefUfuEtNG8o zB42h>$-%B>2to`=$V)L&3MlW0AD0OQo*Mo$1Ck^e6hSn7$67kxJZ`6Yzw3T2#&EgH zX1eWU_vu)uU_vC1vBfGueC18?Ca)D3rCL&fcc8f*o*}Z@uRb#j-TXPCYAqdX8ZE~JwA88qzweg< zVp&GKiYY?~FQ1t0)ef5B?P(LD$11U*Q3zsDE;WCp?<32xY=TpRN0oZiy;07V?=$Dv zW3%z{QIFjCiO_>nTGhzz+X=Tl@$1vPN#jP@(v39O}l)nFqdOxP5 z>zdVvdhBOSsmd7VQ}&HYB43z0f-R@rYmK@^JEV~Ao37Ww6ph?XFkU|_B<7}VcVAxG ziakV7y3thts>nT&GHBn4_SjSG86t_r^By;ikVUGBZfY! zzs$(-<2NH#zT&iM_vEIZww2P}&PC$I<*F%Oj_4sCL5KChO({(pE@2`` zNN1+AbGSunT&C=A*XsxtG-(e(=%*1BZDm}g&_ucPqGalVK+nA+xI)z4D)SwbNc91f zCHdD?y;g!8Q_mh1o3)xg8)`xolAkbtpr77(Ck`Rc;H>%z1RKmi!s~r|0TP@=()Rf* zPxBdQbLdKk1EK>K*3w;@duBip?&Vv}Phzjd;yqL#W@>+&OqTG|bsj7$fYkQVi$j^l zrE_prP3l9@F*)=j#ANg#$h6!2c?`MG=d_Rir%om)8}J~>ccDw`XM`A6C}+ySe>hj7 zCDop5SA*{4a~UE*0ZZN#V>YI(lE{1C!4xo;jQo5@vd| zMdW#Vj9$n1jb%Ih=OOVap5#eS)CG2{CLh6H&ozd*Nlp}=s3%|t?dC&C&YaFvp(oE@_dFk z!uXE&d!Rq1^thhA`fPcuo6p1tLESrQL2!rDR!J=f+$P zT&l^cGw0U{qmJ%=a&n%>@LagWAWB+_O>Acl@OANX~mL^R9XMrY_tTkuu? zk!O+<3#169j_CqpQ>VPkX^z#7i@nzI$v5mU3Rba;#_wN9F@(#id=*!r-~$5HAIsIw zyr%!L*6kFm(?wF<89*=shHZM~uQoBC1_q2LkK5C{7&RQMCYo-KqA~l$56~snu?6=PaX`oE>m!_# zXg+A7yO-PqTv(vHAT0v-bM@z&s|Xzcq2O2qvf2a;IvkHA zymXm6e{+|UkR@88DI?)_;pfNqXkq6*u>?qb@Vc2VOLcqk6zdr`m3OmntuT1xooq-t zpE0A7Eh}O`yt416i5+R^Q;``?yEA}VEy!yOZbIUrJczW$Y>;VYpJTEbLo{o~K1=p6}X9%$_A zJDhJ-$EQajol0LAdaWS0`-pH*|VED$bXe|Rs9z5&P*<90I zRPv{jymVyuz%YM`96%2+?7+kf7d8VyIslhn9zMM?7Q~ZlR&z^8a19?U0B~7wLBcMu z&Pv&}zSLKCmv`t4sQ%fT$0=U$q)2@Q-Lx)!u+|1^$o{jj&n!c>?~Ce_zOgSVJNWJU z_DQ=7?7!JZW9SaQz2jbOnv&0XIEcnC$U0~~R{E$MSUw%1h--cXD`9V7Mxe*#!sdA$ zn@{E6{(gpuA&*ZFJ;X!cU|?b&?v69xDlBy@dXD(5w#mFW!OEA!vPp6mu0)QFt)U`3HEBByP^c< zL#c14?z#fK19}6H#8#OgMh;bTn}Hm%J1E?$hOnm&4T26Mcwd6A5U70pgv-z=?TC&D z9B9IUBUqW+r1~_Qo|51CJ+>S&2%L^6?`D&0f4)S-!kkHY4@};ZRLTdq3ta*XaC?p3 z9d(Kq=z~JJ$!97x+U|ODD-@99q?@hpO){sAo7bm#o&?(mb(|s^4{(^it2HFpGzZ0VIV&d2N?D3lqwb1OfzgG3etZ;(=?-}=PICDfa?2!4$x{0 zl-yoXqW4YlsMf(5aQgb&ZST3jTan?_^XFmN{%d1&VUPt#}H#l#_f)kVp^{iGoQ0OG9CH)Ns~V)LSAYZx!had-mv z{rh)dzNd&bdl4qQ;2FWg=`OYwB=s_Iz9fR+q>^O=gIBv4@43YM?+7s4eA8wL=eQPcwTAwXC(-{onZSsb< ztO}EBO+asF2W$GesgT$ox69$`iXxlDiRYi0Wu# zWqWI%El}@akhB<{%T_qDf+ZVRw|(8+;>00DBRUGcKcO1Tdc4EsR4@VII#8my%lJxV z65yHfXU!ioM2V|A=eE0?f&>>p%$W8p2t6{LY2uhIU^-VBe-?^du;Q|u^}Yi9l(Qm| zzrz@qQ;(q!X`49sSwQOnjo_Vu%d-xNN+zF6%8Hd4rFCp-7(HdEY zd8kbZ{YRI~KaKoluaVNNCFYUv%K!hbY%>AJJ3aUxU{Kq)v2EKb9{laZ@EODd4uJFm zxT9>zFPz`~yHs5NTgt%d?kL*%q@?6MnDvm&fM;(nl>fvlJ zKo#KL63%UzE4#k zSzUB;avBZ0Tf9iQK)dm6m4E&Qh`FY3-*%=6Y%nZAA%bQ!;RG)?dIf9j+5mkrPf6Eu zfOGWcasB=b^dCtG4Crn+KLTL~PpxaYW+3eP=jkf9)D7UTto;7Aqs!P^bszx|mY%+_ zLAT}Pv~64aw%=d6Egvj~vuhER?~oof%n>m$tW)@gc^=6{?B&nyyPQ4bz(1FE$G88C z`9IgAkRGd{YU=8~ciKWm5Oy=@(4#CpPf|Z$er6!y)4SEdBujh$v`?)P5TT(4<_0Rn zRP!4*Zh#zyva+%-nYhZ-0N$XNE?rvlQd-3pzfeREJDGdwJyVEPoZ0%P348xM)gO6` z?syP-6vi|jqW$*aOPD)bm(76nHY~t1c=Y53-E*c^+{o4lL)RXN|8HIK=N|sGlxV6S zFvL%v4(+Vv1XYY!MP;zOSgb`D!%ByB0iR4WYD4Bx+2;8u?y&$)Z>OGY4X(YAq~@J|2BMbJp73hE?~OVRFeOPyrR_P;K^Ej1|U z2mAfBuVEkfr!VV|8rUe>v;*NoC-6T#R-bqOwyoK=EuRCv^q;=7^Nm|i*tbl^R3fk5 zxbdzV(Fm`AZwHF%H{%6_$`O7nL6uHh{Xfj9q4%7xd!*K(?KHN%pPbu$?$)a8`=mj)E8m zih&c8-JrVq=FlXRM^0Iu^O%XD-IoP)*tnTNJV(#K;MAFMU{l_8xC(qOB{`tT+*x+l z@&)LzV&T-A>9xFar3p^?%s{BDe18RP1u4^FMtX1pLs&V0bh<{9y88Qd-`^yb)IM2T zs}vCE$ur2~hF`(w;n2@oL>|aX$LcgS9frr~6hG_rmKdh_52`duHS z_p88hyx*AP;6ZV~>ay}78Gw-WiqF#*z*aV|56t9_ffP(=s=xRbJQrt~DD9BKfH~|d zcB$$2rNduhCGgO`mAP9>3;c!-C}6xn9j{0T(uaGdb_P?lmA)k?1Y`Vi-8OIZ(~~Dn z9Xe~90e_aTeQoL{5m?c1_zpsv2VsV^bAJ)$(KJ{g2phUVmqlYJk3k(oW!}Jro_c*+ zKj*adUQ7(6A&@{Sc5oRWjiW(c}ydb{ht z@>;Il1U-Fdy@U2Yzy2N#(GT}Pckc2meac03O023q=%a%cqh_cG#D%h+a|s^K@G=4! zInLdmej{Of&AS2w`}MtlU4M^E`=Avk`Mkj@*Q9)XWwsI&Hj_so+9R)xheE(6Vvx%z zI~-&&4JwhFqeEtuOwF_3r$L9OXCjCluOhZ|Kt3?erw0V z-V2N~+N*rc4~l?|AY%j)zECcPbisE#MCMw8Y?8ia;yEdB*#K#LhzV|9y?WKeWRT^< z1|G7m7M63M|EdT4j=G!Bzya|Nhm^xb%VLP)V9qgsLGGlvxj7{4DVO7clJRZ)EAZ8W zr5Qj`Nd4M_2M^T6ie3m6adL(YB3iT&SdCLoA~N59Sb#$&&u(p?EiZAzeu*8)R>f%PjvXff4%%qFoWT(L&s?{ z(3l{}@dn=qcq(n0rME1s5n3HGOIOW$08+)y>htP17qCf5N%9^uKOydgMP+}{kGi>9 z=nJ9IQoatz`Fd9vf=V@`=`4*B1*Qv5Ige1@9`nQRL-y|57cPeOTVZ<-=t980v~Xy@ zjFoQaq)~XGz2?aoW_BT%8tL>e_5}n4)NHN{z@6c~L^?wITbcwKl8{bWIe5pN+yton zXV4Z0Ewmr9#-b8El0po!3$0uD4W!_*kH+k#hyL~OEwqOZ`j=`Gb_8){Wbxg*cPGdS zf6nfiS{MqNnZa>iNHNnKp?G@A*&XUW;250`p2(m`4sqYLs9+uhO1(SJjE9@sA2N*8 z;Jmzfu+D{PUD&xT64-D+ltcoIlJybtNzknh3kw63!8pqtHXj(dBhv_!9fgGQi4~c_KQ=sATbP%+OtZO=2TFdmO9vncybcb`pr=mgW$)auWy^W1 zXZ__(Shhn?t|p&kc*xF5oeKeEIGvY9-u&fqRu#HuxBY!A!5gFPp2Dv{kaGPXD+`MR zJO+&GWLu&S2bybt!YCvBGqWZVHn)Vr@*kod=38&D%O$d z$|PI1!BmZ-Yzp9n!8Qo94w>ZO_aA~XJKP22O9%Tb^x2eM)OJ# z&Eg)mIGyKT`;*A-@T@-vY{ou5H7;=yl!49O$%sq@1TOO0s~d{ejjy zvA-_}CN!&<#V62jRon59Qs6qGWJp_ju*;>wo($7V`?>5JWE%*oOULZ41=1Aaij1Y1s~PYnsj;V=y( zhv4q^50AZX14IbWVv7HMdU~B~TJCrb@-7I8|D2tMoCZr+P#uS@FukFM@Z~fdm8EyH z-w+U|saFpP-&}x}YMR%Qkt3SMZ-Q|#0JZ?+7$ax7PURFSG+1X8hI&!-T}5 z5w4chpNF9};9_-W=-EV5&N}s2ZeKf*5T0q@WWA+3Cjo^k7E&HZ+mo9P?n-pAj-M2^ z2LH0hv!%WQ#}a8u7}0C`oAI=x>_lWz{UJSF}e5%l!wcf%+#I5$lTt<>!7GPI$A z0()Tac7@Q;&=ACnXAa+!#lY?iTl#$v?1s(y-WaPh%@zGmEbtG?Pzx_|u+Ulq{_L}7 zduH_w`w-w8)q$uc6Ix(L{gwp-L{q4Ldi0iEcTQ|{w84W1Wg#EJ?gLpu2hlRfKK+-| z_jjM63REN(`xC9_!dN%I(-)uU$*+ZSIusGPNd!Ik%vRc22b>%*aH)cgoa-xO$u(4p zPsN#^b5=`^$~2Aj^F9BWLgkQ&U=n_{^vf0M)e#$@JXGq|L!@QZHhpywdocEy%D!em z@}!)4U$fg-BCMox)@_Y0;g>>WhM`GL**Fb0LKq^hv$r3XmX_|*5TN>k`vnx37F%UT zgaH&vzm^z$P#y*o!a=A`xd7Ibp_9J9IHXNJBmvf4D;hC^#cEx$0XdoP{6Av8#AsF~ z(GtWh3C@3IZzkUnP#`OSzIfVK=w`OV$pSQ2D|VKnM^`~d`{&P}kRh+HvKTC2A)0D| zW0u?fdVI*V*ojTD#C_3X!(1VtI{|$fG6CnApqxN!8uqqc&xF|H@g4$?h^J8LhF^QG z%=CeFJu@e#aC%!>1QI1-`-<}Iw#nf!aJ{AUj5{zO9$L=9|Gu=+qJ|6w&_T;eMZR#sWNZ*O55 ztWJ0R0#cNgNgX2kl(q$+)f}y3v$L?tIMe$8p<0+lylUYieUUo<4-kCJFW@O;KSIW+ zSB3$o2?H`WP^uLL&Q#v8m%4sfK4SVDj-01gKZPw)VjEa5weQJ+vA=Yy?9TDWsYRio zT5ze=iB}NWHs4;u@6kN5UzFB`oVHcA|K~vMS;7w2{adJVI|pqOgU?LE;Z2Mcn12zN zt6|UUD28BEx1_J9XZ88%HQNp{wj_d^LIU>Wty{NXVB6q`ftDx;`+DI8!BlOp>B%u< z;pB8O)46{YLU(mIHw8OfVD>)szEvp=*$%*EK(=XutO|N9p^n0J=unD!QKsB09)uEv zIgk*1vr8eK;PYSyLSR25`xVuYkrHQ)L{Ij^lIll=Z{C5I35!E#FQbrk3pS+ao#@TsHv7My&LQaN%QVP<~YDOn8L``d%l^)Phmyfk3^`(>W* zI5;}PpUW1B_yRfO=@FY(?U4GFR&7|8}7~YYDd9Qd^rtAJ0H$U04iUX zRRX)OL%k%3h@^+GOTGID;{S1eyvGmx&SdLYMh$Xq9@mJ2s6Zs?$Qg*N`&H{>rjxn> zYro!L$M^o$CMM)xQyegkAn(lxq@{bUJC*akGZiFsX>(+o{2f#3%=|n8h6~bQXcjtc z=C|AhX>eB-oOm5FjkJ`(q3cUyBOF5VTAX+^@TLM8*xKQSV9UF~@wFtR`YqJQOJVzf zR*7t=algCt(uxGx&d+#fT1?OYm^`SlRCvx`tGhqlX;^kADN6vrRtWivM2&pF`j`HL zIZ&ISL!Yv_kvXXvD_Nu_or2WogW!!wAnapeO3(lK)6QraNRYr71Z)B7Hn5&<&{y7@ zf;hr9>8auN#&tY6@_f6Uq5s|}R@^%7ED+oImlYUwXR~)md`7f%a?)afOt}naT{VdK z?RBs7iTed@nehJB3|^@uB7H(SZy6v{E-#wWMmY8XCE%T zJOUn8cHkg1cwiYNd|)@UHb))a&w94j&g@It%KQl8?Ad(SyOvzf?E;XY_}j;v^HAo3 zdW|#dbj6!PsV|aH22UkFLJTvasse9xYQ|0`g_Yf)C`%{(n$Y{ACk<65KmfgL1eO!h zhR>y&Rj*vxljz5m+|_TSOS7pc5|e!0fATUg91a{gA`QhSBQTBgi5)enbby`4tqW#? z&NQb14Icl4faP#dgGs-k#FepjiXmZhbp$Uqw%lVDZ7&mi$J5h53{HcUnTqW@OUcb6DWb|o+ zIf(k<0!C#<}d0cGs_8XZDjzN7g_b0P_vgf6dQwY%}24mNxC*fPx=Y zp-)CwT1e;)m34v!e*yy*^v!R1OF5AgX^UzYaBSLCuyrOf1mf2xya!oG0Z&3)rpC9s6_?* zdF20!lU~}y7~BE4dSXhDOu6tU@sora;XmSB|9tKL#?WcTT=2Owh~rsQww>gqm03;e<@R%`ILYy-Tv(k zFi+vX9^Qgd65IyB4J68iA1V_gv|HUq6ZC<5okBw|%>A9)7&lhugJ@yWf5WdsxfN*{ znBcarFfGFRcma{;Wctrwdh1*N3-rGA^FQ^8KSR1zZleACPetP2kUH(h525_=AILoI z$J_ou|4=0Q|Ef#TuKc^y@ptK>a~{ufyNZmkOt^L})>p{rqo?suRB zr@+=f>1{+%yrzdo-8lv}=aJ{u24y7-{Dw^K2p&KFAJRMP`qKsN=7X|L3CG`b#tQN2pb!H+(N%yl7E-LZ!|f za&rTUt=33TGhe=!fs=awCdMSp9|OjHrXvVf`m4`EYkb_?Ho^Mmx8eEkq9N_O@|l26 zPu3XQsPs^LAR~5rk*W^KCYk+>1Jy~~z{usbaC%^!uzOO}M1`Exkpbz>{Q-{w9vDFQ z>=NKVc@c&BIM4IAf?xO}a)$Z`b<7A$C{=YGG;rs}}b6xBgExD~E({+fY_P|FS(^!Br8zgxLPR znaVlt`2Vo?=3zCi?cca<$QH3lXfh=!35}X8qNGxqRWdcF0Sz=+NFpUsX((JEkH2+1qj1E6;h^z0q{PJc>0J|gcBMn=d&*Gewgyt+I7v-KC3dlDd$5xI z!Gj0EFaB#gn7jnzBQHo-Q@k&D`d4+3tG07`m|r_{o3e}Em1ZB=dhLy>kGn{;#3+T# zCLWe<^PIy$#jIUnS1Mb3X_wjaPg-XyqpzF|W;Acx_H3D)SnC-1XwkAC+}I3a^Cf=V zYDO&9oZW``eSL+ezbGk1x!X~my_xU7x#IQNF9+TG{JUlvjx!#0++oXUB?-9YuC^Cp z7x^x(pVsN;^?b9e_<(}K_(Zn3#v=b!FX$HfL)32*o=?3?OC}%ccfbF+)~a8ZqBJ@v zQ;?-=PEOh^LI{c^5YB#*f6p`9TBI=82>6w|AZzpBH*W%@6VV2pS#QS17*N7 zwORdN!uqq1k6CJpg6kv1y^NcK<34%8x9Q)R^^e~vAV;~2A`e#bZ|Cxl2V#8c zJ^qU)`^OgpmiL0K6YetBO>m+{gEeIILxQ0}C`0`#gHQzyp_V0_P8O`{AaL9j3 z5k}rcaF>w(n0k%XlZ^)PV$+}hS5W*4Zf;x|j-SfvKew7miu-4VmUyWjN6D>$|9Yzb zH_D z3=PuiN@3V&SJu#L@essTmaVDLrIw~p;<1MUeT7A zK0I&HRE%k8%aITIGeQY*e--*@3}9$&<^g2-5iFuj%I?uFxGmw7+zQ8IMsuERc)Bel zM$Y2Y@^V$X?PP|#tmOCM;oxw$GiMqz^9|PW@qq`~;e>FdA&?~3QX58_kfhYBCeupG zxeBLyxiO+0#3G55Rl+}pngWX}`}Bz^O@g~Sv7J6-nZ7s>Q&fF;gD#K&*8{GjvG?CT zmh4Axj>|V0I!LdUjlk0C^Cy_Rhe(heP+uxe(S z3{c1n13Lz+aZSX>UAq=l`VOaMf?7|@%gZ%i$&k=92SqjkrgUt6MhLA%02or#3vsRA z9heeQpu?LyR4@t3#3U}3F8_lWnhEiC9DU&G=HmNg=2_kC4xMV!3M>m&9634wktw*z z-yN)^*7Z{hej^_GbAtWE$Pwp#OrD-04TfLkZ`28g`rHZ3o|>vCFw^ns%^T$5@87@o z_a}p81`;5=?!)D4*V-WF0@w=zHXc|SEWO15RD_OQ0!SQPX@Hlxq~Lfin3Djr^504|?(I~&1}!}jE(7DU#2^b~|FJbjx+x-jRO zyKk&9(`18F~5Rvm;v{>W*HC>zyjcD*M5?Q-h)+-KWhnxiI2~k zV&Y%#y9N>o zoDiC_#6n4@`j?xILx)%i40fLhMvu}u6SqP?rk{o^^@S_tk}oXcl`(za0nx(UaJ4XI zk#P6>uTe_;NbVCmKtqAX7$7l?lFl5e`mOA$aIY%&nD1$Nky_n_E@t?#T-?sT)s_Yk zIU^QB%{vtVwEG>y$ftMj-l5_O<-LxsyAd)!A2nSDn_2igSMkPthom`7g3O6CHj3iQ zNR$s>E1-atRLbmY%I*T52A6yC%;epA#K7mk+fRXpCVK!dx`PX*a{y8U;Eb?`7@ z8goAFHXu98`p0JF6>=?Ipi&_t7J9D0@B`4l!WJ`B3j>c~@sC5b5xmJL^@vdBiBot; z8~2%ie7hxd<^x=@C*Dl4;+z{JZ^ydS8=r1IKA*yDX*3tO)AYu=Qg7)I^TVP$P|`jk zX$-Sn_48qULt+`7e$Icxb8hm8RDOEC^QVS=#YQIp_*m=i-u)CjSSrMo@yY>6pMg%| z<&!7vX!-Bxq-f#Z;6G_=k&}Sg&w#KF#qPcWq?)tRvJV;qZGsTf^3Iu47o!XM13FgY)P_N)oct!D>K6Vl`puhqlD2n_P16k}b*zS0XK!sjtnMcWN)2D-WBg|f%?4^& z4B(>vjFa$F3?7=nqq zCm|C|PgHP_tMoZSg0jB&)(-1EnNBaFrhC$^a z_1^{HAig^vXVbMg@EAxO59SeqnI0gt z_&zq?#f!HBXeJH=k%MP|BO_SCfGMn-bfdxtKyCRu9NRCKz;X-hewoO@1K2*HQh>x@ z0#{h$zru~FzC-|!vVxVl8SZ4 zAl0#+xVwn{%~Nnye_iE#_Sgps?raBE2%$g*uwNH<{bj~ZKl|GFD@RrpL+GsAhuXo6 zgy}21vd)3tqwgNgl3v_gDw%ery8eg(hCWnQT@KC*9ZsV=sHs(0P&|~5;^=LI^ugy1 zjvkwsIZXGyW(n;UdUp*UwBQiVYzCQ*pch@h!i;<@%FNF(y#px@q3N^Y$Fge?E~ zak)8RPU6(vou~R#JnI{FA6Lxen6Sy8BdIf=*;~tS`BZskOk{DVY(R1Ik1i5cgk>)l zGSgMmvTc)nd8~C)+enravff@v*YBSrYlS{iY|Bb(()2ga_se-k!p&+N)@L{Dr>5>c ziA@sq#eDUrYiu1<7)?uU8Em@AbO)r_V3SIJ**8p0jPIcALpVh0(^GkVfhtS!*s57! zEXKK<=&w`-`U&Mqa>IxPbB>_&I^x zty8VH`DlEptl3Pwt2w#U23t2^*?V)=KYj65UON9Qkk=naFAKxK;_1_;Z}x>^>wx-D znVXW&7zKC@*Mc$kEbD?S)o}|~LjxEt_V2&$r2^$?$~8lEt7TThRFGF&R4R||M&=HH zTIcTSo#U*En_iN@2t}@ZQ*UFTE!sxH=3#LE5QaPKF*P+s&7*R9);k4yJH;qNdbzuu zs%&vf)pn~Svbw<>)z`;!4w-~9yJ98mXNv3J8df~7my_+xojpJ?bIH=@4a-=@X!(OpgJaKpL>KJ> zCTDg6C7A2eE!OUcy6Z>O{a51q8ah;IvwkUY=FSyX6gi>ST|h^euj2v4ChGT=irB4=#Mp8xp~|z z*T1#7+4c7BD^fO(q~wFalrd_FKS_M?BWuoeITp7tV_V*K=Z@^DS>Mi8xx4| zFJ)NoC{9Xfz78B{M6|rEuf|pK`mE5^ z^=y+S3MQq$Emd`yALQG-bQ^qUS3x#W(J(}D> zj+HiJ+K6~42~A|5H2kAIrJ2P6i-&z$q5ZG6=+lC^V-~I#dBn`saA&YprFtYpJ2SE^ zSP9J-%($fS-fV*Rx2{)afvWYTE@vn+bmdkpYj+iwb?b&lEo3$$B+>PI>*;}y<=M0$4I!eKsdjLYh+{{9z7O{4nwLuq-*McVTwQO$pesL;8ozWw-aA&_v7jmxY9HW^Q0K&Pv(&S0hsVAflBW%>Kv ze}f&ISm@bJx&|*vr1$R2aZPXZl_@jn7a?zGiH5&wor}^!^dMPW82j~@lb(HZ7NMUu zC?;PY`D0XyXuM|d{6^2NI)Oy<0;l8PM&O5NLybW+XO}Le>O$;+f0#B^w4?k(eui`| z5u9Wj0+G?n8+iPt{VVXOKre&B@H_AoxuagPs9R6Bx$LpKZ6h{EyQK{(GmvWg`*ASq zVk&j-b-$#z>}r#$PD)%{T#{O-LgnZBl$$DU3ZNJ^XUWsLC|J=O-F&N3nyc#xNg^1I zpvQ#jp|Uj7rim$Pik%l6h*9P-MX-WI0f64A>^0Z+v-C65XGoO%IL;7=EY^9Vw>iOq zS#h)f2`HHFmF%K1FCC^q|$e z9+1dz!BxPPu<=mQ87Qyx1T2ukouiU?sV&D!8@&S(R_1Md1C!HjTsC-F;>r7UA@}^$ za_^3sr|=D`GpaQPuC%4@`I&Q|yNMfa10_pnaGyNGa@^FrQB+hbtPhSUZGq}bkX-)G z%9<6%43+W8L+%Mtr(u@^M_4D+(~mNm7dcum;DNyw%@!Y`V+wRyYQjPkWpm{>2uk;! zU>2dH54H7N`7*~l&he`~BpADI+VWXcMPPr?4>(MoZ~_4hnd$^;y_ZNE6#I%XJ%q}o z({UT9@HjSkdHJ_)U*ro;Lm$%#8H3OgbbtE4F$^^R*}A8TAp&i8UPoyTH>O3JOU0iG zz5K*74Rqk=rtCeoW<8WE#3sgNUx4919#$M4Wl6d^R8$wXgVZc}(F1zA&H;0?2$aG6i7&lnN7>eT|uMdEB~rY;ns7y(MZ;q1tqEaCo_HvvJPx z*HztWC<)#P5nIDQHTO&YY%NdsM-a%_>2q zdrS20X{8$zs)GH6E;cs3;Fjx!Y}sgyn+@k;6 z3{f}`m}2eMgR= zgUGfK?DWvW`T6?#Zs&XZ?%jK4$6j1aI62_wsC~fKn(s)fEQx}7QEH&K=}EghW%;li zqd)XgwAtE^wPrh;753;}53{ztgBc`Kh|5|(Bd!O;Skk}L9z@+U3H_ZoMXdSGNqpu% zWfF6+1OD^70KQ*1G$z1&-g&NzA>Gr=z+~{r{n8nGvDjpNwM`nkDtHv2Pq(`$`vyq% zzej&*{2O=k@8A4;lPxoA5<$VXoGvg0%KQh5^Y35mVYqxNyNp)pAz!<7`-JDzhx_dp zA5Nr?a<9$T|LWEG1Ca+%=}m)D04N(cC%;q#0O{%53#(nrO!g1$U!o!omOxng<4fZM z{_9JN^iUpLfQM_XhQ|B9VA9`4EFvcjH4n=$+}4icl)$p@^Yvzq-RG> zAvKKe&QpYlvu{QuuFghPk*%;d4#N(85~kITc#c58TNDjj;#eM$QG3Q#%tok090ov7o*! zU^Man56%NmM(>Vyl%0mSPpkQ-%Y&##q{0ZeEty4Y&J~;N8FBgHX(B46|M+A>AAWWq z5mnhNP%BmdNY4dgoe|5xg@xJs?bjSFp0B3!n2wbLws(ih^nNPmNp?O-`2J>lw9WZD zj9?M@UXCFxC`d#9afk&8Y7y@*34>|%%sKLiROi*+*Ozho8fY|gdcQi~)ODOZ$%vOU zV-^jW6YzA%m!|*(etb7jA5|w-5(sE3j0Oi;fO!W0^rCJqE>Pg=8}mXKS2glJQfca< z{rSbR7%oOf;KggbdGpijH2p+ECp zazun&|HH+V^)C{J4Zq;4_MHj`1dPAkz(@h4b$=Q|v%|G~xzy3e7pIYT)QLDo%j7JA zWwH_{rSri5@arWIGy&?au)8+jq=!OtZOSy6YrGuFYpYkO9L9pEnyi3WwtCY7oKet= z1YYJlJ_cFt^-V^3)vr#zd-z*HWi97HYPCV|Z;AZG*t^MPMm)jQ|HUmu2G9suG~~g1 zaCIQ)|AtOh^F3gG+WYrA+c)7or{9MV1ZV4_iA6n~gNkPQQ<^pVVXfaoaaO{d_@dnj zKUgAR2qU+dALyb)hm~S9D zmC?pWY(-6MF7?6-_y?-ya#W>5w#ZTK&=9);Frqw-D5OHS*7mKzWdypkbdzCVRlNYk z{S-dpo#HW-sQcJcUe3_{h5&pEJMGBn1B=*65Ip&>LtwQ>Tg~a-zgcyOZF(VuF$`(q z=~U>AB|6xI4RLEQa&t<;e6;FWnZZ5>DzKOfPE4)RZMgv$8gM)hTvAD zC=~o*dGYx1=&K2+7!zmt-WIHD1-R>Td$a8dV}D28FxwXNXi$2o+V&$K0Zdr#R=tS< zXdgf3!9}1nl&1SMe(%lh&U~QsaYu9&WMjY96`r=wofi~epXSIe*~4aUZ$IDS5$9hU z-;eV$7iSo8Bc5(2mb$x3{NU1TV9fwHYvWXq0-+i#yqEtIXR00};4DA_^!ZZAUg19v z^rqn0GghI^MtQwmEFGPL;>3fGCL;F^kY>$(Swu0SZ7eTE-y^FLC5Kimu}aE%#T++R zSFSlY%-rgeHH8j5$A5bs!=fK(u`khlk3g?QtG3I*sECDA0z5M3D4Jawy|%p(VBV}* zvve!qTGa7XV5##AXGJbW%&DGOcmjNRq;KQ_pbUSLYE~Ys;~)8?rtBP9G65guoATTR zD+n6|YHc5NSHSNO)HcB(<>It}S4QU=Pr+=<%e9BPW3PwTnJFw+#hRnd)ST6eXCbL_ zeCX3@)Z?~prdx~;V+upMUPd#ZHytk@xWL?jdm!u~X$I#(EPVteU%fzEkQ#Eb{W(FJ z97{GY7;g$;O0QdYu^Q=(IW~6@F;5 zl8*0b>BUUI)X*Mbz4Vaud^Fli>8K|l(WWZ5%5wa*d;N25!2N~i`N5g5AD|`l!}YmY z8@+RuP+8?*ZvbCex%(b{kyo9cEg~p*c)`DXTzaiGV)7wQN1oi@Xq{7k6x1M-n)M*6F_r!S&-z1%18q5tbkbxafD--Vcl$1!ezL>HM&pAD=4Ld6l^)#N;#54Rd>7FxEMP zPX}UYp1L)xMZZft(|5Wm`VeNHKzuspBt54P4h=qiG84iQ% zzVQuOY=kdof6N7yr^wqVVlu|DC9g#K3=uipkNzAK7eUe)AS7i;{&!+qzX8=I`pnz- z{DT#_fGc43k$b=H9#DT;YoS!12b^~rXBc8Z`{(QWUKnN|KSeV#=Q|s>q}<-mlq-w2 zj~oH3f#X<1mn2K-rzUP-(m{CFTn`S{)+Mry6u9m=Dkg8d#&UOoUO{8d#psO}ZqMg( z(}^h>D$C&p=Z7yZWb6-w>PCQLYt1VZ#e`p1ga5;ID=EUF+Zk@}dgct#w6m;&*9Un$ zSYi|@`zT==?7(jdg)-r5(IzoQOt|RvXI8CRC4F9c!v;%iO*(c^_+Wp!Xkqt43d z@m_WIZd-=P@APa$#-s^WYKSvJFNw3+=whNf(OMA0GW#M$wiZ-x@D-8i^R;|jUY>?n znw(Tv_Mnvy;0Hbyzz+duGhs>2v40yivx5oS6F~@VXtC*`5J}Wa-y~_Q%2!Fy`T_(@ z^GYo87*D-|w!t*-swhOlKhD!1jR<;$$>Ln}^%UW7BIl8k{Fgs~Z3^gb^uL7!a=7Dz z;+|ZFJikkFHM{HY4n+B+obkjFFyFqDfn-EK0SvNm-VAet5+BcGh5e&!{Lw)*PoLH| z1R0}1k9Bt88K2Wtno!ki`S8h;T`dE(B+UNcbgHigF?Q>a>)ys*N-icdgr7o<*K`R_ z=s7M)_+bE_1u2!{P}!u_PsK&nQ0yu|2tgt-EJDW75?TRlO9_vmcF)A_Yu$)dy~j40 zo~^my>(>{n>XO;>MlJXv8c6V3#F?BrCq;79ap&jaqqM{<)hUJ``wD$G^xLAq@YgO@F z%K@cbzi>nc&1Pu-&=9Ul23H48)1a-*#0P=X?}k!wQ<@2Ms@&U#JLH6m^m}s$xco0G=`3qIcWYx-mo}LNUJa#X0;ISzG0f72L zK7iT)iv&_5r;+}neK{He0@?Hd_Npt3O^8R~xhXYj0=Bp7;l~H;ZJ;B1&LiY>4j?bC zUU!9MM`{IW06bt zy?auTOUK?4;r|XIb4)*+)8GjGNHJ4iAW@1Ksr4qNN()16ca3%-u&a8ay7yI#q1{#T z@Yk<`23hMO6QLp6ux;A`18sq?RJ^~qoA1Rs)$YefVCXF)w@9u_KTUS|ZIxBl`#Zjgs0@+cRO*Tsj|n#7p=-Fpp9- zDG}|`(wozAj2ZJ8E}%mJehv){C6M7C#J`Am47C6se>UJU%Y%{IP9B5dg?MZZmoU&m z1mc0f`)NxtPzQyIR`u~^)3X=jK@e)m_M%f0Vf;q>gDrV^>)WCS55RK>joANT_qI4= zX2eqxvNWB~{;GH1hd`Jg{p}>nv4lylxPCb<=(ptv?w5tUFPAc2>%oSFEtTTM@rg!ltbV`+oPl@ix!|MQ|??XP>-lj`;JZ@I}F7I`p~l zi!)U52ni9mhiU^HeXRFpp<5iOHrz-7K~`Nm`-p`DIA99rl9S14PrQ&zC5ppkPg$C$ z2s?+8{>1>>#JgZH;1LZL`NO({AgoRx4FbGf@+APyFP{^hbeyP552C8Xu9tR1C`tAJ z+6$O~ZY^WV;R+G^(Ir<{ZKWTkNvoF^gs^d{tUjY~<&+B@~g39PT~! zf=!xu`1ih=_j1c$7w^+Ek_lrf)B{TSPYb%fQjrpP<2>x!Vo%r%49k`>fz5xAQ$t0b zGhu_T(_e2E8pelLBJ9bm*L;2Bz4=n#W2IEHlzV92ZGMe?6%MaR3_6(47{#^5i7|>$ z3c++7A*aS1@q=XuyX!or&2RV(R7!if4sPhXv{sugX1w%UPjvZiuh20It{hPb?+S-3 zG#wm8FtdUw+|MQ+kLJs4OP?xBn#WLIi+*v+7C%O4!DU0`<$T7Q>mMW3U5N0|LCUt_ zu##Z!5LHJ^!gry!b>bxqBu##YaSJc6iAFm1!3gr>Y;bn@m5&9-5il2nxu!mZNNvfh z{X~He6^3{0=W}Y(ALKS37I{Ah6J*}pAD-GuT9^Wa87$3@+JdULC2#_m0A zU`80&NXG_gd>C9LhJKy+RC-O4=%f-@8i|&C))kR^_%&;L4|7kVdg1KFcx$%p$S8qX z=vx<++2;18tQ32lZi0(2SiuNJcmQ?lqm;Ne7o1RU%Zd{h1F+FHYgrni-A@sT-=GhwA-d>RX2y1Wz%PA~;%kc)`x>n78EFLva0(0R4JSC5V z!}b6w8bUKCaEXVvc?n;)Fn8ZETo0wKlbyg`Y!JAP5Dl#yEg|w{z3-!dswqL!a21<< zQmUKr?;{r4mIq!QeTVD9>d!0NkhqUqC_X@~-5{v$+^t7wsP}sT(r{cHx=^ejQ0?@d z*M_MV02bU~;|70iYTCiR>)JvgPHX`U*CF6CQc7JFq;qAgZq~C1X$PH35Q4DyMOiT{ z#=IA7+1GPhFSJ;}5hzyTixJq3;|FCFEkGUrz*#o_M;OpwR}09)hOn(#4vt#MTh^~v zN;@b#mpkCbCsozEdGh8)$eyVfo z%#Lx{T$FsS`6yLB?_RY{xSw8%D;Vlc;YPO&3a{S3zpd_x`bWgxT* z&MVd61dwSySJxR*iO4x8=#ebIb|ySvh2J|plFN2}B18HUL0(T|u^?=IX@erLeO~2d z->E`;-nwe+C(j8$j@St%T&YY(31tYf6Y5G)&f1zbYDY^ z+fN@o`oEkPlYoxtN$}!c6)O`>4dz(^$>B9wW8l3QLc#JUh@we;j73O1DBrxIaBhi* zFWUX~r@eu2Q4#rbzfd>)1wXG|2vp%zN9oKttVJl8A{StO#AW))5Pf5b~1`>g7|Br_J|BZ(HCjc5sr<6XY?A2LOPQ22?i|KY-M^Ip%tet?=e$lF5w;b>Yp zc_#j;E%@QQa7ezjp85O|!PP(h^LH2i>UTMyR%3KsDLy~_Rfd1XEF+*(YOWl${$k(YQ=Oy>+$aZDE%bj>KePy*4{oQi~-TLd6cdIx!7Qg>K4I%94`O`%>wf2wzD$SgJ z2#A7h(!}w@q&jCJd)#Y&8)ghipBo^78(qts>K1ta;j~g6>k5g7^z<+HS{I|~ZML)R zwE94Hk{QPrn6}9-AEd6r{r*n^0HFxW3x1U4f%k)TICS8^ z0j0BEVi>@pi_+j7<&$l{zmL!5{_#n}5)xU5&@eGZyC`w7v4qk{fcWckZ82Zu0MOjq zm5SuXlH^o;pvR;_R@7LB2Rdg|F?rs1{ke}^&u2*UeVy)UA83Oy<`( zHa&m#>>1K*8Bw{%r$r-;L`o`tb`)T2KoC?lJDK#%)0U^0Ja=P|RgnARZcpFK)o`v> zy~MSPB}=+6k6>97e>~$yu&=T{W+Pw}>OU62IY*4{AYvV+9Hx^gvBaPK>(>D~Vdg6k z{7+Wb2sI%zZk%;_D9wS8RI4M7lM~{Pt+Kk{dcY$z*$8Zaq=0}(%7+ls<_59kQaQ)& z{b`SAFNlg8@lV#z5%jS6;QiIAiRzIm{GKdqh$iWP#1Z*hI`2VnP6o8yMOW8k4@7F; z_~(f8(9dv+nIBlO1}&dTk}<$m<!O zu+AqM%_`>#VzyKsq2tZs+64~H?CIsjOC?W!*q!m%_{WKxELP z7tXp^{6L$Cl`-4P74w4Zx*?kN>hjISsGsX*a7mwvAY){h)!Rt16H}gvy2T$$1KOeH zZn(zgsuz0}X!?2NJy}1yyh+%&K*!k}*I7$w%}Sth$m?3nrvxDO0W`VwcR?NmK7S8_ z)O3sAQSTg!XFeQRkAcR7-A*tk%tZ}aVz@PN#vIF+pGLQYhcvjM*4EolIZ`PukR=J= ztDja}sv$7Y)9XBQtM!n_^Yz;|(bkv3^-E+<>Tu)|4lL(Yg>%5*obGMh>0dz*Z(Www z>muj$%$DJEJXE{a6;~(pv!UZb;N=N!Zq`z7A)|(%*KzG>H6mB=95a}@Da*GW=!#ogoc zjKAb;F1W2b9}foe<;FY2m=Od;K@4tO;26M<+nKl|tu+>*Z$vsA|B)dXFS4`rPwf{} z-H7eUfx=mq1^qj~zhN}PY9U+J%xdmj$H)h=1s?Ns#Yr^wY0az*gBTO0+VW@k+_@(0 zIR4qV#7l!Vz6NY(>GFZ%(b!EvvN>U31%Zc>3jcjDZK~y@@Qm3VE2&Xvz2h zah^MOuIyc}l(l>l4$xC=N3<|_uU8v(yoH;pA){Frk24^$FSviW7Er8r_wVLO%o{~& z(?BTp_%sApbyK&Gt3?HZ;!XaBJv@{pY0fx(086t0k`351K!BMLPL{D)fB!{nOMH^{ zsK@OFA5>@i$Z|8-lwQ0J_|@*kuYz~;(E2DTZnUP*h51k+w6(RJTJ{mBIeb|JJcxav zwqMzQH;?0&F>LXcUy$tPtR|-(L?lyo-y}TcM9`7sO)9|EWyqbvH5D~`2`Q7}Dk5H! z2-B-cg+y%uw`4j31Q9p8Q-=S8au9jtwiD3{By+O>_ktI2A(p0fg1^Anb*(fUHFV&6 zgnnr|!xz_;V~wLV( z2oe!I!+@ELl7SDwda<7I=raR25#D_8)H)SqfgJSf!fjX(EZPs=96-hcUW zIKxoFa0qL?+9A}+3vm8dm4&vk4YkCszuPP4aJGM!wL|kug?>~;-CGR`m-}oTzo@K{ zrPPt<+V-#yQwG%fOnR3Yc1&+(Y_s{sVekho($`OV}Ow{RyP*NwU zqV(jahE1<#!~rzcy@6Vd`xVIPS9(hcE;;`WNT^cUcUXzIr0jTt07>&9L}kmCEeT<- zgr30(A?$box}_p4;=sJvt%A%qXK^4kp8{tw?`k@Xt~Je|P7^waWYq@`9?KQwesuaJ2QahKXSaewK+mXP3qpq<+`BlqFeY{)vY$Q8s?Tr*6w?i z{Dh`%my_WWqw8pr^wr)qY&(um6q7%2 z0LRSnKlwaQ%oUM8yG*?bUk3va=$T-WPX2}IGXJ_qNUQkn1|<0{9bmB zy&B)4o5T5G)(;nw+D7D{!-_1Jk#QjNn99HkKe_|{gebibZNYJ*fdns1A!Gtxm6~}r z1{jVFLQOH43}P10ag4x14(THgXK)f`cwJ@vn@!@Fge||db%s6mYBN(} z6C)F48Yp<2GG)0qvBgsjGPDpD`9wiLnddVFt=tCYo3_&R39Te3kur%C?t}GfvV=l& zJs~uW(`&3f&+Rnlm3{8UrOW7Iyn%8uf(p6SG_hvEp&ObD{O0ES6nH@W>8P1@gi8+3 z_Fib-a~`|~W%F1t+V&`%nh@9&$mOyT&z$dB)A*~mK0nCux$W4qp`b^1OHk=sS~p|I z>3O=hCpOM1NWvGn#!4GjkP3yiCS{9I0LiAN^~z_>)Hj3AA`=_CC=d`^*T08iOR1&S z*zh*Y^($K&Y3vPy;x+qpKNEFr)H-#u8N11-W8~{7w-S!k{pZp%T zh%vTtETqWLZ6&$1%Eh2MyJPky)%;_(z9g`4 z5ka!ZA64fH6y@@VF#&*vqb#^grb9dfrzcSf=s2M4t?W7G8XIW5lNtiAH>^-bxXiej zZONK^ixP213HzCz)vIOlELyX=&)+J(r8R4VuMnyzcPK_uPNi)Y%4#LmJ-Kf)fXwM8 zs4+qC)h;(jB;%F@Iu&FXoQS)iO4ixJtAi&68t~h%_6@E+h-C0)IlKxiN!$|FfeY+# zt_d4t9`n+4!@dmB^b6qVC|S_q*B@iW4?X9$ukM`1vY=Ys>CoLH z=ilf<6t^j2tRB&#JY%P^60Ewl$XfHQO6q+PFIhIf19EWir+gWxe)Z9>SaC!yFIaKd zgk4-*YC1t+2as0OsHd<9A=L9d>X6D#a$<(%X~!iF9i?kLX@Rp2nk_MGosDydFFJt;`Uq2M`f5UR$C$0F;N(Fai5(yU{3;oy$_v@wCJyO}~F zZ|CLZ4UAx_N%32=1Xb(R8rHR55sH}w%iN|6q5+*#C!uI;-R?GvrV`NPn4+3ul94zP zJ)r8AqLZ>D@?`V;z8q++#FtpgRVP=6S#z~zv0Lgw*Jrg{eE-K%gtACgG6^|=^*q0| z1>>5kIm@~Hc5rz+Zj3&@vtWD6gczGW7qec0tIg3!(utpwsGMLJVIU?>8VJ|bi3Y?sOy@8 zr8}%HV zM8KsfpLp@^5x|$b$m&}F-fI( z)@t}{L1sY{ucBeAvF*xl@)<HuVO-03lo-ZUSz-*rUL+EM;abDqsBr4qavFI1puFsP^h0xML zLTV|!*c;RAOXZO9Q%CaB3*X2TZoH4SSvx$lp`KKp!wmu~@rY}K9(yB>KPY)0Ob6W~ zq~aSDGML08{PH+iH6GzhBy4WOKUOQ;DKG4q;%(NC!@s*wX3o{Xi2(?z&D79v!TOg` z*?V$g%&F%n*AnsVkRaJQE6df4bOG8Rx*x3Of?jqREzTo75Ms6oXaBK(5%()4j}4y0 zpjp*GvWRw~8al9!FU#vy(I@`Vt8bN)OmoLRFM6QzO9J~&d9|%M(oSJIkvI#*FTFj} z?nm@+$$D3|K~y2aZ7vh3aTVTZq)=EBBNDJYH8EoXoiGN2I?fY6-k>JSA5}G!xG&tY zzD)Pjdb!BDttQWlMmxhD)qw)tsqpvvvPw;mnVmvjxL`s2uINm|DcMwMrplhJV5Omx zt(DHDYmo}yl2%OmO=dSMqH94XoN@b3;HA)SR0sq_3)Wf5)%7QSJz}zb01^63l3Ukr z%M^n@f6>#tzWTmO^>OElt0$jt%XX_gTH#V5-F0pr--XdHA=yV16#rnqJ&)frHgCjmGbb6e|<#` zWZ!kgiH}ewTrDhgTg-m4dP}W(Qm*9@G#Y30ITGum^DHB*4r_m^_*g5Li8fw*m8D+w zqsOm5FhV1vyB{6wZb@K-CURD82&0NWjy=82Dk=N>L#rgQrUQ;lIV9mWctdEh+)Vs{ z3LDpR(gaO|JX(I(a)p63Z=U0k+BHQ;w23nE9Jg3j;lEjC&0Qthf^3^6(cxMN+wHO? z6W_^9shgBHq`DHvL$OuyHClv}KmsgJWYCxU?pWX9>{<&ues^6jBwT&qgmOH|!SiwwxOscyWzcE0~F5hdfzRs?J z>*|c0WtF?k3{*B;lJt4@d-jFjC&YG*C|;x=pDV4!jJR<_K}v|;7*iuACKk7`xL<02 z!bb}2OblPZXDK?JZu!0DU~IeB*e*9ePAghKxc*6cwwm*|KKtFlclJv?A&~=4Nj+#D zt+`7s=3;DRKA&&VF%{>!e}3x_6?FWdGLhy2|8gz6yqF{^EM-+yll3p^>m7kn#NL4V z=bH>R?+Fy9T%4RWb=~OrL`6m88PaRlUa*rDOguX=2E;vaMV^TKn%efG*gx)*6JIzq zta3fFe8>X3eEJZMqO=v9pD6}+^Dp8Q`)1qab{(*uyu8bcZ%aolf}K6{9;2ax#_>MK z;6qhEE-o%fT+#=Ql@r-PK|zIuvdrUS>FMc&MIax*o802Ls)fXgQB^I6xO<)_!tNgx z#8i;9D^SehJW$|37IFvNFYfFItQXFj<%vLpr169?7B{#i zZj!{xlso!(b{pGgN{Tmn_jg0e6Jn}`JB_wN=u_-!XJ_Z?I)=^=c#(g$F4 z3ArJUjD4oHWa`aJUTaf0tkW)E+16-SZ;`ib&)7G~N{5CGmF}8x;_)_4j9ZHpm}+8# zLMJ3~M-RnHq{cTk)$+Md?Tx?$a%ABG3?t4*=Q?hYm zBA#~xuPVA+$T;DF>aT?Pizd8h`SN0!?^Jblb@w5yuT%nhI~mtr|LD>AR~4!NJD;~4 z8z;i|9pkfYxNV$b$cYXT#$E|20)urV_|R+F=8>GcbsA6;7KklotWT()a6pPR@5203 z-5ooOGWIY=@2xl*#x~NmS?hD6zAP!MpV|^-Mh{?0zsYqw?LM8B9M+An;~cA-$rrO> zr_Zy*Q5Aawh2>Yw?Al@%-c*>P#iRp40$8wrFP=ItPU*`zIXS3NzuwzRbD>BeRBDMP zx%>UCO|f0aIQX7SIG|>auMi-8cPq z%Ov!-PDWF6vtjqefsW1TM7-8|{g=I88oc-)KP`7T)sim5bci~5cwouV4`xweCNP}{ zDfy0f;c3M>B2sEm!(w2C0nUw1DrFTHSLzm~nD@$It940dFW6pI3m|v$yMUvzvlF3b z+oh1VpXrZIzW5~Db}4^N<{wx)Dt;+5*Q-Y;dyDm1PHtSm&bzif_60DJX-7xz8>@(u z!Q$$3|5a2Kl~&Tmiqc2XCO0oB53PE3>nW+LY?1T(M+s~B=6?b5fCKdr?o-?c8#=nqlnH5b9v0Uuy23O+Rqe$ zePO%n4h1&t>Y*rBM|7|Ub#5yE;}E8_06D3sP+PCDY|~4V9Y*L%*$g52-aMSN3eVMV zB6K~y&y@W9N^Kg2Irh4QwQlDLrf@|>`XzEA`%pdg=w8Y0bOG@QA@<1Oq@~RH3C=^ZT)wscEiKMzA1_-GNiX}XTVKG z|2W^QjT|s%|M6p9!S~vRd#_sau|4@x7o+H=uK4J)Z=yiXF^w&ohsV_}$ zdWbRyhU3+oMLVUA#&-Gdjozr%)&N+{oD&<5n(u3O$tHTnDC_g`%bxbCZVkChZQ2)iLGp{hb7kWZ*@# z0-k}__JzfY+c&L#NGkVfr=b55k#93-W?Pvag$Gy5v6&>hZQB_)H&|s357VyxKKgoL zt;>y)-;Ikg8|mWSdz_EwX$LA6bWzN*b{(Y@llxzn`s*(r{l4gI4t3Qi#-ovo28Efc z;vN_Mjzpq3#;8ALG|oIbh8*IqQa9&miqLvLMAXm}cl&<`ofi;vldM-mIrW`dTd`8u z;&S?993`!>xHjo4u?g*IC&vBdW!JOA5n_5}b3{bMffKl-s7|jW&i)e8%m~e^diIRp z;6gP6k$FCyl!5Kk(lshiV{k+pieD1eoac8Gt1)9^WyCI%(&8O=FHS;?;;#~h>eTjU zS_vmS$4QU!qL||imfOb1%Yv#&)R3*7y2{==P^EV7-Yp-~7Hq)q^XZ`Ah{Od`r0si0 z8E~v5VW*7ckvM!X{uP6B!%T)j*Mu08@u<{Ibz1D;<3Bv!g}`0#*QdLyAJx{@R#kn5 zaydO>ybH~-ini{SGnl8vL`_RG2r@LtKgBQaT~JsElqd@jAo4k--G+t5W+Z%|pk_@- zC-siE25MrBzIhX|GJ#{b4|(;#%3aJpQN%<=Z)1o(gywvFaiBW2SK-}wcz94y9<#PC z0NA6M_s3#XBB7zQ&d%r0xV*zhs|Sp*k+jg}<;ZqH#woepyF zOs4S0Eb@9h*alvFO1^&tr}a~xqEttBwC*M|lWb@A8HSGpw^4k7gl`OoGiOF(c6rAS zm0*6(RihV+d~OP8_^1#PPMfpe!mfUzzzW&4yd=-6&K!i2PLQ|v+;WEI4La4as3Kg- zKXDmv3849<9@%R=%_USdc6vK2exugXsaiSJq&kj>YmQv}GJSOcBJ^gJg~l$}(p3s= z&(Ak{+%znp9;*vadbixJx=RZ+WT?L<`Bjr%ym(Q!Rk83sfMCZBH8%08 z(zyx)+N$(yS161y!-fO?q!S)r2dHIbYpzW{q|f$@PYmFcw6V3d(uDSRVq(H2--k|R zoi~3zsukX6ATL9rcxXFsWQe%)6&wH=&*!=FNQzr;iO@IF@&GX6#3z4QOA;GtsR9b^ zY;8Ov6oVi+QZMGOW`SH)RN;6PNp*mf<`*?$5vGsj9bXoG>{I;! zReYX-((jr#{E84dDkKw;G)gD<@|U8glBeFm=M%-MIP(_Wip6Kie4G*NV7U_$6Gij2 z)Kyh)vZzJLg*pW-+%aOI?lNle936~-Jc@wY1jh&1qC_@Lz`E8w_N<&X^F>3fYLq2M z)MFxBDppZ}DJ&FFcKD)soqTU(oUL%^w~pQ=dnUywYTk-v7tV)#!jgW*F`S|5dv zkB?UDi1WC&q@UW{PRY*7veeHae7Xf6Dd61qj1Qus7RpnXXS#p=pcuSZA<&fXj>1S6 zFma*sQpmuV70VuxHVzOJmE)=`Fuj@>b2t5t26HE}pA2+G&1AYu9E@U0OF!kD7M;}Z zD4!TWiK}#tXYV~1I2(v0jDG2Ij8AQAD+WXfk*{&Cb6Zk@T!okpxOIP75t|D-|&b8%Fo|pi>)Oi9B%3z+88=i(i zIaTf~2=d>{>hx~>{R(^uDJwWDN4wCK<`)!PTe0&Wl@|w_oC4~f4r1&knUh<*^OhMKF0Y>lv zK5#hxQxzp2{$L4lOnHglB`83J<{;tw^%G*1Qq8=1d3hMS61vrdWxTHzZ5=Xg_h`7+ z7xa$=Em^iqsnB;Ju}#&r#k0>mJO~y9_YC7$FfQ*}&S8wF+hm9tBF>J!b(Sa=JIe;r zwbsZxVF2b8Rz<;?sL{jLFgGz%x6=$+H9ILlO!xBbhXSGb1Q&a-a9G}DR;y2z+$ncA zpnBL4BJHqVV&@PTx?2)EXQ_ILmx|ZxlzxhlmxYWUJ4o|uovIrqTY$q+FL zg@k&LcK}W~=IU#}DPCR4uyo5*cb|y!ytYtYW`^JhpbkfcxOdQ$^dD(vwN67tC+?Io zgm$Ee^*zOE7GYe_-^jHJ)MP==$Fj|Lbd*gLyrns6H)OucLd+$Rnb0P zna==Fo}RT`GemW4i@wQX>_yWOd4tGfJlYZ|~8uT6!M*`gw(23-a)oBfgQ8H7*4aB!*M z#5EyCb9Qgt)#}FyTFi>*xdf3F78>feV(SHotxi2UI4*#U@@_kE&imQ(=V%}0+l>qi zYS`t!P@%~`aCiS<B^;$^v7kr68E9 zmX}ToejXZB>VreFqiK87ajGwjOeu}-*U)TTZzhJ_X4Uf``uaPa2bVi98I38J3FM>; z$6y#C_d77e2<|0T5H|Os4B$bWD^?)(BeP;Rg#C(i)80BiK=pM@8h* zf>PQ4*79=qW+dK|BAI5{jo*O;IEYCHkoezjqa zE1=+%mD`EI#_0susRf(+2IH$yYf%Wjg`>kKGdtTPtvY5Wd(d#YIG@yaDv04Fm7D-A zLTM*;#VJ8M_w2)wma<0X8s90LHzr+=jm?nA zDw{!Dw?ph=Pt2OwGNr=dXEaeQop6N+tS zzuk%gVC|h{~vuT!;Pv6&28Ij10t(&u zo3kQsHdW6fzbYS%#T{WrokUZNA|{E~5kqr|Uw6Cepe>M@!O>|&9`5DDI>>+mqE7na z2TW>FoZAX@04Dq%EI6U8A28M>H+nH%1s&#k;l-mC1&d;|IXSdGI-Y8mkN>pYc!KtD zDT4*Vjrvs|?}ffY$c#)kh1nC@pHE(RIzdcVe_CypTP?{XG)u14*&`PN0v5}EXno)& z#mBeH@D;MWwY0UdCuW?;K>48jS_|18=H_GLJt?W zrs71*5w0#2z&>rWmd02y)r=N{McCJ$vAX-w+lLR2zyyR5H@$O|CFo+WFf>oa?^_tg z$!d%TI_*lMi>X%bY{gKluxDNS&Z@D$z^IKFMI~#FS(GN-aBy1X=f}pvvhI1 zC23cRlVR;wl&JGvqKDS?9cXwE>e-6oTkHF&ITp13m|V-l17WlhaX%XNR`rniUKgMd z(daT=sm86G^nW;e6R?`s?hTk@EXtvYC`3wwq(P%iBh8aENF@!sNmPys8`+|SsA$~H z^E@F#nrPm&OB6|ICeozR@ZCS0_kYfR_^$8z&h=jJ`yR6Gy?@WM*1hg^uY29ZuE%GW zyf`XJ&E!Zq5~7P-Zhla*Aqz__p1(@D0sDfMPjg2{R6~~stF`h2%EAS*i9S{p-pJZh zAlo8d{AJ{+nt(qs*jjj~>%k#L(*dWZ>PJvmIE%J#k}Jl>$o&!J^9K8`0QMIWN9;Z4 z*R421y!+oMPuc5J*xy_K0RygGGxpWr*G&Fa2J3AU{YD>eB!qjLIksYmu?WnG9u>e5diTgS1yMI z-41noNRgJ3vM6u}s`3%`#p|8A9LF@V9-#pQF1>k{#@Z4z6^`R%NavF|~L&(5T*OKk*TH%s{&&zq< z;(vUu-h=Q{1mHleD&ikX7RZZC3ia&T~P za?&Jm)#jFyK1uvX8SD+Eg`hfEXZVag!PQUbz{j)@z>pLmn}^0mOoRA_TX-{7NR`91V{n9jFRKp0r zJ?1rp(29klSK;=We}gni@_T&d>&@SO?s{wpQ1G3E((QiMHPGxZ!w%8zgoQj{$iYB@ zaOUHSbLQ^FCMMUmJgOP`k<&1TkZLzReR>p;H6;^I@G6x`F38M#Sz8;R9gPvkZ)M}- z9s&XaRCi~{cA=p%d@LJYhXk464eD}Xe9(~m96dP`WrVETyXvc|-V{3B%OL@Btzu#d zQhQ%Qv9w;;fYZss%GyWF(pvSRN8L*`H8q9rN^BWA=1Z3^7kU@@`SWMI4ztba)2B@c zM}MjlVGwR=4}gBO=bK?A+>yMZaQ4vgG+aN~Rqls_w@Q9DHgZ~8TJnzcRI_m?tFQDu zf9{;o3d4(eteXieItOQk@rtzLpNM@FaU62Gj5AChQG=8Jd=m#wckDE`i){#)Dhl~V z$)e#??Oz$;gs#LtA#4Xr{IpuWj#=hz!l@=KER1mG7Th#5_db3@#Jl?IVR<9QK~TZ>)_CB}2GC>C(a}JDAS1dvVpvzIb`xXoX)84~HHS!2r(i?PivwI&6cFl9 zm``cOQZW~ByjDczJx!Kt zYW+5aJb~C7(hW^CD(w2&mp3+)50TsQ__Hr94=i$mxJL3un$$yP#M95i!jm#XuPZGu{kMzhq>x#=N^Utw=a$+0VHh3oN@nIsFbUz`Wsm>AhD!%KKZpEM*S zB!ImqlrPJgCmLE?CviAYz;}sD7J)J`){jk37Y=|V&GYo>J$v^qz{P5c0gkJQHxk0v zTeohF{I%GlEzxR7XjwB=*ZKy#nG+6vfhDT4M3J*Vp9~$W1h}NLrGNtuhSRkJUnEvi zXiFsH_>0&foqEh2o)Tu_ogOTm8c5`#hbw*t)5xFa8z7xm?kPBLKO1-_v7PjaNxAGwLv4L z9CPRYMu#6?!n{$YnI|Nl86=|RL3m)_6ht2megEwjz`yvsF+--cE43Y@soz*%>Vth* z%^;Og1(=$fTRuLMIaNL_4^)S77zvDm7$h=FRlK-8FU(U8hpiTfd|$W$;FpQ7h@GMR!T?PB9#+l2#bByQN8N-D-^?fpH1X&(KfT6b1dT zZc^I7i!vu=F##zZRILu7t=m+Hqzs!3Z!zxH{Q@;bPq!*{My+C_%Q&SVO{Qi4=aEfbO{Tad! zE2|F~ruhyPb@lawn*{v}z!gZLD2%QbObfFMZZYa-njHfaOpHoq+A(9ZR0>oNfl%I) z#=dU8@#MkpVYrwnhX~3%uFoHT{BibCcD9(JtbqWmbkym0!gVSj$wTf*{sJQ;jj70E z($7ivIMaSMKXDhUYhl$=44{W99L$N*QLu24 ze*=Z^`S1$>7WDN`po=O(C;$%V1|SOV>ZT2^s;;l+0S3}~MBx=be#IdKptI?-Bj^&S zT#_i!*L)pgyd6Z-?#jLB7)5au;(76B`Bs21Jd`{fml^MJ;>)LidD9d(G%?p~l4%4< z3Ckm`D7nMR`P4rPKgc5AJ0_MYZjBxF} zt#)-;vq@8_ldG!^2`ks{vO1D?*B_G8mywfWUXZ>t$(~>D;e9CB{t^@=8b*&xk!+iT zRF(HaTaGHS*$Q%pzW_%HhLN+}PoLI+I0A-0auzAib~nYAN~;UnK#+^Of8zA!hGWT; zt-6n!kn+Lq0%e5ga3Rd0ft+k%<>I1Up2fFzMbxpWIb}RX>dDOXK6oQxI4S7Rtb~hL zdf@WVUFUF%5@{vaWKX^4Q@p>qC;8h3IS)Y|*1^F+qhZuR4$sLj5-QrxyzZ39u_yOm zeg5!a{}@fjXoyY2UjaMP{c67^|{3qAI9u&3WOBnpNfI3LTL{M_H zhxw*x_d7sQ_HAjmm8H0BPe8IFAu)y=XH*WTOIzZw#-1ZmgzeU|=8wQ0z1IFL3hT#BIJXb)bM49dK^Ke|cGhy8DRf8RsTk z3=Y=i24U}{B~r~r7DUWcd=ea%jBNn;I)=W7;LFRPp{M=( zqCG}6!S<`^Go8W$B{nuTp#%++A)D|?qelY|tAtN3d>$Bh2!TbDXTtV*FQncKPdVFf zWzc;?BN)J3^5cuVT?BM6&CdP&WnA~+##e6KiK?OCG&fuE(#Eyw@hyb)mzM(oFV7#U z(@%F>yiC;zJwZs?%jy&=N9oW_952P|^;5C1IWAxa2VHMVMv+2 zs8Tb*6dQLvhy`9VZ`mv_|2Xc(jTU0QEMFuQ*Z?M4)wt7VqsBjE?^a$JI857K;P`3? z2d*HvS1o4Us#U9!icGxOgb3`WSebtx%BVxa*5YMc`G_dbYwn4fb3%%Tz76jo{u=2q zpx-#h!BR`^7pJ$aEO&5yhi!C%+f2>or}1zz2BDZvama#L20dueL{@A@6Zq5C=&4$(kIxkg)|DUSEwC2kD=tz`Ak6WjRtRqxlL6U~DBfVVQnQ9iA5s&T} zF!5(uNf8l%>N9)1?8qqG$P@?>%dQ^BUbdQ15-9xhb@#!5LWmsvggNYVYJwi0*_}l%jB%HW?Tf?#NUVQ zFl}XJ$1(f4@Rbdi&;HRNi=#&o8r7E^q_*gC{~2~PEbjvf%a_#`Q;r@Wc}4F1UN{lp+%Rc>TkwKi3Y!ssE=MZ_!v1kIpEX~e)GOkVo1uW zOSl zpW07Dv4>laF4+-ydg0i>o~}FKZDJXT1o{=nPSV|Bh6m9V=hU_*hNlUj0gMfEiC8vx zh2a@=EgS2S=ZMxy(}6ivOkC3xeL|(ShSUkoN<=9;7&PT7+jE55m5~Z#@?U~l^m1h7 z%s<(=kE1inY&levGq6n}pBuQA)F3!(_OzRCf?lKdmL#k^KpPxCX!sO7rbk2a>1cK6 z)8u@#7B&rv<-k-CnBfRSc+5%lu@cX5X7L2mX5^=?q>Rvs}1;k6jhnZ7r+ZHpG{w&ZD4BLQR$3z}1xA*`y zjI4;e@3EmbRrbm~XDWrMa!z7dKvG~?eleJqpMZRjmVZH1P_T+lPcE0xmq$ntgFG%2U`60*I(ER26X!h zPXTHN6Uf*6jacv@AZBBC;T%7@_IA0i4|N$5yy;8CQPThpV=*O?rD77%)(GIgrdu zOk`wbPo-p!7wgds+VixEHBL#}ifA zNWgU&NB}lSD!ws$CryBvz^hn<SDGV_p`*BS4-4U3Bvb?drMP848875(j*BA72b*e7XHh z|LD*?QpP2E{o2$jqZX>@SLIHC&A zZXRfP4YgzYb%h_NPR->PD9ITOuBHpOL_&im8x=@?Jn(KG(Q_B`2#l%auV3oe^75s6 zSZ;DHn?=Gvq;9f$u`^SN?%i@rAG;KpPR?5N-q;@HypG;bkRSZ24pRWx(<_@*X}jh; zmh6A9IF0hkfc+iQ&7 z3BdU2g(p7WT|-+g^LE|6bLW1yRi?u zc1{V%o|{nUoj0}KtqgtKOZTQ7C&5fgw?Pmm&@FRzWXnd{PQ#>?z7UQOCD>0T?h>8v zlK@P89aVL835S#(%;6Sc-2HIWwfKTr38@-26q34*}Tjv{r2YN@K#`*>$l68@=8f z-YWTtP+NXOVIp_B=i0dKL8ycK<4)NzZFW!>JV)J=J&p-8!;DOffQ%Fsl#=L?vUgcJ z01y(Y1s$Ne?JiekOTw&?WZT)t!~siTOzW9!*E08gB)~fkPU=JeDhkL2gbn< zELkvr&hwr>EmW<%sVV3dv^}_5l<86auS;Cyhxf^`jEeP&WI-&sC2F}BwIESs$@0!K zP>$eA=P%{PB-?Q&$$@btdk!ZjC%Li4n{2JydH_z4p^le42Ni4VaH_C|lx^`i^w#cS z4YMfe+gUuHYfUu&_(hSU`oX*20tSLijri&`H*s>laLI=^ zLiDWIfa?4-t|o$6%pG(v{YOQU6B8{Sx?Sp5PFi8!T7e*;GIz?&%_@MHg*tu$QjT`* zUs_pWK)I@?C``0_z7767wr};CLia3)V5L4Z@DnnfJ#29I_zvgp6=%}Sho=QedpR0 zboV__afb$dM68d)GbF1AiJeP>mEJZi(bW#W~>^B2c6hg%`YLg zHq0DQhlpI~>(zZ= z%cB7@z{Empb|Bs**#o-s5t3vgT+YN_ADy6M5W?eg^Uh+NU_^FO^X6ivuNhKxUJCaXWm=|wY7C<&1+Vm1STdXz%Me!Rh^um_8K?0+~P$4AV;q4sHNVMct^QOTI(*Q=! z6JWpVQ*+$G7#a!LP3-L33tHci zFbOpzwhkom8=9wEO%n;NsbHNlqc!y#$n7k)4w4HJ!a%cB!7=*mj}?FlFWfz_$F2Fq zDi#)7dtPd5@V5GejMas6`53ndi&-Ve!(MhB(MeuIVlW^sc!EM8+-C|+if@2F$tzLmvoVpLCoYbion4uA!u;-OuS{ELdp(%P!h zyk{e-K&Y9j`PAqLg0TbP?j=N2Jg(?60<^3CG_in4LFqx*iUpA^!omSN)+zcx1XPx- z+&k~};rS)WK=9^u$9Elja?sZp)1Wh6=nW_(B2CucrfolHcrG}e!in*;n>*{yi>ms~ zj-komu*P8Z#0j)E*~{-buUtsl?+^2HIW5?gUtznhO$saix!@V(MFQJ0iyHtBSH!IH ziw3S#GcGpnG-|Jo`_YfGve7k8bDf1av`yNjh#7W|FWT{}GNzLV0#E0<$MJ-41g%5j zn0d06YEIOsTv<-ydP>?8v+i%_{Y8pUib^P6Bu1Ihb{k*%^mMO=H{(Pv$fZ3BEclN%`SQkw;g-9H_5ktdf6q%&_x)UScn*n@F)UZ-NPC(c>_ehU)6r%?^It z>(`Hedaaw*l#&49MFHUo0vjbWyk+LlR>=G(Cnuw&UCe+i2CC*@IuEKXAg^mv{WLLk z-EJbc3wU3yCovNzX|<63V)kkc2d;eC-Cm<7!k0XH^yr;vGt;F>!q?g%$j{HO>^m)S zn#K`_@d4jNw2_HGEvxK)Xk5utUr+=0EBF!xmOrdf6wsLiPYxvW*jla=n4sfFk)^Cx z$r8g)meDK28y>X$8A6P3i5fKVyNuBdH102i?ON=i8lyCG@65nzCQ0!(W=Pk6O4Xls zYTQ5uRFd>jwG`g3-U$mO2TwWP!OJ@LF5s1l)$KWog=2)p%qxs{#vxNTASXcvJji|m zVyv%U>1+o;!r%ZJKRj63So*&nhYsibj8(`C9Q%aQsunVCqoIQMqJIv&J}4@payI6A zw$?&qAu=fF04mZS*^m~iCK%1;|EaHb6T2hERPnT-?KB+$&8|{NZXm%EE90P!PJ?0C z!lME9*Cc@*I~Z&$MDucT(DhS06=6sx!JZdd z9B#2EGObm`Jmv~6o=nEc7{j+DLn?ew7{O(blndyZ+Su9cxVx}xkCfB|h*^)sKf}(X zQj(NI?&aKF6GcbKRke=0wr7Lvz=>VsU6B5ZNcrX1r4s&UalU3V@_R5Cfy(lroUXr+ z$dU!E*OtYCjmsIHD&c%rm0xRzZ*SRLT*NHEWZ_{#HIRxDph$(c*%gQ8W};Oct9-rs zM3}ev2BUaKLjWR??@1F5D40J3|&Qc$osn7Ly6{tlEDIMO?!KLf!V%ofGU%J zm6m zVx_SUMnp3zIy*bjOGDKNwK1Wf+_4E~cloDVdO?SF#!^7_opE!EF-9L|Yn{;kHS^Av z_p&Lh%*^eec%We>+OxhdqGO541|A+PHn1a;tDW7|)UKwde}Z%eISvfd_VLr~pL=># zHaBcT_$x>=k zk5E=Va7(m6R#HPLJ~}GuJc=u*a|nGYcm=ddta>4ZxUb-~r~VSIC*c!!zkwJLDon!a zVW*}H)IKqdai9or$_vcfoQhil3DuC6Os78*PGsaJZVI;}RLtCR)YPJqmD;xm+9y_p z?P}7WJV!kg81EC7LzwEu+${_zd5sc#EH zB`@7l!w(&7qmdd@Lw0PH@Ah9cY-&7)lHu@`Cat6mI`l#0HV#MPJ~FAv2j668PO{J{ zHFC!^sKaB-nSI4LNKrt;EU38gDqZoi$XBZ0=pIvzOn2uwqT6t0vHH1H1xI9H05~!G z1lp?}aWVTwGE}_$XC>;rga+R~m5=hFX6tIsjUnp{7HFAklzN;7Gh4@kuJLkrh(}TO z*=2uxk8!jtDG{}SR{`C4D2(d`P-RNC4P360_G?%uP#<`r(obnu_c-Pa83CFP14fNd zG$VsI4u)sy*!#3z*}ct=o!fEpy^MwNm6MrVuSxkgHhs3c_)6_aAoP-5LLSpGU5U-x zMB^4Guab;fitg;7r5sbvHvqKgAm3M7q6|CcuYxIN+$ZD$^LwUOPxZ%rS6^-fqt*X6 zZP9fA3vX^k?DxvlCFUu3Baui_Mjj^)T=&G+0UMn(!(>)P>NnyLl(ov?2sm*3Q+6$b zaZ<%$$gZ2VDL7qjm)f%@&fdWBo*xv~@QSz_-I`B%3<{HhYJbOvp-l zoLjqUS12Lf<(LLl@N8yCIIW_(`ub2ppF>IW4!x+ddv7f)EO3R?tdYpOd2m1Ek0powO`8cp2|dHgY5)+??xtYM35RBgK8KQ=eHX4MwNba zym(=U>%%<1~7^=SM=aP zzc^$+Ci!;S_?{rNd*a$5_udZ@D#L8SvzQ-^a}4OE!Bo<`NygCKNJrGby=uf7Vo$ZI=u@8@RGuelaiJ_osE?a4zcSFW@=d7H5_ z1*n7InGNE0)-S=)Rkgp5j%Z`X2TyMwA83n8(VdNpzuI>_Z@rwG$?ELeX0g81%Tx;2 z7O5vX@+Gmsx98pv-j9Ny5rIfPoa_1&N7kVvHV z2zD*0=6Oi^w*;)cU@H*yMewT5d6BC}4rVqUGGN!@NeU3TMXZk4c~z&Qtn_@r3=k9OofRKbWd$EX0?iIfs&oQ7oj9>{#R|jt z@%6_(xpRt`{0WhGAcN0)Bv}pPY^L!AtIo#5)RNeZhDZf92X$Xy@mg-~b}TTn-W$A3 zQ-7E+Fsv}^|7c@veQJKzYmke^QA_C48MD(c3T0to@#-DFqI8}YMpK1ZIrM^7obZLw zdnF@IQ%&+K(!b&=9u#Jis@9)y?&FWa+n zEyd&ycpyzhdb=xUA1HjiBzd(cpmHU&cKiwoN7svt(hI~ejrZnM#gPQ%=*b2^&;j;} z3#XokTTw3Jzr>O9J*2I&)dJAr;B#0TWsxWaOCJjpiKzG;@GO#QHVsf`Yz5YO08#VG zyQ}j*V8TAn%73uEP}t(nL~)OyyT%6vs_}l9e1SX~pLn@jYXPA^4Ld4V$K<8B$CzkHfbP~>uzcE8|Op@hFc^vQmyQCC)<0LgOWp{6HN44c8_+-_i8*(pMI5(&x#CLA zAMS8H!e)(E+wO*jp6M!E##xu=k(8VaUhiBJGCef_()7g4faC1T4Ojb=1n`!NSrl*2 z{Ar!g1pFl^BPe)HH151m+9SaL8OHr5y4PhAIv)Cb&l<9>yIW!`zyk6FLuq*hN=m_J ze8->-<^0gwJ5i}Nwht@rFlQVjrCG7{23KOo2L+!=E$Bi~t{Xixc5o0}^)ONJ!3)3@ zP?BnzXpwHIIiI#$&A~aEM9IpK7)tE8twe8sq7!{axdIW6WAcEtn~BMKbD>#bA6xO7 z59Ga9^xWfeaOnH{`V5pmm$c|M2?=rT>_McLT*>~mt7~h4wPbru@r+Vt!A8~8uo%;= zv*D!4XDKVuCZe9ST;=Q4&axIFs!-#DD*^=XCn@smDO1(g*UwN{%5xxY$G{u*%0_+N z^k&&h7m~_N$K~1O^mA1C1|qkmh3V{L?3P=`RR5^VDjE`a4hG_5-D#(5$FH~=vug>s z^Hvj@^@42Ypg)T@HF8`j13@7;EAwbt7?LJcg5KgO_)i1?(Dd4q934qL(|Yih=_w@K)6Yk%k55uN$G@CYoF^ zyUe;_lFkugFKOo67Q{0zo1i&hf(^ef?+t696?xID%|L}Q?LC)ID2XZx3{r=;e z(1u>z^8pYB&-9AP-_?6&Ht?U6_X) zsbcLf&3(+&|M;1IPow^q_8RK#|9fzB(QgTV{Qt);jWT!9@dry!hfZG_lR^0h`ABneBX z>Prdx)6&w?aEHC}@)0-n9FN115W-d?^o_O&b&aUrfKjSJHR$reesrP1qdUg=;Sjq2 z`YL|ES?`;nQ~jvw7N+TxqktGXnxWiBd&HQPN4Z13Rfb7lNkN70pe`gB}Gh8{}u{Y zym;a5?G116%9rp}OwZ{JWOYNP!L zX-o+qthPY+L2Yf%Q>WT+tdQ}#KYo;I4`u&Cg9aOIIB%o?vKD+W0MR?<@;Z{K#IBjp zFZ9%t#>U2A4@7-Ag`ZHOCCPUjn$UPbwT#J;HYCUJC0Ku$_$I4`;ELYY*9YDVKr90f zH+E1?%Vf>Vz>P0g?VN&GkzMOYqVv2nCP)f4|C{k|LKC;Kz6cLZ)UmxFwWOq^pbXM2 zdD_^}E8%C7+qRXzeCfvwHB)eC=nf0TJ$vqCC-U7F>sB~7rDsh=T#lQ^&=H62iH8(B z5oqbHdppmKvD{ia(+}GbbR^~dW0G5-1?8RYtKVom4*;H#A<|`L#OJ8LKI8b>SIRzq z7oNfD{A~y)CnrI1-a+y~x1j&LMty9KpMsi-hev_nXl1ey<6IMppEnMxxh1c??CI&r zDMCNxUU2aCjJupoo7i@(3wd(>N9bMwGmD4U4j3M3>A!z}eUYG~WUwRbxOz&BMj>l7 zR$8HS{CM1DuMsA+M8IcY>!_Hhl(;zN__ z_3=`u&z(C!Fy!$YYav|-)L#zFi3u{?TWd1qfp49`kegQNmDnto>B=FPM#{pd)P&>iT6+Q z0xa2uaRt%er$fw=h7pvBOc>VUD>q`G5cAe*xQkKeh%;10=cc$yoT0?GKA1w&@4<|G zTO4ji-a52lrMcDA)D*BplML1JxH~avTEp~7OGgL$eg#G2s$aZsOuBE+l)Z zd+EuW8jz$+6_=^59uyvcpc>VWh{^5na5?N6=GEdSlgSwg;A7BJHc;T`VXr08WZkby ziKB-kNBHEHZ{+A3_*0Y*q<8<|;LZ$K7r=1~$6CGAqxj*4x#EC;RpzhJq@F+&xgAm$ zDJvl?Ovr~s-gI+Q&Us0!l1zH6_JA2w1-E4@?6uL==98N6%z74URG8%Q1ZX3r?6c7=El7@&0>Er zo}M1)Yp$y!I{8rVcUz-t0uRnli1wf%vCLG-8f|_|Oh3!a9L9%)Ud8Cv4T5?j=rp_C z4-u8ukY=rHZ7Xda&YlPW3K%r@`q~fg>AH#vqFDlPY(uQ2vr2ye8xG_IR#sMaICAXZ z<`W_uH%F+$h-kT1y+Cs?2%cFu$C+c{YNn|!t<&% z)zHuNgR0^t@#888_~e68QBhvK(2%z1GAA_{3hcZwY4nT0d+IT0;JtJeE2~|4bB0yN zKx^hk;n<>qpvbG2nFlv?L7GtJ+Uy$llG#k<@gSsB8CNDVw7%%CVBuEL-O#eR{aD%% z6nD;iP0JaRd8!3Z3$DE&1k2!vj$#sLgvZ8=I+2W$6!R#lC;{;un!F@tMZ&||v07ew zAD^OdoC!3mVap8fK{TtDf3t6$Q}D@ooLCjYb?Ky)RU<+puE|(<2|5Tjjf>>8Wm_HK zerLiIn4C9D$815gxQ!af1$>KDmtn2?)5*XeuaLGLn|D$c{mP)lgEYmD%*=3?9?Yr7 zKh@LKK0LqWOyU1c&a`LGD6Cx2FUZ6w&wX*5H;P^!9^=6~4I!R3!C#Hr`Ru}+nOWJV zx~eK{xs8G~a!`;yLIEzY*aTg~4&<%KRquvYMLaJoh;VUqtg(C<=B6wki>BD=#UpTh|Msmb9f7#DzCIJ+qJXdiaCS{d zPR4ZAeY*@?0AxAciqbg=eKd_Ax+hGqj}Vd;vw#<|s21P9fA3WTk2CV^j*bp;QR9~H zgU!S+=sQxr8YttZpv!sb>l_+$4bdJpt0<{&2ET;gkW>L9m9*rp*Nr&JLQEOVS{CXU zt{K>5Ot4F4h3z@kO9B!~lT(#4o4=(W-vn^<2UZZ$@p$7XlUh@SA0!qcmDh-EZTJnA zhGHJidtqMFXTS#cWvzIg2^;VmI$MwT*12E<9NRVgUo3MvszHA=yicE+<_~Z2;o7p}e z_CiAErX+tM%iv)#*g>|zIr;-W`F+p|0)wSU}wUHDN7A7k%pPZC5n)b#_ zlJyC%E!b_?=cQUamY%Q&xeGfgqg#z6T(>!#;xaWDN)6p`&{tDi9??a_|F!VIBJ2Up zl6kx_cK2RRRZU$T{vupJ-+EoY=QW#20!O)eI^9?n255JcBY*FpY1#kR+!*eu3V$TR zYrZNfNUjhO^P(GmR4Vn<+qz?CLT375(g0tGOB%Q=f^}5~z=RY(e3(=Bq5|S36E?V8 zubp@apF2@AL=jwNdGZxGlT`F*Fl)CcW&y6yG}%p#Qnn{>G#Y+}w;0BdZx` z8MDW|_rLSBu?tqHq@qjcp_i#{*suZjLa=Nvzw+%QHEIw0vcQ>}XGkA$*O( z1s6*#T4bc~3*CZB>z<`gJ`?}@U>Yo*9fP#<={|di9{;1#2;}A;qJvLri-VQ~bf)6D zDK|*|oHH?YtEQ@&tNJ<6VV)1(OZK+5xW)Rww^2^OwZN&S&jJvf^FP40>lc)7DFnPy_#;-*m{e5A$At>TywzAuTUDh*f7=VWX7|=@)<4J2`#gT?Z1D zw{C9i3KLtxVR9x>L@F-+RUrQ_H7-0XHg4Q#e&Hsz8<`vJ`e~w8GZU}BFbm`ZLR#P5 z;|Ladzk*d?{y8q>N~_Y|FF$ogNm1Tar=74u<@&^J%CdyXANKGoYHE;@lClku?5Bb3 z;}N(7f}@o9(qig=SA;{f2a2^*+ZNm(3U_pN|K4BKqWojd{oJ`(WGjqLL;x|r!FyT5yQ$_O!35eY;mvnS*ZCCS{_cJ2{n;h8@- zBrBbr6yy{b(dHBuMnQxe62j5JL<|MM1agRmIHxTR?z!{)cOIvJ7h$3XK?{#W=JM~| zdky08jXXWW&!~*^&=|=nlkx>_ta(wjh6W(DA$Ea{7x;yCt;$LI_nT{G&x)@^#$M<`+*xD7xdU~6#_V@R5v9r&H_bDDa=FKzfb;g#9 z`I;iX;W2L^V-piI4))~sxFd`HClAng0UpzD5w{9bAW}z}_v9#43RHl8K%<-8U=pxI zxV-Zb$FBxB49Pxy(oD};K%@MqiVFI-Q%>~Nt`UjzZRl8pU?6P2Q6{QT^vQBQAUy>P z?F^+{_%SJ}NK7}6-GMs~VYKyuhQe#`(k>a9Dg037Ms5^)QbI)(<5M)I6PWn>^nXqK zjnEx`^rxhx0I(67k2$XSF!+Ihq;7&-bYte5Jwp zPVK$<&+iwb_UF(|^*MX?#>Tx_NOVXp`>LkC4C;lct`+E8 zq+JS`!nNFsJ~?imQhtT@Z)O!m0i7(8Ir%GNl^q-eS4TtyQAqcmh)$4a(WaT&hGCZv9+ZuDg z7d&ax?yG)&{p9B)%G5|HQMum34}bsk8Ui^RkvpupU_ThS(qIn6T!GvNB!9B8?y4hn z#iN$9vlykiw(S@C+W!rex7M62)`fKFVyzCL3kT!{qZw>Gfo~5wy}ei-1>G!4?QSQa zvcOE$TXu1WaV`nD@~V3pa}pns=}?eC@W6vB>U12n2h^-k_$0b?Swlh9BAE%#2yN}L zdDIwpm!WFZt*n9}Eg=d$KOB>D#pRFh^j*7l6=a2lwLyyb^#ZHQ9!ng$_?DKIw>Cx@6JIdR1gNy z{ha1`2Sx%@2)baOQ9w&xm6n!9$@C?x?e~!#qKPqnNO{ONqUHZrk|j-$^zSh;{jKf zkxCZq`ilZrhhi&h<$Tyvc)|T5ML98%n{Je+7+B+%U4oOt*tWnrJV z_$dqo6d0pAqB=oaF@m(jD1@*MZBdw}iBB{_=_Y0E=%}IG-_;caN@9o(DoJH7_5;S| ziXT5-<(n8>K{8weZvlCaf#*I|rUedb&5bY-0R-EAyL+Y|&NF zg@nuCHU)*qqL!+vYo5{GIwTsT2$=d=pTxAF6_OJyRo04`{hPdsLe4yk7715QG0ec8jN^Tsd4Tak{74vJpNo zPYTG~ZqEiF&A^RVym;}spp-SLrYf7zjsqnD0qy4!J~|HbGEO!);bdImw0Lq>zg-#n z&S$7pmCFiIc_frFVr|-_&(f*fukP+c6wo!y2+X;+W@AVesL10D zJkk2jjnl;kT|}eUQqtm9c}*L7$%O(arzY7?2r!CCd58e7zuopAoX!~BjUJWHX?(UuF=wqQ49HTQ6PD4x+5TsuP zJT&In#LG)qdN5~!>3Q(rueR|K1U&*5s6o)Bc`K1|5k74>QTr(Kvw4Gek`5g_7~}Ux zJ0B*sk+WANLz#ch#?^Hn(ikd}9RdRPyqh7yv+|XNCzpOTh=sFnz?#As7%;;OWi{fo z{!5H*Ya4ds;)$Hav|8eOVl!#`^1nZwSvjJ|)XUk8Vv#`$Ki9YJ7e#M=uVc#qlBW0{ z=stI*9TtXw0h$Cf&F|SBp*|-$ZGA^9CnFY;l#$uitz%$76vB3l@GydfCz1jN2za9& z$bA@54k}iF1H+fcZEQf=5$AV*_OD)5?fwH!W&dltD$ZqoIz9Ut^U9Tfz95)6%)vva zg&PSv<{5;zrjwy}!^6EnzaqsGse0Eg9Z$FE8GF1>kn^A~^x5?;&AFrA$9dsD8XOdK z3fUFQ($;U-z{0EWu!Zdu3_;!8Ms~@fTI;cfD;$yecHJ;8G<_qZygYFN4Us(jCB6;;)_VYawUJY}jkMn>G81-~A{ z?l5YY;?xjODB7_-rQkZtcAND;a2gR~#W8Qno>8o1wiopZ=8;$AucI!hos%HoVw@G| ze`ulwvw4SPR>;ACK&Mdi}i1^cJbMEKxy`jQ<3)>M5TqjU%oWhUCzz@hAJzy2fdm@ zhYo?llk~hCtu8hj1L45WoO{NL^Dd zF5M@3toIZHRyfGrhFzesc-F5MbnyUQa2ECP`GMQa`3|=NYfP+7jEs!%u+OrgL3yN$ z*7?M%83nWTJ+RjwK7A6tasB2^97vKV+yfLv<5s{Jl^JqvLp^PmU$IJ)`FQwf6kMm|j7wZFl$ z#97<-4{n-4rW*VObd%A9KHJXPg>#?|VVP=zne!;2+LRo$ri60y^6ng(9Rq_zOjZR9 zTn$}@WyjxPmJ5sMhaQ9L)&$(RF^m17WY3}$&}?WKU?wGD3f~+yTM2G538I9a*QmfP zTgJI%f({iiT%wC|a|fH^UuMzaK9GWAhCm1n1pRXA?MxjXM|=x-p~Q7K1Aupi)kkFs zrG9#|KO%mz2Dq7*KKDaI)dB{1ql*GA58Ah95|g3LN%g1@s9)C;>{+1{sG7>=gF2YK zS4?Q$7e|Bg20%jV@kMDjM28j@?<@9(my>$o@!+u5Gg>rGwh?3|;$qXLl`Jg1Qt1uY zl^mifA8eeg@A&?StW$6iRRiqn=Cx~McQ0TXVu$Db=<|YSQ3$YWxj&?C3NI%xhd4X# zMgcmG1PW*#eIzpLzUDO-X#qNv?v=kXEb7KiQohIroDT>C9p4s-D!QCnsM~7|hFxr_ zEHgI1WAIJ$a8n$jl3uUZ=ska!PPCvZ!gSsyG*W;E36pItexUq}E3cpLvBGdcIT{?T zt)X%v1Un2>iwI%4?c6~G*aWC}wLZ{x-Y+5wG7h6K!`-a@o}=G3V{A$xE^aqYms@O8ciUQ4T7%I(AcqKM(ZqI$ay@QHlbf=Vr~xJ@W|8!85iuEksp>97EXt`evWE^I@&}K zi=tX#YnR(q9RM$Su+y4z?#|Ai0p!RfhMx%0Z1&A&Yo&-r)HRM#GfBq<@o*gA2LwO8 z{G?uY(|>tdgQEwbB-OzZ9v%)46QZ&}NakBmfc^}a15fZ-4H}BLVKA3|1v|9HIK*6` za|`q5m6XbG^iZ}Kpe=(!+g}4yHeM_k5JT>emXN^ljrQ|XcXUkq#rP`Q3?RT7@+T)J z!}33$_w)k6Eny1LzzyXAbR1VoF(F25`vmQ!Td{SNj&4doK!A;T>>pofF3!$`r5-M4 z5n$ac-qU(nMkGUMb_@!lR1%Od{bg2d(JBuj6A5vV5#4ej&k}^bkts# zb|cW^#bN!|WzN22x4Yd3k{3Z9lvKKYJiO(o=$yUUHcCggJRmU8w!?~Wz06@x>lYQd7e;nSb*hrP%#z8e2J7k8WlUYNy+#5S2=dE0KOT;_+AESMJsUZ>GI zG5DSOK++hht`-V)nkI{c4?ef2{C&Lo8cy7%C);&D(4g17G8a5UkW$w)WE9@MK&HyvQbIpg1jg8~M@N65*CuVFc$Z}YFn9s~;Xg=&72+2b& z-teBp)4uYxA5i-rnKW>!Kf`j>KblC>12jvSzlQ$??}S~I>7Br=bp*xi`-tL-hCGc% zD`0Y&q(ccX{`{=&a}1N17dUJs)L6kcl zJb#Bd(OYtqxcmGHqA0mI z3hxV02z|6CvlIuVeE^M`&nP)Re-FRg4u>Uz5H-MP7+#VP?y(};5aty|MlC?tXy#dw z$%ppR&@H$JP}> z)&W?ZKx|StOO4RQ0+z?uHr8TT(Uke0Z*Z6In*S=IA_XXKAED*2XZr1H0;JeT-dix$ zAWz$0#hsf#H~7X^5A0ky5xw_hbc!?vt;qBCg-vV=n>KFLl$YGOb8uBTAi{q0UkLQS z>c0Lb{$FTdN>Ip~_WyR_N1O*=-2H45EB=JfFLeF)pNM20q@g6q^PYgP0~>fCjYQ*G zNcW2nqA%(mBACIpq!TpWOYC97V6WZpE;zDAhdCp#H%>JG(dVTNOnRiGLNaab?9`kH za;XaGTRT#wsisC_#|WMM91f`fYo24vu4g$j+}_(F=HT;JX;$hDyL z_!Z_wa9RrDk7Sy0U~bu$tWkFt`%Y!`nLN!acihYRIUn-GOQQZc4zwuP%D(L!43!S} zmSsAeI3bCw|Li#Sg&>syv4Gcn0%U_zejdKn93WKz5^2#_iSX6YaropGoZ`&?=FuvY zfOk{-hUjtwErE!{*&s;!{CtVS$Dl(%QoeHas>YG7Y{l9hF{S)$o*wXg1V4zQML0#l z4fDJ#2D{@3MFiSL60rNx4r%1$)gnyQ@pfA1;Ahdg>jAkb0qd#KqMJYLv3&>{fbS%G zBtPdSVp7=$e_V5bcD>4)UFnSM<1VyQ;9NiMPe8jlV5Ew`Y6kU>L+^0B)+FF!vqJ*A&GeOO`a z0wz>T%ejYW+=W!3X?dA!F{H3&2W+fTY=B5^A))XHOMsM(T@3HM_#Dy=gc}%m|25Q7 z4gRi(S`^oVRg8XX#uJ|4G$6M&XUd;U2mgu8D~C?2h6Zzhh}c4%_d^UDyjR9xl(KR; zl&_3XJmb-W+Ee}S-W_%9Xllv@;4W)L!O8Cke(a*_;-9ekH=Qsb3k4=HiB7b_BcNvd z2fR{B)>c{BX*^DLq9-slb(SLtCHnhsvdB4n(F$H=<*$$@dZLAK0c+&p-7-S zed4*N?PbAN68fvs_>@GMydnHwhAaa80{?Lzb&TWxt;3A_MJoMY4e>?4Ii%kNR>wG< z>GiVdy+_MQGlUt@Z<+^&c&MOp&;)-WG1zyX!tSF^kZr^-FY<)JGV#BE|NfUB{pnqs z$4)+RQ=9+w6NUfn6`(zJq3@ZmTG;fZ{i*yj%Adp^-~az`_a@*__wU=V7A>@gN{dn= zdu2({AlfAR+9LZ>C_BltNu}KuEfbPT$ez8Zgfhs!WXYE7`!HtS^DFhc@B9Dz{h#M~ zpW{7_=Y1RptG`>e~13U)GBYTQ<=rwUi>rV!YJF^dZDg%ogLl%_KtO73&&$C zxtU#k^wh|=B%_5v?c~FY&ir05$>L?qH9S1Mjg7D6mja%+aqE_-oe-M!38bvNySp0+ zwbsic>TGaeN18q^Blwf0mxF>B-6`>ib2wi66xY4JMT!mx+Iqn{s%ns-sMPvnd zL1!*f=!3>L6k&|8uXkJTL8YVgLuidoTx(B%cqeUYUzIH-cPQ?d!$;2?MsF|Ow0JV-?r!hz zboRWt9JfY9*3e&{Zme%$oTZwI3{VZSxi~ml+S|VxL#*$?e;KIpoSZMgUw83Wb**Z_LQd)Y8yFhSaM^+&?9s_v>U^Sn3XewtZy@VcTsb)zX^ApZBGe!$E+MRX>Q!- z9X`p%f0^U({K>K4vBc9i$W2dtyl2@@hL1PitZDi)z5xnsXa73Cp$=oD(GV(4(MJgi z;bufcE6_^c^6N2U#MHjQo5Ld`&vriu32^~Sq2-+DY9<{J9a1gnWyrtY8tS2w_8l=d z4k(8ce{XYhj$TSi3L4NHFmDZGX}2s`x7B1eE8xbj)z$8ZzlAMO8#3x@hwnzr2#s2T z-+E*|3N{td53XH10H0}PIM9g1yBq|zi;(OELaBIrHR4|&%236Ld0m9M3maezQTD(s z15^&UXMOZq)kK4u*rNJ%_H(3oh)sGFb$OjJ3``i;~_ z=VXnt&y^FTGtM+M=6UCy^IFZRzGL^((miyLH3LeI&BBl&C58%AJIU3IreJ)L4gXe(CPxx9rM5YNL+wH-;#8lK$kn#-8EG*iZn%)&+Lcx2f(}13pSE<2X?_3Dz zIs6eLxX^OkU=O3(=8>S}d?;ss0YZH>W>;%{fD5%k%M~ z7cUOq!{$R+Ratl=?pS5Nbi!mWp=izJ-$VNqt+pQ^2?DGdYWh8SaT08=h}9H1Ek zql7*h9xp}x=Js~<2=6j}ou~o^x$F)o^VQ7ehqp`=y&bBot){Mi=lY3T&}o1e;VxuX zCA=kJgrU<`baQ(nK(H!bVT#|r>m~!c`LdQ&G=BdM5L)omt-Sp!UYw6kLOy}^GBC35 zN$pcU4Gl097_23fS~Zy&coB^Qk7Wy`BgKOL})RT+WzIQpt8zbM)2W3_tJpHxWS9{Cx za4Z@US+hoc$ELnfYVniX6ytZ^xvf0o7Z?+nWaI2SZ!+x&$bLBnt|Yp3i_0%3e4g!6 z&v-j1X_WyOfE4%(qph5L518V`Qvh8=)s`9y)er;fPfdd9Qzs-bWK1#>qO1am=EYm zs}6|Dkb&3N-vj)JhvX%E3hw0Ahs2YWMYXj@s*|to-@kt)aIhp|L;<{!uft~F6F+u6 z-5N2K{y;w#6t*qGmx(As9m=^sw_`XNJL_qh@DTOp<{j6#wi-MNVlI~CaJsG9^T?jj zF1DEM>;%WiAiOCvFOu2LV^~v}^19M5r*|EPOX{(z5yPfCezDU&S#SX$ew35|{1QqU zz%1Y^AaoHo0OmlPYDd`%BIAO@k?QF6TMjs1`~^&+g`X<}BOR=RAktM1May8>i9|w? zNw)m8pC2Ka1s(2GC<4561mQ|T7y3-EK^x3c%ET-&-R&YF+sv;gB}vvli?_R4%E}J* z=MWexD$y8Fk^cwTi(uN}x?(cGq2|tfq9kK=IrCb0gfl!_p_sSFV$zIJ* zJ7U3yu+msnJrCzWH}de>tgAf{2-h)9&HYCy-#0(h1k%1dS6VFpK^~$irU08><H9 z;{fIXAVoc_EmaaP2zP+2G!st{TXc~PDi&m(iJ!6A7H5eepzZ^DcL|yr3Tefv_Bih1 z1if4P@H;{hF;e4r3?N^u!RgcD0TBF70(ilZTL98C!Y6wR3n`G*AKPAfYy*#bIAHNg zarvghcM%PIZ)>waYJyoJs8uvgbiT|lDq1vuep9}@mHvVS3ov3VU&|5j*{z#5hx__E zkO@UZm;<)0PH&j9UlN#`xjXy_!=U3~c_3A1B6f1T&Zo`JJ6W22SDgrb+^b1?F^6ZC zS07o#Zf&e%Qo?XR8)bJicdFP)=gIbGG2YJYzb98{FA%&!wkv*e0Wc(zr`s!N?MM|- z6U5f5fzR_dGsPQ&aE6ce2#G#2WEYnaoM$CIjuA8sp*aA34Z3KTfs7J=^OA8(?$1Cq z+0sLAU}#mvIC_6)12EI*?jPEbgh zSUlyMg5LoO;67p7KfsK$lF9TItC2+Ra z<2f}6c~b62+bs{r={}`3BAD^JzF^h1r-(n1F(NFLWfxFp9jOvc;aD!I0fAEv;je$FvQj)Mr3C${ z*&;dB3d%`mKXU#nEcP4p`_siI2|=&mpm|$331#m$K9ud?j}x3taJV#w6x5+H zgO(X*LeLjC=p>{CQEC1P`vq*mVCz&FwIfyMjWwb%AF_Nn;pZ3{ zaME~fN={mjx3k9uH*hF=!$I=;9jG**O9drFSb0N(29|peYHc=qh%=qbuFuOX; zp`VbWX{>*poSX$n3%DO>Rn;!&$xaaF%~3UV-);sH12Q4p1*X`1coa?D+wf4BQB$f5 z3$(HBA?j5`!$U;XA-w6ZMWokulAivc zW)mfbqauu2PTidpyGBcZl9F9Baiq!Ke$eFSQS1K5T%(|<|3GrU6j{JSfRiv@EeS9e zG|rkuA@YQdNE#r1B>ZTFMJhpqyro}3x?k#$}U$?=kr{d=O(0L@6#x$pnjiPVg_uLpse~LyK{c4V^M7HS%&Sr$;wWXLWh6Sox>&>!FI_& zo&HR2bw4w?ea~33BUq4#A%3(2IeOu>(U27m3~^f#n4XDO3C{DD!gU%hpxo+EK@#!5(w2Osxgic7=K(YqqCu3Y(+B7;=D zTvA(uThk5tFA9;(45siUvgkr^+J+j@M0eVn_ZD!wm*`BMBGg#TB$ktXGGV`hP+_4) zm>M-8fRUCsQ05yDIH7C!!^k><(q|ff(i_fTI3{`IV5VBMC5PGdmhI;Xq?sR$7z07S zv66$*X=4lp0xMw|E_PrNYE=a68FTD`-8{@BUWVxjE1+|X5G(`KikePTSRkyE4-a4` zhTxrJ#fnJrU%}mVu`~eMiZX;9AV~25)%5QzWM}tE*V3pqJK62!&7rOV2y~DD~#AR-dCPquYdny3S?b(C9|@f>kFn5uZh9tPH&do`_e7 z7y1(tV{%@tg+6iF``aYO{{Aw8w12%L3V_QLiS&jGBI%12SIL1wR@Fv91zE=gCR{Fb zXthqf&t4MAnagT75iFbBIA#4;FHrmkHW*@Q#R& ztFy`3&({qTnw7ruFd}n-x0nn%WD!K(-HFPFBYNq+QNRvd&CLz56b~$vaQx*dsl^Nj zJ-td80S#Z&w%8Ue;`*5P;e%@Mwg|*G7-oT*wx_^bOsoYeajFETo0pfjN)WkS=u&Zz zRb?DD`GTlv>5GzbAr~$3^o#T)tvgtlr+_9ifI4c}aVpFsyHBKYtVfk~#Q@(aehc$Q4{K&I%V*d2rJ zDbmg?_rcBh?&>U7B!iJJsu;9y{TFz|;&O{fzP{nU4!>#t2F#rDsnz#_8LO1TvMBsvD^HE8%M3G_XdlQ5 zE_VUXKd3!&^x*f_T;WHysqV>XWnmvj9tX@76SdRf9{qQW^JTw~@ZU7C?7klfr6=ly zb65GjR1ML!ZqytWECIpcU$YNbr|W~$^Xv*6wQ3mEO*BU}=pk~8Qkme7{P7U~fY~3R zp8Mb8o_{A|zPj`uinY`5`!sPB7=NHA^TgumpCa?Bj~GWt_>U*kkpJ|v<^H!g ztAENf(aJO}Xt zCuQ)ZMg$^fhCClSFLrDc^r`~g{*e)jtpFmF8+K-K5!7%HZo*>OapVgBw6y)_FuP>pedMbH^Y%=EuFFSSCE1uk%>|sWnH2#V&E%_)*ejX zAt|ZTbRBDhJQ-B4?c(BA6|Ytqr2sun>_J5_CpR}hlADKzj8$U;=_2`c3Adz8@z=SM zsBiHu7zs>(@0W5ygYA}rXQ1FeZes$>f&#)oxtH9p1c@NN`K=y>>UPxD{kIJW1OCN;iw33(x zZzFv$xD4SdbP(_y6}4tIy+a2Na?5!TW9KoNip|6#dl?p}h zE(H;@coA(|nwV@e{fI6jyS|*umuGtjJh9e_(iJhEd}`_FarMbc5B)cA0AeW9lXlI1 zrbdZ*rNK>%9{k$VH#F4ZEs+E^>;WN6mjmzNQPA8ubK;j0vX)V)0*va~+Oya{@R41B zt#I?9RJ)dgBN2!e@D(s*xv%ZOVwn7CgXL-`Cy(BoHU;V{{tdW_@H*aUE@U47q{4T7 zqbvzjw}s7JK1U^e6I-CvhF1oOc83lvF!D#k+p=Y0y!XF1HopBxhEQ6VG7tevgc*iU zUy0n3xa0(1ZRG#x(IhduQvCK(Mbii9=ZM}Ha^5g4?fObXrFyrKuHfs9P)aiQ-GN$Y zZ+TP@CeXcB|H`1DY?UbLd`SQKXObhp#7{P&*U7sfb-<1i?l!TfYfFGc3qm;?Il^SV%OjUP1?1o(VBr(?}7`#vp9u{Dca@JRxFy-1GTaSBX|Ljn8O+t_ICB z9f>0t3VkO8m$D*me<(uCV~Agh?lIGB-6dRT0#4Wq-21Zklxe-r{_C)Y|7%QX>2}uN z^;0=Q{eX`T%=1@3d=U+j=zX&)&w$!s@}Li5FT{+E($azNH^UyHaCLovgvxXbW-^GyH28vd zdWcT}L2Cu@jGwnrd%`d4R1$puziZeaESrbKQdIIFEO@j#{+TcR>%msn2>0~Yu z**VvQLHY=l`$(k2uShug2M-*mPInbs=#Qo=Ft(D0LyRA;&t?{>g~q!>&-Ohvxhrdzj=Pg<~v)+gk=~Q zAShYYAr@URw+Wa4*v$A`U@#1ij;g7tMJfhnnNF1@&_od5c>g|OZ;Iy_9ytPZ@_c6K zT8uQpWF#cC28M#}PD)tY(l!Ci=NgnmP*-8KmcbV#yM75ZTda0hV1 zb%39O2|tCOg35~8#h}N4{{))7%1+D3>UUD$OA6Aq8t2T`kj9C~O9Q>~G?SQ8C&1nY z4Y%m1M&MElcWcBRmqQQ%!V9v?>+xo%(P6a&Nc~_W;u4AVp2s{~#HFQ4(BRfs_YG%P z#D*wZ7jRGU^49<2%vHD(O7r3a-=J(xL~!SuwV>2hzXnO1IGQF_iVaY;mw|z$a@oi< z1v6lD7pr~QAkuWY7Kyv2#{Bw_Qoj@MtV{DYK+OU``ZG?9(#|^`&KU^M;?6!yTZ-Qd z`6q#wm&FWUpO_)k#7M<{mng!<%5m$VC|658#k2_c93{Rr(4Y7myiqV%?rgGv8$tiq zIFn#2PM@4~uepO8UivLDDJg=->bB4g@@UW6?jVFM+^bisp;I#!O?>KD3fR1d08xE! zmOg9|BD!cm2S?f+myi(dF0^nea-9C$Xg5st`RPl6{P3bPQ#B$M7J=R9Gap>GA)=WA zx%J*jkb6HH`#xp3BSQJW?E`@}0vGYyI7B7V=DCX&U_|oWquU72Uq%7pGC>(y5-OM9 z=jFjBdK;Q;1-{XuLz|euaE<=`$Ym9$kg)TIe>qZ^htJ>0zq_B<$1FJ+sYI%}I}b_) zB7&)8i}`XG@r433qAnmP3sv;rAu)trQW*sl$arOCC|1w9g8D;Z4%h+nwFGiWLbC{} zi2Rx9ShSe5OP1WTr4Q&*D~%9X_}#;^kTB{9o@HcE+K5IN%FZSHq}%|28CqrsATEfM zAHxh0z>J|5SE5x5pb*xb(0~1f<-|E-V$SL!+k=hoKo7kF#|PsIRNi_RHT~MEDnjFl zBX@GUvyK57N-SS4>fl+oZ!b1FgLE71?spDsb9npD%Pl2YP8uThqEOU)Y|)KZw2w*8 zNj>?SO(6OA9`mlV<0}EcFKDVQGB!2_9vMklEot*~{H7JBe;vtpj0(0-~I?q=sF)`@RR9s-jt*IRga4 zsooPIqeb6t+Hm(<-wfHBKG3yL@-+II!Jn_9ro?=Z+$=5Q?OpAq)l#XN-K99=zhupr z%2rHbmTzxzoMI+{VDQ^60p$B?&-}d20VeKBbOe;gaj+BjcpDYok922xf>st1NDnwW z=a*N}#QcSRJGo&bW6*lI*UQs2V><1UGVGxc^6lvJf{#y|g;^%@M={~z>0`1N=xY#F zhL@cnob>~#FHlMA5&SV<6xv~Vn5CU?ADhSaTLuj_*0ThTBCz0$qoXMw-w+{s^Nf*D zc^f)5u>4=PTc0MFZ>37m-7p492x7Zu3D8mlG6pl{9Mqm@_xC4A1)89!oO5&AA=aL3 z;7uNZ%o+M>!G=LxmkmG(C~AAY>JNlZ9WM1C(xAv8ZC7{V9l*GuC0~-85wjJ{xo-I4 zc;@(Xjc{l$eqxW9nrx6L{o*C;0BGs0oOz_Lbtmd~pkN{t`VwgZF;`b*;9wiY+9qx@ z(Hn9QMSZ-J+Se=;WF<13)))KVCy{sGbVT%o0kr*~-I$vq#+TRoI~{fn$jaEFyP&J` zT@78_U*V)t`o?)!ULO7!q)_tG4QIQ9L;LuMN)JxT*G9w|?MNOnNC<9-vjpb}fxi#D zpluHBKG(gz)}>@3^WiV^p?Myd6j5pX%k~za3pD?Te&{w)E32EySS-d(^VVXa;iP4%ZiryFyaM^xW_Sw-}bAmmrKn)qR!Lq$F zh4_ZL6l54!oM6!qN&i*&j*#d;_lg7^st`oy`7eL0G;CEyLOU|(j$hHsILnw!Orze| z*4Y_y|NbZ5!jBks4k!*C)q>}S$8?LIZhEG-2UtGT*GaA4R z@8dUsvyRR}Oq{iIxVpHw4?)$FXiT7LxeM?g05b}aS(tx{e!g$rh_Y9&T6J^nE-9d< z=(NTxM$8G?bLh|w>|>;q)~_xFKM2#woHAIlTPI{*}|l+gu( z=gysm+~LAJ4v%I1uH<-J4&Li_L)_9kz8sRNw_;=MOIDzRc?&z2BK#Y4g&$*w4BSVh z9b7fdCQuc;uN{QbjS%XoNm4Ps;o~z`?DOZ(PA)EiF+w+%E?v3ux$qUSdlt@ZzE_EM z)S=C|*@APXNSuH0AgEnVHH$u(ri%WLu$+HjQ$HE*TJjDUdqLg$?N1Q*+t~f4m5xv! zT)OAzI8DenIP>q&nR7KMeIIi`MfBH?<@5hR7VR0g9KBCB@;b2a4R_!2=_k$q$CF~l z+kc+HVwF^8O}PAi(zSm)=`hh|zlxQ$S25XhbXx06{=naXvV=v%lYq~?KgK*f-Lfq| z{~ymOqFMT^sLr;KYZ&RDnEU&4&G-i(cc1)?v2DVL8D^UNeAc_CB(`j62J~VCA{%noVzPSFn3c>UGp= zO9m!COl~JLMtL$wVd9;uhhM9+=qPheIeF9;7X0-sv_u)zU)qP6^j?zT;o98p7;Oc| zpGTCKYsRH?Uf%M3;~!Gx&~ss%)|W1c#p>UGf8M|K$3HttA1p9U@lFojViekFo_2r3 z5VgQeGD;!XI8ana_qO)!>HV+m_Sbg~Ur3__H?}?w&Nm(xV=5$(Exe^?g?AXeAnU%- zP9lH9+luGTnS>_bMH9Zd-@9(Z-(P}ZFwRKWuM~CsQD#h?ZHcir!(dp`oRh6QF>s6xc67YIoM&8`ngBY|Fh8$RWV9f^7G4}>$_#YC)#9w*7O!gY;A3#)Q6L4e1zN= zzMh!lZ^* zuck8|O=~`!Up6gG^h9ImBZ=g=yusRo@6&*T*=KpnNkQMc%)Sy5liE8Yt2#c1TtFXV zyEfBVn74nip0HCHnfcWFh57}y!}M^kCc|r#L-G4vnYSoi6z}*`*$uPeCpQ%)e5g6P z#k`l|`JnBO4qA%Ed@TBcG5#alPnpy9pJ2L|oCP~Nh3;pOvMP#-j2NYN4EXuOx? zR8CU)YO=rKDj34T6GM_$*J$_-8F8u<){yMU!IQD%lC4Mnk~<);lgrq|&!7It<#&1~ z`n!;zoIRP)^;nqSD3CI|?*d};O>UDrCMXVHh5D)4?FEhA7lZuFXI`KyGwH4eVisFB z^;S#G-W$^1utb-!k8xA1En76Um!~Z1FWp?z_1cRr$qZQrekvHg3j$w#k|O zRJI24VWx86SR(|sFFtHg*>PimWDfR?u_*J;_Ug1_7zzx z?}qL;=d|P3$D>n;a)w1!(DkioDlFHYn~v|ixwk}=R28uM@Y%rXLMy0`cDpNj%?Ez*>LQ1?W&Cv!$$G0YS-H- z-UgDF6~{)O7E`k4MFV$yzm~_eg+%XvKUt zb1OQaP-jLXKp&NJ*1uU{JR6np{?XCfSFi2|{Aw)?)M7*lLzy5l`(K?a+av}XeMB<_ zgo%P}Z{4_IW-Z-eX=K#U*w_fv-&zNnX6S32Ui*KQ-SEK?1fa7D?XGPU{4vxR$1z+N zWuIYy&HwSk2ns43^@425a`sQFJ}`8Kef{`XQV4NQue6hj191$mmXKU;xqp_ql|YM`CCQ4#=npO%9ssxQ6ss$7dLs zWw#U#u$!@F7dV)ZxY`&;bnnpieQsbkC#(7AFEjV{CVMi1C*73?BCb)GdfdTdqiU^W zy(Rg(d4&4?CbiV>b&sBXWi-O$O>VzA{}MB1{lM)-^ENWKOl0c*>lj3?nH*$JHZUir zuH;FW*7Z?CoXJb(qeX(5UvE$YBS1qvXU59BYd-Ep?~lwTZ_B(k(^4q@i^Dz(=HiPA7;I}0uC^B(JVEb2cd;~fITb$q?&D;YA!M|#PhJX=T>{i8md*G*;^c`^-#CNHsNRovP5DSLxw zEzNYHVDj8v(#h^W79H~ONSnDPG0)@;EcCXH4aC+wzpcY=6JV$YN^#~vgX916h1c?EW6P>)=nxFBa2?9O_Y)|BIqA_dHgFsuNl}EEbLY}KDy%m za=stCE{j>Prx-1{MyF1H>_*qb3KHgvSfC+!@7~>azxVbs(QJlHciT_?srTndTkYQ8 z%vvA(`UppwUg$2aH2W-Y2QkS{FKP-nNW@c7h7ljh_nwOIaWso$t^e0{iqu~ahoo_+8jAEM6J#Dzk6l>|*OYMl4 zk>?i(Qd$E?lDA?qL0wWvm_xJYncglE_t4)H>Wk1~n4-Y2oIk8CdTj?`kvSVk0`Xsr z{HgAJRP*kCMEKymJxfm?8yiCrHep{XAj1zIKA2lt2AMCOikY+K)l)F6p)`{%-8wWq z2sKI+l};vVz{T(SNn(T5rpV=Bzc0OtbX*zT9X8|y`z{8W!MZjd$ z$kexQ-(pqRR?sKq?-U8XyA7b3cezn?T*;ySrY=J%f~ot)f$X}?O!?ZK$b;f4`=CANVyAM zA(SS8aHB)clpzD?6;fU_qM|x9G(;g20-CeXSn!q<^q!=)e7)f`D)0mwW@@F+dz@yj z;pQF(VFs~q4+VAv1XrPZWL;yi!UbcNnB(19|6ASdUw>3=+k&2 z@(+a3F9>H)YR!BY$x5Vja!mS%wg2uFo}vNl^y$}~VmzPkp!Vu`++E0O%usNu3| zI?iwV>qiB!fm*J4J|#Rn+&dS1le=`&J0(&zvFJ9;H~vXaT@W&R34S(-zhwlq3$y_T zT31uk84%nsz5<5@bBr2Mi9z{xU}VHgII`u-4^eFGEC+z!a3Z*?m>!NZ^075xsMS(q zV4)~Q=sX#{^!50x%2npmr(^2<&J*3=kl#a^_I4TKj9zSmt}ah>(z&{hf>=(X@4!WDW*drhow?TWL*#JGA5owjj>9J$a%QJuTo1HA7M`;^ftb z=uQjFkg4a>UUZWNrUEgw1iK!5CXDlW{#-zm;@-Bcl#uBq^CROg;2@& zH_VVh@rQ?NH_(>1*_Lg*DWNIJadn(UL{MU(U}W)38GrGY#Y6t{*la^*Y->KfOF4o= zn`8Zo<{h_8AG|+&DlcV6(T7yUvoA{vbF04zeKVM_iF8@UPxInP8aZB>d8*fk=g3Jv zQqWxz$(cU(>DQ@bSx;0mxNpw6q(H7l(=IaUEiT`{A-cu2dvs{%>RW?F$D|YF*FO;+ z!!cCq5|*l4xo+JpCEm6^gRTr?_rZh=+Q+m)N~Nr)*Fnb7fc%|w|^@vyQJJzhzyw)Pa<$Fzz;(LX< zdObO2P7Af=SEmMxz6M0)emHrc;(0V#U0^7mpF(W+2liPIjPU}!-_jwvzBb#W{}l5ht$B zE~WD4!r3#M^F6NAo-5?BJLVgu)OG6c;}5guVhLKP=7vd1m3^-LyC^ajxtbC*6Lk}K zrwy|F2Vx3oP+^4Ti>DYQ+X&$nT=RkDK4EUMj31E{RI84h%4+I&!z~RMZ#u1i>rrc+ zv)0y!&M)N;KW^>99Q_6o#Ad$(Dj2}} z^XE@!JWP6#W!F{S^2u$&!Ok46ID-1%{s)`<@=??Jmg>0gR8~o4<%)T;6+_iGE!$ex zFQi!c<>Tp!@Rv6ZzAp+)k$aG9Y3CK=pLEkbXz2OA`p-D*r)0^mo=`NTMNX$q*__9Cac<-*>j0CVHP!`0NT$_y=Fbc9nt+_SG z$l_4xk0DFSIT!E)(X8R*>N??>1o0iiF<`AN6xM8o}w+~86NMI_8EnX34x~Hq_h7vCd=}@fdlhOeVpaLJ? zlR;~*X`^~&lTV*M?dIlYX12*X=|jJT)N%395N%aXtEPnH_Jj?do5`Y-fiFh~pXwu~P=y$hdQgdo%q$Y*yKS%af{82z+Z-%4#XmRO%Wc@~>7pwijdxxg3k$l?2D3Dsg* zW6kNkStsr7N8M!Koe<|>Qw}dt;=P;f@#dR_)CZ+gGW zyFpEoJl5oMRFpq2wEC132OH6Vn%;R+`rGr^*x0Bjt>Z#sU?nZNoyV{GF)xp>cVLti z6&;SP6q0H{*V%yxO^1P3wi0o{ss|ic4ZFHd*Mf2p@s~3dajx&(Tu4KI$Mz|D-|d2~ zw;uHR)*T0X*$q4xvu)Nf!ppj#tz@;B2eBX)w7JcamfW77lRGRfvh{tDvi(^s)pFV( zcN;ZM|Hki)u$@?RHPWO6I`T}-t*ko2Z|||qJl2d6HqeU zvF6s^@O-mve)%i!S<2XbxZy8T7?+T1OTA2O-AFz@Ntb!>#fFyPaBltdnX2l8-p~L5 zIvR~;AcO+;-Tf`#(!uhqUAy*&Q%!t`xSU*lX=#|8r}&yhc_v%W3?|5Ux^!431aCic z>(PP7LKo@o%7d0m6{sNt?KnIKBajpSwzE=~KvkmC2dN03+Bmeof)EVCLrIB-&(7vW zo$wNvxeS9ld*+NdT0*HHuB~bC#*bi+`za=?cHwp|p$%e}6%1eay&$=}FgO6w@&HJ? zg&a->7M7M6PFhw{f>VF--IFT1!Ktj!dYbIXVR^aFyXF+VFA};ycjp{vPtD<4BjZeV zYtr-=XUQVzRz);K7Jb6kkD7Pj0U~BV#iy z!ELrN@7=3PyuWSa>f=x@w#PJSDCY<9?EC`f4SASu7f7G`D2BrGI_(sZYPgeYsi>zt zYoOh{mC9J2l*CUTHVQ;C%4mnML%yp>h?qXCz5~3JeZbiK8x>>!gt;!1>GYRrtEmo zL$1(R-tmFOaPr!y^p?3U$CppoUlrK_i{;O*DD^-!@@u=1Gsw#k$;l%Pzru^xXFzH1 z1iMYGeCW*~$oPPii2)4@=UmFo&E+La*)t9?ZrI2(jw&)9E)FQKGB|52#-k&qWAG*> zqu%{k%}m48MHp$!X?LNA-e_J)8I?>)mg=1tDg zq`@|Yl~@S|fDX8vme7=cNoa-OOg>)pbCN4KsFa101O1M+erl8Xg=!l(QsjL_o?y{- zc-k|0jxmojv+YvSqoSfRGbcmCoT)rV$yHy+`xIV?3M~wzxAGK(lIb5JhRzs>YTVu> zv6O3d8#6Mic#+}g;M*#7FOh|s0%vy5jrf_vbe`nKRIaw8hE7-bigb^QoHN)WWcu*Z zph?vYK2`l_4JU0-Pr*7Y1^wy+7y*Ic7}JC>`5ENH^m@D4 z%AcbXNj{4$5)AtL6l7qc_evu0Fk`&RrWw4TG2sj^?F>oUfa1IaW>kZkKkE+N$ z@>K4WG5juV1X!S#aOd zcp|Rm7N1&`c+4YD$#%o?xb=&ci#i?GPvFhI@{%Spbzju8>;h`Ldo+G z+t_#l-uKkhj@iRF>V;7OyAtCLeF;B#vV851vLjDoyR|oV9FJr7aWG%GdbQTZ4xhP3 z4w++=QQTnvD4&MjUOigi!|{_|=d&LV7!FTEo?HPqA=E`&RClij^@XUG?eq%YDfgl{fC zPfw-O4U9x1i*2?Yt1ZiZEpAkGF}&C9W?|BIGTUkeG$TYUb;_F%OFzD|?AcLie>J7l z^OtotJW3!trXH6)Ep4{JXecE?igjG-*+$pJ83Og@#{}YESZvQyW%AvK5i{I5-+2ek zf9ONu*&{Uz9$B0Wx#jep6SgIZN)*GAm&%29NL@T4(Rr4MlEXwXIXs?mlHxL`)V0t$z zRF_0`c)e_ATvx@*x2F$wei~PZ;4X@YC@Qv2wsEznVTpKkV`I{#Wgp{@$seKhJUpUZ zeepj3sbS+95hck&QEV0ks!s6pYQmnlHJmJ+eNAE$)$#umv zX=my8YR79XhPSyjG$+jaaIDzRujgZQ3~BAThg(*P>=&~p(c=q;M}4igPu%k*yS6&o z7H)i|>tOD*p*8@TTN9@uB+xv3%)b*Vy9K4xxMDl#r z@v(9tJr*Oa=%{D;(m_;8(maU%jaKPaR+!59u`ai$zj@?XO!UoqF6FSUByuo2V>l%4 zOX*V6jrA;TSCq$-1kZ41&dY5X=w84tpjw%lShi|sQH6{5BM+lRKh`|_Xy`Rc`!=q`uGxuCB)kl3m;$s|0=8`l7QFxXam78$97}DHf%buc_SMd5qb9kQv`@`mYbKk6 z$Z|%akM|11Eb!*2nK1s+>^R^1sA#)P^5lJfz0>CDr4CU}Z{A5i`0%UZZBPCsc)8?R<7A_vd}7X zTj$eP{Gny{YH*Wx>0X;Gl&xeH9XonmRiB~2A=fQQ6Y(FrHnlrnpGw$# zr6ss;m5wjnU54gpz%}%FOX6owof#D=^z68s=PTJg>sPOo;-(PKC^zN>VxnbxIc7Z%(;4!!D2P_#!O3bB=c!Xt+ z8c)3%%j>3qmAuhbcUb)|(cM*%%`Jz}VJZ$Y$Z5%I!2-P2H>xu8S?m)ZV_J93++w{+6WyQ4JPn(PBtC`rCn>vYUIh!~U|36@B zY-uj0XKm(WwSKG2Hu3dh`^~K_t(?|x72kpXC|Wx?s+&9Pv9~>KZ)a}jw0_5Wu|4*u z>>adD8=IPoDVe)io0@CxQxw~4eagw)K}>0nwvxH2y_vb#A#*!RyyiAZ>Frx3A)-5d z!OSXVBg>M5dk^eo0W8R}k7Yj#3$vDG4-0S|;vc?d;~(ohR@T|GS=r{!oilF%+kyq` zD5@@8v~0=3MN1d4voGOVvUE8Iz~BXoSFGgXSh>YE@&zix@GIQySSxaXy-?OY`nZYu17B2S}^h?}();Y6g&z(1O#(eyG zHGWR~`q!SAdYmzH*6cZ~bD1?P3ufV$OJ)JfpYeTT+;{n%0Z~UzUdXg;9}78AQ|4l~ zy)r2|bBoS*56^6k&I2Sd52ZUwZJU-DDb?^d2Jb!TXJ!9JMPk@o*!Sb14Z|Bu6?zWs zmk@uZv;6)Y1@p@}Vynb&(C_Uh+g5`&7H?;T#v%fy@ zmkaw}|JHi-%c6I(EG&|e*Y;+;ojdr}Mb>Iv{9~Wg!DC{TewmTqRd0H^$TiF_PgS$1 zsClmHQsi1V%t6(w>{T{$aBPhJQMbEfMyTE96?=;XYqgpeb6%FGSFxVte8Dy%w5?=$ zlyuVKG`+BpmeKRb zgEgNDb>pqySDZ1FZjmT}kjFVb9_dHJ`pWo^m)^w>ScD@Q9%|Jij3 z*MnaZwJNUdH@^^E;j7&gyDdTgAV#VvSEX(yp8au4?9~vhh`j~8^;d7aQff6>rGG_t zL%>z@|G#`gA6|Q#d#+~6Th+10btwo zP+uvty}7sQ|N4i%^<8eoyL+9MnK#crf9d%^Pik~hC)*eA!r>(jyWEP*9sS4Nk+M98 zmJ4f(_5V=nZCB}8cEa(&!;si)YCw76LywXT)R>KJH_y^um35O(zLy>0l9{N#y=-3p z`rFI6jbL>~Gfk3QkB*j` zz2ANC$|<{){GH#DE1z!}WpfoNJMtqrYmw{Pn=iH~M9$_u{m%!+;j0pjmk!VSFAo)7)nk5FVNU}`?G$#l)ZJ#j-)`_ZXtf-m z>l|@k#jiRc(m7fn?2#6?b=$7~_^+!j{_Cdx>mvW#@5DQoiJUvnvQ#rJSE}v|FAGbF z@fhFR$fKSy9zrMIk@jV-V_!GqCVaM}F|K#t#k~LSzxPnhFrAcr@i~HbVv+3T_~nw8 z0Y6l8R(rfldiBLeD!HP#b^MC(o7;|R@>GuQv!7m7UzC<=tQf1~9&^1ysVFYCzo}bX zk((v4J4H#f?0j*>&a<$*FJN&i ztj^jd+m~oR?)71V$GcPhAJQy^9*V7$ENi`We9S7!R%M@d{Fm{wM<>4;o7&tD&JS-> z5Sv)dh}~h>`OV&MKyqlDlJ3dZt+}pAEq>jS>4QVE*Unculxr9&X_5Qj$Vn@Q$vs?0 z_oYTYu{r(Y;E2-U)cVI3&PS^@zg4%~VB$!>mnGzGy!(Y=>yYQ3Zq-2l=IpESsYwsx zgdFzY(;GIah~Tm@c^i8w?8K&+_RBSK{&4~WgIt_E=2F9UpV(S0K0fh$XF3rd%l4gY=K)~eh}8W|Vcx$VS)`_-@8Dr#!hWUGG&TKYJ3i|U}K@A1_l zj#?_Zd$~#;$Zob?$?K4`ac^~9hs=g(ZZEILq^oC*guPuxJ@0HS>6>5#gz~SBjiO0Y zMGUrm{-hV_*}xmOof_>G6ek(AJ+#ejOe#q#){3VfuRW=_hSR~8?Majhm`G%bZg( zNy*7RVr5&+-)l94$2ZCOgCJBuRH(baaKdq*LMw-cgziZRL>UV8*p>Lq6)&{DT3vTz0vf0lk@j8&%a!Q?x9f+t zE(n(Y+qs|p(EQUS{SRkMIX~Rc^9kPzvI@T zAF}@sdv5_2$Fe+%FChsKf)iYVhhV{NvEUv;g8SkcG&m$7!QI^g1XUei)QdXf0|P$I zHS$ONu#NlYQyQ9#UdRigp#5H4j_PEaTj3jSZZnGmRIFI?HpeCVinZJOH5( z7-@}68ct$koD0wo-s2J9%o3Cr%~i;}&B28wV^usxGB@sYZk6`PXjxXR!iiGZenPr) zt2OMGhX7E^EF^Y>wp4<&Rg10%yB;M6Jx{C#0?7U{-(%76~n+DD_^dpTOd+<5%@mC_>b1((FMRx_x zZdg&OkY9Lc+&g?RZ=rTP1?sFNEX)*3+kE5*9K)B)Zk>vwvCdxwwYIWzVIlS<;*Qzt zF`#J|UQDWw_pDiJ2o&|&=@>hzlR1Kd70wYFjZCpN3|4N3=bS2bYJ|UioglaPIM~IL z2t#pmhOgEg{^uc)FVbtEA@6zW$Qs^Qv;j?Ld~0C2bS0>)w{&l|Xz0RBufI1(Ez@Z{ z_FRPN70rTuM8|-`ebDF|!_5=RhW>-^xAFskijY+B{WF+lS8;iKe8vVhpg8UU3&M0K zCOZ@4cI@^`>&G0Dv;OEIPlGv$(<$>skj@!`skaFzY;CWnf3o+se@Xt;HTR>=pP-x5 zUHPX+x8|ja#n0iZnp!j=BF{Aq=;6J(r?X5KdXFl*@Z!{m zBC$Q*_t7ilUJ$5amKYF;zZda)os0agw)OrA+rsv^nMJqpQTA8?31`cjN4j&ui%7!+9fhkmdcW*5=NZH-W6JH$Du#B)aajY(>K9sVIIb6k5 zT-_91;i`1*YtSe*-QZnUt_r*vsvmR$3GhyS=Cyb3II?%{{?pBT1+npL<0eHAShPa_ znCM1N5YL9eVv8pd@xrH|(AB5#o6n zTP$0|0H8JZ+&p2y;9}(R9H>$7f;V9nYa@wWA2Kyf;jDd0rJhJogFYrwWbtv>viy31%1sjh^YLw?zt&m5e)gRae8UO+$yb zeDqxu;Ii{>)ki^k+*Z6$RsC_r#%fqLte>C3C4ks5EUhxyB+GdD+;o-gu#^o{v!*@wkXyaWq|D3!iJa4J-e* zXM)J1)1@8ZO_&m^+`|VbehN{}8D>HGpftO8ty_sGYN5Ph3o1UIUYaHU1gatMcI+na zO4a!}Lu9gN!Tg+HnUuqt;T}0FcYH#~>8?TRm>I7bVO#H_W@@$NyS$gvszXO?rcVWq zhaIp-m&>~_jvV!i8r)E1o^p8Bt>7t=o$>Mm0LS$Yy5XQym+pl}_^-Pao036=J)Hp;9TYYBOCqG}%R^RmT3xsqeRk1Y?k++;R5{Qld$Z zsld+xwlIn+fjMJPbV|e zLoJ_pZ-d==W`%)suSV$Zdd1>*gU)o1+M!?88iYl|3YTm>NzBsDS+T5G#?G4=sKT`- z>C-Z4$iv>fvx2VrjIB6fXeyyJop3Xa8Xx>VyQob5eIJ)h*Q8zh@!`VJAV=(z=Nan? zo*C=E2@-H^_(^G$@=Z1Y{~(Yq&glOqz?7iC&%{QnSz_%;{DW1S8l?okiqvJDm@2_S ziB$U0SBAeeJLoi#8vDxA6hEC=Vm+2^uWX2GS@hNLN(F%}N0qI-CeQI2C+=Ll$XJRt zVE&{SN-U@Jv_8qz+*HH1g!6E4X-)HS?91t}RC616$D!oBXGh&d5~oM24hNj3ucu99 z1tW5|@N4`y#;1Ol){W9MGhP9@=b7W5RJt+*&%qVL5W{Ze+1LmZ^|`?F{k)iNv~Z6K zQY`fG$3XziqL1Y&RsDkLt#hp{&upczz=(&XAkph*s}Bn7)yJDBGh5iW7$)vuq5J3(=t==YhGE)@-S{To;x?_JJuROBe~A%ssoXm!~A%mugzM@lk1l*mYR7< zK2>Oq1<~(YHKi>zeyjsm)aJ0WfA~uH+YgLcrmAcZpj^HmT`tWO;~V-fe=+a}gP6{TVrMJml8x<+H@I^MY0P+I(3~d0Zisx?2=AB&Fts=-`V*JC}*=-!vpl1hW9ty zUEPvw8L&+nngUb$a_KJtk5XwZhrEVG0(1HlrSy1CkMG{JhU-kp4{Y2>v0Je(->LL zf{&B(OORas<7>|7QFgb z@ndySMRDEk;OuK>H@2SWSHDH&W4zC4Cv$&uVA&hR@|bF<|H|7bA$$Ox zxY}_k(wQul4)}%L4*O=^i-;@bMl!G&udh9hbiCccmK(V_z20mVr4IHBgX|+1XA9ez zm2l_gCUB|OSD-n(>vT3Y+`JgdFp*M8j5$6q;lYoaDz)3E#Zv}$6CvNK1Ftyl7p$EA z{!jo#L$r&ifVHz%*~|L-ofa07KKstBJn1GUXAsDsCNix#$W}#cy<9v*hC8p?4)t*$xRAV0rdAt8g4*{{7 zjHPKuFeE){AjpKDcWZIaA`_L&zVs#fzK@)yVr2Fm}wm z3hf;9FK<-U#9_=KY2vhDt&8|NSh zmCD+gXZOw}0M~%s1#btmK?7ecm#tZGvME>xe%xR&IoSW!b$ZP!PfR0;I^cEWj@$4d zDAjS{dFPHvFd_DaL2RJry_xUund|IDt5}ND}-aC(ur&f~XYnwO^^7e8kDl7j^{u}Vw zoCk2j5wD%#x)?kz5we`hdvS_Q{r()Tu~ebJv}5Ezn{+!5vvbU<--(#3qCiCcQ#g-v zT}Wc}t=EH;TVgP$3=k#oprq1{M1HyPowNkhew(cI`)dh}6@I{Z+%L0L$W-0-_J{A4+w$2R zNlqpaeVd_cPJX&s+M?TxYxzyQsT8ZBBcF(5AqmU`wi{wc{kuC|im~|C#Lp5-zz467 zd_HL&*G$o}dE>!iA#S9}Vk*8}+pTR=JaDZzT|TMyDU~D!GZ`)OiE~5CzB&c`$ zyvo=;mD0RVRo!G6u1@?sJZ;3m*^2y2Jn7ZN&;!3xJixcC{Ssip&M>A_xi)YKpd%!< zj-cUTM&VSUq_}T9{tmJ`Kb)kyWEd2LGTm62K%|?UYG$u zrDT>*C+YnxLj?QN5nfr~RKodP47aywj5ia{rCoUMULpAW zJfzPfHSLb_#)1&+(V%0QHpF9~KsD1`qflYz5vlSwuk6XmO31E4?vSZcF2Uj_nVwxY z@|1(;F1IUeN{s>@m+@)(wA&;|TK4Qx6!4#~t#%qai*}Y#TW=9%6!p)sGCA-P%p=d! zj?r_u!j3J&@Y@>gUVG z-JC^JEMNj3h7v7s`J(GmhU3nWZyA5{{3U?-QJGSsw4|t$&>7tHyQ=EVKtzj(4085_{qXEAIWupO#0Yl9Hw%N)tN)VrJaXR9nf z5o4Q~+`RB*BN!W36^vYE1c_?DBd9ws@Gqpv?%FXwj!Kt^0lI^*6 zUu^l-hcmSl%h^|*Z&pIdDUqWy=k3)X2Wvb<742n|X>^XrJpOKy!-z`Xc=-OSyoLoe z9Bcz*hHGnVobPQN9J<-4V+CAvaP^wyu9BKo=6id`8}7;MdEC-bWx-{_f0VjWr&bX0 z;7RfGVyHSj%zJSn8(6d^%P2Ikw<~3k)Uh}9oIi3-;g)XMhGlr>@Lj|EDwlxWhbmMS zz%<68LMu#el)J}59`4^+FgHr)LOy(;U^Z&>as~WEg^L&RK*7