From 002f6273d67c6773c996c93d93e1580a84c43cdd Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Thu, 14 Jan 2016 21:59:22 +0000 Subject: [PATCH] [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257815 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonBitSimplify.cpp | 5 ++--- test/CodeGen/Hexagon/bit-extractu-half.ll | 13 +++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) create mode 100644 test/CodeGen/Hexagon/bit-extractu-half.ll diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp index ab28120ba27..8ded94d062a 100644 --- a/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1966,11 +1966,10 @@ bool BitSimplification::genExtractHalf(MachineInstr *MI, NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR) .addReg(L.Reg, 0, L.Sub); - } else if (!L.Low && Opc != Hexagon::S2_extractu) { + } else if (!L.Low && Opc != Hexagon::S2_lsr_i_r) { NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); - BuildMI(B, MI, DL, HII.get(Hexagon::S2_extractu), NewR) + BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR) .addReg(L.Reg, 0, L.Sub) - .addImm(16) .addImm(16); } if (NewR == 0) diff --git a/test/CodeGen/Hexagon/bit-extractu-half.ll b/test/CodeGen/Hexagon/bit-extractu-half.ll new file mode 100644 index 00000000000..fec4a02d926 --- /dev/null +++ b/test/CodeGen/Hexagon/bit-extractu-half.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Pick lsr (in bit-simplification) for extracting high halfword. +; CHECK: lsr{{.*}}#16 + +define i32 @foo(i32 %x) #0 { + %a = call i32 @llvm.hexagon.S2.extractu(i32 %x, i32 16, i32 16) + ret i32 %a +} + +declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32) #0 + +attributes #0 = { nounwind readnone } + -- 2.11.0