From 015c23600a4dc9844c4a6195a343604bcc88ba01 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 23 Mar 2017 02:06:04 -0400 Subject: [PATCH] drm/amdgpu/gfx8: reduce the functon params for mpq setup MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Everything we need is in the ring structure. No need to pass all the bits explicitly. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 0fc29959f412..d66a061bfbe7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4691,12 +4691,11 @@ static void gfx_v8_0_map_queue_enable(struct amdgpu_ring *kiq_ring, udelay(50); } -static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, +static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring, struct vi_mqd *mqd, - uint64_t mqd_gpu_addr, - uint64_t eop_gpu_addr, - struct amdgpu_ring *ring) + uint64_t eop_gpu_addr) { + struct amdgpu_device *adev = ring->adev; uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; uint32_t tmp; @@ -4737,8 +4736,8 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, mqd->cp_hqd_pq_wptr = 0; /* set the pointer to the MQD */ - mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc; - mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr); + mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); /* set MQD vmid to 0 */ tmp = RREG32(mmCP_MQD_CONTROL); @@ -4811,10 +4810,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_device *adev, return 0; } -static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev, - struct vi_mqd *mqd, - struct amdgpu_ring *ring) +static int gfx_v8_0_kiq_init_register(struct amdgpu_ring *ring, + struct vi_mqd *mqd) { + struct amdgpu_device *adev = ring->adev; uint32_t tmp; int j; @@ -4903,8 +4902,7 @@ static int gfx_v8_0_kiq_init_register(struct amdgpu_device *adev, } static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, - struct vi_mqd *mqd, - u64 mqd_gpu_addr) + struct vi_mqd *mqd) { struct amdgpu_device *adev = ring->adev; struct amdgpu_kiq *kiq = &adev->gfx.kiq; @@ -4925,9 +4923,9 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v8_0_mqd_init(adev, mqd, mqd_gpu_addr, eop_gpu_addr, ring); + gfx_v8_0_mqd_init(ring, mqd, eop_gpu_addr); if (is_kiq) - gfx_v8_0_kiq_init_register(adev, mqd, ring); + gfx_v8_0_kiq_init_register(ring, mqd); vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); @@ -4945,7 +4943,7 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring, if (is_kiq) { mutex_lock(&adev->srbm_mutex); vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); - gfx_v8_0_kiq_init_register(adev, mqd, ring); + gfx_v8_0_kiq_init_register(ring, mqd); vi_srbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); } @@ -4975,8 +4973,7 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); if (!r) { r = gfx_v8_0_kiq_init_queue(ring, - (struct vi_mqd *)ring->mqd_ptr, - ring->mqd_gpu_addr); + (struct vi_mqd *)ring->mqd_ptr); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -5000,8 +4997,7 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); if (!r) { r = gfx_v8_0_kiq_init_queue(ring, - (struct vi_mqd *)ring->mqd_ptr, - ring->mqd_gpu_addr); + (struct vi_mqd *)ring->mqd_ptr); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } -- 2.11.0