From 01ff7b72c9e534c9d6a236c42ddde519cd6eecc0 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 17 May 2018 16:47:30 +0000 Subject: [PATCH] [X86] Split WriteCMOV + WriteCMOV2 scheduler classes Handle SNB+ targets which treat CMOVA/CMOVBE specially due to partial EFLAGS handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332626 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrCMovSetCC.td | 39 +++++++++++++++++---------------- lib/Target/X86/X86SchedBroadwell.td | 9 +------- lib/Target/X86/X86SchedHaswell.td | 11 ++-------- lib/Target/X86/X86SchedSandyBridge.td | 15 +------------ lib/Target/X86/X86SchedSkylakeClient.td | 13 +++-------- lib/Target/X86/X86SchedSkylakeServer.td | 13 +++-------- lib/Target/X86/X86Schedule.td | 3 ++- lib/Target/X86/X86ScheduleAtom.td | 1 + lib/Target/X86/X86ScheduleBtVer2.td | 1 + lib/Target/X86/X86ScheduleSLM.td | 1 + lib/Target/X86/X86ScheduleZnver1.td | 1 + 11 files changed, 36 insertions(+), 71 deletions(-) diff --git a/lib/Target/X86/X86InstrCMovSetCC.td b/lib/Target/X86/X86InstrCMovSetCC.td index 2240e85de8e..eda4ba5ae6f 100644 --- a/lib/Target/X86/X86InstrCMovSetCC.td +++ b/lib/Target/X86/X86InstrCMovSetCC.td @@ -14,9 +14,10 @@ // CMOV instructions. -multiclass CMOV opc, string Mnemonic, PatLeaf CondNode> { +multiclass CMOV opc, string Mnemonic, X86FoldableSchedWrite Sched, + PatLeaf CondNode> { let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - isCommutable = 1, SchedRW = [WriteCMOV] in { + isCommutable = 1, SchedRW = [Sched] in { def NAME#16rr : I opc, string Mnemonic, PatLeaf CondNode> { } let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", - SchedRW = [WriteCMOVLd, ReadAfterLd] in { + SchedRW = [Sched.Folded, ReadAfterLd] in { def NAME#16rm : I opc, string Mnemonic, PatLeaf CondNode> { // Conditional Moves. -defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>; -defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>; -defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>; -defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>; -defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>; -defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>; -defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>; -defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>; -defm CMOVS : CMOV<0x48, "cmovs" , X86_COND_S>; -defm CMOVNS : CMOV<0x49, "cmovns", X86_COND_NS>; -defm CMOVP : CMOV<0x4A, "cmovp" , X86_COND_P>; -defm CMOVNP : CMOV<0x4B, "cmovnp", X86_COND_NP>; -defm CMOVL : CMOV<0x4C, "cmovl" , X86_COND_L>; -defm CMOVGE : CMOV<0x4D, "cmovge", X86_COND_GE>; -defm CMOVLE : CMOV<0x4E, "cmovle", X86_COND_LE>; -defm CMOVG : CMOV<0x4F, "cmovg" , X86_COND_G>; +defm CMOVO : CMOV<0x40, "cmovo" , WriteCMOV, X86_COND_O>; +defm CMOVNO : CMOV<0x41, "cmovno", WriteCMOV, X86_COND_NO>; +defm CMOVB : CMOV<0x42, "cmovb" , WriteCMOV, X86_COND_B>; +defm CMOVAE : CMOV<0x43, "cmovae", WriteCMOV, X86_COND_AE>; +defm CMOVE : CMOV<0x44, "cmove" , WriteCMOV, X86_COND_E>; +defm CMOVNE : CMOV<0x45, "cmovne", WriteCMOV, X86_COND_NE>; +defm CMOVBE : CMOV<0x46, "cmovbe", WriteCMOV2, X86_COND_BE>; +defm CMOVA : CMOV<0x47, "cmova" , WriteCMOV2, X86_COND_A>; +defm CMOVS : CMOV<0x48, "cmovs" , WriteCMOV, X86_COND_S>; +defm CMOVNS : CMOV<0x49, "cmovns", WriteCMOV, X86_COND_NS>; +defm CMOVP : CMOV<0x4A, "cmovp" , WriteCMOV, X86_COND_P>; +defm CMOVNP : CMOV<0x4B, "cmovnp", WriteCMOV, X86_COND_NP>; +defm CMOVL : CMOV<0x4C, "cmovl" , WriteCMOV, X86_COND_L>; +defm CMOVGE : CMOV<0x4D, "cmovge", WriteCMOV, X86_COND_GE>; +defm CMOVLE : CMOV<0x4E, "cmovle", WriteCMOV, X86_COND_LE>; +defm CMOVG : CMOV<0x4F, "cmovg" , WriteCMOV, X86_COND_G>; // SetCC instructions. diff --git a/lib/Target/X86/X86SchedBroadwell.td b/lib/Target/X86/X86SchedBroadwell.td index 5e16d6558bf..743279dca31 100755 --- a/lib/Target/X86/X86SchedBroadwell.td +++ b/lib/Target/X86/X86SchedBroadwell.td @@ -126,6 +126,7 @@ def : WriteRes { let Latency = 3; } // Integer multiplication, h def : WriteRes; // LEA instructions can't fold loads. defm : BWWriteResPair; // Conditional move. +defm : BWWriteResPair; // // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. @@ -686,7 +687,6 @@ def: InstRW<[BWWriteResGroup20], (instrs CWD)>; def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>; def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8", "ADC8ri", - "CMOV(A|BE)(16|32|64)rr", "SBB8i8", "SBB8ri", "SET(A|BE)r")>; @@ -1130,13 +1130,6 @@ def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> { } def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>; -def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>; - def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> { let Latency = 7; let NumMicroOps = 5; diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index 11084143c17..2825ec29c1b 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -123,6 +123,7 @@ defm : HWWriteResPair; defm : HWWriteResPair; defm : HWWriteResPair; // Conditional move. +defm : HWWriteResPair; // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. def : WriteRes { @@ -1293,8 +1294,7 @@ def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,2]; } -def: InstRW<[HWWriteResGroup59], (instregex "CMOV(A|BE)(16|32|64)rr", - "RCL(8|16|32|64)r1", +def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1", "RCL(8|16|32|64)ri", "RCR(8|16|32|64)r1", "RCR(8|16|32|64)ri")>; @@ -1325,13 +1325,6 @@ def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", "IST_F(16|32)m")>; -def HWWriteResGroup65 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[HWWriteResGroup65], (instregex "CMOV(A|BE)(16|32|64)rm")>; - def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { let Latency = 9; let NumMicroOps = 5; diff --git a/lib/Target/X86/X86SchedSandyBridge.td b/lib/Target/X86/X86SchedSandyBridge.td index d35587f2ed1..6e7e2be2b60 100644 --- a/lib/Target/X86/X86SchedSandyBridge.td +++ b/lib/Target/X86/X86SchedSandyBridge.td @@ -123,6 +123,7 @@ defm : SBWriteResPair; defm : SBWriteResPair; defm : SBWriteResPair; // Conditional move. +defm : SBWriteResPair; // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. def : WriteRes { @@ -658,13 +659,6 @@ def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { } def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; -def SBWriteResGroup26 : SchedWriteRes<[SBPort05,SBPort015]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup26], (instregex "CMOV(A|BE)(16|32|64)rr")>; - def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { let Latency = 3; let NumMicroOps = 3; @@ -964,13 +958,6 @@ def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { } def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>; -def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup82], (instregex "CMOV(A|BE)(16|32|64)rm")>; - def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { let Latency = 8; let NumMicroOps = 5; diff --git a/lib/Target/X86/X86SchedSkylakeClient.td b/lib/Target/X86/X86SchedSkylakeClient.td index e8e439bb377..dd09aa4ad83 100644 --- a/lib/Target/X86/X86SchedSkylakeClient.td +++ b/lib/Target/X86/X86SchedSkylakeClient.td @@ -124,7 +124,8 @@ defm : SKLWriteResPair; def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. -defm : SKLWriteResPair; // Conditional move. +defm : SKLWriteResPair; // Conditional move. +defm : SKLWriteResPair; // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. def : WriteRes { @@ -640,8 +641,7 @@ def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKLWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr", - "ROL(8|16|32|64)r1", +def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1", "ROL(8|16|32|64)ri", "ROR(8|16|32|64)r1", "ROR(8|16|32|64)ri", @@ -1188,13 +1188,6 @@ def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm", "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>; -def SKLWriteResGroup93 : SchedWriteRes<[SKLPort23,SKLPort06]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SKLWriteResGroup93], (instregex "CMOV(A|BE)(16|32|64)rm")>; - def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; diff --git a/lib/Target/X86/X86SchedSkylakeServer.td b/lib/Target/X86/X86SchedSkylakeServer.td index fc4681dd55f..1560ab2f50d 100755 --- a/lib/Target/X86/X86SchedSkylakeServer.td +++ b/lib/Target/X86/X86SchedSkylakeServer.td @@ -124,7 +124,8 @@ defm : SKXWriteResPair; def : WriteRes { let Latency = 3; } // Integer multiplication, high part. def : WriteRes; // LEA instructions can't fold loads. -defm : SKXWriteResPair; // Conditional move. +defm : SKXWriteResPair; // Conditional move. +defm : SKXWriteResPair; // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. def : WriteRes { @@ -673,8 +674,7 @@ def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> { let NumMicroOps = 2; let ResourceCycles = [2]; } -def: InstRW<[SKXWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr", - "ROL(8|16|32|64)r1", +def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1", "ROL(8|16|32|64)ri", "ROR(8|16|32|64)r1", "ROR(8|16|32|64)ri", @@ -1417,13 +1417,6 @@ def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", "VPERMT2W256rr", "VPERMT2Wrr")>; -def SKXWriteResGroup98 : SchedWriteRes<[SKXPort23,SKXPort06]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SKXWriteResGroup98], (instregex "CMOV(A|BE)(16|32|64)rm")>; - def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index b74748c6f0f..c8afbe688f9 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -119,7 +119,8 @@ defm WriteBitScan : X86SchedWritePair; // Bit scan forward/reverse. defm WritePOPCNT : X86SchedWritePair; // Bit population count. defm WriteLZCNT : X86SchedWritePair; // Leading zero count. defm WriteTZCNT : X86SchedWritePair; // Trailing zero count. -defm WriteCMOV : X86SchedWritePair; // Conditional move. +defm WriteCMOV : X86SchedWritePair; // Conditional move. +defm WriteCMOV2 : X86SchedWritePair; // Conditional (CF + ZF flag) move. def WriteFCMOV : SchedWrite; // X87 conditional move. def WriteSETCC : SchedWrite; // Set register based on condition code. def WriteSETCCStore : SchedWrite; diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 26d7405f1a6..9549b7cfd71 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -93,6 +93,7 @@ defm : AtomWriteResPair; // NOTE: Doesn't exist on Atom. defm : AtomWriteResPair; +defm : AtomWriteResPair; defm : X86WriteRes; // x87 conditional move. def : WriteRes; diff --git a/lib/Target/X86/X86ScheduleBtVer2.td b/lib/Target/X86/X86ScheduleBtVer2.td index 824db47a48e..acff3db3a0a 100644 --- a/lib/Target/X86/X86ScheduleBtVer2.td +++ b/lib/Target/X86/X86ScheduleBtVer2.td @@ -173,6 +173,7 @@ defm : JWriteResIntPair; defm : JWriteResIntPair; defm : JWriteResIntPair; // Conditional move. +defm : JWriteResIntPair; // Conditional (CF + ZF flag) move. defm : X86WriteRes; // x87 conditional move. def : WriteRes; // Setcc. def : WriteRes; diff --git a/lib/Target/X86/X86ScheduleSLM.td b/lib/Target/X86/X86ScheduleSLM.td index 05c7af403f9..aaf62b11ef8 100644 --- a/lib/Target/X86/X86ScheduleSLM.td +++ b/lib/Target/X86/X86ScheduleSLM.td @@ -102,6 +102,7 @@ defm : SLMWriteResPair; defm : SLMWriteResPair; defm : SLMWriteResPair; +defm : SLMWriteResPair; defm : X86WriteRes; // x87 conditional move. def : WriteRes; def : WriteRes { diff --git a/lib/Target/X86/X86ScheduleZnver1.td b/lib/Target/X86/X86ScheduleZnver1.td index 62d5d90c4b3..743bf015f6e 100644 --- a/lib/Target/X86/X86ScheduleZnver1.td +++ b/lib/Target/X86/X86ScheduleZnver1.td @@ -159,6 +159,7 @@ defm : ZnWriteResPair; defm : ZnWriteResFpuPair; defm : ZnWriteResPair; +defm : ZnWriteResPair; def : WriteRes; def : WriteRes; -- 2.11.0