From 0221da1e5dda9de470490fdd6eb8ae7c8c5ebda7 Mon Sep 17 00:00:00 2001 From: yujiro_kaeko Date: Sat, 5 Nov 2011 11:20:23 +0900 Subject: [PATCH] =?utf8?q?vga=5Fgen=20(=E3=83=A2=E3=83=8E=E3=82=AF?= =?utf8?q?=E3=83=AD=E7=89=88)=E5=86=8D=E6=A7=8B=E6=88=90=20=E3=83=90?= =?utf8?q?=E3=82=B0=E5=8F=96=E3=82=8A=E5=89=8D=E3=83=90=E3=83=83=E3=82=AF?= =?utf8?q?=E3=82=A2=E3=83=83=E3=83=97=E3=80=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Change-Id: Ief4dfed70a09120e675025123cda68dffb6e586d --- VGADisplay/src/vga_gen.nsl | 250 +++++++++++++++++++-------------------------- 1 file changed, 104 insertions(+), 146 deletions(-) diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl index 0e597bb..31339de 100644 --- a/VGADisplay/src/vga_gen.nsl +++ b/VGADisplay/src/vga_gen.nsl @@ -1,5 +1,5 @@ /** -* VGA@Signal Generate Circuit +* Video Graphic Array@Signal Generate Circuit * Module name is "vga_generate" * @auther Yujiro Kaneko * @version 1.2 @@ -20,137 +20,128 @@ #define VCNT_1SEC 26'd25000000 declare vga_gen interface { - input i_clk50M ; // 50MHz main clock + input i_clk50 ; // 50MHz main clock + input i_fifo_fst ; // FIFO rst input m_clock ; input p_reset ; - output o_vsync ; - output o_hsync ; - output o_vga_r[4] ; - output o_vga_g[4] ; - output o_vga_b[4] ; - - input i_wrdata1[8] ; - input i_wrdata2[8] ; - input i_wradrs1[8] ; - input i_wradrs2[8] ; - - func_in fi_fifo1_write( i_wradrs1, i_wrdata1 ) ; - func_in fi_fifo2_write( i_wradrs2, i_wrdata2 ) ; - - output outled ; - output o_vcnt[10] ; + output o_vsync ; // Vertical Sync + output o_hsync ; // Horizontal Hync + output o_vga_r[4] ; // VGA RED + output o_vga_g[4] ; // VGA GREEN + output o_vga_b[4] ; // VGA BLUE + output o_dummy_rgb[3] ; // VGA dummy signal + output o_vcnt[10] ; // V sync Count + + /* FIFO write terminal */ + input i_wrdata[8] ; + func_in fi_fifo_write( i_wrdata ) ; + + /* FIFO terminal */ + output o_rdack ; + + output o_led ; } module vga_gen { - func_self fs_fifo1_read() ; - func_self fs_fifo2_read() ; - - func_self fs_fifo1_exec() ; - func_self fs_fifo2_exec() ; + func_self fs_fifo_read() ; // FIFO read terminal + wire w_rddata[8] ; // FIFO read wire + func_self fs_fifo_ack(w_rddata) ; + func_self fs_initialize() ; - func_self fs_fifo1_reset() ; - func_self fs_fifo2_reset() ; - - reg r_bit_number[5] = 0 ; + reg r_data1[8] = 0 ; + reg r_data2[8] = 0 ; + reg r_reg_cnt = 0 ; + reg r_bit_cnt[3] = 0 ; reg r_vsync = 0 ; reg r_hsync = 0 ; reg r_vcnt[10] = 0 ; reg r_hcnt[10] = 0 ; - reg cnt[26] = 0 ; - reg testled = 0 ; + reg r_cnt[26] = 0 ; reg r_outcnt[3] = 0 ; reg r_outclr[7] = 0 ; reg r_vcnt_hld = 0 ; - wire w_rddata1[24] ; - wire w_rddata2[24] ; - - reg r_rdadrs1[8] = 0 ; - reg r_rdadrs2[8] = 0 ; - + reg r_led = 0 ; + reg r_init_flg = 0 ; + reg r_trg[3] = 0 ; + vga_ram u_FIFO ; { - /* FIFO assign */ - u_FIFO.i_clk50 = i_clk50M ; - u_FIFO.i_clk100 = m_clock ; - - u_FIFO.i_we1 = fi_fifo1_write ; - u_FIFO.i_we2 = fi_fifo2_write ; - u_FIFO.i_wrdata1 = i_wrdata1 ; - u_FIFO.i_wrdata2 = i_wrdata2 ; - u_FIFO.i_wradrs1 = i_wradrs1 ; - u_FIFO.i_wradrs2 = i_wradrs2 ; - u_FIFO.i_re1 = fs_fifo1_read ; - u_FIFO.i_re2 = fs_fifo2_read ; - w_rddata1 = u_FIFO.o_rddata1 ; - w_rddata2 = u_FIFO.o_rddata2 ; - u_FIFO.i_rdadrs1 = r_rdadrs1 ; - u_FIFO.i_rdadrs2 = r_rdadrs2 ; - o_vcnt = r_vcnt ; - - r_vcnt_hld := r_vcnt[0] ; - - /* LED test */ - outled = testled ; + r_trg := { r_trg[1:0], 0b1 } ; + if(r_trg == 0b011) fs_initialize() ; + + /* VGA Generate Node */ o_vsync = r_vsync ; o_hsync = r_hsync ; + /* FIFO assign */ + u_FIFO.i_clk50 = i_clk50 ; + u_FIFO.i_clk25 = m_clock ; + o_rdack = u_FIFO.o_rdack ; + u_FIFO.i_we = fi_fifo_write ; + u_FIFO.i_wrdata = i_wrdata ; + u_FIFO.i_rst = i_fifo_fst ; + u_FIFO.i_re = fs_fifo_read ; + + /* TEST LED cnt routine */ + o_led = r_led ; + any { - ~r_vcnt_hld & r_vcnt[0] : { - fs_fifo1_reset() ; - } - r_vcnt_hld & ~r_vcnt[0] : { - fs_fifo2_reset() ; - } - } - - /* test led count routine */ - any { - cnt == VCNT_1SEC : { - cnt := 0 ; - testled := ~testled ; + r_cnt == VCNT_1SEC : { + r_cnt := 0 ; + r_led := ~r_led ; } else : { - cnt++ ; + r_cnt++ ; } } - /* vsync hsync generate routine */ - if( r_hcnt < H_BACKP_MAX ) { - r_hcnt++ ; - } else { - r_hcnt := 0 ; - if( r_vcnt < V_BACKP_MAX ) { - r_vcnt++ ; + /* VSync & HSync@¶¬ƒ‹[ƒ`ƒ“ */ + if(r_init_flg) { + if( r_hcnt < H_BACKP_MAX ) { + r_hcnt++ ; } else { - r_vcnt := 0 ; + r_hcnt := 0 ; + if( r_vcnt < V_BACKP_MAX ) { + r_vcnt++ ; + } else { + r_vcnt := 0 ; + } } } - // HACTMAX640 VACTMAX480 + + // HACTMAX640 VACTMAX480 ƒJƒ‰[•`‰æƒGƒŠƒA if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) { - any { - ~r_vcnt[0] : fs_fifo1_exec() ; - r_vcnt[0] : fs_fifo2_exec() ; - } - - any { - r_bit_number == 5'd23 : { - r_bit_number := 0 ; + // ƒf[ƒ^ƒoƒbƒtƒ@‰^—pƒJƒEƒ“ƒ^iƒeƒXƒg—pj + if( r_init_flg ) { + r_bit_cnt++ ; // ƒrƒbƒgƒJƒEƒ“ƒgƒAƒbƒv + + // ƒŒƒWƒXƒ^ƒJƒEƒ“ƒg”½“] + if(r_bit_cnt==0b111) { + r_reg_cnt := ~r_reg_cnt ; + fs_fifo_read() ; + } + + // FIFO“ǂݏo‚µ’lƒoƒbƒtƒ@ƒŠƒ“ƒO + if( fs_fifo_ack ) { any { - ~r_vcnt[0] : fs_fifo1_read() ; - r_vcnt[0] : fs_fifo2_read() ; + ~r_reg_cnt : r_data2 := w_rddata ; + r_reg_cnt : r_data1 := w_rddata ; } } - else : { - r_bit_number++ ; + + any { + r_reg_cnt == 0b0 : o_dummy_rgb = 3#(r_data1[r_reg_cnt]) ; + // (r_reg_cnt == 0b1) + else : o_dummy_rgb = 3#(r_data2[r_reg_cnt]) ; } } - + + /* ƒJƒ‰[ƒo[ì¬ */ -/* if( r_outcnt < 3'd4 ) { r_outcnt++ ; } else { @@ -160,23 +151,20 @@ module vga_gen { if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ; else o_vga_b = 0 ; - if( ~r_outclr[5]) o_vga_r = ~r_outclr[3:0] ; else o_vga_r = 0 ; - if( ~r_outclr[6]) o_vga_g = ~r_outclr[3:0] ; else o_vga_g = 0 ; -*/ + } else { + // ƒJƒ‰[•`‰æ‚µ‚È‚¢ƒGƒŠƒA any { r_hcnt == H_ACT_MAX : { - /* VGA@null@ */ o_vga_r = 0 ; o_vga_g = 0 ; o_vga_b = 0 ; r_outcnt := 0 ; r_outclr := 0 ; - r_bit_number := 0 ; } r_hcnt == H_FRONTP_MAX : { r_hsync := 0 ; @@ -188,56 +176,26 @@ module vga_gen { } any { - r_vcnt == V_ACT_MAX : { - ; - } - r_vcnt == V_FRONTP_MAX : { - r_vsync := 0 ; - } - r_vcnt == V_SYNC_MAX : { - r_vsync := 1 ; - } + r_vcnt == V_ACT_MAX : ; + r_vcnt == V_FRONTP_MAX : r_vsync := 0 ; + r_vcnt == V_SYNC_MAX : r_vsync := 1 ; } } - func fs_fifo1_exec { - if(w_rddata1[r_bit_number]){ - o_vga_r = 4'b1111 ; - o_vga_g = 4'b1111 ; - o_vga_b = 4'b1111 ; - } else { - o_vga_r = 4'b0000 ; - o_vga_g = 4'b0000 ; - o_vga_b = 4'b0000 ; - } + // VGA Gen initialize command + func fs_initialize seq { + // ƒf[ƒ^ƒoƒbƒtƒ@‚PC‚Q‚ÉFIFO‚Ì’l‚ðŠi”[ + fs_fifo_read() ; + r_data1 := u_FIFO.o_rddata ; + fs_fifo_read() ; + r_data2 := u_FIFO.o_rddata ; + r_init_flg := 1 ; } - func fs_fifo2_exec { - if(w_rddata2[r_bit_number]){ - o_vga_r = 4'b1111 ; - o_vga_g = 4'b1111 ; - o_vga_b = 4'b1111 ; - } else { - o_vga_r = 4'b0000 ; - o_vga_g = 4'b0000 ; - o_vga_b = 4'b0000 ; - - } - } - - func fs_fifo1_read { - r_rdadrs1 := r_rdadrs1 + 8'd3 ; - } - - func fs_fifo2_read { - r_rdadrs2 := r_rdadrs2 + 8'd3 ; + // FIFO read command + func fs_fifo_read seq { + ; + fs_fifo_ack( u_FIFO.o_rddata ) ; } - - func fs_fifo1_reset { - r_rdadrs1 := 8'd0 ; - } - - func fs_fifo2_reset { - r_rdadrs2 := 8'd0 ; - } -} //module end \ No newline at end of file +} +//module end \ No newline at end of file -- 2.11.0