From 028616130d5f0abc8a3b96f28963da51a875024b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 31 Jan 2020 17:01:38 -0800 Subject: [PATCH] target/riscv: Convert MIP CSR to target_ulong The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access. Now that we don't use atomics for MIP we can change this back to a xlen CSR. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8c86ebc109..efbd676edb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); - qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..95de9e58a2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -121,7 +121,7 @@ struct CPURISCVState { target_ulong mhartid; target_ulong mstatus; - uint32_t mip; + target_ulong mip; uint32_t miclaim; target_ulong mie; -- 2.11.0