From 029c85adccb2e23352f622394288ecd133449332 Mon Sep 17 00:00:00 2001 From: Leo Ma Date: Fri, 21 Apr 2023 09:58:25 -0400 Subject: [PATCH] drm/amd/display: revert "Update scaler recout data for visual confirm" This reverts commit 1068e987ad0be83a109147fe7fa0891700e8d80e. A regression is found on this change, so revert it for the time being and resubmit when issue is fixed. Reviewed-by: Martin Leung Acked-by: Alan Liu Signed-off-by: Leo Ma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 17 ----------------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 18 +++++++++++++++++- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 193e09b05f5a..7e1e5532f88f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -69,9 +69,6 @@ #include "../dcn32/dcn32_resource.h" #include "../dcn321/dcn321_resource.h" -#define VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT 3 -#define VISUAL_CONFIRM_RECT_HEIGHT_MIN 1 -#define VISUAL_CONFIRM_RECT_HEIGHT_MAX 10 #define DC_LOGGER_INIT(logger) @@ -811,8 +808,6 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) struct rect surf_clip = plane_state->clip_rect; bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM; int split_count, split_idx; - struct dpp *dpp = pipe_ctx->plane_res.dpp; - unsigned short visual_confirm_rect_height = VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT; calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx); if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) @@ -881,18 +876,6 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx) data->recout.width = data->h_active - data->recout.x; } } - - /* Check bounds to ensure the VC bar height was set to a sane value */ - if (dpp != NULL) { - if ((dpp->ctx->dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_RECT_HEIGHT_MIN) && - (dpp->ctx->dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_RECT_HEIGHT_MAX)) { - visual_confirm_rect_height = dpp->ctx->dc->debug.visual_confirm_rect_height; - } - - if (dpp->ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) - data->recout.height = data->recout.height - - 2 * (dpp->inst + visual_confirm_rect_height); - } } static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c index 7e140c35a0ce..b33955928bd0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c @@ -39,6 +39,9 @@ #define BLACK_OFFSET_RGB_Y 0x0 #define BLACK_OFFSET_CBCR 0x8000 +#define VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT 3 +#define VISUAL_CONFIRM_RECT_HEIGHT_MIN 1 +#define VISUAL_CONFIRM_RECT_HEIGHT_MAX 10 #define REG(reg)\ dpp->tf_regs->reg @@ -588,6 +591,18 @@ static void dpp1_dscl_set_manual_ratio_init( static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp, const struct rect *recout) { + int visual_confirm_on = 0; + unsigned short visual_confirm_rect_height = VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT; + + if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) + visual_confirm_on = 1; + + /* Check bounds to ensure the VC bar height was set to a sane value */ + if ((dpp->base.ctx->dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_RECT_HEIGHT_MIN) && + (dpp->base.ctx->dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_RECT_HEIGHT_MAX)) { + visual_confirm_rect_height = dpp->base.ctx->dc->debug.visual_confirm_rect_height; + } + REG_SET_2(RECOUT_START, 0, /* First pixel of RECOUT in the active OTG area */ RECOUT_START_X, recout->x, @@ -598,7 +613,8 @@ static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp, /* Number of RECOUT horizontal pixels */ RECOUT_WIDTH, recout->width, /* Number of RECOUT vertical lines */ - RECOUT_HEIGHT, recout->height); + RECOUT_HEIGHT, recout->height + - visual_confirm_on * 2 * (dpp->base.inst + visual_confirm_rect_height)); } /** -- 2.11.0