From 033d5060aaa35fd6e3e871a1f240fc15f58d5d48 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Tue, 2 May 2017 18:09:07 +0000
Subject: [PATCH] [Hexagon] Formatting changes, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301953 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp   | 10 ++++------
 lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h     |  3 ++-
 lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp |  6 ++++++
 lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp    |  2 +-
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
index 7b464c3d60f..3bb658b8445 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
@@ -113,7 +113,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
         // The instruction table models the USR.OVF flag, which can be
         // implicitly modified more than once, but cannot be modified in the
         // same packet with an instruction that modifies is explicitly. Deal
-        // with such situ- ations individually.
+        // with such situations individually.
         SoftDefs.insert(R);
       else if (isPredicateRegister(R) &&
                HexagonMCInstrInfo::isPredicateLate(MCII, MCI))
@@ -196,9 +196,8 @@ void HexagonMCChecker::init(MCInst const &MCI) {
     if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) {
       unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg();
 
-      for (MCRegAliasIterator SRI(R2, &RI,
-                                  !MCSubRegIterator(R2, &RI).isValid());
-           SRI.isValid(); ++SRI)
+      bool HasSubRegs = MCSubRegIterator(R2, &RI).isValid();
+      for (MCRegAliasIterator SRI(R2, &RI, !HasSubRegs); SRI.isValid(); ++SRI)
         if (!MCSubRegIterator(*SRI, &RI).isValid())
           NewDefs[*SRI].push_back(NewSense::Def(
               PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI),
@@ -553,8 +552,7 @@ bool HexagonMCChecker::checkRegisters() {
         if (PM.count(P) && PM.size() > 2) {
           // Error out on conditional changes based on the same predicate
           // multiple times
-          // (e.g., "{ if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...
-          // }").
+          // (e.g., "if (p0) r0 =...; if (!p0) r0 =... }; if (!p0) r0 =...").
           reportErrorRegisters(R);
           return false;
         }
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
index 2095a4a556e..027f78b4899 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h
@@ -105,8 +105,9 @@ class HexagonMCChecker {
   void init();
   void init(MCInst const &);
   void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
-  
+
   bool registerUsed(unsigned Register);
+
   // Checks performed.
   bool checkBranches();
   bool checkPredicates();
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index 2d1113c25ea..cadac010020 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -22,15 +22,18 @@
 #include "llvm/MC/MCSubtargetInfo.h"
 
 namespace llvm {
+
 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
                                         MCInst const &Inst)
     : MCII(MCII), BundleCurrent(Inst.begin() +
                                 HexagonMCInstrInfo::bundleInstructionsOffset),
       BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
+
 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
                                         MCInst const &Inst, std::nullptr_t)
     : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
       DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
+
 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
   if (DuplexCurrent != DuplexEnd) {
     ++DuplexCurrent;
@@ -50,15 +53,18 @@ Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
   }
   return *this;
 }
+
 MCInst const &Hexagon::PacketIterator::operator*() const {
   if (DuplexCurrent != DuplexEnd)
     return *DuplexCurrent->getInst();
   return *BundleCurrent->getInst();
 }
+
 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
   return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
          DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
 }
+
 void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
                                      MCContext &Context) {
   MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 2a3af20b35f..a5afa1daeb9 100644
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -210,7 +210,7 @@ bool HexagonShuffler::check() {
   // Descriptive slot masks.
   const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2,
                  slotThree = 0x8, // slotFirstJump = 0x8,
-      slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
+                 slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
   // Highest slots for branches and stores used to keep their original order.
   // unsigned slotJump = slotFirstJump;
   unsigned slotLoadStore = slotFirstLoadStore;
-- 
2.11.0