From 0341cdf06c272bfc7fc503272c087f924fff51e2 Mon Sep 17 00:00:00 2001 From: astoria-d Date: Tue, 27 Aug 2013 15:24:20 +0900 Subject: [PATCH] DMA controler (apu i/f) added. --- simulation/dev/Makefile | 29 +++++++++++++ simulation/dev/apu.vhd | 94 ++++++++++++++++++++++++++++++++++++++++ simulation/dev/testbench_apu.vhd | 65 +++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 simulation/dev/Makefile create mode 100644 simulation/dev/apu.vhd create mode 100644 simulation/dev/testbench_apu.vhd diff --git a/simulation/dev/Makefile b/simulation/dev/Makefile new file mode 100644 index 0000000..27d2802 --- /dev/null +++ b/simulation/dev/Makefile @@ -0,0 +1,29 @@ + +MODULES=apu.vhd + + +TEST_MODULE= testbench_apu.vhd + +WORKDIR=../work + +GHDL_OPTION=--ieee=synopsys -fexplicit --workdir=$(WORKDIR) + +BIN=$(subst .vhd,, $(TEST_MODULE)) + +OBJS = $(addprefix $(WORKDIR)/,$(addsuffix .o,$(basename $(MODULES) $(TEST_MODULE)))) + + +all: $(BIN) + +$(WORKDIR)/%.o: %.vhd + ghdl -a $(GHDL_OPTION) $(subst .o,.vhd, $(subst $(WORKDIR)/,, $@)) + +$(BIN): $(OBJS) + ghdl -e $(GHDL_OPTION) $(BIN) + +clean: + -rm $(OBJS) + -rm $(BIN) + -rm $(patsubst $(WORKDIR)/,$(WORKDIR)/e~, $(OBJS)) + -rm *.o *.cf testbench.vcd* + diff --git a/simulation/dev/apu.vhd b/simulation/dev/apu.vhd new file mode 100644 index 0000000..8be748d --- /dev/null +++ b/simulation/dev/apu.vhd @@ -0,0 +1,94 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity apu is + port ( clk : in std_logic; + ce_n : in std_logic; + rst_n : in std_logic; + r_nw : in std_logic; + cpu_addr : in std_logic_vector (2 downto 0); + cpu_d : inout std_logic_vector (7 downto 0); + vram_ad : inout std_logic_vector (7 downto 0); + vram_a : out std_logic_vector (13 downto 8) + ); +end apu; + +architecture rtl of apu is + + +component d_flip_flop + generic ( + dsize : integer := 8 + ); + port ( + clk : in std_logic; + res_n : in std_logic; + set_n : in std_logic; + we_n : in std_logic; + d : in std_logic_vector (dsize - 1 downto 0); + q : out std_logic_vector (dsize - 1 downto 0) + ); +end component; + +component counter_register + generic ( + dsize : integer := 8; + inc : integer := 1 + ); + port ( clk : in std_logic; + rst_n : in std_logic; + ce_n : in std_logic; + we_n : in std_logic; + d : in std_logic_vector(dsize - 1 downto 0); + q : out std_logic_vector(dsize - 1 downto 0) + ); +end component; + +procedure d_print(msg : string) is +use std.textio.all; +use ieee.std_logic_textio.all; +variable out_l : line; +begin + write(out_l, msg); + writeline(output, out_l); +end procedure; + +constant dsize : integer := 8; + + +signal clk_n : std_logic; + +signal oam_addr : std_logic_vector (dsize - 1 downto 0); +signal oam_data : std_logic_vector (dsize - 1 downto 0); + +signal oam_bus_ce_n : std_logic; + +begin + + clk_n <= not clk; + +-- ppu_clk_cnt_inst : counter_register generic map (2, 1) +-- port map (clk_n, ppu_clk_cnt_res_n, '0', '1', (others => '0'), ppu_clk_cnt); +-- +-- ppu_ctrl_inst : d_flip_flop generic map(dsize) +-- port map (clk_n, rst_n, '1', ppu_ctrl_we_n, cpu_d, ppu_ctrl); +-- + reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d) + begin + + if (rst_n = '1' and ce_n = '0') then + +-- if(cpu_addr = PPUCTRL) then +-- ppu_ctrl_we_n <= '0'; +-- else +-- ppu_ctrl_we_n <= '1'; +-- end if; + + else + end if; --if (rst_n = '1' and ce_n = '0') + + end process; + + +end rtl; + diff --git a/simulation/dev/testbench_apu.vhd b/simulation/dev/testbench_apu.vhd new file mode 100644 index 0000000..2bd36d0 --- /dev/null +++ b/simulation/dev/testbench_apu.vhd @@ -0,0 +1,65 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use ieee.std_logic_arith.all; + + +entity testbench_apu is +end testbench_apu; + +architecture stimulus of testbench_apu is + component v_address_decoder + generic (abus_size : integer := 14; dbus_size : integer := 8); + port ( clk : in std_logic; + rd_n : in std_logic; + wr_n : in std_logic; + ale : in std_logic; + vram_ad : inout std_logic_vector (7 downto 0); + vram_a : in std_logic_vector (13 downto 8) + ); + end component; + + component clock_divider + port ( base_clk : in std_logic; + reset_n : in std_logic; + cpu_clk : out std_logic; + ppu_clk : out std_logic + ); + end component; + +constant base_clk_time : time := 46 ns; +constant ppu_clk_time : time := (base_clk_time * 4); +constant cpu_clk_time : time := (base_clk_time * 12); +constant vga_clk_time : time := 40 ns; +constant size8 : integer := 8; +constant size14 : integer := 14; + +constant test_init_time : time := 5 us; +constant test_reset_time : time := 10 us; + +signal base_clk : std_logic; +signal cpu_clk : std_logic; +signal ppu_clk : std_logic; +signal ce_n : std_logic; +signal rst_n : std_logic; +signal r_nw : std_logic; +signal cpu_addr : std_logic_vector (2 downto 0); +signal cpu_d : std_logic_vector (7 downto 0); +signal vblank_n : std_logic; +signal rd_n : std_logic; +signal wr_n : std_logic; +signal ale : std_logic; +signal vram_ad : std_logic_vector (7 downto 0); +signal vram_a : std_logic_vector (13 downto 8); + +signal vga_clk : std_logic; +signal h_sync_n : std_logic; +signal v_sync_n : std_logic; +signal r : std_logic_vector(3 downto 0); +signal g : std_logic_vector(3 downto 0); +signal b : std_logic_vector(3 downto 0); + +begin + + +end stimulus ; + -- 2.11.0