From 03fb8cfc638ed18b4364949765778d7121d27f56 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 15 Oct 2011 10:20:20 -0700 Subject: [PATCH] target-sparc: Pass float64 parameters instead of dt0/1 temporaries. Signed-off-by: Richard Henderson --- target-sparc/cpu.h | 1 - target-sparc/fop_helper.c | 120 ++++++------ target-sparc/helper.h | 95 +++++----- target-sparc/ldst_helper.c | 52 ------ target-sparc/translate.c | 449 ++++++++++++++++++++++----------------------- target-sparc/vis_helper.c | 113 ++++++------ 6 files changed, 381 insertions(+), 449 deletions(-) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 25b4f1a1dc..4eace33c47 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -463,7 +463,6 @@ typedef struct CPUSPARCState { uint64_t prom_addr; #endif /* temporary float registers */ - float64 dt0, dt1; float128 qt0, qt1; float_status fp_status; #if defined(TARGET_SPARC64) diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c index 23502f3020..f6348c2e3b 100644 --- a/target-sparc/fop_helper.c +++ b/target-sparc/fop_helper.c @@ -20,8 +20,6 @@ #include "cpu.h" #include "helper.h" -#define DT0 (env->dt0) -#define DT1 (env->dt1) #define QT0 (env->qt0) #define QT1 (env->qt1) @@ -33,9 +31,10 @@ { \ return float32_ ## name (src1, src2, &env->fp_status); \ } \ - F_HELPER(name, d) \ + float64 helper_f ## name ## d (CPUState * env, float64 src1,\ + float64 src2) \ { \ - DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ + return float64_ ## name (src1, src2, &env->fp_status); \ } \ F_HELPER(name, q) \ { \ @@ -48,17 +47,17 @@ F_BINOP(mul); F_BINOP(div); #undef F_BINOP -void helper_fsmuld(CPUState *env, float32 src1, float32 src2) +float64 helper_fsmuld(CPUState *env, float32 src1, float32 src2) { - DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), - float32_to_float64(src2, &env->fp_status), - &env->fp_status); + return float64_mul(float32_to_float64(src1, &env->fp_status), + float32_to_float64(src2, &env->fp_status), + &env->fp_status); } -void helper_fdmulq(CPUState *env) +void helper_fdmulq(CPUState *env, float64 src1, float64 src2) { - QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), - float64_to_float128(DT1, &env->fp_status), + QT0 = float128_mul(float64_to_float128(src1, &env->fp_status), + float64_to_float128(src2, &env->fp_status), &env->fp_status); } @@ -68,9 +67,9 @@ float32 helper_fnegs(float32 src) } #ifdef TARGET_SPARC64 -F_HELPER(neg, d) +float64 helper_fnegd(float64 src) { - DT0 = float64_chs(DT1); + return float64_chs(src); } F_HELPER(neg, q) @@ -85,9 +84,9 @@ float32 helper_fitos(CPUState *env, int32_t src) return int32_to_float32(src, &env->fp_status); } -void helper_fitod(CPUState *env, int32_t src) +float64 helper_fitod(CPUState *env, int32_t src) { - DT0 = int32_to_float64(src, &env->fp_status); + return int32_to_float64(src, &env->fp_status); } void helper_fitoq(CPUState *env, int32_t src) @@ -96,32 +95,32 @@ void helper_fitoq(CPUState *env, int32_t src) } #ifdef TARGET_SPARC64 -float32 helper_fxtos(CPUState *env) +float32 helper_fxtos(CPUState *env, int64_t src) { - return int64_to_float32(*((int64_t *)&DT1), &env->fp_status); + return int64_to_float32(src, &env->fp_status); } -F_HELPER(xto, d) +float64 helper_fxtod(CPUState *env, int64_t src) { - DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); + return int64_to_float64(src, &env->fp_status); } -F_HELPER(xto, q) +void helper_fxtoq(CPUState *env, int64_t src) { - QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status); + QT0 = int64_to_float128(src, &env->fp_status); } #endif #undef F_HELPER /* floating point conversion */ -float32 helper_fdtos(CPUState *env) +float32 helper_fdtos(CPUState *env, float64 src) { - return float64_to_float32(DT1, &env->fp_status); + return float64_to_float32(src, &env->fp_status); } -void helper_fstod(CPUState *env, float32 src) +float64 helper_fstod(CPUState *env, float32 src) { - DT0 = float32_to_float64(src, &env->fp_status); + return float32_to_float64(src, &env->fp_status); } float32 helper_fqtos(CPUState *env) @@ -134,14 +133,14 @@ void helper_fstoq(CPUState *env, float32 src) QT0 = float32_to_float128(src, &env->fp_status); } -void helper_fqtod(CPUState *env) +float64 helper_fqtod(CPUState *env) { - DT0 = float128_to_float64(QT1, &env->fp_status); + return float128_to_float64(QT1, &env->fp_status); } -void helper_fdtoq(CPUState *env) +void helper_fdtoq(CPUState *env, float64 src) { - QT0 = float64_to_float128(DT1, &env->fp_status); + QT0 = float64_to_float128(src, &env->fp_status); } /* Float to integer conversion. */ @@ -150,9 +149,9 @@ int32_t helper_fstoi(CPUState *env, float32 src) return float32_to_int32_round_to_zero(src, &env->fp_status); } -int32_t helper_fdtoi(CPUState *env) +int32_t helper_fdtoi(CPUState *env, float64 src) { - return float64_to_int32_round_to_zero(DT1, &env->fp_status); + return float64_to_int32_round_to_zero(src, &env->fp_status); } int32_t helper_fqtoi(CPUState *env) @@ -161,19 +160,19 @@ int32_t helper_fqtoi(CPUState *env) } #ifdef TARGET_SPARC64 -void helper_fstox(CPUState *env, float32 src) +int64_t helper_fstox(CPUState *env, float32 src) { - *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); + return float32_to_int64_round_to_zero(src, &env->fp_status); } -void helper_fdtox(CPUState *env) +int64_t helper_fdtox(CPUState *env, float64 src) { - *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); + return float64_to_int64_round_to_zero(src, &env->fp_status); } -void helper_fqtox(CPUState *env) +int64_t helper_fqtox(CPUState *env) { - *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); + return float128_to_int64_round_to_zero(QT1, &env->fp_status); } #endif @@ -183,9 +182,9 @@ float32 helper_fabss(float32 src) } #ifdef TARGET_SPARC64 -void helper_fabsd(CPUState *env) +float64 helper_fabsd(CPUState *env, float64 src) { - DT0 = float64_abs(DT1); + return float64_abs(src); } void helper_fabsq(CPUState *env) @@ -199,9 +198,9 @@ float32 helper_fsqrts(CPUState *env, float32 src) return float32_sqrt(src, &env->fp_status); } -void helper_fsqrtd(CPUState *env) +float64 helper_fsqrtd(CPUState *env, float64 src) { - DT0 = float64_sqrt(DT1, &env->fp_status); + return float64_sqrt(src, &env->fp_status); } void helper_fsqrtq(CPUState *env) @@ -245,8 +244,8 @@ void helper_fsqrtq(CPUState *env) break; \ } \ } -#define GEN_FCMPS(name, size, FS, E) \ - void glue(helper_, name)(CPUState *env, float32 src1, float32 src2) \ +#define GEN_FCMP_T(name, size, FS, E) \ + void glue(helper_, name)(CPUState *env, size src1, size src2) \ { \ env->fsr &= FSR_FTT_NMASK; \ if (E && (glue(size, _is_any_nan)(src1) || \ @@ -282,41 +281,42 @@ void helper_fsqrtq(CPUState *env) } \ } -GEN_FCMPS(fcmps, float32, 0, 0); -GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); +GEN_FCMP_T(fcmps, float32, 0, 0); +GEN_FCMP_T(fcmpd, float64, 0, 0); -GEN_FCMPS(fcmpes, float32, 0, 1); -GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); +GEN_FCMP_T(fcmpes, float32, 0, 1); +GEN_FCMP_T(fcmped, float64, 0, 1); GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); #ifdef TARGET_SPARC64 -GEN_FCMPS(fcmps_fcc1, float32, 22, 0); -GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); +GEN_FCMP_T(fcmps_fcc1, float32, 22, 0); +GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0); GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); -GEN_FCMPS(fcmps_fcc2, float32, 24, 0); -GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); +GEN_FCMP_T(fcmps_fcc2, float32, 24, 0); +GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0); GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); -GEN_FCMPS(fcmps_fcc3, float32, 26, 0); -GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); +GEN_FCMP_T(fcmps_fcc3, float32, 26, 0); +GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0); GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); -GEN_FCMPS(fcmpes_fcc1, float32, 22, 1); -GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); +GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1); +GEN_FCMP_T(fcmped_fcc1, float64, 22, 1); GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); -GEN_FCMPS(fcmpes_fcc2, float32, 24, 1); -GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); +GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1); +GEN_FCMP_T(fcmped_fcc2, float64, 24, 1); GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); -GEN_FCMPS(fcmpes_fcc3, float32, 26, 1); -GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); +GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1); +GEN_FCMP_T(fcmped_fcc3, float64, 26, 1); GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); #endif -#undef GEN_FCMPS +#undef GEN_FCMP_T +#undef GEN_FCMP void helper_check_ieee_exceptions(CPUState *env) { diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 615ddefa92..86fad6e16d 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -39,8 +39,6 @@ DEF_HELPER_3(udiv, tl, env, tl, tl) DEF_HELPER_3(udiv_cc, tl, env, tl, tl) DEF_HELPER_3(sdiv, tl, env, tl, tl) DEF_HELPER_3(sdiv_cc, tl, env, tl, tl) -DEF_HELPER_2(stdf, void, tl, int) -DEF_HELPER_2(lddf, void, tl, int) DEF_HELPER_2(ldqf, void, tl, int) DEF_HELPER_2(stqf, void, tl, int) #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) @@ -52,29 +50,29 @@ DEF_HELPER_1(check_ieee_exceptions, void, env) DEF_HELPER_1(clear_float_exceptions, void, env) DEF_HELPER_1(fabss, f32, f32) DEF_HELPER_2(fsqrts, f32, env, f32) -DEF_HELPER_1(fsqrtd, void, env) +DEF_HELPER_2(fsqrtd, f64, env, f64) DEF_HELPER_3(fcmps, void, env, f32, f32) -DEF_HELPER_1(fcmpd, void, env) +DEF_HELPER_3(fcmpd, void, env, f64, f64) DEF_HELPER_3(fcmpes, void, env, f32, f32) -DEF_HELPER_1(fcmped, void, env) +DEF_HELPER_3(fcmped, void, env, f64, f64) DEF_HELPER_1(fsqrtq, void, env) DEF_HELPER_1(fcmpq, void, env) DEF_HELPER_1(fcmpeq, void, env) #ifdef TARGET_SPARC64 DEF_HELPER_2(ldxfsr, void, env, i64) -DEF_HELPER_1(fabsd, void, env) +DEF_HELPER_2(fabsd, f64, env, f64) DEF_HELPER_3(fcmps_fcc1, void, env, f32, f32) DEF_HELPER_3(fcmps_fcc2, void, env, f32, f32) DEF_HELPER_3(fcmps_fcc3, void, env, f32, f32) -DEF_HELPER_1(fcmpd_fcc1, void, env) -DEF_HELPER_1(fcmpd_fcc2, void, env) -DEF_HELPER_1(fcmpd_fcc3, void, env) +DEF_HELPER_3(fcmpd_fcc1, void, env, f64, f64) +DEF_HELPER_3(fcmpd_fcc2, void, env, f64, f64) +DEF_HELPER_3(fcmpd_fcc3, void, env, f64, f64) DEF_HELPER_3(fcmpes_fcc1, void, env, f32, f32) DEF_HELPER_3(fcmpes_fcc2, void, env, f32, f32) DEF_HELPER_3(fcmpes_fcc3, void, env, f32, f32) -DEF_HELPER_1(fcmped_fcc1, void, env) -DEF_HELPER_1(fcmped_fcc2, void, env) -DEF_HELPER_1(fcmped_fcc3, void, env) +DEF_HELPER_3(fcmped_fcc1, void, env, f64, f64) +DEF_HELPER_3(fcmped_fcc2, void, env, f64, f64) +DEF_HELPER_3(fcmped_fcc3, void, env, f64, f64) DEF_HELPER_1(fabsq, void, env) DEF_HELPER_1(fcmpq_fcc1, void, env) DEF_HELPER_1(fcmpq_fcc2, void, env) @@ -86,77 +84,78 @@ DEF_HELPER_1(fcmpeq_fcc3, void, env) DEF_HELPER_2(raise_exception, void, env, int) DEF_HELPER_0(shutdown, void) #define F_HELPER_0_1(name) DEF_HELPER_1(f ## name, void, env) -#define F_HELPER_DQ_0_1(name) \ - F_HELPER_0_1(name ## d); \ - F_HELPER_0_1(name ## q) -F_HELPER_DQ_0_1(add); -F_HELPER_DQ_0_1(sub); -F_HELPER_DQ_0_1(mul); -F_HELPER_DQ_0_1(div); +DEF_HELPER_3(faddd, f64, env, f64, f64) +DEF_HELPER_3(fsubd, f64, env, f64, f64) +DEF_HELPER_3(fmuld, f64, env, f64, f64) +DEF_HELPER_3(fdivd, f64, env, f64, f64) +F_HELPER_0_1(addq) +F_HELPER_0_1(subq) +F_HELPER_0_1(mulq) +F_HELPER_0_1(divq) DEF_HELPER_3(fadds, f32, env, f32, f32) DEF_HELPER_3(fsubs, f32, env, f32, f32) DEF_HELPER_3(fmuls, f32, env, f32, f32) DEF_HELPER_3(fdivs, f32, env, f32, f32) -DEF_HELPER_3(fsmuld, void, env, f32, f32) -F_HELPER_0_1(dmulq); +DEF_HELPER_3(fsmuld, f64, env, f32, f32) +DEF_HELPER_3(fdmulq, void, env, f64, f64); DEF_HELPER_1(fnegs, f32, f32) -DEF_HELPER_2(fitod, void, env, s32) +DEF_HELPER_2(fitod, f64, env, s32) DEF_HELPER_2(fitoq, void, env, s32) DEF_HELPER_2(fitos, f32, env, s32) #ifdef TARGET_SPARC64 -DEF_HELPER_1(fnegd, void, env) +DEF_HELPER_1(fnegd, f64, f64) DEF_HELPER_1(fnegq, void, env) -DEF_HELPER_1(fxtos, i32, env) -F_HELPER_DQ_0_1(xto); +DEF_HELPER_2(fxtos, f32, env, s64) +DEF_HELPER_2(fxtod, f64, env, s64) +DEF_HELPER_2(fxtoq, void, env, s64) #endif -DEF_HELPER_1(fdtos, f32, env) -DEF_HELPER_2(fstod, void, env, f32) +DEF_HELPER_2(fdtos, f32, env, f64) +DEF_HELPER_2(fstod, f64, env, f32) DEF_HELPER_1(fqtos, f32, env) DEF_HELPER_2(fstoq, void, env, f32) -F_HELPER_0_1(qtod); -F_HELPER_0_1(dtoq); +DEF_HELPER_1(fqtod, f64, env) +DEF_HELPER_2(fdtoq, void, env, f64) DEF_HELPER_2(fstoi, s32, env, f32) -DEF_HELPER_1(fdtoi, s32, env) +DEF_HELPER_2(fdtoi, s32, env, f64) DEF_HELPER_1(fqtoi, s32, env) #ifdef TARGET_SPARC64 -DEF_HELPER_2(fstox, void, env, i32) -F_HELPER_0_1(dtox); -F_HELPER_0_1(qtox); -F_HELPER_0_1(aligndata); +DEF_HELPER_2(fstox, s64, env, f32) +DEF_HELPER_2(fdtox, s64, env, f64) +DEF_HELPER_1(fqtox, s64, env) +DEF_HELPER_3(faligndata, i64, env, i64, i64) -F_HELPER_0_1(pmerge); -F_HELPER_0_1(mul8x16); -F_HELPER_0_1(mul8x16al); -F_HELPER_0_1(mul8x16au); -F_HELPER_0_1(mul8sux16); -F_HELPER_0_1(mul8ulx16); -F_HELPER_0_1(muld8sux16); -F_HELPER_0_1(muld8ulx16); -F_HELPER_0_1(expand); +DEF_HELPER_3(fpmerge, i64, env, i64, i64) +DEF_HELPER_3(fmul8x16, i64, env, i64, i64) +DEF_HELPER_3(fmul8x16al, i64, env, i64, i64) +DEF_HELPER_3(fmul8x16au, i64, env, i64, i64) +DEF_HELPER_3(fmul8sux16, i64, env, i64, i64) +DEF_HELPER_3(fmul8ulx16, i64, env, i64, i64) +DEF_HELPER_3(fmuld8sux16, i64, env, i64, i64) +DEF_HELPER_3(fmuld8ulx16, i64, env, i64, i64) +DEF_HELPER_3(fexpand, i64, env, i64, i64) #define VIS_HELPER(name) \ - F_HELPER_0_1(name##16); \ + DEF_HELPER_3(f ## name ## 16, i64, env, i64, i64) \ DEF_HELPER_3(f ## name ## 16s, i32, env, i32, i32) \ - F_HELPER_0_1(name##32); \ + DEF_HELPER_3(f ## name ## 32, i64, env, i64, i64) \ DEF_HELPER_3(f ## name ## 32s, i32, env, i32, i32) VIS_HELPER(padd); VIS_HELPER(psub); #define VIS_CMPHELPER(name) \ - DEF_HELPER_1(f##name##16, i64, env); \ - DEF_HELPER_1(f##name##32, i64, env) + DEF_HELPER_3(f##name##16, i64, env, i64, i64) \ + DEF_HELPER_3(f##name##32, i64, env, i64, i64) VIS_CMPHELPER(cmpgt); VIS_CMPHELPER(cmpeq); VIS_CMPHELPER(cmple); VIS_CMPHELPER(cmpne); #endif #undef F_HELPER_0_1 -#undef F_HELPER_DQ_0_1 #undef VIS_HELPER #undef VIS_CMPHELPER DEF_HELPER_1(compute_psr, void, env); diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 1fb3996fdb..80e540818f 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -66,8 +66,6 @@ #endif #endif -#define DT0 (env->dt0) -#define DT1 (env->dt1) #define QT0 (env->qt0) #define QT1 (env->qt1) @@ -2214,56 +2212,6 @@ target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, } #endif /* TARGET_SPARC64 */ -void helper_stdf(target_ulong addr, int mem_idx) -{ - helper_check_align(addr, 7); -#if !defined(CONFIG_USER_ONLY) - switch (mem_idx) { - case MMU_USER_IDX: - stfq_user(addr, DT0); - break; - case MMU_KERNEL_IDX: - stfq_kernel(addr, DT0); - break; -#ifdef TARGET_SPARC64 - case MMU_HYPV_IDX: - stfq_hypv(addr, DT0); - break; -#endif - default: - DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx); - break; - } -#else - stfq_raw(address_mask(env, addr), DT0); -#endif -} - -void helper_lddf(target_ulong addr, int mem_idx) -{ - helper_check_align(addr, 7); -#if !defined(CONFIG_USER_ONLY) - switch (mem_idx) { - case MMU_USER_IDX: - DT0 = ldfq_user(addr); - break; - case MMU_KERNEL_IDX: - DT0 = ldfq_kernel(addr); - break; -#ifdef TARGET_SPARC64 - case MMU_HYPV_IDX: - DT0 = ldfq_hypv(addr); - break; -#endif - default: - DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx); - break; - } -#else - DT0 = ldfq_raw(address_mask(env, addr)); -#endif -} - void helper_ldqf(target_ulong addr, int mem_idx) { /* XXX add 128 bit load */ diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 937e711284..f41ef98d54 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -186,30 +186,6 @@ static TCGv_i64 gen_dest_fpr_D(void) return cpu_tmp64; } -static void gen_op_load_fpr_DT0(unsigned int src) -{ - tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + - offsetof(CPU_DoubleU, l.upper)); - tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) + - offsetof(CPU_DoubleU, l.lower)); -} - -static void gen_op_load_fpr_DT1(unsigned int src) -{ - tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + - offsetof(CPU_DoubleU, l.upper)); - tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) + - offsetof(CPU_DoubleU, l.lower)); -} - -static void gen_op_store_DT0_fpr(unsigned int dst) -{ - tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + - offsetof(CPU_DoubleU, l.upper)); - tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) + - offsetof(CPU_DoubleU, l.lower)); -} - static void gen_op_load_fpr_QT0(unsigned int src) { tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + @@ -1490,20 +1466,20 @@ static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) } } -static inline void gen_op_fcmpd(int fccno) +static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpd(cpu_env); + gen_helper_fcmpd(cpu_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpd_fcc1(cpu_env); + gen_helper_fcmpd_fcc1(cpu_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpd_fcc2(cpu_env); + gen_helper_fcmpd_fcc2(cpu_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpd_fcc3(cpu_env); + gen_helper_fcmpd_fcc3(cpu_env, r_rs1, r_rs2); break; } } @@ -1544,20 +1520,20 @@ static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) } } -static inline void gen_op_fcmped(int fccno) +static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmped(cpu_env); + gen_helper_fcmped(cpu_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmped_fcc1(cpu_env); + gen_helper_fcmped_fcc1(cpu_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmped_fcc2(cpu_env); + gen_helper_fcmped_fcc2(cpu_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmped_fcc3(cpu_env); + gen_helper_fcmped_fcc3(cpu_env, r_rs1, r_rs2); break; } } @@ -1587,9 +1563,9 @@ static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) gen_helper_fcmps(cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmpd(int fccno) +static inline void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmpd(cpu_env); + gen_helper_fcmpd(cpu_env, r_rs1, r_rs2); } static inline void gen_op_fcmpq(int fccno) @@ -1602,9 +1578,9 @@ static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) gen_helper_fcmpes(cpu_env, r_rs1, r_rs2); } -static inline void gen_op_fcmped(int fccno) +static inline void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmped(cpu_env); + gen_helper_fcmped(cpu_env, r_rs1, r_rs2); } static inline void gen_op_fcmpeq(int fccno) @@ -2461,12 +2437,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x2a: /* fsqrtd */ CHECK_FPU_FEATURE(dc, FSQRT); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsqrtd(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fsqrtd(cpu_dst_64, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x2b: /* fsqrtq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2488,13 +2464,14 @@ static void disas_sparc_insn(DisasContext * dc) gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0x42: /* faddd */ - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_faddd(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_faddd(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x43: /* faddq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2517,13 +2494,14 @@ static void disas_sparc_insn(DisasContext * dc) gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0x46: /* fsubd */ - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fsubd(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fsubd(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x47: /* fsubq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2548,13 +2526,14 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x4a: /* fmuld */ CHECK_FPU_FEATURE(dc, FMUL); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fmuld(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmuld(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2578,13 +2557,14 @@ static void disas_sparc_insn(DisasContext * dc) gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0x4e: /* fdivd */ - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdivd(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fdivd(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x4f: /* fdivq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2601,17 +2581,18 @@ static void disas_sparc_insn(DisasContext * dc) gen_clear_float_exceptions(); cpu_src1_32 = gen_load_fpr_F(dc, rs1); cpu_src2_32 = gen_load_fpr_F(dc, rs2); - gen_helper_fsmuld(cpu_env, cpu_src1_32, cpu_src2_32); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fsmuld(cpu_dst_64, cpu_env, + cpu_src1_32, cpu_src2_32); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x6e: /* fdmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdmulq(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fdmulq(cpu_env, cpu_src1_64, cpu_src2_64); gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); @@ -2625,10 +2606,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0xc6: /* fdtos */ - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); cpu_dst_32 = gen_dest_fpr_F(); - gen_helper_fdtos(cpu_dst_32, cpu_env); + gen_helper_fdtos(cpu_dst_32, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); gen_store_fpr_F(dc, rd, cpu_dst_32); break; @@ -2643,24 +2624,24 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0xc8: /* fitod */ cpu_src1_32 = gen_load_fpr_F(dc, rs2); - gen_helper_fitod(cpu_env, cpu_src1_32); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fitod(cpu_dst_64, cpu_env, cpu_src1_32); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0xc9: /* fstod */ cpu_src1_32 = gen_load_fpr_F(dc, rs2); - gen_helper_fstod(cpu_env, cpu_src1_32); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fstod(cpu_dst_64, cpu_env, cpu_src1_32); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtod(cpu_env); + gen_op_load_fpr_QT1(QFPREG(rs2)); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fqtod(cpu_dst_64, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2678,8 +2659,8 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0xce: /* fdtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fdtoq(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fdtoq(cpu_env, cpu_src1_64); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); break; @@ -2692,10 +2673,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0xd2: /* fdtoi */ - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); cpu_dst_32 = gen_dest_fpr_F(); - gen_helper_fdtoi(cpu_dst_32, cpu_env); + gen_helper_fdtoi(cpu_dst_32, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); gen_store_fpr_F(dc, rd, cpu_dst_32); break; @@ -2726,10 +2707,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_update_fprs_dirty(QFPREG(rd)); break; case 0x6: /* V9 fnegd */ - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fnegd(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fnegd(cpu_dst_64, cpu_src1_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x7: /* V9 fnegq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2739,10 +2720,10 @@ static void disas_sparc_insn(DisasContext * dc) gen_update_fprs_dirty(QFPREG(rd)); break; case 0xa: /* V9 fabsd */ - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fabsd(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fabsd(cpu_dst_64, cpu_env, cpu_src1_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0xb: /* V9 fabsq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -2754,49 +2735,49 @@ static void disas_sparc_insn(DisasContext * dc) case 0x81: /* V9 fstox */ gen_clear_float_exceptions(); cpu_src1_32 = gen_load_fpr_F(dc, rs2); - gen_helper_fstox(cpu_env, cpu_src1_32); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fstox(cpu_dst_64, cpu_env, cpu_src1_32); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x82: /* V9 fdtox */ - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fdtox(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fdtox(cpu_dst_64, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fqtox(cpu_env); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fqtox(cpu_dst_64, cpu_env); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x84: /* V9 fxtos */ - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); cpu_dst_32 = gen_dest_fpr_F(); - gen_helper_fxtos(cpu_dst_32, cpu_env); + gen_helper_fxtos(cpu_dst_32, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0x88: /* V9 fxtod */ - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtod(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fxtod(cpu_dst_64, cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - gen_helper_fxtoq(cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fxtoq(cpu_env, cpu_src1_64); gen_helper_check_ieee_exceptions(cpu_env); gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(QFPREG(rd)); @@ -3046,9 +3027,9 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); break; case 0x52: /* fcmpd, V9 %fcc */ - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_op_fcmpd(rd & 3); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64); break; case 0x53: /* fcmpq, V9 %fcc */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -3062,9 +3043,9 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); break; case 0x56: /* fcmped, V9 %fcc */ - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_op_fcmped(rd & 3); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64); break; case 0x57: /* fcmpeq, V9 %fcc */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -3953,115 +3934,130 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmple16(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmple16(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x022: /* VIS I fcmpne16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpne16(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpne16(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x024: /* VIS I fcmple32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmple32(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmple32(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x026: /* VIS I fcmpne32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpne32(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpne32(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x028: /* VIS I fcmpgt16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpgt16(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpgt16(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02a: /* VIS I fcmpeq16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpeq16(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpeq16(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02c: /* VIS I fcmpgt32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpgt32(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpgt32(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x02e: /* VIS I fcmpeq32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fcmpeq32(cpu_dst, cpu_env); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + gen_helper_fcmpeq32(cpu_dst, cpu_env, + cpu_src1_64, cpu_src2_64); gen_movl_TN_reg(rd, cpu_dst); break; case 0x031: /* VIS I fmul8x16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmul8x16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x033: /* VIS I fmul8x16au */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16au(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmul8x16au(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x035: /* VIS I fmul8x16al */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8x16al(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmul8x16al(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x036: /* VIS I fmul8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8sux16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmul8sux16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x037: /* VIS I fmul8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmul8ulx16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmul8ulx16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x038: /* VIS I fmuld8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmuld8sux16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmuld8sux16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x039: /* VIS I fmuld8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fmuld8ulx16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fmuld8ulx16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x03a: /* VIS I fpack32 */ case 0x03b: /* VIS I fpack16 */ @@ -4071,38 +4067,42 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_faligndata(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_faligndata(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpmerge(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fpmerge(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x04c: /* VIS II bshuffle */ // XXX goto illegal_insn; case 0x04d: /* VIS I fexpand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fexpand(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fexpand(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x050: /* VIS I fpadd16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpadd16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fpadd16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4115,11 +4115,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpadd32(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fpadd32(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4131,11 +4132,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpsub16(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fpsub16(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4148,11 +4150,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - gen_helper_fpsub32(cpu_env); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); + cpu_src1_64 = gen_load_fpr_D(dc, rs1); + cpu_src2_64 = gen_load_fpr_D(dc, rs2); + cpu_dst_64 = gen_dest_fpr_D(); + gen_helper_fpsub32(cpu_dst_64, cpu_env, + cpu_src1_64, cpu_src2_64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4811,16 +4814,10 @@ static void disas_sparc_insn(DisasContext * dc) } break; case 0x23: /* lddf, load double fpreg */ - { - TCGv_i32 r_const; - - r_const = tcg_const_i32(dc->mem_idx); - gen_address_mask(dc, cpu_addr); - gen_helper_lddf(cpu_addr, r_const); - tcg_temp_free_i32(r_const); - gen_op_store_DT0_fpr(DFPREG(rd)); - gen_update_fprs_dirty(DFPREG(rd)); - } + gen_address_mask(dc, cpu_addr); + cpu_dst_64 = gen_dest_fpr_D(); + tcg_gen_qemu_ld64(cpu_dst_64, cpu_addr, dc->mem_idx); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; default: goto illegal_insn; @@ -4971,15 +4968,9 @@ static void disas_sparc_insn(DisasContext * dc) #endif #endif case 0x27: /* stdf, store double fpreg */ - { - TCGv_i32 r_const; - - gen_op_load_fpr_DT0(DFPREG(rd)); - r_const = tcg_const_i32(dc->mem_idx); - gen_address_mask(dc, cpu_addr); - gen_helper_stdf(cpu_addr, r_const); - tcg_temp_free_i32(r_const); - } + gen_address_mask(dc, cpu_addr); + cpu_src1_64 = gen_load_fpr_D(dc, rd); + tcg_gen_qemu_st64(cpu_src1_64, cpu_addr, dc->mem_idx); break; default: goto illegal_insn; diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index a22c10bb43..a007b0f30c 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -20,11 +20,6 @@ #include "cpu.h" #include "helper.h" -#define DT0 (env->dt0) -#define DT1 (env->dt1) -#define QT0 (env->qt0) -#define QT1 (env->qt1) - /* This function uses non-native bit order */ #define GET_FIELD(X, FROM, TO) \ ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) @@ -58,16 +53,16 @@ target_ulong helper_alignaddr(CPUState *env, target_ulong addr, return tmp & ~7ULL; } -void helper_faligndata(CPUState *env) +uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) { uint64_t tmp; - tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); + tmp = src1 << ((env->gsr & 7) * 8); /* on many architectures a shift of 64 does nothing */ if ((env->gsr & 7) != 0) { - tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); + tmp |= src2 >> (64 - (env->gsr & 7) * 8); } - *((uint64_t *)&DT0) = tmp; + return tmp; } #ifdef HOST_WORDS_BIGENDIAN @@ -102,12 +97,12 @@ typedef union { float32 f; } VIS32; -void helper_fpmerge(CPUState *env) +uint64_t helper_fpmerge(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; /* Reverse calculation order to handle overlap */ d.VIS_B64(7) = s.VIS_B64(3); @@ -119,16 +114,16 @@ void helper_fpmerge(CPUState *env) d.VIS_B64(1) = s.VIS_B64(0); /* d.VIS_B64(0) = d.VIS_B64(0); */ - DT0 = d.d; + return d.ll; } -void helper_fmul8x16(CPUState *env) +uint64_t helper_fmul8x16(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ @@ -143,16 +138,16 @@ void helper_fmul8x16(CPUState *env) PMUL(3); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmul8x16al(CPUState *env) +uint64_t helper_fmul8x16al(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \ @@ -167,16 +162,16 @@ void helper_fmul8x16al(CPUState *env) PMUL(3); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmul8x16au(CPUState *env) +uint64_t helper_fmul8x16au(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \ @@ -191,16 +186,16 @@ void helper_fmul8x16au(CPUState *env) PMUL(3); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmul8sux16(CPUState *env) +uint64_t helper_fmul8sux16(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ @@ -215,16 +210,16 @@ void helper_fmul8sux16(CPUState *env) PMUL(3); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmul8ulx16(CPUState *env) +uint64_t helper_fmul8ulx16(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ @@ -239,16 +234,16 @@ void helper_fmul8ulx16(CPUState *env) PMUL(3); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmuld8sux16(CPUState *env) +uint64_t helper_fmuld8sux16(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ @@ -262,16 +257,16 @@ void helper_fmuld8sux16(CPUState *env) PMUL(0); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fmuld8ulx16(CPUState *env) +uint64_t helper_fmuld8ulx16(CPUState *env, uint64_t src1, uint64_t src2) { VIS64 s, d; uint32_t tmp; - s.d = DT0; - d.d = DT1; + s.ll = src1; + d.ll = src2; #define PMUL(r) \ tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ @@ -285,38 +280,38 @@ void helper_fmuld8ulx16(CPUState *env) PMUL(0); #undef PMUL - DT0 = d.d; + return d.ll; } -void helper_fexpand(CPUState *env) +uint64_t helper_fexpand(CPUState *env, uint64_t src1, uint64_t src2) { VIS32 s; VIS64 d; - s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff); - d.d = DT1; + s.l = (uint32_t)src1; + d.ll = src2; d.VIS_W64(0) = s.VIS_B32(0) << 4; d.VIS_W64(1) = s.VIS_B32(1) << 4; d.VIS_W64(2) = s.VIS_B32(2) << 4; d.VIS_W64(3) = s.VIS_B32(3) << 4; - DT0 = d.d; + return d.ll; } #define VIS_HELPER(name, F) \ - void name##16(CPUState *env) \ + uint64_t name##16(CPUState *env, uint64_t src1, uint64_t src2) \ { \ VIS64 s, d; \ \ - s.d = DT0; \ - d.d = DT1; \ + s.ll = src1; \ + d.ll = src2; \ \ d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ \ - DT0 = d.d; \ + return d.ll; \ } \ \ uint32_t name##16s(CPUState *env, uint32_t src1, \ @@ -333,17 +328,17 @@ void helper_fexpand(CPUState *env) return d.l; \ } \ \ - void name##32(CPUState *env) \ + uint64_t name##32(CPUState *env, uint64_t src1, uint64_t src2) \ { \ VIS64 s, d; \ \ - s.d = DT0; \ - d.d = DT1; \ + s.ll = src1; \ + d.ll = src2; \ \ d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ \ - DT0 = d.d; \ + return d.ll; \ } \ \ uint32_t name##32s(CPUState *env, uint32_t src1, \ @@ -365,12 +360,12 @@ VIS_HELPER(helper_fpadd, FADD) VIS_HELPER(helper_fpsub, FSUB) #define VIS_CMPHELPER(name, F) \ - uint64_t name##16(CPUState *env) \ + uint64_t name##16(CPUState *env, uint64_t src1, uint64_t src2) \ { \ VIS64 s, d; \ \ - s.d = DT0; \ - d.d = DT1; \ + s.ll = src1; \ + d.ll = src2; \ \ d.VIS_W64(0) = F(s.VIS_W64(0), d.VIS_W64(0)) ? 1 : 0; \ d.VIS_W64(0) |= F(s.VIS_W64(1), d.VIS_W64(1)) ? 2 : 0; \ @@ -381,12 +376,12 @@ VIS_HELPER(helper_fpsub, FSUB) return d.ll; \ } \ \ - uint64_t name##32(CPUState *env) \ + uint64_t name##32(CPUState *env, uint64_t src1, uint64_t src2) \ { \ VIS64 s, d; \ \ - s.d = DT0; \ - d.d = DT1; \ + s.ll = src1; \ + d.ll = src2; \ \ d.VIS_L64(0) = F(s.VIS_L64(0), d.VIS_L64(0)) ? 1 : 0; \ d.VIS_L64(0) |= F(s.VIS_L64(1), d.VIS_L64(1)) ? 2 : 0; \ -- 2.11.0