From 04187ecd57c6ce2550fbcea43966c5cff234b39a Mon Sep 17 00:00:00 2001
From: Johnny Chen <johnny.chen@apple.com>
Date: Sat, 2 Apr 2011 02:24:54 +0000
Subject: [PATCH] Fixed a bug in disassembly of STR_POST, where the immediate
 is the second operand in am2offset; instead of the second operand in
 addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 18 +++++++++++++-----
 test/MC/Disassembler/ARM/arm-tests.txt              |  3 +++
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 884a056ef5d..27683e39751 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1098,12 +1098,20 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
       OpIdx += 1;
     }
 
-    // Disassemble the 12-bit immediate offset, which is the second operand in
-    // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
-    // 
     unsigned Imm12 = slice(insn, 11, 0);
-    int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
-    MI.addOperand(MCOperand::CreateImm(Offset));
+    if (Opcode == ARM::LDRBi12 || Opcode == ARM::LDRi12 ||
+        Opcode == ARM::STRBi12 || Opcode == ARM::STRi12) {
+      // Disassemble the 12-bit immediate offset, which is the second operand in
+      // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).    
+      int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
+      MI.addOperand(MCOperand::CreateImm(Offset));
+    } else {
+      // Disassemble the 12-bit immediate offset, which is the second operand in
+      // $am2offset => (ops GPR, i32imm).
+      unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
+                                          IndexMode);
+      MI.addOperand(MCOperand::CreateImm(Offset));
+    }
     OpIdx += 1;
   } else {
     // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index c66f8ce9688..8a8bcdde932 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -233,3 +233,6 @@
 
 # CHECK:	adcshi	r10, r8, r0, asr r3
 0x50 0xa3 0xb8 0x80
+
+# CHECK:	streq	r1, [sp], #-1567
+0x1f 0x16 0xd 0x4
-- 
2.11.0