From 05f678f55d58f2e0f94f0cf3017486b01c2cbcda Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 13 Aug 2007 00:20:59 +0000 Subject: [PATCH] bfd/ * elf64-ppc.c (ADDI_R12_R12, LD_R11_0R2, LD_R2_0R2): Define. Update stub comments. (build_plt_stub): Build two variants, one without "addis". (ppc_build_one_stub): Build stubs without "addis" if possible. (ppc_size_one_stub): Size new stubs. ld/testsuite/ * ld-powerpc/relbrlt.s (.text.pad2): Adjust space. * ld-powerpc/relbrlt.d: Update. * ld-powerpc/tlsexe.d: Update. * ld-powerpc/tlsexe.g: Update. * ld-powerpc/tlsexe.r: Update. * ld-powerpc/tlsexetoc.d: Update. * ld-powerpc/tlsexetoc.g: Update. * ld-powerpc/tlsexetoc.r: Update. * ld-powerpc/tlsso.d: Update. * ld-powerpc/tlsso.g: Update. * ld-powerpc/tlsso.r: Update. * ld-powerpc/tlstocso.d: Update. * ld-powerpc/tlstocso.g: Update. --- bfd/ChangeLog | 8 ++ bfd/elf64-ppc.c | 157 ++++++++++++++++++++++++++---------- ld/testsuite/ChangeLog | 16 ++++ ld/testsuite/ld-powerpc/relbrlt.d | 18 ++--- ld/testsuite/ld-powerpc/relbrlt.s | 2 +- ld/testsuite/ld-powerpc/tlsexe.d | 12 ++- ld/testsuite/ld-powerpc/tlsexe.g | 2 +- ld/testsuite/ld-powerpc/tlsexe.r | 2 +- ld/testsuite/ld-powerpc/tlsexetoc.d | 14 ++-- ld/testsuite/ld-powerpc/tlsexetoc.g | 2 +- ld/testsuite/ld-powerpc/tlsexetoc.r | 2 +- ld/testsuite/ld-powerpc/tlsso.d | 20 +++-- ld/testsuite/ld-powerpc/tlsso.g | 2 +- ld/testsuite/ld-powerpc/tlsso.r | 6 +- ld/testsuite/ld-powerpc/tlstocso.d | 16 ++-- ld/testsuite/ld-powerpc/tlstocso.g | 2 +- 16 files changed, 185 insertions(+), 96 deletions(-) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 1dc7bf9aa6..d4fe2fe592 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,11 @@ +2007-08-13 Alan Modra + + * elf64-ppc.c (ADDI_R12_R12, LD_R11_0R2, LD_R2_0R2): Define. + Update stub comments. + (build_plt_stub): Build two variants, one without "addis". + (ppc_build_one_stub): Build stubs without "addis" if possible. + (ppc_size_one_stub): Size new stubs. + 2007-08-11 Richard Sandiford * config.bfd (sh-*-vxworks): Define targ_underscore to "yes". diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c index 1234b9ae5f..c55f3e6396 100644 --- a/bfd/elf64-ppc.c +++ b/bfd/elf64-ppc.c @@ -131,21 +131,25 @@ static bfd_vma opd_entry_value /* .plt call stub instructions. The normal stub is like this, but sometimes the .plt entry crosses a 64k boundary and we need to - insert an addis to adjust r12. */ + insert an addi to adjust r12. */ #define PLT_CALL_STUB_SIZE (7*4) #define ADDIS_R12_R2 0x3d820000 /* addis %r12,%r2,xxx@ha */ #define STD_R2_40R1 0xf8410028 /* std %r2,40(%r1) */ #define LD_R11_0R12 0xe96c0000 /* ld %r11,xxx+0@l(%r12) */ -#define LD_R2_0R12 0xe84c0000 /* ld %r2,xxx+8@l(%r12) */ #define MTCTR_R11 0x7d6903a6 /* mtctr %r11 */ +#define LD_R2_0R12 0xe84c0000 /* ld %r2,xxx+8@l(%r12) */ /* ld %r11,xxx+16@l(%r12) */ #define BCTR 0x4e800420 /* bctr */ #define ADDIS_R12_R12 0x3d8c0000 /* addis %r12,%r12,off@ha */ +#define ADDI_R12_R12 0x398c0000 /* addi %r12,%r12,off@l */ #define ADDIS_R2_R2 0x3c420000 /* addis %r2,%r2,off@ha */ #define ADDI_R2_R2 0x38420000 /* addi %r2,%r2,off@l */ +#define LD_R11_0R2 0xe9620000 /* ld %r11,xxx+0(%r2) */ +#define LD_R2_0R2 0xe8420000 /* ld %r2,xxx+0(%r2) */ + #define LD_R2_40R1 0xe8410028 /* ld %r2,40(%r1) */ /* glink call stub instructions. We enter with the index in R0. */ @@ -3235,13 +3239,12 @@ struct plt_entry ppc_stub_plt_call: Used to call a function in a shared library. If it so happens that the plt entry referenced crosses a 64k boundary, then an extra - "addis %r12,%r12,1" will be inserted before the load at xxx+8 or - xxx+16 as appropriate. + "addi %r12,%r12,xxx@toc@l" will be inserted before the "mtctr". . addis %r12,%r2,xxx@toc@ha . std %r2,40(%r1) . ld %r11,xxx+0@toc@l(%r12) - . ld %r2,xxx+8@toc@l(%r12) . mtctr %r11 + . ld %r2,xxx+8@toc@l(%r12) . ld %r11,xxx+16@toc@l(%r12) . bctr @@ -3261,6 +3264,9 @@ struct plt_entry . addi %r2,%r2,off@l . mtctr %r11 . bctr + + In cases where the "addis" instruction would add zero, the "addis" is + omitted and following instructions modified slightly in some cases. */ enum ppc_stub_type { @@ -8193,19 +8199,35 @@ build_plt_stub (bfd *obfd, bfd_byte *p, int offset) #define PPC_HI(v) (((v) >> 16) & 0xffff) #define PPC_HA(v) PPC_HI ((v) + 0x8000) - bfd_put_32 (obfd, ADDIS_R12_R2 | PPC_HA (offset), p), p += 4; - bfd_put_32 (obfd, STD_R2_40R1, p), p += 4; - bfd_put_32 (obfd, LD_R11_0R12 | PPC_LO (offset), p), p += 4; - if (PPC_HA (offset + 8) != PPC_HA (offset)) - bfd_put_32 (obfd, ADDIS_R12_R12 | 1, p), p += 4; - offset += 8; - bfd_put_32 (obfd, LD_R2_0R12 | PPC_LO (offset), p), p += 4; - if (PPC_HA (offset + 8) != PPC_HA (offset)) - bfd_put_32 (obfd, ADDIS_R12_R12 | 1, p), p += 4; - offset += 8; - bfd_put_32 (obfd, MTCTR_R11, p), p += 4; - bfd_put_32 (obfd, LD_R11_0R12 | PPC_LO (offset), p), p += 4; - bfd_put_32 (obfd, BCTR, p), p += 4; + if (PPC_HA (offset) != 0) + { + bfd_put_32 (obfd, ADDIS_R12_R2 | PPC_HA (offset), p), p += 4; + bfd_put_32 (obfd, STD_R2_40R1, p), p += 4; + bfd_put_32 (obfd, LD_R11_0R12 | PPC_LO (offset), p), p += 4; + if (PPC_HA (offset + 16) != PPC_HA (offset)) + { + bfd_put_32 (obfd, ADDI_R12_R12 | PPC_LO (offset), p), p += 4; + offset = 0; + } + bfd_put_32 (obfd, MTCTR_R11, p), p += 4; + bfd_put_32 (obfd, LD_R2_0R12 | PPC_LO (offset + 8), p), p += 4; + bfd_put_32 (obfd, LD_R11_0R12 | PPC_LO (offset + 16), p), p += 4; + bfd_put_32 (obfd, BCTR, p), p += 4; + } + else + { + bfd_put_32 (obfd, STD_R2_40R1, p), p += 4; + bfd_put_32 (obfd, LD_R11_0R2 | PPC_LO (offset), p), p += 4; + if (PPC_HA (offset + 16) != PPC_HA (offset)) + { + bfd_put_32 (obfd, ADDI_R2_R2 | PPC_LO (offset), p), p += 4; + offset = 0; + } + bfd_put_32 (obfd, MTCTR_R11, p), p += 4; + bfd_put_32 (obfd, LD_R11_0R2 | PPC_LO (offset + 16), p), p += 4; + bfd_put_32 (obfd, LD_R2_0R2 | PPC_LO (offset + 8), p), p += 4; + bfd_put_32 (obfd, BCTR, p), p += 4; + } return p; } @@ -8248,9 +8270,8 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) + stub_entry->stub_sec->output_offset + stub_entry->stub_sec->output_section->vma); - if (stub_entry->stub_type != ppc_stub_long_branch_r2off) - size = 4; - else + size = 4; + if (stub_entry->stub_type == ppc_stub_long_branch_r2off) { bfd_vma r2off; @@ -8258,12 +8279,16 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) - htab->stub_group[stub_entry->id_sec->id].toc_off); bfd_put_32 (htab->stub_bfd, STD_R2_40R1, loc); loc += 4; - bfd_put_32 (htab->stub_bfd, ADDIS_R2_R2 | PPC_HA (r2off), loc); - loc += 4; + size = 12; + if (PPC_HA (r2off) != 0) + { + size = 16; + bfd_put_32 (htab->stub_bfd, ADDIS_R2_R2 | PPC_HA (r2off), loc); + loc += 4; + } bfd_put_32 (htab->stub_bfd, ADDI_R2_R2 | PPC_LO (r2off), loc); loc += 4; - off -= 12; - size = 16; + off -= size - 4; } bfd_put_32 (htab->stub_bfd, B_DOT | (off & 0x3fffffc), loc); @@ -8420,10 +8445,18 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) indx = off; if (stub_entry->stub_type != ppc_stub_plt_branch_r2off) { - bfd_put_32 (htab->stub_bfd, ADDIS_R12_R2 | PPC_HA (indx), loc); - loc += 4; - bfd_put_32 (htab->stub_bfd, LD_R11_0R12 | PPC_LO (indx), loc); - size = 16; + if (PPC_HA (indx) != 0) + { + size = 16; + bfd_put_32 (htab->stub_bfd, ADDIS_R12_R2 | PPC_HA (indx), loc); + loc += 4; + bfd_put_32 (htab->stub_bfd, LD_R11_0R12 | PPC_LO (indx), loc); + } + else + { + size = 12; + bfd_put_32 (htab->stub_bfd, LD_R11_0R2 | PPC_LO (indx), loc); + } } else { @@ -8433,14 +8466,28 @@ ppc_build_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) - htab->stub_group[stub_entry->id_sec->id].toc_off); bfd_put_32 (htab->stub_bfd, STD_R2_40R1, loc); loc += 4; - bfd_put_32 (htab->stub_bfd, ADDIS_R12_R2 | PPC_HA (indx), loc); - loc += 4; - bfd_put_32 (htab->stub_bfd, LD_R11_0R12 | PPC_LO (indx), loc); - loc += 4; - bfd_put_32 (htab->stub_bfd, ADDIS_R2_R2 | PPC_HA (r2off), loc); - loc += 4; + size = 20; + if (PPC_HA (indx) != 0) + { + size += 4; + bfd_put_32 (htab->stub_bfd, ADDIS_R12_R2 | PPC_HA (indx), loc); + loc += 4; + bfd_put_32 (htab->stub_bfd, LD_R11_0R12 | PPC_LO (indx), loc); + loc += 4; + } + else + { + bfd_put_32 (htab->stub_bfd, LD_R11_0R2 | PPC_LO (indx), loc); + loc += 4; + } + + if (PPC_HA (r2off) != 0) + { + size += 4; + bfd_put_32 (htab->stub_bfd, ADDIS_R2_R2 | PPC_HA (r2off), loc); + loc += 4; + } bfd_put_32 (htab->stub_bfd, ADDI_R2_R2 | PPC_LO (r2off), loc); - size = 28; } loc += 4; bfd_put_32 (htab->stub_bfd, MTCTR_R11, loc); @@ -8579,6 +8626,8 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) - htab->stub_group[stub_entry->id_sec->id].toc_off); size = PLT_CALL_STUB_SIZE; + if (PPC_HA (off) == 0) + size -= 4; if (PPC_HA (off + 16) != PPC_HA (off)) size += 4; } @@ -8586,6 +8635,8 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) { /* ppc_stub_long_branch or ppc_stub_plt_branch, or their r2off variants. */ + bfd_vma r2off = 0; + off = (stub_entry->target_value + stub_entry->target_section->output_offset + stub_entry->target_section->output_section->vma); @@ -8601,14 +8652,19 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) size = 4; if (stub_entry->stub_type == ppc_stub_long_branch_r2off) { - off -= 12; - size = 16; + r2off = (htab->stub_group[stub_entry->target_section->id].toc_off + - htab->stub_group[stub_entry->id_sec->id].toc_off); + size = 12; + if (PPC_HA (r2off) != 0) + size = 16; + off -= size - 4; } /* If the branch offset if too big, use a ppc_stub_plt_branch. */ if (off + (1 << 25) >= (bfd_vma) (1 << 26)) { struct ppc_branch_hash_entry *br_entry; + unsigned int indx; br_entry = ppc_branch_hash_lookup (&htab->branch_hash_table, stub_entry->root.string + 9, @@ -8637,9 +8693,28 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg) } stub_entry->stub_type += ppc_stub_plt_branch - ppc_stub_long_branch; - size = 16; - if (stub_entry->stub_type != ppc_stub_plt_branch) - size = 28; + off = (br_entry->offset + + htab->brlt->output_offset + + htab->brlt->output_section->vma + - elf_gp (htab->brlt->output_section->owner) + - htab->stub_group[stub_entry->id_sec->id].toc_off); + + indx = off; + if (stub_entry->stub_type != ppc_stub_plt_branch_r2off) + { + size = 12; + if (PPC_HA (indx) != 0) + size = 16; + } + else + { + size = 20; + if (PPC_HA (indx) != 0) + size += 4; + + if (PPC_HA (r2off) != 0) + size += 4; + } } else if (info->emitrelocations) { diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index 02807f2e39..af099088e8 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,19 @@ +2007-08-13 Alan Modra + + * ld-powerpc/relbrlt.s (.text.pad2): Adjust space. + * ld-powerpc/relbrlt.d: Update. + * ld-powerpc/tlsexe.d: Update. + * ld-powerpc/tlsexe.g: Update. + * ld-powerpc/tlsexe.r: Update. + * ld-powerpc/tlsexetoc.d: Update. + * ld-powerpc/tlsexetoc.g: Update. + * ld-powerpc/tlsexetoc.r: Update. + * ld-powerpc/tlsso.d: Update. + * ld-powerpc/tlsso.g: Update. + * ld-powerpc/tlsso.r: Update. + * ld-powerpc/tlstocso.d: Update. + * ld-powerpc/tlstocso.g: Update. + 2007-08-06 Kai Tietz PR ld/4877 diff --git a/ld/testsuite/ld-powerpc/relbrlt.d b/ld/testsuite/ld-powerpc/relbrlt.d index 1bba8aaa9f..172c60f798 100644 --- a/ld/testsuite/ld-powerpc/relbrlt.d +++ b/ld/testsuite/ld-powerpc/relbrlt.d @@ -8,13 +8,13 @@ Disassembly of section \.text: 0*100000b0 <_start>: -[0-9a-f ]*: 49 bf 00 31 bl .* -[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e0044 +[0-9a-f ]*: 49 bf 00 2d bl .* +[0-9a-f ]*: R_PPC64_REL24 \.text\+0x37e003c [0-9a-f ]*: 60 00 00 00 nop [0-9a-f ]*: 49 bf 00 19 bl .* [0-9a-f ]*: R_PPC64_REL24 \.text\+0x3bf0020 [0-9a-f ]*: 60 00 00 00 nop -[0-9a-f ]*: 49 bf 00 25 bl .* +[0-9a-f ]*: 49 bf 00 21 bl .* [0-9a-f ]*: R_PPC64_REL24 \.text\+0x57e0024 [0-9a-f ]*: 60 00 00 00 nop [0-9a-f ]*: 00 00 00 00 \.long 0x0 @@ -22,23 +22,21 @@ Disassembly of section \.text: \.\.\. [0-9a-f ]*<.*plt_branch.*>: -[0-9a-f ]*: 3d 82 00 00 addis r12,r2,0 -[0-9a-f ]*: e9 6c 80 00 ld r11,-32768\(r12\) +[0-9a-f ]*: e9 62 80 00 ld r11,-32768\(r2\) [0-9a-f ]*: 7d 69 03 a6 mtctr r11 [0-9a-f ]*: 4e 80 04 20 bctr [0-9a-f ]*<.*long_branch.*>: -[0-9a-f ]*: 49 bf 00 14 b .* -[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00f4 +[0-9a-f ]*: 49 bf 00 10 b .* +[0-9a-f ]*: R_PPC64_REL24 \*ABS\*\+0x137e00ec [0-9a-f ]*<.*plt_branch.*>: -[0-9a-f ]*: 3d 82 00 00 addis r12,r2,0 -[0-9a-f ]*: e9 6c 80 08 ld r11,-32760\(r12\) +[0-9a-f ]*: e9 62 80 08 ld r11,-32760\(r2\) [0-9a-f ]*: 7d 69 03 a6 mtctr r11 [0-9a-f ]*: 4e 80 04 20 bctr \.\.\. -0*137e00f4 : +0*137e00ec : [0-9a-f ]*: 4e 80 00 20 blr \.\.\. diff --git a/ld/testsuite/ld-powerpc/relbrlt.s b/ld/testsuite/ld-powerpc/relbrlt.s index eed2f3350d..cee0cddfda 100644 --- a/ld/testsuite/ld-powerpc/relbrlt.s +++ b/ld/testsuite/ld-powerpc/relbrlt.s @@ -20,7 +20,7 @@ far: blr .section .text.pad2,"ax" - .space 0x40ffd8 + .space 0x40ffe0 .section .text.far2far,"ax" far2far: diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d index 26599ac59e..825434eb61 100644 --- a/ld/testsuite/ld-powerpc/tlsexe.d +++ b/ld/testsuite/ld-powerpc/tlsexe.d @@ -8,13 +8,12 @@ Disassembly of section \.text: -.* <_start-0x1c>: -.* 3d 82 00 00 addis r12,r2,0 +.* <_start-0x18>: .* f8 41 00 28 std r2,40\(r1\) -.* e9 6c 80 48 ld r11,-32696\(r12\) -.* e8 4c 80 50 ld r2,-32688\(r12\) +.* e9 62 80 48 ld r11,-32696\(r2\) .* 7d 69 03 a6 mtctr r11 -.* e9 6c 80 58 ld r11,-32680\(r12\) +.* e9 62 80 58 ld r11,-32680\(r2\) +.* e8 42 80 50 ld r2,-32688\(r2\) .* 4e 80 04 20 bctr .* <_start>: @@ -22,7 +21,7 @@ Disassembly of section \.text: .* 60 00 00 00 nop .* 7c 63 6a 14 add r3,r3,r13 .* 38 62 80 18 addi r3,r2,-32744 -.* 4b ff ff d5 bl .* +.* 4b ff ff d9 bl .* .* e8 41 00 28 ld r2,40\(r1\) .* 3c 6d 00 00 addis r3,r13,0 .* 60 00 00 00 nop @@ -56,7 +55,6 @@ Disassembly of section \.text: .* e9 4d 90 2a lwa r10,-28632\(r13\) .* 3d 2d 00 00 addis r9,r13,0 .* a9 49 90 30 lha r10,-28624\(r9\) -.* 60 00 00 00 nop .* 00 00 00 00 .* .* 00 01 01 f0 .* .* 7d 88 02 a6 mflr r12 diff --git a/ld/testsuite/ld-powerpc/tlsexe.g b/ld/testsuite/ld-powerpc/tlsexe.g index 6f9aa974d7..58280df0aa 100644 --- a/ld/testsuite/ld-powerpc/tlsexe.g +++ b/ld/testsuite/ld-powerpc/tlsexe.g @@ -7,6 +7,6 @@ .*: +file format elf64-powerpc Contents of section \.got: -.* 00000000 100185d0 ffffffff ffff8018 .* +.* 00000000 100185c8 ffffffff ffff8018 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* diff --git a/ld/testsuite/ld-powerpc/tlsexe.r b/ld/testsuite/ld-powerpc/tlsexe.r index 4992ab2fd2..296d814ec8 100644 --- a/ld/testsuite/ld-powerpc/tlsexe.r +++ b/ld/testsuite/ld-powerpc/tlsexe.r @@ -16,7 +16,7 @@ Section Headers: +\[ 4\] \.dynstr +.* +\[ 5\] \.rela\.dyn +.* +\[ 6\] \.rela\.plt +.* - +\[ 7\] \.text +PROGBITS .* 0+100 0+ +AX +0 +0 +8 + +\[ 7\] \.text +PROGBITS .* 0+f8 0+ +AX +0 +0 +8 +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d index c1cb190b1c..d6a0388813 100644 --- a/ld/testsuite/ld-powerpc/tlsexetoc.d +++ b/ld/testsuite/ld-powerpc/tlsexetoc.d @@ -8,21 +8,20 @@ Disassembly of section \.text: -.* <_start-0x1c>: -.* 3d 82 00 00 addis r12,r2,0 +.* <_start-0x18>: .* f8 41 00 28 std r2,40\(r1\) -.* e9 6c 80 70 ld r11,-32656\(r12\) -.* e8 4c 80 78 ld r2,-32648\(r12\) +.* e9 62 80 70 ld r11,-32656\(r2\) .* 7d 69 03 a6 mtctr r11 -.* e9 6c 80 80 ld r11,-32640\(r12\) +.* e9 62 80 80 ld r11,-32640\(r2\) +.* e8 42 80 78 ld r2,-32648\(r2\) .* 4e 80 04 20 bctr .* <_start>: .* 38 62 80 08 addi r3,r2,-32760 -.* 4b ff ff e1 bl .* +.* 4b ff ff e5 bl .* .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 18 addi r3,r2,-32744 -.* 4b ff ff d5 bl .* +.* 4b ff ff d9 bl .* .* e8 41 00 28 ld r2,40\(r1\) .* 3c 6d 00 00 addis r3,r13,0 .* 60 00 00 00 nop @@ -40,7 +39,6 @@ Disassembly of section \.text: .* 89 4d 90 60 lbz r10,-28576\(r13\) .* 3d 2d 00 00 addis r9,r13,0 .* 99 49 90 68 stb r10,-28568\(r9\) -.* 60 00 00 00 nop .* 00 00 00 00 .* .* 00 01 02 18 .* .* 7d 88 02 a6 mflr r12 diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.g b/ld/testsuite/ld-powerpc/tlsexetoc.g index 06be9d15dc..df3994ceb0 100644 --- a/ld/testsuite/ld-powerpc/tlsexetoc.g +++ b/ld/testsuite/ld-powerpc/tlsexetoc.g @@ -7,7 +7,7 @@ .*: +file format elf64-powerpc Contents of section \.got: -.* 00000000 10018570 00000000 00000000 .* +.* 00000000 10018568 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000001 .* .* 00000000 00000000 00000000 00000001 .* diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.r b/ld/testsuite/ld-powerpc/tlsexetoc.r index d92edd4a25..539269a57d 100644 --- a/ld/testsuite/ld-powerpc/tlsexetoc.r +++ b/ld/testsuite/ld-powerpc/tlsexetoc.r @@ -16,7 +16,7 @@ Section Headers: +\[ 4\] \.dynstr +.* +\[ 5\] \.rela\.dyn +.* +\[ 6\] \.rela\.plt +.* - +\[ 7\] \.text +PROGBITS .* 0+c0 0+ +AX +0 +0 +8 + +\[ 7\] \.text +PROGBITS .* 0+b8 0+ +AX +0 +0 +8 +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d index 0dbc84909c..3fa4029d5a 100644 --- a/ld/testsuite/ld-powerpc/tlsso.d +++ b/ld/testsuite/ld-powerpc/tlsso.d @@ -9,26 +9,25 @@ Disassembly of section \.text: .* <\.__tls_get_addr>: -.* 3d 82 00 00 addis r12,r2,0 .* f8 41 00 28 std r2,40\(r1\) -.* e9 6c 80 78 ld r11,-32648\(r12\) -.* e8 4c 80 80 ld r2,-32640\(r12\) +.* e9 62 80 78 ld r11,-32648\(r2\) .* 7d 69 03 a6 mtctr r11 -.* e9 6c 80 88 ld r11,-32632\(r12\) +.* e9 62 80 88 ld r11,-32632\(r2\) +.* e8 42 80 80 ld r2,-32640\(r2\) .* 4e 80 04 20 bctr .* <_start>: .* 38 62 80 30 addi r3,r2,-32720 -.* 4b ff ff e1 bl .* <\.__tls_get_addr> +.* 4b ff ff e5 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 08 addi r3,r2,-32760 -.* 4b ff ff d5 bl .* <\.__tls_get_addr> +.* 4b ff ff d9 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 48 addi r3,r2,-32696 -.* 4b ff ff c9 bl .* <\.__tls_get_addr> +.* 4b ff ff cd bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 08 addi r3,r2,-32760 -.* 4b ff ff bd bl .* <\.__tls_get_addr> +.* 4b ff ff c1 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 39 23 80 40 addi r9,r3,-32704 .* 3d 23 00 00 addis r9,r3,0 @@ -41,10 +40,10 @@ Disassembly of section \.text: .* 3d 2d 00 00 addis r9,r13,0 .* 99 49 00 00 stb r10,0\(r9\) .* 38 62 80 18 addi r3,r2,-32744 -.* 4b ff ff 89 bl .* <\.__tls_get_addr> +.* 4b ff ff 8d bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 08 addi r3,r2,-32760 -.* 4b ff ff 7d bl .* <\.__tls_get_addr> +.* 4b ff ff 81 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* f9 43 80 08 std r10,-32760\(r3\) .* 3d 23 00 00 addis r9,r3,0 @@ -56,7 +55,6 @@ Disassembly of section \.text: .* e9 4d 00 02 lwa r10,0\(r13\) .* 3d 2d 00 00 addis r9,r13,0 .* a9 49 00 00 lha r10,0\(r9\) -.* 60 00 00 00 nop .* 00 00 00 00 .* .* 00 01 02 20 .* .* 7d 88 02 a6 mflr r12 diff --git a/ld/testsuite/ld-powerpc/tlsso.g b/ld/testsuite/ld-powerpc/tlsso.g index 82ccc8dc9d..330cb18242 100644 --- a/ld/testsuite/ld-powerpc/tlsso.g +++ b/ld/testsuite/ld-powerpc/tlsso.g @@ -7,7 +7,7 @@ .*: +file format elf64-powerpc Contents of section \.got: -.* 00000000 00018780 00000000 00000000 .* +.* 00000000 00018778 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* diff --git a/ld/testsuite/ld-powerpc/tlsso.r b/ld/testsuite/ld-powerpc/tlsso.r index 69fff679ac..e40c78d97d 100644 --- a/ld/testsuite/ld-powerpc/tlsso.r +++ b/ld/testsuite/ld-powerpc/tlsso.r @@ -49,9 +49,9 @@ Relocation section '\.rela\.dyn' at offset .* contains 16 entries: [0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0 [0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0 [0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0 -[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f8 \.tdata \+ 28 -[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f8 \.tdata \+ 30 -[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f8 \.tdata \+ 30 +[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f0 \.tdata \+ 28 +[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f0 \.tdata \+ 30 +[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f0 \.tdata \+ 30 [0-9a-f ]+R_PPC64_DTPMOD64 +0+ [0-9a-f ]+R_PPC64_DTPMOD64 +0+ [0-9a-f ]+R_PPC64_DTPREL64 +0+ diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d index 073e85da50..deaf2a7818 100644 --- a/ld/testsuite/ld-powerpc/tlstocso.d +++ b/ld/testsuite/ld-powerpc/tlstocso.d @@ -9,26 +9,25 @@ Disassembly of section \.text: .* <\.__tls_get_addr>: -.* 3d 82 00 00 addis r12,r2,0 .* f8 41 00 28 std r2,40\(r1\) -.* e9 6c 80 70 ld r11,-32656\(r12\) -.* e8 4c 80 78 ld r2,-32648\(r12\) +.* e9 62 80 70 ld r11,-32656\(r2\) .* 7d 69 03 a6 mtctr r11 -.* e9 6c 80 80 ld r11,-32640\(r12\) +.* e9 62 80 80 ld r11,-32640\(r2\) +.* e8 42 80 78 ld r2,-32648\(r2\) .* 4e 80 04 20 bctr .* <_start>: .* 38 62 80 08 addi r3,r2,-32760 -.* 4b ff ff e1 bl .* <\.__tls_get_addr> +.* 4b ff ff e5 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 18 addi r3,r2,-32744 -.* 4b ff ff d5 bl .* <\.__tls_get_addr> +.* 4b ff ff d9 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 28 addi r3,r2,-32728 -.* 4b ff ff c9 bl .* <\.__tls_get_addr> +.* 4b ff ff cd bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 38 62 80 38 addi r3,r2,-32712 -.* 4b ff ff bd bl .* <\.__tls_get_addr> +.* 4b ff ff c1 bl .* <\.__tls_get_addr> .* e8 41 00 28 ld r2,40\(r1\) .* 39 23 80 40 addi r9,r3,-32704 .* 3d 23 00 00 addis r9,r3,0 @@ -40,7 +39,6 @@ Disassembly of section \.text: .* 89 4d 00 00 lbz r10,0\(r13\) .* 3d 2d 00 00 addis r9,r13,0 .* 99 49 00 00 stb r10,0\(r9\) -.* 60 00 00 00 nop .* 00 00 00 00 .* .* 00 01 02 18 .* .* 7d 88 02 a6 mflr r12 diff --git a/ld/testsuite/ld-powerpc/tlstocso.g b/ld/testsuite/ld-powerpc/tlstocso.g index dbe78976cc..d670a21329 100644 --- a/ld/testsuite/ld-powerpc/tlstocso.g +++ b/ld/testsuite/ld-powerpc/tlstocso.g @@ -7,7 +7,7 @@ .*: +file format elf64-powerpc Contents of section \.got: -.* 00000000 000186c8 00000000 00000000 .* +.* 00000000 000186c0 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* -- 2.11.0