From 0be32ace8c3ab46d9001636f849b7117bb3635c8 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Fri, 8 Jul 2016 17:01:15 +0000
Subject: [PATCH] [InstCombine] allow or(sext(A), B) --> A ? -1 : B transform
 for vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274883 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 9 +++++----
 test/Transforms/InstCombine/or.ll                  | 6 ++----
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index b5b320f29c5..f6ec03b9721 100644
--- a/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2393,11 +2393,12 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) {
   if (Instruction *CastedOr = foldCastedBitwiseLogic(I))
     return CastedOr;
 
-  // or(sext(A), B) -> A ? -1 : B where A is an i1
-  // or(A, sext(B)) -> B ? -1 : A where B is an i1
-  if (match(Op0, m_SExt(m_Value(A))) && A->getType()->isIntegerTy(1))
+  // or(sext(A), B) / or(B, sext(A)) --> A ? -1 : B, where A is i1 or <N x i1>.
+  if (match(Op0, m_SExt(m_Value(A))) &&
+      A->getType()->getScalarType()->isIntegerTy(1))
     return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op1);
-  if (match(Op1, m_SExt(m_Value(A))) && A->getType()->isIntegerTy(1))
+  if (match(Op1, m_SExt(m_Value(A))) &&
+      A->getType()->getScalarType()->isIntegerTy(1))
     return SelectInst::Create(A, ConstantInt::getSigned(I.getType(), -1), Op0);
 
   // Note: If we've gotten to the point of visiting the outer OR, then the
diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll
index 779edd63528..8cec10c1f65 100644
--- a/test/Transforms/InstCombine/or.ll
+++ b/test/Transforms/InstCombine/or.ll
@@ -447,8 +447,7 @@ define i32 @orsext_to_sel_swap(i32 %x, i1 %y) {
 
 define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
 ; CHECK-LABEL: @orsext_to_sel_vec(
-; CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> %y to <2 x i32>
-; CHECK-NEXT:    [[OR:%.*]] = or <2 x i32> [[SEXT]], %x
+; CHECK-NEXT:    [[OR:%.*]] = select <2 x i1> %y, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %x
 ; CHECK-NEXT:    ret <2 x i32> [[OR]]
 ;
   %sext = sext <2 x i1> %y to <2 x i32>
@@ -458,8 +457,7 @@ define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
 
 define <2 x i132> @orsext_to_sel_vec_swap(<2 x i132> %x, <2 x i1> %y) {
 ; CHECK-LABEL: @orsext_to_sel_vec_swap(
-; CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> %y to <2 x i132>
-; CHECK-NEXT:    [[OR:%.*]] = or <2 x i132> [[SEXT]], %x
+; CHECK-NEXT:    [[OR:%.*]] = select <2 x i1> %y, <2 x i132> <i132 -1, i132 -1>, <2 x i132> %x
 ; CHECK-NEXT:    ret <2 x i132> [[OR]]
 ;
   %sext = sext <2 x i1> %y to <2 x i132>
-- 
2.11.0