From 0db7ad3687e9639c45d598ce0f4ce2cbeedf8840 Mon Sep 17 00:00:00 2001 From: Nicolas Geoffray Date: Fri, 3 Oct 2014 10:07:42 +0000 Subject: [PATCH] Revert "Rename registers in arm64." This reverts commit 11daa0adbb30f341ccbdec64a2d43d8eeb111288. Change-Id: I2ce0879dce8fbf5512649d0d9c3a2c189c23dd5f --- runtime/arch/arm64/registers_arm64.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/runtime/arch/arm64/registers_arm64.h b/runtime/arch/arm64/registers_arm64.h index 7b7a46053..9ccab70bb 100644 --- a/runtime/arch/arm64/registers_arm64.h +++ b/runtime/arch/arm64/registers_arm64.h @@ -56,16 +56,15 @@ enum Register { X29 = 29, X30 = 30, X31 = 31, - SP = 32, // SP and XZR are encoded in instructions using the register - // code 31, the context deciding which is used. We use a - // different enum value to distinguish between the two. - TR = X18, // ART Thread Register - Managed Runtime (Caller Saved Reg) - ETR = X21, // ART Thread Register - External Calls (Callee Saved Reg) - IP0 = X16, // Used as scratch by VIXL. - IP1 = X17, // Used as scratch by ART JNI Assembler. - FP = X29, - LR = X30, - XZR = X31, + TR = 18, // ART Thread Register - Managed Runtime (Caller Saved Reg) + ETR = 21, // ART Thread Register - External Calls (Callee Saved Reg) + IP0 = 16, // Used as scratch by VIXL. + IP1 = 17, // Used as scratch by ART JNI Assembler. + FP = 29, + LR = 30, + SP = 31, // SP is X31 and overlaps with XRZ but we encode it as a + // special register, due to the different instruction semantics. + XZR = 32, kNumberOfCoreRegisters = 33, kNoRegister = -1, }; @@ -105,7 +104,7 @@ enum WRegister { W29 = 29, W30 = 30, W31 = 31, - WZR = W31, + WZR = 31, kNumberOfWRegisters = 32, kNoWRegister = -1, }; -- 2.11.0