From 0ed1f764f4e0d4cc940052e8ccca260bf5c39407 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Mon, 7 May 2012 03:13:22 +0000 Subject: [PATCH] Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsISelLowering.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index bb36d76ab75..be22fed2f45 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -3056,8 +3056,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'r': if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); - assert(VT == MVT::i64 && "Unexpected type."); - return std::make_pair(0U, &Mips::CPU64RegsRegClass); + if (VT == MVT::i64 && HasMips64) + return std::make_pair(0U, &Mips::CPU64RegsRegClass); + // This will generate an error message + return std::make_pair(0u, static_cast(0)); case 'f': if (VT == MVT::f32) return std::make_pair(0U, &Mips::FGR32RegClass); -- 2.11.0