From 1393f652d71c0c84faba5a69fbb02aa459b8f8de Mon Sep 17 00:00:00 2001 From: Chris Demetriou Date: Tue, 30 Sep 2003 16:17:15 +0000 Subject: [PATCH] [ bfd/ChangeLog ] 2003-09-30 Chris Demetriou * archures.c (bfd_mach_mipsisa64r2): New define. * bfd-in2.h: Regenerate. * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. * cpu-mips.c (I_mipsisa64r2): New enum value. (arch_info_struct): Add entry for I_mipsisa64r2. * elfxx-mips.c (_bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. [ binutils/ChangeLog ] 2003-09-30 Chris Demetriou * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. [ gas/Changelog ] 2003-09-30 Chris Demetriou * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs. * configure: Regenerate. * config/tc-mips.c (imm2_expr): New variable. (md_assemble, mips16_ip): Initialize imm2_expr. (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. (macro): Handle M_DEXT and M_DINS. (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. (mips_ip): Likewise. (OPTION_MIPS64R2): New define. (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. (md_parse_option): Handle OPTION_MIPS64R2. (s_mipsset): Handle setting "mips64r2" ISA. (mips_cpu_info_table): Add mips64r2. (md_show_usage): Document -mips64r2 option. * doc/as.texinfo: Docuemnt -mips64r2 option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou * gas/mips/cp0-names-mips64r2.d: New file. * gas/mips/cp0sel-names-mips64r2.d: New file. * gas/mips/elf_arch_mips64r2.d: New file. * gas/mips/hwr-names-mips64r2.d: New file. * gas/mips/mips32r2-ill-fp64.l: New file. * gas/mips/mips32r2-ill-fp64.s: New file. * gas/mips/mips64r2-ill.l: New file. * gas/mips/mips64r2-ill.s: New file. * gas/mips/mips64r2.d: New file. * gas/mips/mips64r2.s: New file. * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. [ include/elf/ChangeLog ] 2003-09-30 Chris Demetriou * mips.h (E_MIPS_ARCH_64R2): New define. [ include/opcode/ChangeLog ] 2003-09-30 Chris Demetriou * mips.h: Document +E, +F, +G, +H, and +I operand types. Update documentation of I, +B and +C operand types. (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. (M_DEXT, M_DINS): New enum values. [ ld/ChangeLog ] 2003-09-30 Chris Demetriou * ldmain.c (get_emulation): Ignore "-mips64r2". [ ld/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations with MIPS64r2. [ opcodes/ChangeLog ] 2003-09-30 Chris Demetriou * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" (print_insn_args): Add handing for +E, +F, +G, and +H. * mips-opc.c (I65): New define for MIPS64r2. (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to be supported on MIPS64r2. --- bfd/ChangeLog | 12 ++++++++++++ bfd/aoutx.h | 1 + bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/cpu-mips.c | 2 ++ bfd/elfxx-mips.c | 11 +++++++++++ include/elf/ChangeLog | 4 ++++ include/elf/mips.h | 3 +++ include/opcode/ChangeLog | 7 +++++++ include/opcode/mips.h | 28 ++++++++++++++++++++++++---- opcodes/ChangeLog | 10 ++++++++++ opcodes/mips-dis.c | 22 ++++++++++++++++++++++ opcodes/mips-opc.c | 23 ++++++++++++++++++++--- 13 files changed, 118 insertions(+), 7 deletions(-) diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 92dbe68c60..aae16dbe95 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,15 @@ +2003-09-30 Chris Demetriou + + * archures.c (bfd_mach_mipsisa64r2): New define. + * bfd-in2.h: Regenerate. + * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. + * cpu-mips.c (I_mipsisa64r2): New enum value. + (arch_info_struct): Add entry for I_mipsisa64r2. + * elfxx-mips.c (_bfd_elf_mips_mach) + (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. + (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. + (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. + 2003-09-29 H.J. Lu * elfxx-ia64.c (elfNN_hpux_backend_symbol_processing): New. diff --git a/bfd/aoutx.h b/bfd/aoutx.h index 674fc76316..3c495380d1 100644 --- a/bfd/aoutx.h +++ b/bfd/aoutx.h @@ -801,6 +801,7 @@ NAME(aout,machine_type) (arch, machine, unknown) case bfd_mach_mipsisa32r2: case bfd_mach_mips5: case bfd_mach_mipsisa64: + case bfd_mach_mipsisa64r2: case bfd_mach_mips_sb1: /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ arch_flags = M_MIPS2; diff --git a/bfd/archures.c b/bfd/archures.c index 9033f2826d..c79e925bb3 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -148,6 +148,7 @@ DESCRIPTION .#define bfd_mach_mipsisa32 32 .#define bfd_mach_mipsisa32r2 33 .#define bfd_mach_mipsisa64 64 +.#define bfd_mach_mipsisa64r2 65 . bfd_arch_i386, {* Intel 386 *} .#define bfd_mach_i386_i386 1 .#define bfd_mach_i386_i8086 2 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index a7cca3e26c..d74fc1c48e 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1577,6 +1577,7 @@ enum bfd_architecture #define bfd_mach_mipsisa32 32 #define bfd_mach_mipsisa32r2 33 #define bfd_mach_mipsisa64 64 +#define bfd_mach_mipsisa64r2 65 bfd_arch_i386, /* Intel 386 */ #define bfd_mach_i386_i386 1 #define bfd_mach_i386_i8086 2 diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c index e64ee069c5..10d4e4775d 100644 --- a/bfd/cpu-mips.c +++ b/bfd/cpu-mips.c @@ -85,6 +85,7 @@ enum I_mipsisa32, I_mipsisa32r2, I_mipsisa64, + I_mipsisa64r2, I_sb1, }; @@ -116,6 +117,7 @@ static const bfd_arch_info_type arch_info_struct[] = N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)), N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), + N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0), }; diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 0063100f8e..fa572958d4 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -4056,6 +4056,10 @@ _bfd_elf_mips_mach (flags) case E_MIPS_ARCH_32R2: return bfd_mach_mipsisa32r2; break; + + case E_MIPS_ARCH_64R2: + return bfd_mach_mipsisa64r2; + break; } } @@ -7192,6 +7196,10 @@ mips_set_isa_flags (abfd) case bfd_mach_mipsisa32r2: val = E_MIPS_ARCH_32R2; break; + + case bfd_mach_mipsisa64r2: + val = E_MIPS_ARCH_64R2; + break; } elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH); elf_elfheader (abfd)->e_flags |= val; @@ -8929,6 +8937,7 @@ struct mips_mach_extension { static const struct mips_mach_extension mips_mach_extensions[] = { /* MIPS64 extensions. */ + { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, { bfd_mach_mips_sb1, bfd_mach_mipsisa64 }, /* MIPS V extensions. */ @@ -9275,6 +9284,8 @@ _bfd_mips_elf_print_private_bfd_data (abfd, ptr) fprintf (file, _(" [mips64]")); else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2) fprintf (file, _(" [mips32r2]")); + else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R2) + fprintf (file, _(" [mips64r2]")); else fprintf (file, _(" [unknown ISA]")); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 160a75eb2f..47216be161 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2003-09-30 Chris Demetriou + + * mips.h (E_MIPS_ARCH_64R2): New define. + 2003-09-23 DJ Delorie * sh.h (R_SH_SWITCH8, R_SH_GNU_VTINHERIT, R_SH_GNU_VTENTRY, diff --git a/include/elf/mips.h b/include/elf/mips.h index 4b36ff763e..ce43158123 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -151,6 +151,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* -mips32r2 code. */ #define E_MIPS_ARCH_32R2 0x70000000 +/* -mips64r2 code. */ +#define E_MIPS_ARCH_64R2 0x80000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index aaea21428e..b248854a57 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,10 @@ +2003-09-30 Chris Demetriou + + * mips.h: Document +E, +F, +G, +H, and +I operand types. + Update documentation of I, +B and +C operand types. + (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. + (M_DEXT, M_DINS): New enum values. + 2003-09-04 Nick Clifton * v850.h (PROCESSOR_V850E1): Define. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 65434a7785..9dab620609 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -236,11 +236,24 @@ struct mips_opcode "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. Floating point instructions: "D" 5 bit destination register (OP_*_FD) @@ -265,7 +278,8 @@ struct mips_opcode Macro instructions: "A" General 32 bit expression - "I" 32 bit immediate + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). "F" 64 bit floating point constant in .rdata "L" 64 bit floating point constant in .lit8 "f" 32 bit floating point constant @@ -292,7 +306,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "ABCD" + "ABCDEFGHI" */ /* These are the bits which may be set in the pinfo field of an @@ -385,6 +399,7 @@ struct mips_opcode #define INSN_ISA32 0x00000020 #define INSN_ISA64 0x00000040 #define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 @@ -432,6 +447,8 @@ struct mips_opcode #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -460,6 +477,7 @@ struct mips_opcode #define CPU_MIPS32R2 33 #define CPU_MIPS5 5 #define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -542,6 +560,8 @@ enum M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, + M_DEXT, + M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1f0b2ab47e..e102fc6414 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2003-09-30 Chris Demetriou + + * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" + (print_insn_args): Add handing for +E, +F, +G, and +H. + * mips-opc.c (I65): New define for MIPS64r2. + (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", + "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", + and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to + be supported on MIPS64r2. + 2003-09-24 Dave Brolley * frv-desc.c, frv-opc.c, frv-opc.h: Regenerated. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index af6c445a56..43fcb3ca79 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -384,6 +384,12 @@ const struct mips_arch_choice mips_arch_choices[] = { mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, + { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, + ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_hwr_names_mips3264r2 }, + { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, mips_cp0_names_sb1, @@ -714,6 +720,7 @@ print_insn_args (d, l, pc, info) break; case 'C': + case 'H': msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); break; @@ -740,6 +747,21 @@ print_insn_args (d, l, pc, info) break; } + case 'E': + lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32; + (*info->fprintf_func) (info->stream, "0x%x", lsb); + break; + + case 'F': + msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); + break; + + case 'G': + msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32; + (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 228357a0c1..340a08468a 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -87,6 +87,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define I32 INSN_ISA32 #define I64 INSN_ISA64 #define I33 INSN_ISA32R2 +#define I65 INSN_ISA64R2 /* MIPS64 MIPS-3D ASE support. */ #define I16 INSN_MIPS16 @@ -481,6 +482,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 }, {"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 }, +{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 }, +{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 }, +{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 }, +{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 }, /* For ddiv, see the comments about div. */ {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 }, {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 }, @@ -491,6 +496,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 }, {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 }, {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 }, +{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 }, +{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 }, +{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 }, +{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 }, /* The MIPS assembler treats the div opcode with two operands as though the first operand appeared twice (the first operand is both a source and a destination). To get the div machine instruction, @@ -559,9 +568,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 }, {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 }, {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 }, -{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5 }, -{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5 }, -{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5 }, +{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 }, +{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I65 }, +{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5|I65 }, +{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 }, +{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 }, +{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 }, +{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 }, +{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, I65 }, +{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 }, +{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 }, +{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, I65 }, {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */ -- 2.11.0