From 149f29f1fdd3f806fcc2570173105d27d718bd1d Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Tue, 20 Sep 2011 22:34:45 +0000 Subject: [PATCH] Simplify max/minp[s|d] dagcombine matching git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140199 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c21b1dcc243..a2b5d046281 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -12562,17 +12562,14 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // Get the LHS/RHS of the select. SDValue LHS = N->getOperand(1); SDValue RHS = N->getOperand(2); + EVT VT = LHS.getValueType(); // If we have SSE[12] support, try to form min/max nodes. SSE min/max // instructions match the semantics of the common C idiom xhasXMMInt() && - (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::v4f32 || - LHS.getValueType() == MVT::f64 || LHS.getValueType() == MVT::v2f64)) || - (Subtarget->hasAVX() && - (LHS.getValueType() == MVT::v8f32 || LHS.getValueType() == MVT::v4f64)))) { + if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && + VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) { ISD::CondCode CC = cast(Cond.getOperand(2))->get(); unsigned Opcode = 0; -- 2.11.0