From 155b8645de9e0f07b654025fe91725ca2f67d12a Mon Sep 17 00:00:00 2001 From: Khaled Almahallawy Date: Fri, 26 Feb 2021 00:15:54 -0800 Subject: [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing Source needs to write DPCD 103-106 after receiving a PHY request to change swing/pre-emphasis after reading DPCD 206-207. This is especially needed if there is a retimer between source and sink and the retimer implements AUX_CH interception scheme to manage DP PHY settings (e.g. adjusting Swing/Pre-emphasis equalization level) for DP output channel. If the source doesn't write to DPCD 103-106, the retimer may not output the requested swing/pre-emphasis and eventually we fail compliance. v2: Rebase and use crtc->lane_count (Imre) Signed-off-by: Khaled Almahallawy Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20210226081554.984307-1-khaled.almahallawy@intel.com Reviewed-by: Imre Deak Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c386ef8eb200..a54e339947c6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3356,6 +3356,9 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp, intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); + drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, + intel_dp->train_set, crtc_state->lane_count); + drm_dp_set_phy_test_pattern(&intel_dp->aux, data, link_status[DP_DPCD_REV]); } -- 2.11.0