From 16082a39ea9fed8b360a8d342e0dc37cc46c1944 Mon Sep 17 00:00:00 2001 From: Ron Lieberman Date: Mon, 1 Aug 2016 19:36:39 +0000 Subject: [PATCH] [Hexagon] Generate vector printing instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277370 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/CMakeLists.txt | 1 + lib/Target/Hexagon/HexagonTargetMachine.cpp | 7 ++ lib/Target/Hexagon/HexagonVectorPrint.cpp | 180 ++++++++++++++++++++++++++++ test/CodeGen/Hexagon/v6vec-vprint.ll | 31 +++++ 4 files changed, 219 insertions(+) create mode 100644 lib/Target/Hexagon/HexagonVectorPrint.cpp create mode 100644 test/CodeGen/Hexagon/v6vec-vprint.ll diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index e39247e474f..6f20d7f873e 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -54,6 +54,7 @@ add_llvm_target(HexagonCodeGen HexagonTargetMachine.cpp HexagonTargetObjectFile.cpp HexagonTargetTransformInfo.cpp + HexagonVectorPrint.cpp HexagonVLIWPacketizer.cpp RDFCopy.cpp RDFDeadCode.cpp diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 17396942898..94fd52c38e5 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -86,6 +86,10 @@ static cl::opt EnableLoopResched("hexagon-loop-resched", cl::init(true), static cl::opt HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations")); +static cl::opt EnableVectorPrint("enable-hexagon-vector-print", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Enable Hexagon Vector print instr pass")); + /// HexagonTargetMachineModule - Note that this is used on hosts that /// cannot link in a library unless there are references into the /// library. In particular, it seems that it is not possible to get @@ -135,6 +139,7 @@ namespace llvm { FunctionPass *createHexagonSplitConst32AndConst64(); FunctionPass *createHexagonSplitDoubleRegs(); FunctionPass *createHexagonStoreWidening(); + FunctionPass *createHexagonVectorPrint(); } // end namespace llvm; static Reloc::Model getEffectiveRelocModel(Optional RM) { @@ -331,6 +336,8 @@ void HexagonPassConfig::addPreEmitPass() { addPass(createHexagonPacketizer(), false); } + if (EnableVectorPrint) + addPass(createHexagonVectorPrint(), false); // Add CFI instructions if necessary. addPass(createHexagonCallFrameInformation(), false); diff --git a/lib/Target/Hexagon/HexagonVectorPrint.cpp b/lib/Target/Hexagon/HexagonVectorPrint.cpp new file mode 100644 index 00000000000..785f581a670 --- /dev/null +++ b/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -0,0 +1,180 @@ +//===-- HexagonVectorPrint.cpp - Generate vector printing instructions -===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass adds the capability to generate pseudo vector/predicate register +// printing instructions. These pseudo instructions should be used with the +// simulator, NEVER on hardware. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "hexagon-vector-print" + +#include "HexagonTargetMachine.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" + +using namespace llvm; + +namespace llvm { + FunctionPass *createHexagonVectorPrint(); + void initializeHexagonVectorPrintPass(PassRegistry&); +} + + +namespace { + +class HexagonVectorPrint : public MachineFunctionPass { + const HexagonSubtarget *QST; + const HexagonInstrInfo *QII; + const HexagonRegisterInfo *QRI; + + public: + static char ID; + HexagonVectorPrint() : MachineFunctionPass(ID), + QST(0), QII(0), QRI(0) { + initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry()); + } + + const char *getPassName() const override { + return "Hexagon VectorPrint pass"; + } + bool runOnMachineFunction(MachineFunction &Fn) override; +}; + +char HexagonVectorPrint::ID = 0; + +static bool isVecReg(unsigned Reg) { + return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) + || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) + || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); +} + +std::string getStringReg(unsigned R) { + if (R >= Hexagon::V0 && R <= Hexagon::V31) { + static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27", + "28", "29", "2a", "2b", "2c", "2d", "2e", "2f", + "30", "31", "32", "33", "34", "35", "36", "37", + "38", "39", "3a", "3b", "3c", "3d", "3e", "3f"}; + return S[R-Hexagon::V0]; + } + if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { + static const char* S[] = { "00", "01", "02", "03"}; + return S[R-Hexagon::Q0]; + + } + llvm_unreachable("valid vreg"); +} + +static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, + MachineBasicBlock::instr_iterator I, + const DebugLoc &DL, const HexagonInstrInfo *QII, + MachineFunction &Fn) { + + std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); + const char *cstr = Fn.createExternalSymbolName(VDescStr.c_str()); + unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects; + BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM)) + .addExternalSymbol(cstr) + .addImm(ExtraInfo); +} + +static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { + if (MI.getNumOperands() < 1) return false; + // Vec load or compute. + if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) { + Reg = MI.getOperand(0).getReg(); + if (isVecReg(Reg)) + return true; + } + // Vec store. + if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) { + Reg = MI.getOperand(2).getReg(); + if (isVecReg(Reg)) + return true; + } + // Vec store post increment. + if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) { + Reg = MI.getOperand(3).getReg(); + if (isVecReg(Reg)) + return true; + } + return false; +} + +bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) { + bool Changed = false; + QST = &Fn.getSubtarget(); + QRI = QST->getRegisterInfo(); + QII = QST->getInstrInfo(); + std::vector VecPrintList; + for (auto &MBB : Fn) + for (auto &MI : MBB) { + if (MI.isBundle()) { + MachineBasicBlock::instr_iterator MII = MI.getIterator(); + for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) { + if (MII->getNumOperands() < 1) continue; + unsigned Reg = 0; + if (getInstrVecReg(*MII, Reg)) { + VecPrintList.push_back((&*MII)); + DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump()); + } + } + } else { + unsigned Reg = 0; + if (getInstrVecReg(MI, Reg)) { + VecPrintList.push_back(&MI); + DEBUG(dbgs() << "Found vector reg \n"; MI.dump()); + } + } + } + + Changed = VecPrintList.size() > 0; + if (!Changed) return Changed; + + for (auto *I : VecPrintList) { + DebugLoc DL = I->getDebugLoc(); + MachineBasicBlock *MBB = I->getParent(); + DEBUG(dbgs() << "Evaluating V MI\n"; I->dump()); + unsigned Reg = 0; + assert(getInstrVecReg(*I, Reg) && "Need a vector reg"); + MachineBasicBlock::instr_iterator MII = I->getIterator(); + if (I->isInsideBundle()) { + DEBUG(dbgs() << "add to end of bundle\n"; I->dump()); + while (MII->isInsideBundle()) ++MII; + } else { + DEBUG(dbgs() << "add after instruction\n"; I->dump()); + MII++; + } + if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { + DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n'); + addAsmInstr(MBB, Reg, MII, DL, QII, Fn); + } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { + DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n'); + addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, + MII, DL, QII, Fn); + addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, + MII, DL, QII, Fn); + } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { + DEBUG(dbgs() << "adding dump for Q" << Reg-Hexagon::Q0 << '\n'); + addAsmInstr(MBB, Reg, MII, DL, QII, Fn); + } else + llvm_unreachable("Bad Vector reg"); + } + return Changed; +} + +} +//===----------------------------------------------------------------------===// +// Public Constructor Functions +//===----------------------------------------------------------------------===// +INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print", + "Hexagon VectorPrint pass", false, false) + +FunctionPass *llvm::createHexagonVectorPrint() { + return new HexagonVectorPrint(); +} diff --git a/test/CodeGen/Hexagon/v6vec-vprint.ll b/test/CodeGen/Hexagon/v6vec-vprint.ll new file mode 100644 index 00000000000..9c9f3ffa3c9 --- /dev/null +++ b/test/CodeGen/Hexagon/v6vec-vprint.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; generate .long XXXX which is a vector debug print instruction. +; CHECK: .long 0x1dffe0 +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind +define void @do_vecs(i8* nocapture readonly %a, i8* nocapture readonly %b, i8* nocapture %c) #0 { +entry: + %0 = bitcast i8* %a to <16 x i32>* + %1 = load <16 x i32>, <16 x i32>* %0, align 4, !tbaa !1 + %2 = bitcast i8* %b to <16 x i32>* + %3 = load <16 x i32>, <16 x i32>* %2, align 4, !tbaa !1 + %4 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %1, <16 x i32> %3) + %5 = bitcast i8* %c to <16 x i32>* + store <16 x i32> %4, <16 x i32>* %5, align 4, !tbaa !1 + ret void +} + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.ident = !{!0} + +!0 = !{!"QuIC LLVM Hexagon Clang version 7.x-pre-unknown"} +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} -- 2.11.0