From 16c00e17ef73711364f993516ed5a93b15a449b7 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Mon, 11 Mar 2019 14:13:31 +0000 Subject: [PATCH] [MIPS][microMIPS] Add a pattern to match TruncIntFP A pattern needed to match TruncIntFP was missing. This was causing multiple tests from llvm test suite to fail during compilation for micromips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355825 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MicroMips32r6InstrInfo.td | 4 +- lib/Target/Mips/MicroMipsInstrFPU.td | 5 + test/CodeGen/Mips/llvm-ir/fptosi.ll | 418 ++++++++++++++++++++++++++++++ 3 files changed, 426 insertions(+), 1 deletion(-) create mode 100644 test/CodeGen/Mips/llvm-ir/fptosi.ll diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td index 190e0d2fc64..499a957e7d8 100644 --- a/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -1039,7 +1039,7 @@ class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd, class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>; class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, - AFGR64Opnd, II_TRUNC>; + FGR64Opnd, II_TRUNC>; class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>; class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, @@ -1749,6 +1749,8 @@ def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6; def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), + (TRUNC_W_S_MMR6 FGR32Opnd:$src)>, ISA_MICROMIPS32R6; def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), (ANDI16_MMR6 GPRMM16:$src, immZExtAndi16:$imm)>, diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index e1f25b137ca..c97dae9c595 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -424,6 +424,11 @@ def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), (TRUNC_W_MM AFGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; +def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), + (CVT_W_D64_MM FGR64Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6, + FGR_64; +def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), + (TRUNC_W_S_MM FGR32Opnd:$src)>, ISA_MICROMIPS32_NOT_MIPS32R6; // Selects defm : MovzPats0, diff --git a/test/CodeGen/Mips/llvm-ir/fptosi.ll b/test/CodeGen/Mips/llvm-ir/fptosi.ll new file mode 100644 index 00000000000..45517c1e6ba --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/fptosi.ll @@ -0,0 +1,418 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32R2-FP64 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32R2-SF +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32R3R5 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32R3R5 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M32R6 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M64 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M64 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M64 +; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=M64R6 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=MMR2-FP32 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=MMR2-FP64 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=MMR2-SF +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=MMR6 +; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\ +; RUN: FileCheck %s -check-prefixes=MMR6-SF + +; Test that fptosi can be matched for MIPS targets for various FPU +; configurations + +define i32 @test1(float %t) { +; M32-LABEL: test1: +; M32: # %bb.0: # %entry +; M32-NEXT: trunc.w.s $f0, $f12 # +; M32-NEXT: # > +; M32-NEXT: jr $ra # > +; M32-NEXT: mfc1 $2, $f0 # +; M32-NEXT: # > +; +; M32R2-FP64-LABEL: test1: +; M32R2-FP64: # %bb.0: # %entry +; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # +; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: jr $ra # > +; M32R2-FP64-NEXT: mfc1 $2, $f0 # +; M32R2-FP64-NEXT: # > +; +; M32R2-SF-LABEL: test1: +; M32R2-SF: # %bb.0: # %entry +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: .cfi_offset 31, -4 +; M32R2-SF-NEXT: jal __fixsfsi # > +; M32R2-SF-NEXT: nop # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: jr $ra # > +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; +; M32R3R5-LABEL: test1: +; M32R3R5: # %bb.0: # %entry +; M32R3R5-NEXT: trunc.w.s $f0, $f12 # +; M32R3R5-NEXT: # > +; M32R3R5-NEXT: jr $ra # > +; M32R3R5-NEXT: mfc1 $2, $f0 # +; M32R3R5-NEXT: # > +; +; M32R6-LABEL: test1: +; M32R6: # %bb.0: # %entry +; M32R6-NEXT: trunc.w.s $f0, $f12 # +; M32R6-NEXT: # > +; M32R6-NEXT: jr $ra # +; M32R6-NEXT: # > +; M32R6-NEXT: mfc1 $2, $f0 # +; M32R6-NEXT: # > +; +; M64-LABEL: test1: +; M64: # %bb.0: # %entry +; M64-NEXT: trunc.w.s $f0, $f12 # +; M64-NEXT: # > +; M64-NEXT: jr $ra # > +; M64-NEXT: mfc1 $2, $f0 # +; M64-NEXT: # > +; +; M64R6-LABEL: test1: +; M64R6: # %bb.0: # %entry +; M64R6-NEXT: trunc.w.s $f0, $f12 # +; M64R6-NEXT: # > +; M64R6-NEXT: jr $ra # +; M64R6-NEXT: # > +; M64R6-NEXT: mfc1 $2, $f0 # +; M64R6-NEXT: # > +; +; MMR2-FP32-LABEL: test1: +; MMR2-FP32: # %bb.0: # %entry +; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # +; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: jr $ra # > +; MMR2-FP32-NEXT: mfc1 $2, $f0 # +; MMR2-FP32-NEXT: # > +; +; MMR2-FP64-LABEL: test1: +; MMR2-FP64: # %bb.0: # %entry +; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # +; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: jr $ra # > +; MMR2-FP64-NEXT: mfc1 $2, $f0 # +; MMR2-FP64-NEXT: # > +; +; MMR2-SF-LABEL: test1: +; MMR2-SF: # %bb.0: # %entry +; MMR2-SF-NEXT: addiusp -24 # > +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: .cfi_offset 31, -4 +; MMR2-SF-NEXT: jal __fixsfsi # > +; MMR2-SF-NEXT: nop # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: addiusp 24 # > +; MMR2-SF-NEXT: jrc $ra # > +; +; MMR6-LABEL: test1: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: trunc.w.s $f0, $f12 # +; MMR6-NEXT: # > +; MMR6-NEXT: mfc1 $2, $f0 # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MMR6-SF-LABEL: test1: +; MMR6-SF: # %bb.0: # %entry +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: .cfi_offset 31, -4 +; MMR6-SF-NEXT: jalr __fixsfsi # > +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: jrc $ra # > +entry: + %conv = fptosi float %t to i32 + ret i32 %conv +} + +define i32 @test2(double %t) { +; M32-LABEL: test2: +; M32: # %bb.0: # %entry +; M32-NEXT: trunc.w.d $f0, $f12 # +; M32-NEXT: # > +; M32-NEXT: jr $ra # > +; M32-NEXT: mfc1 $2, $f0 # +; M32-NEXT: # > +; +; M32R2-FP64-LABEL: test2: +; M32R2-FP64: # %bb.0: # %entry +; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # +; M32R2-FP64-NEXT: # > +; M32R2-FP64-NEXT: jr $ra # > +; M32R2-FP64-NEXT: mfc1 $2, $f0 # +; M32R2-FP64-NEXT: # > +; +; M32R2-SF-LABEL: test2: +; M32R2-SF: # %bb.0: # %entry +; M32R2-SF-NEXT: addiu $sp, $sp, -24 # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: .cfi_def_cfa_offset 24 +; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: .cfi_offset 31, -4 +; M32R2-SF-NEXT: jal __fixdfsi # > +; M32R2-SF-NEXT: nop # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; M32R2-SF-NEXT: jr $ra # > +; M32R2-SF-NEXT: addiu $sp, $sp, 24 # +; M32R2-SF-NEXT: # +; M32R2-SF-NEXT: # > +; +; M32R3R5-LABEL: test2: +; M32R3R5: # %bb.0: # %entry +; M32R3R5-NEXT: trunc.w.d $f0, $f12 # +; M32R3R5-NEXT: # > +; M32R3R5-NEXT: jr $ra # > +; M32R3R5-NEXT: mfc1 $2, $f0 # +; M32R3R5-NEXT: # > +; +; M32R6-LABEL: test2: +; M32R6: # %bb.0: # %entry +; M32R6-NEXT: trunc.w.d $f0, $f12 # +; M32R6-NEXT: # > +; M32R6-NEXT: jr $ra # +; M32R6-NEXT: # > +; M32R6-NEXT: mfc1 $2, $f0 # +; M32R6-NEXT: # > +; +; M64-LABEL: test2: +; M64: # %bb.0: # %entry +; M64-NEXT: trunc.w.d $f0, $f12 # +; M64-NEXT: # > +; M64-NEXT: jr $ra # > +; M64-NEXT: mfc1 $2, $f0 # +; M64-NEXT: # > +; +; M64R6-LABEL: test2: +; M64R6: # %bb.0: # %entry +; M64R6-NEXT: trunc.w.d $f0, $f12 # +; M64R6-NEXT: # > +; M64R6-NEXT: jr $ra # +; M64R6-NEXT: # > +; M64R6-NEXT: mfc1 $2, $f0 # +; M64R6-NEXT: # > +; +; MMR2-FP32-LABEL: test2: +; MMR2-FP32: # %bb.0: # %entry +; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # +; MMR2-FP32-NEXT: # > +; MMR2-FP32-NEXT: jr $ra # > +; MMR2-FP32-NEXT: mfc1 $2, $f0 # +; MMR2-FP32-NEXT: # > +; +; MMR2-FP64-LABEL: test2: +; MMR2-FP64: # %bb.0: # %entry +; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # +; MMR2-FP64-NEXT: # > +; MMR2-FP64-NEXT: jr $ra # > +; MMR2-FP64-NEXT: mfc1 $2, $f0 # +; MMR2-FP64-NEXT: # > +; +; MMR2-SF-LABEL: test2: +; MMR2-SF: # %bb.0: # %entry +; MMR2-SF-NEXT: addiusp -24 # > +; MMR2-SF-NEXT: .cfi_def_cfa_offset 24 +; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: .cfi_offset 31, -4 +; MMR2-SF-NEXT: jal __fixdfsi # > +; MMR2-SF-NEXT: nop # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # +; MMR2-SF-NEXT: # > +; MMR2-SF-NEXT: addiusp 24 # > +; MMR2-SF-NEXT: jrc $ra # > +; +; MMR6-LABEL: test2: +; MMR6: # %bb.0: # %entry +; MMR6-NEXT: trunc.w.d $f0, $f12 # +; MMR6-NEXT: # > +; MMR6-NEXT: mfc1 $2, $f0 # +; MMR6-NEXT: # > +; MMR6-NEXT: jrc $ra # > +; +; MMR6-SF-LABEL: test2: +; MMR6-SF: # %bb.0: # %entry +; MMR6-SF-NEXT: addiu $sp, $sp, -24 # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: .cfi_def_cfa_offset 24 +; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: .cfi_offset 31, -4 +; MMR6-SF-NEXT: jalr __fixdfsi # > +; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: addiu $sp, $sp, 24 # +; MMR6-SF-NEXT: # +; MMR6-SF-NEXT: # > +; MMR6-SF-NEXT: jrc $ra # > +entry: + %conv = fptosi double %t to i32 + ret i32 %conv +} -- 2.11.0