From 17ab24c8db846e6cfa0958b96c67fd5180656569 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 20 Mar 2018 20:24:10 +0000 Subject: [PATCH] [TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328031 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/AMDGPUUsage.rst | 2 +- docs/CodeGenerator.rst | 6 +++ docs/CompilerWriterInfo.rst | 2 + docs/X86Usage.rst | 85 ++++++++++++++++++++++++++++++++++++++ docs/index.rst | 4 ++ utils/TableGen/CodeGenSchedule.cpp | 3 +- 6 files changed, 99 insertions(+), 3 deletions(-) create mode 100644 docs/X86Usage.rst diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index d0671b0a74e..6d70cfa9c45 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -1,4 +1,4 @@ -============================= +============================ User Guide for AMDGPU Backend ============================= diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index 7329f3d1fe6..a9e50707382 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -2656,3 +2656,9 @@ The AMDGPU backend The AMDGPU code generator lives in the ``lib/Target/AMDGPU`` directory. This code generator is capable of targeting a variety of AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information. + +The X86 backend +------------------ + +The X86 code generator lives in the ``lib/Target/X86`` +directory. Refer to :doc:`X86Usage` for more information. diff --git a/docs/CompilerWriterInfo.rst b/docs/CompilerWriterInfo.rst index 60f102472c6..9148ff0aa89 100644 --- a/docs/CompilerWriterInfo.rst +++ b/docs/CompilerWriterInfo.rst @@ -99,6 +99,8 @@ X86 * `X86 and X86-64 SysV psABI `_ * `Calling conventions for different C++ compilers and operating systems `_ +Refer to :doc:`X86Usage` for additional documentation. + XCore ----- diff --git a/docs/X86Usage.rst b/docs/X86Usage.rst new file mode 100644 index 00000000000..a8197d5e4ee --- /dev/null +++ b/docs/X86Usage.rst @@ -0,0 +1,85 @@ +============================= +User Guide for X86 Backend +============================= + +.. contents:: + :local: + +Introduction +============ + +The X86 backend provides ISA code generation for X86 CPUs. It lives in the +``lib/Target/X86`` directory. + +LLVM +==== + +.. _x86-processors + +Processors +---------- + +Use the ``clang -march=`` option to specify the X86 processor. + + .. table:: X86 processors + :name: x86-processor-table + + ================== =================== + Processor Alternative + Name + ``i386`` + ``i486`` + ``i586`` + ``pentium`` + ``pentium-mmx`` + ``i686`` + ``pentiumpro`` + ``pentium2`` + ``pentium3`` - ``pentium3m`` + ``pentium-m`` + ``pentium4`` - ``pentium4m`` + ``lakemont`` + ``yonah`` + ``prescott`` + ``nocona`` + ``core2`` + ``penryn`` + ``bonnell`` - ``atom`` + ``silvermont`` - ``slm`` + ``goldmont`` + ``nehalem`` - ``corei7`` + ``westmere`` + ``sandybridge`` - ``corei7-avx`` + ``ivybridge`` - ``core-avx-i`` + ``haswell`` - ``core-avx2`` + ``broadwell`` - ``skylake`` + ``knl`` + ``knm`` + ``skylake-avx512`` - ``skx`` + ``cannonlake`` + ``icelake`` + ``k6`` + ``k6-2`` + ``k6-3`` + ``athlon`` - ``athlon-tbird`` + ``athlon-4`` - ``athlon-xp`` + - ``athlon-mp`` + ``k8`` - ``opteron`` + - ``athlon64`` + - ``athlon-fx`` + ``k8-sse3`` - ``opteron-sse3`` + - ``athlon64-sse3`` + ``amdfam10h`` - ``barcelona`` + ``btver1`` + ``btver2`` + ``bdver1`` + ``bdver2`` + ``bdver3`` + ``bdver4`` + ``znver1`` + ``geode`` + ``winchip-c6`` + ``winchip2`` + ``c3`` + ``c3-2`` + ================== =================== diff --git a/docs/index.rst b/docs/index.rst index 2173f94459d..84c7ccb1021 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -276,6 +276,7 @@ For API clients and LLVM developers. HowToUseAttributes NVPTXUsage AMDGPUUsage + X86Usage StackMaps InAlloca BigEndianNEON @@ -380,6 +381,9 @@ For API clients and LLVM developers. :doc:`AMDGPUUsage` This document describes using the AMDGPU backend to compile GPU kernels. +:doc:`X86Usage` + This document describes using the X86 backend. + :doc:`StackMaps` LLVM support for mapping instruction addresses to the location of values and allowing code to be patched. diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp index c4ec4933cb8..71d957beaa1 100644 --- a/utils/TableGen/CodeGenSchedule.cpp +++ b/utils/TableGen/CodeGenSchedule.cpp @@ -1398,8 +1398,7 @@ static void inferFromTransitions(ArrayRef LastTransitions, PI = I->PredTerm.begin(), PE = I->PredTerm.end(); PI != PE; ++PI) { Preds.push_back(PI->Predicate); } - RecIter PredsEnd = std::unique(Preds.begin(), Preds.end()); - Preds.resize(PredsEnd - Preds.begin()); + Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end()); SCTrans.PredTerm = Preds; SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans); } -- 2.11.0