From 186d0503559482757cf454d617d9305fcadad614 Mon Sep 17 00:00:00 2001
From: fche <fche>
Date: Tue, 4 Dec 2001 20:16:07 +0000
Subject: [PATCH] 2001-12-04  Frank Ch. Eigler  <fche@redhat.com>

        * cache.cxx (cache_sizes): Add "4" for "4kb".
        * hw-cache.xml, hw-cache.txt: Modified accordingly.
---
 sid/component/cache/ChangeLog    | 5 +++++
 sid/component/cache/cache.cxx    | 2 +-
 sid/component/cache/hw-cache.txt | 2 +-
 sid/component/cache/hw-cache.xml | 2 +-
 4 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/sid/component/cache/ChangeLog b/sid/component/cache/ChangeLog
index c538c45b0e..aa45814054 100644
--- a/sid/component/cache/ChangeLog
+++ b/sid/component/cache/ChangeLog
@@ -1,3 +1,8 @@
+2001-12-04  Frank Ch. Eigler  <fche@redhat.com>
+ 
+ 	* cache.cxx (cache_sizes): Add "4" for "4kb".
+ 	* hw-cache.xml, hw-cache.txt: Modified accordingly.
+
 2001-11-30  Frank Ch. Eigler  <fche@redhat.com>
 
 	* cacheutil.cxx (hash_fn): Fix std:: namespace reference.
diff --git a/sid/component/cache/cache.cxx b/sid/component/cache/cache.cxx
index fdc45b7b15..c6ad4b907e 100644
--- a/sid/component/cache/cache.cxx
+++ b/sid/component/cache/cache.cxx
@@ -30,7 +30,7 @@ string line_sizes[] =
   { "16", "32", "64", "128" };
 
 string cache_sizes[] =
-  { "8", "16", "32", "64", "128", "256", "512" };
+  { "4", "8", "16", "32", "64", "128", "256", "512" };
 
 string assocs[] =
   { "direct", "full", "2way", "4way" };
diff --git a/sid/component/cache/hw-cache.txt b/sid/component/cache/hw-cache.txt
index c54dd00827..6a2be3d0fa 100644
--- a/sid/component/cache/hw-cache.txt
+++ b/sid/component/cache/hw-cache.txt
@@ -18,7 +18,7 @@ Functionality:
 
    The parameters of the cache are a matter of configuration. At
    instantiation time, the following parameters are specified:
-     * cache size in KB (8, 16, 32, 64, 128, 256, 512)
+     * cache size in KB (4, 8, 16, 32, 64, 128, 256, 512)
      * line size in bytes (16, 32, 64, 128)
      * associativity (direct, full, 2way, 4way)
      * replacement policy for N-way and fully associative caches (lru, fifo,
diff --git a/sid/component/cache/hw-cache.xml b/sid/component/cache/hw-cache.xml
index d4c5fa6ac7..7b1da6e869 100644
--- a/sid/component/cache/hw-cache.xml
+++ b/sid/component/cache/hw-cache.xml
@@ -64,7 +64,7 @@
 	instantiation time, the following parameters are specified:
 
 	<ul>
-	  <li>cache size in KB (8, 16, 32, 64, 128, 256, 512)</li>
+	  <li>cache size in KB (4, 8, 16, 32, 64, 128, 256, 512)</li>
 	  <li>line size in bytes (16, 32, 64, 128)</li>
 	  <li>associativity (<tt>direct</tt>, <tt>full</tt>,
 	    <tt>2way</tt>, <tt>4way</tt>)</li>
-- 
2.11.0