From 1a00645fefdc795fa1da1547e8deef0eec528500 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Fri, 9 Mar 2012 08:35:32 +0800 Subject: [PATCH] Setup pipeline to create MFC batchbuffer on Sandybridge Also clean up the source Signed-off-by: Xiang, Haihao --- src/Makefile.am | 1 - src/gen6_mfc.c | 1243 ++++++++++++++++++++++++++++++++------------- src/gen6_mfc.h | 100 +++- src/gen7_mfc.c | 1516 +------------------------------------------------------ src/gen7_mfc.h | 149 ------ 5 files changed, 991 insertions(+), 2018 deletions(-) delete mode 100644 src/gen7_mfc.h diff --git a/src/Makefile.am b/src/Makefile.am index 1d3caef..bb0b033 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -76,7 +76,6 @@ source_h = \ gen6_mfc.h \ gen6_mfd.h \ gen6_vme.h \ - gen7_mfc.h \ gen7_mfd.h \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c index 3177535..e1a1a46 100644 --- a/src/gen6_mfc.c +++ b/src/gen6_mfc.c @@ -40,11 +40,41 @@ #include "gen6_mfc.h" #include "gen6_vme.h" +static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = { +#include "shaders/utils/mfc_batchbuffer_avc_intra.g6b" +}; + +static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = { +#include "shaders/utils/mfc_batchbuffer_avc_inter.g6b" +}; + +static struct i965_kernel gen6_mfc_kernels[] = { + { + "MFC AVC INTRA BATCHBUFFER ", + MFC_BATCHBUFFER_AVC_INTRA, + gen6_mfc_batchbuffer_avc_intra, + sizeof(gen6_mfc_batchbuffer_avc_intra), + NULL + }, + + { + "MFC AVC INTER BATCHBUFFER ", + MFC_BATCHBUFFER_AVC_INTER, + gen6_mfc_batchbuffer_avc_inter, + sizeof(gen6_mfc_batchbuffer_avc_inter), + NULL + }, +}; + static void -gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context) +gen6_mfc_pipe_mode_select(VADriverContextP ctx, + int standard_select, + struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; + assert(standard_select == MFX_FORMAT_AVC); + BEGIN_BCS_BATCH(batch, 4); OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2)); @@ -259,7 +289,8 @@ gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state, ADVANCE_BCS_BATCH(batch); } -static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) +static void +gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; @@ -291,14 +322,15 @@ static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_enc ADVANCE_BCS_BATCH(batch); } -static void gen6_mfc_avc_slice_state(VADriverContextP ctx, - VAEncSliceParameterBufferH264 *slice_param, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int rate_control_enable, - int qp) +static void +gen6_mfc_avc_slice_state(VADriverContextP ctx, + VAEncSliceParameterBufferH264 *slice_param, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int rate_control_enable, + int qp, + struct intel_batchbuffer *batch) { - struct intel_batchbuffer *batch = encoder_context->base.batch; struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; @@ -308,71 +340,75 @@ static void gen6_mfc_avc_slice_state(VADriverContextP ctx, int beginy = beginmb / width_in_mbs; int nextx = endmb % width_in_mbs; int nexty = endmb / width_in_mbs; - int last_slice = (endmb == (width_in_mbs * height_in_mbs)); - int bit_rate_control_target; int slice_type = slice_param->slice_type; + int last_slice = (endmb == (width_in_mbs * height_in_mbs)); + int bit_rate_control_target, maxQpN, maxQpP; + unsigned char correct[6], grow, shrink; + int i; + + if (batch == NULL) + batch = encoder_context->base.batch; if (slice_type == SLICE_TYPE_I) bit_rate_control_target = 0; else bit_rate_control_target = 1; - int maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier; - int maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier; - unsigned char correct[6]; - int i; + + maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier; + maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier; for (i = 0; i < 6; i++) correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i]; - unsigned char grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit + + + grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit + (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4); - unsigned char shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit + + shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit + (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4); BEGIN_BCS_BATCH(batch, 11);; OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); - OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/ - if ( slice_type == SLICE_TYPE_I ) { + if (slice_type == SLICE_TYPE_I) { OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/ } else { OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/ } OUT_BCS_BATCH(batch, - (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/ - (0<<24) | /*Enable deblocking operation*/ - (qp<<16) | /*Slice Quantization Parameter*/ - 0x0202 ); + (slice_param->direct_spatial_mv_pred_flag << 29) | /*Direct Prediction Type*/ + (0 << 24) | /*Enable deblocking operation*/ + (qp << 16) | /*Slice Quantization Parameter*/ + (0x0202 << 0)); OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/ - (beginx << 16) | - slice_param->starting_macroblock_address ); + (beginx << 16) | + slice_param->starting_macroblock_address ); OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/ OUT_BCS_BATCH(batch, - (rate_control_enable<<31) | /*in CBR mode RateControlCounterEnable = enable*/ - (1<<30) | /*ResetRateControlCounter*/ - (0<<28) | /*RC Triggle Mode = Always Rate Control*/ - (4<<24) | /*RC Stable Tolerance, middle level*/ - (rate_control_enable<<23) | /*RC Panic Enable*/ - (0<<22) | /*QP mode, don't modfiy CBP*/ - (0<<21) | /*MB Type Direct Conversion Enabled*/ - (0<<20) | /*MB Type Skip Conversion Enabled*/ + (rate_control_enable << 31) | /*in CBR mode RateControlCounterEnable = enable*/ + (1 << 30) | /*ResetRateControlCounter*/ + (0 << 28) | /*RC Triggle Mode = Always Rate Control*/ + (4 << 24) | /*RC Stable Tolerance, middle level*/ + (rate_control_enable << 23) | /*RC Panic Enable*/ + (0 << 22) | /*QP mode, don't modfiy CBP*/ + (0 << 21) | /*MB Type Direct Conversion Enabled*/ + (0 << 20) | /*MB Type Skip Conversion Enabled*/ (last_slice << 19) | /*IsLastSlice*/ - (0<<18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ - (1<<17) | /*HeaderPresentFlag*/ - (1<<16) | /*SliceData PresentFlag*/ - (1<<15) | /*TailPresentFlag*/ - (1<<13) | /*RBSP NAL TYPE*/ - (0<<12) ); /*CabacZeroWordInsertionEnable*/ - + (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ + (1 << 17) | /*HeaderPresentFlag*/ + (1 << 16) | /*SliceData PresentFlag*/ + (1 << 15) | /*TailPresentFlag*/ + (1 << 13) | /*RBSP NAL TYPE*/ + (0 << 12) ); /*CabacZeroWordInsertionEnable*/ OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); - - OUT_BCS_BATCH(batch, (maxQpN<<24) | /*Target QP - 24 is lowest QP*/ - (maxQpP<<16) | /*Target QP + 20 is highest QP*/ - (shrink<<8) | - (grow<<0)); - OUT_BCS_BATCH(batch, (correct[5] << 20) | + OUT_BCS_BATCH(batch, + (maxQpN << 24) | /*Target QP - 24 is lowest QP*/ + (maxQpP << 16) | /*Target QP + 20 is highest QP*/ + (shrink << 8) | + (grow << 0)); + OUT_BCS_BATCH(batch, + (correct[5] << 20) | (correct[4] << 16) | (correct[3] << 12) | (correct[2] << 8) | @@ -382,6 +418,7 @@ static void gen6_mfc_avc_slice_state(VADriverContextP ctx, ADVANCE_BCS_BATCH(batch); } + static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; @@ -413,7 +450,8 @@ static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_co ADVANCE_BCS_BATCH(batch); } -static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) +static void +gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; int i; @@ -440,17 +478,15 @@ static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encode static void gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, - int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag) + int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, + struct intel_batchbuffer *batch) { - struct i965_driver_data *i965 = i965_driver_data(ctx); - struct intel_batchbuffer *batch = encoder_context->base.batch; + if (batch == NULL) + batch = encoder_context->base.batch; BEGIN_BCS_BATCH(batch, lenght_in_dws + 2); - if (IS_GEN7(i965->intel.device_id)) - OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); - else - OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); + OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2)); OUT_BCS_BATCH(batch, (0 << 16) | /* always start at offset 0 */ @@ -465,103 +501,6 @@ gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *e ADVANCE_BCS_BATCH(batch); } -static int -gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size, unsigned char max_mb_size) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - int len_in_dwords = 11; - - BEGIN_BCS_BATCH(batch, len_in_dwords); - - OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, - (0 << 24) | /* PackedMvNum, Debug*/ - (0 << 20) | /* No motion vector */ - (1 << 19) | /* CbpDcY */ - (1 << 18) | /* CbpDcU */ - (1 << 17) | /* CbpDcV */ - (msg[0] & 0xFFFF) ); - - OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ - OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ - OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ - - /*Stuff for Intra MB*/ - OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ - OUT_BCS_BATCH(batch, msg[2]); - OUT_BCS_BATCH(batch, msg[3]&0xFC); - - /*MaxSizeInWord and TargetSzieInWord*/ - OUT_BCS_BATCH(batch, (max_mb_size << 24) | - (target_mb_size << 16) ); - - ADVANCE_BCS_BATCH(batch); - - return len_in_dwords; -} - -static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size,unsigned char max_mb_size, int slice_type) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - int len_in_dwords = 11; - - BEGIN_BCS_BATCH(batch, len_in_dwords); - - OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); - - OUT_BCS_BATCH(batch, 32); /* 32 MV*/ - OUT_BCS_BATCH(batch, offset); - - OUT_BCS_BATCH(batch, - (1 << 24) | /* PackedMvNum, Debug*/ - (4 << 20) | /* 8 MV, SNB don't use it*/ - (1 << 19) | /* CbpDcY */ - (1 << 18) | /* CbpDcU */ - (1 << 17) | /* CbpDcV */ - (0 << 15) | /* Transform8x8Flag = 0*/ - (0 << 14) | /* Frame based*/ - (0 << 13) | /* Inter MB */ - (1 << 8) | /* MbType = P_L0_16x16 */ - (0 << 7) | /* MBZ for frame */ - (0 << 6) | /* MBZ */ - (2 << 4) | /* MBZ for inter*/ - (0 << 3) | /* MBZ */ - (0 << 2) | /* SkipMbFlag */ - (0 << 0)); /* InterMbMode */ - - OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ - OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ -#if 0 - if ( slice_type == SLICE_TYPE_B) { - OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ - } else { - OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ - } -#else - OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ -#endif - - - /*Stuff for Inter MB*/ - OUT_BCS_BATCH(batch, 0x0); - OUT_BCS_BATCH(batch, 0x0); - OUT_BCS_BATCH(batch, 0x0); - - /*MaxSizeInWord and TargetSzieInWord*/ - OUT_BCS_BATCH(batch, (max_mb_size << 24) | - (target_mb_size << 16) ); - - ADVANCE_BCS_BATCH(batch); - - return len_in_dwords; -} - static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct i965_driver_data *i965 = i965_driver_data(ctx); @@ -625,12 +564,32 @@ static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *en 0x1000); assert(bo); mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; + + dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); + mfc_context->mfc_batchbuffer_surface.bo = NULL; + + dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); + mfc_context->aux_batchbuffer_surface.bo = NULL; + + if (mfc_context->aux_batchbuffer) + intel_batchbuffer_free(mfc_context->aux_batchbuffer); + + mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD); + mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer; + dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); + mfc_context->aux_batchbuffer_surface.pitch = 16; + mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16; + mfc_context->aux_batchbuffer_surface.size_block = 16; + + i965_gpe_context_init(ctx, &mfc_context->gpe_context); } static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + struct intel_batchbuffer *slice_batch) { + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; static int count = 0; VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; int rate_control_mode = pSequenceParameter->rate_control_method; @@ -644,15 +603,16 @@ static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx, param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderSPS]->buffer; length_in_bits = param->length_in_bits[0]; - gen6_mfc_avc_insert_object(ctx, - encoder_context, - header_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - param->skip_emulation_check_count, - 0, - 0, - param->insert_emulation_bytes); + mfc_context->insert_object(ctx, + encoder_context, + header_data, + ALIGN(length_in_bits, 32) >> 5, + length_in_bits & 0x1f, + param->skip_emulation_check_count, + 0, + 0, + param->insert_emulation_bytes, + slice_batch); } if (encode_state->packed_header_data[VAEncPackedHeaderPPS]) { @@ -664,15 +624,16 @@ static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx, param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderPPS]->buffer; length_in_bits = param->length_in_bits[0]; - gen6_mfc_avc_insert_object(ctx, - encoder_context, - header_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - param->skip_emulation_check_count, - 0, - 0, - param->insert_emulation_bytes); + mfc_context->insert_object(ctx, + encoder_context, + header_data, + ALIGN(length_in_bits, 32) >> 5, + length_in_bits & 0x1f, + param->skip_emulation_check_count, + 0, + 0, + param->insert_emulation_bytes, + slice_batch); } if ( (rate_control_mode == 0) && encode_state->packed_header_data[VAEncPackedHeaderSPS]) { // this is frist AU @@ -681,15 +642,16 @@ static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx, unsigned char *sei_data = NULL; int length_in_bits = build_avc_sei_buffering_period(mfc_context->vui_hrd.i_initial_cpb_removal_delay_length, mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, &sei_data); - gen6_mfc_avc_insert_object(ctx, - encoder_context, - (unsigned int *)sei_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - 4, - 0, - 0, - 1); + mfc_context->insert_object(ctx, + encoder_context, + (unsigned int *)sei_data, + ALIGN(length_in_bits, 32) >> 5, + length_in_bits & 0x1f, + 4, + 0, + 0, + 1, + slice_batch); free(sei_data); } @@ -701,15 +663,16 @@ static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx, mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number, mfc_context->vui_hrd.i_dpb_output_delay_length, 0, &sei_data); - gen6_mfc_avc_insert_object(ctx, - encoder_context, - (unsigned int *)sei_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - 4, - 0, - 0, - 1); + mfc_context->insert_object(ctx, + encoder_context, + (unsigned int *)sei_data, + ALIGN(length_in_bits, 32) >> 5, + length_in_bits & 0x1f, + 4, + 0, + 0, + 1, + slice_batch); free(sei_data); } @@ -720,127 +683,21 @@ static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { - gen6_mfc_pipe_mode_select(ctx, encoder_context); - gen6_mfc_surface_state(ctx, encoder_context); - gen6_mfc_ind_obj_base_addr_state(ctx, encoder_context); + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + + mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context); + mfc_context->set_surface_state(ctx, encoder_context); + mfc_context->ind_obj_base_addr_state(ctx, encoder_context); gen6_mfc_pipe_buf_addr_state(ctx, encoder_context); gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context); - gen6_mfc_avc_img_state(ctx, encode_state, encoder_context); - gen6_mfc_avc_qm_state(ctx, encoder_context); - gen6_mfc_avc_fqm_state(ctx, encoder_context); + mfc_context->avc_img_state(ctx, encode_state, encoder_context); + mfc_context->avc_qm_state(ctx, encoder_context); + mfc_context->avc_fqm_state(ctx, encoder_context); gen6_mfc_avc_directmode_state(ctx, encoder_context); gen6_mfc_avc_ref_idx_state(ctx, encoder_context); } static void -gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index) -{ - struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; - struct gen6_vme_context *vme_context = encoder_context->vme_context; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; - VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; - VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL; - unsigned int *msg = NULL, offset = 0; - int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs); - int i,x,y; - int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; - int rate_control_mode = pSequenceParameter->rate_control_method; - unsigned char *slice_header = NULL; - int slice_header_length_in_bits = 0; - unsigned int tail_data[] = { 0x0, 0x0 }; - - gen6_mfc_avc_slice_state(ctx, pSliceParameter, - encode_state, encoder_context, - (rate_control_mode == 0), qp); - - if ( slice_index == 0) - gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context); - - if (encode_state->dec_ref_pic_marking) - pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer; - slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header); - - // slice hander - gen6_mfc_avc_insert_object(ctx, encoder_context, - (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, - 5, /* first 5 bytes are start code + nal unit type */ - 1, 0, 1); - - if ( rate_control_mode == 0) { - qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY; - } - - if (is_intra) { - dri_bo_map(vme_context->vme_output.bo , 1); - msg = (unsigned int *)vme_context->vme_output.bo->virtual; - } - - for (i = pSliceParameter->starting_macroblock_address; - i < pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs; i++) { - int last_mb = (i == (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs - 1) ); - x = i % width_in_mbs; - y = i / width_in_mbs; - - if (is_intra) { - assert(msg); - gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0); - msg += 4; - } else { - gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, 0, 0, pSliceParameter->slice_type); - offset += 64; - } - } - - if (is_intra) - dri_bo_unmap(vme_context->vme_output.bo); - if ( last_slice ) { - gen6_mfc_avc_insert_object(ctx, encoder_context, - tail_data, 2, 8, - 2, 1, 1, 0); - } else { - gen6_mfc_avc_insert_object(ctx, encoder_context, - tail_data, 1, 8, - 1, 1, 1, 0); - } - - free(slice_header); - -} - -static void -gen6_mfc_avc_pipeline_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - int i; - - // begin programing - intel_batchbuffer_start_atomic_bcs(batch, 0x4000); - intel_batchbuffer_emit_mi_flush(batch); - - // picture level programing - gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); - - for ( i = 0; i < encode_state->num_slice_params_ext; i++) { - // slice level programing - gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i); - } - - // end programing - intel_batchbuffer_end_atomic(batch); - - return; -} - -static void gen6_mfc_free_avc_surface(void **data) { struct gen6_mfc_avc_surface_aux *avc_surface = *data; @@ -857,8 +714,9 @@ gen6_mfc_free_avc_surface(void **data) *data = NULL; } -static void gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context) +static void +gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state, + struct gen6_mfc_context *mfc_context) { VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; @@ -900,7 +758,7 @@ static void gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_s static int gen6_mfc_bit_rate_control_context_update(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context, - int current_frame_size) + int current_frame_size) { VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I); @@ -962,13 +820,6 @@ gen6_mfc_hrd_context_init(struct encode_state *encode_state, } -static VAStatus -gen6_mfc_hrd_context_check(struct encode_state *encode_state, - struct gen6_mfc_context *mfc_context) -{ - return VA_STATUS_SUCCESS; -} - static void gen6_mfc_hrd_context_update(struct encode_state *encode_state, struct gen6_mfc_context *mfc_context) @@ -1091,9 +942,6 @@ static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx, if ( (rate_control_mode == 0) && (mfc_context->vui_hrd.i_cpb_size_value == 0) ) gen6_mfc_hrd_context_init(encode_state, mfc_context); - /*Programing bcs pipeline*/ - gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline - return vaStatus; } @@ -1108,10 +956,11 @@ static VAStatus gen6_mfc_run(VADriverContextP ctx, return VA_STATUS_SUCCESS; } -static VAStatus gen6_mfc_stop(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int *encoded_bits_size) +static VAStatus +gen6_mfc_stop(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int *encoded_bits_size) { struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; unsigned int *status_mem; @@ -1135,38 +984,692 @@ static VAStatus gen6_mfc_stop(VADriverContextP ctx, return VA_STATUS_SUCCESS; } -static VAStatus -gen6_mfc_avc_encode_picture(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) +#if __SOFTWARE__ + +static int +gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, + struct intel_encoder_context *encoder_context, + unsigned char target_mb_size, unsigned char max_mb_size, + struct intel_batchbuffer *batch) { - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; - int rate_control_mode = pSequenceParameter->rate_control_method; - int MAX_CBR_INTERATE = 4; - int current_frame_bits_size; - int i; - - for(i = 0; i < MAX_CBR_INTERATE; i++) { - gen6_mfc_init(ctx, encoder_context); - gen6_mfc_avc_prepare(ctx, encode_state, encoder_context); - gen6_mfc_run(ctx, encode_state, encoder_context); - gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); - if ( rate_control_mode == 0) { - //gen6_mfc_hrd_context_check(encode_state, mfc_context); - if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) { - gen6_mfc_hrd_context_update(encode_state, mfc_context); - break; - } - } else { - break; - } - } + int len_in_dwords = 11; - return VA_STATUS_SUCCESS; + if (batch == NULL) + batch = encoder_context->base.batch; + + BEGIN_BCS_BATCH(batch, len_in_dwords); + + OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, + (0 << 24) | /* PackedMvNum, Debug*/ + (0 << 20) | /* No motion vector */ + (1 << 19) | /* CbpDcY */ + (1 << 18) | /* CbpDcU */ + (1 << 17) | /* CbpDcV */ + (msg[0] & 0xFFFF) ); + + OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/ + OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ + OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ + + /*Stuff for Intra MB*/ + OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ + OUT_BCS_BATCH(batch, msg[2]); + OUT_BCS_BATCH(batch, msg[3]&0xFC); + + /*MaxSizeInWord and TargetSzieInWord*/ + OUT_BCS_BATCH(batch, (max_mb_size << 24) | + (target_mb_size << 16) ); + + ADVANCE_BCS_BATCH(batch); + + return len_in_dwords; +} + +static int +gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset, + struct intel_encoder_context *encoder_context, + unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, + struct intel_batchbuffer *batch) +{ + int len_in_dwords = 11; + + if (batch == NULL) + batch = encoder_context->base.batch; + + BEGIN_BCS_BATCH(batch, len_in_dwords); + + OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); + + OUT_BCS_BATCH(batch, 32); /* 32 MV*/ + OUT_BCS_BATCH(batch, offset); + + OUT_BCS_BATCH(batch, + (1 << 24) | /* PackedMvNum, Debug*/ + (4 << 20) | /* 8 MV, SNB don't use it*/ + (1 << 19) | /* CbpDcY */ + (1 << 18) | /* CbpDcU */ + (1 << 17) | /* CbpDcV */ + (0 << 15) | /* Transform8x8Flag = 0*/ + (0 << 14) | /* Frame based*/ + (0 << 13) | /* Inter MB */ + (1 << 8) | /* MbType = P_L0_16x16 */ + (0 << 7) | /* MBZ for frame */ + (0 << 6) | /* MBZ */ + (2 << 4) | /* MBZ for inter*/ + (0 << 3) | /* MBZ */ + (0 << 2) | /* SkipMbFlag */ + (0 << 0)); /* InterMbMode */ + + OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ + OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ +#if 0 + if ( slice_type == SLICE_TYPE_B) { + OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ + } else { + OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ + } +#else + OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ +#endif + + + /*Stuff for Inter MB*/ + OUT_BCS_BATCH(batch, 0x0); + OUT_BCS_BATCH(batch, 0x0); + OUT_BCS_BATCH(batch, 0x0); + + /*MaxSizeInWord and TargetSzieInWord*/ + OUT_BCS_BATCH(batch, (max_mb_size << 24) | + (target_mb_size << 16) ); + + ADVANCE_BCS_BATCH(batch); + + return len_in_dwords; +} + +static void +gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int slice_index, + struct intel_batchbuffer *slice_batch) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + struct gen6_vme_context *vme_context = encoder_context->vme_context; + VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; + VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; + VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; + VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL; + unsigned int *msg = NULL, offset = 0; + int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; + int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; + int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; + int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs); + int i,x,y; + int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; + int rate_control_mode = pSequenceParameter->rate_control_method; + unsigned char *slice_header = NULL; + int slice_header_length_in_bits = 0; + unsigned int tail_data[] = { 0x0, 0x0 }; + + gen6_mfc_avc_slice_state(ctx, pSliceParameter, + encode_state, encoder_context, + (rate_control_mode == 0), qp, slice_batch); + + if ( slice_index == 0) + gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); + + if (encode_state->dec_ref_pic_marking) + pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer; + slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header); + + // slice hander + mfc_context->insert_object(ctx, encoder_context, + (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, + 5, /* first 5 bytes are start code + nal unit type */ + 1, 0, 1, slice_batch); + + if ( rate_control_mode == 0) { + qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY; + } + + if (is_intra) { + dri_bo_map(vme_context->vme_output.bo , 1); + msg = (unsigned int *)vme_context->vme_output.bo->virtual; + } + + for (i = pSliceParameter->starting_macroblock_address; + i < pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs; i++) { + int last_mb = (i == (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs - 1) ); + x = i % width_in_mbs; + y = i / width_in_mbs; + + if (is_intra) { + assert(msg); + gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); + msg += 4; + } else { + gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch); + offset += 64; + } + } + + if (is_intra) + dri_bo_unmap(vme_context->vme_output.bo); + if ( last_slice ) { + mfc_context->insert_object(ctx, encoder_context, + tail_data, 2, 8, + 2, 1, 1, 0, slice_batch); + } else { + mfc_context->insert_object(ctx, encoder_context, + tail_data, 1, 8, + 1, 1, 1, 0, slice_batch); + } + + free(slice_header); + +} + +static dri_bo * +gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD); + dri_bo *batch_bo = batch->buffer; + int i, used; + + for (i = 0; i < encode_state->num_slice_params_ext; i++) { + gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch); + } + + used = intel_batchbuffer_used_size(batch); + + if ((used & 4) == 0) { + BEGIN_BCS_BATCH(batch, 2); + OUT_BCS_BATCH(batch, 0); + OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); + } + + dri_bo_reference(batch_bo); + intel_batchbuffer_free(batch); + + return batch_bo; +} + +#else + +static void +gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) + +{ + struct gen6_vme_context *vme_context = encoder_context->vme_context; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + + assert(vme_context->vme_output.bo); + mfc_context->buffer_suface_setup(ctx, + &mfc_context->gpe_context, + &vme_context->vme_output, + BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT), + SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT)); + assert(mfc_context->aux_batchbuffer_surface.bo); + mfc_context->buffer_suface_setup(ctx, + &mfc_context->gpe_context, + &mfc_context->aux_batchbuffer_surface, + BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER), + SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER)); +} + +static void +gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) + +{ + struct i965_driver_data *i965 = i965_driver_data(ctx); + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; + int width_in_mbs = pSequenceParameter->picture_width_in_mbs; + int height_in_mbs = pSequenceParameter->picture_height_in_mbs; + mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 2 + 1; + mfc_context->mfc_batchbuffer_surface.size_block = 48; /* 3 OWORDs */ + mfc_context->mfc_batchbuffer_surface.pitch = 16; + mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr, + "MFC batchbuffer", + mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block, + 0x1000); + mfc_context->buffer_suface_setup(ctx, + &mfc_context->gpe_context, + &mfc_context->mfc_batchbuffer_surface, + BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER), + SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER)); +} + +static void +gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); + gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); +} + +static void +gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + struct gen6_interface_descriptor_data *desc; + int i; + dri_bo *bo; + + bo = mfc_context->gpe_context.idrt.bo; + dri_bo_map(bo, 1); + assert(bo->virtual); + desc = bo->virtual; + + for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) { + struct i965_kernel *kernel; + + kernel = &mfc_context->gpe_context.kernels[i]; + assert(sizeof(*desc) == 32); + + /*Setup the descritor table*/ + memset(desc, 0, sizeof(*desc)); + desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); + desc->desc2.sampler_count = 0; + desc->desc2.sampler_state_pointer = 0; + desc->desc3.binding_table_entry_count = 2; + desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); + desc->desc4.constant_urb_entry_read_offset = 0; + desc->desc4.constant_urb_entry_read_length = 4; + + /*kernel start*/ + dri_bo_emit_reloc(bo, + I915_GEM_DOMAIN_INSTRUCTION, 0, + 0, + i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), + kernel->bo); + desc++; + } + + dri_bo_unmap(bo); +} + +static void +gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + + (void)mfc_context; +} + +static void +gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, + int index, + int head_offset, + int batchbuffer_offset, + int head_size, + int tail_size, + int number_mb_cmds, + int first_object, + int last_object, + int last_slice, + int mb_x, + int mb_y, + int width_in_mbs, + int qp) +{ + BEGIN_BATCH(batch, 12); + + OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2)); + OUT_BATCH(batch, index); + OUT_BATCH(batch, 0); + OUT_BATCH(batch, 0); + OUT_BATCH(batch, 0); + OUT_BATCH(batch, 0); + + /*inline data */ + OUT_BATCH(batch, head_offset); + OUT_BATCH(batch, batchbuffer_offset); + OUT_BATCH(batch, + head_size << 16 | + tail_size); + OUT_BATCH(batch, + number_mb_cmds << 16 | + first_object << 2 | + last_object << 1 | + last_slice); + OUT_BATCH(batch, + mb_y << 8 | + mb_x); + OUT_BATCH(batch, + qp << 16 | + width_in_mbs); + + ADVANCE_BATCH(batch); +} + +static void +gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, + struct intel_encoder_context *encoder_context, + VAEncSliceParameterBufferH264 *slice_param, + int head_offset, + unsigned short head_size, + unsigned short tail_size, + int batchbuffer_offset, + int qp, + int last_slice) +{ + struct intel_batchbuffer *batch = encoder_context->base.batch; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; + int total_mbs = slice_param->number_of_mbs; + int number_mb_cmds = 512; + int starting_mb = 0; + int last_object = 0; + int first_object = 1; + int i; + int mb_x, mb_y; + int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER; + + for (i = 0; i < total_mbs / number_mb_cmds; i++) { + last_object = (total_mbs - starting_mb) == number_mb_cmds; + mb_x = (slice_param->starting_macroblock_address + starting_mb) % width_in_mbs; + mb_y = (slice_param->starting_macroblock_address + starting_mb) / width_in_mbs; + assert(mb_x <= 255 && mb_y <= 255); + + starting_mb += number_mb_cmds; + + gen6_mfc_batchbuffer_emit_object_command(batch, + index, + head_offset, + batchbuffer_offset, + head_size, + tail_size, + number_mb_cmds, + first_object, + last_object, + last_slice, + mb_x, + mb_y, + width_in_mbs, + qp); + + if (first_object) { + head_offset += head_size; + batchbuffer_offset += head_size; + } + + if (last_object) { + head_offset += tail_size; + batchbuffer_offset += tail_size; + } + + batchbuffer_offset += number_mb_cmds * 3; + + first_object = 0; + } + + if (!last_object) { + last_object = 1; + number_mb_cmds = total_mbs % number_mb_cmds; + mb_x = (slice_param->starting_macroblock_address + starting_mb) % width_in_mbs; + mb_y = (slice_param->starting_macroblock_address + starting_mb) / width_in_mbs; + assert(mb_x <= 255 && mb_y <= 255); + starting_mb += number_mb_cmds; + + gen6_mfc_batchbuffer_emit_object_command(batch, + index, + head_offset, + batchbuffer_offset, + head_size, + tail_size, + number_mb_cmds, + first_object, + last_object, + last_slice, + mb_x, + mb_y, + width_in_mbs, + qp); + } +} + +/* + * return size in Owords (16bytes) + */ +static int +gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context, + int slice_index, + int batchbuffer_offset) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; + VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; + VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; + VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; + VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL; + int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; + int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; + int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; + int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs); + int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; + int rate_control_mode = pSequenceParameter->rate_control_method; + unsigned char *slice_header = NULL; + int slice_header_length_in_bits = 0; + unsigned int tail_data[] = { 0x0, 0x0 }; + long head_offset; + int old_used = intel_batchbuffer_used_size(slice_batch), used; + unsigned short head_size, tail_size; + + head_offset = old_used / 16; + gen6_mfc_avc_slice_state(ctx, + pSliceParameter, + encode_state, + encoder_context, + (rate_control_mode == 0), + qp, + slice_batch); + + if (slice_index == 0) + gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); + + if (encode_state->dec_ref_pic_marking) + pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer; + + slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header); + + // slice hander + mfc_context->insert_object(ctx, + encoder_context, + (unsigned int *)slice_header, + ALIGN(slice_header_length_in_bits, 32) >> 5, + slice_header_length_in_bits & 0x1f, + 5, /* first 5 bytes are start code + nal unit type */ + 1, + 0, + 1, + slice_batch); + free(slice_header); + + intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ + used = intel_batchbuffer_used_size(slice_batch); + head_size = (used - old_used) / 16; + old_used = used; + + if (rate_control_mode == 0) { + qp = mfc_context->bit_rate_control_context[1 - is_intra].QpPrimeY; + } + + /* tail */ + if (last_slice) { + mfc_context->insert_object(ctx, + encoder_context, + tail_data, + 2, + 8, + 2, + 1, + 1, + 0, + slice_batch); + } else { + mfc_context->insert_object(ctx, + encoder_context, + tail_data, + 1, + 8, + 1, + 1, + 1, + 0, + slice_batch); + } + + intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ + used = intel_batchbuffer_used_size(slice_batch); + tail_size = (used - old_used) / 16; + + + gen6_mfc_avc_batchbuffer_slice_command(ctx, + encoder_context, + pSliceParameter, + head_offset, + head_size, + tail_size, + batchbuffer_offset, + qp, + last_slice); + + return head_size + tail_size + pSliceParameter->number_of_mbs * 3; +} + +static void +gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + struct intel_batchbuffer *batch = encoder_context->base.batch; + int i, size, offset = 0; + intel_batchbuffer_start_atomic(batch, 0x4000); + gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch); + + for ( i = 0; i < encode_state->num_slice_params_ext; i++) { + size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset); + offset += size; + } + + intel_batchbuffer_end_atomic(batch); + intel_batchbuffer_flush(batch); +} + +static void +gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); + gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); + gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context); + gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context); +} + +static dri_bo * +gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + + gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context); + dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo); + + return mfc_context->mfc_batchbuffer_surface.bo; +} + +#endif + +static void +gen6_mfc_avc_pipeline_programing(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + struct intel_batchbuffer *batch = encoder_context->base.batch; + +#if __SOFTWARE__ + dri_bo *slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context); +#else + dri_bo *slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context); +#endif + + // begin programing + intel_batchbuffer_start_atomic_bcs(batch, 0x4000); + intel_batchbuffer_emit_mi_flush(batch); + + // picture level programing + gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); + + BEGIN_BCS_BATCH(batch, 2); + OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); + OUT_BCS_RELOC(batch, + slice_batch_bo, + I915_GEM_DOMAIN_COMMAND, 0, + 0); + ADVANCE_BCS_BATCH(batch); + + // end programing + intel_batchbuffer_end_atomic(batch); + + dri_bo_unreference(slice_batch_bo); } static VAStatus +gen6_mfc_avc_encode_picture(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context) +{ + VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; + int rate_control_mode = pSequenceParameter->rate_control_method; + int MAX_CBR_INTERATE = 4; + int current_frame_bits_size; + int i; + + for(i = 0; i < MAX_CBR_INTERATE; i++) { + gen6_mfc_init(ctx, encoder_context); + gen6_mfc_avc_prepare(ctx, encode_state, encoder_context); + /*Programing bcs pipeline*/ + gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline + gen6_mfc_run(ctx, encode_state, encoder_context); + gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); + if ( rate_control_mode == 0) { + //gen6_mfc_hrd_context_check(encode_state, mfc_context); + if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) { + gen6_mfc_hrd_context_update(encode_state, mfc_context); + break; + } + } else { + break; + } + } + + return VA_STATUS_SUCCESS; +} + +VAStatus gen6_mfc_pipeline(VADriverContextP ctx, VAProfile profile, struct encode_state *encode_state, @@ -1188,7 +1691,7 @@ gen6_mfc_pipeline(VADriverContextP ctx, return vaStatus; } -static void +void gen6_mfc_context_destroy(void *context) { struct gen6_mfc_context *mfc_context = context; @@ -1229,12 +1732,54 @@ gen6_mfc_context_destroy(void *context) mfc_context->reference_surfaces[i].bo = NULL; } + i965_gpe_context_destroy(&mfc_context->gpe_context); + + dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); + mfc_context->mfc_batchbuffer_surface.bo = NULL; + + dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); + mfc_context->aux_batchbuffer_surface.bo = NULL; + + if (mfc_context->aux_batchbuffer) + intel_batchbuffer_free(mfc_context->aux_batchbuffer); + + mfc_context->aux_batchbuffer = NULL; + free(mfc_context); } Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { - encoder_context->mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); + struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); + + mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; + + mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS; + mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data); + + mfc_context->gpe_context.curbe.length = 32 * 4; + + mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1; + mfc_context->gpe_context.vfe_state.num_urb_entries = 16; + mfc_context->gpe_context.vfe_state.gpgpu_mode = 0; + mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1; + mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1; + + i965_gpe_load_kernels(ctx, + &mfc_context->gpe_context, + gen6_mfc_kernels, + NUM_MFC_KERNEL); + + mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select; + mfc_context->set_surface_state = gen6_mfc_surface_state; + mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state; + mfc_context->avc_img_state = gen6_mfc_avc_img_state; + mfc_context->avc_qm_state = gen6_mfc_avc_qm_state; + mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state; + mfc_context->insert_object = gen6_mfc_avc_insert_object; + mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup; + + encoder_context->mfc_context = mfc_context; encoder_context->mfc_context_destroy = gen6_mfc_context_destroy; encoder_context->mfc_pipeline = gen6_mfc_pipeline; diff --git a/src/gen6_mfc.h b/src/gen6_mfc.h index 9ff5ee4..c7d1580 100644 --- a/src/gen6_mfc.h +++ b/src/gen6_mfc.h @@ -29,15 +29,38 @@ #ifndef _GEN6_MFC_H_ #define _GEN6_MFC_H_ -#include #include #include #include +#include "i965_gpe_utils.h" + struct encode_state; -#define MAX_MFC_REFERENCE_SURFACES 16 -#define NUM_MFC_DMV_BUFFERS 34 +#define MAX_MFC_REFERENCE_SURFACES 16 +#define NUM_MFC_DMV_BUFFERS 34 + +#define __SOFTWARE__ 0 + +#define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32) +#define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32) +#define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7) + +#define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32) +#define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32) +#define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6) + +#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) +#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) +#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) + +#define MFC_BATCHBUFFER_AVC_INTRA 0 +#define MFC_BATCHBUFFER_AVC_INTER 1 +#define NUM_MFC_KERNEL 2 + +#define BIND_IDX_VME_OUTPUT 0 +#define BIND_IDX_MFC_SLICE_HEADER 1 +#define BIND_IDX_MFC_BATCHBUFFER 2 struct gen6_mfc_avc_surface_aux { @@ -45,7 +68,6 @@ struct gen6_mfc_avc_surface_aux dri_bo *dmv_bottom; }; - struct gen6_mfc_context { struct { @@ -55,56 +77,55 @@ struct gen6_mfc_context unsigned int h_pitch; } surface_state; - //MFX_PIPE_BUF_ADDR_STATE struct { dri_bo *bo; - } post_deblocking_output; //OUTPUT: reconstructed picture + } post_deblocking_output; //OUTPUT: reconstructed picture struct { dri_bo *bo; - } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked + } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked struct { dri_bo *bo; - } uncompressed_picture_source; //INPUT: original compressed image + } uncompressed_picture_source; //INPUT: original compressed image struct { dri_bo *bo; - } intra_row_store_scratch_buffer; //INTERNAL: + } intra_row_store_scratch_buffer; //INTERNAL: - struct { - dri_bo *bo; - } macroblock_status_buffer; //INTERNAL: + struct { + dri_bo *bo; + } macroblock_status_buffer; //INTERNAL: struct { dri_bo *bo; - } deblocking_filter_row_store_scratch_buffer; //INTERNAL: + } deblocking_filter_row_store_scratch_buffer; //INTERNAL: struct { - dri_bo *bo; - } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces + dri_bo *bo; + } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces //MFX_IND_OBJ_BASE_ADDR_STATE struct{ dri_bo *bo; - } mfc_indirect_mv_object; //INPUT: the blocks' mv info + } mfc_indirect_mv_object; //INPUT: the blocks' mv info struct { dri_bo *bo; int offset; int end_offset; - } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream + } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream //MFX_BSP_BUF_BASE_ADDR_STATE struct { dri_bo *bo; - }bsd_mpc_row_store_scratch_buffer; //INTERNAL: + } bsd_mpc_row_store_scratch_buffer; //INTERNAL: //MFX_AVC_DIRECTMODE_STATE struct { dri_bo *bo; - }direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output + } direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output //Bit rate tracking context struct { @@ -121,7 +142,7 @@ struct gen6_mfc_context unsigned int target_mb_size; unsigned int target_frame_size; - }bit_rate_control_context[2]; //INTERNAL: 0 for intra frames, 1 for inter frames. + } bit_rate_control_context[2]; //INTERNAL: 0 for intra frames, 1 for inter frames. //HRD control context struct { @@ -137,6 +158,45 @@ struct gen6_mfc_context int i_cpb_removal_delay_length; int i_dpb_output_delay_length; }vui_hrd; + + struct i965_gpe_context gpe_context; + struct i965_buffer_surface mfc_batchbuffer_surface; + struct intel_batchbuffer *aux_batchbuffer; + struct i965_buffer_surface aux_batchbuffer_surface; + + void (*pipe_mode_select)(VADriverContextP ctx, + int standard_select, + struct intel_encoder_context *encoder_context); + void (*set_surface_state)(VADriverContextP ctx, + struct intel_encoder_context *encoder_context); + void (*ind_obj_base_addr_state)(VADriverContextP ctx, + struct intel_encoder_context *encoder_context); + void (*avc_img_state)(VADriverContextP ctx, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); + void (*avc_qm_state)(VADriverContextP ctx, + struct intel_encoder_context *encoder_context); + void (*avc_fqm_state)(VADriverContextP ctx, + struct intel_encoder_context *encoder_context); + void (*insert_object)(VADriverContextP ctx, + struct intel_encoder_context *encoder_context, + unsigned int *insert_data, + int lenght_in_dws, int data_bits_in_last_dw, + int skip_emul_byte_count, + int is_last_header, int is_end_of_slice, + int emulation_flag, + struct intel_batchbuffer *batch); + void (*buffer_suface_setup)(VADriverContextP ctx, + struct i965_gpe_context *gpe_context, + struct i965_buffer_surface *buffer_surface, + unsigned long binding_table_offset, + unsigned long surface_state_offset); }; +VAStatus gen6_mfc_pipeline(VADriverContextP ctx, + VAProfile profile, + struct encode_state *encode_state, + struct intel_encoder_context *encoder_context); +void gen6_mfc_context_destroy(void *context); + #endif /* _GEN6_MFC_BCS_H_ */ diff --git a/src/gen7_mfc.c b/src/gen7_mfc.c index 3d94cf3..ba78886 100644 --- a/src/gen7_mfc.c +++ b/src/gen7_mfc.c @@ -38,29 +38,9 @@ #include "i965_drv_video.h" #include "i965_encoder.h" #include "i965_encoder_utils.h" -#include "gen7_mfc.h" +#include "gen6_mfc.h" #include "gen6_vme.h" -#define SURFACE_STATE_PADDED_SIZE_0_GEN7 ALIGN(sizeof(struct gen7_surface_state), 32) -#define SURFACE_STATE_PADDED_SIZE_1_GEN7 ALIGN(sizeof(struct gen7_surface_state2), 32) -#define SURFACE_STATE_PADDED_SIZE_GEN7 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7) - -#define SURFACE_STATE_PADDED_SIZE_0_GEN6 ALIGN(sizeof(struct i965_surface_state), 32) -#define SURFACE_STATE_PADDED_SIZE_1_GEN6 ALIGN(sizeof(struct i965_surface_state2), 32) -#define SURFACE_STATE_PADDED_SIZE_GEN6 MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6) - -#define SURFACE_STATE_PADDED_SIZE MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7) -#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE * index) -#define BINDING_TABLE_OFFSET(index) (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index) - -#define MFC_BATCHBUFFER_AVC_INTRA 0 -#define MFC_BATCHBUFFER_AVC_INTER 1 -#define NUM_MFC_KERNEL 2 - -#define BIND_IDX_VME_OUTPUT 0 -#define BIND_IDX_MFC_SLICE_HEADER 1 -#define BIND_IDX_MFC_BATCHBUFFER 2 - static const uint32_t gen7_mfc_batchbuffer_avc_intra[][4] = { #include "shaders/utils/mfc_batchbuffer_avc_intra.g7b" }; @@ -128,7 +108,7 @@ static void gen7_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; BEGIN_BCS_BATCH(batch, 6); @@ -154,55 +134,10 @@ gen7_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encod } static void -gen7_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - int i; - - BEGIN_BCS_BATCH(batch, 24); - - OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2)); - OUT_BCS_BATCH(batch, 0); /* pre output addr */ - OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); /* post output addr */ - OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); /* uncompressed data */ - OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); /* StreamOut data*/ - OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); - OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); - - /* 7..22 Reference pictures*/ - for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) { - if ( mfc_context->reference_surfaces[i].bo != NULL) { - OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); - } else { - OUT_BCS_BATCH(batch, 0); - } - } - - OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); /* Macroblock status buffer*/ - - ADVANCE_BCS_BATCH(batch); -} - -static void gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; struct gen6_vme_context *vme_context = encoder_context->vme_context; BEGIN_BCS_BATCH(batch, 11); @@ -231,29 +166,11 @@ gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_cont } static void -gen7_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - - BEGIN_BCS_BATCH(batch, 4); - - OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2)); - OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo, - I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, - 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - - ADVANCE_BCS_BATCH(batch); -} - -static void gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, struct intel_encoder_context *encoder_context) { struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; + struct gen6_mfc_context *mfc_context = encoder_context->mfc_context; VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; @@ -310,137 +227,6 @@ gen7_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state, } static void -gen7_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - - int i; - - BEGIN_BCS_BATCH(batch, 69); - - OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2)); - - /* Reference frames and Current frames */ - for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++) { - if (mfc_context->direct_mv_buffers[i].bo != NULL) { - OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - 0); - } else { - OUT_BCS_BATCH(batch, 0); - } - } - - /* POL list */ - for (i = 0; i < 32; i++) { - OUT_BCS_BATCH(batch, i / 2); - } - - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - - ADVANCE_BCS_BATCH(batch); -} - -static void -gen7_mfc_avc_slice_state(VADriverContextP ctx, - VAEncSliceParameterBufferH264 *slice_param, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int rate_control_enable, - int qp, - struct intel_batchbuffer *batch) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - int beginmb = slice_param->starting_macroblock_address; - int endmb = beginmb + slice_param->number_of_mbs; - int beginx = beginmb % width_in_mbs; - int beginy = beginmb / width_in_mbs; - int nextx = endmb % width_in_mbs; - int nexty = endmb / width_in_mbs; - int slice_type = slice_param->slice_type; - int last_slice = (endmb == (width_in_mbs * height_in_mbs)); - int bit_rate_control_target, maxQpN, maxQpP; - unsigned char correct[6], grow, shrink; - int i; - - if (batch == NULL) - batch = encoder_context->base.batch; - - if (slice_type == SLICE_TYPE_I) - bit_rate_control_target = 0; - else - bit_rate_control_target = 1; - - maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier; - maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier; - - for (i = 0; i < 6; i++) - correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i]; - - grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit + - (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4); - shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit + - (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4); - - BEGIN_BCS_BATCH(batch, 11);; - - OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) ); - OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/ - - if (slice_type == SLICE_TYPE_I) { - OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/ - } else { - OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/ - } - - OUT_BCS_BATCH(batch, - (slice_param->direct_spatial_mv_pred_flag << 29) | /*Direct Prediction Type*/ - (0 << 24) | /*Enable deblocking operation*/ - (qp << 16) | /*Slice Quantization Parameter*/ - (0x0202 << 0)); - OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/ - (beginx << 16) | - slice_param->starting_macroblock_address ); - OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/ - OUT_BCS_BATCH(batch, - (rate_control_enable << 31) | /*in CBR mode RateControlCounterEnable = enable*/ - (1 << 30) | /*ResetRateControlCounter*/ - (0 << 28) | /*RC Triggle Mode = Always Rate Control*/ - (4 << 24) | /*RC Stable Tolerance, middle level*/ - (rate_control_enable << 23) | /*RC Panic Enable*/ - (0 << 22) | /*QP mode, don't modfiy CBP*/ - (0 << 21) | /*MB Type Direct Conversion Enabled*/ - (0 << 20) | /*MB Type Skip Conversion Enabled*/ - (last_slice << 19) | /*IsLastSlice*/ - (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/ - (1 << 17) | /*HeaderPresentFlag*/ - (1 << 16) | /*SliceData PresentFlag*/ - (1 << 15) | /*TailPresentFlag*/ - (1 << 13) | /*RBSP NAL TYPE*/ - (0 << 12) ); /*CabacZeroWordInsertionEnable*/ - OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset); - OUT_BCS_BATCH(batch, - (maxQpN << 24) | /*Target QP - 24 is lowest QP*/ - (maxQpP << 16) | /*Target QP + 20 is highest QP*/ - (shrink << 8) | - (grow << 0)); - OUT_BCS_BATCH(batch, - (correct[5] << 20) | - (correct[4] << 16) | - (correct[3] << 12) | - (correct[2] << 8) | - (correct[1] << 4) | - (correct[0] << 0)); - OUT_BCS_BATCH(batch, 0); - - ADVANCE_BCS_BATCH(batch); -} - -static void gen7_mfc_qm_state(VADriverContextP ctx, int qm_type, unsigned int *qm, @@ -519,33 +305,6 @@ gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encod } static void -gen7_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - int i; - - BEGIN_BCS_BATCH(batch, 10); - OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); - OUT_BCS_BATCH(batch, 0); //Select L0 - OUT_BCS_BATCH(batch, 0x80808020); //Only 1 reference - - for (i = 0; i < 7; i++) { - OUT_BCS_BATCH(batch, 0x80808080); - } - - ADVANCE_BCS_BATCH(batch); - - BEGIN_BCS_BATCH(batch, 10); - OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8); - OUT_BCS_BATCH(batch, 1); //Select L1 - OUT_BCS_BATCH(batch, 0x80808022); //Only 1 reference - for(i = 0; i < 7; i++) { - OUT_BCS_BATCH(batch, 0x80808080); - } - ADVANCE_BCS_BATCH(batch); -} - -static void gen7_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context, unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw, int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag, @@ -570,1261 +329,10 @@ gen7_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *e ADVANCE_BCS_BATCH(batch); } -static int -gen7_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size, unsigned char max_mb_size, - struct intel_batchbuffer *batch) -{ - int len_in_dwords = 11; - - if (batch == NULL) - batch = encoder_context->base.batch; - - BEGIN_BCS_BATCH(batch, len_in_dwords); - - OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, - (0 << 24) | /* PackedMvNum, Debug*/ - (0 << 20) | /* No motion vector */ - (1 << 19) | /* CbpDcY */ - (1 << 18) | /* CbpDcU */ - (1 << 17) | /* CbpDcV */ - (msg[0] & 0xFFFF) ); - - OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/ - OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ - OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */ - - /*Stuff for Intra MB*/ - OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/ - OUT_BCS_BATCH(batch, msg[2]); - OUT_BCS_BATCH(batch, msg[3]&0xFC); - - /*MaxSizeInWord and TargetSzieInWord*/ - OUT_BCS_BATCH(batch, (max_mb_size << 24) | - (target_mb_size << 16) ); - - ADVANCE_BCS_BATCH(batch); - - return len_in_dwords; -} - -int -gen7_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset, - struct intel_encoder_context *encoder_context, - unsigned char target_mb_size,unsigned char max_mb_size, int slice_type, - struct intel_batchbuffer *batch) -{ - int len_in_dwords = 11; - - if (batch == NULL) - batch = encoder_context->base.batch; - - BEGIN_BCS_BATCH(batch, len_in_dwords); - - OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2)); - - OUT_BCS_BATCH(batch, 32); /* 32 MV*/ - OUT_BCS_BATCH(batch, offset); - - OUT_BCS_BATCH(batch, - (1 << 24) | /* PackedMvNum, Debug*/ - (4 << 20) | /* 8 MV, SNB don't use it*/ - (1 << 19) | /* CbpDcY */ - (1 << 18) | /* CbpDcU */ - (1 << 17) | /* CbpDcV */ - (0 << 15) | /* Transform8x8Flag = 0*/ - (0 << 14) | /* Frame based*/ - (0 << 13) | /* Inter MB */ - (1 << 8) | /* MbType = P_L0_16x16 */ - (0 << 7) | /* MBZ for frame */ - (0 << 6) | /* MBZ */ - (2 << 4) | /* MBZ for inter*/ - (0 << 3) | /* MBZ */ - (0 << 2) | /* SkipMbFlag */ - (0 << 0)); /* InterMbMode */ - - OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/ - OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */ -#if 0 - if ( slice_type == SLICE_TYPE_B) { - OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */ - } else { - OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ - } -#else - OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */ -#endif - - - /*Stuff for Inter MB*/ - OUT_BCS_BATCH(batch, 0x0); - OUT_BCS_BATCH(batch, 0x0); - OUT_BCS_BATCH(batch, 0x0); - - /*MaxSizeInWord and TargetSzieInWord*/ - OUT_BCS_BATCH(batch, (max_mb_size << 24) | - (target_mb_size << 16) ); - - ADVANCE_BCS_BATCH(batch); - - return len_in_dwords; -} - -static void -gen7_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) -{ - struct i965_driver_data *i965 = i965_driver_data(ctx); - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - dri_bo *bo; - int i; - - /*Encode common setup for MFC*/ - dri_bo_unreference(mfc_context->post_deblocking_output.bo); - mfc_context->post_deblocking_output.bo = NULL; - - dri_bo_unreference(mfc_context->pre_deblocking_output.bo); - mfc_context->pre_deblocking_output.bo = NULL; - - dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); - mfc_context->uncompressed_picture_source.bo = NULL; - - dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); - mfc_context->mfc_indirect_pak_bse_object.bo = NULL; - - for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ - if ( mfc_context->direct_mv_buffers[i].bo != NULL); - dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); - mfc_context->direct_mv_buffers[i].bo = NULL; - } - - for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ - if (mfc_context->reference_surfaces[i].bo != NULL) - dri_bo_unreference(mfc_context->reference_surfaces[i].bo); - mfc_context->reference_surfaces[i].bo = NULL; - } - - dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); - bo = dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 128 * 64, - 64); - assert(bo); - mfc_context->intra_row_store_scratch_buffer.bo = bo; - - dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); - bo = dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 128*128*16, - 64); - assert(bo); - mfc_context->macroblock_status_buffer.bo = bo; - - dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); - bo = dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 49152, /* 6 * 128 * 64 */ - 64); - assert(bo); - mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo; - - dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); - bo = dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 12288, /* 1.5 * 128 * 64 */ - 0x1000); - assert(bo); - mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo; - - dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); - mfc_context->mfc_batchbuffer_surface.bo = NULL; - - dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); - mfc_context->aux_batchbuffer_surface.bo = NULL; - - if (mfc_context->aux_batchbuffer) - intel_batchbuffer_free(mfc_context->aux_batchbuffer); - - mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD); - mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer; - dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo); - mfc_context->aux_batchbuffer_surface.pitch = 16; - mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16; - mfc_context->aux_batchbuffer_surface.size_block = 16; - - i965_gpe_context_init(ctx, &mfc_context->gpe_context); -} - -static void gen7_mfc_avc_pipeline_header_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - struct intel_batchbuffer *slice_batch) -{ - static int count = 0; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - int rate_control_mode = pSequenceParameter->rate_control_method; - - if (encode_state->packed_header_data[VAEncPackedHeaderSPS]) { - VAEncPackedHeaderParameterBuffer *param = NULL; - unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderSPS]->buffer; - unsigned int length_in_bits; - - assert(encode_state->packed_header_param[VAEncPackedHeaderSPS]); - param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderSPS]->buffer; - length_in_bits = param->length_in_bits[0]; - - gen7_mfc_avc_insert_object(ctx, - encoder_context, - header_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - param->skip_emulation_check_count, - 0, - 0, - param->insert_emulation_bytes, - slice_batch); - } - - if (encode_state->packed_header_data[VAEncPackedHeaderPPS]) { - VAEncPackedHeaderParameterBuffer *param = NULL; - unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderPPS]->buffer; - unsigned int length_in_bits; - - assert(encode_state->packed_header_param[VAEncPackedHeaderPPS]); - param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderPPS]->buffer; - length_in_bits = param->length_in_bits[0]; - - gen7_mfc_avc_insert_object(ctx, - encoder_context, - header_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - param->skip_emulation_check_count, - 0, - 0, - param->insert_emulation_bytes, - slice_batch); - } - - if ( (rate_control_mode == 0) && encode_state->packed_header_data[VAEncPackedHeaderSPS]) { // this is frist AU - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - unsigned char *sei_data = NULL; - int length_in_bits = build_avc_sei_buffering_period(mfc_context->vui_hrd.i_initial_cpb_removal_delay_length, - - mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, &sei_data); - gen7_mfc_avc_insert_object(ctx, - encoder_context, - (unsigned int *)sei_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - 4, - 0, - 0, - 1, - slice_batch); - free(sei_data); - } - - // SEI pic_timing header - if ( rate_control_mode == 0) { - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - unsigned char *sei_data = NULL; - int length_in_bits = build_avc_sei_pic_timing( mfc_context->vui_hrd.i_cpb_removal_delay_length, - mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number, - mfc_context->vui_hrd.i_dpb_output_delay_length, - 0, &sei_data); - gen7_mfc_avc_insert_object(ctx, - encoder_context, - (unsigned int *)sei_data, - ALIGN(length_in_bits, 32) >> 5, - length_in_bits & 0x1f, - 4, - 0, - 0, - 1, - slice_batch); - free(sei_data); - } - - count++; -} - -static void gen7_mfc_avc_pipeline_picture_programing( VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context); - gen7_mfc_surface_state(ctx, encoder_context); - gen7_mfc_ind_obj_base_addr_state(ctx, encoder_context); - gen7_mfc_pipe_buf_addr_state(ctx, encoder_context); - gen7_mfc_bsp_buf_base_addr_state(ctx, encoder_context); - gen7_mfc_avc_img_state(ctx, encode_state, encoder_context); - gen7_mfc_avc_qm_state(ctx, encoder_context); - gen7_mfc_avc_fqm_state(ctx, encoder_context); - gen7_mfc_avc_directmode_state(ctx, encoder_context); - gen7_mfc_avc_ref_idx_state(ctx, encoder_context); -} - -static void -gen7_mfc_avc_pipeline_slice_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index, - struct intel_batchbuffer *slice_batch) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - struct gen6_vme_context *vme_context = encoder_context->vme_context; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; - VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; - VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL; - unsigned int *msg = NULL, offset = 0; - int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs); - int i,x,y; - int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; - int rate_control_mode = pSequenceParameter->rate_control_method; - unsigned char *slice_header = NULL; - int slice_header_length_in_bits = 0; - unsigned int tail_data[] = { 0x0, 0x0 }; - - gen7_mfc_avc_slice_state(ctx, pSliceParameter, - encode_state, encoder_context, - (rate_control_mode == 0), qp, slice_batch); - - if (slice_index == 0) - gen7_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); - - if (encode_state->dec_ref_pic_marking) - pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer; - slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header); - - // slice hander - gen7_mfc_avc_insert_object(ctx, encoder_context, - (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f, - 5, /* first 5 bytes are start code + nal unit type */ - 1, 0, 1, slice_batch); - - if ( rate_control_mode == 0) { - qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY; - } - - if (is_intra) { - dri_bo_map(vme_context->vme_output.bo , 1); - msg = (unsigned int *)vme_context->vme_output.bo->virtual; - } - - for (i = pSliceParameter->starting_macroblock_address; - i < pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs; i++) { - int last_mb = (i == (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs - 1) ); - x = i % width_in_mbs; - y = i / width_in_mbs; - - if (is_intra) { - assert(msg); - gen7_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch); - msg += 4; - } else { - gen7_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch); - offset += 64; - } - } - - if (is_intra) - dri_bo_unmap(vme_context->vme_output.bo); - - if ( last_slice ) { - gen7_mfc_avc_insert_object(ctx, encoder_context, - tail_data, 2, 8, - 2, 1, 1, 0, slice_batch); - } else { - gen7_mfc_avc_insert_object(ctx, encoder_context, - tail_data, 1, 8, - 1, 1, 1, 0, slice_batch); - } - - free(slice_header); -} -static void -gen7_mfc_free_avc_surface(void **data) -{ - struct gen7_mfc_avc_surface_aux *avc_surface = *data; - - if (!avc_surface) - return; - - dri_bo_unreference(avc_surface->dmv_top); - avc_surface->dmv_top = NULL; - dri_bo_unreference(avc_surface->dmv_bottom); - avc_surface->dmv_bottom = NULL; - - free(avc_surface); - *data = NULL; -} - -static void -gen7_mfc_bit_rate_control_context_init(struct encode_state *encode_state, - struct gen7_mfc_context *mfc_context) -{ - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - float fps = pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ; - int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs; - int intra_mb_size = inter_mb_size * 5.0; - int i; - - mfc_context->bit_rate_control_context[0].target_mb_size = intra_mb_size; - mfc_context->bit_rate_control_context[0].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs; - mfc_context->bit_rate_control_context[1].target_mb_size = inter_mb_size; - mfc_context->bit_rate_control_context[1].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs; - - for(i = 0 ; i < 2; i++) { - mfc_context->bit_rate_control_context[i].QpPrimeY = 26; - mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6; - mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6; - mfc_context->bit_rate_control_context[i].GrowInit = 6; - mfc_context->bit_rate_control_context[i].GrowResistance = 4; - mfc_context->bit_rate_control_context[i].ShrinkInit = 6; - mfc_context->bit_rate_control_context[i].ShrinkResistance = 4; - - mfc_context->bit_rate_control_context[i].Correct[0] = 8; - mfc_context->bit_rate_control_context[i].Correct[1] = 4; - mfc_context->bit_rate_control_context[i].Correct[2] = 2; - mfc_context->bit_rate_control_context[i].Correct[3] = 2; - mfc_context->bit_rate_control_context[i].Correct[4] = 4; - mfc_context->bit_rate_control_context[i].Correct[5] = 8; - } - - mfc_context->bit_rate_control_context[0].TargetSizeInWord = (intra_mb_size + 16)/ 16; - mfc_context->bit_rate_control_context[1].TargetSizeInWord = (inter_mb_size + 16)/ 16; - - mfc_context->bit_rate_control_context[0].MaxSizeInWord = mfc_context->bit_rate_control_context[0].TargetSizeInWord * 1.5; - mfc_context->bit_rate_control_context[1].MaxSizeInWord = mfc_context->bit_rate_control_context[1].TargetSizeInWord * 1.5; -} - -static int -gen7_mfc_bit_rate_control_context_update(struct encode_state *encode_state, - struct gen7_mfc_context *mfc_context, - int current_frame_size) -{ - VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; - int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I); - int oldQp = mfc_context->bit_rate_control_context[control_index].QpPrimeY; - - if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 4.0 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY += 4; - } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 2.0 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY += 3; - } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.50 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY += 2; - } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.20 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY ++; - } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.30 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 3; - } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.50 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 2; - } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.80 ) { - mfc_context->bit_rate_control_context[control_index].QpPrimeY --; - } - - if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY > 51) - mfc_context->bit_rate_control_context[control_index].QpPrimeY = 51; - if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY < 1) - mfc_context->bit_rate_control_context[control_index].QpPrimeY = 1; - - if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY != oldQp) - return 0; - - return 1; -} -static void -gen7_mfc_hrd_context_init(struct encode_state *encode_state, - struct gen7_mfc_context *mfc_context) -{ - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - int rate_control_mode = pSequenceParameter->rate_control_method; - int target_bit_rate = pSequenceParameter->bits_per_second; - - // current we only support CBR mode. - if ( rate_control_mode == 0) { - mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10; - mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10; - mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000; - mfc_context->vui_hrd.i_cpb_removal_delay = 2; - mfc_context->vui_hrd.i_frame_number = 0; - - mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24; - mfc_context->vui_hrd.i_cpb_removal_delay_length = 24; - mfc_context->vui_hrd.i_dpb_output_delay_length = 24; - } - -} - -static VAStatus -gen7_mfc_hrd_context_check(struct encode_state *encode_state, - struct gen7_mfc_context *mfc_context) -{ - return VA_STATUS_SUCCESS; -} - -static void -gen7_mfc_hrd_context_update(struct encode_state *encode_state, - struct gen7_mfc_context *mfc_context) -{ - mfc_context->vui_hrd.i_frame_number++; -} - -static VAStatus -gen7_mfc_avc_prepare(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct i965_driver_data *i965 = i965_driver_data(ctx); - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - struct object_surface *obj_surface; - struct object_buffer *obj_buffer; - struct gen7_mfc_avc_surface_aux* gen7_avc_surface; - dri_bo *bo; - VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - int rate_control_mode = pSequenceParameter->rate_control_method; - VAStatus vaStatus = VA_STATUS_SUCCESS; - int i; - - /*Setup all the input&output object*/ - - /* Setup current frame and current direct mv buffer*/ - obj_surface = SURFACE(pPicParameter->CurrPic.picture_id); - assert(obj_surface); - i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420); - - if ( obj_surface->private_data == NULL) { - gen7_avc_surface = calloc(sizeof(struct gen7_mfc_avc_surface_aux), 1); - gen7_avc_surface->dmv_top = - dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 68*8192, - 64); - gen7_avc_surface->dmv_bottom = - dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 68*8192, - 64); - assert(gen7_avc_surface->dmv_top); - assert(gen7_avc_surface->dmv_bottom); - obj_surface->private_data = (void *)gen7_avc_surface; - obj_surface->free_private_data = (void *)gen7_mfc_free_avc_surface; - } - - gen7_avc_surface = (struct gen7_mfc_avc_surface_aux*) obj_surface->private_data; - mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen7_avc_surface->dmv_top; - mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen7_avc_surface->dmv_bottom; - dri_bo_reference(gen7_avc_surface->dmv_top); - dri_bo_reference(gen7_avc_surface->dmv_bottom); - - mfc_context->post_deblocking_output.bo = obj_surface->bo; - dri_bo_reference(mfc_context->post_deblocking_output.bo); - - mfc_context->surface_state.width = obj_surface->orig_width; - mfc_context->surface_state.height = obj_surface->orig_height; - mfc_context->surface_state.w_pitch = obj_surface->width; - mfc_context->surface_state.h_pitch = obj_surface->height; - - /* Setup reference frames and direct mv buffers*/ - for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) { - if (pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID) { - obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id); - assert(obj_surface); - if (obj_surface->bo != NULL) { - mfc_context->reference_surfaces[i].bo = obj_surface->bo; - dri_bo_reference(obj_surface->bo); - } - /* Check DMV buffer */ - if (obj_surface->private_data == NULL) { - - gen7_avc_surface = calloc(sizeof(struct gen7_mfc_avc_surface_aux), 1); - gen7_avc_surface->dmv_top = - dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 68*8192, - 64); - gen7_avc_surface->dmv_bottom = - dri_bo_alloc(i965->intel.bufmgr, - "Buffer", - 68*8192, - 64); - assert(gen7_avc_surface->dmv_top); - assert(gen7_avc_surface->dmv_bottom); - obj_surface->private_data = gen7_avc_surface; - obj_surface->free_private_data = gen7_mfc_free_avc_surface; - } - - gen7_avc_surface = (struct gen7_mfc_avc_surface_aux*) obj_surface->private_data; - /* Setup DMV buffer */ - mfc_context->direct_mv_buffers[i*2].bo = gen7_avc_surface->dmv_top; - mfc_context->direct_mv_buffers[i*2+1].bo = gen7_avc_surface->dmv_bottom; - dri_bo_reference(gen7_avc_surface->dmv_top); - dri_bo_reference(gen7_avc_surface->dmv_bottom); - } else { - break; - } - } - - obj_surface = SURFACE(encoder_context->input_yuv_surface); - assert(obj_surface && obj_surface->bo); - mfc_context->uncompressed_picture_source.bo = obj_surface->bo; - dri_bo_reference(mfc_context->uncompressed_picture_source.bo); - - obj_buffer = BUFFER (pPicParameter->CodedBuf); /* FIXME: fix this later */ - bo = obj_buffer->buffer_store->bo; - assert(bo); - mfc_context->mfc_indirect_pak_bse_object.bo = bo; - mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64); - mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN (obj_buffer->size_element - 0x1000, 0x1000); - dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo); - - /*Programing bit rate control */ - if ( mfc_context->bit_rate_control_context[0].MaxSizeInWord == 0 ) - gen7_mfc_bit_rate_control_context_init(encode_state, mfc_context); - - /*Programing HRD control */ - if ( (rate_control_mode == 0) && (mfc_context->vui_hrd.i_cpb_size_value == 0) ) - gen7_mfc_hrd_context_init(encode_state, mfc_context); - - return vaStatus; -} - -static VAStatus -gen7_mfc_run(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - - intel_batchbuffer_flush(batch); //run the pipeline - - return VA_STATUS_SUCCESS; -} - -static VAStatus -gen7_mfc_stop(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int *encoded_bits_size) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - unsigned int *status_mem; - unsigned int buffer_size_bits = 0; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - int i; - - dri_bo_map(mfc_context->macroblock_status_buffer.bo, 1); - status_mem = (unsigned int *)mfc_context->macroblock_status_buffer.bo->virtual; - - //Detecting encoder buffer size and bit rate control result - for(i = 0; i < width_in_mbs * height_in_mbs; i++) { - unsigned short current_mb = status_mem[1] >> 16; - buffer_size_bits += current_mb; - status_mem += 4; - } - - dri_bo_unmap(mfc_context->macroblock_status_buffer.bo); - - *encoded_bits_size = buffer_size_bits; - - return VA_STATUS_SUCCESS; -} - -static void -gen7_mfc_batchbuffer_surfaces_input(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) - -{ - struct gen6_vme_context *vme_context = encoder_context->vme_context; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - - assert(vme_context->vme_output.bo); - gen7_gpe_buffer_suface_setup(ctx, - &mfc_context->gpe_context, - &vme_context->vme_output, - BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT), - SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT)); - assert(mfc_context->aux_batchbuffer_surface.bo); - gen7_gpe_buffer_suface_setup(ctx, - &mfc_context->gpe_context, - &mfc_context->aux_batchbuffer_surface, - BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER), - SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER)); -} - -static void -gen7_mfc_batchbuffer_surfaces_output(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) - -{ - struct i965_driver_data *i965 = i965_driver_data(ctx); - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - int width_in_mbs = pSequenceParameter->picture_width_in_mbs; - int height_in_mbs = pSequenceParameter->picture_height_in_mbs; - mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 2 + 1; - mfc_context->mfc_batchbuffer_surface.size_block = 48; /* 3 OWORDs */ - mfc_context->mfc_batchbuffer_surface.pitch = 16; - mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr, - "MFC batchbuffer", - mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block, - 0x1000); - gen7_gpe_buffer_suface_setup(ctx, - &mfc_context->gpe_context, - &mfc_context->mfc_batchbuffer_surface, - BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER), - SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER)); -} - -static void -gen7_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - gen7_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context); - gen7_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context); -} - -static void -gen7_mfc_batchbuffer_idrt_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - struct gen6_interface_descriptor_data *desc; - int i; - dri_bo *bo; - - bo = mfc_context->gpe_context.idrt.bo; - dri_bo_map(bo, 1); - assert(bo->virtual); - desc = bo->virtual; - - for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) { - struct i965_kernel *kernel; - - kernel = &mfc_context->gpe_context.kernels[i]; - assert(sizeof(*desc) == 32); - - /*Setup the descritor table*/ - memset(desc, 0, sizeof(*desc)); - desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6); - desc->desc2.sampler_count = 0; - desc->desc2.sampler_state_pointer = 0; - desc->desc3.binding_table_entry_count = 2; - desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5); - desc->desc4.constant_urb_entry_read_offset = 0; - desc->desc4.constant_urb_entry_read_length = 4; - - /*kernel start*/ - dri_bo_emit_reloc(bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - 0, - i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0), - kernel->bo); - desc++; - } - - dri_bo_unmap(bo); -} - -static void -gen7_mfc_batchbuffer_constant_setup(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - - (void)mfc_context; -} - -static void -gen7_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch, - int index, - int head_offset, - int batchbuffer_offset, - int head_size, - int tail_size, - int number_mb_cmds, - int first_object, - int last_object, - int last_slice, - int mb_x, - int mb_y, - int width_in_mbs, - int qp) -{ - BEGIN_BATCH(batch, 12); - - OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2)); - OUT_BATCH(batch, index); - OUT_BATCH(batch, 0); - OUT_BATCH(batch, 0); - OUT_BATCH(batch, 0); - OUT_BATCH(batch, 0); - - /*inline data */ - OUT_BATCH(batch, head_offset); - OUT_BATCH(batch, batchbuffer_offset); - OUT_BATCH(batch, - head_size << 16 | - tail_size); - OUT_BATCH(batch, - number_mb_cmds << 16 | - first_object << 2 | - last_object << 1 | - last_slice); - OUT_BATCH(batch, - mb_y << 8 | - mb_x); - OUT_BATCH(batch, - qp << 16 | - width_in_mbs); - - ADVANCE_BATCH(batch); -} - -static void -gen7_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx, - struct intel_encoder_context *encoder_context, - VAEncSliceParameterBufferH264 *slice_param, - int head_offset, - unsigned short head_size, - unsigned short tail_size, - int batchbuffer_offset, - int qp, - int last_slice) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int total_mbs = slice_param->number_of_mbs; - int number_mb_cmds = 512; - int starting_mb = 0; - int last_object = 0; - int first_object = 1; - int i; - int mb_x, mb_y; - int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER; - - for (i = 0; i < total_mbs / number_mb_cmds; i++) { - last_object = (total_mbs - starting_mb) == number_mb_cmds; - mb_x = (slice_param->starting_macroblock_address + starting_mb) % width_in_mbs; - mb_y = (slice_param->starting_macroblock_address + starting_mb) / width_in_mbs; - assert(mb_x <= 255 && mb_y <= 255); - - starting_mb += number_mb_cmds; - - gen7_mfc_batchbuffer_emit_object_command(batch, - index, - head_offset, - batchbuffer_offset, - head_size, - tail_size, - number_mb_cmds, - first_object, - last_object, - last_slice, - mb_x, - mb_y, - width_in_mbs, - qp); - - if (first_object) { - head_offset += head_size; - batchbuffer_offset += head_size; - } - - if (last_object) { - head_offset += tail_size; - batchbuffer_offset += tail_size; - } - - batchbuffer_offset += number_mb_cmds * 3; - - first_object = 0; - } - - if (!last_object) { - last_object = 1; - number_mb_cmds = total_mbs % number_mb_cmds; - mb_x = (slice_param->starting_macroblock_address + starting_mb) % width_in_mbs; - mb_y = (slice_param->starting_macroblock_address + starting_mb) / width_in_mbs; - assert(mb_x <= 255 && mb_y <= 255); - starting_mb += number_mb_cmds; - - gen7_mfc_batchbuffer_emit_object_command(batch, - index, - head_offset, - batchbuffer_offset, - head_size, - tail_size, - number_mb_cmds, - first_object, - last_object, - last_slice, - mb_x, - mb_y, - width_in_mbs, - qp); - } -} - -/* - * return size in Owords (16bytes) - */ -static int -gen7_mfc_avc_batchbuffer_slice(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context, - int slice_index, - int batchbuffer_offset) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer; - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer; - VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer; - VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL; - int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I; - int width_in_mbs = (mfc_context->surface_state.width + 15) / 16; - int height_in_mbs = (mfc_context->surface_state.height + 15) / 16; - int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs); - int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta; - int rate_control_mode = pSequenceParameter->rate_control_method; - unsigned char *slice_header = NULL; - int slice_header_length_in_bits = 0; - unsigned int tail_data[] = { 0x0, 0x0 }; - long head_offset; - int old_used = intel_batchbuffer_used_size(slice_batch), used; - unsigned short head_size, tail_size; - - head_offset = old_used / 16; - gen7_mfc_avc_slice_state(ctx, - pSliceParameter, - encode_state, - encoder_context, - (rate_control_mode == 0), - qp, - slice_batch); - - if (slice_index == 0) - gen7_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch); - - if (encode_state->dec_ref_pic_marking) - pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer; - - slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header); - - // slice hander - gen7_mfc_avc_insert_object(ctx, - encoder_context, - (unsigned int *)slice_header, - ALIGN(slice_header_length_in_bits, 32) >> 5, - slice_header_length_in_bits & 0x1f, - 5, /* first 5 bytes are start code + nal unit type */ - 1, - 0, - 1, - slice_batch); - free(slice_header); - - intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ - used = intel_batchbuffer_used_size(slice_batch); - head_size = (used - old_used) / 16; - old_used = used; - - if (rate_control_mode == 0) { - qp = mfc_context->bit_rate_control_context[1 - is_intra].QpPrimeY; - } - - /* tail */ - if (last_slice) { - gen7_mfc_avc_insert_object(ctx, - encoder_context, - tail_data, - 2, - 8, - 2, - 1, - 1, - 0, - slice_batch); - } else { - gen7_mfc_avc_insert_object(ctx, - encoder_context, - tail_data, - 1, - 8, - 1, - 1, - 1, - 0, - slice_batch); - } - - intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */ - used = intel_batchbuffer_used_size(slice_batch); - tail_size = (used - old_used) / 16; - - - gen7_mfc_avc_batchbuffer_slice_command(ctx, - encoder_context, - pSliceParameter, - head_offset, - head_size, - tail_size, - batchbuffer_offset, - qp, - last_slice); - - return head_size + tail_size + pSliceParameter->number_of_mbs * 3; -} - -static void -gen7_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - struct intel_batchbuffer *batch = encoder_context->base.batch; - int i, size, offset = 0; - intel_batchbuffer_start_atomic(batch, 0x4000); - gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch); - - for ( i = 0; i < encode_state->num_slice_params_ext; i++) { - size = gen7_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset); - offset += size; - } - - intel_batchbuffer_end_atomic(batch); - intel_batchbuffer_flush(batch); -} - -static void -gen7_mfc_build_avc_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - gen7_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context); - gen7_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context); - gen7_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context); - gen7_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context); -} - - -#if __SOFTWARE__ -static dri_bo * -gen7_mfc_avc_software_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct i965_driver_data *i965 = i965_driver_data(ctx); - struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD); - dri_bo *batch_bo = batch->buffer; - int i, used; - - for (i = 0; i < encode_state->num_slice_params_ext; i++) { - gen7_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch); - } - - used = intel_batchbuffer_used_size(batch); - - if ((used & 4) == 0) { - BEGIN_BCS_BATCH(batch, 2); - OUT_BCS_BATCH(batch, 0); - OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END); - } - - dri_bo_reference(batch_bo); - intel_batchbuffer_free(batch); - - return batch_bo; -} - -#else - -static dri_bo * -gen7_mfc_avc_hardware_batchbuffer(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - - gen7_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context); - dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo); - - return mfc_context->mfc_batchbuffer_surface.bo; -} - -#endif - -static void -gen7_mfc_avc_pipeline_programing(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - struct intel_batchbuffer *batch = encoder_context->base.batch; - -#if __SOFTWARE__ - dri_bo *slice_batch_bo = gen7_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context); -#else - dri_bo *slice_batch_bo = gen7_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context); -#endif - - // begin programing - intel_batchbuffer_start_atomic_bcs(batch, 0x4000); - intel_batchbuffer_emit_mi_flush(batch); - - // picture level programing - gen7_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context); - - BEGIN_BCS_BATCH(batch, 2); - OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8)); - OUT_BCS_RELOC(batch, - slice_batch_bo, - I915_GEM_DOMAIN_COMMAND, 0, - 0); - ADVANCE_BCS_BATCH(batch); - - // end programing - intel_batchbuffer_end_atomic(batch); - - dri_bo_unreference(slice_batch_bo); -} - -static VAStatus -gen7_mfc_avc_encode_picture(VADriverContextP ctx, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer; - struct gen7_mfc_context *mfc_context = encoder_context->mfc_context; - int rate_control_mode = pSequenceParameter->rate_control_method; - int MAX_CBR_INTERATE = 4; - int current_frame_bits_size; - int i; - - for(i = 0; i < MAX_CBR_INTERATE; i++) { - gen7_mfc_init(ctx, encoder_context); - gen7_mfc_avc_prepare(ctx, encode_state, encoder_context); - /*Programing bcs pipeline*/ - gen7_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline - gen7_mfc_run(ctx, encode_state, encoder_context); - gen7_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size); - - if (rate_control_mode == 0) { - //gen7_mfc_hrd_context_check(encode_state, mfc_context); - if (gen7_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size)) { - gen7_mfc_hrd_context_update(encode_state, mfc_context); - break; - } - } else { - break; - } - } - - return VA_STATUS_SUCCESS; -} - -static VAStatus -gen7_mfc_pipeline(VADriverContextP ctx, - VAProfile profile, - struct encode_state *encode_state, - struct intel_encoder_context *encoder_context) -{ - VAStatus vaStatus; - - switch (profile) { - case VAProfileH264Baseline: - vaStatus = gen7_mfc_avc_encode_picture(ctx, encode_state, encoder_context); - break; - - /* FIXME: add for other profile */ - default: - vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE; - break; - } - - return vaStatus; -} - -static void -gen7_mfc_context_destroy(void *context) -{ - struct gen7_mfc_context *mfc_context = context; - int i; - - dri_bo_unreference(mfc_context->post_deblocking_output.bo); - mfc_context->post_deblocking_output.bo = NULL; - - dri_bo_unreference(mfc_context->pre_deblocking_output.bo); - mfc_context->pre_deblocking_output.bo = NULL; - - dri_bo_unreference(mfc_context->uncompressed_picture_source.bo); - mfc_context->uncompressed_picture_source.bo = NULL; - - dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo); - mfc_context->mfc_indirect_pak_bse_object.bo = NULL; - - for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){ - dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo); - mfc_context->direct_mv_buffers[i].bo = NULL; - } - - dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo); - mfc_context->intra_row_store_scratch_buffer.bo = NULL; - - dri_bo_unreference(mfc_context->macroblock_status_buffer.bo); - mfc_context->macroblock_status_buffer.bo = NULL; - - dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo); - mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL; - - dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo); - mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL; - - - for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){ - dri_bo_unreference(mfc_context->reference_surfaces[i].bo); - mfc_context->reference_surfaces[i].bo = NULL; - } - - i965_gpe_context_destroy(&mfc_context->gpe_context); - - dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo); - mfc_context->mfc_batchbuffer_surface.bo = NULL; - - dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo); - mfc_context->aux_batchbuffer_surface.bo = NULL; - - if (mfc_context->aux_batchbuffer) - intel_batchbuffer_free(mfc_context->aux_batchbuffer); - - mfc_context->aux_batchbuffer = NULL; - - free(mfc_context); -} - Bool gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context) { - struct gen7_mfc_context *mfc_context = calloc(1, sizeof(struct gen7_mfc_context)); + struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context)); mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6; @@ -1843,9 +351,19 @@ gen7_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encode &mfc_context->gpe_context, gen7_mfc_kernels, NUM_MFC_KERNEL); + + mfc_context->pipe_mode_select = gen7_mfc_pipe_mode_select; + mfc_context->set_surface_state = gen7_mfc_surface_state; + mfc_context->ind_obj_base_addr_state = gen7_mfc_ind_obj_base_addr_state; + mfc_context->avc_img_state = gen7_mfc_avc_img_state; + mfc_context->avc_qm_state = gen7_mfc_avc_qm_state; + mfc_context->avc_fqm_state = gen7_mfc_avc_fqm_state; + mfc_context->insert_object = gen7_mfc_avc_insert_object; + mfc_context->buffer_suface_setup = gen7_gpe_buffer_suface_setup; + encoder_context->mfc_context = mfc_context; - encoder_context->mfc_context_destroy = gen7_mfc_context_destroy; - encoder_context->mfc_pipeline = gen7_mfc_pipeline; + encoder_context->mfc_context_destroy = gen6_mfc_context_destroy; + encoder_context->mfc_pipeline = gen6_mfc_pipeline; return True; } diff --git a/src/gen7_mfc.h b/src/gen7_mfc.h deleted file mode 100644 index 9543b88..0000000 --- a/src/gen7_mfc.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Zhou Chang - * Xiang, Haihao - * - */ - -#ifndef _GEN7_MFC_H_ -#define _GEN7_MFC_H_ - -#include -#include -#include - -#include "i965_gpe_utils.h" - -struct encode_state; - -#define MAX_MFC_REFERENCE_SURFACES 16 -#define NUM_MFC_DMV_BUFFERS 34 - -#define __SOFTWARE__ 0 - -struct gen7_mfc_avc_surface_aux -{ - dri_bo *dmv_top; - dri_bo *dmv_bottom; -}; - -struct gen7_mfc_context -{ - struct { - unsigned int width; - unsigned int height; - unsigned int w_pitch; - unsigned int h_pitch; - } surface_state; - - //MFX_PIPE_BUF_ADDR_STATE - struct { - dri_bo *bo; - } post_deblocking_output; //OUTPUT: reconstructed picture - - struct { - dri_bo *bo; - } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked - - struct { - dri_bo *bo; - } uncompressed_picture_source; //INPUT: original compressed image - - struct { - dri_bo *bo; - } intra_row_store_scratch_buffer; //INTERNAL: - - struct { - dri_bo *bo; - } macroblock_status_buffer; //INTERNAL: - - struct { - dri_bo *bo; - } deblocking_filter_row_store_scratch_buffer; //INTERNAL: - - struct { - dri_bo *bo; - } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces - - //MFX_IND_OBJ_BASE_ADDR_STATE - struct{ - dri_bo *bo; - } mfc_indirect_mv_object; //INPUT: the blocks' mv info - - struct { - dri_bo *bo; - int offset; - int end_offset; - } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream - - //MFX_BSP_BUF_BASE_ADDR_STATE - struct { - dri_bo *bo; - } bsd_mpc_row_store_scratch_buffer; //INTERNAL: - - //MFX_AVC_DIRECTMODE_STATE - struct { - dri_bo *bo; - } direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output - - //Bit rate tracking context - struct { - unsigned int QpPrimeY; - unsigned int MaxQpNegModifier; - unsigned int MaxQpPosModifier; - unsigned char MaxSizeInWord; - unsigned char TargetSizeInWord; - unsigned char Correct[6]; - unsigned char GrowInit; - unsigned char GrowResistance; - unsigned char ShrinkInit; - unsigned char ShrinkResistance; - - unsigned int target_mb_size; - unsigned int target_frame_size; - } bit_rate_control_context[2]; //INTERNAL: 0 for intra frames, 1 for inter frames. - - //HRD control context - struct { - int i_bit_rate_value; - int i_cpb_size_value; - - int i_initial_cpb_removal_delay; - int i_cpb_removal_delay; - - int i_frame_number; - - int i_initial_cpb_removal_delay_length; - int i_cpb_removal_delay_length; - int i_dpb_output_delay_length; - }vui_hrd; - - struct i965_gpe_context gpe_context; - struct i965_buffer_surface mfc_batchbuffer_surface; - struct intel_batchbuffer *aux_batchbuffer; - struct i965_buffer_surface aux_batchbuffer_surface; -}; - -#endif /* _GEN7_MFC_BCS_H_ */ -- 2.11.0