From 1b7a9ecfa8d1f37960b57b661cda664a69d82c2e Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Wed, 13 Jun 2018 15:01:07 +0000 Subject: [PATCH] [x86] add test for fadd with more than one use; NFC The equivalent AArch64 test added at rL334556 isn't showing the expected output from the DAGCombiner code change that would fix this example. That's a machine combiner bug from what I see. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334605 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/fadd-combines.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/test/CodeGen/X86/fadd-combines.ll b/test/CodeGen/X86/fadd-combines.ll index ce7ee94e0fb..1f9740da49d 100644 --- a/test/CodeGen/X86/fadd-combines.ll +++ b/test/CodeGen/X86/fadd-combines.ll @@ -221,4 +221,23 @@ define <4 x float> @fadd_fadd_x_x_fadd_x_x_4f32(<4 x float> %x) #0 { ret <4 x float> %z } +; FIXME: +; ((x + 42.0) + 17.0) + (x + 42.0) --> (x + 59.0) + (x + 17.0) +; It's still 3 adds, but the first two are independent. +; More reassocation could get this to 2 adds or 1 FMA (that's done in IR, but not in the DAG). + +define float @fadd_const_multiuse_attr(float %x) #0 { +; CHECK-LABEL: fadd_const_multiuse_attr: +; CHECK: # %bb.0: +; CHECK-NEXT: addss {{.*}}(%rip), %xmm0 +; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero +; CHECK-NEXT: addss %xmm0, %xmm1 +; CHECK-NEXT: addss %xmm1, %xmm0 +; CHECK-NEXT: retq + %a1 = fadd float %x, 42.0 + %a2 = fadd float %a1, 17.0 + %a3 = fadd float %a1, %a2 + ret float %a3 +} + attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "no-signed-zeros-fp-math"="true" } -- 2.11.0