From 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa Mon Sep 17 00:00:00 2001 From: Georg Kotheimer Date: Tue, 13 Oct 2020 19:22:23 +0200 Subject: [PATCH] target/riscv: Fix implementation of HLVX.WU instruction MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The HLVX.WU instruction is supposed to read a machine word, but prior to this change it read a byte instead. Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions") Signed-off-by: Georg Kotheimer Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e987bd262f..4ce73575a7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -333,12 +333,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, riscv_cpu_set_two_stage_lookup(env, true); switch (memop) { - case MO_TEUL: - pte = cpu_ldub_data_ra(env, address, GETPC()); - break; case MO_TEUW: pte = cpu_lduw_data_ra(env, address, GETPC()); break; + case MO_TEUL: + pte = cpu_ldl_data_ra(env, address, GETPC()); + break; default: g_assert_not_reached(); } -- 2.11.0