From 1e2ccf8a3497a64e449fc6db6ccefb8d15470364 Mon Sep 17 00:00:00 2001 From: fche Date: Wed, 4 Aug 2004 15:42:00 +0000 Subject: [PATCH] 2004-08-04 Robert Shideleff * arm7f.cxx (arm7f_cpu): Change nfiq_pin and nirq_pin to normal input pins. Remove handler callbacks. (arm7f_cpu ctor, reset): Initialize them high. (step_insns): Handle their proper level sensitivity. (step_arm, step_thumb, step_arm_pbb, step_thumb_pbb): Remove previous incorrect support. * arm7f.h: Corresponding changes. * hw-cpu-arm7t.xml: Note level sensitivity. * hw-cpu-arm7t.txt: Regenerated. --- sid/component/cgen-cpu/arm7t/ChangeLog | 16 +- sid/component/cgen-cpu/arm7t/arm7f.cxx | 79 ++----- sid/component/cgen-cpu/arm7t/arm7f.h | 7 +- sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.txt | 327 ++++++++++++++------------ sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml | 4 +- 5 files changed, 224 insertions(+), 209 deletions(-) diff --git a/sid/component/cgen-cpu/arm7t/ChangeLog b/sid/component/cgen-cpu/arm7t/ChangeLog index f933f1d7b5..b82fb27274 100644 --- a/sid/component/cgen-cpu/arm7t/ChangeLog +++ b/sid/component/cgen-cpu/arm7t/ChangeLog @@ -1,8 +1,20 @@ +2004-08-04 Robert Shideleff + + * arm7f.cxx (arm7f_cpu): Change nfiq_pin and nirq_pin to normal + input pins. Remove handler callbacks. + (arm7f_cpu ctor, reset): Initialize them high. + (step_insns): Handle their proper level sensitivity. + (step_arm, step_thumb, step_arm_pbb, step_thumb_pbb): Remove + previous incorrect support. + * arm7f.h: Corresponding changes. + * hw-cpu-arm7t.xml: Note level sensitivity. + * hw-cpu-arm7t.txt: Regenerated. + 2003-09-08 Doug Evans - * arm7t/Makefile.am (cgen-arm,cgen-arm7f,cgen-arm7f-arm): Update call + * Makefile.am (cgen-arm,cgen-arm7f,cgen-arm7f-arm): Update call to CGEN.sh. - * arm7t/Makefile.in: Regenerate. + * Makefile.in: Regenerate. 2003-07-05 Doug Evans diff --git a/sid/component/cgen-cpu/arm7t/arm7f.cxx b/sid/component/cgen-cpu/arm7t/arm7f.cxx index d78b50b7c4..9062647215 100644 --- a/sid/component/cgen-cpu/arm7t/arm7f.cxx +++ b/sid/component/cgen-cpu/arm7t/arm7f.cxx @@ -2,6 +2,7 @@ // simulator. -*- C++ -*- // Copyright (C) 1999, 2000 Red Hat. +// Portions Copyright (C) 2004 Sirius Satellite Radio Inc. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. @@ -17,8 +18,6 @@ using namespace arm7f; arm7f_cpu::arm7f_cpu (): arm_engine (32768), // XXX: tune size thumb_engine (32768), // XXX: tune size - nfiq_pin (this, & arm7f_cpu::do_nfiq_pin), - nirq_pin (this, & arm7f_cpu::do_nirq_pin), initialized_p (false) { // ??? One might want to quibble over the case of these pins (nFIQ?). @@ -87,6 +86,10 @@ arm7f_cpu::arm7f_cpu (): // Add register access for debugger this->create_gdb_register_attrs (26, "7;11;13;14;15;25", & this->hardware.h_pc); + + // These need to be 'pulled' high if they are not connected. + nirq_pin.driven(1); + nfiq_pin.driven(1); } string @@ -168,6 +171,10 @@ arm7f_cpu::reset () this->initialized_p = true; this->triggerpoint_manager.check_and_dispatch (); + + // These need to be 'pulled' high if they are not connected. + nirq_pin.driven(1); + nfiq_pin.driven(1); } @@ -182,6 +189,18 @@ arm7f_cpu::step_insns () return; } + // Check for currently asserted interrupt pins. Interrupts are only checked for at each + // step size block of instructions. + if(!this->h_fbit_get() && !nfiq_pin.sense()) + queue_eit (EIT_FIQ); + + if(!this->h_ibit_get() && !nirq_pin.sense()) + queue_eit (EIT_IRQ); + + // If an eit is queued, process it now. + if (this->pending_eit != EIT_NONE) + this->process_eit (this->pending_eit); + if (this->engine_type == ENGINE_PBB) { if (this->h_tbit_get ()) @@ -412,10 +431,6 @@ arm7f_cpu::step_arm () { assert (! this->h_tbit_get ()); - // If an eit is queued, process it now. - if (this->pending_eit != EIT_NONE) - this->process_eit (this->pending_eit); - while (true) { // Fetch/decode the instruction ------------------------------ @@ -482,10 +497,6 @@ arm7f_cpu::step_thumb () { assert (this->h_tbit_get ()); - // If an eit is queued, process it now. - if (this->pending_eit != EIT_NONE) - this->process_eit (this->pending_eit); - while (true) { // Fetch/decode the instruction ------------------------------ @@ -553,10 +564,6 @@ arm7f_cpu::step_arm_pbb () || this->enable_step_trap_p) return this->step_arm (); - // If an eit is queued, process it now. - if (this->pending_eit != EIT_NONE) - this->process_eit (this->pending_eit); - try { // This function takes care of step_insn_count. @@ -583,10 +590,6 @@ arm7f_cpu::step_thumb_pbb () || this->enable_step_trap_p) return this->step_thumb (); - // If an eit is queued, process it now. - if (this->pending_eit != EIT_NONE) - this->process_eit (this->pending_eit); - try { // This function takes care of step_insn_count. @@ -961,46 +964,6 @@ arm7f_cpu::step_reset (host_int_4) // EIT (exception, interrupt, and trap) pins. -void -arm7f_cpu::do_nfiq_pin (host_int_4 value) -{ - // FIXME: Should be able to catch high-low transition but can't do - // that with callback_pin. - //if (nfiq_pin.sense () == value) - // return; - if (value) - return; - - // nFIQ has been driven low. - - // Are FIQ interrupts disabled? - if (this->h_fbit_get ()) - return; - - // Queue the interrupt. - this->queue_eit (EIT_FIQ); -} - -void -arm7f_cpu::do_nirq_pin (host_int_4 value) -{ - // FIXME: Should be able to catch high-low transition but can't do - // that with callback_pin. - //if (nirq_pin.sense () == value) - // return; - if (value) - return; - - // nIRQ has been driven low. - - // Are IRQ interrupts disabled? - if (this->h_ibit_get ()) - return; - - // Queue the interrupt. - this->queue_eit (EIT_IRQ); -} - // Miscellaneous pins. diff --git a/sid/component/cgen-cpu/arm7t/arm7f.h b/sid/component/cgen-cpu/arm7t/arm7f.h index 9ab20f3656..0d6b0f38f2 100644 --- a/sid/component/cgen-cpu/arm7t/arm7f.h +++ b/sid/component/cgen-cpu/arm7t/arm7f.h @@ -1,6 +1,7 @@ // arm7f.h - Main header for the ARM7 CPU family. -*- C++ -*- // Copyright (C) 1999, 2000 Red Hat. +// Portions Copyright (C) 2004 Sirius Satellite Radio Inc. // This file is part of SID and is licensed under the GPL. // See the file COPYING.SID for conditions for redistribution. @@ -158,10 +159,8 @@ private: // FIQ/IRQ are generated by driving these pins (low). // It is synchronous if ISYNC is high, asynchronous if ISYNC is low. // If asynchronous, a cycle delay for synchronization is incurred. - callback_pin nfiq_pin; - void do_nfiq_pin (host_int_4 value); - callback_pin nirq_pin; - void do_nirq_pin (host_int_4 value); + input_pin nfiq_pin; + input_pin nirq_pin; // cpu is reset by driving this pin low #if 0 diff --git a/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.txt b/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.txt index 14410defef..b4ca062947 100644 --- a/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.txt +++ b/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.txt @@ -56,11 +56,15 @@ Functionality: | |from memory via the insn-memory | | |accessor, and its decoding traced if| | |the trace-extract? attribute is set | - | |to a true value. The decoded form | - | |may be cached indefinitely | - | |afterwards, although this cache is | - | |flushed when the flush-icache pin is| - | |driven. | + | |to a true value. To prevent unwanted| + | |cache side effects, the | + | |disassembler-memory accessor can be | + | |used and connected directly to main | + | |memory, bypassing any memory caches.| + | |The decoded form may be cached | + | |indefinitely afterwards, although | + | |this cache is flushed when the | + | |flush-icache pin is driven. | | | | | |The engine-type attribute specifies | | |whether the "scache" ("semantic | @@ -108,7 +112,15 @@ Functionality: | |is used to represent standard | | |output. Trace output files are not | | |appended, but overwritten each time | - | |they are opened. | + | |they are opened. The | + | |print-insn-summary! pin can be | + | |driven to print a summary of | + | |instruction and cycle counts, | + | |usually at the end of the | + | |simulation. The trace pin can be | + | |driven with any value which will be | + | |output as a character into the trace| + | |stream. | |----------------+------------------------------------| |exceptions/traps|When encountering exception/trap | | |conditions such as memory access | @@ -177,7 +189,12 @@ Functionality: | |step! pin is next invoked. Note that| | |this may not be the next instruction| | |if the step-insn-count attribute is | - | |greater than one. | + | |greater than one. Also note that | + | |these pins are level sensitive, so | + | |interrupts will occur repeatedly | + | |until the pin is driven non-zero. | + | |They are 'pulled' to one (high) at | + | |processor invocation and reset. | |----------------+------------------------------------| | register access|All 16 general purpose registers are| | |accessible as attribute r0 through | @@ -215,6 +232,13 @@ Functionality: | |to the target program's address | | |space, and is used by gdb to access | | |target memory. | + | | | + | |The gdb-breakpoint-big and | + | |gdb-breakpoint-little attributes, if| + | |present, are used as memory images | + | |of software breakpoint instructions | + | |for the appropriate run-time | + | |endianness mode. | +-----------------------------------------------------+ +-------------------------------------------------+ @@ -258,42 +282,46 @@ Component Reference: Component: hw-cpu-arm7t - +-----------------------------------------------------------+ - | pins | - |-----------------------------------------------------------| - | name |direction| legalvalues | behaviors | - |-------------+---------+------------------+----------------| - |endian-set! |in |1 (big) / 2 |initialization | - | | |(little) | | - |-------------+---------+------------------+----------------| - |start-pc-set!|in |any value |initialization | - |-------------+---------+------------------+----------------| - |reset! |in |0 or 1 |initialization | - |-------------+---------+------------------+----------------| - |trap |inout |enum values |exceptions/traps| - |-------------+---------+------------------+----------------| - |trap-code |out |various values |exceptions/traps| - |-------------+---------+------------------+----------------| - |step-cycles |out |1..step-insn-count|execution | - |-------------+---------+------------------+----------------| - |step! |in |any value |execution | - |-------------+---------+------------------+----------------| - |yield |in |any |execution | - |-------------+---------+------------------+----------------| - |flush-icache |in |any |execution | - |-------------+---------+------------------+----------------| - |nreset |in |0 or 1 |execution | - |-------------+---------+------------------+----------------| - |nm |out |0 or 1 |register access | - |-------------+---------+------------------+----------------| - |tbit |out |0 or 1 |register access | - |-------------+---------+------------------+----------------| - |nfiq |in |0 or 1 |hardware | - | | | |interrupts | - |-------------+---------+------------------+----------------| - |nirq |in |0 or 1 |hardware | - | | | |interrupts | - +-----------------------------------------------------------+ + +-----------------------------------------------------------------+ + | pins | + |-----------------------------------------------------------------| + | name |direction| legalvalues | behaviors | + |-------------------+---------+------------------+----------------| + |endian-set! |in |1 (big) / 2 |initialization | + | | |(little) | | + |-------------------+---------+------------------+----------------| + |start-pc-set! |in |any value |initialization | + |-------------------+---------+------------------+----------------| + |reset! |in |0 or 1 |initialization | + |-------------------+---------+------------------+----------------| + |trap |inout |enum values |exceptions/traps| + |-------------------+---------+------------------+----------------| + |trap-code |out |various values |exceptions/traps| + |-------------------+---------+------------------+----------------| + |step-cycles |out |1..step-insn-count|execution | + |-------------------+---------+------------------+----------------| + |step! |in |any value |execution | + |-------------------+---------+------------------+----------------| + |yield |in |any |execution | + |-------------------+---------+------------------+----------------| + |flush-icache |in |any |execution | + |-------------------+---------+------------------+----------------| + |print-insn-summary!|in |any |tracing | + |-------------------+---------+------------------+----------------| + |trace |in |any |tracing | + |-------------------+---------+------------------+----------------| + |nreset |in |0 or 1 |execution | + |-------------------+---------+------------------+----------------| + |nm |out |0 or 1 |register access | + |-------------------+---------+------------------+----------------| + |tbit |out |0 or 1 |register access | + |-------------------+---------+------------------+----------------| + |nfiq |in |0 or 1 |hardware | + | | | |interrupts | + |-------------------+---------+------------------+----------------| + |nirq |in |0 or 1 |hardware | + | | | |interrupts | + +-----------------------------------------------------------------+ +-------------------------------------------------+ | buses | @@ -304,111 +332,122 @@ Component Reference: | | | | access | +-------------------------------------------------+ - +---------------------------------------------------------------------------+ - | attributes | - |---------------------------------------------------------------------------| - | name |category | legal values |default| behaviors || - | | | | value | || - |-----------------+---------+----------------------+-------+---------------|| - |endian |register |'1'/'big'/'2'/'little'|big |initialization,|| - | | | | |register access|| - |-----------------+---------+----------------------+-------+---------------|| - |trace-extract? |setting |boolean |false |tracing || - |-----------------+---------+----------------------+-------+---------------|| - |trace-filename |setting |string |- |tracing || - |-----------------+---------+----------------------+-------+---------------|| - |trace-result? |setting |boolean |false |tracing || - |-----------------+---------+----------------------+-------+---------------|| - |engine-type |setting |scache or pbb |pbb |execution || - |-----------------+---------+----------------------+-------+---------------|| - |insn-count |watchable|number |- |execution || - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |step-insn-count |setting |number |1 |execution || - |-----------------+---------+----------------------+-------+---------------|| - |enable-step-trap?|setting |boolean |false |execution || - |-----------------+---------+----------------------+-------+---------------|| - |rN |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |pc |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |gdb-register-N |debugger |byte array |- |register access|| - |-----------------+---------+----------------------+-------+---------------|| - |gdb-num-registers|debugger |number |- |register access|| - |-----------------+---------+----------------------+-------+---------------|| - |gdb-exp-registers|debugger |number list |- |register access|| - |-----------------+---------+----------------------+-------+---------------|| - |state-snapshot |- |opaque string |- |state || - | | | | |save/restore || - |-----------------+---------+----------------------+-------+---------------|| - |step-cycles |watchable|number |- |execution || - | |pin | | | || - |-----------------+---------+----------------------+-------+---------------|| - |trap |watchable|number |- |execution/traps|| - | |pin | | | || - |-----------------+---------+----------------------+-------+---------------|| - |trap-code |watchable|number |- |execution/traps|| - | |pin | | | || - |-----------------+---------+----------------------+-------+---------------|| - |cpsr |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |cpsr-flags |register |string |- |register access|| - |-----------------+---------+----------------------+-------+---------------|| - |nm |watchable|number |- |register access|| - | |pin | | | || - |-----------------+---------+----------------------+-------+---------------|| - |tbit |watchable|number |- |register access|| - | |pin | | | || - |-----------------+---------+----------------------+-------+---------------|| - |nfiq |watchable|number |- |hardware || - | |pin | | |interrupts || - |-----------------+---------+----------------------+-------+---------------|| - |nirq |watchable|number |- |hardware || - | |pin | | |interrupts || - |-----------------+---------+----------------------+-------+---------------|| - |rN_fiq |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |rN_svc |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |rN_abt |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |rN_irq |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |rN_und |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |spsr_fiq |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |spsr_svc |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |spsr_abt |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |spsr_irq |watchable|number |- |register access|| - | |register | | | || - |-----------------+---------+----------------------+-------+---------------|| - |spsr_und |watchable|number |- |register access|| - | |register | | | || - +---------------------------------------------------------------------------+ ++-------------------------------------------------------------------------------+ +| attributes | +|-------------------------------------------------------------------------------| +| name |category | legal values |default| behaviors || +| | | | value | || +|---------------------+---------+----------------------+-------+---------------|| +|endian |register |'1'/'big'/'2'/'little'|big |initialization,|| +| | | | |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|trace-extract? |setting |boolean |false |tracing || +|---------------------+---------+----------------------+-------+---------------|| +|trace-filename |setting |string |- |tracing || +|---------------------+---------+----------------------+-------+---------------|| +|trace-result? |setting |boolean |false |tracing || +|---------------------+---------+----------------------+-------+---------------|| +|trace-counter? |setting |boolean |false |tracing || +|---------------------+---------+----------------------+-------+---------------|| +|final-insn-count? |setting |boolean |false |tracing || +|---------------------+---------+----------------------+-------+---------------|| +|engine-type |setting |scache or pbb |pbb |execution || +|---------------------+---------+----------------------+-------+---------------|| +|insn-count |watchable|number |- |execution || +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|step-insn-count |setting |number |1 |execution || +|---------------------+---------+----------------------+-------+---------------|| +|enable-step-trap? |setting |boolean |false |execution || +|---------------------+---------+----------------------+-------+---------------|| +|rN |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|pc |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|gdb-register-N |debugger |byte array |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|gdb-num-registers |debugger |number |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|gdb-exp-registers |debugger |number list |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|gdb-breakpoint-big |debugger |byte array |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|gdb-breakpoint-little|debugger |byte array |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|state-snapshot |- |opaque string |- |state || +| | | | |save/restore || +|---------------------+---------+----------------------+-------+---------------|| +|step-cycles |watchable|number |- |execution || +| |pin | | | || +|---------------------+---------+----------------------+-------+---------------|| +|trap |watchable|number |- |execution/traps|| +| |pin | | | || +|---------------------+---------+----------------------+-------+---------------|| +|trap-code |watchable|number |- |execution/traps|| +| |pin | | | || +|---------------------+---------+----------------------+-------+---------------|| +|cpsr |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|cpsr-flags |register |string |- |register access|| +|---------------------+---------+----------------------+-------+---------------|| +|nm |watchable|number |- |register access|| +| |pin | | | || +|---------------------+---------+----------------------+-------+---------------|| +|tbit |watchable|number |- |register access|| +| |pin | | | || +|---------------------+---------+----------------------+-------+---------------|| +|nfiq |watchable|number |- |hardware || +| |pin | | |interrupts || +|---------------------+---------+----------------------+-------+---------------|| +|nirq |watchable|number |- |hardware || +| |pin | | |interrupts || +|---------------------+---------+----------------------+-------+---------------|| +|rN_fiq |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|rN_svc |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|rN_abt |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|rN_irq |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|rN_und |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|spsr_fiq |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|spsr_svc |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|spsr_abt |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|spsr_irq |watchable|number |- |register access|| +| |register | | | || +|---------------------+---------+----------------------+-------+---------------|| +|spsr_und |watchable|number |- |register access|| +| |register | | | || ++-------------------------------------------------------------------------------+ +-------------------------------------------------+ | accessors | |-------------------------------------------------| - | name | accesses | behaviors | - |-------------+-----------------------+-----------| - | data-memory | any | execution | - |-------------+-----------------------+-----------| - | insn-memory | typically 4-byte | execution | - | | accesses | | + | name | accesses | behaviors | + |---------------------+---------------+-----------| + | data-memory | any | execution | + |---------------------+---------------+-----------| + | | typically | | + | insn-memory | 4-byte | execution | + | | accesses | | + |---------------------+---------------+-----------| + | disassembler-memory | any | execution | +-------------------------------------------------+ ---------------------------------------------------------------------- diff --git a/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml b/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml index bd2c065cad..20be797df9 100644 --- a/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml +++ b/sid/component/cgen-cpu/arm7t/hw-cpu-arm7t.xml @@ -56,7 +56,9 @@ step! pin is next invoked. Note that this may not be the next instruction if the step-insn-count attribute is greater than - one.

+ one. Also note that these pins are level sensitive, so interrupts + will occur repeatedly until the pin is driven non-zero. They are + 'pulled' to one (high) at processor invocation and reset.

-- 2.11.0