From 1e4cb86baca254719f0c21785b6aca58815e9d45 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 12 Apr 2018 20:47:34 +0000 Subject: [PATCH] [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329953 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86InstrAVX512.td | 181 ++++++++++------------ lib/Target/X86/X86InstrFormats.td | 310 +++++++++++++++++++------------------- lib/Target/X86/X86InstrSSE.td | 111 +++++++------- 3 files changed, 284 insertions(+), 318 deletions(-) diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index af03c3fc0ce..532b5a2cbf4 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -212,7 +212,6 @@ multiclass AVX512_maskable_custom O, Format F, list Pattern, list MaskingPattern, list ZeroMaskingPattern, - InstrItinClass itin = NoItinerary, string MaskingConstraint = "", bit IsCommutable = 0, bit IsKCommutable = 0> { @@ -220,14 +219,14 @@ multiclass AVX512_maskable_custom O, Format F, def NAME: AVX512; + Pattern>; // Prefer over VMOV*rrk Pat<> let isCommutable = IsKCommutable in def NAME#k: AVX512, + MaskingPattern>, EVEX_K { // In case of the 3src subclass this is overridden with a let. string Constraints = MaskingConstraint; @@ -239,8 +238,7 @@ multiclass AVX512_maskable_custom O, Format F, def NAME#kz: AVX512, + ZeroMaskingPattern>, EVEX_KZ; } @@ -252,7 +250,6 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, dag MaskingRHS, - InstrItinClass itin = NoItinerary, SDNode Select = vselect, string MaskingConstraint = "", bit IsCommutable = 0, @@ -263,7 +260,7 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, [(set _.RC:$dst, MaskingRHS)], [(set _.RC:$dst, (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))], - itin, MaskingConstraint, IsCommutable, + MaskingConstraint, IsCommutable, IsKCommutable>; // This multiclass generates the unconditional/non-masking, the masking and @@ -274,7 +271,6 @@ multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, dag MaskRHS, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0, bit IsKCommutable = 0, SDNode Select = vselect> : AVX512_maskable_custom O, Format F, X86VectorVTInfo _, (Select _.KRCWM:$mask, MaskRHS, _.RC:$src0))], [(set _.RC:$dst, (Select _.KRCWM:$mask, MaskRHS, _.ImmAllZerosV))], - itin, "$src0 = $dst", IsCommutable, IsKCommutable>; + "$src0 = $dst", IsCommutable, IsKCommutable>; // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the @@ -295,14 +291,13 @@ multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0, bit IsKCommutable = 0, SDNode Select = vselect> : AVX512_maskable_common; // This multiclass generates the unconditional/non-masking, the masking and @@ -311,10 +306,9 @@ multiclass AVX512_maskable_scalar O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0> : AVX512_maskable; + RHS, IsCommutable, 0, X86selects>; // Similar to AVX512_maskable but in this case one of the source operands // ($src1) is already tied to $dst so we just use that for the preserved @@ -323,7 +317,7 @@ multiclass AVX512_maskable_scalar O, Format F, X86VectorVTInfo _, multiclass AVX512_maskable_3src O, Format F, X86VectorVTInfo _, dag Outs, dag NonTiedIns, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, InstrItinClass itin = NoItinerary, + dag RHS, bit IsCommutable = 0, bit IsKCommutable = 0, SDNode Select = vselect, @@ -334,31 +328,30 @@ multiclass AVX512_maskable_3src O, Format F, X86VectorVTInfo _, !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns), OpcodeStr, AttSrcAsm, IntelSrcAsm, !if(MaskOnly, (null_frag), RHS), - (Select _.KRCWM:$mask, RHS, _.RC:$src1), itin, + (Select _.KRCWM:$mask, RHS, _.RC:$src1), Select, "", IsCommutable, IsKCommutable>; multiclass AVX512_maskable_3src_scalar O, Format F, X86VectorVTInfo _, dag Outs, dag NonTiedIns, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, InstrItinClass itin = NoItinerary, + dag RHS, bit IsCommutable = 0, bit IsKCommutable = 0, bit MaskOnly = 0> : AVX512_maskable_3src; multiclass AVX512_maskable_in_asm O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - list Pattern, - InstrItinClass itin = NoItinerary> : + list Pattern> : AVX512_maskable_custom; + "$src0 = $dst">; // Instruction with mask that puts result in mask register, @@ -370,18 +363,17 @@ multiclass AVX512_maskable_custom_cmp O, Format F, string AttSrcAsm, string IntelSrcAsm, list Pattern, list MaskingPattern, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0> { let isCommutable = IsCommutable in def NAME: AVX512; + Pattern>; def NAME#k: AVX512, EVEX_K; + MaskingPattern>, EVEX_K; } multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, @@ -390,30 +382,27 @@ multiclass AVX512_maskable_common_cmp O, Format F, X86VectorVTInfo _, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, dag MaskingRHS, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0> : AVX512_maskable_custom_cmp; + [(set _.KRC:$dst, MaskingRHS)], IsCommutable>; multiclass AVX512_maskable_cmp O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, - dag RHS, InstrItinClass itin = NoItinerary, - bit IsCommutable = 0> : + dag RHS, bit IsCommutable = 0> : AVX512_maskable_common_cmp; + (and _.KRCWM:$mask, RHS), IsCommutable>; multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, - string AttSrcAsm, string IntelSrcAsm, - InstrItinClass itin = NoItinerary> : + string AttSrcAsm, string IntelSrcAsm> : AVX512_maskable_custom_cmp; + AttSrcAsm, IntelSrcAsm, [], []>; // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the @@ -422,7 +411,6 @@ multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, dag RHS, dag MaskedRHS, - InstrItinClass itin = NoItinerary, bit IsCommutable = 0, SDNode Select = vselect> : AVX512_maskable_custom O, Format F, X86VectorVTInfo _, [(set _.RC:$dst, (Select _.KRCWM:$mask, MaskedRHS, _.ImmAllZerosV))], - itin, "$src0 = $dst", IsCommutable>; + "$src0 = $dst", IsCommutable>; // Alias instruction that maps zero vector to pxor / xorp* for AVX-512. @@ -807,8 +795,8 @@ multiclass vextract_for_size_split, AVX512AIi8Base, EVEX, Sched<[SchedRR]>; + (vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm))>, + AVX512AIi8Base, EVEX, Sched<[SchedRR]>; def mr : AVX512AIi8, EVEX, + addr:$dst)]>, EVEX, Sched<[SchedMR]>; let mayStore = 1, hasSideEffects = 0 in @@ -825,9 +813,8 @@ multiclass vextract_for_size_split, EVEX_K, EVEX, - Sched<[SchedMR]>; + "$dst {${mask}}, $src1, $idx}", []>, + EVEX_K, EVEX, Sched<[SchedMR]>; } } @@ -1157,8 +1144,8 @@ multiclass avx512_broadcast_rm_split opc, string OpcodeStr, (MaskInfo.VT (bitconvert (DestInfo.VT - (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))))), - NoItinerary>, T8PD, EVEX, Sched<[SchedRR]>; + (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))))>, + T8PD, EVEX, Sched<[SchedRR]>; let mayLoad = 1 in defm m : AVX512_maskable_split opc, string OpcodeStr, (MaskInfo.VT (bitconvert (DestInfo.VT (X86VBroadcast - (SrcInfo.ScalarLdFrag addr:$src))))), - NoItinerary>, T8PD, EVEX, EVEX_CD8, + (SrcInfo.ScalarLdFrag addr:$src)))))>, + T8PD, EVEX, EVEX_CD8, Sched<[SchedRM]>; } @@ -1263,7 +1250,7 @@ multiclass avx512_int_broadcast_reg opc, SchedWrite SchedRR, defm r : AVX512_maskable, T8PD, EVEX, + (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX, Sched<[SchedRR]>; } @@ -1276,7 +1263,7 @@ multiclass avx512_int_broadcastbw_reg opc, string Name, SchedWrite Sched !con((ins _.RC:$src0, _.KRCWM:$mask), (ins GR32:$src)), !con((ins _.KRCWM:$mask), (ins GR32:$src)), "vpbroadcast"##_.Suffix, "$src", "$src", [], [], [], - NoItinerary, "$src0 = $dst">, T8PD, EVEX, Sched<[SchedRR]>; + "$src0 = $dst">, T8PD, EVEX, Sched<[SchedRR]>; def : Pat <(_.VT (OpNode SrcRC:$src)), (!cast(Name#r) @@ -1373,9 +1360,8 @@ multiclass avx512_subvec_broadcast_rm opc, string OpcodeStr, defm rm : AVX512_maskable, AVX5128IBase, EVEX, - Sched<[WriteShuffleLd]>; + (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>, + AVX5128IBase, EVEX, Sched<[WriteShuffleLd]>; } // This should be used for the AVX512DQ broadcast instructions. It disables @@ -1388,9 +1374,8 @@ multiclass avx512_subvec_broadcast_rm_dq opc, string OpcodeStr, (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src", (null_frag), (_Dst.VT (X86SubVBroadcast - (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))), - NoItinerary>, AVX5128IBase, EVEX, - Sched<[WriteShuffleLd]>; + (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>, + AVX5128IBase, EVEX, Sched<[WriteShuffleLd]>; } let Predicates = [HasAVX512] in { @@ -1746,14 +1731,14 @@ let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { defm rr: AVX512_maskable_3src, EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; + (_.VT (X86VPermi2X _.RC:$src1, _.RC:$src2, _.RC:$src3)), 1>, + EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; defm rm: AVX512_maskable_3src, + (_.VT (bitconvert (_.LdFrag addr:$src3))))), 1>, EVEX_4V, AVX5128IBase, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -1766,8 +1751,8 @@ multiclass avx512_perm_i_mb opc, string OpcodeStr, OpndItins itins, OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ), (_.VT (X86VPermi2X _.RC:$src1, - _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), - NoItinerary, 1>, AVX5128IBase, EVEX_4V, EVEX_B, + _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), 1>, + AVX5128IBase, EVEX_4V, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } @@ -1817,14 +1802,14 @@ let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { defm rr: AVX512_maskable_3src, EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; + (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3)), 1>, + EVEX_4V, AVX5128IBase, Sched<[itins.Sched]>; defm rm: AVX512_maskable_3src, + (bitconvert (_.LdFrag addr:$src3)))), 1>, EVEX_4V, AVX5128IBase, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -1836,8 +1821,8 @@ multiclass avx512_perm_t_mb opc, string OpcodeStr, OpndItins itins, OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ), (_.VT (X86VPermt2 _.RC:$src1, - IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), - NoItinerary, 1>, AVX5128IBase, EVEX_4V, EVEX_B, + IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))), 1>, + AVX5128IBase, EVEX_4V, EVEX_B, Sched<[itins.Sched.Folded, ReadAfterLd]>; } @@ -2439,7 +2424,7 @@ multiclass avx512_vcmp_common { "$src2, $src1", "$src1, $src2", (X86cmpm (_.VT _.RC:$src1), (_.VT _.RC:$src2), - imm:$cc), NoItinerary, 1>, + imm:$cc), 1>, Sched<[itins.Sched]>; defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _, @@ -4340,7 +4325,7 @@ multiclass avx512_binop_rm opc, string OpcodeStr, SDNode OpNode, (ins _.RC:$src1, _.RC:$src2), OpcodeStr, "$src2, $src1", "$src1, $src2", (_.VT (OpNode _.RC:$src1, _.RC:$src2)), - NoItinerary, IsCommutable>, AVX512BIBase, EVEX_4V, + IsCommutable>, AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable opc, string OpcodeStr, OpndItins itins, (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (_Src.VT _Src.RC:$src2))), - NoItinerary, IsCommutable>, + IsCommutable>, AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable opc, string OpcodeStr, (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (_Src.VT _Src.RC:$src2))), - NoItinerary, IsCommutable>, + IsCommutable>, EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V, Sched<[itins.Sched]>; defm rm : AVX512_maskable opc, string OpcodeStr, (bitconvert (_.VT _.RC:$src2)))), (_.VT (bitconvert (_.i64VT (OpNodeMsk _.RC:$src1, _.RC:$src2)))), - NoItinerary, IsCommutable>, AVX512BIBase, EVEX_4V, + IsCommutable>, AVX512BIBase, EVEX_4V, Sched<[itins.Sched]>; let hasSideEffects = 0, mayLoad = 1 in @@ -4857,7 +4842,7 @@ multiclass avx512_fp_scalar_round opc, string OpcodeStr,X86VectorVTInfo (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr, "$rc, $src2, $src1", "$src1, $src2, $rc", (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), - (i32 imm:$rc)), NoItinerary, IsCommutable>, + (i32 imm:$rc)), IsCommutable>, EVEX_B, EVEX_RC, Sched<[itins.Sched]>; } multiclass avx512_fp_scalar_sae opc, string OpcodeStr,X86VectorVTInfo _, @@ -4979,8 +4964,8 @@ multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpN defm rr: AVX512_maskable, EVEX_4V, Sched<[itins.Sched]>; + (_.VT (OpNode _.RC:$src1, _.RC:$src2)), IsCommutable>, + EVEX_4V, Sched<[itins.Sched]>; let mayLoad = 1 in { defm rm: AVX512_maskable opc, string OpcodeStr, SDNode OpNode, defm r: AVX512_maskable_3src, + (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)), 1, 1>, AVX512FMA3Base, Sched<[WriteFMA]>; defm m: AVX512_maskable_3src, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; + (_.VT (OpNode _.RC:$src2, _.RC:$src1, (_.LdFrag addr:$src3))), 1, 0>, + AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; defm mb: AVX512_maskable_3src, AVX512FMA3Base, EVEX_B, - Sched<[WriteFMALd, ReadAfterLd]>; + _.RC:$src1,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))), 1, 0>, + AVX512FMA3Base, EVEX_B, Sched<[WriteFMALd, ReadAfterLd]>; } } @@ -6187,8 +6171,8 @@ multiclass avx512_fma3_213_round opc, string OpcodeStr, SDNode OpNode, defm rb: AVX512_maskable_3src, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[WriteFMA]>; + (_.VT ( OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 imm:$rc))), 1, 1>, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[WriteFMA]>; } multiclass avx512_fma3p_213_common opc, string OpcodeStr, SDNode OpNode, @@ -6229,14 +6213,14 @@ multiclass avx512_fma3p_231_rm opc, string OpcodeStr, SDNode OpNode, defm r: AVX512_maskable_3src, AVX512FMA3Base, Sched<[WriteFMA]>; defm m: AVX512_maskable_3src, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; + (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1)), 1, 0>, + AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; defm mb: AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, "$src2, ${src3}"##_.BroadcastStr, (_.VT (OpNode _.RC:$src2, (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))), - _.RC:$src1)), NoItinerary, 1, 0>, AVX512FMA3Base, EVEX_B, + _.RC:$src1)), 1, 0>, AVX512FMA3Base, EVEX_B, Sched<[WriteFMALd, ReadAfterLd]>; } } @@ -6256,7 +6240,7 @@ multiclass avx512_fma3_231_round opc, string OpcodeStr, SDNode OpNode, (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc), OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc))), - NoItinerary, 1, 1, vselect, 1>, + 1, 1, vselect, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[WriteFMA]>; } @@ -6297,16 +6281,16 @@ multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, defm r: AVX512_maskable_3src, AVX512FMA3Base, Sched<[WriteFMA]>; + (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)), 1, 1, vselect, 1>, + AVX512FMA3Base, Sched<[WriteFMA]>; // Pattern is 312 order so that the load is in a different place from the // 213 and 231 patterns this helps tablegen's duplicate pattern detection. defm m: AVX512_maskable_3src, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; + (_.VT (OpNode (_.LdFrag addr:$src3), _.RC:$src1, _.RC:$src2)), 1, 0>, + AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; // Pattern is 312 order so that the load is in a different place from the // 213 and 231 patterns this helps tablegen's duplicate pattern detection. @@ -6315,7 +6299,7 @@ multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, OpcodeStr, "${src3}"##_.BroadcastStr##", $src2", "$src2, ${src3}"##_.BroadcastStr, (_.VT (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))), - _.RC:$src1, _.RC:$src2)), NoItinerary, 1, 0>, + _.RC:$src1, _.RC:$src2)), 1, 0>, AVX512FMA3Base, EVEX_B, Sched<[WriteFMALd, ReadAfterLd]>; } } @@ -6327,7 +6311,7 @@ multiclass avx512_fma3_132_round opc, string OpcodeStr, SDNode OpNode, (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc), OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (_.VT ( OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 imm:$rc))), - NoItinerary, 1, 1, vselect, 1>, + 1, 1, vselect, 1>, AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[WriteFMA]>; } @@ -6369,19 +6353,18 @@ multiclass avx512_fma3s_common opc, string OpcodeStr, X86VectorVTInfo _, let Constraints = "$src1 = $dst", hasSideEffects = 0 in { defm r_Int: AVX512_maskable_3src_scalar, + "$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>, AVX512FMA3Base, Sched<[WriteFMA]>; defm m_Int: AVX512_maskable_3src_scalar, + "$src3, $src2", "$src2, $src3", RHS_VEC_m, 1, 1>, AVX512FMA3Base, Sched<[WriteFMALd, ReadAfterLd]>; defm rb_Int: AVX512_maskable_3src_scalar, AVX512FMA3Base, EVEX_B, EVEX_RC, - Sched<[WriteFMA]>; + OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1>, + AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[WriteFMA]>; let isCodeGenOnly = 1, isCommutable = 1 in { def r : AVX512FMA3S opc, string OpcodeStr, SDNode OpNode, defm r: AVX512_maskable_3src, + (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)), 1, 1>, AVX512FMA3Base, Sched<[itins.Sched]>; defm m: AVX512_maskable_3src, AVX512AIi8Base, Sched<[itins.Sched]>; + (i32 imm:$src2)), 0, 0>, + AVX512AIi8Base, Sched<[itins.Sched]>; let hasSideEffects = 0, mayStore = 1 in { def mr : AVX512AIi8<0x1D, MRMDestMem, (outs), (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2), @@ -10201,7 +10184,7 @@ multiclass avx512_ternlog opc, string OpcodeStr, SDNode OpNode, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT _.RC:$src3), - (i8 imm:$src4)), NoItinerary, 1, 1>, + (i8 imm:$src4)), 1, 1>, AVX512AIi8Base, EVEX_4V, Sched<[itins.Sched]>; defm rmi : AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT (bitconvert (_.LdFrag addr:$src3))), - (i8 imm:$src4)), NoItinerary, 1, 0>, + (i8 imm:$src4)), 1, 0>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, Sched<[itins.Sched.Folded, ReadAfterLd]>; defm rmbi : AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))), - (i8 imm:$src4)), NoItinerary, 1, 0>, EVEX_B, + (i8 imm:$src4)), 1, 0>, EVEX_B, AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>, Sched<[itins.Sched.Folded, ReadAfterLd]>; }// Constraints = "$src1 = $dst" diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index eb52275f758..56d9f0229e4 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -244,9 +244,7 @@ class FoldGenData { class NotMemoryFoldable { bit isMemoryFoldable = 0; } class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, - string AsmStr, - InstrItinClass itin, - Domain d = GenericDomain> + string AsmStr, Domain d = GenericDomain> : Instruction { let Namespace = "X86"; @@ -262,7 +260,7 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, // If this is a pseudo instruction, mark it isCodeGenOnly. let isCodeGenOnly = !eq(!cast(f), "Pseudo"); - let Itinerary = itin; + let Itinerary = NoItinerary; // // Attributes specific to X86 instructions... @@ -357,75 +355,71 @@ class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, let TSFlags{53} = hasNoTrackPrefix; } -class PseudoI pattern, - InstrItinClass itin = NoItinerary> - : X86Inst<0, Pseudo, NoImm, oops, iops, "", itin> { +class PseudoI pattern> + : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { let Pattern = pattern; } class I o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary, - Domain d = GenericDomain> - : X86Inst { + list pattern, Domain d = GenericDomain> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } -class Ii8 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary, - Domain d = GenericDomain> - : X86Inst { +class Ii8 o, Format f, dag outs, dag ins, string asm, + list pattern, Domain d = GenericDomain> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii8Reg o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary, - Domain d = GenericDomain> - : X86Inst { + list pattern, Domain d = GenericDomain> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii8PCRel o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii16 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii32 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii32S o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii64 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii16PCRel o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Ii32PCRel o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } @@ -448,24 +442,23 @@ class FpI_ pattern> // Iseg32 - 16-bit segment selector, 32-bit offset class Iseg16 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } class Iseg32 o, Format f, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : X86Inst { + list pattern> + : X86Inst { let Pattern = pattern; let CodeSize = 3; } // SI - SSE 1 & 2 scalar instructions class SI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary, - Domain d = GenericDomain> - : I { + list pattern, Domain d = GenericDomain> + : I { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], @@ -481,9 +474,8 @@ class SI o, Format F, dag outs, dag ins, string asm, // SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 class SI_Int o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary, - Domain d = GenericDomain> - : I { + list pattern, Domain d = GenericDomain> + : I { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], @@ -498,8 +490,8 @@ class SI_Int o, Format F, dag outs, dag ins, string asm, } // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 class SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8 { + list pattern> + : Ii8 { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], @@ -513,8 +505,8 @@ class SIi8 o, Format F, dag outs, dag ins, string asm, // PI - SSE 1 & 2 packed instructions class PI o, Format F, dag outs, dag ins, string asm, list pattern, - InstrItinClass itin, Domain d> - : I { + Domain d> + : I { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], @@ -529,15 +521,15 @@ class PI o, Format F, dag outs, dag ins, string asm, list pattern, // MMXPI - SSE 1 & 2 packed instructions with MMX operands class MMXPI o, Format F, dag outs, dag ins, string asm, list pattern, Domain d> - : I { + : I { let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2], [HasSSE1]); } // PIi8 - SSE 1 & 2 packed instructions with immediate class PIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin, Domain d> - : Ii8 { + list pattern, Domain d> + : Ii8 { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], @@ -558,26 +550,26 @@ class PIi8 o, Format F, dag outs, dag ins, string asm, // VPSI - SSE1 instructions with PS prefix in AVX form, packed single. class SSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, Requires<[UseSSE1]>; + list pattern> + : I, XS, Requires<[UseSSE1]>; class SSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, XS, Requires<[UseSSE1]>; + list pattern> + : Ii8, XS, Requires<[UseSSE1]>; class PSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PS, + list pattern> + : I, PS, Requires<[UseSSE1]>; class PSIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, PS, + list pattern> + : Ii8, PS, Requires<[UseSSE1]>; class VSSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, + list pattern> + : I, XS, Requires<[HasAVX]>; class VPSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PS, + list pattern> + : I, PS, Requires<[HasAVX]>; // SSE2 Instruction Templates: @@ -599,44 +591,44 @@ class VPSI o, Format F, dag outs, dag ins, string asm, // MMX operands. class SDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XD, Requires<[UseSSE2]>; + list pattern> + : I, XD, Requires<[UseSSE2]>; class SDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, XD, Requires<[UseSSE2]>; + list pattern> + : Ii8, XD, Requires<[UseSSE2]>; class S2SI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, Requires<[UseSSE2]>; + list pattern> + : I, XS, Requires<[UseSSE2]>; class S2SIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> + list pattern> : Ii8, XS, Requires<[UseSSE2]>; class PDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, + list pattern> + : I, PD, Requires<[UseSSE2]>; class PDIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, PD, + list pattern> + : Ii8, PD, Requires<[UseSSE2]>; class VSDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XD, + list pattern> + : I, XD, Requires<[UseAVX]>; class VS2SI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, + list pattern> + : I, XS, Requires<[HasAVX]>; class VPDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, + list pattern> + : I, PD, Requires<[HasAVX]>; class VS2I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, + list pattern> + : I, PD, Requires<[UseAVX]>; class S2I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, Requires<[UseSSE2]>; + list pattern> + : I, PD, Requires<[UseSSE2]>; class MMXSDIi8 o, Format F, dag outs, dag ins, string asm, list pattern> : Ii8, XD, Requires<[HasSSE2]>; @@ -651,16 +643,16 @@ class MMXS2SIi8 o, Format F, dag outs, dag ins, string asm, // S3DI - SSE3 instructions with XD prefix. class S3SI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, + list pattern> + : I, XS, Requires<[UseSSE3]>; class S3DI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XD, + list pattern> + : I, XD, Requires<[UseSSE3]>; class S3I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, + list pattern> + : I, PD, Requires<[UseSSE3]>; @@ -676,20 +668,20 @@ class S3I o, Format F, dag outs, dag ins, string asm, // classes. They need to be enabled even if AVX is enabled. class SS38I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[UseSSSE3]>; class SS3AI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TAPD, + list pattern> + : Ii8, TAPD, Requires<[UseSSSE3]>; class MMXSS38I o, Format F, dag outs, dag ins, string asm, list pattern> - : I, T8PS, + : I, T8PS, Requires<[HasSSSE3]>; class MMXSS3AI o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, TAPS, + : Ii8, TAPS, Requires<[HasSSSE3]>; // SSE4.1 Instruction Templates: @@ -698,20 +690,20 @@ class MMXSS3AI o, Format F, dag outs, dag ins, string asm, // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. // class SS48I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[UseSSE41]>; class SS4AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TAPD, + list pattern> + : Ii8, TAPD, Requires<[UseSSE41]>; // SSE4.2 Instruction Templates: // // SS428I - SSE 4.2 instructions with T8 prefix. class SS428I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[UseSSE42]>; // SS42FI - SSE 4.2 instructions with T8XD prefix. @@ -723,7 +715,7 @@ class SS42FI o, Format F, dag outs, dag ins, string asm, // SS42AI = SSE 4.2 instructions with TA prefix class SS42AI o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, TAPD, + : Ii8, TAPD, Requires<[UseSSE42]>; // AVX Instruction Templates: @@ -732,12 +724,12 @@ class SS42AI o, Format F, dag outs, dag ins, string asm, // AVX8I - AVX instructions with T8PD prefix. // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. class AVX8I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[HasAVX]>; class AVXAIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TAPD, + list pattern> + : Ii8, TAPD, Requires<[HasAVX]>; // AVX2 Instruction Templates: @@ -746,12 +738,12 @@ class AVXAIi8 o, Format F, dag outs, dag ins, string asm, // AVX28I - AVX2 instructions with T8PD prefix. // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. class AVX28I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[HasAVX2]>; class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TAPD, + list pattern> + : Ii8, TAPD, Requires<[HasAVX2]>; @@ -768,34 +760,34 @@ class AVX2AIi8 o, Format F, dag outs, dag ins, string asm, // AVX512SI - AVX-512 scalar instructions with PD prefix. class AVX5128I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + list pattern> + : I, T8PD, Requires<[HasAVX512]>; class AVX5128IBase : T8PD { Domain ExeDomain = SSEPackedInt; } class AVX512XS8I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, T8XS, + list pattern> + : I, T8XS, Requires<[HasAVX512]>; class AVX512XSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XS, + list pattern> + : I, XS, Requires<[HasAVX512]>; class AVX512XDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, XD, + list pattern> + : I, XD, Requires<[HasAVX512]>; class AVX512BI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, + list pattern> + : I, PD, Requires<[HasAVX512]>; class AVX512BIBase : PD { Domain ExeDomain = SSEPackedInt; } class AVX512BIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, PD, + list pattern> + : Ii8, PD, Requires<[HasAVX512]>; class AVX512BIi8Base : PD { Domain ExeDomain = SSEPackedInt; @@ -818,39 +810,39 @@ class AVX512PDIi8Base : PD { ImmType ImmT = Imm8; } class AVX512AIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, TAPD, + list pattern> + : Ii8, TAPD, Requires<[HasAVX512]>; class AVX512AIi8Base : TAPD { ImmType ImmT = Imm8; } class AVX512Ii8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, + list pattern> + : Ii8, Requires<[HasAVX512]>; class AVX512PDI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PD, + list pattern> + : I, PD, Requires<[HasAVX512]>; class AVX512PSI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, PS, + list pattern> + : I, PS, Requires<[HasAVX512]>; class AVX512PIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d, InstrItinClass itin = NoItinerary> - : Ii8, Requires<[HasAVX512]>; + list pattern, Domain d> + : Ii8, Requires<[HasAVX512]>; class AVX512PI o, Format F, dag outs, dag ins, string asm, - list pattern, Domain d, InstrItinClass itin = NoItinerary> - : I, Requires<[HasAVX512]>; + list pattern, Domain d> + : I, Requires<[HasAVX512]>; class AVX512FMA3S o, Format F, dag outs, dag ins, string asm, - listpattern, InstrItinClass itin = NoItinerary> - : I, T8PD, + listpattern> + : I, T8PD, EVEX_4V, Requires<[HasAVX512]>; class AVX512FMA3Base : T8PD, EVEX_4V; class AVX512 o, Format F, dag outs, dag ins, string asm, - listpattern, InstrItinClass itin = NoItinerary> - : I, Requires<[HasAVX512]>; + listpattern> + : I, Requires<[HasAVX512]>; // AES Instruction Templates: // @@ -858,18 +850,18 @@ class AVX512 o, Format F, dag outs, dag ins, string asm, // These use the same encoding as the SSE4.2 T8 and TA encodings. class AES8I o, Format F, dag outs, dag ins, string asm, listpattern> - : I, T8PD, + : I, T8PD, Requires<[NoAVX, HasAES]>; class AESAI o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, TAPD, + : Ii8, TAPD, Requires<[NoAVX, HasAES]>; // PCLMUL Instruction Templates class PCLMULIi8 o, Format F, dag outs, dag ins, string asm, listpattern> - : Ii8, TAPD; + : Ii8, TAPD; // FMA3 Instruction Templates class FMA3 o, Format F, dag outs, dag ins, string asm, @@ -902,54 +894,54 @@ class FMA4S_Int o, Format F, dag outs, dag ins, string asm, // XOP 2, 3 and 4 Operand Instruction Template class IXOP o, Format F, dag outs, dag ins, string asm, list pattern> - : I, + : I, XOP9, Requires<[HasXOP]>; // XOP 2 and 3 Operand Instruction Templates with imm byte class IXOPi8 o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8, + : Ii8, XOP8, Requires<[HasXOP]>; // XOP 4 Operand Instruction Templates with imm byte class IXOPi8Reg o, Format F, dag outs, dag ins, string asm, list pattern> - : Ii8Reg, + : Ii8Reg, XOP8, Requires<[HasXOP]>; // XOP 5 operand instruction (VEX encoding!) class IXOP5 o, Format F, dag outs, dag ins, string asm, listpattern> - : Ii8Reg, TAPD, + : Ii8Reg, TAPD, VEX_4V, Requires<[HasXOP]>; // X86-64 Instruction templates... // class RI o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : I, REX_W; + list pattern> + : I, REX_W; class RIi8 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii8, REX_W; + list pattern> + : Ii8, REX_W; class RIi16 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii16, REX_W; + list pattern> + : Ii16, REX_W; class RIi32 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii32, REX_W; + list pattern> + : Ii32, REX_W; class RIi32S o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii32S, REX_W; + list pattern> + : Ii32S, REX_W; class RIi64 o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : Ii64, REX_W; + list pattern> + : Ii64, REX_W; class RS2I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : S2I, REX_W; + list pattern> + : S2I, REX_W; class VRS2I o, Format F, dag outs, dag ins, string asm, - list pattern, InstrItinClass itin = NoItinerary> - : VS2I, VEX_W; + list pattern> + : VS2I, VEX_W; // MMX Instruction templates // diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index af51fcd3365..7e4b6a19537 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -257,14 +257,14 @@ multiclass sse12_fp_scalar opc, string OpcodeStr, SDNode OpNode, !if(Is2Addr, !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), - [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], NoItinerary, d>, + [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>, Sched<[itins.Sched]>; } def rm : SI, + [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } @@ -279,14 +279,14 @@ let isCodeGenOnly = 1, hasSideEffects = 0 in { !if(Is2Addr, !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"), !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), - [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], NoItinerary, d>, + [(set RC:$dst, (VT (OpNode RC:$src1, RC:$src2)))], d>, Sched<[itins.Sched]>; let mayLoad = 1 in def rm_Int : SI_Int, + [(set RC:$dst, (VT (OpNode RC:$src1, mem_cpat:$src2)))], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } } @@ -301,7 +301,7 @@ multiclass sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, !if(Is2Addr, !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), - [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], NoItinerary, d>, + [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>, Sched<[itins.Sched]>; let mayLoad = 1 in def rm : PI opc, string OpcodeStr, SDNode OpNode, !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], - NoItinerary, d>, + d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } @@ -323,14 +323,14 @@ multiclass sse12_fp_packed_logical_rm opc, RegisterClass RC, Domain d, !if(Is2Addr, !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), - pat_rr, NoItinerary, d>, + pat_rr, d>, Sched<[WriteVecLogic]>; let hasSideEffects = 0, mayLoad = 1 in def rm : PI, + pat_rm, d>, Sched<[WriteVecLogicLd, ReadAfterLd]>; } @@ -406,8 +406,8 @@ multiclass sse12_move_rr, Sched<[WriteFShuffle]>; + [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))], d>, + Sched<[WriteFShuffle]>; // For the disassembler let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in @@ -428,7 +428,7 @@ multiclass sse12_move, + [(store RC:$src, addr:$dst)], d>, VEX, VEX_LIG, Sched<[WriteStore]>, VEX_WIG; // SSE1 & 2 let Constraints = "$src1 = $dst" in { @@ -438,8 +438,8 @@ multiclass sse12_move, - Sched<[WriteStore]>; + [(store RC:$src, addr:$dst)], d>, + Sched<[WriteStore]>; } // Loading from memory automatically zeroing upper bits. @@ -447,12 +447,12 @@ multiclass sse12_move_rm { def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(set RC:$dst, (mem_pat addr:$src))], - NoItinerary, d>, VEX, VEX_LIG, Sched<[WriteLoad]>, VEX_WIG; + [(set RC:$dst, (mem_pat addr:$src))], d>, + VEX, VEX_LIG, Sched<[WriteLoad]>, VEX_WIG; def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), - [(set RC:$dst, (mem_pat addr:$src))], - NoItinerary, d>, Sched<[WriteLoad]>; + [(set RC:$dst, (mem_pat addr:$src))], d>, + Sched<[WriteLoad]>; } defm MOVSS : sse12_move opc, RegisterClass RC, OpndItins itins> { let hasSideEffects = 0 in def rr : PI, + !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, Sched<[WriteFMove]>; let canFoldAsLoad = 1, isReMaterializable = 1 in def rm : PI, + [(set RC:$dst, (ld_frag addr:$src))], d>, Sched<[WriteFLoad]>; } @@ -880,7 +880,7 @@ multiclass sse12_mov_hilo_packed_baseopc, SDNode psnode, SDNode pdnode, [(set VR128:$dst, (psnode VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))], - NoItinerary, SSEPackedSingle>, PS, + SSEPackedSingle>, PS, Sched<[WriteFShuffleLd, ReadAfterLd]>; def PDrm : PIopc, SDNode psnode, SDNode pdnode, !strconcat(base_opc, "d", asm_opr), [(set VR128:$dst, (v2f64 (pdnode VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))))], - NoItinerary, SSEPackedDouble>, PD, + SSEPackedDouble>, PD, Sched<[WriteFShuffleLd, ReadAfterLd]>; } @@ -1202,13 +1202,13 @@ multiclass sse12_cvt_p opc, RegisterClass RC, X86MemOperand x86memop, string asm, Domain d, OpndItins itins> { let hasSideEffects = 0 in { def rr : I, Sched<[itins.Sched]>; + [(set RC:$dst, (DstTy (sint_to_fp (SrcTy RC:$src))))], d>, + Sched<[itins.Sched]>; let mayLoad = 1 in def rm : I, Sched<[itins.Sched.Folded]>; + (SrcTy (bitconvert (ld_frag addr:$src))))))], d>, + Sched<[itins.Sched.Folded]>; } } @@ -2308,26 +2308,23 @@ multiclass sse12_cmp_packed, + [(set RC:$dst, (VT (X86cmpp RC:$src1, RC:$src2, imm:$cc)))], d>, Sched<[WriteFAdd]>; def rmi : PIi8<0xC2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, [(set RC:$dst, - (VT (X86cmpp RC:$src1, (ld_frag addr:$src2), imm:$cc)))], - NoItinerary, d>, + (VT (X86cmpp RC:$src1, (ld_frag addr:$src2), imm:$cc)))], d>, Sched<[WriteFAddLd, ReadAfterLd]>; // Accept explicit immediate argument form instead of comparison code. let isAsmParserOnly = 1, hasSideEffects = 0 in { def rri_alt : PIi8<0xC2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc), - asm_alt, [], NoItinerary, d>, Sched<[WriteFAdd]>; + asm_alt, [], d>, Sched<[WriteFAdd]>; let mayLoad = 1 in def rmi_alt : PIi8<0xC2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc), - asm_alt, [], NoItinerary, d>, - Sched<[WriteFAddLd, ReadAfterLd]>; + asm_alt, [], d>, Sched<[WriteFAddLd, ReadAfterLd]>; } } @@ -2426,12 +2423,12 @@ multiclass sse12_shuffle, + (i8 imm:$src3))))], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$src3), asm, [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2, - (i8 imm:$src3))))], NoItinerary, d>, + (i8 imm:$src3))))], d>, Sched<[itins.Sched]>; } @@ -2476,14 +2473,13 @@ multiclass sse12_unpack_interleave opc, SDNode OpNode, ValueType vt, def rr : PI, Sched<[itins.Sched]>; + (vt (OpNode RC:$src1, RC:$src2)))], d>, + Sched<[itins.Sched]>; def rm : PI, + (mem_frag addr:$src2))))], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; } @@ -2559,7 +2555,7 @@ multiclass sse12_extr_sign_mask { def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src), !strconcat(asm, "\t{$src, $dst|$dst, $src}"), - [(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], NoItinerary, d>, + [(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], d>, Sched<[WriteFMOVMSK]>; } @@ -3103,12 +3099,12 @@ multiclass sse_fp_unop_s opc, string OpcodeStr, RegisterClass RC, let hasSideEffects = 0 in { def r : I, Sched<[itins.Sched]>, + [(set RC:$dst, (OpNode RC:$src1))], d>, Sched<[itins.Sched]>, Requires<[target]>; let mayLoad = 1 in def m : I, + [(set RC:$dst, (OpNode (load addr:$src1)))], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>, Requires<[target, OptForSize]>; @@ -3152,11 +3148,11 @@ multiclass avx_fp_unop_s opc, string OpcodeStr, RegisterClass RC, let hasSideEffects = 0 in { def r : I, Sched<[itins.Sched]>; + [], d>, Sched<[itins.Sched]>; let mayLoad = 1 in def m : I, Sched<[itins.Sched.Folded, ReadAfterLd]>; + [], d>, Sched<[itins.Sched.Folded, ReadAfterLd]>; let isCodeGenOnly = 1, ExeDomain = d in { def r_Int : I opc, bits<8> opc2, Format ImmForm, !if(Is2Addr, !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), - [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))], - SSE_INTSHIFT_ITINS_P.rr>, Sched<[WriteVecShift]>; + [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))]>, + Sched<[WriteVecShift]>; def rm : PDI, Sched<[WriteVecShiftLd, ReadAfterLd]>; + (SrcVT (bitconvert (ld_frag addr:$src2))))))]>, + Sched<[WriteVecShiftLd, ReadAfterLd]>; def ri : PDIi8, Sched<[WriteVecShift]>; + [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))]>, + Sched<[WriteVecShift]>; } multiclass PDI_binop_rmi_all opc, bits<8> opc2, Format ImmForm, @@ -6552,7 +6548,7 @@ multiclass SS41I_quaternary_int_avx opc, string OpcodeStr, !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))], - NoItinerary, SSEPackedInt>, TAPD, VEX_4V, + SSEPackedInt>, TAPD, VEX_4V, Sched<[itins.Sched]>; def rm : Ii8Reg opc, string OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)), - RC:$src3))], - NoItinerary, SSEPackedInt>, TAPD, VEX_4V, + RC:$src3))], SSEPackedInt>, TAPD, VEX_4V, Sched<[itins.Sched.Folded, ReadAfterLd, // x86memop:$src2 ReadDefault, ReadDefault, ReadDefault, ReadDefault, @@ -8500,14 +8495,12 @@ multiclass GF2P8MULB_rm, + [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, RC:$src2)))]>, Sched<[SSE_INTALU_ITINS_P.Sched]>, T8PD; def rm : PDI<0xCF, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, X86MemOp:$src2), "", [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1, - (bitconvert (MemOpFrag addr:$src2)))))], - SSE_INTALU_ITINS_P.rm>, + (bitconvert (MemOpFrag addr:$src2)))))]>, Sched<[SSE_INTALU_ITINS_P.Sched.Folded, ReadAfterLd]>, T8PD; } } @@ -8521,14 +8514,12 @@ multiclass GF2P8AFFINE_rmi Op, string OpStr, ValueType OpVT, def rri : Ii8, - Sched<[WriteVecALU]>; + SSEPackedInt>, Sched<[WriteVecALU]>; def rmi : Ii8, + imm:$src3)))], SSEPackedInt>, Sched<[WriteVecALU.Folded, ReadAfterLd]>; } } -- 2.11.0