From 1f258a6d53b29f6dfb60436da4aa76e996644d84 Mon Sep 17 00:00:00 2001 From: Cameron Zwarich Date: Thu, 14 Feb 2013 03:25:24 +0000 Subject: [PATCH] RegisterCoalescer::reMaterializeTrivialDef() can constrain the destination register class to match the defining instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175130 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegisterCoalescer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index 07ae8a2e3af..e2488adcdc8 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -769,7 +769,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(CoalescerPair &CP, // extract_subreg, insert_subreg, subreg_to_reg coalescing. const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI, *MF); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { - if (MRI->getRegClass(DstReg) != RC) + if (!MRI->constrainRegClass(DstReg, RC)) return false; } else if (!RC->contains(DstReg)) return false; -- 2.11.0