From 20614b956257d8702736ede13762385972cf4e43 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 5 Mar 2006 21:08:06 +0000 Subject: [PATCH] Add a new scheduling type. This is, of course, a hack. Proper factoring will come later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26551 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 5bc51e8582f..b99e429ab12 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -34,17 +34,16 @@ namespace llvm { typedef std::vector NIVector; typedef std::vector::iterator NIIterator; - // Scheduling heuristics enum SchedHeuristics { defaultScheduling, // Let the target specify its preference. noScheduling, // No scheduling, emit breath first sequence. simpleScheduling, // Two pass, min. critical path, max. utilization. simpleNoItinScheduling, // Same as above exact using generic latency. - listSchedulingBURR // Bottom up reg reduction list scheduling. + listSchedulingBURR, // Bottom up reg reduction list scheduling. + listSchedulingG5 // G5-specific scheduler. FIXME: parameterize better }; - //===--------------------------------------------------------------------===// /// /// Node group - This struct is used to manage flagged node groups. @@ -359,6 +358,12 @@ namespace llvm { /// reduction list scheduler. ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB); + + /// createTDG5ListDAGScheduler - This creates a top-down list scheduler for + /// the PowerPC G5. FIXME: pull the priority function out into the PPC + /// backend! + ScheduleDAG* createTDG5ListDAGScheduler(SelectionDAG &DAG, + MachineBasicBlock *BB); } #endif -- 2.11.0