From 20cd0008bb01ea0f5dd5779896bf6f069aab9c8a Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 10 Apr 2013 17:34:37 -0500 Subject: [PATCH] mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE This controller only does ECC on full-page accesses, even though the ECC consists of multiple steps. fsl_elbc_nand can get away with this because the ECC of an all-0xff region will be all-0xff, but this is not true with the ECC algorithms used by IFC. Signed-off-by: Scott Wood Signed-off-by: Artem Bityutskiy Signed-off-by: David Woodhouse --- drivers/mtd/nand/fsl_ifc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 180bfa798e13..317a771f1587 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) /* set up nand options */ chip->bbt_options = NAND_BBT_USE_FLASH; - + chip->options = NAND_NO_SUBPAGE_WRITE; if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { chip->read_byte = fsl_ifc_read_byte16; -- 2.11.0