From 2259918e087d9967e6c8f9b621d67d5968019724 Mon Sep 17 00:00:00 2001 From: "JinZe.Xu" Date: Tue, 18 May 2021 14:36:37 +0800 Subject: [PATCH] drm/amd/display: Control power gating by driver. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit [Why] This disablement would be specific for Nav10 and shouldn’t be propagated to the other programs. [How] Power gating is controlled by driver. Signed-off-by: JinZe.Xu Reviewed-by: Jun Lei Acked-by: Stylon Wang Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c | 34 ++++++++-------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c index e8580cccbebf..0a6d58dd8f6d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c @@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po 1, 1000); break; case 4: /* DPP4 */ - /* - * Do not power gate DPP4, should be left at HW default, power on permanently. - * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard - * reset. - * REG_UPDATE(DOMAIN9_PG_CONFIG, - * DOMAIN9_POWER_GATE, power_gate); - * - * REG_WAIT(DOMAIN9_PG_STATUS, - * DOMAIN9_PGFSM_PWR_STATUS, pwr_status, - * 1, 1000); - */ + REG_UPDATE(DOMAIN9_PG_CONFIG, + DOMAIN9_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN9_PG_STATUS, + DOMAIN9_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); @@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool 1, 1000); break; case 4: /* DCHUBP4 */ - /* - * Do not power gate DCHUB4, should be left at HW default, power on permanently. - * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard - * reset. - * REG_UPDATE(DOMAIN8_PG_CONFIG, - * DOMAIN8_POWER_GATE, power_gate); - * - * REG_WAIT(DOMAIN8_PG_STATUS, - * DOMAIN8_PGFSM_PWR_STATUS, pwr_status, - * 1, 1000); - */ + REG_UPDATE(DOMAIN8_PG_CONFIG, + DOMAIN8_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN8_PG_STATUS, + DOMAIN8_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); break; default: BREAK_TO_DEBUGGER(); -- 2.11.0