From 249933f254e1eed3c1b90384ef4616b9e87e22a5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sun, 28 Jun 2020 10:49:06 -0400 Subject: [PATCH] X86: Use Register --- llvm/lib/Target/X86/X86ISelLowering.cpp | 42 ++++++++++++++++----------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 255c69754c3..6f9753cee21 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2592,7 +2592,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, /// Breaks v64i1 value into two registers and adds the new node to the DAG static void Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, - SmallVectorImpl> &RegsToPass, CCValAssign &VA, + SmallVectorImpl> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) { assert(Subtarget.hasBWI() && "Expected AVX512BW target!"); assert(Subtarget.is32Bit() && "Expecting 32 bit target"); @@ -2637,7 +2637,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); CCInfo.AnalyzeReturn(Outs, RetCC_X86); - SmallVector, 4> RetVals; + SmallVector, 4> RetVals; for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E; ++I, ++OutsIndex) { CCValAssign &VA = RVLocs[I]; @@ -2757,7 +2757,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is // false, then an sret argument may be implicitly inserted in the SelDAG. In // either case FuncInfo->setSRetReturnReg() will have been called. - if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) { + if (Register SRetReg = FuncInfo->getSRetReturnReg()) { // When we have both sret and another return value, we should use the // original Chain stored in RetOps[0], instead of the current Chain updated // in the above loop. If we only have sret, RetOps[0] equals to Chain. @@ -2780,7 +2780,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, SDValue Val = DAG.getCopyFromReg(RetOps[0], dl, SRetReg, getPointerTy(MF.getDataLayout())); - unsigned RetValReg + Register RetValReg = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ? X86::RAX : X86::EAX; Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag); @@ -2906,7 +2906,7 @@ static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, if (nullptr == InFlag) { // When no physical register is present, // create an intermediate virtual register. - unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + Register Reg = MF.addLiveIn(VA.getLocReg(), RC); ArgValueLo = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32); Reg = MF.addLiveIn(NextVA.getLocReg(), RC); ArgValueHi = DAG.getCopyFromReg(Root, Dl, Reg, MVT::i32); @@ -3425,15 +3425,15 @@ void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters( // Gather all the live in physical registers. for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) { - unsigned GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass); + Register GPR = TheMachineFunction.addLiveIn(Reg, &X86::GR64RegClass); LiveGPRs.push_back(DAG.getCopyFromReg(Chain, DL, GPR, MVT::i64)); } const auto &AvailableXmms = ArgXMMs.slice(NumXMMRegs); if (!AvailableXmms.empty()) { - unsigned AL = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass); + Register AL = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass); ALVal = DAG.getCopyFromReg(Chain, DL, AL, MVT::i8); for (MCPhysReg Reg : AvailableXmms) { - unsigned XMMReg = TheMachineFunction.addLiveIn(Reg, &X86::VR128RegClass); + Register XMMReg = TheMachineFunction.addLiveIn(Reg, &X86::VR128RegClass); LiveXMMRegs.push_back( DAG.getCopyFromReg(Chain, DL, XMMReg, MVT::v4f32)); } @@ -3505,7 +3505,7 @@ void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) { // Forward AL for SysV x86_64 targets, since it is used for varargs. if (is64Bit() && !isWin64() && !CCInfo.isAllocated(X86::AL)) { - unsigned ALVReg = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass); + Register ALVReg = TheMachineFunction.addLiveIn(X86::AL, &X86::GR8RegClass); Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8)); } @@ -3630,7 +3630,7 @@ SDValue X86TargetLowering::LowerFormalArguments( else llvm_unreachable("Unknown argument type!"); - unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + Register Reg = MF.addLiveIn(VA.getLocReg(), RC); ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); } @@ -3684,7 +3684,7 @@ SDValue X86TargetLowering::LowerFormalArguments( // the argument into a virtual register so that we can access it from the // return points. if (Ins[I].Flags.isSRet()) { - unsigned Reg = FuncInfo->getSRetReturnReg(); + Register Reg = FuncInfo->getSRetReturnReg(); if (!Reg) { MVT PtrTy = getPointerTy(DAG.getDataLayout()); Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); @@ -3750,7 +3750,7 @@ SDValue X86TargetLowering::LowerFormalArguments( if (CallConv == CallingConv::X86_RegCall || F.hasFnAttribute("no_caller_saved_registers")) { MachineRegisterInfo &MRI = MF.getRegInfo(); - for (std::pair Pair : MRI.liveins()) + for (std::pair Pair : MRI.liveins()) MRI.disableCalleeSavedRegister(Pair.first); } @@ -3971,7 +3971,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit, FPDiff, dl); - SmallVector, 8> RegsToPass; + SmallVector, 8> RegsToPass; SmallVector MemOpChains; SDValue StackPtr; @@ -4062,7 +4062,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (isVarArg && IsWin64) { // Win64 ABI requires argument XMM reg to be copied to the corresponding // shadow reg if callee is a varargs function. - unsigned ShadowReg = 0; + Register ShadowReg; switch (VA.getLocReg()) { case X86::XMM0: ShadowReg = X86::RCX; break; case X86::XMM1: ShadowReg = X86::RDX; break; @@ -4090,7 +4090,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // GOT pointer. if (!isTailCall) { RegsToPass.push_back(std::make_pair( - unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), + Register(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy(DAG.getDataLayout())))); } else { // If we are tail calling and generating PIC/GOT style code load the @@ -4128,7 +4128,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs); assert((Subtarget.hasSSE1() || !NumXMMRegs) && "SSE registers cannot be used when SSE is disabled"); - RegsToPass.push_back(std::make_pair(unsigned(X86::AL), + RegsToPass.push_back(std::make_pair(Register(X86::AL), DAG.getConstant(NumXMMRegs, dl, MVT::i8))); } @@ -4137,7 +4137,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, const auto &Forwards = X86Info->getForwardedMustTailRegParms(); for (const auto &F : Forwards) { SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT); - RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val)); + RegsToPass.push_back(std::make_pair(F.PReg, Val)); } } @@ -4448,7 +4448,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, int FI = INT_MAX; if (Arg.getOpcode() == ISD::CopyFromReg) { - unsigned VR = cast(Arg.getOperand(1))->getReg(); + Register VR = cast(Arg.getOperand(1))->getReg(); if (!Register::isVirtualRegister(VR)) return false; MachineInstr *Def = MRI->getVRegDef(VR); @@ -32649,7 +32649,7 @@ X86TargetLowering::emitEHSjLjLongJmp(MachineInstr &MI, Register Tmp = MRI.createVirtualRegister(RC); // Since FP is only updated here but NOT referenced, it's treated as GPR. const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); - unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; + Register FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP; Register SP = RegInfo->getStackRegister(); MachineInstrBuilder MIB; @@ -49597,7 +49597,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, // Use the default implementation in TargetLowering to convert the register // constraint into a member of a register class. - std::pair Res; + std::pair Res; Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); // Not found as a standard register? @@ -49668,7 +49668,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, if (isGRClass(*Class)) { unsigned Size = VT.getSizeInBits(); if (Size == 1) Size = 8; - unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size); + Register DestReg = getX86SubSuperRegisterOrZero(Res.first, Size); if (DestReg > 0) { bool is64Bit = Subtarget.is64Bit(); const TargetRegisterClass *RC = -- 2.11.0