From 2530cd31f441f959f9189f791cf8c5ccbdbce7e3 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Mon, 31 Mar 2014 00:02:10 +0000 Subject: [PATCH] [ARM64] Fix materialization of an fp128 zero immediate. There currently is not a pattern to lower this with clever instructions that zero the register, so restrict the zero immediate legality special case to f64 and f32 (the only two sizes which fmov seems to directly support). Fixes backend errors when building code such as libxml. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205161 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64ISelLowering.cpp | 5 +++-- test/CodeGen/ARM64/fp-imm.ll | 11 +++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index 9154328c27c..5bd7b47c772 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -3879,8 +3879,9 @@ ARM64TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { } bool ARM64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { - // We can materialize #0.0 as fmov $Rd, XZR. - if (Imm.isPosZero()) + // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. + // FIXME: We should be able to handle f128 as well with a clever lowering. + if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32)) return true; if (VT == MVT::f64) diff --git a/test/CodeGen/ARM64/fp-imm.ll b/test/CodeGen/ARM64/fp-imm.ll index db16b65de11..6e271e03d28 100644 --- a/test/CodeGen/ARM64/fp-imm.ll +++ b/test/CodeGen/ARM64/fp-imm.ll @@ -19,3 +19,14 @@ define float @bar() { ; CHECK-NEXT: ret ret float 0x400921FB60000000 } + +; CHECK: literal16 +; CHECK: .quad 0 +; CHECK: .quad 0 +define fp128 @baz() { +; CHECK: _baz: +; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0@PAGE +; CHECK: ldr q0, [x[[REG]], lCPI2_0@PAGEOFF] +; CHECK-NEXT: ret + ret fp128 0xL00000000000000000000000000000000 +} -- 2.11.0