From 263d0e48672c552c97cdbdbe2105d7b9fd0b133c Mon Sep 17 00:00:00 2001 From: Mostafa Saleh Date: Thu, 25 May 2023 10:37:49 +0100 Subject: [PATCH] hw/arm/smmuv3: Add missing fields for IDR0 In preparation for adding stage-2 support. Add IDR0 fields related to stage-2. VMID16: 16-bit VMID supported. S2P: Stage-2 translation supported. They are described in 6.3.1 SMMU_IDR0. No functional change intended. Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Signed-off-by: Mostafa Saleh Tested-by: Eric Auger Tested-by: Jean-Philippe Brucker Message-id: 20230516203327.2051088-2-smostafa@google.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index e8f0ebf25e..183d5ac8dc 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -34,10 +34,12 @@ typedef enum SMMUTranslationStatus { /* MMIO Registers */ REG32(IDR0, 0x0) + FIELD(IDR0, S2P, 0 , 1) FIELD(IDR0, S1P, 1 , 1) FIELD(IDR0, TTF, 2 , 2) FIELD(IDR0, COHACC, 4 , 1) FIELD(IDR0, ASID16, 12, 1) + FIELD(IDR0, VMID16, 18, 1) FIELD(IDR0, TTENDIAN, 21, 2) FIELD(IDR0, STALL_MODEL, 24, 2) FIELD(IDR0, TERM_MODEL, 26, 1) -- 2.11.0