From 267a5044344cff6b29eaefd555c7f6f0359c8c2b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 13 Aug 2017 17:29:07 +0000 Subject: [PATCH] [X86][ARM][TargetLowering] Add SrcVT to isExtractSubvectorCheap Summary: Without the SrcVT its hard to know what is really being asked for. For example if your target has 128, 256, and 512 bit vectors. Maybe extracting 128 from 256 is cheap, but maybe extracting 128 from 512 is not. For x86 we do support extracting a quarter of a 512-bit register. But for i1 vectors we don't have isel patterns for extracting arbitrary pieces. So we need this to have a correct implementation of isExtractSubvectorCheap for mask vectors. Reviewers: RKSimon, zvi, efriedma Reviewed By: RKSimon Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310793 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 11 ++++++----- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 2 +- lib/Target/ARM/ARMISelLowering.h | 3 ++- lib/Target/X86/X86ISelLowering.cpp | 2 +- lib/Target/X86/X86ISelLowering.h | 3 ++- 6 files changed, 13 insertions(+), 10 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 1f1562bf35b..4c8a220eac2 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -2172,11 +2172,12 @@ public: return false; } - /// Return true if EXTRACT_SUBVECTOR is cheap for this result type - /// with this index. This is needed because EXTRACT_SUBVECTOR usually - /// has custom lowering that depends on the index of the first element, - /// and only the target knows which lowering is cheap. - virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const { + /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type + /// from this source type with this index. This is needed because + /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of + /// the first element, and only the target knows which lowering is cheap. + virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, + unsigned Index) const { return false; } diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4cdac46ee6b..d2973e5a832 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -14212,7 +14212,7 @@ SDValue DAGCombiner::createBuildVecShuffle(const SDLoc &DL, SDNode *N, VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps); VecIn2 = SDValue(); } else if (InVT1.getSizeInBits() == VT.getSizeInBits() * 2) { - if (!TLI.isExtractSubvectorCheap(VT, NumElems)) + if (!TLI.isExtractSubvectorCheap(VT, InVT1, NumElems)) return SDValue(); if (!VecIn2.getNode()) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 753008588fc..778ed3b26d2 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -13402,7 +13402,7 @@ bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, return true; } -bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, +bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const { if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) return false; diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 6ccd4b87000..7761aa1315e 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -459,7 +459,8 @@ class InstrItineraryData; /// Return true if EXTRACT_SUBVECTOR is cheap for this result type /// with this index. - bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; + bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, + unsigned Index) const override; /// \brief Returns true if an argument of type Ty needs to be passed in a /// contiguous block of registers in calling convention CallConv. diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index aab8df81597..f5040b8e0b3 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4574,7 +4574,7 @@ bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, return true; } -bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, +bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const { if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) return false; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 82117523bf0..45787bf0baf 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -1036,7 +1036,8 @@ namespace llvm { /// Return true if EXTRACT_SUBVECTOR is cheap for this result type /// with this index. - bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; + bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, + unsigned Index) const override; /// Intel processors have a unified instruction and data cache const char * getClearCacheBuiltinName() const override { -- 2.11.0