From 269e0fed84dba9f1ddb0b08730857ac9582b2cca Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 22 Apr 2010 18:28:43 +0000 Subject: [PATCH] Update ARM frame index scavenging description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102101 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/ReleaseNotes.html | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index d36b0c2db31..c95f0b8d5ca 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -737,8 +737,11 @@ href="http://blog.llvm.org/2010/04/arm-advanced-simd-neon-intrinsics-and.html"> helpful information if migrating code from GCC to LLVM-GCC.
  • The ARM and Thumb code generators now use register scavenging for stack - object address materialization.(FIXME: WHAT BENEFIT DOES THIS PROVIDE?)
    • - + object address materialization. This allows the use of R3 as a general + purpose register in Thumb1 code, as it was previous reserved for use in + stack address materialization. Secondly, sequential uses of the same + value will now re-use the materialized constant. +
  • The ARM backend now has good support for ARMv4 targets and has been tested on StrongARM hardware. Previously, LLVM only supported ARMv4T and newer chips.
    • -- 2.11.0