From 275f6459ab5fca1a0b56920291d9cba4aae5d3b5 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 28 Feb 2004 19:37:18 +0000 Subject: [PATCH] Bring this directory into "it actually compiles" land git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11955 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcRegisterInfo.cpp | 12 ++++++------ lib/Target/Sparc/SparcV8Instrs.td | 11 +++++++++++ lib/Target/Sparc/SparcV8Instrs_F2.td | 2 +- lib/Target/Sparc/SparcV8Instrs_F3.td | 3 ++- lib/Target/SparcV8/SparcV8Instrs.td | 11 +++++++++++ lib/Target/SparcV8/SparcV8Instrs_F2.td | 2 +- lib/Target/SparcV8/SparcV8Instrs_F3.td | 3 ++- lib/Target/SparcV8/SparcV8RegisterInfo.cpp | 12 ++++++------ 8 files changed, 40 insertions(+), 16 deletions(-) diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index d6fd83a4f5f..7f576f956b5 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -17,8 +17,8 @@ using namespace llvm; SparcV8RegisterInfo::SparcV8RegisterInfo() - : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN, - SparcV8::ADJCALLSTACKUP) {} + : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, + V8::ADJCALLSTACKUP) {} int SparcV8RegisterInfo::storeRegToStackSlot( MachineBasicBlock &MBB, @@ -80,6 +80,9 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, const TargetRegisterClass* SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { switch (Ty->getPrimitiveID()) { + case Type::FloatTyID: + case Type::DoubleTyID: + assert(0 && "Floating point registers not supported yet!"); case Type::LongTyID: case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); default: assert(0 && "Invalid type to getClass!"); @@ -90,10 +93,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::UShortTyID: case Type::IntTyID: case Type::UIntTyID: - case Type::PointerTyID: return &GPRCInstance; - - case Type::FloatTyID: - case Type::DoubleTyID: return &FPRCInstance; + case Type::PointerTyID: return &IntRegsInstance; } } diff --git a/lib/Target/Sparc/SparcV8Instrs.td b/lib/Target/Sparc/SparcV8Instrs.td index ac4e8be143f..37b4d744ca1 100644 --- a/lib/Target/Sparc/SparcV8Instrs.td +++ b/lib/Target/Sparc/SparcV8Instrs.td @@ -35,6 +35,17 @@ include "SparcV8Instrs_F3.td" // Instructions //===----------------------------------------------------------------------===// +// Pseudo instructions. +def PHI : InstV8 { + let Name = "PHI"; +} +def ADJCALLSTACKDOWN : InstV8 { + let Name = "ADJCALLSTACKDOWN"; +} +def ADJCALLSTACKUP : InstV8 { + let Name = "ADJCALLSTACKUP"; +} + // Section B.20: SAVE and RESTORE - p117 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r diff --git a/lib/Target/Sparc/SparcV8Instrs_F2.td b/lib/Target/Sparc/SparcV8Instrs_F2.td index 69b0a4e81c5..7b550bd7ddf 100644 --- a/lib/Target/Sparc/SparcV8Instrs_F2.td +++ b/lib/Target/Sparc/SparcV8Instrs_F2.td @@ -31,7 +31,7 @@ class F2_1 op2Val, string name> : F2 { let Inst{29-25} = rd; } -class F2_2 cond, bits<3> op2Val, string name> : F2 { +class F2_2 condVal, bits<3> op2Val, string name> : F2 { bits<4> cond; bit annul = 0; // currently unused diff --git a/lib/Target/Sparc/SparcV8Instrs_F3.td b/lib/Target/Sparc/SparcV8Instrs_F3.td index a19cd34480e..f1bf6a05f8f 100644 --- a/lib/Target/Sparc/SparcV8Instrs_F3.td +++ b/lib/Target/Sparc/SparcV8Instrs_F3.td @@ -47,6 +47,7 @@ class F3_2 opVal, bits<6> op3val, string name> : F3 { let Inst{12-0} = simm13; } +/* class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> : F3_rs1rs2 { bits<5> rs2; @@ -58,4 +59,4 @@ class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> let Inst{13-5} = opfVal; let Inst{4-0} = rs2; } - +*/ \ No newline at end of file diff --git a/lib/Target/SparcV8/SparcV8Instrs.td b/lib/Target/SparcV8/SparcV8Instrs.td index ac4e8be143f..37b4d744ca1 100644 --- a/lib/Target/SparcV8/SparcV8Instrs.td +++ b/lib/Target/SparcV8/SparcV8Instrs.td @@ -35,6 +35,17 @@ include "SparcV8Instrs_F3.td" // Instructions //===----------------------------------------------------------------------===// +// Pseudo instructions. +def PHI : InstV8 { + let Name = "PHI"; +} +def ADJCALLSTACKDOWN : InstV8 { + let Name = "ADJCALLSTACKDOWN"; +} +def ADJCALLSTACKUP : InstV8 { + let Name = "ADJCALLSTACKUP"; +} + // Section B.20: SAVE and RESTORE - p117 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r diff --git a/lib/Target/SparcV8/SparcV8Instrs_F2.td b/lib/Target/SparcV8/SparcV8Instrs_F2.td index 69b0a4e81c5..7b550bd7ddf 100644 --- a/lib/Target/SparcV8/SparcV8Instrs_F2.td +++ b/lib/Target/SparcV8/SparcV8Instrs_F2.td @@ -31,7 +31,7 @@ class F2_1 op2Val, string name> : F2 { let Inst{29-25} = rd; } -class F2_2 cond, bits<3> op2Val, string name> : F2 { +class F2_2 condVal, bits<3> op2Val, string name> : F2 { bits<4> cond; bit annul = 0; // currently unused diff --git a/lib/Target/SparcV8/SparcV8Instrs_F3.td b/lib/Target/SparcV8/SparcV8Instrs_F3.td index a19cd34480e..f1bf6a05f8f 100644 --- a/lib/Target/SparcV8/SparcV8Instrs_F3.td +++ b/lib/Target/SparcV8/SparcV8Instrs_F3.td @@ -47,6 +47,7 @@ class F3_2 opVal, bits<6> op3val, string name> : F3 { let Inst{12-0} = simm13; } +/* class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> : F3_rs1rs2 { bits<5> rs2; @@ -58,4 +59,4 @@ class F3_3 opVal, bits<6> op3val, bits<9> opfVal, string name> let Inst{13-5} = opfVal; let Inst{4-0} = rs2; } - +*/ \ No newline at end of file diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp index d6fd83a4f5f..7f576f956b5 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp @@ -17,8 +17,8 @@ using namespace llvm; SparcV8RegisterInfo::SparcV8RegisterInfo() - : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN, - SparcV8::ADJCALLSTACKUP) {} + : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, + V8::ADJCALLSTACKUP) {} int SparcV8RegisterInfo::storeRegToStackSlot( MachineBasicBlock &MBB, @@ -80,6 +80,9 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, const TargetRegisterClass* SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { switch (Ty->getPrimitiveID()) { + case Type::FloatTyID: + case Type::DoubleTyID: + assert(0 && "Floating point registers not supported yet!"); case Type::LongTyID: case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); default: assert(0 && "Invalid type to getClass!"); @@ -90,10 +93,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::UShortTyID: case Type::IntTyID: case Type::UIntTyID: - case Type::PointerTyID: return &GPRCInstance; - - case Type::FloatTyID: - case Type::DoubleTyID: return &FPRCInstance; + case Type::PointerTyID: return &IntRegsInstance; } } -- 2.11.0