From 276621da451ae93321de05bf63baaf20ee2f32ca Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 30 Jan 2016 02:29:32 +0100 Subject: [PATCH] gallium/radeon: set num_banks in the winsys MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit amdgpu doesn't have to set this, because radeonsi gets it from tile mode arrays by default. Reviewed-by: Michel Dänzer --- src/gallium/drivers/r600/evergreen_state.c | 8 +++---- src/gallium/drivers/r600/r600_uvd.c | 2 +- src/gallium/drivers/radeon/r600_pipe_common.c | 26 +---------------------- src/gallium/drivers/radeon/r600_pipe_common.h | 1 - src/gallium/drivers/radeon/radeon_winsys.h | 1 + src/gallium/drivers/radeonsi/si_state.c | 2 +- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 5 +++++ 7 files changed, 13 insertions(+), 32 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index a7e673a3b1f..9a0a30e3a6f 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -772,7 +772,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, if (util_format_get_blocksize(pipe_format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); if (state->target == PIPE_TEXTURE_1D_ARRAY) { height = 1; @@ -1098,7 +1098,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, if (util_format_get_blocksize(surf->base.format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); desc = util_format_description(surf->base.format); for (i = 0; i < 4; i++) { if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { @@ -1253,7 +1253,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); offset >>= 8; surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | @@ -3467,7 +3467,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, sub_cmd = EG_DMA_COPY_TILED; lbpp = util_logbase2(bpp); pitch_tile_max = ((pitch / bpp) / 8) - 1; - nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks); if (dst_mode == RADEON_SURF_MODE_LINEAR) { /* T2L */ diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c index 18d2b69afb0..0c928345773 100644 --- a/src/gallium/drivers/r600/r600_uvd.c +++ b/src/gallium/drivers/r600/r600_uvd.c @@ -160,7 +160,7 @@ static struct pb_buffer* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_ struct r600_texture *chroma = (struct r600_texture *)buf->resources[1]; msg->body.decode.dt_field_mode = buf->base.interlaced; - msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.tiling_info.num_banks)); + msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.info.r600_num_banks)); ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface); diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index e0c2469747e..ec1d882f8c0 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -803,17 +803,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen, static bool r600_interpret_tiling(struct r600_common_screen *rscreen, uint32_t tiling_config) { - switch ((tiling_config & 0x30) >> 4) { - case 0: - rscreen->tiling_info.num_banks = 4; - break; - case 1: - rscreen->tiling_info.num_banks = 8; - break; - default: - return false; - - } switch ((tiling_config & 0xc0) >> 6) { case 0: rscreen->tiling_info.group_bytes = 256; @@ -830,20 +819,6 @@ static bool r600_interpret_tiling(struct r600_common_screen *rscreen, static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen, uint32_t tiling_config) { - switch ((tiling_config & 0xf0) >> 4) { - case 0: - rscreen->tiling_info.num_banks = 4; - break; - case 1: - rscreen->tiling_info.num_banks = 8; - break; - case 2: - rscreen->tiling_info.num_banks = 16; - break; - default: - return false; - } - switch ((tiling_config & 0xf00) >> 8) { case 0: rscreen->tiling_info.group_bytes = 256; @@ -981,6 +956,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen, printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map); printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid); printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config); + printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks); printf("num_render_backends = %i\n", rscreen->info.num_render_backends); printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes); printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid); diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 0c44bd7de00..52c517fb3e4 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -282,7 +282,6 @@ struct r600_surface { }; struct r600_tiling_info { - unsigned num_banks; unsigned group_bytes; }; diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 25b90558a66..b4cca0efcec 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -277,6 +277,7 @@ struct radeon_info { uint32_t r300_num_z_pipes; uint32_t r600_gb_backend_map; /* R600 harvest config */ boolean r600_gb_backend_map_valid; + uint32_t r600_num_banks; uint32_t r600_tiling_config; uint32_t num_render_backends; uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 580aa789098..bf780777b50 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -97,7 +97,7 @@ uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex) } /* The old way. */ - switch (sscreen->b.tiling_info.num_banks) { + switch (sscreen->b.info.r600_num_banks) { case 2: return V_02803C_ADDR_SURF_2_BANK; case 4: diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index b97ccfd1679..f857a14e033 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -385,6 +385,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL, &ws->info.r600_tiling_config); + ws->info.r600_num_banks = + ws->info.chip_class >= EVERGREEN ? + 4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) : + 4 << ((ws->info.r600_tiling_config & 0x30) >> 4); + if (ws->info.drm_minor >= 11) { radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL, &ws->info.num_tile_pipes); -- 2.11.0