From 27e1fb13f21e132011673f0a39e17bcc97583633 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 18 Nov 2014 03:20:28 +0000 Subject: [PATCH] target-mips: Output CP0.Config2-5 in the register dump Include CP0.Config2 through CP0.Config5 registers in the register dump produced with the `info registers' monitor command. Align vertically with the registers already output. Signed-off-by: Maciej W. Rozycki Signed-off-by: Leon Alrae --- target-mips/translate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 1a275bf099..70da66f958 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19264,6 +19264,10 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, env->CP0_Status, env->CP0_Cause, env->CP0_EPC); cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n", env->CP0_Config0, env->CP0_Config1, env->lladdr); + cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); if (env->hflags & MIPS_HFLAG_FPU) fpu_dump_state(env, f, cpu_fprintf, flags); #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) -- 2.11.0