From 29d1efe070d3cb5c52d51d82af71790ffaf0a64f Mon Sep 17 00:00:00 2001 From: Rodrigo Vivi Date: Thu, 7 Sep 2017 16:00:38 -0700 Subject: [PATCH] drm/i915/psr: Re-org Activate after enable Let's move the activation calls together after enable is done. No real functional change should be expected here. Just an attempt to get it clear when we are really activating PSR after enabling it. v2: Add braces on if/else because commit message there is too long as suggested by Jani. v3: Rebased on top of commit d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") Cc: Jani Nikula Cc: Daniel Vetter Cc: Dhinakaran Pandiyan Cc: Vathsala Nagaraju Signed-off-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-9-rodrigo.vivi@intel.com --- drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 245cf3ee979f..7031dfd50ae9 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -549,8 +549,6 @@ void intel_psr_enable(struct intel_dp *intel_dp, hsw_psr_enable_source(intel_dp, crtc_state); - if (INTEL_GEN(dev_priv) >= 9) - intel_psr_activate(intel_dp); } else { vlv_psr_setup_vsc(intel_dp, crtc_state); @@ -560,20 +558,25 @@ void intel_psr_enable(struct intel_dp *intel_dp, vlv_psr_enable_source(intel_dp, crtc_state); } - /* - * FIXME: Activation should happen immediately since this function - * is just called after pipe is fully trained and enabled. - * However on every platform we face issues when first activation - * follows a modeset so quickly. - * - On VLV/CHV we get bank screen on first activation - * - On HSW/BDW we get a recoverable frozen screen until next - * exit-activate sequence. - */ - if (INTEL_GEN(dev_priv) < 9) + dev_priv->psr.enabled = intel_dp; + + if (INTEL_GEN(dev_priv) >= 9) { + intel_psr_activate(intel_dp); + } else { + /* + * FIXME: Activation should happen immediately since this + * function is just called after pipe is fully trained and + * enabled. + * However on some platforms we face issues when first + * activation follows a modeset so quickly. + * - On VLV/CHV we get bank screen on first activation + * - On HSW/BDW we get a recoverable frozen screen until + * next exit-activate sequence. + */ schedule_delayed_work(&dev_priv->psr.work, msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); + } - dev_priv->psr.enabled = intel_dp; unlock: mutex_unlock(&dev_priv->psr.lock); } -- 2.11.0