From 29d26d20e5b4a9f28cdd9d072b407223e7b0e610 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Fri, 5 Sep 2008 19:07:53 +0000 Subject: [PATCH] fix alpha cmovxx instruction MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The CMOV instruction is defined by the alpha manual as: CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate format CMOVxx Ra.rq,#b.ib,Rc.wq !Operate format Operation: IF TEST(Rav, Condition_based_on_Opcode) THEN Rc ← Rbv The current qemu behavior inverses Ra and Rb. This is fixed by this patch. Signed-off-by: Tristan Gingold Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5171 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-alpha/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 8376c043ea..847646f0d0 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -390,15 +390,15 @@ static always_inline void gen_cmov (DisasContext *ctx, int islit, int8_t lit) { if (ra != 31) - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]); + tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); else - tcg_gen_movi_i64(cpu_T[1], 0); + tcg_gen_movi_i64(cpu_T[0], 0); if (islit) - tcg_gen_movi_i64(cpu_T[0], lit); + tcg_gen_movi_i64(cpu_T[1], lit); else if (rb != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); + tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]); else - tcg_gen_movi_i64(cpu_T[0], 0); + tcg_gen_movi_i64(cpu_T[1], 0); (*gen_test_op)(); gen_op_cmov_ir(rc); } -- 2.11.0