From 2a0ee94fef9aa87f23070693764175982700f0f5 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 19 May 2015 17:05:41 +0300 Subject: [PATCH] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+ On B0 and C0 steppings the workaround enable bit would be overriden by default, so the overriding must be disabled. The WA was added in commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3 Author: Nick Hoath Date: Fri Apr 10 13:12:26 2015 +0100 drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent Spotted-by: Mika Kuoppala Signed-off-by: Imre Deak Reviewed-by: Mika Kuoppala Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04b9f2b4c042..3f94f38eec1f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5791,6 +5791,7 @@ enum skl_disp_power_wells { /* GEN8 chicken */ #define HDC_CHICKEN0 0x7300 +#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15) #define HDC_FENCE_DEST_SLM_DISABLE (1<<14) #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11) #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 461b9befa776..a071b1062e30 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1043,6 +1043,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; gen9_init_workarounds(ring); @@ -1058,8 +1059,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) } /* WaForceContextSaveRestoreNonCoherent:bxt */ - WA_SET_BIT_MASKED(HDC_CHICKEN0, - HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; + if (INTEL_REVID(dev) >= BXT_REVID_B0) + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); return 0; } -- 2.11.0