From 2a2b221b65f5a4bcbbb9b508cdb76ff527e48aa6 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Tue, 23 May 2023 17:35:35 +0800 Subject: [PATCH] disas/riscv.c: Support disas for Zcm* extensions Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- disas/riscv.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index f2dd5fd531..6659f92179 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2505,7 +2505,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_sqsp; } else { op = rv_op_c_fsdsp; - if (((inst >> 12) & 0b01)) { + if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) { switch ((inst >> 8) & 0b01111) { case 8: if (((inst >> 4) & 0b01111) >= 4) { @@ -2531,6 +2531,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } else { switch ((inst >> 10) & 0b011) { case 0: + if (!dec->cfg->ext_zcmt) { + break; + } if (((inst >> 2) & 0xFF) >= 32) { op = rv_op_cm_jalt; } else { @@ -2538,6 +2541,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 3: + if (!dec->cfg->ext_zcmp) { + break; + } switch ((inst >> 5) & 0b011) { case 1: op = rv_op_cm_mvsa01; break; case 3: op = rv_op_cm_mva01s; break; -- 2.11.0