From 2a8bfa139a4515cd020c7a5be1e1e45d5d116352 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Mon, 6 May 2019 16:28:22 +0800 Subject: [PATCH] drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabled MP1 cannot access clock IP during MP1 FW reload, disable PLL shutdown as a workaround. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index af4b07a02426..2466c2ab13d4 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -383,10 +383,14 @@ static int navi10_append_powerplay_table(struct smu_context *smu) /* Mvdd Svi2 Div Ratio Setting */ smc_pptable->MvddRatio = smc_dpm_table->MvddRatio; - if (adev->pm.pp_feature & PP_GFXOFF_MASK) + if (adev->pm.pp_feature & PP_GFXOFF_MASK) { *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT) | FEATURE_MASK(FEATURE_GFXOFF_BIT); + /* TODO: remove it once SMU fw fix it */ + smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN; + } + return 0; } -- 2.11.0