From 2bd54bb2ce5cda5eb27a6a7466b7a85eb4d8d7f5 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 9 May 2019 18:38:55 +0000 Subject: [PATCH] [AMDGPU] gfx1010 v_interp_* instructions Differential Revision: https://reviews.llvm.org/D61703 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360364 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AMDGPU/SIInstrInfo.td | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 72b7d5088d9..7cec40c99e8 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -2008,13 +2008,12 @@ class VINTRP_Pseudo pattern> : let isCodeGenOnly = 1; } +// FIXME-GFX10: WIP. class VINTRP_Real_si op, string opName, dag outs, dag ins, - string asm> : + string asm, int encodingFamily> : VINTRPCommon , VINTRPe , - SIMCInstr { - let AssemblerPredicate = SIAssemblerPredicate; - let DecoderNamespace = "GFX6GFX7"; + SIMCInstr { let DisableDecoder = DisableSIDecoder; } @@ -2028,15 +2027,21 @@ class VINTRP_Real_vi op, string opName, dag outs, dag ins, let DisableDecoder = DisableVIDecoder; } +// FIXME-GFX10: WIP. multiclass VINTRP_m op, dag outs, dag ins, string asm, list pattern = []> { def "" : VINTRP_Pseudo ; - def _si : VINTRP_Real_si ; + let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { + def _si : VINTRP_Real_si ; + } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" def _vi : VINTRP_Real_vi ; -} + let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { + def _gfx10 : VINTRP_Real_si; + } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" +} //===----------------------------------------------------------------------===// // Vector instruction mappings //===----------------------------------------------------------------------===// -- 2.11.0