From 2c322ce8131e3a3ce190a0fdc434c9502920ea72 Mon Sep 17 00:00:00 2001
From: astoria-d <astoria-d@mail.goo.ne.jp>
Date: Fri, 9 Aug 2013 19:47:10 +0900
Subject: [PATCH] - cmp zp, x - cmp abs - cmp abs, x - cmp indir, y supported.
 - test case added.

---
 simulation/cpu/decoder.vhd   | 25 +++++++++++++++++++++++++
 tools/test-image/sample1.asm | 27 +++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index 21acf79..162ee7f 100644
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -480,6 +480,7 @@ begin
     front_we(acc_cmd, '1');
     front_we(x_cmd, '1');
     front_we(y_cmd, '1');
+    stat_alu_we_n <= '1';
 end  procedure;
 
 procedure a2_abs_xy (is_x : in boolean) is
@@ -1319,14 +1320,32 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#d5#, dsize) then
                     --zp, x
                     d_print("cmp");
+                    a2_zp_xy(true);
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#cd#, dsize) then
                     --abs
                     d_print("cmp");
+                    a2_abs;
+                    if exec_cycle = T3 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#dd#, dsize) then
                     --abs, x
                     d_print("cmp");
+                    a2_abs_xy(true);
+                    if exec_cycle = T3 or exec_cycle = T4 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#d9#, dsize) then
                     --abs, y
@@ -1345,6 +1364,12 @@ end  procedure;
                 elsif instruction  = conv_std_logic_vector(16#d1#, dsize) then
                     --(indir), y
                     d_print("cmp");
+                    a2_indir_y;
+                    if exec_cycle = T4 or exec_cycle = T5 then
+                        arith_en_n <= '0';
+                        back_oe(acc_cmd, '0');
+                        set_nzc_from_alu;
+                    end if;
 
                 elsif instruction  = conv_std_logic_vector(16#e0#, dsize) then
                     --imm
diff --git a/tools/test-image/sample1.asm b/tools/test-image/sample1.asm
index 51f8ce4..95f82a4 100644
--- a/tools/test-image/sample1.asm
+++ b/tools/test-image/sample1.asm
@@ -447,6 +447,33 @@ boundary_3_4:
     ;c9&07=01
     and ($07), y
 
+    ;;cmp zp, x/abs/abs, x/indir, y
+    lda #$de
+    ldx #$e4
+    sta $a4
+    ;c5-de=-19 > (e7)
+    lda #$c5
+    cmp $c0, x
+
+    sec
+    lda #$75
+    stx $0734
+    ;75-e4=-6f > 91
+    cmp $0650, x
+
+    ldx #$c9
+    stx $0825
+    lda #$34
+    sta $07
+    lda #$07
+    sta $08
+    ldy #$f1
+    lda #$c9
+    ;page crossing
+    ;c9-c9=0
+    cmp ($07), y
+
+
     ;;infinite loop.
 mainloop:
 	jmp	mainloop
-- 
2.11.0