From 2c77a625b79908f6e1238890caae630d28c48bee Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Fri, 28 Jun 2013 20:00:07 +0000
Subject: [PATCH] Fix a PPC rlwimi instruction-selection bug

Under certain (evidently rare) circumstances, this code used to convert OR(a,
AND(x, y)) into OR(a, x). This was incorrect.

While there, I've added a comment to the code immediately above.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185201 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCISelDAGToDAG.cpp |  4 ++--
 test/CodeGen/PowerPC/rlwimi-and.ll     | 44 ++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 2 deletions(-)
 create mode 100644 test/CodeGen/PowerPC/rlwimi-and.ll

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 35f4b7c8d21..f8d990cee62 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -447,10 +447,10 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
         unsigned SHOpc = Op1.getOperand(0).getOpcode();
         if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
             isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
+	  // Note that Value must be in range here (less than 32) because
+	  // otherwise there would not be any bits set in InsertMask.
           Op1 = Op1.getOperand(0).getOperand(0);
           SH  = (SHOpc == ISD::SHL) ? Value : 32 - Value;
-        } else {
-          Op1 = Op1.getOperand(0);
         }
       }
 
diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll
new file mode 100644
index 00000000000..e20a13fec0f
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+define void @test() align 2 {
+entry:
+  br i1 undef, label %codeRepl1, label %codeRepl31
+
+codeRepl1:                                        ; preds = %entry
+  br i1 undef, label %codeRepl4, label %codeRepl29
+
+codeRepl4:                                        ; preds = %codeRepl1
+  br i1 undef, label %codeRepl12, label %codeRepl17
+
+codeRepl12:                                       ; preds = %codeRepl4
+  unreachable
+
+codeRepl17:                                       ; preds = %codeRepl4
+  %0 = load i8* undef, align 2
+  %1 = and i8 %0, 1
+  %not.tobool.i.i.i = icmp eq i8 %1, 0
+  %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256
+  %3 = load i8* undef, align 1
+  %4 = and i8 %3, 1
+  %not.tobool.i.1.i.i = icmp eq i8 %4, 0
+  %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
+  %rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2
+  store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
+  unreachable
+
+; CHECK: @test
+; CHECK-DAG: slwi [[R1:[0-9]+]],
+; CHECK-DAG: rlwinm [[R2:[0-9]+]],
+; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]]
+; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23
+; CHECK: rlwimi [[R4]], [[R2]], 0,
+
+codeRepl29:                                       ; preds = %codeRepl1
+  unreachable
+
+codeRepl31:                                       ; preds = %entry
+  ret void
+}
+
-- 
2.11.0