From 2d72e7b047d800c9f99262466f65a98684ecca14 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 27 Jun 2016 16:19:10 +0100 Subject: [PATCH] target-mips: change ASID type to hold more than 8 bits ASID currently has uint8_t type which is too small since some processors support more than 8 bits ASID. Therefore change its type to uint16_t. Signed-off-by: Paul Burton Signed-off-by: James Hogan Signed-off-by: Leon Alrae --- target-mips/cpu.h | 2 +- target-mips/helper.c | 4 ++-- target-mips/machine.c | 10 +++++----- target-mips/op_helper.c | 8 ++++---- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6325e15bab..3e233ad639 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -19,7 +19,7 @@ typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; uint32_t PageMask; - uint8_t ASID; + uint16_t ASID; unsigned int G:1; unsigned int C0:3; unsigned int C1:3; diff --git a/target-mips/helper.c b/target-mips/helper.c index 1e194e9c22..9fbca26d41 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type) { - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; int i; for (i = 0; i < env->tlb->tlb_in_use; i++) { @@ -898,7 +898,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) r4k_tlb_t *tlb; target_ulong addr; target_ulong end; - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; target_ulong mask; tlb = &env->tlb->mmu.r4k.tlb[idx]; diff --git a/target-mips/machine.c b/target-mips/machine.c index 7314cfe8c7..a27f2f156d 100644 --- a/target-mips/machine.c +++ b/target-mips/machine.c @@ -132,7 +132,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size) qemu_get_betls(f, &v->VPN); qemu_get_be32s(f, &v->PageMask); - qemu_get_8s(f, &v->ASID); + qemu_get_be16s(f, &v->ASID); qemu_get_be16s(f, &flags); v->G = (flags >> 10) & 1; v->C0 = (flags >> 7) & 3; @@ -156,7 +156,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) { r4k_tlb_t *v = pv; - uint8_t asid = v->ASID; + uint16_t asid = v->ASID; uint16_t flags = ((v->EHINV << 15) | (v->RI1 << 14) | (v->RI0 << 13) | @@ -172,7 +172,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) qemu_put_betls(f, &v->VPN); qemu_put_be32s(f, &v->PageMask); - qemu_put_8s(f, &asid); + qemu_put_be16s(f, &asid); qemu_put_be16s(f, &flags); qemu_put_be64s(f, &v->PFN[0]); qemu_put_be64s(f, &v->PFN[1]); @@ -192,8 +192,8 @@ const VMStateInfo vmstate_info_tlb = { const VMStateDescription vmstate_tlb = { .name = "cpu/tlb", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1562f22b5c..31c85f9aee 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2013,7 +2013,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) { int idx; r4k_tlb_t *tlb; - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; for (idx = 0; idx < env->tlb->nb_tlb; idx++) { tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -2039,7 +2039,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) r4k_tlb_t *tlb; int idx; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; bool G, V0, D0, V1, D1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; @@ -2081,7 +2081,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) target_ulong mask; target_ulong tag; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; int i; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; @@ -2136,7 +2136,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) void r4k_helper_tlbr(CPUMIPSState *env) { r4k_tlb_t *tlb; - uint8_t ASID; + uint16_t ASID; int idx; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; -- 2.11.0