From 2d7f1d1c37e86a5a3cc4055fc761fbf7bdcb4988 Mon Sep 17 00:00:00 2001 From: Eli Billauer Date: Sat, 16 Aug 2014 18:58:01 +0300 Subject: [PATCH] staging: xillybus: Removed read barrier at beginning of ISR The comment (also removed) explains why it was there in the first place, but that doesn't make much sense. Signed-off-by: Eli Billauer Signed-off-by: Greg Kroah-Hartman --- drivers/staging/xillybus/xillybus_core.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/staging/xillybus/xillybus_core.c b/drivers/staging/xillybus/xillybus_core.c index 8de4fbd50fa2..d5a7202b0ac7 100644 --- a/drivers/staging/xillybus/xillybus_core.c +++ b/drivers/staging/xillybus/xillybus_core.c @@ -133,17 +133,9 @@ irqreturn_t xillybus_isr(int irq, void *data) unsigned int msg_channel, msg_bufno, msg_data, msg_dir; struct xilly_channel *channel; - /* - * The endpoint structure is altered during periods when it's - * guaranteed no interrupt will occur, but in theory, the cache - * lines may not be updated. So a memory barrier is issued. - */ - smp_rmb(); - buf = ep->msgbuf_addr; buf_size = ep->msg_buf_size/sizeof(u32); - ep->ephw->hw_sync_sgl_for_cpu(ep, ep->msgbuf_dma_addr, ep->msg_buf_size, -- 2.11.0