From 2f752e914d943c199f3255b4aba3358fd78cc8c9 Mon Sep 17 00:00:00 2001 From: Nikola Cornij Date: Thu, 5 Mar 2020 16:32:35 -0500 Subject: [PATCH] drm/amd/display: Remove connect DIG FE to its BE during timing programming [why] Causes regression with MST DSC displays not lighting up after DPMS [how] Revert commit 8cc426d79be1c3 ("drm/amd/display: Program DSC during timing programming") Signed-off-by: Nikola Cornij Reviewed-by: Aric Cyr Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +++-------- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ------- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 1 - 4 files changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fb603bd46fac..67cfff1586e9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3069,14 +3069,9 @@ void core_link_enable_stream( if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || - dc_is_virtual_signal(pipe_ctx->stream->signal)) { - /* Here we only need to enable DSC on RX. DSC HW programming - * was done earlier, as part of timing programming. - */ - dp_set_dsc_on_rx(pipe_ctx, true); - } + dc_is_virtual_signal(pipe_ctx->stream->signal)) + dp_set_dsc_enable(pipe_ctx, true); } - dc->hwss.enable_stream(pipe_ctx); /* Set DPS PPS SDP (AKA "info frames") */ @@ -3103,7 +3098,7 @@ void core_link_enable_stream( } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) - dp_set_dsc_on_rx(pipe_ctx, true); + dp_set_dsc_enable(pipe_ctx, true); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index ac2103dec9e7..51e0ee6e7695 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -394,7 +394,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } -bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) +static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; struct dc_stream_state *stream = pipe_ctx->stream; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 69eb7b3697d2..233318260da4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -623,13 +623,6 @@ enum dc_status dcn20_enable_stream_timing( /* TODO check if timing_changed, disable stream if timing changed */ - /* Have to setup DSC here to make sure the bandwidth sent to DIG BE won't be bigger than - * what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag will be automatically - * set at a later time when the video is enabled (DP_VID_STREAM_EN = 1). - */ - if (pipe_ctx->stream->timing.flags.DSC) - dp_set_dsc_on_stream(pipe_ctx, true); - for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; opp_cnt++; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 64f401e4db54..e94e5fbf2aa2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -85,7 +85,6 @@ void dp_set_fec_enable(struct dc_link *link, bool enable); bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); -bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable); bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); #endif /* __DC_LINK_DP_H__ */ -- 2.11.0